MT8841AN [MITEL]
CMOS Calling Number Identification Circuit; CMOS主叫号码识别电路
| 型号： | MT8841AN |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | CMOS Calling Number Identification Circuit |
| 文件： | 总10页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS
MT8841
Calling Number Identification Circuit
ISSUE 4
May 1995
Features
Ordering Information
•
•
1200 baud BELL 202 and CCITT V.23
Frequency Shift Keying (FSK) demodulation
MT8841AE
MT8841AS
MT8841AN
16 Pin Plastic DIP
16 Pin SOIC
20 Pin SSOP
Compatible with Bellcore TR-NWT-000030 and
SR-TSV-002476
-40 °C to +85 °C
•
•
High input sensitivity: -36dBm
Simple serial 3-wire data interface eliminating
the need for a UART
Description
The MT8841 Calling Number Identification Circuit
(CNIC) is a CMOS integrated circuit providing an
interface to various calling line information delivery
services that utilize 1200 baud BELL 202 or CCITT
V.23 FSK voiceband data transmission schemes.
The CNIC receives and demodulates the signal and
outputs data into a simple 3-wire serial interface.
•
•
•
•
Power down mode
Internal gain adjustable amplifier
Carrier detect status output
Uses 3.579545 MHz crystal or ceramic
resonator
Single 5V power supply
•
•
Low power CMOS technology
Typically, the FSK modulated data containing
information on the calling line is sent before alerting
the called party or during the silent interval between
the first and second ring using either CCITT V.23
recommendations or Bell 202 specifications.
Applications
•
Calling Number Delivery (CND), Calling Name
Delivery (CNAM) and Calling Identity on Call
Waiting (CIDCW) features of Bellcore CLASSSM
service
The CNIC accepts and demodulates both CCITT
V.23 and BELL 202 signals. Along with serial data
and clock, the CNIC provides a data ready signal to
indicate the reception of every 8-bit character sent
from the Central Office. The received data can be
processed externally by a microcontroller, stored in
memory, or displayed as is, depending on the
application.
•
•
•
•
•
Feature phones
Phone set adjunct boxes
FAX machines
Telephone Answering machines
Database query systems
GS
DATA
Receive
Bandpass
Filter
Data and Timing
IN-
-
DR
FSK
Demodulator
Recovery
+
IN+
DCLK
CAP
Bias
Generator
Carrier
Detector
V
Ref
CD
to other
circuits
Clock
Generator
V
V
IC1 IC2
PWDN
OSC1 OSC2
SS
DD
Figure 1 - Functional Block Diagram
CLASSSM is a service mark of Bellcore
5-11
MT8841
16
15
14
13
12
11
10
9
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
IN+
IN-
GS
VRef
CAP
OSC1
OSC2
VSS
VDD
IC2
IC1
PWDN
CD
DR
IN+
IN-
GS
VRef
CAP
NC
OSC1
NC
VDD
IC2
NC
NC
IC1
PWDN
CD
DR
DATA
DCLK
DATA
DCLK
OSC2
VSS
9
10
16 PIN PLASTIC DIP/SOIC
20 PIN SSOP
Figure 2 - Pin Connections
Description
Pin Description
Pin #
Name
16 20
1
2
3
4
5
6
1
2
3
4
5
7
IN+ Non-inverting Op-Amp (Input).
IN-
GS
Inverting Op-Amp (Input).
Gain Select (Output). Gives access to op-amp output for connection of feedback resistor.
VRef Voltage Reference (Output). Nominally VDD/2. This is used to bias the op-amp inputs.
CAP Capacitor. Connect a 0.1µF capacitor to VSS
.
OSC1 Oscillator (Input). Crystal or ceramic resonator connection. This pin can be driven directly
from an external clocking source.
7
9
OSC2 Oscillator (Output). Crystal or ceramic resonator connection. When OSC1 is driven by an
external clock, this pin should be left open.
8
9
10
VSS Power supply ground.
11 DCLK Data Clock (Output). Outputs a clock burst of 8 low going pulses at 1202.8Hz (3.5795MHz
divided by 2976). Every clock burst is initiated by the DATA stop bit start bit sequence. When
the input DATA is 1202.8 baud, the positive edge of each DCLK pulse coincides with the
middle of the data bits output at the DATA pin. No DCLK pulses are generated during the start
or stop bits. Typically, DCLK is used to clock the eight data bits from the 10 bit data word into a
serial-to-parallel converter.
10 12 DATA Data (Output). Serial data output corresponding to the FSK input and switching at the input
baud rate. Mark frequency at the input corresponds to a logic high, while space frequency
corresponds to a logic low at the DATA output. With no FSK input, DATA is at logic high. This
output stays high until CD has become active.
11 13
DR
Data Ready (Open Drain Output). This output goes low after the last DCLK pulse of each
word. This can be used to identify the data (8-bit word) boundary on the serial output stream.
Typically, DR is used to latch the eight data bits from the serial-to-parallel converter into a
microcontroller.
12 14
CD
Carrier Detect (Open Drain Output). A logic low indicates that a carrier has been present for
a specified time on the line. A time hysteresis is provided to allow for momentary discontinuity
of carrier.
13 15 PWDN Power Down (Input). Active high, Schmitt Trigger input. Powers down the device including the
input op-amp and the oscillator.
14 16
15 19
16 20
IC1 Internal Connection 1. Connect to VSS.
IC2 Internal Connection 2. Internally connected, leave open circuit.
VDD Positive power supply voltage.
6,8
17,
18
NC
No Connection.
5-12
MT8841
Functional Description
IN+
The MT8841 Calling Number Identification Circuit
(CNIC) is a device compatible with the Bellcore
proposal (TR-NWT-000030) on generic requirements
for transmitting asynchronous voiceband data to
Customer Premises Equipment (CPE) from a serving
Stored Program Controlled Switching System
IN-
R
C
IN
GS
V
R
F
(SPCS) or
a Central Office (CO). This data
transmission technique is applicable in a variety of
services like Calling Number Delivery (CND), Calling
Name Delivery (CNAM) or Calling Identity Delivery
on Call Waiting (CIDCW) as specified in Custom
Local Area Signalling Service (CLASSSM) calling
information delivery features by Bellcore.
Ref
VOLTAGE GAIN
(A ) = R / R
V
F
IN
MT8841
Figure 4 - Single-Ended Input Configuration
at the called subscriber location either in the on-hook
case as in CND, or the off-hook case, as in
CIDCW. The functional block diagram of the CNIC
is shown in Figure 1. Note however, for CIDCW
applications, a separate CAS (CPE Alerting Signal)
detector is required.
With CND, CNAM and CIDCW service, the called
subscriber has the capability to display or to store
the information on the calling party which is sent by
the CO and received by the CNIC.
In Europe, Caller ID and CIDCW services are being
proposed. These schemes may be different from
their North American counterparts. In most cases,
1200 baud CCITT V.23 FSK is used instead of Bell
202. Because the CNIC can also demodulate 1200
baud CCITT V.23 with the same performance, it is
suitable for these applications.
In the CND service, information about a calling party
is embedded in the silent interval between the first
and second ring. During this period, the CNIC
receives and demodulates the 1200 baud FSK signal
(compatible with Bell-202 specification) and outputs
data into a 3-wire serial interface.
In the CIDCW service, information about a second
calling party is sent to the subscriber, while they are
engaged in another call. During this period, the CNIC
receives and demodulates the FSK signal as in the
CND case.
Although the main application of the CNIC is to
support CND and CIDCW service, it may also be
used in any application where 1200 baud Bell 202
and/or CCITT V.23 FSK data reception is required.
Input Configuration
The CNIC is designed to provide the data
transmission interface required for the above service
The input arrangement of the MT8841 provides an
operational amplifier, as well as a bias source (VRef
)
which is used to bias the inputs at VDD/2. Provision is
made for connection of a feedback resistor to the op-
amp output (GS) for adjustment of gain. In a single-
ended configuration, the input pins are connected as
shown in Figure 4.
R1
R4
IN+
IN-
C1
C2
R5
GS
Figure 3 shows the necessary connections for a
differential input configuration.
R2
R3
V
Ref
User Interface
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
MT8841
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5) / (R2 + R5)
The CNIC provides a powerful 3-pin interface which
can reduce the external hardware and software
requirements. The CNIC receives the FSK signal,
demodulates it, and outputs the extracted data to the
DATA pin. For each received stop bit start bit
sequence, the CNIC outputs a fixed frequency clock
string of 8 pulses at the DCLK pin. Each clock rising
VOLTAGE GAIN
(A diff) = R5/R1
V
INPUT IMPEDANCE
R12 + (1/ωC)2
(Z diff) = 2
IN
Figure 3 - Differential Input Configuration
5-13
MT8841
edge corresponds to the centre of each DATA bit cell
(providing the incoming baud rate matches the DCLK
rate). DCLK is not generated for the stop and start
bits. Consequently, DCLK will clock only valid data
into a peripheral device such as a serial to parallel
shift register or a micro-controller. The CNIC also
outputs an end of word pulse (data ready) at the DR
pin. The data ready signal indicates the reception of
every 10-bit word sent from the Central Office. This
output is typically used to interrupt a micro-controller.
The three outputs together, eliminate the need for a
MT8841
MT8841
MT8841
OSC1 OSC2
OSC1 OSC2
OSC1 OSC2
to the
next MT8841
3.579545 MHz
Figure 5 - Common Crystal Connection
Crystal Oscillator
UART
(Universal
Asynchronous
Receiver
Transmitter) or the high software overhead of
performing the UART function (asynchronous serial
data reception).
The CNIC uses a crystal oscillator as the master
timing source for filters and the FSK demodulator.
The crystal specification is as follows:
Note that the 3-pin interface may also output data
generated by voice since these frequencies are in
the input frequency detection band of the device.
The user may choose to ignore these outputs when
FSK data is not expected, or force the CNIC into its
powerdown mode.
Frequency:
3.579545 MHz
±0.1%(-40°C+85°C)
Parallel
Frequency tolerance:
Resonance mode:
Load capacitance:
18 pF
Maximum series resistance: 150 ohms
Maximum drive level (mW): 2 mW
e.g. CTS MP036S
Power Down Mode
For
applications
requiring
reduced
power
consumption, the CNIC can be forced into power
down when it is not needed to receive FSK data.
This is done by pulling the PWDN pin high. In
powerdown mode, the crystal oscillator, op-amp and
internal circuitry are all disabled and the CNIC will
not react to the input signal. DATA and DCLK are at
logic high, and DR and CD are at high impedance or
at logic high when pulled up with resistors.The CNIC
can be awakened for reception of the FSK signal by
pulling the PWDN pin to ground (see Figure 9).
A number of MT8841 devices can be connected as
shown in Figure 5 such that only one crystal is
required. The connection between OSC2 and OSC1
can be D.C. coupled as shown, or A.C. coupled
using 30pF capacitors. Alternatively, the OSC1
inputs on all devices can be driven from a CMOS
buffer (dc coupled) with the OSC2 outputs left
unconnected.
VRef and CAP Inputs
Carrier Detect
V
Ref is the output of a low impedance voltage source
equal to VDD/2 and is used to bias the input op-amp.
The presence of the FSK signal is indicated by a
logic low at the carrier detect (CD) output. This
output has built in hysteresis to prevent toggling
when the received signal is shortly interrupted. Note
that the CD output is also activated by voice since
these frequencies are in the input frequency
detection band of the device. The user may choose
to ignore this output when FSK data is not expected,
or force the CNIC into its powerdown mode.
A 0.1µF capacitor is required between CAP and V
SS
to suppress noise on VRef.
5-14
MT8841
Applications
The circuit shown in Figure 6 illustrates the use of
the MT8841 device in a typical FSK receiver system.
Bellcore Special Report SR-TSV-002476 specifies
that the FSK receiver should be able to receive FSK
signal levels as follows:
Received Signal Level at 1200Hz:
-32dBm to -12dBm
Received Signal Level at 2200Hz:
-36dBm to -12dBm
This condition can be attained by choosing suitable
values of R1 and R2. The MT8841 configured in a
unity gain mode as shown in Fig. 6 meets the above
level requirements.
For applications requiring detection of lower FSK
signal level, the input op amp may be configured to
provide adequate gain.
+5V
MT8841
C1
C3
R4
IN +
VDD
IC2
R1
R3
IN -
IC1
GS
R2
PWDN
CD
VRef
CAP
OSC1
OSC2
VSS
To
DR
X-tal
C2
Controller
DATA
DCLK
Notes:
R1, R2 = 100 kΩ 1%
R3, R4 = 100 kΩ 10%
C1, C2, C3 = 0.1µF 20%
X-tal = 3.579545 MHz
Figure 6 - Application Circuit (Single-Ended Input)
5-15
MT8841
Absolute Maximum Ratings* - Voltages are with respect to VSS unless otherwise stated.
Parameter
Symbol
Min
Max
Units
1
2
3
4
5
DC Power Supply Voltage VDD to VSS
Voltage on any pin
VDD
VP
-0.3
-0.3
6
VDD+0.3
±10
V
V
Current at any pin (except VDD and VSS
)
I I/O
TST
PD
mA
°C
Storage Temperature
-65
+150
500
Package Power Dissipation
mW
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
DC Power Supply Voltage
Clock Frequency
VDD
fOSC
∆fc
4.5
5.0
5.5
V
MHz
%
3.579545
Tolerance on Clock Frequency
Operating Temperature
±0.2
+85
-40
°C
DC Electrical Characteristics†
Characteristics
Sym
Min
Typ*
Max
Units
µA
Test Conditions
PWDN=VDD
S
1
2
3
Standby Supply Current
Operating Supply Current
Power Consumption
IDDQ
IDD
15
3
100
5
U
P
P
L
mA PWDN=VSS
mW
PO
28
Y
4
Low Level Output Voltage
High Level Output Voltage
VOL
VOH
0.4
1.2
V
V
IOL=2.5mA
OH=0.8mA
DATA
DCLK
V
V
-0.4
I
DD
DR
CD
5
6
Sink Current
IOL
2.5
mA VOL=0.4V
Low Level Input Voltage
High Level Input Voltage
VIL
VIH
V
V
-1.2
DD
PWDN
VRef
7
8
Input Current
IIN
10
µA
VSS ≤ VIN ≤ VDD
Output Voltage
VRef
2.45
2.5
2.55
V
VDD=5.0V
No Load
9
Output Resistance
RRef
2
kΩ
† DC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
* Typical figures are at 25°C and are for design aid only.
5-16
MT8841
Electrical Characteristics† - Gain Setting Amplifier
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
VSS ≤ VIN ≤ VDD
1
2
3
4
5
6
7
8
9
Input Leakage Current
Input Resistance
IIN
Rin
1
µA
MΩ
mV
dB
5
Input Offset Voltage
VOS
PSRR
CMRR
AVOL
fC
25
Power Supply Rejection Ratio
Common Mode Rejection
DC Open Loop Voltage Gain
Unity Gain Bandwidth
30
30
30
.2
40
40
32
1kHz ripple on VDD
VCMmin ≤ VIN ≤ VCMmax
dB
dB
0.3
MHz
Vpp
pF
V
V
-0.5
Output Voltage Swing
VO
0.5
Load ≥ 50kΩ
DD
Maximum Capacitive Load (GS)
CL
100
10 Maximum Resistive Load (GS)
RL
50
kΩ
V
-1.0
DD
11 Common Mode Range Voltage
VCM
1.0
† Electrical characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FSK Detection
‡
Characteristics
Input Detection Level
Sym
Min
Typ
Max
Units
Notes*
1
-36
12.3
-9
275
dBm 1, 2, 3
mV 1, 2, 3
2
3
Input Baud Rate
1188 1200 1212
baud
7
Input Frequency Detection
Bell 202 1 (Mark)
1188 1200 1212
2178 2200 2222
Hz
Hz
}
7
BELL 202 Frequencies
CCITT V.23 Frequencies
Bell 202 0 (Space)
CCITT V.23 1 (Mark)
CCITT V.23 0 (Space)
1280.5 1300 1319.5
2068.5 2100 2131.5
Hz
Hz
}
7
signal
noise
4
Input Noise Tolerance 20 log(
SNR
20
dB
2, 3, 4, 5
)
† AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
5-17
MT8841
AC Electrical Characteristics† - Timing
‡
Characteristics
Power-up time
Sym
Min
Typ
Max
Units
Notes*
1
2
tPU
tPD
tIAL
tIAH
35
50
1000
25
ms
µs
PWDN
OSC1
Power-down time
Input FSK to CD low delay
Input FSK to CD high delay
Hysteresis
100
11
3
ms
ms
ms
bps
ms
ns
CD
4
8
8
5
DATA
6
Rate
1188
1200
1
1212
5
6,12
7
Input FSK to DATA delay
Rise time
tIDD
tR
8
200
200
8
9
Fall time
tF
ns
8
DATA
DCLK
10
11
12
13
14
15
DATA to DCLK delay
DCLK to DATA delay
Frequency
tDCD
tCDD
6
6
416
416
µs
6, 7, 10
µs
6, 7, 10
1200 1202.8 1205
Hz
µs
7
7
7
7
DCLK
High time
tCH
tCL
415
415
415
416
416
416
417
417
417
Low time
µs
DCLK
DR
DCLK to DR delay
tCRD
µs
16
17
18
Rise time
Fall time
Low time
tRR
tFF
tRL
10
µs
ns
µs
9
9
7
DR
200
417
415
416
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only, not guaranteed and not subject to production testing.
*Notes:
1.
dBm=decibels above or below a reference power of 1mW into 600Ω.
Using unity gain test circuit shown in Figure 6.
Mark and Space frequencies have the same amplitude.
Band limited random noise (200-3200Hz).
Referenced to the minimum input detection level.
FSK input data at 1200 ±12 baud.
OSC1 at 3.579545 MHz ±0.2%.
2.
3.
4.
5.
6.
7.
8.
10k to V , 50pF to V
SS SS.
9.
10k to V , 50pF to V
.
SS
DD
10.
11.
12.
Function of signal condition.
The device will stop functioning within this time, but more time may be required to reach I
For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations.
.
DDQ
t
t
CDD
DCD
t
F
t
R
DATA
DCLK
t
t
RR
FF
DR
t
RL
t
t
CH
CL
t
F
t
R
Figure 7 - DATA and DCLK Output Timing
Figure 8 - DR Output Timing
5-18
MT8841
channel seizure
Mark state
checksum
2 sec
TIP/RING
PWDN
Input FSK
Second
Ringing
First Ringing
500ms
(min)
200ms
(min)
Data
t
PU
t
PD
OSC2
CD *
t
t
IAL
IAH
DATA
High (Input Idle)
High (Input Idle)
DCLK
DR *
* with external pull-up resistor
Figure 9 - Input and Output Timing (Bellcore CND Service)
start
stop
start
stop
start
stop
TIP/RING
DATA
b7
b6
b6
b0 b1 b2
1
0
b0 b1 b2 b3 b4 b5
b7
b6
b0 b1 b2 b3 b4 b5
b7
b6
1
0
1
0
t
IDD
start
start
start
b0 b1 b2
b7
b0 b1 b2 b3 b4 b5
b7
b0 b1 b2 b3 b4 b5
b7
stop
stop
stop
DCLK
DR *
t
CRD
* with external pull-up resistor
Figure 10 - Serial Data Interface Timing
5-19
MT8841
NOTES:
5-20
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