MT3271BE [MITEL]
Wide Dynamic Range DTMF Receiver; 宽动态范围的DTMF接收器
| 型号： | MT3271BE |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | Wide Dynamic Range DTMF Receiver |
| 文件： | 总8页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT3170B/71B, MT3270B/71B, MT3370B/71B
Wide Dynamic Range DTMF Receiver
ISSUE 2
May 1995
Features
•
Wide dynamic range (50dB) DTMF Receiver
Ordering Information
•
Call progress (CP) detection via cadence
indication
MT3170/71BE
8 Pin Plastic DIP
8 Pin Plastic DIP
18 Pin SOIC
MT3270/71BE
MT3370/71BS
MT3370/71BN
•
•
•
•
•
4-bit synchronous serial data output
20 Pin SSOP
Software controlled guard time for MT3x70B
Internal guard time circuitry for MT3x71B
Powerdown option (MT317xB & MT337xB)
-40 °C to +85 °C
signalling. The MT3x70B provides an early steering
(ESt) logic output to indicate the detection of a DTMF
signal and requires external software guard time to
validate the DTMF digit. The MT3x71B, with preset
internal guard times, uses a delay steering (DStD)
logic output to indicate the detection of a valid DTMF
digit. The 4-bit DTMF binary digit can be clocked out
synchronously at the serial data (SD) output. The
SD pin is multiplexed with call progress detector
output. In the presence of supervisory tones, the
call progress detector circuit indicates the cadence
(i.e., envelope) of the tone burst. The cadence
information can then be processed by an external
microcontroller to identify specific call progress
signals. The MT327xB and MT337xB can be used
with a crystal or a ceramic resonator without
additional components. A power-down option is
provided for the MT317xB and MT337xB.
4.194304MHz crystal or ceramic resonator
(MT337xB and MT327xB)
•
•
External clock input (MT317xB)
Guarantees non-detection of spurious tones
Applications
•
•
•
Integrated telephone answering machine
End-to-end signalling
Fax Machines
Description
The MT3x7xB is a family of high performance DTMF
receivers which decode all 16 tone pairs into a 4-bit
binary code. These devices incorporate an AGC for
wide dynamic range and are suitable for end-to-end
➀
PWDN
Steering
Digital
Circuit
ESt
or
DStD
VDD
Guard
Voltage
Bias Circuit
➂
Time
High
Group
Filter
VSS
Parallel to
Serial
Converter
& Latch
ACK
Dial
Tone
Filter
Code
Converter
and
Anti-
alias
Filter
Digital
INPUT
AGC
Detector
Algorithm
Latch
Low
Group
Filter
Mux
SD
➁
Oscillator
OSC2
and
Clock
Circuit
Energy
Detection
OSC1
(CLK)
To All Chip Clocks
➀ MT3170B/71B and MT337xB only.
➁ MT3270B/71B and MT337xB only.
➂ MT3x71B only.
Figure 1 - Functional Block Diagram
4-3
MT3170B/71B, MT3270B/71B, MT3370B/71B
MT3370B/71B
MT3170B/71B
MT3270B/71B
MT3370B/71B
20
1
2
3
4
5
6
7
8
NC
NC
VDD
NC
ESt/DStD
NC
ACK
SD
NC
NC
NC
NC
INPUT
PWDN
NC
OSC2
OSC1
VSS
NC
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
NC
INPUT
PWDN
OSC2
NC
VDD
NC
NC
ESt/DStD
NC
ACK
NC
19
18
17
16
15
14
13
12
11
INPUT
PWDN
CLK
VDD INPUT
VDD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
ESt/
ESt/
DStD
OSC2
DStD
OSC1
VSS
ACK
SD
ACK
OSC1
NC
VSS
SD
NC
SD
NC
9
10
VSS
NC
8 PIN PLASTIC DIP
18 PIN PLASTIC SOIC
20 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
337xB
327xB
317xB
2
4
6
1
2
3
1
-
INPUT DTMF/CP Input. Input signal must be AC coupled via capacitor.
OSC2 Oscillator Output.
3
OSC1 Oscillator/Clock Input. This pin can either be driven by:
(CLK) 1) an external digital clock with defined input logic levels. OSC2
should be left open.
2) connecting a crystal or ceramic resonator between OSC1 and
OSC2 pins.
9
4
5
4
5
VSS
SD
Ground. (0V)
11
Serial Data/Call Progress Output. This pin serves the dual function
of being the serial data output when clock pulses are applied after
validation of DTMF signal, and also indicates the cadence of call
progress input. As DTMF signal lies in the same frequency band as
call progress signal, this pin may toggle for DTMF input. The SD pin
is at logic low in powerdown state.
13
15
18
6
7
6
7
ACK
Acknowledge Pulse Input. After ESt or DStD is high, applying a
sequence of four pulses on this pin will then shift out four bits on the
SD pin, representing the decoded DTMF digit. The rising edge of the
first clock is used to latch the 4-bit data prior to shifting. This pin is
pulled down internally. The idle state of the ACK signal should be
low.
ESt
(MT3x70B)
Early Steering Output. A logic high on ESt indicates that a DTMF
signal is present. ESt is at logic low in powerdown state.
Delayed Steering Output. A logic high on DStD indicates that a
valid DTMF digit has been detected. DStD is at logic low in
powerdown state.
DStD
(MT3x71B)
8
-
8
-
VDD
NC
Positive Power Supply (5V Typ.) Performance of the device can be
optimized by minimizing noise on the supply rails. Decoupling
capacitors across VDD and VSS are therefore recommended.
1,5,7,8,
10, 12,
14,16,
17
No Connection. Pin is unconnected internally.
3
-
2
PWDN Power Down Input. A logic high on this pin will power down the
device to reduce power consumption. This pin is pulled down
internally and can be left open if not used. ACK pin should be at logic
’0’ to power down device.
4-4
MT3170B/71B, MT3270B/71B, MT3370B/71B
Summary of MT3x70/71B Product Family
Device
Type
2 Pin
OSC
Ext
CLK
8 Pin
18 Pin
20 Pin
PWDN
ESt
DStD
MT3170B
MT3171B
MT3270B
MT3271B
MT3370B
MT3371B
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
resulting squarewave signals are applied to a digital
detection circuit where an averaging algorithm is
employed to determine the valid DTMF signal. For
MT3x70B, upon recognition of a valid frequency from
each tone group, the early steering (ESt) output will
go high, indicating that a DTMF tone has been
detected. Any subsequent loss of DTMF signal
condition will cause the ESt pin to go low. For
MT3x71B, an internal delayed steering counter
Functional Description
The MT3x7xBs are high performance and low power
consumption DTMF receivers. These devices
provide wide dynamic range DTMF detection and a
serial decoded data output. These devices also
incorporate an energy detection circuit. An input
voiceband signal is applied to the devices via a
series decoupling capacitor. Following the unity gain
buffering, the signal enters the AGC circuit followed
by an anti-aliasing filter. The bandlimited output is
routed to a dial tone filter stage and to the input of
the energy detection circuit. A bandsplit filter is then
used to separate the input DTMF signal into high
and low group tones. The high group and low group
tones are then verified and decoded by the internal
frequency counting and DTMF detection circuitry.
Following the detection stage, the valid DTMF digit is
translated to a 4-bit binary code (via an internal look-
up ROM). Data bits can then be shifted out serially
by applying external clock pulses.
validates the early steering signal after
a
predetermined guard time which requires no external
components. The delayed steering (DStD) will go
high only when the validation period has elapsed.
Once the DStD output is high, the subsequent loss of
early steering signal due to DTMF signal dropout will
activate the internal counter for a validation of tone
absent guard time. The DStD output will go low only
after this validation period.
Energy Detection
The output signal from the AGC circuit is also
applied to the energy detection circuit. The detection
circuit consists of a threshold comparator and an
active integrator. When the signal level is above the
threshold of the internal comparator (-35dBm), the
energy detector produces an energy present
indication on the SD output. The integrator ensures
the SD output will remain at high even though the
input signal is changing. When the input signal is
removed, the SD output will go low following the
integrator decay time. Short decay time enables the
signal envelope (or cadence) to be generated at the
SD output. An external microcontroller can monitor
this output for specific call progress signals. Since
presence of speech and DTMF signals (above the
threshold limit) can cause the SD output to toggle,
both ESt (DStD) and SD outputs should be
monitored to ensure correct signal identification. As
the energy detector is multiplexed with the digital
serial data output at the SD pin, the detector output
is selected at all times except during the time
between the rising edge of the first pulse and the
falling edge of the fourth pulse applied at the ACK
pin.
Automatic Gain Control (AGC) Circuit
As the device operates on a single power supply, the
input signal is biased internally at approximately
VDD/2. With large input signal amplitude (between 0
and approximately -30dBm for each tone of the
composite signal), the AGC is activated to prevent
the input signal from being clipped. At low input
level, the AGC remains inactive and the input signal
is passed directly to the hardware DTMF detection
algorithm and to the energy detection circuit.
Filter and Decoder Section
The signal entering the DTMF detection circuitry is
filtered by a notch filter at 350 and 440 Hz for dial
tone rejection. The composite dual-tone signal is
further split into its individual high and low frequency
th
components by two 6 order switched capacitor
bandpass filters. The high group and low group
tones are then smoothed by separate output filters
and squared by high gain limiting comparators. The
4-5
MT3170B/71B, MT3270B/71B, MT3370B/71B
Serial Data (SD) Output
FLOW
FHIGH
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
DIGIT
1
b3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
b2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
b1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
b0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
When a valid DTMF signal burst is present, ESt or
DStD will go high. The application of four clock
pulses on the ACK pin will provide a 4-bit serial
binary code representing the decoded DTMF digit on
the SD pin output. The rising edge of the first pulse
applied on the ACK pin latches and shifts the least
significant bit of the decoded digit on the SD pin.
The next three pulses on ACK pin will shift the
remaining latched bits in a serial format (see Figure
5). If less than four pulses are applied to the ACK
pin, new data cannot be latched even though ESt/
DStD can be valid. Clock pulses should be applied
to clock out any remaining data bits to resume
normal operation. Any transitions in excess of four
pulses will be ignored until the next rising edge of the
ESt/DStD. ACK should idle at logic low. The 4-bit
binary representing all 16 standard DTMF digits are
shown in Table 1.
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
Powerdown Mode (MT317xB/337xB)
0= LOGIC LOW, 1= LOGIC HIGH
The MT317xB/337xB devices offer a powerdown
function to preserve power consumption when the
device is not in use. A logic high can be applied at
the PWDN pin to place the device in powerdown
mode. The ACK pin should be kept at logic low to
avoid undefined ESt/DStD and SD outputs (see
Table 2).
Table 1. Serial Decode Bit Table
Note: b0=LSB of decoded DTMF digit and shifted out first.
MT317xB/337xB
ACK (input)
PWDN (input)
ESt/DStD (output)
SD (output)
status
low
low
Refer to Fig. 4 for
timing waveforms
Refer to Fig. 4 for
timing waveforms
normal operation
+
low
high
high
high
low
low
low
powerdown mode
undefined
low
undefined
undefined
high
undefined
undefined
Table 2. Powerdown Mode
+ =enters powerdown mode on the rising edge.
Frequency 1 (Hz)
Frequency 2 (Hz)
On/Off
Description
350
425
400
480
440
480
440
480
440
---
continuous
continuous
continuous
0.5s/0.5s
North American Dial Tones
European Dial Tones
---
Far East Dial Tones
620
---
North American Line Busy
Japanese Line Busy
0.5s/0.5s
620
480
620
0.25s/0.25s
2.0s/4.0s
North American Reorder Tones
North American Audible Ringing
North American Reorder Tones
0.25s/0.25s
Table 3. Call Progress Tones
4-6
MT3170B/71B, MT3270B/71B, MT3370B/71B
be driven by an 4.194304 MHz external clock applied
on pin OSC 1. The OSC2 pin should be left open.
Parameter
Unit
Resonator
Crystal
R1
L1
Ohms
mH
pF
pF
-
6.580
0.359
4.441
34.890
25
For MT317xB devices , the CLK input is driven
directly by an 4.194304 MHz external digital clock.
95.355
15.1E-03
12.0
C1
C0
Qm
∆f
Applications
1.299E+03 101.2E+ 03
±0.2% ±0.01%
%
The circuit shown in Figure 3 illustrates the use of a
MT327xB in a typical receiver application. It requires
only a coupling capacitor (C1) and a crystal or
ceramic resonator (X1) to complete the circuit.
Table 4. Recommended Resonator and Crystal
Specifications
Note:
Qm=quality factor of RLC model, i.e., 1/2ΠƒR1C1.
The MT3x70B is designed for user who wishes to
tailor the guard time for specific applications. When
a DTMF signal is present, the ESt pin will go high.
An external microcontroller monitors ESt in real time
for a period of time set by the user. A guard time
algorithm must be implemented such that DTMF
signals not meeting the timing requirements are
rejected. The MT3x71B uses an internal counter to
provide a preset DTMF validation period. It requires
no external components. The DStD output high
indicates that a valid DTMF digit has been detected.
L1
C1
R1
C0
R1 = Equivalent resistor.
L1 = Equivalent inductance.
C1 = Equivalent compliance.
C0 = Capacitance between electrode.
Resonator and Crystal Electric Equivalent Circuit
Oscillator
The 4.194304 MHz frequency has a secondary
advantage in some applications where a real time
The MT327xB/337xB can be used in both external
clock or two pin oscillator mode. In two pin oscillator
mode, the oscillator circuit is completed by
connecting either a 4.194304 MHz crystal or ceramic
resonator across OSC1 and OSC2 pins.
Specifications of the ceramic resonator and crystal
are tabulated in Table 4. It is also possible to
configure a number of these devices employing only
a single oscillator crystal. The OSC2 output of the
first device in the chain is connected to the OSC1
input of the next device. Subsequent devices are
connected similarily. The oscillator circuit can also
clock is required.
4,194,304 cycles to provide a one second time base.
A 22-bit counter will count
VDD
C1
8
1
VDD
DTMF/CP Input
INPUT
MT327xB
7
6
2
3
OSC2
ESt/DStD
ACK
X1
To microprocessor or
microcontroller
OSC1
VSS
5
4
SD
COMPONENTS LIST:
C1 = 0.1 µF ± 10 %
X1 = Crystal or Resonator (4.194304 MHz)
Figure 3 - Application Circuit for MT327xB
4-7
MT3170B/71B, MT3270B/71B, MT3370B/71B
Absolute Maximum Ratings† - Voltages are with respect to VSS=0V unless otherwise stated.
Parameter
DC Power Supply Voltage
Symbol
Min
Max
Units
1
2
3
4
5
VDD-VSS
VI/O
II/O
6
V
V
Voltage on any pin (other than supply)
Current at any pin (other than supply)
Storage temperature
-0.3
-65
6.3
10
mA
°C
TS
150
500
Package power dissipation
PD
mW
† Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VSS=0V unless otherwise stated
‡
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
Positive Power Supply
VDD
fOSC
∆fOSC
Td
4.75
5.0
5.25
V
MHz
%
4.194304
Oscillator Clock Frequency
Oscillator Frequency Tolerance
Operating Temperature
±0.1
85
-40
25
°C
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to VDD=5V±5%,VSS=0V, and temperature -40 to 85°C, unless
otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
Operating supply current
Standby supply current
IDD
3
8
mA
µA
IDDQ
30
100
PWDN=5V, ACK=0V
ESt/DStD = SD = 0V
3a
3b
Input logic 1
VIH
VIH
4.0
3.5
V
V
Input logic 1
(for OSC1 input only)
MT327xB/MT337xB
MT327xB/MT337xB
4a
4b
Input logic 0
VIL
VIL
1.0
1.5
V
V
Input logic 0
(for OSC1 input only)
5
6
Input impedance (pin 1)
RIN
IPD
50
kΩ
Pull-down Current
(PWDN, ACK pins)
25
µA
with internal pull-down
resistor of approx.
200kΩ. PWDN/ACK = 5V
7
8
Output high (source) current
Output low (sink) current
IOH
IOL
0.4
1.0
4.0
9.0
mA
mA
VOUT=VDD-0.4V
VOUT=VSS+0.4V
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing
4-8
MT3170B/71B, MT3270B/71B, MT3370B/71B
AC Electrical Characteristics - voltages are with respect to VDD=5V±5%, VSS=0V and temperature -40 to +85°C unless
otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions*
1
Valid input signal level
-50
0
dBm
1,2,3,5,6,12
(each tone of composite signal)
2.45
775
mVRMS
2
3
4
5
6
7
8
9
Positive twist accept
Negative twist accept
Frequency deviation accept
Frequency deviation reject
Third tone tolerance
Noise tolerance
8
8
dB
dB
1,2,3,4,11,12,15
1,2,3,4,11,12,15
1,2,3,5,12
1,2,3,5,12,15
1,2,3,4,5,12
7,9,12
±1.5%± 2Hz
±3.5%
-16
-12
+15
dB
dB
Dial tone tolerance
dB
8,10,12
Supervisory tones detect level
(Total power)
-35
3
dBm
16
10 Supervisory tones reject level
11 Energy detector attack time
12 Energy detector decay time
-50
6.5
25
dBm
ms
16
16
16
tSA
tSD
1.0
ms
13a Powerdown time
13b Powerup time
10
30
50
ms
ms
ms
IDDQ ≤ 100µA
MT3170B/3370B
MT3171B/3371B
Note 14
14 Tone present detect time (ESt
logic output)
tDP
tDA
3
13
3
20
15
40
ms
ms
ms
ms
ms
ms
MT3x70B
MT3x70B
MT3x71B
MT3x71B
MT3x71B
MT3x71B
13,15
15 Tone absent detect time (ESt
logic output)
16 Tone duration accept
(DStD logic output)
tREC
tREC
tID
17 Tone duration reject
(DStD logic output)
20
20
18 Interdigit pause accept (DStD
logic output)
40
19 Interdigit pause reject (DStD
logic output)
tDO
20 Data shift rate 40-60% duty cycle fACK
1.0
3.0
MHz
ns
21 Propagation delay
(ACK to Data Bit)
tPAD
100
140
1MHz fACK
13,15
,
22 Data hold time (ACK to SD)
tDH
30
50
ns
13,15
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing
* Test Conditions
1. dBm refers to a reference power of 1 mW delivered into a 600 ohms load.
2. Data sequence consists of all DTMF digits.
3. Tone on = 40 ms, tone off = 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by ±1.5%± 2 Hz.
7. Bandwidth limited (0-3 kHz) Gaussian noise.
8. Precise dial tone frequencies are 350 Hz and 440 Hz (± 2%).
9. Referenced to lowest level frequency component in DTMF signal.
10. Referenced to the minimum valid accept level.
11. Both tones must be within valid input signal range.
12. External guard time for MT3x70B = 20ms.
13. Timing parameters are measured with 70pF load at SD output.
14. Time duration between PWDN pin changes from ‘1‘ to ‘0‘ and ESt/DStD becomes active.
15. Guaranteed by design and characterization. Not subject to production testing.
16. Value measured with an applied tone of 450 Hz.
4-9
MT3170B/71B, MT3270B/71B, MT3370B/71B
tDO
tREC
DTMF
Tone
#n + 1
DTMF
Tone #n
DTMF
Tone #n + 1
Input
Signal
INPUT
tDA
tDP
ESt
(MT3x70B)
tID
tREC
DStD
(MT3x71B)
ACK
SD
tSA
tSD
LSB
LSB
MSB
MSB
Input
Signal
Envelope
b0b1b2b3
b0b1b2b3
tDO
tID
- maximum allowable dropout during valid DTMF signals. (MT3x7xB).
- minimum time between valid DTMF signals (MT3x71B).
t
t
REC - maximum DTMF signal duration not detected as valid (MT3x7xB).
REC - minimum DTMF signal duration required for valid recognition (MT3x71B).
tDA
tDP
tSA
tSD
- time to detect the absence of valid DTMF signals (MT3x70B).
- time to detect the presence of valid DTMF signals (MT3x70B).
- supervisory tone integrator attack time (MT3x7xB).
- supervisory tone integrator decay time (MT3x7xB).
Figure 4 - Timing Diagram
ESt/DStD
1/fACK
VIH
ACK
VIL
tPAD
tDH
VIH
DTMF Energy
Detect
DTMF Energy
Detect
SD
b0
b1
b2
b3
MSB
VIL
LSB
Figure 5 - ACK to SD Timing
4-10
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