MH88437AS-PI [MITEL]
Data Access Arrangement Advance Information; 数据访问安排超前信息
| 型号： | MH88437AS-PI |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | Data Access Arrangement Advance Information |
| 文件： | 总16页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MH88437-P
Data Access Arrangement
Advance Information
DS5060
ISSUE 4
October 1998
Features
•
•
•
FAX and Modem interface (V.34/V.34+)
Package Information
Designed to work at data rates up to 56kbits
MH88437AD-P 28 Pin DIL Package
MH88437AS-P 28 Pin SM Package
0˚C to 70˚C
External programmable line and network
balance impedances
•
•
•
•
•
•
•
Programmable DC termination characteristics
IEC950 recognised component
MH88437AD-PI Ind. Temp. DIL Variant
-40˚C to +80˚C
Transformerless 2-4 Wire conversion
Integral Loop Switch
MH88437AS-PI Ind. Temp. SM Variant
-40˚C to + 80˚C
Dial Pulse and DTMF operation
Accommodates parallel phone detection
•
•
Telemetry
Line state detection outputs:
-loop current/ringing voltage/line voltage
Set Top Boxes
•
•
•
•
•
•
•
+5V operation, low on-hook power (25mW)
Full duplex voice and data transmission
On-Hook reception from the line
Description
The Mitel MH88437 Data Access Arrangement
(D.A.A.) provides a complete interface between
audio or data transmission equipment and
telephone line. All functions are integrated into a
single thick film hybrid module which provides high
voltage isolation, very high reliability and optimum
circuit design, needing a minimum of external
components.
Meets French current limit requirements
Conforms to German dial pulse standards
Approvable to UL 1950
a
Industrial Temperature Range Available
Applications
Interface to Central Office or PABX line for:
•
•
•
FAX/Modem
The impedance and network balance are externally
programmable, as are the DC termination
characteristics, making the device suitable for most
countries worldwide.
Electronic Point of Sale
Security System
Isolation Barrier
VCC
VBIAS
AGND
CL
Opto-
Isolation
Logic Input
Buffer
LC
Input Buffer
&
Line Termination
TIP
VR+
Analog
Buffer
Isolation
RING
VR-
NB1
NB2
THL cancellation
and line
impedance
VX
ZA
Analog
Buffer
Isolation
Isolation
VLOOP1
VLOOP2
matching circuit
Ring & Loop
Buffer
RV
LCD
LOOP
RS
User Connections
Network Connections
Figure 1 - Functional Block Diagram
1
MH88437-P
Advance Information
NB1
NB2
VR+
VR-
VX
TIP
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
RING
IC
3
4
VLOOP1
VLOOP2
IC
5
6
LC
7
ZA
AGND
SC
SC
IC
8
9
VCC
10
11
12
13
14
VBIAS
NP
NP
CL
RV
LCD
LOOP
IC
RS
IC
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
NB1
Network Balance 1. External passive components must be connected between this pin and
NB2.
2
NB2
Network Balance 2. External passive components must be connected between this pin and
NB1.
3
4
5
VR+
VR-
VX
Differential Receive (Input). Analog input from modem/fax chip set.
Differential Receive (Input). Analog input from modem/fax chip set.
Transmit (Output). Ground referenced (AGND) output to modem/fax chip set, biased at
+2.0V.
6
7
LC
ZA
Loop Control (Input). A logic 1 applied to this pin activates internal circuitry which provides
a DC termination across Tip and Ring. This pin is also used for dial pulse application.
Line Impedance. Connect impedance matching components from this pin to Ground
(AGND).
8
9
AGND
Analog Ground. 4-Wire 0V reference connect to mains earth (ground).
Positive Supply Voltage. +5V.
V
CC
10
VBIAS
LOOP
IC
Internal Reference Voltage. +2.0V reference voltage. This pin should be decoupled
externally to AGND, typically with a 10µF 6.3V capacitor.
11
Loop (Output). The output voltage on this pin is proportional to the line voltage across Tip -
Ring, scaled down by a factor of 50.
12,
14
Internal Connection. No connection should be made to this pin externally.
13
RS
Ringing Sensitivity. Connecting a link or resistor between this pin and LOOP (pin 11) will
vary the ringing detection sensitivity of the module.
15
16
LCD
RV
Loop Condition Detect (Output). Indicates the status of loop current.
Ringing Voltage Detect (Output). The RV output indicates the presence of a ringing voltage
applied across the Tip and Ring leads.
17
CL
Current Limit. A logic 0 applied to this pin activates internal circuitry which limits the loop
current.
18
19
NP
NP
No Pin. Isolation Barrier, fitted, no pin fitted in this position.
No Pin. Isolation barrier, no pin fitted in this position
2
Advance Information
MH88437-P
Pin Description (continued)
Pin #
Name
Description
20,23
26
IC
Internal Connection. No connection should be made to this pin externally.
21,22
24
SC
Short Circuit. These two pins should be connected to each other via a 0Ω link.
VLOOP2 Loop Voltage Control Node 2. Used to set DC termination characteristics.
VLOOP1 Loop Voltage Control Node 1. Used to set DC termination characteristics.
25
27
RING
TIP
Ring Lead. Connects to the “Ring” lead of the telephone line.
Tip Lead. Connects to the “Tip” lead of the telephone line.
28
applications the MH88437 will comply with
Luxembourg and Italian specifications. For approval
in Denmark and Sweden the TRB21 route is
recommended.
Functional Description
The device is a Data Access Arrangement (D.A.A.). It
is used to correctly terminate a 2-Wire telephone
line. It provides a signalling link and a 2-4 Wire line
interface between an analog loop and subscriber
data transmission equipment, such as Modems,
Facsimiles (Fax’s), Remote Meters, Electronic Point
of Sale equipment and Set Top Boxes.
Approval specifications are regularly changing and
the relevant specification should always be consulted
before commencing design.
Line Termination
Isolation Barrier
When Loop Control (LC) is at a logic 1, a line
termination is applied across Tip and Ring. The
device can be considered off-hook and DC loop
current will flow. The line termination consists of both
a DC line termination and an AC input impedance. It
is used to terminate an incoming call, seize the line
for an outgoing call, or if it is applied and
disconnected at the required rate, can be used to
generate dial pulses.
The device provides an isolation barrier capable of
meeting the supplementary barrier requirements of
the international standard IEC 950 and the national
variants of this scheme such as EN 60950 for
European applications and UL 1950 for North
American applications.
External Protection Circuit
The DC termination resembles approximately 300Ω
resistance, which is loop current dependent.
Furthermore, it can be programmed to meet different
national requirements. For normal operation
VLOOP3 should be open circuit and a resistor (R2)
should be fitted between VLOOP1 and VLOOP2, as
shown in Figure 4.
An External Protection Circuit assists in preventing
damage to the device and the subscriber equipment,
due to over-voltage conditions. See Application Note
MSAN-154 for recommendations.
Suitable Markets
The approval specification will give a DC mask
characteristic that the equipment will need to comply
to. The DC mask specifies the amount of current the
DAA can sink for a given voltage across tip and ring.
Graph 1 shows how the voltage across tip and ring
varies with different resistors (R2) for a given loop
current.
The MH88437 has features such as programmable
line and network balance impedance, programmable
DC termination and a supplementary isolation
barrier. For countries that do not need to meet the
French and German requirements there is a pin for
pin compatible device the MH88435.
There are, however, a small number of countries with
a 100MΩ leakage requirement that this device does
not meet. These are Belgium, Greece, Italy,
Network Balance
Luxembourg,
Spain
and
Poland.
Although
The network balance impedance of the device can
be programmed by adding external components By
Luxembourg will now accept TBR21 and there are
exceptions to the Italian specification, in most
3
MH88437-P
Advance Information
40
35
30
25
Iloop=15mA
Iloop=20mA
V(t-r)
20
Iloop=26mA
15
10
5
0
50
150
250
350
450
550
650
750
850
950
R2(kOhms)
Figure 3 - DC Programming Capability
applying a logic 0 to Pin 17, CL, the loop current will
be limited to below 60mA as required in France and
the European TBR21 specification. For all other
countries where current limiting is not required, CL
should be set to 1.
To find the external programming components for
configuration 4, the following formula should be
used:
Zext = [(10 x R1)-1k3]+[(10 x R2)//(C1/10)]
The AC input impedance should be set by the user to
match the line impedance.
e.g. If the required input impedance = 220Ω + (820Ω/
/115nF), the external network to be connected to ZA
will be:
Input Impedance
ZA = 900Ω + (8k2Ω//12nF)
Where the input impedance (Z) = 600R the equation
can be simplified to:
The MH88437 has a programmable input impedance
set by fitting external components between the ZA
pin and AGND.
ZA = (10 x Z) - 1k3Ω
ZA = 4k7Ω
For complex impedances the configuration shown in
Figure 4 (below) is most commonly found.
Note: A table of commonly used impedances can be
found in the DAA Application’s document MSAN-154.
R2
R1
Where Zext = external network connected between
ZA and AGND and Zint = 1.3kΩ (internal resistance)
C1
between NB1 and NB2. For countries where the
balance impedance matches the line impedance, a
16kΩ resistor should be added between NB1 and
NB2.
Figure 4 - Complex Impedances
4
Advance Information
MH88437-P
Ringing Voltage Detection
2-4 Wire Conversion
The sensitivity of the ringing voltage detection
circuitry can be adjusted by applying an external
resistor (R7, Figure 5) between the RS and LOOP
pins. With a short circuit, the threshold sensitivity is
~10Vrms, therefore R7 = 30kΩ x (Desired threshold
voltage - 10Vrms).
The device converts the balanced 2-Wire input,
presented by the line at Tip and Ring, to a ground
referenced signal at VX, biased at 2.0V. This
simplifies the interface to a modem chip set.
Conversely, the device converts the differential signal
input at VR+ and VR- to a balanced 2-Wire signal at
Tip and Ring. The device can also be used in a
single ended mode at the receive input, by leaving
VR+ open circuit and connecting the input signal to
VR- only. Both inputs are biased at 2.0V.
Example: 300kΩ gives ~20Vrms and 600kΩ gives
~30Vrms.
An AC ringing voltage across Tip and Ring will cause
RV to output TTL pulses at the ringing frequency,
with an envelope determined by the ringing cadence.
During full duplex transmission, the signal at Tip and
Ring consists of both the signal from the device to
the line and the signal from the line to the device.
The signal input at VR+ and VR- being sent to the
line, must not appear at the output VX. In order to
prevent this, the device has an internal cancellation
circuit, the measure of this attenuation is Transhybrid
Loss (THL).
Parallel Phone and Dummy Ringer
An external parallel phone or dummy ringer circuit
can be connected across Tip and Ring as shown in
Figure 5. A Dummy Ringer is an AC load which
represents a telephone’s mechanical ringer.
The MH88437 has the ability to transmit analog
signals from Tip and Ring through to VX when on-
hook. This can be used when receiving caller line
identification information.
In normal circumstances when a telephone is On-
Hook and connected to the PSTN, its AC (Ringer)
load is permanently presented to the network. This
condition is used by many PTT’s to test line
continuity, by placing a small AC current onto the line
and measuring the voltage across tip (A) and ring
(B).
Transmit Gain
The Transmit Gain of the MH88437 is the gain from
the differential signal across Tip and Ring to the
ground referenced signal at VX. The internal
Transmit Gain of the device is fixed as shown in the
AC Electrical Characteristics table. For the correct
gain, the Input Impedance of the MH88437, must
match the specified line impedance.
Today’s telecom equipment may not have an AC load
present across tip and ring (e.g. modems), therefore
any testing carried out by the PTT will see an open
circuit across tip and ring. In this instance the PTT
assumes that the line continuity has been damaged.
To overcome this problem many PTT’s specify that a
"Dummy Ringer" is presented to the network at all
times. Ideally its impedance should be low in the
audio band and high at the ringing frequencies (e.g.
25Hz). Note that the requirement for the "Dummy
Ringer" is country specific.
By adding an external potential divider to VX, it is
possible to reduce the overall gain in the application.
The output impedance of VX is approximately 10Ω
and the minimum resistance from VX to ground
should be 2kΩ.
Parallel phone detection is used mostly in set-top
box applications. This is when a modem call will
need to be disconnected from the central office by
the equipment when the parallel phone is in the off-
hook state. This is to allow the subscriber to make
emergency calls.
Example: If R3 = R4 = 2kΩ, in Figure 5, the overall
gain would reduce by 6.0dB.
Receive Gain
The Receive Gain of the MH88437 is the gain from
the differential signal at VR+ and VR- to the
differential signal across Tip and Ring. The internal
Receive Gain of the device is fixed as shown in the
AC Electrical Characteristics table. For the correct
To detect this state, additional circuitry will be
required. Refer to Application Note MSAN-154.
5
MH88437-P
Advance Information
gain, the Input Impedance of the MH88437 must
match the specified line impedance.
With an internal series input resistance of 47kΩ at
the VR+ and VR- pins, external series resistors can
be used to reduce the overall gain.
Overall Receive Gain
=
0dB+20log (47kΩ/
(47kΩ+R5)).
For differential applications R6 must be equal to R5
in Figure 5.
Example: If R5 = R6 = 47k in Figure 3, the overall
gain would reduce by 6.0dB.
Supervisory Features
The device is capable of monitoring the line
conditions across Tip and Ring, this is shown in
Figure 5. The Loop Condition Detect pin (LCD),
indicates the status of the line. The LCD output is at
logic 1 when loop current flows, indicating that the
MH88437 is in an off hook state. LCD will also go
high if a parallel phone goes off-hook. Therefore, line
conditions can be determined with the LC and the
LCD pins.
The LOOP pin output voltage VLOOP is proportional
to the line voltage across Tip and Ring scaled down
by a factor of 50 and offset by 2.0V(t-r). With the aid
of a simple external detector the LC, LCD and LOOP
pins can be used to generate the signals necessary
for parallel phone operation, e.g. with a Set Top Box.
See MSAN-154 for further details.
When the device is generating dial pulses, the LCD
pin outputs TTL pulses at the same rate. The LCD
output will also pulse if a parallel phone is used to
dial and when ringing voltage is present at Tip and
Ring.
Mechanical Data
See Figures 12, 13 and 14 for details of the
mechanical specification.
6
Advance Information
MH88437-P
+5V
R7
R2
21
C2
+
11
13
9 25 24
22
R4
R3
C4
C5
C6
Analog
Output
28
5
4
3
TIP
VX
VR-
VR+
TIP
R1
D1
R5
R6
Analog
Input
L2
MH88437
Analog
Input
16
15
RV
Ringing Voltage Detect Output
Loop Current Detect Output
Loop Control Input
D2
LCD
6
1
C1
C8
L1
LC
27
NB1
NB2
RING
RING
ZB
2
AGND VBIAS ZA
8
10
7
CL
C7
C3
Zext
+
Notes:
1) R1 & C1: Dummy Ringer, country specific
typically 0.39µF, 250V & 3kΩ
2)
R2: DC Mask Resistor 120kΩ typical
3)
4)
R3 & R4: Transmit Gain Resistors ≥ 2k2
R5 = R6: Receive Gain Resistors typically 100k
ZB: Network Balance Impedance
C2 & C3 = 10µF 6V
C7 & C8 = 39nF for 12kHz filter and 22nF for
16KHz filter. These can be left off if meter pulse
filtering not required.
5)
6)
7)
8)
9)
Zext: External Impedance
D1 Zener Diode 6V2
= Ground (Earth)
10)
L1, L2 = 4.7mH RDC<10Ω. These can be left
off if meter pulse filtering not required.
C4, C5 & C6 = 1µF coupling capacitors
11)
12) R7 = 620kΩ (30V RMS ringing sensitivity)
13) D2 = Teccor P2703 Protection
Figure 5 - Typical Application Circuit
7
MH88437-P
Advance Information
.
Absolute Maximum Ratings* - All voltages are with respect to AGND unless otherwise specified.
Parameter
DC Supply Voltage
Sym
Min
Max
Units
Comments
1
2
3
4
5
6
V
-0.3
-55
6
V
˚C
CC
Storage Temperature
DC Loop Voltage
Transient loop voltage
Ringing Voltage
T
+125
+110
300
S
V
V
-110
V
TR
TR
V
1ms On hook
VBAT = -56V
V
150
Vrms
R
Loop Current
I
60
90
mA
mA
CL=0 V
CL=1
≤40V
TIP-RING
LOOP
7
Ring Trip Current
ITRIP
180
mArms
250ms 10% duty cycle or
500ms single shot
*Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions
‡
Parameter
DC Supply Voltages
Sym
Min
Typ
Max
Units
V
Test Conditions
1
2
V
4.75
5.0
25
5.25
CC
Operating Temperatures
Industrial Temperature
T
0
-40
70
+85
˚C
OP
3
Ringing Voltage
V
75
90
Vrms VBat = -48V
R
‡ Typical figures are at 25˚C with nominal +5V supply and are for design aid only
Loop Electrical Characteristics †
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
Externally Adjustable
1
Ringing Voltage
VR
No Detect
Detect
7
Vrms
Vrms
14
15
15
2
3
Ringing Frequency
68
Hz
Operating Loop Current
60
80
mA
mA
CL=0 V
≤40V
TIP-RING
CL=1 (see Note 1)
4
Off-Hook DC Voltage
Externally Adjustable
6.0
6.0
7.8
V
V
V
I
I
I
=15mA)
=20mA) (Note 3)
26mA)
LOOP
LOOP
LOOP=
where R2 = 110kΩ
5
6
7
8
Leakage Current
(Tip or Ring to AGND)
10
7
µA
mA
100V DC (see Note 2)
1000V AC
Leakage Current on-hook
(Tip to Ring)
9
18
10
20
µΑ
V
V
(= -50V)
(= -100V)
BAT
BAT
Dial Pulse Detection
ON
OFF
0
0
+1
+1
+2
+2
ms
ms
Dial pulse delay
Loop Condition Detect Threshold
Off-Hook
Voltage across tip and
ring
5
16
V
† Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated.
‡ Typical figures are at 25°C with nominal + 5V supplies and are for design aid only.
Note 1: Low Loop current operation depends on value of resistor connected between V
Note 2: This is equivalent to 10MΩ leakage Tip/Ring to Ground.
Note 3. Refer to EIA/TIA 464 Section 4.1.1.4.4
1 and V
2.
Loop
Loop
8
Advance Information
MH88437-P
)
Variations from Standard Loop Electrical Characteristics
(MH88437AD-PI/MH88437AS-PI) (+70˚C to +85˚C)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Operating Loop Current
16
60
80
mA
mA
CL\=0
CL\=1
DC Electrical Characteristics †
‡
Characteristics
Sym
Min Typ
Max
Units
Test Conditions
1
2
Supply Current
I
5
mA
V
(= 5.0V, On-hook)
DD
CC
RV,
LCD
Low Level Output Voltage
High Level Output Voltage
V
V
0.4
0.8
V
V
I
I
= 4mA
= 0.4mA
OL
OL
2.4
OH
OH
3
LC
Low Level Input Voltage
High Level Input Voltage
Low Level Input Current
High Level Input Current
V
V
I
I
V
V
µA
µA
IL
IH
IL
2.0
0
60
400
V = 0.0V
IL
V
350
= 5.0V
IH
IH
4
VR+
VR-
DC common mode
VCM
0
2
VCC
VDC
Use coupling caps for
higher voltages and single
ended
† Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated.
‡ Typical figures are at 25°C with nominal + 5V supplies and are for design aid only.
AC Electrical Characteristics †
‡
Characteristics
Sym
Min
Typ
Max Units
Test Conditions
1
Input Impedance
47k
94k
Ω
Ω
VR-
VR+
2
3
Output Impedance at VX
10
0
Ω
Receive Gain (VR to 2-Wire)
-1
1
Test circuit (Figure 8)
Input 0.5V at 1kHz
dB
4
5
Frequency Response Gain
(relative to Gain @ 1kHz)
-0.5
0
0.5
dB
ILOOP = 15-60mA
300Hz to 3400 Hz
Signal Output Overload Level
at 2-Wire
at VX
THD < 5% @ 1kHz
0
0
dBm
dBm
I
= 25-60mA
LOOP
VCC = 5V
6
7
Signal/Noise & Distortion
SINAD
PSRR
Input 0.5V at 1kHz
at 2-Wire
at VX
70
70
dB
dB
I
= 25-60mA
LOOP
300-3400Hz
Power Supply Rejection Ratio
Ripple 0.1Vrms 1kHz on
at 2-Wire
at VX
25
25
40
40
dB
dB
V
DD
8
9
Transhybrid Loss
THL
Zin
16
25
dB
Test circuit (Figure 8)
300-3400Hz at V
R
2-Wire Input Impedance
Note 3
Ω
@ 1kHz
9
MH88437-P
Advance Information
AC Electrical Characteristics † (continued)
‡
Characteristics
Sym
Min
Typ
Max Units
Test Conditions
10 Return Loss at 2-Wire
RL
Test circuit(Figure 9)
200-500Hz
500-2500Hz
(Reference 600Ω)
14
20
18
24
24
24
dB
dB
dB
2500-3400Hz
11 Longitudinal to Metallic Balance
Metallic to Longitudinal Balance
Nc
Test circuit (Figure 10)
300-1000Hz
1000-3400Hz
Test circuit (Figure 11)
200-1000Hz
1000-4000Hz
46
46
58
53
dB
dB
60
40
dB
dB
12 Idle Channel Noise
at 2-Wire
at VX
at 2-Wire
at VX
15
15
-65
-65
20
20
dBrnC Cmess filter
dBrnC
dBm
300-3400Hz filter
dBm
13 Transmit Gain (2-Wire to VX)
Off-Hook
Test circuit (Figure 7)
Input 0.5V @ 1kHz
-1
0
0
+1
dB
dB
On-Hook
LC = 0V
14 Frequency Response Gain
(relative to Gain @ 1kHz)
-0.5
-0.5
0
0
0.5
0.5
dB
dB
300Hz
3400Hz
15 Intermodulation Distortion
products at VX and 2W
IMD
75
dB
dB
dB
I
= 25-60mA
LOOP
F1 = 1kHz at -6dBm
F2 = 800Hz at -6dBm
Total signal power =
-3dBm
16 Distortion at VX due to near end
echo
75
I
= 25-60mA
LOOP
F1 = 1kHz at -6dBm
F2 = 800Hz at -6dBm
Total signal power =
-3dBm
(300Hz - 3400Hz bandwidth)
17 Common Mode Rejection at VX
18 Common Mode overload
CMR
CML
50
Test circuit (Figure 10)
1-100Hz Note 4
100V
V
Test circuit (Figure 10)
1-100Hz Note 4
pk-pk
† Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated.
‡ Typical figures are at 25°C with nominal + 5V supplies and are for design aid only.
Variations from Standard AC Electrical Characteristics
(MH88437AD-PI/MH88437AS-PI) (-40˚C to 0˚C)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
Receive Gain (VR to 2-Wire)
-1.1
dB
Test circuit (Figure 8)
Input 0.5V at 1kHz
Frequency Response Gain
(Relative to Gain @ 1kHz)
-1.2
dB
dB
I
= 16-60mA
LOOP
300Hz to 3400Hz
Transhybrid Loss
THL
-12
-15
300Hz to 1kHz
1kHz to 3400Hz
10
Advance Information
MH88437-P
15
13
RS
11
LOOP
VR+
LCD
TIP
ILOOP
16K
3
4
5
28
1
VR-
NB1
NB2
DUT
VX
21
22
23
2
VLOOP5
VLOOP4
VLOOP3
VLOOP2
VLOOP1
27
10
RING
82K
24
25
VBIAS
10uF
+
LC RV AGND VCC ZA
9
7
6
16
8
1K
4.7K
5V
= Ground (Earth)
5V
Figure 6 - Test Circuit 1
-V
10H 500Ω
15
13
11
100uF
+
RS
LOOP
VR+
LCD
TIP
3
4
5
I=20mA
28
1
VR-
NB1
DUT
VX
16K
Vs
21
22
23
2
VLOOP5
NB2
Impedance = Zin
VLOOP4
VLOOP3
VLOOP2
VLOOP1
100uF
+
27
10
RING
82K
24
25
10H 500Ω
VBIAS
10uF
+
LC RV AGND VCC ZA
7
9
6
16
8
1K
4.7K
5V
5V
= Ground (Earth)
Gain = 20 * Log (VX / Vs)
Figure 7 - Test Circuit 2
11
MH88437-P
Advance Information
-V
10H 500Ω
15
13
RS
11
100uF
+
LOOP
VR+
LCD
TIP
I=20mA
3
4
5
28
1
Vs
VR-
NB1
NB2
DUT
VX
16K
Zin
21
22
23
2
VLOOP5
VLOOP4
VLOOP3
VLOOP2
VLOOP1
100uF
+
27
10
RING
82K
24
25
10H 500Ω
VBIAS
10uF
LC RV AGND VCC ZA
+
9
6
16
8
7
4.7K
1K
5V
5V
= Ground (Earth)
Gain = 20 * Log (V(Zin) / Vs)
Figure 8 - Test Circuit 3
-V
10H 500Ω
I=20mA
15
LCD
TIP
13
RS
11
100uF
+
LOOP
VR+
Zin
3
28
1
4
VR-
NB1
300Ω
V1
DUT
5
Vs = 0.5V
VX
16K
21
2
VLOOP5
NB2
300Ω
22
VLOOP4
100uF
+
23
27
10
RING
VLOOP3
82K
10H 500Ω
24
VLOOP2
25
VBIAS
VLOOP1
10uF
LC RV AGND VCC ZA
+
9
6
16
8
7
4.7K
1K
5V
5V
= Ground (Earth)
Return Loss = 20 * Log (V1 / Vs)
Figure 9 - Test Circuit 4
12
Advance Information
MH88437-P
-V
10H 500Ω
15
13
RS
11
100uF
+
I=20mA
LOOP
VR+
LCD
TIP
3
4
5
28
1
VR-
NB1
NB2
300Ω
DUT
VX
16K
V1
21
22
23
2
VLOOP5
Vs = 0.5V
300Ω
VLOOP4
VLOOP3
VLOOP2
VLOOP1
100uF
+
27
10
RING
82K
24
25
10H 500Ω
VBIAS
10uF
+
LC RV AGND VCC ZA
9
7
6
16
8
1K
4.7K
5V
5V
Long. to Met. Balance = 20 * Log (V1 / Vs)
CMR = 20 * Log (VX / Vs)
= Ground (Earth)
Figure 10 - Test Circuit 5
-V
10H 500Ω
15
LCD
TIP
13
RS
11
100uF
+
I=20mA
LOOP
VR+
3
4
5
28
1
VR-
NB1
DUT
300Ω
VX
16K
Vs
21
22
23
2
VLOOP5
NB2
V1
300Ω
100uF
510Ω
VLOOP4
VLOOP3
VLOOP2
VLOOP1
27
10
RING
+
82K
24
25
10H 500Ω
VBIAS
10uF
+
LC RV AGND VCC ZA
9
7
6
16
8
1K
4.7K
5V
5V
Met. to Long. Balance = 20 * Log (V1 / Vs)
= Ground (Earth)
Figure 11 - Test Circuit 6
13
MH88437-P
Advance Information
0.162 Max (4.12 Max)
0.27 Max
(6.9 Max)
0.063 Max
(1.6 Max)
0.08 Typ (2 Typ)
*
0.260+0.015
(6.6+0.38)
1.00 Typ
(25.4 Typ)
*
0.100+0.010
(2.54+0.25)
*
0.05 Typ
(1.27 Typ)
1.05 Max
0.020 + 0.005
(0.5 + 0.13)
(26.7 Max)
*
0.300+0.010
(7.62+0.25)
Notes:
1) Not to scale
2) Dimensions in inches.
(Dimensions in millimetres)
1
3) Pin tolerances are non-accumulative.
4) Recommended soldering conditions:
Wave Soldering - Max temp at pins 260˚C for 10 secs.
1.42 Max
(36.1 Max)
* Dimensions to centre of pin.
Figure 12 - Mechanical Data for 28 Pin DIL Hybrid
0.162 Max (4.11 Max)
0.265 Max
(6.73 Max)
0.063 Max
(1.6 Max)
0.9 + 0.015
(2.3 + 0.38)
(0.5 + 0.13)
0.99 Typ
(25.15 Typ)
0.020 + 0.005
*
0.05 Typ
(1.27 Typ)
*
0.100+0.010
(2.54+0.25)
*
0.300+0.010
(7.62+0.25)
0.060 Typ
(1.52 Typ)
Notes:
1.15 Max
(29.2 Max)
1) Not to scale
2) Dimensions in inches.
(Dimensions in millimetres)
1
3) Pin tolerances are non-accumulative.
4) Recommended soldering conditions:
Max reflow temp: 220˚C for 10 secs.
* Dimensions to centre of pin.
1.42 Max
(36.1 Max)
Figure 13 - Mechanical Data for 28 Pin Surface Mount Hybrid
14
Advance Information
MH88437-P
0.10
(2.54)
*
0.26
(6.60)
0.10
(2.54)
0.97
(24.64)
0.06
(1.52)
0.04
(1.02)
Notes:
1) Not to scale
2) Dimensions in inches.
(Dimensions in millimetres)
3) All dimensions are Typical except
where marked with an. This gap is
associated with the isolation barrier.
Figure 14 - Recommended Footprint for 28 Pin Surface Mount Hybrid
15
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