3KDAT-31R5-SP+T [MINI]
Variable Attenuator, 0MHz Min, 2400MHz Max, 2.4dB Insertion Loss-Max, 4 X 4 MM, ROHS COMPLIANT, DG983-1, 20 PIN;
| 型号： | 3KDAT-31R5-SP+T |
| 厂家： | 
MINI-CIRCUITS |
| 描述： | Variable Attenuator, 0MHz Min, 2400MHz Max, 2.4dB Insertion Loss-Max, 4 X 4 MM, ROHS COMPLIANT, DG983-1, 20 PIN 衰减器 射频 微波 |
| 文件： | 总12页 (文件大小：531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Digital Step Attenuator
50Ω DC-2400 MHz
31.5 dB, 0.5 dB Step
6 Bit, Serial Control Interface, Single Positive Supply Voltage, +3V
Product Features
• Single positive supply voltage, +3V
• Immune to latch up
• Excellent accuracy, 0.1 dB Typ
• Serial control interface
• Low Insertion Loss
• High IP3, +52 dBm typ.
• Very low DC power consumption
• Excellent return loss, 20 dB Typ
DAT-31R5-SP+
+ RoHS compliant in accordance
• Small size 4.0 x 4.0 mm
with EU Directive (2002/95/EC)
The +Suffix has been added in order to identify RoHS
Compliance. See our web site for RoHS Compliance
methodologies and qualifications.
Typical Applications
• Base Station Infrastructure
• Portable Wireless
• CATV & DBS
• MMDS & Wireless LAN
• Wireless Local Loop
• UNII & Hiper LAN
• Power amplifier distortion canceling loops
General Description
The DAT-31R5-SP+ is a 50Ω RF digital step attenuator that offers an attenuation range up to 31.5 dB in
0.5 dB steps. The control is a 6-bit serial interface, operating on a single +3 volt supply. The DAT-31R5-SP+
is produced using a unique CMOS process on silicon, offering the performance of GaAs, with the advantages
of conventional CMOS devices.
Simplified Schematic
RF Input
RF Out
16dB
8dB
4dB
0.5dB
2dB
1dB
Digital Serial Control
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REV. D
M114163
DAT-31R5-SP+
071025
Page 1 of 12
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DAT-31R5-SP+
Digital Step Attenuator
RF Electrical Specifications, DC-2400 MHz, TAMB=25°C, VDD=+3V
Freq. Range
Parameter
Min.
Typ.
Max.
Units
(GHz)
DC-1
1-2.4
DC-1
1-2.4
DC-1
1-2.4
DC-1
1-2.4
DC-1
1-2.4
DC-1
1-2.4
—
—
—
—
—
—
—
—
—
—
—
—
0.03
0.05
0.02
0.05
0.05
0.15
0.07
0.15
0.03
0.15
0.1
0.1
0.15
0.1
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Accuracy @ 0.5 dB Attenuation Setting
Accuracy @ 1 dB Attenuation Setting
Accuracy @ 2 dB Attenuation Setting
Accuracy @ 4 dB Attenuation Setting
Accuracy @ 8 dB Attenuation Setting
Accuracy @ 16 dB Attenuation Setting
0.15
0.15
0.25
0.2
0.25
0.2
0.25
0.3
0.15
0.3
DC-1
1-2.4
—
—
—
1.3
1.6
1.9
2.4
—
dB
dB
Insertion Loss(note1) @ all attenuator set to 0dB
Input IP3(note 2) (at Min. and Max. Attenuation)
DC-2.4
+52
dBm
Input Power @ 0.2dB Compression*
(at Min. and Max. Attenuation)
DC-2.4
—
+24
—
dBm
DC-1
1-2.4
—
—
1.2
1.2
1.5
1.5
—
—
VSWR
Notes:
1. I. Loss values are de-embedded from test board Loss (test board’s Insertion Loss: 0.10dB @100MHz, 0.35dB @1000MHz,
0.60dB @2400MHz, 0.75dB @4000MHz)
2. Input IP3 and 1dB compression degrades below 1 MHz
DC Electrical Specifications
Parameter
DD, Supply Voltage
DD, Supply Current
Min.
Typ.
Max.
Units
V
2.7
—
3
3.3
100
V
μA
V
I
—
—
—
Control Input Low
Control Input High
Control Current
—
0.3xVDD
—
0.7xVDD
V
—
—
1
μA
Switching Specifications
Parameter
Min.
—
Typ.
1.0
—
Max.
—
Units
Switching Speed, 50% Control to 0.5dB
of Attenuation Value
μ
Sec
Switching Control Frequency
—
25
KHz
Absolute Maximum Ratings
Parameter
Ratings
-40°C to 85°C
-55°C to 100°C
-0.3V Min., 4V Max.
-0.3V Min., VDD+0.3V Max.
500V
Operating Temperature
Storage Temperature
VDD
Voltage on any input
ESD, HBM
ESD, MM
100V
Input Power
+24dBm
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Digital Step Attenuator
DAT-31R5-SP+
Pin Description
Pin Configuration (Top View)
Pin
Number
Function
Description
C16
RF in
Data
Clock
LE
1
2
Control for Attenuation bit, 16 dB (Notes 3,4)
RF in port (Note 1)
3
Serial Interface data input (Note 3)
Serial Interface clock input
Latch Enable Input (Note 2)
Power Supply
1
2
3
4
5
15
14
13
12
11
C8
C16
RFin
Data
Clock
4
RFout
VDD
GND
GND
2x2mm
Paddle
ground
5
VDD
6
N/C
7
Not connected
N/C
8
Not connected
LE
VDD
9
Power Supply
GND
GND
GND
VDD
10
11
12
13
14
15
16
17
18
19
20
Paddle
Ground connection
Ground connection
Ground connection
Power Supply
RF out
C8
RF out port (Note 1)
Control for attenuation bit, 8 dB (Note 4)
Control for attenuation bit, 4 dB (Note 4)
Control for attenuation bit, 2 dB (Note 4)
Ground Connection
C4
C2
GND
C1
Control for attenuation bit, 1 dB (Note 4)
Control for attenuation bit, 0.5 dB (Note 4)
Paddle ground (Note 5)
C0.5
GND
Notes:
1. Both RF ports must be held at 0VDC or DC blocked with an external series capacitor.
2. Latch Enable (LE) has an internal 100KΩ resistor to VDD
.
3. Place a 10KΩ resistor in series, as close to pin as possible to avoid freq. resonance.
4. Refer to Power-up Control Settings.
5. The exposed solder pad on the bottom of the package (See Pin Configuration) must
be grounded for proper device operation
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Page 3 of 12
DAT-31R5-SP+
Digital Step Attenuator
Typical Performance Curves
INSERTION LOSS (Ref) @ +25°C, +85°C, -45°C
ATTENUATION (0.5dB) @ +25°C, +85°C, -45°C
8
7
6
5
4
3
2
1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
+85°C
+25°C
-45°C
-45°C
+25°C
+85°C
0
0
0
500
500
500
1000
1500
2000
2500
3000
3500
4000
4000
4000
0
0
0
500
500
500
1000
1500
2000
2500
3000
3500
4000
4000
4000
Frequency (MHz)
Frequency (MHz)
ATTENUATION (1dB) @ +25°C, +85°C, -45°C
ATTENUATION (2dB) @ +25°C, +85°C, -45°C
2.5
2.4
2.3
2.2
2.1
2
1.5
1.4
1.3
1.2
1.1
1
1.9
1.8
1.7
1.6
1.5
0.9
0.8
0.7
0.6
0.5
-45°C
+25°C
+85°C
-45°C
+25°C
+85°C
1000
1500
2000
2500
3000
3500
1000
1500
2000
2500
3000
3500
Frequency (MHz)
Frequency (MHz)
ATTENUATION (4dB) @ +25°C, +85°C, -45°C
ATTENUATION (8dB) @ +25°C, +85°C, -45°C
9
8.8
8.6
8.4
8.2
8
4.5
4.4
4.3
4.2
4.1
4
7.8
7.6
7.4
7.2
7
3.9
3.8
3.7
3.6
3.5
-45°C
+25°C
+85°C
-45°C
+25°C
+85°C
1000
1500
2000
2500
3000
3500
1000
1500
2000
2500
3000
3500
Frequency (MHz)
Frequency (MHz)
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ꢓꢔꢕꢖꢔꢃꢗꢖꢘꢓꢙꢚꢛꢜꢉꢃꢘꢙꢗꢝꢙꢞꢉꢞꢀꢋ
DAT-31R5-SP+
Digital Step Attenuator
Typical Performance Curves
ATTENUATION (16dB) @ +25°C, +85°C, -45°C
ATTENUATION (31.5dB) @ +25°C, +85°C, -45°C
17
16.8
16.6
16.4
16.2
16
32
31
30
29
28
27
26
-45°C
+25°C
+85°C
-45°C
+25°C
+85°C
15.8
15.6
15.4
15.2
15
0
500
1000
1500
2000
2500
3000
3500
4000
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency (MHz)
Frequency (MHz)
RETURN LOSS IN S11 (REF) @ +25°C, +85°C, -45°C
RETURN LOSS OUT S22 (REF) @ +25°C, +85°C, -45°C
50
40
30
20
10
0
50
40
30
20
10
0
-45°C
+25°C
+85°C
-45°C
+25°C
+85°C
0
500
1000
1500
2000
2500
3000
3500
4000
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency (MHz)
Frequency (MHz)
RETURN LOSS OUT S22 (Major Attenuation Steps) @+25°C
RETURN LOSS IN S11(Major Attenuation Steps) @ +25°C
60
50
40
30
20
10
0
60
50
40
30
20
10
0
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=16dB
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=16dB
ATT=31.5dB
ATT=31.5dB
0
500
1000
1500
2000
2500
3000
3500
4000
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency (MHz)
Frequency (MHz)
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ꢀꢁꢂꢃꢄꢂꢅꢆꢇꢈꢃꢉꢈꢇꢆꢈꢂꢂꢊꢅꢃꢋꢂꢌꢊꢍꢁꢃꢉꢈꢇꢆꢈꢂꢃꢃꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢊꢋꢌꢉꢍꢈꢎꢏꢐꢏꢈꢑꢒꢇꢐꢏꢒꢐꢓꢔꢈꢕꢁꢂꢖꢈꢗꢑꢘꢑꢙꢊꢑꢚꢊꢌꢑꢋꢛ ꢉꢐꢜꢃ ꢎꢏꢆꢈꢆꢍꢆꢊꢍꢐꢆꢑꢅꢎꢍꢒꢏ
Page 5 of 12
ꢓꢔꢕꢖꢔꢃꢗꢖꢘꢓꢙꢚꢛꢜꢉꢃꢘꢙꢗꢝꢙꢞꢉꢞꢀꢋ
DAT-31R5-SP+
Digital Step Attenuator
Typical Performance Curves
IP-3 INPUT (Major Attenuation Steps) @ +85°C
IP-3 INPUT (Major Attenuation Steps) @ +25°C
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=16dB
ATT=31.5dB
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=16dB
ATT=31.5dB
0
0
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
IP-3 INPUT (Major Attenuation Steps) @ -45°C
COMPRESSION @INPUT POWER=+24dBm (+25°C)
0.2
0
70
60
50
40
30
20
10
0
-0.2
-0.4
-0.6
-0.8
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=16dB
ATT=31.5dB
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=16dB
ATT=31.5dB
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
COMPRESSION @INPUT POWER=+24dBm (-45°C)
COMPRESSION @INPUT POWER=+24dBm (+85°C)
0.2
0
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.2
-0.4
-0.6
-0.8
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=16dB
ATT=31.5dB
ATT=0dB
ATT=0.5dB
ATT=1dB
ATT=2dB
ATT=4dB
ATT=8dB
ATT=16dB
ATT=31.5dB
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
ꢂꢃꢄꢅ
ꢀ
ꢀꢁꢁ
ꢊꢋꢁꢂꢁꢆꢁꢅꢆꢇꢁꢈꢉꢌꢆꢍꢋ
ꢀꢁꢂꢁꢃꢄꢁꢅꢆꢇꢁꢈꢉ
ꢀꢁꢂꢃꢄꢅꢅꢆꢃꢃꢀꢁꢂꢃꢆꢇꢅꢅꢆ ꢀꢁꢂꢃꢄꢅꢄꢁꢆ
ꢀꢁꢂꢁꢃꢄ'.ꢃꢅꢆꢇꢈꢉꢉꢊꢃꢄ)''#$/&ꢊꢃꢋꢌ-ꢃꢍ')#ꢃꢈꢈꢎꢅꢆꢏꢇꢇꢇꢅꢃꢐꢑꢈꢒꢓꢃꢔꢅꢕꢏꢕꢆꢇꢇꢃꢃꢖꢗ.ꢃꢐꢑꢈꢒꢓꢃꢅꢅꢎꢏꢕꢉꢉꢈꢃꢖ')ꢃꢘꢌ+ꢗ"$ꢌꢘꢃ(ꢌ)ꢙ')%ꢗ&ꢚꢌꢃ*(ꢌꢚ*ꢃꢛꢃ*!'(("& ꢃ'&$"&ꢌꢃ*ꢌꢌꢃꢜ"&"ꢏꢝ")ꢚ,"+*ꢃ-ꢌꢞꢃ*"+ꢌ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇꢈꢃꢉꢈꢇꢆꢈꢂꢂꢊꢅꢃꢋꢂꢌꢊꢍꢁꢃꢉꢈꢇꢆꢈꢂꢃꢃꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢊꢋꢌꢉꢍꢈꢎꢏꢐꢏꢈꢑꢒꢇꢐꢏꢒꢐꢓꢔꢈꢕꢁꢂꢖꢈꢗꢑꢘꢑꢙꢊꢑꢚꢊꢌꢑꢋꢛ ꢉꢐꢜꢃ ꢎꢏꢆꢈꢆꢍꢆꢊꢍꢐꢆꢑꢅꢎꢍꢒꢏ
Page 6 of 12
ꢓꢔꢕꢖꢔꢃꢗꢖꢘꢓꢙꢚꢛꢜꢉꢃꢘꢙꢗꢝꢙꢞꢉꢞꢀꢋ
Digital Step Attenuator
DAT-31R5-SP+
Outline Drawing (DG983-1)
PCB Land Pattern
Suggested Layout,
Tolerance to be within .002
Device Marking
Pin 1
Index
MCL
31R5
+
Date
Code
inch
Outline Dimensions (
)
mm
E
WT.
GRAMS
A
B
C
D
F
G
H
J
K
L
M
N
P
Q
R
.157
.157
.035 .008 .081 .081 .010
—
.022
.020
.166
.166
.070
.012
.026
.070
.04
4.00
4.00
0.90 0.20 2.06 2.06 0.25
—
0.56
0.50
4.22
4.22
1.78
0.31
0.66
1.78
ꢂꢃꢄꢅ
ꢀ
ꢀꢁꢁ
ꢊꢋꢁꢂꢁꢆꢁꢅꢆꢇꢁꢈꢉꢌꢆꢍꢋ
ꢀꢁꢂꢁꢃꢄꢁꢅꢆꢇꢁꢈꢉ
ꢀꢁꢂꢃꢄꢅꢅꢆꢃꢃꢀꢁꢂꢃꢆꢇꢅꢅꢆ ꢀꢁꢂꢃꢄꢅꢄꢁꢆ
ꢀꢁꢂꢁꢃꢄ'.ꢃꢅꢆꢇꢈꢉꢉꢊꢃꢄ)''#$/&ꢊꢃꢋꢌ-ꢃꢍ')#ꢃꢈꢈꢎꢅꢆꢏꢇꢇꢇꢅꢃꢐꢑꢈꢒꢓꢃꢔꢅꢕꢏꢕꢆꢇꢇꢃꢃꢖꢗ.ꢃꢐꢑꢈꢒꢓꢃꢅꢅꢎꢏꢕꢉꢉꢈꢃꢖ')ꢃꢘꢌ+ꢗ"$ꢌꢘꢃ(ꢌ)ꢙ')%ꢗ&ꢚꢌꢃ*(ꢌꢚ*ꢃꢛꢃ*!'(("& ꢃ'&$"&ꢌꢃ*ꢌꢌꢃꢜ"&"ꢏꢝ")ꢚ,"+*ꢃ-ꢌꢞꢃ*"+ꢌ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇꢈꢃꢉꢈꢇꢆꢈꢂꢂꢊꢅꢃꢋꢂꢌꢊꢍꢁꢃꢉꢈꢇꢆꢈꢂꢃꢃꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢊꢋꢌꢉꢍꢈꢎꢏꢐꢏꢈꢑꢒꢇꢐꢏꢒꢐꢓꢔꢈꢕꢁꢂꢖꢈꢗꢑꢘꢑꢙꢊꢑꢚꢊꢌꢑꢋꢛ ꢉꢐꢜꢃ ꢎꢏꢆꢈꢆꢍꢆꢊꢍꢐꢆꢑꢅꢎꢍꢒꢏ
ꢓꢔꢕꢖꢔꢃꢗꢖꢘꢓꢙꢚꢛꢜꢉꢃꢘꢙꢗꢝꢙꢞꢉꢞꢀꢋ
Page 7 of 12
DAT-31R5-SP+
Digital Step Attenuator
Suggested Layout for PCB Design (PL-182)
The suggested Layout shows only the footprint area of the DAT, and the components located near this area
(i.e.: R1-R7). For the complete Layout, see photo and schematic diagram on page 11 of 12.
NOTES:
1. TRACE WIDTH IS SHOWN FOR FR4 WITH DIELECTRIC THICKNESS.
.025” .002”. COPPER: 1/2 Oꢀ. EACH SIDE.
FOR OTHER MATERIALS TRACE WIDTH MAY NEED TO BE MODIFIED.
2. 0603 SIꢀE CHIP FOOT PRINTS SHOWN FOR REFERENCE,
VALUES OF RESISTORS WILL VARY BASED ON APPLICATION.
3. BOTTOM SIDE OF THE PCB IS CONTINUOUS GROUND PLANE.
DENOTES PCB COPPER LAYOUT WITH SMOBC
(SOLDER MASK OVER BARE COPPER)
DENOTES COPPER LAND PATTERN FREE OF SOLDERMASK
ꢂꢃꢄꢅ
ꢀ
ꢀꢁꢁ
ꢊꢋꢁꢂꢁꢆꢁꢅꢆꢇꢁꢈꢉꢌꢆꢍꢋ
ꢀꢁꢂꢁꢃꢄꢁꢅꢆꢇꢁꢈꢉ
ꢀꢁꢂꢃꢄꢅꢅꢆꢃꢃꢀꢁꢂꢃꢆꢇꢅꢅꢆ ꢀꢁꢂꢃꢄꢅꢄꢁꢆ
ꢀꢁꢂꢁꢃꢄ'.ꢃꢅꢆꢇꢈꢉꢉꢊꢃꢄ)''#$/&ꢊꢃꢋꢌ-ꢃꢍ')#ꢃꢈꢈꢎꢅꢆꢏꢇꢇꢇꢅꢃꢐꢑꢈꢒꢓꢃꢔꢅꢕꢏꢕꢆꢇꢇꢃꢃꢖꢗ.ꢃꢐꢑꢈꢒꢓꢃꢅꢅꢎꢏꢕꢉꢉꢈꢃꢖ')ꢃꢘꢌ+ꢗ"$ꢌꢘꢃ(ꢌ)ꢙ')%ꢗ&ꢚꢌꢃ*(ꢌꢚ*ꢃꢛꢃ*!'(("& ꢃ'&$"&ꢌꢃ*ꢌꢌꢃꢜ"&"ꢏꢝ")ꢚ,"+*ꢃ-ꢌꢞꢃ*"+ꢌ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇꢈꢃꢉꢈꢇꢆꢈꢂꢂꢊꢅꢃꢋꢂꢌꢊꢍꢁꢃꢉꢈꢇꢆꢈꢂꢃꢃꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢊꢋꢌꢉꢍꢈꢎꢏꢐꢏꢈꢑꢒꢇꢐꢏꢒꢐꢓꢔꢈꢕꢁꢂꢖꢈꢗꢑꢘꢑꢙꢊꢑꢚꢊꢌꢑꢋꢛ ꢉꢐꢜꢃ ꢎꢏꢆꢈꢆꢍꢆꢊꢍꢐꢆꢑꢅꢎꢍꢒꢏ
Page 8 of 12
ꢓꢔꢕꢖꢔꢃꢗꢖꢘꢓꢙꢚꢛꢜꢉꢃꢘꢙꢗꢝꢙꢞꢉꢞꢀꢋ
Digital Step Attenuator
Simplified Schematic
DAT-31R5-SP+
RF Input
RF Out
16dB
8dB
4dB
0.5dB
2dB
1dB
Digital Serial Control
The DAT-31R5-SP+ Serial interface consists of 6 control bits that select the desired attenuation state, as
shown in Table 1: Truth Table
Table 1. Truth Table
Attenuation
C16
C8
C4
C2
C1
C0.5
State
Reference
0.5 (dB)
1 (dB)
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
1
2 (dB)
4 (dB)
8 (dB)
16 (dB)
31.5 (dB)
Note: Not all 64 possible combinations of C0.5 - C16 are shown in table
The serial interface is a 6-bit serial in, parallel-out shift register buffered by a transparent latch.
It is controlled by three CMOS-compatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock
inputs allow data to be serially entered into the shift register, a process that is independent of the state of
the LE input.
The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift
register control the attenuator. When LE is brought LOW, data in the shift register is latched.
The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as
data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data.
The timing for this operation is defined by Figure 1 (Serial Interface Timing Diagram) and Table 2 (Serial
Interface AC Characteristics).
Table 2. Serial Interface AC Characteristics
Symbol
Parameter
Min.
Max.
Units
MHz
ns
Figure 1: Serial Interface Timing Diagram
Serial data clock
frequency (Note 1)
10
fclk
LE
Serial clock HIGH time
Serial clock LOW time
30
30
10
30
10
10
tclkH
ns
tclkL
Clock
LE set-up time after last
clock falling edge
ns
tLESUP
tLEPW
tSDSUP
tSDHLD
LE minimum pulse
width
Data
MSB
LSB
ns
Serial data set-up time
before clock rising edge
ns
tLEPW
tLESUP
tSDSUP
tSDHLD
Serial data hold time
after clock falling edge
ns
Note 1. fclk verified during the functional pattern test. Serial programming
sections of the functional pattern are clocked at 10MHz to verify fclk speci-
fication.
ꢂꢃꢄꢅ
ꢀ
ꢀꢁꢁ
ꢊꢋꢁꢂꢁꢆꢁꢅꢆꢇꢁꢈꢉꢌꢆꢍꢋ
ꢀꢁꢂꢁꢃꢄꢁꢅꢆꢇꢁꢈꢉ
ꢀꢁꢂꢃꢄꢅꢅꢆꢃꢃꢀꢁꢂꢃꢆꢇꢅꢅꢆ ꢀꢁꢂꢃꢄꢅꢄꢁꢆ
ꢀꢁꢂꢁꢃꢄ'.ꢃꢅꢆꢇꢈꢉꢉꢊꢃꢄ)''#$/&ꢊꢃꢋꢌ-ꢃꢍ')#ꢃꢈꢈꢎꢅꢆꢏꢇꢇꢇꢅꢃꢐꢑꢈꢒꢓꢃꢔꢅꢕꢏꢕꢆꢇꢇꢃꢃꢖꢗ.ꢃꢐꢑꢈꢒꢓꢃꢅꢅꢎꢏꢕꢉꢉꢈꢃꢖ')ꢃꢘꢌ+ꢗ"$ꢌꢘꢃ(ꢌ)ꢙ')%ꢗ&ꢚꢌꢃ*(ꢌꢚ*ꢃꢛꢃ*!'(("& ꢃ'&$"&ꢌꢃ*ꢌꢌꢃꢜ"&"ꢏꢝ")ꢚ,"+*ꢃ-ꢌꢞꢃ*"+ꢌ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇꢈꢃꢉꢈꢇꢆꢈꢂꢂꢊꢅꢃꢋꢂꢌꢊꢍꢁꢃꢉꢈꢇꢆꢈꢂꢃꢃꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢊꢋꢌꢉꢍꢈꢎꢏꢐꢏꢈꢑꢒꢇꢐꢏꢒꢐꢓꢔꢈꢕꢁꢂꢖꢈꢗꢑꢘꢑꢙꢊꢑꢚꢊꢌꢑꢋꢛ ꢉꢐꢜꢃ ꢎꢏꢆꢈꢆꢍꢆꢊꢍꢐꢆꢑꢅꢎꢍꢒꢏ
ꢓꢔꢕꢖꢔꢃꢗꢖꢘꢓꢙꢚꢛꢜꢉꢃꢘꢙꢗꢝꢙꢞꢉꢞꢀꢋ
Page 9 of 12
DAT-31R5-SP+
Digital Step Attenuator
The DAT-31R5-SP+, uses a common 6-bit serial word format, as shown in Table 3: 6-Bit attenuator Serial
Programming Register Map.
The first bit, the MSB, corresponds to the 16-dB Step and the last bit, the LSB, corresponds to the 0.5dB
step.
Table 3. 6-Bit attenuator Serial Programming Register Map
B5
B4
C8
B3
C4
B2
C2
B1
C1
B0
C16
C0.5
MSB
(first in)
LSB
(last in)
Power-up Control Settings
The DAT-31R5-SP+ always assumes a specifiable attenuation setting on power-up, allowing a known at-
tenuation state to be established before an initial serial control word is provided.
When the attenuator powers up, the six control bits are set to whatever data is present on the six data inputs
(C0.5 to C16).
This allows any one of the 64 attenuation settings to be specified as the power-up state.
ꢂꢃꢄꢅ
ꢀ
ꢀꢁꢁ
ꢊꢋꢁꢂꢁꢆꢁꢅꢆꢇꢁꢈꢉꢌꢆꢍꢋ
ꢀꢁꢂꢁꢃꢄꢁꢅꢆꢇꢁꢈꢉ
ꢀꢁꢂꢃꢄꢅꢅꢆꢃꢃꢀꢁꢂꢃꢆꢇꢅꢅꢆ ꢀꢁꢂꢃꢄꢅꢄꢁꢆ
ꢀꢁꢂꢁꢃꢄ'.ꢃꢅꢆꢇꢈꢉꢉꢊꢃꢄ)''#$/&ꢊꢃꢋꢌ-ꢃꢍ')#ꢃꢈꢈꢎꢅꢆꢏꢇꢇꢇꢅꢃꢐꢑꢈꢒꢓꢃꢔꢅꢕꢏꢕꢆꢇꢇꢃꢃꢖꢗ.ꢃꢐꢑꢈꢒꢓꢃꢅꢅꢎꢏꢕꢉꢉꢈꢃꢖ')ꢃꢘꢌ+ꢗ"$ꢌꢘꢃ(ꢌ)ꢙ')%ꢗ&ꢚꢌꢃ*(ꢌꢚ*ꢃꢛꢃ*!'(("& ꢃ'&$"&ꢌꢃ*ꢌꢌꢃꢜ"&"ꢏꢝ")ꢚ,"+*ꢃ-ꢌꢞꢃ*"+ꢌ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇꢈꢃꢉꢈꢇꢆꢈꢂꢂꢊꢅꢃꢋꢂꢌꢊꢍꢁꢃꢉꢈꢇꢆꢈꢂꢃꢃꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢊꢋꢌꢉꢍꢈꢎꢏꢐꢏꢈꢑꢒꢇꢐꢏꢒꢐꢓꢔꢈꢕꢁꢂꢖꢈꢗꢑꢘꢑꢙꢊꢑꢚꢊꢌꢑꢋꢛ ꢉꢐꢜꢃ ꢎꢏꢆꢈꢆꢍꢆꢊꢍꢐꢆꢑꢅꢎꢍꢒꢏ
Page 10 of 12
ꢓꢔꢕꢖꢔꢃꢗꢖꢘꢓꢙꢚꢛꢜꢉꢃꢘꢙꢗꢝꢙꢞꢉꢞꢀꢋ
Digital Step Attenuator
DAT-31R5-SP+
TB-334 Evaluation Board Schematic Diagram
R3
R4
16
R2
R5
R1
R6
20
19
18
17
15
RFin
RFout
1
C16
C8
2
3
4
5
14
13
RFin
RFout
VDD
Connected to +VDD
DAT
DATA
Clock
R7
C4
C1
R8
R11
12
11
GND
GND
C2
R9
6
7
8
9
10
LE
C3
R10
C5
C6
+
6
8
5
9
4
3
2
1
IC1
7
14
+Vcc
10
11
2
12
3
13
4
1
5
1
2
3
4
SERIAL
CONTROL
J1
DC SUPPLY
J2
Bill of Materials
Resistor 0603 10 KOhm +/- 1%
R1 - R11
C1 - C5
C6
NPO Capacitor 0603 100pF +/- 5%
Tantalum Capacitor 100nF +/- 10%
IC1
Hex inverting Schmitt trigger MM74HC14
TB-334
ꢂꢃꢄꢅ
ꢀꢁꢁ
ꢀ
ꢊꢋꢁꢂꢁꢆꢁꢅꢆꢇꢁꢈꢉꢌꢆꢍꢋ
ꢀꢁꢂꢁꢃꢄꢁꢅꢆꢇꢁꢈꢉ
ꢀꢁꢂꢃꢄꢅꢅꢆꢃꢃꢀꢁꢂꢃꢆꢇꢅꢅꢆ ꢀꢁꢂꢃꢄꢅꢄꢁꢆ
ꢀꢁꢂꢁꢃꢄ'.ꢃꢅꢆꢇꢈꢉꢉꢊꢃꢄ)''#$/&ꢊꢃꢋꢌ-ꢃꢍ')#ꢃꢈꢈꢎꢅꢆꢏꢇꢇꢇꢅꢃꢐꢑꢈꢒꢓꢃꢔꢅꢕꢏꢕꢆꢇꢇꢃꢃꢖꢗ.ꢃꢐꢑꢈꢒꢓꢃꢅꢅꢎꢏꢕꢉꢉꢈꢃꢖ')ꢃꢘꢌ+ꢗ"$ꢌꢘꢃ(ꢌ)ꢙ')%ꢗ&ꢚꢌꢃ*(ꢌꢚ*ꢃꢛꢃ*!'(("& ꢃ'&$"&ꢌꢃ*ꢌꢌꢃꢜ"&"ꢏꢝ")ꢚ,"+*ꢃ-ꢌꢞꢃ*"+ꢌ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇꢈꢃꢉꢈꢇꢆꢈꢂꢂꢊꢅꢃꢋꢂꢌꢊꢍꢁꢃꢉꢈꢇꢆꢈꢂꢃꢃꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢊꢋꢌꢉꢍꢈꢎꢏꢐꢏꢈꢑꢒꢇꢐꢏꢒꢐꢓꢔꢈꢕꢁꢂꢖꢈꢗꢑꢘꢑꢙꢊꢑꢚꢊꢌꢑꢋꢛ ꢉꢐꢜꢃ ꢎꢏꢆꢈꢆꢍꢆꢊꢍꢐꢆꢑꢅꢎꢍꢒꢏ
Page 11 of 12
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DAT-31R5-SP+
Digital Step Attenuator
Tape and Reel Packaging Information
Table T&R
TR
No.
No. of Devices Designation
Letter
Reel Size
Tape
Width
Pitch
Unit
Orientation
3000
T
13 inch
Tape
Cavity
T-005
12 mm 8 mm
multiples of 10,
less than full
reel of 3K
PR
E
13 inch
Direction of Feed
multiples of 10,
on tape only
not
applicable
Ordering Information
Packaging
Designation Letter
(See Table T&R)
Quantity
Min.
No. of Units
Price
$
Ea.
Model No.
Description
Serial Interface,
DAT-31R5-SP+
TB-334
E
10
1
$3.80
Single Positive Voltage
Test Board Only
Not Applicable
$79.95
How to Order
Example: 3000 pieces of DAT-31R5-SP+
3K
DAT-31R5-SP+
T&R=T
Quantity
Model No.
T&R designation letter (see Table T&R)
ꢂꢃꢄꢅ
ꢀ
ꢀꢁꢁ
ꢊꢋꢁꢂꢁꢆꢁꢅꢆꢇꢁꢈꢉꢌꢆꢍꢋ
ꢀꢁꢂꢁꢃꢄꢁꢅꢆꢇꢁꢈꢉ
ꢀꢁꢂꢃꢄꢅꢅꢆꢃꢃꢀꢁꢂꢃꢆꢇꢅꢅꢆ ꢀꢁꢂꢃꢄꢅꢄꢁꢆ
ꢀꢁꢂꢁꢃꢄ'.ꢃꢅꢆꢇꢈꢉꢉꢊꢃꢄ)''#$/&ꢊꢃꢋꢌ-ꢃꢍ')#ꢃꢈꢈꢎꢅꢆꢏꢇꢇꢇꢅꢃꢐꢑꢈꢒꢓꢃꢔꢅꢕꢏꢕꢆꢇꢇꢃꢃꢖꢗ.ꢃꢐꢑꢈꢒꢓꢃꢅꢅꢎꢏꢕꢉꢉꢈꢃꢖ')ꢃꢘꢌ+ꢗ"$ꢌꢘꢃ(ꢌ)ꢙ')%ꢗ&ꢚꢌꢃ*(ꢌꢚ*ꢃꢛꢃ*!'(("& ꢃ'&$"&ꢌꢃ*ꢌꢌꢃꢜ"&"ꢏꢝ")ꢚ,"+*ꢃ-ꢌꢞꢃ*"+ꢌ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇꢈꢃꢉꢈꢇꢆꢈꢂꢂꢊꢅꢃꢋꢂꢌꢊꢍꢁꢃꢉꢈꢇꢆꢈꢂꢃꢃꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢊꢋꢌꢉꢍꢈꢎꢏꢐꢏꢈꢑꢒꢇꢐꢏꢒꢐꢓꢔꢈꢕꢁꢂꢖꢈꢗꢑꢘꢑꢙꢊꢑꢚꢊꢌꢑꢋꢛ ꢉꢐꢜꢃ ꢎꢏꢆꢈꢆꢍꢆꢊꢍꢐꢆꢑꢅꢎꢍꢒꢏ
Page 12 of 12
ꢓꢔꢕꢖꢔꢃꢗꢖꢘꢓꢙꢚꢛꢜꢉꢃꢘꢙꢗꢝꢙꢞꢉꢞꢀꢋ
相关型号：
3KDAT-31R5-SPT+
Variable Attenuator, 0MHz Min, 2400MHz Max, 2.4dB Insertion Loss-Max, 4 X 4 MM, ROHS COMPLIANT, DG983-1, 20 PIN
MINI
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