M512S32GAMB-25 [MICROSS]
SRAM,;型号: | M512S32GAMB-25 |
厂家: | MICROSS COMPONENTS |
描述: | SRAM, 静态存储器 |
文件: | 总11页 (文件大小:322K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M512S32
512K x 32 Fast SRAM
December 2007
Issue 3.1
General Description
Features
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ꢀ
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16MBit Fast SRAM Module.
Fast Access times of 20/25/35ns.
Configurable as 8 / 16 / 32 bit wide output.
Operating Power 1980 / 2640 / 3960 mW
(max). Standby TTL 1320mW (max).
Single 5V 10% Power supply.
TTL compatible inputs and outputs.
May be screened in accordance with MIL-
STD-883.
The M512S32 is a hi-rel grade16Mbit fast Static RAM
multichip module, that is normally organised as
512Kx32 bits wide , but can also be user configured
as 1Mx16 or 2Mx8. Access times are available as 20,
25 and 35ns, with 15 and 17ns in development. The
part is housed in a ceramic high reliability surface
mount CQFP with an industry standard footprint that
matches the Standard Militarised Drawing for such
devices. The part operates from a single 5V supply.
Screening levels from Commercial to Space grade
can be applied.
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68 pin ceramic Gullwing, CQFP
A0 – A18
/OE
A0 – A18
/OE
/CS1
/CS1
/CS2
/CS3
/CS4
/WE
/CS2
/CS3
/CS4
/WE1
/WE2
/WE3
/WE4
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
D0 – D7
D0 – D7
D8 – D15
D16 – D23
D24 – D31
D8 – D15
D16 – D23
D24 – D31
(G Pin out)
Block Diagram (GA Pin out)
Pin Functions
A0~A18
/CS1~4
/WE1~4
VCC
Address Inputs
Chip Select
Write Enable
Power (+5V)
D0_D31
/OE
NC
Data Inputs/Outputs
Output Enable
No Connect
GND
Ground
Page 1 of 11
TS2 Micro Limited. Registered Office: 2 Oriel Court, Omega Park, Alton, Hampshire GU34 2YT
Phone: +44 (0) 1420 594180 Fax: +44 (0) 1420 89151 Email: sales@ts2micro.co.uk Web: http://www.ts2micro.com uk
M512S32
512K x 32 Fast SRAM
December 2007
Issue 3.1
Pin Definition
CQFP “G” Package Option
Pin Signal Pin Signal
1
2
3
4
5
6
7
8
9
GND 35 /OE
/CS3 36 /CS2
A5
A4
A3
A2
A1
A0
NC
37 A17
38 NC
39 NC
40 NC
41 A18
42 NC
43 NC
44 D31
45 D30
46 D29
47 D28
48 D27
49 D26
50 D25
51 D24
10 D0
11 D1
12 D2
13 D3
14 D4
15 D5
16 D6
17 D7
18 GND 52 GND
19 D8
20 D9
53 D23
54 D22
21 D10 55 D21
22 D11 56 D20
23 D12 57 D19
24 D13 58 D18
25 D14 59 D17
26 D15 60 D16
27 VCC 61 VCC
28 A11 62 A10
29 A12 63 A9
30 A13 64 A8
31 A14 65 A7
32 A15 66 A6
33 A16 67 /WE1
34 /CS1 68 /CS4
Pinout Alternative - same as "G" option except:
GA - pin38=/WE2, pin39=/WE3, pin40=/WE4
Page 2 of 11
TS2 Micro Limited. Registered Office: 2 Oriel Court, Omega Park, Alton, Hampshire GU34 2YT
Phone: +44 (0) 1420 594180 Fax: +44 (0) 1420 89151 Email: sales@ts2micro.co.uk Web: http://www.ts2micro.com uk
M512S32
512K x 32 Fast SRAM
December 2007
Issue 3.1
Electrical Characteristics
DC Operating Conditions
Absolute Maximum Ratings (1)
Parameter
Symbol
VT
Unit
V
(2)
Voltage on any pin relative to VSS
-0.5V to +730 V
4
Power Dissipation
PD
W
Storage temperature
TSTG
-55 to +150
°C
Notes (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Min
4.5
2.2
-0.5
0
Type
Max
5.5
Unit
Supply Voltage
VCC
VIH
VIL
TA
5.0
V
Input High Voltage
Input Low Voltage
Operating Temp Range
Operating Temp Range
Operating Temp Range
-
-
-
-
-
VCC+0.5
0.8
V
V
70
°C
°C (I Suffix)
°C (M, MB Suffix)
TAI
TAM
-40
-55
85
125
Parameter
Symbol Test Condition
Min Typ(1) Max Unit
Input Leakage Current Address, ILI1
/OE
VIN=0V to VCC
-8
-
8
µA
Input Leakage Current Address, IL12
/WE, /CS
VIN=0V to VCC
-2
-
2
µA
Output Leakage Current
ILo
/CS(2) =VIH or /OE = VIH’ VI/O =0V to VCC /WE(2)=VIL
-8
-
-
-
8
µA
Average Supply Current 32 bit ICC32
/CS(2)=VIL’ Minimum cycle, II/O=0mA /WE(2)=VIL or
/WE(2)+/OE=VIH’ 100% duty
720
mA
Average Supply Current 16 bit ICC16
/CS(2)=VIL’ Minimum cycle, II/O=0mA /WE(2)=VIL or
/WE(2)+/OE=VIH’ 100% duty
-
-
-
-
-
-
480
360
240
mA
mA
mA
Average Supply Current 8 bit
ICC8
/CS(2)=VIL’ Minimum cycle, II/O=0mA /WE(2)=VIL or
/WE(2)+/OE=VIH’ 100% duty
Standby Supply Current TTL
levels
ISB
/CS(2)=VIH,VCC=5.5V
Output Voltage Low
Output voltage High
VOL
VOH
IOL=8.0 mA
IOH=-4.0 mA
-
-
-
0.4
-
V
V
2.4
Notes (1) Typical values are at VCC=5.0V,TA=25°C and specified loading.
(2) /CS and /WE above are accessed through /CS1~4 and /WE1~4 respectively. These inputs must be operated simultaneously
for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
Page 3 of 11
TS2 Micro Limited. Registered Office: 2 Oriel Court, Omega Park, Alton, Hampshire GU34 2YT
Phone: +44 (0) 1420 594180 Fax: +44 (0) 1420 89151 Email: sales@ts2micro.co.uk Web: http://www.ts2micro.com uk
M512S32
512K x 32 Fast SRAM
December 2007
Issue 3.1
Capacitance (VCC=5V 10%, TA=25°C)
Note: These parameters are calculated, not measured.
Parameter
Symbol
Test Condition
VIN=0V
Typ Max
Unit
pF
Input Capacitance address, /OE
Input Capacitance address /WE1~4, /CS1~4
I/O Capacitance D0~31
CIN1
CIN2
CI/O
-
-
-
34
6
VIN=0V
VI/O=0V
pF
42 PF (8 bit mode)
Operating Modes
The table below shows the logic inputs required to control the operating modes of each of the SRAMs on the
device.
Mode
/CS
1
/OE
X
/WE
X
VCC Current
ISB1’ SB2
I/O PIN Reference Cycle
Not Selected
Output Disable
Read
I
High Z
High z
DOUT
DIN
Power Down
0
1
1
ICC
ICC
ICC
0
0
1
Read Cycle
Write Cycle
Write
0
X
0
1 = VIH,
0 = VIL,
X = Don't Care
Note: /CS above is accessed through /CS1~4 and /WE is accessed through /WE1~4. For correct operation, /CS1~ 4 and
/WE1~4 must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or singly for 8 bit operation.
AC Test Conditions
Output Load
•
•
•
Input pulse levels: 0.0V to 3.0V
167 Ohm
30pf
I/O Pin
1.76V
Input rise and fall times: 3 ns
Input and Output timing reference levels:
1.5V
•
•
VCC=5V 10%
module is tested in 32bit mode.
Page 4 of 11
TS2 Micro Limited. Registered Office: 2 Oriel Court, Omega Park, Alton, Hampshire GU34 2YT
Phone: +44 (0) 1420 594180 Fax: +44 (0) 1420 89151 Email: sales@ts2micro.co.uk Web: http://www.ts2micro.com uk
M512S32
512K x 32 Fast SRAM
December 2007
Issue 3.1
AC Operating Conditions
Read Cycle
20
25
35
Parameter
Symbol
tRC
Min
20
-
Max
-
Min
25
-
Max
-
Min
35
-
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
-
35
35
15
-
Address Access Time
tAA
20
20
10
-
25
25
15
-
Chip Select Access Time
TACS
tOE
-
-
-
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output In Low Z
Output Enable to Output In Low Z
Chip Deselection to Output In High Z(3)
Output Disable to Output In High Z(3)
-
-
-
tOH
5
5
5
tCLZ
tOLZ
tCHZ
tOHZ
5
-
0
10
-
0
10
-
5
-
10
0
10
0
-
10
10
-
-
0
5
-
5
-
Write Cycle
20
25
35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
TWC
TCW
tAW
tAS
20
15
15
0
-
-
25
15
15
0
-
-
35
15
15
0
-
-
Chip Selection to End of Write
Address Valid to End of Write
Address Set-up Time
-
-
-
-
-
-
Write Pulse Width
tWP
tWR
tWHZ
tDW
tDH
15
0
-
15
0
-
15
0
-
Write Recovery Time
-
-
-
Write top Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
10
-
0
10
-
0
10
-
10
0
10
0
10
0
-
-
-
tOW
5
-
5
-
5
-
Page 5 of 11
TS2 Micro Limited. Registered Office: 2 Oriel Court, Omega Park, Alton, Hampshire GU34 2YT
Phone: +44 (0) 1420 594180 Fax: +44 (0) 1420 89151 Email: sales@ts2micro.co.uk Web: http://www.ts2micro.com uk
M512S32
512K x 32 Fast SRAM
December 2007
Issue 3.1
Read Cycle Timing Waveform (1,2)
Address Valid
ADDR
tRC
/CS
/OE
t
CHZ
t
ACS
tOE
tOHZ
tOH
tAA
High Z
Data Valid
DATA
tOLZ
tCLZ
Notes:
(1) During the Read Cycle, /WE is high for the module.
(2) Address valid prior to or coincident with /CS transition Low.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
tWC
/OE
tWR
tAS
ADDR
/CS
t
AW
t
CW
tWP
/WE
t
OW
tOHZ
High Z
Data Out
tDW
t
OH
High Z
Data In
Page 6 of 11
TS2 Micro Limited. Registered Office: 2 Oriel Court, Omega Park, Alton, Hampshire GU34 2YT
Phone: +44 (0) 1420 594180 Fax: +44 (0) 1420 89151 Email: sales@ts2micro.co.uk Web: http://www.ts2micro.com uk
M512S32
512K x 32 Fast SRAM
December 2007
Issue 3.1
Write Cycle No.2 Timing Waveform (5)
tWC
ADDR
/CS
tCW
tWR
tAW
tWP
t
OH
/WE
t
AS
tWHZ
tOW
High Z
Data Out
Data In
t
DH
tDW
High Z
AC Characteristics Notes
(1) A write occurs during the overlap (tWP) of a low /CS and a low /WE.
(2) tWR is measured from the earlier of /CS or /WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the /CS low transition occurs simultaneously with the /WE low transition or after the /WE low transition, outputs
remain
in a high impedance state.
(5) /OE is continuously low. (/OE=VIL)
(6) DOUT is in the same phase as written data of this write cycle.
(7) DOUT is the read data of next address.
(8) If /CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) tWHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Page 7 of 11
TS2 Micro Limited. Registered Office: 2 Oriel Court, Omega Park, Alton, Hampshire GU34 2YT
Phone: +44 (0) 1420 594180 Fax: +44 (0) 1420 89151 Email: sales@ts2micro.co.uk Web: http://www.ts2micro.com uk
M512S32
512K x 32 Fast SRAM
December 2007
Issue 3.1
A
B
C
Pin 1
G
H
D
E
F
Pin 18
J
K
L
Package
Page 8 of 11
TS2 Micro Limited. Registered Office: 2 Oriel Court, Omega Park, Alton, Hampshire GU34 2YT
Phone: +44 (0) 1420 594180 Fax: +44 (0) 1420 89151 Email: sales@ts2micro.co.uk Web: http://www.ts2micro.com uk
M512S32
512K x 32 Fast SRAM
December 2007
Issue 3.1
Milimeters
Min Max
Inches
Symbol
Min
Max
A / D
B / E
C / F
G
24.89 25.40 0.980 1.000
22.10 22.61 0.870 0.890
20.32 BSC
0.43
1.27 BSC
0.800 BSC
0.013 0.017
0.05 BSC
0.33
H
J
2.30
3.12
4.72
5.08
0.118 0.186
0.123 0.200
K
L
23.77 24.28 0.936 0.956
G & GA
Page 9 of 11
TS2 Micro Limited. Registered Office: 2 Oriel Court, Omega Park, Alton, Hampshire GU34 2YT
Phone: +44 (0) 1420 594180 Fax: +44 (0) 1420 89151 Email: sales@ts2micro.co.uk Web: http://www.ts2micro.com uk
M512S32
512K x 32 Fast SRAM
December 2007
Issue 3.1
Screening
Military Screening Procedure
MultiChip Screening Flow for high reliability product in accordance with Mil-883 method 5004 shown below
Item
MIL-STD Test Condition
2010 Condition B
1010 Condition C (10 cycle)
Level
100%
100%
100%
100%
100%
100%
Internal Visual
Temperature cycle
Constant acceleration
Pre Burn in electrical
Burn in
2001 Condition E, Y only (10,000g)
As per device specification (25C)
1015 Condition D, Ta=125C, 160hrs
As per device specification
Final electrical test
Static, functional, switching
1. @Ta = 25C and power supply extremes
2. @ temperature and power supply extremes
Percent Defective Allowable (PDA) Calculated at post burn in at Ta=25C
5%
Hermeticity - Fine
Hermeticity - Gross
External visual
1014 condition A
1014 condition C
2009 per vendor or customer specification
100%
100%
100%
Page 10 of 11
TS2 Micro Limited. Registered Office: 2 Oriel Court, Omega Park, Alton, Hampshire GU34 2YT
Phone: +44 (0) 1420 594180 Fax: +44 (0) 1420 89151 Email: sales@ts2micro.co.uk Web: http://www.ts2micro.com uk
M512S32
512K x 32 Fast SRAM
December 2007
Issue 3.1
Ordering Information
Part Number
Package
Pinout
Access Times ns Screening Level Comment
68 ceramic
CQFP
single write
enable
M512S32G-xxx
M512S32GI-xxx
M512S32GM-xxx
M512S32GMB-xxx
15/17/20/25/35 Commercial
15/17/20/25/35 Industrial
15/17/20/25/35 Mil Temp
15/17/20/25/35 MIL-STD-883
68 ceramic
CQFP
single write
enable
68 ceramic
CQFP
single write
enable
68 ceramic
CQFP
single write
enable
68 ceramic
CQFP
M512S32GA-xxx
M512S32GAI-xxx
M512S32GAM-xxx
4 x write enable 15/17/20/25/35 Commercial
4 x write enable 15/17/20/25/35 Industrial
4 x write enable 15/17/20/25/35 Mil Temp
4 x write enable 15/17/20/25/35 MIL-STD-883
68 ceramic
CQFP
68 ceramic
CQFP
68 ceramic
M512S32GAMB-xxx CQFP
Page 11 of 11
TS2 Micro Limited. Registered Office: 2 Oriel Court, Omega Park, Alton, Hampshire GU34 2YT
Phone: +44 (0) 1420 594180 Fax: +44 (0) 1420 89151 Email: sales@ts2micro.co.uk Web: http://www.ts2micro.com uk
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