5962-9561301HYC [MICROSS]
Standard SRAM, 512KX8, 120ns, CMOS, CDIP32, CERAMIC, DIP-32;
| 型号： | 5962-9561301HYC |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Standard SRAM, 512KX8, 120ns, CMOS, CDIP32, CERAMIC, DIP-32 CD 静态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
512K x 8 SRAM
PIN ASSIGNMENT
Ultra Low Power SRAM
(TopView)
AVAILABLE AS MILITARY
SPECIFICATION
• SMD 5962-956131,2
• MIL STD-8831
32-Pin DIP, 32-Pin SOJ
& 32-Pin TSOP
A18
A16
A14
A12
A7
1
2
32
Vcc
FEATURES
• Ultra Low Power with 2V Data Retention
(0.2mW MAX worst case Power-down standby)
• Fully Static, No Clocks
31 A15
30 A17
29 WE\
28 A13
3
4
• Single +5V ±10% power supply
• Easy memory expansion with CE\ and OE\ options
• All inputs and outputs are TTL-compatible
• Three state outputs
5
A6
6
27
26
A8
A9
A5
7
A4
8
25 A11
24
• Operating temperature range:
Ceramic -55oC to +125oC & -40oC to +85oC
A3
9
OE\
Plastic
-40oC to +85oC3
A2
10
11
12
13
14
15
16
23 A10
1. Not applicable to plastic package
2. Applies to CW package only.
A1
22
CE\
3. Contact factory for -55oC to +125oC
A0
21 I/08
20 I/07
19 I/06
18 I/05
17 I/04
OPTIONS
• Timing
MARKING
I/01
I/02
I/03
Vss
55ns access
70ns access
85ns access
-554
-70
-85
100ns access
• Packages
Ceramic Dip (600 mil)
Ceramic SOJ5
Plastic TSOP
-100
CW
ECJ
DG
No. 112
No. 502
No. 1002
4. For DG package, contact factory
5. Contact Factory
Pin Name
WE\
Function
NOTE: Not all combinations of operating temperature, speed, data retention and low power are
necessarily available. Please contact the factory for availability of specific part number
Write Enable Input
Chip Select Input
Output Enable Input
combinations.
CE\
OE\
GENERAL DESCRIPTION
The AS5C4009LL is organized as 524,288 x 8 SRAM utilizing a
special ultra low power design process. ASI’s pinout adheres to the
JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32
pin version allows for easy upgrades from the 1 meg SRAM design.
For flexibility in memory applications, ASI offers chip enable (CE\)
and output enable (OE\) capabilities. These features can place the
outputs in High-Z for additional flexibility in system design.
This devices operates from a single +5V power supply and all
inputs and outputs are fully TTL-compatible.
A0 - A18 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
Vcc
Vss
Power
Ground
For more products and information
please visit our web site at
www.austinsemiconductor.com
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW. The device offers a re-
duced power standby mode when disabled, by lowering VCC to 2V and
maintaining CE\ = 2V. This allows system designers to meet ultra low
standby power requirements.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
1
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
Clk. gen.
Precharge circuit
A18
A16
A14
A12
Memory Array
1024 rows
Row
512 x 8 columns
select
A7
A6
A5
A4
A1
A0
I/O
I/O
1
I/O Circuit
Data
cont
Column Select
8
Data
cont
A9 A8 A13 A17 A15 A10 A11 A3
A2
CE\
Control
logic
WE\
OE\
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
2
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
ABSOLUTEMAXIMUMRATINGS*
*Stresses greater than those listed under "Absolute Maximum
Voltage on Vcc Supply Relative to Vss...................-.5V to +7.0V Ratings" may cause permanent damage to the device. This is
Voltage on any pin Relative to Vss..........................-.5V to +7.0V a stress rating only and functional operation of the device at
Storage Temperature ....................................-65°C to +150°C these or any other conditions above those indicated in the
Operating Temperature Range.............................-55oC to +125oC operation section of this specification is not implied. Exposure
Soldering Temperature Range...............................................260oC to absolute maximum rating conditions for extended periods
Maximum Junction Temperature**....................................+150°C may affect reliability.
Power Dissipation...................................................................1.0W ** Junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TA < 125oC;Vcc = 5V +10%)
SYMBOL
NOTES
PARAMETER/CONDITION
MIN
MAX
UNITS
ILI
Input Leakage Current (VIN = VSS to VCC)
-5
5
µΑ
Output Leakage Current
(CE\=VIH or OE\=VIH or WE\=VIL, VIO=VSS to VCC)
ILO
-5
5
µΑ
VOL
VOH
Output Low Voltage (IOL = 2.1mA)
Output High Voltage (IOH = -1.0 mA)
--
0.4
--
V
V
15
15
2.4
VCC
VIH
VIL
Supply Voltage
4.5
2.2
5.5
Vcc +0.5
0.8
V
V
V
15
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
1, 15
2, 15
-0.5
MAX
PARAMETER
CONDITIONS
Cycle Time = Min., 100%
SYM
-55
-70
-85
-100 UNITS NOTES
Power Supply Current:
Operating
Duty Cycle, IIO = 0mA,
CE\ = VIL, VIN = VIH or VIL
100
6
90
80
6
70
6
mA
mA
mA
3
I
cc1
CE\ = VIH,
Other inputs = VIL or VIH
TTL
6
ISB
Power Supply Current:
Standby
CE\ = Vcc -0.2V,
Other inputs = 0 ~ Vcc
CMOS
ISB1
0.75
0.75
0.75
0.75
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
3
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
CAPACITANCE
PARAMETER
CONDITIONS
SYMBOL MAXIMUM
UNITS
NOTES
VIN=0V
VIO=0V
CIN
CIO
TA = 25oC, f = 1MHz
Input Capacitance
8
pF
4
VCC = 5V
Input/Output Capactiance
10
pF
4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55oC < TA < 125oC;Vcc = 5V +10%)
-55
-70
-85
-100
DESCRIPTION
READ Cycle
SYM
MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
t RC
t AA
t ACE
t OH
READ cycle Time
55
70
85
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
55
55
70
70
85
85
100
100
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
Output Enable access time
Output Enable to output in Low-Z
10
10
10
10
10
10
10
10
t LZCE
t HZCE
t PU
4,6
4,6
4
20
25
30
30
0
5
0
5
0
5
0
5
t PD
55
30
70
35
85
40
100
45
4
t AOE
t LZOE
t HZOE
4,6
4,6
Output disable to output in High-Z
20
25
30
30
WRITE Cycle
t WC
t CW
t AW
WRITE cycle time
55
50
50
0
70
60
60
0
85
70
70
0
100
80
80
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to end of write
Address valid to end of write
Address setup time
t AS
t AH
Address hold from end of write
WRITE pulse width
0
0
0
0
t WP1
t DS
50
30
0
60
30
0
70
35
0
80
40
0
Data setup time
t DH
Data hold time
t LZWE
t HZWE
Write disable to output in Low-Z
Write Enable to output in High-Z
5
5
5
5
4,6
4,6
25
25
30
30
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
4
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
ACTESTCONDITIONS
50 ohms
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 3ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load ......................................... See Figures 1
Q
1.73V
C = 100pF
Fig. 1 Output Load Equivalent
NOTES
1. Overshoot: Vcc +3.0V for pulse width < 20ms.
2. Undershoot: -3V for pulse width < 20ms.
3. ICC is dependent on output loading and cycle rates.
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
occurring chip enable.
10. RC = Read Cycle Time.
11. Chip enable and write enable can initiate and
terminate a WRITE cycle.
12. Output enable (OE\) is inactive (HIGH).
13. Output enable (OE\) is active (LOW).
14. ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
t
6. At any given temperature and voltage condition,
t
HZCE is less than tLZCE, and tHZWE is less than
tLZWE
.
7. WE\ is HIGH for READ cycle.
15. All voltage referenced to Vss (GND).
8. Device is continuously selected. Chip enables and
output enables are held in their active state.
9. Address valid prior to, or coincident with, latest
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
VCC for Retention Data
VDR
2
V
CE\ > (VCC - 0.2V)
VIN > (VCC - 0.2V)
VCC = 2V
VCC = 3V
ICCDR
ICCDR
100
200
µA
µA
Data Retention Current
Chip Deselect to Data
Retention Time
tCDR
tR
0
5
ns
4
ms
4, 10
Operation Recovery Time
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
5
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
LOW VCC DATA RETENTION WAVEFORM
CE\ Controlled
tRDR
tSDR
Data Retention
VCC
4.5V
2.2V
VDR
CE\ > Vcc - 0.2V
CE\
GND
READ CYCLE NO. 1 1
(Address Controlled, CE\ = OE\ = VIL, WE\ = VIH)
tRC
ADDRESS
tAA
tOH
Previous Data Valid
DATA OUT
Data Valid
READ CYCLE NO. 2 2
(WE\ = VIH)
tRC
ADDRESS
tAA
tOH
tCO1
CE\
OE\
tHZ
tOE
tOHZ
tOLZ
tLZ
High-Z
Data Valid
DATA OUT
Don’t Care
Undefined
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
6
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
WRITE CYCLE NO. 1
(WE Controlled)
tWC
ADDRESS
tCW(4)
tWR(6)
CE\
tAW
tWP(3)
WE\
tAS(5)
tDH
tDW
Data Valid
DATA IN
tWHZ
tOW
DATA OUT
Data Undefined
WRITE CYCLE NO. 2
(Write Enabled Controlled)
tWC
ADDRESS
CE\
tAS(5)
tCW(4)
tWR(6)
tAW
tWP(3)
WE\
tDH
tDW
Data Valid
DATA IN
High-Z
High-Z
DATA OUT
NOTES:
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature adn voltage condition, tHZ (MAX) is less than tLZ (MIN) both for a given device and from device to
device interconnection.
3. A write occurs during the overlap of a low CE\ adn a low WE\. A write begins at the latest transistion among CE\ going Low and
WE\ going Low: A write end at the earliest transistion among CE\ going High and WE\ going High, tWP is measured from the
beginning of write to the end of write.
4. tCW is measured from the CE\ going Low to end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measure from the end of write to the address change. tWR applied in case a write ends are CE\ or WE\ going High.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
7
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
MECHANICAL DEFINITION*
ASI Case #112 (Package Designator CW)
D
A
L
L1
b
e
Pin 1
b1
E
b2
E1
ASI PACKAGE
SYMBOL
MIN
MAX
0.111
0.020
0.055
0.012
1.615
0.605
0.610
0.110
0.060
0.175
A
b
b1
b2
D
E
E1
e
0.089
0.016
0.045
0.008
1.585
0.585
0.590
0.090
0.040
0.125
L
L1
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
8
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
MECHANICAL DEFINITION*
ASI Case #502 (Package Designator ECJ)
A
b1
b2
e
D
L
D1
E1
b
A1
E
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
9
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
MECHANICAL DEFINITION*
ASI Case #1002 (Package Designator DG)
0 - 8°
0.463±0.008
0.400TYP
0.018 ~ 0.030
0.006+0.004/-0.002
0.841 MAX
0.825 ± 0.004
0.039 ± 0.004
0.047 MAX
0.004 MAX
0.002 MIN
0.016 ± 0.004
0.050TYP
0.037TYP
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
10
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS5C4009LLCW-55/883C **
Package Speed
EXAMPLE: AS5C4009LLECJ-55/883C **
Package
Type
Speed
ns
Device Number
AS5C4009LL
AS5C4009LL
AS5C4009LL
AS5C4009LL
Process
Device Number
AS5C4009LL
AS5C4009LL
AS5C4009LL
AS5C4009LL
Process
Type
ns
CW
-55
/*
/*
/*
/*
ECJ
ECJ
ECJ
ECJ
-55
-70
/*
/*
/*
/*
CW
CW
CW
-70
-85
-85
-100
-100
EXAMPLE: AS5C4009LLDG-55/IT ***
Package
Type
Speed
ns
Device Number
AS5C4009LL
AS5C4009LL
AS5C4009LL
AS5C4009LL
Process
DG
DG
DG
DG
-55
/*
/*
/*
/*
-70
-85
-100
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
**NOTE: All CSOJ devices, please consult factory. Not all combinations of
operating temperature, speed, data retention and low power are necessarily
available. Please contact the factory for availability of specific part number
combinations.
***NOTE: Plastic devices not available as 883. For XT or 55ns devices,
contact factory.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
11
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
ASI TO DSCC PART NUMBER
CROSS REFERENCE
FOR 5962-95613
Package Designator CW
ASI Part #
SMD Part
AS5C4009CW-120/H
5962-9561301HYA
AS5C4009CW-120L/H 5962-9561315HYA
AS5C4009CW-100/H 5962-9561302HYA
AS5C4009CW-100L/H 5962-9561316HYA
AS5C4009CW-85/H
AS5C4009CW-85L/H
AS5C4009CW-70/H
AS5C4009CW-70L/H
5962-9561303HYA
5962-9561317HYA
5962-9561304HYA
5962-9561318HYA
AS5C4009CW-120/H
5962-9561301HYC
AS5C4009CW-120L/H 5962-9561315HYC
AS5C4009CW-100/H 5962-9561302HYC
AS5C4009CW-100L/H 5962-9561316HYC
AS5C4009CW-85/H
AS5C4009CW-85L/H
AS5C4009CW-70/H
AS5C4009CW-70L/H
5962-9561303HYC
5962-9561317HYC
5962-9561304HYC
5962-9561318HYC
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
12
相关型号：
©2020 ICPDF网 联系我们和版权申明