ZLS30383 [MICROSEMI]
IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizers;型号: | ZLS30383 |
厂家: | Microsemi |
描述: | IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizers |
文件: | 总8页 (文件大小:375K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ZL30791, ZL30795, ZL30793
IEEE 1588 & Synchronous Ethernet
Packet Clock Network Synchronizers
Product Brief
August 2019
Features
Ordering Information
• One, Two or Three DPLL Channels
ZL30791LFG7 1-Channel 80-lead LGA Trays
ZL30795LFG7 2-Channel 80-lead LGA Trays
ZL30793LFG7 3-Channel 80-lead LGA Trays
• Packet and/or physical-layer frequency, phase
and time synchronization
• Physical-layer compliance with ITU-T G.8262,
G.8262.1, G.813, G.812, Telcordia GR-1244,
GR-253
NiAu (Pb-free)
Package size: 11 x 11 mm
-40 C to +85 C
• Packet-timing compliance with ITU-T G.8261,
G.8263, G.8273.2 (class A,B,C&D), G.8273.4
• Per-output programmable duty cycle
• Enables 5G wireless applications with sub-
• Precise output alignment circuitry and per-
100ns time/phase alignment requirements
output phase adjustment
• Programmable bandwidth, 0.1mHz to 470Hz
• Hitless reference switching and mode switching
• High-resolution holdover averaging
• Per-output enable/disable and glitchless
start/stop (stop high or low)
• Local Oscillator
• Programmable phase slope limit for transients,
• Operates from a single TCXO or OCXO: 23.75-
downto 1 ns/s
25MHz, 47.5-50MHz, 114.285-125MHz
• Per-DPLL phase adjustment, 1ps resolution
• Very-low-jitter applications can connect a TCXO
or OCXO as the stability reference and a low-
jitter XO as the jitter reference
• Input Clocks
• Accepts up to 10 differential or CMOS inputs
• Any input frequency from 0.5Hz to 900MHz
• Per-input activity and frequency monitoring
• Automatic or manual reference switching
• Fast lock to 1 PPS input, <30 seconds
• General Features
• Automatic self-configuration at power-up from
internal Flash memory
• Input-to-output alignment <2ns
• Internal compensation (1ppt) for local oscillator
• Any input can be a 1PPS SYNC input for
frequency error in DPLLs and input monitors
REF+SYNC frequency/phase/time locking
• Numerically controlled oscillator behavior in
• Any input can be a clock with embedded 1PPS
• Per-input phase adjustment, 1ps resolution
each DPLL and each fractional output divider
• Programmable Time of Day counters
• Output Clock Frequency Generation
• Easy-to-configure design requires no external
VCXO or loop filter components
• Any output frequency from <0.5Hz to 1045MHz
(180MHz max for Synth0)
• 7 GPIO pins with many possible behaviors
• SPI or I2C processor Interface
• High-resolution fractional frequency conversion
with 0ppm error
• 1.8V and 3.3V core VDD voltages
• Synthesizers 1 & 2 have integer and fractional
• Power: 1.3W for 2 inputs, 1 synth, 6 LVDS out
• Easy-to-use evaluation/programming software
• Factory programmable power-up configuration
dividers to make a total of 5 frequency families
• Output jitter from Synths 1 & 2 is <0.3ps RMS
• Output jitter from fractional dividers is typically
< 1ps RMS, many frequencies <0.5ps RMS
Applications
• Each HPOUTP/N pair can be LVDS, LVPECL,
•
Central system timing ICs for SyncE and/or
IEEE 1588, SONET/SDH, OTN, wireless base
station and other carrier-grade systems
HCSL, 2xCMOS, HSTL or programable diff.
• Four output banks each with VDDO pin; CMOS
output voltages from 1.5V to 3.3V
•
G.8262/813 EEC/SEC, Telcordia Stratum 2-4
• Per-synthesizer phase adjust, 1ps resolution
1
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Copyright 2019. Microsemi Corporation. All Rights Reserved.
ZL30791, ZL30795, ZL30793
Product Brief
1. Block Diagram
Register Access
PACKET_REF[2:0]
DIV
DIV
GPOUT0
GPOUT1
GP Synthesizer 0
general purpose
DPLL0
REF0P
REF0N
One Diff / Two
Single-Ended
REF1P
REF1N
HPOUT0P
HPOUT0N
One Diff / Two
Single-Ended
IntDiv
DIV
DIV
DIV
DIV
DIV
DIV
DIV
DIV
HP Synthesizer 1
low-jitter
DPLL1
DPLL2
HPOUT1P
HPOUT1N
REF2P
REF2N
One Diff / Two
Single-Ended
FracDiv
IntDiv
HPOUT2P
HPOUT2N
REF3P
REF3N
One Diff / Two
Single-Ended
HP Synthesizer 2
low-jitter
HPOUT3P
HPOUT3N
REF4P
REF4N
One Diff / Two
Single-Ended
FracDiv
HPOUT4P
HPOUT4N
HPOUT5P
HPOUT5N
Reference Monitors
& State Machines
HPOUT6P
HPOUT6N
Microprocessor Port
SPI or I2C I/F & GPIO Pins
Master
Clock
XO
Optional x2
HPOUT7P
HPOUT7N
DPLL1 only present on ZL30795 and ZL30793
DPLL2 only present on ZL30793
Figure 1 - Functional Block Diagram
2. Application Example
1.544 or 2.048MHz
TCXO
CMOS to BITS/SSU
to BITS/SSU system
DPLL0
Synth0
T4 path
1 PPS or clock w/ embedded PPS
BITS/SSU
2x 156.25MHz
2x 125MHz
GPS (1PPS)
SyncE signals to
system components
DPLL1
Synth1
Synth2
SyncE
Line
Extracted
Clocks[7:0]
155.52MHz, 161.1328125MHz
or other frequency
25MHz
1 PPS
1588 signals to
system components
DPLL2
1588
Control info from
IEEE 1588 algorithm
Figure 2 - Synchronous Ethernet and IEEE 1588 Central Timing Application
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ZL30791, ZL30795, ZL30793
Product Brief
3. Detailed Features
3.1 Input Block Features
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Ten input reference pins; each can accept a CMOS signal or the POS side of a differential pair; or two
can be paired to accept both sides of a differential pair
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Any input can be a SYNC signal for REF+SYNC frequency/phase/time locking
Any input can be a clock signal with embedded PPS signal (duty cycle distortion indicates PPS location)
Input clocks can be any frequency from 0.5Hz up to 900MHz (180MHz max for CMOS inputs)
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, wireless
Inputs constantly monitored by programmable frequency and single-cycle monitors
Single-cycle monitor can quickly disqualify a reference when measured period is incorrect
Frequency measurement (ppb or Hz) and monitoring (coarse, fine, and frequency-step monitors)
Optional input clock invalidation on GPIO assertion to react to LOS signals from PHYs
Input-to-input phase measurement, 1ps resolution
Input-to-DPLL phase measurement, 1ps resolution
Per-input phase adjustment, 1ps resolution
3.2 DPLL Features
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One, two or three full-featured DPLLs
Very high-resolution DPLL architecture
State machine automatically transitions among freerun, tracking and holdover states
Revertive or nonrevertive reference selection algorithm
Programmable bandwidth from 0.1mHz to 470Hz
Less than 0.1dB gain peaking
Fast frequency/phase/time lock capability for 1PPS or clock+1PPS input references
Programmable phase-slope limiting (PSL)
Programmable frequency rate-of-change limiting (FCL)
Programmable tracking range (i.e. hold-in range)
Truly hitless reference switching and mode switching
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Physical-to-physical reference switching
Physical-to-packet reference switching
Packet-to-physical reference switching
Packet-to-packet reference switching
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Per-DPLL phase adjustment, 1ps resolution
High-resolution frequency and phase measurement
Fast detection of input clock failure and transition to holdover mode
High-resolution holdover frequency averaging, better than 0.01ppb when using <10mHz filter
Time-of-Day registers: 48-bit seconds, 32-bit nanoseconds, writeable on input PPS edge
3.3 Synthesizer Features
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Any-to-any frequency conversion with 0ppm error
Two low-jitter synthesizers (Synth1, Synth2) with very high-resolution fractional scaling (i.e. non-integer
multiplication)
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Two output dividers per low-jitter synthesizer: one integer (4 to 15 plus half divides 4.5 to 7.5) and one
40-bit fractional
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One general-purpose synthesizer (Synth0)
A total of five output frequency families
Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter
components
3.4 Low-Jitter Output Clock Features
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Up to 16 single-ended outputs (up to 8 differential outputs) from Synth1 and Synth2
Each output can be one differential output or two CMOS outputs
Output clocks can be any frequency from 1Hz to 1045MHz (250MHz max for CMOS and HSTL outputs)
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ZL30791, ZL30795, ZL30793
Product Brief
•
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Output jitter from Synth1 and Synth2 integer dividers is <0.3ps RMS
Output jitter from fractional dividers is <1ps RMS, many frequencies <0.5ps RMS
In CMOS mode, the HPOUTxN frequency can be an integer divisor of the HPOUTxP frequency
(Example 1: HPOUT3P 125MHz, HPOUT3N 25MHz. Example 2: HPOUT2P 25MHz, HPOUT2N 1Hz)
Outputs directly interface (DC coupled) with LVDS, LVPECL, HSTL, HCSL and CMOS components
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN
Can produce clock frequencies for microprocessors, ASICs, FPGAs and other components
Can produce PCIe clocks
Sophisticated output-to-output phase alignment
Per-synthesizer phase adjustment, 1ps resolution
Per-output phase adjustment
Per-output duty cycle / pulse width configuration
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Per-output enable/disable
Per-output glitchless start/stop (stop high or low)
3.5 General-Purpose Output Clock Features
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Two CMOS outputs from Synth0
Any frequency from 0.5Hz to 180MHz
Output jitter is typically 20-30ps
Useful for applications where the component or system receiving the signal has low bandwidth such as
a central timing IC
•
Can output a clock signal with embedded PPS (ePPS) (duty cycle distortion indicates PPS location)
3.6 Local Oscillator
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•
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Operates from a single TCXO or OCXO. Acceptable frequencies: 23.75MHz to 25MHz, 47.5MHz to
50MHz, 114.285MHz to 125MHz. Best jitter: 48MHz.
Very-low-jitter applications can connect a TCXO or OCXO (any frequency, any output jitter) as the
stability reference and a low-cost low-jitter XO as the jitter reference
This ability to have separate jitter and stability references greatly reduces the cost of the TCXO or
OCXO (no jitter requirement, no high-frequency-requirement) and allows reuse of already-qualified
TCXO and OCXO components
3.7 General Features
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Automatic self-configuration at power-up from internal Flash memory
Input-to-output alignment <200ps with external feedback
Fast REF+SYNC locking for frequency and 1PPS phase alignment with lower-cost oscillator
Generates output SYNC signals: 1PPS (IEEE 1588), 2kHz or 8kHz (SONET/SDH) or other frequency
JESD204B clocking: device clock and SYSREF signal generation with skew adjustment
Internal compensation for local oscillator frequency error in DPLLs and input monitors, 1ppt resolution
Numerically controlled oscillator (NCO) behavior allows system software to steer DPLL frequency or
fractional output divider frequency with resolution better than 0.005ppt
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Spread-spectrum modulation available in each fractional output divider (PCIe compliant)
Seven general-purpose I/O pins each with many possible status and control options
SPI or I2C serial microprocessor interface
3.8 Evaluation Software
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Simple, intuitive Windows-based graphical user interface
Supports all device features and register fields
Makes lab evaluation of the device quick and easy
Generates configuration scripts to be stored in internal Flash memory
Generates full or partial configuration scripts to be run on a system processor
Works with or without an evaluation board
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ZL30791, ZL30795, ZL30793
Product Brief
4. Software Features
The following figure shows the Time Synchronization Algorithm system environment. The subsections below list the
features of the Time Synchronization Algorithm.
Host Processor
Application Layer
Control, Configuration, Stats & Alarms
Clock
Microsemi
PLL
Packet
Network
Microsemi
Ethernet
MAC & PHY
(Timestamp)
Microsemi
ZLS30390
Microsemi
ZLS30380
SyncE/
Stratum 3/
GNSS/
Transport
Layer
Protocols
PPS
IEEE 1588-2008
Protocol Engine
Time Sync
Algorithm
IEEE 1588
Operating System
Timestamp Reference Clock
4.1 Time Synchronization Algorithm
The Time Synchronization Algorithm is responsible to accurately synchronize the local clock to a selected Server.
The Time Synchronization Algorithm is synchronizing the Client to the Server to meet a variety of specifications or
applications related to frequency accuracy (FFO), frequency (MTIE, TDEV), phase (1 Hz or 1PPS) and time (UTC
& GNSS/GPS).
The Time Synchronization Algorithm can run on a variety of host processor architectures, whether embedded into
an SoC or on a dedicated small scale CPU (such as Microsemi’s SmartFusion2 SoC FPGA). The Time
Synchronization Algorithm will interconnect with a wide array of software-programmable clock generators (such as
Microsemi’s Network Synchronizer PLLs), protocol engines (such as Microsemi’s ZLS30390 IEEE 1588-2008
Protocol Engine) and underlying Ethernet MACs and PHYs that perform hardware timestamping.
4.2 End Application Target Performance
The Time Synchronization Algorithm is suitable for many end application targets, including:
•
Frequency offset accuracy performance for GSM, WCDMA-FDD, LTE-FDD femtocell, small cell
(residential, urban, rural, enterprise), picocell and macrocell applications, with target performance less than
± 15 ppb
•
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Frequency performance for ITU-T G.823 and G.824 synchronization interface, as well as G.8261 PNT
EEC, PNT PEC and CES interface specifications
Phase Synchronization performance for WCDMA-TDD, Mobile WiMAX, TD-SCDMA, CDMA2000, LTE-
TDD, LTE-A, LTE-A Pro and 5G NR femtocell, small cell (residential, urban, rural, enterprise), picocell and
macrocell applications with target performance less than ± 1 s phase alignment
Time Synchronization for TAI, UTC-traceability and GNSS/GPS replacement
•
4.3 Packet Networks
The Time Synchronization Algorithm is suitable for high performance over a variety of packet networks including:
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ITU-T G.8261 Appendix VI
ITU-T G.8261.1 network limit compliant
ITU-T G.8271.1 network limit compliant without SyncE
ITU-T G.8271.2 network limit compliant
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ZL30791, ZL30795, ZL30793
Native Ethernet (switched) & IP (routed) networks
xDSL
Microwave
Fully aware, partially aware and unaware timing supported networks
Networks including intermediate Boundary Clocks and Transparent Clocks
Networks with and without SyncE or frequency physical layer support
Product Brief
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4.4 Clock Specifications
The Time Synchronization Algorithm meets the performance requirements from ITU-T packet clock specifications,
or draft packet clock specifications, including:
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ITU-T G.8261 Appendix VI
ITU-T G.8263 PEC-S
ITU-T G.8273.2 T-BC full on-path without SyncE
ITU-T G.8273.2 T-BC full on-path with SyncE
ITU-T G.8273.2 T-TSC full on-path without SyncE
ITU-T G.8273.2 T-TSC full on-path with SyncE
ITU-T G.8273.4 T-BC-A (draft)
ITU-T G.8273.4 T-BC-P (draft)
ITU-T G.8273.4 T-TSC-A (draft)
ITU-T G.8273.4 T-TSC-P (draft)
4.5 Profiles
The Time Synchronization Algorithm is suitable for use in a wide variety of markets and applications, including the
following IEEE 1588-2008 Profiles:
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IEEE 1588 Annex J.3 Delay Request-Response Default Profile (2008)
IEEE 1588 Annex J.4 Peer-to-peer Default Profile (2008)
ITU-T G.8265.1 Telecom Profile for Frequency Synchronization (Edition 1)
ITU-T G.8275.1 Telecom Profile for Phase with Full Timing Support Networks (Edition 1)
ITU-T G.8275.1 Telecom Profile for Phase with Full Timing Support Networks (Edition 2)
ITU-T G.8275.2 Telecom Profile for Phase with Partial Timing Support Networks (Edition 1)
CableLabs CM-SP-RDTI Remote DTI Profile (Edition I0x)
AES 67 Standard for Audio Applications of Networks – High-Performance Streaming Audio-over-IP
interoperability: PTP Profile for Media Applications
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SMPTE 2095-2 Profile for Use of IEEE-1588 Precision Time Protocol in Professional Broadcast
Applications
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AES R16 Project Report – PTP parameters for AES67 and SMPTE ST 2059-2 interoperability
IEEE C37.238 Standard Profile for Use of IEEE 1588 Precision Time Protocol in Power System
Applications (Edition 2011)
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IEEE C37.238 Standard Profile for Use of IEEE 1588 Precision Time Protocol in Power System
Applications (Edition 2017)
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IEC 61850-9-3 Precision time protocol profile for power utility automation (Edition 1.0)
IEC 62439-3 PTP profiles for high-availability automation networks (Edition 3.0)
IEEE802.1as AVB-TSN gPTP
IEEE 1588-2018 Annex J.5 High Accuracy Profile (based on White Rabbit)
IETF TICTOC Enterprise Profile
4.6 Monitoring & Redundancy
The Time Synchronization Algorithm includes monitoring and redundancy for high availability synchronization,
including:
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Synchronization to the best available server
Client monitoring of secondary server references
o
Monitoring includes full time synchronization reporting of secondary server
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Product Brief
o
Supports a programmable number of secondary server connections
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Hitless reference switching between multiple servers
Holdover when server packet connectivity is lost
TIE-clear option to build out, or clear, phase offsets between server references
4.7 General
The Time Synchronization Algorithm includes many advanced features to aide in the high-accuracy & high-stability
applications, including:
•
Full PLL state machine (Freerun, Holdover, Frequency Lock Acquiring, Frequency Lock Acquired, Phase
Lock Acquired), with programmable thresholds for state transitions
Programmable, non-linear packet selection with PDV suppression
Programmable bandwidth configurability from sub-mHz to 100s of mHz.
Programmable packet rates from 1 packet/second to over 128 packets/second
Programmable phase slope limiting, down to 1 ns/s
Programmable frequency change limiting, down to 1 ppb/s
Warm-start to initialize or seed the Time Synchronization Algorithm from a stored or last-known-good
frequency offset to improve convergence
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Programmable thresholds for management of phase errors: when to adjust with frequency offsets and
when to adjust with phase jumps
User ability to manually add frequency offsets due to temperature or ageing (especially during holdover
state)
4.8 Reporting
The Time Synchronization Algorithm includes user reporting to aide in performance debugging, including:
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Set of user notifications about packet network events, such as packet loss, small transient phase jumps,
large transient phase jumps, outliers, network path re-routes
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Set of metrics related to the synchronization, such as frequency stability and phase stability
Independent reporting of the forward path and reverse path lock status
Oscillator stability analysis for excessive ageing or temperature variation
Server tracking impairments such as pull-in range exceeded
4.9 Product Number Support
There are several Time Synchronization Algorithm products. The following table provides a summary of
support with the ZL3079x devices. Refer to ZLS30380 API User Guide section 1.0 “Products”.
Product Number
Product Name
Supported
ZLS30387
Basic Frequency and Phase Support
No
ZLS30384
Intermediate
Frequency & Phase
Support
No
ZLS30383
ZLS30380
Qualcomm
Small Cell Custom
No
Advanced
Yes
7
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