WF4M32-150H2E5A [MICROSEMI]
Flash Module, 4MX32, 150ns, CPGA66, 1.385 X 1.385 INCH, HERMETICALLY SEALED, CERAMIC, HIP-66;
| 型号： | WF4M32-150H2E5A |
| 厂家： | 
Microsemi |
| 描述： | Flash Module, 4MX32, 150ns, CPGA66, 1.385 X 1.385 INCH, HERMETICALLY SEALED, CERAMIC, HIP-66 |
| 文件： | 总15页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WF4M32-XXX5
White Electronic Designs
PRELIMINARY*
4MX32 5V FLASH MODULE
FEATURES
!
!
Organized as 4Mx32
!
Access Times of 100, 120, 150ns
User configurable as 8Mx16 or 16Mx8 in HIP and
G4T packages.
!
Packaging:
!
Commercial, Industrial, and Extended
Temperature Ranges
• 66 pin, PGA Type, 1.385" square, Hermetic
Ceramic HIP (Package 402).
• 68 lead, 40mm Low Profile CQFP ( Package
502 ), 3.5mm (0.140") height.
!
!
!
5 Volt Read and Write. 5V ± 10% Supply.
Low Power CMOS
• 68 lead, Hermetic CQFP (G2T), 22.4mm
(0.880") square (Package 509) 4.57mm
(0.180") height. Designed to fit JEDEC 68
lead 0.990CQFJ footprint (Fig. 3)
Data Polling and Toggle Bit feature for detection
of program or erase cycle completion.
!
!
!
Supports reading or programming data to a
sector not being erased.
!
!
Sector Architecture
RESET pin resets internal state machine to the
read mode.
• 32 equal size sectors of 64KBytes per each
2Mx8 chip
Built-in Decoupling Caps and Multiple Ground
Pins for Low Noise Operation, Separate Power
and Ground Planes to improve noise immunity
• Any combination of sectors can be erased. Also
supports full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
*This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Note:
For programming information refer to Flash Programming 16M5
Application Note.
FIG. 1 PIN CONFIGURATION FOR WF4M32-XH2X5
PIN DESCRIPTION
TOP VIEW
I/O0-31 Data Inputs/Outputs
1
12
23
34
45
56
A0-21
WE
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
I/O
8
9
RESET
I/O15
I/O14
I/O13
I/O12
OE
I/O24
I/O25
I/O26
V
CC
I/O31
I/O30
I/O29
I/O28
CS1-4
OE
I/O
CS
2
CS4
I/O10
GND
I/O11
NC
VCC
GND
RESET
A
A
A
A
A
14
16
11
0
A
7
I/O27
Reset
A
A
A
V
10
A
A
A
12
21
13
A
A
A
4
5
6
A1
A2
A3
9
A
17
BLOCK DIAGRAM
15
CC
WE
CS
CS
3
CS
4
1
CS
2
A
21
18
I/O
I/O
I/O
I/O
7
A
8
A20
CS
I/O23
I/O22
I/O21
I/O20
I/O0
I/O1
I/O2
CS
1
6
5
4
I/O16
I/O17
I/O18
3
OE
WE
A19
GND
I/O19
A
0-20
RESET
2M x 8
2M x 8
2Mx 8
2M x 8
I/O3
2M x 8
2M x 8
2M x 8
2M x 8
11
22
33
44
55
66
I/O16-23
I/O24-31
I/O0-7
I/O8-15
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
December2003 Rev.5
WF4M32-XXX5
White Electronic Designs
FIG. 2 PIN CONFIGURATION FOR WF4M32-XG4TX5
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
TOP VIEW
A0-21
WE
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Reset
CS1-4
OE
9
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
VCC
RESET
GND
NC
Ground
Not Connected
GND
BLOCK DIAGRAM
I/O
8
9
CS
CS
3
CS
4
CS
2
1
I/O
A
21
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
OE
WE
BUFFER
A
0-20
RESET
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
FIG. 3 PIN CONFIGURATION FOR WF4M32-XG2TX5
PIN DESCRIPTION
I/O0-31DataInputs/Outputs
TOP VIEW
A0-20
WE
Address Inputs
Write Enables
Banks Selects
Output Enable
Power Supply
Ground
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CS1-2
OE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
The WEDC 68 lead G2T
CQFP fills the same fit
and function as the
VCC
GND
RESET
JEDEC 68 lead CQFJ or
68 PLCC. But the G2T has
the TCE and lead inspec-
tion advantage of the
CQFP form.
Reset
GND
I/O
8
9
I/O
BLOCK DIAGRAM
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CS
1
RESET
WE
OE
0-20
A
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
8
8
8
8
CS
2
I/O16-23
I/O24-31
I/O0-7
I/O8-15
Note: CS1& CS2 are used as bank select
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ABSOLUTE MAXIMUM RATINGS
CAPACITANCE (PF)
(TA = +25°C, VIN = OV, F = 1.0MHZ)
Parameter
Symbol Ratings
Unit
V
Parameter
Symbol HIP (H2) CQFP (G2T) CQFP(G4T)
Voltage on Any Pin Relative to VSS
Power Dissipation
VT
PT
-2.0 to +7.0
8
OE capacitance
COE
CWE
CCS
CI/O
CAD
75
75
20
30
75
75
75
50
30
75
20
20
20
30
20
W
WE capacitance
StorageTemperature
Short Circuit Output Current
Tstg -65 to +125
°C
CS capacitance
IOS
100
mA
cycles
Data I/O capacitance
Address input capacitance
Endurance - Write/Erase Cycles
(Extended)
100,000 min
Data Retention (Mil Temp)
20
years
This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Parameter Symbol Min Typ
Max
5.5
Unit
Supply Voltage
VCC
VSS
VIH
VIL
TA
4.5 5.0
V
V
Ground
0
0
-
0
Input High Voltage
2.0
-0.5
-55
-40
VCC + 0.5
+0.8
V
Input Low Voltage
-
V
OperatingTemperature(Extended.)(4)
Operating Temperature (Ind.)
-
+100
+85
°C
°C
TA
-
DC CHARACTERISTICS - CMOS COMPATIBLE
(VCC = 5.0V, GND = 0V, TA = -55°C TO +125°C) (NOTE 4)
Parameter
Symbol
Conditions
HIP
G2T
G4T
Min
Unit
Min
Max Min Max
Max
10
Input Leakage Current
ILI
VCC = 5.5, VIN = GND to VCC
VCC = 5.5, VIN = GND to VCC
CS = VIL, OE = VIH, f = 5MHz
CS = VIL, OE = VIH
10
10
10
10
µA
µA
Output Leakage Current
VCC Active Current for Read (1)
ILOx32
ICC1
ICC2
10
320
420
215
295
345
445
mA
mA
VCC Active Current for Program
or Erase (2)
VCC Standby Current
Output Low Voltage
Output High Voltage
ICC3
VOL
VOH
VCC = 5.5, CS = VIH, f = 5MHz, RESET = VIH
IOL = 12.0 mA, VCC = 4.5
20
2.0
95
mA
V
0.45
0.45
0.45
IOH = -2.5 mA, VCC = 4.5
0.85 x
Vcc
0.85 x
Vcc
0.85 x
Vcc
V
Low VCC Lock-Out Voltage
VLKO
3.2
4.2
3.2
4.2
3.2
4.2
V
NOTES:
1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The
frequency component typically is less than 2mA/MHz, with OE at VIH.
2. Icc active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions VIL = 0.3V, VIH = VCC - 0.3V
4. Extended temperature device are fully operational from -55° to +100°C.
Operation above 100°C to 125°C
is limited to read only operations.
HIP = 66 pin, PGA Type, 1.385" square, Hermetic
Ceramic HIP (Package 402).
G2T = 68 lead, Hermetic CQFP (G2T), 22.4mm
(0.880") square. Designed to fit JEDEC 68 lead
0.990" CQFJ footprint (Fig. 3) (Package 509)
G4T = 68 lead, 40mm Low Profile CQFP, 3.5mm
(0.140") (Package 502 )
3
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AC CHARACTERISTICS FOR G2T PACKAGE – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
(VCC = 5.0V, TA = -55°C TO +100°C) (NOTE 5)
Parameter
Symbol
-100
-120
-150
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
tAVAV
tWC
tCS
100
120
150
ns
ns
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
tELWL
0
45
0
0
50
0
0
50
0
tWLWH
tAVWL
tDVWH
tWHDX
tWLAX
tWHWL
tWHWH1
tWHWH2
tWP
tAS
ns
ns
Data Setup Time
tDS
45
0
50
0
50
0
ns
Data Hold Time
tDH
ns
Address Hold Time
tAH
45
20
50
20
50
20
ns
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase (2)
tWPH
ns
300
15
300
15
300
15
µs
sec
µs
Read Recovery Time before Write
VCC Setup Time
tGH
W
L
0
0
0
tV C S
50
50
50
µs
Chip Programming Time
Chip Erase Time (3)
44
44
44
sec
sec
ns
256
256
256
Output Enable Hold Time (4)
RESET Pulse Width
tOEH
10
10
10
tRP
500
500
500
ns
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
5. Extended temperature device are fully operational from -55° to +100°C.
Operation above 100°C to 125°C is limited to read only operations.
AC CHARACTERISTICS FOR G2T PACKAGE – READ-ONLY OPERATIONS
(VCC = 5.0V, TA = -55°C TO +125°C) (NOTE 2)
Parameter
Symbol
-100
-120
-150
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
tAVAV
tRC
tACC
tCE
tOE
tDF
100
120
150
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
100
100
40
120
120
50
150
150
55
Chip Select Access Time
Output Enable to Output Valid
Chip Select High to Output High Z (1)
Output Enable High to Output High Z (1)
20
30
35
tDF
20
30
35
Output Hold from Addresses, CS or OE Change,
whichever is First
tOH
0
0
0
RST Low to Read Mode (1)
tReady
20
20
20
µs
1. Guaranteed by design, not tested.
2. Extended temperature device are fully operational from -55° to +100°C.
Operation above 100°C to 125°C is limited to read only operations.
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4
WF4M32-XXX5
White Electronic Designs
AC CHARACTERISTICS FOR G2T PACKAGE – WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED
(VCC = 5.0V, GND = 0V, TA = -55°C TO +100°C) (Note 5)
Parameter
Symbol
-100
-120
-150
Unit
Min
100
0
Max
Min
120
0
Max
Min
150
0
Max
Write Cycle Time
tAVAV
tWC
tWS
tCP
tAS
tDS
tDH
tAH
tCPH
ns
ns
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
tWLEL
tELEH
45
0
50
0
50
0
ns
tAVEL
ns
Data Setup Time
tDVEH
tEHDX
tELAX
45
0
50
0
50
0
ns
Data Hold Time
ns
Address Hold Time
45
20
50
20
50
20
ns
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
Chip Erase Time (3)
tEHEL
ns
tWHWH1
tWHWH2
tGHEL
300
15
300
15
300
15
µs
sec
µs
0
0
0
44
44
44
sec
sec
ns
256
256
256
Output Enable Hold Time (4)
tOEH
10
10
10
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
5. Extended temperature device are fully operational from -55° to +100°C.
Operation above 100°C to 125°C is limited to read only operations.
5
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White Electronic Designs
AC CHARACTERISTICS FOR G4T AND H2 PACKAGES – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
(VCC = 5.0V, TA = -55°C TO +100°C) (Note 7)
Parameter
Symbol
-100
-120
-150
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
tAVAV
tWC
tCS
100
120
150
ns
ns
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
tELWL
0
0
0
tWLWH
tAVWL
tWP
tAS
45
0
50
0
50
0
ns
ns
Data Setup Time
tDVWH
tWHDX
tWLAX
tWHWL
tWHWH1
tWHWH2
tDS
45
15
45
20
50
15
50
20
50
15
50
20
ns
Data Hold Time
tDH
ns
Address Hold Time (1)
Write Enable Pulse Width High (2)
Duration of Byte Programming Operation (3)
Sector Erase (4)
tAH
ns
tWPH
ns
300
15
300
15
300
15
µs
sec
µs
Read Recovery Time before Write
VCC Setup Time
tGH
W
L
0
0
0
tV C S
50
50
50
µs
Chip Programming Time
Chip Erase Time (5)
44
44
44
sec
sec
ns
256
256
256
Output Enable Hold Time (6)
RESET Pulse Width
tOEH
10
10
10
tRP
500
500
500
ns
NOTES:
1. A21 must be held constant until WE or CS go high, whichever occurs first.
2. Guaranteed by design, but not tested.
3. Typical value for tWHWH1 is 7µs.
4. Typical value for tWHWH2 is 1sec.
5. Typical value for Chip Erase Time is 32sec.
6. For Toggle and Data Polling.
7. Extended temperature device are fully operational from -55° to +100°C.
Operation above 100°C to 125°C is limited to read only operations.
AC CHARACTERISTICS FOR G4T AND H2 PACKAGES – READ-ONLY OPERATIONS
(VCC = 5.0V, TA = -55°C TO +125°C) (NOTE 1)
Parameter
Symbol
-100
-120
-150
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
tAVAV
tRC
tACC
tCE
tOE
tDF
100
120
150
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
100
100
50
120
120
50
150
150
55
Chip Select Access Time
Output Enable to Output Valid
Chip Select High to Output High Z
Output Enable High to Output High Z
40
45
45
tDF
40
45
45
Output Hold from Addresses, CS or OE Change,
whichever is First
tOH
0
0
0
RST Low to Read Mode
tReady
20
20
20
µs
NOTES:
1. Extended temperature device are fully operational from -55° to +100°C.
Operation above 100°C to 125°C is limited to read only operations.
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WF4M32-XXX5
White Electronic Designs
AC CHARACTERISTICS FOR G4T AND H2 PACKAGES – WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED
(VCC = 5.0V, GND = 0V, TA = -55°C TO +100°C) (Note 6)
Parameter
Symbol
-100
-120
-150
Unit
Min
100
0
Max
Min
120
0
Max
Min
150
0
Max
Write Cycle Time
tAVAV
tWC
tWS
tCP
tAS
tDS
tDH
tAH
tCPH
ns
ns
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
tWLEL
tELEH
45
0
50
0
50
0
ns
tAVEL
ns
Data Setup Time
tDVEH
tEHDX
tELAX
45
15
45
20
50
15
50
20
50
15
50
20
ns
Data Hold Time
ns
Address Hold Time (1)
Chip Select Pulse Width High
Duration of Byte Programming Operation (2)
Sector Erase Time (3)
Read Recovery Time
Chip Programming Time
Chip Erase Time (4)
ns
tEHEL
ns
tWHWH1
tWHWH2
tGHEL
300
15
300
15
300
15
µs
sec
µs
0
0
0
44
44
44
sec
sec
ns
256
256
256
Output Enable Hold Time (5)
tOEH
10
10
10
NOTES:
1. A21 must be held constant until WE or CS go high, whichever occurs first.
2. Typical value for tWHWH1 is 7µs.
3. Typical value for tWHWH2 is 1sec.
4. Typical value for Chip Erase Time is 32sec.
5. For Toggle and Data Polling.
6. Extended temperature device are fully operational from -55° to +100°C. Operation above 100°C to 125°C
is limited to read only operations.
AC TEST CONDITIONS
Typ
FIG. 4 AC TEST CIRCUIT
Parameter
Unit
Input Pulse Levels
Input Rise and Fall
VIL = 0, VIH = 3.0
5
V
ns
V
Input and Output Reference Level 1.5
Output Timing Reference Level
1.5
V
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75W.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load
circuit.
ATE tester includes jig capacitance.
FIG. 5 RESET TIMING DIAGRAM
RESET
tRP
tReady
7
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FIG. 6 AC WAVEFORMS FOR READ OPERATIONS
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FIG. 7 WRITE/ERASE/PROGRAM OPERATION, WE CONTROLLED
NO TES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure ind icates last two b us cycles of four b us cycle seq uence.
9
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FIG. 8 AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
NO TE:
1. SA is the sector ad d ress for Sector Erase.
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FIG. 9 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS
1 1
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FIG. 10 ALTERNATE CS CONTROLLED PROGRAMMING OPERATION TIMINGS
No tes:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure ind icates the last two b us cycles of a four b us cycle seq uence.
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PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 502: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G4T)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
1 3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF4M32-XXX5
White Electronic Designs
PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
The WEPC 68 lead G2T
CQFP fills the same fit
and function as the
JEDEC 68 lead CQFJ or
68 PLCC. But the G2T has
the TCE and lead inspec-
tion advantage of the
CQFP form.
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
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WF4M32-XXX5
White Electronic Designs
ORDERING INFORMATION
W F 4M32 - XXX X X 5 X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
VPP PROGRAMMING VOLTAGE
5 = 5 V
DEVICE GRADE:
E = Extended
I = Industrial
-55°C to +100°C (Note 1)
-40°C to +85°C
0°C to +70°C
C = Commercial
PACKAGETYPE:
H2 = Ceramic Hex In line Package, HIP (Package 402)
G4T = 40mm Low Profile CQFP (Package 502)
G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509)
ACCESS TIME (ns)
ORGANIZATION, 4M x 32
User configurable as 8M x 16 or 16M x 8 in HIP and G4T packages
FLASH
WHITE ELECTRONIC DESIGNS CORP.
NOTE 1:
4. Extended temperature device are fully operational from -55° to +100°C.
Operation above 100°C to 125°C is limited to read only operations.
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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