W3EG7264S262BD4 [MICROSEMI]
DDR DRAM Module, 64MX8, 0.75ns, CMOS, ROHS COMPLIANT, SO-DIMM-200;
| 型号： | W3EG7264S262BD4 |
| 厂家： | 
Microsemi |
| 描述： | DDR DRAM Module, 64MX8, 0.75ns, CMOS, ROHS COMPLIANT, SO-DIMM-200 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总13页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3EG7264S-AD4
-BD4
White Electronic Designs
PRELIMINARY*
512MB – 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL
FEATURES
DESCRIPTION
Double-data-rate architecture
The W3EG7264S is a 2x32Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of nine 64Mx8 DDR
SDRAMs stacked in 54 pin TSOP packages mounted on
a 200 pin FR4 substrate. This module is structured as 2
Ranks of 64Mx72 DDR SDRAM.
DDR200, DDR266 DDR333
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Serial presence detect
Dual Rank
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Power supply: 2.5V ± 0.2V
200 pin SO-DIMM package
• Package height options:
AD4: 35.05 mm (1.38”)
BD4: 31.75 mm (1.25”)
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
DDR333@CL=2.5
166MHz
DDR266@CL=2
133MHz
DDR266@CL=2.5
133MHz
DDR200@CL=2
100MHz
Clock Speed
CL-tRCD-tRP
2.5-3-3
2-2-2
2.5-3-3
2-2-2
January 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG7264S-AD4
-BD4
White Electronic Designs
PRELIMINARY
PIN CONFIGURATION
PIN NAMES
A0 – A12
BA0-BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
CK0
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Check bits
Pin
1
Symbol
VREF
VREF
VSS
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
VSS
Pin
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
A9
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Symbol
DQ42
DQ46
DQ43
DQ47
VCC
2
VSS
A8
3
DQ19
DQ23
DQ24
DQ28
VCC
VSS
Data Strobe Input/Output
Clock Input
4
VSS
VSS
5
DQ0
DQ4
DQ1
DQ5
VCC
A7
CK0#
Clock input
6
A6
VCC
CKE0-CKE1
CS0#-CS1#
RAS#
Clock Enable input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
7
A5
VCC
8
VCC
A4
CK1#*
VSS
9
DQ25
DQ29
DQS3
DQM3
VSS
A3
CAS#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
A2
CK1*
VSS
WE#
DQS0
DQM0
DQ2
DQ6
VSS
A1
DQM0-DQM8 Data-In Mask
A0
VSS
VCC
Power Supply (2.5V)
VCC
DQ48
DQ52
DQ49
DQ53
VCC
VSS
Ground
VSS
VCC
VREF
VCCSPD
SDA
Power Supply for Reference
Serial EEPROM Power Supply (2.3V to 3.6V)
Serial data I/O
DQ26
DQ30
DQ27
DQ31
VCC
A10/AP
BA1
BA0
RAS#
WE#
CAS#
CS0#
CS1#
NC
VSS
DQ3
DQ7
DQ8
DQ12
VCC
SCL
Serial clock
VCC
SA0-SA2
VCCID
NC
Address in EEPROM
VCC Identification Flag
No Connect
DQS6
DQM6
DQ50
DQ54
VSS
VCC
CB0
CB4
CB1
CB5
VSS
VCC
* Not Used
DQ9
DQ13
DQS1
DQM1
VSS
NC
VSS
VSS
DQ51
DQ55
DQ56
DQ60
VCC
VSS
VSS
DQS8
DQM8
CB2
CB6
VCC
DQ32
DQ36
DQ33
DQ37
VCC
VSS
DQ10
DQ14
DQ11
DQ15
VCC
VCC
DQ57
DQ61
DQS7
DQM7
VSS
VCC
VCC
CB3
CB7
NC
DQS4
DQM4
DQ34
DQ38
VSS
VCC
CK0
VCC
NC
VSS
CK0#
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VCC
VSS
VSS
VSS
CK2*
VSS
DQ35
DQ39
DQ40
DQ44
VCC
VSS
DQ16
DQ20
DQ17
DQ21
VCC
CK2#*
VCC
VCC
VCC
SDA
VCC
VCC
SA0
CKE1
CKE0
NC
DQ41
DQ45
DQS5
DQM5
VSS
SCL
VCC
SA1
DQS2
DQM2
DQ18
DQ22
VCCSPD
SA2
NC
A12
VCCID
NC
A11
VSS
January 2005
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG7264S-AD4
-BD4
White Electronic Designs
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS0
DQM0
DQS4
DQM4
CS#
CS#
DM
CS#
DQS
DM
CS#
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS1
DQM1
DQS5
DQM5
CS#
CS#
CS#
CS#
DM
CS#
CS#
CS#
DQS
DQS
DQS
DM
CS#
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQM2
DQS6
DQM6
CS#
DM
CS#
DQS
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQM7
DQS3
DQM3
CS#
DM
DM
CS#
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DQM8
CS#
VCC
DDR SDRAM
DM
CS#
DQS
120Ω
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0A
CK0
PLL
CK0A#
CK0#
FEEDBACK
RAS#
RAS: DDR SDRAMs
CAS: DDR SDRAMs
CAS#
BA0-BA1
WE#
SERIAL PD
A1
SCL
SDA
BA0-BA1: DDR SDRAMs
WE: DDR SDRAMs
A0
A2
SA0 SA1 SA2
A0-A12
CKE0
A0-A12: DDR SDRAMs
CKE0: DDR SDRAMs
CKE1: DDR SDRAMs
VCC
DDR SDRAM
DDR SDRAM
CKE1
GND
NOTE: All datalines are terminated through a 22 ohm series resistor.
January 2005
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG7264S-AD4
-BD4
White Electronic Designs
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
– 0.5 ~ 3.6
–1.0 ~ 3.6
– 55 ~ +150
9
Units
V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC, VCCQ
TSTG
V
°C
W
Power Dissipation
PD
Short Circuit Current
IOS
50
mA
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC CHARACTERISTICS
0°C TA 70°C, VCC = 2.5V ± 0.2V
Parameter
Symbol
VCC
Min
2.3
Max
2.7
Unit
V
Supply Voltage
Supply Voltage
VCCQ
VREF
VTT
2.3
2.7
V
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
1.15
1.35
V
1.15
1.35
V
VIH
VREF + 0.15
– 0.3
VCCQ + 0.3
VREF – 0.15
—
V
VIL
V
VOH
VTT + 0.76
—
V
VOL
VTT – 0.76
V
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 2.5V
Parameter
Symbol
Max
56
56
29
5.5
29
13
56
13
13
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A12)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT
COUT
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0,CKE1)
Input Capacitance (CK0,CK0#)
Input Capacitance (CS0#,CS1#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output Capacitance (DQ0-DQ63)(DQS)
Data input/output Capacitance (CB0-CB7)
January 2005
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG7264S-AD4
-BD4
White Electronic Designs
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C TA 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
DDR333@CL=2.5 DDR266@CL=2, 2.5 DDR200@CL=2
Parameter
Symbol Conditions
Max
Max
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge;
2205
2025
2025
mA
(MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address
and control inputs changing once every
two cycles. TRC=TRC(MIN); TCK=TCK
Operating Current
IDD1
One device bank; Active-
2610
2340
2340
mA
Read-Precharge; Burst = 2;
TRC=TRC(MIN);TCK=TCK (MIN); Iout
= 0mA; Address and control inputs
changing once per clock cycle.
Precharge Power-Down IDD2P All device banks idle; Power-down
72
72
72
mA
mA
Standby Current
mode; TCK=TCK(MIN); CKE=(low)
Idle Standby Current
IDD2F CS# = High; All device banks idle;
TCK=TCK(MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
900
810
810
Active Power-Down
Standby Current
IDD3P One device bank active; Power-down
mode; TCK(MIN); CKE=(low)
540
450
900
450
900
mA
mA
Active Standby Current
IDD3N CS# = High; CKE = High; One
device bank; Active-Precharge;
1080
TRC=TRAS(MAX); TCK=TCK(MIN); DQ,
DM and DQS inputs changing twice per
clock cycle; Address and other control
inputs changing once per clock cycle.
Operating Current
Operating Current
IDD4R Burst = 2; Reads; Continous burst; One
device bank active;Address andcontrol
inputs changing once per clock cycle;
TCK=TCK(MIN); IOUT = 0mA.
2655
2655
2250
2250
2250
2250
mA
mA
IDD4W Burst = 2; Writes; Continous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
TCK=TCK(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
Auto Refresh Current
Self Refresh Current
Operating Current
IDD5
IDD6
TRC=TRC(MIN)
3375
72
3015
72
3015
72
mA
mA
mA
CKE ≤ 0.2V
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with TRC=TRC (MIN);
TCK=TCK(MIN); Address and control
inputs change only during Active Read
or Write commands
4770
4050
4050
January 2005
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG7264S-AD4
-BD4
White Electronic Designs
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
3. Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
4. Timing Patterns :
•
•
•
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
•
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
•
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
January 2005
Rev. 3
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG7264S-AD4
-BD4
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
AC CHARACTERISTICS
335
262
265
202
PARAMETER
SYMBOL MIN
MAX
+0.7
0.55
0.55
13
MIN
MAX
MIN
MAX
MIN
MAX UNITS NOTES
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
tAC
tCH
-0.7
0.45
0.45
7.6
+0.75 -0.75 +0.75 -0.75 +0.75 -0.75
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
0.45
0.45
10
0.55
0.55
13
0.45
0.45
10
0.55
0.55
13
0.45
0.45
10
0.55
0.55
13
25
25
tCL
Clock cycle time
CL = 2.5
CL = 2
tCK (2.5)
tCK (2)
tDH
37, 42
41
7.5
13
7.5
13
7.5
13
7.5
13
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
0.45
0.45
1.75
22, 26
22, 26
26
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
-0.60 +0.60
0.35
+0.8
+0.8
+0.8
DQS input low pulse width
0.35
DQS-DQ skew, DQS to last DQ valid, per group, per
access
0.45
0.6
0.6
0.6
22
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
tDQSS
tDSS
tDSH
tHP
0.75
0.2
1.25
0.75
0.2
1.25
0.75
0.2
1.25
0.75
0.2
1.25
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.2
0.2
0.2
0.2
tCH,tCL
tCH,tCL
tCH,tCL
tCH,tCL
29
16, 36
16, 36
12
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (1 V/ns)
Address and control input setup time (1 V/ns)
Address and control input hold time (0.5 V/ns)
Address and control input setup time (0.5 V/ns)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
tHZ
+0.70
+0.8
12
+0.8
12
+0.8
12
tLZ
-0.70
0.75
-0.8
ns
-0.8
ns
-0.8
ns
tIHF
tISF
0.75
1.1
1.1
1.1
12
tIHS
tISS
tIPW
tMRD
tQH
0.80
1.1
1.1
1.1
12
0.80
1.1
1.1
1.1
12
2.2
2.2
2.2
2.2
12
16
16
16
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tHP - tQHS
tHP - tQHS
tHP - tQHS
tHP - tQHS
22
30
Data hold skew factor
tQHS
tRAS
tRAP
tRC
0.55
1
1
1
ns
ns
ns
ns
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
42
15
60
70,000
40
20
70
120,000
40
20
70
120,000
40
20
70
120,000
ACTIVE to ACTIVE/AUTO REFRESH command
period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
tRFC
tRCD
72
15
75
20
75
20
75
20
ns
ns
ns
tCK
tCK
ns
tCK
ns
40
tRP
15
20
20
20
tRPRE
tRPST
tRRD
0.9
0.4
12
1.1
0.6
0.9
0.4
15
1.1
0.6
0.9
0.4
15
1.1
0.6
0.9
0.4
15
1.1
0.6
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
tWPRE
tWPRES
0.25
0
0.25
0
0.25
0
0.25
0
DQS write preamble setup time
17, 19
January 2005
Rev. 3
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG7264S-AD4
-BD4
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS (Continued)
AC CHARACTERISTICS
335
262
265
202
PARAMETER
SYMBOL MIN
MAX
MIN
0.4
15
MAX
MIN
0.4
15
MAX
MIN
0.4
15
MAX UNITS NOTES
DQS write postamble
Write recovery time
tWPST
tWR
0.4
15
0.6
0.6
0.6
0.6
tCK
ns
17
Internal WRITE to READ command delay
tWTR
1
1
1
1
tCK
Data valid output window
na
tQH - tDQSQ
70.3
7.8
tQH - tDQSQ
70.3
7.8
tQH - tDQSQ
70.3
7.8
tQH - tDQSQ
70.3
7.8
ns
μs
μs
ns
ns
tCK
22
21
21
REFRESH to REFRESH command interval
Average periodic refresh interval
tREFC
tREFI
tVTD
Terminating voltage delay to VCC
0
0
0
0
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tXSNR
tXSRD
75
75
75
75
200
200
200
200
January 2005
Rev. 3
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG7264S-AD4
-BD4
White Electronic Designs
PRELIMINARY
Notes
1. All voltages referenced to VSS
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified.
.
18. tHZ and tLZ transitions occur in the same access time windows as data valid
transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
19. The intent of the “Don’t Care” state after completion of the postamble is that the
DQS-driven signal should either be HIGH, LOW, or High-Z and that any signal
transition within the input switching region must follow valid input requirements. If
DQS transitions HIGH, above DC VIH (MIN) then it must not transition LOW, below
DC VIH, prior to tDQSH (MIN).
20. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
3. Outputs (except for IDD measurements) measured with equivalent load:
V
TT
50Ω
RReeffeerreennccee
Output
(VOUT
Point
30pF
)
progress, DQS could be HIGH during this time, depending on tDQSS
.
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing point for
CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The mini-mum slew rate for the input signals
used to test the device is 1 V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC input
level and will remain in that state as long as the signal does not ring back above
[below] the DC input LOW [HIGH] level).
22. tRC (MIN) or tRFC (MIN) for IDD measurements is the smallest multiple of tCK that
meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD
measurements is the largest multiple of tCK that meets the maxi-mum absolute value
for tRAS
.
23. The refresh period is 64ms. This equates to an average refresh rate of 7.8125μs.
However, an AUTO REFRESH command must be asserted at least once every
70.3μs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
6.
VREF is expected to equal VCC/2 of the transmitting device and to track variations in
the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not
exceed ±2 percent of the DC value. Thus, from VCC/2, VREF is allowed ±25mV for
DC error and an additional ±25mV for AC noise. This measurement is to be taken at
the nearest VREF bypass capacitor.
25. The data valid window is derived by achieving other specifications: tHP (tCK/2), tDQSQ
and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the
clock duty cycle and a practical data valid window can be derived. The clock is
,
allowed a maximum duty-cycle variation of 45/55, because functionality is uncertain
when operating beyond a 45/55 ratio.
7.
8.
V
TT is not applied directly to the device. VTT, a system supply for signal termination
resistors, is expected to be set equal to VREF and must track variations in the DC
level of VREF
ID is the magnitude of the difference between the input level on CK and the input
level on CK#.
26. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with
DQ0–DQ7; x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.
27. This limit is actually a nominal value and does not result in a fail value. CKE is
HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during
standby).
28. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL (AC) or VIH (AC).
.
V
9. The value of VIX and VMP are expected to equal VCC/2 of the transmitting device and
must track variations in the DC level of the same.
10. IDD is dependent on output loading and cycle rates. Specified values are obtained
with mini-mum cycle times at CL = 2.5 for 335, and CL = 2 for 262, 265 and 202
speeds with the outputs open.
b. Reach at least the target AC level.
11. Enables on-chip refresh and address counters.
12. IDD specifications are tested after the device is properly initialized and is averaged at
the defined cycle rate.
c. After the AC target level is reached, continue to maintain at least the target DC
level, VIL (DC) or VIH (DC).
29. The Input capacitance per pin group will not differ by more than this maximum
amount for any given device.
30. CK and CK# input slew rate must be ≥ 1V/ns ( ≥ 2V/ns if measured differentially).
31. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If
the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must
be added to tDS and tDH for each 0.1 V/ns reduction in slew rate. For 335 speed
grades, slew rate must be ≥ 0.5 V/ns. If slew rate exceeds 4 V/ns, functionality is
uncertain.
13. This parameter is sampled. VCC = +2.5V±0.2V, VCC = +2.5V±0.2V, VREF = VSS, f =
100 MHz, TA = 25°C, VOUT (DC) = VCC/2, VOUT (peak to peak) = 0.2V. DM input is
grouped with I/O pins, reflecting that they are matched in loading.
14. For slew rates < 1 V/ns and ≥ 0.5 V/ns. If slew rate is less than 0.5 V/ns, timing
must be derated; tIS has an additional 50ps per each 100mV/ns reduction in slew
rate from the 500mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns,
functionality is uncertain. For 335, slew rates must be greater than or equal to
0.5V/ns.
32. VCC must not vary more than four percent if CKE is not active while any bank is
active.
33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary
by the same amount.
15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
VREF
.
16. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including
Self-Refresh mode, VREF must be powered within the specified range. Exception:
during the period before VREF stabilizes, CKE = 0.3 x VCC is recognized as LOW.
17. The output timing reference level, as measured at the timing reference point
34. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the
device CK and CK# inputs, collectively during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS
(MIN) can be satisfied prior to the internal PRECHARGE command being issued.
indicated in Note 3, is VTT
.
January 2005
Rev. 3
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG7264S-AD4
-BD4
White Electronic Designs
PRELIMINARY
36. Any positive glitch must be less than 1/3 of the clock cycle and not more than
+400mV or 2.9V. Any negative glitch must be less than 1/3 of the clock cycle and
not exceed either -300mV or 2.2V.
37. The voltage levels used are derived from a mini-mum VCC level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide significantly different voltage values.
38. VIH overshoot: VIH (MAX) = VCC + 1.5V for a pulse width ≤ 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL under-shoot: VIL (MIN) = -1.5V for a
pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
39. VCC and VCC must track each other.
40. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
41. tRPST end point and tRPRE begin point are not referenced to a specific voltage level
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
42. During initialization, VCC, VTT, and VREF must be equal to or less than VCC + 0.3V.
Alternatively, VTT may be 1.35V maximum during power-up, even if VCC/VCC are 0V,
provided a minimum of 42Ω of series resistance is used between the VTT supply
and the input pin.
44. When an input signal is indicated to be HIGH or LOW, it is defined as a steady state
logic HIGH or LOW.
45. Random addressing changing; 50 percent of data changing at every transfer.
46. Random addressing changing; 100 percent of data changing at every transfer.
47. CKE must be active (HIGH) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC has been satisfied.
48. IDD2N specifies the DQ, DQS and DM to be driven to a valid HIGH or LOW logic
level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs
to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
49. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset followed by 200 clock cycles before any READ command.
50. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20
MHz. Any noise above 20 MHz at the DRAM generated from any source other than
that of the DRAM itself may not exceed the DC voltage range of 2.6V±100mV.
51. The 335 speed grades will operate with tRAS(min) = 40ns and tRAS(max) = 120,000ns
at any slower frequency.
43. The current part operates below the slowest JEDEC operating frequency of 83 MHz.
As such, future die may not reflect this option.
January 2005
Rev. 3
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG7264S-AD4
-BD4
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR BD4
Part Number
Speed
Height*
W3EG7264S335BD4
W3EG7264S262BD4
W3EG7264S265BD4
W3EG7264S202BD4
166MHz/333Mbps, CL=2.5
133MHz/266Mbps, CL=2
133MHz/266Mbps, CL=2.5
100MHz/200Mbps, CL=2
31.75 (1.25")
31.75 (1.25")
31.75 (1.25")
31.75 (1.25")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR BD4
6.35
(0.250)
MAX.
67.56
(2.666) MAX
3.98 0.1
(0.157 0.004)
31.75
(1.25)
20
(0.787)
2.31
(0.091) REF.
3.99
(0.157) MIN.
4.19
(0.165)
47.40
(1.866)
0.99 0.10
(0.039 0.004)
1.80
(0.071)
11.40
(0.449)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
January 2005
Rev. 3
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG7264S-AD4
-BD4
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR AD4
Part Number
Speed
Height*
W3EG7264S335AD4
W3EG7264S262AD4
W3EG7264S265AD4
W3EG7264S202AD4
166MHz/333Mbps, CL=2.5
133MHz/266Mbps, CL=2
133MHz/266Mbps, CL=2.5
100MHz/200Mbps, CL=2
35.05 (1.38")
35.05 (1.38")
35.05 (1.38")
35.05 (1.38")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR AD4
67.56
(2.664 MAX.
6.35
(0 .2504
MAX.
2.0
(0.0794
3.98 0.1
(0.157 0.00ꢀ4
35.05
(1.384 MAX.
20
(0.7874
P1
2.31
(0.0914 REF.
3.98
(0.1574 MIN.
ꢀ.19
(0.1654
ꢀ7.ꢀ0
(1.8664
1.80
(0.0714
1.0 0.1
(0.039 0.00ꢀ4
11.ꢀ0
(0.ꢀꢀ94
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
January 2005
Rev. 3
12
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG7264S-AD4
-BD4
White Electronic Designs
PRELIMINARY
Document Title
512MB – 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL
Revision History
Rev #
History
Release Date Status
Rev 0
Rev 1
Created
8-1-03
6-04
Advanced
1.1 Added “BD4” package option
Preliminary
1.2 Updated CAP and IDD specs
1.3 Removed “ED” from part number
1.4 Changed datasheet from Advanced to Preliminary
Rev 2
Rev 3
2.1 Added AC Specs
10-04
1-05
Preliminary
Preliminary
3.1 Added lead-free and RoHS notes
3.2 Added source control notes
3.2 Added industrial temperature option
January 2005
Rev. 3
13
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
相关型号：
©2020 ICPDF网 联系我们和版权申明