MT8920BP1_技术文档

MT8920B

ST-BUS Parallel Access Circuit

Data Sheet

August 2005

Features

•

High speed parallel access to the serial

ST-BUS

Ordering Information

•

Parallel bus optimized for 68000 µP (mode 1)

Fast dual-port RAM access (mode 2)

Access time: 120 nsec

MT8920BE

MT8920BP

MT8920BS

MT8920BE1

MT8920BP1

MT8920BS1

28 Pin PDIP

28 Pin PLCC

28 Pin SOIC

28 Pin PDIP*

28 Pin PLCC*

28 Pin SOIC*

Tubes

•

Parallel bus controller (mode 3) - no external

Tubes

controller required

Tubes

Flexible interrupt capabilities - two

independent/programmable interrupt sources

with auto-vectoring

Tubes

MT8920BPR1 28 Pin PLCC*

*PB Free Matte Tin

Tape & Reel

•

Selectable 24 and 32 channel operation

Programmable loop-around modes

Low power CMOS technology

-40°C to 85°C

Description

Applications

The ST-BUS Parallel Access Circuit (STPA) provides

a simple interface between Zarlink’s ST-BUS and

parallel system environments.

•

Parallel control/data access to T1/CEPT digital

trunk interfaces

•

Digital signal processor interface to ST-BUS

Computer to Digital PABX link

Voice store and forward systems

Interprocessor communications

Tx0

Parallel-

D7-D0

Dual Port Ram

32 X 8

to-serial

STo0

STi0

Converter

A4-A0

Rx0

Dual Port Ram

32 X 8

Serial-to-

Parallel

CS

DS, OE

Converter

Parallel

Port

R/W, WE

Interface

Tx1

Dual Port Ram

32 X 8

Parallel-

to-Serial

Converter

DTACK,

BUSY, DCS

STo1

Interrupt

Registers

IRQ, 24/32

Comp/

MUX

Control

Registers

IACK, MS1

A5, STCH

MMS

F0i

C4i

Address

Generator

V_SS

V_DD

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

1

MT8920B

Data Sheet

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

C4i

F0i

VDD

MMS

IACK, MS1

STi0

3

4

5

DTACK, BUSY, DCS

IRQ, 24/32

STo1

STo0

D7

•

CS

IRQ, 24/32

5

25

24

23

22

21

20

19

CS

DS, OE

R/W, WE

A0

STo1

STo0

D7

6

7

6

DS, OE

7

R/W, WE

8

D6

8

A0

9

D6

A1

A2

A3

A1

D5

9

10

11

D5

A2

D4

10

11

12

13

14

D4

A3

D3

A4

D2

A5, STCH

VSS

D1

D0

28 PIN PDIP/SOIC

28 PIN J-LEAD

Figure 2 - Pin Connections

Description^‡

Pin Description

Pin # Name

1

C4i

4.096 MHz Clock. The ST-BUS timing clock used to establish bit cell boundaries for the serial

bus.

2

F0i

Framing Pulse. A low going pulse used to synchronize the STPA to the 2048 kbit/s ST-BUS

stream. The first falling edge of C4i subsequent to the falling edge of F0i identifies the start of

a frame.

3

IACK Interrupt Acknowledge (Mode 1). This active low input signals that the current bus cycle is

an interrupt vector fetch cycle. Upon receiving this acknowledgement, the STPA will

output a user-programmed vector number on D₀- D₇indicating the source of the interrupt.

MS1 Mode Select 1 (Mode 2,3). This input is used to select the device operating modes. A low

applied to this pin will select mode 3 while a high will select mode 2. (Refer to Table 1.)

4

5

6

STi0 ST-BUS Input 0. This is the input for the 2048 kbit/s ST-BUS serial data stream.

CS

DS

Chip Select. This active low input is used to select the STPA for a parallel access .

Data Strobe (Mode 1). This active low input indicates to the STPA that valid data is on the data

bus during a write operation or that the STPA must output valid data on the data bus during a

read operation.

OE

Output Enable (Mode 2). This active low input enables the data bus driver outputs.

Output Enable (Mode 3). This active low output indicates that the selected device is to be

read and that the data bus is available for data transfer.

7

R/W Read/Write (Mode 1,2). This input defines the data bus transfer as a read (R/W = 1) or a write

(R/W= 0) cycle.

WE Write Enable (Mode 3). This active low output indicates the data on the data bus is to be

written into the selected location of an external device.

8-12 A0-A4 Address Bus (Mode 1,2). These inputs are used to select the internal registers and two-port

memories of the STPA.

A0-A4 Address Bus (Mode 3). These address outputs are generated by the STPA and reflect the

position in internal RAM where the information will be fetched from or stored in. Addresses

generated in this mode are used to access external devices for direct memory transfer.

2

Data Sheet

MT8920B

Pin Description (continued)

Pin # Name

Description^‡

13

A5

Address Bit A5 (Mode 1). This input is used to extend the address range of the STPA. A5

selects internal registers when high and Tx/Rx RAM’s when low.

A5

Address Bit A5 (Mode 2). This input is used to extend the address range of the STPA. A5

selects Tx0/Rx0 RAM’s when low and Tx1/Rx0 RAM’s when high.

STCH Start of Channel (Mode 3). This signal is a low going pulse which indicates the start of an

ST-BUS channel. The pulse is four bits wide and begins at the start of each valid channel.

14

V_SSGround.

15-22 D0-D7 Bidirectional Data Bus. This bus is used to transfer data to or from the STPA during a write

or read operation.

23

24

STo0 ST-BUS Output 0. This output supplies the output ST-BUS 2048 kbit/s serial data stream from

Tx0 two-port RAM.

STo1 ST-BUS Output 1. In modes 1 and 2 this output supplies the output ST-BUS 2048 kbit/s serial

data stream from Tx1 two-port RAM. In mode 3, information arriving at STi0 is output here with

one frame delay.

25

IRQ Interrupt Request (Mode 1). This open drain output, when low, indicates when an interrupt

condition has been raised within the STPA.

24/32 24 Channel/32 Channel Select (Mode 2,3). This input is used to select the channel

configuration in modes 2 and 3. A low applied to this pin will select a 24 (T1) channel mode

while a high will select a 32 (CEPT) channel mode.

26

DTACK Data Transfer Acknowledge (Mode 1). This open drain output is supplied by the STPA to

acknowledge the completion of data transfers back to the µP. On a read of the STPA, DTACK

low indicates that the STPA has put valid data on the data bus. On a write, DTACK low

indicates that the STPA has completed latching the µP’s data from the data bus.

BUSY BUSY (Mode 2). This open drain output signals that the controller and the ST-BUS are

accessing the same location in the dual-port RAM’s. It is intended to delay the controller

access until after the ST-BUS completes its access.

DCS Delayed Chip Select (Mode 3). This low going pulse, which is four bit cells long, is active

during the last half of a valid channel. This signal is used to daisy-chain together two STPA’s in

mode 3 that are accessing devices on the same parallel data bus.

27

28

MMS Master Mode Select (Reset). This Schmitt trigger input selects between either mode 1 (MMS

= 1), or modes 2and 3 (MMS = 0). If MMS is pulsed low in Mode 1 operation the control and

interrupt registers will be reset. (Refer to Table 1.) During power-up, the time constant of the

reset circuit (see Fig. 8) must be a minimum of five times the rise time of the power supply.

V_DDPower Supply Input. (+5V).

‡ Pin Descriptions pertain to all modes unless otherwise stated.

Mode of

Mode MMS MS1

Operation

Function

1

N/A

µP

The STPA provides parallel-to-serial and serial-to-parallel conversions through a

Peripheral 68000-type interface. Two Tx RAMs and one Rx RAM are available along with full

Mode

interrupt capability. 32 channel or 24 channel support is available. Control Register 1, bit

D₅(RAMCON) = 0 for 32 channel operation and D₅(RAMCON)= 1 for 24 channel

operation.

2

3

0

1

0

Fast RAM The STPA provides a fast access interface to Tx0, Tx1 and Rx0 RAMs. This mode is

Mode

intended for full parallel support of 24 channel T1/ESF trunks and 32 channel CEPT

trunks. Input 24/32 (pin 25) = 0 for 24 channel operation, input 24/32 (pin 25) = 1 for 32

channel operation.

Bus

The STPA will synchronously drive the parallel bus using the address generator and

Controller provide all data transfer signals. This mode is intended to support 24 or 32 channel

Mode

devices in the absence of a parallel bus controller. Input 24/32 (pin 25) = 0 for 24 channel

operation, input 24/32 (pin 25) = 1 for 32 channel operation.

Table 1. STPA Modes of Operation

3

MT8920B

Data Sheet

and control busses are used to communicate

between the RAM‘s and a parallel environment.

Functional Description

The STPA (ST-BUS Parallel Access) device provides

a simple interface between Zarlink’s ST-BUS and

parallel system environments. The ST-BUS is a

synchronous, time division, multiplexed serial

bussing scheme with data streams operating at 2048

kbit/s. The ST-BUS is the primary means of access

for voice, data and control information to Zarlink’s

family of digital telecommunications components,

including North American and European digital trunk

interfaces, ISDN U and S digital line interfaces, filter

codecs, rate adapters, etc. The STPA provides

several modes of operation optimized according to

the type of information being handled.

Two

parallel-to-serial

converters,

and

one

serial-to-parallel converter interface the dual port

RAM’s to the ST-BUS port of the STPA. This port

consists of two serial output streams and one serial

input stream operating at 2048 kbit/s.

This

configuration of two outputs and one input was

designed to allow a single STPA to form a complete

control interface to Zarlink’s digital trunk interfaces

(MT8976, MT8978 and MT8979) which have two

serial input and one serial output control streams.

ST-BUS clocking circuitry, address generator and

various control and interrupt registers complete the

STPA’s functionality.

For interfacing parallel data and control information

to the ST-BUS, such as signalling and link control for

digital trunks, the STPA provides a µP access mode

(Mode 1), and looks like a 68000 type peripheral. In

this mode, the device provides powerful interrupt

features, useful in monitoring digital trunk or line

status (i.e., synchronization, alarms, etc.) or for

setting up message communication links between

microprocessors.

Modes of Operation

The three basic modes of operation, µP Peripheral

Mode (Mode 1), Fast RAM Mode (Mode 2) and Bus

Controller Mode (Mode 3) are selected using two

external input pins. These inputs are MMS and MS1

and are decoded as shown in Table 1. Whenever

MMS=1 the device resides in Mode 1. In this mode,

MS1 pin is unavailable and is used for a different

function.

To interface high speed data or multi-channel voice/

data to the ST-BUS for switching or transmission, the

STPA has a high speed synchronous access mode

(Mode 2) and acts like a fast RAM. For voice storage

and forward, bulk data transfer, data buffering and

When MMS=0, Modes 2 or 3 are selected as

determined by input MS1. If MS1=1, Mode 2 is

selected and if MS1 =0, Mode 3 is selected.

other similar applications, the STPA has

a

controllerless mode (Mode 3) in which it provides

address and control signals to the parallel bus This

is useful for performing direct transfers to the

ST-BUS from external devices such as a RAM buffer.

Each of the modes of the STPA provides a different

pinout to ease interfacing requirements of different

parallel environments. These are shown in Figure 3

below. In µP Peripheral Mode the device uses

interface signals consistent with a 68000-type µP

bus. Mode 2, Fast RAM Mode, uses signals typical

of standard RAM type interfaces. Mode 3 interface

signals are very similiar to Mode 2 signals except

that the address and control signals are supplied as

outputs by the STPA.

The STPA is a two port device as shown in the

functional block diagram in Figure 1. The parallel

port provides direct access to three dual port RAM’s,

two transmit and one receive. The address, data

µP Peripheral Mode #1

Fast RAM Mode #2

Bus Controller Mode #3

28

27

26

25

24

23

22

21

20

19

18

17

16

15

28

27

26

25

24

23

22

21

20

19

18

17

16

15

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

1

2

1

2

C4i

F0i

VDD

MMS

DTACK

IRQ

STo1

STo0

D7

C4i

F0i

VDD

MMS

BUSY

24/32

STo1

STo0

D7

C4i

F0i

VDD

MMS

DCS

24/32

STo1

STo0

D7

IACK

STi0

CS

3

4

5

MS1

STi0

CS

3

4

5

MS1

STi0

CS

3

4

5

DS

OE

R/W

A0

OE

6

7

6

7

6

7

R/W

A0

WE

A0

D6

8

A1

D5

9

A2

D4

10

11

12

13

14

10

11

12

13

14

10

11

12

13

14

A3

D3

A4

D2

A5

STCH

VSS

D1

VSS

D0

Figure 3 - Modes 1, 2, 3 Pin Connections

4

Data Sheet

MT8920B

24/32 Channel Operation

lessened since ST-BUS accesses require only the

last half cycle of C4i of every channel. When

contention does occur, priority is always given to the

ST-BUS access.

The STPA may be configured to operate as a 32

channel or 24 channel device. This feature, which is

available in all three modes of operation, is

particularly useful in applications involving data

access to CEPT and T1 digital trunk interfaces.

The STPA indicates this contention situation in a

different manner for Modes 1 and 2. In Mode 1, the

contention is masked by virtue of the "handshaking"

method used to transfer data on this 68000-type

When used as a data interface to Zarlink‘s CEPT

digital trunks, the STPA maps the 32 consecutive

bytes of each dual port memory directly to ST-BUS

channels 0-31. This is performed by the address

generator shown in the functional block diagram (see

Figure 1). Figures 4 c & d show the relationship

between relative dual port RAM locations and

corresponding ST-BUS channels, for both input and

output serial streams, when the STPA is configured

as a 32 channel device.

interface.

Data Strobe (DS) and Data Transfer

Acknowledge (DTACK) control the exchange. If

contention should occur the device will delay

returning DTACK and thus stretch the bus cycle until

the µP access can be completed.

In Mode 2, if access is attempted during a

"contention window" the STPA will supply the

BUSY signal to delay the start of the bus cycle. This

“contention window” is defined as shown in Figure

16. The window exists during the last cycle of C4i

clock in each channel timeslot. Although ST-BUS

access is only required during the last half of this

clock period, the “contention window“ exists for the

entire clock period since a parallel access occurring

just prior to an ST-BUS access will not complete

before the ST-BUS access begins. Figure 16 further

shows four possible situations that may occur when

parallel accesses are attempted in and around the

“contention window”. Condition 1 indicates that an

access occurring prior to the contention window but

lasting into the first half of it will complete normally

with no contention arbitration. If the access should

extend past the first half of the contention window

and into the ST-BUS access period, the BUSY signal

will be generated. Conditions 3 and 4 show accesses

When used as a data interface to Zarlink’s T1 trunk

devices, however, only the first 24 consecutive RAM

locations are mapped to 24 of the 32 ST-BUS

channels. This mapping follows a specific pattern

which corresponds with the data streams used by

Zarlink‘s T1 products. Instead of a direct correlation

(as in 32 channel operation), the 24 consecutive

RAM locations are mapped to the ST-BUS with every

fourth channel, beginning at channel 0, set to FF₁₆

(ie. channel 0, 4, 8, 12, 16, 20, 24 and 28). Figures

4 a & b show the relationship between RAM

locations and ST-BUS channel configuration. This

feature allows the STPA to be interfaced directly to

Zarlink’s T1 trunk family.

When the STPA is operated in Mode 1, 24 and 32

channel configurations are selected using bit D₅

(RAMCON) in Control Register 1. D₅= 0 selects 32

channel operation and D₅= 1 selects 24 channel

operation. When the STPA is operated in Modes 2

or 3, however, the channel configuration is done

using input 24/32 (pin 25). When 24/32 = 1 the

device uses all 32 channels and when 24/32 = 0 it

uses 24.

occurring inside

the contention window. These

accesses will result in BUSY becoming active

immediately after the access is initiated and

remaining active as shown in Figure 16.

Access contention is non-existent in Mode 3 since

the parallel bus signals, driven by the STPA, are

synchronized to the ST-BUS clocks.

Mode 1 - µP Peripheral Mode

Dual Port RAMS

In Mode 1, the STPA operates as an asynchronous

68000-type microprocessor peripheral. All three

dual-port RAMS (Tx0, Tx1, Rx0) are made available

and may be configured as 32 or 24 byte RAM’s. Also

available are the full complement of control and

interrupt registers. The address map for Mode 1 is

shown in Table 2.

Each of the three serial ST-BUS streams is

interfaced to the parallel bus through a 32 byte dual

port RAM. This allows parallel bus accesses to be

performed asynchronously while accesses at the

ST-BUS port are synchronous with ST-BUS clock.

As with any dual port RAM interface between two

asynchronous systems, the possibility of access

contention exists. The STPA minimizes this

occurrence by recognizing contention only when

accesses are performed at the same time for the

same 8-bit cell within the dual port RAM’s.

Furthermore, the probability of contention is

The STPA, in Mode 1, uses signals CS, R/W, DS

(Data Strobe), DTACK (Data Acknowledge) IRQ, and

IACK (Interrupt Acknowledge) at the parallel interface.

The pinout of the device is shown in Figure 3.

5

MT8920B

Data Sheet

6

Data Sheet

MT8920B

ADDRESS BITS

REGISTERS

A₆

A₅

A₄

A₃

A₂

A₁

A₀

READ

WRITE

0

•

0

•

0

•

0

•

0

•

0

•

0

•

Rx0 - Channel 0

Tx0 - Channel 0

•

0

1

Rx0 - Channel 31

Tx0 - Channel 31

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Control Register 1

Control Register 2

Interrupt Vector Register

Interrupt Flag Register 1

Interrupt Flag Register 2

Image Register 1

Control Register 1

Control Register 2

Interrupt Vector Register

-

Image Register 2

Interrupt Mask Register 1

Interrupt Mask Register 2

Match Byte Register 1

Match Byte Register 2

Interrupt Channel Address 1

Interrupt Channel Address 2

Interrupt Mask Register 1

Interrupt Mask Register 2

Match Byte Register 1

Match Byte Register 2

Interrupt Channel Address 1

Interrupt Channel Address 2

1

•

0

•

0

•

0

•

0

•

0

•

0

•

Rx0 - Channel 0

Tx1 - Channel 0

•

1

0

1

Rx0 - Channel 31

Tx1 - Channel 31

Table 2. Mode 1 Address Map

NOTES:

X is don’t care

A₆is bit D₄of Control Register 1

Bit

Name

Description

7

6

(Unused)

IRQRST

Interrupt Reset. This bit, when set high, automatically clears the Interrupt Flag Register

and the Interrupt Image Register without these registers being serviced. This bit

automatically resets to zero after the register clear is completed.

5

RAMCON

A₆

RAM Configuration. This bit configures Tx0, Tx1 and Rx0 RAMS for 32 or 24 byte

operation. D₅= 0 for 32 channel; D₅= 1 for 24 channel.

4

3

Address Bit A6. This bit extends the addressing range for access to Tx1 memory.

IRQ2MODE Interrupt Source 2 Mode Select. This bit configures the source 2 interrupt generator.

D₃= 0 selects “static” interrupt mode; D₃= 1 selects “dynamic” interrupt mode.

2

IRQ1MODE Interrupt Source 1 Mode Select. This bit configures the source 1 interrupt generator.

D₂= 0 selects “static” interrupt mode; D₂= 1 selects “dynamic” interrupt mode.

1

0

IRQ2EN

IRQ1EN

Interrupt Source 2 Enable. IRQ2EN = 1 enables interrupts to occur from source 2.

Interrupt Source 1 Enable. IRQ1EN = 1 enables interrupts to occur from source 1.

Table 3. Control Register 1 Bit Definitions

7

MT8920B

Data Sheet

Timing information for data transfers on this interface

is shown in Figure 14. The Mode 1 interface is

designed to operate directly with a 68000-type

asynchronous bus but can easily accommodate most

other popular microprocessors as well.

a and b. Figure 6 c shows the effect of combining

these two features.

Interrupt Registers

Interrupts can be generated in Mode 1 only. Two

channels of the ST-BUS input stream, STi0, can be

selected to provide an interrupt to the system.

Interrupts can be of two types: Static or Dynamic.

Static interrupts are caused when data within a

selected channel matches a given pattern. Dynamic

interrupts occur when bits in a selected channel

change state (1 to 0, 0 to 1 or toggle). Interrupts are

controlled through two identical paths (1 and 2)

consisting of the following registers:

Control Registers

Two control registers allow control of Mode 1

features. Control Register 1 provides bits to select

the type of interrupt, to enable interrupts from two

different and independent sources and to reset the

interrupt registers.

Also contained in Control

Register 1 are bits to configure the device for 24 or

32 channel operation and to expand the address

range for convenient access to the second transmit

RAM Tx1. A description of the bit functions in

Control Register 1 is shown in Table 3.

Interrupt Channel Address (1/2): The address

(0-31) of the channel which will generate the

interrupt is stored in this register.

Mode 1 provides various loopback paths and output

configuration options which are controlled by bits in

Control Register 2. Bits D₀, D₁of Control Register 2

configure loopbacks using input and output streams

STi0, STo0 as described in Table 4. The input

stream STi0 can be looped back to source the output

stream STo0 as well as receive RAM Rx0. The

transmit RAM Tx0 can be looped to source the

receive RAM Rx0, as well as STo0 and, the transmit

RAM Tx0 can be looped to the receive RAM Rx0

while STi0 sources STo0. The function of these

loopback configurations is shown in Figure 5.

Image Register (1/2):

The contents of the

channel causing the interrupt is stored in this

register. Reading this register will clear its contents.

Match Byte Register (1/2):

In static mode this

register is used to store the byte which will be

compared with the contents of the selected channel

causing the interrupt.

In dynamic mode, the bits in this register and the

corresponding bit in the Interrupt Mask Register

define the type of dynamic interrupt (i.e., 0 to 1, 1 to

0, toggle). (Refer to Table 5.)

In a similar way, the output STo1 can be reconfigured

for different functionality. Bits D₂and D₃of Control

Register 2 allow STo1 to be sourced, with a one

frame delay via Tx1 from receive stream STi0. STo1

can also output the result of a comparison of the

contents of Tx1 ram with input stream STi0. These

output configurations of STo1 are shown in Figure 6

Bit

Name

Description

7-4

3-2

(Unused)

CONFIG

STo1 Output Configuration Bits:

D₃D₂= 00-

Normal operation. ST-BUS stream from Tx1 is output on STo1 pin.

STi0 stream is output on STo1 pin delayed one frame (Figure 6 a).

STi0 is compared through XOR (exclusive OR) with ST-BUS stream

from Tx1 and output at STo1 (Figure 6 b).

01-

10-

11-

STi0 stream, delayed one frame (via Tx1), is compared (XOR) with the

next frame arriving at STi0 and the result output at STo1 (Figure 6 c).

1-0

LOOPBACK Internal Loopback Configuration Bits:

D₁D₀= 00-

Normal operation. No internal loops.

01-

10-

Loop STi0 to STo0 while still receiving STi0 in Rx0 (Figure 5 a).

Loop Tx0 output ST-BUS stream to Rx0 input ST-BUS stream while

outputting Tx0 output to STo0. STi0 is not received (Figure 5 b).

Loop Tx0 output ST-BUS stream to Rx0 input ST-BUS stream. Loop

STi0 to STo0 (Figure 5 c).

11-

Table 4. Control Register 2 Bit Definitions

8

Data Sheet

MT8920B

Control Register 2

Bits D₃= 0, D₂= 1

Control Register 2

Bits D₁= 0, D₀= 1

Tx0

STo0

STi0

µP

STo0

STi0

Rx0

Tx1

µP

Rx0

STo1

1 Frame Delay

a)

Control Register 2

Bits D₃= 1, D₂= 0

Control Register 2

Bits D₁= 1, D₀= 0

Tx0

STo0

STi0

µP

Tx0

Rx0

STo0

Rx0

Tx1

µP

STi0

STo1

b)

Control Register 2

Bits D₃= 1, D₂= 1

Control Register 2

Bits D₁= 1, D₀= 1

Tx0

STo0

STi0

µP

STo0

STi0

Tx0

Rx0

Tx1

µP

STo1

1 Frame Delay

c)

Figure 5 - Loopback Configurations

Figure 6 - STo1 Configurations

Interrupt Mask Register (1/2): In static mode the

contents of this register masks bits in the Match Byte

Register that are ’don’t care’ bits

Interrupt Vector Register

This register shown in Figure 7 is common to both

interrupt paths and stores an 8 bit vector number

which will be output on the data bus when

Interrupt Acknowledge (IACK) is asserted. Bits

labelled V₂- V₇are stored by the controlling µP.

Bits IRQ1 and IRQ2 are set by the STPA to indicate

which path caused the interrupt. This creates unique

vectors which are used by the µP to vector to

interrupt service routines. This feature may be

bypassed by simply not asserting IACK during

interrupt acknowledged.

1 - bit masked

0 - bit not masked

In dynamic mode, each bit in this register and the

corresponding bit in the Match Byte Register define

what type of dynamic interrupt is selected. (Refer to

Table 5.)

Interrupt Flag Register (1/2):

In static mode

the least significant bit in this register is set to 1 to

flag the corresponding path in which the interrupt

occurs.

D7

V₇

D6

V₆

D5

V₅

D4

V₄

D3

V₃

D2

V₂

D1

D0

In dynamic mode this register sets the bits which

reflect the position of the bits in the corresponding

Interrupt Register which caused the interrupt.

IRQ2 IRQ1

Figure 7 - Interrupt Vector Registers

9

MT8920B

Data Sheet

Interrupt Modes and Servicing

D₇D₆D₅D₄D₃D₂D₁D₀

Channel Address Register 1 =

0

1

0

Static Interrupt Mode

(channel 4 of STi0 selected)

A static interrupt is caused when an incoming byte

matches a predefined byte. The incoming byte from

a selected channel is stored in Interrupt Image

Register (1/2) where it is compared with the contents

of the corresponding Match Byte Register. The

result of the comparison of individual bits is masked

by the contents of the Mask Register (1/2) before it

is used to generate an IRQ. After a static interrupt

occurs, information in the Interrupt Image Register is

frozen until the µP performs a read operation on this

register.

Match Byte Register 1 =

0

1

0

Interrupt Mask Register 1 =

(When bit D₃toggles 0 to 1)

Dynamic interrupts from interrupt path 1 would then

be enabled using the Control Register 1.

Control Register 1 =

0

1

0

1

This would cause interrupt 1 path to be enabled

while interrupt 2 path is disabled.

When servicing static interrupts assertion of IACK

will cause the contents of the Vector Register, with

the IRQ1 or IRQ2 bit set, to be output on the data

bus. The service routine can subsequently clear IRQ

by reading the Interrupt Image Register.

Alternatively, the IRQRST bit in Control Register 1

can be set to clear the associated interrupt registers.

As with static interrupts, upon serving a dynamic

interrupt, assertion of IACK will cause the contents

of the Vector Register, with the appropriate path bit

set, to be output on the data bus. The information

contained in the channel is frozen in the Interrupt

Image Register.

To clear a dynamic interrupt,

however, the µP must read the Interrupt Flag

Register of the path responsible for the interrupt to

determine which bit caused the interrupt. The bit in

the corresponding position will be set to 1 and

reading this register will clear its contents.

Static Interrupts are selected using IRQ1MODE and

IRQ2MODE bits in Control Register 1. Interrupts are

then enabled to the IRQ pin with IRQ1EN and

IRQ2EN bits of the same register.

Alternatively, as with static interrupts, the IRQRST bit

in Control Register 1 can be set to clear the Image

Interrupt Register, Flag Register and path bits in the

Vector Register.

Dynamic Interrupt Mode

A dynamic interrupt is generated by a change of

state of bits in a selected channel. A 0 to 1 transition

or a 1 to 0 transition or a simple change of state from

the previous state (toggle) can be detected. The

type of transition to be detected is selected using two

bits, one from the Match Byte Register (1/2) and one

from the Interrupt Mask Register (1/2), in the

corresponding bit positions. Table 5 shows how the

two registers are programmed.

Dynamic Interrupts are selected using IRQ1MODE

and IRQ2MODE bits in Control Register 1 and are

enabled using IRQ1EN and IRQ2EN in the same

register.

MMS Pin Reset

The STPA can be RESET in Mode 1 using the MMS

pin (27). Applying a low pulse (0V) to MMS after

power is applied to the device will reset all control

Match

Byte

Mask

Byte

Transition Type Detected

on Incoming bit D_X

(x = 0 ....7)

and interrupt registers to 00₁₆.

This can be

accomplished on power up with a simple R-C circuit

as shown in Figure 8.

Register Register

bit D_X

0

1

0

1

0

1

Mask Bit D_X

0 to 1 transition

1 to 0 transition

Toggle

V_DD

R

Table 5 - Dynamic Interrupt Types

STPA

MMS

27

For example, the following steps are required to

generate an interrupt when bit D₃of channel 4

changes state from 0 to 1 (all other bits are masked):

C

Figure 8 - MMS Reset Function

10

Data Sheet

MT8920B

reads and writes with framing and channel boundary

information.

Mode 2 - Fast RAM Mode

Mode 2 operates as a high speed dual port RAM

interface to the ST-BUS. Only the two transmit

RAM’s, Tx0 and Tx1, and the receive RAM, Rx0 are

active in this mode (i.e., control registers and

interrupt registers are inactive).

Mode 3 - Parallel Bus Controller

In this mode the STPA outputs all necessary signals

required to drive devices attached to the parallel

port. The STPA can be used to drive devices such

as RAM’s, FIFO’s, latches, A/D and D/A converters,

and CODECS, directly from the ST-BUS without an

intervening µP. As with the other modes, Mode 3

can operate from 32 channels or 24 channels by

connecting 24/32 high or low, respectively. This

allows devices to be driven remotely via a T1 or

CEPT digital trunk link when used with Zarlink’s trunk

products.

The main feature of this mode is fast access to the

dual-port RAM’s. Fast access allows high-speed

controllers to use this device as a data interface to

T1 and CEPT digital links. Timing information is

shown in Figure 15.

Mode 2 can also support 24 channel and 32 channel

operation. The channel configuration is selected

using 24/32 pin. When 24/32=0 the device operates

in 24 channel mode and when 24/32=1, it operates in

32 channel mode.

Referring to Figure 1, the Address Generator block

generates and drives the external address lines

A4-A0. The STPA also generates OE (output

enable) and WE (write enable) to facilitate data

transfers from Rx0 RAM and to Tx0 RAM. Tx1 RAM

is unavailable in this mode.

The physical interface in this mode resembles that of

a simple RAM device. The signals used to read

and write the device are CS, OE, R/W. The pinout of

the STPA in this mode is shown in Figure 3. Address

decoding for Tx0, Tx1, Rx0 is shown in Table 6.

The STPA, in Mode 3, generates external addresses

in a particular sequence that minimizes throughput

delay through the device. When channel N is

present on the ST-BUS, the STPA generates

address N+1 on the address bus and asserts OE

to output data from an external device and latch it

into the STPA. During the same channel N, the

STPA will generate address N-1 with WE asserted

to write from the STPA to an external device. Timing

for Mode 3 transfers is shown in Figure 17. All

parallel bus signals are synchronized to the ST- BUS

clock.

Contention can arise for access to the dual port

RAMS. The occurrence of this is minimized since

the ST-BUS serial-to-parallel and parallel-to-serial

converters require RAM access for only 1/32 of

a channel time (i.e., last half cycle of C4i for

each channel). For contention to occur the high

speed controller must access the same RAM

location as that of the ST-BUS. For a parallel read

operation this corresponds to the current ST-BUS

channel and for a write operation, the next ST-BUS

channel. Access contention in Mode 2 is arbitrated

with the BUSY signal. BUSY is intended to hold

off any parallel access cycle until it again goes

inactive. Figure 16 shows how the access is

arbitrated for accesses near the contention window.

The device must be selected using CS in order for

the parallel bus drivers to be enabled. CS should

remain active for four ST-BUS bit periods (8 x C4i

cycles) since a read and a write operation require 2

bit periods each. The STPA generates a signal STCH

(start of channel) which becomes active at the start

of each channel and remains active for 1/2 of the

channel time (Figure 18). This signal may be

Applications using high speed access can easily

avoid generating BUSY by co-ordinating channel

ADDRESS BITS

REGISTERS

A₅

A₄

A₃

A₂

A₁

A₀

READ

WRITE

0

Rx0 - Channel 0

Tx0 - Channel 0

•

0

1

Rx0 - Channel 31

Tx0 - Channel 31

1

•

0

•

0

•

0

•

0

•

0

•

Rx0 - Channel 0

Tx1 - Channel 0

•

1

Rx0 - Channel 31

Tx1 - Channel 31

Table 6. Mode 2 Address Map

11

MT8920B

Data Sheet

connected directly to CS to enable the device

appropriately.

connected on a common bus, to be driven by two

ST-BUS streams. Figure 9 shows how this "daisy

chaining" of STPA’s is implemented while Figure 10

illustrates the timing on the shared parallel bus.

Common Bus

CS

STCH

Applications

OE

WE

STi0

A0

A1

A2

A3

A4

Parallel PBX to Digital Trunk Interface

STo0

The STPA is an ideal component for interfacing

parallel PBX environments to Zarlink’s family of

digital trunk devices.

MMS MS1 24/32

0

1

Figure 11 shows a typical interface for both T1/ESF

and CRC-4 CEPT digital trunks to a system utilizing

CS

DCS

OE

WE

a parallel bus architecture.

Both the MH89760B

STi0

T1/ESF and the MH89790B CRC-4 CEPT trunk

modules are shown interfaced to a parallel bus

structure using two STPAs operating in modes 1 and

2.

A0

A1

A2

A3

A4

STo0

MMS MS1 24/32

The first STPA operating in mode 2 (MMS=0,

MS1=1, 24/32=0), routes data and/or voice

information between the parallel telecom bus and the

T1 or CEPT link via DSTi and DSTo. The second

STPA, operating in mode 1 (MMS=1) provides

access from the signalling and link control bus to the

MH89760B or MH89790B status and control

channels. All signalling and link functions may be

controlled easily through the STPA transmit RAM’s

Tx0, Tx1, while status information is read at receive

RAM Rx0. In addition, interrupts can be set up to

notify the system in case of slips, loss of sync,

alarms, violations, etc.

0

1

Figure 9 - "Daisy-chained" STPA’s in 32 Channel

Parallel Bus Controller Mode (Mode 3)

In order to facilitate efficient use of the parallel bus

another signal, similar to STCH, is supplied by the

STPA. Delayed Chip Select (DCS) becomes active

for the last half of each channel (Figure 19). This

may be connected to a second STPA, residing on the

same physical parallel bus, enabling it to perform its

read/write operations in the second half of each

channel. This allows a large number of devices,

CHANNEL N

BIT 4

ST-BUS

C4i

BIT 7

BIT 6

BIT 5

BIT 3

BIT 2

BIT 1

BIT 0

Address

N + 1

N - 1

N + 1

N - 1

OE

WE

Data Bus

IN

OUT

IN

OUT

STCH

DCS

Figure 10 - Timing Relationship for Mode 3 Daisy Chaining

12

Data Sheet

MT8920B

13

MT8920B

Data Sheet

Digital Signal Processor to ST-BUS Interface

-

Digital Filtering

Voice Conferencing

Speech/Data Compression

Encryption

Mode 2 allows many high speed devices to be easily

connected to the ST-BUS. Figure 12 shows a

TMS32020 digital signal processor interfaced to the

ST-BUS through the STPA. This simple interface

allows complex functions to be implemented in such

systems as PBX’s and computer systems. Some of

the possible functions include:

Tone Detection and Generation

Frequency Spectrum Analysis

Image Processing

µ-Law to A-Law Conversion

Echo Cancellation

Modulation

Speech Synthesis and Recognition

74HCT

138

TMS32020

MT8920B

DS

E2

A9

A8

A7

A6

E1

A

B

C

CS

STo0

A8-A0

D7-D0

A5-A0

STi0

D7-D0

STo1

STRB

RW

OE

WE

MSC

READY

MMS MS1 24/32

+5V +5V

Figure 12 - ST-BUS to DSP Interface

14

Data Sheet

MT8920B

Connecting the STPA to a shared ST-BUS Line

a high impedance state at the output of U1,

corresponding to the selected channel.

The STPA’s STo0 and STo1 outputs cannot be

This method of three-state buffering permits output

control on a per-channel or per-bit basis.

directly forced into

a

high impedance state.

However, with some external logic, the STo0 output

can be buffered by a three-state device, controlled

by the STo1 output. This application is only possible

if the Tx1 RAM and associated STo1 output are not

required for some other purpose.

The ODE input is used to enable the ST-BUS outputs

after all ST-BUS devices are properly configured by

software.

This eliminates the possibility of

contention on the ST-BUS lines during the power-up

state.

Figure 13 shows an external buffer U1 controlled by

the STo1 output and an external Output Data Enable

(ODE) signal. When FF (hex) is written to the Tx1

RAM, the corresponding STo1 output channel goes

to logic high. This signal, AND-ed together with a

logic high at ODE, enables U1, resulting in the STo0

signal transparently passed to the output of U1.

When 00 (hex) is written to the Tx1 RAM, the STo1

output goes logic low. This disables U1, resulting in

74HC125

ST-BUS

STo0

U1

Parallel Port

MT8920B

74HC00

STo1

U2

ODE

STi0

STi1

STo0

STo1

MT8980

STi7

STo7

Parallel Port

Figure 13 - Connecting STPA to a Common ST-BUS Line

15

MT8920B

Data Sheet

Absolute Maximum Ratings* - Voltages are with respect to ground (V_SS) unless otherwise stated.

Parameter

Symbol

Min.

Max.

Units

1

2

3

4

5

Supply Voltage

V_DD

-0.3

7.0

V_DD+ 0.3

±25

V

Voltage on any I/O pin

Current on any I/O pin

Storage Temperature

I_I/O

T_ST

P_D

mA

°C

-55

125

Package Power Dissipation

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Plastic

600

mW

Recommended Operating Conditions - Voltages are with respect to ground (V_SS) unless otherwise stated.

Characteristics

Supply Voltage

Sym.

Min. Typ.^‡Max. Units

Test Conditions

1

2

3

4

5

V_DD

V_IH

V_IL

T_A

4.75

2.4

0

5.0

5.25

V_DD

0.4

V

Input High Voltage

for 400mV noise margin

Input Low Voltage

V

Operating Temperature

-40

25

85

°C

MHz

Operating Clock Frequency

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

f_CK

4.096

DC Electrical Characteristics - Voltages are with respect to ground (V_SS) unless otherwise stated.

Typ.

Characteristics

Sym.

Min.

Max. Units

Test Conditions

‡

1

Supply Current

Static

Dynamic

I_CCS

I_CCD

10

5

µA

outputs unloaded

10

mA

V

@f_CK= 4.096 MHz

2

3

4

Input High Voltage

Input Low Voltage

V_IH

V_IL

I_Z

2.0

0.8

V

Input Leakage Current

±10

µA

V_DD=5.25V,

V_IN=V_SSto V_DD

5

6

7

8

9

Input capacitance

C_IN

V_T+

V_T-

V_H

10

pF

V

Schmitt trigger input high (MMS)

Schmitt trigger input low (MMS)

Schmitt trigger hysteresis (MMS)

Output high current (except IRQ)

3.8

3.0

2.0

1.0

15

1.0

V

0.8

10

5

V

I_OH

I_OL

I_OZ

mA

µA

V_OH= 2.4V, V_DD= 4.75V

V_OL= 0.4V, V_DD= 4.75V

10 Output low current (except IRQ)

11 IRQ, DTACK, BUSY Sink Current

10

15

12 Tristate Leakage A₄-A₀, OE, WE

(mode 3)

±1

±10

±20

15

V_DD= 5.25V

V_OUT= V_SSto V_DD

13 Open drain off-state current

IRQ, DTACK, BUSY

I_OFF

C_O

±1

µA

V_DD= 5.25V

V_OUT= V_DD

14 Output capacitance

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

pF

16

Data Sheet

MT8920B

AC Electrical Characteristics^†- Mode 1 Parallel Bus Timing (see Fig. 14)

(V_CC=5.0V ±5%,T_A=-40 to 85°C)

Characteristics

Sym.

Min.

Typ.^‡

Max.

Units

Test Conditions

1

2

3

4

Address to DS (CS) Low^††

R/W to DS (CS) Low^††

DS (CS) Low to DTACK Low^††

t_ARDS

t_RWDS

0

ns

20

1,2

Load C

t_RDS

t_cwm

t_CLK

2*t_CLK

Load A, C_L=130pF, R_L=740Ω

Valid Data to DTACK Low (Read)

t_RD

t_cwm

-30

Load C, C_L=50pF

5

6

7

8

9

DS High to DTACK High

DS High to Data High Imped.(Read)

DS High to CS High

t_DAR

t_DHZ

t_CSH

t_DHT

t_DST

65

45

ns

Load A, C_L=130pF, R_L=740Ω

0

Data Hold Time (Write)

Input Data Valid after DS

t_cwm

-30

10 Address Hold Time^††

t_ADHT

50

ns

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C, V_DD=5V, t_CLK=244 ns, t_CH=t_CL=122 ns and are for design aid only: not guaranteed and not subject to production

testing.

††The cycle is initiated by the falling edge of CS or DS, whichever occurs last. Timing is relative to the last falling edge which initiates the cycle.

(1) t_cwmis equal to t_CHor t_CLwhichever is smaller (some ST-BUS compatible transceivers may generate C4 clock having t_CHmin=70ns

or t_CLmin=70ns.

(2) Worst case access when memory contention occurs.

A0 - A5

t_ADHT

CS (IACK^†)

t_ARDS

R/W

t_RWDS

t_CSH

DS

t_RDS

t_DAR

DTACK

D0 - D7

t_RD

t_DHZ

DATA OUT

t_DHT

t_DST

DATA IN

D0 - D7

Figure 14 - Mode 1 Parallel Bus Timing

† During Interrupt Acknowledge cycle IACK replaces CS. R/W must remain high.

17

MT8920B

Data Sheet

AC Electrical Characteristics^†- Mode 2 Parallel Bus Timing - (see Figures 15 and 16)

(V_CC=5.0V ±5%,T_A=-40 to 85°C)

Characteristics

Sym.

Min.

Typ.^‡Max. Units

Test Conditions

Load A, C_L=130pF, R_L=740Ω

Load A, C_L=130pF, R_L= 740Ω

Load A, C_L=130pF, R_L=740Ω

1

2

3

4

5

6

7

8

9

OE Low to Valid Data

Address Access Time

CS Low to Valid Data

Output Disable

t_EVD

t_AA

60

120

60

ns

t_CSD

t_OHZ

t_ASF

t_DST

t_DHT

t_AH

50

Address Setup Time

Data Setup Time

20

30

5

Data Hold Time

Address Hold Time

Write Pulse Width

50

t_WP

10 OE, R/W High to C4i High

11 OE, R/W Low to C4i Low

12 C4i High to Busy Low

t_EC4H

t_EC4L

t_C4BL

t_C4BH

t_EBL

-10

10

50

40

Load C

13 C4i Low to Busy High

14 OE, R/W High to Busy Low

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C, V_DD=5V, t_CLK=244 ns, t_CH=t_CL=122 ns and are for design aid only: not guaranteed and not subject to production

testing.

A0 - A5

t_AH

CS

t_ASF

OE

t_WP

R/W

t_OHZ

t_EVD

t_CSD

t_AA

t_DHT

t_DST

DATA OUT

DATA IN

D0 - D7

Figure 15 - Mode 2 Timing Diagram (No Contention)

18

Data Sheet

MT8920B

CHANNEL N - BIT 0

CHANNEL (N + 1) - BIT 7

ST-BUS ACCESS

CONTENTION WINDOW

C4i

(N matches incoming

ST-BUS channel)

A0 - A5

READ ADDRESS N or WRITE ADDRESS (N + 1)

CS

CONDITION 1:

Access begins before contention window and finishes before ST-BUS access - No contention.

OE, R/W

BUSY

t_EC4H

CONDITION 2:

Access begins before contention window and continues into ST-BUS access.

t_EC4L

OE, R/W

t_C4BL

t_C4BH

BUSY

Access begins within contention window but before ST-BUS access.

CONDITION 3:

OE, R/W

t_EC4L

t_C4BH

t_EBL

BUSY

CONDITION 4:

Access begins during ST-BUS access

OE, R/W

t_C4BH

t_EBL

BUSY

Figure 16 - Mode 2 Access Contention Resolution

19

MT8920B

Data Sheet

AC Electrical Characteristics^†- Mode 3 Timing (see Fig.17, 18 and 19)

((V_CC=5.0V ±5%,TA=-40 to 85°C)

Characteristics

Sym. Min. Typ.^‡

Max.

Units

Test Conditions

1

CS to OE, WE, Address

Enabled

t_ZR

50

ns

Load A, C_L= 130pF, R_L= 740Ω

2

3

C4i Low to Address Change t_ACS

110

ns

Load A, C_L= 130pF, R_L= 740Ω

CS to OE, WE, Address

Disabled

t_RZ

50

4

5

C4i Low to Output Enable

Low

t_OED

t_OEH

75

ns

Load A, C_L= 130pF, R_L= 740Ω

C4i Low to Output Enable

High

6

7

OE, WE, Pulse Width

t_ENPW

t_WED

2*t_CLK

ns

Load A, C_L= 130pF, R_L= 740Ω

C4i Low to Write Enable

Low

75

8

9

C4i Low to Write Enable

High

t_WEH

t_RST

ns

Load A, C_L= 130pF, R_L= 740Ω

Read Data Valid from OE

(2*t_CLK

-60

)

10 Read Data Hold Time

11 Write Data Setup Time

12 Write Data Hold Time

t_RHT

t_WST

t_WHT

t_STC

0

ns

70

100

Load A, C_L= 130pF, R_L= 740Ω

Load A, C_L= 70pF, R_L= 1.22KΩ

13 C4i Transition to STCH,

DCS Trans.

120

14 STCH Pulse Width

t_SCPW

t_CSPW

1830

ns

Load A, C_L= 70pF, R_L= 1.22KΩ

15 DCS Pulse Width

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C, V_DD=5V,t_CLK=244ns, t_CH=t_CL=122ns and are for design aid only: not guaranteed and not subject to production

testing.

20

Data Sheet

MT8920B

CHANNEL N

BIT 6 (BIT 2)

BIT 7 (BIT 3)

BIT 5 (BIT 1)

BIT 4 (BIT 0)

C4i

t_ACS

A4 - A0

N + 1

N - 1

t_OEH

t_OED

t_ENPW

OE

WE

t_WED

t_WEH

t_ENPW

t_RST

t_WST

t_WHT

t_RHT

D7 - D0

DATA IN

DATA OUT

t_RZ

t_ZR

CS

Figure 17 - Mode 3 Timing Diagram

CHANNEL N

CHANNEL N-1

BIT 0

BIT 7

BIT 6

BIT 5

BIT 4

C4i

STCH

t_STC

t_SCPW

Figure 18 - Mode 3 STCH Timing Diagram

21

MT8920B

Data Sheet

CHANNEL N

CHANNEL

N+1

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

C4i

STCH

DCS

t_STC

t_CSPW

Figure 19 - Mode 3 DCS Timing Diagram

22

Data Sheet

MT8920B

AC Electrical Characteristics^†- ST-BUS Timing (see Figure 20)

(V_CC= 5.0V ± 5%, T_A= -40 to 85°C)

Characteristics

Clock C4i Period

Sym. Min.

Typ.^‡

Max. Units

Test Conditions

1

2

3

4

5

6

7

8

9

t_CLK

244

122

ns

Clock C4i Period High

Clock C4i Period Low

C4i Rise Time

t_CH

t_CL

70

t_R

20

12

ns

C4i Fall Time

t_F

Frame Pulse Setup Time

Frame Pulse Hold Time

STo0/1 Delay from C4i

STi0 Setup Time

t_FPS

t_FPH

t_SOD

t_STS

t_STH

20

100

Load B

20

35

10 STi0 Hold Time

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C, V_DD=5V and are for design aid only: not guaranteed and not subject to production testing.

Bit Cell

t_CL

C4i

t_CLK

t_CH

t_R

t_F

t_FPS

t_FPH

F0i

t_SOD

STo0

STo1

t_STS

t_STH

STi0

Figure 20 - ST-BUS Timing Diagram

23

Data Sheet

MT8920B

125 µs

CHANNEL

31

CHANNEL

0

CHANNEL

30

CHANNEL

31

CHANNEL

0

(8/2.048) µs

Bit D₇

on

Data Bus

Bit D₀

on

Data Bus

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Figure 21 - Format of 2048 kbit/s ST-BUS Streams

2.0 V

INPUTS

0.8 V

2.0 V

0.8 V

OUTPUTS

Figure 22 - Waveform Test Point Reference

V_DD

R_L

500Ω

C_L=150pF

C_L

6.0k

C_L=130pF

IN4148

LOAD A

LOAD B

LOAD C

Figure 23 - Test Load Circuits

24


型号：	MT8920BP1
厂家：	Microsemi
描述：	Telecom Circuit, 1-Func, CMOS, PQCC28, LEAD FREE, PLASTIC, MS-018AB, LCC-28 电信电信集成电路
文件：	总28页 (文件大小：620K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT8920BP1 [MICROSEMI]

相关型号：

MT8920BPR

MT8920BPR1

MT8920BS

MT8920BS1

MT8920BS1

MT8924

MT8924-1

MT8924AE

MT8924AS

MT8924ASR

MT8926

MT8926AE