MAL6216FCXXX [MICROSEMI]
SRAM,;
| 型号： | MAL6216FCXXX |
| 厂家： | 
Microsemi |
| 描述： | SRAM, 静态存储器 |
| 文件： | 总13页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
MARCH 1995
DS3582-3.1
MA6116 & MA6216
RADIATION HARD 2048 x 8 BIT STATIC RAM
The MA6116 16k Static RAM is configured as 2048 x 8 bits and
FEATURES
manufactured using CMOS-SOS high performance, radiation hard,
3µmtechnology.TheMA6216ismanufacturedusing2.5µmtechnology
resulting in faster performance.
■ 3µm CMOS-SOS Technology
■ Latch-up Free
Thedesignusesa6transistorcellandhasfullstaticoperationwith
noclockortimingstroberequired.Addressinputbuffersaredeselected
when chip select is in the HIGH state.
■ Fast Access Time 110ns (MA6116) and 85ns
(MA6216) Typical
■ Total Dose 106 Rad(Si)
■ Transient Upset >1010 Rad(Si)/sec
■ SEU <10-10 Errors/bitday
■ Single 5V Supply
Operation Mode CS OE WE
I/O
Power
Read
Write
Write
L
L
L
L
H
L
H
L
L
D OUT
D IN
ISB1
ISB2
■ Three State Output
D IN
■ Low Standby Current 100µA Typical
■ -55°C to +125°C Operation
■ TTL and CMOS Compatible Inputs
■ Fully Static Operation
Standby
H
X
X
High Z
Figure 1: Truth Table
Figure 2: Block Diagram
MA6116 & MA6216
CHARACTERISTICS AND RATINGS
Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functlonal operation of the device at these condltions,
or at any other condition above those indicated in the
operations section of this specification, is not Implied
Exposure to absolute maxlmum rating conditions for
extended perlods may affect device reliability.
Symbol
VDD
VI
Parameter
Min.
-0.5
-0.3
-55
Max.
7
Units
V
Supply Voltage
Input Voltage
VDD+0.3
125
V
TA
Operating Temperature
Storage Temperature
°C
°C
TS
-65
150
Figure 3: Absolute Maximum Ratings
Notes for Tables 4 and 5:
1. Characteristics apply to pre radiation at TA = -55°C to +125°C with VDD = 5V ±10% and to post 100k Rad(Si) total dose
radiation at TA = 25°C with VDD = 5V ±10% (characteristics at higher radiation levels available on request).
2. Worst case at TA = +125°C, guaranteed but not tested at TA = -55°C.
3. GROUP A SUBGROUPS 1, 2, 3.
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
VDD
VlH
VlL
Supply voltage
-
4.5
5.0
5.5
VDD
0.8
-
V
V
Input High Voltage
-
VDD/2
-
-
Input Low Voltage
-
VSS
V
VOH
VOL
ILI
Output High Voltage
IOH1 = -1mA
2.4
-
V
Output Low Voltage
IOL = 4mA
-
-
-
-
-
-
0.4
±10
±20
40
V
Input Leakage Current (note 2)
Output Leakage Current (note 2)
Power Supply Current
Selected Supply Current
All inputs except CS
-
µA
µA
mA
mA
ILO
Output disabled, VOUT = VSS or VDD
fRC = 1MHz, CS = 50% mark:space
-
IDD
ISB1
20
50
All inputs = VDD-0.2V except
70
CS = VSS+0.2V
ISB2
Standby Supply Current
Chip disabled, CS = VDD-0.2V
-
0.1
5
mA
Figure 4: Electrical Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDR
IDDR
VCC for Data Retention
Data Retention Current
CS = VDR
2.0
-
-
-
V
CS = VDR, VDR = 2.0V
50
3000
µA
Figure 5: Data Retention Characteristics
2
MA6116 & MA6216
AC CHARACTERISTICS
Conditions of Test for Tables 5 and 6:
1. Input pulse = VSS to 3.0V.
2. Times measurement reference level = 1.5V.
3. Output load 1TTL gate and CL = 60pF.
4. Transition is measured at ±500mV from steady state.
5. This parameter is sampled and not 100% tested.
Notes for Tables 6 and 7:
Characteristics apply to pre-radiation at TA = -55°C to +125°C with VDD = 5V±10% and to post 100k Rad(Si) total dose radiation
at TA = 25°C with VDD = 5V ±10%. GROUP A SUBGROUPS 9, 10, 11.
MA6116
MA6216
Symbol
Parameter
Min Max Min Max Units
TAVAVR
TAVQV
Read Cycle Time
150
-
-
130
140
-
100
-
-
95
100
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
TELQV
Chip Select Access Time
-
-
TELQX (4,5)
TGLQV
Chip Select to Output in Low Z
Output Enable to Output Valid
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Disable to Output in High Z
Output Hold from Address Change
10
-
10
-
80
-
60
-
TGLQX (4,5)
TEHQZ (4,5)
10
0
10
0
60
60
-
50
50
-
T
GHQZ (4,5)
TAXQX
0
0
10
10
Figure 6: Read Cycle AC Electrical Characteristics
MA6116
MA6216
Symbol
Parameter
Min Max Min Max Units
TAVAVW
TELWH
Write Cycle Tlme
150
85
80
20
50
5
-
-
100
75
70
10
40
5
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Set Up Time
TAVWH
-
-
TAVWL
-
-
TWLWH
Write Pulse Width
-
-
TWHAV
Write Recovery Time
-
-
TWLQZ (4,5)
TDVWH
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End to Write
Chip Selection to Write Low
0
60
-
0
50
-
30
10
5
25
10
5
TWHDX
-
-
TWHQX (4,5)
TELWL
-
-
25
-
25
-
Figure 7: Write Cycle AC Electrical Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
CIN
Input Capacitance
Output Capacitance
Vl = 0V
-
-
6
5
10
7
pF
pF
COUT
VO = 0V
Note: TA = 25°C and f = 1MHz. Data obtained by characterisation or analysis; not routinely measured.
Figure 8: Capacitance
3
MA6116 & MA6216
Symbol
Parameter
Conditions
FT
Basic Functionality
VDD = 4.5V - 5.5V, FREQ = 1MHz
VIL = VSS, VIH = VDD, VOL ≤ 1.5V, VOH ≥ 1.5V
TEMP = -55°C to +125°C, GPS PATTERN SET
GROUP A SUBGROUPS 7, 8A, 8B
Figure 9: Functionality
Subgroup
Definition
1
2
Static characteristics specified in Tables 4 and 5 at +25°C
Static characteristics specified in Tables 4 and 5 at +125°C
Static characteristics specified in Tables 4 and 5 at -55°C
Functional characteristics specified in Table 9 at +25°C
Functional characteristics specified in Table 9 at +125°C
Functional characteristics specified in Table 9 at -55°C
Switching characteristics specified in Tables 6 and 7 at +25°C
Switching characteristics specified in Tables 6 and 7 at +125°C
Switching characteristics specified in Tables 6 and 7 at -55°C
3
7
8A
8B
9
10
11
Figure 10: Definition of Subgroups
4
MA6116 & MA6216
TIMING DIAGRAMS
T
AVAVR
ADDRESS
T
AVQV
ELQV
T
AXQX
T
CS
T
ELQX
T
EHQZ
HIGH
IMPEDANCE
DATA OUT
DATA VALID
T
GLQX
T
GHQZ
T
GLQV
OE
1. WE is high for Read Cycle.
2. Address Vaild prior to or coincident with CS transition low.
Figure 11a: Read Cycle 1
T
AVAVR
ADDRESS
DATA OUT
T
AVQV
T
AXQX
DATA VALID
1. WE is high for Read Cycle.
2. Device is continually selected. CS is high.
Figure 11b: Read Cycle 2
5
MA6116 & MA6216
T
AVAVW
ADDRESS
T
AVWH
T
WHAV (3)
T
WLWH (2)
T
AVWL
(4)
WE
T
AXQX
(6)
T
WLQZ
T
ELWL
(8)
T
WLQH
(7)
HIGH
IMPEDANCE
DATA OUT
DATA IN
T
DVWH
T
WHDX
DATA VALID
T
ELWH
CS
1. WE must be high during all address transitions.
2. A write occurs during the overlap (TWLWH) of a low CS and a low WE.
3. TWHAV is measured from either CS or WE going high, whichever is the earlier, to the end of the write cycle.
4. If the CS low transition occurs simultaneously with, or after, the WE low transition, the output remains in the
high impedance state.
5. DATA OUT is in the active state, so DATA IN must not be in opposing state.
6. DATA OUT is the write data of the current cycle, if selected.
7. DATA OUT is the read data of the next address, if selected.
8. TELWL must be met to prevent memory corruption.
9. OE is low. (If OE is high then DATA OUT remains in the high impedance state throughout the cycle).
Figure 12: Write Cycle
6
MA6116 & MA6216
OUTLINES AND PIN ASSIGNMENTS
D
12
1
13
24
W
ME
Seating Plane
A1
A
C
H
e1
e
b
Z
15°
1
2
A7
24 Vdd
23 A8
22 A9
Millimetres
Inches
Nom.
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
Vss
Ref
Min.
Nom.
Max.
5.715
1.53
0.59
0.36
30.79
-
Min.
Max.
0.225
0.060
0.023
0.014
1.212
-
3
A
A1
b
-
-
-
-
-
-
-
-
4
0.38
-
0.015
21
20
WE
OE
0.35
-
0.014
5
c
0.20
-
0.008
Top
View
6
19 A10
18
D
-
-
-
7
CS
e
-
2.54 Typ.
-
0.100 Typ.
e1
H
-
15.24 Typ.
-
-
0.600 Typ.
-
8
17 D7
16 D6
15 D5
14 D4
13 D3
4.71
-
-
-
-
5.38
15.90
1.27
1.53
0.185
-
-
-
-
0.212
0.626
0.050
0.060
9
Me
Z
-
-
-
-
-
-
10
11
12
W
XG403
Figure 13: 24-Lead Ceramic DIL (Solder Seal) - Package Style C
7
MA6116 & MA6216
M
b
D
Z
e
L
A
c
ME
A1
Millimetres
Inches
Pin 1
Ref
Min.
-
Nom.
Max.
3.07
-
Min.
-
Nom.
Max.
0.121
-
A
A1
b
-
-
0.66
0.38
0.08
14.99
-
-
0.026
0.015
0.003
0.590
-
-
-
0.48
0.152
15.50
-
-
0.019
0.006
0.610
-
c
-
-
D
-
-
e
2.54
0.050
L
6.73
9.96
7.6
-
-
-
-
7.75
10.36
-
0.265
0.392
0.30
0.005
-
-
-
-
0.305
0.408
-
M
Me
Z
0.13
1.14
0.045
XG544
Vdd 24
A8 23
A9 22
1
2
3
4
5
6
7
8
9
A7
A6
A5
A4
A3
A2
A1
A0
D0
21
20
WE
OE
A10 19
18
Bottom
View
CS
D7 17
D6 16
D5 15
D4 14
D3 13
10 D1
11 D2
12 Vss
Figure 14: 24-Lead Ceramic Flatpack (Solder Seal) - Package Style F
8
MA6116 & MA6216
A5
A6
D1
D2
Vss
NC
D3
D4
D5
A7
NC
Vdd
A8
A9
Millimetres
Inches
Ref
Min.
Nom.
Max.
Min.
Nom.
Max.
A
B1
D
1.83
-
2.28
0.072
-
0.090
0.56
-
-
0.71
0.022
-
0.028
11.30
11.63
0.445
-
0.458
D1
E
-
7.62
-
-
-
0.300
-
-
13.84
14.22
0.545
0.560
E1
e
-
10.61
1.27
-
-
-
0.400
0.050
-
-
-
-
-
-
e1
h
0.38
-
0.015
-
-
1.016
0.51
1.27
-
-
-
0.040
0.020
0.050
-
-
i
-
-
-
-
-
-
-
-
L
L2
1.96
2.36
0.077
0.093
XG520
Figure 15: 32-Pad Leadless Chip Carrier - Package Style L
9
MA6116 & MA6216
Package Options
Burnin
Static 2
5V
Function
A7
L
2
C&F
1
Via
R
R
R
R
R
R
R
R
R
R
R
Direct
R
R
R
R
R
Static1
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
5V
Dynamic
F7
Radiation
5V
A6
3
2
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
0V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
F6
5V
A5
4
3
F5
5V
A4
5
4
F4
5V
A3
6
5
F3
5V
A2
7
6
F2
5V
A1
10
11
13
14
15
16
18
19
20
21
22
23
27
28
29
30
31
32
7
8
9
F1
5V
A0
F0
5V
D0
D1
D2
VSS
D3
D4
D5
D6
D7
CSB
A10
OEB
WEB
A9
LOAD
LOAD
LOAD
0V
LOAD
LOAD
LOAD
LOAD
LOAD
0V
5V
5V
5V
0V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R
R
R
R
R
R
Direct
F10
5V
5V
F9
A8
F8
5V
VDD
5V
5V
1. F0=150KHz, F1=F0/2, F2=F0/4, F3=F0/8 etc.
2. Burnin R=1k
3. Radiation R=10k
Figure 16: Burnin and Radiation Configuration
10
MA6116 & MA6216
RADIATION TOLERANCE
Total Dose (Function to specification)*
Transient Upset (Stored data loss)
Transient Upset (Survivability)
1x105 Rad(Si)
5x1010 Rad(Si)/sec
>1x1012 Rad(Si)/sec
Total Dose Radiation Testing
For product procured to guaranteed total dose radiation
levels, each wafer lot will be approved when all sample
devices from each lot pass the total dose radiation test.
The sample devices will be subjected to the total dose
radiation level (Cobalt-60 Source), defined by the ordering
code, and must continue to meet the electrical parameters
specified in the data sheet. Electrical tests, pre and post
irradiation, will be read and recorded.
Neutron Hardness (Function to specification)
Single Event Upset**
>1x1015 n/cm2
3.4x10-9 Errors/bit day
Not possible
Latch Up
* Other total dose radiation levels available on request
** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
GEC Plessey Semiconductors can provide radiation
testing compliant with MIL-STD-883 test method 1019,
Ionizing Radiation (Total Dose).
Figure 17: Radiation Hardness Parameters
SINGLE EVENT UPSET CHARACTERISTICS
UPSET BIT
CROSS-SECTION
(cm2/bit)
Ion LET (MeV.cm2/mg)
Figure 18: Typical Per-Bit Upset Cross-Section vs Ion LET
11
MA6116 & MA6216
ORDERING INFORMATION
Unique Circuit Designator
MAx6116xxxxx
MAx6216xxxxx
Radiation Tolerance
S
L
C
R
Radiation Hard Processing
30 kRads (Si) Guaranteed
50 kRads (Si) Guaranteed
100 kRads (Si) Guaranteed
QA/QCI Process
(See Section 9 Part 4)
Test Process
(See Section 9 Part 3)
Package Type
C
F
L
Ceramic DIL (Solder Seal)
Flatpack (Solder Seal)
Leadless Chip Carrier
Assembly Process
(See Section 9 Part 2)
Reliability Level
L
Rel 0
C
D
E
B
S
Rel 1
Rel 2
Rel 3/4/5/STACK
Class B
Class S
For details of reliability, QA/QC, test and assembly
options, see ‘Manufacturing Capability and Quality
Assurance Standards’ Section 9.
HEADQUARTERS OPERATIONS
CUSTOMER SERVICE CENTRES
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07
• GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55
• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire, SN2 2QW, United Kingdom.
Tel: (01793) 518000
• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
• NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023
• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
• SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
• TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260
• UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK
Tel: (01793) 518527/518566 Fax: (01793) 518582
Fax: (01793) 518411
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017,
1500 Green Hills Road, Scotts Valley,
California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576
These are supported by Agents and Distributors in major countries world-wide.
© GEC Plessey Semiconductors 1995 Publication No. DS3582-3.1 March 1995
TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to
be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide
only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of
any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose
failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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