MAH28151CDXXX [MICROSEMI]
Telecom IC,;
Microsemi 
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
APRIL 1995
DS3574-3.3
MA28151
RADIATION HARD PROGRAMMABLE
COMMUNICATION INTERFACE
The MA28151 is based on the industry standard 8251A
Universal Synchronous Asynchronous Receiver/Transmitter
(USART), modified for data communications with the MAS281
microprocessor.
The MA28151 is used as a peripheral device and is
programmed by the CPU to operate using virtually any serial
data transmission technique presently in use (including IBM
“bi-sync”). The USART accepts data characters from the CPU
in parallel format and then converts them into a continuous
serial data stream for transmission.
Simultaneously, it can receive serial data streams and
convert them into parallel data characters for the CPU. The
USART signals the CPU whenever it receives a character for
transmission or whenever it receives a character for the CPU.
The CPU can read the complete status of the USART at any
time, including data transmission errors and control signals
such as SYNDET and TxEMPTY.
FEATURES
■ Radiation Hard to 1MRad(Si)
■ Latch Up Free, High SEU Immunity
■ Silicon-on-Sapphire Technology
■ Synchronous 5 - 8 Bit Characters; Internal or External
Figure 1: MA28151 Block Diagram
Character Synchronisation; Automatic Sync Insertion
■ Asynchronous 5 - 8 Bit Characters; Clock Rate - 1, 16 or
64 Times Baud Rate; Break Character Generation, 1 1⁄
2 Stop Bits
2
or
■ All Inputs and Outputs are TTL Compatible
■ Compatible with the MAS281 (MIL-STD-1750A)
Microprocessor
The MA28151 is based on the industry standard 8251A
USART, modified for use with the MAS281 processor,
incorporating the following features:
prevents the transmitter from turning off in the middle of a
word.
6. When external Sync Detect is programmed, Internal Sync
Detect is disabled and an External Sync Detect status is
provided via a flip-flop, which clears itself upon a status read.
7. The possibility of a false sync detect is minimized in two
ways: by ensuring that if double character sync is
programmed, the characters will be continuously detected and
by clearing the Rx register to all 1’s whenever Enter-Hunt
command is issued in Sync mode.
8. When the MA28151 is not selected, the RDWN and DSN
lines do not affect the internal operation of the device.
9. The MA28151 Status can be read at any time but the status
update will be inhibited during status read.
1. MA28151 has double-buffered data paths with separate l/O
registers for control status, data in and data out, which
considerably simplifies control programming and minimizes
CPU overhead.
2. In synchronous operations, the Receiver detects and
handles “break” automatically, relieving the CPU of this task.
3. A refined Rx initialisation prevents the Receiver from
starting when in the “break” state, preventing unwanted
interrupts from the disconnected USART.
4. At the conclusion of a transmission, the TxD line will always
return to the marking state unless SBRK is programmed.
5. Tx Enable logic enhancement prevents a Tx Disable
command from prematurely halting transmission of the
previously written data before completion. The logic also
10. The MA28151 is free from extraneous glitches, providing
higher speed and better operating margins.
11. Synchronous Baud rate is from DC to 64K.
12. Asynchronous Baud rate is from DC to 19.2K.
MA28151
1. FUNCTIONAL DESCRIPTION
1.1 GENERAL
1.6 READ/WRITE SELECT (RDWN)
A high on the RDWN input indicates a read of data or
status information from the MA28151. A low on this input
indicates a transfer of data or control words into the MA28151.
The RDWN line is valid only when DSN is low. Figure 2
summarises the MAS28151 read/write operati ons.
The MA28151 is a Universal Synchronous/Asynchronous
Receiver/Transmitter designed for use with the MAS281
microprocessor. Like other l/O devices in a microcomputer
system, its functional configuration is programmed by the
system’s software for maximum flexibility. The MA28151 can
support most serial data techniques in use, including IBM bi-
sync.
In a communication environment, an interface device must
convert parallel format system data into serial format for
transmission, and convert incoming serial data into parallel
system data for reception. The interface device must also
delete or insert bits or characters that are functionally unique to
the communication technique. In essence, the interface should
appear transparent to the CPU for the simple input or output of
byte-oriented system data.
1.7 CONTROL/DATA (CDN)
This input, in conjunction with the DSN and RDWN inputs,
informs the MA28151 that the word on the Data Bus is either a
data character, control word or status information.
1 = CONTROL/STATUS; 0= DATA
CDN RDWN DSN
CSN
ACTION
0
0
1
1
x
x
1
0
1
0
x
x
0
0
0
0
1
x
0
0
0
0
0
1
28151 TO CPU
CPU TO 28151
STATUS TO CPU
CPU TO CONTROL
BUS TRISTATE
BUS TRISTATE
1.2 DATA BUS BUFFER
This 3-state, bidirectional, 8-bit buffer is used to interface
the MA28151 to the system data bus. Data is transmitted or
received by the buffer upon execution of OUTput or INput
instructions from the CPU.
Control word, Command words and Status information are
also transferred through the Data Bus Buffer. The Command
Status, Data-in and Data-out registers are separate 8-bit
registers, communicating with the system bus through the
Data Bus Buffer.
This functional block accepts inputs from the system
control bus and generates control signals for overall device
operation. It contains the Control Word Register and
Command Word Register, which store the various control
formats for the device’s functional definition.
Figure 2: Read/Write Control
1.8 CHIP SELECT (CSN)
A low on this input selects the MA28151. No reading or
writing will occur unless the device is selected. When CSN is
high, the Data Bus is in the float state and the DSN and RDWN
lines have no effect on the chip.
1.9 MODEM CONTROL
The MA28151 has a set of control inputs and outputs which
can be used to simplify the interface to almost any modem.
The modem control signals are general purpose in nature and
can be used for functions other than modem control, if
necessary.
1.3 RESET
A high on this input forces the MA28151 into idle mode.
The MA28151 will remain at idle until its functional definition is
programmed with a new set of control words. Minimum RESET
pulse width is 6 tcy (clock must be running).
The device can also be put into the idle state by a
command reset operation .
1.10 DATA SET READY (DSR)
The DSR input signal is a general-purpose, 1-bit inverting
input port. Its condition can be tested by the CPU using a
Status Read operation. The DSR input is normally used to test
modem conditions such as Data Set Ready.
1.4 CLOCK (CLK)
The CLK input is used to generate internal device timing
and is normally connected to the clock generator (OSC) of the
system.
Please note: None of the external inputs or outputs are
referenced to CLK but the frequency of CLK must be greater
than 30 times the Receiver or Transmitter data bit rates.
1.11 DATA TERMINAL READY (DTR)
The DTR output signal is a general purpose, 1-bit inverting
output port. It can be set low by programming the appropriate
bit in the Command instruction word. The DTR output signal is
normally used for modem control such as Data Terminal
Ready.
1.5 DATA STROBE (DSN)
This input indicates that a data transfer is taking place.
During a CPU write operation the MA28151 reads data from
the bus on the rising edge of DSN. During a read operation the
MA28151 can output data while DSN is low. Data is valid on
the rising edge of DSN.
2
MA28151
1.12 REQUEST TO SEND (RTS)
automatically transmitted as fillers. TxEMPTY does not go low
when the SYNC characters are being shifted out.
The RTS output signal is a general purpose, 1-bit inverting
output port. It can be set low by programming the appropriate
bit in the Command instruction word. The RTS output signal is
normally used for modem control such as Request To Send.
1.18 TRANSMITTER CLOCK (TxC)
The Transmitter Clock controls the rate at which the
character is to be transmitted. In the Synchronous
transmission mode, the Baud Rate (1x) is equal to the TxC
frequency. In Asynchronous transmission mode, the baud rate
is a fraction of the actual TxC frequency. A portion of the mode
instruction selects this factor; it can be 1,1/16 or 1/64 the TxC.
1.13 CLEAR TO SEND (CTS)
A low on this input enables the MA28151 to transmit serial
data if the Tx Enable bit in the Command byte is set to a high.
If either a Tx Enable off or CTS off condition occurs while the
Tx is in operation, the Tx will transmit all the data in the
USART, written prior to Tx disable command, before shutting
down.
For Example:
If Baud Rate equals 110 Baud
TxC equals 110Hz in the 1x mode
TxC equals 1 72KHz in the 16x mode
TxC equals 7.04KHz in the 64x mode
The falling edge of TxC shifts the serial data out of the
MA28151.
1.14 TRANSMITTER BUFFER
The Transmitter Buffer accepts parallel data from the Data
Bus Buffer, converts it to a serial bit stream, inserts the
appropriate characters or bits (based on the communication
technique) and outputs a composite serial stream of data on
the TxD output pin on the falling edge of TxC. The transmitter
will begin transmission upon being enabled if CTS = 0. The
TxD line will be held in the marking state immediately upon a
master Reset, or when Tx Enable or CTS = 1, or the
transmitter is empty.
1.19 RECEIVER BUFFER
The Receiver accepts serial data, converts the data to
parallel format, checks for bits or characters that are unique to
the communications techniques and sends an assembled
character to the CPU. Serial data is input to the RxD pin and is
clocked in on the rising edge of RxC.
1.15 TRANSMITTER CONTROL
The Transmitter Control manages all activities associated
with the transmission of serial data. It accepts and issues
signals both externally and internally to accomplish this
function.
1.20 RECEIVER CONTROL
This functional block manages all receiver-related activities
which consist of the following features:
The RxD initialisation circuit prevents the MA28151 from
mistaking an unused input line for an active low data line in the
break condition. Before starting to receive serial characters on
the RxD line, a valid 1 must first be detected after a chip master
Reset. Once this has been determined, a search for a valid low
(start bit) is enabled. This feature is only active in the
asynchronous mode and is only done once for each master
Reset.
The False Start bit detection circuit prevents false starts as
the result of a transient noise spike by first detecting the falling
edge and then strobing the nominal center of the Start bit (RxD
= low).
1.16 TRANSMITTER READY (TxRDY)
This output signals the CPU that the transmitter is ready to
accept a data character. The TxRDY output pin can be used as
an interrupt to the system since it is masked by TxEnable; or,
for Polled operation, the CPU can check TxRDY using a Status
Read operation. TxRDY is automatically reset by the falling
edge of DSN (with RDWN low) when a data character is
loaded from the CPU.
Note that when using the polled operation, the TxRDY
status bit is not masked by TxEnable, but will only indicate the
Empty/Full Status of the Tx Data input Register.
Parity error detection sets the corresponding status bit.
The Framing Error status bit is set if the Stop bit is absent
at the end of the data byte (asynchronous mode).
1.17 TRANSMITTER EMPTY (TxE)
When the MA28151 has no characters to send, the
TxEMPTY output will go high. It resets upon receiving a
character from CPU if the transmitter is enabled. TxEMPTY
remains high when the transmitter is disabled. TxEMPTY can
be used to indicate the end of transmission mode, so that the
CPU can turn the line around in the half-duplex operational
mode.
In the Synchronous mode, a high on the TxEMPTY output
indicates that a character has not been loaded and the SYNC
character or characters are about to be or are being
1.21 RxRDY (RECEIVER READY)
This output indicates that the MA28151 contains a
character that is ready to be input to the CPU. RxRDY can be
connected to the interrupt structure of the CPU or, for polled
operation, the CPU can check the condition of RxRDY using a
Status Read operation. RxEnable, when off holds RxRDY in
the Reset Condition. For Asynchronous mode, to set RxRDY,
the Receiver must be enabled to sense a Start Bit and a
complete character must be assembled and transferred to the
Data Output Register. For Synchronous mode, to set RxRDY,
3
MA28151
the Receiver must be enabled and a character must finish
assembly and be transferred to the Data Output Register
Failure to read the received character from the Rx Data
Output Register prior to the assembly of the next Rx Data
character will set overrun condition error and the previous
character will be written over and lost. If the Rx Data is being
read by the CPU when the internal transfer is occurring, the
overrun error will be set and the old character will be Iost.
1.24 BREAK (ASYNC MODE ONLY)
This output will go high whenever the receiver remains low
through two consecutive stop bit sequences including the start
bits, data bits, and parity bits. Break Detect may also be read
as a Status bit. It is reset only upon a master chip Reset or Rx
Data returning to a “one” state.
C/D
ACTION
1.22 RxC (RECEIVER CLOCK)
1
1
1
1
0
1
0
1
MODE INSTRUCTION
SYNC CHARACTER 1 (SYNC ONLY) *
SYNC CHARACTER 2 (SYNC ONLY) *
COMMAND INSTRUCTION
DATA
COMMAND INSTRUCTION
DATA
COMMAND INSTRUCTION
The Receiver Clock controls the rate at which the character
is to be received. In Synchronous Mode the Baud Rate (1x) is
equal to the actual frequency of RxC. In Asynchronous Mode,
the Baud Rate is a fraction of the actual RxC frequency. A
portion of the mode instruction selects this factor: 1,1⁄16 or 1⁄64 of
the Receiver Clock.
For example:
Baud Rate equals 300 Baud, if
Note: The second sync character is skipped if mode instruction
has programmed the MA28151 to single character mode. Both
sync characters are skipped if mode instruction has
programmed the MA28151 to async mode
RxC equals 300 Hz in the 1 x mode:
RxC equals 4800 Hz in the 16x mode
RxC equals 19.2 KHz in the 64x mode.
Baud Rate equals 2400 Baud if
RxC equals 2400Hz in the 1x mode
RxC equals 38.4 KHz in the 16x mode;
RxC equals 153.6 KHz in the 64x mode.
Data is sampled into the MA28151 on the rising edge of RxC.
Figure 3: Typical data block
2. OPERATION DESCRIPTION
Note: In most communications systems, the MA28151 will
be handling both the transmission and reception operations of
a single link. Consequently the Receive and Transmit Baud
Rates will be the same. Both TxC and RxC will require identical
frequencies for this operation and can be tied together and
connected to a single frequency source (Baud Rate
Generator) to simplify the interface.
2.1 GENERAL
The complete functional definition of the MA28151 is
programmed by the system’s software. A set of control words
must be sent out by the CPU to initialize the MA28151 to
support the desired communications format. These control
words will program the: Baud Rate, Character Length, Number
of Stop Bits, Synchronous or Asynchronous Operation, Even/
Odd/Off Parity, etc. In the Synchronous Mode, options are also
provided to select either internal or external character
synchronization.
Once programmed, the MA28151 is ready to perform its
communication functions. The TxRDY output is raised high to
signal the CPU that the MA28151 is ready to receive a data
character from the CPU. This output (TxRDY) is reset
automatically when the CPU writes a character into the
MA28151. Alternatively, the MA28151 receives serial data
from the MODEM or l/O device. Upon receiving an entire
character, the RxRDY output is raised high to signal the CPU
that the MA28151 has a complete character ready for the CPU
to fetch. RxRDY is reset automatically upon the CPU data read
operation.
1.23 SYNC/BREAK DETECT (SYNDET/BRKDET)
This pin is used in Synchronous Mode for SYNDET and
may be used as either input or output, programmable through
the Control Word. It is reset to output mode, low upon RESET.
When used as an output (internal Sync mode), the SYNDET
pin will go high to indicate that the MA28151 has located the
SYNC character in the Receive mode. If the MA28151 is
programmed to use double Sync characters (bi-sync), the
SYNDET will go high in the middle of the last bit of the second
Sync character.
SYNDET is automatically reset upon a Status Read
operation.
When used as an input (external SYNC detect mode), a
positive going signal will cause the MA28151 to start
assembling data characters on the rising edge of the next RxC.
Once in SYNC, the high input signal can be removed. When
External SYNC Detect is programmed, Internal SYNC Detect
is disabled.
The MA28151 cannot begin transmission until the
TxEnable (Transmitter Enable) bit is set in the Command
instruction and it has received a Clear To Send (CTS) input.
The TxD output will be held in the marking state upon Reset.
4
MA28151
3. PROGRAMMING THE MA28151
3.1 MODE AND COMMAND INSTRUCTIONS
3.3 TEST MODE
The Mode Instruction can be used to select a scan path
test facility. In this mode a test vector is read in through RxD
and read out in TxD. For further information of test mode
please contact GEC Plessey Semiconductors.
Prior to starting data transmission or reception, the
MA28151 must be loaded with a set of control words
generated by the CPU. These control signals define the
complete functional definition of the MA28151 and must
immediately follow a Reset operation (internal or external).
The control words are split into two formats:
1. Mode Instruction
2. Command Instruction
3.4 ASYNCHRONOUS MODE (TRANSMISSION)
Whenever a data character is sent by the CPU the
MA28151 automatically adds a Start bit (low level), followed by
the data bits (least significant bit first,) and the programmed
number of Stop bits to each character. Also, an even or odd
Parity bit is inserted prior to the Stop bit(s), as defined by the
Mode Instruction. The Character is then transmitted as a serial
data stream on the TxD output. The serial data is shifted out on
the falling edge of TxC at a rate equal to 1, 1⁄16 or 1⁄64 times that
of the TxC, as defined by the Mode Instruction. BREAK
characters can be continuously sent to the TxD if commanded
to do so.
3.1.1 Mode Instruction
This instruction defines the general operational
characteristics of the MA28151. It must follow a Reset
operation (internal or external). Once the Mode instruction has
been written into the MA28151 by the CPU, SYNC characters
or Command Instructions may be written.
3.1.2 Command Instruction
When no data characters have been loaded into the
MA28151 the TxD output remains high (marking) unless a
Break (continuously low) has been programmed.
This instruction defines a word that is used to control the
actual operation of the MA28151.
Both the Mode and Command Instruction must conform to
a specified sequence for proper device operation. The Mode
instruction must be written immediately following a Reset
operation, prior to using the MA28151 for data
communications.
All control words written into the MA28151 after the Mode
Instruction will load the Command Instruction. Command
Instructions can be written into the MA28151 at any time in the
data block during the operation of the MA28151. To return to
the Mode Instruction format, the master Reset bit in the
Command Instruction word can be set to initiate an internal
Reset operation. This automatically places the MA28151 back
into the Mode Instruction format. Command Instructions must
follow the Mode Instructions or Sync characters.
3.5 ASYNCHRONOUS MODE (RECEIVE)
The RxD line is normally high. A falling edge on this line
triggers the beginning of a START bit. The validity of this
START bit is checked by again strobing this bit at its nominal
center (16x or 64X mode only). If a low is detected again, it is a
valid START bit, and the bit counter will start counting. The bit
counter thus locates the center of the data bits, the parity bit (if
it exists) and the stop bits. If a parity error occurs, the parity
error flag is set. Data and parity bits are sampled on the RxD
pin with the rising edge of RxC. If a low level is detected as the
STOP bit, the Framing Error flag will be set. The STOP bit
signals the end of a character. Note that the receiver requires
only one stop bit, regardless of the number of stop bits
programmed. This character is then loaded into the parallel l/O
buffer of the MA28151. The RxRDY pin is raised to signal the
CPU that a character is ready to be fetched.
3.2 MODE INSTRUCTION DEFINITION
The MA28151 can be used for either Asynchronous or
Synchronous data communications. To understand how the
Mode Instruction defines the functional operation of the
MA28151, the designer can best view the device as two
separate components, one Asynchronous and the other
Synchronous, sharing the same package. The format
definition can be changed only after a master chip Reset. For
explanation purposes the two formats will be isolated.
NOTE: When parity is enabled it is not considered as one
of the data bits for the purpose of programming the word
length. The actual parity bit received on the Rx Data line
cannot be read on the Data Bus. In the case of a programmed
character length of less than 8 bits, the least significant data
bus bits will hold the data; unused bits are ‘don’t care’ when
writing data to the MA28151, and will be zeros when reading
the data from the MA28151.
If a previous character has not been fetched by the CPU,
the present character replaces it in the l/O buffer, and the
OVERRUN Error flag is raised (thus the previous character is
lost). All of the error flags can be reset by an Error Reset
Instruction. The occurrence of any of these errors will not affect
the operation of the MA28151.
5
MA28151
D7 D6 D5 D4 D3 D2 D1 D0
S2 S1 EP PEN L2 L1 B2 B1
BAUD RATE FACTOR
0
0
0
0
1
1
1
1
SYNC
MODE
(1x)
(16x)
(64x)
CHARACTER LENGTH
0
0
1
0
0
1
1
1
5
6
7
8
BITS
BITS
BITS
BITS
PARITY ENABLE AND SENSE
1 = ENABLE 0 = DISABLE
1 = EVEN 0 = ODD
NUMBER OF STOP BITS
0
0
1
0
0
1
1
1
NOT
1
1 1/2
BITS
2
VALID
BIT
BITS
Figure 4: Mode Instruction Format, Asynchronous Mode
DATA BITS D0-Dx
GENERATED BY MA28151
PARITY BIT
TxD MARKING
STOP
BITS
DATA BITS D0-Dx
DOES NOT APPEAR ON DBUS
RxD
PROGRAMMED CHAR. LENGTH
PARITY BIT
STOP
BITS
6
MA28151
CPU BYTE (5-8 BITS/CHARACTER)
DATA CHARACTER
ASSEMBLED SERIAL DATA OUTPUT (TxD)
START BIT
DATA CHARACTER
PARITY BIT
STOP BITS
Figure 6: Transmission Format
SERIAL DATA INPUT (RxD)
START BIT
DATA CHARACTER
PARITY BIT
STOP BITS
CPU BYTE (5-8 BITS/CHARACTER) (See Note Below)
DATA CHARACTER
NOTE: If character length is defined as 5, 6 or 7 bits the unused bits are set to zero.
Figure 7: Receive Format
3.6 SYNCHRONOUS MODE (TRANSMISSION)
synchronization. The SYNDET pin is then set high, and is reset
automatically by a STATUS READ. If parity is programmed,
SYNDET will not be set until the middle of the parity bit, instead
of the middle of the last data bit.
In the external SYNC mode, synchronization is achieved
by applying a high level on the SYNDET pin, thus forcing the
MA28151 out of the HUNT mode. The high level can be
removed after one RxC cycle. An ENTER HUNT command
has no effect in the asynchronous mode of operation.
The TxD output is continuously high until the CPU sends its
first character to the MA28151 which usually is a SYNC
character. When the CTS line goes low, the first character is
serially transmitted out. All characters are shifted out on the
falling edge of TxC. Data is shifted out at the same rate as the
TxC.
Once transmission has started, the data stream at the TxD
output must continue at the TxC rate. If the CPU does not
provide the MA28151 with a data character before the
MA28151 Transmitter Buffers become empty, the SYNC
characters (or character if in single SYNC character mode) will
be automatically inserted in the TxD data stream. In this case,
the TxEMPTY does not go low when the SYNC is being shifted
out (see figure 8). The TxEMPTY pin is internally reset by a
data character being written into the MA28151.
3.7 SYNCHRONOUS MODE (RECEIVER)
In this mode character synchronisation can be internally or
externally achieved. If the SYNC mode has been
programmed, ENTER-HUNT command should be included in
the first command instruction word written. Data on the RxD
pin is then sampled on the rising edge of RxC. The content of
the Rx buffer is compared to every bit boundary with the first
SYNC character until a match occurs.
If the MA28151 has been programmed for two SYNC
characters, the subsequent received character is also
compared; when both SYNC characters have been detected,
the USART ends the HUNT mode and is in character
Figure 8: Sync Character Insertion
7
MA28151
Parity error and overrun error are both checked in the same
3.9 DATA FORMAT, SYNCHRONOUS MODE
way as in the Asynchronous Receive mode. Parity is checked
when not in HUNT, regardless of whether the Receiver is
enabled or not.
DATA CHARACTERS
The CPU can command the receiver to enter the HUNT
mode if synchronisation is lost. This will also set all the used
character bits in the buffer to a one thus preventing a possible
false SYNDET caused by data that happens to be in the Rx
buffer at ENTER HUNT time.
ASSEMBLED SERIAL DATA OUTPUT (TxD)
SYNC CHAR 1 SYNC CHAR 2 DATA CHARACTERS
Note: the SYNDET flip-flop is reset at each Status Read,
regardless of whether internal or external SYNC has been
programmed. This does not cause the MA28151 to return to
the HUNT mode. When in SYNC mode, but not in HUNT, Sync
Detection is still functional, but only occurs at the known word
boundaries. Thus, if one Status Read indicates SYNDET and a
second Status Read also indicates SYNDET, then the
programmed SYNDET characters have been received since
the previous Status Read. (If double character sync has been
contiguously received to gate a SYNDET indication). When
external SYNDET mode is selected, internal Sync Detect is
disabled, and the SYNDET flip-flop may be set at any bit
boundary.
Figure 9: Receive Format, Synchronous Mode
SYNC CHAR 1 SYNC CHAR 2 DATA CHARACTERS
CPU BYTES (5-8 BITS/CHARACTER)
DATA CHARACTERS
Figure 10: Data Format, Synchronous Mode
3.8 MODE INSTRUCTION FORMAT, SYNCHRONOUS MODE
D7 D6 D5 D4 D3 D2 D1 D0
SS ES EP PEN L2 L1
0
0
CHARACTER LENGTH
0
0
1
0
0
1
1
1
5
6
7
8
BITS
BITS
BITS
BITS
PARITY ENABLE AND SENSE
1 = ENABLE 0 = DISABLE
1 = EVEN 0 = ODD
EXTERNAL SYNC DETECT
1 = SYNCDET IS AN INPUT
0 = SYNCDET IS AN OUTPUT
SINGLE CHARACTER SYNC
1 = SINGLE SYNC CHAR.
0 = DOUBLE SYNC CHAR.
Figure 11: Mode Instruction Format, Synchronous Mode
8
MA28151
3.10 COMMAND INSTRUCTION DEFINITION
Once the functional definition of the MA28151 has been
programmed by the Mode Instruction and the sync characters
are loaded (if in Sync Mode) then the device is ready to be
used for data communications. The Command Instruction
controls the actual operation of the selected format. Functions
such as: Enable Transmit/Receive, Error Reset and Modem
Controls are provided by the Command Instruction.
Once the Mode Instruction has been written into the
MA28151 and Sync characters inserted, if necessary, then all
further “control writes” (CDN=1) will load a Command
Instruction. A Reset Operation (internal or external) will return
the MA28151 to the Mode instruction format.
Note: Internal Reset on Power-up. When power is first
applied, the MA28151 may come up in the Mode, Sync
character or Command format. To guarantee that the device is
in the Command instruction format before the Reset command
is issued, it is safest to execute the worst-case initialization
sequence (sync mode with two sync characters). Loading
three 00Hs consecutively into the device with CDN=1
configures sync operation and writes two dummy 00H sync
characters. An internal reset command (40H) may then be
issued to return the device to the idle state.
3.11 COMMAND INSTRUCTION FORMAT
D7
D6
IR
D5
D4
D3
D2
D1
D0
EH
RTS
ER SBRK RxE DTR TxEN
TRANSMIT ENABLE
1 = ENABLE
0 = DISABLE
DATA TERMINAL READY
HIGH WILL FORCE DTR
OUTPUT TO ZERO
RECEIVE ENABLE
1 = ENABLE
0 = DISABLE
SEND BREAK CHARACTER
1 = FORCES TxD LOW
0 = NORMAL OPERATION
ERROR RESET
1 = RESET ERROR FLAGS
PE, OE, FE
REQUEST TO SEND
HIGH WILL FORCE RTS
OUTPUT TO ZERO
INTERNAL RESET
HIGH RETURNS THE MA28151 TO
MODE INSTRUCTION FORMAT
ENTER HUNT MODE*
HIGH ENABLES SEARCH FOR SYNC
CHARACTERS (HAS NO EFFECT IN ASYNC MODE)
*NOTE: ERROR RESET must be performed whenever RxENABLE and ENTER-HUNT
are programmed.
Figure 12: Command Instruction Format
9
MA28151
3.12 STATUS READ DEFINITION
In data communication systems it is often necessary to
examine the status of the active device to ascertain if errors
have occurred or other conditions that require the processor’s
attention. The MA28151 has facilities that allow the
programmer to read the status of the device at any time during
the functional operation. (Status update is inhibited during
status read).
A normal read command is issued by the CPU with CDN
high to accomplish this function.
Some of the bits in the Status Read Format have identical
meanings to external output pins so that the MA28151 can be
used in a completely polled or interrupt-driven environment.
TxRDY is an exception.
Note that status update can have a maximum delay of 28
clock periods from the actual event affecting the status.
3.13 STATUS READ FORMAT
D7
D6
D5
D4
D3
D2
D1
D0
DSR SYNDET
BRKDET
FE
OE
PE
Tx
EMPTY
RxRDY TxRDY
Note 1
Same as I/O pins
PARITY ERROR
The PE flag is set when the
parity error is detected. It is
reset by the ER bit of the
Command Instruction. PE does
not inhibit the operation of the
MA28151.
OVERRUN ERROR
The OE flag is set when the
CPU does not read a character
before the next one becomes
available. It is reset by the ER
bit of the Command Instruction
OE does not inhibit operation
of the MA28151, however the
previously overrun character is
lost.
FRAMING ERROR (ASYNC
ONLY)
The FE flag is set when a valid
Stop bit is not detected at the
end of every character. It is
reset by the ER bit of the
Command Instruction. FE does
not inhibit the operation of the
MA28151.
DATA SET READY
Indicates that the DSR is at a
zero level.
Note 1: TxRDY status bit has different meanings from the TxRDY output pin. The former
is not conditioned by CTS and TxEN, the latter is conditioned by both CTS and TxEN.
ie. TxRDY status bit 0 DB buffer empty
TxRDY pin out = DB buffer empty OR (CTSN = 0) OR (TxEN = 1)
Figure 13: Status Read Format
10
MA28151
4. TIMING WAVEFORMS
Figure 14: System Clock Input
Figure 15: Transmitter Clock and Data
Figure 16: Receive Clock and Data
11
MA28151
Figure 17: Write Data Cycle (CPU to USART)
Figure 18: Read Data Cycle (USART to CPU)
Note: tWC includes the response timing of a control byte.
Figure 19: Write Control or Output Port Cycle (CPU to USART)
12
MA28151
Note: tCR includes the effect of CTS on the TxENABLE circuitary.
Figure 20: Read Control or Output Port Cycle (USART to CPU)
Example Format = 7 bit character with parity and 2 stop bits.
Figure 21: Transmitter Control and Flag Timing (ASYNC Mode)
13
MA28151
Example Format = 7 bit character with parity and 2 stop bits.
Figure 22: Receiver Control and Flag Timing (ASYNC Mode)
14
MA28151
5. AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Condition
tCY
t0
Internal clock cycle time
External Clock high pulse width
External Clock low pulse width
Clock rise and fall time
TxD delay from falling edge of TxD
Transmitter input clock pulse width
200
25
1000
-
nS
nS
Notes 1, 5, 6
-
t0
25
-
-
12xtCY
1xtCY
-
10
1
-
nS
nS
µS
-
-
-
-
tR, tF
tDTX
tTPW
1 x baud rate
16 x and 64 x baud rate
-
-
tTPD
tRPW
tRPD
Transmitter input clock pulse delay
Receive input clock pulse width
Receive input clock pulse delay
15xtCY
3xtCY
-
-
-
-
1 x baud rate
16 x and 64 x baud rate
12xtCY
1xtCY
15xtCY
3xtCY
-
-
-
-
-
-
-
-
-
-
-
-
1 x baud rate
16 x and 64 x baud rate
1 x baud rate
16 x and 64 x baud rate
Note 7
tTxRDY
tTxRDY CLEAR
tRxRDY
tRxRDY CLEAR
tTxEMPTY
tWC
TxRDY pin delay from CENTER of last bit
TxRDY fall from falling DSN (WRITE)
RxRDY pin delay from center of last bit
RxRDY fall from falling DSN (READ)
TxEMPTY from centre of last bit
Control delay from rising edge of WRITE
Control to READ set-up time (DSR, CTS)
Address stable before DSN (CSN, CDN)
Address hold time before DSN (CSN, CDN)
DSN pulse width
8xtCY
45
Note 7
-
26xtCY
45
-
-
-
-
Note 7
Note 7
Note 7
Note 7
Note 7
Note 2
Note 2
-
-
20xtCY
8xtCY
20xtCY
0
-
-
tCR
tAR
tRA
tRR
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
-
0
20
tRD
tDF
tDW
tWD
Data delay from DSN falling (READ)
DSN rising to data floating (READ)
Data set-up time to DSN rising (WRITE)
Data hold time to DSN rising (WRITE)
Recovery time between writes (not shown)
-
10
15
5
30
45
-
Note 3
Note 8
-
-
-
tRV
6xtCY
-
Note 4
Notes: 1. AC Timings measured VOH = 1.5 VOL = 1.5.
2. CSN and Command/Data are considered as addresses.
3. Assumes that address is valid before DSN goes low.
4. This recovery time is for Mode Initialisation only. Write data is allowed when TxRDY = 1. Recovery time between
writes for Asynchronous Mode is 8xtCY and for Synchronous Mode is 16xtCY
.
5. The TxC and RxC frequencies have the following limitation with respect to clock: For 1 x baudrate, fTX or fRX≤1/
(30tCY): For 16 x and 64 x baud rate, fTX or fRX ≤1/(4.5tCY).
6. Reset Pulse Width = 6tCY minimum; System clock must be running during Reset.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
8. Data Bus connected to VDD via loads of 680Ω (minimum).
Mil-Std-883, method 5005, subgroups 9, 10, 11
Figure 23: AC Electrical Characteristics
Symbol
Parameter
Min.
Max.
Units
Condition
-
Clock Frequency (osc)
-
20
MHz
-
fTx
Transmitter input clock frequency
DC
DC
DC
64
310
615
kHz
kHz
kHz
1 x baud rate
16 x baud rate
64 x baud rate
fRx
Receiver input clock frequency
DC
DC
DC
64
310
615
kHz
kHz
kHz
1x baud rate
16 x baud rate
64 x baud rate
Mil-Std-883, method 5005, subgroups 7, 8A, 8B
Figure 24: Operating AC Electrical Characteristics
15
MA28151
6. DC CHARACTERISTICS AND RATINGS
Note: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these conditions, or at
any other condition above those indicated in the operations
section of this specification, is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
Parameter
Min
-0.5
-0.3
-20
-55
-65
Max
7
Units
V
Supply Voltage
Input Voltage
V
DD+0.3
+20
125
150
V
Current Through Any Pin
Operating Temperature
Storage Temperature
mA
°C
°C
Figure 25: Absolute Maximum Ratings
Total dose radiation not
exceeding 3x105 Rad(SI)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VDD
VIH
VIL
Supply Voltage
-
4.5
5.0
5.5
V
V
Input High Voltage
-
2.2
-
-
-
-
-
-
0.8
Input Low Voltage
-
-
V
VOH
VOL
IIN
Output High Voltage
Output Low Voltage
Input Leakage Current (Note 1)
IOH = -2mA
IOL = 5mA
VDD-0.5
-
V
-
-
VSS+0.4
±10
V
VDD = 5.5V,
µA
VIN = VSS or VDD
IOZ
Tristate Leakage Current (Note 1)
VDD = 5.5V,
VIN = VSS or VDD
-
-
-
±50
µA
IDD
Power Supply Current
Static, VDD = 5.5V
0.1
10
mA
VDD = 5V±10%, over full operating temperature range.
Mil-Std-883, method 5005, subgroups 1, 2, 3
Note 1: Guaranteed but not tested at -55°C
Figure 26: Electrical Characteristics
Subgroup
Definition
1
2
Static characteristics specified in Figure 26 at +25°C
Static characteristics specified in Figure 26 at +125°C
Static characteristics specified in Figure 26 at -55°C
Functional characteristics specified in Figure 24 at +25°C
Functional characteristics specified in Figure 24 at +125°C
Functional characteristics specified in Figure 24 at -55°C
Switching characteristics specified in Figure 23 at +25°C
Switching characteristics specified in Figure 23 at +125°C
Switching characteristics specified in Figure 23 at -55°C
3
7
8A
8B
9
10
11
Figure 27: Definition of Mil-Std-883, Method 5005 Subgroups
16
MA28151
7. OUTLINES AND PIN ASSIGNMENTS
D
14
1
15
28
W
ME
Seating Plane
A1
A
C
H
e1
e
b
Z
15°
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D2
D3
D1
Millimetres
Inches
D0
Ref
Min.
Nom.
Max.
5.715
1.53
0.59
0.36
36.02
-
Min.
Nom.
Max.
0.225
0.060
0.023
0.014
1.418
-
3
Vdd
RxD
GND
D4
A
A1
b
-
-
-
-
4
RxC
DTR
RTS
DSR
RESET
CLK
TxD
0.38
-
0.015
-
5
0.35
-
0.014
-
6
D5
c
0.20
-
0.008
-
Top
View
7
D6
D
-
-
-
-
8
D7
e
-
2.54 Typ.
-
0.100 Typ.
9
TxC
RDWN
CSN
e1
H
-
15.24 Typ.
-
-
0.600 Typ.
-
10
11
12
13
14
4.71
-
-
-
-
5.38
15.90
1.27
1.53
0.185
-
-
-
-
0.212
0.626
0.050
0.060
Me
Z
-
-
-
-
-
-
TxE
CDN
CTS
W
DSN
SYNDET
TxRDY
XG404
RxRDY
Figure 28: 28-Lead Ceramic DIL (Solder Seal) - Package Style C
17
MA28151
D
A
e
b
1
Z
Pad 1
Bottom
View
E
Millimetres
Inches
Radius r
3 corners
Ref
Min.
Nom.
Max.
Min.
Nom.
Max.
A
b1
D
E
-
-
-
-
-
-
-
2.29
-
-
-
-
-
-
-
0.090
0.51
-
0.020
-
-
-
14.60
-
-
0.575
14.60
0.575
e
1.02
-
-
0.040
0.060 Typ.
-
-
Z
1.52 Typ.
XG431
7
8
9
10 11 12 13 14 15 16 17 18
19
20
NC
6
5
NC
GND
RxD
D3
CDN
DSN
4
3
21
22
RxRDY
NC
NC
D2
2
1
23
24
Bottom
View
NC
NC
NC
D1
48
47
25
26
TxRDY
SYNDET
NC
46
45
27
28
D0
CTS
NC
Vdd
44
43
29
30
TxEMPTY
NC
42 41 40 39 38 37 36 35 34 33 32 31
Figure 29: 48-Pad Leadless Chip Carrier - Package Style L
18
MA28151
A
A1
c
L
D1
j1
Z
Pin 1
b
e
D2
Top View
j2
Millimetres
Inches
Ref
Min.
-
Nom.
Max.
2.72
2.24
0.51
0.30
24.51
-
Min.
-
Nom.
Max.
A
A1
b
-
-
0.107
0.088
0.020
0.012
0.960
-
1.83
0.41
0.20
23.88
-
-
0.072
0.016
0.008
0.940
-
-
-
-
c
-
-
D1, D2
-
-
e
j1
j2
L
2.54
1.02
0.51
-
0.050
0.040
0.020
-
-
-
-
-
-
-
-
-
10.16
1.65
10.54
2.16
0.400
0.065
0.415
0.085
Z
-
-
XG540
Figure 30a: 68-Lead Topbraze Flatpack - Package Style F
19
MA28151
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NC
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
8
NC
NC
Vss
NC
NC
CDN
7
NC
6
DSN
5
RxD
NC
4
NC
RXRDY
NC
3
D3
2
NC
D2
TXRDY
NC
Top View
1
68
67
66
65
64
63
62
61
NC
D1
SYNDET
NC
NC
D0
CTS
NC
NC
Vdd
NC
NC
TXE
NC
NC
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Figure 30b: 68-Lead Topbraze Flatpack - Package Style F
20
MA28151
8. RADIATION TOLERANCE
Total Dose (Function to specification)*
Transient Upset (Stored data loss)
Transient Upset (Survivability)
Neutron Hardness (Function to specification)
Single Event Upset**
3x105 Rad(Si)
5x1010 Rad(Si)/sec
>1x1012 Rad(Si)/sec
>1x1015 n/cm2
Total Dose Radiation Testing
For product procured to guaranteed total dose radiation
levels, each wafer lot will be approved when all sample
devices from each lot pass the total dose radiation test.
The sample devices will be subjected to the total dose
radiation level (Cobalt-60 Source), defined by the ordering
code, and must continue to meet the electrical parameters
specified in the data sheet. Electrical tests, pre and post
irradiation, will be read and recorded.
<1x10-10 Errors/bit day
Not possible
Latch Up
* Other total dose radiation levels available on request
** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
GEC Plessey Semiconductors can provide radiation
testing compliant with MIL-STD-883 Ionizing Radiation (Total
Dose) test 1019.
Figure 31: Radiation Hardness Parameters
9. ORDERING INFORMATION
Unique Circuit Designator
MAx28151xxxxx
Radiation Tolerance
S
R
Q
H
Radiation Hard Processing
100 kRads (Si) Guaranteed
300 kRads (Si) Guaranteed
1000 kRads (Si) Guaranteed
QA/QCI Process
(See Section 9 Part 4)
Test Process
(See Section 9 Part 3)
Package Type
C
F
L
Ceramic DIL (Solder Seal)
Flatpack (Solder Seal)
Leadless Chip Carrier
Assembly Process
(See Section 9 Part 2)
Reliability Level
L
Rel 0
C
D
E
B
S
Rel 1
Rel 2
Rel 3/4/5/STACK
Class B
Class S
For details of reliability, QA/QC, test and assembly
options, see ‘Manufacturing Capability and Quality
Assurance Standards’ Section 9.
21
MA28151
HEADQUARTERS OPERATIONS
CUSTOMER SERVICE CENTRES
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07
• GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55
• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire, SN2 2QW, United Kingdom.
Tel: (01793) 518000
• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
• NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023
• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
• SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
• TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260
• UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK Tel: (01793) 518527/518566
Fax: (01793) 518582
Fax: (01793) 518411
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017,
1500 Green Hills Road, Scotts Valley,
California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576
These are supported by Agents and Distributors in major countries world-wide.
© GEC Plessey Semiconductors 1995 Publication No. DS3574-3.3 April 1995
TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to
be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only
and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any
equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose
failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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