LX1672-06CLQ-TR [MICROSEMI]
Multiple Output LoadSHARE PWM TM; 多路输出负载共享PWM TM
| 型号： | LX1672-06CLQ-TR |
| 厂家： | 
Microsemi |
| 描述： | Multiple Output LoadSHARE PWM TM |
| 文件： | 总20页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
KEY FEATURES
DESCRIPTION
Up to Three Independently
Regulated Outputs
The LX1672 is a highly integrated
This patented approach also gives
power supply controller IC featuring system designers maximum flexibility with
two PWM switching regulator stages respect to MOSFET supply. Each phase
with an additional onboard linear can utilize different supply voltages, for
DDR Termination Compliant
Bi-phase Current Sharing
Outputs As Low As 0.8V
Generated From An Internal 1%
Reference
Multiphase High Current Output
Reduces Required Capacitance
Integrated High Current MOSFET
Drivers
300KHz, 500KHz and 600KHz
High Frequency Operation
Minimizes External Component
Requirements
Independent Phase Programmable
Soft-Start and Power Sequencing
Adjustable Linear Regulator Driver
Output
regulator driver.
efficient use of available supplies, while
The two constant frequency voltage- programming the ratio of current pulled
mode PWM phases can be easily from each using one of three methods (see
configured as a single Bi-Phase high application section).
current output, two independently
regulated outputs, or as a DDR memory programmable
I/O supply with a tracking DDR capabilities.
termination voltage supply. Power loss configured to come up in any order
and noise, due to the ESR of the input necessary as required by the application.
capacitors, are minimized by operating
each PWM output 180° out of phase. Linear Regulator Driver output, which
This architecture also minimizes when coupled with an inexpensive
The LX1672 incorporates fully
soft-start
sequencing
Each output can be
The LX1672 features an additional
capacitor
maximizing regulator response.
requirements
while MOSFET is capable of supplying up to 5A
for I/O, memory, and other supplies
No current-sense resistors
In bi-phase operation, the high surrounding today’s micro-processor
current output utilizes a patented current designs.
APPLICATIONS/BENEFITS
sharing architecture, called Forced
Each regulator voltage output is
Current Sharing†, to allow accurate programmed via a simple voltage-divider
current sharing without the use of network. The LX1672, utilizing MOSFET
Multi-Output Power Supplies
Video Card Power Supplies
DDR, VDDQ and Termination
Supply
PC Peripherals
Portable PC Processor and I/O
Supply
expensive current sense resistors.
RDS(ON) impedance, monitors maximum
current limit conditions, in each PWM
phase without the use of expensive current
sense resistors.
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
† U.S Patents: 6,285,571,6,292,378
PRODUCT HIGHLIGHT
DDR Termination
Refer to Typical
Application for
Memory Core
....
complete circuit.
12V
5V
Graphics
Controller
Memory Bus
LX1672
DDR Memory
3.3V
I/O
PACKAGE ORDER INFO
Plastic TSSOP
28-Pin
Plastic MLPQ
38-Pin
Switching
Frequency (kHz)
PW
LQ
TA (°C)
RoHS Compliant / Pb-free Transition DC: 0518 RoHS Compliant / Pb-free Transition DC: 0512
0 to 70
0 to 70
0 to 70
300
500
600
LX1672-03CPW
LX1672-05CPW
LX1672-03CLQ
LX1672-06CLQ
NOTE: Available in Tape & Reel. Append the letters “TR” to the part number (i.e. LX1672-06CLQ-TR)
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 1
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
ABSOLUTE MAXIMUM RATINGS
PACKAGE PIN OUT
Supply Voltage (VCC) DC.................................................................-0.3V to 5.5V
Driver Supply Voltage (VCx, VCCL) DC ............................................-0.3V to 12V
Current Sense Inputs (VSX, CSX) ....................................................... -0.3V to 12V
Error Amplifier Inputs (FBX, RF2, LDFB)........................................-0.3V to 5.5V
Input Voltage (SS / Enable, LDDIS) .................................................-0.3V to5.5V
Output Drive Peak Current Source (HOx, LOx)....................................1A (500ns)
Output Drive Peak Current Sink (HOx, LOx) .......................................1A (500ns)
Operating Junction Temperature.................................................................. 150°C
Storage Temperature Range...........................................................-65°C to 150°C
Peak Package Solder Reflow Temp.(40 second max. exposure) .... 260°C (+0, -5)
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
HO2
LO2
PG2
VC2
VC1
HO1
LO1
PG1
VCCL
VCC
VS1
CS1
EO1
FB1
SS1
DIS1
VS2
3
4
LDGD
LDFB
LDDIS
DGND
AGND
DIS2
SS2
5
6
7
8
9
10
11
12
13
14
RF2
FB2
EO2
CS2
PW PACKAGE
(Top View)
Note: Exceeding these ratings could cause damage to the device. All voltages are with
respect to Ground. Currents are positive into, negative out of specified
terminal.
33
36 35
34
38 37
32
1
31
HO2
x= Denote Phases 1 & 2
N.C.
N.C.
2
3
4
5
VC2
LDGD
LDFB
LDDIS
DGND
AGND
RSVD
SS2
30
29
28
27
26
25
24
23
VCCL
VCC
DIS2
THERMAL DATA
6
7
Connect Bottom to
Power GND
DIS1
N.C.
Plastic TSSOP 28-Pin
PW
8
9
N.C.
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
85°C/W
PWGD
N.C.
10
22
21
20
RF2
11
12
FB2
N.C.
N.C.
EO2
13 14 15 16 17 18 19
Plastic MLPQ 38-Pin
LQ
35°C/W
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
(N.C. – No Internal Connection
N/U – Not Used)
Junction Temperature Calculation: TJ = TA + (PD x θJC).
The θJA numbers are guidelines for the thermal performance of the device/pc-board system.
All of the above assume no ambient airflow.
RoHS / Pb-free 100% Matte Tin Lead Finish
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 2
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
FUNCTIONAL PIN DESCRIPTION
NAME
DESCRIPTION
Bi-Phase Operation: Phase 1 and 2 Voltage Feedback
FB1
Single Phase Operation: Phase 1 Voltage Feedback – connected to the output through a resistor network to
set desired output voltage of Phase 1
EOX
Error Amplifier Output – Sets external compensation for the corresponding phase denoted by “X”.
Bi-phase Operation: Load Sharing Voltage Sense Feedback – Connect filtered phase 2 switching output (pre-
inductor) to FB2 to ensure proper current sharing between phase 1 and phase 2.
Single Phase Operation: Phase 2 Voltage Feedback – connected to the output through a resistor network (post
inductor) to set desired output voltage of Phase 2.
FB2
RF2
Bi-Phase Operation: Load Sharing Voltage Sense Feedback Reference – Sets reference for current sharing
control loop. Connecting filtered phase 1 switching output (pre-inductor) to REF2 forces average current in
phase 2 to be equal to phase 1.
Single Phase Operation: Phase 2 Voltage Reference – connected to SS2 pin as reference.
VCC
VCCL
LDFB
IC supply voltage (nominal 5V).
Power supply pin for all Low side drivers.
Low Dropout Regulator Voltage Feedback – Sets output voltage of external MOSFET via resistor network.
Over-Current Limit Set – Connecting a resistor between CS pin and the source of the high-side MOSFET sets the
current-limit threshold for the corresponding phase denoted by “X”. Exceeding the current-limit threshold forces
the corresponding phase into hiccup mode protection. A minimum of 1KΩ must be in series with this input.
CSX
SSX
Soft-start/Hiccup Capacitor Pin – During start-up, the voltage on this pin controls the output voltage of its
respective regulator. An internal 20kΩ resistor and the external capacitor set the time constant for soft-start
function. The Soft-start function does not initialize until the supply voltage exceeds the UVLO threshold. When
an over-current condition occurs, this capacitor is used for the timing of hiccup mode protection.
AGND
DGND
Analog ground reference.
Digital ground reference.
Low Dropout Regulator Gate Drive – Connects to gate of external N-Channel MOSFET for linear regulator
function.
LDGD
Driver Power Ground. Connects to the source of the bottom N-channel MOSFETS of phase 1 where X=1, and
phase 2 where X=2 for the TSSOP. The MLPQ package has a common PG output .
PGX
HOX
LOX
High Side MOSFET Gate Driver – “X” denotes corresponding phase.
Low Side MOSFET Gate Driver – “X” denotes corresponding phase.
Phase High-Side MOSFET Gate Driver Supply – Connect to separate supply or boot strap supply to ensure
VCX
proper high-side gate driver supply voltage. “X” denotes corresponding phase. If the phase is not used connect to
VCC.
LDDIS
LDO Disable input. High disables the LDO output. This pin has a 100KΩ nominal pull down resistor
Voltage reference for Current sense. This is also the supply pin for the Current Sense Comparator.
“X” denotes corresponding phase. This pin cannot be left floating, if the phase is not used connect to VCC
VSX
PWM Disable Input – High disables the PWM output. This pin has a nominal 80KΩ pull down resistor. “X”
denotes corresponding phase.
DISX
Open drain output , high at end of Soft Start and no Fault. Pulls low if any Fault condition occurs.
This output is present on the MLP package only.
PWGD
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 3
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 70°C except where
otherwise noted and the following test conditions: VCC = 5V, VCCL = 5V, VCX = 12V, HOX = LOX = 3000pF Load.
LX1672
Typ
Parameter
Symbol
Test Conditions
Units
Min
Max
SWITCHING REGULATORS
Input Voltage
Input Voltage
`
VCC
VCCL, VCX
ICC
4.5
5.5
12
V
V
mA
Operation Current
Static and Dynamic
10
TA = 25°C
0°C < TA < 70°C
0.792
0.784
-1
0.8
0.808
0.816
1
1
250
150
Reference Voltage
VSS
V
Line Regulation (Note 2)
Load Regulation (Note 2)
Minimum Pulse Width
Minimum Pulse Width
Maximum Duty Cycle
Maximum Duty Cycle
Maximum Duty Cycle
ERROR AMPLIFIERS
Input Offset Voltage
DC Open Loop Gain
Unity Gain Bandwidth
High Output Voltage
Low Output Voltage
Input Common Mode Range
Input Bias Current
%
%
nS
nS
%
-1
TSSOP Package
MLPQ Package
LX1672-03 Load = 3000pF
LX1672-05 Load = 3000pF
LX1672-06 Load = 3000pF
85
75
70
%
%
`
Vos
Common Mode Input Voltage = 1V
-6.0
6.0
mV
dB
MHz
V
mV
V
70
16
3.8
200
UGBW
VOH
VOL
I Source = 2mA
I Sink = 10µA
Input Offset Voltage < 20mV
0 and 3.5 V Common Mode Input Voltage
3.5
.1
400
3.5
IIN
100
nA
CURRENT SENSE
Current Sense Bias Current
Trip Threshold
Current Sense Delay
Current Sense Comparator
Operating Current
`
`
ISET
VTRIP
TCSD
VCSX = VVSX – 0.3V , VVSX = 5V
Referenced to VSX , VVSX = 5V
45
260
50
300
350
55
340
μA
mV
nS
ICSX
Current into VSX pins
2
5
mA
OUTPUT DRIVERS – N-CHANNEL MOSFETS
Low Side Driver Operating Current
High Side Driver Operating Current
Drive Rise Time, Fall Time
High Level Output Voltage
Low Level Output Voltage
OSCILLATOR
IVCCL
IVCX
TRF
VDH
VDL
Static
Static
2.5
3
50
11
0.15
mA
mA
nS
V
CL = 3000pF
ISOURCE = 20mA, VCCL = 12V
ISINK = 20mA, VCCL = 12V
10
0.25
V
`
PWM Switching Frequency
PWM Switching Frequency
PWM Switching Frequency
Ramp Amplitude
LX1672-03
LX1672-05
LX1672-06
255
425
510
300
500
600
1.25
345
575
690
KHz
KHz
KHz
VPP
FSW
VRAMP
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 4
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 70°C except where
otherwise noted and the following test conditions: VCC = 5V, VCCL = 5V, VCX = 12V, HOX = LOX = 3000pF Load
LX1672
Typ
Parameter
Symbol
Test Conditions
Units
Min
Max
UVLO AND SOFT-START (SS)
`
Start-Up Threshold (VCX), (VCCL
)
3.5
4.0
4.0
4.25
0.1
20
0.15
10
4.5
4.5
V
V
V
Start-Up Threshold (VCC
Hysteresis Vcc
)
SS Input Resistance
SS Shutdown Threshold
Hiccup Mode Duty Cycle
RSS
VSHDN
KΩ
V
%
CSS = 0.1μF
LINEAR REGULATOR CONTROLLER
Voltage Reference Tolerance
Source Current
Sink Current
DISABLE INPUT
`
`
VLDFB = 0.8V, COUT = 330µF
VOUT = 9V
VOUT = 0.4V
2
%
mA
mA
IHDRV
ILDRV
6
0.2
1.0
80
2.5
100
V
ΚΩ
V
PWM Disable
LDO Disable
DISX
Pull down Resistance
Pull down Resistance
LDDIS
KΩ
Note 1 – X = Phase 1,2
Note 2 – System Specification
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 5
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
BLOCK DIAGRAM
RSET
ISET
CS1
V in
+12V
CS Comp
-
IRESET
PWM
R2
R
Q
VC1
+
CIN
L1
VTRIP
ISET
VS1
R1
S
Q
V out 1
HO1
ESR
COUT
EO1
LO1
PG1
+5V
Error Comp
+
VCCL
Hiccup
-
-
FB1
+
Amplifier/
Compensation
VREF
+5V
16V
16V
20k
Ramp
Oscillator
UVLO
UVLO
VCC
S
F FAULT S
S
R
5.5V
TEMP
SS1
SS2
PWGD
(MLP Only)
DIS1
SS
CSS
Figure 1 – Block Diagram of PWM Phase 1
+12V
+V
LDGD
VC1
VREF
VOUT3
-
LDFB
+5V
LDDIS
Figure 2 – LDO Controller Block Diagram
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 6
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
BLOCK DIAGRAM
RSET
ISET
+5V
CS2
Vin
CS Comp
-
IRESET
PWM
R
Q
VC2
HO2
+
CIN
L2
VS2
EO2
VTRIP
ISET
S
Q
V out
2
ESR
COUT
LO2
PG2
LPF2
+5V
Error Comp
+
-
VCCL
Hiccup
-
FB2
RF2
+
Amplifier/
Compensation
VREF
+5V
16V
16V
20k
UVLO
Ramp
Oscillator
UVLO
LPF1
VCC
S
F FAULT S
R
5.5V
S
TEMP
SS1
SS2
PHASE1
SS
CSS
DIS 2
Figure 3– Block Diagram of Phase 2 Connected in LoadSHARE Mode
Note: With the MLPQ package there is only one PGX output (PG1 and PG2 are common)
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Integrated Products Division
Page 7
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
APPLICATION CIRCUIT
+12V
+5V
HO2
LO2
VC2
VC1
HO1
LO1
PG1
+
PG2
L1
LDGD
LDFB
+
+3.3V
+2.7V
+5V
+5V
LDDIS VCCL
DGND
AGND VS1
VCC
DIS2
SS2
RF2
FB2
EO2
CS1
EO1
FB1
1.5VDC
+3.3V
SS1
DIS1
+
CS2
VS2
+
L2
Figure 4 – Bi-Phase Operation With Phase 1 & 2 LoadSHARING™ From 5V & 3.3V
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Integrated Products Division
Page 8
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
APPLICATION CIRCUIT
+12V
+5V
HO2
LO2
VC2
VC1
HO1
LO1
PG1
+
PG2
L1
LDGD
LDFB
+
2.8VDC
+3.3V
+2.7V
+5V
+5V
LDDIS VCCL
DGND
AGND VS1
VCC
DIS2
SS2
RF2
FB2
EO2
CS1
EO1
FB1
SS1
DIS1
+5V
+
CS2
VS2
L2
+
1.40VDC
Figure 5 – Bi-Phase Operation with Phase 2 Output Tracking The Output of Phase 1.
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Integrated Products Division
Page 9
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
THEORY OF OPERATION
Hiccup is disabled during the soft-start interval, allowing start
GENERAL DESCRIPTION
up with maximum current. If the rate of rise of the output voltage
is too fast, the required charging current to the output capacitor
may be higher than the limit-current. In this case, the peak
MOSFET current is regulated to the limit-current by the current-
sense comparator. If the MOSFET current still reaches its limit
after the soft-start finishes, the hiccup is triggered again. When the
output has a short circuit the hiccup circuit ensures that the
average heat generation in both MOSFETs and the average current
is much less than in normal operation.
The LX1672 is a voltage-mode pulse-width modulation
controller integrated circuit.
frequency is fixed to 300kHz.
The internal ramp generator
The device has external
compensation, for more flexibility of output current magnitude.
UNDER VOLTAGE LOCKOUT (UVLO)
At power up, the LX1672 monitors the supply voltage for
VCC, VCCL, and VCX (there is no requirement for sequencing
the supplies). Before all supplies reach their under-voltage lock-
out (UVLO) thresholds, the soft-start (SS) pin is held low to
prevent soft-start from beginning, the oscillator is disabled and all
MOSFETs are held off. There is an internal delay that will filter
out transients less that 1.5µSec.
Over-current protection can also be implemented using a sense
resistor, instead of using the RDS(ON) of the upper MOSFET, for
greater set-point accuracy.
OSCILLATOR FREQUENCY
SOFT-START
An internal oscillator sets the PWM switching frequency at
300KHz, 500KHz, or 600KHz.
Once the supplies are above the UVLO threshold, the soft-start
capacitor begins to be charged by the reference through a 20kΩ
internal resistor. The capacitor voltage at the SS pin rises as a
simple RC circuit. The SS pin is connected to the error
amplifier’s non-inverting input that controls the output voltage.
The output voltage will follow the SS pin voltage if sufficient
charging current is provided to the output capacitor.
THEORY OF OPERATION FOR
CONFIGURATION
A
BI-PHASE, LOADSHARE
The basic principle used in LoadSHARING™, in a multiple
phase buck converter topology, is that if multiple, identical,
inductors have the same identical voltage impressed across their
leads, they must then have the same identical current passing
through them. The current that we would like to balance between
inductors is mainly the DC component along with as much as
possible the transient current. All inductors in a multiphase buck
converter topology have their output side tied together at the
output filter capacitors. Therefore, this side of all the inductors
have the same identical voltage.
The simple RC soft-start allows the output to rise faster at the
beginning and slower at the end of the soft-start interval. Thus,
the required charging current into the output capacitor is less at
the end of the soft-start interval. A comparator monitors the SS
pin voltage and indicates the end of soft-start when SS pin
voltage reaches 95% of VREF
.
OVER-CURRENT PROTECTION (OCP) AND HICCUP
If the input side of the inductors can be forced to have the same
equivalent DC potential on this lead, then they will have the same
DC current flowing. To achieve this requirement, phase 1 will be
the control phase that sets the output operating voltage, under
normal PWM operation. To force the current of phase 2 to be
equal to the current of phase 1, a second feedback loop is used.
Phase 2 has a low pass filter connected from the input side of each
inductor. This side of the inductors has a square wave signal that
is proportional to its duty cycle. The output of each LPF is a DC
(+ some AC) signal that is proportional to the magnitude and duty
cycle of its respective inductor signal. The second feedback loop
will use the output of the phase 1 LPF as a reference signal for an
error amplifier that will compare this reference to the output of the
phase 2 LPF. This error signal will be amplified and used to
control the PWM circuit of phase 2. Therefore, the duty cycle of
phase 2 will be set so that the equivalent voltage potential will be
forced across the phase 2 inductor as compared to the phase 1
inductor. This will force the current in the phase 2 inductor to
follow and be equal to the current in the phase 1 inductor.
The LX1672 uses the RDS(ON) of the upper MOSFET, together
with a resistor (RSET) to set the actual current limit point. The
current sense comparator senses the MOSFET current 350nS
after the top MOSFET is switched on in order to reduce
inaccuracies due to ringing. A current source supplies a current
(ISET), whose magnitude is 50µA. The set resistor RSET is
selected to set the current limit for the application. RSET and VSX
should be connected directly at the upper MOSFET drain and
source to get an accurate measurement across the low resistance
RDS(ON)
.
When the sensed voltage across RDS(ON) plus the set resistor
exceeds the 300mV, VTRIP threshold, the OCP comparator outputs
a signal to reset the PWM latch and to start hiccup mode. The
soft-start capacitor (CSS) is discharged slowly (10 times slower
than when being charged up by RSS). When the voltage on the SS
pin reaches a 0.1V threshold, hiccup finishes and the circuit soft-
starts again. During hiccup both MOSFETs for that phase are
held off.
There are four methods that can be used to implement the
LoadSHARE feature of the LX1672 in the Bi-Phase mode of
operation.
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 10
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
THEORY OF OPERATION (CONTINUED)
BI-PHASE, LOADSHARE ( ESR METHOD)
BI-PHASE, LOADSHARE ( FEEDBACK DIVIDER METHOD)
The first method is to change the ratio of the inductors
equivalent series resistance, (ESR). As can be seen in the previous
example, if the offset error is zero and the ESR of the two
inductors are identical; then the two inductor currents will be
identical. To change the ratio of current between the two
inductors, the value of the inductor’s ESR can be changed to allow
more current to flow through one inductor than the other. The
inductor with the lower ESR value will have the larger current.
The inductor currents are directly proportional to the ratio of the
inductor’s ESR value.
Sometimes it is desirable to use the same inductor in both phases
while having a much larger current in one phase versus the other. A
simple resistor divider can be used on the input side of the Low Pass
Filter that is taken off of the switching side of the inductors. If the
Phase 2 current is to be larger than the current in Phase 1; the resistor
divider is placed in the feedback path before the Low Pass Filter that
is connected to the Phase 2 inductor. If the Phase 2 current needs to
be less than the current in Phase 1; the resistor divider is then placed
in the feedback path before the Low Pass Filter that is connected to
the Phase 1 inductor.
The following circuit description shows how to select the
inductor ESR for each phase where a different amount of power is
taken from two different input power supplies. A typical setup will
have a +5V power supply connected to the phase 1 half bridge
driver and a +3.3V power supply connected to the phase 2 half
bridge driver. The combined power output for this core voltage is
18W (+1.5V @ 12A). For this example the +5V power supply will
supply 7W and the +3.3V power supply will supply the other 11W.
7W @ 1.5V is a 4.67A current through the phase 1 inductor. 11W
As in Figure 7, the millivolts of DC offset created by the resistor
divider network in the feedback path, appears as a voltage generator
between the ESR of the two inductors.
A divider in the feedback path from Phase 2 will cause the
voltage generator to be positive at Phase 2. With a divider in the
feedback path of Phase 1 the voltage generator becomes positive at
Phase 1. The Phase with the positive side of the voltage generator
will have the larger current. Systems that operate continuously
above a 30% power level can use this method, a down side is that
that the current difference between the two inductors still flows
during a no load condition.
@ 1.5V is a 7.33A current through the phase 2 inductor.
The
ratio of inductor ESR is inversely proportional to the power level
ESR1 I2
split.
=
This produces a low efficiency condition during a no load or light
load state, this method should not be used if a wide range of output
power is required.
ESR2 I1
The higher current inductor will have the lower ESR value. If
the ESR of the phase 1 inductor is selected as 10mΩ, then the ESR
value of the phase 2 inductor is calculated as:
The following description and Figure 8 show how to determine
the value of the resistor divider network required to generate the
offset voltage necessary to produce the different current ratio in the
two output inductors. The power sharing ratio is the same as that of
Figure 7. The Offset Voltage Generator is symbolic for the DC
voltage offset between Phase 1 & 2. This voltage is generated by
small changes in the duty cycle of Phase 2. The output of the LPF is
a DC voltage proportional to the duty cycle on its input. A small
amount of attenuation by a resistor divider before the LPF of Phase 2
will cause the duty cycle of Phase 2 to increase to produce the added
offset at V2. The high DC gain of the error amplifier will force
LPF2 to always be equal to LPF1. The following calculations
determine the value of the resistor divider necessary to satisfy this
example.
4.67A
⎛
⎜
⎝
⎞
⎟
⎠
×10 mΩ = 6.4 mΩ
7.33A
Depending on the required accuracy of this power sharing;
inductors can be chosen from standard vendor tables with an ESR
ratio close to the required values. Inductors can also be designed
for a given application so that there is the least amount of
compromise in the inductor’s performance.
+5V @ 7W
L1
4.67A
VOUT
10mΩ
6.4mΩ
1.5V +
46.7mV
1.5V @ 12A
18W
L2
7.33A
+3.3V @ 11W
Figure 7 – Ratio LoadSHARE™ Using Inductor ESR
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 11
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
THEORY OF OPERATION (CONTINUED)
.
+5V @ 7W
L1,
Switch
Side
Phase 2
1.5V
ESR L1
10mΩ
V1
4.67A
Error Amp
+46.7mV
100
62k
LPF1
Phase 1
PW M
Input
Not
Used
4700pF
Resistor
Divider
-
Offset
Voltage
-
Vout1
1.5V @ 12A
18W
Generator
+
L2,
Switch
Side
Resistor
Divider
62k
62k
LPF2
ESR L2
10mΩ
100
V2
1.5V
+73.3mV
4700pF
TBD
7.33A
Phase 2
+3.3V @ 11W
Figure 8 – LoadSHARE™ Using Feedback Divider Offset
V1
K ×100
K =
Where V1 = 1.5467 ; V2 = 1.5733 and
then TBD =
= 5.814 K
1 − K
V 2
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 12
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
THEORY OF OPERATION (CONTINUED)
Also a speed up capacitor can be used between the offset
amplifier output and the negative input of the Phase 2 error
amplifier. This will improve the transient response of the Phase 2
output current, so that it will share more equally with phase 1
current during a transient condition.
BI-PHASE, LOADSHARE™ ( PROPORTIONAL METHOD)
The best topology for generating a current ratio at full load and
proportional between full load and no load is shown in figure 9.
The DC voltage difference between LPF1 and VOUT is a voltage
that is proportional to the current flowing in the Phase 1 inductor.
This voltage can be amplified and used to offset the voltage at
LPF2 through a large impedance that will not significantly alter
the characteristics of the low pass filter. At no load there will be
no offset voltage and no offset current between the two phases.
This will give the highest efficiency at no load.
The use of a MOSFET input amplifier is required for the buffer
to prevent loading the low pass filter. The gain of the offset
amplifier, and the value of Ra and Rb, will determine the ratio of
currents between the phases at full load. Two external amplifiers are
required or this method.
L1,
Switch
Side
Offset Amp
62k
LPF1
Rin
Vos
+5V @ 7W
-
ESR L1
10mΩ
Rf
-
1.5V
+46.7mV
4.67A
V1
4700pF
Phase 1
Phase 2
Error Amp
PWM
Input
-
Offset
Voltage
Generator
RF2
-
Vout
1.5V @ 12A
18W
+
L2,
Switch
Side
FB2
62k
62k
LPF2
ESR L2
10mΩ
V2
Ra
1.5V
+73.3mV
7.33A
4700pF
Phase 2
Rb
1M
+3.3V @ 11W
Figure 9 –LoadSHARE™ Using Proportional Control
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 13
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
THEORY OF OPERATION (CONTINUED)
The circuit in Figure 9 sums a current through a 1MΩ resistor
(Rb) offsetting the phase 2 error amplifier to create an imbalance
in the L1 and L2 currents. Although there are many ways to
calculate component values the approach taken here is to pick Ra,
Rb, RIN, VOUT, and inductor ESR. A value for the remaining
resistor Rf can then be calculated.
BI-PHASE, LOADSHARE™ (SERIES RESISTOR METHOD)
A fourth but less desirable way to produce the ratio current
between the two phases is to add a resistor in series with one of the
inductors. This will reduce the current in the inductor that has the
resistor and increase the current in the inductor of the opposite
phase. The example of Figure 7 can be used to determine the
current ratio by adding the value of the series resistor to the ESR
value of the inductor. The added resistance will lower the overall
efficiency
The first decision to be made is the current sharing ratio,
follow the previous examples to understand the basics of
LoadSHARE™. The most common reason to imbalance the
current in the two phases is because of limitations on the
available power from the input rails for each phase. Use the
available input power and total required output power to
determine the inductor currents for each phase.
LoadSHARE ERROR SOURCES
With the high DC feedback gain of this second loop, all phase
timing errors, RDS(On) mismatch, and voltage differences across the
half bridge drivers are removed from the current sharing accuracy.
The errors in the current sharing accuracy are derived from the
tolerance on the inductor’s ESR and the input offset voltage
specification of the error amplifier. The equivalent circuit is shown
next for an absolute worst case difference of phase currents
between the two inductors.
All references are to Figure 9
1) Calculate the voltages V1 and V2.
V1 = L1Current× L1ESR+ Vout
V 2 = L 2 Current× L 2 ESR+ Vout
2) Select values for Ra and Rb (Ra is typically 62KΩ ; Rb
is typically 1MΩ)
ESR L1
V1
3) Calculate the offset voltage Vos at the output of the offset
amplifier
VOUT
-
Offset
Error
5mV
Phase 1
V 2 − V1
⎛
⎜
⎝
⎞
⎟
⎠
ESR L2
+
Vos = V 2 −
×
(
Ra+ Rb
)
V2
Ra
Phase 2
Figure 6 – Error Amplitude
4) Calculate the value for Rf
(select a value for RIN typically 5KΩ)
Nominal ESR of 6mΩ. ESR ±5%
Max offset Error = 6mV
+5% ESR L1 = 6.3 mΩ
⎛
⎞
Vos − VOUT
VOUT − V1
⎜
⎜
⎟
⎟
Rf = RIN
⎝
⎠
-5% ESR L2 = 5.7 mΩ
Due to the high impedances in this circuit layout can affect the
actual current ratio by allowing some of the switching waveforms
to couple into the current summing path. It may be necessary to
make some adjustment in Rf after the final layout is evaluated.
Also, the equation for Rf requires very accurate numbers for the
voltages to insure an accurate result.
V1- VOUT
If phase1current =12 A =
ESRL1
V1 − VOUT = 12 × 6.3×10−3 = 75.6 mV
V2 = V1+ 6mV = 81.6mV
V2 - VOUT 81.6x10−3
Phase 2 current =
=
= 14.32A
5.7x10−3
ESR L2
Phase 2 current is 2.32A greater than Phase 1.
Input bias current also contributes to imbalance.
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 14
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
APPLICATION NOTE
OUTPUT INDUCTOR
OUTPUT CAPACITOR
The output inductor should be selected to meet the
requirements of the output voltage ripple in steady-state operation
and the inductor current slew-rate during transient. The peak-to-
peak output voltage ripple is:
The output capacitor is sized to meet ripple and transient
performance specifications. Effective Series Resistance (ESR) is a
critical parameter. When a step load current occurs, the output
voltage will have a step that equals the product of the ESR and the
current step, ΔI. In an advanced microprocessor power supply, the
output capacitor is usually selected for ESR instead of capacitance
or RMS current capability. A capacitor that satisfies the ESR
requirements usually has a larger capacitance and current capability
than strictly needed. The allowed ESR can be found by:
VRIPPLE = ESR× IRIPPLE
where
VIN − VOUT
D
ΔI =
×
L
f s
ESR×
IRIPPLE + ΔI < VEX
)
Where IRIPPLE is the inductor ripple current, ΔI is the maximum
load current step change, and VEX is the allowed output voltage
excursion in the transient.
ΔI is the inductor ripple current, L is the output inductor value
and ESR is the Effective Series Resistance of the output
capacitor.
ΔI should typically be in the range of 20% to 40% of the
maximum output current. Higher inductance results in lower
output voltage ripple, allowing slightly higher ESR to satisfy the
transient specification. Higher inductance also slows the inductor
current slew rate in response to the load-current step change, ΔI,
resulting in more output-capacitor voltage droop. When using
electrolytic capacitors, the capacitor voltage droop is usually
negligible, due to the large capacitance
Electrolytic capacitors can be used for the output capacitor, but
are less stable with age than tantalum capacitors. As they age, their
ESR degrades, reducing the system performance and increasing the
risk of failure. It is recommended that multiple parallel capacitors
be used, so that, as ESR increase with age, overall performance
will still meet the processor’s requirements.
There is frequently strong pressure to use the least expensive
components possible; however, this could lead to degraded long-
term reliability, especially in the case of filter capacitors.
Microsemi’s demonstration boards use the CDE Polymer AL-EL
(ESRE) filter capacitors, which are aluminum electrolytic, and
have demonstrated reliability. The OS-CON series from Sanyo
generally provides the very best performance in terms of long term
ESR stability and general reliability, but at a substantial cost
penalty. The CDE Polymer AL-EL (ESRE) filter series provides
excellent ESR performance at a reasonable cost. Beware of off-
brand, very low-cost filter capacitors, which have been shown to
degrade in both ESR and general electrolytic characteristics over
time.
The inductor-current rise and fall times are:
ΔI
TRISE = L×
(
V − VOUT
)
IN
and
ΔI
TFALL = L×
VOUT
The inductance value can be calculated by
VIN − VOUT
ΔI
D
L =
×
f s
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 15
Integrated Products Division
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LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
APPLICATION NOTE (CONTINUED)
Values of Css equal to .1µF or greater are unlikely to result in
INPUT CAPACITOR
saturation of the output inductor unless very large output capacitors
are used..
The input capacitor and the input inductor, if used, are to filter
the pulsating current generated by the buck converter to reduce
interference to other circuits connected to the same 5V rail. In
addition, the input capacitor provides local de-coupling for the
buck converter. The capacitor should be rated to handle the RMS
current requirements. The RMS current is:
OVER-CURRENT PROTECTION
Current limiting occurs at current level ICL when the voltage
detected by the current sense comparator is greater than the current
sense comparator threshold, VTRIP (300mV).
IRMS = IL d(1 − d)
ICL × RDS(ON) + ISET × RSET = VTRIP
Where IL is the inductor current and d is the duty cycle. The
maximum value occurs when d = 50%, then IRMS =0.5IL. For 5V
input and output in the range of 2 to 3V, the required RMS
current is very close to 0.5IL.
So,
VTRIP − ICL × RDS(ON)
300 mV− ICL × RDS(ON)
RSET
=
=
ISET
50µA
SOFT-START CAPACITOR
Example:
The value of the soft-start capacitor determines how fast the
output voltage rises and how large the inductor current is required
to charge the output capacitor. The output voltage will follow the
voltage at the SS pin if the required inductor current does not
exceed the maximum allowable current for the inductor. The SS
pin voltage can be expressed as:
For 10A current limit, using FDS6670A MOSFET (10mΩ
DS(ON)):
R
0.3 −10× 0.010
RSET
=
= 4KΩ
50×10−6
Note: Maximum RSET is 6KΩ. Any resistor 6KΩ or greater will not
allow startup since ICL will equal zero (50µA x 6KΩ = 300mV).
SSCSS
VSS = V ref
1 − e− t/R
At higher PWM frequencies or low duty cycles, where the upper
gate drive is less than 350nS wide, the 350nS delay for current
limit enable may result in current pulses exceeding the desired
current limit set point. If the upper MOSFET on time is less than
350nS and a short circuit condition occurs the duty cycle will
increase, since VOUT will be low. The current limit circuit will be
enabled when the upper gate drive exceeds 350nS although the
actual peak current limit value will be higher than calculated with
the above equation.
Where RSS and CSS are the soft-start resistor and capacitor.
The current required to charge the output capacitor during the soft
start interval is.
dVss
Iout = Cout
dt
Taking the derivative with respect to time results in
VrefCout
RssCss
SSCSS
Iout =
e−t/R
Short circuit protection still exists due to the narrow pulse width
even though the magnitude of the current pulses will be higher than
the calculated value.
and at t=0
VrefCout
RssCss
If OCP is not desired connect both VSX and VCX to VCC. Do not
leave them floating.
Imax =
The required inductor current for the output capacitor to follow
the soft start voltage equals the required capacitor current plus the
load current. The soft-start capacitor should be selected to
provide the desired power on sequencing and insure that the
overall inductor current does not exceed its maximum allowable
rating.
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 16
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
APPLICATION NOTE (CONTINUED)
The LX1672 can supply both voltages by using two of the three
OUTPUT DISABLE
PWM phases. Since the currents for VTT and (VDD plus VDDQ)
are quite often several amps, (2A to 6A is common) a switching
regulator is a logical choice
The LX1672 PWM MOSFET driver outputs are shut off by
pulling the disable (DISX) pins above 1.2V.
The LDO voltage regulator has its own Disable pin (LDDIS)
for control of this output voltage. Pulling this pin above 3V
disables the LDO.
VTT for DDR memory can be generated with the LX1672 by
using the positive input of the phase 2 error amplifier RF2 as a
reference input from an external reference voltage VREF which is
defined as one half of VDDQ. Using VREF as the reference input
will insure that all voltages are correct and track each other as
specified in the JEDEC (EIA/JESD8-9A) specification. The phase
2 output will then be equal to VREF and track the VDDQ supply as
required.
PROGRAMMING THE OUTPUT VOLTAGE
The output Voltage is sensed by the feedback pin (FBX) which
is compared to a 0.8V reference. The output voltage can be set to
any voltage above 0.8V (and lower than the input voltage) by
means of a resistor divider R1 - R2 (see Figure 1).
When an external reference is used the Soft Start will not be
functional for that phase.
VOUT = VREF (1+ R1/R2 )
See Microsemi Application Note 17 for more details.
Note: Keep R1 and R2 close to 1kΩ (order of magnitude)
DDR VTT TERMINATION VOLTAGE
Double Data Rate (DDR) SDRAM requires a termination
voltage (VTT) in addition to the line driver supply voltage
(VDDQ) and receiver supply voltage (VDD). Although it is not a
requirement VDD is generally equal to VDDQ; so that only VTT
and VDDQ are required..
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 17
Integrated Products Division
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LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
APPLICATION NOTE CONSIDERATIONS
1. The power N-MOSFET transistor’s total gate charge spec,
(Qg) should not exceed 40Nc when VCx = +12V. This
condition will guarantee operation over the specified ambient
temperature range. The Qg value of the N-MOSFET is
directly related to the amount of power dissipation inside the
IC package, from the two sets of MOSFET drivers. The
equation relating Qg to the power dissipation of a MOSFET
driver is: Pd = f * Qg * Vd . f = 300KHs and Vd is the
supply voltage for the MOSFET driver. The two bottom
MOSFET drivers are powered by the VCCL pin that is
connected to +5V. The upper MOSFET drivers can be
connected to the +12V supply or to a bootstrap supply
generated by its output bridge. The bootstrap supply will be at
4. When phases 1 and 2 are used in the Bi-phase mode to current
share into the same output load, the phase 2 current is forced to
follow the phase 1 current. It is important to use a larger soft-
start capacitor on phase 2 than phase 1 so that the phase 1
current becomes active before phase 2 becomes active. This will
minimize any start up transient. It is also important to disable
phase 1 and 2 at the same time. Disabling phase 1 without
disabling phase 2, in the Bi-phase mode, allows phase 2 to turn
on and off randomly because it has lost its reference.
5. The minimum RSET resistor value is 1k ohm for the current
limit sensing. If this resistor becomes shorted, it will do
permanent damage to the IC.
6. A resistor has been put in series with the gate of the LDO pass
transistor to reduce the output noise level. The resistor value
can be changed to optimize the output transient response versus
output noise.
+17V.
Depending on the thermal environment of the
application circuit, the Qg value of the N-MOSFETs will have
to be less than the 40nC value. A typical configuration of the
input voltage rails to generate the output voltages required is
having the 5volt supply on phase 1 and the 3.3 volt supply on
phase 2. At the max Qg value, the two bottom MOSFET
drivers will dissipate 60mw each. The upper MOSFET drivers
for phases 1 and 2 operate off of +12volts. Their dissipation
is 144mw each. The total power dissipation for gate drive is
408 mw. Icc x Vcc =15ma x 5 V= 75mW. Total package
power dissipation = 483mW. Using the thermal equation of:
TJ = TA + Pd * Oja, the Junction temperature for this IC
package is = 23 + .483 * 85 which = 64°C. This means that
the ambient temperature rise has to be less than 86°C.
7. The LDO controller inside the IC uses the voltage at VC1 as
the drive voltage. Due to noise considerations ideally the
voltage on the VC1 pin would be a fixed +12volt supply. When
VC1 is connected to a bootstrap supply the LDO output will
reflect significant switching noise without filtering.
8. To delay the turn on of the LDO controller output, a capacitor
should be connected between the LDDIS pin and the +5volts.
The LDDIS input has a 100K pull down resistor, which keeps
the LDO active until this pin is pulled high. During the power
up sequence the capacitor connected to the LDDIS pin will keep
the LDO off until this capacitor, being charge by the 100K pull
down resistor, goes through the low input threshold level.
2. The Soft-Start reference input has a 300mv threshold, above
which the PWM starts to operate. The internal operating
reference level is set at 800mV. This means that the output
voltage is 37.5% low when the PWM becomes active. This
starts each phase up in the current limit mode without Hiccup
operation. If more than one phase is using the 5volt rail for
conversion, then their soft-start capacitor values should be
changed so that the two phases do not start up together. This
will help reduce the amount of 5 volt input capacitance
required. Also the VCC pin and the VCCL pin should be kept
separated and should be decoupled separately. This will
prevent the VCC pin from drooping back below the UVLO set
point during start up.
3. If a phase is not used connect VSX and VCX pins to VCC.
Do not leave them floating. A floating VSX pin will result in
operation resembling a hiccup condition.
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Page 18
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
PACKAGE DIMENSIONS
28-Pin Thin Small Shrink Outline (TSSOP)
PW
MILLIMETERS
INCHES
Dim
MIN
0.85
0.19
0.09
9.60
4.30
MAX
0.95
0.30
0.20
9.80
4.50
MIN
MAX
0.037
0.012
0.008
0.390
.176
3 2 1
A
B
C
D
E
0.033
0.007
0.003
0.378
0.169
P
E
F
F
G
H
L
M
0.65 BSC
0.025 BSC
D
0.05
–
0.15
1.10
0.75
8°
0.002
–
0.005
0.043
0.030
8°
A
H
L
SEATING PLANE
0.50
0.020
B
C
G
M
0°
0°
P
*LC
6.25
–
6.50
0.10
0.246
–
0.256
0.004
LQ
38-Pin Thin Micro Lead Quad Package (MLPQ)
D
MILLIMETERS
INCHES
Dim
MIN
MAX
MIN
MAX
A
B
C
0.20 REF
0.0078 REF
E
0.18
0.18
0.30
0.18
0.007
0.007
0.011
0.007
D
5.00 BSC
.196 BSC
P
F
E
F
G
H
I
3.00
5.00
0.50 BSC
0
0.70
3.25
5.25
0.118
0.196
0.019 BSC
0.127
0.206
3
2
0.05
0.80
0
0.19
0.031
0.027
1
C
P
7.00 BSC
0.275 BSC
G
C
I
B
A
H
Note: Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(0.006”) on any side. Lead dimension shall
not include solder coverage.
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Integrated Products Division
Page 19
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1672
®
Multiple Output LoadSHARE™ PWM
TM
PRODUCTION DATA SHEET
NOTES
PRODUCTION DATA – Information contained in this document is proprietary to
Microsemi and is current as of publication date. This document may not be modified in
any way without the express written consent of Microsemi. Product processing does not
necessarily include testing of all parameters. Microsemi reserves the right to change the
configuration and performance of the product and to discontinue product at any time.
Copyright © 2000
Rev. 1.0, 2005-08-10
Microsemi
Integrated Products Division
Page 20
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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MICROSEMI
LX1673-03CPW-TR
Switching Controller, Voltage-mode, 1A, 345kHz Switching Freq-Max, PDSO20, ROHS COMPLIANT, PLASTIC, TSSOP-20
MICROSEMI
LX1673-06CLQ-TR
Switching Controller, Voltage-mode, 1A, 690kHz Switching Freq-Max, PQCC20, ROHS COMPLIANT, PLASTIC, MLPQ-20
MICROSEMI
LX1673-06CLQT
Switching Controller, Voltage-mode, 1A, 690kHz Switching Freq-Max, PQCC20, PLASTIC, MLPQ-20
MICROSEMI
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