LE79R70-1DJCT [MICROSEMI]

SLIC, 2-4 Conversion, Bipolar, PQCC32, GREEN, PLASTIC, MS-016, LCC-32;


型号：	LE79R70-1DJCT
厂家：	Microsemi
描述：	SLIC, 2-4 Conversion, Bipolar, PQCC32, GREEN, PLASTIC, MS-016, LCC-32 电池电信电信集成电路
文件：	总22页 (文件大小：465K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

™

Le79R70

Ringing Subscriber Line Interface Circuit

VE580 Series

APPLICATIONS

Integrated Access Devices (IADs)

Network Interface Units (NIUs)

Cable Modems

DSL Modems

Set Top / House Side Boxes

Intelligent PBX

ORDERING INFORMATION

Device¹

Package Type^{2, 3}

Packing⁴

Tube

32-pin PLCC, No Pol. Rev.

(Green package)

Le79R70DJC

32-pin PLCC, Pol. Rev.

(Green package)

32-pin QFN, Pol. Rev.

(Green package)

Le79R70-1DJC

Le79R70-1FQC

Tube

Tray

1. Zarlink reserves the right to fulfill all orders for this device with

parts marked with the "Am" part number prefix until all inventory

bearing this mark has been depleted. Note that parts marked with

either the "Am" or the "Le" part number prefix are equivalent

devices in terms of form, fit, and function—the prefix appearing on

the topside mark is the only difference.

Pain Gain

FXS Cards

Voice over ISDN or T1/E1

Smart Residential Gateways

WLL, APON, FITL, NGN, and all other short-loop CPE/

2. The green package meets RoHS Directive 2002/95/EC of the

European Council to minimize the environmental impact of

electrical equipment.

Enterprise telephony applications

FEATURES

Ideal for ISDN-TA and set top applications

On-chip ringing with on-chip ring-trip detector

Low Standby state power

3. Due to size constraints, QFN devices are marked by omitting the

“Le” prefix and the performance grade dash character. For

example, Le79R70-1QC is marked 79R701QC.

4. For delivery using a tape and reel packing system, add a "T" suffix

to the OPN (Ordering Part Number) when placing an order.

Battery operation:

— VBAT1: –40 V to –67 V

— VBAT2: –19 V to VBAT1

On-chip battery switching and feed selection

On-hook transmission

Polarity reversal option

Programmable constant-current feed

Programmable open circuit voltage

Programmable loop-detect threshold

Current gain = 1000

Two-wire impedance set by single component

Ground-key detector

DESCRIPTION

The Le79R70 Ringing Subscriber Line Interface Circuit

(RSLIC) device is a bipolar monolithic SLIC that offers on-chip

ringing. Designers can achieve significant cost reductions at

the system level for short-loop applications by integrating the

ringing function on chip. Examples of such applications would

be ISDN Terminal Adaptors and set top boxes. Using a CMOS-

compatible input waveform and wave shaping R-C network,

the Le79R70 Ringing SLIC device can provide trapezoidal

wave ringing to meet various design requirements.

Tip Open state for ground-start lines

Internal VEE regulator (no external –5 V power supply

required)

Two on-chip relay drivers and snubber circuits

Space-saving package options (8x8 QFN)

See the Le79R70 Block Diagram, on page 3.

RELATED LITERATURE

080917 VE790 Series RSLIC Device Product Brief

080158 Le79R70/79/100/101 Ringing SLIC Devices

Technical Overview

080255 Le71HE0040J Evaluation Board User’s Guide

080753 Le58QL02/021/031 QLSLAC™ Data Sheet

Document ID#: 080211 Date:

Sep 19, 2007

Rev:

Version:

Distribution:

Public Document

Le79R70

Data Sheet

TABLE OF CONTENTS

Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Relay Driver Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Ring-Trip Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Test Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

32-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Revision A to B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Revision B to C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Revision C to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Revision D to E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Revision E to F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Revision F to G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Revision G1 to H1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Revision H1 to I1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Revision I1 to J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Revision J1 to J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

PRODUCT DESCRIPTION

The Zarlink family of subscriber line interface circuit (SLIC) products provide the telephone interface functions required

throughout the worldwide market. Zarlink SLIC devices address all major telephony markets including central office (CO),

private branch exchange (PBX), digital loop carrier (DLC), fiber-in-the-loop (FITL), radio-in-the-loop (RITL), hybrid fiber coax

(HFC), and video telephony applications.

The Zarlink SLIC devices offer support of BORSHT (battery feed, over voltage protection, ringing, supervision, hybrid, and test)

functions with features including current limiting, on-hook transmission, polarity reversal, tip-open, and loop-current detection.

These features allow reduction of line card cost by minimizing component count, conserving board space, and supporting

automated manufacturing.

The Zarlink SLIC devices provide the two- to four-wire hybrid function, DC loop feed, and two-wire supervision. Two-wire

termination is programmed by a scaled impedance network. Transhybrid balance can be achieved with an external balance

circuit or simply programmed using a companion Zarlink codec/filter, such as the Le58QL0xx Quad SLAC (QLSLAC™) device.

The Le79R70 Ringing SLIC device is a bipolar monolithic SLIC that offers on-chip ringing. Now designers can achieve significant

cost reductions at the system level for short-loop applications by integrating the ringing function on chip. Examples of such

applications would be ISDN Terminal Adaptors and set top boxes. Using a CMOS-compatible input waveform and wave shaping

R-C network, the Le79R70 Ringing SLIC can provide trapezoidal wave ringing to meet various design requirements.

In order to further enhance the suitability of this device in short-loop, distributed switching applications, Zarlink has maximized

power savings by incorporating battery switching on chip. The Le79R70 Ringing SLIC device switches between two battery

supplies such that in the Off-hook (active) state, a low battery is used to save power. In order to meet the Open Circuit voltage

requirements of fax machines and maintenance termination units (MTU), the SLIC automatically switches to a higher voltage in

the On-hook (standby) state.

Like all of the Zarlink SLIC devices, the Le79R70 Ringing SLIC device supports on-hook transmission, ring-trip detection and

programmable loop-detect threshold. The Le79R70 Ringing SLIC device is a programmable constant-current feed device with

two on-chip relay drivers to operate external relays. This unique device is available in the proven Zarlink 75 V bipolar process.

Figure 1. Le79R70 Block Diagram

Relay

RYOUT2

RYE

Driver

RTRIP1

RTRIP2

Relay

Driver

RYOUT1

A(TIP)

HPA

Ring-Trip

Detector

Input Decoder

and Control

Ground-Key

Detector

Two-Wire

Interface

Off-Hook

Detector

DET

HPB

B(RING)

VBAT2

VBAT1

VTX

RSN

Signal

Transmission

Power-Feed

Controller

RINGIN

RDC

RDCR

RSGL

RSGH

B2EN

Switch

Driver

VCC VNEG BGND AGND/DGND

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

CONNECTION DIAGRAM

32 31 30

RYE

RTRIP1

RTRIP2

HPB

RYOUT1

B2EN

VBAT1

HPA

32-Pin PLCC

RINGIN

RDCR

VTX

VNEG

RSN

DET

14 15 16 17 18 19 20

32 31

30 29

28 27

26 25

RYE

RTRIP2

HPB

RYOUT1

B2EN

HPA

VBAT1

RINGIN

32-pin QFN

RDCR

VTX

VNEG

RSN

Exposed Pad

11 12

13 14

15 16

Notes:

1. Pin 1 is marked for orientation.

2. NC = No connect

3. RSVD = Reserved. Do not connect to this pin.

4. The thermally enhanced QFN package features an exposed pad on the underside which must be electrically tied to VBAT1.

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

Pin Descriptions

Pin Names

AGND/DGND

A(TIP)

Type

Description

Gnd

Analog and digital ground are connected internally to a single pin.

Output of A(TIP) power amplifier.

Output

V_BAT2enable. Logic Low enables operation from V_BAT2. Logic High enables operation from V_BAT1. TTL

compatible.

B2EN

Input

BGND

B(RING)

C3–C1

Gnd

Battery (power) ground

Output of B(RING) power amplifier.

Decoder. TTL compatible. C3 is MSB and C1 is LSB.

Relay1 control. TTL compatible. Logic Low activates the Relay1 relay driver.

(Option) Relay2 control. TTL compatible. Logic Low activates the Relay2 relay driver.

Output

Input

Detector. Logic Low indicates that the selected detector is tripped. Logic inputs C3–C1 and E1 select the

DET

Output

Input

detector. Open-collector with a built-in 15 kΩ pull-up resistor.

(Option) A logic High selects the off-hook detector. A logic Low selects the ground-key detector. TTL

compatible.

HPA

HPB

Capacitor

Resistor

High-pass filter capacitor. A(TIP) side of high-pass filter capacitor.

High-pass filter capacitor. B(RING) side of high-pass filter capacitor.

Detect resistor. Threshold modification and filter point for the off-hook detector.

DC feed resistor. Connection point for the DC-feed current programming network, which also connects to the

receiver summing node (RSN). V_RDCis negative for normal polarity and positive for reverse polarity.

RDC

Resistor

—

RDCR

RINGIN

RSGH

Connection point for feedback during ringing.

Ring Signal Input. Pin for ring signal input. Square-wave shaped by external RC filter. Requires 50% duty

cycle. CMOS-compatible input.

Input

Saturation Guard High. Pin for resistor to adjust Open Circuit voltage when operating from V_BAT1

Saturation Guard Low. Pin for resistor to adjust the anti-saturation cut-in voltage when operating from both

_{BAT1 and}V_BAT2

RSGL

Input

The metallic current (AC and DC) between A(TIP) and B(RING) is equal to 1000 x the current into this pin.

The networks that program receive gain, two-wire impedance, and feed resistance all connect to this node.

Ring-trip detector. Ring-trip detector threshold set and filter pin.

Ring-trip detector threshold offset (switch to V_BAT1). For power conservation in any non-ringing state, this

switch is open.

RSN

Input

RTRIP1

RTRIP2

Common Emitter of RYOUT1/RYOUT2. Emitter output of RYOUT1 and RYOUT2. Normally connected to

relay ground.

RYE

Output

RYOUT1

RYOUT2

VBAT1

VBAT2

VCC

Output

Battery

Power

Relay/switch driver. Open-collector driver with emitter internally connected to RYE.

(Option) Relay/switch driver. Open-collector driver with emitter internally connected to RYE.

Battery supply and connection to substrate.

Power supply to output amplifiers. Connect to off-hook battery through a diode.

Positive analog power supply.

VNEG

Negative analog power supply. This pin is the return for the internal VEE regulator.

Transmit Audio. This output is a 0.5066 gain version of the A(TIP) and B(RING) metallic AC voltage. VTX also

sources the two-wire input impedance programming network.

This must be electrically tied to VBAT1.

VTX

Output

Battery

Exposed Pad

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above

these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

Storage temperature

Ambient temperature under bias

V_CCwith respect to AGND/DGND

–55 to +150°C

0 to +70°C

0.4 to + 7 V

_NEGwith respect to AGND/DGND

V_BAT2

_BAT1with respect to AGND/DGND:

0.4 V to V_BAT2

V_BAT2to GND

Continuous

10 ms

BGND with respect to AGND/DGND

A (TIP) or B (RING) to BGND:

Continuous

+0.4 to -80 V

+0.4 to -85 V

+3 to -3 V

V_BAT1– 5 V+ 1 V

V_BAT1– 10 V+ 5 V

V_BAT1– 15 V+ 8 V

V_BAT1– 20 V+ 12 V

10 ms (F = 0.1 Hz)

1 µs (F = 0.1 Hz)

250 ns (F = 0.1 Hz)

Current from A (TIP) or B (RING)

RYOUT1, RYOUT2 current

RYOUT1, RYOUT2 voltage

RYOUT1, RYOUT2 transient

RYE voltage

± 150 mA

75 mA

RYE to +7 V

RYE to +10 V

BGND to V_BAT1

C3-C1, D2-D1, E1, B2EN and RINGIN:

-0.4 V to V_CC+ 0.4 V

Input voltage

Maximum continuous power dissipation, TA = 70° C¹:

In 32-pin PLCC package

1.67 W

3.00 W

θ_JA

In 32-pin QFN package

Thermal Data:

In 32-pin PLCC package

45° C/W

In 32-pin QFN package²

25° C/W

ESD Immunity (Human Body Model)

JESD22 Class 1C compliant

Note:

1. Thermal limiting circuitry on the chip will shut down the circuit at a junction temperature of about 165ºC. Continuous operation above 145ºC

junction temperature may degrade device reliability.

2. The thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout. Specified performance

requires that the exposed thermal pad be soldered to an equally sized exposed copper surface, which, in turn, conducts heat through

multiple vias to a large internal copper plane.

Package Assembly

Green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and antimony-free

materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer lead-

free board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.

Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile.

OPERATING RANGES

Environmental Ranges

Zarlink guarantees the performance of this device over the commercial (0º C to 70º C) temperature range by conducting

electrical characterization and by conducting a production test with single insertion coupled to periodic sampling. These

characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component Reliability Assurance

Requirements for Telecommunications Equipment.

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

Environmental Ranges

Ambient Temperature

0 to 70° C

Electrical Ranges

V_CC

4.75 V to 5.25 V

-4.75 V to V_BAT2

V_NEG

V_BAT1

-40 to -67 V

V_BAT2

-19 V to V_BAT1

AGND/DGND

0 V

BGND with respect to AGND/DGND

Load resistance on VTX to GND

-100 mV to +100 mV

20 kΩ min

Note:

The Operating Ranges define those limits between which the functionality of the device is guaranteed.

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

ELECTRICAL CHARACTERISTICS

Description

Transmission Performance

2-wire return loss

Z_VTX, analog output impedance

V_VTX, analog output offset voltage

Z_RSN, analog input impedance

Test Conditions (See Note 1)

Min

Typ

Max

Unit

Note

200 Hz to 3.4 kHz (Test Circuit D)

Ω

1, 4, 6

+50

–50

Ω

Overload level, 2-wire and 4-wire, off hook Active state

2.5

0.88

Vpk

Vrms

Overload level, 2-wire

On hook, R_LAC= 600 Ω

THD (Total Harmonic Distortion)

THD, on hook, OHT state

+3 dBm, BAT2 = –24 V

0 dBm, R_LAC= 600 Ω,

BAT1 = –67 V

–64

–50

–40

Longitudinal Performance (See Test Circuit C)

Longitudinal to metallic L-T, L-4 balance

Longitudinal signal generation 4-L

Longitudinal current per pin (A or B)

Longitudinal impedance at A or B

Idle Channel Noise

200 Hz to 3.4 kHz

200 Hz to 800 Hz, Normal polarity

Active or OHT state

mArms

Ω/pin

0 to 100 Hz, T_A= +25°C

C-message weighted noise

Psophometric weighted noise

–83

+14

–76

dBrnC

dBmp

Insertion Loss and Four- to Four-Wire Balance Return Signal (See Test Circuits A and B)

Gain accuracy

4- to 2-wire

2- to 4-wire and

4- to 4-wire

0 dBm, 1 kHz

–0.20

+0.20

–6.22 –6.02 –5.82

Gain accuracy

4- to 2-wire

2- to 4-wire and

4- to 4-wire

OHT state, on hook

–0.35

+0.35

–6.37 –6.02 –5.77

µs

Gain accuracy over frequency

300 to 3400 Hz

relative to 1 kHz

+3 dBm to –55 dBm

relative to 0 dBm

0 dBm to –37 dBm

+3 dBm to 0 dBm

0 dBm, 1 kHz

–0.10

+0.10

Gain tracking

3, 4

Gain tracking

OHT state, on hook

Group delay

–0.10

–0.35

+0.10

+0.35

3, 4

1, 4, 6

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

ELECTRICAL CHARACTERISTICS (CONTINUED)

Description

Line Characteristics

Test Conditions (See Note 1)

Min

Typ

Max

Unit

Note

I_L, Loop-current accuracy

I_L, Long loops, Active state

I_L, Accuracy, Standby state

I_Lin constant-current region,

B2EN = 0

0.87I_L

I_L

21.7

I_L

1.1I_L

R_LDC= 600 Ω, RSGL = open

0.8I_L

R_LDC= 750 Ω, RSGL = short

1.2I_L

V_BAT1– 10 V

I_L= --------------------------------------

R_L+ 400

I_L= constant-current region

T_A= 25°C

I_LLIM

Active, A and B to ground

OHT, A and B to ground

110

I_L, Loop current, Open Circuit state

I_A, Pin A leakage, Tip Open state

I_B, Pin B current, Tip Open state

V_A, Standby, ground-start signaling

R_L= 0

B to ground

A to –48 V = 7 kΩ,

B to ground = 100 Ω

100

µA

–5

–7.5

V_AB, Open Circuit voltage

Power Supply Rejection Ratio (V_RIPPLE= 100 mVrms), Active Normal State

V_CC

V_NEG

V_BAT1

V_BAT2

50 Hz to 3400 Hz

Power Dissipation

On hook, Open Circuit state

On hook, Standby state

On hook, OHT state

On hook, Active state

Off hook, Standby state

Off hook, OHT state

Off hook, Active state

Supply Currents

I_CC, On-hook V_CCsupply current

V_BAT1

V_BAT2

V_BAT1

V_BAT1or V_BAT2

V_BAT1

V_BAT2

100

200

220

2000

550

300

350

2800

2200

750

R_L= 300 Ω

Open Circuit state

Standby state

OHT state

Active state–normal

3.0

3.2

6.2

6.5

4.5

5.5

8.0

9.0

I_NEG, On-hook V_NEGsupply current

I_BAT, On-hook V_BATsupply current

Open Circuit state

Standby state

0.1

0.7

0.45

0.6

2.0

2.7

0.2

1.1

1.0

1.5

4.0

5.0

OHT state

Active state–normal

Open Circuit state

Standby state

OHT state

Active state–normal

Zarlink Semiconductor Inc.

Le79R70

ELECTRICAL CHARACTERISTICS (continued)

Data Sheet

Description

Logic Inputs (C3–C1, D2–D1, E1, and B2EN)

V_IH, Input High voltage

V_IL, Input Low voltage

I_IH, Input High current

Test Conditions (See Note 1)

Min

Typ

Max

Unit

Note

2.0

0.8

–75

–400

µA

I_IL, Input Low current

Logic Output DET

V_OL, Output Low voltage

V_OH, Output High voltage

Ring-Trip Detector Input

Ring detect accuracy

I_OUT= 0.8 mA, 15 kΩ to V_CC

I_OUT= –0.1 mA, 15 kΩ to V_CC

0.40

+10

2.4

–10

BAT1 – 1









IRTD = --------------------------- + 24 µA • 335

RRT1

Ring Signal

V_AB, Ringing

V_ABRinging offset

Bat1 = –67 V, ringload = 1570 Ω

V_RINGIN= 2.5 V

180

Vpk

—

∆V_AB/∆V_RINGIN(RINGIN gain)

Ground-Key Detector Thresholds

Ground-key resistive threshold

Ground-key current threshold

Loop Detector

B to ground

kΩ

R_LTH, Loop-resistance detect threshold

Active, V_BAT1

Active, V_BAT2

Standby

–20

–12

Relay Driver Output (RELAY1 and 2)

V_OL, On voltage (each output)

I_OH, Off leakage (each output)

Zener breakover (each output)

Zener on voltage (each output)

I_OL= 30 mA

I_OL= 40 mA

V_OH= +5 V

I_Z= 100 µA

I_Z= 30 mA

+0.25

+0.30

+0.4

+0.8

100

µA

6.6

7.9

RELAY DRIVER SCHEMATIC

RYOUT2

RYOUT1

RYE

BGND

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

Notes:

1. Unless otherwise noted, test conditions are BAT1 = –67 V, BAT2 = –24 V, V_CC= +5 V, V_NEG= –5 V, R_L= 600 Ω,

R_DC1= 80 kΩ, R_DC2= 20 kΩ, R_D= 75 kΩ, no fuse resistors, C_HP= 0.018 µF, C_DC= 1.2 µF, D₁= D₂= 1N400x,

two-wire AC input impedance (ZSL) is a 600 Ω resistance synthesized by the programming network shown below.

R_SGL= open, R_SGH= open, R_DCR= 2 kΩ, R_RT1= 430 kΩ, R_RT2= 12 kΩ, C_RT= 1.5 µF, R_SLEW= 150 kΩ, C_SLEW= 0.33 µF.

VTX

RT1 = 150 kΩ

RT2 = 150 kΩ

CT1 = 60 pF

RSN

V_RX

RRX = 300 kΩ

2. a. Overload level is defined when THD = 1%.

b. Overload level is defined when THD = 1.5%.

3. Balance return signal is the signal generated at V_TXby V_RX. This specification assumes that the two-wire AC load impedance

matches the programmed impedance.

4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.

5. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.

6. Group delay can be greatly reduced by using a Z_Tnetwork such as that shown in Note 1 above. The network reduces the

group delay to less than 2 µs and increases 2WRL. The effect of group delay on line card performance may also be compen-

sated for by synthesizing complex impedance with the QSLAC or DSLAC device.

7. Open Circuit V_ABcan be modified using RSGH.

8. R_Dmust be greater than 56 kΩ. Refer to Table 2 for typical value of R_LTH

9. Lower power is achieved by switching into low-battery state in standby. Standby loop current is returned to V_BAT1regardless

of the battery selected.

Table 1. SLIC Decoding

(DET) Output

State

C3 C2 C1

2-Wire Status

Open Circuit

E1 = 1

Ring trip

E1 = 0

Ring trip

Battery Selection

Ringing

Ring trip

B2EN

Active

Loop detector

Ground key

On-hook TX (OHT)

Tip Open

B2EN = 1**

V_BAT1

Standby

Active Polarity Reversal

OHT Polarity Reversal

B2EN

Notes:

* Only –1 performance grade devices support polarity reversal.

** For correct ground-start operation using Tip Open, V_BAT1on-hook battery must be used.

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

Table 2. User-Programmable Components

Z_T= 500(Z_2WIN– 2R_F)

Z_Tis connected between the VTX and RSN pins. The fuse resistors are

R_F, and Z_2WINis the desired 2-wire AC input impedance. When com-

puting Z_T, the internal current amplifier pole and any external stray ca-

pacitance between VTX and RSN must be taken into account.

Z_RXis connected from V_RXto R_SN. Z_Tis defined above, and G_42Lis the

desired receive gain.

Z_L

1000 • Z_T

----------- --------------------------------------------------

Z_RX

•

G_42LZ_T+ 500(Z_L+ 2R_F)

R_DC1, R_DC2, and C_DCform the network connected to the RDC pin.

2500

--------------

I_LOOP

R_DC1+ R_DC2

_LOOPis the desired loop current in the constant-current region.

_DCR1, R_DCR2, and C_DCRform the network connected to the RDCR pin.

3000

R_DCR1+ R_DCR2= ---------------------

Iringlim

See Applications Circuit for these components.

R_DC1+ R_DC2

---------------------------------

C_DC= 19 ms •

_DC1R_DC2

_DCRsets the ringing time constant, which can be between 15 µs and

R_DCR1+ R_DCR2

----------------------------------------

• 150 µs

150 µs.

C_DCR

_DCR1R_DCR2

R_Dis the resistor connected from the RD pin to GND and R_LTHis the

loop-resistance threshold between on-hook and off-hook detection. R_D

should be greater than 56 kΩ to guarantee detection will occur in the

Standby state. Choose the value of R_Dfor high battery state; then use

the equation for R_LTHto find where the threshold is for low battery.

R_D= R_LTH• 12.67 for high battery state

Loop-Threshold Detect Equations

This is the same equation as for R_Din the preceding equation, except

R_D

R_LTH= ------------ for high battery

solved for R_LTH

12.67

For low battery, the detect threshold is slightly higher, which will avoid

oscillating between states.

R_D

R_LTH= ------------ for low battery

11.37

R_LTHstandby < R_LTHactive V_BAT1< R_LTHactive V_BAT2, which will guar-

antee no unstable states under all operating conditions. This equation

will show at what resistance the standby threshold will be; it is actually

a current threshold rather than a resistance threshold, which is shown

by the Vbat dependency.

V_BAT1–10

-----------------------------

915

R_LTH

• R_D– 400 – 2R_F

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

DC FEED CHARACTERISTICS

5) V_APPH

High Battery Anti-Sat

4) V_ASH

V_AB

(Volts)

1) Constant-Current Region

2) V_ASL

3) V_APPL

Low Battery Anti-Sat

I_L(mA)

Figure 1. Typical V_ABvs. I_LDC Feed Characteristics

R_DC= R_DC1+ R_DC2= 20 kΩ + 80 kΩ = 100 kΩ

(V_BAT1= –67 V, V_BAT2= –24 V)

Notes:

2500

------------

RDC

1. Constant-current region: V_AB= I_LR_L

R_L; where R_L= R_L+ 2R_F

1000 • (104 • 10³+ R_SGL

)

------------------------------------------------------------------

; where R_SGL= resistor to GND, B2EN = logic Low.

2. Low battery

V_ASL

6720 • 10³+ (80 • R_SGL

)

1000 • (R_SGL– 56 • 10³)

--------------------------------------------------------------

Anti-sat region:

V_ASL

; where R_SGL= resistor to V_CC, B2EN = logic Low.

R_SGLto V_CCmust be greater than 100 kΩ.

6720 • 10³+ (80 • R_SGL

)

V_APPL= 4.17 + V_ASL

V_APPL

I_LOOPL= ------------------------------------------------------------------------------

(R_DC1+ R_DC2

)

-------------------------------------- + 2 R _F+ R_LOOP

600

4. High battery

Anti-sat region:

V_ASH= V_ASHH+ V_ASL

1000 • (70 • 10³+ R_SGH

)

----------------------------------------------------------------------

V_ASHH

; where R_SGH= resistor to GND, B2EN = logic High.

; where R_SGH= resistor to V_CC, B2EN = logic High.

1934 • 10³+ (31.75 • R_SGH

)

1000 • (R_SGH+ 2.75 • 10³)

----------------------------------------------------------------------

V_ASHH

1934 • 10³+ (31.75 • R_SGH

)

R_SGHto V_CCmust be greater than 100 kΩ.

V_APPH= 4.17 + V_ASH

V_APPH

I_LOOPH= ------------------------------------------------------------------------------

(R_DC1+ R_DC2

)

-------------------------------------- + 2 R _F+ R_LOOP

600

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

RING-TRIP COMPONENTS

R_RT2= 12 kΩ

C_RT= 1.5 µF

V_BAT1

-----------------------------------------------------------------------------------------------------------------------------------------

R_RT1= 320 • CF •

• (R_LRT+ 150 + 2R_F)

V_BAT1– 5 – (24 µA • 320 • CF • (R_LRT+ 150 + 2R_F))

where R_LRT= Loop-detection threshold resistance for ring trip and CF = Crest factor of ringing signal (≈ 1.25)

R_SLEW, C_SLEW

Ring waveform rise time ≈ 0.214 • (R_SLEW• C_SLEW) ≈ tr.

For a 1.25 crest factor @ 20 Hz, tr ≈ 10 mS.

∴ (R_SLEW= 150 kΩ, C_SLEW= 0.33 µF.)

C_SLEWshould be changed if a different crest factor is desired.

Ringing Reference

(Input to R_SLEW

)

B(RING)

A(TIP)

Battery

This is the best time for

switching between RINGING

and other states for minimizing

detect switching transients.

Figure 2. Ringing Waveforms

RSN

R_L

I_L

SLIC

R_DC2

C_DC

R_DC1

RDC

Feed current programmed by R_DC1and R_DC2

Figure 3. Feed Programming

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

TEST CIRCUITS

A(TIP)

VTX

R_L

SLIC

V_AB

V_L

R_T

R_RX

AGND

R_L

B(RING) RSN

_L2-4= 20 log (V_TX/ V_AB)

A. Two- to Four-Wire Insertion Loss

A(TIP)

VTX

SLIC

V_AB

R_L

R_T

R_RX

AGND

B(RING)

RSN

V_RX

I_L4-2= 20 log (V_AB/ V_RX

)

BRS = 20 log (V_TX/ V_RX

)

B. Four- to Two-Wire Insertion Loss and Four- to Four-Wire Balance Return Signal

ωC

A(TIP)

SLIC

AGND

VTX

<< R_L

R_L

R_T

V_L

V_AB

R_L

V_L

R_RX

B(RING) RSN

V_RX

S2 Open, S1 Closed

S2 Closed, S1 Open

4-L Long. Sig. Gen. = 20 log (V_L/ V_RX

L-T Long. Bal. = 20 log (V_AB/ V_L)

L-4 Long. Bal. = 20 log (V_TX/ V_L)

)

C. Longitudinal Balance

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

TEST CIRCUITS (continued)

Z_D

A(TIP)

VTX

R_T1

SLIC

V_S

V_M

AGND

Z_IN

C_T1

R_T2

B(RING)

RSN

R_RX

Z_D: The desired impedance;

e.g., the characteristic impedance of the line

Return loss = –20 log (2 V_M/ V_S)

D. Two-Wire Return Loss Test Circuit

V_CC

6.2 kΩ

A(TIP)

DET

B(RING)

15 pF

R_L= 600 Ω

B(RING)

E. Loop-Detector Switching

F. Ground-Key Switching

RF₁

C₁

L₁

200 Ω

50 Ω

C_AX

33 nF

RF₂

50 Ω

200 Ω

GEN

C_BX

33 nF

VTX

C₂

L₂

50 Ω

SLIC

under test

1.5 Vrms

80% Amplitude

Modulated

100 kHz to 30 MHz

G. RFI Test Circuit

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

TEST CIRCUITS (continued)

+5 V

–5 V

VCC

RTRIP1

RTRIP2

VNEG

R_RT2

R_RT1

C_RT

1.5 µF

12 kΩ

R_D

75 kΩ

R_SGH

open

430 kΩ

R_SGL

open

C_AX

2.2 nF

RSGH

RSGL

A(TIP)

HPA

A(TIP)

V_TX

VTX

R_T

300 kΩ

R_RX

300 kΩ

C_HP

18 nF

HPB

V_RX

RSN

B(RING)

R_DC1

R_DC2

C_BX

80 kΩ

2.2 nF

20 kΩ

RDC

R_DCR

RYOUT1

RDCR

2.0 kΩ

RYOUT2

RYE

C_DC

1.2 µF

B2EN

D₁

DET

BAT1

VBAT1

VBAT2

0.1 µF

D₂

BAT2

0.1 µF

R_SLEW

100 kΩ

BGND

RINGIN

See Note.

C_SLEW

0.33 µF

AGND/

DGND

BATTERY

GROUND

ANALOG

GROUND

Note:

The input should be 50% duty cycle CMOS-compatible input.

DIGITAL

GROUND

H. Le79R70 Test Circuit

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

APPLICATION CIRCUIT

+5 V

–5 V

VCC

RTRIP1

RTRIP2

VNEG

R_RT2

R_RT1

C_RT

12 kΩ

1.5 µF

R_D

66 kΩ

R_SGH

515 kΩ

open

R_SGL

open

C_AX= 2.2 nF

RSGH

RSGL

VTX

R_FA= 50 Ω

TIP

A(TIP)

HPA

V_TX

R_T1

125 kΩ

R_RX

250 kΩ

Bat1

TISP

C_HP

18 nF

C_T

R_T2

61089

V_RX

HPB

RSN

R_DC1

50 kΩ

R_DC2

50 kΩ

B(RING)

RING

R_FB= 50 Ω

C_BX= 2.2 nF

RDC

R_DCR2

15 kΩ

C_DC

R_DCR1

820 nF

RYOUT1

RYOUT2

RYE

RDCR

C_DCR

15 kΩ

10 nF

B2EN

D₁

DET

BAT1

BAT2

VBAT1

VBAT2

0.1 µF

D₂

0.1 µF

R_SLEW

150 kΩ

BGND

See Note.

RINGIN

C_SLEW

0.33 µF

BATTERY

GROUND

AGND/

DGND

ANALOG

GROUND

Assumptions:

1. 1.25 CF

4. 5.2 kΩ High Battery Loop Threshold

5. 925 Ω Ringing Loop Threshold

6. 600 Ω Two-wire Impedance,

600 Ω Z_L

7. G_42L= 1

8. –67 V Vbat1, –24 V Vbat2

2. 25 mA I_LOOP

3. 100 mA Ringing Current Limit

DIGITAL

Note:

GROUND

The input should be 50% duty cycle CMOS-compatible input.

I. Application Circuit

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

PHYSICAL DIMENSIONS

32-Pin PLCC

NOTES:

Dimensioning and tolerancing conform to ASME Y14,5M-1994.

32-Pin PLCC

JEDEC # MS-016

To be measured at seating plan - C - contact point.

Min

Nom

Max

0.140

0.095

0.495

0.453

Symbol

0.125

0.075

0.485

0.447

Dimensions “D1” and “E1” do not include mold protrusion.

Allowable mold protrusion is 0.010 inch per side. Dimensions

“D” and “E” include mold mismatch and determined at the

parting line; that is “D1” and “E1” are measured at the extreme

material condition at the upper or lower parting line.

0.090

0.490

0.450

0.205 REF

0.590

0.550

0.255 REF

0.585

0.547

0.595

0.553

Exact shape of this feature is optional.

Details of pin 1 identifier are optional but must be located

within the zone indicated.

0 deg

10 deg

Sum of DAM bar protrusions to be 0.007 max per lead.

Controlling dimension : Inch.

Reference document : JEDEC MS-016

32-Pin PLCC

Note:

Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the

device. Markings will vary with the mold tool used in manufacturing.

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

32-Pin QFN

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

32 LEAD QFN

Nom

Symbol

Min

Max

2. All dimensions are in millimeters.

3. N is the total number of terminals.

is in degrees.

0.80

0.90

1.00

0.57 REF

0.23

The Terminal #1 identifier and terminal numbering convention

0.18

5.70

0.43

0.00

0.28

5.90

0.63

0.05

shall conform to JEP 95-1 and SSP-012. Details of the erminal #1

8.00 BSC

5.80

identifier are optional, but must be located within the zone

indicated. The Terminal #1 identifier may be either a mold or

marked feature.

8.00 BSC

5.80

5. Coplanarity applies to the exposed pad as well as the terminals.

6. Reference Document: JEDEC MO-220.

7. Lead width deviates from the JEDEC MO-220 standard.

0.80 BSC

0.53

aaa

bbb

ccc

0.02

0.20 REF

0.20

0.10

32-Pin QFN

Note:

Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the

device. Markings will vary with the mold tool used in manufacturing.

Zarlink Semiconductor Inc.

Le79R70

Data Sheet

REVISION HISTORY

Revision A to B

•

Minor changes were made to the data sheet style and format to conform to Zarlink standards.

Revision B to C

•

The 28-pin SOIC information and package was added to the Ordering Information and the Connection Dia-

grams sections.

•

The physical dimensions (PL032 and SOW28) were added to the Physical Dimensions section.

Updated the Pin Description table to correct inconsistencies.

Revision C to D

•

Changed Ring-Trip Components equation from:

V_BAT1

-----------------------------------------------------------------------------------------------------------------------------------------

R_RT1= 300 • CF •

• (R_LRT+ 150 + 2R_F)

Vbat – 3.5 – (15 µA • 300 • CF • (R_LRT+ 150 + 2R_F))

To:

V_BAT1

-------------------------------------------------------------------------------------------------------------------------------------

R_RT1= 320 • CF •

• (R_LRT+ 150 + 2R_F)

Vbat – 5 – (24 µA • 320 • CF • (R_LRT+ 150 + 2R_F))

Revision D to E

•

In “Ordering Information” section, added description for wafer foundry facility optional character.

Revision E to F

•

Updated device name from “Am79R70” to “Le79R70” throughout document.

Added QFN package to “Connection Diagram,” “Absolute Maximum Ratings,” and “Physical Dimensions.”

Removed reference to PLCC package type in “General Description.”

Ordering Information: Temperature statement updated to standard.

Absolute Maximum Ratings: Notes updated to standard.

Operating Ranges: Temperature statement updated to standard.

Revision F to G1

•

Added green package OPNs to Ordering Information, on page 1

Added Package Assembly, on page 6

Revision G1 to H1

•

Added "Packing" column and Note 5 to Ordering Information, on page 1

Updated 32QFN drawing in Physical Dimensions, on page 19

Revision H1 to I1

•

Added green package OPNs and removed OPN for SOIC package in Ordering Information, on page 1

Removed SOIC drawing in Physical Dimensions, on page 19

Added note to Physical Dimensions, on page 19

Revision I1 to J1

•

Removed the following OPNs from Ordering Information, on page 1: Le79R70JC, Le79R70-1JC, Le79R70QC, Le79R70-

1QC.

•

Changed I_LLoop-Current Accuracy from 0.9 to 0.871 in Electrical Characteristics.

Revision J1 to J2

•

Enhanced format of package drawings in Physical Dimensions, on page 19

Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007

Zarlink Semiconductor Inc.

For more information about all Zarlink products

visit our Web Site at

www.zarlink.com

Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.

However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such

information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or

use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual

property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in

certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.

This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part

of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other

information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the

capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute

any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and

suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does

not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in

significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.

Purchase of Zarlink’s I²C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system

conforms to the I²C Standard Specification as defined by Philips.

Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are

trademarks of Zarlink Semiconductor Inc.

TECHNICAL DOCUMENTATION - NOT FOR RESALE

LE79R70-1DJCT [MICROSEMI]

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