A500K130-BGG272I [MICROSEMI]
Field Programmable Gate Array, 12800-Cell, CMOS, PBGA272;型号: | A500K130-BGG272I |
厂家: | Microsemi |
描述: | Field Programmable Gate Array, 12800-Cell, CMOS, PBGA272 栅 可编程逻辑 |
文件: | 总72页 (文件大小:1555K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
v3.0
ProASIC™ 500K Family
I/O
Features and Benefits
• Mixed 2.5V/3.3V Support with Individually-Selectable
High Capacity
Voltage and Slew Rate
• 100,000 to 475,000 System Gates
• 3.3V, PCI Compliance (PCI Revision 2.2)
• 14k to 63k Bits of Two-Port SRAM
• 106 to 440 User I/Os
Secure Programming
The Industry’s Most Effective Security Key Prevents Read
Back of Programming Bit Stream
Performance
• 33 MHz PCI 32-bit PCI
Standard FPGA and ASIC Design Flow
• Internal System Performance up to 250 MHz
• External System Performance up to 100 MHz
• Flexibility with Choice of Industry-Standard Front-End
Tools
• Efficient Design Through Front-End Timing and Gate
Low Power
Optimization
• Low Impedance Flash Switches
ISP Support
• Segmented Hierarchical Routing Structure
• Small, Efficient Logic Cells
• In-System Programming (ISP) with Silicon Sculptor and
Flash Pro
High Performance Routing Hierarchy
SRAMs and FIFOs
• Ultra Fast Local Network
• Up to 150 MHz Synchronous and Asynchronous Operation
• Efficient Long Line Network
• Netlist Generator Ensures Optimal Usage of Embedded
• High Speed Very Long Line Network
• High Performance Global Network
Memory Blocks
Boundary Scan Test
Nonvolatile and Reprogrammable Flash
Technology
IEEE Std. 1149.1 (JTAG) Compliant
• Live at Power Up
• No Configuration Device Required
• Retains Programmed Design During Power-Down/
Power-Up Cycles
ProASIC Product Profile
Device
A500K050
A500K130
A500K180
A500K270
Maximum System Gates
Typical Gates
100,000
43,000
5,376
14k
290,000
105,000
12,800
45k
370,000
150,000
18,432
54k
475,000
215,000
26,880
63k
Maximum Flip-Flops
Embedded RAM Bits
Embedded RAM Blocks (256 X 9)
Logic Tiles
6
20
24
28
5,376
4
12,800
4
18,432
4
26,880
4
Global Routing Resources
Maximum User I/Os
JTAG
204
306
362
440
Yes
Yes
Yes
Yes
PCI
Yes
Yes
Yes
Yes
Package (by Pin Count)
PQFP
PBGA
FBGA
208
272
144
208
272, 456
144, 256
208
456
256
208
456
256, 676
February 2002
1
© 2002 Actel Corporation
ProASIC™ 500K Family
General Description
embedded two-port memory. These memory blocks include
hardwired FIFO circuitry as well as circuits to generate or
check parity. This minimizes external logic gate count and
complexity while maximizing flexibility and utility.
The ProASIC 500K family’s nonvolatile Flash technology
combines the advantages of ASICs with the benefits of
programmable devices. ProASIC 500K devices shorten
time-to-production by enabling designers to create
high-density systems using existing ASIC or FPGA design
flows and tools. ASIC migration is not necessary for any
volume because the family offers cost effective
reprogrammable solutions, ideal for applications in the
networking, telecom, computer, and consumer markets.
Process Technology
The ProASIC 500K family achieves its nonvolatile and
reprogrammability through an advanced 0.25µ, four-level
metal LVCMOS process enhanced with Flash technology.
The use of standard CMOS design techniques to implement
logic and control functions results in highly predictable
performance and gate array compatibility.
The ProASIC 500K family consists of four devices ranging
from 100k to 475k system gates and with up to 63k bits of
Ordering Information
A500K130
PQ
208
Application (Ambient Temperature Range)
Blank = Commercial (0 to +70˚ C)
I = Industrial (-40 to +85˚ C)
PP = Pre-production
ES = Engineering Silicon (Room Temperature Only)
Package Lead Count
Package Type
=
=
=
BG
PQ
FG
Plastic Ball Grid Array
Plastic Quad Flat Pack
Fine Ball Grid Array
Part Number
A500K050 = 100,000 Equivalent System Gates
A500K130 = 290,000 Equivalent System Gates
A500K180 = 370,000 Equivalent System Gates
A500K270 = 475,000 Equivalent System Gates
2
v3.0
ProASIC™ 500K Family
Product Plan
Application
C
I
A500K050 Device
144-Pin Fine Ball Grid Array (FBGA)
208-Pin Plastic Quad Flat Pack (PQFP)
272-Pin Plastic Ball Grid Array (PBGA)
A500K130 Device
✔
✔
✔
✔
✔
✔
144-Pin Fine Ball Grid Array (FBGA)
208-Pin Plastic Quad Flat Pack (PQFP)
272-Pin Plastic Ball Grid Array (PBGA)
256-Pin Plastic Ball Grid Array (PBGA)
456-Pin Plastic Ball Grid Array (PBGA)
A500K180 Device
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
208-Pin Plastic Quad Flat Pack (PQFP)
256-Pin Plastic Ball Grid Array (PBGA)
456-Pin Plastic Ball Grid Array (PBGA)
A500K270 Device
✔
✔
✔
✔
✔
✔
208-Pin Plastic Quad Flat Pack (PQFP)
256-Pin Plastic Ball Grid Array (PBGA)
456-Pin Plastic Ball Grid Array (PBGA)
676-Pin Fine Ball Grid Array (FBGA)
✔
✔
✔
✔
✔
✔
✔
✔
Contact your Actel sales representative for package availability.
Applications: C = Commercial
= Industrial
Availability: ✔ = Available – Contact your Actel Sale’s representative for the latest
I
availability information.
Plastic Device Resources
User I/Os
PQFP
208-Pin
PBGA
272-Pin
PBGA
456-Pin
FBGA
144-Pin
FBGA
256-Pin
FBGA
676-Pin
Device
A500K050
164
164
164
164
204
204
—
—
106
106
—
—
—
—
A500K130
306
362
362
192
192
192
A500K180
—
A500K270
—
—
440
Package Definitions
PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Ball Grid Array
v3.0
3
ProASIC™ 500K Family
ProASIC 500K Architecture
Programming options include synchronous or asynchronous
operation, two-port RAM configurations, user defined depth
and width, and parity generation or checking. Table 3 on
page 12 lists the 24 basic memory configurations.
The ProASIC 500K family’s proprietary architecture
provides granularity comparable to gate arrays. Unlike
SRAM-based FPGAs that utilize look-up tables or
architectural mapping during design, ProASIC device
designs are directly synthesized to gates. That streamlines
the design flow, increases design productivity, and
eliminates dependencies on vendor-specific design tools.
Flash Switch
In the ProASIC Flash switch, two transistors share the
floating gate which stores the programming information.
One is the Flash transistor which stores programming
information and in which erasing is performed. The second
transistor connects/separates routing elements or
configuration signal lines (Figure 2 on page 5).
The ProASIC 500K device core
consists of
a
Sea-of-Tiles™(Figure 1), each of which can be configured as
a 3-input logic function (e.g., NAND gate, D-Flip-Flop, etc.)
by programming the appropriate Flash switch
interconnections (See Figure 2 on page 5 and Figure 3 on
page 5). Gates and larger functions are connected with four
levels of routing hierarchy. Flash memory bits are
distributed throughout the device to provide nonvolatile,
reconfigurable interconnect programming. Flash switches
are programmed to connect signal lines to the appropriate
logic cell inputs and outputs. Dedicated high-performance
lines are connected as needed for fast, low-skew global
signal distribution throughout the core. Maximum core
utilization is possible for virtually any design.
Logic Tile
The logic tile cell, Figure 3 on page 5, has three inputs (any
or all of which can be inverted) and one output (which can
connect to both ultra fast local and efficient long line
routing resources). Any three-input one-output logic
function, except a three input XOR, can be configured as
one tile. Two multiplexers with feedback paths through the
NAND gates allow the tile to be configured as a latch with
clear or set, or as a flip-flop with clear or set. Thus, the tiles
can flexibly map logic and sequential gates of a design.
The ProASIC 500K devices also contain embedded two-port
SRAM blocks with built-in FIFO/RAM control logic.
256x9 Two-Port SRAM
or FIFO Block
Logic Tile
Figure 1 • The ProASIC Device Architecture
4
v3.0
ProASIC™ 500K Family
Sel 1 Sel 2
Switch In
Floating Gate
Word
Switch Out
Figure 2 • Flash Switch
Local Routing
In 1
Efficient Long
Line Routing
In 2 (CLK)
In 3 (Reset)
Figure 3 • Core Logic Tile
Routing Resources
and horizontally, providing multiple access to each group of
tiles throughout the device (Figure 6 on page 7).
The routing structure of the ProASIC 500K devices is
designed to provide high performance through a flexible
four-level hierarchy of routing resources: ultra fast local
resources, efficient long line resources, high speed very long
line resources, and high performance global networks.
The high performance global networks’ clock trees are low
skew, high fanout nets that are accessible from four
dedicated pins or from internal logic (Figure 7 on page 8).
These nets are typically used to distribute clocks, resets,
and other high fanout nets requiring a minimum skew. The
global networks are implemented as clock trees, and signals
can be introduced at any junction. These can be employed
hierarchically, with signals accessing every input on all
tiles.
The ultra fast local resources are dedicated lines that allow
the output of each tile to connect directly to every input of
the eight surrounding tiles (Figure 4 on page 6).
The efficient long line resources provide routing for longer
distances and higher fanout connections. These resources
vary in length (spanning 1, 2, or 4 tiles), run both vertically
and horizontally, and cover the entire ProASIC device
(Figure 5 on page 6). Each tile can drive signals onto the
efficient long line resources, while the resources can also
access every input of any tile. The routing software
automatically inserts active buffers to limit loading effects
due to distance and fanout.
Clock Resources
ProASIC’s high-drive routing structure provides four global
networks, each accessible from either a dedicated global
pad or a logic tile. Global lines provide optimized worst-case
clock skew of 0.3ns.
The high speed very long line resources, spanning across
the entire device with minimal delay, are used to route very
long or very high fanout nets. These resources run vertically
v3.0
5
ProASIC™ 500K Family
L
L
L
L
L
L
Inputs
Ultra Fast
Local Lines
(connect a tile to the
adjacent tile, I/O buffer,
or memory block)
L
L
L
Figure 4 • Ultra Fast Local Resources
4 Tiles Long
1 Tile Long
2 Tiles Long
Logic Tile
L
L
L
L
L
L
L
L
L
L
L
L
1 Tile Long
L
L
L
L
L
L
2 Tiles Long
4 Tiles Long
L
L
L
L
L
L
Logic Cell
L
L
L
L
L
L
Figure 5 • Efficient Long Line Resources
6
v3.0
ProASIC™ 500K Family
High Speed Very Long Line Resouces
PAD RING
PAD RING
Figure 6 • High Speed Very Long Line Resources
v3.0
7
ProASIC™ 500K Family
Clock Trees
The flexible use of the ProASIC clock spine allows the
designer to cope with several design requirements. Users
implementing clock resource intensive applications can
easily route external or gated internal clocks using global
routing spines. Users can also drastically reduce delay
penalties and save buffering resources by mapping critical
high fanout nets to spines. For design hints on using these
features, refer to the Efficient Use of ProASIC Clock Trees
application note.
One of the main architectural benefits of ProASIC is the set
of power and delay friendly global networks. The ProASIC
family offers 4 global trees. Each of these trees is based on a
network of spines and ribs that reach all the tiles in their
regions (Figure 7). This flexible clock tree architecture
allows users to map up to 56 different internal/external
clocks in an A500K270 device (Table 1).
High Performace
Global Network
PAD RING
Low Skew
Global Networks
Global
Pads
Global
Pads
Global Spine
Global Ribs
Scope of Spine
PAD RING
Figure 7 • A500K130 Global Routing Resources
Table 1 • Number of Clock Spines
A500K050
A500K130
A500K180
A500K270
Top Spine Height
24
768
32
32
1,024
40
40
1,280
56
56
1,792
64
Tiles in Each Top Spine
Bottom Spine Height
Tiles in Each Bottom Spine
Global Clock Networks (Trees)
Clock Spines/Tree
Total Spines
1,024
4
1,280
4
1,792
4
2,048
4
6
10
12
14
24
40
48
56
Total Tiles
5,376
12,800
18,432
26,880
8
v3.0
ProASIC™ 500K Family
Input/Output Blocks
All I/Os also include an ESD protection circuit. Each I/O is
tested according to the following model:
To meet complex system design needs, the ProASIC 500K
family offers devices with a large number of I/O pins, up to
440 user I/O pins on the A500K270. If the I/O pad is powered
at 3.3V, each I/O can be selectively configured at 2.5V and
3.3V threshold levels. Table 2 shows the available supply
voltage configurations. Figure 8 illustrates I/O interfaces
with other devices.
•
Human Body Model (HBM)
2000V
(Per Mil Std 883 Method 3015)
ProASIC
2.5V
2.5V
Device
V
V
= 2.5V
DDL
DDP
Device
= 2.5V
Table 2 • ProASIC Power Supply Voltages
VDDP
2.5V
2.5V
2.5V
3.3V
2.5V
Device
2.5V
Device
Input Tolerance
3.3V, 2.5V
3.3V, 2.5V
ProASIC
Output Drive
V
V
= 2.5V
= 3.3V
DDL
DDP
Note: VDDL is always 2.5V.
3.3V
Device
3.3V
Device
The I/O pads are fully configurable to provide the maximum
flexibility and speed. Each pad can be configured as an
input, an output, a three-state driver, or a bidirectional
buffer (Figure 9). I/O pads configured as inputs have the
following features:
Figure 8 • I/O Interfaces
3.3V/2.5V
Signal Control
• Individually selectable 2.5V or 3.3V threshold levels1
Pull-up
Control
• Optional pull-up resistor
I/O pads configured as outputs have the following features:
Y
• Individually selectable 2.5V or 3.3V compliant output
signals1
EN
A
• 3.3V PCI compliant
Pad
• Ability to drive LVTTL and LVCMOS levels
• Selectable drive strengths
• Selectable slew rates
• Tristate
3.3V/2.5V Signal Control
Drive Strength and Slew
Rate Control
I/O pads configured as bidirectional buffers have the
following features:
Figure 9 • I/O Block Schematic Representation
• Individually selectable 2.5V or 3.3V compliant output
Boundary Scan
signals and threshold levels1
ProASIC devices are compatible with IEEE Standard 1149.1,
• 3.3V PCI compliant
• Optional pull-up resistor
• Selectable drive strengths
• Selectable slew rates
• Tristate
which defines
a set of hardware architecture and
mechanisms for cost-effective board-level testing. The basic
ProASIC boundary-scan logic circuit is composed of the TAP
(test access port), TAP controller, test data registers, and
instruction register (Figure 10 on page 10). This circuit
supports all mandatory IEEE 1149.1 instructions (EXTEST,
SAMPLE/PRELOAD and BYPASS), the optional IDCODE
instructions and private instructions used for device
programming and factory testing.
Each test section is accessed through the TAP, which has
five associated pins: TCK (test clock input), TDI and TDO
(test data input and output), TMS (test mode selector) and
TRST (test reset input). TMS, TDI, and TRST are equipped
1. If pads are configured for 2.5V operation, they are compliant with 2.5V level
signals as defined by JEDEC JESD 8-5. If pads are configured for 3.3V operation,
they are compliant to the standard as defined by JEDEC JESD 8-A (LVTTL and
LVCMOS).
v3.0
9
ProASIC™ 500K Family
with pull-up resistors to ensure proper operation when no
input data is supplied to them. These pins are dedicated for
boundary-scan test usage.
register is selected when no other register needs to be
accessed in a device; this speeds up test data transfer to
other devices in a test data path. The 32-bit device
identification register is a shift register with four fields
(LSB, ID number, part number and version). The
boundary-scan register observes and controls the state of
each I/O pin.
The TAP controller is a four-bit state machine (16 states)
that operates as shown in Figure 11 on page 11. The ‘1’s and
‘0’s represent the values that must be present at TMS at a
rising edge of TCK for the given state transition to occur. IR
and DR indicate that the instruction register or the data
register is operating in that state.
Each I/O cell has three boundary-scan register cells, each
with a serial-in, serial-out, parallel-in, and parallel-out pin.
The serial pins are used to serially connect all the
boundary-scan register cells in a device into a boundary
scan register chain which starts at the TDI pin and ends at
the TDO pin. The parallel ports are connected to the
internal core logic tile and the input, output, and control
ports of an I/O buffer to capture and load data into the
register to control or observe the logic state of each I/O.
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest of
the test logic architecture. On power up, the TAP controller
enters the Test-Logic-Reset state. To guarantee a reset of
the controller from any of the possible states, TMS must
remain high for five TCK cycles. The TRST pin may also be
used to asynchronously place the TAP controller in the
Test-Logic-Reset state.
Details on the implementation of boundary-scan testing on
ProASIC devices can be found in the Actel application note,
Using JTAG Boundary-Scan with ProASIC Devices.
ProASIC devices support three types of test data registers:
bypass, device identification, and boundary scan. The bypass
I/O
I/O
I/O
I/O
I/O
Test Data
Registers
Bypass Register
Instruction
Register
TAP
Controller
Device
Logic
I/O
I/O
I/O
I/O
I/O
Figure 10 • ProASIC JTAG Boundary Scan Test Logic Circuit
10
v3.0
ProASIC™ 500K Family
Test-Logic
Reset
1
0
0
1
0
1
0
1
Run-Test/
Idle
Select-DR-
Scan
Select-IR-
Scan
0
0
Capture-DR
0
Capture-IR
0
1
1
Shift-IR
1
Shift-DR
1
1
1
Exit-DR
Exit-IR
0
Pause-DR
1
0
Pause-IR
1
0
0
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
0
0
1
1
Figure 11 • TAP Controller State Diagram
User Security
Embedded Memory Configurations
The ProASIC 500K devices have read-protect bits that, once
programmed, lock the entire programmed contents from
being read externally. The user can only reprogram the
device using the security key. This protects it from being
read back and duplicated. Since programmed data is stored
in nonvolatile Flash cells (which act like very small
capacitors), rather than in the wiring, physical
deconstruction cannot be used to compromise data. That
approach would be further hampered by the placement of
the flash cells, beneath the four metal layers (whose
removal could not be accomplished without disturbing the
charge on the floating gate). This is the highest security
provided in the industry. For more information, refer to the
Design Security for Nonvolatile Flash and Antifuse FPGAs
white paper for more information.
The embedded memory in the ProASIC 500K family provides
great configuration flexibility. While other programmable
vendors typically use single port memories that can only be
transformed into two-port memories by sacrificing half the
memory, each ProASIC block is designed and optimized as a
two-port memory (1 read, 1 write). This provides 63k bits of
total memory for two-port and single port usage in the
A500K270 device.
Each memory can be configured as FIFO or SRAM, with
independent selection of synchronous or asynchronous read
and write ports (Table 3 on page 12). Multiple write ports
are not supported. Additional characteristics include
programmable flags as well as parity check and generation.
Figure 12 and Figure 13 on page 13 show the block diagrams
of the basic SRAM and FIFO blocks. These memories are
designed to operate up to 133 MHz when operated
individually. Each block contains a 256 word deep by 9-bit
wide (1 read, 1 write) memory. The memory blocks may be
combined in parallel to form wider memories or stacked to
form deeper memories (Figure 14 on page 14). This
provides optimal bit widths of 9 (1 block), 18, 36, and 72,
and optimal depths of 256, 512, 768, and 1024. Refer to the
Macro Library Guide for more information.
Embedded Memory Floorplan
The embedded memory is located across the top of the
device (see Figure 1 on page 4) in 256x9 blocks. Depending
upon the device, 6 to 28 blocks are available to support a
variety of memory configurations. Each block can be
programmed as an independent memory or combined
(using dedicated memory routing resources) to form larger,
more complex memories.
v3.0
11
ProASIC™ 500K Family
Figure 15 on page 14 gives an example of optimal memory
usage. Ten blocks with 23,040 bits have been used to
generate three memories of various widths and depths.
Figure 16 on page 14 shows how memory can be doubled up
to create extra read ports. In this example, 10 out of 28
blocks of the A500K270 yield an effective 6,912 bits of
multiple port memories. The ACTgen™ software facilitates
building wider and deeper memories for optimal memory
usage.
Table 3 • Basic Memory Configurations
Type
Write Access
Read Access
Parity
Library Cell Name
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
RAM256x9AA
Asynchronous
RAM256x9AAP
RAM256xAST
RAM256xASTP
RAM256x9ASR
RAM256x9ASRP
RAM256x9SA
Synchronous Transparent
Synchronous Transparent
Synchronous Pipelined
Synchronous Pipelined
Asynchronous
Asynchronous
RAM256xSAP
RAM256x9SST
RAM256x9SSTP
RAM256x9SSR
RAM256x9SSRP
FIFO256xAA
Synchronous Transparent
Synchronous Transparent
Synchronous Pipelined
Synchronous Pipelined
Asynchronous
Asynchronous
FIFO256x9AAP
FIFO256xAST
FIFO256x9ASTP
FIFO256x9ASR
FIFO256x9ASRP
FIFO256x9SA
FIFO256xSAP
FIFO256x9SST
FIFO256x9SSTP
FIFO256x9SSR
FIFO256x9SSRP
Synchronous Transparent
Synchronous Transparent
Synchronous Pipelined
Synchronous Pipelined
Asynchronous
Asynchronous
Synchronous Transparent
Synchronous Transparent
Synchronous Pipelined
Synchronous Pipelined
12
v3.0
ProASIC™ 500K Family
DI <0:8>
WADDR <0:7>
DO <0:8>
DO <0:8>
DI <0:8>
SRAM
(256 X 9)
SRAM
(256 X 9)
RADDR <0:7>
WADDR <0:7>
RADDR <0:7>
WRB
Async Write
&
Async Read
WRB
RDB
RBLKB
RDB
Sync Write &
Sync Read
Ports
WBLKB
RBLKB
RCLKS
Ports
WCLKS
WPE
WBLKB
WPE
RPE
RPE
PARODD
PARODD
DO <0:8>
DI <0:8>
DI <0:8>
DO <0:8>
SRAM
(256 X 9)
SRAM
(256 X 9)
WADDR <0:7>
WADDR <0:7>
RADDR <0:7>
RADDR <0:7>
WRB
Sync Write
&
RDB
RDB
WRB
WBLKB
Async Write
&
Sync Read
WBLKB
RBLKB
RBLKB
RCLKS
Async Read
WCLKS
Ports
Ports
RPE
RPE
WPE
WPE
PARODD
PARODD
Note: For memory block interface signal definitions, see Table 4 on page 28.
Figure 12 • Example SRAM Block Diagrams
D1<0:8>
D0 <0:8>
D1 <0:8>
LEVEL <0:7>
LGDEP<0:2>
WRB
LEVEL<0:7>
LGDEP<0:2>
D0 <0:8>
WPE
WPE
WRB
WBLKB
FIFO
(256 X 9)
Sync Write &
Sync Read
Ports
FIFO
(256 X 9)
Sync Write &
Async Read
Ports
WBLKB
RPE
RPE
FULL
EMPTY
FULL
EMPTY
RDB
RBLKB
RDB
RBLKB
EQTH
EQTH
PARODD
PARODD
GEQTH
GEQTH
WCLKS
WCLKS
RESET
RCLKS
D0 <0:8>
WPE
D1 <0:8>
D1 <0:8>
D0 <0:8>
WPE
LEVEL <0:7>
LGDEP<0:2>
WRB
LEVEL <0:7>
LGDEP<0:2>
WRB
FIFO
(256 X 9)
Async Write &
Sync Read
Ports
FIFO
(256 X 9)
Async Write &
Async.Read
Ports
WBLKB
WBLKB
RPE
RPE
FULL
FULL
EMPTY
RDB
RBLKB
EMPTY
EQTH
RDB
EQTH
RBLKB
PARODD
GEQTH
GEQTH
PARODD
RCLKS
Note: For memory block FIFO signal definitions, see Table 5 on page 34.
Figure 13 • Basic FIFO Block Diagrams
v3.0
13
ProASIC™ 500K Family
9
Word Width
9
9
9
9
256
9
256
256
9
256
…
256
9
256
9
256
256
Word
256
Depth
88 blocks
Figure 14 • A500K270 Memory Block Architecture
Word Width
9
9
9
9
9
Word
Depth
256
256
256 words x 18bits, 1 read, 1 write
256
256
256
256
512 words x 18bits, 1 read, 1 write
256
1,024 words x 9bits, 1 read, 1 write
Total Memory Blocks Used = 10
Total Memory Bits = 23,040
Figure 15 • Example Showing Memories with Different Width and Depth
Word Width
9
9
Write Port
Write Port
9
9
Word
Depth
256
256
Read Ports
256 words x 9bits, 2 read, 1 write
Read Ports
512 words x 9bits, 4 read, 1 write
Total Memory Blocks Used = 10
Total Memory Bits = 6,912
Figure 16 • Multiport Memory Usage
14
v3.0
ProASIC™ 500K Family
Design Environment
design into the selected device/package, and provides
postlayout timing information for backannotated simulation
or static timing analysis. The Designer software also
contains very powerful layout capabilities for the
experienced user. A very comprehensive set of floor
planning, timing, and routing constraints gives users
optimal control over the tools’ capabilities, enabling them
to meet their tight design requirements. Users have access
to constraints that allow them full control of the resources
management. See the Designer User’s Guide for various
constraints and their uses.
ProASIC devices are supported by Actel’s Designer Series
software, as well as all of the industry standard third party
CAE tools. Unlike other FPGA vendors, no special HDL
instantiation or device related attributes are needed when
using the standard VHDL or Verilog HDL design flow with
ProASIC. As a result, designers can utilize the technology
independent of HDL code for ProASIC devices. This feature
and the ASIC-like design flow ensure a seamless transition
to an ASIC implementation, if production volumes warrant a
migration to a gate array or a standard cell product
(Figure 17).
The ProASIC devices are also fully supported by Actel’s
Libero design tool suite. Libero is a design management
environment that integrates the needed design tools,
streamlines the design flow, manages all design and log
files, and passes the necessary design data between tools.
Libero includes Synplify, ViewDraw, Actel’s Designer Series,
ModelSim HDL Simulator, and WaveFormer Lite.
ACTgen automatically generates memories and FIFOs with
all the various options (width, depth, access mode, parity
checking or generation, flags, etc.). For a synchronous read
port, the user can choose whether the output is pipelined or
transparent. ACTgen allows any bit width up to 252 (for the
A500K270 device). ACTgen also enables optimal memory
stacking in 256-word increments. However, any word depth
may be combined for up to 7,168 words. ACTgen allows the
user to generate distributed memory.
Once the design is finalized, the programming bitstream is
downloaded into the device programmer for ProASIC part
programming. ProASIC 500K devices can be programmed
with the Silicon Sculptor II and Flash Pro programmers.
On-board programming is also available. Refer to the
In-System Programming ProASIC 500K with Silicon
Sculptor application note for more information.
Place and route is performed by Actel’s Designer software.
Available for UNIX workstations and PC platforms, Designer
software accepts standard netlists in Verilog, VHDL, and in
EDIF format, performs timing driven place and route of the
Design Creation/Verification
High-Level
Simulation
Verilog orVHDL Simulator
Library
Design
(Verilog orVHDL)
Synthesis
Library
SynthesisTool
Forward
Constraints
Structural
Netlist
Design Implementation
P&R User
Constraints
Designer
(P&RTool)
ACTgen
Backannotation
SDF
Timing
File
Programming
Data
Timing and Simulation
Programming
Simulation
Library
Silicon
Sculptor II
Timing
Libraries
Verilog orVHDL Simulator
Flash
Pro
Timing
Analyzer
Figure 17 • ProASIC Design Flow
v3.0
15
ProASIC™ 500K Family
Package Thermal Characteristics
The ProASIC 500K family is available in a number of
package types. Actel has selected packages based on high
pin count, reliability factors, and superior thermal
characteristics.
operating temperature (TA), and junction-to-ambient
thermal resistance Θ . Maximum junction temperature is
ja
the maximum allowable temperature on the active surface
of the IC and is 110° C. P is defined as:
Thermal resistance indicates the ability of a package to
conduct heat away from the silicon, through the package, to
the surrounding air. Junction-to-ambient thermal resistance
is measured in degrees Celsius/Watt and is represented as
TJ – TA
----------------
P =
Θja
Θ
is a function of the rate (in linear feet per minute –
ja
Theta ja (Θ ). The lower the thermal resistance, the more
ja
lfpm) of airflow in contact with the package. When the
estimated power consumption exceeds the maximum
allowed power, other means of cooling, such as increasing
the airflow rate, must be used.
efficiently a package will dissipate heat.
A package’s maximum allowed power (P) is a function of
maximum junction temperature (TJ), maximum ambient
Package Type
Pin Count
Θjc
Θja Still Air
Θja 300 ft/min
Units
Plastic Quad Flat Pack (PQFP)
PQFP with Heatspreader
208
208
272
456
144
256
8
3.8
3
30
20
23
17
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Plastic Ball Grid Array (PBGA)
Plastic Ball Grid Array (PBGA)
Fine Ball Grid Array (FBGA)
Fine Ball Grid Array (FBGA)
20
16.5
14.5
26.7
25
3
18
3.8
3.0
38.8
30
16
v3.0
ProASIC™ 500K Family
Calculating Power Dissipation
ProASIC device power is calculated with both a static and
an active component. The active component is a function of
both the number of tiles utilized and the system speed.
Power dissipation can be calculated using the following
formula:
P
memory = P6 * Nmem * Fmem
where:
P6
= 100.0 uW/MHz
is the average power consumption of a memory
block normalized per MHz of the clock
Nmem = the number of RAM/FIFO blocks (1 block = 256
words * 9 bits)
Fmem = the clock frequency of the memory
Ptotal = Pdc + Pac
where:
Pdc
Pac
Pclock
=
=
=
10 mW
The following is an example using a shift register design
with 13,440 storage tiles and 0 logic tile. This design has one
clock at 10 MHz, and 24 outputs toggling at 5 MHz for a
A500K270.
Pclock + Pstorage + Plogic + Pios + Pmemory
(P1 + P2 * s) * Fs
where:
Fs = 10 MHz
P1 = 2500 uW/MHz
the basic power consumption of the clock-tree
normalized per MHz of the clock
P2 = 1.0 uW/MHz
s
= 13,440
=> Pclock = (P1 + P2 * s) * Fs = 159.4 mW
ms = 13,440 (in a shift register 100% of storage-tiles are
toggling at each clock cycle and Fs = 10 MHz
the extra power consumption of the clock-tree
per storage-tile normalized per MHz of the clock
=> Pstorage = P5 * ms * Fs = 134.4 mW
s
= the number of storage tiles clocked by this clock
mc
=
0 (no logic tile in this shift-register)
=> logic = 0 mW
Fs = the clock frequency
P
Pstorage = P5 * ms * Fs
Fp = 5 MHz
where:
Cload
VDDP
=
=
40 pF
3.3 V
P5 = 1.0 uW/MHz
the average power consumption of a storage-tile
normalized per MHz of its output
ms = the number of storage tiles switching at each Fs
cycle
Fs = the clock frequency
and p = 24
=> Pios = (P4 + Cload * Vddp^2) * p * Fp = 54.1 mW
Nmem 0 (no RAM/FIFO in this shift-register)
=
=> Pmemory = 0 mW
Plogic = P3 * mc * Fs
where:
• Pac = Pclock + Pstorage + Plogic + Pios + Pmemory = 347.9 mW
• Pdc = 10 mW
P3 = 3.0 uW/MHz
the average power consumption of a logic-tile
normalized per MHz of its output
mc = the number of logic tiles switching at each Fs
cycle
• Ptotal = Pdc + Pac = 357.9 mW
Power Consumption of a 500K Device
1000
ProASIC
Fs = the clock frequency
900
SRAM
800
700
600
500
400
300
200
Pios = (P4 + Cload * Vddp^2) * p * Fp
where:
P4 = 15.0 uW/MHz
the average power consumption of an output-pad
normalized per MHz of its output (internal power-
load is not included)
P
110 instances of 16-bit binary counters
Cload = the output load
100
0
p
= the number of outputs
90
80
20
70
100 120
50
60
30
40
Fp = the average output frequency
Frequency (MHz)
v3.0
17
ProASIC™ 500K Family
Operating Conditions
Absolute Maximum Ratings
Parameter
Condition
Minimum
Maximum
Units
Supply Voltage Core (VDDL
)
–0.3
–0.3
–0.3
–0.5
–10
3.0
4.0
V
V
Supply Voltage I/O Ring (VDDP
DC Input Voltage
)
VDDP + 0.3
V
PCI DC Input Voltage
DC Input Clamp Current
V
DDP + 0.5
V
VIN < 0 or VIN> VDDP
+10
mA
Note: Stresses beyond those listed in the Absolute Maximum Ratings table can cause permanent damage to the device. Exposure to maximum
rated conditions for extended periods can adversely affect device reliability. Operation of the device at these conditions or any others
beyond those listed in the Recommended Operating Conditions is not implied.
Programming and Storage Temperature LImits
Storage Temperature
Programming
Cycles
Program
Retention
Product Grade
Min.
Max.
Commercial
Industrial
50
50
20 years
20 years
–55°C
–55°C
110°C
110°C
Supply Voltages
Mode
VDDL
VDDP
VPP
VPN
Single Voltage
Mixed Voltage
2.5V
2.5V
2.5V
3.3V
2.5V ≤ Vpp ≤ 16.5V
3.3V ≤ Vpp ≤ 16.5V
–12V≤ VPN ≤ 0V
–12V ≤VPN ≤ 0V
Recommended Operating Conditions
Parameter
Symbol
Limits
Commercial
DC Supply Voltage (2.5V I/Os)
VDDL & VDDP
2.3V to 2.7V
DC Supply Voltage (Mixed 2.5V and 3.3V I/Os)
VDDP
VDDL
3.0V to 3.6V
2.3V to 2.7V
Operating Ambient Temperature Range
Maximum Operating Junction Temperature
Maximum Clock Frequency
Maximum RAM Frequency
Industrial
TA
TJ
0°C to 70°C
110°C
fCLOCK
fRAM
250 MHz
150 MHz
DC Supply Voltage (2.5V I/Os)
VDDL & VDDP
2.3V to 2.7V
DC Supply Voltage (Mixed 2.5V and 3.3V I/Os)
VDDP
VDDL
3.0V to 3.6V
2.3V to 2.7V
Operating Ambient Temperature Range
Maximum Operating Junction Temperature
Maximum Clock Frequency
TA
TJ
–40°C to 85°C
110°C
fCLOCK
fRAM
250 MHz
150 MHz
Maximum RAM Frequency
18
v3.0
ProASIC™ 500K Family
DC Electrical Specifications (VDDP = 2.5V)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDDP, VDDL Supply Voltage
2.3
2.7
V
Output High Voltage
IOH = –2.0 mA
2.1
2.0
1.7
I
I
OH = –4.0 mA
OH = –8.0 mA
High Drive (OB25LPH)
VOH
V
V
IOH = –1.0 mA
2.1
2.0
1.7
I
I
OH = –2.0 mA
OH = –4.0 mA
Low Drive (OB25LPL)
Output Low Voltage
I
OL = 5.0 mA
0.2
0.4
0.7
High Drive (OB25LPH)
IOL = 10.0 mA
VOL
I
OL = 15.0 mA
I
OL = 2.0 mA
0.2
0.4
0.7
Low Drive (OB25LPL)
IOL = 3.5 mA
OL = 5.0 mA
I
VIH
VIL
Input High Voltage
Input Low Voltage
1.7
–0.3
25
VDDP + 0.3
0.7
V
V
with pull-up
250
10
µA
µA
2
IIN
Input Current
without pull-up
IDDQ
IOZ
Quiescent Supply Current
VIN = VSS3 or VDDL
4.0
10
10
mA
µA
3-State Output Leakage Current
VOH = VSS or VDDL
Output Short Circuit Current High
High Drive (OB25LPH)
2
IOSH
VIN = VSS
VIN = VSS
120
100
mA
Low Drive (OB25LPL)
Output Short Circuit Current Low
High Drive (OB25LPH)
IOSL
VIN = VDDP
VIN = VDDP
100
30
mA
Low Drive (OB25LPL)
CI/O
I/O Pad Capacitance
10
10
pF
pF
CCLK
Notes:
Clock Input Pad Capacitance
1. All process conditions. Junction Temperature: –40 to +110°C.
2. Current is negative.
3. No pull-up resistor.
v3.0
19
ProASIC™ 500K Family
DC Electrical Specifications (VDDP = 3.3V)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDDP
VDDL
Supply Voltage
3.0
2.3
3.6
2.7
V
V
Supply Voltage, Logic Array
Output High Voltage
3.3V I/O, High Drive (OB33P)
IOH = –5.0 mA
0.9VDDP
2.4
I
OH = –10.0 mA
V
V
V
V
IOH = –2.5 mA
OH = –5.0 mA
0.9VDDP
2.4
3.3V I/O, Low Drive (OB33L)
I
VOH
Output High Voltage
2.5V I/O, High Drive (OB25H)
IOH = –200µA
2.1
2.0
1.7
I
I
OH = –10.0 mA
OH = –2.0 mA
IOH = –100µA
IOH = –1.0 mA
IOH = –2.0 mA
2.1
2.0
1.7
2.5V I/O, Low Drive (OB25L)
Output High Voltage
3.3V I/O, High Drive (OB33P)
IOL = 7.5 mA
IOL = 12.0 mA
0.1VDDP
0.4
IOL = 4.0 mA
IOL = 5.0 mA
0.1VDDP
0.4
3.3V I/O, Low Drive (OB33L)
VOL
Output High Voltage
2.5V I/O, High Drive (OB25H)
IOL = 5.0 mA
IOL = 12.0 mA
IOL = 16.0 mA
0.2
0.4
0.7
IOL = 2.5 mA
IOL = 5.0 mA
IOL = 8.0 mA
0.2
0.4
0.7
2.5V I/O, Low Drive (OB25L)
Input High Voltage
3.3V LVTTL/LVCMOS
2.5V Mode
VIH
2
1.7
VDDP + 0.3
VDDP + 0.3
V
V
Input Low Voltage
3.3V LVTTL/LVCMOS
2.5V Mode
VIL
–0.3
–0.3
0.8
0.7
Input Current
LVTTL/LVCMOS
LVTTL/LVCMOS
2
IIN
with pull-up
without pull-up
30
300
10
µA
µA
IDDQ
Quiescent Supply Current
VIN = VSS3 or VDDL
4.0
70
10
mA
Incremental Quiescent Supply
Current
4
IDDQI
400
µA
IOZ
3-State Output Leakage Current
VOH = VSS or VDDL
10
µA
Notes:
1. All process conditions. Junction Temperature: –40 to +110°C.
2. Current is negative.
3. No pull-up resistor.
4. IDDQ is augmented by IDDQI for each 2.5V I/O when operating in a mixed voltage environment.
20
v3.0
ProASIC™ 500K Family
DC Electrical Specifications (VDDP = 3.3V) (Continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Output Short Circuit Current High
3.3V High Drive
3.3 Low Drive
200
140
2
IOSH
mA
2.5V High Drive
2.5 Low Drive
120
100
Output Short Circuit Current Low
3.3V High Drive
3.3 Low Drive
160
150
IOSL
mA
2.5V High Drive
2.5 Low Drive
160
50
CI/O
I/O Pad Capacitance
10
10
pF
pF
CCLK
Notes:
Clock Input Pad Capacitance
1. All process conditions. Junction Temperature: –40 to +110°C.
2. Current is negative.
3. No pull-up resistor.
4. IDDQ is augmented by IDDQI for each 2.5V I/O when operating in a mixed voltage environment.
DC Specifications (3.3V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
VDDL
VDDP
VIH
Supply Voltage for Core
Supply Voltage for I/O Ring
Input High Voltage
2.3
3.0
2.7
3.6
V
V
0.5VDPP VDPP + 0.5
V
VIL
Input Low Voltage
–0.5
0.7VDDP
–10
0.3VDDP
V
IIPU
Input Pull-up Voltage1
Input Leakage Current2
Output High Voltage
Output Low Voltage
V
IIL
0 < VIN < VCCI
IOUT = –500 µA
IOUT = 1500 µA
+10
µA
V
VOH
VOL
CIN
0.9VDPP
0.1VDPP
10
V
Input Pin Capacitance3
pF
pF
CCLK
Notes:
CLK Pin Capacitance
5
12
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated
network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this
input voltage.
2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
v3.0
21
ProASIC™ 500K Family
AC Specifications (3.3V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
1
0 < VOUT ≤ 0.3VCCI
–12VCCI
mA
mA
1
Switching Current High
0.3VCCI ≤ VOUT < 0.9VCCI
(–17.1 + (VDDP – VOUT))
IOH(AC)
Equation A
on page 23
1, 2
0.7VCCI < VOUT < VCCI
2
(Test Point)
VOUT = 0.7VCC
–32VCCI
mA
mA
mA
1
VCCI > VOUT ≥ 0.6VCCI
16VDDP
1
Switching Current Low
0.6VCCI > VOUT > 0.1VCCI
0.18VCCI > VOUT > 0 1, 2
(26.7VOUT)
IOL(AC)
Equation B
on page 23
2
(Test Point)
VOUT = 0.18VCC
38VCCI
mA
mA
ICL
Low Clamp Current
High Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
–3 < VIN ≤ –1
–25 + (VIN + 1)/0.015
ICH
VCCI + 4 > VIN ≥ VCCI + 1
0.2VCCI to 0.6VCCI load 3
0.6VCCI to 0.2VCCI load 3
25 + (VIN – VDDP – 1)/0.015
mA
slewR
slewF
Notes:
1
1
4
4
V/ns
V/ns
1. Refer to the V/I curves in Figure 18 on page 23. Switching current characteristics for REQ# and GNT# are permitted to be one half of that
specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are
system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain
outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B)
are provided with the respective diagrams in Figure 18 on page 23. The equation defined maxima should be met by design. In order to
facilitate component testing, a maximum current test point is defined for each side of the output driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an
unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs.
pin
1/2 in. max.
output
buffer
10 pF
1k Ω
pin
1k Ω
output
buffer
10 pF
22
v3.0
ProASIC™ 500K Family
Figure 18 shows the 3.3V PCI V/I curve and the minimum
and maximum PCI drive characteristics of the ProASIC
family.
150.0
I
MAX Spec
OL
100.0
50.0
I
I
OL
MIN Spec
OL
I
MIN Spec
OH
3
0.0
0
0.5
1
1.5
2
2.5
3.5
4
–50.0
–100.0
–150.0
I
OH
I
MAX Spec
OH
Voltage Out (V)
Figure 18 • 3.3V PCI V/I Curve for ProASIC Family
Equation A
Equation B
I
OH = (98.0/VCCI) * (VOUT – VCCI) * (VOUT + 0.4VCCI
)
I
OL = (256/VCCI) * VOUT * (VCCI – VOUT)
for 0.7 VCCI < VOUT < VCCI
for 0V < VOUT < 0.18 VCCI
Timing Characteristics
Very Long Lines
Timing characteristics for ProASIC 500K devices fall into
three categories: family dependent, device dependent, and
design-dependent. The input and output buffer
characteristics are common to all ProASIC 500K family
members. Internal routing delays are device-dependent.
Design dependency means that actual delays are not
determined until after placement and routing of the user’s
design are completed. Design timing attributes may then be
determined by using Timer, the Static Analysis tool
Some nets in the design are very long lines marked using
VLLs, which are special routing resources that span
multiple rows, columns, or modules. This increases
capacitance and resistance, resulting in longer net delays
for macros connected to long tracks. Typically, up to 6
percent of nets in a fully utilized device require long tracks.
Very long lines contribute between 4 and 8.4ns routing delay
depending on the fanout. This additional delay is
represented statistically in higher fanout routing delays.
embedded into Designer software,
or performing
simulation with post-layout delays using ModelSim
Simulator integrated into Libero design environment.
Timing Derating
Since ProASIC 500K devices are manufactured with a CMOS
process, device performance will vary with temperature,
voltage, and process. Minimum timing parameters reflect
maximum operating voltage, minimum operating
temperature, and optimal process variations. Maximum
timing parameters reflect minimum operating voltage,
maximum operating temperature, and worst-case process
variations (within process specifications).
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most critical
timing paths. Critical nets are determined by net property
assignment prior to placement and routing. Up to 6 percent
of the nets in a design may be designated as critical, while
more than 90% of the nets in a design are typical. User’s can
control priorities between critical nets and use routing
constraints, such as set_critical to focus the routing
optimization on the most critical ones. Please see the
Designer User’s Guide for more information on using
constraints.
v3.0
23
ProASIC™ 500K Family
Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70°C, VCCA = 2.3V)
Junction Temperature (TJ)
VCCA
2.3V
2.5V
2.7V
–55°C
0.84
–40°C
0.86
0°C
0.91
0.87
0.84
25°C
0.94
0.90
0.86
70°C
1.00
0.96
0.92
85°C
1.02
0.98
0.93
110°C
1.05
125°C
1.07
0.81
0.83
1.01
1.02
0.77
0.79
0.96
0.98
Slew Rates Measured at Cout = 10pF (Total Output Load), Nominal Power Supplies and 25°C
Type
Trig. Lev.
Rising Edge
pS
Slew Rate
V/nS
Falling Edge
pS
Slew Rate
V/nS
OB33PH
OB33PN
OB33PL
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
397
463
567
467
620
813
750
850
1310
793
870
1287
470
533
770
597
873
1153
3.33
2.85
2.33
2.83
2.13
1.62
1.33
1.18
0.76
1.26
1.15
0.78
2.13
1.81
1.30
1.68
1.15
0.87
390
450
527
700
767
1100
310
390
510
430
730
1037
433
527
753
707
760
1563
-3.38
-2.93
-2.51
-1.89
-1.72
-1.20
-3.23
-2.56
-1.96
-2.33
-1.37
-0.96
-2.31
-1.90
-1.33
-1.42
-1.32
-0.54
OB33LH
OB33LN
OB33LL
OB25HH
OB25HN
OB25HL
OB25LH
OB25LN
OB25LL
OB25LPHH
OB25LPHN
OB25LPHL
OB25LPLH
OB25LPLN
OB25LPLL
Tristate Buffer Delays
EN
A
PAD
OTBx
A
50%
VOH
EN
50%
EN
50%
50%
VCC
50%
VOH
50%
50%
50%
VOL
90%
PAD
VOL
PAD
PAD
GND
50%
10%
50%
tDLH
tDHL
tENZL
tENZH
24
v3.0
ProASIC™ 500K Family
Tristate Buffer Delays
(Worst-Case Commercial Conditions, VDDP = 3.0V, VDDL = 2.3V, TJ = 70°C, fCLOCK = 250 MHz)
Max
tDLH
Max
tDHL
Max
tENZH
Max
tENZL
Macro Type Description
Units
OTB33PH
OTB33PN
OTB33PL
OTB33LH
OTB33LN
OTB33LL
OTB25HH
OTB25HN
OTB25HL
OTB25LH
OTB25LN
OTB25LL
3.3V, PCI Output Current, High Slew Rate
4.2
4.7
5.3
6.0
6.7
7.5
6.9
7.2
8.2
10.4
11.0
11.9
5.1
6.0
6.9
7.4
8.6
9.8
4.1
5.9
7.0
4.2
4.8
5.3
6.0
6.7
7.5
6.9
7.2
8.2
10.4
11.0
11.9
5.1
6.0
6.8
7.4
8.5
9.8
3.67
5.3
6.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.3V, PCI Output Current, Nominal Slew Rate
3.3V, PCI Output Current, Low Slew Rate
3.3V, Low Output Current, High Slew Rate
3.3V, Low Output Current, Nominal Slew Rate
3.3V, Low Output Current, Low Slew Rate
2.5V, High Output Current, High Slew Rate
2.5V, High Output Current, Nominal Slew Rate
2.5V, High Output Current, Low Slew Rate
2.5V, Low Output Current, High Slew Rate
2.5V, Low Output Current, Nominal Slew Rate
2.5V, Low Output Current, Low Slew Rate
6.6
5.9
9.2
8.9
12.0
3.6
5.2
11.8
3.4
4.9
6.4
6.1
5.2
8.1
11.7
4.4
7.4
9.3
7.8
5.5
8.3
10.9
5.1
OTB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate
OTB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew Rate
OTB25LPHL 2.5V, Low Power, High Output Current, Low Slew Rate
OTB25LPLH 2.5V, Low Power, Low Output Current, High Slew Rate
OTB25LPLN 2.5V, Low Power, Low Output Current, Nominal Slew Rate
OTB25LPLL 2.5V, Low Power, Low Output Current, Low Slew Rate
7.7
9.8
8.6
12.6
17.0
12.3
16.7
Notes:
1. tDLH = Data-to-Pad HIGH
2. tDHL = Data-to-Pad LOW
3. tENZH = Enable-to-Pad, Z to HIGH
4. tENZL = Enable-to-Pad, Z to LOW
Output Buffer Delays
A
50%
VOH
50%
A
PAD
50%
PAD
VOL
50%
OBx
tDLH
tDHL
v3.0
25
ProASIC™ 500K Family
Output Buffer Delays
(Worst-Case Commercial Conditions, VDDP = 3.0V, VDDL = 2.3V, TJ = 70°C, fCLOCK = 250 MHz)
Macro Type Description
Max. tDLH
Max. tDHL
Units
OB33PH
OB33PN
OB33PL
3.3V, PCI Output Current, High Slew Rate
4.2
4.7
5.3
6.0
6.7
7.5
6.9
7.2
8.2
10.4
11.0
11.9
5.1
6.0
6.9
7.4
8.6
9.8
4.1
5.9
7.1
6.6
9.2
12.1
3.6
5.2
6.4
5.5
8.3
10.9
5.1
7.7
9.8
8.6
12.6
17.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.3V, PCI Output Current, Nominal Slew Rate
3.3V, PCI Output Current, Low Slew Rate
OB33LH
OB33LN
OB33LL
3.3V, Low Output Current, High Slew Rate
3.3V, Low Output Current, Nominal Slew Rate
3.3V, Low Output Current, Low Slew Rate
OB25HH
OB25HN
OB25HL
OB25LH
OB25LN
OB25LL
2.5V, High Output Current, High Slew Rate
2.5V, High Output Current, Nominal Slew Rate
2.5V, High Output Current, Low Slew Rate
2.5V, Low Output Current, High Slew Rate
2.5V, Low Output Current, Nominal Slew Rate
2.5V, Low Output Current, Low Slew Rate
OB25LPHH
OB25LPHN
OB25LPHL
OB25LPLH
OB25LPLN
OB25LPLL
Notes:
2.5V, Low Power, High Output Current, High Slew Rate
2.5V, Low Power, High Output Current, Nominal Slew Rate
2.5V, Low Power, High Output Current, Low Slew Rate
2.5V, Low Power, Low Output Current, High Slew Rate
2.5V, Low Power, Low Output Current, Nominal Slew Rate
2.5V, Low Power, Low Output Current, Low Slew Rate
1.
tDLH = Data-to-Pad HIGH
2. tDHL = Data-to-Pad LOW
Input Buffer Delays
VCC
PAD
0V
50%
50%
VCC
50%
Y
PAD
Y
GND
50%
IBx
tINYH
tINYL
Input Buffer Delays
(Worst-Case Commercial Conditions, VDDP = 3.0V, VDDL = 2.3V, TJ = 70°C, fCLOCK = 250 MHz)
Max.
tINYH
Max.
tINYL
Macro Type
Description
Units
IB25
2.5V, CMOS Input Levels, No Pull-up Resistor
2.5V, CMOS Input Levels, Low Power
2.2
2.2
1.9
0.7
1.4
1.0
ns
ns
ns
IB25LP
IB33
3.3V, CMOS Input Levels, No Pull-up Resistor
Notes:
1. tINYH = Input Pad-to-Y HIGH
2. tINYL = Input Pad-to-Y LOW
26
v3.0
ProASIC™ 500K Family
Global Input Buffer Delays
(Worst-Case Commercial Conditions, VDDP = 3.0V, VDDL = 2.3V, TJ = 70°C, fCLOCK = 250 MHz)
Max.
tINYH
Max.
tINYL
Macro Type
Description
Units
GL25
2.5V, CMOS Input Levels
2.1
2.3
3.8
2.1
2.3
3.8
1.6
2.3
1.2
1.6
2.3
1.2
ns
ns
ns
ns
ns
ns
GL25LP
GL33
2.5V, CMOS Input Levels
3.3V, CMOS Input Levels
GL25U
GL25LPU
GL33U
2.5V, CMOS Input Levels, with Pull-up Resistor
2.5V, CMOS Input Levels, Low Power, with Pull-up Resistor
3.3V, CMOS Input Levels, with Pull-up Resistor
Predicted Global Routing Delay*
(Worst-Case Commercial Conditions, VDDP = 3.0V, VDDL = 2.3V, TJ = 70°C, fCLOCK = 250 MHz)
Parameter
Description
Max.
Units
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (fully loaded row—32 inputs)
Input High to Low (fully loaded row—32 inputs)
Input Low to High (minimally loaded row—1 input)
Input High to Low (minimally loaded row—1 input)
1.2
1.1
0.9
0.9
ns
ns
ns
ns
* The timing delay difference between tile locations is less than 15ps.
Global Routing Skew
(Worst-Case Commercial Conditions, VDDP = 3.0V, VDDL = 2.3V, TJ = 70°C, fCLOCK = 250 MHz)
Parameter
Description
Max.
Units
tRCKSWH
tRCKSHH
Maximum Skew Low to High
Maximum Skew High to Low
0.3
0.3
ns
ns
Module Delays
A
B
C
Y
A
B
50% 50%
50% 50%
C
Y
50% 50%
50%
50%
50%
50%
50%
50%
tDCLH
tDCHL
tDBLH
tDBHL
tDALH
tDAHL
v3.0
27
ProASIC™ 500K Family
Sample Macrocell Library Listing
(Worst-Case Commercial Conditions, VDDL = 2.3V, TJ = 70º C)
Maximum
Intrinsic Delay
Minimum
Setup/Hold
Cell Name
Description
Units
NAND2
AND2
NOR3
MUX2L
OA21
XOR2
LDL
2-Input NAND
2-Input AND
3-Input NOR
2-1 Mux with Active Low Select
2-Input OR into a 2-Input AND
2-Input Exclusive OR
Active Low Latch (LH/HL)
0.4
0.4
0.4
0.4
0.4
ns
ns
ns
ns
ns
ns
0.3
D: 0.3/0.2
tsetup 0.5
ns
ns
t
hold 0.2
DFFL
Negative Edge-Triggered D-type Flip-Flop (LH/HL)
CLK-Q:
0.4/0.4
tsetup 0.4
thold 0.2
Note: Assumes fanout of two.
Embedded Memory Specifications
This section focuses on the embedded memory of the
ProASIC 500K family. It describes the SRAM and FIFO
interface signals and includes timing diagrams that show
the relationships of signals as they pertain to single
embedded memory blocks (Table 4 and Table 5 on page 34).
Refer to Table 3 on page 12 for basic RAM configurations.
Simultaneous Read and Write to the same location must be
done with care. On such accesses the DI bus is output to the
DO bus.
Note: The difference between synchronous transparent
and pipeline modes is the timing of all the output
signals from the memory. In transparent mode
the outputs will change within the same clock
cycle to reflect the data requested by the currently
valid access to the memory. However, if clock
cycles are short (high clock speed), the data
requires most of the clock cycle to change to valid
values (stable signals). This makes processing of
this data in the same clock cycle nearly
impossible. Most designers solve this problem by
adding registers at all outputs of the memory to
push the data processing into the next clock cycle.
In this setup, the whole cycle time can be used to
process the data. To simplify the use of this kind of
memory setup these registers have been
implemented as part of the memory primitive
and are available to the user in the synchronous
pipeline mode. In this mode, the output signals
will change shortly after the second rising edge,
following the initiation of the read access.
Enclosed Timing Diagrams—SRAM Mode:
• Synchronous RAM Read, Access Timed Output Strobe
(Synchronous Transparent)
• Synchronous RAM Read, Pipeline Mode Outputs
(Synchronous Pipelined)
• Asynchronous RAM Write
• Asynchronous RAM Read, Address Controlled, RDB=0
• Asynchronous RAM Read, RDB Controlled
• Synchronous RAM Write
Table 4 • Memory Block SRAM Interface Signals
SRAM Signal
Bits
In/Out
Description
WCLKS
RCLKS
RADDR<0:7>
RBLKB
RDB
1
1
8
1
1
8
1
9
1
9
1
1
1
IN
IN
Write clock used on synchronization on write side
Read clock used on synchronization on read side
Read address
Negative true read block select
Negative true read pulse
IN
IN
IN
WADDR<0:7>
WBLKB
DI<0:8>
WRB
IN
Write address
IN
Negative true write block select
Input data bits <0:8>, <8> can be used for parity in
Negative true write pulse
IN
IN
DO<0:8>
RPE
OUT
OUT
OUT
IN
Output data bits <0:8>, <8> can be used for parity out
Read parity error
WPE
Write parity error
PARODD
Selects odd parity generation/detect when high, even when low
Note: Not all signals shown are used in all modes.
28
v3.0
ProASIC™ 500K Family
Synchronous RAM Read, Access Timed Output Strobe (Synchronous Transparent)
RCLKS
Cycle Start
RB=(RBD+RBLKB)
New Valid
RADDR
Address
Old Data Out
New Valid Data Out
DO
RPE
t
RACS
t
RDCS
t
RDCH
t
RACH
t
OCH
t
RPCH
t
t
CMH
CML
t
OCA
t
RPCA
t
CCYC
TJ = 0°C to 110°C; VDDL = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
CCYC
CMH
Cycle time
7.5
3.0
3.0
7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock high phase
CML
Clock low phase
OCA
New DO access from RCLKS ↑
Old DO valid from RCLKS ↑
RADDR hold from RCLKS ↑
RADDR setup to RCLKS ↑
RDB hold from RCLKS ↑
RDB setup to RCLKS ↑
New RPE access from RCLKS ↑
Old RPE valid from RCLKS ↑
OCH
3.0
RACH
RACS
RDCH
RDCS
RPCA
RPCH
0.5
1.0
0.5
1.0
9.5
3.0
v3.0
29
ProASIC™ 500K Family
Synchronous RAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
RCLKS
Cycle Start
RB=(RDB+RBLKB)
New Valid
RADDR
Address
DO
New Valid Data Out
New RPE Out
Old Data Out
RPE
Old RPE Out
t
t
RACS
OCA
t
t
RACH
RPCH
t
t
RDCH
OCH
t
t
RDCS
RPCA
t
t
CMH
CML
t
CCYC
TJ = 0°C to 110°C; VDDL = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
CCYC
CMH
Cycle time
7.5
3.0
3.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock high phase
CML
Clock low phase
OCA
New DO access from RCLKS ↑
Old DO valid from RCLKS ↑
RADDR hold from RCLKS ↑
RADDR setup to RCLKS ↑
RDB hold from RCLKS ↑
RDB setup to RCLKS ↑
New RPE access from RCLKS ↑
Old RPE valid from RCLKS ↑
OCH
.75
RACH
RACS
RDCH
RDCS
RPCA
RPCH
0.5
1.0
0.5
1.0
4.0
1.0
30
v3.0
ProASIC™ 500K Family
Asynchronous RAM Write
WADDR
WB=(WRB+WBLKB)
DI
WPE
t
t
AWRS
AWRH
t
t
DWRH
WPDH
t
WPDA
t
DWRS
t
t
WRMH
WRML
t
WRCYC
TJ = 0°C to 110°C; VDDL = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
AWRH
AWRS
DWRH
DWRS
DWRS
WPDA
WPDH
WRCYC
WRMH
WRML
WADDR hold from WB ↑
WADDR setup to WB ↓
DI hold from WB ↑
DI setup to WB ↑
DI setup to WB ↑
WPE access from DI
WPE hold from DI
Cycle time
1.0
0.5
1.5
0.5
2.5
3.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARGEN is inactive
PARGEN is active
WPE is invalid while
PARGEN is active
1.0
7.5
3.0
3.0
WB high phase
Inactive
Active
WB low phase
v3.0
31
ProASIC™ 500K Family
Asynchronous RAM Read, Address Controlled, RDB=0
RADDR
DO
RPE
t
OAH
t
RPAH
t
OAA
t
RPAA
t
ACYC
TJ = 0°C to 110°C; VDDL = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
ACYC
OAA
Read cycle time
7.5
7.5
ns
ns
ns
ns
ns
New DO access from RADDR stable
Old DO hold from RADDR stable
New RPE access from RADDR stable
Old RPE hold from RADDR stable
OAH
3.0
3.0
RPAA
RPAH
10.0
Asynchronous RAM Read, RDB Controlled
RB=(RDB+RBLKB)
DO
RPE
t
ORDH
t
RPRDH
t
ORDA
t
RPRDA
t
t
RDML
RDMH
t
RDCYC
TJ = 0°C to 110°C; VDDL = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
ORDA
New DO access from RB ↓
Old DO valid from RB ↓
Read cycle time
7.5
ns
ns
ns
ns
ns
ns
ns
ORDH
RDCYC
RDMH
RDML
3.0
7.5
3.0
3.0
9.5
RB high phase
Inactive setup to new cycle
Active
RB low phase
RPRDA
RPRDH
New RPE access from RB ↓
Old RPE valid from RB ↓
3.0
32
v3.0
ProASIC™ 500K Family
Synchronous RAM Write
WCLKS
WRB, WBLKB
WADDR, DI
WPE
Cycle Start
t
, t
WRCH WBCH
t
, t
WRCS WBCS
t
, t
DCS WDCS
t
WPCH
t
, t
DCH WACH
t
WPCA
t
t
CML
CMH
t
CCYC
TJ = 0°C to 110°C; VDDL = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
CCYC
CMH
Cycle time
7.5
3.0
3.0
0.5
1.0
0.5
1.0
3.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock high phase
CML
Clock low phase
DCH
DI hold from WCLKS ↑
DI setup to WCLKS ↑
DCS
WACH
WDCS
WPCA
WPCH
WADDR hold from WCLKS ↑
WADDR setup to WCLKS ↑
New WPE access from WCLKS ↑
Old WPE valid from WCLKS ↑
WRB & WBLKB hold from WCLKS ↑
WPE is invalid while
PARGEN is active
0.5
WRCH,
WBCH
0.5
1.0
WRCS,
WBCS
WRB & WBLKB setup to WCLKS ↑
ns
Note: On simultaneous read and write accesses to the same location DI is output to DO.
v3.0
33
ProASIC™ 500K Family
Asynchronous FIFO Full and Empty Transitions
The asynchronous FIFO accepts writes and reads while not
full or not empty. When the FIFO is full, all writes are
inhibited. Conversely, when the FIFO is empty, all reads are
inhibited. A problem is created if the FIFO is written during
the transition out of full to not full or read during the
transition out of empty to not empty. The exact time at
which the write (read) operation changes from inhibited to
accepted after the read (write) signal which causes the
transition from full (empty) to not full (empty) is
indeterminate. This indeterminate period starts 1ns after
the RB (WB) transition which deactivates full (not empty).
For slow cycles, the indeterminate period ends 3ns after the
RB (WB) transition. For fast cycles, this period ends either
3ns or (7.5ns - tRDL (tWRL)) after the RB (WB) transition,
whichever is later.
on page 35. For basic RAM configurations, see Table 3 on
page 12. For memory block interface signals, see Table 4 on
page 28, and for memory block FIFO signals, see Table 5.
Enclosed Timing Diagrams—FIFO Mode:
• Asynchronous FIFO Read
• Asynchronous FIFO Write
• Synchronous FIFO Read, Access Timed Output
Strobe (Synchronous Transparent)
• Synchronous FIFO Read, Pipeline Mode Outputs
(Synchronous Pipelined)
• Synchronous FIFO Write
• FIFO Reset
The timing diagram for write is shown in Figure 19 on
page 35. The timing diagram for read is shown in Figure 20
Table 5 • Memory Block FIFO Interface Signals
FIFO Signal
Bits
In/Out
Description
WCLKS
RCLKS
1
1
8
1
1
1
1
9
1
2
IN
Write clock used to synchronize write side
Read clock used to synchronize read side
Direct configuration implements static flag logic
Active low read block select
IN
LEVEL <0:7>
RBLKB
IN
IN
RDB
IN
Active low read pulse
RESET
IN
Active low reset for FIFO pointers
WBLKB
DI<0:8>
WRB
IN
Active low write block select
IN
Input data bits <0:8>, <8> can be used for parity in.
Active low write pulse
IN
FULL, EMPTY
OUT
FIFO flags. FULL prevents write and EMPTY prevents read
EQTH is true when the FIFO holds (LEVEL) words. GEQTH is true when the
FIFO holds (LEVEL) words or more
EQTH, GEQTH
2
OUT
DO<0:8>
RPE
9
1
1
3
1
OUT
OUT
OUT
IN
Output data bits <0:8>, <8> can be used for parity out.
Read parity error
WPE
Write parity error
LGDEP <0:2>
PARODD
Configures DEPTH of the FIFO to 2 (LGDEP+1)
IN
Selects odd parity generation/detect when high, even when low
34
v3.0
ProASIC™ 500K Family
FULL
RB
Write
cycle
Write inhibited
Write accepted
1ns
3ns
WB
Figure 19 • Write Timing Diagram
EMPTY
WB
Read
cycle
Read inhibited
Read accepted
1ns
3ns
RB
Figure 20 • Read Timing Diagram
v3.0
35
ProASIC™ 500K Family
Asynchronous FIFO Read
Cycle Start
RB=(RDB+RBLKB)
(Empty inhibits read)
DO
RPE
WB
EMPTY
FULL
EQTH, GETH
t
t
t
, t
RDWRS
ERDH FRDH
t
, t
ORDH
ERDA FRDA
t
t
RPRDH
THRDH
t
t
ORDA
THRDA
t
RPRDA
t
t
RDL
RDH
t
RDCYC
TJ = 0°C to 110°C; VDDL = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
ERDH,
FRDH,
THRDH
Old EMPTY, FULL, EQTH, & GETH valid
hold time from RB ↑
0.5
ns
Empty/full/thresh are invalid
from the end of hold until the
new access is complete
ERDA
New EMPTY access from RB ↑
FULL↓ access from RB ↑
New DO access from RB ↓
Old DO valid from RB ↓
Read cycle time
3.01
3.01
7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FRDA
ORDA
ORDH
RDCYC
RDWRS
3.0
1.0
7.5
3.02
WB ↑, clearing EMPTY, setup to
RB ↓
Enabling the read operation
Inhibiting the read operation
Inactive
RDH
RB high phase
3.0
3.0
9.5
RDL
RB low phase
Active
RPRDA
RPRDH
THRDA
Notes:
New RPE access from RB ↓
Old RPE valid from RB ↓
EQTH or GETH access from RB↑
4.0
4.5
1. At fast cycles, ERDA & FRDA = MAX ((7.5ns – RDL), 3.0ns)
2. At fast cycles, RDWRS (for enabling read) = MAX ((7.5ns – WRL), 3.0ns)
36
v3.0
ProASIC™ 500K Family
Asynchronous FIFO Write
Cycle Start
WB=(WRB+WBLKB)
DI
WPE
(Full inhibits write)
RB
FULL
EMPTY
EQTH, GETH
t
t
WRRDS
DWRH
t
t
t
WPDH
WPDA
DWRS
t
, t
EWRH FWRH
t
, t
EWRA FWRA
t
THWRH
t
THWRA
t
t
WRL
WRH
t
WRCYC
TJ = 0°C to 110°C; VDDL = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
DWRH
DWRS
DWRS
DI hold from WB ↑
DI setup to WB ↑
DI setup to WB ↑
1.5
0.5
2.5
ns
ns
ns
ns
PARGEN is inactive
PARGEN is active
EWRH,
FWRH,
THWRH
Old EMPTY, FULL, EQTH, & GETH valid
hold time after WB ↑
0.5
Empty/full/thresh are invalid
from the end of hold until the
new access is complete
EWRA
EMPTY ↓ access from WB ↑
New FULL access from WB ↑
EQTH or GETH access from WB ↑
WPE access from DI
WPE hold from DI
3.01
3.01
4.5
ns
ns
ns
ns
ns
ns
ns
FWRA
THWRA
WPDA
3.0
WPE is invalid while
PARGEN is active
WPDH
WRCYC
WRRDS
1.0
1.0
Cycle time
7.5
3.02
RB ↑, clearing FULL, setup to
WB ↓
Enabling the write operation
Inhibiting the write operation
Inactive
WRH
WRL
Notes:
WB high phase
3.0
3.0
ns
ns
WB low phase
Active
1. At fast cycles, EWRA, FWRA = MAX ((7.5ns – WRL), 3.0ns)
2. At fast cycles, WRRDS (for enabling write) = MAX ((7.5ns – RDL), 3.0ns)
v3.0
37
ProASIC™ 500K Family
Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)
RCLKS
RDB
Cycle Start
DO
Old Data Out
New Valid Data Out (Empty Inhibits Read)
RPE
EMPTY
FULL
EQTH, GETH
t
t
t
, t
RDCH
ECBH FCBH
, t
t
ECBA FCBA
RDCS
t
t
THCBH
t
OCH
t
RPCH
HCBA
t
OCA
t
RPCA
t
t
CMH
CML
t
CCYC
TJ = 0°C to 110°C; VDDL = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
CCYC
CMH
Cycle time
7.5
3.0
ns
ns
ns
ns
ns
Clock high phase
Clock low phase
CML
3.0
ECBA
FCBA
New EMPTY access from RCLKS ↓
FULL ↓ access from RCLKS ↓
3.01
3.01
ECBH,
FCBH,
THCBH
Old EMPTY, FULL, EQTH, & GETH valid
hold time from RCLKS ↓
Empty/full/thresh are invalid
from the end of hold until the
new access is complete
1.0
3.0
ns
OCA
New DO access from RCLKS ↑
Old DO valid from RCLKS ↑
RDB hold from RCLKS ↑
7.5
ns
ns
ns
ns
ns
ns
ns
OCH
RDCH
RDCS
RPCA
RPCH
HCBA
Note:
0.5
1.0
9.5
RDB setup to RCLKS ↑
New RPE access from RCLKS ↑
Old RPE valid from RCLKS ↑
EQTH or GETH access from RCLKS ↓
3.0
4.5
1. At fast cycles, ECBA & FCBA = MAX ((7.5ns – CMH), 3.0ns)
38
v3.0
ProASIC™ 500K Family
Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)
RCLKS
Cycle Start
RDB
DO
RPE
Old Data Out
New Valid Data Out
New RPE Out
Old RPE Out
EMPTY
FULL
EQTH, GETH
t
, t
t
ECBH FCBH
OCA
t
t
t
t
, t
RDCH
ECBA FCBA
t
t
RDCS
THCBH
t
RPCH
OCH
HCBA
t
RPCA
t
t
CML
CMH
t
CCYC
TJ = 0°C to 110°C; VDDL = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
CCYC
CMH
Cycle time
7.5
3.0
ns
ns
ns
ns
ns
ns
Clock high phase
Clock low phase
CML
3.0
ECBA
FCBA
New EMPTY access from RCLKS ↓
FULL ↓ access from RCLKS ↓
3.01
3.01
ECBH,
FCBH,
THCBH
Old EMPTY, FULL, EQTH, & GETH valid
hold time from RCLKS ↓
1.0
Empty/full/thresh are invalid
from the end of hold until the
new access is complete
OCA
New DO access from RCLKS ↑
Old DO valid from RCLKS ↑
RDB hold from RCLKS ↑
2.0
ns
ns
ns
ns
ns
ns
ns
OCH
0.75
RDCH
RDCS
RPCA
RPCH
HCBA
Note:
0.5
1.0
4.0
RDB setup to RCLKS ↑
New RPE access from RCLKS ↑
Old RPE valid from RCLKS ↑
EQTH or GETH access from RCLKS ↓
1.0
4.5
1. At fast cycles, ECBA & FCBA = MAX ((7.5ns – CMS), 3.0ns)
v3.0
39
ProASIC™ 500K Family
Synchronous FIFO Write
WCLKS
Cycle Start
WRB, WBLKB
(Full Inhibits Write)
DI
WPE
FULL
EMPTY
EQTH, GETH
t
, t
t
t
, t
WRCH WBCH
ECBH FCBH
, t
t
, t
ECBA FCBA
WRCS WBCS
t
t
DCS
HCBH
t
t
HCBA
WPCH
t
DCH
t
WPCA
t
t
CML
CMH
t
CCYC
TJ = 0°C to 110°C; VDDL = 2.3V to 2.7V
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
CMH
CML
Cycle time
7.5
3.0
ns
ns
ns
ns
ns
ns
ns
ns
Clock high phase
Clock low phase
3.0
DCH
DI hold from WCLKS ↑
DI setup to WCLKS ↑
0.5
DCS
1.0
FCBA
ECBA
New FULL access from WCLKS ↓
EMPTY↓ access from WCLKS ↓
3.01
3.01
ECBH,
FCBH,
HCBH
Old EMPTY, FULL, EQTH, & GETH valid
hold time from WCLKS ↓
1.0
0.5
Empty/full/thresh are invalid
from the end of hold until the
new access is complete
HCBA
WPCA
WPCH
EQTH or GETH access from WCLKS ↓
New WPE access from WCLKS ↑
Old WPE valid from WCLKS ↑
4.5
3.0
ns
ns
ns
ns
WPE is invalid while
PARGEN is active
WRCH,
WBCH
WRB & WBLKB hold from WCLKS ↑
0.5
1.0
WRCS,
WBCS
WRB & WBLKB setup to WCLKS ↑
ns
Note:
1. At fast cycles, ECBA & FCBA = MAX ((7.5ns – CMH), 3.0ns)
40
v3.0
ProASIC™ 500K Family
FIFO Reset
RESETB
Cycle Start
WRB, WBLKB
WCLKS, RCLKS
FULL
Cycle Start
EMPTY
EQTH, GETH
t
t
CBRSS
t
, t
t
ERSA FRSA
CBRSH
t
WBRSH
t
THRSA
RSL
t
WBRSS
TJ = 0°C to 110°C; VDDL = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
CBRSH
CBRSS
ERSA
WCLKS or RCLKS ↑ hold from RESETB ↑
WCLKS or RCLKS ↓ setup to RESETB ↑
New EMPTY ↑ access from RESETB ↓
FULL ↓ access from RESETB ↓
RESETB low phase
1.5
1.5
3.0
3.0
7.5
4.5
1.5
1.5
ns
ns
ns
ns
ns
ns
ns
ns
Synchronous mode only
Synchronous mode only
FRSA
RSL
THRSA
WBRSH
WBRSS
EQTH or GETH access from RESETB ↓
WB ↓ hold from RESETB ↑
Asynchronous mode only
Asynchronous mode only
WB ↑ setup to RESETB ↑
v3.0
41
ProASIC™ 500K Family
Pin Description
I/O
User Input/Output
VPN
Programming Supply Pin
The I/O pin functions as an input, output, three-state, or
bidirectional buffer. Input and output signal levels are
compatible with standard LVTTL and LVCMOS
specifications. Unused I/O pins are configured as inputs
with pull-up resistors.
This pin must be connected to GND during normal
operation, or it can remain at –12V in an ISP application.
This pin must not float.
TMS
Test Mode Select
The TMS pin controls the use of Boundary Scan circuitry.
N/C
No Connect
TCK
Test Clock
To maintain compatibility with future Actel ProASIC
products it is recommended that this pin not be connected
to the circuitry on the board.
Clock input pin for Boundary Scan.
TDI
Test Data In
Serial input for Boundary Scan.
GL
Global Input Pin
TDO
Test Data Out
Low skew input pin for clock or other global signals. Input
only. This pin can be configured with a pull-up resistor.
Serial output for Boundary Scan.
TRST
Test Reset Input
GND
Ground
Asynchronous, active low input pin for resetting Boundary
Scan circuitry.
Common ground supply voltage.
VDDL
Logic Array Power Supply Pin
RCK
Running Clock
2.5V supply voltage.
A free running clock is needed during programming if the
programmer cannot guarantee that TCK will be
uninterrupted.
VDDP
I/O Pad Power Supply Pin
2.5V or 3.3V supply voltage.
VPP
Programming Supply Pin
This pin must be connected to VDDP during normal
operation, or it can remain at 16.5V in an ISP application.
This pin must not float.
42
v3.0
ProASIC™ 500K Family
Package Pin Assignments
208-Pin PQFP
208
1
208-Pin PQFP
v3.0
43
ProASIC™ 500K Family
208-Pin PQFP
Pin
Number
A500K050
Function
A500K130
Function
A500K180
Function
A500K270
Function
Pin
Number
A500K050
Function
A500K130
Function
A500K180
Function
A500K270
Function
1
GND
I/O
GND
I/O
GND
I/O
GND
I/O
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
2
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
GND
I/O
VDDL
GND
I/O
VDDL
GND
I/O
VDDL
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
VDDP
I/O
VDDL
VDDP
I/O
VDDL
VDDP
I/O
VDDL
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GL
GL
GL
GL
I/O
I/O
I/O
I/O
GL
GL
GL
GL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
I/O
VDDL
I/O
VDDL
I/O
VDDL
I/O
VDDL
VDDP
I/O
VDDL
VDDP
I/O
VDDL
VDDP
I/O
VDDL
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
GND
I/O
VDDP
GND
I/O
VDDP
GND
I/O
VDDP
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
TDI
TMS
VDDP
TCK
TDI
TMS
VDDP
TCK
TDI
TMS
VDDP
TCKO
TDI
TMS
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
44
v3.0
ProASIC™ 500K Family
208-Pin PQFP (Continued)
Pin
Number
A500K050
Function
A500K130
Function
A500K180
Function
A500K270
Function
Pin
Number
A500K050
Function
A500K130
Function
A500K180
Function
A500K270
Function
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
GND
VPP
VPN
TDO
TRST
RCK
I/O
GND
VPP
VPN
TDO
TRST
RCK
I/O
GND
VPP
VPN
TDO
TRST
RCK
I/O
GND
VPP
VPN
TDO
TRST
RCK
I/O
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDL
I/O
VDDP
VDDL
I/O
VDDP
VDDL
I/O
VDDP
VDDL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VDDP
I/O
GND
VDDP
I/O
GND
VDDP
I/O
GND
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
I/O
VDDL
I/O
VDDL
I/O
VDDL
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GL
GL
GL
GL
I/O
I/O
I/O
I/O
GL
GL
GL
GL
VDDP
VDDL
I/O
VDDP
VDDL
I/O
VDDP
VDDL
I/O
VDDP
VDDL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VDDL
I/O
GND
VDDL
I/O
GND
VDDL
I/O
GND
VDDL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
VDDP
VDDP
VDDP
VDDP
v3.0
45
ProASIC™ 500K Family
Package Pin Assignments (Continued)
272-Pin PBGA (Bottom View)
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
46
v3.0
ProASIC™ 500K Family
272-Pin PBGA
Pin
Number
A500K050 A500K130
Pin
Number
A500K050 A500K130
Pin
Number
A500K050 A500K130
Function
Function
Function
Function
Function
Function
A1
A2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
C7
C8
I/O
I/O
I/O
I/O
F17
F18
F19
F20
G1
VDDP
I/O
VDDP
I/O
A3
C9
I/O
I/O
I/O
I/O
A4
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
I/O
I/O
I/O
I/O
A5
I/O
I/O
I/O
I/O
A6
I/O
I/O
G2
I/O
I/O
A7
I/O
I/O
G3
I/O
I/O
A8
I/O
I/O
G4
I/O
I/O
A9
I/O
I/O
G17
G18
G19
G20
H1
I/O
I/O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
H2
I/O
I/O
I/O
I/O
H3
I/O
I/O
D2
I/O
I/O
H4
I/O
I/O
D3
I/O
I/O
H17
H18
H19
H20
J1
I/O
I/O
D4
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
I/O
I/O
I/O
D5
I/O
I/O
D6
GL
GL
D7
I/O
I/O
B2
D8
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
I/O
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
I/O
J2
GL
GL
B3
D9
J3
GL
GL
B4
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E1
J4
VDDL
GND
GND
GND
GND
VDDL
GL
VDDL
GND
GND
GND
GND
VDDL
GL
B5
J9
B6
J10
J11
J12
J17
J18
J19
J20
K1
B7
B8
B9
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
I/O
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
K2
I/O
I/O
I/O
I/O
K3
I/O
I/O
E2
I/O
I/O
K4
VDDL
GND
GND
GND
GND
VDDL
I/O
VDDL
GND
GND
GND
GND
VDDL
I/O
E3
I/O
I/O
K9
E4
VDDP
VDDP
I/O
VDDP
VDDP
I/O
K10
K11
K12
K17
K18
K19
K20
L1
E17
E18
E19
E20
F1
I/O
I/O
C2
I/O
I/O
C3
I/O
I/O
I/O
I/O
C4
F2
I/O
I/O
I/O
I/O
C5
F3
I/O
I/O
I/O
I/O
C6
F4
VDDP
VDDP
L2
I/O
I/O
v3.0
47
ProASIC™ 500K Family
272-Pin PBGA (Continued)
Pin
Number
A500K050 A500K130
Pin
Number
A500K050 A500K130
Pin
Number
A500K050 A500K130
Function
Function
Function
Function
Function
Function
L3
L4
I/O
VDDL
GND
GND
GND
GND
VDDL
I/O
I/O
VDDL
GND
GND
GND
GND
VDDL
I/O
T1
T2
I/O
I/O
I/O
I/O
V19
V20
W1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
VPP
TRST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
VPN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
VPP
TRST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
VPN
I/O
L9
T3
I/O
I/O
L10
L11
L12
L17
L18
L19
L20
M1
T4
VDDP
VDDP
I/O
VDDP
VDDP
I/O
W2
T17
T18
T19
T20
U1
W3
W4
I/O
I/O
W5
I/O
I/O
W6
I/O
I/O
I/O
I/O
W7
I/O
I/O
U2
I/O
I/O
W8
I/O
I/O
U3
I/O
I/O
W9
M2
I/O
I/O
U4
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
I/O
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y1
M3
I/O
I/O
U5
M4
VDDL
GND
GND
GND
GND
VDDL
I/O
VDDL
GND
GND
GND
GND
VDDL
I/O
U6
M9
U7
M10
M11
M12
M17
M18
M19
M20
N1
U8
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
I/O
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
I/O
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V1
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
VDDP
RCK
I/O
VDDP
VDDP
VDDP
RCK
I/O
N2
I/O
I/O
Y2
N3
I/O
I/O
Y3
N4
VDDL
VDDL
I/O
VDDL
VDDL
I/O
Y4
N17
N18
N19
N20
P1
Y5
I/O
I/O
Y6
I/O
I/O
I/O
I/O
Y7
I/O
I/O
V2
I/O
I/O
Y8
I/O
I/O
V3
I/O
I/O
Y9
P2
I/O
I/O
V4
I/O
I/O
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
P3
I/O
I/O
V5
I/O
I/O
P4
VDDP
VDDP
I/O
VDDP
VDDP
I/O
V6
I/O
I/O
P17
P18
P19
P20
R1
V7
I/O
I/O
V8
I/O
I/O
I/O
I/O
V9
I/O
I/O
I/O
I/O
V10
V11
V12
V13
V14
V15
V16
V17
V18
I/O
I/O
I/O
I/O
I/O
I/O
R2
I/O
I/O
I/O
I/O
R3
I/O
I/O
I/O
I/O
R4
VDDP
VDDP
I/O
VDDP
VDDP
I/O
I/O
I/O
R17
R18
R19
R20
I/O
I/O
I/O
I/O
I/O
I/O
TMS
TDO
TMS
TDO
I/O
I/O
48
v3.0
ProASIC™ 500K Family
Package Pin Assignments (Continued)
456-Pin PBGA (Bottom View)
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
v3.0
49
ProASIC™ 500K Family
456-Pin PBGA
A500K130
Function
A500K180
Function
A500K270
Function
A500K130
Function
A500K180
Function
A500K270
Function
Pin Number
Pin Number
A1
A2
VDDP
VDDP
NC
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AC1
I/O
I/O
I/O
I/O
I/O
I/O
A3
I/O
I/O
I/O
A4
I/O
I/O
I/O
I/O
I/O
A5
I/O
I/O
I/O
I/O
I/O
I/O
A6
NC
I/O
I/O
I/O
I/O
I/O
I/O
A7
I/O
I/O
I/O
I/O
I/O
A8
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
A9
I/O
I/O
I/O
I/O
I/O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
AA1
AA2
AA3
AA4
AA5
AA22
AA23
AA24
AA25
AA26
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
I/O
I/O
VDDL
VDDL
VDDL
I/O
VDDL
VDDL
VDDL
I/O
VDDL
VDDL
VDDL
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AC2
I/O
I/O
I/O
I/O
I/O
AC3
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
AC4
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
AC5
I/O
I/O
AC6
I/O
I/O
I/O
NC
NC
VDDP
VDDP
I/O
I/O
I/O
AC7
I/O
I/O
I/O
I/O
I/O
AC8
I/O
I/O
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
AC9
I/O
I/O
I/O
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
VDDL
I/O
VDDL
VDDL
I/O
VDDL
VDDL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
TDO
VDDP
RCK
I/O
TMS
TDO
VDDP
RCK
I/O
TMS
TDO
VDDP
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
VDDL
VDDL
I/O
VDDL
VDDL
VDDL
I/O
VDDL
VDDL
VDDL
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
AD2
I/O
I/O
I/O
I/O
I/O
AD3
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
AD4
50
v3.0
ProASIC™ 500K Family
456-Pin PBGA (Continued)
A500K130
Function
A500K180
Function
A500K270
Function
A500K130
Function
A500K180
Function
A500K270
Function
Pin Number
Pin Number
AD5
AD6
I/O
I/O
I/O
I/O
I/O
I/O
AE25
AE26
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
B1
VDDP
VDDP
VDDP
VDDP
NC
NC
I/O
VDDP
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
VDDP
I/O
AD7
I/O
I/O
I/O
AD8
I/O
I/O
I/O
AD9
I/O
I/O
I/O
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
VPP
I/O
TCK
VPP
I/O
TCK
VPP
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
NC
VDDP
VDDP
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
NC
I/O
I/O
I/O
AE2
I/O
I/O
AE3
TDI
NC
VDDP
VDDP
VDDP
VDDP
I/O
TDI
I/O
TDI
I/O
AE4
I/O
I/O
I/O
AE5
I/O
I/O
I/O
VDDP
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
VDDP
I/O
AE6
I/O
I/O
I/O
AE7
I/O
I/O
I/O
AE8
I/O
I/O
I/O
B2
AE9
I/O
I/O
I/O
B3
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
I/O
I/O
I/O
B4
I/O
I/O
I/O
I/O
I/O
I/O
B5
I/O
I/O
I/O
I/O
I/O
I/O
B6
I/O
I/O
I/O
I/O
I/O
I/O
B7
I/O
I/O
I/O
I/O
I/O
I/O
B8
I/O
I/O
I/O
I/O
I/O
I/O
B9
I/O
I/O
I/O
I/O
I/O
I/O
B10
B11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B12
B13
B14
B15
B16
B17
B18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VPN
TRST
VPN
TRST
VPN
TRST
I/O
I/O
I/O
I/O
I/O
I/O
v3.0
51
ProASIC™ 500K Family
456-Pin PBGA (Continued)
A500K130
Function
A500K180
Function
A500K270
Function
A500K130
Function
A500K180
Function
A500K270
Function
Pin Number
Pin Number
B19
B20
B21
B22
B23
B24
B25
B26
C1
I/O
I/O
I/O
I/O
I/O
I/O
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
C2
I/O
I/O
I/O
C3
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
C4
C5
I/O
I/O
I/O
I/O
I/O
I/O
C6
I/O
I/O
I/O
I/O
I/O
I/O
C7
I/O
I/O
I/O
NC
I/O
I/O
I/O
C8
I/O
I/O
I/O
E2
I/O
I/O
C9
I/O
I/O
I/O
E3
I/O
I/O
I/O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
I/O
I/O
I/O
E4
I/O
I/O
I/O
I/O
I/O
I/O
E5
VDDL
VDDL
VDDL
VDDL
I/O
VDDL
VDDL
VDDL
VDDL
I/O
VDDL
VDDL
VDDL
VDDL
I/O
I/O
I/O
I/O
E6
I/O
I/O
I/O
E7
I/O
I/O
I/O
E8
I/O
I/O
I/O
E9
I/O
I/O
I/O
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
VDDL
VDDL
VDDL
I/O
VDDL
VDDL
VDDL
I/O
VDDL
VDDL
VDDL
I/O
I/O
I/O
D2
I/O
I/O
D3
I/O
I/O
I/O
D4
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
D5
I/O
I/O
I/O
D6
I/O
I/O
I/O
I/O
I/O
I/O
D7
I/O
I/O
I/O
I/O
I/O
I/O
D8
I/O
I/O
I/O
F2
I/O
I/O
I/O
D9
I/O
I/O
I/O
F3
I/O
I/O
I/O
D10
D11
D12
I/O
I/O
I/O
F4
I/O
I/O
I/O
I/O
I/O
I/O
F5
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
I/O
I/O
I/O
F22
52
v3.0
ProASIC™ 500K Family
456-Pin PBGA (Continued)
A500K130
Function
A500K180
Function
A500K270
Function
A500K130
Function
A500K180
Function
A500K270
Function
Pin Number
Pin Number
F23
F24
F25
F26
G1
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
VDDL
VDDL
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
VDDL
VDDL
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
VDDL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
VDDL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
VDDL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
VDDL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L3
L4
I/O
I/O
I/O
I/O
I/O
I/O
L5
I/O
I/O
I/O
L11
L12
L13
L14
L15
L16
L22
L23
L24
L25
L26
M1
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
G2
G3
G4
G5
G22
G23
G24
G25
G26
H1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
GL
GL
GL
H2
M2
GL
GL
GL
H3
M3
I/O
I/O
I/O
H4
M4
I/O
I/O
I/O
H5
M5
I/O
I/O
I/O
H22
H23
H24
H25
H26
J1
M11
M12
M13
M14
M15
M16
M22
M23
M24
M25
M26
N1
GND
GND
GND
GND
GND
GND
GL
GND
GND
GND
GND
GND
GND
GL
GND
GND
GND
GND
GND
GND
GL
J2
J3
I/O
I/O
I/O
J4
I/O
I/O
I/O
J5
I/O
I/O
I/O
J22
J23
J24
J25
J26
K1
NC
I/O
I/O
NC
I/O
I/O
N2
I/O
I/O
I/O
N3
I/O
I/O
I/O
N4
I/O
I/O
I/O
N5
I/O
I/O
I/O
K2
N11
N12
N13
N14
N15
N16
N22
N23
N24
N25
N26
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
K3
K4
K5
K22
K23
K24
K25
K26
L1
GL
GL
GL
I/O
I/O
I/O
I/O
I/O
I/O
L2
I/O
I/O
I/O
v3.0
53
ProASIC™ 500K Family
456-Pin PBGA (Continued)
A500K130
Function
A500K180
Function
A500K270
Function
A500K130
Function
A500K180
Function
A500K270
Function
Pin Number
Pin Number
P1
P2
NC
I/O
I/O
I/O
I/O
I/O
T23
T24
T25
T26
U1
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
VDDL
VDDL
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
VDDL
VDDL
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
VDDL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
VDDL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
VDDL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
VDDL
I/O
I/O
I/O
I/O
P3
I/O
I/O
I/O
P4
I/O
I/O
I/O
P5
I/O
I/O
I/O
P11
P12
P13
P14
P15
P16
P22
P23
P24
P25
P26
R1
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
U2
U3
U4
U5
U22
U23
U24
U25
U26
V1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
V2
I/O
I/O
I/O
V3
R2
I/O
I/O
I/O
V4
R3
I/O
I/O
I/O
V5
R4
I/O
I/O
I/O
V22
V23
V24
V25
V26
W1
W2
W3
W4
W5
W22
W23
W24
W25
W26
Y1
R5
I/O
I/O
I/O
R11
R12
R13
R14
R15
R16
R22
R23
R24
R25
R26
T1
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
T2
I/O
I/O
I/O
T3
I/O
I/O
I/O
T4
I/O
I/O
I/O
Y2
T5
I/O
I/O
I/O
Y3
T11
T12
T13
T14
T15
T16
T22
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
Y4
Y5
Y22
Y23
Y24
Y25
Y26
54
v3.0
ProASIC™ 500K Family
Package Assignments (Continued)
144-FBGA (Bottom View)
2
12 11 10
9
8
7
6
5
4
3
1
A
B
C
D
E
F
G
H
J
K
L
M
v3.0
55
ProASIC™ 500K Family
144-pin FBGA
Pin
Number
A500K050
Function
A500K130
Function
Pin
Number
A500K050
Function
A500K130
Function
Pin
Number
A500K050
Function
A500K130
Function
A1
A2
I/O
I/O
I/O
I/O
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
I/O
I/O
I/O
I/O
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
I/O
GND
I/O
I/O
GND
I/O
A3
I/O
I/O
I/O
I/O
A4
I/O
I/O
I/O
I/O
I/O
I/O
A5
I/O
I/O
I/O
I/O
GND
GND
GND
I/O
GND
GND
GND
I/O
A6
GND
I/O
GND
I/O
I/O
I/O
A7
I/O
I/O
A8
VDDL
I/O
VDDL
I/O
I/O
I/O
A9
I/O
I/O
I/O
I/O
A10
A11
A12
B1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
I/O
VDDL
I/O
VDDL
I/O
VDDL
I/O
B2
GND
I/O
GND
I/O
E2
B3
E3
I/O
I/O
I/O
I/O
B4
I/O
I/O
E4
VDDP
I/O
VDDP
I/O
I/O
I/O
B5
I/O
I/O
E5
VDDL
I/O
VDDL
I/O
B6
I/O
I/O
E6
VDDP
VDDP
I/O
VDDP
VDDP
I/O
B7
I/O
I/O
E7
I/O
I/O
B8
I/O
I/O
E8
I/O
I/O
B9
I/O
I/O
E9
VDDP
VDDL
I/O
VDDP
VDDL
I/O
I/O
I/O
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
I/O
I/O
E10
E11
E12
F1
VDDP
I/O
VDDP
I/O
GND
I/O
GND
I/O
I/O
I/O
VDDL
I/O
VDDL
I/O
I/O
I/O
GL
GL
GL
GL
I/O
F2
I/O
I/O
J2
I/O
I/O
I/O
F3
I/O
I/O
J3
VDDP
I/O
VDDP
I/O
VDDL
I/O
VDDL
I/O
F4
I/O
I/O
J4
F5
GND
GND
GND
I/O
GND
GND
GND
I/O
J5
I/O
I/O
I/O
I/O
F6
J6
I/O
I/O
I/O
I/O
F7
J7
VDDL
TCK
I/O
VDDL
TCK
I/O
I/O
I/O
F8
J8
I/O
I/O
F9
GL
GL
J9
I/O
I/O
F10
F11
F12
GND
I/O
GND
I/O
J10
J11
J12
TDO
I/O
TDO
I/O
I/O
I/O
I/O
I/O
GL
GL
I/O
I/O
56
v3.0
ProASIC™ 500K Family
144-pin FBGA (Continued)
Pin
Number
A500K050
Function
A500K130
Function
Pin
Number
A500K050
Function
A500K130
Function
Pin
Number
A500K050
Function
A500K130
Function
K1
K2
I/O
I/O
I/O
I/O
L1
L2
GND
I/O
GND
I/O
M1
M2
I/O
I/O
I/O
I/O
K3
I/O
I/O
L3
I/O
I/O
M3
I/O
I/O
K4
I/O
I/O
L4
I/O
I/O
M4
I/O
I/O
K5
I/O
I/O
L5
VDDP
I/O
VDDP
I/O
M5
I/O
I/O
K6
I/O
I/O
L6
M6
I/O
I/O
K7
GND
I/O
GND
I/O
L7
I/O
I/O
M7
I/O
I/O
K8
L8
I/O
I/O
M8
I/O
I/O
K9
I/O
I/O
L9
TMS
RCK
I/O
TMS
RCK
I/O
M9
TDI
VDDP
VPP
VPN
TDI
VDDP
VPP
VPN
K10
K11
K12
GND
I/O
GND
I/O
L10
L11
L12
M10
M11
M12
I/O
I/O
TRST
TRST
v3.0
57
ProASIC™ 500K Family
Package Assignments (Continued)
256-FBGA (Bottom View)
Pin one corner
1
7
6
4
5
3
2
16 15 14 13 12 11 10 9
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
58
v3.0
ProASIC™ 500K Family
256-pin FBGA
Pin
Number
A500K130
Function
A500K180
Function
A500K270
Function
Pin
Number
A500K130
Function
A500K180
Function
A500K270
Function
A1
A2
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
C8
C9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
I/O
VDDP
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
I/O
VDDP
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
I/O
VDDP
VDDP
I/O
I/O
I/O
A3
C10
C11
C12
C13
C14
C15
C16
D1
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
B1
D2
D3
D4
D5
D6
D7
D8
B2
D9
B3
D10
D11
D12
D13
D14
D15
D16
E1
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
C1
E2
E3
E4
E5
E6
E7
E8
C2
E9
C3
E10
E11
E12
E13
E14
C4
C5
C6
C7
v3.0
59
ProASIC™ 500K Family
256-pin FBGA (Continued)
Pin
Number
A500K130
Function
A500K180
Function
A500K270
Function
Pin
Number
A500K130
Function
A500K180
Function
A500K270
Function
E15
E16
F1
I/O
I/O
I/O
I/O
I/O
I/O
H6
H7
VDDL
GND
GND
GND
GND
VDDL
I/O
VDDL
GND
GND
GND
GND
VDDL
I/O
VDDL
GND
GND
GND
GND
VDDL
I/O
I/O
I/O
I/O
H8
F2
I/O
I/O
I/O
H9
F3
I/O
I/O
I/O
H10
H11
H12
H13
H14
H15
H16
J1
F4
I/O
I/O
I/O
F5
VDDP
GND
VDDL
VDDL
VDDL
VDDL
GND
VDDP
I/O
VDDP
GND
VDDL
VDDL
VDDL
VDDL
GND
VDDP
I/O
VDDP
GND
VDDL
VDDL
VDDL
VDDL
GND
VDDP
I/O
F6
I/O
I/O
I/O
F7
I/O
I/O
I/O
F8
I/O
I/O
I/O
F9
GL
GL
GL
F10
F11
F12
F13
F14
F15
F16
G1
GL
GL
GL
J2
I/O
I/O
I/O
J3
I/O
I/O
I/O
J4
I/O
I/O
I/O
I/O
I/O
I/O
J5
I/O
I/O
I/O
I/O
I/O
I/O
J6
VDDL
GND
GND
GND
GND
VDDL
I/O
VDDL
GND
GND
GND
GND
VDDL
I/O
VDDL
GND
GND
GND
GND
VDDL
I/O
I/O
I/O
I/O
J7
I/O
I/O
I/O
J8
G2
I/O
I/O
I/O
J9
G3
I/O
I/O
I/O
J10
J11
J12
J13
J14
J15
J16
K1
G4
I/O
I/O
I/O
G5
VDDP
VDDL
GND
GND
GND
GND
VDDL
VDDP
I/O
VDDP
VDDL
GND
GND
GND
GND
VDDL
VDDP
I/O
VDDP
VDDL
GND
GND
GND
GND
VDDL
VDDP
I/O
G6
I/O
I/O
I/O
G7
I/O
I/O
I/O
G8
I/O
I/O
I/O
G9
GL
GL
GL
G10
G11
G12
G13
G14
G15
G16
H1
I/O
I/O
I/O
K2
I/O
I/O
I/O
K3
I/O
I/O
I/O
K4
I/O
I/O
I/O
I/O
I/O
I/O
K5
VDDP
VDDL
GND
GND
GND
GND
VDDL
VDDP
VDDP
VDDL
GND
GND
GND
GND
VDDL
VDDP
VDDP
VDDL
GND
GND
GND
GND
VDDL
VDDP
I/O
I/O
I/O
K6
I/O
I/O
I/O
K7
GL
GL
GL
K8
H2
I/O
I/O
I/O
K9
H3
I/O
I/O
I/O
K10
K11
K12
H4
I/O
I/O
I/O
H5
I/O
I/O
I/O
60
v3.0
ProASIC™ 500K Family
256-pin FBGA (Continued)
Pin
Number
A500K130
Function
A500K180
Function
A500K270
Function
Pin
Number
A500K130
Function
A500K180
Function
A500K270
Function
K13
K14
K15
K16
L1
I/O
I/O
I/O
I/O
I/O
I/O
N4
N5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
VPP
TRST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
VPP
TRST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
VPP
TRST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N6
I/O
I/O
I/O
N7
I/O
I/O
I/O
N8
L2
I/O
I/O
I/O
N9
L3
I/O
I/O
I/O
N10
N11
N12
N13
N14
N15
N16
P1
L4
I/O
I/O
I/O
L5
VDDP
GND
VDDL
VDDL
VDDL
VDDL
GND
VDDP
I/O
VDDP
GND
VDDL
VDDL
VDDL
VDDL
GND
VDDP
I/O
VDDP
GND
VDDL
VDDL
VDDL
VDDL
GND
VDDP
I/O
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
P2
P3
P4
I/O
I/O
I/O
P5
I/O
I/O
I/O
P6
I/O
I/O
I/O
P7
I/O
I/O
I/O
P8
I/O
I/O
I/O
P9
I/O
I/O
I/O
P10
P11
P12
P13
P14
P15
P16
R1
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
R2
R3
I/O
I/O
I/O
R4
I/O
I/O
I/O
R5
I/O
I/O
I/O
R6
I/O
I/O
I/O
R7
I/O
I/O
I/O
R8
N2
I/O
I/O
I/O
R9
N3
I/O
I/O
I/O
R10
v3.0
61
ProASIC™ 500K Family
256-pin FBGA (Continued)
Pin
Number
A500K130
Function
A500K180
Function
A500K270
Function
Pin
Number
A500K130
Function
A500K180
Function
A500K270
Function
R11
R12
R13
R14
R15
R16
T1
I/O
I/O
I/O
I/O
I/O
I/O
T6
T7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
T8
I/O
I/O
I/O
TDI
VPN
TDO
GND
I/O
TDI
VPN
TDO
GND
I/O
TDI
VPN
TDO
GND
I/O
T9
I/O
I/O
I/O
T10
T11
T12
T13
T14
T15
T16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
T2
I/O
I/O
I/O
T3
I/O
I/O
I/O
I/O
I/O
I/O
T4
I/O
I/O
I/O
TMS
GND
TMS
GND
TMS
GND
T5
I/O
I/O
I/O
62
v3.0
ProASIC™ 500K Family
Package Assignments (Continued)
676-pin FBGA (Bottom View)
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
v3.0
63
ProASIC™ 500K Family
676-Pin FBGA
Pin
Number
A500K270
Function
Pin
A500K270
Pin
A500K270
Pin
Number
A500K270
Function
Pin
Number
A500K270
Function
Number Function
Number Function
A1
A2
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AB1
I/O
I/O
AB25
AB26
AC1
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
VPN
I/O
I/O
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AE23
AE24
AE25
AE26
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
B1
I/O
I/O
A3
I/O
GND
GND
GND
GND
GND
GND
I/O
A4
I/O
AC2
A5
I/O
AC3
A6
I/O
AC4
A7
I/O
AC5
A8
I/O
AC6
A9
TDO
GND
GND
I/O
AC7
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AC8
I/O
AC9
I/O
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AB2
I/O
I/O
AB3
I/O
I/O
AB4
I/O
AE2
I/O
AB5
I/O
AE3
I/O
AB6
GND
GND
I/O
AE4
I/O
AB7
AE5
I/O
AB8
AE6
I/O
AB9
I/O
AE7
I/O
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
I/O
AE8
I/O
I/O
AE9
I/O
I/O
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
GND
GND
I/O
I/O
AD2
I/O
AD3
I/O
AD4
B2
I/O
AD5
B3
I/O
AD6
B4
TCK
TRST
I/O
AD7
B5
AD8
B6
I/O
AD9
B7
I/O
I/O
AD10
B8
I/O
64
v3.0
ProASIC™ 500K Family
676-Pin FBGA (Continued)
Pin
Number
A500K270
Function
Pin
A500K270
Pin
A500K270
Pin
Number
A500K270
Function
Pin
Number
A500K270
Function
Number Function
Number Function
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
I/O
I/O
C21
C22
C23
C24
C25
C26
D1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
E7
E8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
F19
F20
F21
F22
F23
F24
F25
F26
G1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDL
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
H5
H6
I/O
I/O
I/O
E9
H7
VDDP
VDDL
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDL
VDDL
I/O
I/O
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
H8
I/O
H9
I/O
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
J1
I/O
I/O
D2
I/O
D3
I/O
D4
G2
I/O
D5
G3
I/O
D6
G4
I/O
D7
G5
I/O
D8
G6
I/O
D9
G7
I/O
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
G8
GND
GND
GND
GND
GND
GND
I/O
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G20
G19
G21
G22
G23
G24
G25
G26
H1
I/O
I/O
C2
I/O
C3
I/O
C4
F2
I/O
C5
F3
I/O
C6
I/O
F4
J2
I/O
C7
I/O
F5
J3
I/O
C8
I/O
F6
J4
I/O
C9
I/O
F7
J5
I/O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
I/O
F8
J6
I/O
I/O
F9
J7
NC
I/O
F10
F11
F12
F13
F14
F15
F16
F17
F18
J8
VDDP
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
I/O
J9
I/O
J10
J11
J12
J13
J14
J15
J16
I/O
I/O
E2
I/O
E3
I/O
E4
H2
I/O
E5
H3
I/O
E6
H4
v3.0
65
ProASIC™ 500K Family
676-Pin FBGA (Continued)
Pin
Number
A500K270
Function
Pin
A500K270
Pin
A500K270
Pin
Number
A500K270
Function
Pin
Number
A500K270
Function
Number Function
Number Function
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
K1
VDDL
VDDL
VDDP
NC
L3
L4
I/O
I/O
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
N1
GND
GND
GND
VDDL
VDDP
NC
P1
P2
GL
I/O
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
T1
GND
GND
GND
GND
GND
VDDL
VDDP
NC
L5
I/O
P3
I/O
L6
I/O
P4
I/O
I/O
L7
NC
P5
I/O
I/O
L8
VDDP
VDDL
GND
GND
GND
GND
GND
GND
GND
GND
VDDL
VDDP
NC
P6
I/O
I/O
L9
I/O
P7
NC
I/O
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
M1
I/O
P8
VDDP
VDDL
GND
GND
GND
GND
GND
GND
GND
GND
VDDL
VDDP
NC
I/O
I/O
P9
I/O
I/O
I/O
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
R1
I/O
I/O
I/O
I/O
K2
I/O
I/O
I/O
K3
I/O
GL
I/O
K4
I/O
N2
I/O
I/O
K5
I/O
N3
I/O
I/O
K6
I/O
N4
I/O
T2
I/O
K7
NC
N5
I/O
T3
I/O
K8
VDDP
VDDL
GND
GND
GND
GND
GND
GND
GND
GND
VDDL
VDDP
NC
N6
I/O
T4
I/O
K9
I/O
N7
NC
T5
I/O
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
L1
I/O
N8
VDDP
VDDL
GND
GND
GND
GND
GND
GND
GND
GND
VDDL
VDDP
NC
T6
I/O
I/O
N9
I/O
T7
NC
I/O
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
I/O
T8
VDDP
VDDL
GND
GND
GND
GND
GND
GND
GND
GND
VDDL
VDDP
NC
I/O
I/O
T9
I/O
I/O
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
I/O
I/O
M2
I/O
I/O
M3
I/O
I/O
M4
I/O
R2
I/O
M5
I/O
R3
I/O
M6
I/O
R4
I/O
I/O
M7
NC
R5
I/O
I/O
M8
VDDP
VDDL
GND
GND
GND
GND
GND
R6
I/O
I/O
M9
I/O
R7
NC
I/O
M10
M11
M12
M13
M14
GL
R8
VDDP
VDDL
GND
GND
GND
I/O
I/O
R9
I/O
I/O
I/O
R10
R11
R12
I/O
I/O
GL
I/O
L2
I/O
I/O
I/O
66
v3.0
ProASIC™ 500K Family
676-Pin FBGA (Continued)
Pin
Number
A500K270
Function
Pin
A500K270
Pin
A500K270
Pin
Number
A500K270
Function
Pin
Number
A500K270
Function
Number Function
Number Function
T25
T26
U1
I/O
I/O
U20
U21
U22
U23
U24
U25
U26
V1
NC
I/O
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
W1
W2
W3
W4
W5
W6
W7
W8
W9
VDDL
VDDL
VDDL
VDDL
VDDP
NC
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
Y1
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDL
VDDP
I/O
Y5
I/O
I/O
Y6
I/O
I/O
Y7
I/O
U2
I/O
I/O
Y8
VDDP
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDDL
VPP
I/O
U3
I/O
I/O
Y9
U4
I/O
I/O
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
U5
I/O
I/O
I/O
U6
I/O
I/O
I/O
U7
NC
V2
I/O
I/O
U8
VDDP
VDDL
GND
GND
GND
GND
GND
GND
GND
GND
VDDL
VDDP
V3
I/O
I/O
U9
V4
I/O
I/O
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
V5
I/O
I/O
V6
I/O
I/O
I/O
V7
NC
I/O
I/O
V8
VDDP
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
I/O
I/O
V9
I/O
I/O
V10
V11
V12
V13
V14
I/O
I/O
I/O
I/O
I/O
VDDL
VDDL
VDDP
Y2
I/O
I/O
Y3
I/O
I/O
Y4
I/O
I/O
I/O
v3.0
67
ProASIC™ 500K Family
List of Changes
The following table lists critical changes that were made in
the current version of the document.
Previous version Changes in current version (v3.0)
Page
WDATA has been changed to DI, and RDATA has been changed to DO to make
them consistent with the signal names found in the Macro Library Guide.
v2.0
The “Product Plan” on page 3 has been updated to include the 256-FBGA package. page 3
The “Plastic Device Resources” on page 3 has been updated to include the
256-FBGA package.
page 3
Figure 12 and Figure 13 on page 13 have been updated.
page 13
page 15
The “Design Environment” on page 15 and Figure 17 on page 15 have been
updated.
Package Thermal Characteristics table on page 16 has been updated to include the
256-FBGA package.
page 16
Preliminary v1.1
The “Calculating Power Dissipation” on page 17 has been changed.
The “Programming and Storage Temperature LImits” on page 18 is new.
The “DC Electrical Specifications (VDDP = 2.5V)” on page 19 has been updated.
The “DC Electrical Specifications (VDDP = 3.3V)” on page 20 has been updated.
The Table 4 on page 28 has been updated.
page 17
page 18
page 19
page 20
page 28
page 34
page 58
The Table 5 on page 34 has been updated.
The “256-FBGA (Bottom View)” on page 58 is new.
In the “676-pin FBGA (Bottom View)” on page 63, the functions for pins N1, N22,
N25, and P1 have changed from I/O to GL
Preliminary v1.0
page 59
The section, “Clock Trees” on page 8 is new.
page 8
The table, “DC Electrical Specifications (VDDP = 3.3V)” on page 20 is new.
The table, “AC Specifications (3.3V PCI Operation)” on page 22 is new.
page 18
page 20
The table, the “Slew Rates Measured at Cout = 10pF (Total Output Load), Nominal
Power Supplies and 25°C” on page 24 is new.
page 22
The numbers found in the “Tristate Buffer Delays (Worst-Case Commercial
Conditions, VDDP = 3.0V, VDDL = 2.3V, TJ = 70°C, fCLOCK = 250 MHz)” on page 25 page 23
have changed.
The numbers found in the “Output Buffer Delays (Worst-Case Commercial
Conditions, VDDP = 3.0V, VDDL = 2.3V, TJ = 70°C, fCLOCK = 250 MHz)” on page 26 page 24
have changed.
Advanced v.4
The numbers found in the “Input Buffer Delays (Worst-Case Commercial Conditions,
VDDP = 3.0V, VDDL = 2.3V, TJ = 70°C, fCLOCK = 250 MHz)” on page 26 have
page 24
changed.
The numbers found in the “Global Input Buffer Delays (Worst-Case Commercial
Conditions, VDDP = 3.0V, VDDL = 2.3V, TJ = 70°C, fCLOCK = 250 MHz)” on page 27 page 25
have changed.
The “144-FBGA (Bottom View)” on page 55 for A500K050 is new.
pages 53-55
pages 56-60
The “676-pin FBGA (Bottom View)” on page 63 for A500K130 and A500K270 are
new.
68
v3.0
ProASIC™ 500K Family
Data Sheet Categories
In order to provide the latest information to designers, some data sheets are published before data has been fully
characterized. These data sheets are marked as “Advanced” or Preliminary” data sheets. The definition of these categories
are as follows:
Advanced
The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This
information can be used as estimates, but not for production.
Preliminary
The data sheet contains information based on simulation and/or initial characterization. The information is believed to be
correct, but changes are possible.
Unmarked (production)
The data sheet contains information that is considered to be final.
Web-only Versions
Web-only versions have three numbers in the version number (example: v2.0.1). A web-only version means Actel is posting
the data sheet so customers have the latest information, but we are not printing the version because some information is
going to change shortly after posting.
v3.0
69
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5172140-7/2.02
相关型号:
A500K130-FG144I
Field Programmable Gate Array, 105000 Gates, 250MHz, 12800-Cell, CMOS, PBGA144, FBGA-144
ACTEL
A500K130-FG256I
Field Programmable Gate Array, 105000 Gates, 250MHz, 12800-Cell, CMOS, PBGA256, FBGA-256
ACTEL
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