A3P1000-FGG484YM_技术文档

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

with Flash*Freeze Technology

•

Architecture Supports Ultra-High Utilization

Features and Benefits

Advanced and Pro (Professional) I/Os^††

Military Temperature Tested and Qualified

•

700 Mbps DDR, LVDS-Capable I/Os

1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages—up to 8 Banks per Chip

†

•

Each Device Tested from –55°C to 125°C

Firm-Error Immune

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

•

Not Susceptible to Neutron-Induced Configuration Loss

†

Low Power

LVCMOS 2.5 V / 5.0 V Input

•

Dramatic Reduction in Dynamic and Static Power

1.2 V to 1.5 V Core and I/O Voltage Support for Low Power

•

Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS

Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II (A3PE3000L only)

†

Low Power Consumption in Flash*Freeze Mode Allows for

Instantaneous Entry To / Exit From Low-Power Flash*Freeze

ƒ

Mode

•

I/O Registers on Input, Output, and Enable Paths

Hot-Swappable and Cold-Sparing I/Os

Programmable Output Slew Rate and Drive Strength

Programmable Input Delay (A3PE3000L only)

Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)

Weak Pull-Up/-Down

•

Supports Single-Voltage System Operation

Low-Impedance Switches

High Capacity

•

250K to 3M System Gates

Up to 504 Kbits of True Dual-Port SRAM

Up to 620 User I/Os

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages across the Military ProASIC 3EL Family

®

Reprogrammable Flash Technology

Clock Conditioning Circuit (CCC) and PLL

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

Live-at-Power-Up (LAPU) Level 0 Support

Single-Chip Solution

•

Six CCC Blocks—One Block with Integrated PLL in ProASIC3

and All Blocks with Integrated PLL in ProASIC3EL

Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

and External Feedback

Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V

systems) and 350 MHz (1.5 V systems)

Retains Programmed Design when Powered Off

High Performance

•

350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System

Performance

3.3 V, 66 MHz, 64-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit

PCI (1.2 V systems)

SRAMs and FIFOs

•

Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

True Dual-Port SRAM (except ×18)

24 SRAM and FIFO Configurations with Synchronous

Operation:

– 250 MHz: For 1.2 V Systems

– 350 MHz: For 1.5 V Systems

In-System Programming (ISP) and Security

•

Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

®

•

FlashLock to Secure FPGA Contents

High-Performance Routing Hierarchy

ARM^®Processor Support in ProASIC3/EL FPGAs

•

Segmented, Hierarchical Routing and Clock Structure

High-Performance, Low-Skew Global Network

ARM Cortex™-M1 Soft Processor Available with or without

Debug

Table 1 • Military ProASIC3/EL Low-Power Devices

ProASIC3/EL Devices

ARM Cortex-M1 Devices

System Gates

A3P250

A3PE600L

A3P1000

A3PE3000L

1

M1A3P1000

M1A3PE3000L

250,000

600,000

13,824

108

24

1M

24,576

144

32

3M

75,264

504

112

1

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

6,144

36

8

FlashROM Kbits

1

2

Secure (AES) ISP

Yes

1

Yes

6

Yes

1

Yes

6

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

18

4

18

8

4

8

Maximum User I/Os

68

270

154

620

Package Pins

VQFP

VQ100

PQFP

PQ208

FG144, FG256, FG484

FBGA

FG484

FG484, FG896

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. AES is not available for ARM-enabled ProASIC3/EL devices.

† A3P250 and A3P1000 support only 1.5 V core operation.

ƒ Flash*Freeze technology is not available for A3P250 or A3P1000.

††Pro I/Os are not available on A3P250 or A3P1000.

September 2014

I

Military ProASIC3/EL Low Power Flash FPGAs

1

I/Os Per Package

ProASIC3/EL

Low Power Devices

A3P250

A3PE600L

A3P1000

A3PE3000L

ARM

Cortex-M1 Devices

M1A3P1000

M1A3PE3000L

Single-

Differential

Single-

Differential

I/O Pairs

Single-

Differential

Single- Differential

Ended I/O²I/O Pairs Ended I/O²

Ended I/O²

I/O Pairs Ended I/O²I/O Pairs

Package

VQ100

PQ208

FG144

FG256

FG484

FG896

Notes:

68

–

13

–

154

97

35

25

44

74

–

177

300

–

270

–

135

–

341

620

168

310

–

1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to

ensure you are complying with design and board migration requirements.

2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

3. "G" indicates RoHS-compliant packages. Refer to "Military ProASIC3/EL Ordering Information" on page III for the location of the

"G" in the part number.

4. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:

– SSTL3(I) and (II): up to 40 I/Os per north or south bank

– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank

– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank

5. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended

user I/Os available is reduced by one.

Military ProASIC3/EL Device Status

Military ProASIC3/EL Devices

Status

M1 Military ProASIC3/EL Devices

Status

A3P250

Production

A3PE600L

A3P1000

M1A3P1000

Production

A3PE3000L

M1A3PE3000L

II

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

Military ProASIC3/EL Ordering Information

_

A3P1000

1

FG

G

144

Y

M

Application (Temperature Range)

M = Military ( 55°C to 125°C Junction Temperature)

–

Security Feature

Y = Device Includes License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio

Package Lead Count

Lead-Free Packaging

Blank = Standard Packaging

G = RoHS-Compliant (Green) Packaging

Package Type

=

VQ Very Thin Quad Flat Pack (0.5 mm pitch)

=

FG

Fine Pitch Ball Grid Array (1.0 mm pitch)

=

PQ Plastic Quad Flat Pack (0.5 mm pitch)

Speed Grade

Blank = Standard

1 = 15% Faster than Standard

2 = 25% Faster than Standard

Note: Speed Grade –2 is available only for A3P1000 device in FG256 and FG484 packages

Part Number

Military ProASIC3/EL Devices

A3P250 = 250,000 System Gates

A3PE600L= 600,000 System Gates

A3P1000 1,000,000 System Gates

=

A3PE3000L= 3,000,000 System Gates

Military ProASIC3/EL Devices with ARM Cortex-M1

M1A3P1000 = 1,000,000 System Gates

M1A3PE3000L = 3,000,000 System Gates

Temperature Grade Offerings

Package

ARM Cortex-M1 Devices

VQ100

A3P250

A3PE600L

A3P1000

A3PE3000L

M1A3P1000

M1A3PE3000L

M

–

M

–

PQ208

FG144

–

FG256

–

FG484

M

–

M

FG896

Note: M = Military temperature range: –55°C to 125°C junction temperature

Revision 5

III

Temperature Grade Offerings

Speed Grade and Temperature Grade Matrix

Temperature Grade

Std.

–1

–2¹

M



Notes:

1. M1 devices are not available in -2 speed grade

2. M = Military temperature range: –55°C to 125°C junction temperature

Contact your local Microsemi SoC Products Group (formerly Actel) representative for device availability:

http://www.microsemi.com/contact/default.aspx.

IV

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

Table of Contents

Military ProASIC3/EL Device Family Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Military ProASIC3/EL DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-108

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-117

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-123

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-144

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-145

Pin Descriptions and Packaging

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Package Pin Assignments

VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

FG896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Revision 5

V

1 – Military ProASIC3/EL Device Family Overview

General Description

The military ProASIC3/EL family of flash FPGAs dramatically reduces dynamic power consumption by

40% and static power by 50%. These power savings are coupled with performance, density, true single

chip, 1.2 V to 1.5 V core and I/O operation, reprogrammability, and advanced features.

Microsemi’s proven Flash*Freeze technology enables military ProASIC3EL device users to shut off

dynamic power instantaneously and switch the device to static mode without the need to switch off clocks

or power supplies, and retaining internal states of the device. This greatly simplifies power management.

In addition, optimized software tools using power-driven layout provide instant push-button power

reduction.

Nonvolatile flash technology gives military ProASIC3/EL devices the advantage of being a secure, low-

power, single-chip solution that is live at power-up (LAPU). Military ProASIC3/EL devices offer dramatic

dynamic power savings, giving FPGA users flexibility to combine low power with high performance.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

Military ProASIC3/EL devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as

well as clock conditioning circuitry (CCC) based on an integrated phase-locked loop (PLL). Military

ProASIC3/EL devices support devices from 250K system gates to 3 million system gates with up to 504

kbits of true dual-port SRAM and 620 user I/Os.

M1 military ProASIC3/EL devices support the high-performance, 32-bit Cortex-M1 processor developed

by ARM for implementation in FPGAs. ARM Cortex-M1 is a soft processor that is fully implemented in the

FPGA fabric. It has a three-stage pipeline that offers a good balance between low-power consumption

and speed when implemented in an M1 military ProASIC3/EL device. The processor runs the ARMv6-M

instruction set, has a configurable nested interrupt controller, and can be implemented with or without the

debug block. ARM Cortex-M1 is available at no cost from Microsemi for use in M1 military ProASIC3/EL

FPGAs.

The ARM-enabled devices have ordering numbers that begin with M1 and do not support AES

decryption.

†

Flash*Freeze Technology

Military ProASIC3EL devices offer Flash*Freeze technology, which allows instantaneous switching from

an active state to a static state. When Flash*Freeze mode is activated, military ProASIC3EL devices

enter a static state while retaining the contents of registers and SRAM. Power is conserved without the

need for additional external components to turn off I/Os or clocks. Flash*Freeze technology is combined

with in-system programmability, which enables users to quickly and easily upgrade and update their

designs in the final stages of manufacturing or in the field. The ability of military ProASIC3EL devices to

support a 1.2 V core voltage allows for an even greater reduction in power consumption, which enables

low total system power.

When the military ProASIC3EL device enters Flash*Freeze mode, the device automatically shuts off the

clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and

data is retained.

The availability of low-power modes, combined with a reprogrammable, single-chip, single-voltage

solution, make military ProASIC3EL devices suitable for low-power data transfer and manipulation in

military-temperature applications where available power may be limited (e.g., in battery-powered

equipment); or where heat dissipation may be limited (e.g., in enclosures with no forced cooling).

† Flash*Freeze technology is not supported on A3P1000.

Revision 5

1-1

Military ProASIC3/EL Device Family Overview

Flash Advantages

ƒ

Low Power

The military ProASIC3EL family of flash-based FPGAs provides a low-power advantage, and when

coupled with high performance, enables designers to make power-smart choices using a single-chip,

reprogrammable, and live-at-power-up device.

Military ProASIC3EL devices offer 40% dynamic power and 50% static power savings by reducing the

core operating voltage to 1.2 V. In addition, the power-driven layout (PDL) feature in Libero^®SoC offers

up to 30% additional power reduction. With Flash*Freeze technology, military ProASIC3EL device is able

to retain device SRAM and logic while dynamic power is reduced to a minimum, without the need to stop

clock or power supplies. Combining these features provides a low-power, feature-rich, and high-

performance solution.

Security

Nonvolatile, flash-based military ProASIC3/EL devices do not require a boot PROM, so there is no

vulnerable external bitstream that can be easily copied. Military ProASIC3/EL devices incorporate

FlashLock, which provides a unique combination of reprogrammability and design security without

external overhead, advantages that only an FPGA with nonvolatile flash programming can offer.

Military ProASIC3/EL devices utilize a 128-bit flash-based lock and a separate AES key to secure

programmed intellectual property and configuration data. In addition, all FlashROM data in military

ProASIC3/EL devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192)

bit block cipher encryption standard. AES was adopted by the National Institute of Standards and

Technology (NIST) in 2000 and replaces the 1977 DES standard. Military ProASIC3/EL devices have a

built-in AES decryption engine and a flash-based AES key that make them the most comprehensive

programmable logic device security solution available today. Military ProASIC3/EL devices with AES-

based security allow for secure, remote field updates over public networks such as the Internet, and

ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves.

Security, built into the FPGA fabric, is an inherent component of the military ProASIC3/EL family. The

flash cells are located beneath seven metal layers, and many device design and layout techniques have

been used to make invasive attacks extremely difficult. The military ProASIC3/EL family, with FlashLock

and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your

valuable IP is protected and secure, making remote ISP possible. A military ProASIC3/EL device

provides the most impenetrable security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the

configuration data is an inherent part of the FPGA structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based military

ProASIC3/EL FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area,

and increases security and system reliability.

Live at Power-Up

Flash-based military ProASIC3/EL devices support Level 0 of the LAPU classification standard. This

feature helps in system component initialization, execution of critical tasks before the processor wakes

up, setup and configuration of memory blocks, clock generation, and bus activity management. The

LAPU feature of flash-based military ProASIC3/EL devices greatly simplifies total system design and

reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition,

glitches and brownouts in system power will not corrupt the military ProASIC3/EL device's flash

configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system

power is restored. This enables the reduction or complete removal of the configuration PROM, expensive

voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based

military ProASIC3/EL devices simplify total system design and reduce cost and design risk while

increasing system reliability and improving system initialization time.

ƒ A3P1000 only supports 1.5 V core operation.

1-2

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-

based FPGAs, flash-based military ProASIC3/EL devices allow all functionality to be live at power-up; no

external boot PROM is required. On-board security mechanisms prevent access to all the programming

information and enable secure remote updates of the FPGA logic. Designers can perform secure remote

in-system reprogramming to support future design iterations and field upgrades with confidence that

valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the

industry-standard AES algorithm. The military ProASIC3/EL family device architecture mitigates the need

for ASIC migration at higher volumes. This makes the military ProASIC3/EL family a cost-effective ASIC

replacement.

Firm-Error Immunity

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike

a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These

errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not exist in the configuration memory of military ProASIC3/EL

flash-based FPGAs. Once it is programmed, the flash cell configuration element of military ProASIC3/EL

FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or

soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using

error detection and correction (EDAC) circuitry built into the FPGA fabric.

Advanced Flash Technology

The military ProASIC3/EL family offers many benefits, including nonvolatility and reprogrammability,

through an advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS

design techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization

without compromising device routability or performance. Logic functions within the device are

interconnected through a four-level routing hierarchy.

Advanced Architecture

The proprietary military ProASIC3/EL architecture provides granularity comparable to standard-cell

ASICs. The military ProASIC3/EL device consists of five distinct and programmable architectural

features (Figure 1-1 on page 1-4 and Figure 1-2 on page 1-4):

•

FPGA VersaTiles

Dedicated FlashROM

Dedicated SRAM/FIFO memory

Extensive CCCs and PLLs

I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic

function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch

interconnections. The versatility of the military ProASIC3/EL core tile, as either a three-input lookup table

(LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric. The

VersaTile capability is unique to the ProASIC family of third-generation-architecture flash FPGAs.

VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed

throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core

utilization is possible for virtually any design.

Revision 5

1-3

Military ProASIC3/EL Device Family Overview

Bank 0

CCC

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

I/Os

VersaTile

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

ISP AES

Decryption

User Nonvolatile

FlashROM

Charge Pumps

Bank 2

Figure 1-1 • Military ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250 and A3P1000)

CCC

RAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

Pro I/Os

VersaTile

RAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

ISP AES

Decryption*

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

Figure 1-2 • Military ProASIC3EL Device Architecture Overview (A3PE600L and A3PE3000L)

1-4

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

††

Flash*Freeze Technology

Military ProASIC3EL devices offer proven Flash*Freeze technology, which enables designers to

instantaneously shut off dynamic power consumption while retaining all SRAM and register information.

Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by

activating the Flash*Freeze (FF) pin while all power supplies are kept at their original values. In addition,

I/Os and global I/Os can still be driven and can be toggling without impact on power consumption; clocks

can still be driven or can be toggling without impact on power consumption; all core registers and SRAM

cells retain their states. I/Os are tristated during Flash*Freeze mode or can be set to a certain state using

weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks,

JTAG pins, or PLLs. Flash*Freeze technology allows the user to switch to active mode on demand, thus

simplifying the power management of the device.

The FF pin (active low) can be routed internally to the core to allow the user's logic to decide when it is

safe to transition to this mode. It is also possible to use the FF pin as a regular I/O if Flash*Freeze mode

usage is not planned, which is advantageous because of the inherent low-power static and dynamic

capabilities of the military ProASIC3EL device. Refer to Figure 1-3 for an illustration of entering/exiting

Flash*Freeze mode.

Microsemi ProASIC3EL

FPGA

Flash*Freeze

Mode Control

Flash*Freeze Pin

Figure 1-3 • Military ProASIC3EL Flash*Freeze Mode

VersaTiles

The military ProASIC3/EL core consists of VersaTiles, which have been enhanced beyond the

ProASIC^PLUS®core tiles. The military ProASIC3/EL VersaTile supports the following:

•

All 3-input logic functions—LUT-3 equivalent

Latch with clear or set

D-flip-flop with clear or set

Enable D-flip-flop with clear or set

Refer to Figure 1-4 for VersaTile configurations.

Enable D-Flip-Flop with Clear or Set

D-Flip-Flop with Clear or Set

LUT-3 Equivalent

X1

Data

Y

Data

CLK

CLR

Y

X2

X3

LUT-3

Y

D-FF

CLK

D-FF

Enable

CLR

Figure 1-4 • VersaTile Configurations

††Flash*Freeze technology is not supported for A3P1000.

Revision 5

1-5

Military ProASIC3/EL Device Family Overview

User Nonvolatile FlashROM

Military ProASIC3/EL devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The

FlashROM can be used in diverse system applications:

•

Internet protocol addressing (wireless or fixed)

System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, set-top boxes)

Secure key storage for secure communications algorithms

Asset management/tracking

Date stamping

Version management

FlashROM is written using the standard military ProASIC3/EL IEEE 1532 JTAG programming interface.

The core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks, as in security keys stored in the FlashROM for a

user design.

FlashROM can be programmed via the JTAG programming interface, and its contents can be read back

either through the JTAG programming interface or via direct FPGA core addressing. Note that the

FlashROM can only be programmed from the JTAG interface and cannot be programmed from the

internal logic array.

FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis

using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and

which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the

FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM

address define the byte.

Microsemi military ProASIC3/EL development software solutions, Libero SoC has extensive support for

the FlashROM. One such feature is auto-generation of sequential programming files for applications

requiring a unique serial number in each part. Another feature allows the inclusion of static data for

system version control. Data for the FlashROM can be generated quickly and easily using the Libero

SoC software tools. Comprehensive programming file support is also included to allow for easy

programming of large numbers of parts with differing FlashROM contents.

SRAM and FIFO

Military ProASIC3/EL devices have embedded SRAM blocks along their north and south sides. Each

variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18,

512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can

be configured with different bit widths on each port. For example, data can be sent through a 4-bit port

and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port

(ROM emulation mode) using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width

and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and

Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control

unit contains the counters necessary for generation of the read and write address pointers. The

embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

Military ProASIC3 devices provide designers with flexible clock conditioning circuit (CCC) capabilities.

Each member of the military ProASIC3 family contains six CCCs, located at the four corners and the

centers of the east and west sides. One CCC (center west side) has a PLL. All six CCC blocks are

usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock

spine access.

Military ProASIC3EL devices also contain six CCCs; however, all six are equipped with a PLL.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

1-6

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

The CCC block has these key features:

•

Wide input frequency range (f_{IN_CCC}) = 1.5 MHz up to 250 MHz

Output frequency range (f_{OUT_CCC}) = 0.75 MHz up to 250 MHz

2 programmable delay types for clock skew minimization

Clock frequency synthesis

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration.

•

Output duty cycle = 50% ± 1.5% or better

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used

•

Maximum acquisition time is 300 µs

Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns

Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

f_{OUT_CCC}

Global Clocking

Military ProASIC3/EL devices have extensive support for multiple clocking domains. In addition to the

CCC and PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high-fanout nets.

I/Os with Advanced I/O Standards

The military ProASIC3/EL family of FPGAs features a flexible I/O structure, supporting a range of

voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). In addition, 1.2 V I/O operation is supported for military

ProASIC3EL devices. Military ProASIC3/EL FPGAs support different I/O standards, including single-

ended, differential, and voltage-referenced (military ProASIC3EL). The I/Os are organized into banks,

with two, four, or eight (military ProASIC3EL only) banks per device. The configuration of these banks

determines the I/O standards supported. For military ProASIC3EL, each I/O bank is subdivided into V_REF

minibanks, which are used by voltage-referenced I/Os. V_REFminibanks contain 8 to 18 I/Os. All the I/Os

in a given minibank share a common V_REFline. Therefore, if any I/O in a given V_REFminibank is

configured as a V_REFpin, the remaining I/Os in that minibank will be able to use that reference voltage.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

•

Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)

Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).

Military ProASIC3EL banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can

support up to 20 loads.

Revision 5

1-7

2 – Military ProASIC3/EL DC and Switching

Characteristics

General Specifications

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

absolute maximum ratings are stress ratings only; functional operation of the device at these or any other

conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on

page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings¹

Symbol

VCC

Parameter

DC core supply voltage

JTAG DC voltage

Limits

Units

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

V

VJTAG

VPUMP Programming voltage

VCCPLL Analog power supply (PLL)

VCCI

DC I/O buffer supply voltage for

A3PE600/3000L

DC output buffer supply voltage for

A3P250/A3P1000

VMV

VI

DC input buffer supply voltage for

A3P250/A3P1000

–0.3 to 3.75

V

I/O input voltage

–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is

lower (when I/O hot-insertion mode is disabled)

2

T_STG

Storage temperature

Junction temperature

–65 to +150

+150

°C

2

T_J

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. For flash programming and retention maximum limits, refer to Table 2-4 on page 2-3, and for recommended operating

limits, refer to Table 2-2 on page 2-2.

Revision 5

2-1

Military ProASIC3/EL DC and Switching Characteristics

Table 2-2 • Recommended Operating Conditions ¹

Symbol

T_J

Parameter

Military

Units

°C

V

Junction temperature

1.5 V DC core supply voltage³

–55 to 125 ²

1.425 to 1.575

1.14 to 1.575

VCC

1.2 V – 1.5 V wide range DC core

supply voltage ⁴

V

VJTAG

JTAG DC voltage

1.4 to 3.6

3.15 to 3.45

0 to 3.6

V

VPUMP⁵

Programming voltage

Programming mode

Operation⁶

VCCPLL⁵

Analog power supply (PLL)

1.5 V DC core supply voltage³

1.425 to 1.575

1.2 V – 1.5 V DC core supply 1.14 to 1.575

voltage⁴

VCCI and VMV⁵1.2 V DC supply voltage⁴

1.2 V wide range DC supply voltage⁴

1.14 to 1.26

1.14 to 1.575

1.425 to 1.575

1.7 to 1.9

V

1.5 V DC supply voltage

1.8 V DC supply voltage

2.5 V DC supply voltage

3.0 V DC supply voltage⁷

3.3 V DC supply voltage

LVDS differential I/O

2.3 to 2.7

2.7 to 3.6

3.0 to 3.6

2.375 to 2.625

3.0 to 3.6

LVPECL differential I/O

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. Default Junction Temperature Range in the Libero SoC software is set from 0°C to +70°C for commercial, and -40°C to

+85°C for industrial. To ensure targeted reliability standards are met across the full range of junction temperatures,

Microsemi recommends using custom settings for temperature range before running timing and power analysis tools.

For more information regarding custom settings, refer to the New Project Dialog Box in the Libero SoC Online Help.

3. For A3P250 and A3P1000

4. For A3PE600L and A3PE3000L devices only, operating at VCCI  VCC.

5. See the "Pin Descriptions and Packaging" section on page 3-1 for instructions and recommendations on tie-off and

supply grouping.

6. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-25 on page 2-22. VCCI should be at the same voltage within a given I/O bank.

7. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.

8. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi

recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.

2-2

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature¹

Product

Grade

Programming Program Retention

Maximum Storage

Maximum Operating

Cycles

(biased/unbiased) Temperature T_STG(°C) ²Junction Temperature T_J(°C) ²

Commercial

Industrial

Notes:

500

20 years

110

100

500

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

Table 2-4 • Overshoot and Undershoot Limits¹

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle²

Maximum Overshoot/

Undershoot (125°C)²

VCCI and VMV

2.7 V or less

10%

5%

0.72 V

0.82 V

0.72 V

0.82 V

0.69 V

0.79 V

N/A

3 V

10%

5%

3.3 V

3.6 V

Notes:

10%

5%

10%

5%

N/A

1. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

2. This table does not provide PCI overshoot/undershoot limits.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Military)

Sophisticated power-up management circuitry is designed into every ProASIC^®3 device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-4 and Figure 2-2 on page 2-5.

There are five regions to consider during power-up.

Military ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and

Figure 2-2 on page 2-5).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

•

During programming, I/Os become tristated and weakly pulled up to VCCI.

Revision 5

2-3

Military ProASIC3/EL DC and Switching Characteristics

•

JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic, at least until VCC and VCCPLX exceed brownout

activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 and Figure 2-

2 on page 2-5 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V

± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-

Down Behavior of Low-Power Flash Devices" chapter of the Military ProASIC3/EL FPGA Fabric User’s

Guide for information on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation.

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

(except differential

and timer specifications for

speed, VIH / VIL, VOH / VOL,

etc.

but slower because VCCI

is below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.425 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

I/Os are functional (except differential inputs)

but slower because VCCI / VCC are below

specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Activation trip point:

V_a= 0.85 V ± 0.25 V

Deactivation trip point:

Region 1: I/O buffers are OFF

V_d= 0.75 V ± 0.25 V

VCCI

Activation trip point:

_a= 0.9 V ± 0.3 V

Deactivation trip point:

Min VCCI datasheet specification

V

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

V_d= 0.8 V ± 0.3 V

Figure 2-1 • Devices Operating at 1.5 V Core – I/O State as a Function of VCCI and VCC Voltage Levels

2-4

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL , VOH / VOL , etc.

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.14 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Activation trip point:

V_a= 0.85 V ± 0.2 V

Deactivation trip point:

Region 1: I/O buffers are OFF

V_d= 0.75 V ± 0.2 V

VCCI

Activation trip point:

_a= 0.9 V ± 0.15 V

Deactivation trip point:

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.14 V,1.425 V, 1.7 V,

2.3 V, or 3.0 V

V

V_d= 0.8 V ± 0.15 V

Figure 2-2 • Device Operating at 1.2 V Core Voltage – I/O State as a Function of VCCI and VCC Voltage

Levels; Only A3PE600L and A3PE3000L Devices Operate at 1.2 V Core Voltage

Thermal Characteristics

Introduction

The temperature variable in the Designer software refers to the junction temperature, not the ambient

temperature. This is an important distinction because dynamic and static power consumption cause the

chip junction temperature to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

T_J= Junction Temperature = T + T_A

EQ 1

where:

T_A= Ambient Temperature

T = Temperature gradient between junction (silicon) and ambient T = _ja* P

_ja= Junction-to-ambient of the package. _janumbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is _jcand the junction-to-ambient air thermal resistivity is

_ja. The thermal characteristics for _jaare shown for two air flow rates. The recommended maximum

junction temperature is 125°C. EQ 2 shows a sample calculation of the recommended maximum power

dissipation allowed for a 484-pin FBGA package at military temperature and in still air.

Max. junction temp. (C) – Max. ambient temp. (C) 125C – 70C

Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------- = 2.670

_ja(C/W)

20.6C/W

Revision 5

2-5

Military ProASIC3/EL DC and Switching Characteristics

EQ 2

Table 2-5 • Package Thermal Resistivities

_ja

Pin Count _jcStill Air 200 ft./min. 500 ft./min. Units

Package Type

Device

A3P250

Very Thin Quad Flat Pack (VQ100)

Plastic Quad Flat Pack (PQ208)*

Fine Pitch Ball Grid Array (FBGA)

100

208

144

256

484

896

10.0

3.8

6.3

6.6

8.0

9.5

4.7

2.4

35.3

16.2

31.6

28.1

23.3

27.5

20.6

13.6

29.4

13.3

26.2

24.4

19.0

21.9

15.7

10.4

27.1

11.9

24.2

22.7

16.7

20.2

14.0

9.4

C/W

A3P1000

A3PE600L

A3PE3000L

* Embedded heatspreader

Temperature and Voltage Derating Factors

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 125°C, VCC = 1.14 V)

Applicable to A3PE600L and A3PE3000L Only

Junction Temperature

Array Voltage VCC (V)

–55°C

0.85

0.82

0.79

0.77

0.74

0.72

0.71

0.67

0.65

–40°C

0.86

0.83

0.80

0.78

0.75

0.73

0.71

0.68

0.66

0°C

0.89

0.86

0.83

0.81

0.78

0.75

0.74

0.70

0.68

25°C

0.92

0.88

0.85

0.83

0.80

0.77

0.76

0.72

0.70

70°C

85°C

0.97

0.93

0.90

0.88

0.85

0.82

0.80

0.76

0.74

125°C

1.14

1.2

0.96

0.92

0.89

0.86

0.84

0.81

0.79

0.75

0.73

1.00

0.96

0.93

0.90

0.88

0.85

0.83

0.79

0.76

1.26

1.30

1.35

1.40

1.425

1.5

1.575

Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 125°C, VCC = 1.425 V)

Applicable to A3P250 and A3P1000 Devices Only

Junction Temperature

Array Voltage VCC (V)

–55°C

0.80

–40°C

0.82

0°C

25°C

0.89

0.84

0.82

70°C

85°C

0.96

0.91

0.87

125°C

1.00

1.425

1.5

0.87

0.82

0.79

0.94

0.89

0.86

0.76

0.78

0.95

1.575

0.73

0.75

0.91

2-6

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

Calculating Power Dissipation

Quiescent Supply Current

Table 2-8 • Power Supply State Per Mode

Power Supply Configurations

VCCPLL VCCI VJTAG

On On

Modes/Power Supplies

Flash*Freeze

Sleep

VCC

On

VPUMP

On/off/floating

Off

On

Off

On

Off

On

Off

On

Off

On

Shutdown

Off

Static and Active

On

On/off/floating

Table 2-9 • Quiescent Supply Current (IDD) Characteristics, Flash*Freeze Mode*

Core Voltage

1.2 V

A3PE600L

A3PE3000L

Units

mA

Nominal (25°C)

0.55

0.83

9

2.75

4.2

17

1.5 V

Typical maximum (25ºC)

Military maximum (125ºC)

1.2 V

1.5 V

12

20

1.2 V

65

165

185

1.5 V

85

Note: *IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. Values do not include I/O static contribution

(PDC6 and PDC7).

Table 2-10 • Quiescent Supply Current (IDD) Characteristics, Sleep Mode (VCC = 0 V)*

Core Voltage

A3PE600L

A3PE3000L

Units

VCCI / VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V

1.7

µA

VCCI / VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V

1.8

1.9

2.2

2.5

1.8

1.9

2.2

2.5

µA

VCCI / VJTAG = 1.8 V (per bank)

Typical (25°C)

VCCI / VJTAG = 2.5 V (per bank)

Typical (25°C)

VCCI / VJTAG = 3.3 V (per bank)

Typical (25°C)

Note: *IDD = N

× ICCI. Values do not include I/O static contribution, which is shown in Table 2-22 on page 2-14 (PDC6

BANKS

and PDC7).

Table 2-11 • Quiescent Supply Current (IDD) Characteristics, Shutdown Mode*

Core Voltage

1.2 V / 1.5 V

A3P250

A3P1000

A3PE600L

A3PE3000L

Units

µA

Nominal (25°C)

Military (125ºC)

N/A

0

µA

Note: *This is applicable to A3PE600L and A3PE3000L only for cold-sparable I/O devices. Not available on A3P250 or

A3P1000.

Revision 5

2-7

Military ProASIC3/EL DC and Switching Characteristics

Table 2-12 • Quiescent Supply Current (IDD), Static Mode and Active Mode ¹

Core Voltage

A3PE600L

A3PE3000L

Units

ICCA Current²

Nominal (25°C)

1.2 V

1.5 V

1.2 V

1.5 V

1.2 V

1.5 V

0.55

0.83

9

2.75

4.2

17

mA

Typical maximum (25°C)

Military maximum (125°C)

ICCI or IJTAG Current³

12

20

65

165

185

85

VCCI / VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

µA

VCCI / VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V

VCCI / VJTAG = 1.8 V (per bank)

Typical (25°C)

VCCI / VJTAG = 2.5 V (per bank)

Typical (25°C)

VCCI / VJTAG = 3.3 V (per bank)

Typical (25°C)

Notes:

1. IDD = N

× ICCI + ICCA. JTAG counts as one bank when powered.

BANKS

2. Includes VCC , VCCPLL, and VPUMP currents.

3. Values do not include I/O static contribution (PDC6 and PDC7).

Table 2-13 • Quiescent Supply Current (IDD) Characteristics for A3P250 and A3P1000

Core Voltage

1.5 V

A3P250

A3P1000

Units

mA

Nominal (25°C)

3

8

Typical maximum (25°C)

Military maximum (125°C)

1.5 V

15

65

30

mA

1.5 V

150

mA

Note: IDD includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution (PDC6 and PDC7),

which is shown in Table 2-22 on page 2-14.

2-8

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

Power per I/O Pin

Table 2-14 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Static Power PDC6

Dynamic Power

PAC9 (µW/MHz)²

VCCI (V)

(mW)¹

Single-Ended

3.3 V LVTTL/LVCMOS

3.3 V LVTTL/LVCMOS – Schmitt trigger

3.3 V LVCMOS Wide Range

3.3 V LVCMOS – Schmitt trigger Wide Range

2.5 V LVCMOS

3.3

2.5

1.8

1.5

1.2

3.3

–

16.34

24.49

16.34

24.49

4.71

2.5 V LVCMOS – Schmitt trigger

1.8 V LVCMOS

6.13

1.66

1.8 V LVCMOS – Schmitt trigger

1.5 V LVCMOS (JESD8-11)

1.5 V LVCMOS (JESD8-11) – Schmitt trigger

1.2 V LVCMOS

1.78

1.01

0.97

0.60

1.2 V LVCMOS (JESD8-11) – Schmitt trigger

1.2 V LVCMOS Wide Range

1.2 V LVCMOS Schmitt trigger Wide Range

3.3 V PCI

0.53

0.60

0.53

17.76

19.10

17.76

19.10

3.3 V PCI – Schmitt trigger

3.3 V PCI-X

3.3 V PCI-X – Schmitt trigger

Voltage-Referenced

3.3 V GTL

3.3

2.5

3.3

2.5

1.5

2.5

3.3

2.90

2.13

2.81

2.57

0.17

1.38

3.21

7.14

3.54

2.91

2.61

0.79

3.26

7.97

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

2.5

3.3

2.26

5.71

0.89

1.94

LVPECL

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

Revision 5

2-9

Military ProASIC3/EL DC and Switching Characteristics

Table 2-15 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only

Static Power

PDC6 (mW)¹

Dynamic Power

VMV (V)

PAC9 (µW/MHz)²

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS – Wide Range

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

3.3

2.5

1.8

1.5

3.3

–

16.22

4.65

1.65

0.98

17.64

3.3 V PCI-X

Differential

LVDS

2.5

3.3

2.26

5.72

0.83

1.81

LVPECL

Notes:

1. PDC6 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VMV.

Table 2-16 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only

Static Power

PDC6 (mW) ¹

Dynamic Power

VMV (V)

PAC9 (µW/MHz) ²

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS – Wide Range

2.5 V LVCMOS

3.3

2.5

1.8

1.5

3.3

–

16.23

4.66

1.8 V LVCMOS

1.64

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

0.99

17.64

3.3 V PCI-X

Notes:

1. PDC6 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VMV.

2-10

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings ¹

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Static Power

PDC7 (mW)²

Dynamic Power

C_LOAD(pF)

VCCI (V)

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL/LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS

1.2 V LVCMOS Wide Range

3.3 V PCI

5

3.3

2.5

1.8

1.5

1.2

3.3

–

148.00

83.23

54.58

37.05

17.94

204.61

5

10

3.3 V PCI-X

Voltage-Referenced

3.3 V GTL

10

20

30

3.3

2.5

3.3

2.5

1.5

2.5

3.3

–

24.08

13.52

24.10

13.54

26.22

27.18

105.56

116.48

114.67

131.69

2.5 V GTL

–

3.3 V GTL+

–

2.5 V GTL+

–

HSTL (I)

7.08

13.88

16.69

25.91

26.02

42.21

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

–

2.5

3.3

7.70

89.58

LVPECL

19.42

167.86

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

Revision 5

2-11

Military ProASIC3/EL DC and Switching Characteristics

Table 2-18 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings ¹

Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only

Static Power PDC7

Dynamic Power

C_LOAD(pF)

VCCI (V)

(mW) ²

PAC10 (µW/MHz) ³

Single-Ended

3.3 V LVTTL /

5

3.3

–

141.97

3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

5

3.3

2.5

1.8

1.5

3.3

–

141.97

79.98

5

52.26

5

35.62

10

201.02

3.3 V PCI-X

Differential

LVDS

–

2.5

3.3

7.74

89.82

LVPECL

19.54

167.55

Notes:

1. Dynamic Power consumption is given for software default drive strength and output slew. Output load is lower than the

software default.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

Table 2-19 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only

Static Power

PDC7 (mW) ²

Dynamic Power

C_LOAD(pF)

VCCI (V)

PAC10 (µW/MHz) ³

Single-Ended

3.3 V LVTTL /

5

3.3

–

125.97

3.3 V LVCMOS

3.3 V LVCMOS – Wide Range

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

5

3.3

2.5

1.8

1.5

3.3

–

125.97

70.82

5

36.39

5

25.34

10

184.92

3.3 V PCI-X

Notes:

1. Dynamic Power consumption is given for software default drive strength and output slew. Output load is lower than the

software default.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

2-12

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

Power Consumption of Various Internal Resources

Table 2-20 • Different Components Contributing to Dynamic Power Consumption in Military ProASIC3/EL

Devices Operating at 1.2 V VCC

Device-Specific Dynamic Power

(µW/MHz)

Parameter

PAC1

Definition

Clock contribution of a Global Rib

Clock contribution of a Global Spine

Clock contribution of a VersaTile row

A3PE3000L

8.34

A3PE600L

3.99

PAC2

4.28

2.22

PAC3

0.94

PAC4

Clock contribution of a VersaTile used as a sequential

module

0.08

PAC5

PAC6

First contribution of a VersaTile used as a sequential module

0.05

0.19

Second contribution of a VersaTile used as a sequential

module

PAC7

PAC8

PAC9

Contribution of a VersaTile used as a combinatorial module

Average contribution of a routing net

0.11

0.45

Contribution of an I/O input pin (standard-dependent)

See Table 2-14 on page 2-9

through Table 2-16 on page 2-10.

PAC10

Contribution of an I/O output pin (standard-dependent)

See Table 2-17 on page 2-11

through Table 2-19 on page 2-12.

PAC11

PAC12

PAC13

Average contribution of a RAM block during a read operation

Average contribution of a RAM block during a write operation

Dynamic contribution for PLL

25.00

30.00

1.74

Revision 5

2-13

Military ProASIC3/EL DC and Switching Characteristics

Table 2-21 • Different Components Contributing to Dynamic Power Consumption in Military ProASIC3 and

ProASIC3/EL Devices at 1.5 V VCC

Device-Specific Dynamic Power (µW/MHz)

Parameter

PAC1

Definition

A3PE3000L A3PE600L A3P1000

A3P250

11.00

1.58

Clock contribution of a Global Rib

Clock contribution of a Global Spine

Clock contribution of a VersaTile row

13.03

6.69

1.46

0.13

6.24

3.47

1.46

0.13

14.50

2.48

0.81

0.12

PAC2

PAC3

0.81

PAC4

Clock contribution of a VersaTile used as a

sequential module

0.12

PAC5

PAC6

PAC7

First contribution of a VersaTile used as a

sequential module

0.07

0.29

0.70

Second contribution of a VersaTile used as a

sequential module

Contribution of

a

VersaTile used as

a

combinatorial Module

PAC8

PAC9

Average contribution of a routing net

Contribution of an I/O input pin (standard- See Table 2-14 on page 2-9 through Table 2-16 on

dependent) page 2-10.

PAC10

PAC11

PAC12

PAC13

Contribution of an I/O output pin (standard- See Table 2-17 on page 2-11 through Table 2-19 on

dependent)

page 2-12.

Average contribution of a RAM block during a

read operation

25.00

Average contribution of a RAM block during a

write operation

30.00

2.60

Dynamic contribution for PLL

Table 2-22 • Different Components Contributing to the Static Power Consumption in Military ProASIC3/EL

Devices

Device-Specific Dynamic Power (µW)

Parameter

PDC0

Definition

A3PE3000L A3PE600L A3P1000 A3P250

0 mW 0 mW N/A N/A

Array static power in Sleep mode

Array static power in Active mode

Array static power in Static (Idle) mode

Array static power in Flash*Freeze mode

PDC1

See Table 2-12 on page 2-8.

See Table 2-9 on page 2-7.

PDC2

PDC3

PDC4

Static PLL contribution at 1.2 V operating core

voltage (for A3PE600L and A3PE3000L only)

1.42 mW

N/A

Static PLL contribution 1.5 V operating core

voltage

2.55 mW

PDC5

PDC6

PDC7

Bank quiescent power (V_CCI-dependent)

See Table 2-9 on page 2-7, Table 2-10 on page 2-7,

Table 2-12 on page 2-8.

I/O input pin static power (standard-dependent)

I/O output pin static power (standard-dependent)

See Table 2-14 on page 2-9. through Table 2-16 on

page 2-10.

See Table 2-17 on page 2-11 through Table 2-19 on

page 2-12.

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi

power spreadsheet calculator or SmartPower tool in the Libero SoC.

2-14

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in the Libero SoC software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock generated

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-23 on

page 2-17.

•

Enable rates of output buffers—guidelines are provided for typical applications in Table 2-24 on

page 2-17.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-24 on page 2-17. The calculation should be repeated for each clock domain defined in the

design.

Methodology

Total Power Consumption—P

TOTAL

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

P

STAT

P_STAT= (PDC0 or PDC1 or PDC2 or PDC3) + N_BANKS* P_DC5+ N_INPUTS* PDC6 + N_OUTPUTS* PDC7

N_INPUTSis the number of I/O input buffers used in the design.

N

_OUTPUTSis the number of I/O output buffers used in the design.

_BANKSis the number of I/O banks powered in the design.

N

Total Dynamic Power Consumption—P

DYN

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL

Global Clock Contribution—P

CLOCK

P_CLOCK= (PAC1 + N_SPINE* PAC2 + N_ROW* PAC3 + N_S-CELL* PAC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided in

Table 2-23 on page 2-17.

N_ROWis the number of VersaTile rows used in the design—guidelines are provided in

Table 2-23 on page 2-17.

F

_CLKis the global clock signal frequency.

_S-CELLis the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—P

N

S-CELL

P_S-CELL= N_S-CELL* (PAC5 + ₁/ 2 * PAC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on

page 2-17.

F_CLKis the global clock signal frequency.

Revision 5

2-15

Military ProASIC3/EL DC and Switching Characteristics

Combinatorial Cells Contribution—P

C-CELL

P_C-CELL= N_C-CELL* ₁/ 2 * PAC7 * F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on

page 2-17.

F_CLKis the global clock signal frequency.

Routing Net Contribution—P

NET

P_NET= (N_S-CELL+ N_C-CELL) * ₁/ 2 * PAC8 * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on

page 2-17.

F

_CLKis the global clock signal frequency.

I/O Input Buffer Contribution—P

INPUTS

P_INPUTS= N_INPUTS* ₂/ 2 * PAC9 * F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-23 on page 2-17.

F

_CLKis the global clock signal frequency.

I/O Output Buffer Contribution—P

OUTPUTS

P_OUTPUTS= N_OUTPUTS* ₂/ 2 * ₁* PAC10 * F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-23 on page 2-17.

₁is the I/O buffer enable rate—guidelines are provided in Table 2-24 on page 2-17.

F

_CLKis the global clock signal frequency.

RAM Contribution—P

MEMORY

P_MEMORY= PAC11 * N_BLOCKS* F_READ-CLOCK* ₂+ P_AC12* N_BLOCK* F_WRITE-CLOCK* ₃

N_BLOCKSis the number of RAM blocks used in the design.

F

_READ-CLOCKis the memory read clock frequency.

₂is the RAM enable rate for read operations.

_WRITE-CLOCKis the memory write clock frequency.

F

₃is the RAM enable rate for write operations—guidelines are provided in Table 2-24 on

page 2-17.

PLL Contribution—P

PLL

P_PLL= PDC4 + PAC13 * F_CLKOUT

F_CLKOUTis the output clock frequency.¹

1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding

contribution (P_AC13* F_CLKOUTproduct) to the total PLL contribution.

2-16

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are

some examples:

•

The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the

clock frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1

Bit 2

…

= 50%

= 25%

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

nontristate output buffers are used, the enable rate should be 100%.

Table 2-23 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

₁

₂

10%

Table 2-24 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

₁

₂

₃

RAM enable rate for read operations

RAM enable rate for write operations

12.5%

Revision 5

2-17

Military ProASIC3/EL DC and Switching Characteristics

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

Y

Combinational Cell

Y

LVPECL

t

= 0.78 ns

t

= 0.67 ns

PD

t

= 1.51 ns

DP

I/O Module

(Non-Registered)

Combinational Cell

Y

LVTTL Output Drive Strength = 12 mA

High Slew Rate

t

= 2.09 ns

DP

t

= 1.21 ns

PD

I/O Module

(Non-Registered)

Combinational Cell

Y

I/O Module

(Registered)

Output Drive Strength = 8 mA

High Slew Rate

LVTTL

t

= 1.84 ns

PY

t

= 2.38 ns

DP

LVPECL

t

= 0.70 ns

PD

I/O Module

(Non-Registered)

D

Q

Combinational Cell

Y

LVCMOS 1.5 V

Output Drive Strength = 4 mA

High Slew Rate

t

= 0.33 ns

= 0.36 ns

ICLKQ

ISUD

t

= 2.84 ns

DP

t

= 0.65 ns

PD

Input LVTTL

Clock

I/O Module

Register Cell

(Registered)

Register Cell

Combinational Cell

Y

t

= 1.49 ns

PY

D

Q

D

Q

D

t

Q

LVTTL 3.3 V Output Drive

Strength = 12 mA

I/O Module

t

= 0.65 ns

PD

t

= 2.09 ns

High Slew Rate

(Non-Registered)

DP

t

= 0.76 ns

= 0.59 ns

CLKQ

= 0.81 ns

= 0.43 ns

t

= 0.76 ns

= 0.9 ns

OCLKQ

CLKQ

LVDS,

B-LVDS,

M-LVDS

SUD

t

OSUD

SUD

Input LVTTL

Clock

Input LVTTL

Clock

t

= 2.11 ns

PY

t

= 1.49 ns

t

= 1.49 ns

PY

Figure 2-3 • Timing Model

Operating Conditions: –1 Speed, Military Temperature Range (T_J= 125°C), Worst-Case

VCC = 1.14 V (example for A3PE3000L and A3PE600L)

2-18

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

t_PY

t_DIN

D

Q

PAD

DIN

Y

CLK

To Array

I/O Interface

t

_PY= MAX(t_PY(R), t_PY(F))

_DIN= MAX(t_DIN(R), t_DIN(F))

VIH

V_trip

VIL

PAD

VCC

50%

Y

GND

t_PY

(R)

t_PY

(F)

VCC

50%

DIN

t_DIN

(R)

GND

t_DIN

(F)

Figure 2-4 • Input Buffer Timing Model and Delays (Example)

Revision 5

2-19

Military ProASIC3/EL DC and Switching Characteristics

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

D

From Array

t_DP= MAX(t_DP(R), t_DP(F))

t_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t_DOUT

(R)

t_DOUT

(F)

VCC

50%

VCC

50%

D

0 V

50%

DOUT

PAD

0 V

VOH

Vtrip

V_OL

Vtrip

t_DP

(R)

t_DP

(F)

Figure 2-5 • Output Buffer Model and Delays (example)

2-20

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

t

EOUT

D

Q

CLK

t

, t , t , t , t , t

E

ZL ZH HZ LZ ZLS ZHS

EOUT

D

Q

PAD

DOUT

CLK

D

t

= MAX(t

(r), t (f))

EOUT

I/O Interface

EOUT

VCC

D

E

VCC

50%

t

50%

t

EOUT (F)

EOUT (R)

VCC

50%

ZH

50%

t

LZ

EOUT

PAD

t

ZL

HZ

VCCI

90% VCCI

Vtrip

VOL

10% V

CCI

VCC

D

E

VCC

50%

t

EOUT (F)

EOUT (R)

VCC

50%

EOUT

PAD

50%

VOH

t

ZHS

t

ZLS

Vtrip

VOL

Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)

Revision 5

2-21

Military ProASIC3/EL DC and Switching Characteristics

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Military Conditions—Software Default Settings

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

2

Equiv.

Software

VIL

VIH

VOL

VOH

I_OLI_OH

Default

Drive

Drive Strength Slew Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

I/O Standard

Strength Option¹Rate

V

mA mA

3.3 V LVTTL / 3.3 12 mA 12 mA High –0.3

V LVCMOS

0.8

2

3.6

0.4

2.4

12 12

3.3 V LVCMOS

Wide Range^1,3

100 µA 12 mA High –0.3

0.8

0.7

2

0.2

VCCI – 0.2 0.1 0.1

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

12 mA 12mA High –0.3

1.7

0.7

1.7

12 12

12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6

0.45

VCCI – 0.45 12 12

12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12

2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI

1.2 V LVCMOS^4,52 mA

2

1.2 V LVCMOS

Wide Range^1,4,5

100 µA

2 mA High –0.3 0.3 * VCCI 0.7 * VCCI 3.6

0.1

VCCI – 0.1 0.1 0.1

3.3 V PCI

3.3 V PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

Per PCI Specification

Per PCI-X Specification

20 mA⁶20 mA High –0.3 VREF – 0.05 VREF + 0.05 3.6

35 mA 35 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6

33 mA 33 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6

0.4

–

20 20

35 35

33 33

–

0.6

–

0.6

8 mA

8 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6

0.4

VCCI – 0.4

8

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

15 mA⁶15 mA⁶High –0.3 VREF – 0.1 VREF + 0.1 3.6

15 mA 15 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6

18 mA 18 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6

14 mA 14 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6

21 mA 21 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6

VCCI – 0.4 15 15

VCCI – 0.62 15 15

VCCI – 0.43 18 18

VCCI – 1.1 14 14

VCCI – 0.9 21 21

0.54

0.35

0.7

0.5

1. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration

will not operate at the equivalent software default drive strength These values are for normal ranges only.

2. Currents are measured at 125°C junction temperature.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

4. Applicable to A3PE600L and A3PE3000L devices operating at VCCI VCC.

5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

6. Output drive strength is below JEDEC specification.

7. Output slew rate can be extracted using the IBIS Models.

2-22

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

Table 2-26 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Military

Conditions—Software Default Settings

Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only

2

Equiv.

Software

VIL

VIH

VOL

VOH

I_OLI_OH

Default

Drive

Drive Strength Slew Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

I/O Standard Strength Option¹Rate

V

mA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High –0.3

0.8

2

3.6

2.7

0.4

2.4

12 12

3.3 VLVCMOS 100 µA 12 mA High –0.3

Wide Range^1,3

0.8

2

0.2

VCCI – 0.2 0.1 0.1

2.5 V LVCMOS 12 mA 12 mA High –0.3

0.7

1.7

0.7

1.7

12 12

1.8 V LVCMOS 12 mA

1.5 V LVCMOS 12 mA

3.3 V PCI

12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9

0.45

VCCI – 0.45 12 12

12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12

Per PCI specifications

3.3 V PCI-X

Per PCI-X specifications

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the

equivalent software default drive strength. These values are for normal ranges only.

2. Currents are measured at 125°C junction temperature.

3. Output slew rate can be extracted using the IBIS Models.

4. Output drive strength is below JEDEC specification.

5. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

Table 2-27 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Military

Conditions—Software Default Settings

Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only

2

Equiv.

Software

VIL

VIH

VOL

VOH

I_OLI_OH

Default

Drive

Drive Strength Slew Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

I/O Standard Strength Option¹Rate

V

mA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA

12 mA High –0.3

0.8

2

3.6

2.7

0.4

2.4

12 12

3.3 V LVCMOS 100 µA 12 mA High –0.3

Wide Range^1,3

0.8

0.7

2

0.2

VCCI – 0.2 0.1 0.1

2.5 V LVCMOS 12 mA

1.8 V LVCMOS 8 mA

1.5 V LVCMOS 4 mA

3.3 V PCI

12 mA High –0.3

1.7

0.7

1.7

12 12

8 mA

4 mA

High –0.3 0.35 * VCCI 0.65 * VCCI 1.9

0.45

VCCI – 0.45

8

4

8

4

High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI

Per PCI specifications

3.3 V PCI-X

Per PCI-X specifications

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the

equivalent software default drive strength. These values are for normal ranges only.

2. Currents are measured at 125°C junction temperature.

3. Output slew rate can be extracted using the IBIS Models.

4. Output drive strength is below JEDEC specification.

5. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

Revision 5

2-23

Military ProASIC3/EL DC and Switching Characteristics

Table 2-28 • Summary of Maximum and Minimum DC Input Levels

Applicable to Military Conditions

Military¹

2

3

I_IL

I_IH

DC I/O Standard

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS⁴

1.2 V LVCMOS Wide Range⁴

3.3 V PCI

µA

15

µA

15

3.3 V PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

1. Military temperature range: –55°C to 125°C.

2.

I

is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

IL

3.

is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

IH

larger when operating outside recommended ranges.

4. Applicable to Military A3PE600L and A3PE3000L devices operating at VCCI ≥ VCC.

2-24

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-29 • Summary of AC Measuring Points

Input/Output

Input Reference

Board Termination

Measuring Trip

Point (Vtrip)

Standard

Supply Voltage Voltage (VREF_TYP) Voltage (VTT_REF)

3.3 V LVTTL /

3.30 V

–

1.4 V

3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

3.30 V

2.50 V

1.80 V

1.50 V

1.20 V

3.30 V

2.50 V

3.30 V

2.50 V

1.50 V

3.30 V

2.50 V

3.30 V

–

1.4 V

1.2 V

–

1.8 V LVCMOS

–

0.90 V

1.5 V LVCMOS

–

0.75 V

1.2 V LVCMOS*

–

0.6 V

1.2 V LVCMOS Wide Range*

3.3 V PCI

–

0.6 V

–

0.285 * VCCI (RR)

0.615 * VCCI (FF))

0.285 * VCCI (RR)

0.615 * VCCI (FF)

VREF

–

3.3 V PCI-X

–

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

0.8 V

1.0 V

0.75 V

1.25 V

1.5 V

–

1.2 V

1.5 V

0.75 V

1.25 V

1.485 V

–

VREF

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

VREF

Cross point

LVPECL

–

Note: *Applicable to A3PE600L and A3PE3000L devices operating at 1.2 V core regions only.

Table 2-30 • I/O AC Parameter Definitions

Parameter

t_DP

Parameter Definition

Data to Pad delay through the Output Buffer

t_PY

Pad to Data delay through the Input Buffer

t_DOUT

t_EOUT

t_DIN

Data to Output Buffer delay through the I/O interface

Enable to Output Buffer Tristate Control delay through the I/O interface

Input Buffer to Data delay through the I/O interface

t_HZ

Enable to Pad delay through the Output Buffer—High to Z

Enable to Pad delay through the Output Buffer—Z to High

Enable to Pad delay through the Output Buffer—Low to Z

Enable to Pad delay through the Output Buffer—Z to Low

Enable to Pad delay through the Output Buffer with delayed enable—Z to High

Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

t_ZH

t_LZ

t_ZL

t_ZHS

t_ZLS

Revision 5

2-25

Military ProASIC3/EL DC and Switching Characteristics

1.2 V Core Operating Voltage

Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Military-Case Conditions: T_J= 125°C, Worst Case VCC = 1.14 V, Worst Case

VCCI

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High

5

–

0.68 2.09 0.05 1.49 2.03 0.44 2.12 1.56 2.76 3.06 3.99 3.43

0.68 3.01 0.04 1.86 2.69 0.44 3.01 2.22 4.03 4.42 4.89 4.09

3.3 V LVCMOS 100 µA 12 mA High

Wide Range³

2.5 V LVCMOS 12 mA 12 mA High

1.8 V LVCMOS 12 mA 12 mA High

1.5 V LVCMOS 12 mA 12 mA High

5

–

0.68 2.12 0.04 1.73 2.17 0.44 2.15 1.74 2.84 2.95 4.03 3.62

0.68 2.36 0.05 1.70 2.40 0.44 2.40 1.94 3.16 3.58 4.27 3.81

0.68 2.71 0.04 1.86 2.61 0.44 2.76 2.24 3.34 3.69 4.63 4.12

0.68 4.39 0.04 2.25 3.19 0.44 4.24 3.74 4.34 4.09 6.11 5.61

1.2 V LVCMOS

2 mA

2 mA High

1.2 V LVCOMS 100 µA

Wide Range⁴

3.3 V PCI

Per PCI

spec

–

High 10 25⁵0.68 2.37 0.04 2.31 3.13 0.44 2.40 1.68 2.77 3.06 4.28 3.56

3.3 V PCI-X

Per PCI-X

spec

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20 mA⁶20 mA⁶High 10 25 0.68 1.75 0.05 1.99

20 mA⁶20 mA⁶High 10 25 0.68 1.79 0.05 1.93

35 mA 35 mA High 10 25 0.68 1.74 0.05 1.99

33 mA 33 mA High 10 25 0.68 1.86 0.05 1.93

–

0.44 1.71 1.75

0.44 1.82 1.79

0.44 1.76 1.73

0.44 1.89 1.77

0.44 2.73 2.65

0.44 2.59 2.28

0.44 1.82 1.55

0.44 1.86 1.49

0.44 1.98 1.55

0.44 1.77 1.41

–

3.59 3.62

3.70 3.67

3.64 3.61

3.77 3.64

4.60 4.52

4.47 4.16

1.82 1.55

1.86 1.49

1.98 1.55

1.77 1.41

8 mA

8 mA High 20 25 0.68 2.68 0.05 2.34

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

15 mA⁶15 mA⁶High 20 50 0.68 2.55 0.05 2.34

15 mA 15 mA High 30 25 0.68 1.80 0.05 1.78

15 mA 15 mA High 30 50 0.68 1.83 0.05 1.78

14 mA 14 mA High 30 25 0.68 1.95 0.05 1.71

21 mA 21 mA High 30 50 0.68 1.75 0.05 1.71

24 mA

–

High

–

0.68 1.59 0.05 2.11

0.68 1.51 0.05 1.84

–

LVPECL

Notes:

1. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range are applicable to 100 µA drive strength only. The configuration

will not operate at the equivalent software default drive strength. These values are for normal ranges only.

2. Output delays provided in this table were extracted with an output load indicated in the Capacitive Load column. For a

specific output load, refer to Designer software.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

5. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-14 on page 2-71 for

connectivity. This resistor is not required during normal operation.

6. Output drive strength is below JEDEC specification.

7. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-26

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

1.5 V Core Voltage

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst Case VCCI

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Standard

3.3 V LVTTL / 12 mA 12 mA High

3.3 V LVCMOS

5

–

0.52 1.97 0.03 1.23 1.78 0.34 1.99 1.46 2.63 2.89 3.23 2.71

0.52 2.89 0.03 1.61 2.44 0.34 2.88 2.12 3.89 4.25 4.12 3.36

3.3 V LVCOMS 100 µA 12 mA High

Wide Range³

2.5 V LVCMOS 12 mA 12 mA High

1.8 V LVCMOS 12 mA 12 mA High

1.5 V LVCMOS 12 mA 12 mA High

5

–

0.52 2.01 0.03 1.49 1.93 0.34 2.02 1.65 2.71 2.78 3.27 2.89

0.52 2.24 0.03 1.44 2.14 0.34 2.26 1.84 3.02 3.41 3.51 3.08

0.52 2.60 0.03 1.60 2.35 0.34 2.62 2.14 3.21 3.52 3.87 3.39

3.3 V PCI

Per PCI

spec

–

High 10 25⁴0.52 2.25 0.03 2.03 2.88 0.34 2.27 1.58 2.64 2.89 3.52 2.83

3.3 V PCI-X

Per PCI-X

spec

–

High 10 25⁴0.52 2.25 0.03 2.03 2.88 0.34 2.27 1.58 2.64 2.89 3.52 2.83

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20 mA⁵20 mA⁵High 10 25 0.52 1.68 0.03 1.79

20 mA⁵20 mA⁵High 10 25 0.52 1.72 0.03 1.73

35 mA 35 mA High 10 25 0.52 1.66 0.03 1.79

33 mA 33 mA High 10 25 0.52 1.75 0.03 1.73

–

0.34 1.58 1.68

0.34 1.69 1.72

0.34 1.63 1.66

0.34 1.76 1.69

0.34 2.59 2.55

0.34 2.46 2.19

034 1.69 1.46

0.34 1.73 1.39

0.34 1.84 1.45

0.34 1.64 1.31

–

2.83 2.92

2.93 2.97

2.88 2.90

3.00 2.94

3.84 3.79

3.71 3.43

1.69 1.46

1.73 1.39

1.84 1.45

1.64 1.31

8 mA

8 mA High 20 25 0.52 2.57 0.03 2.14

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

15 mA⁵15 mA⁵High 20 50 0.52 2.44 0.03 2.14

15 mA 15 mA High 30 25 0.52 1.68 0.03 1.58

18 mA 18 mA High 30 50 0.52 1.72 0.03 1.58

14 mA 14 mA High 30 25 0.52 1.83 0.03 1.51

21 mA 21 mA High 30 50 0.52 1.63 0.03 1.51

24 mA

–

High

–

0.52 1.48 0.03 1.86

0.52 1.40 0.03 1.61

–

LVPECL

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the

equivalent software default drive strength. These values are for normal ranges only.

2. Output delays provided in this table were extracted with an output load indicated in the Capacitive Load column. For a

specific output load, refer to Designer software.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-14 on page 2-71 for

connectivity. This resistor is not required during normal operation.

5. Output drive strength is below JEDEC specification.

6. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 5

2-27

Military ProASIC3/EL DC and Switching Characteristics

Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Military-Case Conditions: TJ = 125°C, Worst Case VCC = 1.425 V,

Worst Case VCCI

Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA

12 mA High

5

–

0.54 2.24 0.04 0.95 0.39 2.28 1.70 3.00 3.35 4.38 3.79

0.54 3.47 0.04 1.44 0.39 3.47 2.57 4.65 5.18 6.64 5.75

3.3 V LVCMOS 100 µA

Wide Range³

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

12 mA

12 mA High

5

–

0.54 2.26 0.04 1.23 0.39 2.30 1.89 3.09 3.22 4.39 3.99

0.54 2.49 0.04 1.14 0.39 2.54 2.12 3.46 3.82 4.63 4.21

0.54 2.85 0.04 1.35 0.39 2.90 2.45 3.69 3.93 4.99 4.55

Per PCI

spec.

High 10 25⁴0.54 2.51 0.04 0.81 0.39 2.55 1.83 3.00 3.35 4.65 3.92

3.3 V PCI-X

Per PCI-X

spec.

High 10 25 ⁴0.54 2.51 0.04 0.78 0.39 2.55 1.83 3.00 3.35 4.65 3.92

LVDS

24 mA

High

–

0.54 1.76 0.04 1.55

0.54 1.68 0.04 1.31

–

LVPECL

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the

equivalent software default drive strength. These values are for normal ranges only.

2. Output delays provided in this table were extracted with an output load indicated in the Capacitive Load column. For a

specific output load, refer to Designer software. Software default load is higher.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-14 on page 2-71 for

connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

2-28

Revision 5

Military ProASIC3/EL Low Power Flash FPGAs

Table 2-34 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Military-Case Conditions: TJ = 125°C, Worst Case VCC = 1.425 V,

Worst Case VCCI

Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA

12 mA High

5

–

0.54 1.90 0.04 0.94 0.39 1.94 1.47 2.61 3.01 4.03 3.56

0.54 2.94 0.04 1.42 0.39 2.94 2.22 4.03 4.66 6.12 5.40

3.3 V LVCMOS

Wide Range³

100 µA

–

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

12 mA

8 mA

4 mA

12 mA High

8 mA High

4 mA High

5

–

0.54 1.94 0.04 1.21 0.39 1.97 1.62 2.64 2.91 4.07 3.71

0.54 2.62 0.04 1.33 0.39 2.67 2.23 2.84 2.93 4.77 4.32

Per PCI

spec.

–

High 10 25 ⁴0.54 2.16 0.04 0.80 0.39 2.20 1.60 2.61 3.01 4.29 3.69

3.3 V PCI-X

Per PCI-X

spec.

–

High 10 25 ⁴0.54 2.16 0.04 0.78 0.39 2.20 1.60 2.61 3.01 4.29 3.69