A3P030-CSG100YPP_技术文档

1 – ProASIC3 Device Family Overview

General Description

ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and

features beyond those of the ProASIC^PLUS®family. Nonvolatile flash technology gives ProASIC3 devices

the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3 is

reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable

designers to create high-density systems using existing ASIC or FPGA design flows and tools.

ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030

devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported

with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.

ProASIC3 devices support the ARM Cortex-M1 processor. The ARM-enabled devices have Microsemi

ordering numbers that begin with M1A3P (Cortex-M1) and do not support AES decryption.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-

based FPGAs, flash-based ProASIC3 devices allow all functionality to be Instant On; no external boot

PROM is required. On-board security mechanisms prevent access to all the programming information

and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system

reprogramming to support future design iterations and field upgrades with confidence that valuable

intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the

industry-standard AES algorithm. The ProASIC3 family device architecture mitigates the need for ASIC

migration at higher user volumes. This makes the ProASIC3 family a cost-effective ASIC replacement

solution, especially for applications in the consumer, networking/ communications, computing, and

avionics markets.

Security

The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock, which provides a

unique combination of reprogrammability and design security without external overhead, advantages that

only an FPGA with nonvolatile flash programming can offer.

ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level

of protection in the FPGA industry for intellectual property and configuration data. In addition, all

FlashROM data in ProASIC3 devices can be encrypted prior to loading, using the industry-leading

AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National

Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3

devices have a built-in AES decryption engine and a flash-based AES key that make them the most

comprehensive programmable logic device security solution available today. ProASIC3 devices with

AES-based security provide a high level of protection for remote field updates over public networks such

as the Internet, and are designed to ensure that valuable IP remains out of the hands of system

overbuilders, system cloners, and IP thieves.

ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the

ARM core must be protected at all times, AES encryption is always on for the core logic, so bitstreams

are always encrypted. There is no user access to encryption for the FlashROM programming data.

Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The flash cells are

located beneath seven metal layers, and many device design and layout techniques have been used to

make invasive attacks extremely difficult. The ProASIC3 family, with FlashLock and AES security, is

unique in being highly resistant to both invasive and noninvasive attacks.

Revision 13

1-1

ProASIC3 Device Family Overview

Your valuable IP is protected with industry-standard security, making remote ISP possible. A ProASIC3

device provides the best available security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the

configuration data is an inherent part of the FPGA structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 FPGAs

do not require system configuration components such as EEPROMs or microcontrollers to load device

configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system

reliability.

Instant On

Flash-based ProASIC3 devices support Level 0 of the Instant On classification standard. This feature

helps in system component initialization, execution of critical tasks before the processor wakes up, setup

and configuration of memory blocks, clock generation, and bus activity management. The Instant On

feature of flash-based ProASIC3 devices greatly simplifies total system design and reduces total system

cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these purposes in

a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3 device's

flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when

system power is restored. This enables the reduction or complete removal of the configuration PROM,

expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-

based ProASIC3 devices simplify total system design and reduce cost and design risk while increasing

system reliability and improving system initialization time.

Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike

a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These

errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 flash-based

FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 FPGAs cannot be

altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in

the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and

correction (EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based ProASIC3 devices exhibit power characteristics similar to an ASIC, making them an ideal

choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current

surge and no high-current transition period, both of which occur on many FPGAs.

ProASIC3 devices also have low dynamic power consumption to further maximize power savings.

1-2

Revision 13

ProASIC3 Flash Family FPGAs

Advanced Flash Technology

The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through an

advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization

without compromising device routability or performance. Logic functions within the device are

interconnected through a four-level routing hierarchy.

Advanced Architecture

The proprietary ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The

ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1 and

Figure 1-2 on page 1-4):

•

FPGA VersaTiles

Dedicated FlashROM

Dedicated SRAM/FIFO memory^†

Extensive CCCs and PLLs^†

Advanced I/O structure

Bank 0

CCC

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block*

I/Os

VersaTile

ISP AES

Decryption*

User Nonvolatile

FlashROM

Charge Pumps

Bank 1

Note: *Not supported by A3P015 and A3P030 devices

Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks (A3P015, A3P030, A3P060, and

A3P125)

† The A3P015 and A3P030 do not support PLL or SRAM.

Revision 13

1-3

ProASIC3 Device Family Overview

Bank 0

CCC

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

I/Os

VersaTile

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

(A3P600 and A3P1000)

ISP AES

Decryption

User Nonvolatile

FlashROM

Charge Pumps

Bank 2

Figure 1-2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000)

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic

function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch

interconnections. The versatility of the ProASIC3 core tile as either a three-input lookup table (LUT)

equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile

capability is unique to the Microsemi ProASIC family of third-generation architecture flash FPGAs.

VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed

throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core

utilization is possible for virtually any design.

VersaTiles

The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASIC^PLUS®core

tiles. The ProASIC3 VersaTile supports the following:

•

All 3-input logic functions—LUT-3 equivalent

Latch with clear or set

D-flip-flop with clear or set

Enable D-flip-flop with clear or set

Refer to Figure 1-3 for VersaTile configurations.

Enable D-Flip-Flop w ith Clear or Set

D-Flip-Flop w ith Clear or Set

LUT-3 Equivalent

X1

Data

Y

Data

CLK

CLR

Y

X2

X3

LUT-3

Y

D-FF

CLK

D-FF

Enable

CLR

Figure 1-3 • VersaTile Configurations

1-4

Revision 13

ProASIC3 Flash Family FPGAs

User Nonvolatile FlashROM

ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can

be used in diverse system applications:

•

Internet protocol addressing (wireless or fixed)

System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, set-top boxes)

Secure key storage for secure communications algorithms

Asset management/tracking

Date stamping

Version management

The FlashROM is written using the standard ProASIC3 IEEE 1532 JTAG programming interface. The

core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks (except in the A3P015 and A3P030 devices), as in

security keys stored in the FlashROM for a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be read

back either through the JTAG programming interface or via direct FPGA core addressing. Note that the

FlashROM can only be programmed from the JTAG interface and cannot be programmed from the

internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte

basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks

and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the

FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM

address define the byte.

The ProASIC3 development software solutions, Libero^®System-on-Chip (SoC) and Designer, have

extensive support for the FlashROM. One such feature is auto-generation of sequential programming

files for applications requiring a unique serial number in each part. Another feature allows the inclusion of

static data for system version control. Data for the FlashROM can be generated quickly and easily using

Libero SoC and Designer software tools. Comprehensive programming file support is also included to

allow for easy programming of large numbers of parts with differing FlashROM contents.

SRAM and FIFO

ProASIC3 devices (except the A3P015 and A3P030 devices) have embedded SRAM blocks along their

north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory

configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent

read and write ports that can be configured with different bit widths on each port. For example, data can

be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be

initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in A3P015

and A3P030 devices).

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width

and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and

Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control

unit contains the counters necessary for generation of the read and write address pointers. The

embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member of

the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P015 and

A3P030 devices do not have a PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides.

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay

operations as well as clock spine access.

Revision 13

1-5

ProASIC3 Device Family Overview

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

•

Wide input frequency range (f_{IN_CCC}) = 1.5 MHz to 350 MHz

Output frequency range (f_{OUT_CCC}) = 0.75 MHz to 350 MHz

Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns

2 programmable delay types for clock skew minimization

Clock frequency synthesis (for PLL only)

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration (for PLL only).

•

Output duty cycle = 50% ± 1.5% or better (for PLL only)

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used (for PLL only)

•

Maximum acquisition time = 300 µs (for PLL only)

Low power consumption of 5 mW

Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns (for PLL only)

Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /

f

_{OUT_CCC}) (for PLL only)

Global Clocking

ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL

support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high fanout nets.

1-6

Revision 13

ProASIC3 Flash Family FPGAs

I/Os with Advanced I/O Standards

The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V,

1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards—single-ended and

differential.

The I/Os are organized into banks, with two or four banks per device. The configuration of these banks

determines the I/O standards supported (Table 1-1).

Table 1-1 • I/O Standards Supported

I/O Standards Supported

LVTTL/

LVPECL, LVDS,

I/O Bank Type

Device and Bank Location

LVCMOS PCI/PCI-X B-LVDS, M-LVDS

Advanced

East and west Banks of A3P250 and

larger devices



Standard Plus

Standard

North and south banks of A3P250 and

larger devices

Not supported

All banks of A3P060 and A3P125

All banks of A3P015 and A3P030

Not

supported

Not supported



Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

•

Single-Data-Rate applications

Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications

ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS.

B-LVDS and M-LVDS can support up to 20 loads.

Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card

in a powered-up system.

Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed

when the system is powered up, while the component itself is powered down, or when power supplies

are floating.

Wide Range I/O Support

ProASIC3 devices support JEDEC-defined wide range I/O operation. ProASIC3 supports the JESD8-B

specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V.

Wider I/O range means designers can eliminate power supplies or power conditioning components from

the board or move to less costly components with greater tolerances. Wide range eases I/O bank

management and provides enhanced protection from system voltage spikes, while providing the flexibility

to easily run custom voltage applications.

Specifying I/O States During Programming

You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for

PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.

Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have

limited display of Pin Numbers only.

1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during

programming.

2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator

window appears.

3. Click the Specify I/O States During Programming button to display the Specify I/O States During

Programming dialog box.

Revision 13

1-7

ProASIC3 Device Family Overview

4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.

Select the I/Os you wish to modify (Figure 1-4 on page 1-8).

5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings

for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state

settings:

1 – I/O is set to drive out logic High

0 – I/O is set to drive out logic Low

Last Known State – I/O is set to the last value that was driven out prior to entering the

programming mode, and then held at that value during programming

Z -Tristate: I/O is tristated

Figure 1-4 • I/O States During Programming Window

6. Click OK to return to the FlashPoint – Programming File Generator window.

Note: I/O States During programming are saved to the ADB and resulting programming files after

completing programming file generation.

1-8

Revision 13

2 – ProASIC3 DC and Switching Characteristics

General Specifications

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any

other conditions beyond those listed under the Recommended Operating Conditions specified in

Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol

VCC

Parameter

DC core supply voltage

JTAG DC voltage

Limits

Units

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

V

VJTAG

VPUMP Programming voltage

VCCPLL Analog power supply (PLL)

VCCI

VMV

VI

DC I/O output buffer supply voltage

DC I/O input buffer supply voltage

I/O input voltage

–0.3 V to 3.6 V

(when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-insertion mode is disabled)

2

T_STG

Storage temperature

Junction temperature

–65 to +150

+125

°C

2

T_J

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on

page 3-1 for further information.

3. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating

limits, refer to Table 2-2 on page 2-2.

Revision 13

2-1

ProASIC3 DC and Switching Characteristics

Table 2-2 • Recommended Operating Conditions ^1,2

Symbol

T_A

Parameters ¹

Commercial

0 to +70

Industrial

-40 to +85

-40 to 100

1.425 to 1.575

1.4 to 3.6

Units

°C

V

Ambient temperature

T_J

Junction temperature

1.5 V DC core supply voltage

JTAG DC voltage

0 to 85

VCC³

VJTAG

VPUMP

1.425 to 1.575

1.4 to 3.6

V

Programming voltage

Programming Mode ⁴

Operation ⁵

3.15 to 3.45

0 to 3.6

3.15 to 3.45

0 to 3.6

V

VCCPLL

Analog power supply (PLL)

1.425 to 1.575

1.7 to 1.9

1.425 to 1.575

1.7 to 1.9

V

VCCI and VMV ⁶1.5 V DC supply voltage

V

1.8 V DC supply voltage

V

2.5 V DC supply voltage

2.3 to 2.7

V

3.3 V DC supply voltage

3.0 to 3.6

V

3.3 V wide range DC supply voltage ⁷

LVDS/B-LVDS/M-LVDS differential I/O

LVPECL differential I/O

2.7 to 3.6

V

2.375 to 2.625

3.0 to 3.6

2.375 to 2.625

3.0 to 3.6

V

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi

recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.

3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-18 on page 2-18.

4. The programming temperature range supported is T

= 0°C to 85°C.

ambient

5. VPUMP can be left floating during operation (not programming mode).

6. VMV and VCCI should be at the same voltage within a given I/O bank. VMV pins must be connected to the

corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information.

7. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.

Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature¹

Product

Grade

Programming Program Retention

Maximum Storage

Maximum Operating

Cycles

(biased/unbiased) Temperature T_STG(°C) ²Junction Temperature T_J(°C) ²

Commercial

Industrial

Notes:

500

20 years

110

100

500

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

2-2

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-4 • Overshoot and Undershoot Limits ¹

Average VCCI–GND Overshoot or Undershoot

Maximum Overshoot/

Undershoot²

VCCI and VMV

Duration as a Percentage of Clock Cycle²

2.7 V or less

10%

5%

1.4 V

1.49 V

1.1 V

3 V

10%

5%

1.19 V

0.79 V

0.88 V

0.45 V

0.54 V

3.3 V

3.6 V

Notes:

10%

5%

10%

5%

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC^®3 device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-4.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

•

During programming, I/Os become tristated and weakly pulled up to VCCI.

JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout

activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4

for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25

V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down

Behavior of Low Power Flash Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for

information on clock and lock recovery.

Revision 13

2-3

ProASIC3 DC and Switching Characteristics

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

(except differential

and timer specifications for

speed, VIH / VIL, VOH / VOL,

etc.

but slower because VCCI

is below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.425 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

I/Os are functional (except differential inputs)

but slower because VCCI / VCC are below

specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Activation trip point:

V

= 0.85 V ± 0.25 V

a

Deactivation trip point:

= 0.75 V ± 0.25 V

Region 1: I/O buffers are OFF

V

d

VCCI

Activation trip point:

= 0.9 V ± 0.3 V

Min VCCI datasheet specification

V

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

a

Deactivation trip point:

= 0.8 V ± 0.3 V

V

d

Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels

Thermal Characteristics

Introduction

The temperature variable in the Microsemi Designer software refers to the junction temperature, not the

ambient temperature. This is an important distinction because dynamic and static power consumption

cause the chip junction to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

T_J= Junction Temperature = T + T_A

EQ 1

where:

T_A= Ambient Temperature

T = Temperature gradient between junction (silicon) and ambient T = _ja* P

_ja= Junction-to-ambient of the package. _janumbers are located in Table 2-5.

P = Power dissipation

2-4

Revision 13

ProASIC3 Flash Family FPGAs

Package Thermal Characteristics

The device junction-to-case thermal resistivity is _jcand the junction-to-ambient air thermal resistivity is

_ja. The thermal characteristics for _jaare shown for two air flow rates. The absolute maximum junction

temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation

allowed for a 484-pin FBGA package at commercial temperature and in still air.

Max. junction temp. (C) – Max. ambient temp. (C) 100C – 70C

·

------------------------------------------------------------------------------------------------------------------------------------------ -------------------------------------

= 1.463 W

Maximum Power Allowed =

=

_ja(C/W)

20.5C/W

EQ 2

Table 2-5 • Package Thermal Resistivities

_ja

Package Type

Device

Pin Count _jcStill Air 200 ft./min. 500 ft./min. Units

Quad Flat No Lead

A3P030

A3P060

132

100

144

208

144

256

484

144

256

484

0.4

0.3

0.2

0.1

10.0

11.0

8.0

3.8

3.2

6.3

6.6

8.0

21.4

21.2

21.1

21.0

35.3

33.5

26.1

16.2

26.9

26.6

20.5

31.6

28.1

23.3

16.8

16.6

16.5

16.4

29.4

28.0

22.5

13.3

22.9

22.8

17.0

26.2

24.4

19.0

15.3

15.0

14.9

14.8

27.1

25.7

20.8

11.9

21.5

15.9

24.2

22.7

16.7

C/W

A3P125

A3P250

Very Thin Quad Flat Pack (VQFP)

Thin Quad Flat Pack (TQFP)

All devices

See note*

A3P1000

Plastic Quad Flat Pack (PQFP)

PQFP with embedded heatspreader

Fine Pitch Ball Grid Array (FBGA)

Note: *This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal

information will be available in future revisions of the datasheet.

Revision 13

2-5

ProASIC3 DC and Switching Characteristics

Temperature and Voltage Derating Factors

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 70°C, VCC = 1.425 V)

Junction Temperature (°C)

Array Voltage VCC

(V)

–40°C

0°C

0.93

0.88

0.84

25°C

0.95

0.90

0.87

70°C

1.00

0.95

0.91

85°C

1.02

0.96

0.93

100°C

1.04

1.425

1.500

1.575

0.88

0.83

0.98

0.80

0.94

Calculating Power Dissipation

Quiescent Supply Current

Table 2-7 • Quiescent Supply Current Characteristics

A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000

Typical (25°C)

2 mA

3 mA

20 mA

30 mA

5 mA

30 mA

45 mA

8 mA

50 mA

75 mA

Max. (Commercial)

Max. (Industrial)

10 mA 10 mA 10 mA 10 mA 20 mA

15 mA 15 mA 15 mA 15 mA 30 mA

Note: IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static

contribution, which is shown in Table 2-11 and Table 2-12 on page 2-8.

Power per I/O Pin

Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Applicable to Advanced I/O Banks

Static Power

P_DC2(mW) ¹

Dynamic Power

PAC9 (µW/MHz) ²

VMV (V)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range³

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

3.3

2.5

1.8

1.5

3.3

–

16.22

5.12

2.13

1.45

18.11

3.3 V PCI-X

Differential

LVDS

2.5

3.3

2.26

5.72

1.20

1.87

LVPECL

Notes:

1. PDC2 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VCC and VMV.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B

specification.

2-6

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks

Static Power

PDC2 (mW) ¹

Dynamic Power

PAC9 (µW/MHz) ²

VMV (V)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range³

2.5 V LVCMOS

3.3

2.5

1.8

1.5

3.3

–

16.23

5.14

1.8 V LVCMOS

2.13

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

1.48

18.13

3.3 V PCI-X

Notes:

1. PDC2 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VCC and VMV.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B

specification.

Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Applicable to Standard I/O Banks

Static Power

PDC2 (mW) ¹

Dynamic Power

PAC9 (µW/MHz) ²

VMV (V)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range³

2.5 V LVCMOS

3.3

2.5

1.8

1.5

–

17.24

5.19

1.8 V LVCMOS

2.18

1.5 V LVCMOS (JESD8-11)

Notes:

1.52

1. PDC2 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VCC and VMV.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B

specification.

Revision 13

2-7

ProASIC3 DC and Switching Characteristics

Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Advanced I/O Banks

Static Power

Dynamic Power

C_LOAD(pF)

VCCI (V)

PDC3 (mW)²

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range⁴

2.5 V LVCMOS

35

3.3

2.5

1.8

1.5

–

468.67

267.48

149.46

103.12

1.8 V LVCMOS

1.5 V LVCMOS

(JESD8-11)

3.3 V PCI

3.3 V PCI-X

Differential

LVDS

10

3.3

–

201.02

–

2.5

3.3

7.74

88.92

LVPECL

Notes:

19.54

166.52

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC3 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCC and VCCI.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

Table 2-12 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings¹

Applicable to Standard Plus I/O Banks

Static Power

PDC3 (mW)²

Dynamic Power

C_LOAD(pF)

VCCI (V)

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range⁴

2.5 V LVCMOS

35

10

3.3

2.5

1.8

1.5

3.3

–

452.67

258.32

133.59

92.84

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

184.92

3.3 V PCI-X

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2.

P

is the static power (where applicable) measured on VMV.

DC3

3.

P

is the total dynamic power measured on VCC and VMV.

AC10

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

2-8

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings ¹

Applicable to Standard I/O Banks

Static Power

PDC3 (mW) ²

Dynamic Power

C_LOAD(pF)

VCCI (V)

PAC10 (µW/MHz) ³

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range⁴

2.5 V LVCMOS

35

3.3

2.5

1.8

1.5

–

431.08

247.36

128.46

89.46

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2.

3.

P

is the static power (where applicable) measured on VCCI.

is the total dynamic power measured on VCC and VCCI.

DC3

P

AC10

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

Revision 13

2-9

ProASIC3 DC and Switching Characteristics

Power Consumption of Various Internal Resources

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices

Device Specific Dynamic Contributions

(µW/MHz)

Parameter

PAC1

Definition

Clock contribution of a Global Rib

Clock contribution of a Global Spine

Clock contribution of a VersaTile row

14.50 12.80 12.80 11.00 11.00 9.30 9.30 9.30

PAC2

2.48 1.85 1.35 1.58 0.81 0.81 0.41 0.41

PAC3

0.81

0.12

PAC4

Clock contribution of a VersaTile used as a

sequential module

PAC5

PAC6

PAC7

First contribution of a VersaTile used as a

sequential module

0.07

0.29

0.70

Second contribution of a VersaTile used as a

sequential module

Contribution of a VersaTile used as a

combinatorial Module

PAC8

PAC9

Average contribution of a routing net

Contribution of an I/O input pin (standard

dependent)

See Table 2-8 on page 2-6 through

Table 2-10 on page 2-7.

PAC10

PAC11

PAC12

PAC13

Contribution of an I/O output pin (standard

dependent)

See Table 2-11 on page 2-8 through

Table 2-13 on page 2-9.

Average contribution of a RAM block during a

read operation

25.00

30.00

2.60

Average contribution of a RAM block during a

write operation

Dynamic contribution for PLL

Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power

spreadsheet calculator or SmartPower tool in Libero SoC software.

2-10

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-15 • Different Components Contributing to the Static Power Consumption in ProASIC3 Devices

Definition

Device Specific Static Power (mW)

Parameter

PDC1

Array static power in Active mode

See Table 2-7 on page 2-6.

PDC2

I/O input pin static power (standard-dependent)

See Table 2-8 on page 2-6 through

Table 2-10 on page 2-7.

PDC3

I/O output pin static power (standard-dependent)

See Table 2-11 on page 2-8 through

Table 2-13 on page 2-9.

PDC4

PDC5

Static PLL contribution

2.55 mW

Bank quiescent power (VCCI-dependent)

See Table 2-7 on page 2-6.

Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power

spreadsheet calculator or SmartPower tool in Libero SoC software.

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock generated

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-16 on

page 2-13.

•

Enable rates of output buffers—guidelines are provided for typical applications in Table 2-17 on

page 2-13.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-17 on page 2-13. The calculation should be repeated for each clock domain defined in the

design.

Methodology

Total Power Consumption—P

TOTAL

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

P_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

STAT

P_STAT= P_DC1+ N_INPUTS* P_DC2+ N_OUTPUTS* P_DC3

N_INPUTSis the number of I/O input buffers used in the design.

N_OUTPUTSis the number of I/O output buffers used in the design.

Revision 13

2-11

ProASIC3 DC and Switching Characteristics

Total Dynamic Power Consumption—P

DYN

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL

Global Clock Contribution—P

CLOCK

P_CLOCK= (P_AC1+ N_SPINE*P_AC2+ N_ROW*P_AC3+ N_S-CELL* P_AC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided in the

"Spine Architecture" section of the Global Resources chapter in the ProASIC3 FPGA

Fabric User's Guide.

N_ROWis the number of VersaTile rows used in the design—guidelines are provided in the "Spine

Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric

User's Guide.

F_CLKis the global clock signal frequency.

N

_S-CELLis the number of VersaTiles used as sequential modules in the design.

_AC1, P_AC2, P_AC3, and P_AC4are device-dependent.

Sequential Cells Contribution—P

P

S-CELL

P_S-CELL= N_S-CELL* (P_AC5+ ₁/ 2 * P_AC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a multi-tile

sequential cell is used, it should be accounted for as 1.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.

F_CLKis the global clock signal frequency.

Combinatorial Cells Contribution—P

C-CELL

P_C-CELL= N_C-CELL* ₁/ 2 * P_AC7* F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.

F_CLKis the global clock signal frequency.

Routing Net Contribution—P

NET

P_NET= (N_S-CELL+ N_C-CELL) * ₁/ 2 * P_AC8* F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

N

_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.

_CLKis the global clock signal frequency.

I/O Input Buffer Contribution—P

F

INPUTS

P_INPUTS= N_INPUTS* ₂/ 2 * P_AC9* F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-13.

F_CLKis the global clock signal frequency.

I/O Output Buffer Contribution—P

OUTPUTS

P_OUTPUTS= N_OUTPUTS* ₂/ 2 * ₁* P_AC10* F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-13.

₁is the I/O buffer enable rate—guidelines are provided in Table 2-17 on page 2-13.

F_CLKis the global clock signal frequency.

2-12

Revision 13

ProASIC3 Flash Family FPGAs

RAM Contribution—P

MEMORY

P_MEMORY= P_AC11* N_BLOCKS* F_READ-CLOCK* ₂+ P_AC12* N_BLOCK* F_WRITE-CLOCK* ₃

N_BLOCKSis the number of RAM blocks used in the design.

F

_READ-CLOCKis the memory read clock frequency.

₂is the RAM enable rate for read operations.

_WRITE-CLOCKis the memory write clock frequency.

₃is the RAM enable rate for write operations—guidelines are provided in Table 2-17 on page 2-13.

PLL Contribution—P

F

PLL

P_PLL= P_DC4+ P_AC13*F_CLKOUT

F_CLKOUTis the output clock frequency.¹

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are

some examples:

•

The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the

clock frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1

Bit 2

…

= 50%

= 25%

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

nontristate output buffers are used, the enable rate should be 100%.

Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

₁

₂

10%

Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

₁

₂

₃

RAM enable rate for read operations

RAM enable rate for write operations

12.5%

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the

PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output

clock in the formula by adding its corresponding contribution (P_AC14* F_CLKOUTproduct) to the total PLL contribution.

Revision 13

2-13

ProASIC3 DC and Switching Characteristics

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

Y

LVPECL (Applicable to

Advanced I/O Banks Only)L

Y

t_PD= 0.56 ns

t_PD= 0.49 ns

t_DP= 1.34 ns

I/O Module

(Non-Registered)

Combinational Cell

Y

Output drive strength = 12 mA

High slew rate

LVTTL

t_DP= 2.64 ns (Advanced I/O Banks)

t_PD= 0.87 ns

I/O Module

(Non-Registered)

Combinational Cell

I/O Module

(Registered)

Y

Output drive strength = 8 mA

High slew rate

LVTTL

t

_PY= 1.05 ns

t_DP= 3.66 ns (Advanced I/O Banks)

LVPECL

(Applicable

to Advanced

I/O Banks only)

t_PD= 0.47 ns

I/O Module

(Non-Registered)

D

Q

Combinational Cell

Y

Output drive strength = 4 mA

LVCMOS 1.5 V

High slew rate

t

_ICLKQ= 0.24 ns

t

_DP= 3.97 ns (Advanced I/O Banks)

t_PD= 0.47 ns

t_ISUD= 0.26 ns

Input LVTTL

Clock

I/O Module

(Registered)

Register Cell

Combinational Cell

t

_PY= 0.76 ns (Advanced I/O Banks)

Y

D

Q

D

Q

D

Q

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

I/O Module

(Non-Registered)

t_PD= 0.47 ns

t_DP= 2.64 ns

(Advanced I/O Banks)

t_CLKQ= 0.55 ns

_SUD= 0.43 ns

t

_OCLKQ= 0.59 ns

_OSUD= 0.31 ns

t

_CLKQ= 0.55 ns

LVDS,

BLVDS,

M-LVDS

t

t_SUD= 0.43 ns

Input LVTTL

Clock

Input LVTTL

Clock

(Applicable for

Advanced I/O

Banks only)

t_PY= 1.20 ns

t_PY= 0.76 ns

(Advanced I/O Banks)

Figure 2-2 • Timing Model

Operating Conditions: –2 Speed, Commercial Temperature Range (T_J= 70°C), Worst Case

VCC = 1.425 V

2-14

Revision 13

ProASIC3 Flash Family FPGAs

t_PY

t_DIN

D

Q

PAD

DIN

Y

CLK

To Array

I/O Interface

t

_PY= MAX(t_PY(R), t_PY(F))

_DIN= MAX(t_DIN(R), t_DIN(F))

VIH

V_trip

VIL

PAD

VCC

50%

Y

GND

t_PY

(R)

t_PY

(F)

VCC

50%

DIN

t_DIN

(R)

GND

t_DIN

(F)

Figure 2-3 • Input Buffer Timing Model and Delays (example)

Revision 13

2-15

ProASIC3 DC and Switching Characteristics

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

D

From Array

t_DP= MAX(t_DP(R), t_DP(F))

t_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t_DOUT

(R)

t_DOUT

(F)

VCC

50%

VCC

D

0 V

50%

DOUT

PAD

0 V

VOH

Vtrip

V_OL

Vtrip

t_DP

(R)

t_DP

(F)

Figure 2-4 • Output Buffer Model and Delays (example)

2-16

Revision 13

ProASIC3 Flash Family FPGAs

t

EOUT

D

Q

CLK

t

, t , t , t , t , t

E

ZL ZH HZ LZ ZLS ZHS

EOUT

D

Q

PAD

DOUT

CLK

D

t

= MAX(t

(r), t (f))

EOUT

I/O Interface

EOUT

VCC

D

E

VCC

50%

t

50%

t

EOUT (F)

EOUT (R)

VCC

50%

ZH

50%

t

LZ

EOUT

PAD

t

ZL

HZ

VCCI

90% VCCI

Vtrip

VOL

10% V

CCI

VCC

D

E

VCC

50%

t

EOUT (F)

EOUT (R)

VCC

50%

EOUT

PAD

50%

VOH

t

ZHS

t

ZLS

Vtrip

VOL

Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)

Revision 13

2-17

ProASIC3 DC and Switching Characteristics

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Advanced I/O Banks

Equiv.

Software

VIL

VIH

VOL

VOH

IOL¹IOH¹

Default

Drive

Drive Strength Slew Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

I/O Standard Strength Option²Rate

V

mA mA

3.3 V LVTTL / 12 mA

3.3 V

LVCMOS

12 mA High –0.3

0.8

2

3.6

2.7

0.4

2.4

12

3.3 V

100 µA

0.8

0.7

2

0.2

VCCI – 0.2 0.1 0.1

LVCMOS

Wide Range³

2.5 V

LVCMOS

12 mA

1.7

0.7

1.7

12

1.8 V

LVCMOS

12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9

0.45

VCCI – 0.45 12

1.5 V

12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI 12

LVCMOS

3.3 V PCI

3.3 V PCI-X

Notes:

Per PCI specifications

Per PCI-X specifications

1. Currents are measured at 85°C junction temperature.

2. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

2-18

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard Plus I/O Banks

Equiv.

Software

Default

IOH

1

VIL

VIH

VOL

VOH

IOL¹

Drive

Drive Strength Slew Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

I/O Standard Strength Option²Rate

V

mA mA

3.3 V LVTTL / 12 mA

3.3 V

LVCMOS

12 mA High –0.3

0.8

2

3.6

2.7

0.4

2.4

12 12

3.3 V

100 µA

0.8

0.7

2

0.2

VCCI – 0.2 0.1 0.1

LVCMOS

Wide Range³

2.5 V

LVCMOS

12 mA

8 mA

4 mA

1.7

0.7

1.7

12 12

1.8 V

LVCMOS

8 mA

4 mA

High –0.3 0.35 * VCCI 0.65 * VCCI 1.9

0.45

VCCI – 0.45

8

4

8

4

1.5 V

High –0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI

LVCMOS

3.3 V PCI

3.3 V PCI-X

Notes:

Per PCI specifications

Per PCI-X specifications

1. Currents are measured at 85°C junction temperature.

2. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

Revision 13

2-19

ProASIC3 DC and Switching Characteristics

Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard I/O Banks

Equiv.

Software

VIL

VIH

VOL

VOH

IOL¹IOH¹

Default

Drive

Drive Strength Slew Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

I/O Standard Strength Option²Rate

V

mA mA

3.3 V LVTTL / 8 mA

3.3 V

LVCMOS

8 mA

High –0.3

0.8

2

3.6

0.4

2.4

8

3.3 V

100 µA

8 mA

0.8

0.7

2

0.2

VCCI – 0.2 0.1 0.1

LVCMOS

Wide Range³

2.5 V

LVCMOS

8 mA

4 mA

2 mA

8 mA

4 mA

2 mA

1.7

0.7

1.7

8

4

2

8

4

2

1.8 V

LVCMOS

High –0.3 0.35 * VCCI 0.65 * VCCI 3.6

0.45

VCCI – 0.45

1.5 V

High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI

LVCMOS

Notes:

1. Currents are measured at 85°C junction temperature.

2. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT

operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

Table 2-21 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

Commercial¹

IIH⁴

Industrial²

IIL³

µA

10

IIL³

µA

15

IIH⁴

µA

15

DC I/O Standards

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

µA

10

3.3 V PCI-X

Notes:

1. Commercial range (0°C < T < 70°C)

A

2. Industrial range (–40°C < T < 85°C)

A

3. IIL is the input leakage current per I/O pin over recommended operation conditions where

–0.3V < V <V .

IN

IL

4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

2-20

Revision 13

ProASIC3 Flash Family FPGAs

Summary of I/O Timing Characteristics – Default I/O Software

Settings

Table 2-22 • Summary of AC Measuring Points

Standard

Measuring Trip Point (V_trip

)

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

1.4 V

1.2 V

1.8 V LVCMOS

0.90 V

1.5 V LVCMOS

0.75 V

3.3 V PCI

0.285 * VCCI (RR)

0.615 * VCCI (FF)

0.285 * VCCI (RR)

0.615 * VCCI (FF)

3.3 V PCI-X

Table 2-23 • I/O AC Parameter Definitions

Parameter

t_DP

Parameter Definition

Data to Pad delay through the Output Buffer

Pad to Data delay through the Input Buffer

t_PY

t_DOUT

t_EOUT

t_DIN

Data to Output Buffer delay through the I/O interface

Enable to Output Buffer Tristate Control delay through the I/O interface

Input Buffer to Data delay through the I/O interface

t_HZ

Enable to Pad delay through the Output Buffer—High to Z

Enable to Pad delay through the Output Buffer—Z to High

Enable to Pad delay through the Output Buffer—Low to Z

Enable to Pad delay through the Output Buffer—Z to Low

t_ZH

t_LZ

t_ZL

t_ZHS

t_ZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to High

Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

Revision 13

2-21

ProASIC3 DC and Switching Characteristics

Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case VCC = 1.425 V,

Worst-Case VCCI (per standard)

Advanced I/O Banks

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High 35

–

0.45 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns

0.45 4.08 0.03 0.76 0.32 4.08 3.20 3.71 4.14 6.61 5.74 ns

3.3 V LVCMOS 100 µA 12 mA High 35

Wide Range²

2.5 V LVCMOS 12 mA 12 mA High 35

1.8 V LVCMOS 12 mA 12 mA High 35

1.5 V LVCMOS 12 mA 12 mA High 35

–

0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns

0.45 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns

0.45 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns

3.3 V PCI

Per

PCI

–

High 10 25 ⁴0.45 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

spec

3.3 V PCI-X

Per

PCI-X

spec

–

High 10 25 ⁴0.45 2.00 0.03 0.62 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

LVDS

24 mA

–

High

–

0.45 1.37 0.03 1.20

0.45 1.34 0.03 1.05

–

ns

LVPECL

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-63 for

connectivity. This resistor is not required during normal operation.

2-22

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case VCC = 1.425 V,

Worst-Case VCCI (per standard)

Standard Plus I/O Banks

I/O Standard

3.3 V LVTTL / 12 mA 12 mA High 35

3.3 V LVCMOS

–

0.45 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns

0.45 3.65 0.03 1.14 0.32 3.65 2.93 3.22 3.72 6.18 5.46 ns

3.3 V LVCMOS 100 µA 12 mA High 35

Wide Range²

2.5 V LVCMOS 12 mA 12 mA High 35

1.8 V LVCMOS 8 mA 8 mA High 35

1.5 V LVCMOS 4 mA 4 mA High 35

–

0.45 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns

0.45 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns

0.45 3.61 0.03 1.06 0.32 3.35 3.61 2.26 2.34 5.02 5.28 ns

3.3 V PCI

3.3 V PCI-X

Notes:

Per

PCI

spec

–

High 10 25 ⁴0.45 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns

Per

PCI-X

spec

–

High 10 25 ⁴0.45 1.72 0.03 0.62 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-63 for

connectivity. This resistor is not required during normal operation.

Revision 13

2-23

ProASIC3 DC and Switching Characteristics

Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case VCC = 1.425 V,

Worst-Case VCCI (per standard)

Standard I/O Banks

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

8 mA 8 mA High

35

–

0.45 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns

0.45 5.09 0.03 1.13 0.32 5.09 4.25 2.77 3.11 ns

3.3 V LVCMOS 100 µA 8 mA High

Wide Range²

2.5 V LVCMOS 8 mA 8 mA High

1.8 V LVCMOS 4 mA 4 mA High

1.5 V LVCMOS 2 mA 2 mA High

Notes:

35

–

0.45 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns

0.45 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns

0.45 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-24

Revision 13

ProASIC3 Flash Family FPGAs

Detailed I/O DC Characteristics

Table 2-27 • Input Capacitance

Symbol

C_IN

Definition

Input capacitance

Input capacitance on the clock pin

Conditions

Min. Max. Units

VIN = 0, f = 1.0 MHz

8

pF

C_INCLK

Table 2-28 • I/O Output Buffer Maximum Resistances¹

Applicable to Advanced I/O Banks

Standard

Drive Strength

2 mA

R_PULL-DOWN()²

R_PULL-UP()³

3.3 V LVTTL / 3.3 V LVCMOS

100

50

300

150

75

4 mA

6 mA

8 mA

50

12 mA

16 mA

24 mA

100 µA

25

17

50

11

33

3.3 V LVCMOS Wide Range⁴

2.5 V LVCMOS

Same as regular

3.3 V LVCMOS

Same as regular

3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

12 mA

100

50

200

100

50

25

20

40

11

22

1.8 V LVCMOS

200

100

50

225

112

56

50

56

20

22

20

22

1.5 V LVCMOS

200

100

67

224

112

75

33

37

33

37

3.3 V PCI/PCI-X

Per PCI/PCI-X

specification

25

75

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design

considerations and detailed output buffer resistances, use the corresponding IBIS models located at

http://www.microsemi.com/soc/download/ibis/default.aspx.

2.

R

= (VOLspec) / IOLspec

(PULL-DOWN-MAX)

3.

R

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B

specification.

Revision 13

2-25

ProASIC3 DC and Switching Characteristics

Table 2-29 • I/O Output Buffer Maximum Resistances ¹

Applicable to Standard Plus I/O Banks

Standard

Drive Strength

R

_PULL-DOWN()²

R_PULL-UP()³

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

100

50

300

150

75

6 mA

8 mA

50

12 mA

16 mA

100 µA

25

75

3.3 V LVCMOS Wide Range⁴

2.5 V LVCMOS

Same as regular Same as regular

3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

12 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

100

50

200

100

50

25

1.8 V LVCMOS

1.5 V LVCMOS

200

100

50

225

112

56

50

56

200

100

25

224

112

75

3.3 V PCI/PCI-X

Per PCI/PCI-X

specification

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design

considerations and detailed output buffer resistances, use the corresponding IBIS models located at

http://www.microsemi.com/soc/download/ibis/default.aspx.

2.

3.

R

= (VOLspec) / IOLspec

(PULL-DOWN-MAX)

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B

specification.

2-26

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-30 • I/O Output Buffer Maximum Resistances¹

Applicable to Standard I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

2 mA

()²

100

50

()³

3.3 V LVTTL / 3.3 V LVCMOS

300

150

4 mA

6 mA

8 mA

50

3.3 V LVCMOS Wide Range⁴

2.5 V LVCMOS

100 µA

Same as regular

3.3 V LVCMOS

Same as regular

3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

2 mA

100

50

200

100

225

112

224

50

1.8 V LVCMOS

200

100

200

1.5 V LVCMOS

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design

considerations and detailed output buffer resistances, use the corresponding IBIS models located at

http://www.microsemi.com/soc/download/ibis/default.aspx.

2.

R

= (VOLspec) / IOLspec

(PULL-DOWN-MAX)

3.

R

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B

specification.

Table 2-31 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

1

2

R_{(WEAK PULL-UP)}

R_{(WEAK PULL-DOWN)}

()

VCCI

Min.

10 k

11 k

18 k

19 k

Max.

45 k

55 k

70 k

90 k

Min.

10 k

12 k

17 k

19 k

Max.

45 k

3.3 V

3.3 V (wide range I/Os)

45 k

2.5 V

1.8 V

1.5 V

Notes:

74 k

110 k

140 k

1.

2.

R

= (VCCI

– VOH

) / I

spec (WEAK PULL-UP-MIN)

(WEAK PULL-UP-MAX)

(WEAK PULL-DOWN-MAX)

MAX

= (VOL

) / I

(WEAK PULL-DOWN-MIN)

spec

Revision 13

2-27

ProASIC3 DC and Switching Characteristics

Table 2-32 • I/O Short Currents IOSH/IOSL

Applicable to Advanced I/O Banks

Drive Strength

IOSL (mA)¹

IOSH (mA)¹

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

27

25

6 mA

54

51

8 mA

54

51

12 mA

16 mA

24 mA

100 µA

109

127

181

103

132

268

3.3 V LVCMOS Wide Range²

2.5 V LVCMOS

Same as regular

3.3 V LVCMOS

Same as regular

3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

12 mA

18

37

74

87

124

11

16

32

65

83

169

9

1.8 V LVCMOS

22

44

51

74

16

33

39

55

109

17

35

45

91

13

25

32

66

103

1.5 V LVCMOS

3.3 V PCI/PCI-X

Per PCI/PCI-X

specification

Notes:

1. T = 100°C

J

2. Applicable to 3.3 V LVCMOS Wide Range. I

/I

dependent on the I/O buffer drive strength selected

OSL OSH

for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as

specified in the JESD8-B specification.

2-28

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-33 • I/O Short Currents IOSH/IOSL

Applicable to Standard Plus I/O Banks

Drive Strength

IOSL (mA)*

IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

27

25

6 mA

54

51

8 mA

54

51

12 mA

16 mA

100 µA

109

103

3.3 V LVCMOS Wide Range²

2.5 V LVCMOS

Same as regular

3.3 V LVCMOS

Same as regular

3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

12 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

18

37

74

11

16

32

65

9

1.8 V LVCMOS

1.5 V LVCMOS

22

44

16

33

109

17

35

13

25

103

3.3 V PCI/PCI-X

Per PCI/PCI-X

specification

Notes:

1. T = 100°C

J

2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength

selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide

range as specified in the JESD8-B specification.

Revision 13

2-29

ProASIC3 DC and Switching Characteristics

Table 2-34 • I/O Short Currents IOSH/IOSL

Applicable to Standard I/O Banks

Drive Strength

IOSL (mA)*

IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

27

54

25

51

6 mA

8 mA

3.3 V LVCMOS Wide Range²

2.5 V LVCMOS

100 µA

Same as regular

3.3 V LVCMOS

Same as regular

3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

2 mA

18

37

11

22

16

32

9

1.8 V LVCMOS

17

13

1.5 V LVCMOS

Notes:

1. T = 100°C

J

2. Applicable to 3.3 V LVCMOS Wide Range. I

/I

dependent on the I/O buffer drive strength selected

OSL OSH

for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as

specified in the JESD-8B specification.

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 100°C, the short current condition would have to be sustained for more than six months

to cause a reliability concern. The I/O design does not contain any short circuit protection, but such

protection would only be needed in extremely prolonged stress conditions.

Table 2-35 • Duration of Short Circuit Event Before Failure

Temperature

–40°C

0°C

Time before Failure

> 20 years

5 years

25°C

70°C

85°C

2 years

100°C

6 months

Table 2-36 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer

Input Rise/Fall Time (min.) Input Rise/Fall Time (max.)

Reliability

LVTTL/LVCMOS

No requirement

10 ns *

20 years (110°C)

10 years (100°C)

LVDS/B-LVDS/

M-LVDS/LVPECL

Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the

noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum

value. The longer the rise/fall times, the more susceptible the input signal is to the board noise.

Microsemi recommends signal integrity evaluation/characterization of the system to ensure that

there is no excessive noise coupling into input signals.

2-30

Revision 13

ProASIC3 Flash Family FPGAs

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer.

Table 2-37 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL¹IIH²

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA³

Max.

mA³

Drive Strength

2 mA

V

mA mA

µA⁴µA⁴

10 10

–0.3

0.8

2

3.6

0.4

2.4

2

27

25

4 mA

4

6 mA

6

54

51

8 mA

8

54

51

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

109

127

181

103

132

268

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-38 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

IOSL

IOSH

IIL¹IIH²

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA³

Max.

mA³

Drive Strength

2 mA

mA mA

µA⁴µA⁴

10 10

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

2

27

25

4 mA

4

6 mA

6

54

51

8 mA

8

54

51

12 mA

16 mA

Notes:

12

16

12

16

109

103

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Revision 13

2-31

ProASIC3 DC and Switching Characteristics

Table 2-39 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL¹IIH²

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA³

Max.

mA³

Drive Strength

2 mA

V

mA mA

µA⁴µA⁴

10 10

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

2

25

51

27

54

4 mA

4

6 mA

6

8 mA

8

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

I

IH

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

35 pF

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

Figure 2-6 • AC Loading

Table 2-40 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C

_LOAD(pF)

0

3.3

1.4

35

Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.

2-32

Revision 13

ProASIC3 Flash Family FPGAs

Timing Characteristics

Table 2-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

8.82

7.51

6.59

6.31

5.36

4.71

6.31

5.36

4.71

5.06

4.30

3.78

4.80

4.08

3.58

4.35

3.70

3.25

Units

ns

4 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

7.66 0.04 1.02

6.51 0.04 0.86

5.72 0.03 0.76

4.91 0.04 1.02

4.17 0.04 0.86

3.66 0.03 0.76

4.91 0.04 1.02

4.17 0.04 0.86

3.66 0.03 0.76

3.53 0.04 1.02

3.00 0.04 0.86

2.64 0.03 0.76

3.33 0.04 1.02

2.83 0.04 0.86

2.49 0.03 0.76

3.08 0.04 1.02

2.62 0.04 0.86

2.30 0.03 0.76

7.80 6.59 2.65 2.61 10.03

6.63 5.60 2.25 2.22

5.82 4.92 1.98 1.95

5.00 4.07 2.99 3.20

4.25 3.46 2.54 2.73

3.73 3.04 2.23 2.39

5.00 4.07 2.99 3.20

4.25 3.46 2.54 2.73

3.73 3.04 2.23 2.39

3.60 2.82 3.21 3.58

3.06 2.40 2.73 3.05

2.69 2.11 2.40 2.68

3.39 2.56 3.26 3.68

2.89 2.18 2.77 3.13

2.53 1.91 2.44 2.75

3.13 2.12 3.32 4.06

2.66 1.80 2.83 3.45

2.34 1.58 2.48 3.03

8.54

7.49

7.23

6.15

5.40

7.23

6.15

5.40

5.83

4.96

4.36

5.63

4.79

4.20

5.37

4.57

4.01

–2

6 mA

Std.

–1

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Notes:

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-33

ProASIC3 DC and Switching Characteristics

Table 2-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

10.45

8.89

7.80

7.41

6.30

5.53

7.41

6.30

5.53

5.68

4.84

4.24

5.30

4.51

3.96

4.94

4.20

3.69

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

10.26 0.04 1.02 0.43

8.72 0.04 0.86 0.36

7.66 0.03 0.76 0.32

7.27 0.04 1.02 0.43

6.19 0.04 0.86 0.36

5.43 0.03 0.76 0.32

7.27 0.04 1.02 0.43

6.19 0.04 0.86 0.36

5.43 0.03 0.76 0.32

5.58 0.04 1.02 0.43

4.75 0.04 0.86 0.36

4.17 0.03 0.76 0.32

5.21 0.04 1.02 0.43

4.43 0.04 0.86 0.36

3.89 0.03 0.76 0.32

4.85 0.04 1.02 0.43

4.13 0.04 0.86 0.36

3.62 0.03 0.76 0.32

8.90 2.64 2.46 12.68 11.13

ns

7.57 2.25 2.09 10.79

6.64 1.98 1.83 9.47

6.28 2.98 3.04 9.65

5.35 2.54 2.59 8.20

4.69 2.23 2.27 7.20

6.28 2.98 3.04 9.65

5.35 2.54 2.59 8.20

4.69 2.23 2.27 7.20

4.87 3.21 3.42 7.92

4.14 2.73 2.91 6.74

3.64 2.39 2.55 5.91

4.56 3.26 3.51 7.54

3.88 2.77 2.99 6.41

3.41 2.43 2.62 5.63

4.54 3.32 3.88 7.18

3.87 2.82 3.30 6.10

3.39 2.48 2.90 5.36

9.47

8.31

8.52

7.25

6.36

8.52

7.25

6.36

7.11

6.05

5.31

6.80

5.79

5.08

6.78

5.77

5.06

–2

6 mA

Std.

–1

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-34

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-43 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

9.57

8.14

7.15

6.82

5.80

5.09

6.82

5.80

5.09

5.45

4.64

4.07

5.45

4.64

4.07

t_ZHS

8.52

7.25

6.36

6.05

5.15

4.52

6.05

5.15

4.52

4.82

4.10

3.60

4.82

4.10

3.60

Units

ns

4 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

7.20 0.04 1.00

6.13 0.04 0.85

5.38 0.03 0.75

4.50 0.04 1.00

3.83 0.04 0.85

3.36 0.03 0.75

4.50 0.04 1.00

3.83 0.04 0.85

3.36 0.03 0.75

3.16 0.04 1.00

2.69 0.04 0.85

2.36 0.03 0.75

3.16 0.04 1.00

2.69 0.04 0.85

2.36 0.03 0.75

7.34 6.29 2.27 2.34

6.24 5.35 1.93 1.99

5.48 4.69 1.70 1.75

4.58 3.82 2.58 2.88

3.90 3.25 2.19 2.45

3.42 2.85 1.92 2.15

4.58 3.82 2.58 2.88

3.90 3.25 2.19 2.45

3.42 2.85 1.92 2.15

3.22 2.58 2.79 3.22

2.74 2.20 2.37 2.74

2.40 1.93 2.08 2.41

3.22 2.58 2.79 3.22

2.74 2.20 2.37 2.74

2.40 1.93 2.08 2.41

–2

6 mA

Std.

–1

–2

8 mA

Std.

–1

–2

12 mA

16 mA

Notes:

Std.

–1

–2

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-35

ProASIC3 DC and Switching Characteristics

Table 2-44 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

9.68 0.04 1.00 0.43

8.23 0.04 0.85 0.36

7.23 0.03 0.75 0.32

6.70 0.04 1.00 0.43

5.70 0.04 0.85 0.36

5.00 0.03 0.75 0.32

6.70 0.04 1.00 0.43

5.70 0.04 0.85 0.36

5.00 0.03 0.75 0.32

5.05 0.04 1.00 0.43

4.29 0.04 0.85 0.36

3.77 0.03 0.75 0.32

5.05 0.04 1.00 0.43

4.29 0.04 0.85 0.36

3.77 0.03 0.75 0.32

9.86

8.39

7.36

6.82

5.80

5.10

6.82

5.80

5.10

5.14

4.37

3.84

5.14

4.37

3.84

8.42 2.28 2.21 12.09 10.66

ns

7.17 1.94 1.88 10.29

6.29 1.70 1.65 9.03

5.89 2.58 2.74 9.06

5.01 2.20 2.33 7.71

4.40 1.93 2.05 6.76

5.89 2.58 2.74 9.06

5.01 2.20 2.33 7.71

4.40 1.93 2.05 6.76

4.51 2.79 3.08 7.38

3.84 2.38 2.62 6.28

3.37 2.09 2.30 5.51

4.51 2.79 3.08 7.38

3.84 2.38 2.62 6.28

3.37 2.09 2.30 5.51

9.07

7.96

8.12

6.91

6.06

8.12

6.91

6.06

6.75

5.74

5.04

6.75

5.74

5.04

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-45 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

4 mA

6 mA

8 mA

Notes:

Std.

–1

7.07

6.01

5.28

7.07

6.01

5.28

4.41

3.75

3.29

4.41

3.75

3.29

1.00

0.85

0.75

1.00

0.85

0.75

1.00

0.85

0.75

1.00

0.85

0.75

7.20

6.12

5.37

7.20

6.12

5.37

4.49

3.82

3.36

4.49

3.82

3.36

6.23

5.30

4.65

6.23

5.30

4.65

3.75

3.19

2.80

3.75

3.19

2.80

2.07

1.76

1.55

2.07

1.76

1.55

2.39

2.04

1.79

2.39

2.04

1.79

2.15

1.83

1.60

2.15

1.83

1.60

2.69

2.29

2.01

2.69

2.29

2.01

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-36

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-46 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

4 mA

6 mA

8 mA

9.46

8.05

7.07

9.46

8.05

7.07

6.57

5.59

4.91

6.57

5.59

4.91

1.00

0.85

0.75

1.00

0.85

0.75

1.00

0.85

0.75

1.00

0.85

0.75

9.64

8.20

7.20

9.64

8.20

7.20

6.69

5.69

5.00

6.69

5.69

5.00

8.54

7.27

6.38

8.54

7.27

6.38

5.98

5.09

4.47

5.98

5.09

4.47

2.07

1.76

1.55

2.07

1.76

1.55

2.40

2.04

1.79

2.40

2.04

1.79

2.04

1.73

1.52

2.04

1.73

1.52

2.57

2.19

1.92

2.57

2.19

1.92

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-37

ProASIC3 DC and Switching Characteristics

3.3 V LVCMOS Wide Range

Table 2-47 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

3.3 V

Equiv.

LVCMOS

Wide Range Default

Drive

Strength

Software

VIL

VIH

VOL

VOH

IOL IOH IOSL

Max.

IOSH IIL²IIH³

Strength Min.

Max. Min. Max. Max.

Min.

V

Max.

Option¹

2 mA

V

2

V

µA µA

mA⁴

25

mA⁴µA⁵µA⁵

100 µA

Notes:

–0.3

0.8

3.6

0.2

VDD – 0.2 100 100

27

10 10

4 mA

25

6 mA

51

54

8 mA

51

54

12 mA

16 mA

24 mA

103

132

268

109

127

181

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

4. Currents are measured at 85°C junction temperature.

5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

6. Software default selection highlighted in gray.

Table 2-48 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

3.3 V LVCMOS

Wide Range

Equiv.

Software

Default

Drive

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH IIL²IIH³

Strength Min. Max. Min. Max. Max.

Min.

V

Max.

Drive Strength Option¹

V

2

V

µA µA mA⁴

mA⁴µA⁵µA⁵

100 µA

100 A

Notes:

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

–0.3

0.8

3.6

0.2

VDD – 0.2 100 100

25

51

27

10 10

54

VDD – 0.2 100 100 103

109

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

4. Currents are measured at 85°C junction temperature.

5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

6. Software default selection highlighted in gray.

2-38

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-49 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

3.3 V

Equiv.

LVCMOS

Wide Range Default

Drive

Strength

Software

VIL

VIH

VOL

VOH

IOL IOH

µA µA

IOSL

IOSH IIL²IIH³

Max.

Strength Min. Max. Min. Max. Max.

Min.

V

Max.

mA⁴

Option¹

2 mA

V

2

V

mA⁴

27

µA⁵µA⁵

10 10

100 µA

Notes:

–0.3

0.8

3.6

0.2

VDD – 0.2 100 100

25

51

4 mA

27

6 mA

54

8 mA

54

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

4. Currents are measured at 85°C junction temperature.

5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

6. Software default selection highlighted in gray.

Revision 13

2-39

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Equiv.

Software

Default

Drive

Strength

Strength Speed

Option¹

Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

Std.

–1

0.60 11.84 0.04 1.02 0.43 11.84 10.00 4.10 4.04 15.23 13.40 ns

0.51 10.07 0.04 0.86 0.36 10.07 8.51 3.48 3.44 12.96 11.40 ns

0.45 8.84 0.03 0.76 0.32 8.84 7.47 3.06 3.02 11.38 10.00 ns

–2

6 mA

8 mA

Std.

–1

0.60 7.59 0.04 1.02 0.43 7.59 6.18 4.62 4.95 10.98 9.57

0.51 6.45 0.04 0.86 0.36 6.45 5.25 3.93 4.21 9.34 8.14

0.45 5.67 0.03 0.76 0.32 5.67 4.61 3.45 3.70 8.20 7.15

0.60 7.59 0.04 1.02 0.43 7.59 6.18 4.62 4.95 10.98 9.57

0.51 6.45 0.04 0.86 0.36 6.45 5.25 3.93 4.21 9.34 8.14

0.45 5.67 0.03 0.76 0.32 5.67 4.61 3.45 3.70 8.20 7.15

0.60 5.46 0.04 1.02 0.43 5.46 4.29 4.97 5.54 8.86 7.68

0.51 4.65 0.04 0.86 0.36 4.65 3.65 4.22 4.71 7.53 6.54

0.45 4.08 0.03 0.76 0.32 4.08 3.20 3.71 4.14 6.61 5.74

0.60 5.15 0.04 1.02 0.43 5.15 3.89 5.04 5.69 8.55 7.29

0.51 4.38 0.04 0.86 0.36 4.38 3.31 4.29 4.84 7.27 6.20

0.45 3.85 0.03 0.76 0.32 3.85 2.91 3.77 4.25 6.38 5.44

0.60 4.75 0.04 1.02 0.43 4.75 3.22 5.14 6.28 8.15 6.61

0.51 4.04 0.04 0.86 0.36 4.04 2.74 4.37 5.34 6.93 5.62

0.45 3.55 0.03 0.76 0.32 3.55 2.40 3.84 4.69 6.09 4.94

ns

–2

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. Software default selection highlighted in gray.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-40

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Equiv.

Software

Default

Drive

Strength

Strength Speed

Option¹

Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

2 mA

Std.

–1

0.60 15.86 0.04 1.54 0.43 15.86 13.51 4.09 3.80 19.25 16.90 ns

0.51 13.49 0.04 1.31 0.36 13.49 11.49 3.48 3.23 16.38 14.38 ns

0.45 11.84 0.03 1.15 0.32 11.84 10.09 3.05 2.84 14.38 12.62 ns

0.60 11.25 0.04 1.54 0.43 11.25 9.54 4.61 4.70 14.64 12.93 ns

0.51 9.57 0.04 1.31 0.36 9.57 8.11 3.92 4.00 12.46 11.00 ns

–2

4 mA

6 mA

Std.

–1

–2

0.45 8.40 0.03 1.15 0.32 8.40 7.12 3.44 3.51 10.93 9.66

ns

Std.

–1

0.60 11.25 0.04 1.54 0.43 11.25 9.54 4.61 4.70 14.64 12.93 ns

0.51 9.57 0.04 1.31 0.36 9.57 8.11 3.92 4.00 12.46 11.00 ns

–2

0.45 8.40 0.03 1.15 0.32 8.40 7.12 3.44 3.51 10.93 9.66

ns

8 mA

Std.

–1

0.60 8.63 0.04 1.54 0.43 8.63 7.39 4.96 5.28 12.02 10.79 ns

0.51 7.34 0.04 1.31 0.36 7.34 6.29 4.22 4.49 10.23 9.18

0.45 6.44 0.03 1.15 0.32 6.44 5.52 3.70 3.94 8.98 8.06

ns

–2

16 mA

24 mA

Std.

–1

0.60 8.05 0.04 1.54 0.43 8.05 6.93 5.03 5.43 11.44 10.32 ns

0.51 6.85 0.04 1.31 0.36 6.85 5.90 4.28 4.62 9.74 8.78

0.45 6.01 0.03 1.15 0.32 6.01 5.18 3.76 4.06 8.55 7.71

ns

–2

Std.

–1

0.60 7.50 0.04 1.54 0.43 7.50 6.90 5.13 6.00 10.89 10.29 ns

0.51 6.38 0.04 1.31 0.36 6.38 5.87 4.36 5.11 9.27 8.76

0.45 5.60 0.03 1.15 0.32 5.60 5.15 3.83 4.48 8.13 7.69

ns

–2

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-41

ProASIC3 DC and Switching Characteristics

Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Equiv.

Software

Default

Drive

Strength

Strength Speed

Option¹

Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

2 mA

Std.

–1

0.60 11.14 0.04 1.52 0.43 11.14 9.54 3.51 3.61 14.53 12.94 ns

0.51 9.48 0.04 1.29 0.36 9.48 8.12 2.99 3.07 12.36 11.00 ns

–2

0.45 8.32 0.03 1.14 0.32 8.32 7.13 2.62 2.70 10.85 9.66

0.60 6.96 0.04 1.52 0.43 6.96 5.79 3.99 4.45 10.35 9.19

0.51 5.92 0.04 1.29 0.36 5.92 4.93 3.39 3.78 8.81 7.82

0.45 5.20 0.03 1.14 0.32 5.20 4.33 2.98 3.32 7.73 6.86

0.60 6.96 0.04 1.52 0.43 6.96 5.79 3.99 4.45 10.35 9.19

0.51 5.92 0.04 1.29 0.36 5.92 4.93 3.39 3.78 8.81 7.82

0.45 5.20 0.03 1.14 0.32 5.20 4.33 2.98 3.32 7.73 6.86

0.60 4.89 0.04 1.52 0.43 4.89 3.92 4.31 4.98 8.28 7.32

0.51 4.16 0.04 1.29 0.36 4.16 3.34 3.67 4.24 7.04 6.22

0.45 3.65 0.03 1.14 0.32 3.65 2.93 3.22 3.72 6.18 5.46

0.60 4.89 0.04 1.52 0.43 4.89 3.92 4.31 4.98 8.28 7.32

0.51 4.16 0.04 1.29 0.36 4.16 3.34 3.67 4.24 7.04 6.22

0.45 3.65 0.03 1.14 0.32 3.65 2.93 3.22 3.72 6.18 5.46

ns

4 mA

6 mA

8 mA

16 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. Software default selection highlighted in gray.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-42

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Equiv.

Software

Default

Drive

Strength

Strength Speed

Option¹

Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

2 mA

Std.

–1

0.60 14.97 0.04 1.52 0.43 14.97 12.79 3.52 3.41 18.36 16.18 ns

0.51 12.73 0.04 1.29 0.36 12.73 10.88 2.99 2.90 15.62 13.77 ns

0.45 11.18 0.03 1.14 0.32 11.18 9.55 2.63 2.55 13.71 12.08 ns

0.60 10.36 0.04 1.52 0.43 10.36 8.93 3.99 4.24 13.75 12.33 ns

0.51 8.81 0.04 1.29 0.36 8.81 7.60 3.39 3.60 11.70 10.49 ns

–2

4 mA

6 mA

8 mA

16 mA

Std.

–1

–2

0.45 7.74 0.03 1.14 0.32 7.74 6.67 2.98 3.16 10.27 9.21

ns

Std.

–1

0.60 10.36 0.04 1.52 0.43 10.36 8.93 3.99 4.24 13.75 12.33 ns

0.51 8.81 0.04 1.29 0.36 8.81 7.60 3.39 3.60 11.70 10.49 ns

–2

0.45 7.74 0.03 1.14 0.32 7.74 6.67 2.98 3.16 10.27 9.21

ns

Std.

–1

0.60 7.81 0.04 1.52 0.43 7.81 6.85 4.32 4.76 11.20 10.24 ns

0.51 6.64 0.04 1.29 0.36 6.64 5.82 3.67 4.05 9.53 8.71

0.45 5.83 0.03 1.14 0.32 5.83 5.11 3.22 3.56 8.36 7.65

ns

–2

Std.

–1

0.60 7.81 0.04 1.52 0.43 7.81 6.85 4.32 4.76 11.20 10.24 ns

0.51 6.64 0.04 1.29 0.36 6.64 5.82 3.67 4.05 9.53 8.71

0.45 5.83 0.03 1.14 0.32 5.83 5.11 3.22 3.56 8.36 7.65

ns

–2

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-43

ProASIC3 DC and Switching Characteristics

Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Equiv.

Software

Default

Drive

Strength

Speed

Grade

Option¹

t_DOUT

0.60

0.51

0.45

0.60

0.51

0.45

0.60

0.51

0.45

0.60

0.51

0.45

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZUnits

100 µA

Notes:

2 mA

4 mA

6 mA

8 mA

Std.

–1

10.93 0.04 1.52 0.43 10.93 9.46 3.20 3.32

ns

9.29

8.16

0.04 1.29 0.36

0.03 1.13 0.32

9.29

8.16

8.04 2.72 2.82

7.06 2.39 2.48

–2

Std.

–1

10.93 0.04 1.52 0.43 10.93 9.46 3.20 3.32

9.29

8.16

6.82

5.80

5.09

6.82

5.80

5.09

0.04 1.29 0.36

0.03 1.13 0.32

0.04 1.52 0.43

0.04 1.29 0.36

0.03 1.13 0.32

0.04 1.52 0.43

0.04 1.29 0.36

0.03 1.13 0.32

9.29

8.16

6.82

5.80

5.09

6.82

5.80

5.09

8.04 2.72 2.82

7.06 2.39 2.48

5.70 3.70 4.16

4.85 3.15 3.54

4.25 2.77 3.11

5.70 3.70 4.16

4.85 3.15 3.54

4.25 2.77 3.11

–2

Std.

–1

–2

Std.

–1

–2

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. Software default selection highlighted in gray.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-44

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Equiv.

Software

Default

Drive

Strength

Speed

Grade

Option¹

t_DOUT

0.60

0.51

0.45

0.60

0.51

0.45

0.60

0.51

0.45

0.60

0.51

0.45

t_DP

t_DINt_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZUnits

100 µA

Notes:

2 mA

4 mA

6 mA

8 mA

Std.

–1

14.64 0.04 1.52 0.43 14.64 12.97 3.21 3.15

12.45 0.04 1.29 0.36 12.45 11.04 2.73 2.68

10.93 0.03 1.13 0.32 10.93 9.69 2.39 2.35

14.64 0.04 1.52 0.43 14.64 12.97 3.21 3.15

12.45 0.04 1.29 0.36 12.45 11.04 2.73 2.68

10.93 0.03 1.13 0.32 10.93 9.69 2.39 2.35

10.16 0.04 1.52 0.43 10.16 9.08 3.71 3.98

ns

–2

Std.

–1

–2

Std.

–1

8.64 0.04 1.29 0.36

7.58 0.03 1.13 0.32

8.64

7.58

7.73 3.15 3.39

6.78 2.77 2.97

–2

Std.

–1

10.16 0.04 1.52 0.43 10.16 9.08 3.71 3.98

8.64 0.04 1.29 0.36

7.58 0.03 1.13 0.32

8.64

7.58

7.73 3.15 3.39

6.78 2.77 2.97

–2

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-45

ProASIC3 DC and Switching Characteristics

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications.

Table 2-56 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

2.5 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL1 IIH²

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA³

Max.

mA³

Drive Strength

2 mA

V

mA mA

µA⁴µA⁴

10 10

–0.3

0.7

1.7

2.7

0.7

1.7

2

4

6

8

2

4

6

8

18

16

4 mA

6 mA

37

32

8 mA

37

32

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

74

65

87

83

124

169

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-57 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

2.5 V LVCMOS

VIL

VIH

Max.

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL¹IIH²

Min.

V

Max.

V

Min.

V

Max.

V

Max.

mA³

Max.

mA³

Drive Strength

2 mA

V

mA mA

µA⁴µA⁴

10 10

–0.3

0.7

1.7

2.7

0.7

1.7

2

18

37

74

16

32

65

4 mA

4

6 mA

6

8 mA

8

12 mA

Notes:

12 12

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

2-46

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-58 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

2.5 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL¹IIH²

Min.

V

Max.,

V

Min.

V

Max.

V

Max.

V

Max.

mA³

Max.

mA³

Drive Strength

2 mA

V

mA mA

µA⁴µA⁴

10 10

–0.3

0.7

1.7

3.6

0.7

1.7

2

16

32

18

37

4 mA

4

6 mA

6

8 mA

8

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

Figure 2-7 • AC Loading

Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C

_LOAD(pF)

0

2.5

1.2

35

Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.

Revision 13

2-47

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-60 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

4 mA

Std.

–1

0.60

0.51

0.45

0.60

0.51

0.45

0.60

0.51

0.45

0.60

0.51

0.45

0.60

0.51

0.45

0.60

0.51

0.45

8.66

7.37

6.47

5.17

4.39

3.86

5.17

4.39

3.86

3.56

3.03

2.66

3.35

2.85

2.50

3.09

2.63

2.31

0.04 1.31

0.04 1.11

0.03 0.98

0.04 1.31

0.04 1.11

0.03 0.98

0.04 1.31

0.04 1.11

0.03 0.98

0.04 1.31

0.04 1.11

0.03 0.98

0.04 1.31

0.04 1.11

0.03 0.98

0.04 1.31

0.04 1.11

0.03 0.98

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

7.83

6.66

5.85

5.04

4.28

3.76

5.04

4.28

3.76

3.63

3.08

2.71

3.41

2.90

2.55

3.15

2.68

2.35

8.66

7.37

6.47

5.17

4.39

3.86

5.17

4.39

3.86

3.43

2.92

2.56

3.06

2.60

2.29

2.44

2.08

1.82

2.68 2.30 10.07 10.90

2.28 1.96

2.00 1.72

3.05 3.00

2.59 2.55

2.28 2.24

3.05 3.00

2.59 2.55

2.28 2.24

3.30 3.44

2.81 2.92

2.47 2.57

3.36 3.55

2.86 3.02

2.51 2.65

3.44 4.00

2.92 3.40

2.57 2.98

8.56

7.52

7.27

6.19

5.43

7.27

6.19

5.43

5.86

4.99

4.38

5.65

4.81

4.22

5.38

4.58

4.02

9.27

8.14

7.40

6.30

5.53

7.40

6.30

5.53

5.67

4.82

4.23

5.30

4.51

3.96

4.68

3.98

3.49

–2

6 mA

Std.

–1

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Notes:

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-48

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-61 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

11.40 0.04 1.31 0.43

9.69 0.04 1.11 0.36

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.60

0.51

0.45

0.60

0.51

0.45

0.60

0.51

0.45

0.60

0.51

0.45

0.60

0.51

0.45

0.60

0.51

0.45

11.22 11.40 2.68 2.20 13.45 13.63

ns

9.54

8.38

8.11

6.90

6.05

8.11

6.90

6.05

6.29

5.35

4.70

5.87

4.99

4.38

5.50

4.68

4.11

9.69 2.28 1.88 11.44 11.60

8.51 2.00 1.65 10.05 10.18

7.81 3.05 2.89 10.34 10.05

–2

8.51 0.03 0.98 0.32

7.96 0.04 1.31 0.43

6 mA

Std.

–1

6.77 0.04 1.11

0.36

6.65 2.59 2.46 8.80

5.84 2.28 2.16 7.72

8.55

7.50

–2

5.94 0.03 0.98 0.32

7.96 0.04 1.31 0.43

8 mA

Std.

–1

7.81 3.05 2.89 10.34 10.05

6.77 0.04 1.11

0.36

6.65 2.59 2.46 8.80

5.84 2.28 2.16 7.72

5.92 3.30 3.32 8.53

5.03 2.81 2.83 7.26

4.42 2.47 2.48 6.37

8.55

7.50

8.15

6.94

6.09

7.76

6.60

5.80

7.74

6.59

5.78

–2

5.94 0.03 0.98 0.32

6.18 0.04 1.31 0.43

12 mA

16 mA

24 mA

Std.

–1

5.26 0.04 1.11

0.36

–2

4.61 0.03 0.98 0.32

5.76 0.04 1.31 0.43

Std.

–1

5.53 3.36 3.44

8.11

4.90 0.04 1.11

0.36

4.70 2.86 2.92 6.90

4.13 2.51 2.57 6.05

5.51 3.43 3.87 7.74

4.68 2.92 3.29 6.58

–2

4.30 0.03 0.98 0.32

5.51 0.04 1.31 0.43

Std.

–1

4.68 0.04 1.11

0.36

–2

4.11 0.03 0.98 0.32

4.11

2.56 2.89 5.78

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-49

ProASIC3 DC and Switching Characteristics

Table 2-62 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

9.64

8.20

7.20

6.88

5.85

5.14

6.88

5.85

5.14

5.50

4.68

4.11

t_ZHS

10.51

8.94

7.85

7.09

6.03

5.29

7.09

6.03

5.29

5.38

4.57

4.02

Units

ns

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.28 0.04 1.30

7.04 0.04 1.10

6.18 0.03 0.97

4.85 0.04 1.30

4.13 0.04 1.10

3.62 0.03 0.97

4.85 0.04 1.30

4.13 0.04 1.10

3.62 0.03 0.97

3.21 0.04 1.30

2.73 0.04 1.10

2.39 0.03 0.97

7.41 8.28 2.25 2.07

6.30 7.04 1.92 1.76

5.53 6.18 1.68 1.55

4.65 4.85 2.59 2.71

3.95 4.13 2.20 2.31

3.47 3.62 1.93 2.02

4.65 4.85 2.59 2.71

3.95 4.13 2.20 2.31

3.47 3.62 1.93 2.02

3.27 3.14 2.82 3.11

2.78 2.67 2.40 2.65

2.44 2.35 2.11 2.32

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-63 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

6 mA

8 mA

12 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

10.84 0.04 1.30 0.43

9.22 0.04 1.10 0.36

8.10 0.03 0.97 0.32

7.37 0.04 1.30 0.43

6.27 0.04 1.10 0.36

5.50 0.03 0.97 0.32

7.37 0.04 1.30 0.43

6.27 0.04 1.10 0.36

5.50 0.03 0.97 0.32

5.63 0.04 1.30 0.43

4.79 0.04 1.10 0.36

4.20 0.03 0.97 0.32

10.64 10.84 2.26 1.99 12.87 13.08

ns

9.05

7.94

7.50

6.38

5.60

7.50

6.38

5.60

5.73

4.88

4.28

9.22 1.92 1.69 10.95 11.12

–2

8.10 1.68 1.49 9.61

7.36 2.59 2.61 9.74

6.26 2.20 2.22 8.29

5.50 1.93 1.95 7.27

7.36 2.59 2.61 9.74

6.26 2.20 2.22 8.29

5.50 1.93 1.95 7.27

5.51 2.83 3.01 7.97

4.68 2.41 2.56 6.78

9.77

9.60

8.16

7.17

9.60

8.16

7.17

7.74

6.59

5.78

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

4.11

2.11 2.25 5.95

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-50

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-64 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

4 mA

6 mA

8 mA

Notes:

8.20

6.98

6.13

8.20

6.98

6.13

4.77

4.05

3.56

4.77

4.05

3.56

1.29

1.10

0.96

1.29

1.10

0.96

1.29

1.10

0.96

1.29

1.10

0.96

7.24

6.16

5.41

7.24

6.16

5.41

4.55

3.87

3.40

4.55

3.87

3.40

8.20

6.98

6.13

8.20

6.98

6.13

4.77

4.05

3.56

4.77

4.05

3.56

2.03

1.73

1.52

2.03

1.73

1.52

2.38

2.03

1.78

2.38

2.03

1.78

1.91

1.62

1.43

1.91

1.62

1.43

2.55

2.17

1.91

2.55

2.17

1.91

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-65 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

11.00

9.35

8.21

11.00

9.35

8.21

7.50

6.38

5.60

7.50

6.38

5.60

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

10.37

8.83

7.75

10.37

8.83

7.75

7.36

6.26

5.49

7.36

6.26

5.49

t_ZH

11.00

9.35

8.21

11.00

9.35

8.21

7.50

6.38

5.60

7.50

6.38

5.60

t_LZ

t_HZ

Units

ns

2 mA

4 mA

6 mA

8 mA

1.29

1.10

0.96

1.29

1.10

0.96

1.29

1.10

0.96

1.29

1.10

0.96

2.03

1.73

1.52

2.03

1.73

1.52

2.39

2.03

1.78

2.39

2.03

1.78

1.83

1.56

1.37

1.83

1.56

1.37

2.46

2.10

1.84

2.46

2.10

1.84

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-51

ProASIC3 DC and Switching Characteristics

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-66 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.8 V

LVCMOS

VIL

Max.,

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Drive

Strength

Min.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

V

mA mA mA³

mA³µA⁴µA⁴

2 mA

–0.3

0.35 * VCCI

0.65 * VCCI

1.9

0.45 VCCI – 0.45

2

4

2

4

11

22

44

51

74

9

10 10

4 mA

17

35

45

91

6 mA

6

8 mA

8

12 mA

16 mA

Notes:

0.45 VCCI – 0.45 12 12

0.45 VCCI – 0.45 16 16

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-67 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O I/O Banks

1.8 V

LVCMOS

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Drive

Strength

Min.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max. Max.

V

mA mA mA³mA³µA⁴µA⁴

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3 0.35 * VCCI 0.65 * VCCI

3.6

0.45 VCCI – 0.45

2

4

6

8

2

4

6

8

11

22

44

9

10 10

17

35

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <V CCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

2-52

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-68 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.8 V

LVCMOS

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Max. Max.

Drive

Strength

Min.

V

Max. Max.

Min.

V

mA mA mA³

mA³µA⁴µA⁴

2 mA

4 mA

Notes:

–0.3 0.35 * VCCI 0.65 * VCCI

3.6 0.45 VCCI – 0.45

2

4

2

4

9

11

22

10 10

17

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

Figure 2-8 • AC Loading

Table 2-69 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.8

0.9

35

Note: *Measuring point = Vtrip_.See Table 2-22 on page 2-21 for a complete table of trip points.

Revision 13

2-53

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-70 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

11.86 0.04 1.22 0.43

10.09 0.04 1.04 0.36

8.86 0.03 0.91 0.32

6.91 0.04 1.22 0.43

5.88 0.04 1.04 0.36

5.16 0.03 0.91 0.32

4.45 0.04 1.22 0.43

3.78 0.04 1.04 0.36

3.32 0.03 0.91 0.32

3.92 0.04 1.22 0.43

3.34 0.04 1.04 0.36

2.93 0.03 0.91 0.32

3.53 0.04 1.22 0.43

3.01 0.04 1.04 0.36

2.64 0.03 0.91 0.32

3.53 0.04 1.22 0.43

3.01 0.04 1.04 0.36

2.64 0.03 0.91 0.32

9.14

7.77

6.82

5.86

4.99

4.38

4.18

3.56

3.12

3.93

3.34

2.93

3.60

3.06

2.69

3.60

3.06

2.69

11.86 2.77 1.66 11.37 14.10

ns

10.09 2.36 1.41 9.67

8.86 2.07 1.24 8.49

6.91 3.22 2.84 8.10

5.88 2.74 2.41 6.89

5.16 2.41 2.12 6.05

4.45 3.53 3.38 6.42

3.78 3.00 2.88 5.46

3.32 2.64 2.53 4.79

3.92 3.60 3.52 6.16

3.34 3.06 3.00 5.24

2.93 2.69 2.63 4.60

3.04 3.70 4.08 5.84

2.59 3.15 3.47 4.96

2.27 2.76 3.05 4.36

3.04 3.70 4.08 5.84

2.59 3.15 3.47 4.96

2.27 2.76 3.05 4.36

11.99

10.53

9.15

7.78

6.83

6.68

5.69

4.99

6.16

5.24

4.60

5.28

4.49

3.94

5.28

4.49

3.94

–2

4 mA

Std.

–1

–2

6 mA

Std.

–1

–2

8 mA

Std.

–1

–2

12 mA

16 mA

Notes:

Std.

–1

–2

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-54

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-71 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

15.53 0.04 1.22 0.43

14.11 15.53 2.78 1.60 16.35 17.77

13.21 0.04 1.04 0.36 12.01 13.21 2.36 1.36 13.91 15.11

11.60 0.03 0.91 0.32 10.54 11.60 2.07 1.19 12.21 13.27

10.48 0.04 1.22 0.43 10.41 10.48 3.23 2.73 12.65 12.71

–2

Std.

–1

8.91 0.04 1.04 0.36

7.82 0.03 0.91 0.32

8.05 0.04 1.22 0.43

6.85 0.04 1.04 0.36

6.01 0.03 0.91 0.32

7.50 0.04 1.22 0.43

6.38 0.04 1.04 0.36

5.60 0.03 0.91 0.32

7.29 0.04 1.22 0.43

6.20 0.04 1.04 0.36

5.45 0.03 0.91 0.32

7.29 0.04 1.22 0.43

6.20 0.04 1.04 0.36

5.45 0.03 0.91 0.32

8.86

7.77

8.20

6.97

6.12

7.64

6.50

5.71

7.23

6.15

5.40

7.23

6.15

5.40

8.91 2.75 2.33 10.76 10.81

7.82 2.41 2.04 9.44 9.49

7.84 3.54 3.27 10.43 10.08

–2

Std.

–1

6.67 3.01 2.78 8.88

5.86 2.64 2.44 7.79

7.30 3.61 3.41 9.88

6.21 3.07 2.90 8.40

5.45 2.69 2.55 7.38

7.29 3.71 3.95 9.47

6.20 3.15 3.36 8.06

5.45 2.77 2.95 7.07

7.29 3.71 3.95 9.47

6.20 3.15 3.36 8.06

5.45 2.77 2.95 7.07

8.57

7.53

9.53

8.11

7.12

9.53

8.11

7.12

9.53

8.11

7.12

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-55

ProASIC3 DC and Switching Characteristics

Table 2-72 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

11.33 2.24 1.52 10.96 13.57

9.64 1.91 1.29 9.32 11.54

8.46 1.68 1.14 8.18 10.13

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

Notes:

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

11.33 0.04 1.20 0.43

9.64 0.04 1.02 0.36

8.46 0.03 0.90 0.32

6.48 0.04 1.20 0.43

5.51 0.04 1.02 0.36

4.84 0.03 0.90 0.32

4.06 0.04 1.20 0.43

3.45 0.04 1.02 0.36

3.03 0.03 0.90 0.32

4.06 0.04 1.20 0.43

3.45 0.04 1.02 0.36

3.03 0.03 0.90 0.32

8.72

7.42

6.51

5.48

4.66

4.09

3.84

3.27

2.87

3.84

3.27

2.87

ns

–2

ns

Std.

–1

6.48 2.65 2.60 7.72

5.51 2.25 2.21 6.56

4.84 1.98 1.94 5.76

4.06 2.93 3.10 6.07

3.45 2.49 2.64 5.17

3.03 2.19 2.32 4.54

4.06 2.93 3.10 6.07

3.45 2.49 2.64 5.17

3.03 2.19 2.32 4.54

8.72

7.42

6.51

6.30

5.36

4.70

6.30

5.36

4.70

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-56

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-73 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

14.80 0.04 1.20

12.59 0.04 1.02

11.05 0.03 0.90

0.43 13.49 14.80 2.25 1.46 15.73 17.04

0.36 11.48 12.59 1.91 1.25 13.38 14.49

0.32 10.08 11.05 1.68 1.09 11.75 12.72

ns

–2

Std.

–1

9.90

8.42

7.39

7.44

6.33

5.55

7.44

6.33

5.55

0.04 1.20

0.04 1.02

0.03 0.90

0.04 1.20

0.04 1.02

0.03 0.90

0.04 1.20

0.04 1.02

0.03 0.90

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

9.73

8.28

7.27

7.58

6.44

5.66

7.58

6.44

5.66

9.90 2.65 2.50 11.97 12.13

8.42 2.26 2.12 10.18 10.32

–2

7.39 1.98 1.86 8.94

7.32 2.94 2.99 9.81

6.23 2.50 2.54 8.35

5.47 2.19 2.23 7.33

7.32 2.94 2.99 9.81

6.23 2.50 2.54 8.35

5.47 2.19 2.23 7.33

9.06

9.56

8.13

7.14

9.56

8.13

7.14

Std.

–1

–2

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-74 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

11.21

9.54

8.37

6.34

5.40

4.74

t_DIN

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

11.21

9.54

8.37

6.34

5.40

4.74

t_LZ

t_HZ

Units

ns

2 mA

4 mA

Notes:

Std.

–1

1.20

1.02

0.90

1.20

1.02

0.90

8.53

7.26

6.37

5.38

4.58

4.02

1.99

1.69

1.49

2.41

2.05

1.80

1.21

1.03

0.90

2.48

2.11

1.85

ns

–2

ns

Std.

–1

ns

–2

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-57

ProASIC3 DC and Switching Characteristics

Table 2-75 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

13.15

11.19

9.82

9.55

8.13

7.13

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

15.01

12.77

11.21

10.10

8.59

1.20

1.02

0.90

1.20

1.02

0.90

15.01

12.77

11.21

10.10

8.59

1.99

1.70

1.49

2.41

2.05

1.80

1.99

1.70

1.49

2.37

2.02

1.77

ns

–2

ns

4 mA

Std.

–1

ns

–2

7.54

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-76 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.5 V

LVCMOS

VIL

Max.

VIH

Min.

V

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Drive

Strength

Min.

V

Max.,

V

Max.

V

Min.

V

Max. Max.

V

mA mA mA³mA³µA⁴µA⁴

2 mA

4 mA

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI

2

4

6

8

2

4

16

33

39

55

13

25

32

66

10 10

6 mA

6

8 mA

8

12 mA

Notes:

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

2-58

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-77 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.5 V

LVCMOS

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSL

IOSH IIL¹IIH²

Drive

Strength

Min.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

V

mA mA mA³

mA³µA⁴µA⁴

2 mA

4 mA

Notes:

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI

2

4

2

4

16

33

13

25

10 10

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-78 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.5 V

LVCMOS

VIL

Max.

VIH

Min.

V

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Max.

V

Min.

V

Max. Max.

V

mA mA mA³mA³µA⁴µA⁴

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI

3.6

0.25 * VCCI 0.75 * VCCI

2

13

16

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

Figure 2-9 • AC Loading

Table 2-79 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.5

0.75

35

Note: *Measuring point = V_trip.See Table 2-22 on page 2-21 for a complete table of trip points.

Revision 13

2-59

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-80 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

6.82 8.36 3.39 2.77 9.06 10.60

5.80 7.11 2.88 2.35 7.71

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.36 0.04 1.44

7.11 0.04 1.22

6.24 0.03 1.07

5.31 0.04 1.44

4.52 0.04 1.22

3.97 0.03 1.07

4.67 0.04 1.44

3.97 0.04 1.22

3.49 0.03 1.07

4.08 0.04 1.44

3.47 0.04 1.22

3.05 0.03 1.07

4.08 0.04 1.44

3.47 0.04 1.22

3.05 0.03 1.07

ns

9.02

7.91

7.55

6.42

5.64

6.90

5.87

5.16

5.81

4.95

4.34

5.81

4.95

4.34

–2

5.10 6.24 2.53 2.06 6.76

4.85 5.31 3.74 3.40 7.09

4.13 4.52 3.18 2.89 6.03

3.62 3.97 2.79 2.54 5.29

4.55 4.67 3.82 3.56 6.78

3.87 3.97 3.25 3.03 5.77

3.40 3.49 2.85 2.66 5.07

4.15 3.58 3.94 4.20 6.39

3.53 3.04 3.36 3.58 5.44

3.10 2.67 2.95 3.14 4.77

4.15 3.58 3.94 4.20 6.39

3.53 3.04 3.36 3.58 5.44

3.10 2.67 2.95 3.14 4.77

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-60

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-81 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

12.78 0.04 1.44 0.43 12.81 12.78 3.40 2.64 15.05 15.02

10.87 0.04 1.22 0.36 10.90 10.87 2.89 2.25 12.80 12.78

ns

–2

9.55 0.03 1.07 0.32

9.57 9.55 2.54 1.97 11.24 11.22

Std.

–1

10.01 0.04 1.44 0.43 10.19 9.55 3.75 3.27 12.43 11.78

8.51 0.04 1.22 0.36

7.47 0.03 1.07 0.32

9.33 0.04 1.44 0.43

7.94 0.04 1.22 0.36

6.97 0.03 1.07 0.32

8.91 0.04 1.44 0.43

7.58 0.04 1.22 0.36

6.65 0.03 1.07 0.32

8.91 0.04 1.44 0.43

7.58 0.04 1.22 0.36

6.65 0.03 1.07 0.32

8.67 8.12 3.19 2.78 10.57 10.02

7.61 7.13 2.80 2.44 9.28 8.80

9.51 8.89 3.83 3.43 11.74 11.13

–2

Std.

–1

8.09 7.56 3.26 2.92 9.99

7.10 6.64 2.86 2.56 8.77

9.47

8.31

–2

Std.

–1

9.07 8.89 3.95 4.05 11.31 11.13

7.72 7.57 3.36 3.44 9.62

6.78 6.64 2.95 3.02 8.45

9.47

8.31

–2

Std.

–1

9.07 8.89 3.95 4.05 11.31 11.13

7.72 7.57 3.36 3.44 9.62

6.78 6.64 2.95 3.02 8.45

9.47

8.31

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-61

ProASIC3 DC and Switching Characteristics

Table 2-82 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

Notes:

7.83 0.04 1.42

6.66 0.04 1.21

5.85 0.03 1.06

4.84 0.04 1.42

4.12 0.04 1.21

3.61 0.03 1.06

6.42 7.83 2.71 2.55 8.65 10.07

ns

5.46 6.66 2.31 2.17 7.36

4.79 5.85 2.02 1.90 6.46

4.49 4.84 3.03 3.13 6.72

3.82 4.12 2.58 2.66 5.72

3.35 3.61 2.26 2.34 5.02

8.56

7.52

7.08

6.02

5.28

–2

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-83 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DINt_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

2 mA

12.08 0.04 1.42

10.27 0.04 1.21

9.02 0.03 1.06

9.28 0.04 1.42

7.89 0.04 1.21

6.93 0.03 1.06

12.01 12.08 2.72 2.43 14.24 14.31

10.21 10.27 2.31 2.06 12.12 12.18

8.97 9.02 2.03 1.81 10.64 10.69

9.45 8.91 3.04 3.00 11.69 11.15

8.04 7.58 2.58 2.55 9.94 9.49

7.06 6.66 2.27 2.24 8.73 8.33

ns

–2

4 mA

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-84 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

Std.

–1

7.65

6.50

5.71

1.42

1.21

1.06

6.31

5.37

4.71

7.65

6.50

5.71

2.45

2.08

1.83

2.45

2.08

1.83

ns

–2

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-62

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-85 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard I/O Banks

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

12.33

10.49

9.21

1.42

1.21

1.06

11.79

10.03

8.81

12.33

10.49

9.21

2.45

2.08

1.83

2.32

1.98

1.73

ns

–2

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus

applications.

Table 2-86 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X

VIL

Max.

VIH

Max.

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL IIH

Min.

V

Min.

V

Max,.

V

Max.

mA¹

Max.

mA¹

Drive Strength

Per PCI specification

Notes:

V

mA mA

µA²µA²

Per PCI curves

10 10

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable

path characterization are described in Figure 2-10.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R to VCCI for t_DP(F)

R to GND for t_DP(R)

R = 25

Test Point

Datapath

R = 1 k

Test Point

Enable Path

10 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-10 • AC Loading

AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is

described in Table 2-87.

Table 2-87 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C_LOAD(pF)

0

3.3

0.285 * VCCI for t_DP(R)

0.615 * VCCI for t_DP(F)

10

Note: *Measuring point = V_trip.See Table 2-22 on page 2-21 for a complete table of trip points.

Revision 13

2-63

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-88 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Speed Grade t_DOUT

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.97

4.22

3.71

t_ZHS

4.19

3.56

3.13

Units

ns

Std.

–1

0.66

0.56

0.49

2.68

2.28

2.00

0.86

0.73

0.65

2.73

2.32

2.04

1.95

1.66

1.46

3.21

2.73

2.40

3.58

3.05

2.68

ns

–2

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-89 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade t_DOUT

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.59

3.90

3.42

t_ZHS

3.94

3.35

2.94

Units

ns

Std.

–1

0.66

0.56

0.49

2.31

1.96

1.72

0.85

0.72

0.64

2.35

2.00

1.76

1.70

1.45

1.27

2.79

2.37

2.08

3.22

2.74

2.41

ns

–2

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by Microsemi Designer software when

the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-11. The

building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVPECL implementation because the output standard

specifications are different.

Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Bourns Part Number: CAT16-LV4F12

FPGA

OUTBUF_LVDS

P

N

P

N

165 

Z₀= 50 

140 

Z₀= 50 

INBUF_LVDS

+

–

100 

Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation

2-64

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-90 • LVDS Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Supply Voltage

Min.

2.375

0.9

Typ.

2.5

Max.

2.625

1.25

1.6

Units

V

VOL

Output Low Voltage

1.075

1.425

0.91

V

VOH

Output High Voltage

1.25

0.65

0

V

IOL ¹

Output Lower Current

Output High Current

1.16

2.925

10

mA

V

IOH ¹

VI

Input Voltage

IIH ^2,3

IIL ^2,4

Input High Leakage Current

Input Low Leakage Current

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

Input Differential Voltage

µA

mV

V

10

VODIFF

VOCM

VICM

250

1.125

0.05

100

350

1.25

350

450

1.375

2.35

V

VIDIFF

Notes:

mV

1. IOL/ IOH defined by VODIFF/(Resistor Network)

2. Currents are measured at 85°C junction temperature.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <VCCI. Input current is

larger when operating outside recommended ranges.

4. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN <VIL.

Table 2-91 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

1.075

1.325

Cross point

Note: *Measuring point = V_trip.See Table 2-22 on page 2-21 for a complete table of trip points.

Timing Characteristics

Table 2-92 • LVDS

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Speed Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

Units

ns

Std.

–1

1.83

1.56

1.37

1.60

1.36

1.20

ns

–2

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-65

ProASIC3 DC and Switching Characteristics

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to

high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain

any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive

current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series

terminations for better signal quality and to control voltage swing. Termination is also required at both

ends of the bus since the driver can be located anywhere on the bus. These configurations can be

implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.

Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20

loads. A sample application is given in Figure 2-12. The input and output buffer delays are available in

the LVDS section in Table 2-92.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required

differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: R_S= 60  and

R_T= 70 , given Z₀= 50  (2") and Z_stub= 50  (~1.5").

Receiver

Transceiver

Driver

D

Receiver

Transceiver

EN

BIBUF_LVDS

R

T

R

T

+

-

+

-

+

-

+

-

+

-

R_SR_S

Z_stub

R_SR_S

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

...

Z₀

R_T

Z₀

Figure 2-12 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires

that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The

building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVDS implementation because the output standard

specifications are different.

Bourns Part Number: CAT16-PC4F12

FPGA

P

N

OUTBUF_LVPECL

100 

Z₀= 50 

187 W

INBUF_LVPECL

+

–

100 

Z₀= 50 

N

Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation

2-66

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-93 • Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Supply Voltage

Min.

Max.

Min.

Max.

Min.

Max.

Units

V

3.0

3.3

3.6

VOL

Output Low Voltage

0.96

1.8

1.27

2.11

3.6

1.06

1.92

0

1.43

2.28

3.6

1.30

2.13

0

1.57

2.41

3.6

V

VOH

Output High Voltage

V

VIL, VIH

VODIFF

VOCM

VICM

Input Low, Input High Voltages

Differential Output Voltage

Output Common-Mode Voltage

Input Common-Mode Voltage

Input Differential Voltage

0

V

0.625

1.762

1.01

300

0.97

1.98

2.57

0.625

1.762

1.01

300

0.97

1.98

2.57

0.625

1.762

1.01

300

0.97

1.98

2.57

V

VIDIFF

mV

Table 2-94 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

1.64

1.94

Cross point

Note: *Measuring point = V_trip.See Table 2-22 on page 2-21 for a complete table of trip points.

Timing Characteristics

Table 2-95 • LVPECL

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

Units

ns

Std.

–1

1.80

1.53

1.34

1.40

1.19

1.05

ns

–2

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-67

ProASIC3 DC and Switching Characteristics

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Preset

Preset

L

D

DOUT

Data_out

PRE

F

PRE

Y

E

Core

Array

Data

Enable

CLK

D

Q

D

Q

C

DFN1E1P1

G

E

EOUT

B

A

H

I

PRE

J

D

Q

DFN1E1P1

K

Data Input I/O Register with:

Active High Enable

E

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

INBUF

CLKBUF

Postive-Edge Triggered

Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

2-68

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-96 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

H, DOUT

F, H

Data Setup Time for the Output Data Register

Data Hold Time for the Output Data Register

t_OHD

F, H

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

G, H

t_OHE

G, H

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

t_OEHD

L, DOUT

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

J, H

t_OESUE

t_OEHE

K, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

I, EOUT

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

I, H

A, E

C, A

B, A

D, E

D, A

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_IPRE2Q

t_IREMPRE

t_IRECPRE

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Note: *See Figure 2-14 on page 2-68 for more information.

Revision 13

2-69

ProASIC3 DC and Switching Characteristics

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Clear

DOUT

FF

Data_out

Y

Core

D

Q

D

Q

Data

Array

CC

EE

DFN1E1C1

GG

EOUT

E

Enable

CLK

CLR

BB

AA

DD

CLR

LL

HH

JJ

D

Q

CLR

DFN1E1C1

KK

E

Data Input I/O Register with

Active High Enable

CLR

Active High Clear

Positive-Edge Triggered

Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

INBUF

CLKBUF

Figure 2-15 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

2-70

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-97 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

HH, DOUT

FF, HH

Data Setup Time for the Output Data Register

Data Hold Time for the Output Data Register

t_OHD

FF, HH

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

GG, HH

LL, DOUT

LL, HH

t_OHE

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

t_OEHD

LL, HH

HH, EOUT

JJ, HH

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

JJ, HH

t_OESUE

t_OEHE

KK, HH

II, EOUT

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

II, HH

AA, EE

CC, AA

BB, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IREMCLR

t_IRECCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Note: *See Figure 2-15 on page 2-70 for more information.

Revision 13

2-71

ProASIC3 DC and Switching Characteristics

Input Register

t_ICKMPWHt_ICKMPWL

50%

CLK

t_IHD

t_ISUD

50%

1

0

Data

t_IREMPRE

t_IRECPRE

t_IWPRE

Enable

Preset

50%

t_IHE

t_ISUE

50%

t_IWCLR

t_IRECCLR

50%

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-16 • Input Register Timing Diagram

Timing Characteristics

Table 2-98 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_ICLKQ

Description

–2 –1 Std. Units

0.24 0.27 0.32 ns

0.26 0.30 0.35 ns

0.00 0.00 0.00 ns

0.37 0.42 0.50 ns

0.00 0.00 0.00 ns

0.45 0.52 0.61 ns

0.00 0.00 0.00 ns

0.22 0.25 0.30 ns

0.00 0.00 0.00 ns

0.22 0.25 0.30 ns

0.36 0.41 0.48 ns

0.32 0.37 0.43 ns

Clock-to-Q of the Input Data Register

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

t_IWPRE

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

t_ICKMPWHClock Minimum Pulse Width High for the Input Data Register

t_ICKMPWLClock Minimum Pulse Width Low for the Input Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-72

Revision 13

ProASIC3 Flash Family FPGAs

Output Register

t_OCKMPWHt_OCKMPWL

50%

CLK

t_OSUDt_OHD

50%

1

0

Data_out

t_OREMPRE

Enable

Preset

50%

t_OWPREt_ORECPRE

50%

t_OHE

50%

t_OSUE

t_OREMCLR

50%

t_ORECCLR

50%

t_OWCLR

50%

Clear

t_OPRE2Q

50%

t_OCLKQ

50%

DOUT

t_OCLR2Q

Figure 2-17 • Output Register Timing Diagram

Timing Characteristics

Table 2-99 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_OCLKQ

Description

–2

–1 Std. Units

Clock-to-Q of the Output Data Register

0.59 0.67 0.79

0.31 0.36 0.42

0.00 0.00 0.00

0.44 0.50 0.59

0.00 0.00 0.00

0.80 0.91 1.07

0.00 0.00 0.00

0.22 0.25 0.30

0.00 0.00 0.00

0.22 0.25 0.30

0.36 0.41 0.48

0.32 0.37 0.43

ns

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

t_OCKMPWHClock Minimum Pulse Width High for the Output Data Register

t_OCKMPWLClock Minimum Pulse Width Low for the Output Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-73

ProASIC3 DC and Switching Characteristics

Output Enable Register

t_OECKMPWHt_OECKMPWL

50%

CLK

t_{OESUD OEHD}

t

50% 50%

1

0

D_Enable

50%

Enable

Preset

t_OEWPRE

50%

t_OEREMPRE

50%

t_OERECPRE

50%

t_OESUEOEHE

t

t_OEREMCLR

50%

t_OEWCLRt_OERECCLR

50%

Clear

t_OECLR2Q

50%

t_OEPRE2Q

50%

t_OECLKQ

EOUT

Figure 2-18 • Output Enable Register Timing Diagram

2-74

Revision 13

ProASIC3 Flash Family FPGAs

Timing Characteristics

Table 2-100 • Output Enable Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_OECLKQ

t_OESUD

Description

–2

–1 Std. Units

Clock-to-Q of the Output Enable Register

0.59 0.67 0.79

0.31 0.36 0.42

0.00 0.00 0.00

0.44 0.50 0.58

0.00 0.00 0.00

0.67 0.76 0.89

0.00 0.00 0.00

0.22 0.25 0.30

0.00 0.00 0.00

0.22 0.25 0.30

ns

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

t_OEHD

t_OESUE

t_OEHE

t_OECLR2Q

t_OEPRE2Q

t_OEREMCLRAsynchronous Clear Removal Time for the Output Enable Register

t_OERECCLRAsynchronous Clear Recovery Time for the Output Enable Register

t_OEREMPREAsynchronous Preset Removal Time for the Output Enable Register

t_OERECPREAsynchronous Preset Recovery Time for the Output Enable Register

t_OEWCLR

t_OEWPRE

Asynchronous Clear Minimum Pulse Width for the Output Enable Register

Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30

t_OECKMPWHClock Minimum Pulse Width High for the Output Enable Register

t_OECKMPWLClock Minimum Pulse Width Low for the Output Enable Register

0.36 0.41 0.48

0.32 0.37 0.43

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-75

ProASIC3 DC and Switching Characteristics

DDR Module Specifications

Input DDR Module

Input DDR

INBUF

Data

A

D

Out_QF

(to core)

FF1

B

C

E

Out_QR

(to core)

CLK

CLKBUF

FF2

CLR

INBUF

DDR_IN

Figure 2-19 • Input DDR Timing Model

Table 2-101 • Parameter Definitions

Parameter Name

t_DDRICLKQ1

t_DDRICLKQ2

t_DDRISUD

Parameter Definition

Measuring Nodes (from, to)

Clock-to-Out Out_QR

Clock-to-Out Out_QF

B, D

B, E

A, B

C, D

C, E

C, B

Data Setup Time of DDR input

Data Hold Time of DDR input

Clear-to-Out Out_QR

Clear-to-Out Out_QF

Clear Removal

t_DDRIHD

t_DDRICLR2Q1

t_DDRICLR2Q2

t_DDRIREMCLR

t_DDRIRECCLR

Clear Recovery

2-76

Revision 13

ProASIC3 Flash Family FPGAs

CLK

t_DDRISUD

6

t_DDRIHD

Data

CLR

1

2

3

4

5

7

8

9

t_DDRIRECCLR

t_DDRIREMCLR

t_DDRICLKQ1

t_DDRICLR2Q1

Out_QF

Out_QR

6

7

2

4

t_DDRICLKQ2

t_DDRICLR2Q2

3

5

Figure 2-20 • Input DDR Timing Diagram

Timing Characteristics

Table 2-102 • Input DDR Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst Case VCC = 1.425 V

Parameter

t_DDRICLKQ1

t_DDRICLKQ2

t_DDRISUD

Description

–2

–1

Std. Units

Clock-to-Out Out_QR for Input DDR

Clock-to-Out Out_QF for Input DDR

Data Setup for Input DDR (Fall)

0.27

0.39

0.25

0.00

0.46

0.57

0.00

0.22

0.36

0.32

350

0.31

0.44

0.28

0.00

0.53

0.65

0.00

0.25

0.41

0.37

309

0.37

0.52

0.33

0.00

0.62

0.76

0.00

0.30

0.48

0.43

263

ns

Data Setup for Input DDR (Rise)

ns

t_DDRIHD

Data Hold for Input DDR (Fall)

ns

Data Hold for Input DDR (Rise)

ns

t_DDRICLR2Q1

t_DDRICLR2Q2

Asynchronous Clear-to-Out Out_QR for Input DDR

Asynchronous Clear-to-Out Out_QF for Input DDR

ns

t_DDRIREMCLRAsynchronous Clear Removal time for Input DDR

t_DDRIRECCLRAsynchronous Clear Recovery time for Input DDR

ns

t_DDRIWCLR

Asynchronous Clear Minimum Pulse Width for Input DDR

ns

t_DDRICKMPWHClock Minimum Pulse Width High for Input DDR

t_DDRICKMPWLClock Minimum Pulse Width Low for Input DDR

ns

F_DDRIMAX

Maximum Frequency for Input DDR

MHz

Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-77

ProASIC3 DC and Switching Characteristics

Output DDR Module

Output DDR

A

B

Data_F

(from core)

X

FF1

Out

0

1

CLK

E

X

CLKBUF

C

X

OUTBUF

D

Data_R

(from core)

X

FF2

B

X

CLR

INBUF

C

X

DDR_OUT

Figure 2-21 • Output DDR Timing Model

Table 2-103 • Parameter Definitions

Parameter Name

t_DDROCLKQ

Parameter Definition

Measuring Nodes (from, to)

Clock-to-Out

B, E

C, E

C, B

A, B

D, B

A, B

D, B

t_DDROCLR2Q

t_DDROREMCLR

t_DDRORECCLR

t_DDROSUD1

Asynchronous Clear-to-Out

Clear Removal

Clear Recovery

Data Setup Data_F

Data Setup Data_R

Data Hold Data_F

Data Hold Data_R

t_DDROSUD2

t_DDROHD1

t_DDROHD2

2-78

Revision 13

ProASIC3 Flash Family FPGAs

CLK

t

DDROHD2

DDROSUD2

4

9

5

Data_F

1

2

3

t

DDROHD1

DDROREMCLR

Data_R 6

CLR

7

8

10

11

t

DDRORECCLR

t

DDROREMCLR

t

DDROCLKQ

DDROCLR2Q

Out

7

2

8

3

9

4

10

Figure 2-22 • Output DDR Timing Diagram

Timing Characteristics

Table 2-104 • Output DDR Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_DDROCLKQ

t_DDROSUD1

t_DDROSUD2

t_DDROHD1

Description

–2

–1

Std. Units

Clock-to-Out of DDR for Output DDR

Data_F Data Setup for Output DDR

Data_R Data Setup for Output DDR

Data_F Data Hold for Output DDR

0.70 0.80 0.94

0.38 0.43 0.51

0.00 0.00 0.00

0.80 0.91 1.07

0.00 0.00 0.00

0.22 0.25 0.30

0.36 0.41 0.48

0.32 0.37 0.43

ns

t_DDROHD2

Data_R Data Hold for Output DDR

t_DDROCLR2Q

Asynchronous Clear-to-Out for Output DDR

t_DDROREMCLR

t_DDRORECCLR

t_DDROWCLR1

t_DDROCKMPWH

t_DDROCKMPWL

F_DDOMAX

Asynchronous Clear Removal Time for Output DDR

Asynchronous Clear Recovery Time for Output DDR

Asynchronous Clear Minimum Pulse Width for Output DDR

Clock Minimum Pulse Width High for the Output DDR

Clock Minimum Pulse Width Low for the Output DDR

Maximum Frequency for the Output DDR

350 309 263 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-79

ProASIC3 DC and Switching Characteristics

VersaTile Characteristics

VersaTile Specifications as a Combinatorial Module

The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing

characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO^®/e,

and ProASIC3/E Macro Library Guide.

A

Y

INV

A

B

NOR2

OR2

Y

B

A

B

A

B

Y

AND2

Y

NAND2

A

B

C

A

B

Y

XOR3

XOR2

Y

A

B

C

A

MAJ3

0

Y

A

B

C

MUX2

Y

B

S

NAND3

1

Figure 2-23 • Sample of Combinatorial Cells

2-80

Revision 13

ProASIC3 Flash Family FPGAs

t_PD

A

B

NAND2 or

Any Combinatorial

Logic

Y

t_PD= MAX(t_PD(RR), t_PD(RF), t_PD(FF), t_PD(FR)

)

where edges are applicable for the particular

combinatorial cell

VCC

50%

A, B, C

GND

50%

VCC

50%

OUT

GND

VCC

t_PD

(RR)

(FF)

t_PD

(FR)

50%

t_PD

GND

(RF)

Figure 2-24 • Timing Model and Waveforms

Revision 13

2-81

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-105 • Combinatorial Cell Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Combinatorial Cell

INV

Equation

Y = !A

Parameter

t_PD

–2

–1

Std.

0.54

0.63

0.65

0.99

0.93

1.17

0.68

0.75

Units

ns

0.40

0.47

0.49

0.74

0.70

0.87

0.51

0.56

0.46

0.54

0.55

0.84

0.79

1.00

0.58

0.64

AND2

Y = A · B

t_PD

ns

NAND2

OR2

Y = !(A · B)

Y = A + B

t_PD

ns

t_PD

ns

NOR2

Y = !(A + B)

Y = A B

Y = MAJ(A, B, C)

^{Y = A} B C

Y = A !S + B S

Y = A · B · C

t_PD

ns

XOR2

t_PD

ns

MAJ3

t_PD

ns

XOR3

t_PD

ns

MUX2

t_PD

ns

AND3

t_PD

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

VersaTile Specifications as a Sequential Module

The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a

data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a

representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E

Macro Library Guide.

Data

CLK

Out

Data

Out

D

Q

D

Q

En

DFN1

DFN1E1

CLK

PRE

Data

Out

Q

D

Q

En

DFN1C1

DFI1E1P1

CLK

CLR

Figure 2-25 • Sample of Sequential Cells

2-82

Revision 13

ProASIC3 Flash Family FPGAs

t_{CKMPWH CKMPWL}

t

50%

t_SUD

50%

CLK

t_HD

50%

Data

EN

0

50%

t_RECPRE

50%

t_WPRE

t_REMPRE

t_HE

50%

t_SUE

PRE

CLR

Out

t_REMCLR

t_RECCLR

50%

t_WCLR

50%

t_PRE2Q

50%

t_CLR2Q

50%

t_CLKQ

Figure 2-26 • Timing Model and Waveforms

Timing Characteristics

Table 2-106 • Register Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_CLKQ

Description

–2

–1 Std. Units

Clock-to-Q of the Core Register

0.55 0.63 0.74

0.43 0.49 0.57

0.00 0.00 0.00

0.45 0.52 0.61

0.00 0.00 0.00

0.40 0.45 0.53

0.00 0.00 0.00

0.22 0.25 0.30

0.00 0.00 0.00

0.22 0.25 0.30

0.32 0.37 0.43

0.36 0.41 0.48

ns

t_SUD

Data Setup Time for the Core Register

t_HD

Data Hold Time for the Core Register

t_SUE

Enable Setup Time for the Core Register

t_HE

Enable Hold Time for the Core Register

t_CLR2Q

t_PRE2Q

t_REMCLR

t_RECCLR

t_REMPRE

t_RECPRE

t_WCLR

Asynchronous Clear-to-Q of the Core Register

Asynchronous Preset-to-Q of the Core Register

Asynchronous Clear Removal Time for the Core Register

Asynchronous Clear Recovery Time for the Core Register

Asynchronous Preset Removal Time for the Core Register

Asynchronous Preset Recovery Time for the Core Register

Asynchronous Clear Minimum Pulse Width for the Core Register

Asynchronous Preset Minimum Pulse Width for the Core Register

Clock Minimum Pulse Width High for the Core Register

Clock Minimum Pulse Width Low for the Core Register

t_WPRE

t_CKMPWH

t_CKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-83

ProASIC3 DC and Switching Characteristics

Global Resource Characteristics

A3P250 Clock Tree Topology

Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing. The

global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A3P250 device. It

is used to drive all D-flip-flops in the device.

Central

Global Rib

CCC

VersaTile

Rows

Global Spine

Figure 2-27 • Example of Global Tree Use in an A3P250 Device for Clock Routing

Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not

include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven

and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer

to the "Clock Conditioning Circuits" section on page 2-89. Table 2-108 to Table 2-114 on page 2-88

present minimum and maximum global clock delays within each device. Minimum and maximum delays

are measured with minimum and maximum loading.

2-84

Revision 13

ProASIC3 Flash Family FPGAs

Timing Characteristics

Table 2-107 • A3P015 Global Resource

Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

–2

Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

–1

Std.

Parameter Description

t_RCKLInput Low Delay for Global Clock

t_RCKHInput High Delay for Global Clock

0.66 0.81 0.75 0.92 0.88 1.08

0.67 0.84 0.76 0.96 0.89 1.13

ns

t_RCKMPWHMinimum Pulse Width High for Global Clock

t_RCKMPWLMinimum Pulse Width Low for Global Clock

0.75

0.85

0.96

1.00

1.13

t_RCKSW

Maximum Skew for Global Clock

0.18

0.21

0.25

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-108 • A3P030 Global Resource

Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

–2

–1

Std.

Parameter

t_RCKL

Description

Input Low Delay for Global Clock

Input High Delay for Global Clock

Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

0.67 0.81 0.76 0.92 0.89 1.09

0.68 0.85 0.77 0.97 0.91 1.14

ns

t_RCKH

t_RCKMPWHMinimum Pulse Width High for Global Clock

t_RCKMPWLMinimum Pulse Width Low for Global Clock

0.75

0.85

0.96

1.00

1.13

t_RCKSW

Maximum Skew for Global Clock

0.18

0.21

0.24

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-85

ProASIC3 DC and Switching Characteristics

Table 2-109 • A3P060 Global Resource

Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

–2

Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

–1

Std.

Parameter

t_RCKL

Description

Input Low Delay for Global Clock

Input High Delay for Global Clock

0.71 0.93 0.81 1.05 0.95 1.24

0.70 0.96 0.80 1.09 0.94 1.28

ns

t_RCKH

t_RCKMPWHMinimum Pulse Width High for Global Clock

t_RCKMPWLMinimum Pulse Width Low for Global Clock

0.75

0.85

0.96

1.00

1.13

t_RCKSW

Maximum Skew for Global Clock

0.26

0.29

0.34

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-110 • A3P125 Global Resource

Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

–2

–1

Std.

Parameter

t_RCKL

Description

Input Low Delay for Global Clock

Input High Delay for Global Clock

Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

0.77 0.99 0.87 1.12 1.03 1.32

0.76 1.02 0.87 1.16 1.02 1.37

ns

t_RCKH

t_RCKMPWHMinimum Pulse Width High for Global Clock

t_RCKMPWLMinimum Pulse Width Low for Global Clock

0.75

0.85

0.96

1.00

1.13

t_RCKSW

Maximum Skew for Global Clock

0.26

0.29

0.34

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-86

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-111 • A3P250 Global Resource

Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

–2

–1

Std.

Parameter

t_RCKL

Description

Input Low Delay for Global Clock

Input High Delay for Global Clock

Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

0.80 1.01 0.91 1.15 1.07 1.36

0.78 1.04 0.89 1.18 1.04 1.39

ns

t_RCKH

t_RCKMPWHMinimum Pulse Width High for Global Clock

t_RCKMPWLMinimum Pulse Width Low for Global Clock

0.75

0.85

0.96

1.00

1.13

t_RCKSW

Maximum Skew for Global Clock

0.26

0.29

0.34

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-112 • A3P400 Global Resource

Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

–2

–1

Std.

Parameter

t_RCKL

Description

Input Low Delay for Global Clock

Input High Delay for Global Clock

Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

0.87 1.09 0.99 1.24 1.17 1.46

0.86 1.11 0.98 1.27 1.15 1.49

ns

t_RCKH

t_RCKMPWHMinimum Pulse Width High for Global Clock

t_RCKMPWLMinimum Pulse Width Low for Global Clock

0.75

0.85

0.96

1.00

1.13

t_RCKSW

Maximum Skew for Global Clock

0.26

0.29

0.34

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-87

ProASIC3 DC and Switching Characteristics

Table 2-113 • A3P600 Global Resource

Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

–2

–1

Std.

Parameter

t_RCKL

Description

Input Low Delay for Global Clock

Input High Delay for Global Clock

Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

0.87 1.09 0.99 1.24 1.17 1.46

0.86 1.11 0.98 1.27 1.15 1.49

ns

t_RCKH

t_RCKMPWHMinimum Pulse Width High for Global Clock

t_RCKMPWLMinimum Pulse Width Low for Global Clock

0.75

0.85

0.96

1.00

1.13

t_RCKSW

Maximum Skew for Global Clock

0.26

0.29

0.34

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-114 • A3P1000 Global Resource

Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

–2

–1

Std.

Parameter

t_RCKL

Description

Input Low Delay for Global Clock

Input High Delay for Global Clock

Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

0.94 1.16 1.07 1.32 1.26 1.55

0.93 1.19 1.06 1.35 1.24 1.59

ns

t_RCKH

t_RCKMPWHMinimum Pulse Width High for Global Clock

t_RCKMPWLMinimum Pulse Width Low for Global Clock

0.75

0.85

0.96

1.00

1.13

t_RCKSW

Maximum Skew for Global Clock

0.26

0.29

0.35

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-88

Revision 13

ProASIC3 Flash Family FPGAs

Clock Conditioning Circuits

CCC Electrical Specifications

Timing Characteristics

Table 2-115 • ProASIC3 CCC/PLL Specification

Parameter

Minimum

1.5

Typical

Maximum

350

Units

MHz

ps

Clock Conditioning Circuitry Input Frequency f_{IN_CCC}

Clock Conditioning Circuitry Output Frequency f_{OUT_CCC}

Serial Clock (SCLK) for Dynamic PLL¹

0.75

350

125

Delay Increments in Programmable Delay Blocks^{2, 3}

200⁴

Number of Programmable Values in Each Programmable

Delay Block

32

Input Period Jitter

1.5

ns

CCC Output Peak-to-Peak Period Jitter F_{CCC_OUT}

Max Peak-to-Peak Period Jitter

1 Global

Network

Used

3 Global

Networks

Used

0.75 MHz to 24 MHz

24 MHz to 100 MHz

100 MHz to 250 MHz

250 MHz to 350 MHz

Acquisition Time

0.50%

1.00%

1.75%

2.50%

0.70%

1.20%

2.00%

5.60%

(A3P250 and A3P1000 only)

LockControl = 0

LockControl = 1

LockControl = 0

LockControl = 1

300

6.0

µs

ms

(all other dies)

Tracking Jitter ⁵

(A3P250 and A3P1000 only)

LockControl = 0

LockControl = 1

LockControl = 0

LockControl = 1

1.6

ns

%

1.6

(all other dies)

1.6

0.8

Output Duty Cycle

48.5

0.6

51.5

Delay Range in Block: Programmable Delay 1^{2, 3}

Delay Range in Block: Programmable Delay 2^{2, 3}

Delay Range in Block: Fixed Delay^{2, 3}

Notes:

5.56

ns

0.225

5.56

2.2

1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction

temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 for deratings.

3. T = 25°C, VCC = 1.5 V

J

4. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay

increments are available. Refer to the Libero SoC Online Help for more information.

5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock

edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter

parameter.

6. The A3P030 device does not contain a PLL.

Revision 13

2-89

ProASIC3 DC and Switching Characteristics

Output Signal

T_{period_max}

T_{period_min}

Note: Peak-to-peak jitter measurements are defined by T_peak-to-peak= T_{period_max}– T_{period_min}

.

Figure 2-28 • Peak-to-Peak Jitter Definition

2-90

Revision 13

ProASIC3 Flash Family FPGAs

Embedded SRAM and FIFO Characteristics

SRAM

RAM4K9

RAM512X18

RADDR8

RADDR7

RD17

RD16

ADDRA11 DOUTA8

DOUTA7

DOUTA0

ADDRA10

ADDRA0

DINA8

RADDR0

RD0

DINA7

RW1

RW0

DINA0

WIDTHA1

WIDTHA0

PIPEA

PIPE

WMODEA

BLKA

WENA

REN

RCLK

CLKA

ADDRB11 DOUTB8

ADDRB10 DOUTB7

WADDR8

WADDR7

ADDRB0

DOUTB0

WADDR0

WD17

WD16

DINB8

DINB7

WD0

DINB0

WW1

WW0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WEN

WCLK

WENB

CLKB

RESET

Figure 2-29 • RAM Models

Revision 13

2-91

ProASIC3 DC and Switching Characteristics

Timing Waveforms

t_CYC

t_CKH

t_CKL

CLK

[R|W]ADDR

BLK

t_AS

t_BKS

t_ENS

t

AH

A

2

0

1

t_BKH

t_ENH

WEN

t_CKQ1

D_n

D₀

D₁

D₂

DOUT|RD

t_DOH1

Figure 2-30 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18.

t_CYC

t_CKH

t_CKL

CLK

[R|W]ADDR

BLK

t

t_AH

AS

A

2

0

1

t_BKS

t_BKH

t_ENH

t_ENS

WEN

t_CKQ2

D_n

D₀

D₁

DOUT|RD

t_DOH2

Figure 2-31 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18.

2-92

Revision 13

ProASIC3 Flash Family FPGAs

t_CYC

t_CKH

t_CKL

CLK

[R|W]ADDR

BLK

t_AS

t_AH

A₀

t_BKS

A₁

A₂

t_BKH

t_ENS

t_ENH

WEN

t_DS

t_DH

DI₁

DI₀

DIN|RD

D_n

D₂

DOUT|RD

Figure 2-32 • RAM Write, Output Retained. Applicable to Both RAM4K9 and RAM512x18.

t_CYC

t_CKH

t_CKL

CLK

ADDR

BLK

t_ASt_AH

A₀

t_BKS

A₁

A₂

t_BKH

t_ENS

WEN

DIN

t_DSt_DH

DI₁

DI₀

DI₂

DOUT

D_n

DI₀

DI₁

(pass-through)

DOUT

DI₀

D_n

DI₁

(pipelined)

Figure 2-33 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 Only.

Revision 13

2-93

ProASIC3 DC and Switching Characteristics

t

CYC

t

CKL

CKH

CLK

RESET

t

RSTBQ

D

DOUT|RD

m

n

Figure 2-34 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18.

Timing Characteristics

Table 2-116 • RAM4K9

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_AS

Description

Address setup time

–2

–1 Std. Units

0.25 0.28 0.33

0.00 0.00 0.00

0.14 0.16 0.19

0.10 0.11 0.13

0.23 0.27 0.31

0.02 0.02 0.02

0.18 0.21 0.25

0.00 0.00 0.00

2.36 2.68 3.15

1.79 2.03 2.39

0.89 1.02 1.20

ns

t_AH

Address hold time

t_ENS

t_ENH

t_BKS

t_BKH

t_DS

REN, WEN setup time

REN, WEN hold time

BLK setup time

BLK hold time

Input data (DIN) setup time

t_DH

Input data (DIN) hold time

t_CKQ1

Clock High to new data valid on DOUT (output retained, WMODE = 0)

Clock High to new data valid on DOUT (flow-through, WMODE = 1)

Clock High to new data valid on DOUT (pipelined)

t_CKQ2

1

t_C2CWWL

Address collision clk-to-clk delay for reliable write after write on same 0.33 0.28 0.25

address—Applicable to Closing Edge

1

t_C2CWWH

Address collision clk-to-clk delay for reliable write after write on same 0.30 0.26 0.23

address—Applicable to Rising Edge

ns

1

t_C2CRWH

Address collision clk-to-clk delay for reliable read access after write on same 0.45 0.38 0.34

address—Applicable to Opening Edge

1

t_C2CWRH

Address collision clk-to-clk delay for reliable write access after read on same 0.49 0.42 0.37

address— Applicable to Opening Edge

t_RSTBQ

RESET Low to data out Low on DOUT (flow-through)

RESET Low to Data Out Low on DOUT (pipelined)

RESET removal

0.92 1.05 1.23

0.29 0.33 0.38

ns

t_REMRSTB

Notes:

1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-94

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-116 • RAM4K9

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V (continued)

Parameter

t_RECRSTB

t_MPWRSTB

t_CYC

Description –2

–1 Std. Units

RESET recovery

1.50 1.71 2.01

0.21 0.24 0.29

3.23 3.68 4.32

ns

RESET minimum pulse width

Clock cycle time

F_MAX

Maximum frequency

310 272 231 MHz

Notes:

1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-95

ProASIC3 DC and Switching Characteristics

Table 2-117 • RAM512X18

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_AS

Description

–2

–1 Std. Units

Address setup time

0.25 0.28 0.33

0.00 0.00 0.00

0.13 0.15 0.17

0.10 0.11 0.13

0.18 0.21 0.25

0.00 0.00 0.00

2.16 2.46 2.89

0.90 1.02 1.20

ns

t_AH

Address hold time

t_ENS

REN, WEN setup time

REN, WEN hold time

Input data (WD) setup time

Input data (WD) hold time

t_ENH

t_DS

t_DH

t_CKQ1

t_CKQ2

Clock High to new data valid on RD (output retained)

Clock High to new data valid on RD (pipelined)

1

t_C2CRWH

Address collision clk-to-clk delay for reliable read access after write on same 0.50 0.43 0.38

address—Applicable to Opening Edge

1

t_C2CWRH

Address collision clk-to-clk delay for reliable write access after read on same 0.59 0.50 0.44

address—Applicable to Opening Edge

ns

t_RSTBQ

RESET Low to data out Low on RD (flow-through)

RESET Low to data out Low on RD (pipelined)

RESET removal

0.92 1.05 1.23

0.29 0.33 0.38

1.50 1.71 2.01

0.21 0.24 0.29

3.23 3.68 4.32

ns

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET recovery

RESET minimum pulse width

Clock cycle time

F_MAX

Maximum frequency

310 272 231 MHz

Notes:

1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-96

Revision 13

ProASIC3 Flash Family FPGAs

FIFO

FIFO4K18

RW2

RW1

RW0

RD17

RD16

WW2

WW1

WW0

RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AEVAL11

AEVAL10

AEMPTY

AEVAL0

AFVAL11

AFVAL10

AFVAL0

REN

RBLK

RCLK

WD17

WD16

WD0

WEN

WBLK

WCLK

RPIPE

RESET

Figure 2-35 • FIFO Model

Revision 13

2-97

ProASIC3 DC and Switching Characteristics

Timing Waveforms

t_CYC

RCLK

t_ENH

t_ENS

REN

t_BKS

t_BKH

RBLK

t_CKQ1

RD

D₁

D_n

D₀

D₂

(flow-through)

t_CKQ2

RD

(pipelined)

D_n

D₀

D₁

Figure 2-36 • FIFO Read

t_CYC

WCLK

t_ENS

t_ENH

WEN

t_BKS

t_BKH

WBLK

t_DS

t_DH

DI₁

DI₀

WD

Figure 2-37 • FIFO Write

2-98

Revision 13

ProASIC3 Flash Family FPGAs

RCLK/

WCLK

t_MPWRSTB

t_RSTCK

RESET

EMPTY

AEMPTY

FULL

t_RSTFG

t_RSTAF

t_RSTFG

t_RSTAF

AFULL

WA/RA

MATCH (A₀)

(Address Counter)

Figure 2-38 • FIFO Reset

t_CYC

RCLK

t_RCKEF

EMPTY

t_CKAF

AEMPTY

WA/RA

NO MATCH

Dist = AEF_TH

MATCH (EMPTY)

(Address Counter)

Figure 2-39 • FIFO EMPTY Flag and AEMPTY Flag Assertion

Revision 13

2-99

ProASIC3 DC and Switching Characteristics

t_CYC

WCLK

FULL

t_WCKFF

t_CKAF

AFULL

WA/RA

NO MATCH

Dist = AFF_TH

MATCH (FULL)

(Address Counter)

Figure 2-40 • FIFO FULL Flag and AFULL Flag Assertion

WCLK

MATCH

WA/RA

NO MATCH

2nd Rising

Edge

After 1st

Write

NO MATCH

Dist = AEF_TH + 1

(Address Counter)

(EMPTY)

1st Rising

Edge

After 1st

Write

RCLK

EMPTY

t

RCKEF

t

CKAF

AEMPTY

Figure 2-41 • FIFO EMPTY Flag and AEMPTY Flag Deassertion

RCLK

WA/RA

(Address Counter)

Dist = AFF_TH – 1

MATCH (FULL)

1st Rising

NO MATCH

1st Rising

Edge

After 2nd

Read

NO MATCH

Edge

After 1st

Read

WCLK

FULL

t_WCKF

t_CKAF

AFULL

Figure 2-42 • FIFO FULL Flag and AFULL Flag Deassertion

2-100

Revision 13

ProASIC3 Flash Family FPGAs

Timing Characteristics

Table 2-118 • FIFO (for all dies except A3P250)

Worst Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

Parameter

t_ENS

Description

–2

–1

Std. Units

REN, WEN Setup Time

REN, WEN Hold Time

BLK Setup Time

1.34 1.52 1.79

0.00 0.00 0.00

0.19 0.22 0.26

0.00 0.00 0.00

0.18 0.21 0.25

0.00 0.00 0.00

2.17 2.47 2.90

0.94 1.07 1.26

1.72 1.96 2.30

1.63 1.86 2.18

6.19 7.05 8.29

1.69 1.93 2.27

6.13 6.98 8.20

0.92 1.05 1.23

0.29 0.33 0.38

1.50 1.71 2.01

0.21 0.24 0.29

3.23 3.68 4.32

ns

MHz

t_ENH

t_BKS

t_BKH

BLK Hold Time

t_DS

Input Data (WD) Setup Time

Input Data (WD) Hold Time

t_DH

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock High to New Data Valid on RD (flow-through)

Clock High to New Data Valid on RD (pipelined)

RCLK High to Empty Flag Valid

WCLK High to Full Flag Valid

Clock High to Almost Empty/Full Flag Valid

RESET Low to Empty/Full Flag Valid

RESET Low to Almost Empty/Full Flag Valid

RESET Low to Data Out Low on RD (flow-through)

RESET Low to Data Out Low on RD (pipelined)

RESET Removal

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET Recovery

RESET Minimum Pulse Width

Clock Cycle Time

F_MAX

Maximum Frequency for FIFO

310

272

231

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-101

ProASIC3 DC and Switching Characteristics

Table 2-119 • FIFO (for A3P250 only, aspect-ratio-dependent)

Worst Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

Parameter

t_ENS

Description

–2

–1

Std. Units

REN, WEN Setup Time

REN, WEN Hold Time

BLK Setup Time

3.26 3.71 4.36

0.00 0.00 0.00

0.19 0.22 0.26

0.00 0.00 0.00

0.18 0.21 0.25

0.00 0.00 0.00

2.17 2.47 2.90

0.94 1.07 1.26

1.72 1.96 2.30

1.63 1.86 2.18

6.19 7.05 8.29

1.69 1.93 2.27

6.13 6.98 8.20

0.92 1.05 1.23

0.29 0.33 0.38

1.50 1.71 2.01

0.21 0.24 0.29

3.23 3.68 4.32

ns

MHz

t_ENH

t_BKS

t_BKH

BLK Hold Time

t_DS

Input Data (WD) Setup Time

Input Data (WD) Hold Time

t_DH

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock High to New Data Valid on RD (flow-through)

Clock High to New Data Valid on RD (pipelined)

RCLK High to Empty Flag Valid

WCLK High to Full Flag Valid

Clock High to Almost Empty/Full Flag Valid

RESET Low to Empty/Full Flag Valid

RESET Low to Almost Empty/Full Flag Valid

RESET Low to Data Out Low on RD (flow-through)

RESET Low to Data Out Low on RD (pipelined)

RESET Removal

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET Recovery

RESET Minimum Pulse Width

Clock Cycle Time

F_MAX

Maximum Frequency for FIFO

310

272

231

2-102

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-120 • A3P250 FIFO 512×8

Worst Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

Parameter

t_ENS

Description

–2

–1

Std. Units

REN, WEN Setup Time

REN, WEN Hold Time

BLK Setup Time

3.75 4.27 5.02

0.00 0.00 0.00

0.19 0.22 0.26

0.00 0.00 0.00

0.18 0.21 0.25

0.00 0.00 0.00

2.17 2.47 2.90

0.94 1.07 1.26

1.72 1.96 2.30

1.63 1.86 2.18

6.19 7.05 8.29

1.69 1.93 2.27

6.13 6.98 8.20

0.92 1.05 1.23

0.29 0.33 0.38

1.50 1.71 2.01

0.21 0.24 0.29

3.23 3.68 4.32

ns

MHz

t_ENH

t_BKS

t_BKH

BLK Hold Time

t_DS

Input Data (WD) Setup Time

Input Data (WD) Hold Time

t_DH

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock High to New Data Valid on RD (flow-through)

Clock High to New Data Valid on RD (pipelined)

RCLK High to Empty Flag Valid

WCLK High to Full Flag Valid

Clock High to Almost Empty/Full Flag Valid

RESET Low to Empty/Full Flag Valid

RESET Low to Almost Empty/Full Flag Valid

RESET Low to Data Out Low on RD (flow-through)

RESET Low to Data Out Low on RD (pipelined)

RESET Removal

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET Recovery

RESET Minimum Pulse Width

Clock Cycle Time

F_MAX

Maximum Frequency for FIFO

310

272

231

Revision 13

2-103

ProASIC3 DC and Switching Characteristics

Table 2-121 • A3P250 FIFO 1k×4

Worst Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

Parameter

t_ENS

Description

–2

–1

Std.

5.42

0.00

0.26

0.00

0.25

0.00

3.15

1.20

2.30

2.18

8.29

2.27

8.20

1.23

0.38

2.01

0.29

4.32

231

Units

ns

REN, WEN Setup Time

REN, WEN Hold Time

BLK Setup Time

4.05

0.00

0.19

0.00

0.18

0.00

2.36

0.89

1.72

1.63

6.19

1.69

6.13

0.92

0.29

1.50

0.21

3.23

310

4.61

0.00

0.22

0.00

0.21

0.00

2.68

1.02

1.96

1.86

7.05

1.93

6.98

1.05

0.33

1.71

0.24

3.68

272

t_ENH

ns

t_BKS

ns

t_BKH

BLK Hold Time

ns

t_DS

Input Data (WD) Setup Time

ns

t_DH

Input Data (WD) Hold Time

ns

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock High to New Data Valid on RD (flow-through)

Clock High to New Data Valid on RD (pipelined)

RCLK High to Empty Flag Valid

WCLK High to Full Flag Valid

ns

Clock High to Almost Empty/Full Flag Valid

RESET Low to Empty/Full Flag Valid

RESET Low to Almost Empty/Full Flag Valid

RESET Low to Data Out Low on RD (flow-through)

RESET Low to Data Out Low on RD (pipelined)

RESET Removal

ns

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

ns

RESET Recovery

ns

RESET Minimum Pulse Width

ns

Clock Cycle Time

ns

F_MAX

Maximum Frequency for FIFO

MHz

2-104

Revision 13

ProASIC3 Flash Family FPGAs

Table 2-122 • A3P250 FIFO 2k×2

Worst Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

Parameter

t_ENS

Description

–2

–1

Std.

5.88

0.00

0.26

0.00

0.25

0.00

3.15

1.20

2.30

2.18

8.29

2.27

8.20

1.23

0.38

2.01

0.29

4.32

231

Units

ns

REN, WEN Setup Time

REN, WEN Hold Time

BLK Setup Time

4.39

0.00

0.19

0.00

0.18

0.00

2.36

0.89

1.72

1.63

6.19

1.69

6.13

0.92

0.29

1.50

0.21

3.23

310

5.00

0.00

0.22

0.00

0.21

0.00

2.68

1.02

1.96

1.86

7.05

1.93

6.98

1.05

0.33

1.71

0.24

3.68

272

t_ENH

ns

t_BKS

ns

t_BKH

BLK Hold Time

ns

t_DS

Input Data (WD) Setup Time

ns

t_DH

Input Data (WD) Hold Time

ns

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock High to New Data Valid on RD (flow-through)

Clock High to New Data Valid on RD (pipelined)

RCLK High to Empty Flag Valid

WCLK High to Full Flag Valid

ns

Clock High to Almost Empty/Full Flag Valid

RESET Low to Empty/Full Flag Valid

RESET Low to Almost Empty/Full Flag Valid

RESET Low to Data Out Low on RD (flow-through)

RESET Low to Data Out Low on RD (pipelined)

RESET Removal

ns

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

ns

RESET Recovery

ns

RESET Minimum Pulse Width

ns

Clock Cycle Time

ns

F_MAX

Maximum Frequency for FIFO

MHz

Revision 13

2-105

ProASIC3 DC and Switching Characteristics

Table 2-123 • A3P250 FIFO 4k×1

Worst Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

Parameter

t_ENS

Description

–2

–1

Std.

6.50

0.00

0.26

0.00

0.25

0.00

3.15

1.20

2.30

2.18

8.29

2.27

8.20

1.23

0.38

2.01

0.29

4.32

231

Units

ns

REN, WEN Setup Time

REN, WEN Hold Time

BLK Setup Time

4.86

0.00

0.19

0.00

0.18

0.00

2.36

0.89

1.72

1.63

6.19

1.69

6.13

0.92

0.29

1.50

0.21

3.23

310

5.53

0.00

0.22

0.00

0.21

0.00

2.68

1.02

1.96

1.86

7.05

1.93

6.98

1.05

0.33

1.71

0.24

3.68

272

t_ENH

ns

t_BKS

ns

t_BKH

BLK Hold Time

ns

t_DS

Input Data (WD) Setup Time

ns

t_DH

Input Data (WD) Hold Time

ns

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock High to New Data Valid on RD (flow-through)

Clock High to New Data Valid on RD (pipelined)

RCLK High to Empty Flag Valid

WCLK High to Full Flag Valid

ns

Clock High to Almost Empty/Full Flag Valid

RESET Low to Empty/Full Flag Valid

RESET Low to Almost Empty/Full Flag Valid

RESET Low to Data Out Low on DO (pass-through)

RESET Low to Data Out Low on DO (pipelined)

RESET Removal

ns

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

ns

RESET Recovery

ns

RESET Minimum Pulse Width

ns

Clock Cycle Time

ns

F_MAX

Maximum Frequency

MHz

2-106

Revision 13

ProASIC3 Flash Family FPGAs

Embedded FlashROM Characteristics

t_SU

CLK

t_HOLD

Address

A₀

A₁

t_CKQ2

D₀

t_CKQ2

D₁

D₀

Data

Figure 2-43 • Timing Diagram

Timing Characteristics

Table 2-124 • Embedded FlashROM Access Time

Parameter

t_SU

Description

Address Setup Time

–2

0.53

0.00

21.42

15

–1

Std.

0.71

0.00

28.68

15

Units

ns

0.61

0.00

24.40

15

t_HOLD

t_CK2Q

Address Hold Time

Clock to Out

ns

F_MAX

Maximum Clock Frequency

MHz

Revision 13

2-107

ProASIC3 DC and Switching Characteristics

JTAG 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to

the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O

Characteristics" section on page 2-14 for more details.

Timing Characteristics

Table 2-125 • JTAG 1532

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_DISU

Description

Test Data Input Setup Time

Test Data Input Hold Time

Test Mode Select Setup Time

Test Mode Select Hold Time

Clock to Q (data out)

–2

–1

Std.

0.67

1.33

0.67

1.33

8.00

26.67

19.00

0.00

0.27

TBD

Units

ns

0.50

1.00

0.50

1.00

6.00

20.00

25.00

0.00

0.20

TBD

0.57

1.13

0.57

1.13

6.80

22.67

22.00

0.00

0.23

TBD

t_DIHD

ns

t_TMSSU

ns

t_TMDHD

ns

t_TCK2Q

ns

t_RSTB2Q

F_TCKMAX

t_TRSTREM

t_TRSTREC

t_TRSTMPW

Reset to Q (data out)

ns

TCK Maximum Frequency

ResetB Removal Time

MHz

ns

ResetB Recovery Time

ResetB Minimum Pulse

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for

derating values.

2-108

Revision 13

3 – Pin Descriptions

Supply Pins

GND

Ground supply voltage to the core, I/O outputs, and I/O logic.

GNDQ Ground (quiet)

Ground

Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is

decoupled from the simultaneous switching noise originated from the output buffer ground domain. This

minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always

be connected to GND on the board.

VCC

Core Supply Voltage

Supply voltage to the FPGA core, nominally 1.5 V. VCC is required for powering the JTAG state machine

in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices,

both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device.

VCCIBx

I/O Supply Voltage

Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to

eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a

separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V,

1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied

to GND.

VMVx

I/O Supply Voltage (quiet)

Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the

VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within

the package and improves input signal integrity. Each bank must have at least one VMV connection, and

no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to

provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or

3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV

and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to

the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).

VCCPLA/B/C/D/E/F PLL Supply Voltage

Supply voltage to analog PLL, nominally 1.5 V.

When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs

to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground.

Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise

from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in

IGLOO and ProASIC3 Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for a complete

board solution for the PLL analog power supply and ground.

There is one VCCPLF pin on ProASIC3 devices.

VCOMPLA/B/C/D/E/F PLL Ground

Ground to analog PLL power supplies. When the PLLs are not used, the Designer place-and-route tool

automatically disables the unused PLLs to lower power consumption. The user should tie unused

VCCPLx and VCOMPLx pins to ground.

There is one VCOMPLF pin on ProASIC3 devices.

VJTAG

JTAG Supply Voltage

Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run

at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank

gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG

interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to

GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is

Revision 13

3-1

Pin Descriptions

insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can

be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals

will not be able to transition the device, even in bypass mode.

Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent

filtering capacitors rather than supplying them from a common rail.

VPUMP

Programming Supply Voltage

ProASIC3 devices support single-voltage ISP of the configuration flash and FlashROM. For

programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left

floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming

power supply voltage (VPUMP) range is listed in Table 2-2 on page 2-2.

When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of

oscillation from the charge pump circuitry.

For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in

parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.

Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent

filtering capacitors rather than supplying them from a common rail.

User Pins

I/O

User Input/Output

The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are

compatible with the I/O standard selected.

During programming, I/Os become tristated and weakly pulled up to V_CCI. With V_CCI, VMV, and V_CC

supplies continuously powered up, when the device transitions from programming to operating mode, the

I/Os are instantly configured to the desired user configuration.

Unused I/Os are configured as follows:

•

Output buffer is disabled (with tristate value of high impedance)

Input buffer is disabled (with tristate value of high impedance)

Weak pull-up is programmed

GL

Globals

GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the

global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have

identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.

See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in IGLOO

and ProASIC3 Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide. All inputs labeled GC/GF

are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2

are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into

the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global

network are multiplexed, and only one input can be used as a global input.

Refer to the I/O Structure section of the handbook for the device you are using for an explanation of the

naming of global pins.

FF

Flash*Freeze Mode Activation Pin

Flash*Freeze is available on IGLOO, ProASIC3L, and RT ProASIC3 devices. It is not supported on

ProASIC3/E devices. The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The

FF pin is active-low, has the same characteristics as a single-ended I/O, and must meet the maximum

rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a

regular I/O. For IGLOOe, ProASIC3EL, and RT ProASIC3 only, the FF pin can be configured as a

Schmitt trigger input.

When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering

Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.

The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in

which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin

3-2

Revision 13

ProASIC3 Flash Family FPGAs

should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,

simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be

considered.

Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both

Flash*Freeze mode and normal operation mode. No user intervention is required.

JTAG Pins

Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run

at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to

operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the

part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a

separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB

design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST

pin could be tied to GND.

TCK

Test Clock

Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-

up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor

placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.

Note that to operate at all VJTAG voltages, 500  to 1 k will satisfy the requirements. Refer to Table 1

for more information.

Table 1 • Recommended Tie-Off Values for the TCK and TRST Pins

VJTAG

Tie-Off Resistance

200  to 1 k

500  to 1 k

VJTAG at 3.3 V

VJTAG at 2.5 V

VJTAG at 1.8 V

VJTAG at 1.5 V

Notes:

1. Equivalent parallel resistance if more than one device is on the JTAG chain

2. The TCK pin can be pulled up/down.

3. The TRST pin is pulled down.

TDI

Test Data Input

Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor

on the TDI pin.

TDO

Serial output for JTAG boundary scan, ISP, and UJTAG usage.

TMS Test Mode Select

Test Data Output

The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an

internal weak pull-up resistor on the TMS pin.

TRST

Boundary Scan Reset Pin

The TRST pin functions as an active low input to asynchronously initialize (or reset) the boundary scan

circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-

down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor

values must be chosen from Table 1 and must satisfy the parallel resistance value requirement. The

values in Table 1 correspond to the resistor recommended when a single device is used, and the

equivalent parallel resistor when multiple devices are connected via a JTAG chain.

In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In

such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA

pin.

Note that to operate at all VJTAG voltages, 500  to 1 k will satisfy the requirements.

Revision 13

3-3

Pin Descriptions

Special Function Pins

NC

No Connect

This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be

left floating with no effect on the operation of the device.

DC

Do Not Connect

This pin should not be connected to any signals on the PCB. These pins should be left unconnected.


型号：	A3P030-CSG100YPP
厂家：	Microsemi
描述：	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support 闪光的ProASIC3系列FPGA具有可选的软ARM支持
文件：	总220页 (文件大小：10669K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A3P030-CSG100YPP [MICROSEMI]

相关型号：

A3P030-CSG144

A3P030-CSG144ES

A3P030-CSG144I

A3P030-CSG144PP

A3P030-CSG144Y

A3P030-CSG144YES

A3P030-CSG144YI

A3P030-CSG144YPP

A3P030-FFG144

A3P030-FFG144ES

A3P030-FFG144I

A3P030-FFG144PP