PZ28F032M29EWXX [MICRON]
Parallel NOR Flash Embedded Memory;
| 型号： | PZ28F032M29EWXX |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | Parallel NOR Flash Embedded Memory |
| 文件： | 总87页 (文件大小：1118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Features
Parallel NOR Flash Embedded Memory
JR28F032M29EWXX; PZ28F032M29EWXX; JS28F064M29EWXX
PC28F064M29EWXX; JR28F064M29EWXX; PZ28F064M29EWXX
JS28F128M29EWXX; PC28F128M29EWXX; RC28F128M29EWXX
• VPP/WP# pin protection
– VPPH voltage on VPP to accelerate programming
Features
• Supply voltage
– VCC = 2.7–3.6V (program, erase, read)
– VCCQ = 1.65–3.6V (I/O buffers)
• Asynchronous random or page read
– Page size: 8 words or 16 bytes
performance
– Protects highest/lowest block (H/L uniform) or
top/bottom two blocks (T/B boot)
• Software protection
– Volatile protection
– Nonvolatile protection
– Page access: 25ns
– Random access: 60ns (BGA); 70ns (TSOP)
• Buffer program: 256-word MAX program buffer
• Program time
– Password protection
– Password access
• Extended memory block
– 0.56µs per byte (1.8 MB/s TYP when using 256-
word buffer size in buffer program without VPPH
– 0.31µs per byte (3.2 MB/s TYP when using 256-
– 128-word (256-byte) block for permanent secure
identification
– Program or lock implemented at the factory or by
the customer
• Low-power consumption: Standby mode
• JESD47H-compliant
– 100,000 minimum ERASE cycles per block
– Data retention: 20 years (TYP)
• 65nm single-bit cell process technology
• Packages (JEDEC-standard)
– 56-pin TSOP (128Mb, 64Mb)
– 48-pin TSOP (64Mb, 32Mb)
– 64-ball FBGA (128Mb, 64Mb)
– 48-ball BGA (64Mb, 32Mb)
• Green packages available
– RoHS-compliant
)
word buffer size in buffer program with VPPH
• Memory organization
)
– 32Mb: 64 main blocks, 64KB each, or eight 8KB
boot blocks (top or bottom) and 63 main blocks,
64KB each
– 64Mb: 128 main blocks, 64KB each, or eight 8KB
boot blocks (top or bottom) and 127 main blocks,
64 KB each
– 128Mb: 128 main blocks, 128KB each
• Program/erase controller
– Embedded byte/word program algorithms
• Program/erase suspend and resume capability
– READ operation on any block during a PRO-
GRAM SUSPEND operation
– Halogen-free
– READ or PROGRAM operation on one block dur-
ing an ERASE SUSPEND operation on another
block
• Operating temperature
– Ambient: –40°C to +85°C
• BLANK CHECK operation to verify an erased block
• Unlock bypass, block erase, chip erase, and write to
buffer capability
– Fast buffered/batch programming
– Fast block and chip erase
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
© 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Features
Part Numbering Information
This product is available with the prelocked extended memory block. Devices are shipped from the factory with
memory content bits erased to 1. For a list of available options, such as packages or high/low protection, or for
further information, contact your Micron sales representative.
Table 1: Part Number Information
Part Number
Category
Category Details
Package
JS = 56-pin TSOP, 14mm x 20mm, lead-free, halogen-free, RoHS-compliant
PC = 64-ball Fortified BGA, 11mm x 13mm, lead-free, halogen-free, RoHS-compliant
RC = 64-ball Fortified BGA, 11mm x 13mm, leaded
JR = 48-pin TSOP, 12mm x 20mm, lead-free, halogen-free, RoHS-compliant
PZ = 48-ball BGA, 6mm x 8mm, lead-free, halogen-free, RoHS-compliant
28F = Parallel NOR interface
Product designator
Density
128 = 128Mb
064 = 64Mb
032 = 32Mb
Device type
M29EW = Embedded Flash memory (3V core, page read)
H = Highest block protected by VPP/WP#; uniform block
L = Lowest block protected by VPP/WP#; uniform block
B = Bottom boot; bottom two blocks protected by VPP/WP#
T = Top boot; top two blocks protected by VPP/WP#
Device function
Features
A/B/F/X or an asterisk (*) = Combination of features, including packing media, security features,
and specific customer request information
Valid M29EW Part Number Combinations
Table 2: Standard Part Numbers by Density, Medium, and Package
Package
JS
PC
RC
JR
PZ
32Mb Tray
–
–
–
JR28F032M29EWHA PZ28F032M29EWHA
JR28F032M29EWLA PZ28F032M29EWLA
JR28F032M29EWBA PZ28F032M29EWBA
JR28F032M29EWTA PZ28F032M29EWTA
JR28F032M29EWBB PZ28F032M29EWBB
JR28F032M29EWTB
Tape
and
reel
–
–
–
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
© 2012 Micron Technology, Inc. All rights reserved.
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Features
Table 2: Standard Part Numbers by Density, Medium, and Package (Continued)
Package
JS
PC
RC
JR
PZ
64Mb Tray JS28F064M29EWHA PC28F064M29EWHA
JS28F064M29EWLA PC28F064M29EWLA
JS28F064M29EWBA PC28F064M29EWBA
JS28F064M29EWTA PC28F064M29EWTA
–
JR28F064M29EWHA PZ28F064M29EWHA
JR28F064M29EWLA PZ28F064M29EWLA
JR28F064M29EWBA PZ28F064M29EWBA
JR28F064M29EWTA PZ28F064M29EWTA
JR28F064M29EWHB PZ28F064M29EWBB
JR28F064M29EWLB
Tape JS28F064M29EWLB
–
–
and
reel
JR28F064M29EWTB
128Mb Tray JS28F128M29EWHF PC28F128M29EWHF RC28F128M29EWHF
JS28F128M29EWLA PC28F128M29EWLA RC28F128M29EWLA
–
–
–
Tape
and
reel
–
–
–
–
Table 3: Part Numbers with Security Features by Density, Medium, and Package
Package
Density
Medium
PC
PZ
64Mb
Tray
PC28F064M29EWHX
PC28F064M29EWLX
PC28F064M29EWBX
PC28F064M29EWTX
PC28F064M29EWTY
PC28F128M29EWHX
PC28F128M29EWLX
–
PZ28F064M29EWHX
PZ28F064M29EWLX
PZ28F064M29EWBX
PZ28F064M29EWTX
Tape and Reel
Tray
–
–
128Mb
Tape and Reel
–
1. This data sheet covers only standard parts. For security parts, contact your local Micron sales representative.
Note:
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2012 Micron Technology, Inc. All rights reserved.
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Features
Contents
General Description ......................................................................................................................................... 8
Signal Assignments ........................................................................................................................................... 9
Signal Descriptions ......................................................................................................................................... 13
Memory Organization .................................................................................................................................... 14
Memory Configuration ............................................................................................................................... 14
Memory Map – 32Mb ................................................................................................................................. 15
Memory Map – 64Mb ................................................................................................................................. 17
Memory Map – 128Mb ................................................................................................................................ 19
Bus Operations ............................................................................................................................................... 20
Read .......................................................................................................................................................... 20
Write .......................................................................................................................................................... 20
Standby ..................................................................................................................................................... 20
Output Disable ........................................................................................................................................... 21
Reset .......................................................................................................................................................... 21
Registers ........................................................................................................................................................ 22
Status Register ............................................................................................................................................ 22
Lock Register .............................................................................................................................................. 27
Standard Command Definitions – Address-Data Cycles .................................................................................... 30
READ and AUTO SELECT Operations .............................................................................................................. 33
READ/RESET Command ............................................................................................................................ 33
READ CFI Command .................................................................................................................................. 33
AUTO SELECT Command ........................................................................................................................... 33
Bypass Operations .......................................................................................................................................... 35
UNLOCK BYPASS Command ...................................................................................................................... 35
UNLOCK BYPASS RESET Command ............................................................................................................ 36
Program Operations ....................................................................................................................................... 36
PROGRAM Command ................................................................................................................................ 36
UNLOCK BYPASS PROGRAM Command ..................................................................................................... 37
DOUBLE BYTE/WORD PROGRAM Command ............................................................................................. 37
QUADRUPLE BYTE/WORD PROGRAM Command ...................................................................................... 37
OCTUPLE BYTE PROGRAM Command ....................................................................................................... 38
WRITE TO BUFFER PROGRAM Command .................................................................................................. 38
UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command ....................................................................... 40
ENHANCED WRITE TO BUFFER PROGRAM Command ............................................................................... 41
UNLOCK BYPASS ENHANCED WRITE TO BUFFER PROGRAM Command ................................................... 41
WRITE TO BUFFER PROGRAM CONFIRM Command .................................................................................. 42
ENHANCED WRITE TO BUFFER PROGRAM CONFIRM Command .............................................................. 42
BUFFERED PROGRAM ABORT AND RESET Command ................................................................................ 42
PROGRAM SUSPEND Command ................................................................................................................ 42
PROGRAM RESUME Command .................................................................................................................. 43
Erase Operations ............................................................................................................................................ 43
CHIP ERASE Command .............................................................................................................................. 43
UNLOCK BYPASS CHIP ERASE Command ................................................................................................... 43
BLOCK ERASE Command ........................................................................................................................... 44
UNLOCK BYPASS BLOCK ERASE Command ................................................................................................ 44
ERASE SUSPEND Command ....................................................................................................................... 44
ERASE RESUME Command ........................................................................................................................ 45
BLANK CHECK Operation .............................................................................................................................. 45
BLANK CHECK Commands ........................................................................................................................ 45
Block Protection Command Definitions – Address-Data Cycles ........................................................................ 47
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2012 Micron Technology, Inc. All rights reserved.
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Features
Protection Operations .................................................................................................................................... 50
LOCK REGISTER Commands ...................................................................................................................... 50
PASSWORD PROTECTION Commands ....................................................................................................... 50
NONVOLATILE PROTECTION Commands .................................................................................................. 50
NONVOLATILE PROTECTION BIT LOCK BIT Commands ............................................................................ 53
VOLATILE PROTECTION Commands .......................................................................................................... 53
EXTENDED MEMORY BLOCK Commands .................................................................................................. 53
EXIT PROTECTION Command .................................................................................................................... 54
Device Protection ........................................................................................................................................... 55
Hardware Protection .................................................................................................................................. 55
Software Protection .................................................................................................................................... 55
Volatile Protection Mode ............................................................................................................................. 56
Nonvolatile Protection Mode ...................................................................................................................... 56
Password Protection Mode .......................................................................................................................... 57
Password Access ......................................................................................................................................... 57
Common Flash Interface ................................................................................................................................ 59
Power-Up and Reset Characteristics ................................................................................................................ 64
Absolute Ratings and Operating Conditions ..................................................................................................... 66
DC Characteristics .......................................................................................................................................... 68
Read AC Characteristics .................................................................................................................................. 70
Write AC Characteristics ................................................................................................................................. 73
Accelerated Program, Data Polling/Toggle AC Characteristics ........................................................................... 80
Electrical Specifications – Program/Erase Characteristics ................................................................................. 82
Package Dimensions ....................................................................................................................................... 83
Revision History ............................................................................................................................................. 87
Rev. B – 11/12 ............................................................................................................................................. 87
Rev. A – 08/12 ............................................................................................................................................. 87
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2012 Micron Technology, Inc. All rights reserved.
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 8
Figure 2: 56-Pin TSOP (Top View) .................................................................................................................... 9
Figure 3: 48-Pin TSOP (Top View) .................................................................................................................. 10
Figure 4: 48-Ball BGA (Top and Bottom Views) ............................................................................................... 11
Figure 5: 64-Ball Fortified BGA (Top and Bottom Views) .................................................................................. 12
Figure 6: Data Polling Flowchart .................................................................................................................... 24
Figure 7: Toggle Bit Flowchart ........................................................................................................................ 25
Figure 8: Status Register Polling Flowchart ..................................................................................................... 26
Figure 9: Lock Register Program Flowchart ..................................................................................................... 28
Figure 10: Boundary Condition of Program Buffer Size .................................................................................... 39
Figure 11: WRITE TO BUFFER PROGRAM Flowchart ...................................................................................... 40
Figure 12: Program/Erase Nonvolatile Protection Bit Algorithm ...................................................................... 52
Figure 13: Software Protection Scheme .......................................................................................................... 57
Figure 14: Power-Up Timing .......................................................................................................................... 64
Figure 15: Reset AC Timing – No PROGRAM/ERASE Operation in Progress ...................................................... 65
Figure 16: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 65
Figure 17: AC Measurement Load Circuit ....................................................................................................... 67
Figure 18: AC Measurement I/O Waveform ..................................................................................................... 67
Figure 19: Random Read AC Timing (8-Bit Mode) ........................................................................................... 71
Figure 20: Random Read AC Timing (16-Bit Mode) ......................................................................................... 71
Figure 21: BYTE# Transition Read AC Timing .................................................................................................. 72
Figure 22: Page Read AC Timing (16-Bit Mode) ............................................................................................... 72
Figure 23: WE#-Controlled Program AC Timing (8-Bit Mode) .......................................................................... 74
Figure 24: WE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 75
Figure 25: CE#-Controlled Program AC Timing (8-Bit Mode) ........................................................................... 77
Figure 26: CE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 78
Figure 27: Chip/Block Erase AC Timing (8-Bit Mode) ...................................................................................... 79
Figure 28: Accelerated Program AC Timing ..................................................................................................... 80
Figure 29: Data Polling AC Timing .................................................................................................................. 80
Figure 30: Toggle/Alternative Toggle Bit Polling AC Timing (8-Bit Mode) .......................................................... 81
Figure 31: 56-Pin TSOP – 14mm x 20mm ........................................................................................................ 83
Figure 32: 48-Pin TSOP – 12mm x 20mm ........................................................................................................ 84
Figure 33: 48-Ball BGA – 6mm x 8mm ............................................................................................................. 85
Figure 34: 64-Ball Fortified BGA – 11mm x 13mm ........................................................................................... 86
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2012 Micron Technology, Inc. All rights reserved.
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Features
List of Tables
Table 1: Part Number Information ................................................................................................................... 2
Table 2: Standard Part Numbers by Density, Medium, and Package ................................................................... 2
Table 3: Part Numbers with Security Features by Density, Medium, and Package ................................................ 3
Table 4: Signal Descriptions ........................................................................................................................... 13
Table 5: 32Mb Memory Map – x8 Top and Bottom Boot [70:0] ......................................................................... 15
Table 6: 32Mb Memory Map – x16 Top and Bottom Boot [70:0] ........................................................................ 15
Table 7: 32Mb Memory Map – x8/x16 Uniform Blocks [63:0] ............................................................................ 16
Table 8: 64Mb Memory Map – x8 Top and Bottom Boot [134:0] ........................................................................ 17
Table 9: 64Mb Memory Map – x16 Top and Bottom Boot [134:0] ...................................................................... 17
Table 10: 64Mb Memory Map – x8/x16 Uniform Blocks [127:0] ........................................................................ 18
Table 11: 128Mb Memory Map – x8/x16 Uniform Blocks [127:0] ...................................................................... 19
Table 12: Bus Operations ............................................................................................................................... 20
Table 13: Status Register Bit Definitions ......................................................................................................... 22
Table 14: Operations and Corresponding Bit Settings ...................................................................................... 23
Table 15: Lock Register Bit Definitions ............................................................................................................ 27
Table 16: Block Protection Status ................................................................................................................... 27
Table 17: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ........................................... 30
Table 18: Read Electronic Signature ............................................................................................................... 34
Table 19: Block Protection ............................................................................................................................. 35
Table 20: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ................................ 47
Table 21: Extended Memory Block Address and Data ...................................................................................... 53
Table 22: VPP/WP# Functions ......................................................................................................................... 55
Table 23: Query Structure Overview ............................................................................................................... 59
Table 24: CFI Query Identification String ........................................................................................................ 59
Table 25: CFI Query System Interface Information .......................................................................................... 60
Table 26: Device Geometry Definition ............................................................................................................ 60
Table 27: Erase Block Region Information ....................................................................................................... 61
Table 28: Primary Algorithm-Specific Extended Query Table ........................................................................... 62
Table 29: Power-Up Specifications ................................................................................................................. 64
Table 30: Reset AC Specifications ................................................................................................................... 65
Table 31: Absolute Maximum/Minimum Ratings ............................................................................................ 66
Table 32: Operating Conditions ...................................................................................................................... 66
Table 33: Input/Output Capacitance .............................................................................................................. 67
Table 34: DC Current Characteristics .............................................................................................................. 68
Table 35: DC Voltage Characteristics .............................................................................................................. 69
Table 36: Read AC Characteristics .................................................................................................................. 70
Table 37: WE#-Controlled Write AC Characteristics ......................................................................................... 73
Table 38: CE#-Controlled Write AC Characteristics ......................................................................................... 76
Table 39: Accelerated Program and Data Polling/Data Toggle AC Characteristics .............................................. 80
Table 40: Program/Erase Characteristics ........................................................................................................ 82
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2012 Micron Technology, Inc. All rights reserved.
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
General Description
General Description
The M29EW is an asynchronous, parallel NOR Flash memory device manufactured on
65nm single-bit cell (SBC) technology. READ, ERASE, and PROGRAM operations are
performed using a single low-voltage supply. Upon power-up, the device defaults to
read array mode.
The main memory array is divided into uniform blocks that can be erased independent-
ly so that valid data can be preserved while old data is purged. PROGRAM and ERASE
commands are written to the command interface of the memory. An on-chip program/
erase controller simplifies the process of programming or erasing the memory by taking
care of all special operations required to update the memory contents. The end of a
PROGRAM or ERASE operation can be detected and any error condition can be identi-
fied. The command set required to control the device is consistent with JEDEC stand-
ards.
CE#, OE#, and WE# control the bus operation of the device and enable a simple con-
nection to most microprocessors, often without additional logic.
The M29EW supports asynchronous random read and page read from all blocks of the
array. It also features an internal program buffer that improves throughput by program-
ming 256 words via one command sequence. The device contains a 128-word extended
memory block which overlaps addresses with array block 0. The user can program this
additional space and then protect it to permanently secure the contents. The device al-
so features different levels of hardware and software protection to secure blocks from
unwanted modification.
Figure 1: Logic Diagram
VCC
VCCQ
VPP/WP#
15
A[MAX:0]
DQ[14:0]
DQ15/A-1
RY/BY#
WE#
CE#
OE#
RST#
BYTE#
VSS
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m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
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© 2012 Micron Technology, Inc. All rights reserved.
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Signal Assignments
Signal Assignments
Figure 2: 56-Pin TSOP (Top View)
RFU
1
RFU
RFU
A16
BYTE#
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A22
2
A15
3
A14
4
A13
5
V
SS
A12
6
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
A11
7
A10
8
A9
9
A8
10
A19
11
A20
12
WE#
RST#
A21
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
/WP#
PP
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
RFU
RFU
V
SS
CE#
A0
RFU
V
CCQ
1. A-1 is the least significant address bit in x8 mode.
2. A21 is valid for 64Mb and above; otherwise, it is RFU.
3. A22 is valid for 128Mb and above; otherwise, it is RFU.
4. RFU = Reserved for future use.
Notes:
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2012 Micron Technology, Inc. All rights reserved.
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Signal Assignments
Figure 3: 48-Pin TSOP (Top View)
A16
BYTE#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A15
A14
A13
A12
A11
A10
A9
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
A8
A19
A20
WE#
RST#
A21
/WP#
RY/BY#
A18
A17
A7
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
PP
A6
A5
A4
A3
A2
A1
28
27
26
25
V
SS
CE#
A0
1. A-1 is the least significant address bit in x8 mode.
2. A21 is valid for 64Mb and above; otherwise, it is RFU.
3. RFU = Reserved for future use.
Notes:
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2012 Micron Technology, Inc. All rights reserved.
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Signal Assignments
Figure 4: 48-Ball BGA (Top and Bottom Views)
1
2
3
4
5
6
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
A3
A7 RY/BY# WE# A9 A13
A13 A9 WE# RY/BY# A7
A3
A4 A17
V
/WP#RST# A8 A12
A12 A8 RST#V /WP# A17 A4
PP
PP
A2
A1
A0
A6
A5
D0
A18 A21 A10 A14
A20 A19 A11 A15
A14 A10 A21 A18 A6
A15 A11 A19 A20 A5
A2
A1
A0
D2
D5
D7 A16
A16 D7
D5
D2
D0
F
F
CE# D8
OE# D9
D10 D12 D14 BYTE#
BYTE# D14 D12 D10 D8 CE#
G
H
G
H
D11
D3
V
D13 D15/A-1
D15/A-1 D13
V
D11 D9 OE#
CC
CC
V
D1
D4
D6
V
V
D6
D4
D3
D1
V
SS
SS
SS
SS
BGA
Top view – ball side down
BGA
Bottom view – ball side up
1. A-1 is the least significant address bit in x8 mode.
2. A21 is valid for 64Mb and above; otherwise, it is RFU.
3. RFU = Reserved for future use.
Notes:
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2012 Micron Technology, Inc. All rights reserved.
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Signal Assignments
Figure 5: 64-Ball Fortified BGA (Top and Bottom Views)
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
RFU A3
A7 RY/BY# WE# A9 A13 RFU
RFU A13 A9 WE# RY/BY# A7
A3 RFU
RFU A4 A17
V
/WP#RST# A8 A12 A22
A22 A12 A8 RST#V /WP# A17 A4 RFU
PP
PP
RFU A2
RFU A1
RFU A0
A6 A18 A21 A10 A14 RFU
RFU A14 A10 A21 A18 A6
A2 RFU
A1 RFU
A0 RFU
A5 A20 A19 A11 A15
V
V
A15 A11 A19 A20 A5
CCQ
CCQ
D0
D2
D5
D7 A16
V
V
A16 D7
D5
D2
D0
SS
SS
F
F
V
CE# D8 D10 D12 D14 BYTE# RFU
RFU BYTE# D14 D12 D10 D8 CE# V
CCQ
CCQ
G
H
G
H
RFU OE# D9 D11
V
D13 D15/A-1 RFU
RFU D15/A-1 D13
V
D11 D9 OE# RFU
CC
CC
RFU
V
D1
D3
D4
D6
V
RFU
RFU
V
D6
D4
D3
D1
V
SS
RFU
SS
SS
SS
Fortified BGA
Top view – ball side down
Fortified BGA
Bottom view – ball side up
1. A-1 is the least significant address bit in x8 mode.
2. A21 is valid for 64Mb and above; otherwise, it is RFU.
3. A22 is valid for 128Mb and above; otherwise, it is RFU.
4. RFU = Reserved for future use.
Notes:
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Signal Descriptions
Signal Descriptions
The signal description table below is a comprehensive list of signals for this device fami-
ly. All signals listed may not be supported on this device. See Signal Assignments for in-
formation specific to this device.
Table 4: Signal Descriptions
Name
Type
Description
A[MAX:0]
Input
Address: Selects the cells in the array to access during READ operations. During WRITE oper-
ations, they control the commands sent to the command interface of the program/erase con-
troller.
CE#
Input
Chip enable: Activates the device, enabling READ and WRITE operations to be performed.
When CE# is HIGH, the device goes to standby and data outputs are at HIGH-Z.
OE#
WE#
Input
Input
Input
Output enable: Controls the bus READ operation.
Write enable: Controls the bus WRITE operation of the command interface.
VPP/WP#
VPP/Write Protect: Provides WRITE PROTECT function and VPPH function. These functions
protect the lowest or highest block or top two blocks or bottom two blocks, enable the de-
vice to enter unlock bypass mode and accelerate program speed, respectively. (Refer to Hard-
ware Protection, Bypass Operations, and Program Operations for details.)
A 0.1μF capacitor should be connected between VPP/WP# and VSS to decouple the current
surges from the power supply when VPPH is applied. The PCB track widths must be sufficient
to carry the currents required during PROGRAM and ERASE operation when VPPH is applied
(see DC Characteristics).
BYTE#
RST#
Input
Input
Byte/word organization select: Switches between x8 and x16 bus modes. When BYTE# is
LOW, the device is in x8 mode; when HIGH, the device is in x16 mode.
Reset: Applies a hardware reset to the device, which is achieved by holding RST# LOW for at
least tPLPX. After RST# goes HIGH, the device is ready for READ and WRITE operations (after
tPHEL or tRHEL, whichever occurs last). See RESET AC Specifications for more details.
DQ[7:0]
I/O
I/O
Data I/O: Outputs the data stored at the selected address during a READ operation. During
WRITE operations, they represent the commands sent to the command interface of the inter-
nal state machine.
DQ[14:8]
Data I/O: Outputs the data stored at the selected address during a READ operation when
BYTE# is HIGH. When BYTE# is LOW, these pins are not used and are High-Z. During WRITE
operations, these bits are not used. When reading the status register, these bits should be ig-
nored.
DQ15/A-1
I/O
Data I/O or address input: When the device operates in x16 bus mode, this pin behaves as
data I/O, together with DQ[14:8]. When the device operates in x8 bus mode, this pin behaves
as the least significant bit of the address.
Except where stated explicitly otherwise, DQ15 = data I/O (x16 mode); A-1 = address input (x8
mode).
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Memory Organization
Table 4: Signal Descriptions (Continued)
Name
Type
Description
RY/BY#
Output Ready busy: Open-drain output that can be used to identify when the device is performing
a PROGRAM or ERASE operation. During PROGRAM or ERASE operations, RY/BY# is LOW,
and is High-Z during read mode, auto select mode, and erase suspend mode. After a hard-
ware reset, READ and WRITE operations cannot begin until RY/BY# goes High-Z (see RESET
AC Specifications for more details).
The use of an open-drain output enables the RY/BY# pins from several devices to be connec-
ted to a single pull-up resistor to VCCQ. A low value will then indicate that one (or more) of
the devices is (are) busy. A 10K Ohm or bigger resistor is recommended as pull-up resistor to
achieve 0.1V VOL
.
VCC
Supply
Supply voltage: Provides the power supply for READ, PROGRAM, and ERASE operations.
The command interface is disabled when VCC <= VLKO. This prevents WRITE operations from
accidentally damaging the data during power-up, power-down, and power surges. If the pro-
gram/erase controller is programming or erasing during this time, then the operation aborts
and the contents being altered will be invalid.
A 0.1μF capacitor should be connected between VCC and VSS to decouple the current surges
from the power supply. The PCB track widths must be sufficient to carry the currents required
during PROGRAM and ERASE operations (see DC Characteristics).
VCCQ
Supply
I/O supply voltage: Provides the power supply to the I/O pins and enables all outputs to be
powered independently from VCC
.
VSS
Supply
–
Ground: All VSS pins must be connected to the system ground.
Reserved for future use: RFUs should be not connected.
RFU
Memory Organization
Memory Configuration
The 32Mb device memory array (x8/x16) is divided into 63 main blocks (64KB each) and
8 top or bottom boot blocks (8KB each). It is also divided into 64 main uniform blocks
(64KB each).
The 64Mb device memory array (x8/x16) is divided into 127 main blocks (64KB each)
and 8 top or bottom boot blocks (8KB each). It is also divided into 128 main uniform
blocks (64KB each).
The 128Mb device memory array (x8/x16) is divided into 128 main uniform blocks
(128KB each).
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Memory Organization
Memory Map – 32Mb
Table 5: 32Mb Memory Map – x8 Top and Bottom Boot [70:0]
Address Range (x8 Top Boot)
Address Range (x8 Bottom Boot)
Block
Size
Block
Size
Block
70
69
68
67
66
65
64
63
62
⋮
Start
End
Block
Start
End
8KB
003F E000
003F C000
003F A000
003F 8000
003F 6000
003F 4000
003F 2000
003F 0000
003E 0000
⋮
003F FFFF
003F DFFF
003F BFFF
003F 9FFF
003F 7FFF
003F 5FFF
003F 3FFF
003F 1FFF
003E FFFF
⋮
70
69
68
⋮
64KB
003F 0000
003E 0000
003D 0000
⋮
003F FFFF
003E FFFF
003D FFFF
⋮
⋮
8
64KB
8KB
0001 0000
0000 E000
0000 C000
0000 A000
0000 8000
0000 6000
0000 4000
0000 2000
0000 0000
0001 FFFF
0000 FFFF
0000 DFFF
0000 BFFF
0000 9FFF
0000 7FFF
0000 5FFF
0000 3FFF
0000 1FFF
7
6
5
64KB
⋮
4
3
2
64KB
0002 0000
0001 0000
0000 0000
0002 FFFF
0001 FFFF
0000 FFFF
2
1
1
0
0
Table 6: 32Mb Memory Map – x16 Top and Bottom Boot [70:0]
Address Range (x16 Top Boot)
Address Range (x16 Bottom Boot)
Block
Size
Block
Block
70
69
68
67
66
65
64
63
62
⋮
Start
End
Block
Size
Start
End
4KW
001F F000
001F E000
001F D000
001F C000
001F B000
001F A000
001F 9000
001F 8000
001F 0000
⋮
001F FFFF
001F EFFF
001F DFFF
001F CFFF
001F BFFF
001F AFFF
001F 9FFF
001F 8FFF
001F 7FFF
⋮
70
69
68
⋮
32KW
001F 8000
001F 0000
001E 8000
⋮
001F FFFF
001F 7FFF
001E FFFF
⋮
⋮
8
32KW
4KW
0000 8000
0000 7000
0000 6000
0000 5000
0000 4000
0000 3000
0000 2000
0000 1000
0000 0000
0000 FFFF
0000 7FFF
0000 6FFF
0000 5FFF
0000 4FFF
0000 3FFF
0000 2FFF
0000 1FFF
0000 0FFF
7
6
5
32KW
⋮
4
3
2
32KW
0001 0000
0000 8000
0000 0000
0001 7FFF
0000 FFFF
0000 7FFF
2
1
1
0
0
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Memory Organization
Table 7: 32Mb Memory Map – x8/x16 Uniform Blocks [63:0]
Address Range (x8)
Address Range (x16)
Block
Size
Block
Size
Block
Start
03F 0000h
⋮
End
03F FFFFh
⋮
Block
Start
01F 8000h
⋮
End
01F FFFFh
⋮
63
⋮
64KB
63
⋮
32KW
0
000 0000h
000 FFFFh
0
000 0000h
000 7FFFh
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Memory Organization
Memory Map – 64Mb
Table 8: 64Mb Memory Map – x8 Top and Bottom Boot [134:0]
Address Range (x8 Top Boot)
Address Range (x8 Bottom Boot)
Block
Size
Block
Block
134
133
132
131
130
129
128
127
126
⋮
Start
End
Block
Size
Start
End
8KB
007F E000
007F C000
007F A000
007F 8000
007F 6000
007F 4000
007F 2000
007F 0000
007E 0000
⋮
007F FFFF
007F DFFF
007F BFFF
007F 9FFF
007F 7FFF
007F 5FFF
007F 3FFF
007F 1FFF
007E FFFF
⋮
134
133
132
⋮
64KB
007F 0000
007E 0000
007D 0000
⋮
007F FFFF
007E FFFF
007D FFFF
⋮
⋮
8
64KB
8KB
0001 0000
0000 E000
0000 C000
0000 A000
0000 8000
0000 6000
0000 4000
0000 2000
0000 0000
0001 FFFF
0000 FFFF
0000 DFFF
0000 BFFF
0000 9FFF
0000 7FFF
0000 5FFF
0000 3FFF
0000 1FFF
7
6
5
64KB
⋮
4
3
2
64KB
0002 0000
0001 0000
0000 0000
0002 FFFF
0001 FFFF
0000 FFFF
2
1
1
0
0
Table 9: 64Mb Memory Map – x16 Top and Bottom Boot [134:0]
Address Range (x16 Top Boot)
Address Range (x16 Bottom Boot)
Block
Size
Block
Block
134
133
132
131
130
129
128
127
126
⋮
Start
End
Block
Size
Start
End
4KW
003F F000
003F E000
003F D000
003F C000
003F B000
003F A000
003F 9000
003F 8000
003F 0000
⋮
003F FFFF
003F EFFF
003F DFFF
003F CFFF
003F BFFF
003F AFFF
003F 9FFF
003F 8FFF
003F 7FFF
⋮
134
133
132
⋮
32KW
003F 8000
003F 0000
003E 8000
⋮
003F FFFF
003F 7FFF
003E FFFF
⋮
⋮
8
32KW
4KW
0000 8000
0000 7000
0000 6000
0000 5000
0000 4000
0000 3000
0000 2000
0000 1000
0000 0000
0000 FFFF
0000 7FFF
0000 6FFF
0000 5FFF
0000 4FFF
0000 3FFF
0000 2FFF
0000 1FFF
0000 0FFF
7
6
5
32KW
⋮
4
3
2
32KW
0001 0000
0000 8000
0000 0000
0001 7FFF
0000 FFFF
0000 7FFF
2
1
1
0
0
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Memory Organization
Table 10: 64Mb Memory Map – x8/x16 Uniform Blocks [127:0]
Address Range (x8)
Address Range (x16)
Block
Size
Block
Size
Block
Start
End
Block
Start
End
127
64KB
07F 0000h
07F FFFFh
127
32KW
03F 8000h
03F FFFFh
⋮
63
⋮
⋮
⋮
⋮
63
⋮
⋮
⋮
03F 0000h
⋮
03F FFFFh
⋮
01F 8000h
⋮
01F FFFFh
⋮
0
000 0000h
000 FFFFh
0
000 0000h
000 7FFFh
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Memory Organization
Memory Map – 128Mb
Table 11: 128Mb Memory Map – x8/x16 Uniform Blocks [127:0]
Address Range (x8)
Block
Address Range (x16)
Block
Size
Block
Size
Start
End
Block
Start
End
127
128KB
0FE 0000h
0FF FFFFh
127
64KW
07F 0000h
07F FFFFh
⋮
63
⋮
⋮
⋮
⋮
63
⋮
⋮
⋮
07E 0000h
⋮
07F FFFFh
⋮
03F 0000h
⋮
03F FFFFh
⋮
0
000 0000h
001 FFFFh
0
000 0000h
000 FFFFh
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Bus Operations
Bus Operations
Table 12: Bus Operations
Notes 1 and 2 apply to entire table
8-Bit Mode
16-Bit Mode
DQ15/A-1,
DQ[14:0]
Data output Word address Data output
A[MAX:0],
DQ15/A-1
Operation CE# OE# WE# RST# VPP/WP#
DQ[14:8]
High-Z
DQ[7:0]
A[MAX:0]
READ
L
L
L
H
L
H
H
X
H3
Byte address
WRITE
H
Command
address
High-Z
Data input4
Command
address
Data input4
STANDBY
H
L
X
H
X
H
H
H
H
X
X
X
High-Z
High-Z
High-Z
High-Z
X
X
High-Z
High-Z
OUTPUT
DISABLE
RESET
X
X
X
L
X
X
High-Z
High-Z
X
High-Z
1. Typical glitches of less than 3ns on CE#, WE#, and RST# are ignored by the device and do
not affect bus operations.
Notes:
2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
3. If WP# is LOW, then the highest or the lowest block remains protected, or the top two
blocks or the bottom two blocks, depending on line item.
4. Data input is required when issuing a command sequence or when performing data
polling or block protection.
Read
Bus READ operations read from the memory cells, registers, or CFI space. To accelerate
the READ operation, the memory array can be read in page mode where data is inter-
nally read and stored in a page buffer.
Page size is 8 words (16 bytes) and is addressed by address inputs A[2:0] in x16 bus
mode and A[2:0] plus DQ15/A-1 in x8 bus mode. The extended memory blocks and CFI
area do not support page read mode.
A valid bus READ operation involves setting the desired address on the address inputs,
taking CE# and OE# LOW, and holding WE# HIGH. The data I/Os will output the value.
(See AC Characteristics for details about when the output becomes valid.)
Write
Bus WRITE operations write to the command interface. A valid bus WRITE operation
begins by setting the desired address on the address inputs. The address inputs are
latched by the command interface on the falling edge of CE# or WE#, whichever occurs
last. The data I/Os are latched by the command interface on the rising edge of CE# or
WE#, whichever occurs first. OE# must remain HIGH during the entire bus WRITE oper-
ation. (See AC Characteristics for timing requirement details.)
Standby
Driving CE# HIGH in read mode causes the device to enter standby, and data I/Os to be
High-Z. To reduce the supply current to the standby supply current (ICC2), CE# must be
held within VCC ±0.3V. (See DC Characteristics.)
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Bus Operations
During PROGRAM or ERASE operations the device will continue to use the program/
erase supply current (ICC3) until the operation completes.
Output Disable
Reset
Data I/Os are High-Z when OE# is HIGH.
During reset mode the device is deselected and the outputs are High-Z. The device is in
reset mode when RST# is LOW. The power consumption is reduced to the standby level,
independently from CE#, OE#, or WE# inputs.
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Registers
Registers
Status Register
Table 13: Status Register Bit Definitions
Note 1 applies to entire table
Bit
Name
Settings
Description
Notes
DQ7 Data polling 0 or 1, depending on
Monitors whether the program/erase controller has successful- 2, 3, 4
ly completed its operation, or has responded to an ERASE SUS-
PEND operation.
bit
operations
DQ6 Toggle bit
Toggles: 0 to 1; 1 to 0;
and so on
Monitors whether the program/erase controller has successful- 3, 4, 5
ly completed its operations, or has responded to an ERASE
SUSPEND operation. During a PROGRAM/ERASE operation,
DQ6 toggles from 0 to 1, 1 to 0, and so on, with each succes-
sive READ operation from any address.
DQ5 Error bit
0 = Success
1 = Failure
Identifies errors detected by the program/erase controller. DQ5
is set to 1 when a PROGRAM, BLOCK ERASE, or CHIP ERASE op-
eration fails to write the correct data to the memory, or when
a BLANK CHECK operation fails.
4, 6
DQ3 Erase timer 0 = Erase not in progress Identifies the start of program/erase controller operation dur-
4
bit
1 = Erase in progress
ing a BLOCK ERASE command. Before the program/erase con-
troller starts, this bit set to 0, and additional blocks to be
erased can be written to the command interface.
DQ2 Alternative Toggles: 0 to 1; 1 to 0;
Monitors the program/erase controller during ERASE opera-
tions. During CHIP ERASE, BLOCK ERASE, and ERASE SUSPEND
operations, DQ2 toggles from 0 to 1, 1 to 0, and so on, with
each successive READ operation from addresses within the
blocks being erased.
3, 4
toggle bit
and so on
DQ1 Buffered
program
1 = Abort
Indicates a BUFFER PROGRAM operation abort. The BUFFERED
PROGRAM ABORT and RESET command must be issued to re-
turn the device to read mode (see WRITE TO BUFFER PRO-
GRAM command).
abort bit
1. The status register can be read during PROGRAM, ERASE, or ERASE SUSPEND operations;
the READ operation outputs data on DQ[7:0].
Notes:
2. For a PROGRAM operation in progress, DQ7 outputs the complement of the bit being
programmed. For a READ operation from the address previously programmed success-
fully, DQ7 outputs existing DQ7 data. For a READ operation from addresses with blocks
to be erased while an ERASE SUSPEND operation is in progress, DQ7 outputs 0; upon
successful completion of the ERASE SUSPEND operation, DQ7 outputs 1. For an ERASE or
BLANK CHECK operation in progress, DQ7 outputs 0; upon either operation's successful
completion, DQ7 outputs 1.
3. After successful completion of a PROGRAM, ERASE, or BLANK CHECK operation, the de-
vice returns to read mode.
4. During erase suspend mode, READ operations to addresses within blocks not being
erased output memory array data as if in read mode. A protected block is treated the
same as a block not being erased. See the Toggle Flowchart for more information.
5. During erase suspend mode, DQ6 toggles when addressing a cell within a block being
erased. The toggling stops when the program/erase controller has suspended the ERASE
operation. See the Toggle Flowchart for more information.
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Registers
6. When DQ5 is set to 1, a READ/RESET command must be issued before any subsequent
command.
Table 14: Operations and Corresponding Bit Settings
Note 1 applies to entire table
Operation
PROGRAM
Address
DQ7
DQ6
DQ5
DQ3
DQ2
–
DQ1
RY/BY# Notes
Any address
Any address
DQ7#
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
0
0
0
0
0
0
0
–
–
1
0
0
1
1
0
0
–
–
–
–
–
0
2
BLANK CHECK
CHIP ERASE
1
0
0
0
0
0
–
0
Any address
Toggle
Toggle
No toggle
Toggle
No toggle
0
BLOCK ERASE
before time-out
Erasing block
Non-erasing block
Erasing block
Non-erasing block
0
0
BLOCK ERASE
0
0
PROGRAM
SUSPEND
Programming
block
Invalid operation
High-Z
Nonprogramming
block
Outputs memory array data as if in read mode
High-Z
ERASE
SUSPEND
Erasing blk
Non-erasing blk
Erasing block
1
No Toggle
0
–
Toggle
–
High-Z
High-Z
0
Outputs memory array data as if in read mode
PROGRAM during
ERASE SUSPEND
DQ7#
Toggle
Toggle
Toggle
0
0
0
–
–
–
Toggle
No Toggle
–
–
–
1
2
2
Non-erasing block DQ7#
0
BUFFERED
Any address
DQ7#
High-Z
PROGRAM ABORT
PROGRAM Error
ERASE Error
Any address
Erase success block
Erase fail block
Any address
DQ7#
Toggle
Toggle
Toggle
Toggle
1
1
1
1
–
1
1
1
–
–
–
–
–
High-Z
High-Z
High-Z
High-Z
2
0
0
1
No toggle
Toggle
Toggle
BLANK CHECK Er-
ror
1. Unspecified data bits should be ignored.
2. DQ7# for buffer program is related to the last address location loaded.
Notes:
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Registers
Figure 6: Data Polling Flowchart
Start
Read DQ7, DQ5, and DQ1
at valid address1
Yes
DQ7 = Data
No
No
No
DQ5 = 1
DQ1 = 1
Yes
Yes
Read DQ7 at valid address
Yes
DQ7 = Data
No
Failure2
Success
1. Valid address is the address being programmed or an address within the block being
erased or on which a BLANK CHECK operation has been executed.
Notes:
2. The data polling process does not support the BLANK CHECK operation. The process
represented in the Toggle Bit Flowchart figure can provide information on the BLANK
CHECK operation.
3. Failure results: DQ5 = 1 indicates an operation error; DQ1 = 1 indicates a WRITE TO BUF-
FER PROGRAM ABORT operation.
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Registers
Figure 7: Toggle Bit Flowchart
Start
Read DQ6 at valid address
Read DQ6, DQ5, and DQ1
at valid address
No
DQ6 = Toggle
Yes
No
No
DQ5 = 1
DQ1 = 1
Yes
Yes
Read DQ6 (twice) at valid address
No
DQ6 = Toggle
Yes
Failure1
Success
1. Failure results: DQ5 = 1 indicates an operation error; DQ1 = 1 indicates a WRITE TO BUF-
FER PROGRAM ABORT operation.
Note:
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Registers
Figure 8: Status Register Polling Flowchart
Start
Read 1
Yes
Yes
Yes
Yes
Read 2
Read 3
PROGRAM operation
No
Read 3 correct data?
No
DQ7 = Valid data
No
PROGRAM operation
failure
Read 2
Read 3
DQ5 = 1
No
Yes
Yes
DQ6 = Toggling
Device error
Read2.DQ6 = Read3.DQ6
No
Yes
DQ2 = Toggling
Read2.DQ2 = Read3.DQ2
DQ6 = Toggling
Timeout failure
Erase/suspend mode
Read1.DQ6 = Read2.DQ6
No
No
ERASE operation
complete
PROGRAM operation
complete
Device busy: Repolling
WRITE TO BUFFER
Yes
Yes
WRITE TO BUFFER
PROGRAM
DQ1 = 1
No
PROGRAM
abort
No
Device busy: Repolling
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Registers
Lock Register
Table 15: Lock Register Bit Definitions
Note 1 applies to entire table
Bit Name
Settings
Description
Notes
DQ2 Password
protection
0 = Password protection
mode enabled
Places the device permanently in password protection mode.
2
mode lock bit 1 = Password protection
mode disabled (Default)
DQ1 Nonvolatile
protection
0 = Nonvolatile protection Places the device in nonvolatile protection mode with pass-
mode enabled with pass- word protection mode permanently disabled. When shipped
2
mode lock bit word protection mode
from the factory, the device will operate in nonvolatile protec-
tion mode, and the memory blocks are unprotected.
permanently disabled
1 = Nonvolatile protection
mode enabled (Default)
DQ0 Extended
memory
0 = Protected
If the device is shipped with the extended memory block un-
1 = Unprotected (Default) locked, the block can be protected by setting this bit to 0. The
extended memory block protection status can be read in auto
select mode by issuing an AUTO SELECT command.
block
protection bit
1. The lock register is a 16-bit, one-time programmable register. DQ[15:3] are reserved and
are set to a default value of 1.
Notes:
2. The password protection mode lock bit and nonvolatile protection mode lock bit cannot
both be programmed to 0. Any attempt to program one while the other is programmed
causes the operation to abort, and the device returns to read mode. The device is ship-
ped from the factory with the default setting.
Table 16: Block Protection Status
Nonvolatile
Block
Protection
Status
Protection Bit
Lock Bit1
Nonvolatile
Volatile
Protection Bit2 Protection Bit3
Block Protection Status
1
1
1
1
1
1
0
0
1
0
1
0
00h
01h
01h
01h
Block unprotected; nonvolatile protection bit changea-
ble.
Block protected by volatile protection bit; nonvolatile
protection bit changeable.
Block protected by nonvolatile protection bit; nonvola-
tile protection bit changeable.
Block protected by nonvolatile protection bit and vola-
tile protection bit; nonvolatile protection bit changea-
ble.
0
0
0
1
1
0
1
0
1
00h
01h
01h
Block unprotected; nonvolatile protection bit un-
changeable.
Block protected by volatile protection bit; nonvolatile
protection bit unchangeable.
Block protected by nonvolatile protection bit; nonvola-
tile protection bit unchangeable.
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Registers
Table 16: Block Protection Status (Continued)
Nonvolatile
Protection Bit
Lock Bit1
Block
Protection
Status
Nonvolatile
Volatile
Protection Bit2 Protection Bit3
Block Protection Status
0
0
0
01h
Block protected by nonvolatile protection bit and vola-
tile protection bit; nonvolatile protection bit unchange-
able.
1. Nonvolatile protection bit lock bit: when cleared to 1, all nonvolatile protection bits are
unlocked; when set to 0, all nonvolatile protection bits are locked.
Notes:
2. Block nonvolatile protection bit: when cleared to 1, the block is unprotected; when set
to 0, the block is protected.
3. Block volatile protection bit: when cleared to 1, the block is unprotected; when set to 0,
the block is protected.
Figure 9: Lock Register Program Flowchart
Start
ENTER LOCK REGISTER COMMAND SET
Address-data (unlock) cycle 1
Address-data (unlock) cycle 2
Address-data cycle 3
PROGRAM LOCK REGISTER
Address-data cycle 1
Address-data cycle 2
Polling algorithm
Yes
Done?
No
No
DQ5 = 1
Yes
Success:
Failure:
EXIT PROTECTION COMMAND SET
(Returns to device read mode)
Address-data cycle 1
READ/RESET
(Returns device to read mode)
Address-data cycle 2
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Registers
1. Each lock register bit can be programmed only once.
Notes:
2. See the Block Protection Command Definitions table for address-data cycle details.
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Standard Command Definitions – Address-Data Cycles
Standard Command Definitions – Address-Data Cycles
Table 17: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit
Note 1 applies to entire table
Address and Data Cycles
1st
2nd
3rd
4th
5th
6th
Command and
Code/Subcode
Bus
Size
A
D
A
D
A
D
A
D
A
D
A
D
Notes
READ and AUTO SELECT Operations
READ/RESET (F0h)
x8
X
F0
AAA AA
555
55
55
X
X
F0
F0
x16
X
F0
555
AA
55
AA 2AA
98
READ CFI (98h)
x8
x16
x8
AUTO SELECT (90h)
AAA AA
555
555
55
AAA
555
90 Note Note
2, 3, 4
2
2
x16
2AA
BYPASS Operations
UNLOCK BYPASS (20h)
x8
x16
x8
AAA AA
555
555
2AA
X
55
00
AAA
555
20
UNLOCK BYPASS
RESET (90h/00h)
X
90
x16
PROGRAM Operations
PROGRAM (A0h)
x8
x16
x8
AAA AA
555
555
2AA
PA
55
PD
PD
PD
AAA A0
555
PA
PD
UNLOCK BYPASS
PROGRAM (A0h)
X
A0
50
56
6
x16
x8
DOUBLE BYTE/WORD
PROGRAM (50h)
AAA
555
PA2
PA4
PA8
x16
x8
QUADRUPLE BYTE/
WORD PROGRAM (56h)
AAA
555
x16
x8
OCTUPLE BYTE PRO-
GRAM (8Bh)
AAA 8B
PD
55
5
WRITE TO BUFFER
PROGRAM (25h)
x8
AAA AA
555
555
BAd
BAd
25
33
BAd
PA
N
PA
PD
7, 8, 9
x16
x16
2AA
ENHANCED WRITE
TO BUFFER
PROGRAM (33h)
555
AA 2AA
55
N
PD
7, 9, 10
5
UNLOCK BYPASS
WRITE TO BUFFER
PROGRAM (25h)
x8
BAd
25
BAd
PA
PD
x16
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Standard Command Definitions – Address-Data Cycles
Table 17: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit (Continued)
Note 1 applies to entire table
Address and Data Cycles
1st
2nd
3rd
4th
5th
6th
Command and
Code/Subcode
Bus
Size
A
D
A
D
A
D
A
D
A
D
A
D
Notes
UNLOCK BYPASS
x16 BAd
33
PA
PD
10
ENHANCED WRITE TO
BUFFER PROGRAM (33h)
WRITE TO BUFFER
PROGRAM CONFIRM
(29h)
x8
BAd
BAd
29
29
x16
ENHANCED WRITE
TO BUFFER
PROGRAM CONFIRM
(29h)
x8
x16
BUFFERED PROGRAM
ABORT and RESET (F0h)
x8
x16
x8
AAA AA
555
555
55
AAA
555
F0
2AA
PROGRAM SUSPEND
(B0h)
X
B0
x16
x8
PROGRAM RESUME
(30h)
X
30
x16
ERASE Operations
CHIP ERASE (80/10h)
x8
x16
x8
AAA AA
555
555
2AA
X
55
10
55
30
AAA
555
80 AAA AA
555
555
55
55
AAA
555
10
30
2AA
UNLOCK BYPASS
CHIP ERASE (80/10h)
X
80
5
11
5
x16
x8
BLOCK ERASE (80/30h)
AAA AA
555
555
2AA
BAd
AAA
555
80 AAA AA
555
555
BAd
x16
x8
2AA
UNLOCK BYPASS
BLOCK ERASE (80/30h)
X
X
X
80
B0
30
x16
x8
ERASE SUSPEND (B0h)
ERASE RESUME (30h)
x16
x8
x16
BLANK CHECK Operations
BLANK CHECK
SETUP (EB/76h)
x8
x16
AAA AA
555
555
55
BAd
EB
BAd
76
BAd
00
BAd
00
2AA
BLANK CHECK CONFIRM x8
BAd
29
BAd Note
2
2
and READ (29h)
x16
1. A = Address; D = Data; X = "Don't Care;" BAd = Any address in the block; N = Number of
bytes to be programmed; PA = Program address; PA2 = Program address with constant
AMAX:A0 for x8 or AMAX:A1 for x16, which should be used two times to select adjacent
Notes:
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Standard Command Definitions – Address-Data Cycles
two bytes/words; PA4 = Program address with constant AMAX:A1 for x8 or AMAX:A2
for x16, which should be used four times to select adjacent four bytes/words; PA8 = Pro-
gram address with constant AMAX:A2 for x8, which should be used eight times to select
adjacent eight bytes; PD = Program data; Gray shading = Not applicable. All values in
the table are hexadecimal. Some commands require both a command code and sub-
code.
2. These cells represent READ cycles (versus WRITE cycles for the others).
3. AUTO SELECT enables the device to read the manufacturer code, device code, block pro-
tection status, and extended memory block protection indicator.
4. AUTO SELECT addresses and data are specified in the Electronic Signature table and the
Extended Memory Block Protection table.
5. For any UNLOCK BYPASS ERASE/PROGRAM command, the first two UNLOCK cycles are
unnecessary.
6. This command is only for x8 devices.
7. BAd must be the same as the address loaded during the WRITE TO BUFFER PROGRAM
3rd and 4th cycles.
8. WRITE TO BUFFER PROGRAM operation: maximum cycles = 261 (x8) and 261 (x16). UN-
LOCK BYPASS WRITE TO BUFFER PROGRAM operation: maximum cycles = 259 (x8), 259
(x16). WRITE TO BUFFER PROGRAM operation: N + 1 = bytes to be programmed; maxi-
mum buffer size = 256 bytes (x8) and 512 bytes (x16).
9. For x8, A[MAX:7] address pins should remain unchanged while A[6:0] and A-1 pins are
used to select a byte within the N + 1 byte page. For x16, A[MAX:8] address pins should
remain unchanged while A[7:0] pins are used to select a word within the N+1 word
page.
10. This command is only for x16 devices. For ENHANCED WRITE TO BUFFER PROGRAM op-
eration, total cycles = 259. For UNLOCK BYPASS ENHANCED WRITE TO BUFFER PRO-
GRAM operation, total cycles = 257.
11. BLOCK ERASE address cycles can extend beyond six address-data cycles, depending on
the number of blocks to erase.
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
READ and AUTO SELECT Operations
READ and AUTO SELECT Operations
READ/RESET Command
The READ/RESET (F0h) command returns the device to read mode and resets the errors
in the status register. One or three bus WRITE operations can be used to issue the
READ/RESET command.
To return the device to read mode, this command can be issued between bus WRITE
cycles before the start of a PROGRAM or ERASE operation. If the READ/RESET com-
mand is issued during the timeout of a BLOCK ERASE operation, the device requires up
to 10μs to abort, during which time no valid data can be read.
This command will not abort an ERASE operation while in erase suspend.
READ CFI Command
The READ CFI (98h) command puts the device in read CFI mode and is only valid when
the device is in read array or auto select mode. One bus WRITE cycle is required to issue
the command.
Once in read CFI mode, bus READ operations will output data from the CFI memory
area (Refer to the Common Flash Interface for details). A READ/RESET command must
be issued to return the device to the previous mode (read array or auto select ). A sec-
ond READ/RESET command is required to put the device in read array mode from auto
select mode.
AUTO SELECT Command
At power-up or after a hardware reset, the device is in read mode. It can then be put in
auto select mode by issuing an AUTO SELECT (90h) command. Auto select mode ena-
bles the following device information to be read:
• Electronic signature, which includes manufacturer and device code information as
shown in the Electronic Signature table.
• Block protection, which includes the block protection status and extended memory
block protection indicator, as shown in the Block Protection table.
Electronic signature or block protection information is read by executing a READ opera-
tion with control signals and addresses set, as shown in the Read Electronic Signature
table or the Block Protection table, respectively. In addition, this device information can
be read or set by issuing an AUTO SELECT command.
Auto select mode can be used by the programming equipment to automatically match a
device with the application code to be programmed.
Three consecutive bus WRITE operations are required to issue an AUTO SELECT com-
mand. The device remains in auto select mode until a READ/RESET or READ CFI com-
mand is issued.
The device cannot enter auto select mode when a PROGRAM or ERASE operation is in
progress (RY/BY# LOW). However, auto select mode can be entered if the PROGRAM or
ERASE operation has been suspended by issuing a PROGRAM SUSPEND or ERASE SUS-
PEND command.
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
READ and AUTO SELECT Operations
Auto select mode is exited by performing a reset. The device returns to read mode un-
less it entered auto select mode after an ERASE SUSPEND or PROGRAM SUSPEND
command, in which case it returns to erase or program suspend mode.
Table 18: Read Electronic Signature
Note 1 applies to entire table
Address Input
8-Bit/16-Bit
Data Input/Output
16-Bit
Only
8-Bit
Only
8-Bit Only
Read Cycle
CE# OE# WE# A[MAX:11] A[10:4] A3 A2 A1 A0
A-1 DQ[14:8] DQ[7:0] DQ[15:0]
Manufacturer
code
L
L
H
X
L
L
L
L
L
X
X
89h
0089h
Device code 1
L
L
L
L
H
H
X
X
L
L
L
L
L
H
L
X
X
X
X
7Eh
21h
10h
227Eh
2221h
2210h
Device 128Mb
code 2
64Mb
H
H
H
boot
64Mb
uniform
0Ch
1Ah
1Dh
01h
220Ch
221Ah
221Dh
2201h
32Mb
boot
32Mb
uniform
Device 128Mb
code 3 uniform
L
L
H
X
L
H
H
H
H
X
X
64Mb
uniform
64Mb
top
32Mb
top
Device 64Mb
L
L
H
X
L
H
H
H
H
X
X
00h
2200h
code 3 bottom
32Mb
bottom
32Mb
uniform
1. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
Note:
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Bypass Operations
Table 19: Block Protection
Note 1 applies to entire table
Address Input
8-Bit/16-Bit
Data Input/Output
16-Bit
Only
8-Bit
Only
8-Bit Only
Read Cycle
CE# OE# WE# A[MAX:15] A[14:11] A[10:2] A1 A0 A-1 DQ[14:8] DQ[7:0] DQ[15:0]
Extended
memory
Block
protection
indicator
(DQ7)
M29EWL
128Mb
L
L
L
L
L
L
H
H
H
X
X
X
X
X
X
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
89h2
09h3
99h2
19h3
8Ah2
0Ah3
0089h2
0009h3
0099h2
0019h3
008Ah2
000Ah3
M29EWH
128Mb
M29EWL
64Mb
32Mb
M29EWH
64Mb
32Mb
L
L
L
L
L
L
L
H
H
H
H
X
X
X
X
X
X
L
L
L
L
L
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
X
9Ah2
1Ah3
009Ah2
001Ah3
M29EWB
64Mb
32Mb
8Ah2
0Ah3
008Ah2
000Ah3
M29EWT
64Mb
32Mb
9Ah2
1Ah3
009Ah2
001Ah3
Block protection
status
L
Block base
address6
01h4
00h5
0001h4
0000h5
1. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
2. Micron-prelocked (permanent).
Notes:
3. Customer-lockable.
4. Protected: 01h (in x8 mode) is output on DQ[7:0].
5. Unprotected: 00h (in x8 mode) is output on DQ[7:0].
6. Block base address for 128Mb device, should be A[MAX:16], while A15 = X.
Bypass Operations
UNLOCK BYPASS Command
The UNLOCK BYPASS (20h) command is used to place the device in unlock bypass
mode. Three bus WRITE operations are required to issue the UNLOCK BYPASS com-
mand.
When the device enters unlock bypass mode, the two initial UNLOCK cycles required
for a standard PROGRAM or ERASE operation are not needed, thus enabling faster total
program or erase time.
The UNLOCK BYPASS command is used in conjunction with UNLOCK BYPASS PRO-
GRAM or UNLOCK BYPASS ERASE commands to program or erase the device faster
than with standard PROGRAM or ERASE commands. When the cycle time to the device
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Program Operations
is long, considerable time savings can be gained by using these commands. When in
unlock bypass mode, only the following commands are valid:
• The UNLOCK BYPASS PROGRAM command can be issued to program addresses
within the device.
• The UNLOCK BYPASS BLOCK ERASE command can then be issued to erase one or
more memory blocks.
• The UNLOCK BYPASS CHIP ERASE command can be issued to erase the whole mem-
ory array.
• The UNLOCK BYPASS WRITE TO BUFFER PROGRAM and UNLOCK BYPASS EN-
HANCED WRITE TO BUFFER PROGRAM commands can be issued to speed up the
programming operation.
• The UNLOCK BYPASS RESET command can be issued to return the device to read
mode.
In unlock bypass mode, the device can be read as if in read mode.
In addition to the UNLOCK BYPASS command, when VPP/WP# is raised to VPPH, the de-
vice automatically enters unlock bypass mode. When VPP/WP# returns to VIH or VIL, the
device is no longer in unlock bypass mode and normal operation resumes. The transi-
tions from VIH to VPPH and from VPPH to VIH must be slower than tVHVPP (see the Accel-
erated Program, Data Polling/Toggle AC Characteristics).
Note: Micron recommends the user enter and exit unlock bypass mode using ENTER
UNLOCK BYPASS and UNLOCK BYPASS RESET commands rather than raising VPP/WP#
to VPPH. VPP/WP# should never be raised to VPPH from any mode except read mode; oth-
erwise, the device may be left in an indeterminate state.
UNLOCK BYPASS RESET Command
The UNLOCK BYPASS RESET (90/00h) command is used to return to read/reset mode
from unlock bypass mode. Two bus WRITE operations are required to issue the UN-
LOCK BYPASS RESET command. The READ/RESET command does not exit from un-
lock bypass mode.
Program Operations
PROGRAM Command
The PROGRAM (A0h) command can be used to program a value to one address in the
memory array. The command requires four bus WRITE operations, and the final WRITE
operation latches the address and data in the internal state machine and starts the pro-
gram/erase controller. After programming has started, bus READ operations output the
status register content.
Programming can be suspended and then resumed by issuing a PROGRAM SUSPEND
command and a PROGRAM RESUME command, respectively.
If the address falls in a protected block, the PROGRAM command is ignored, and the
data remains unchanged. The status register is not read, and no error condition is given.
After the PROGRAM operation has completed, the device returns to read mode, unless
an error has occurred. When an error occurs, bus READ operations to the device contin-
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Program Operations
ue to output the status register. A READ/RESET command must be issued to reset the
error condition and return the device to read mode.
The PROGRAM command cannot change a bit set to 0 back to 1, and an attempt to do
so is masked during a PROGRAM operation. Instead, an ERASE command must be used
to set all bits in one memory block or in the entire memory from 0 to 1.
The PROGRAM operation is aborted by performing a reset or by powering-down the de-
vice. In this case, data integrity cannot be ensured, and it is recommended that the
words or bytes that were aborted be reprogrammed.
UNLOCK BYPASS PROGRAM Command
When the device is in unlock bypass mode, the UNLOCK BYPASS PROGRAM (A0h)
command can be used to program one address in the memory array. The command re-
quires two bus WRITE operations instead of four required by a standard PROGRAM
command; the final WRITE operation latches the address and data and starts the pro-
gram/erase controller (The standard PROGRAM command requires four bus WRITE op-
erations). The PROGRAM operation using the UNLOCK BYPASS PROGRAM command
behaves identically to the PROGRAM operation using the PROGRAM command. The
operation cannot be aborted. A bus READ operation to the memory outputs the status
register.
DOUBLE BYTE/WORD PROGRAM Command
The DOUBLE BYTE/WORD PROGRAM (50h) command is used to write a page of two
adjacent bytes/words in parallel. The two bytes/words must differ only for the address
A-1 or A0, respectively. Three bus write cycles are necessary to issue the command: The
first bus cycle sets up the command, the second bus cycle latches the address and data
of the first byte/word to be programmed, and the third bus cycle latches the address
and data of the second byte/word to be programmed and starts the program/erase con-
troller.
Note: The DOUBLE BYTE/WORD PROGRAM command is available only in the 32Mb
and 64Mb devices; also only VPPL is to be applied to the VPP/WP# pin.
QUADRUPLE BYTE/WORD PROGRAM Command
The QUADRUPLE BYTE/WORD PROGRAM (56h) command is used to write a page of
four adjacent bytes/words in parallel. The four bytes/words must differ for addresses
A0, DQ15/A-1 in x8 mode or for addresses A1, A0 in x16 mode. Five bus write cycles are
necessary to issue the command: The first bus cycle sets up the command, the second
bus cycle latches the address and data of the first byte/word to be programmed, the
third bus cycle latches the address and data of the second byte/word to be program-
med, the fourth bus cycle latches the address and data of the third byte/word to be pro-
grammed, and the fifth bus cycle latches the address and data of the fourth byte/word
to be programmed and starts the program/erase controller.
Note: The QUADRUPLE BYTE/WORD PROGRAM command is available only in the
32Mb and 64Mb devices; also only VPPL is to be applied to the VPP/WP# pin.
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Program Operations
OCTUPLE BYTE PROGRAM Command
The OCTUPLE BYTE PROGRAM (8Bh) command is used to write a page of eight adja-
cent bytes in parallel. The eight bytes must differ for addresses A1, A0, DQ15/A-1 in x8
mode only.
Nine bus write cycles are necessary to issue the command: The first bus cycle sets up
the command, the second bus cycle latches the address and data of the first byte to be
programmed, the third bus cycle latches the address and data of the second byte to be
programmed, the fourth bus cycle latches the address and data of the third byte to be
programmed, the fifth bus cycle latches the address and data of the fourth byte to be
programmed, the sixth bus cycle latches the address and data of the fifth byte to be pro-
grammed, the seventh bus cycle latches the address and data of the sixth byte to be pro-
grammed, the eighth bus cycle latches the address and data of the seventh byte to be
programmed, and the ninth bus cycle latches the address and data of the eighth byte to
be programmed, and starts the program/erase controller.
Note: The OCTUPLE BYTE PROGRAM command is available only in the 32Mb and
64Mb x8 devices; also only VPPL is to be applied to the VPP/WP# pin.
WRITE TO BUFFER PROGRAM Command
The WRITE TO BUFFER PROGRAM (25h) command makes use of the program buffer to
speed up programming and dramatically reduces system programming time compared
to the standard non-buffered PROGRAM command. 32Mb through 128Mb devices sup-
port a 256-word maximum program buffer.
When issuing a WRITE TO BUFFER PROGRAM command, V PP/WP# can be held HIGH
or raised to VPPH. Also, it can be held LOW if the block is not the lowest or highest block
or the top/bottom two blocks, depending on the part number. When VPPH is applied to
the VPP/WP# pin during execution of the command, programming speed increases (see
the Accelerated Program, Data Polling/Toggle AC Characteristics section).
The following successive steps are required to issue the WRITE TO BUFFER PROGRAM
command:
First, two UNLOCK cycles are issued. Next, a third bus WRITE cycle sets up the WRITE
TO BUFFER PROGRAM command. The set-up code can be addressed to any location
within the targeted block. Then, a fourth bus WRITE cycle sets up the number of words/
bytes to be programmed. Value n is written to the same block address, where n + 1 is the
number of words/bytes to be programmed. Value n + 1 must not exceed the size of the
program buffer, or the operation will abort. A fifth cycle loads the first address and data
to be programmed. Last, n bus WRITE cycles load the address and data for each word/
byte into the program buffer. Addresses must lie within the range from the start address
+1 to the start address + (n - 1).
Optimum programming performance and lower power usage are achieved by aligning
the starting address at the beginning of a 256-word boundary (A[7:0] = 0x000h). Any
buffer size smaller than 256 words is allowed within a 256-word boundary, while all ad-
dresses used in the operation must lie within the 256-word boundary. In addition, any
crossing boundary buffer program will result in a program abort. For a x8 device, maxi-
mum buffer size is 256 bytes; for a x16 device, the maximum buffer size is 512 bytes.
To program the content of the program buffer, this command must be followed by a
WRITE TO BUFFER PROGRAM CONFIRM command.
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Program Operations
If an address is written several times during a WRITE TO BUFFER PROGRAM operation,
the address/data counter will be decremented at each data load operation, and the data
will be programmed to the last word loaded into the buffer.
Invalid address combinations or the incorrect sequence of bus WRITE cycles will abort
the WRITE TO BUFFER PROGRAM command.
The status register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status
during a WRITE TO BUFFER PROGRAM operation.
The WRITE TO BUFFER PROGRAM command should not be used to change a bit set to
0 back to 1, and an attempt to do so is masked during the operation. Rather than the
WRITE TO BUFFER PROGRAM command, the ERASE command should be used to set
memory bits from 0 to 1.
Figure 10: Boundary Condition of Program Buffer Size
0000h
255 words
or less are
allowed
in the
program
buffer
256-word
program
buffer is
allowed
256 Words
Any
buffer
program
attempt
is not
0100h
allowed
256-word
program
256 Words
buffer is
allowed
0200h
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Program Operations
Figure 11: WRITE TO BUFFER PROGRAM Flowchart
Start
WRITE TO BUFFER
command,
WRITE TO BUFFER
confirm, block address
block address
Read status register
(DQ1, DQ5, DQ7) at
last loaded address
1
Write n,
block address
First three cycles of the
WRITE TO BUFFER
PROGRAM command
Write buffer data,
start address
Yes
DQ7 = Data
No
X = n
No
No
DQ1 = 1
Yes
DQ5 = 1
Yes
Yes
Yes
X = 0
No
Check status register
(DQ5, DQ7) at
last loaded address
Abort
WRITE TO BUFFER
Write to a different
block address
Yes
No
4
DQ7 = Data
WRITE TO BUFFER
and PROGRAM
3
Write next data,
program address pair
2
aborted
No
Fail or
abort
End
5
X = X - 1
1. n + 1 is the number of addresses to be programmed.
Notes:
2. The BUFFERED PROGRAM ABORT and RESET command must be issued to return the de-
vice to read mode.
3. When the block address is specified, any address in the selected block address space is
acceptable. However, when loading program buffer address with data, all addresses
must fall within the selected program buffer page.
4. DQ7 must be checked because DQ5 and DQ7 may change simultaneously.
5. If this flowchart location is reached because DQ5 = 1, then the WRITE TO BUFFER PRO-
GRAM command failed. If this flowchart location is reached because DQ1 = 1, then the
WRITE TO BUFFER PROGRAM command aborted. In both cases, the appropriate RESET
command must be issued to return the device to read mode: A RESET command if the
operation failed; a WRITE TO BUFFER PROGRAM ABORT AND RESET command if the op-
eration aborted.
6. See the Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit table for
details about the WRITE TO BUFFER PROGRAM command sequence.
UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command
When the device is in unlock bypass mode, the UNLOCK BYPASS WRITE TO BUFFER
(25h) command can be used to program the device in fast program mode. The com-
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Program Operations
mand requires two bus WRITE operations fewer than the standard WRITE TO BUFFER
PROGRAM command.
The UNLOCK BYPASS WRITE TO BUFFER PROGRAM command behaves the same way
as the WRITE TO BUFFER PROGRAM command: the operation cannot be aborted, and
a bus READ operation to the memory outputs the status register.
The WRITE TO BUFFER PROGRAM CONFIRM command is used to confirm an UN-
LOCK BYPASS WRITE TO BUFFER PROGRAM command and to program the n + 1
words/bytes loaded in the program buffer by this command.
ENHANCED WRITE TO BUFFER PROGRAM Command
The ENHANCED WRITE TO BUFFER PROGRAM (33h) command enables loading 256
words into the writer buffer to reduce system programming time. Each write buffer has
the same A[22:8] addresses. Execution speed is identical to the 256-word WRITE TO
BUFFER program speed (See the Program/Erase Characteristics table for details).
When issuing this command, the VPP/WP# pin can be held HIGH or raised to VPPH (pro-
gramming acceleration).
Note: The ENHANCED WRITE TO BUFFER PROGRAM command is available only in
the 128Mb x16 device,
The following successive steps are required to issue the command: Two unlock cycles
begin the command, followed by a third bus write cycle that sets up the command with
setup code that can be addressed to any location within the targeted block. The fourth
bus write cycle loads the first address and data to be programmed. There are a total of
256 address and data loading cycles.
The command must be followed by an ENHANCED WRITE TO BUFFER PROGRAM
CONFIRM command to program the buffer content, which confirm cycle ends the
command.
Note that address/data cycles must be loaded in an increasing address order (A[7:0]
from 00h to FFh) that includes all 256 words. Invalid address combinations or the cor-
rect sequence of bus write cycles will result in an abort.
Status register bits DQ1, DQ5, DQ6, and DQ7 enable monitoring the device status dur-
ing operation. A 12V external supply can be used to improve programming efficiency.
The ENHANCED WRITE TO BUFFER PROGRAM command should not be used to
change a bit set to 0 back to 1. Any attempt to do so is masked during the operation. The
ERASE command should be used to set memory bits from 0 to 1.
UNLOCK BYPASS ENHANCED WRITE TO BUFFER PROGRAM Command
The UNLOCK BYPASS ENHANCED WRITE TO BUFFER PROGRAM (33h)command can
be used to program the memory in fast program mode. The command requires two ad-
dress/data loading cycles less than the regular ENHANCED WRITE TO BUFFER PRO-
GRAM command. This command behaves identically to the ENHANCED WRITE TO
BUFFER PROGRAM command. The operation cannot be aborted and a bus read opera-
tion to the memory outputs the status register. This command is confirmed by the EN-
HANCED WRITE TO BUFFER PROGRAM CONFIRM command, which programs the
256 words loaded in the buffer.
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Program Operations
WRITE TO BUFFER PROGRAM CONFIRM Command
The WRITE TO BUFFER PROGRAM CONFIRM (29h) command is used to confirm a
WRITE TO BUFFER PROGRAM command and to program the n + 1 words/bytes loaded
in the program buffer by this command.
ENHANCED WRITE TO BUFFER PROGRAM CONFIRM Command
The ENHANCED WRITE TO BUFFER PROGRAM CONFIRM (29h) command is used to
confirm an ENHANCED WRITE TO BUFFER PROGRAM command and to program the
256 words loaded in the buffer.
BUFFERED PROGRAM ABORT AND RESET Command
A BUFFERED PROGRAM ABORT AND RESET (F0h) command must be issued to reset
the device to read mode when the BUFFER PROGRAM operation is aborted. The buffer
programming sequence can be aborted in the following ways:
• Load a value that is greater than the page buffer size during the number of locations
to program in the WRITE TO BUFFER PROGRAM command.
• Write to an address in a different block than the one specified during the WRITE BUF-
FER LOAD command.
• Write an address/data pair to a different write buffer page than the one selected by
the starting address during the program buffer data loading stage of the operation.
• Write data other than the CONFIRM command after the specified number of data
load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DQ7# (for the last address location
loaded), DQ6 = toggle, and DQ5 = 0 (all of which are status register bits). A BUFFERED
PROGRAM ABORT and RESET command sequence must be written to reset the device
for the next operation.
Note: The full three-cycle BUFFERED PROGRAM ABORT and RESET command se-
quence is required when using buffer programming features in unlock bypass mode.
PROGRAM SUSPEND Command
The PROGRAM SUSPEND (B0h) command can be used to interrupt a program opera-
tion so that data can be read from any block. When the PROGRAM SUSPEND command
is issued during a program operation, the device suspends the operation within the pro-
gram suspend latency time and updates the status register bits.
After the program operation has been suspended, data can be read from any address.
However, data is invalid when read from an address where a program operation has
been suspended.
The PROGRAM SUSPEND command may also be issued during a PROGRAM operation
while an erase is suspended. In this case, data may be read from any address not in
erase suspend or program suspend mode. To read from the extended memory block
area (one-time programmable area), the ENTER/EXIT EXTENDED MEMORY BLOCK
command sequences must be issued.
The system may also issue the AUTO SELECT command sequence when the device is in
program suspend mode. The system can read as many auto select codes as required.
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Erase Operations
When the device exits auto select mode, the device reverts to program suspend mode
and is ready for another valid operation.
The PROGRAM SUSPEND operation is aborted by performing a device reset or power-
down. In this case, data integrity cannot be ensured, and it is recommended that the
words or bytes that were aborted be reprogrammed.
PROGRAM RESUME Command
The PROGRAM RESUME (30h) command must be issued to exit a program suspend
mode and resume a PROGRAM operation. The controller can use DQ7 or DQ6 status
bits to determine the status of the PROGRAM operation. After a PROGRAM RESUME
command is issued, subsequent PROGRAM RESUME commands are ignored. Another
PROGRAM SUSPEND command can be issued after the device has resumed program-
ming.
Erase Operations
CHIP ERASE Command
The CHIP ERASE (80/10h) command erases the entire chip. Six bus WRITE operations
are required to issue the command and start the program/erase controller.
Protected blocks are not erased. If all blocks are protected, the CHIP ERASE operation
appears to start, but will terminate within approximately100μs, leaving the data un-
changed. No error is reported when protected blocks are not erased.
During the CHIP ERASE operation, the device ignores all other commands, including
ERASE SUSPEND. It is not possible to abort the operation. All bus READ operations dur-
ing CHIP ERASE output the status register on the data I/Os. See the Status Register sec-
tion for more details.
After the CHIP ERASE operation completes, the device returns to read mode, unless an
error has occurred. If an error occurs, the device will continue to output the status regis-
ter. A READ/RESET command must be issued to reset the error condition and return to
read mode.
The CHIP ERASE command sets all of the bits in unprotected blocks of the device to 1.
All previous data is lost.
The operation is aborted by performing a reset or by powering-down the device. In this
case, data integrity cannot be ensured, and it is recommended that the entire chip be
erased again.
UNLOCK BYPASS CHIP ERASE Command
When the device is in unlock bypass mode, the UNLOCK BYPASS CHIP ERASE (80/10h)
command can be used to erase all memory blocks at one time. The command requires
only two bus WRITE operations instead of six using the standard CHIP ERASE com-
mand. The final bus WRITE operation starts the program/erase controller.
The UNLOCK BYPASS CHIP ERASE command behaves the same way as the CHIP
ERASE command: the operation cannot be aborted, and a bus READ operation to the
memory outputs the status register.
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Erase Operations
BLOCK ERASE Command
The BLOCK ERASE (80/30h) command erases a list of one or more blocks. It sets all of
the bits in the unprotected selected blocks to 1. All previous data in the selected blocks
is lost.
Six bus WRITE operations are required to select the first block in the list. Each addition-
al block in the list can be selected by repeating the sixth bus WRITE operation using the
address of the additional block. After the command sequence is written, a block erase
timeout occurs. During the timeout period, additional block addresses and BLOCK
ERASE commands can be written. After the program/erase controller has started, it is
not possible to select any more blocks. Each additional block must therefore be selected
within the timeout period of the last block. The timeout timer restarts when an addi-
tional block is selected. After the sixth bus WRITE operation, a bus READ operation out-
puts the status register. See the WE#-Controlled Program waveforms for details on how
to identify if the program/erase controller has started the BLOCK ERASE operation.
After the BLOCK ERASE operation completes, the device returns to read mode, unless
an error has occurred. If an error occurs, bus READ operations will continue to output
the status register. A READ/RESET command must be issued to reset the error condi-
tion and return to read mode.
If any selected blocks are protected, they are ignored, and all the other selected blocks
are erased. If all of the selected blocks are protected, the BLOCK ERASE operation ap-
pears to start, but will terminate within approximately100μs, leaving the data un-
changed. No error condition is given when protected blocks are not erased.
During the BLOCK ERASE operation, the device ignores all commands except the
ERASE SUSPEND command and the READ/RESET command, which is accepted only
during the timeout period. The operation is aborted by performing a reset or powering-
down the device. In this case, data integrity cannot be ensured, and it is recommended
that the aborted blocks be erased again.
UNLOCK BYPASS BLOCK ERASE Command
When the device is in unlock bypass mode, the UNLOCK BYPASS BLOCK ERASE
(80/30h) command can be used to erase one or more memory blocks at a time. The
command requires two bus WRITE operations instead of six using the standard BLOCK
ERASE command. The final bus WRITE operation latches the address of the block and
starts the program/erase controller.
To erase multiple blocks (after the first two bus WRITE operations have selected the first
block in the list), each additional block in the list can be selected by repeating the sec-
ond bus WRITE operation using the address of the additional block.
The UNLOCK BYPASS BLOCK ERASE command behaves the same way as the BLOCK
ERASE command: the operation cannot be aborted, and a bus READ operation to the
memory outputs the status register. See the BLOCK ERASE Command section for de-
tails.
ERASE SUSPEND Command
The ERASE SUSPEND (B0h) command temporarily suspends a BLOCK ERASE opera-
tion. One bus WRITE operation is required to issue the command. The block address is
"Don't Care."
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BLANK CHECK Operation
The program/erase controller suspends the ERASE operation within the erase suspend
latency time of the ERASE SUSPEND command being issued. However, when the
ERASE SUSPEND command is written during the block erase timeout, the device im-
mediately terminates the timeout period and suspends the ERASE operation. After the
program/erase controller has stopped, the device operates in read mode, and the erase
is suspended.
During an ERASE SUSPEND operation, it is possible to read and execute PROGRAM op-
erations or WRITE TO BUFFER PROGRAM operations in blocks that are not suspended.
Both READ and PROGRAM operations behave normally on these blocks. Reading from
blocks that are suspended will output the status register. If any attempt is made to pro-
gram in a protected block or in the suspended block, the PROGRAM command is ignor-
ed, and the data remains unchanged. In this case, the status register is not read, and no
error condition is given.
It is also possible to issue AUTO SELECT, READ CFI, and UNLOCK BYPASS commands
during an ERASE SUSPEND operation. The READ/RESET command must be issued to
return the device to read array mode before the RESUME command will be accepted.
During an ERASE SUSPEND operation, a bus READ operation to the extended memory
block will output the extended memory block data. After the device enters extended
memory block mode, the EXIT EXTENDED MEMORY BLOCK command must be issued
before the ERASE operation can be resumed.
An ERASE SUSPEND command is ignored if it is written during a CHIP ERASE opera-
tion.
If the ERASE SUSPEND operation is aborted by performing a device reset or power-
down, data integrity cannot be ensured, and it is recommended that the suspended
blocks be erased again.
ERASE RESUME Command
The ERASE RESUME (30h) command restarts the program/erase controller after an
ERASE SUSPEND operation.
The device must be in read array mode before the RESUME command will be accepted.
An erase can be suspended and resumed more than once.
BLANK CHECK Operation
BLANK CHECK Commands
Two commands are required to execute a BLANK CHECK operation: BLANK CHECK
SETUP (EB/76h) and BLANK CHECK CONFIRM AND READ (29h).
The BLANK CHECK operation determines whether a specified block is blank (that is,
completely erased). It can also be used to determine whether a previous ERASE opera-
tion was successful, including ERASE operations that might have been interrupted by
power loss.
The BLANK CHECK operation checks for cells that are programmed or over-erased. If it
finds any, it returns a failure status, indicating that the block is not blank. If it returns a
passing status, the block is guaranteed blank (all 1s) and is ready to program.
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BLANK CHECK Operation
Before executing, the ERASE operation initiates a BLANK CHECK operation, and if the
target block is blank, the ERASE operation is skipped, benefitting overall cycle perform-
ance; otherwise, the ERASE operation continues.
The BLANK CHECK operation can occur in only one block at a time, and during its exe-
cution, reading the status register is the only other operation allowed. Reading from any
address in the device enables reading the status register to monitor blank check pro-
gress or errors. Operations such as READ (array data), PROGRAM, ERASE, and any sus-
pended operation are not allowed.
After the BLANK CHECK operation has completed, the device returns to read mode un-
less an error has occurred. When an error occurs, the device continues to output status
register data. A READ/RESET command must be issued to reset the error condition and
return the device to read mode.
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Block Protection Command Definitions – Address-Data Cycles
Block Protection Command Definitions – Address-Data Cycles
Table 20: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit
Notes 1 and 2 apply to entire table
Address and Data Cycles
1st
2nd
3rd
4th
nth
Command and
Code/Subcode
Bus
Size
A
D
A
D
A
D
A
D
…
A
D
Notes
LOCK REGISTER Commands
ENTER LOCK REGISTER
COMMAND SET (40h)
x8
x16
x8
AAA
555
X
AA
AA
A0
555
55
55
AAA
555
40
3
5
2AA
X
PROGRAM LOCK REGISTER
(A0h)
Data
x16
x8
READ LOCK REGISTER
X
Data
4, 5, 6
x16
PASSWORD PROTECTION Commands
ENTER PASSWORD
PROTECTION COMMAND
SET (60h)
x8
AAA
555
AA
AA
555
55
55
AAA
555
60
3
7
x16
2AA
PROGRAM PASSWORD
(A0h)
x8
x16
x8
X
A0
PWAn PWDn
READ PASSWORD
00
00
00
PWD0
PWD0
25
01
01
00
PWD1
PWD1
03
02
02
00
PWD2 03 PWD3 … 07 PWD7 4, 6, 8,
9
x16
x8
PWD2 03 PWD3
UNLOCK PASSWORD (25h/
03h)
PWD0 01 PWD1 … 00
29
8, 10
x16
NONVOLATILE PROTECTION Commands
ENTER NONVOLATILE
PROTECTION COMMAND
SET (C0h)
x8
AAA
555
AA
AA
555
55
55
AAA
555
C0
3
x16
2AA
PROGRAM NONVOLATILE
PROTECTION BIT (A0h)
x8
x16
x8
X
A0
BAd
00
11
READ NONVOLATILE
PROTECTION BIT STATUS
BAd READ(0)
4, 6,
11
x16
x8
CLEAR ALL NONVOLATILE
PROTECTION BITS (80/30h)
X
80
00
30
12
x16
NONVOLATILE PROTECTION BIT LOCK BIT Commands
ENTER NONVOLATILE
PROTECTION BIT LOCK BIT
COMMAND SET (50h)
x8
AAA
555
AA
AA
555
55
55
AAA
555
50
3
x16
2AA
PROGRAM NONVOLATILE
PROTECTION BIT LOCK BIT
(A0h)
x8
X
A0
X
00
11
x16
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Block Protection Command Definitions – Address-Data Cycles
Table 20: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit (Continued)
Notes 1 and 2 apply to entire table
Address and Data Cycles
1st
2nd
3rd
4th
nth
Command and
Code/Subcode
Bus
Size
A
D
A
D
A
D
A
D
…
A
D
Notes
READ NONVOLATILE
PROTECTION BIT LOCK BIT
STATUS
x8
X
READ(0)
4, 6,
11
x16
VOLATILE PROTECTION Commands
ENTER VOLATILE
PROTECTION COMMAND
SET (E0h)
x8
AAA
555
AA
AA
555
55
55
AAA
555
E0
3
x16
2AA
PROGRAM VOLATILE
PROTECTION BIT (A0h)
x8
x16
x8
X
A0
BAd
00
11
4, 6
11
READ VOLATILE
PROTECTION BIT STATUS
BAd READ(0)
x16
x8
CLEAR VOLATILE
X
A0
BAd
01
PROTECTION BIT (A0h)
x16
EXTENDED MEMORY BLOCK Commands
ENTER EXTENDED
MEMORY BLOCK (88h)
x8
x16
x8
AAA
555
AA
AA
AA
AA
555
2AA
555
55
55
55
55
AAA
555
88
90
3
EXIT EXTENDED
MEMORY BLOCK (90/00h)
AAA
555
AAA
555
X
00
x16
2AA
EXIT PROTECTION Commands
EXIT PROTECTION
COMMAND SET (90/00h)
x8
x16
X
90
X
00
3
1. Key: A = Address and D = Data; X = "Don’t Care;" BAd = any address in the block; PWDn
= password bytes 0 to 7; PWAn = password address, n = 0 to 7; Gray = not applicable. All
values in the table are hexadecimal.
Notes:
2. DQ[15:8] are "Don’t Care" during UNLOCK and COMMAND cycles. A[MAX:16] are
"Don’t Care" during UNLOCK and COMMAND cycles, unless an address is required.
3. The ENTER command sequence must be issued prior to any operation. It disables READ
and WRITE operations from and to block 0. READ and WRITE operations from and to
any other block are allowed. Also, when an ENTER COMMAND SET command is issued,
an EXIT PROTECTION COMMAND SET command must be issued to return the device to
READ mode.
4. READ REGISTER/PASSWORD commands have no command code; CE# and OE# are driven
LOW and data is read according to a specified address.
5. Data = Lock register content.
6. All address cycles shown for this command are READ cycles.
7. Only one portion of the password can be programmed or read by each PROGRAM PASS-
WORD command.
8. Each portion of the password can be entered or read in any order as long as the entire
64-bit password is entered or read.
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Block Protection Command Definitions – Address-Data Cycles
9. For the x8 READ PASSWORD command, the nth (and final) address cycle equals the 8th
address cycle. From the 5th to the 8th address cycle, the values for each address and da-
ta pair continue the pattern shown in the table as follows: for x8, address and data = 04
and PWD4; 05 and PWD5; 06 and PWD6; 07 and PWD7.
10. For the x8 UNLOCK PASSWORD command, the nth (and final) address cycle equals the
11th address cycle. From the 5th to the 10th address cycle, the values for each address
and data pair continue the pattern shown in the table as follows: address and data = 02
and PWD2; 03 and PWD3; 04 and PWD4; 05 and PWD5; 06 and PWD6; 07 and PWD7.
For the x16 UNLOCK PASSWORD command, the nth (and final) address cycle equals the
7th address cycle. For the 5th and 6th address cycles, the values for the address and data
pair continue the pattern shown in the table as follows: address and data = 02 and
PWD2; 03 and PWD3.
11. Both nonvolatile and volatile protection bit settings are as follows: Protected state = 00;
Unprotected state= 01.
12. The CLEAR ALL NONVOLATILE PROTECTION BITS command programs all nonvolatile pro-
tection bits before erasure. This prevents over-erasure of previously cleared nonvolatile
protection bits.
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Protection Operations
Protection Operations
Blocks can be protected individually against accidental PROGRAM, ERASE, or READ op-
erations on both 8-bit and 16-bit configurations. The block protection scheme is shown
in the Software Protection Scheme figure.
Memory block and extended memory block protection is configured through the lock
register (see Lock Register section).
LOCK REGISTER Commands
After the ENTER LOCK REGISTER COMMAND SET (40h) command has been issued, all
bus READ or PROGRAM operations can be issued to the lock register.
The PROGRAM LOCK REGISTER (A0h) command allows the lock register to be config-
ured. The programmed data can then be checked with a READ LOCK REGISTER com-
mand by driving CE# and OE# LOW with the appropriate address data on the address
bus.
PASSWORD PROTECTION Commands
After the ENTER PASSWORD PROTECTION COMMAND SET (60h) command has been
issued, the commands related to password protection mode can be issued to the device.
The PROGRAM PASSWORD (A0h) command is used to program the 64-bit password
used in the password protection mode. To program the 64-bit password, the complete
command sequence must be entered eight times at eight consecutive addresses selec-
ted by A[1:0] plus DQ15/A-1 in 8-bit mode, or four times at four consecutive addresses
selected by A[1:0] in 16-bit mode. By default, all password bits are set to 1. The password
can be checked by issuing a READ PASSWORD command.
The READ PASSWORD command is used to verify the password used in password pro-
tection mode. To verify the 64-bit password, the complete command sequence must be
entered eight times at eight consecutive addresses selected by A[1:0] plus DQ15/A-1 in
8-bit mode, or four times at four consecutive addresses selected by A[1:0] in 16-bit
mode. If the password mode lock bit is programmed and the user attempts to read the
password, the device will output FFh onto the I/O data bus.
The UNLOCK PASSWORD (25/03h) command is used to clear the nonvolatile protec-
tion bit lock bit, allowing the nonvolatile protection bits to be modified. The UNLOCK
PASSWORD command must be issued, along with the correct password, and requires a
1μs delay between successive UNLOCK PASSWORD commands in order to prevent
hackers from cracking the password by trying all possible 64-bit combinations. If this
delay does not occur, the latest command will be ignored. Approximately 1μs is required
for unlocking the device after the valid 64-bit password has been provided.
NONVOLATILE PROTECTION Commands
After the ENTER NONVOLATILE PROTECTION COMMAND SET (C0h) command has
been issued, the commands related to nonvolatile protection mode can be issued to the
device.
A block can be protected from program or erase by issuing a PROGRAM NONVOLATILE
PROTECTION BIT (A0h) command, along with the block address. This command sets
the nonvolatile protection bit to 0 for a given block.
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Protection Operations
The status of a nonvolatile protection bit for a given block or group of blocks can be
read by issuing a READ NONVOLATILE MODIFY PROTECTION BIT command, along
with the block address.
The nonvolatile protection bits are erased simultaneously by issuing a CLEAR ALL
NONVOLATILE PROTECTION BITS (80/30h) command. No specific block address is re-
quired. If the nonvolatile protection bit lock bit is set to 0, the command fails.
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Protection Operations
Figure 12: Program/Erase Nonvolatile Protection Bit Algorithm
Start
ENTER Nonvolatile
Protection
COMMAND SET
PROGRAM Nonvolatile
Protection Bit
Addr = BAd
Read byte twice
Addr = BAd
No
DQ6 = Toggle
Yes
No
DQ5 = 1
Yes
Wait 500µs
Read byte twice
Addr = BAd
No
Read byte twice
Addr = BAd
DQ6 = Toggle
Yes
DQ0 =
1 (erase)
0 (program)
No
Yes
Fail
Reset
Pass
EXIT PROTECTION
COMMAND SET
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Protection Operations
NONVOLATILE PROTECTION BIT LOCK BIT Commands
After the ENTER NONVOLATILE PROTECTION BIT LOCK BIT COMMAND SET (50h)
command has been issued, the commands that allow the nonvolatile protection bit lock
bit to be set can be issued to the device.
The PROGRAM NONVOLATILE PROTECTION BIT LOCK BIT (A0h) command is used to
set the nonvolatile protection bit lock bit to 0, thus locking the nonvolatile protection
bits and preventing them from being modified.
The READ NONVOLATILE PROTECTION BIT LOCK BIT STATUS command is used to
read the status of the nonvolatile protection bit lock bit.
VOLATILE PROTECTION Commands
After the ENTER VOLATILE PROTECTION COMMAND SET (E0h) command has been
issued, commands related to the volatile protection mode can be issued to the device.
The PROGRAM VOLATILE PROTECTION BIT (A0h) command individually sets a vola-
tile protection bit to 0 for a given block. If the nonvolatile protection bit for the same
block is set, the block is locked regardless of the value of the volatile protection bit. (See
the Block Protection Status table.)
The status of a volatile protection bit for a given block can be read by issuing a READ
VOLATILE PROTECTION BIT STATUS command along with the block address.
The CLEAR VOLATILE PROTECTION BIT (A0h) command individually clears (sets to 1)
the volatile protection bit for a given block. If the nonvolatile protection bit for the same
block is set, the block is locked regardless of the value of the volatile protection bit. (See
the Block Protection Status table.)
EXTENDED MEMORY BLOCK Commands
The device has one extra 128-word extended memory block that can be accessed only
by the ENTER EXTENDED MEMORY BLOCK (88h) command. The extended memory
block is 128 words (x16) or 256 bytes (x8). It is used as a security block to provide a per-
manent 128-bit security identification number or to store additional information. The
device can be shipped with the extended memory block prelocked permanently by Mi-
cron, including the 128-bit security identification number. Or, the device can be ship-
ped with the extended memory block unlocked, enabling customers to permanently
program and lock it. (See Lock Register, the AUTO SELECT command, and the Block
Protection table.)
Table 21: Extended Memory Block Address and Data
Address
x16
Data
x8
Micron prelocked
Customer Lockable
000000h–00000Fh 000000h–000007h
000010h–0000FFh 000008h–00007Fh
Secure ID number
Determined by customer
Secure ID number
Determined by customer
Protected and
unavailable
After the ENTER EXTENDED MEMORY BLOCK command has been issued, the device
enters the extended memory block mode. All bus READ or PROGRAM operations are
conducted on the extended memory block, and the extended memory block is ad-
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Protection Operations
dressed using the addresses occupied by block 0 in the other operating modes (see the
Memory Map table).
In extended memory block mode, ERASE, CHIP ERASE, ERASE SUSPEND, and ERASE
RESUME commands are not allowed. The extended memory block cannot be erased,
and each bit of the extended memory block can only be programmed once.
The extended memory block is protected from further modification by programming
lock register bit 0. Once invoked, this protection cannot be undone.
The device remains in extended memory block mode until the EXIT EXTENDED MEM-
ORY BLOCK (90/00h) command is issued, which returns the device to read mode, or
until power is removed from the device. After a power-up sequence or hardware reset,
the device will revert to reading memory blocks in the main array.
EXIT PROTECTION Command
The EXIT PROTECTION COMMAND SET (90/00h) command is used to exit the lock
register, password protection, nonvolatile protection, volatile protection, and nonvola-
tile protection bit lock bit command set modes and return the device to read mode.
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Device Protection
Device Protection
Hardware Protection
The VPP/WP# function provides a hardware method of protecting either the highest/
lowest block or the top/bottom two blocks. When VPP/WP# is LOW, PROGRAM and
ERASE operations on either of these block options is ignored to provide protection.
When VPP/WP# is HIGH, the device reverts to the previous protection status for the
highest/lowest block or top/bottom two blocks. PROGRAM and ERASE operations can
modify the data in either of these block options unless block protection is enabled.
Note: Micron highly recommends driving VPP/WP# HIGH or LOW. If a system needs to
float the VPP/WP# pin, without a pull-up/pull-down resistor and no capacitor, then an
internal pull-up resistor is enabled.
Table 22: VPP/WP# Functions
VPP/WP# Settings
Function
VIL
Highest/lowest block or the top/bottom two blocks are protected.
VIH
Highest/lowest block or the top/bottom two blocks are unprotected unless software pro-
tection is activated.
Software Protection
Four software protection modes are available:
• Volatile protection
• Nonvolatile protection
• Password protection
• Password access
The device is shipped with all blocks unprotected. On first use, the device defaults to
the nonvolatile protection mode but can be activated in either the nonvolatile protec-
tion or password protection mode.
The desired protection mode is activated by setting either the nonvolatile protection
mode lock bit or the password protection mode lock bit of the lock register (see the Lock
Register section). Both bits are one-time-programmable and nonvolatile; therefore, af-
ter the protection mode has been activated, it cannot be changed, and the device is set
permanently to operate in the selected protection mode. It is recommended that the
desired software protection mode be activated when first programming the device.
For the lowest and highest blocks or for the top/bottom two blocks, a higher level of
block protection can be achieved by locking the blocks using nonvolatile protection
mode and holding VPP /WP# LOW.
Blocks with volatile protection and nonvolatile protection can coexist within the memo-
ry array. If the user attempts to program or erase a protected block, the device ignores
the command and returns to read mode.
The block protection status can be read by performing a read electronic signature or by
issuing an AUTO SELECT command (see the Block Protection table).
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Device Protection
Refer to the Block Protection Status table and the Software Protection Scheme figure for
details on the block protection scheme. Refer to the Protection Operations section for a
description of the command sets.
Volatile Protection Mode
Volatile protection enables the software application to protect blocks against inadver-
tent change and can be disabled when changes are needed. Volatile protection bits are
unique for each block and can be individually modified. Volatile protection bits control
the protection scheme only for unprotected blocks whose nonvolatile protection bits
are cleared to 1. Issuing a PROGRAM VOLATILE PROTECTION BIT or CLEAR VOLATILE
PROTECTION BIT command sets to 0 or clears to 1 the volatile protection bits and pla-
ces the associated blocks in the protected (0) or unprotected (1) state, respectively. The
volatile protection bit can be set or cleared as often as needed.
When the device is first shipped, or after a power-up or hardware reset, the volatile pro-
tection bits default to 1 (unprotected).
Nonvolatile Protection Mode
A nonvolatile protection bit is assigned to each block. Each of these bits can be set for
protection individually by issuing a PROGRAM NONVOLATILE PROTECTION BIT com-
mand. Also, each device has one global volatile bit called the nonvolatile protection bit
lock bit; it can be set to protect all nonvolatile protection bits at once. This global bit
must be set to 0 only after all nonvolatile protection bits are configured to the desired
settings. When set to 0, the nonvolatile protection bit lock bit prevents changes to the
state of the nonvolatile protection bits. When cleared to 1, the nonvolatile protection
bits can be set and cleared using the PROGRAM NONVOLATILE PROTECTION BIT and
CLEAR ALL NONVOLATILE PROTECTION BITS commands, respectively.
No software command unlocks the nonvolatile protection bit lock bit unless the device
is in password protection mode; in nonvolatile protection mode, the nonvolatile protec-
tion bit lock bit can be cleared only by taking the device through a hardware reset or
power-up.
Nonvolatile protection bits cannot be cleared individually; they must be cleared all at
once using a CLEAR ALL NONVOLATILE PROTECTION BITS command. They will re-
main set through a hardware reset or a power-down/power-up sequence.
If one of the nonvolatile protection bits needs to be cleared (unprotected), additional
steps are required: First, the nonvolatile protection bit lock bit must be cleared to 1, us-
ing either a power-cycle or hardware reset. Then, the nonvolatile protection bits can be
changed to reflect the desired settings. Finally, the nonvolatile protection bit lock bit
must be set to 0 to lock the nonvolatile protection bits. The device now will operate nor-
mally.
To achieve the best protection, the PROGRAM NONVOLATILE PROTECTION LOCK BIT
command should be executed early in the boot code, and the boot code should be pro-
tected by holding VPP/WP# LOW.
Nonvolatile protection bits and volatile protection bits have the same function when
VPP/WP# is HIGH or when VPP/WP# is at the voltage for program acceleration (VPPH ).
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Device Protection
Password Protection Mode
The password protection mode provides a higher level of security than the nonvolatile
protection mode by requiring a 64-bit password to unlock the nonvolatile protection bit
lock bit. In addition to this password requirement, the nonvolatile protection bit lock
bit is set to 0 after power-up and reset to maintain the device in password protection
mode.
Executing the UNLOCK PASSWORD command by entering the correct password clears
the nonvolatile protection bit lock bit, enabling the block nonvolatile protection bits to
be modified. If the password provided is incorrect, the nonvolatile protection bit lock
bit remains locked, and the state of the nonvolatile protection bits cannot be modified.
To place the device in password protection mode, the following two steps are required:
First, before activating the password protection mode, a 64-bit password must be set
and the setting verified. Password verification is allowed only before the password pro-
tection mode is activated. Next, password protection mode is activated by program-
ming the password protection mode lock bit to 0. This operation is irreversible. After the
bit is programmed, it cannot be erased, the device remains permanently in password
protection mode, and the 64-bit password can be neither retrieved nor reprogrammed.
In addition, all commands to the address where the password is stored are disabled.
Note: There is no means to verify the password after password protection mode is ena-
bled. If the password is lost after enabling the password protection mode, there is no
way to clear the nonvolatile protection bit lock bit.
Password Access
Password access is a security enhancement that protects information stored in the main
array blocks by preventing content alteration or reads until a valid 64-bit password is
received. Password access may be combined with nonvolatile and/or volatile protection
to create a multi-tiered solution. Contact your Micron sales representative for further
details.
Figure 13: Software Protection Scheme
Volatile protection bit
Nonvolatile protection bit
1 = unprotected (default)
1 = unprotected
0 = protected
0 = protected
(Default setting depends on the product order option)
Volatile
protection
Nonvolatile
protection
Nonvolatile protection bit lock bit (volatile)
Array block
1 = unlocked (default, after power-up or hardware reset)
0 = locked
Nonvolatile protection
mode
Password protection
mode
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Device Protection
1. Volatile protection bits are programmed and cleared individually. Nonvolatile protection
bits are programmed individually and cleared collectively.
Notes:
2. Once programmed to 0, the nonvolatile protection bit lock bit can be reset to 1 only by
taking the device through a power-up or hardware reset.
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Common Flash Interface
Common Flash Interface
The common Flash interface (CFI) is a JEDEC-approved, standardized data structure
that can be read from the Flash memory device. It allows a system's software to query
the device to determine various electrical and timing parameters, density information,
and functions supported by the memory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when necessary.
When the READ CFI QUERY command is issued, the device enters CFI query mode and
the data structure is read from memory. The following tables show the addresses (A-1,
A[7:0]) used to retrieve the data. The query data is always presented on the lowest order
data outputs (DQ[7:0]), and the other data outputs (DQ[15:8]) are set to 0.
Table 23: Query Structure Overview
Note 1 applies to the entire table
Address
x16
10h
1Bh
27h
40h
x8
Subsection Name
Description
20h
36h
4Eh
80h
CFI query identification string
System interface information
Device geometry definition
Command set ID and algorithm data offset
Device timing and voltage information
Flash device layout
Primary algorithm-specific extended query table Additional information specific to the primary al-
gorithm (optional)
1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8]
are set to 0.
Note:
Table 24: CFI Query Identification String
Note 1 applies to the entire table
Address
x16
10h
11h
12h
x8
Data Description
Value
"Q"
"R"
"Y"
–
20h
22h
24h
0051h Query unique ASCII string "QRY"
0052h
0059h
13h
14h
26h
28h
0002h Primary algorithm command set and control interface ID code 16-bit ID
0000h code defining a specific algorithm
15h
16h
2Ah
2Ch
0040h Address for primary algorithm extended query table (see the Primary Algo-
0000h rithm-Specific Extended Query Table)
P = 40h
17h
18h
2Eh
30h
0000h Alternate vendor command set and control Interface ID code second ven-
0000h dor-specified algorithm supported
–
–
19h
1Ah
32h
34h
0000h Address for alternate algorithm extended query table
0000h
1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8]
are set to 0.
Note:
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Common Flash Interface
Table 25: CFI Query System Interface Information
Note 1 applies to the entire table
Address
x16
x8
Data
Description
Value
1Bh
36h
0027h
VCC logic supply minimum program/erase voltage
Bits[7:4] BCD value in volts
2.7V
Bits[3:0] BCD value in 100mV
1Ch
1Dh
1Eh
38h
3Ah
3Ch
0036h
00B5h
00C5h
VCC logic supply maximum program/erase voltage
Bits[7:4] BCD value in volts
Bits[3:0] BCD value in 100mV
3.6V
11.5V
12.5V
VPPH (programming) supply minimum program/erase voltage
Bits[7:4] hex value in volts
Bits[3:0] BCD value in 100mV
VPPH (programming) supply maximum program/erase voltage
Bits[7:4] hex value in volts
Bits[3:0] BCD value in 100mV
1Fh
20h
21h
22h
3Eh
40h
42h
44h
0004h
0009h
0009h
000Fh
0010h
0011h
0004h
0002h
0003h
0002h
0002h
0002h
Typical timeout for single byte/word program = 2nμs
Typical timeout for maximum size buffer program = 2nμs
Typical timeout per individual block erase = 2nms
Typical timeout for full chip erase = 2nms
16µs
512µs
0.5s
32Mb: 33s
64Mb: 66s
128Mb: 131s
256µs
23h
24h
25h
26h
46h
48h
4Ah
4Ch
Maximum timeout for byte/word program = 2n times typical
Maximum timeout for buffer program = 2n times typical
Maximum timeout per individual block erase = 2n times typical
Maximum timeout for chip erase = 2n times typical
2048µs
4s
32Mb: 131s
64Mb: 262s
128Mb: 524s
1. The values in this table are valid for all packages.
Note:
Table 26: Device Geometry Definition
Address
x16
x8
Data
0016h
0017h
0018h
Description
Device size = 2n in number of bytes
Value
4MB
27h
4Eh
8MB
16MB
28h
29h
50h
52h
0002h
0000h
Flash device interface code description
x8, x16 asynchro-
nous
2Ah
2Bh
54h
56h
0008h1 Maximum number of bytes in multi-byte program or page = 2n
0000h
256
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Common Flash Interface
Table 26: Device Geometry Definition (Continued)
Address
x16
x8
Data
Description
Value
2Ch
58h
(See table Number of erase block regions. It specifies the number of regions
–
below)
containing contiguous erase blocks of the same size.
01h = Uniform device
02h = Boot device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
(See table Erase block region 1 information
below) Bits[15:0] = y, y + 1 = Number of identical-size erase blocks
Bits[31:16] = z, block size in region 1 is z x 256 bytes
–
–
0
0
31h
32h
33h
34h
62h
64h
66h
68h
(See table Erase block region 2 information
below)
Bits[15:0] = y, y + 1 = Number of identical-size erase blocks
Bits[31:16] = z, block size in region 1 is z x 256 bytes
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase block region 3 information
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase block region 4 information
1. The value at 2Ah in the CFI region is set to 08h (256 bytes) due to compatibility issues.
The maximum 256-word program buffer can be used to optimize system program per-
formance.
Note:
Table 27: Erase Block Region Information
32Mb
64Mb
Bottom
02h
128Mb
Uniform
01h
Address
2Ch
Top
02h
07h
00h
20h
00h
3Eh
00h
00h
01h
Bottom
02h
Uniform
01h
Top
02h
07h
00h
20h
00h
7Eh
00h
00h
01h
Uniform
01h
2Dh
2Eh
07h
3Fh
07h
7Fh
7Fh
00h
00h
00h
00h
00h
2Fh
20h
00h
20h
00h
00h
30h
00h
01h
00h
01h
02h
31h
3Eh
00h
7Eh
00h
00h
32h
00h
00h
00h
00h
00h
33h
00h
00h
00h
00h
00h
34h
01h
00h
01h
00h
00h
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Common Flash Interface
Table 28: Primary Algorithm-Specific Extended Query Table
Note 1 applies to the entire table
Address
x16
40h
41h
42h
43h
44h
45h
x8
Data
0050h
0052h
0049h
0031h
0033h
0018h
Description
Value
"P"
80h
82h
84h
86h
88h
8Ah
Primary algorithm extended query table unique ASCII string “PRI”
"R"
"I"
Major version number, ASCII
Minor version number, ASCII
"1"
"3"
Address sensitive unlock (bits[1:0]):
00 = Required
Required
01 = Not required
Silicon revision number (bits[7:2])
46h
8Ch
0002h
Erase suspend:
2
00 = Not supported
01 = Read only
02 = Read and write
47h
48h
8Eh
90h
0001h
0000h
Block protection:
00 = Not supported
x = Number of blocks per group
1
Temporary block unprotect:
00 = Not supported
01 = Supported
Not supported
49h
4Ah
4Bh
92h
94h
96h
0008h
0000h
0000h
Block protect/unprotect:
08 = M29EWH/M29EWL
8
n/a
Simultaneous operations:
Not supported
Burst mode:
Not supported
00 = Not supported
01 = Supported
4Ch
98h
0002h
Page mode:
8-word page
00 = Not supported
01 = 8-word page
02 = 8-word page
03 = 16-word page
4Dh
4Eh
9Ah
9Ch
00B5h
00C5h
VPPH supply minimum program/erase voltage:
Bits[7:4] hex value in volts
Bits[3:0] BCD value in 100mV
11.5V
12.5V
VPPH supply maximum program/erase voltage:
Bits[7:4] hex value in volts
Bits[3:0] BCD value in 100mV
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Common Flash Interface
Table 28: Primary Algorithm-Specific Extended Query Table (Continued)
Note 1 applies to the entire table
Address
x16
x8
Data
Description
Value
4Fh
9Eh
00xxh
Top/bottom boot block flag:
xx = 02h: Bottom boot device, HW protection for bottom two
blocks
Device type (bot-
tom boot, top
boot, uniform)
xx = 03h: Top boot device, HW protection for top two blocks
xx = 04h: Uniform device, HW protection for lowest block
xx = 05h: Uniform device, HW protection for highest block
50h
A0h
0001h
Program suspend:
00 = Not supported
01 = supported
Supported
1. The values in this table are valid for both packages.
Note:
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Power-Up and Reset Characteristics
Power-Up and Reset Characteristics
Table 29: Power-Up Specifications
Symbol
Parameter
Legacy
JEDEC
Min
0
Unit
µs
Notes
VCC HIGH to VCCQ HIGH
–
tVCHVCQH
tVCHPH
tVCQHPH
tPHEL
1
2
2
VCC HIGH to rising edge of RST#
VCCQ HIGH to rising edge of RST#
RST# HIGH to chip enable LOW
RST# HIGH to write enable LOW
tVCS
tVIOS
tRH
60
0
µs
µs
50
150
ns
–
tPHWL
ns
1. VCC and VCCQ ramps must be synchronized during power-up.
Notes:
2. If RST# is not stable for tVCS or tVIOS, the device will not allow any READ or WRITE oper-
ations, and a hardware reset is required.
Figure 14: Power-Up Timing
tVCHVCQH
VCC
VCCQ
tRH
CE#
tVIOS
RST#
tVCS
WE#
tPHWL
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Power-Up and Reset Characteristics
Table 30: Reset AC Specifications
Condition/Parameter
Symbol
Legacy
JEDEC
Min
Max
Unit
Notes
RST# LOW to read mode during program or
erase
tREADY
tPLRH
–
25
µs
1
RST# pulse width
tRP
tRH
tRPD
tPLPH
tPHEL, tPHGL
–
100
50
–
–
–
–
ns
ns
µs
µs
RST# HIGH to CE# LOW, OE# LOW
RST# LOW to standby mode during read mode
1
1
10
RST# LOW to standby mode during program or
erase
50
RY/BY# HIGH to CE# LOW, OE# LOW
tRB
tRHEL, tRHGL
0
–
ns
1. Sampled only; not 100% tested.
Note:
Figure 15: Reset AC Timing – No PROGRAM/ERASE Operation in Progress
RY/BY#
CE#, OE#
t
RH
RST#
t
RP
Figure 16: Reset AC Timing During PROGRAM/ERASE Operation
t
READY
RY/BY#
t
RB
CE#, OE#
t
RH
RST#
t
RP
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32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Absolute Ratings and Operating Conditions
Absolute Ratings and Operating Conditions
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions outside those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may ad-
versely affect reliability.
Table 31: Absolute Maximum/Minimum Ratings
Parameter
Symbol
TBIAS
TSTG
Min
–40
–65
–0.6
–2
Max
85
Units
°C
°C
V
Notes
Temperature under bias
Storage temperature
Input/output voltage
Supply voltage
125
VIO
VCC + 0.6
5.6
1, 2
1, 2
VCC
V
Input/output supply voltage
Program voltage
VCCQ
VPPH
–2
5.6
V
1, 2
–2
14.5
V
1, 2, 3
1. During signal transitions, minimum voltage may undershoot to −2V during periods less
than 20ns.
Notes:
2. During signal transitions, maximum voltage may overshoot to VCC + 2V for periods less
than 20ns.
3. VPPH must not remain at 12V for more than 80 hours cumulative.
Table 32: Operating Conditions
Parameter
Symbol
Min
2.7
Max
3.6
Unit
V
Supply voltage
VCC
VCCQ
VPP
TA
CL
Input/output supply voltage (VCCQ ≤ VCC
Program voltage
)
1.65
–0.6
–40
3.6
V
12.5
85
V
Ambient operating temperature
Load capacitance
°C
pF
ns
V
30
Input rise and fall times
Input pulse voltages
–
–
2.5
–
0 to VCCQ
VCCQ/2
Input and output timing reference voltages
–
V
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Absolute Ratings and Operating Conditions
Figure 17: AC Measurement Load Circuit
VCCQ
VPP
VCC
25kΩ
25kΩ
Device
under
test
C
L
0.1µF
0.1µF
1. CL includes jig capacitance.
Note:
Figure 18: AC Measurement I/O Waveform
VCCQ
VCCQ/2
0V
Table 33: Input/Output Capacitance
Parameter
Input capacitance
Symbol
Test Condition
VIN = 0V
Min
Max
Unit
pF
CIN
2
2
7
5
Output capacitance
COUT
VOUT = 0V
pF
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DC Characteristics
DC Characteristics
Table 34: DC Current Characteristics
Parameter
Symbol
Conditions
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
Min
Typ
–
Max
±1
Unit Notes
Input leakage current
Output leakage current
ILI
–
–
–
µA
µA
1
ILO
–
±1
VCC read
current
Random read
ICC1
CE# = VIL, OE# = VIH,
20
25
mA
f = 5 MHz
Page read
CE# = VIL, OE# = VIH,
–
12
16
mA
f = 13 MHz
VCC standby
current
128Mb
64Mb
32Mb
ICC2
CE# = VCCQ ±0.2V,
RST# = VCCQ ±0.2V
–
–
–
–
50
35
35
35
120
120
120
50
µA
µA
µA
mA
VCC program/erase/blank
check current
ICC3
Program/
erase
VPP/WP# = VIL
or VIH
2
controller
active
VPP/WP# =
VPPH
–
26
33
mA
VPP current
Read
IPP1
VPP/WP# ≤ VCC
–
–
–
–
–
–
–
2
0.2
0.2
5
15
5
µA
µA
Standby
Reset
IPP2
IPP3
RST# = VSS ±0.2V
VPP/WP# = 12V ±5%
VPP/WP# = VCC
5
µA
PROGRAM operation
ongoing
10
mA
mA
mA
mA
0.05
5
0.10
10
ERASE operation
ongoing
IPP4
VPP/WP# = 12V ±5%
VPP/WP# = VCC
0.05
0.10
1. The maximum input leakage current is ±5µA on the VPP/WP# pin.
2. Sampled only; not 100% tested.
Notes:
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DC Characteristics
Table 35: DC Voltage Characteristics
Parameter
Input LOW voltage
Symbol
VIL
Conditions
VCC ≥ 2.7V
VCC ≥ 2.7V
IOL = 100µA,
Min
–0.5
Typ
Max
0.8
Unit
V
Notes
–
–
–
Input HIGH voltage
Output LOW voltage
VIH
VCCQ–0.4
–
VCCQ+0.5
0.2
V
1
VOL
V
VCC = VCC,min
,
VCCQ = VCCQ,min
Output HIGH voltage
VOH
IOH = 100µA,
VCCQ - 0.2
11.5
–
–
–
V
V
VCC = VCC,min
VCCQ = VCCQ,min
–
,
Voltage for VPP/WP# program
acceleration
VPPH
12.5
VPP logic level
VPPL
2.7
2.3
–
–
3.6
–
V
V
Program/erase lockout supply
voltage
VLKO
–
2
1. If VCCQ range is 2.7v~3.6v, VIH Min is 2v.
2. Sampled only; not 100% tested.
Notes:
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Read AC Characteristics
Read AC Characteristics
Table 36: Read AC Characteristics
Symbol
Parameter
Legacy
JEDEC
tAVAV
Condition
Package
BGA
Min Max Unit Notes
Address valid to next address valid
tRC
tACC
tPAGE
tLZ
CE# = VIL,
OE# = VIL
60
70
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSOP
BGA
Address valid to output valid
tAVQV
tAVQV1
tELQX
tELQV
tGLQX
tGLQV
tEHQZ
tGHQZ
CE# = VIL,
OE# = VIL
60
70
25
25
–
TSOP
BGA
–
Address valid to output valid
(page)
CE# = VIL,
OE# = VIL
–
TSOP
BGA
–
CE# LOW to output transition
OE# = VIL
OE# = VIL
CE# = VIL
CE# = VIL
OE# = VIL
CE# = VIL
–
0
0
–
1
1
TSOP
BGA
–
CE# LOW to output valid
tE
60
70
–
TSOP
BGA
–
OE# LOW to output transition
OE# LOW to output valid
CE# HIGH to output High-Z
OE# HIGH to output High-Z
tOLZ
tOE
0
0
–
1
1
TSOP
BGA
–
25
25
20
20
15
15
–
TSOP
BGA
–
tHZ
–
1
1
1
1
TSOP
BGA
–
tDF
–
TSOP
BGA
–
CE#, OE#, or address transition to
output transition
tOH
tEHQX,
tGHQX,
tAXQX
0
0
TSOP
–
CE# to BYTE# LOW
tELFL
tELFH
tFLQV
tFHQV
tFLQZ
tELBL
tELBH
tBLQV
tBHQV
tBLQZ
–
–
–
–
–
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
–
–
–
–
–
–
–
–
–
–
10
10
10
10
1
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
CE# to BYTE# HIGH
BYTE# LOW to output valid
BYTE# HIGH to output valid
BYTE# LOW to output in High-Z
1
1
1
1
1
1. Sampled only; not 100% tested.
Note:
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Read AC Characteristics
Figure 19: Random Read AC Timing (8-Bit Mode)
t
RC
Valid
A[MAX:0]/A-1
CE#
t
t
ACC
OH
t
t
E
OH
t
t
LZ
t
HZ
OE#
t
OLZ
t
OH
t
OE
DF
DQ[7:0]
BYTE#
Valid
t
t
ELFL
FLQZ
Figure 20: Random Read AC Timing (16-Bit Mode)
t
RC
Valid
A[MAX:0]
t
t
ACC
OH
CE#
t
t
E
OH
t
t
LZ
HZ
OE#
t
t
OLZ
OH
t
t
OE
DF
Valid
DQ[15:0]
BYTE#
t
ELFH
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Read AC Characteristics
Figure 21: BYTE# Transition Read AC Timing
Valid
A[MAX:0]
A–1
Valid
t
t
ACC
OH
BYTE#
t
FHQV
Data-out
Data-out
DQ[7:0]
DQ[15:8]
t
BLQX
High-Z
Figure 22: Page Read AC Timing (16-Bit Mode)
Valid
Valid
A[MAX:4]
Valid
tACC
Valid
Valid
Valid
Valid
Valid
A[3:0]
CE#
tE
tOH
tHZ
OE#
tOE
tPAGE
tOH
tDF
DQ[15:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
1. Page size is 8 words (16 bytes) and is addressed by address inputs A[2:0] in x16 bus mode
and A[2:0] plus DQ15/A−1 in x8 bus mode.
Note:
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Write AC Characteristics
Write AC Characteristics
Table 37: WE#-Controlled Write AC Characteristics
Parameter
Symbol
Package
Min
Typ
Max Unit
Notes
Legacy
JEDEC
Address valid to next address valid
CE# LOW to WE# LOW
tWC
tAVAV
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
60
70
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
tCS
tWP
tDS
tELWL
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWL
tWLAX
tGHWL
tWHGL
tWHRL
tVCHEL
–
0
–
WE# LOW to WE# HIGH
35
35
30
30
0
–
–
Input valid to WE# HIGH
WE# HIGH to input transition
WE# HIGH to CE# HIGH
–
–
tDH
tCH
–
0
–
0
–
0
–
WE# HIGH to WE# LOW
tWPH
tAS
20
20
0
–
–
Address valid to WE# LOW
WE# LOW to address transition
OE# HIGH to WE# LOW
–
0
–
tAH
–
45
45
0
–
–
–
0
–
WE# HIGH to OE# LOW
tOEH
tBUSY
tVCS
0
–
0
–
Program/erase valid to RY/BY# LOW
VCC HIGH to CE# LOW
–
90
90
–
1
1
–
60
60
–
1. Sampled only; not 100% tested.
Note:
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Write AC Characteristics
Figure 23: WE#-Controlled Program AC Timing (8-Bit Mode)
3rd Cycle 4th Cycle
Data Polling
READ Cycle
t
t
WC
WC
AAAh
t
PA
PA
A[MAX:0]/A-1
CE#
t
AS
AH
t
t
CH
t
E
CS
t
t
GHWL
OE
OE#
t
t
WP
WPH
WE#
t
t
DF
OH
t
WHWH1
t
DS
DQ[7:0]
AOh
DH
PD
DQ7#
D
D
OUT
OUT
t
1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-
GRAM command is followed by checking of the status register data polling bit and by a
READ operation that outputs the data (DOUT) programmed by the previous PROGRAM
command.
Notes:
2. PA is the address of the memory location to be programmed. PD is the data to be pro-
grammed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit
[DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
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Write AC Characteristics
Figure 24: WE#-Controlled Program AC Timing (16-Bit Mode)
3rd Cycle 4th Cycle
Data Polling
READ Cycle
t
t
WC
WC
555h
t
PA
PA
A[MAX:0]
CE#
t
AS
AH
t
t
CH
t
E
CS
t
t
GHWL
OE
OE#
t
t
WP
WPH
WE#
t
t
tWHWH1
DF
OH
t
DS
DQ[15:0]
Notes:
AOh
DH
PD
DQ7#
D
D
OUT
OUT
t
1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-
GRAM command is followed by checking of the status register data polling bit and by a
READ operation that outputs the data (DOUT) programmed by the previous PROGRAM
command.
2. PA is the address of the memory location to be programmed. PD is the data to be pro-
grammed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit
[DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
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Write AC Characteristics
Table 38: CE#-Controlled Write AC Characteristics
Parameter
Address valid to next address valid
WE# LOW to CE# LOW
Symbol
Package
Min
Typ
Max
Unit
Legacy
JEDEC
tWC
tWS
tCP
tAVAV
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
60
70
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEL
tELAX
tGHEL
0
CE# LOW to CE# HIGH
35
35
30
30
0
Input valid to CE# HIGH
CE# HIGH to input transition
CE# HIGH to WE# HIGH
CE# HIGH to CE# LOW
tDS
tDH
tWH
tCPH
tAS
tAH
–
0
0
0
20
20
0
Address valid to CE# LOW
CE# LOW to address transition
OE# HIGH to CE# LOW
0
45
45
0
0
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Write AC Characteristics
Figure 25: CE#-Controlled Program AC Timing (8-Bit Mode)
3rd Cycle 4th Cycle
Data Polling
PA
t
WC
WS
AAAh
t
PA
A[MAX:0]/A-1
WE#
t
AS
AH
t
WH
t
t
GHEL
OE#
CE#
t
t
t
CP
CPH
PD
t
WHWH1
DS
DQ[7:0]
AOh
DQ7#
D
OUT
t
DH
1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-
GRAM command is followed by checking of the status register data polling bit.
Notes:
2. PA is the address of the memory location to be programmed. PD is the data to be pro-
grammed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit
[DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
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Write AC Characteristics
Figure 26: CE#-Controlled Program AC Timing (16-Bit Mode)
3rd Cycle 4th Cycle
Data Polling
PA
t
WC
WS
A[MAX:0]
WE#
555h
t
PA
t
AS
AH
t
WH
t
t
GHEL
OE#
CE#
t
t
t
CP
CPH
PD
tWHWH1
DQ7#
DS
DQ[15:0]
AOh
D
OUT
t
DH
1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-
GRAM command is followed by checking of the status register data polling bit.
Notes:
2. PA is the address of the memory location to be programmed. PD is the data to be pro-
grammed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit
[DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
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Write AC Characteristics
Figure 27: Chip/Block Erase AC Timing (8-Bit Mode)
t
WC
A[MAX:0]/
A–1
AAAh
BAh1
AAAh
t
555h
AAAh
AAAh
555h
t
AS
AH
t
CH
t
CS
CE#
t
GHWL
OE#
t
t
WP
WPH
55h
WE#
t
DS
t
10h/
30h
DQ[7:0]
Notes:
AAh
80h
AAh
55h
DH
1. For a CHIP ERASE command, the address is 555h, and the data is 10h; for a BLOCK ERASE
command, the address is BAd, and the data is 30h.
2. BAd is the block address.
3. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
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Accelerated Program, Data Polling/Toggle AC Characteristics
Accelerated Program, Data Polling/Toggle AC Characteristics
Table 39: Accelerated Program and Data Polling/Data Toggle AC Characteristics
Symbol
Parameter
Legacy
–
JEDEC
tVHVPP
tVHHWH
tAXGL
Min
250
50
Max
Unit
ns
VPP/WP# rising or falling time
–
–
–
–
–
–
Valid VHH on VPP/WP# to WE# HIGH
–
ns
Address setup time to OE# LOW during toggle bit polling
Address hold time from OE# during toggle bit polling
CE# HIGH during toggle bit polling
tASO
tAHT
tEPH
tOEH
15
ns
tGHAX, tEHAX
tEHEL2
0
ns
20
ns
Output hold time during data and toggle bit polling
tWHGL2,
tGHGL2
20
ns
Program/erase valid to RY/BY# LOW
tBUSY
tWHRL
–
90
ns
1. Sampled only; not 100% tested.
Note:
Figure 28: Accelerated Program AC Timing
VPPH
VPP/WP#
VIL or VIH
tVHVPP
tVHVPP
Figure 29: Data Polling AC Timing
t
t
t
t
CH
E
HZ/ DF
CE#
t
OE
OE#
t
OEH
WE#
DQ7
Valid DQ7
Data
Data
DQ7#
DQ7#
Valid
DQ[6:0] Data
DQ[6:0] Data
RY/BY#
Output flag
Output flag
t
BUSY
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Accelerated Program, Data Polling/Toggle AC Characteristics
1. DQ7 returns a valid data bit when the PROGRAM or ERASE command has completed.
Notes:
2. See the following tables for timing details: Read AC Characteristics, Accelerated Pro-
gram and Data Polling/Data Toggle AC Characteristics.
Figure 30: Toggle/Alternative Toggle Bit Polling AC Timing (8-Bit Mode)
A[MAX:0]/
A–1
t
t
AHT
ASO
CE#
WE#
OE#
t
t
t
OEH
AHT
AS
t
t
t
OEH
EPH
OEH
t
t
t
DH
Data
OE
E
Stop
toggling
Output
Valid
DQ6/DQ2
RY/BY#
Toggle
Toggle
Toggle
t
BUSY
1. DQ6 stops toggling when the PROGRAM or ERASE command has completed. DQ2 stops
toggling when the CHIP ERASE or BLOCK ERASE command has completed.
Notes:
2. See the following tables for timing details: Read AC Characteristics, Accelerated Pro-
gram and Data Polling/Data Toggle AC Characteristics.
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Electrical Specifications – Program/Erase Characteristics
Electrical Specifications – Program/Erase Characteristics
Table 40: Program/Erase Characteristics
Buffer
Size
Parameter
Byte
Word
Min
Typ1, 2
0.5
20
Max2
4
Unit
s
Block erase
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Erase suspend latency
Block erase timeout
25
µs
µs
µs
µs
50
–
–
–
Byte program
Single-byte program
15
175
200
Double-/
–
10
quadruple-/
octuple-byte program
Byte write to buffer program
32
64
32
64
256
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
70
85
200
200
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
256
32
–
160
2.19
1.33
0.625
15
710
Effective write to buffer program
per byte
–
6.25
3.125
2.77
175
64
1
–
256
–
1
–
Word program
Single-word program
–
–
Word write to buffer program
16
–
16
32
128
256
256
1
70
200
32
–
85
200
128
256
256
16
–
160
284
160
4.375
2.66
1.25
1.11
0.625
710
–
1280
800
Full buffer program with VPPH
–
Effective write to buffer program
per word
–
12.5
6.25
5.55
5
32
–
1
128
256
256
–
1
–
1
Effective full buffer program per
word with VPPH
–
1
3.125
Program suspend latency
Blank check
–
–
–
–
–
–
–
–
–
–
–
20
3.2
–
25
–
µs
ms
PROGRAM/ERASE cycles (per block)
100,000
–
cycles
1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
Notes:
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Package Dimensions
Package Dimensions
Figure 31: 56-Pin TSOP – 14mm x 20mm
20.00 ±0.20
18.40 ±0.10
Pin #1
0.50 TYP
14.00 ±0.10
0.22 ± 0.05
0.10 MIN/
0.21 MAX
1.00 ±0.05
0.10
α
See Detail A
1.20 MAX
0.10 ±0.05
0.50 ±0.10
3 TYP/
5 MAX
Detail A
1. All dimensions are in millimeters.
2. For the lead width value of 0.22 ±0.05, there is also a legacy value of 0.15 ±0.05.
Notes:
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Package Dimensions
Figure 32: 48-Pin TSOP – 12mm x 20mm
1
48
0.50 TYP
+
12.00 0.10
+
0.22 0.05
0.80 TYP
24
25
+
1.00 0.05
1.20 MAX
+
18.40 0.10
+
20.00 0.20
o
o
o
+
2
3
0.10 0.05
+
3
Die
0.10 MIN/
0.21 MAX
+
0.60 0.10
0.10 MAX
1. All dimensions are in millimeters.
Note:
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Package Dimensions
Figure 33: 48-Ball BGA – 6mm x 8mm
+
6.00 0.10
4.00 TYP
0.40 TYP
1.00 TYP
1.20 TYP
0.40 TYP
+
8.00 0.10
Ball A1
5.60 TYP
0.10 MAX
0.80 TYP
+
0.80 TYP
0.35 0.5
0.64 TYP
1.00 MAX
0.20 MIN
1. All dimensions are in millimeters.
Note:
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Package Dimensions
Figure 34: 64-Ball Fortified BGA – 11mm x 13mm
0.80 TYP
Seating
plane
0.10
64X
Ball A1 ID
8
7
6
5
4
3
2 1
3.00
TYP
A
B
C
D
E
13.00 ±0.10
7.00 TYP
F
G
H
1.00
TYP
1.00
TYP
0.60 ±0.05
2.00 TYP
1.40 MAX
0.49 TYP/
0.40 MIN
7.00 TYP
11.00 ±0.10
1. All dimensions are in millimeters.
Note:
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Revision History
Revision History
Rev. B – 11/12
• Added text to Signal Descriptions to clarify VPP/WP# and VSS decoupling require-
ment.
• Added note to DC Voltage Characteristics table to clarify VIH spec.
Rev. A – 08/12
• Initial Micron rebrand release
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
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