MT9LD272AG-6X_技术文档

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

MT9LD272A(X), MT18LD472A(X)

DRAM

MODULE

For the latest data sheet revisions, please refer to the Micron

Web site: www.micron.com/mti/msp/html/datasheet.html

FEATURES

PIN ASSIGNMENT (Front View)

168-Pin DIMM

• JEDEC-standard, eight-CAS#, ECC pinout in a 168-pin,

dual in-line memory module (DIMM)

• 16MB (2 Meg x 72) and 32MB (4 Meg x 72)

• Nonbuffered

• High-performance CMOS silicon-gate process

• Single +3.3V ±0.3V power supply

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes:RAS#-ONLY, CAS#-BEFORE-RAS#

(CBR) and HIDDEN

• 2,048-cycle refresh distributed across 32ms

• FAST-PAGE-MODE (FPM) or Extended Data-Out

(EDO) PAGE MODE access cycles

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1

VSS

DQ0

DQ1

DQ2

DQ3

VDD

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

VSS

OE2#

RAS2#

CAS2#

CAS3#

WE2#

VDD

85

86

VSS

DQ32

DQ33

DQ34

DQ35

VDD

127

128

VSS

2

RFU

3

87

129 NC/RAS3#*

• Serial presence-detect (SPD)

4

5

6

7

8

9

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

CAS6#

CAS7#

RFU

VDD

NC

OPTIONS

• Package

MARKING

DQ4

DQ5

DQ6

DQ7

DQ8

VSS

DQ9

DQ10

DQ11

DQ12

DQ13

VDD

DQ36

DQ37

DQ38

DQ39

DQ40

VSS

DQ41

DQ42

DQ43

DQ44

DQ45

VDD

NC

CB2

CB3

168-pin DIMM (gold)

G

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

CB6

CB7

• Timing

50ns access

60ns access

-5*

-6

VSS

DQ16

DQ17

DQ18

DQ19

VDD

DQ20

NC

RFU

NC

DQ48

DQ49

DQ50

DQ51

VDD

DQ52

NC

RFU

NC

• Access Cycles

FAST PAGE MODE

EDO PAGE MODE

None

X

DQ14

DQ15

CB0

DQ46

DQ47

CB4

*EDO version only

KEY TIMING PARAMETERS

EDO Operating Mode

CB1

VSS

CB5

VSS

DQ21

DQ22

DQ23

VSS

DQ24

DQ25

DQ26

DQ27

VDD

DQ28

DQ29

DQ30

DQ31

VSS

NC

SDA

SCL

V^DD

VSS

DQ53

DQ54

DQ55

VSS

DQ56

DQ57

DQ58

DQ59

VDD

DQ60

DQ61

DQ62

DQ63

VSS

NC

t

SPEED

-5

RC

RAC

PC

AA

CAC

CAS

VDD

84ns

50ns

60ns

20ns

25ns

30ns

13ns

15ns

8ns

WE0#

CAS0#

CAS1#

RAS0#

OE0#

VSS

A0

A2

A4

A6

RFU

CAS4#

CAS5#

NC

RFU

VSS

A1

A3

A5

A7

-6

104ns

10ns

FPM Operating Mode

t

SPEED

RC

110ns

RAC

60ns

PC

AA

CAC

RP

-6

35ns

30ns

15ns

40ns

A8

A10

NC (A12)

VDD

A9

NC

SA0

SA1

122 NC (A11) 164

123 NC (A13) 165

124

125

126

VDD

RFU

166

167

168

VDD

SA2

RFU

VDD

NOTE: Pin symbols in parentheses are not used on these modules but may be used

for other modules in this product family. They are for reference only.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

1

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

PART NUMBERS

EDO PAGE MODE

EDO Operating Mode

EDO PAGE MODE, designated by the “X” version, is an

accelerated FAST-PAGE-MODEcycle. The primary advan-

tage of EDO is the availability of data-out even after CAS#

goes back HIGH. EDO provides for CAS# precharge time

(^tCP) to occur without the output data going invalid. This

elimination of CAS# output control provides for pipelined

READs.

PART NUMBER

CONFIGURATION

2 Meg x 72 ECC

4 Meg x 72 ECC

SPEED

50ns

60ns

50ns

60ns

MT9LD272AG-5 X

MT9LD272AG-6 X

MT18LD472AG-5 X

MT18LD472AG-6 X

FAST-PAGE-MODE modules have traditionally turned

the output buffers off (High-Z) with the rising edge of

CAS#. EDO-PAGE-MODE DRAMs operate like FAST-

PAGE-MODE DRAMs, except data will remain valid or

become valid after CAS# goes HIGH during READs, pro-

vided RAS# and OE# are held LOW. If OE# is pulsed while

RAS# and CAS# are LOW, data will toggle from valid data

to High-Z and back to the same valid data. If OE# is toggled

or pulsed after CAS# goes HIGH while RAS# remains

LOW, data will transition to and remain High-Z.

During an application, if the DQ outputs are wire OR’d,

OE#must be used to disable idle banks ofDRAMs. Alterna-

tively, pulsing WE# to the idle banks during CAS# HIGH

time will also High-Z the outputs. Independent of OE#

control, the outputs will disable after ^tOFF, which is refer-

enced from the rising edge of RAS# or CAS#, whichever

occurs last. (Refer to the 4 Meg x 4 [MT4LC4M4E8] DRAM

data sheet for additional information on EDO functional-

ity.)

FPM Operating Mode

PART NUMBER

CONFIGURATION

2 Meg x 72 ECC

4 Meg x 72 ECC

SPEED

60ns

MT9LD272AG-6

MT18LD472AG-6

60ns

GENERAL DESCRIPTION

The MT9LD272A(X) and MT18LD472A(X) are randomly

accessed 16MB and 32MB memories organized in a x72

configuration. They are specially processed to operate from

3V to 3.6V for low-voltage memory systems.

During READ or WRITE cycles, each bit is uniquely

addressed through the 21/ 22 address bits, which are en-

tered 11 bits (A0-A10) at RAS# time and 10/ 11 bits (A0-

A10) at CAS# time.

READ and WRITE cycles are selected with the WE#

input. A logic HIGH on WE# dictates read mode, while a

logic LOW on WE# dictates write mode. During a WRITE

cycle, data-in (D) is latched by the falling edge of WE# or

CAS#, whichever occurs last. An EARLY WRITE occurs

when WE# is taken LOW prior to CAS# falling. A LATE

WRITE or READ-MODIFY-WRITE occurs when WE# falls

after CAS# was taken LOW. During EARLY WRITE cycles,

the data-outputs (Q) will remain High-Z regardless of the

state of OE#. During LATE WRITE or READ-MODIFY-

WRITEcycles,OE#must be taken HIGH to disable the data-

outputs prior to applying input data. If a LATE WRITE or

READ-MODIFY-WRITE is attempted while keeping OE#

LOW, no WRITEwill occur, and the data-outputs will drive

read data from the accessed location.

REFRESH

Returning RAS# and CAS# HIGH terminates a memory

cycle and decreases chip current to a reduced standby level.

Also, the chip is preconditioned for the next cycle during

the RAS# HIGH time. Correct memory cell data is pre-

served by maintaining power and executing any RAS#

cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-

ONLY, CBR or HIDDEN) so that all combinations of RAS#

t

addresses (A0-A9/ A10) are executed at least every REF,

regardless of sequence. The CBR REFRESH cycle will in-

voke the internal refresh counter for automatic RAS# ad-

dressing.

SERIAL PRESENCE-DETECT OPERATION

This module family incorporates serial presence-detect

(SPD). The SPD function is implemented using a 2,048-bit

EEPROM. This nonvolatile storage device contains 256

bytes. The first 128 bytes can be programmed by Micron to

identify the module type and various DRAM organizations

and timing parameters. The remaining 128 bytes of storage

are available for use by the customer. System READ/

WRITE operations between the master (system logic) and

the slave EEPROM device (DIMM) occur via a standard IIC

bus using the DIMM’s SCL (clock) and SDA (data) signals,

FAST PAGE MODE

FAST-PAGE-MODE operations allow faster data opera-

tions (READ or WRITE) within a row-address-defined

page boundary. The FAST-PAGE-MODE cycle is always

initiated with a row address strobed in by RAS#, followed

by a column address strobed in by CAS#. Additional col-

umns may be accessed by providing valid column

addresses, strobing CAS# and holding RAS# LOW , thus

executing faster memory cycles. Returning RAS# HIGH

terminates the FAST-PAGE-MODE operation.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

2

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

together with SA(2:0), which provide eight unique DIMM/

EEPROM addresses.

SPD ACKNOWLEDGE

Acknowledge is a software convention used to indicate

successful data transfers. The transmitting device, either

master or slave, will release the bus after transmitting eight

bits. During the ninth clock cycle, the receiver will pull the

SDA line LOW to acknowledge that it received the eight bits

of data (Figure 3).

SPD CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are reserved

for indicating start and stop conditions (Figures 1 and 2).

The SPD device will always respond with an acknowl-

edge after recognition of a start condition and its slave

address. If both the device and a write operation have been

selected, the SPD device will respond with an acknowledge

after the receipt of each subsequent eight-bit word. In the

read mode the SPD device will transmit eight bits of data,

release the SDA line and monitor the line for an acknowl-

edge. If an acknowledge is detected and no stop condition

is generated by the master, the slave will continue to trans-

mit data. If an acknowledge is not detected, the slave will

terminate further data transmissions and await the stop

condition to return to standby power mode.

SPD START CONDITION

All commands are preceded by the start condition, which

is a HIGH-to-LOW transition of SDA when SCL is HIGH.

The SPD device continuously monitors the SDA and SCL

lines for the start condition and will not respond to any

command until this condition has been met.

SPD STOP CONDITION

All communications are terminated by a stop condition,

which is a LOW-to-HIGH transition of SDA when SCL is

HIGH. The stop condition is also used to place the SPD

device into standby power mode.

SCL

SDA

SCL

SDA

START

BIT

STOP

BIT

DATA STABLE

DATA

CHANGE

DATA STABLE

Figure 2

DEFINITION OF START AND STOP

Figure 1

DATA VALIDITY

SCL from Master

8

9

Data Output

from Transmitter

Data Output

from Receiver

Acknowledge

Figure 3

ACKNOWLEDGE RESPONSE FROM RECEIVER

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

3

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

FUNCTIONAL BLOCK DIAGRAM

MT9LD272A(X) (16MB)

DQ0-DQ7

DQ8-DQ15

CB0-CB7

DQ16-DQ23

DQ0-DQ7

DQ24-DQ31

DQ0-DQ7

U2

DQ0-DQ7

U3

WE#

OE#

WE#

OE#

WE#

OE#

WE#

WE0#

OE0#

U1

U4

U5

OE#

RAS0#

CAS0#

CAS1#

CAS2#

CAS3#

RAS#

CAS#

RAS#

CAS#

RAS#

CAS#

RAS#

CAS#

RAS#

CAS#

A0–A10

11

A0-A10

DQ32-DQ39

DQ0-DQ7

DQ40-DQ41

DQ0-DQ7

DQ48-DQ55

DQ0-DQ7

DQ56-DQ63

DQ0-DQ7

WE2#

OE2#

WE#

U6

U7

U8

U9

OE#

RAS2#

CAS4#

CAS5#

CAS6#

CAS7#

RAS#

CAS#

RAS#

CAS#

RAS#

CAS#

RAS#

CAS#

A0–A10

11

SPD

U1-U9 = MT4LC2M8B1 FAST PAGE MODE

U1-U9 = MT4LC2M8E7 EDO PAGE MODE

SCL

SDA

VDD

VSS

U1-U9

A0

A1

A2

SA0 SA1 SA2

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

4

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

FUNCTIONAL BLOCK DIAGRAM

MT18LD472A(X) (32MB)

DQ0-DQ3

DQ4-DQ7

DQ0-DQ3

DQ8-DQ11

DQ12-DQ15

CB4-CB7

DQ16-DQ19

DQ20-DQ23

DQ24-DQ27

DQ28-DQ31

DQ0-DQ3

WE#

DQ0-DQ3

WE#

DQ0-DQ3

WE#

DQ0-DQ3

WE#

DQ0-DQ3

WE#

DQ0-DQ3

WE#

DQ0-DQ3

WE#

WE0#

OE0#

WE#

U1

U2

U3

U4

U5

U6

U7

U8

U9

OE#

RAS0#

CAS0#

CAS1#

CAS2#

CAS3#

RAS#

CAS# A0–A10

11

A0-A10

DQ32-DQ35

DQ36-DQ39

DQ40-DQ43

DQ44-DQ47

CB4-CB7

DQ48-DQ51

DQ52-DQ55

DQ56-DQ59

DQ06-DQ63

DQ0-DQ3

WE#

DQ0-DQ3

WE#

DQ0-DQ3

WE#

DQ0-DQ3

WE#

DQ0-DQ3

WE#

DQ0-DQ3

WE#

DQ0-DQ3

WE#

DQ0-DQ3

WE#

DQ0-DQ3

WE#

WE2#

OE2#

U10

OE#

U11

OE#

U12

OE#

U13

OE#

U14

OE#

U15

OE#

U16

OE#

U17

OE#

U18

OE#

RAS2#

RAS#

CAS4#

CAS5#

CAS6#

CAS7#

CAS# A0–A10

11

SPD

U1-U18 = MT4LC4M4B1 FAST PAGE MODE

U1-U18 = MT4LC4M4E8 EDO PAGE MODE

SCL

SDA

V

DD

SS

U1-U18

A0

A1

A2

V

SA0 SA1 SA2

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

5

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

PIN DESCRIPTIONS

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

30, 45

RAS0#, RAS2#

Input

Row-Address Strobe: RAS# is used to clock-in the row-

address bits. Two RAS# inputs allow for one x72 bank or

two x36 banks.

28, 29, 46, 47, 112,

113, 130, 131

CAS0#-CAS7#

WE0#, WE2#

Input

Column-Address Strobe: CAS# is used to clock-in the

column-address bits, enable the DRAM output buffers

and strobe the data inputs on WRITE cycles. Eight CAS#

inputs allow byte access control for any memory bank

configuration.

27, 48

Write Enable: WE# is the READ/WRITE control for the

DQ pins. If WE# is LOW prior to CAS# going LOW, the

access is an EARLY WRITE cycle. If WE# is HIGH while

CAS# is LOW, the access is a READ cycle, provided OE#

is also LOW. If WE# goes LOW after CAS# goes LOW,

then the cycle is a LATE WRITE cycle. A LATE WRITE

cycle is generally used in conjunction with a READ cycle

to form a READ-MODIFY-WRITE cycle.

31, 44

OE0#, OE2#

Input

Output Enable: OE# is the input/output control for the DQ

pins. These signals may be driven, allowing LATE WRITE

cycles.

33-38, 117-121

A0-A10

Address Inputs: These inputs are multiplexed and clocked

by RAS# and CAS#.

2-5, 7-11, 13-17, 19-20,

55-58, 60, 65-67, 69-72,

74-77, 86-89,91-95,

97-101, 103-104,

DQ0-DQ63

Input/

Output

Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs to

the addressed DRAM location. For READ access cycles,

DQ0-DQ63 act as outputs for the addressed DRAM

location.

139-142, 144, 149-151,

153-156, 158-161

21-22, 52-53, 105-106,

136-137

CB0-CB7

RFU

Input/Output

Check Bits.

42, 62, 111, 115,

125-126, 128, 132, 146

–

Reserved for Future Use: These pins should be left

unconnected.

6, 18, 26, 40, 41, 49, 59,

73, 84, 90, 102, 110,

VDD

Supply

Power Supply: +3.3V ±0.3V.

124, 133, 143, 157, 168

1, 12, 23, 32, 43, 54, 64,

68, 78, 85, 96, 107, 116,

127, 138, 148, 152, 162

VSS

SDA

Supply

Input/Output

Input

Ground.

82

Serial Presence-Detect Data. SDA is a bidirectional pin

used to transfer addresses and data into and data out of

the presence-detect portion of the module.

83

SCL

Serial Clock for Presence-Detect. SCL is used to

synchronize the presence-detect data transfer to and

from the module.

165-167

SA0-SA2

Input

Presence-Detect Address Inputs. These pins are used to

configure the presence-detect device.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

6

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

SERIAL PRESENCE-DETECT MATRIX

BYTE

DESCRIPTION

NUMBER OF BYTES USED BY MICRON

TOTAL NUMBER OF SPD MEMORY BYTES

MEMORY TYPE

ENTRY (VERSION) BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

HEX

80

0

1

2

128

256

1

0

1

0

08

FAST PAGE MODE

EDO PAGE MODE

0

1

0

01

02

3

4

NUMBER OF ROW ADDRESSES

11

0

1

0

1

0B

NUMBER OF COLUMN ADDRESSES

10 (16MB)

11 (32MB)

0

1

0

1

0

1

0A

0B

5

6

7

8

9

NUMBER OF BANKS

DATA WIDTH

1

0

1

0

1

0

1

0

1

01

48

00

01

x72

DATA WIDTH (continued)

VOLTAGE INTERFACE

NONE

LVTTL

t

RAS# ACCESS TIME ( RAC)

50ns (-5)

60ns (-6)

0

1

0

1

0

1

0

32

3C

t

10

CAS# ACCESS TIME ( CAC)

13ns (-5)

15ns (-6)

0

1

0

1

0D

0F

11

12

13

MODULE CONFIGURATION TYPE

REFRESH RATES

ECC

0

1

0

02

00

15.625µs/NORMAL

DRAM WIDTH (PRIMARY DRAM)

x8 (16MB)

x4 (32MB)

0

1

0

1

0

08

04

14

ERROR CHECKING DRAM DATA WIDTH

x8 (16MB)

x4 (32MB)

0

1

0

1

0

08

04

00

15-61 RESERVED

62

63

SPD REVISION

REV. 0

0

1

0

x

0

x

–

0

1

0

1

0

x

0

x

–

0

1

0

1

0

x

0

x

–

0

1

0

1

0

1

0

x

0

x

–

0

1

0

1

0

x

0

x

–

0

1

0

1

0

1

x

0

1

0

x

–

0

1

0

1

0

1

0

1

0

x

0

1

0

x

–

0

1

0

1

0

1

0

x

1

0

1

0

x

–

00

3A

46

45

33

3F

3E

2C

FF

01

02

03

04

xx

01

02

03

04

00

xx

–

CHECKSUM FOR BYTES 0-62

16MB -5 (EDO)

16MB -6 (EDO)

16MB -6 (FPM)

32MB -5 (EDO)

32MB -6 (EDO)

32MB -6 (FPM)

MICRON

64

MANUFACTURER’S JEDEC ID CODE

65-71 MANUFACTURER’S JEDEC CODE (CONT.)

72 MANUFACTURING LOCATION

73-90 MODULE PART NUMBER (ASCII)

91

PCB IDENTIFICATION CODE

1

2

3

4

0

92

93

94

IDENTIFICATION CODE (CONT.)

YEAR OF MANUFACTURE IN BCD

WEEK OF MANUFACTURE IN BCD

95-98 MODULE SERIAL NUMBER

99-125 MANUFACTURE SPECIFIC DATA (RSVD)

NOTE:

1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”

2. x = Variable Data.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

7

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

*Stresses greater than those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the device.

This is a stress rating only, and functional operation of the

device at these or any other conditions above those indi-

cated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability.

ABSOLUTE MAXIMUM RATINGS*

Voltage on VDD Pin Relative to VSS ................. -1V to +4.6V

Voltage on Inputs or I/ O Pins

Relative to V^SS................................................ -1V to +4.6V

Operating Temperature, T_A(ambient) .......... 0°C to +70°C

Storage Temperature (plastic).................... -55°C to +125°C

Power Dissipation ............................................................. 9W

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1) (VDD = +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL

VDD

VIH

SIZE

ALL

MIN

3

MAX

3.6

UNITS NOTES

SUPPLY VOLTAGE

V

INPUT HIGH VOLTAGE: Logic 1; All inputs

INPUT LOW VOLTAGE: Logic 0; All inputs

2

VDD + 0.3

0.8

V

30

VIL

-0.5

INPUT LEAKAGE CURRENT:

Any input 0V ≤ VIN ≤ VDD + 0.3V

(All other pins not under test = 0V)

CAS0#-CAS7#

A0-A10

II1

16MB

32MB

16MB

32MB

16MB

32MB

16MB

32MB

-4

-6

4

6

µA

II2

I^I3

I^I4

-18

-36

-10

-18

-10

-18

18

36

10

18

10

18

µA

WE0#, WE2#,

OE0#, OE2#

RAS0#-RAS3#

µA

OUTPUT LEAKAGE CURRENT:

DQ is disabled; 0V ≤ VOUT ≤ VDD + 0.3V

DQ0-DQ63,

CB0-CB7

I^OZ

16MB

32MB

-5

5

OUTPUT LEVELS:

Output High Voltage (IOUT = -2mA)

Output Low Voltage (IOUT = 2mA)

V^OH

ALL

2.4

–

V

VOL

ALL

–

0.4

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

8

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

ICC OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 5, 6) (VDD = +3.3V ±0.3V)

MAX

PARAMETER/CONDITION

SYMBOL SIZE

-5*

-6

UNITS NOTES

STANDBY CURRENT: TTL

(RAS# = CAS# = VIH)

ICC1

ICC2

ICC3

16MB

32MB

9

18

9

18

mA

STANDBY CURRENT: CMOS

(RAS# = CAS# = VDD - 0.2V)

16MB

32MB

9

mA

OPERATING CURRENT: Random READ/WRITE

Average power supply current

16MB

32MB 1,980 1,800

990

900

mA

3, 24

3, 4

(RAS#, CAS#, address cycling: ^tRC = ^tRC [MIN])

OPERATING CURRENT: FAST PAGE MODE

Average power supply current

ICC4

I^CC5

16MB

32MB

–

720

1,440

(RAS# = VIL, CAS#, address cycling: ^tPC = ^tPC [MIN])

OPERATING CURRENT: EDO PAGE MODE (“X” version only)

Average power supply current

16MB

990

900

(X only) 32MB 1,980 1,800

(RAS# = VIL, CAS#, address cycling: ^tPC = ^tPC [MIN])

REFRESH CURRENT: RAS#-ONLY

Average power supply current

ICC6

ICC7

16MB

32MB 1,980 1,800

990

900

(RAS# cycling, CAS# = VIH: ^tRC = ^tRC [MIN])

REFRESH CURRENT: CBR

16MB

990

900

Average power supply current

(RAS#, CAS#, address cycling: ^tRC = ^tRC [MIN])

32MB 1,980 1,800

* EDO version only

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

9

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

CAPACITANCE

MAX

PARAMETER

SYMBOL 16MB 32MB UNITS NOTES

Input Capacitance: A0-A10

CI1

CI2

CI3

CI4

CI5

CIO

51

39

17

6

96

67

24

6

pF

2

Input Capacitance: WE0#, WE2#, OE0#, OE2#

Input Capacitance: RAS0#, RAS2#

Input Capacitance: CAS0#-CAS7#

Input Capacitance: SCL, SA0-SA2

Input/Output Capacitance: DQ0-DQ63, CB0-CB7, SDA

10

FAST PAGE MODE

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V)

AC CHARACTERISTICS - FAST PAGE MODE OPTION

PARAMETER

-6

SYMBOL

MIN

MAX

UNITS

NOTES

t

Access time from column address

Column-address hold time (referenced to RAS#)

Column-address setup time

Row-address setup time

AA

30

ns

t

AR

45

0

t

ASC

t

ASR

0

t

Column address to WE# delay time

Access time from CAS#

AWD

55

23

14

t

CAC

15

t

Column-address hold time

CAH

10

15

10

3

t

CAS# pulse width

CAS

10,000

t

CAS# hold time (CBR Refresh)

CAS# to output in Low-Z

CHR

4

t

CLZ

25

15

t

CAS# precharge time

CP

10

t

Access time from CAS# precharge

CAS# to RAS# precharge time

CAS# hold time

CPA

35

t

CRP

5

60

5

t

CSH

t

CAS# setup time (CBR Refresh)

CAS# to WE# delay time

CSR

4

t

CWD

40

15

10

0

23

t

WRITE command to CAS# lead time

Data-in hold time

CWL

t

DH

22

t

Data-in setup time

DS

t

Output disable

OD

3

15

t

Output enable

OE

t

OE# hold time from WE# during READ-MODIFY-WRITE cycle

Output buffer turn-off delay

OEH

15

3

21

t

OFF

15

19, 25, 26

t

OE# setup prior to RAS# during HIDDEN REFRESH cycle

FAST-PAGE-MODE READ or WRITE cycle time

ORD

0

t

PC

35

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

10

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

FAST PAGE MODE

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V)

AC CHARACTERISTICS - FAST PAGE MODE OPTION

PARAMETER

-6

SYMBOL

MIN

MAX

UNITS

ns

ms

ns

NOTES

t

FAST-PAGE-MODE READ-WRITE cycle time

Access time from RAS#

PRWC

85

t

RAC

60

13

17

t

RAS# to column-address delay time

Row-address hold time

RAD

15

10

60

110

20

0

t

RAH

t

RAS# pulse width

RAS

10,000

t

RAS# pulse width (FAST PAGE MODE)

Random READ or WRITE cycle time

RAS# to CAS# delay time

RASP

125,000

t

RC

t

RCD

16

18

t

READ command hold time (referenced to CAS#)

READ command setup time

RCH

t

RCS

0

t

Refresh period (2,048 cycles)

RAS# precharge time

REF

32

t

RP

40

0

t

RAS# to CAS# precharge time

READ command hold time (referenced to RAS#)

RAS# hold time

RPC

t

RRH

0

18

23

t

RSH

15

155

85

15

2

t

READ-WRITE cycle time

RWC

t

RAS# to WE# delay time

RWD

t

WRITE command to RAS# lead time

Transition time (rise or fall)

RWL

t

T

50

t

WRITE command hold time

WCH

10

45

0

t

WRITE command hold time (referenced to RAS#)

WE# command setup time

WCR

t

WCS

23

t

WRITE command pulse width

WE# hold time (CBR Refresh)

WE# setup time (CBR Refresh)

WP

10

t

WRH

t

WRP

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

11

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

EDO PAGE MODE

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V)

AC CHARACTERISTICS - EDO PAGE MODE OPTION

PARAMETER

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

NOTES

t

Access time from column address

Column-address setup to CAS# precharge

Column-address hold time (referenced to RAS#)

Column-address setup time

Row-address setup time

AA

25

30

t

ACH

12

38

0

15

45

0

t

AR

t

ASC

t

ASR

0

t

Column-address to WE# delay time

Access time from CAS#

AWD

42

49

23

14

t

CAC

13

15

t

Column-address hold time

CAS# pulse width

CAH

8

0

3

8

10

0

t

CAS

10,000

t

CAS# hold time (CBR Refresh)

CAS# to output in Low-Z

CHR

4

t

CLZ

t

Data output hold after CAS# LOW

CAS# precharge time

COH

3

t

CP

10

15

t

Access time from CAS# precharge

CAS# to RAS# precharge time

CAS# hold time

CPA

28

35

t

CRP

5

38

5

45

5

t

CSH

t

CAS# setup time (CBR Refresh)

CAS# to WE# delay time

CSR

4

t

CWD

28

8

35

10

0

23

t

WRITE command to CAS# lead time

Data-in hold time

CWL

t

DH

8

22

t

Data-in setup time

DS

0

t

Output disable

OD

0

12

0

15

t

Output enable

OE

t

OE# hold time from WE# during

READ-MODIFY-WRITE cycle

OEH

8

10/12*

21

t

OE# HIGH hold time from CAS# HIGH

OE# HIGH pulse width

OEHC

5

4

0

10

5

ns

t

OEP

t

OE# LOW to CAS# HIGH setup time

Output buffer turn-off delay

OES

5

t

OFF

12

50

0

15

60

19, 26

t

OE# setup prior to RAS#

during HIDDEN REFRESH cycle

ORD

0

t

EDO-PAGE-MODE READ or WRITE cycle time

EDO-PAGE-MODE READ-WRITE cycle time

Access time from RAS#

PC

20

47

25

56

ns

ms

ns

t

PRWC

t

RAC

13

17

t

RAS# to column-address delay time

Row-address hold time

RAD

9

12

10

60

104

14

0

t

RAH

t

RAS# pulse width

RAS

50

84

11

0

10,000

t

RAS# pulse width (EDO PAGE MODE)

Random READ or WRITE cycle time

RAS# to CAS# delay time

RASP

125,000

t

RC

t

RCD

16

18

t

READ command hold time (referenced to CAS#)

READ command setup time

RCH

t

RCS

0

t

Refresh period (2,048 cycles)

REF

32

t

RAS# precharge time

RP

30

40

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

12

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

EDO PAGE MODE

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V)

AC CHARACTERISTICS - EDO PAGE MODE OPTION

PARAMETER

-5

-6

SYMBOL

MIN

5

MAX

MIN

5

MAX

UNITS

ns

NOTES

t

RAS# to CAS# precharge time

READ command hold time (referenced to RAS#)

RAS# hold time

RPC

t

RRH

0

18

t

RSH

13

116

67

13

2

15

140

79

15

2

t

READ WRITE cycle time

RWC

t

RAS# to WE# delay time

RWD

23

t

WRITE command to RAS# lead time

Transition time (rise or fall)

RWL

t

T

50

12

50

15

t

WRITE command hold time

WCH

8

10

45

0

t

WRITE command hold time (referenced to RAS#)

WE# command setup time

WCR

38

0

t

WCS

t

Output disable delay from WE# (CAS# HIGH)

WRITE command pulse width

WE# pulse to disable at CAS# HIGH

WE# hold time (CBR Refresh)

WE# setup time (CBR Refresh)

WHZ

0

t

WP

5

t

WPZ

10

8

10

t

WRH

t

WRP

8

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

13

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS

(Notes: 1) (VDD = +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL

VDD

VIH

MIN

MAX

UNITS NOTES

SUPPLY VOLTAGE

3

3.6

V

INPUT HIGH VOLTAGE: Logic 1; All inputs

INPUT LOW VOLTAGE: Logic 0; All inputs

OUTPUT LOW VOLTAGE: IOUT = 3mA

INPUT LEAKAGE CURRENT: VIN = GND to VDD

OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD

VDD × 0.7 VDD + 0.5

VIL

-1

–

VDD × 0.3

V

VOL

ILI

0.4

10

30

V

–

µA

ILO

–

STANDBY CURRENT:

ISB

–

SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10%

POWER SUPPLY CURRENT:

SCL clock frequency = 100 KHz

ICC

–

2

mA

SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS

(Notes: 1) (VDD = +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL

MIN

0.3

MAX

UNITS

µs

NOTES

t

SCL LOW to SDA data-out valid

Time the bus must be free before a new transition can start

Data-out hold time

AA

3.5

t

BUF

4.7

µs

t

DH

300

ns

t

SDA and SCL fall time

F

300

100

ns

t

Data-in hold time

HD:DAT

0

4

µs

t

Start condition hold time

Clock HIGH period

HD:STA

µs

t

HIGH

t

µs

Noise suppression time constant at SCL, SDA inputs

Clock LOW period

I

ns

t

LOW

4.7

µs

t

SDA and SCL rise time

R

1

µs

t

SCL clock frequency

SCL

100

KHz

ns

t

Data-in setup time

SU:DAT

250

4.7

t

Start condition setup time

Stop condition setup time

WRITE cycle time

SU:STA

µs

t

SU:STO

t

µs

WR

10

ms

28

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

14

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

NOTES

t

1. All voltages referenced to VSS.

^tAA (^tRAC and CAC no longer applied). With or

t

2. This parameter is sampled. V^DD= +3.3V; f = 1 MHz.

3. ICC is dependent on output loading. Specified values

are obtained with minimum cycle time and the

outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indicate

cycle time at which proper operation over the full

temperature range is ensured.

6. An initial pause of 100µs is required after power-up,

followed by eight RAS# REFRESH cycles (RAS#-

ONLY or CBR with WE# HIGH), before proper device

operation is ensured. The eight RAS# cycle wake-ups

should be repeated any time the ^tREF refresh

requirement is exceeded.

7. AC characteristics assume ^tT = 5ns for FPM and 2.5ns

for EDO.

8. V^IH(MIN) and VIL (MAX) are reference levels for

measuring timing of input signals. Transition times

are measured between V^IHand VIL (or between VIL

and VIH).

9. In addition to meeting the transition rate specifica-

tion, all input signals must transit between V^IHand

VIL (or between VIL and VIH) in a monotonic manner.

10. If CAS# = V^IH, data output is High-Z.

11. If CAS# = VIL, data output may contain data from the

last valid READ cycle.

without the ^tRAD (MAX) limit, ^tAA, ^tRAC and CAC

must always be met.

t

18. Either RCH or RRH must be satisfied for a READ

cycle.

19. ^tOFF (MAX) defines the time at which the output

achieves the open circuit condition and is not

referenced to V^OHor VOL.

20. A HIDDEN REFRESH may also be performed after

a WRITE cycle. In this case, WE# = LOW and

OE# = HIGH.

21. LATE WRITE and READ-MODIFY-WRITE cycles

t

must have both OD and OEH met (OE# HIGH

during WRITE cycle) in order to ensure that the

output buffers will be open during the WRITE cycle.

The DQs will provide the previously read data if

CAS# remains LOW and OE# is taken back LOW after

^tOEH is met. If CAS# goes HIGH prior to OE# going

back LOW, the DQs will remain open.

22. These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles and WE# leading edge

in LATE WRITE or READ-MODIFY-WRITE cycles.

23. ^tWCS, ^tRWD, ^tAWD and CWD are not restrictive

t

operating parameters. ^tWCS applies to EARLY

WRITE cycles. ^tRWD, ^tAWD and CWD apply to

t

READ-MODIFY-WRITE cycles. If ^tWCS ≥ ^tWCS

(MIN), the cycle is an EARLY WRITE cycle and the

data output will remain an open circuit throughout

12. Measured with a load equivalent to two TTL gates

and 100pF and V^OL= 0.8V and VOH = 2V.

the entire cycle. If ^tWCS < ^tWSC (MIN) and RWD ≥

t

13. Requires that ^tAA and RAC are not violated.

^tRWD (MIN), ^tAWD ≥ ^tAWD (MIN) and CWD ≥

t

14. Requires that ^tAA and CAC are not violated.

^tCWD (MIN), the cycle is a READ-MODIFY-WRITE

and the data output will contain data read from the

selected cell. If neither of the above conditions is met,

the state of data-out is indeterminate. OE# held HIGH

and WE# taken LOW after CAS# goes LOW result in a

t

15. If CAS# is LOW at the falling edge of RAS#, Q will be

maintained from the previous cycle. To initiate a new

cycle and clear the data-out buffer, CAS# must be

t

pulsed HIGH for CP.

16. The ^tRCD (MAX) limit is no longer specified. ^tRCD

(MAX) was specified as a reference point only. If

LATE WRITE (OE#-controlled) cycle. WCS, ^tRWD,

^tCWD and AWD are not applicable in a LATE

t

^tRCD was greater than the specified RCD (MAX)

WRITE cycle.

t

limit, then access time was controlled exclusively by

24. Column address changed once each cycle.

25. The 3ns minimum parameter guaranteed by design.

26. With the FPM option, ^tOFF is determined by the first

RAS# or CAS# signal to transition HIGH. In compari-

son, ^tOFF on an EDO option is determined by the

latter of the RAS# and CAS# signals to transition

HIGH.

^tCAC (^tRAC [MIN] no longer applied). With or

t

without the ^tRCD (MAX) limit, ^tAA and CAC must

always be met.

17. The ^tRAD (MAX) limit is no longer specified. ^tRAD

(MAX) was specified as a reference point only. If

t

^tRAD was greater than the specified RAD (MAX)

limit, then access time was controlled exclusively by

27. Applies to both FPM and EDO modules.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

15

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

NOTES (continued)

28. The SPD EEPROM WRITE cycle time (^tWR) is the

time from a valid stop condition of a write sequence

to the end of the EEPROM internal erase/ program

cycle. During the WRITE cycle, the EEPROM bus

interface circuit are disabled, SDA remains HIGH due

to pull-up resistor, and the EEPROM does not

respond to its slave address.

29. If OE# is tied permanently LOW, LATE WRITE or

READ-MODIFY-WRITE operations are not possible.

30. V^IHovershoot: VIH (MAX) = VDD + 2V for a pulse

width ≤ 10ns, and the pulse width cannot be greater

than one third of the cycle rate. V^ILundershoot: VIL

(MIN) = -2V for a pulse width ≤ 10ns, and the pulse

width cannot be greater than one third of the cycle

rate.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

16

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

READ CYCLE ²⁷

t

RC

t

RAS

RP

V

IH

IL

RAS#

CAS#

t

CSH

t

RSH

RRH

t

RCD

CAS

CRP

V

IH

IL

t

AR

t

RAD

RAH

t

ASR

ASC

CAH

t

ACH

V

IH

IL

ROW

COLUMN

ADDR

WE#

t

RCS

RCH

V

IH

IL

t

AA

RAC

CAC

CLZ

NOTE 1

t

OFF

V

OH

OL

DQ

OPEN

VALID DATA

t

OD

OE

V

IH

IL

OE#

DON’T CARE

UNDEFINED

FAST PAGE MODE AND EDO PAGE MODE

TIMING PARAMETERS

-5*

-6

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

0

MAX

12

–

MIN

MAX

15

UNITS

ns

t

AA

25

30

OFF (EDO)

0

3

t

ACH (EDO)

12

38

0

15

45

0

OFF (FPM)

–

15

t

AR

RAC

50

60

t

ASC

RAD (EDO)

9

–

12

15

10

60

104

110

14

20

0

t

ASR

0

RAD (FPM)

t

CAC

13

15

RAH

9

t

CAH

8

10

15

0

RAS

50

84

–

10,000

t

CAS (EDO)

10,000

–

10,000

RC (EDO)

t

CAS (FPM)

–

RC (FPM)

t

CLZ (EDO)

0

RCD (EDO)

11

–

t

CLZ (FPM)

–

3

RCD (FPM)

t

CRP

5

RCH

0

t

CSH (EDO)

38

–

45

60

0

RCS

0

t

CSH (FPM)

RP

30

0

40

0

t

OD (EDO)

0

12

–

15

RRH

t

OD (FPM)

–

3

RSH

13

15

t

OE

12

*EDO version only

t

NOTE: 1. For EDO, OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. For FPM, OFF is referenced from rising edge of RAS# or

CAS#, whichever occurs first.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

17

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

EARLY WRITE CYCLE ²⁷

t

RC

t

RAS

RP

V

IH

RAS#

CAS#

V

IL

t

CSH

RSH

CAS

t

CRP

RCD

V

IH

IL

t

AR

t

RAD

RAH

ASC

CAH

t

ACH

ASR

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

CWL

t

RWL

WCR

WCH

WP

t

WCS

WE#

V

IH

IL

t

DS

DH

V

IOH

IOL

DQ

VALID DATA

V

IH

IL

OE#

DON’T CARE

UNDEFINED

FAST PAGE MODE AND EDO PAGE MODE

TIMING PARAMETERS

-5*

-6

-5*

-6

SYMBOL

MIN

12

38

0

MAX

MIN

15

45

0

MAX

UNITS

ns

SYMBOL

MIN

9

MAX

MIN

MAX

UNITS

ns

t

ACH (EDO)

RAD (EDO)

RAH

12

10

60

110

104

20

14

40

15

10

45

0

t

AR

9

t

ASC

RAS

50

–

10,000

t

ASR

0

RC (FPM)

RC (EDO)

RCD (FPM)

RCD (EDO)

RP

t

CAH

8

10

15

10

5

84

–

t

CAS (FPM)

–

10,000

t

CAS (EDO)

8

10,000

11

30

13

8

t

CRP

5

t

CSH (FPM)

–

60

45

15

10

0

RSH

t

CSH (EDO)

38

–

RWL

t

CWL (FPM)

WCH

t

CWL (EDO)

8

WCR

38

0

t

DH

8

WCS

t

DS

0

WP (FPM)

WP (EDO)

–

10

5

t

RAD (FPM)

–

15

5

*EDO version only

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

18

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

FAST-PAGE-MODE READ CYCLE

t

RP

RASP

V

IH

RAS#

CAS#

V

IL

t

RSH

CAS

CSH

PC

CP

t

CP

CRP

RCD

CAS

CP

V

IH

IL

t

AR

t

RAD

RAH

t

CAH

ASR

ASC

CAH

ASC

CAH

ASC

V

IH

IL

ADDR

WE#

ROW

COLUMN

t

COLUMN

t

ROW

t

RRH

RCS

t

RCS

t

RCH

RCS

t

RCH

V

IH

IL

t

AA

RAC

CAC

CPA

CAC

CPA

CAC

t

OFF

t

OFF

t

CLZ

V

IOH

IOL

VALID

DATA

VALID

DATA

VALID

DATA

DQ

OPEN

t

OE

OD

OE

OD

OE

OD

V

IH

IL

OE#

DON’T CARE

UNDEFINED

FAST PAGE MODE

TIMING PARAMETERS

-6

SYMBOL

MIN

MAX

UNITS

SYMBOL

MIN

MAX

15

UNITS

t

AA

30

ns

OE

ns

t

AR

45

0

OFF

3

15

t

ASC

PC

35

t

ASR

0

RAC

60

t

CAC

15

RAD

15

10

60

20

0

t

CAH

10

15

3

RAH

t

CAS

10,000

35

RASP

125,000

t

CLZ

RCD

t

CP

10

RCH

t

CPA

RCS

0

t

CRP

5

60

3

RP

40

0

t

CSH

RRH

t

OD

15

RSH

15

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

19

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

EDO-PAGE-MODE READ CYCLE

t

RP

RASP

V

IH

RAS#

CAS#

V

IL

t

RSH

CSH

PC

CP

t

CP

CRP

RCD

CAS

CP

CAS

V

IH

IL

t

AR

t

ACH

RAD

RAH

ACH

t

CAH

ASR

ASC

CAH

ASC

CAH

ASC

V

IH

IL

ADDR

WE#

ROW

COLUMN

ROW

t

RCS

t

RCH

V

IH

IL

t

RRH

AA

t

AA

CPA

CAC

t

RAC

CPA

CAC

t

CAC

CLZ

t

OEHC

t

OFF

t

COH

t

CLZ

V

OH

OL

VALID

DATA

VALID

DATA

VALID

DATA

DQ

OPEN

t

OE

t

OD

t

OES

t

V

OES

IH

IL

OE#

t

OEP

DON’T CARE

UNDEFINED

EDO PAGE MODE

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

5

MAX

MIN

10

5

MAX

UNITS

ns

t

AA

25

30

OEHC

t

ACH

12

38

0

15

45

0

OEP

5

t

AR

OES

4

5

t

ASC

OFF

0

12

50

0

15

60

t

ASR

0

PC

20

25

t

CAC

13

15

RAC

t

CAH

8

0

3

8

10

0

RAD

9

12

10

60

14

0

t

CAS

10,000

RAH

t

CLZ

RASP

50

11

0

125,000

t

COH

3

RCD

t

CP

10

RCH

t

CPA

28

35

RCS

0

t

CRP

5

38

0

5

45

0

RP

30

0

40

0

t

CSH

RRH

t

OD

12

15

RSH

13

15

t

OE

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

20

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

FAST/EDO-PAGE-MODE EARLY WRITE CYCLE ²⁷

t

RP

RASP

V

IH

RAS#

CAS#

V

IL

t

CSH

PC

CP

RSH

CAS

t

CP

CRP

RCD

CAS

CP

V

IH

IL

t

AR

t

ACH

RAD

ACH

t

CAH

ASR

RAH

ASC

CAH

ASC

CAH

ASC

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

CWL

WCH

WP

CWL

WCH

WP

t

WCS

WCH

WP

WCS

V

IH

IL

WE#

t

WCR

DH

RWL

t

DS

DH

DS

DH

V

IOH

IOL

DQ

VALID DATA

V

IH

IL

OE#

DON’T CARE

UNDEFINED

FAST PAGE MODE AND EDO PAGE MODE

TIMING PARAMETERS

-5*

-6

-5*

-6

SYMBOL

MIN

12

38

0

MAX

MIN

15

45

0

MAX

UNITS

ns

SYMBOL

MIN

–

MAX

MIN

35

12

15

10

60

14

20

40

15

10

45

0

MAX

UNITS

ns

t

ACH (EDO)

PC (FPM)

t

AR

RAD (EDO)

9

t

ASC

RAD (FPM)

–

t

ASR

0

RAH

9

t

CAH

8

10

15

10

5

RASP

50

11

–

125,000

t

CAS (EDO)

8

10,000

–

10,000

RCD (EDO)

t

CAS (FPM)

–

RCD (FPM)

t

CP

8

RP

30

13

8

t

CRP

5

RSH

t

CSH (EDO)

38

–

45

60

10

15

10

0

RWL

t

CSH (FPM)

WCH

t

CWL (EDO)

8

WCR

38

0

t

CWL (FPM)

–

WCS

t

DH

8

WP (EDO)

5

t

DS

0

WP (FPM)

–

10

t

PC (EDO)

20

25

*EDO version only

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

21

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

READ-WRITE CYCLE ²⁷

(LATE WRITE and READ-MODIFY-WRITE cycles)

t

RWC

t

RP

RAS

V

IH

IL

RAS#

t

CSH

t

RSH

t

CAS

CRP

ASR

RCD

V

IH

IL

CAS#

ADDR

t

AR

t

CAH

RAD

ASC

RCS

t

ACH

RAH

V

IH

IL

ROW

COLUMN

ROW

t

RWD

CWL

RWL

WP

t

CWD

t

AWD

V

IH

IL

WE#

t

AA

t

RAC

t

CAC

t

DS

DH

t

CLZ

V

IOH

IOL

VALID D

DQ

OPEN

OUT

IN

t

OE

OD

OEH

V

IH

IL

OE#

DON’T CARE

UNDEFINED

FAST PAGE MODE AND EDO PAGE MODE

TIMING PARAMETERS

-5*

-6

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

30

UNITS

ns

SYMBOL

MIN

0

MAX

12

–

MIN

0

MAX

15

UNITS

ns

t

AA

25

OD (EDO)

OD (FPM)

OE

t

ACH (EDO)

12

38

0

15

45

0

–

3

15

t

AR

12

15

t

ASC

OEH (EDO)

OEH (FPM)

RAC

8

–

10/12**

15

t

ASR

0

t

AWD (EDO)

42

–

49

55

50

60

t

AWD (FPM)

RAD (EDO)

RAD (FPM)

RAH

9

–

12

15

10

60

14

20

0

t

CAC

13

15

t

CAH

8

10

15

0

9

t

CAS (EDO)

10,000

–

10,000

RAS

50

11

–

10,000

t

CAS (FPM)

–

RCD (EDO)

RCD (FPM)

RCS

t

CLZ (EDO)

0

t

CLZ (FPM)

–

3

0

t

CRP

5

RP

30

13

116

–

40

15

140

155

79

85

15

5

t

CSH (EDO)

38

–

45

60

35

40

10

15

10

0

RSH

t

CSH (FPM)

RWC (EDO)

RWC (FPM)

RWD (EDO)

RWD (FPM)

RWL

t

CWD (EDO)

28

–

t

CWD (FPM)

67

–

t

CWL (EDO)

8

t

CWL (FPM)

–

13

5

t

DH

8

WP (EDO)

WP (FPM)

t

DS

0

–

10

* EDO version only

**16MB DIMM

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

22

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

FAST/EDO-PAGE-MODE READ-WRITE CYCLE ²⁷

(LATE WRITE and READ-MODIFY-WRITE cycles)

t

RP

RASP

V

IH

IL

RAS#

CAS#

t

NOTE 1

CSH

PC

PRWC

RSH

CAS

t

CP

CRP

RCD

CAS

CP

CAS

CP

V

IH

IL

t

AR

t

RAD

RAH

t

CAH

ASR

ASC

CAH

ASC

CAH

ASC

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

RWD

t

RWL

t

CWL

t

RCS

t

CWL

t

WP

t

AWD

CWD

t

CWD

V

IH

IL

WE#

t

AA

t

RAC

t

DH

t

CPA

t

DS

t

CAC

CLZ

CAC

CLZ

CAC

CLZ

V

IOH

IOL

VALID

OUT

VALID

IN

VALID

OUT

VALID

IN

VALID

OUT

VALID

IN

DQ

OPEN

D

t

OD

t

OE

OEH

V

IH

IL

OE#

DON’T CARE

UNDEFINED

FAST PAGE MODE AND EDO PAGE MODE

TIMING PARAMETERS

-5*

-6

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

–

MIN

MAX

15

UNITS

ns

t

AA

25

30

OD (FPM)

OE

–

3

t

AR

38

0

45

0

12

15

t

ASC

OEH (EDO)

OEH (FPM)

PC (EDO)

PC (FPM)

PRWC (EDO)

PRWC (FPM)

RAC

8

–

10/12**

15

t

ASR

0

t

AWD (EDO)

42

–

49

55

20

–

25

t

AWD (FPM)

35

t

CAC

13

15

47

–

56

t

CAH

8

–

0

–

8

10

15

0

85

t

CAS (EDO)

10,000

–

10,000

50

60

t

CAS (FPM)

RAD (EDO)

RAD (FPM)

RAH

9

–

12

15

10

60

14

20

0

t

CLZ (EDO)

t

CLZ (FPM)

3

9

t

CP

10

RASP

50

11

–

125,000

t

CPA

28

35

RCD (EDO)

RCD (FPM)

RCS

t

CRP

5

38

–

5

t

CSH (EDO)

45

60

35

40

10

15

10

0

t

CSH (FPM)

RP

30

13

67

–

40

15

79

85

15

5

t

CWD (EDO)

28

–

RSH

t

CWD (FPM)

RWD (EDO)

RWD (FPM)

RWL

t

CWL (EDO)

8

t

CWL (FPM)

–

13

5

t

DH

8

WP (EDO)

WP (FPM)

t

DS

0

–

10

t

OD (EDO)

0

12

0

15

* EDO version only

**16MB DIMM

t

NOTE: 1. PC is for LATE WRITE cycles only.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

23

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

EDO-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

t

RP

RASP

V

IH

IL

RAS#

t

CSH

t

PC

RSH

PC

t

CP

CRP

RCD

CAS

CP

CAS

CP

CAS

V

IH

IL

CAS#

t

AR

t

RAD

ACH

CAH

t

ASR

t

ASC

RAH

ASC

CAH

ASC

CAH

V

IH

IL

ADDR

WE#

ROW

COLUMN (A)

COLUMN (B)

ROW

COLUMN (N)

t

RCH

t

RCS

WCS

WCH

V

IH

IL

t

AA

t

AA

t

CPA

RAC

t

DH

t

CAC

DS

CAC

t

WHZ

COH

V

IOH

IOL

VALID

DATA (B)

DQ

VALID DATA

IN

OPEN

VALID DATA (A)

t

OE

V

IH

IL

OE#

DON’T CARE

UNDEFINED

EDO PAGE MODE

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

t

AA

25

30

ns

OE

12

15

t

ACH

12

38

0

15

45

0

PC

20

25

t

AR

RAC

50

60

t

ASC

RAD

9

12

10

60

14

0

t

ASR

0

RAH

t

CAC

13

15

RASP

50

11

0

125,000

t

CAH

8

3

8

10

3

RCD

t

CAS

10,000

RCH

t

COH

RCS

0

t

CP

10

RP

30

13

8

40

15

10

0

t

CPA

28

35

RSH

t

CRP

5

38

8

5

45

10

0

WCH

t

CSH

WCS

0

t

DH

WHZ

0

12

0

15

t

DS

0

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

24

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

FAST-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

t

RP

RASP

V

IH

IL

RAS#

CAS#

ADDR

V

t

RSH

t

CSH

PC

t

CP

CRP

RCD

CAS

CP

CAS

V

IH

IL

t

AR

t

RAD

RAH

t

CAH

t

CAH

ASC

ASR

ASC

V

IH

IL

ROW

COLUMN

t

ROW

CWL

t

RCS

RWL

t

WP

t

WCS

WCH

V

IH

IL

WE#

t

CAC

NOTE 1

t

DH

CLZ

OFF

DS

V

VALID

DATA

OH

OL

DQ

VALID DATA

OPEN

t

AA

t

RAC

V

IH

IL

OE#

DON’T CARE

UNDEFINED

FAST PAGE MODE

TIMING PARAMETERS

-6

SYMBOL

MIN

3

MAX

UNITS

ns

SYMBOL

MIN

MAX

UNITS

ns

t

OFF

15

AA

30

t

PC

35

AR

45

0

t

RAC

RAD

RAH

RASP

RCD

RCS

RP

60

ASC

t

15

10

60

20

0

ASR

0

t

CAC

15

t

125,000

CAH

10

15

3

t

CAS

10,000

t

CLZ

t

40

15

10

0

CP

10

5

t

RSH

RWL

WCH

WCS

WP

CRP

t

CSH

60

15

10

0

t

CWL

t

DH

t

10

DS

NOTE: 1. Do not drive data prior to tristate.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

25

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

EDO READ CYCLE

(with WE#-controlled disable)

V

IH

RAS#

CAS#

V

IL

t

CSH

t

CP

RCD

CAS

CAH

CRP

V

IH

IL

t

AR

t

RAD

RAH

t

ASC

ASR

ASC

V

IH

IL

ROW

COLUMN

ADDR

WE#

t

RCS

t

RCH

WPZ

RCS

V

IH

IL

t

AA

RAC

CAC

CLZ

t

WHZ

CLZ

V

OH

OL

DQ

OPEN

VALID DATA

t

OD

OE

V

IH

IL

OE#

DON’T CARE

UNDEFINED

EDO PAGE MODE

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

SYMBOL

MIN

MAX

12

MIN

MAX

15

UNITS

t

AA

25

30

ns

OD

0

ns

t

AR

38

0

45

0

OE

12

15

t

ASC

RAC

50

60

t

ASR

0

RAD

9

12

10

14

0

t

CAC

13

15

RAH

t

CAH

8

10

0

RCD

11

0

t

CAS

10,000

RCH

t

CLZ

0

RCS

0

t

CP

8

10

5

WHZ

0

12

0

15

t

CRP

5

WPZ

10

t

CSH

38

45

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

26

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

RAS#-ONLY REFRESH CYCLE ²⁷

t

RC

t

RP

RAS

V

IH

IL

RAS#

CAS#

ADDR

V

t

RPC

CRP

V

IH

IL

t

RAH

ASR

V

IH

IL

ROW

V

OH

OL

DQ

OPEN

V

IH

IL

WE#

CBR REFRESH CYCLE ²⁷

(Addresses, OE# = DON’T CARE)

t

RAS

RP

RAS

NOTE 1

RP

V

IH

IL

RAS#

t

RPC

CP

t

RPC

t

CHR

CSR

CHR

CSR

V

IH

IL

CAS#

DQ

V

OH

OL

OPEN

t

WRH

WRP

WRH

WRP

V

IH

IL

WE#

DON’T CARE

UNDEFINED

FAST PAGE MODE AND EDO PAGE MODE

TIMING PARAMETERS

-5*

-6

-5*

-6

SYMBOL

MIN

0

MAX

MIN

0

MAX

UNITS

ns

SYMBOL

MIN

–

MAX

MIN

110

104

40

0

MAX

UNITS

ns

t

ASR

RC (FPM)

t

CHR

8

10

5

ns

RC (EDO)

84

30

–

ns

t

CP

8

ns

RP

ns

t

CRP

5

ns

RPC (FPM)

ns

t

CSR

5

ns

RPC (EDO)

5

ns

t

RAH

9

10

60

ns

WRH

8

10

ns

t

RAS

50

10,000

ns

WRP

8

ns

*EDO version only

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

27

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

HIDDEN REFRESH CYCLE^{20, 27}

(WE# = HIGH; OE# = LOW)

t

RC

t

RAS

RP

V

IH

RAS#

CAS#

V

IL

t

CRP

RCD

RSH

CHR

V

IH

IL

t

AR

RAD

t

CAH

ASR

RAH

ASC

V

IH

IL

ADDR

ROW

COLUMN

t

AA

t

RAC

CAC

CLZ

t

OFF

V

IOH

IOL

DQ

OPEN

VALID DATA

OPEN

t

OD

OE

ORD

V

IH

IL

OE#

DON’T CARE

UNDEFINED

FAST PAGE MODE AND EDO PAGE MODE

TIMING PARAMETERS

-5*

-6

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

MIN

MAX

UNITS

t

AA

25

30

OFF (EDO)

ORD

0

12

0

15

ns

t

AR

38

0

45

0

t

ASC

RAC

50

60

t

ASR

0

RAD (FPM)

RAD (EDO)

RAH

–

9

15

12

t

CAC

13

15

t

CAH

8

–

0

5

–

0

10

3

9

10

t

CHR

RAS

50

–

10,000

60

10,000

t

CLZ (FPM)

RC (FPM)

RC (EDO)

RCD (FPM)

RCD (EDO)

RP

110

104

20

t

CLZ (EDO)

0

84

–

t

CRP

5

t

OD (FPM)

–

12

–

3

15

11

30

13

14

t

OD (EDO)

0

40

t

OE

RSH

15

t

OFF (FPM)

–

3

*EDO version only

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

28

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

SPD EEPROM

t

F

HIGH

R

t

LOW

SCL

t

SU:STO

SU:STA

HD:STA

HD:DAT

SU:DAT

SDA IN

t

DH

AA

BUF

SDA OUT

UNDEFINED

SERIAL PRESENCE-DETECT EEPROM

TIMING PARAMETERS

SYMBOL

MIN

0.3

MAX

UNITS

µs

SYMBOL

MIN

4

MAX

UNITS

µs

t

AA

3.5

HIGH

t

BUF

4.7

µs

LOW

4.7

µs

t

DH

300

ns

R

1

µs

t

F

300

ns

SU:DAT

250

4.7

ns

t

HD:DAT

0

4

µs

SU:STA

µs

t

HD:STA

µs

SU:STO

µs

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

29

OBSOLETE

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

168-PIN DIMM

DF-12 (16MB)

FRONT VIEW

5.256 (133.50)

5.244 (133.20)

.200 (5.08)

MAX

.079 (2.00) R

(2X)

1.005 (25.53)

.995 (25.27)

.700 (17.78)

TYP

.118 (3.00)

(2X)

.118 (3.00) TYP

.054 (1.37)

.046 (1.17)

.250 (6.35) TYP

1.661 (42.18)

2.625 (66.68)

PIN 1 (PIN 85 on backside)

.128 (3.25)

.118 (3.00)

(2X)

.118 (3.00)

TYP

.039 (1.00) R(2X)

.039 (1.00)

TYP

.050 (1.27)

TYP

PIN 84 (PIN 168 ON BACKSIDE)

4.550 (115.57)

168-PIN DIMM

DF-13 (32MB)

FRONT VIEW

5.256 (133.50)

.350 (8.89)

MAX

5.244 (133.20)

.079 (2.00) R

(2X)

1.005 (25.53)

.995 (25.27)

.118 (3.00)

(2X)

.700 (17.78)

TYP

.118 (3.00) TYP

.054 (1.37)

.046 (1.17)

.250 (6.35) TYP

.039 (1.00) R(2X)

PIN 84

PIN 1

.118 (3.00)

TYP

.039 (1.00)

TYP

.050 (1.27)

TYP

4.550 (115.57)

BACK VIEW

.128 (3.25)

.118 (3.00)

(2X)

1.661 (42.18)

2.625 (66.68)

PIN 168

PIN 85

MAX

NOTE: 1. All dimensions in inches (millimeters)

or typical where noted.

MIN

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

DM60.p65 – Rev. 6/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1998, Micron Technology, Inc.

30


型号：	MT9LD272AG-6X
厂家：	MICRON TECHNOLOGY
描述：	2, 4 MEG x 72 NONBUFFERED DRAM DIMMs 2 ， 4梅格X 72无缓冲DIMM的DRAM 动态存储器
文件：	总30页 (文件大小：412K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT9LD272AG-6X [MICRON]

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