MT40A1G16WBU-075E_技术文档

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

Description

TwinDie™ 1.2V DDR4 SDRAM

MT40A1G16 – 64 Meg x 16 x 16 Banks x 1 Ranks

Options

• Configuration

Marking

Description

The 16Gb (TwinDie™) DDR4 SDRAM uses

Micron’s 8Gb DDR4 SDRAM die; two x8s combined to

make one x16. Similar signals as mono x16, there is

one extra ZQ connection for faster ZQ Calibration and

a BG1 control required for x8 addressing. Refer to Mi-

cron’s 8Gb DDR4 SDRAM data sheet (x8 option) for

the specifications not included in this document.

Specifications for base part number MT40A1G8 corre-

late to TwinDie manufacturing part number

MT40A1G16.

– 64 Meg x 16 x 16 banks x 1 rank

• 96-ball FBGA package (Pb-free)

– 9.5mm x 14mm x 1.2mm Die Rev :A

– 8.0mm x 14mm x 1.2mm Die Rev :B,

D

1G16

HBA

WBU

– 7.5mm x 13.5mm x 1.2mm Die

Rev :H

KNR

• Timing – cycle time¹

– 0.682ns @ CL = 20 (DDR4-2933)

– 0.682ns @ CL = 21 (DDR4-2933)

– 0.750ns @ CL = 18 (DDR4-2666)

– 0.750ns @ CL = 19 (DDR4-2666)

– 0.833ns @ CL = 16 (DDR4-2400)

– 0.833ns @ CL = 17 (DDR4-2400)

– 0.937ns @ CL = 15 (DDR4-2133)

– 0.937ns @ CL = 16 (DDR4-2133)

– 1.071ns @ CL = 13 (DDR4-1866)

• Self refresh

-068E

-068

-075E

-075

-083E

-083

-093E

-093

Features

• Uses two x8 8Gb Micron die to make one x16

• Single rank TwinDie

• V_DD= V_DDQ= 1.2V (1.14–1.26V)

• 1.2V V_DDQ-terminated I/O

• JEDEC-standard ball-out

• Low-profile package

• T_Cof 0°C to 95°C

– 0°C to 85°C: 8192 refresh cycles in 64ms

– 85°C to 95°C: 8192 refresh cycles in 32ms

-107E

– Standard

None

• Operating temperature

– Commercial (0°C ≤ T_C≤ 95°C)

• Revision

None

:A

:B, D

:H

1. CL = CAS (READ) latency.

Note:

Table 1: Key Timing Parameters

Speed Grade

-068E¹

-068¹

Data Rate (MT/s)

Target ^tRCD-^tRP-CL

^tRCD (ns)

13.64

14.32

13.5

^tRP (ns)

13.64

14.32

13.5

CL (ns)

13.64

14.32

13.5

2933

2666

2400

2133

1866

20-20-20

21-21-21

18-18-18

19-19-19

16-16-16

17-17-17

15-15-15

16-16-16

13-13-13

-075E²

-075²

-083E³

-083³

-093E⁴

-093⁴

-107E⁵

14.25

13.32

14.16

14.06

15

14.25

13.32

14.16

14.06

15

14.25

13.32

14.16

14.06

15

13.92

1. Backward compatible to 1600, CL = 11; 1866, CL = 13; 2133, CL = 15; 2400, CL = 17; and 2666, CL = 19.

2. Backward compatible to 1600, CL = 11; 1866, CL = 13; 2133, CL = 15; and 2400, CL = 17.

Notes:

09005aef86573aa8

DDR4_16Gb_x16_1CS_TwinDie.pdf - Rev. E 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

1

Products and specifications discussed herein are subject to change by Micron without notice.

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

Description

3. Backward compatible to 1600, CL = 11; 1866, CL = 13; and 2133, CL = 15.

4. Backward compatible to 1600, CL = 11 and 1866, CL = 13.

5. Backward compatible to 1600, CL = 11.

Table 2: Addressing

Parameter

1024 Meg x 16

Configuration

64 Meg x 16 x 16 banks x 1 rank

Bank group address

Bank count per group

Bank address in bank group

Row addressing

BG[1:0]

4

BA[1:0]

64K (A[15:0])

1K (A[9:0])

1KB

Column addressing

Page size

1. Page size is per bank, calculated as follows:

Note:

Page size = 2^COLBITS× ORG/8, where COLBIT = the number of column address bits and ORG = the number of

DQ bits.

09005aef86573aa8

DDR4_16Gb_x16_1CS_TwinDie.pdf - Rev. E 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

Ball Assignments

Figure 1: 96-Ball x16 SR DDP Ball Assignments

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

A

B

C

D

E

F

V

UDQ0

UDQS_c

V

DDQ

SSQ

V

UDQS_t UDQ1

UDQ3 UDQ5

V

DD

PP

SS

DD

V

UDQ4 UDQ2

V

DDQ

SSQ

DDQ

V

UDQ6

UDQ7

V

DD

SSQ

NF/LDM_n/

LDBI_n

NF/UDM_n/

UDBI_n

V

UZQ

LZQ

SS

SSQ

DDQ

SSQ

V

LDQS_c

LDQ1

V

DDQ

G

H

J

G

H

J

V

LDQ0 LDQS_t

LDQ4 LDQ2

V

SS

DDQ

DD

V

LDQ3

LDQ7

CK_t

LDQ5

V

SSQ

V

LDQ6

ODT

V

DD

DDQ

K

L

K

L

V

CKE

CK_c

V

SS

DD

SS

DD

V

WE_n/A14 ACT_n

BG0 A10/AP

CS_n RAS_n/A16 V

M

N

P

R

T

M

N

P

R

T

V

A12/BC_n CAS-n/A15 BG1

REFCA

V

BA0

A4

A0

A3

A1

A9

V

BA1

A5

TEN

SS

ALERT_n

RESET_n A6

V

A8

A2

A7

V

DD

PP

V

A11

PAR

A13

V

SS

DD

1. See Ball Descriptions in the monolithic data sheet.

Notes:

2. A slash “/” defines a selectable function. For example: Ball E2 = NF/UDM_n/UDBI_n

where either NF, UDM_n, or UDBI_n is defined via MRS.

09005aef86573aa8

DDR4_16Gb_x16_1CS_TwinDie.pdf - Rev. E 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

3

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

Functional Block Diagrams

Figure 2: Functional Block Diagram (128 Meg x 16 x 16 Banks x 1 Rank)

(128 Meg x 16 x 16 banks)

Byte 1

(64 Meg x 8 x 16 banks)

Byte 0

(64 Meg x 8 x 16 banks)

CS_n

CK_t

CK_c

CKE

LZQ

LDM_n/

LDBI_n

RAS_n/A16

CAS_n/A15

WE_n/A14

ACT_n

UDM_n/

UDBI_n

UZQ

BG[1:0]

BA[1:0]

A[13:0]

ODT

TEN

UDQ[7:0]

UDQS_t

UDQS_c

LDQ[7:0]

LDQS_t

LDQS_c

PAR

VrefCA

RESET_n

ALERT_n

09005aef86573aa8

DDR4_16Gb_x16_1CS_TwinDie.pdf - Rev. E 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

Connectivity Test Mode

Connectivity test (CT) mode for the x16 TwinDie single rank (SR) device is the same as

two mono x8 devices connected in parallel. The mapping is restated for clarity.

Minimum Terms Definition for Logic Equations

The test input and output pins are related by the following equations, where INV de-

notes a logical inversion operation and XOR a logical exclusive OR operation:

MT0 = XOR (A1, A6, PAR)

MT1 = XOR (A8, ALERT_n, A9)

MT2 = XOR (A2, A5, A13)

MT3 = XOR (A0, A7, A11)

MT4 = XOR (CK_c, ODT, CAS_n/A15)

MT5 = XOR (CKE, RAS_n/A16, A10/AP)

MT6 = XOR (ACT_n, A4, BA1)

MT7L = XOR (BG1, LDM_n/LDBI_n, CK_t)

MT7U = XOR (BG1, UDM_n/UDBI_n, CK_t)

MT8 = XOR (WE_n/A14, A12 / BC, BA0)

MT9 = XOR (BG0, A3, RESET_n and TEN)

Logic Equations for a x16 TwinDie, SR Device

Byte 0

Byte 1

LDQ0 = MT0

LDQ1 = MT1

LDQ2 = MT2

LDQ3 = MT3

LDQ4 = MT4

LDQ5 = MT5

LDQ6 = MT6

LDQ7 = MT7L

LDQS_t = MT8

LDQS_c = MT9

UDQ0 = MT0

UDQ1 = MT1

UDQ2 = MT2

UDQ3 = MT3

UDQ4 = MT4

UDQ5 = MT5

UDQ6 = MT6

UDQ7 = MT7U

UDQS_t = MT8

UDQS_c = MT9

x16 TwinDie, SR Internal Connections

The figure below shows the internal connections of the x16 TwinDie, SR. The diagram

shows why byte 0 and byte 1 outputs have the same logic equations except LDQ7 and

UDQ7; they are different because the DM_n/DBI_n pins are not common for each byte.

09005aef86573aa8

DDR4_16Gb_x16_1CS_TwinDie.pdf - Rev. E 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

5

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

Connectivity Test Mode

Figure 3: x16 TwinDie, SR

Byte 1

Byte 0

CS_n

RAS_n/A16

CAS_n/A15

WE_n/A14

ACT_n

CK_t

LZQ

LDM_n/

LDBI_n

UDM_n/

UDBI_n

UZQ

CK_c

CKE

BG[1:0]

BA[1:0]

A[13:0]

UDQ[7:0]

UDQS_t

UDQS_c

ODT

TEN

LDQ[7:0]

LDQS_t

LDQS_c

PAR

RESET_n

ALERT_n

V

REFCA

09005aef86573aa8

DDR4_16Gb_x16_1CS_TwinDie.pdf - Rev. E 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

6

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

Electrical Specifications – Leakages

Table 3: Input and Output Leakages

Symbol

Parameter

Min

Max

Units

Notes

I_I

Input leakage current

Any input 0V ≤ V_IN≤ V_DD

V_REFpin 0V ≤ V_IN≤ 1.1V

–4

4

µA

1

,

(All other pins not under test = 0V)

I_VREF

V_REFsupply leakage current

–4

4

µA

2

V_REFDQ= V_DD/2 or V_REFCA= V_DD/2

(All other pins not under test = 0V)

I_ZQ

Input leakage on ZQ pin

–3

–12

–

3

20

10

–

µA

I_TEN

Input leakage on TEN pin

Output leakage: V_OUT= V_DDQ

Output leakage: V_OUT= V_SSQ

I_OZPD

I_OZPU

3

–100

3, 4

1. Any input 0V < Vin < 1.1V

2. V_REFCA= V_DD/2, V_DDat valid level.

3. DQs are disabled.

Notes:

4. ODT is disabled with the ODT input HIGH.

Temperature and Thermal Impedance

It is imperative that the DDR4 SDRAM device’s temperature specifications, shown in

the following table, be maintained in order to ensure the junction temperature is in the

proper operating range to meet data sheet specifications. An important step in main-

taining the proper junction temperature is using the device’s thermal impedances cor-

rectly. The thermal impedances listed in Table 5 (page 8) apply to the current die re-

vision and packages.

Incorrectly using thermal impedances can produce significant errors. Read Micron

technical note TN-00-08, “Thermal Applications,” prior to using the values listed in the

thermal impedance table. For designs that are expected to last several years and require

the flexibility to use several DRAM die shrinks, consider using final target theta values

(rather than existing values) to account for increased thermal impedances from the die

size reduction.

The DDR4 SDRAM device’s safe junction temperature range can be maintained when

the T_Cspecification is not exceeded. In applications where the device’s ambient tem-

perature is too high, use of forced air and/or heat sinks may be required to satisfy the

case temperature specifications.

09005aef86573aa8

DDR4_16Gb_x16_1CS_TwinDie.pdf - Rev. E 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

7

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

Electrical Specifications – Leakages

Table 4: Thermal Characteristics

Notes 1–3 apply to entire table

Parameter

Symbol

Value

0 to 85

0 to 95

Units

°C

Notes

Operating temperature

T_C

°C

4

1. MAX operating case temperature T_Cis measured in the center of the package, as shown

below.

Notes:

2. A thermal solution must be designed to ensure that the device does not exceed the

maximum T_Cduring operation.

3. Device functionality is not guaranteed if the device exceeds maximum T_Cduring

operation.

4. If T_Cexceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9µs

interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh

(ASR), if available, must be enabled.

Figure 4: Temperature Test Point Location

Test point

Length (L)

0.5 (L)

0.5 (W)

Width (W)

Table 5: Thermal Impedance

Θ JA (°C/W)

Airflow =

0m/s

Θ JA (°C/W)

Airflow =

1m/s

Θ JA (°C/W)

Airflow =

2m/s

Substrate

Die Rev. conductivity

Θ JB (°C/W)

Θ JC (°C/W)

TBD

Notes

Low

TBD

43.9

27.1

TBD

33.0

21.7

TBD

29.5

20.1

TBD

N/A

TBD

N/A

10.5

N/A

TBD

A

1

High

N/A

Low

3.3

B, D

1

High

N/A

Low

TBD

H

High

N/A

1. Thermal resistance data is based on a number of samples from multiple lots and should

be viewed as a typical number.

Note:

09005aef86573aa8

DDR4_16Gb_x16_1CS_TwinDie.pdf - Rev. E 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

8

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

DRAM Package Electrical Specifications

Table 6: DRAM Package Electrical Specifications for x16 Devices

Notes 1–4 apply to the entire table

DDR4-1600, -1866 DDR4-2133, -2400 DDR4-2666, -2933

Parameter

Symbol

Z_IO

Min

30

65

–

Max

50

Min

30

65

–

Max

50

Min

30

65

–

Max

50

Unit Notes

Input/

output

Zpkg

ohm

ps

5, 6

Package delay

Lpkg

Td_IO

120

5.0

3.0

50

120

5.0

3.0

50

120

5.0

3.0

50

6 , 7

L_IO

nH

pF

Cpkg

C_IO

–

DQSL_t/

DQSL_c/

DQSU_t/

DQSU_c

Zpkg

Z_{IO DQS}

Td_{IO DQS}

L_{IO DQS}

C_{IO DQS}

DZ_{IO DQS}

DTd_{IO DQS}

30

65

–

30

65

–

30

65

–

ohm

ps

5

7

Package delay

Lpkg

120

5.0

3.0

20

120

5.0

3.0

20

120

5.0

3.0

20

nH

pF

Cpkg

–

DQSL_t/

DQSL_c,

DQSU_t/

DQSU_c,

Delta Zpkg

Delta delay

–

ohm

ps

5, 8

7, 8

–

45

–

45

–

45

Input CTRL Zpkg

pins

Z_{I CTRL}

Td_{I CTRL}

L_{I CTRL}

35

75

–

65

120

6.5

2.5

65

35

75

–

65

120

6.5

2.5

65

35

75

–

65

120

6.5

2.5

65

ohm

ps

5, 9

7, 9

Package delay

Lpkg

Cpkg

nH

pF

C_{I CTRL}

–

Input CMD Zpkg

ADD pins

Z_{I ADD CMD}

35

70

–

35

70

–

35

70

–

ohm

ps

5, 10

7, 10

Package delay Td_{I ADD CMD}

125

6.5

3.0

55

125

6.5

3.0

55

125

6.5

3.0

55

Lpkg

Cpkg

L_{I ADD CMD}

C_{I ADD CMD}

Z_CK

nH

pF

–

CK_t, CK_c Zpkg

30

80

–

30

80

–

30

80

–

ohm

ps

5

Package delay

Td_CK

135

0.5

1.2

6.0

3.0

40

135

0.5

1.2

6.0

3.0

40

135

0.5

1.2

6.0

3.0

40

7

Delta Zpkg

Delta delay

Lpkg

DZ_DCK

DTd_DCK

L_{I CLK}

ohm

ps

5, 11

7, 11

–

Input CLK

–

nH

pF

Cpkg

C_{I CLK}

–

ZQ Zpkg

Z_{O ZQ}

–

ohm

ps

5

7

5

7

ZQ delay

Td_{O ZQ}

Z_{O ALERT}

Td_{O ALERT}

55

30

65

120

55

30

65

120

55

30

65

120

55

ALERT Zpkg

ALERT delay

ohm

ps

110

1. The package parasitic (L and C) are not subject to production testing. If the package par-

asitic (L and C) are measured, the capacitance is measured with V_DD, V_DDQ, V_SS, and V_SSQ

Notes:

shorted with all other signal pins floating. The inductance is measured with V_DD, V_DDQ

V_SS, and V_SSQshorted and all other signal pins shorted at the die, not pin, side.

,

2. Package implementations should satisfy targets if the Zpkg and package delay fall with-

in the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maximum

09005aef86573aa8

DDR4_16Gb_x16_1CS_TwinDie.pdf - Rev. E 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

9

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

DRAM Package Electrical Specifications

values shown. The package design targets are provided for reference, system signal sim-

ulations should not use these values but use the Micron package model.

3. It is assumed that Lpkg can be approximated as Lpkg = Z_O× Td.

4. It is assumed that Cpkg can be approximated as Cpkg = Td/Z_O.

5. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a

given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg).

6. Z_IOand Td_IOapply to DQ, DM, DQS_c, DQS_t, TDQS_t, and TDQS_c.

7. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin

where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg).

8. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO

(DQS_t), TdIO (DQS_c) for delay (Td).

9. Z_{I CTRL}and Td_{I CTRL}apply to ODT, CS_n, and CKE.

10. Z_{I ADD CMD}and Td_{I ADD CMD}apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, and WE_n.

11. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c

for delay (Td).

Table 7: Pad Input/Output Capacitance

DDR4-1600,

-1866, -2133

DDR4-2400,

-2666

DDR4-2933

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit Notes

Input/output capacitance: DQ,

DM, DQS_t, DQS_c, TDQS_t,

TDQS_c

C_IO

1.8

2.8

1.8

2.8

1.8

2.8

pF

1, 2, 3

Input capacitance: CK_t and

CK_c

C_CK

C_DCK

C_DDQS

C_I

2.1

0

2.9

0.05

2.6

2.1

0

2.9

0.05

2.6

2.1

0

2.9

0.05

2.6

pF

1, 2, 3, 4

1, 2, 3, 5

1, 3

Input capacitance delta: CK_t

and CK_c

Input/output capacitance delta:

DQS_t and DQS_c

0

Input capacitance: CTRL, ADD,

CMD input-only pins

1.6

1, 3, 6

Input capacitance delta: All

CTRL input-only pins

C_{DI_CTRL}

C_{DI_ADD_CMD}

C_DIO

–0 .9

–0.16

0.9

–0 .9

–0.16

0.9

–0 .9

–0.16

0.9

1, 3, 7

Input capacitance delta: All

ADD/CMD input-only pins

0.9

1, 3, 8, 9

Input/output capacitance delta:

DQ, DM, DQS_t, DQS_c, TDQS_t,

TDQS_c

0.16

1, 2, 10,

11

Input/output capacitance:

ALERT pin

C_ALERT

C_ZQ

1.1

–

2.3

3.7

2.3

1.1

–

2.3

3.7

2.3

1.1

–

2.3

3.7

2.3

pF

1, 3

Input/output capacitance: ZQ

1, 3, 12

1, 3, 13

Input/output capacitance: TEN

C_TEN

0.2

1. Although the DM, TDQS_t, and TDQS_c pins have different functions, the loading

matches DQ and DQS.

Notes:

09005aef86573aa8

DDR4_16Gb_x16_1CS_TwinDie.pdf - Rev. E 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

10

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

DRAM Package Electrical Specifications

2. This parameter is not subject to a production test; it is verified by design and characteri-

zation and are provided for reference; system signal simulations should not use these

values but use the Micron package model. The capacitance, if and when, is measured ac-

cording to the JEP147 specification, “Procedure for Measuring Input Capacitance Using

a Vector Network Analyzer (VNA),” with V_DD, V_DDQ, V_SS, and V_SSQapplied and all other

pins floating (except the pin under test, CKE, RESET_n and ODT, as necessary). V_DD

V_DDQ= 1.5V, V_BIAS= V_DD/2 and on-die termination off.

=

3. This parameter applies to SR x16 TwinDie, obtained by de-embedding the package L and

C parasitics.

4. C_DIO= C_IO(DQ, DM) - 0.5 × (C_IO(DQS_t) + C_IO(DQS_c)).

5. Absolute value of C_IO(DQS_t), C_IO(DQS_c)

6. Absolute value of CCK_t, CCK_c

7. C_Iapplies to ODT, CS_n, CKE, A[15:0], BA[1:0], RAS_n, CAS_n, and WE_n.

8. C_{DI_CTRL}applies to ODT, CS_n, and CKE.

9. C_{DI_CTRL}= C_I(CTRL) - 0.5 × (C_I(CLK_t) + C_I(CLK_c)).

10. C_{DI_ADD_CMD}applies to A[15:0], BA1:0], RAS_n, CAS_n and WE_n.

11. C_{DI_ADD_CMD}= C_I(ADD_CMD) - 0.5 × (C_I(CLK_t) + C_I(CLK_c)).

12. Maximum external load capacitance on ZQ pin: 5pF.

13. Only applicable if TEN pin does not have an internal pull-up.

09005aef86573aa8

DDR4_16Gb_x16_1CS_TwinDie.pdf - Rev. E 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

11

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

Current Specifications – Limits

Table 8: x16 I_DD, I_PP, and I_DDQCurrent Limits – Rev. A

Symbol

_DD0: One bank ACTIVATE-to-PRECHARGE

current

_PP0: One bank ACTIVATE-to-PRECHARGE I_PP

current

_DD1: One bank ACTIVATE-to-READ-to-PRE-

CHARGE current

DDR4-2133¹DDR4-2400 DDR4-2666 DDR4-2933

Unit

Notes

I

110

120

130

TBD

mA

2, 3, 4

I

6

mA

I

140

90

150

100

160

110

3, 4, 5

I

_DD2N: Precharge standby current

4, 6, 7, 8,

9, 10, 11

I

_DD2NT: Precharge standby ODT current

_DD2P: Precharge power-down current

_DD2Q: Precharge quiet standby current

_DD3N: Active standby current

110

50

120

60

130

70

TBD

mA

4, 11

90

100

120

6

110

6

110

6

_PP3N: Active standby I_PPcurrent

_DD3P: Active power-down current

_DD4R: Burst read current

70

80

4, 11

300

350

4, 14, 13,

11

I

_DD4W: Burst write current

300

320

350

TBD

mA

4, 11, 15,

16, 17,

18

I_DD5B: Burst refresh current (1X REF)

I_PP5B: Burst refresh I_PPcurrent (1X REF)

I_DD6N: Self refresh current; 0–85°C

I_DD6E: Self refresh current; 0–95°C

I_DD6R: Self refresh current; 0–45°C

450

60

70

50

450

60

70

50

450

60

70

50

TBD

mA

4, 19, 20

11, 21

11, 22

11, 23,

24

I_DD6A: Auto self refresh current (25°C)

I_DD6A: Auto self refresh current (45°C)

I_DD6A: Auto self refresh current (75°C)

I_DD7: Bank interleave read current

I_PP7: Bank interleave read I_PPcurrent

I_DD8: Maximum power-down current

40

50

40

50

40

50

TBD

mA

11, 24

4

70

400

30

410

30

430

30

40

11

1. DDR4-1600 and DDR4-1866 use the same I_DDlimits as DDR4-2133.

Notes:

2. When additive latency is enabled for I_DD0, current changes by approximately 0%.

3. I_PP0test and limit is applicable for I_DD0and I_DD1conditions.

4. The I_DDvalues must be derated (increased) when operated outside of the range 0°C ≤ T_C

≤ 85°C:

When T_C< 0°C: I_DD2Pand I_DD3Pmust be derated by 6%; I_DD4Rand I_DD4Wmust be derated

by 4%; and I_DD7must be derated by 11%.

09005aef86573aa8

DDR4_16Gb_x16_1CS_TwinDie.pdf - Rev. E 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

12

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

Current Specifications – Limits

When T_C> 85°C: I_DD0, I_DD1, I_DD2N, I_DD2NT, I_DD2Q, I_DD3N, I_DD3P, I_DD4R, I_DD4W, and I_DD5Bmust

be derated by 3%; I_DD2Pmust be derated by 40%.

5. When additive latency is enabled for I_DD1, current changes by approximately +4%.

6. When additive latency is enabled for I_DD2N, current changes by approximately +0%.

7. When DLL is disabled for I_DD2N, current changes by approximately –23%.

8. When CAL is enabled for I_DD2N, current changes by approximately –25%.

9. When gear-down is enabled for I_DD2N, current changes by approximately 0%.

10. When CA parity is enabled for I_DD2N, current changes by approximately +7%.

11. I_PP3Ntest and limit is applicable for all I_DD2x, I_DD3x, I_DD4x, I_DD6x, and I_DD8conditions; that

is, testing I_PP3Nshould satisfy the I_PPs for the noted I_DDtests.

12. When additive latency is enabled for I_DD3N, current changes by approximately +0.6%.

13. When additive latency is enabled for I_DD4R, current changes by approximately +5%.

14. When read DBI is enabled for I_DD4R, current changes by approximately 0%.

15. When additive latency is enabled for I_DD4W, current changes by approximately +4%.

16. When write DBI is enabled for I_DD4W, current changes by approximately 0%.

17. When write CRC is enabled for I_DD4W, current changes by approximately –3%.

18. When CA parity is enabled for I_DD4W, current changes by approximately +12%.

19. When 2X REF is enabled for I_DD5B, current changes by approximately –14%.

20. When 4X REF is enabled for I_DD5B, current changes by approximately –33%.

21. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature

range of operation (0–85°C).

22. Applicable for MR2 settings A7 = 1 and A7 = 0; manual mode with extended tempera-

ture range of operation (0–95°C).

23. Applicable for MR2 settings A7 = 0 and A7 = 1; manual mode with reduced temperature

range of operation (0–45°C).

24. I_DD6Rand I_DD6Avalues are typical.

Table 9: x16 I_DD, I_PP, and I_DDQCurrent Limits – Rev. B, D

Symbol

_DD0: One bank ACTIVATE-to-PRECHARGE

current

_PP0: One bank ACTIVATE-to-PRECHARGE I_PP

current

_DD1: One bank ACTIVATE-to-READ-to-PRE-

CHARGE current

DDR4-2133¹DDR4-2400 DDR4-2666 DDR4-2933

Unit

Notes

I

90

96

102

108

mA

2, 3, 4

I

6

mA

I

114

66

120

68

126

70

132

72

3, 4, 5

I

_DD2N: Precharge standby current

4, 6, 7, 8,

9, 10, 11

I

_DD2NT: Precharge standby ODT current

_DD2P: Precharge power-down current

_DD2Q: Precharge quiet standby current

_DD3N: Active standby current

90

50

60

80

6

100

50

60

86

6

100

50

60

92

6

110

50

60

98

6

mA

4, 11

_PP3N: Active standby I_PPcurrent

_DD3P: Active power-down current

_DD4R: Burst read current

78

250

82

270

86

292

90

314

4, 11

4, 14, 13,

11

09005aef86573aa8

DDR4_16Gb_x16_1CS_TwinDie.pdf - Rev. E 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

13

16Gb: x16 TwinDie Single Rank DDR4 SDRAM

Current Specifications – Limits

Table 9: x16 I_DD, I_PP, and I_DDQCurrent Limits – Rev. B, D (Continued)

Symbol

DDR4-2133¹DDR4-2400 DDR4-2666 DDR4-2933

Unit

Notes

I

_DD4W: Burst write current

230

246

264

282

mA

4, 11, 15,

16, 17,

18

I_DD5B: Burst refresh current (1X REF)

I_PP5B: Burst refresh I_PPcurrent (1X REF)

I_DD6N: Self refresh current; 0–85°C

I_DD6E: Self refresh current; 0–95°C

I_DD6R: Self refresh current; 0–45°C

500

56

60

70

40

500

56

60

70

40

500

56

60

70

40

500

56

60

70

40

mA

4, 19, 20

11, 21

11, 22

11, 23,

24

I_DD6A: Auto self refresh current (25°C)

I_DD6A: Auto self refresh current (45°C)

I_DD6A: Auto self refresh current (75°C)

I_DD7: Bank interleave read current

I_PP7: Bank interleave read I_PPcurrent

I_DD8: Maximum power-down current

17.2

40

17.2

40

17.2

40

17.2

40

mA

11, 24

4

60

340

30

350

30

360

30

370