MT28F320J3RG-11_技术文档

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

TM

‡

MT28F128J3 , MT28F640J3,

Q-FLASH MEMORY

‡

MT28F320J3

FEATURES

56-Pin TSOP Type I

• x8/x16 organization

• One hundred twenty-eight 128KB erase blocks

(128Mb)

Sixty-four 128KB erase blocks (64Mb)

Thirty-two 128KB erase blocks (32Mb)

• V^CC, VCCQ, and VPEN voltages:

2.7V to 3.6V V^CCoperation

2.7V to 3.6V or 4.5V to 5.5V* VCCQ operation

2.7V to 3.6V, or 5V V^PENapplication programming

• Interface Asynchronous Page Mode Reads:

150ns/25ns read access time (128Mb)

120ns/25ns read access time (64Mb)

110ns/25ns read access time (32Mb)

• Enhanced data protection feature with V^PEN= VSS

Flexible sector locking

Sector erase/program lockout during power

transition

• Security OTP block feature

64-BallFBGA

Permanent block locking (Contact factory for

availability)

• Industry-standard pinout

• Inputs and outputs are fully TTL-compatible

• Common Flash Interface (CFI) and Scalable

Command Set

• Automatic write and erase algorithm

• 4.7µs-per-byte effective programming time using

write buffer

• 128-bit protection register

64-bit unique device identifier

64-bit user-programmable OTP cells

• 100,000 ERASE cycles per block

• Automatic suspend options:

Block Erase Suspend-to-Read

Block Erase Suspend-to-Program

Program Suspend-to-Read

‡

NOTE: MT28F128J3, and MT28F320J3 are preliminary status.

• VCCQ Option*

MT28F640J3isproductionstatus.

2.7V–3.6V

None

F

4.5V–5.5V

• Packages

OPTIONS

MARKING

• Timing

56-pin TSOP Type I

64-ball FBGA (1.0mm pitch)

RG

FS

150ns (128Mb)

120ns (64Mb)

110ns (32Mb)

-15

-12

-11

Part Number Example:

MT28F640J3RG-12ET

• Operating Temperature Range

Commercial Temperature (0ºC to +85ºC)

Extended Temperature (-40ºC to +85ºC)

*Contact factory for availability of the MT28F320J3 and

MT28F640J3.

None

ET

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

1

‡

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE

SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S

PRODUCTIONDATASHEETSPECIFICATIONS.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

GENERALDESCRIPTION

The MT28F128J3 is a nonvolatile, electrically block-

erasable (Flash), programmable memory containing

134,217,728 bits organized as 16,777,218 bytes (8 bits)

or 8,388,608 words (16 bits). This 128Mb device is orga-

nized as one hundred twenty-eight 128KB erase blocks.

The MT28F640J3 contains 67,108,864 bits organized

as 8,388,608 bytes (8 bits) or 4,194,304 words (16 bits).

This 64Mb device is organized as sixty-four 128KB erase

blocks.

can provide data protection when connected to ground.

This pin also enables program or erase lockout during

power transition.

Micron’s even-sectored Q-Flash devices offer indi-

vidual block locking that can lock and unlock a block

using the sector lock bits command sequence.

Status (STS) is a logic signal output that gives an

additional indicator of the internal state machine (ISM)

activity by providing a hardware signal of both status

and status masking. This status indicator minimizes

central processing unit (CPU) overhead and system

power consumption. In the default mode, STS acts as

an RY/BY# pin. When LOW, STS indicates that the ISM

is performing a block erase, program, or lock bit con-

figuration. When HIGH, STS indicates that the ISM is

ready for a new command.

Three chip enable (CE) pins are used for enabling and

disabling the device by activating the device’s control

logic, input buffer, decoders, and sense amplifiers.

BYTE# enables selecting x8 or x16 READs/WRITEs

to the device. BYTE# at logic LOW selects an 8-bit mode

with address A0 selecting between the low byte

and the high byte. BYTE# at logic HIGH enables 16-bit

operation.

RP# is used to reset the device. When the device is

disabled and RP# is at V^CC, the standby mode is en-

abled. A reset time (^tRWH) is required after RP#

switches HIGH until outputs are valid. Likewise, the

device has a wake time (^tRS) from RP# HIGH until

WRITEs to the command user interface (CUI) are rec-

ognized. When RP# is at GND, it provides write protec-

tion, resets the ISM, and clears the status register.

A variant of the MT28F320J3 also supports the new

security block lock feature for additional code security.

This feature provides an OTP function for locking the

top two blocks, the bottom two blocks, or the entire

device. (Contact factory for availability.)

Similarly, the MT28F320J3 contains 33,554,432 bits

organized as 4,194,304 bytes (8 bits) or 2,097,152 words

(16 bits). This 32Mb device is organized as thirty-two

128KB erase blocks.

These three devices feature in-system block lock-

ing. They also have common flash interface (CFI) that

permits software algorithms to be used for entire fami-

lies of devices. The software is device-independent,

JEDEC ID-independent with forward and backward

compatibility.

Additionally, the scalable command set (SCS) al-

lows a single, simple software driver in all host systems

to work with all SCS-compliant Flash memory devices.

The SCS provides the fastest system/device data trans-

fer rates and minimizes the device and system-level

implementation costs.

To optimize the processor-memory interface, the

device accommodates V^PEN, which is switchable during

block erase, program, or lock bit configuration, or

hardwired to V^CC, depending on the application. VPEN is

treated as an input pin to enable erasing, program-

ming, and block locking. When V^PENis lower than the

VCC lockout voltage (VLKO), all program functions are

disabled. Block erase suspend mode enables the user

to stop block erase to read data from or program data to

any other blocks. Similarly, program suspend mode

enables the user to suspend programming to read data

or execute code from any unsuspended blocks.

VPEN serves as an input with 2.7V, 3.3V, or 5V for

application programming. VPEN in this Q-Flash family

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

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2

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

DEVICEMARKING

Due to the size of the package, Micron’s standard

part number is not printed on the top of each device.

Instead, an abbreviated device mark comprised of a

five-digit alphanumeric code is used. The abbreviated

device marks are cross referenced to Micron part num-

bers in Table 1.

Table 1

Cross Reference for Abbreviated Device Marks

PRODUCT

MARKING

ENGINEERING

SAMPLE

QUALIFIED

SAMPLE

PART NUMBER

MT28F320J3FS-11

MT28F320J3FS-11 ET

MT28F640J3FS-12

MT28F640J3FS-12 ET

MT28F128J3FS-15

MT28F128J3FS-15 ET

FW201

FW207

FW202

FW209

FW203

FW501

FX201

FX207

FX202

FX209

FX203

FX501

FQ201

FQ207

FQ202

FQ209

FQ203

FQ501

PIN/BALLASSIGNMENT(TopView)

64-BallFBGA

56-Pin TSOP Type I

1

2

3

4

5

6

7

8

56

NC

A22

CE1

A21

A20

A19

A18

A17

A16

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

WE#

OE#

STS

DQ15

DQ7

DQ14

DQ6

VSS

DQ13

DQ5

1

2

3

4

5

6

7

8

A1

A6

A8

V

PEN

A13

V

CC

A18

A22

A

B

C

D

E

A2

A3

VSS

A9

A10

CE0

A14

A15

DNU

DQ6

A19

A20

CE1

A21

A17

STS

9

V

CC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

A15

A14

A13

A12

CE0

A12

A7

A5

DQ12

DQ4

A4

A11

RP#

DNU

DQ4

DQ12

DQ5

DQ13

A16

V

CC

Q

SS

V

PEN

RP#

A11

A10

A9

DQ8

BYTE#

A23

CE2

DQ9

DQ10

DQ2

DQ3

DQ11

DQ15

DNU

DQ14

DQ7

DQ1

DQ0

A0

DQ11

DQ3

DQ10

DQ2

OE#

WE#

NC

F

V

CC

A8

VCCQ

G

H

DQ9

DQ1

DQ8

DQ0

A0

BYTE#

A23

CE2

V

SS

A7

A6

A5

A4

A3

A2

A1

VCC

V

SS

VSS

DNU

Top View

(Ball Down)

NOTE: 1. A22 only exists on the 64Mb and 128Mb devices. On the 32Mb, this pin/ball is a no connect (NC).

2. A23 only exists on the 128Mb device. On the 32Mb and 64Mb, this pin/ball is a no connect (NC).

3. The # symbol indicates signal is active LOW.

128Mb, 64Mb, 32MbQ-FlashMemory

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

FUNCTIONALBLOCKDIAGRAM

(128Mb)

Input

Buffer

I/O

Control

Logic

128KB Memory Block (0)

128KB Memory Block (1)

128KB Memory Block (2)

Addr.

Buffer/

Latch

A0–A23

Addr.

Power

(Current)

Control

Write

Buffer

Counter

DQ0–DQ15

CE0

CE1

CE2

OE#

WE#

RP#

128KB Memory Block (125)

128KB Memory Block (126)

128KB Memory Block (127)

CE Logic

Command

Execution

Logic

State

Y -

Decoder

Machine

Y - Select Gates

V

CC

Sense Amplifiers

Write/Erase-Bit

Compare and Verify

V

PP

STS

Switch/

Pump

VPEN

Status

Register

Identification

Register

Query

Output

Buffer

FUNCTIONALBLOCKDIAGRAM

(64Mb)

Input

Buffer

I/O

Control

Logic

128KB Memory Block (0)

Addr.

Buffer/

Latch

128KB Memory Block (1)

128KB Memory Block (2)

A0–A22

Addr.

Power

(Current)

Control

Write

Buffer

Counter

DQ0–DQ15

CE0

CE1

CE2

OE#

WE#

RP#

128KB Memory Block (61)

128KB Memory Block (62)

128KB Memory Block (63)

CE Logic

Command

Execution

Logic

State

Y -

Decoder

Machine

Y - Select Gates

V

CC

Sense Amplifiers

Write/Erase-Bit

Compare and Verify

V

PP

STS

Switch/

Pump

V^PEN

Status

Register

Identification

Register

Query

Output

Buffer

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

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4

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

FUNCTIONALBLOCKDIAGRAM

(32Mb)

Input

Buffer

I/O

Control

Logic

128KB Memory Block (0)

128KB Memory Block (1)

128KB Memory Block (2)

Addr.

Buffer/

Latch

A0–A21

Addr.

Power

(Current)

Control

Write

Buffer

Counter

DQ0–DQ15

CE0

CE1

CE2

OE#

WE#

RP#

128KB Memory Block (29)

128KB Memory Block (30)

128KB Memory Block (31)

CE Logic

Command

Execution

Logic

State

Y -

Decoder

Machine

Y - Select Gates

V

CC

Sense Amplifiers

Write/Erase-Bit

Compare and Verify

V^PP

Switch/

Pump

STS

VPEN

Status

Register

Identification

Register

Query

Output

Buffer

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

PIN/BALLDESCRIPTIONS

56-PIN TSOP 64-BALL FBGA

NUMBERS

SYMBOL TYPE

WE#

DESCRIPTION

55

G8

Input Write Enable: Determines if a given cycle is a WRITE

cycle. If WE# is LOW, the cycle is either a WRITE to the

command execution logic (CEL) or to the memory array.

Addresses and data are latched on the rising edge of the

WE# pulse.

14, 2, 29

B4, B8, H1

CE0, CE1, Input Chip Enable: Three CE pins enable the use of multiple

CE2

Flash devices in the system without requiring additional

logic. The device can be configured to use a single CE

signal by tying CE1 and CE2 to ground and then using

CE0 as CE. Device selection occurs with the first edge of

CE0, CE1, or CE2 (CEx) that enables the device. Device

deselection occurs with the first edge of CEx that

disables the device (see Table 2).

16

D4

F8

RP#

Input Reset/Power-Down: When LOW, RP# clears the status

register, sets the ISM to the array read mode, and places

the device in deep power-down mode. All inputs,

including CEx, are “Don’t Care,” and all outputs are

High-Z. RP# must be held at V^IHduring all other modes

of operation.

54

OE#

Input Output Enables: Enables data ouput buffers when LOW.

When OE# is HIGH, the output buffers are disabled.

32, 28, 27,

G2, A1, B1, C1, A0–A21/ Input Address inputs during READ and WRITE operations. A0 is

26, 25, 24, 23, D1, D2, A2, C2,

(A22)

(A23)

only used in x8 mode. A22 (pin 1, ball A8) is only

available on the 64Mb and 128Mb devices. A23 (pin 30,

ball G1) is only available on the 128Mb device.

22, 20, 19, 18,

17, 13, 12, 11,

A3, B3, C3, D3,

C4, A5, B5, C5,

10, 8, 7, 6, 5, 4, D7, D8, A7, B7,

3, 1, 30

C7, C8, A8, G1

31

F1

BYTE#

Input BYTE# LOW places the device in the x8 mode. BYTE#

HIGH places the device in the x16 mode and turns off

the A0 input buffer. Address A1 becomes the lowest

order address in x16 mode.

15

A4

VPEN

Input Necessary voltage for erasing blocks, programming data,

or configuring lock bits. Typically, VPEN is connected to

V

CC. When VPEN ≤ VPENLK, this pin enables hardware write

protect.

33, 35, 38, 40,

44, 46, 49, 51,

34, 36, 39, 41,

45, 47, 50, 52

F2, E2, G3, E4,

E5, G5, G6, H7,

E1, E3, F3, F4,

F5, H5, G7, E7

DQ0–

Input/ Data I/O: Data output pins during any READ operation

DQ15 Output or data input pins during a WRITE. DQ8–DQ15 are not

used in byte mode.

53

E8

STS

Output Status: Indicates the status of the ISM. When configured

in level mode, default mode it acts as an RY/BY# pin.

When configured in its pulse mode, it can pulse to

indicate program and/or erase completion. Tie STS to

VCCQ through a pull-up resistor.

(continued on next page)

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

PIN/BALLDESCRIPTIONS(continued)

56-PIN TSOP 64-BALL FBGA

NUMBERS

SYMBOL TYPE

DESCRIPTION

43

G4

VCCQ

Supply VCCQ controls the output voltages. To obtain output

voltage compatible with system data bus voltages,

connect VCCQ to the system supply voltage.

9, 37

21, 42, 48

56

H3, A6

B2, H4, H6

H8

VCC

VSS

NC

Supply Power Supply: 2.7V to 3.6V.

Supply Ground.

–

No Connect: These may be driven or left unconnected.

Pin 1 and ball A8 are NCs on the 32Mb device. Pin 30

and ball G1 are NCs on the 32Mb and 64Mb devices.

–

B6, C6, D5, D6,

E6, F6, F7, H2

DNU

–

Do Not Use: Must float to minimize noise.

128Mb, 64Mb, 32MbQ-FlashMemory

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

MEMORYARCHITECTURE

Table 2

Chip Enable Truth Table

The MT28F128J3, MT28F640J3, and MT28F320J3

memory array architecture is divided into one hun-

dred twenty-eight, sixty-four, or thirty-two 128KB

blocks, respectively (see Figure 1). The internal archi-

tecture allows greater flexibility when updating data

because individual code portions can be updated in-

dependently of the rest of the code.

CE2

VIL

VIH

V^IH

CE1

VIL

VIH

VIL

VIH

CE0

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

DEVICE

Enabled

Disabled

Enabled

Disabled

Figure 1

Memory Map

7FFFFFh

7F0000h

FFFFFFh

FE0000h

128KB Block

127

64K-Word Block

127

NOTE: For single-chip applications, CE2 and CE1 can be

3FFFFFh

3F0000h

7FFFFFh

7E0000h

128KB Block

63

31

64K-Word Block

63

31

connectedtoGND.

high-speed page buffer. A0–A2 select data in the page

buffer. Asynchronous page mode, with a page size of

four words or eight bytes, is supported with no addi-

tional commands required.

3FFFFFh

3E0000h

1FFFFFh

1F0000h

03FFFFh

020000h

01FFFFh

000000h

01FFFFh

010000h

00FFFFh

000000h

128KB Block

1

0

64K-Word Block

1

0

OUTPUTDISABLE

The device outputs are disabled with OE# at a logic

HIGH level (VIH). Output pins DQ0–DQ15 are placed in

High-Z.

A0–A23: 128Mb

A0–A22: 64Mb

A0–A21: 32Mb

A1–A23: 128Mb

A1–A22: 64Mb

A1–A21: 32Mb

Byte-Wide (x8) Mode

Word-Wide (x16) Mode

BUSOPERATION

STANDBY

All bus cycles to and from the Flash memory must

conform to the standard microprocessor bus cycles.

The local CPU reads and writes Flash memory in-

system.

CE0, CE1, and CE2 can disable the device (see

Table 2) and place it in standby mode, which substan-

tially reduces device power consumption. DQ0–DQ15

outputs are placed in High-Z, independent of OE#. If

deselected during block erase, program, or lock bit con-

figuration, the ISM continues functioning and consum-

ing active power until the operation completes.

READ

Information can be read from any block, query, iden-

tifier codes, or status register, regardless of the VPEN

voltage. The device automatically resets to read array

mode upon initial device power-up or after exit from

reset/power-down mode. To access other read mode

commands (READ ARRAY, READ QUERY, READ IDEN-

TIFIER CODES, or READ STATUS REGISTER), these

commands should be issued to the CUI. Six control

pins dictate the data flow in and out of the device: CE0,

CE1, CE2, OE#, WE#, and RP#. In system designs using

multiple Q-Flash devices, CE0, CE1, and CE2 (CEx)

select the memory device (see Table 2). To drive data

out of the device and onto the I/O bus, OE# must be

active and WE# must be inactive (V^IH).

RESET/POWER-DOWN

RP# puts the device into the reset/power-down

mode when set to VIL.

During read, RP# LOW deselects the memory, places

output drivers in High-Z, and turns off internal cir-

cuitry. RP# must be held LOW for a minimum of ^tPLPH.

^tRWH is required after return from reset mode until

initial memory access outputs are valid. After this wake-

up interval, normal operation is restored. The com-

mand execution logic (CEL) is reset to the read array

mode and the status register is set to 80h.

During block erase, program, or lock bit configura-

tion, RP# LOW aborts the operation. In default mode,

STS transitions LOW and remains LOW for a maximum

When reading information in read array mode, the

device defaults to asynchronous page mode, thus pro-

viding a high data transfer rate for memory subsystems.

In this state, data is internally read and stored in a

t

time of PLPH + PHRH, until the RESET operation is

complete. Any memory content changes are no longer

128Mb, 64Mb, 32MbQ-FlashMemory

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

valid; the data may be partially corrupted after a pro-

gram or partially changed after an erase or lock bit

configuration. After RP# goes to logic HIGH (VIH), and

Figure 2

Device Identifier Code Memory Map

t

after RS, another command can be written.

7FFFFFh

It is important to assert RP# during system reset.

After coming out of reset, the system expects to read

from the Flash memory. During block erase, program,

or lock bit configuration mode, automated Flash memo-

ries provide status information when accessed. When

a CPU reset occurs with no Flash memory reset, proper

initialization may not occur because the Flash memory

may be providing status information instead of array

data. Micron Flash memories allow proper initializa-

tion following a system reset through the use of the RP#

input. RP# should be controlled by the same RESET#

signal that resets the system CPU.

Block 127

Reserved for Future

Implementation

7F0003h

7F0002h

Block 127 Lock Configuration

Reserved for Future

Implementation

7F0000h

7EFFFFh

(Blocks 64 through 126)

3FFFFFh

Block 63

Reserved for Future

Implementation

3F0003h

3F0002h

Block 63 Lock Configuration

READQUERY

Reserved for Future

Implementation

The READ QUERY operation produces block status

information, CFI ID string, system interface informa-

tion, device geometry information, and extended query

information.

3F0000h

3EFFFFh

(Blocks 32 through 62)

Block 31

Reserved for Future

Implementation

READIDENTIFIERCODES

1F0003h

1F0002h

The READ IDENTIFIER CODES operation produces

the manufacturer code, device code, and the block lock

configuration codes for each block (see Figure 2). The

block lock configuration codes identify locked and un-

locked blocks.

Block 31 Lock Configuration

Reserved for Future

Implementation

1F0000h

1EFFFFh

(Blocks 2 through 30)

01FFFFh

Block 1

WRITE

Reserved for Future

Implementation

Writing commands to the CEL allows reading of de-

vice data, query, identifier codes, and reading and clear-

ing of the status register. In addition, when V^PEN= VPENH,

block erasure, program, and lock bit configuration can

also be performed.

010003h

010002h

Block 1 Lock Configuration

Reserved for Future

Implementation

010000h

00FFFFh

The BLOCK ERASE command requires suitable com-

mand data and an address within the block. The BYTE/

WORD PROGRAM command requires the command

and address of the location to be written to. The CLEAR

BLOCK LOCK BITS command requires the command

and any address within the device. SET BLOCK LOCK

BITS command requires the command and the block to

be locked. The CEL does not occupy an addressable

memory location. It is written to when the device is

enabled and WE# is LOW. The address and data needed

to execute a command are latched on the rising edge of

WE# or the first edge of CEx that disables the device

(see Table 2). Standard microprocessor write timings

are used.

Block 0

Reserved for Future

Implementation

000004h

000003h

000002h

000001h

000000h

Block 0 Lock Configuration

Device Code

Manufacturer Code

NOTE: When obtaining these identifier codes, A0 is not used

in either x8 or x16 modes. Data is always given on the

LOW byte in x16 mode (upper byte contains 00h).

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Table 3

Bus Operations

CE0, CE1,

CE2¹

STS DEFAULT

MODE

RP#

VIH

VIL

OE#²WE#²ADDRESS

VPEN

X

DQ³

DOUT

MODE

High-Z⁴

X

NOTES

Read Array

Output Disable

Standby

Enabled

Disabled

X

VIL

VIH

X

VIH

X

5, 6, 7

X

High-Z

X

Reset/Power-Down

Mode

X

High-Z⁴

Read Identifier Codes

VIH

Enabled

VIL

VIH

See

Figure 2

X

Note 8

Note 9

DOUT

High-Z⁴

Read Query

See

Table 7

Read Status (ISM off)

VIH

Enabled

VIL

VIH

X

Read Status (ISM on)

DQ7

DOUT

DQ15–DQ8

DQ6–DQ0

High-Z

Write

VIH

Enabled

VIH

VIL

X

VPENH

DIN

X

7, 10, 11

NOTE: 1. See Table 2 for valid CE configurations.

2. OE# and WE# should never be enabled simultaneously.

3. DQ refers to DQ0–DQ7 if BYTE# is LOW and DQ0–DQ15 if BYTE# is HIGH.

4. High-Z is V^OHwith an external pull-up resistor.

5. Refer to DC Characteristics. When VPEN ≤ VPENLK, memory contents can be read, but not altered.

6. X can be V^ILor VIH for control and address pins, and VPENLK or VPENH for VPEN. See DC Characteristics for VPENLK and

VPENH voltages.

7. In default mode, STS is V^OLwhen the ISM is executing internal block erase, program, or lock bit configuration

algorithms. It is VOH when the ISM is not busy, in block erase suspend mode (with programming inactive), program

suspendmode,orreset/power-downmode.

8. See Read Identifier Codes section for read identifier code data.

9. See Read Query Mode Command section for read query data.

10. Command writes involving block erase, program, or lock bit configuration are reliably executed when V^PEN= VPENH and

VCC is within specification.

11. Refer to Table 4 for valid D^INduring a WRITE operation.

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Q-FLASH MEMORY

COMMANDDEFINITIONS

When the VPEN voltage is less than VPPLK, only READ

operations from the status register, query, identifier

codes, or blocks are enabled. Placing V^PENHon VPEN en-

ables BLOCK ERASE, PROGRAM, and LOCK BIT CON-

FIGURATION operations. Device operations are se-

lected by writing specific commands into the CEL, as

seen in Table 4.

Table 4

Micron Q-Flash Memory Command Set Definitions

1

COMMAND

SCALABLE

OR BASIC CYCLES

BUS

FIRST BUS CYCLE

SECOND BUS CYCLE

COMMAND REQ’D

2

3

4

5, 6

3

4

5, 6

SET

OPER

ADDR DATA

OPER

ADDR DATA

NOTES*

READ ARRAY

SCS/BCS

1

WRITE

X

FFh

READ IDENTIFIER

CODES

ꢀ 2

90h

READ

IA

ID

7

READ QUERY

SCS

ꢀ 2

WRITE

X

98h

70h

READ

QA

X

QD

READ STATUS

REGISTER

SCS/BCS

2

SRD

8

CLEAR STATUS

REGISTER

SCS/BCS

1

WRITE

X

50h

E8h

WRITE TO BUFFER

SCS/BCS

> 2

2

WRITE

BA

X

WRITE

BA

PA

N

9, 10, 11

12, 13

WORD/BYTE

PROGRAM

40h

or

PD

10h

BLOCK ERASE

SCS/BCS

2

1

WRITE

BA

X

20h

B0h

WRITE

BA

D0h

11, 12

12, 14

BLOCK ERASE,

PROGRAM SUSPEND

BLOCK ERASE,

SCS/BCS

1

WRITE

X

D0h

12

PROGRAM RESUME

CONFIGURATION

SCS

2

WRITE

X

B8h

60h

WRITE

X

BA

X

CC

01h

D0h

SET BLOCK LOCK BITS

CLEAR BLOCK

LOCK BITS

15

PROTECTION

PROGRAM

2

WRITE

X

C0h

WRITE

PA

PD

*Notes appear on the next page.

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Q-FLASH MEMORY

NOTE: 1. Commands other than those shown in Table 4 are reserved for future device implementations and should not be used.

2. The SCS is also referred to as the extended command set.

3. Bus operations are defined in Table 3.

4.

X = Any valid address within the device

BA= Address within the block

IA = Identifier code address; see Figure 2 and Table 15

QA= Query data base address

PA= Address of memory location to be programmed

ID = Data read from identifier codes

5.

QD= Data read from query data base

SRD= Data read from status register; see Table 16 for a description of the status register bits

PD= Data to be programmed at location PA; data is latched on the rising edge of WE#

CC= Configurationcode

6. The upper byte of the data bus (DQ8–DQ15) during command WRITEs is a “Don’t Care” in x16 operation.

7. Following the READ IDENTIFIER CODES command, READ operations access manufacturer, device, and block lock codes.

See Block Status Register section for read identifier code data.

8. If the ISM is running, only DQ7 is valid; DQ15–DQ8 and DQ6–DQ0 float, which places them in High-Z.

9. After the WRITE-to-BUFFER command is issued, check the XSR to make sure a buffer is available for writing.

10. The number of bytes/words to be written to the write buffer = n + 1, where n = byte/word count argument. Count

ranges on this device for byte mode are n = 00h to n = 1Fh and for word mode, n = 0000h to n = 000Fh. The third and

consecutive bus cycles, as determined by n, are for writing data into the write buffer. The CONFIRM command (D0h) is

expected after exactly n + 1 WRITE cycles; any other command at that point in the sequence aborts the WRITE-to-

BUFFER operation. Please see Figure 4, WRITE-to-BUFFER Flowchart, for additional information.

11. The WRITE-to-BUFFER or ERASE operation does not begin until a CONFIRM command (D0h) is issued.

12. Attempts to issue a block erase or program to a locked block while RP# = V^IHwill fail.

13. Either 40h or 10h is recognized by the ISM as the byte/word program setup.

14. Program suspend can be issued after either the WRITE-to-BUFFER or WORD/BYTE PROGRAM operation is initiated.

15. The CLEAR BLOCK LOCK BITS operation simultaneously clears all block lock bits.

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Q-FLASH MEMORY

READARRAYCOMMAND

QUERYSTRUCTUREOUTPUT

The device defaults to read array mode upon initial

device power-up and after exiting reset/power-down

mode. The read configuration register defaults to asyn-

chronous read page mode. Until another command is

written, the READ ARRAY command also causes the

device to enter read array mode. When the ISM has

started a block erase, program, or lock bit configura-

tion, the device does not recognize the READ ARRAY

command until the ISM completes its operation, un-

less the ISM is suspended via an ERASE or PROGRAM

SUSPEND command. The READ ARRAY command

functions independently of the V^PENvoltage.

The query “data base” enables system software to

obtain information about controlling the Flash compo-

nent. The device’s CFI-compliant interface allows the

host system to access query data. Query data are al-

ways located on the lowest-order data outputs (DQ0–

DQ7) only. The numerical offset value is the address

relative to the maximum bus width supported by the

device. On this family of devices, the query table de-

vice starting address is a 10h, which is a word address

for x16 devices.

For a x16 organization, the first two bytes of the

query structure, “Q” and “R” in ASCII, appear on the

low byte at word addresses 10h and 11h. This CFI-

compliant device outputs 00h data on upper bytes,

thus making the device output ASCII “Q” on the LOW

byte (DQ7–DQ0) and 00h on the HIGH byte (DQ15–

DQ8). At query addresses containing two or more bytes

of information, the least significant data byte is located

at the lower address, and the most significant data

byte is located at the higher address. This is summa-

rized in Table 5. A more detailed example is provided in

Table 6.

READQUERYMODECOMMAND

This section is related to the definition of the data

structure or “data base” returned by the CFI QUERY

command. System software should retain this struc-

ture to gain critical information such as block size,

density, x8/x16, and electrical specifications. When

this information has been obtained, the software

knows which command sets to use to enable Flash

writes or block erases, and otherwise control the Flash

component.

Table 5

Summary of Query Structure Output as a Function of Device and Mode

QUERY DATA WITH

MAXIMUM DEVICE BUS

WIDTH ADDRESSING

QUERY DATA WITH BYTE

ADDRESSING

DEVICE

QUERY START LOCATION IN

TYPE/

MODE

MAXIMUM DEVICE BUS

WIDTH ADDRESSES

HEX

OFFSET

HEX

CODE

ASCII

VALUE

HEX

OFFSET

HEX

CODE

ASCII

VALUE

x16 device

x16 mode

10h

10

11

12

0051

0052

0059

Q

R

Y

20

21

22

51

00

52

Q

Null

R

x16 device

x8 mode

20

21

22

51

52

Q

R

N/A¹

NOTE: 1. The system must drive the lowest-order addresses to access all the device’s array data when the device is configured in

x8 mode. Therefore, word addressing where these lower addresses are not toggled by the system is “Not Applicable”

for x8-configured devices.

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Q-FLASH MEMORY

QUERYSTRUCTUREOVERVIEW

The QUERY command makes the Flash component

display the CFI query structure or data base. The struc-

ture subsections and address locations are outlined in

Table 7.

Table 6

Example of Query Structure Output of a x16- and x8-Capable Device

WORD ADDRESSING

HEX CODE

BYTE ADDRESSING

HEX CODE

OFFSET

A16–A1

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

...

VALUE

OFFSET

A7–A0

20h

VALUE

DQ15–DQ0

DQ7–DQ0

0051

0052

Q

R

51

Q

21h

Q

0059

Y

22h

52

R

P_ID LO

P_ID HI

P LO

PrVendor

ID #

23h

52

R

24h

59

Y

PrVendor

TblAdr

AltVendor

ID #

25h

59

P HI

26h

P_ID LO

P_ID HI

...

PrVendor

ID #

A_ID LO

A_ID HI

...

27h

28h

...

Table 7

Query Structure

1

OFFSET

SUBSECTION NAME

DESCRIPTION

00h

Manufacturer compatibility code

Device code

01h

(BA+2)h²

04–0Fh

10h

Block Status Register

Block-specific information

Reserved

Reserved for vendor-specific information

Command set ID and vendor data offset

Flash device layout

CFI Query Identification String

System Interface Information

Device Geometry Definition

Primary Extended Query Table

1Bh

27h

P³

Vendor-defined additional information specific to the

primary vendor algorithm

NOTE: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function

of device bus width and mode.

2. BA = Block address beginning location (i.e., 020000h is block two’s beginning location when the block size is 64K-word).

3. Offset 15 defines “P,” which points to the Primary Extended Query Table.

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Q-FLASH MEMORY

CFIQUERYIDENTIFICATIONSTRING

The CFI query identification string verifies whether

the component supports the CFI specification. Addi-

tionally, it indicates the specification version and sup-

ported vendor-specified command set(s).

Table 8

Block Status Register

OFFSET LENGTH DESCRIPTION

(BA+2)h¹

Block Lock Status Register

ADDRESS¹

VALUE

1

(BA+2)h

00 or 01

BSR0 Block Lock Status

0 = Unlocked

1 = Locked

(BA+2)h

(bit 0) 0 or 1

(bit 2–7) 0

BSR1–7 Reserved for Future Use

NOTE: 1. BA = The beginning location of a block address (i.e., 010000h is block one’s (64K-word) beginning location in word

mode).

Table 9

CFIIdentification

OFFSET LENGTH

DESCRIPTION

ADDRESS

HEX

CODE

VALUE

10h

3

Query-unique ASCII string “QRY”

10h

11h

12h

51

52

59

Q

R

Y

13h

15h

17h

2

Primary vendor command set and control interface ID

code. 16-bit ID code for vendor-specified algorithms

13h

14h

01

00

Extended query table primary algorithm address

15h

16h

31

00

Alternate vendor command set and control interface ID

code; 0000h means no second vendor-specified

algorithm exists

17h

18h

00

19h

2

Secondary algorithm extended query table address;

0000h means none exists

19h

1Ah

00

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SYSTEMINTERFACEINFORMATION

Table 10 provides useful information about opti-

mizing system interface software.

Table10

System Interface Information

OFFSET LENGTH DESCRIPTION

ADDRESS

1Bh

HEX

CODE

VALUE

2.7V

1Bh

1Ch

1Dh

1

V^CClogic supply minimum program/erase voltage

Bits 0–3 BCD 100mV

Bits 4–7 BCD volts

27

36

V^CClogic supply maximum program/erase voltage

Bits 0–3 BCD 100mV

Bits 4–7 BCD volts

1Ch

3.6V

VPP [programming] supply minimum program/erase

voltage

Bits 0–3 BCD 100mV

Bits 4–7 Hex volts

1Dh

00

0.0V

1Eh

1Fh

1

VPP [programming] supply maximum program/erase

voltage

Bits 0–3 BCD 100mV

Bits 4–7 Hex volts

1Eh

1Fh

00

07

0.0V

“n” such that typical single word program

timeout = 2ⁿµs

128µs

20h

21h

22h

23h

1

“n” such that typical max. buffer write timeout = 2ⁿµs

“n” such that typical block erase timeout = 2ⁿms

“n” such that typical full chip erase timeout = 2ⁿms

“n” such that maximum word program timeout = 2ⁿ

times typical

20h

21h

22h

23h

07

0A

00

04

128µs

1s

N/A

2ms

24h

25h

26h

1

“n” such that maximum buffer write timeout = 2ⁿ

times typical

“n” such that maximum block erase timeout = 2ⁿ

times typical

“n” such that maximum chip erase timeout = 2ⁿ

times typical

24h

25h

26h

04

00

2ms

16s

N/A

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Q-FLASH MEMORY

DEVICEGEOMETRYDEFINITION

Tables 11a and 11b provide important details about

the device geometry.

Table 11a

Device Geometry Definitions

OFFSET LENGTH

DESCRIPTION

CODE

(see table below)

27h

28h

1

2

“n” such that device size = 2ⁿin number of bytes

27h

Flash device interface: x8 async, x16 async, x8/x16 async;

28:00 29:00, 28:01 29:00, 28:02 29:00

28h

29h

02

00

x8/x16

2Ah

2Ch

2

1

“n” such that maximum number of bytes in write

buffer = 2ⁿ

2Ah

2Bh

05

00

32

1

Number of erase block regions within device:

1. x = 0 means no erase blocking; the device erases in “bulk”

2. x specifies the number of device or partition regions

with one or more contiguous same-size erase blocks

3. Symmetrically blocked partitions have one blocking

region

2Ch

01

4. Partition size = (total blocks) x (individual block size)

2Dh

4

Erase Block Region 1 Information

Bits 0–15 = y; y + 1 = number of identical-size erase blocks

Bits 16–31 = z; region erase block(s) size are z x 256 bytes

2Dh

2Eh

2Fh

30h

Table 11b

Device Geometry Definition Codes

ADDRESS

27h

32Mb

16

64Mb

17

128Mb

18

28h

02

29h

00

2Ah

2Bh

05

00

05

00

05

00

2Ch

01

2Dh

2Eh

1F

00

3F

00

7F

00

2Fh

00

30h

02

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Q-FLASH MEMORY

PRIMARYVENDOR-SPECIFICEXTENDED

QUERYTABLE

Table 12 includes information about optional

Flash features and commands and other similar infor-

mation.

Table12

Primary Vendor-Specific Extended Query

OFFSET¹DESCRIPTION

P = 31h (OPTIONAL FLASH FEATURES AND COMMANDS)

ADDRESS

HEX

CODE

VALUE

(P+0)h

(P+1)h

(P+2)h

Primary extended query table

Unique ASCII string, PRI

31h

32h

33h

50

52

49

P

R

I

(P+3)h

(P+4)h

Major version number, ASCII

Minor version number, ASCII

34h

35h

31

1

(P+5)h

(P+6)h

(P+7)h

(P+8)h

Optional feature and command support (1 = yes, 0 = no) bits 9–31

are reserved; undefined bits are “0.” If bit 31 is “1,” then another

31-bit field of optional features follows at the end of the bit 30

field.

36h

37h

38h

39h

0A

00

0

Bit 0 Chip erase supported = no = 0

Bit 1 Suspend erase supported = yes = 1

Bit 2 Suspend program supported = yes = 1

Bit 3 Legacy lock/unlock supported = yes = 1¹

Bit 4 Queued erase supported = no = 0

Bit 5 Instant Individual block locking supported = no = 0

Bit 6 Protection bits supported = yes = 1

Bit 7 Page mode read supported = yes = 1

Bit 8 Synchronous read supported = no = 0

(P+9)h

Supported functions after suspend: read array, status, query

Other supported operations:

3Ah

01

Bits 1–7 Reserved; undefined bits are “0”

Bit 0 Program supported after erase suspend = yes = 1

(P+A)h

(P+B)h

Block status register mask

3Bh

3Ch

01

00

Bits 2–15 Reserved; undefined bits are “0”

Bit 0 Block lock bit status register active = yes = 1

Bit 1 Block lock down bit status active = no = 0

(P+C)h

(P+D)h

VCC logic supply highest-performance program/erase voltage

Bits 0–3 BCD value in 100mV

Bits 4–7 BCD value in volts

3Dh

3Eh

33

00

3.3V

0.0V

V^PPoptimum program/erase supply voltage

Bits 0–3 BCD value in 100mV

Bits 4–7 Hex value in volts

NOTE: 1. Future devices may not support the described “Legacy Lock/Unlock” function. On these devices, bit 3 would have a

value of “0.”

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Q-FLASH MEMORY

Table13

Protection Register Information

OFFSET¹DESCRIPTION

P = 31h (OPTIONAL FLASH FEATURES AND COMMANDS)

ADDRESS

3Fh

HEX

01

VALUE

CODE

(P+E)h

Number of protection register fields in JEDEC ID space. “00h”

indicates that 256 protection bytes are available.

01

(P+F)h

Protection Field 1: Protection Description

40h

00

00h

(P+10)h This field describes user-available, one-time programmable (OTP)

(P+11)h protection register bytes. Some are preprogrammed with device-

(P+12)h unique serial numbers; others are user-programmable. Bits 0–15

point to the protection register lock byte, the section’s first byte.

The following bytes are factory-preprogrammed and user-

programmable.

Bits 0–7 Lock/bytes JEDEC-plane physical low address

Bits 8–15 Lock/bytes JEDEC-plane physical high address

Bits 16–23 “n” such that 2ⁿ= factory preprogrammed bytes

Bits 24–31 “n” such that 2ⁿ= user-programmable bytes

Table14

Burst Read Information

OFFSET¹DESCRIPTION

P = 31h (OPTIONAL FLASH FEATURES AND COMMANDS)

ADDRESS

HEX

VALUE

CODE

(P+13)h Page Mode Read Capability

44h

03

8 byte

Bits 0–7 = “n” such that 2ⁿHex value represents the number of

read page bytes. See offset 28h for device word width to determine

page mode data output width. 00h indicates no read page buffer.

(P+14)h Number of synchronous mode read configuration fields

that follow. 00h indicates no burst capability.

45h

46h

00

(P+15)h Reserved for future use.

NOTE: 1. The variable “P” is a pointer which is defined at CFI offset 15h.

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Q-FLASH MEMORY

READIDENTIFIERCODESCOMMAND

Writing the READ IDENTIFIER CODES command

initiates the IDENTIFIER CODE operation. Following

the writing of the command, READ cycles from ad-

dresses shown in Figure 2 retrieve the manufacturer,

device, and block lock configuration codes (see Table

15 for identifier code values). Page mode READs are

not supported in this read mode. To terminate the op-

eration, write another valid command. The READ

IDENTIFIER CODES command functions indepen-

dently of the V^PENvoltage. This command is valid only

when the ISM is off or the device is suspended. See

Table 15 for read identifier codes.

erasure, or lock bit configuration. After writing this com-

mand, all subsequent READ operations output data

from the status register until another valid command is

written. Page mode READs are not supported in this

read mode. The status register contents are latched on

the falling edge of OE# or the first edge of CEx that

enables the device (see Table 2). To update the status

register latch, OE# must toggle to V^IHor the device must

be disabled before further READs. The READ STATUS

REGISTER command functions independently of the

V^PENvoltage. During a program, block erase, set block

lock bits, or clear block lock bits command sequence,

only SR7 is valid until the ISM completes or suspends

the operation. Device I/O pins DQ0–DQ6 and DQ8–

DQ15 are placed in High-Z. When the operation com-

pletes or suspends (check status register bit 7), all con-

tents of the status register are valid during a READ.

READSTATUSREGISTERCOMMAND

The status register may be read at any time by writ-

ing the READ STATUS REGISTER command to deter-

mine the successful completion of programming, block

Table15

Identifier Codes

CODE

ADDRESS¹

DATA

Manufacturer Compatibility Code

00000h

(00) 89

Device Code

• 32Mb

00001h

(00) 16

(00) 17

(00) 18

• 64Mb

• 128Mb

Block Lock Configuration

• Block is Unlocked

X0002h²

DQ0 = 0

DQ0 = 1

DQ1–DQ7

• Block is Locked

• Reserved for Future Use

NOTE: 1. A0 is not used in either x8 or x16 modes when obtaining the identifier

codes. The lowest-order address line is A1. Data is always presented on the

low byte in x16 mode (upper byte contains 00h).

2. X selects the specific block’s lock configuration code. See Figure 2 for the

device identifier code memory map.

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Table16

Status Register Definitions

ISMS

ESS

ECLBS

PSLBS

VPENS

PSS

DPS

R

7

6

5

4

3

2

1

0

HIGH-Z

WHEN

BUSY?

STATUS REGISTER BITS

NOTES

No

SR7 = WRITE STATE MACHINE STATUS (ISMS)

Check STS or SR7 to determine block

erase, program, or lock bit

configuration completion. SR6–SR0 are

not driven while SR7 = 0.

1 = Ready

0 = Busy

Yes

SR6 = ERASE SUSPEND STATUS (ESS)

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

SR5 = ERASE AND CLEAR LOCK BITS STATUS (ECLBS) If both SR5 and SR4 are “1s” after a

1 = Error in Block Erasure or Clear Lock Bits

0 = Successful Block Erase or Clear Lock Bits

block erase or lock bit configuration

attempt, an improper command

sequence was entered.

Yes

SR4 = PROGRAM AND SET LOCK BIT STATUS (PSLBS)

1 = Error in Programming or Setting Block Lock Bits

0 = Successful Program or Set Block Lock Bits

SR3 = PROGRAMMING VOLTAGE STATUS (VPENS)

1 = Low Programming Voltage Detected,

Operation Aborted

SR3 does not provide a continuous

programming voltage level indication.

The ISM interrogates and indicates the

programming voltage level only after

block erase, program, set block lock

bits, or clear block lock bits command

sequences.

0 = Programming Voltage OK

Yes

SR2 = PROGRAM SUSPEND STATUS (PSS)

1 = Program Suspended

0 = Program in Progress/Completed

SR1 = DEVICE PROTECT STATUS (DPS)

1 = Block Lock Bit Detected, Operation Aborted

0 = Unlock

SR1 does not provide a continuous

indication of block lock bit values. The

ISM interrogates the block lock bits

only after block erase, program, or lock

bit configuration command sequences.

It informs the system, depending on

the attempted operation, if the block

lock bit is set. Read the block lock

configuration codes using the READ

IDENTIFIER CODES command to

determine block lock bit status. SR0 is

reserved for future use and should be

masked when polling the status

register.

Yes

SR0 = RESERVED FOR FUTURE ENHANCEMENTS

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Table17

Extended Status Register Definitions (XSR)

WBS

7

RESERVED

6–0

HIGH-Z

WHEN

BUSY?

STATUS REGISTER BITS

NOTES

No

XSR7 = WRITE BUFFER STATUS (WBS)

1 = Write Buffer Available

After a BUFFER WRITE command,

XSR7 = 1 indicates that a write buffer is

available.

0 = Write Buffer Not Available

Yes

XSR6–XSR0 = RESERVED FOR FUTURE

ENHANCEMENTS

SR6–SR0 are reserved for future use

and should be masked when polling

the status register.

CLEARSTATUSREGISTERCOMMAND

The ISM sets the status register bits SR5, SR4, SR3,

and SR1 to “1s.” These bits, which indicate various

failure conditions, can only be reset by the CLEAR STA-

TUS REGISTER command. Allowing system software to

reset these bits can perform several operations (such

as cumulatively erasing or locking multiple blocks or

writing several bytes in sequence). To determine if an

error occurred during the sequence, the status register

may be polled. To clear the status register, the CLEAR

STATUS REGISTER command (50h) is written. The

CLEAR STATUS REGISTER command functions inde-

pendently of the applied V^PENvoltage and is only valid

when the ISM is off or the device is suspended.

results in status register bits SR4 and SR5 being set to

“1.” Also, reliable block erasure can only occur when

VCC is valid and VPEN = VPENH. Note that SR3 and SR5 are

set to “1” if block erase is attempted while VPEN ≤ VPENLK.

Successful block erase requires that the corresponding

block lock bit be cleared. Similarly, SR1 and SR5 are set

to “1” if block erase is attempted when the correspond-

ing block lock bit is set.

BLOCKERASESUSPENDCOMMAND

The BLOCK ERASE SUSPEND command allows

block erase interruption in order to read or program

data in another block of memory. Writing the BLOCK

ERASE SUSPEND command immediately after start-

ing the block erase process requests that the ISM sus-

pend the block erase sequence at an appropriate point

in the algorithm. When reading after the BLOCK ERASE

SUSPEND command is written, the device outputs sta-

tus register data. Polling status register bit SR7, fol-

lowed by SR6, shows when the BLOCK ERASE opera-

tion has been suspended. In the default mode, STS

also transitions to VOH. ^tLES defines the block erase

suspend latency. At this point, a READ ARRAY com-

mand can be written to read data from blocks other

than that which is suspended. During erase suspend

to program data in other blocks, a program command

sequence can also be issued. During a PROGRAM op-

eration with block erase suspended, status register bit

SR7 returns to “0” and STS output (in default mode)

transitions to VOL. However, SR6 remains “1” to indicate

block erase suspend status. Using the PROGRAM SUS-

PEND command, a PROGRAM operation can also be

suspended. Resuming a suspended programming op-

eration by issuing the PROGRAM RESUME command

BLOCKERASECOMMAND

The BLOCK ERASE command is a two-cycle com-

mand that erases one block. First, a block erase setup is

written, followed by a block erase confirm. This com-

mand sequence requires an appropriate address within

the block to be erased. The ISM handles all block pre-

conditioning, erase, and verify. Time ^tWB after the two-

cycle block erase sequence is written, the device auto-

matically outputs status register data when read. The

CPU can detect block erase completion by analyzing

the output of the STS pin or status register bit SR7.

Toggle OE# or CEx to update the status register. Upon

block erase completion, status register bit SR5 should

be checked to detect any block erase error. When an

error is detected, the status register should be cleared

before system software attempts corrective actions.

The CEL remains in read status register mode until a

new command is issued. This two-step setup command

sequence ensures that block contents are not acciden-

tally erased. An invalid block erase command sequence

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Q-FLASH MEMORY

enables the suspended programming operation to con-

tinue. To resume the suspended erase, the user must

wait for the programming operation to complete be-

fore issuing the BLOCK ERASE RESUME command.

While block erase is suspended, the only other valid

commands are READ QUERY, READ STATUS REGIS-

TER, CLEAR STATUS REGISTER, CONFIGURE, and

BLOCK ERASE RESUME. After a BLOCK ERASE RESUME

command to the Flash memory is completed, the ISM

continues the block erase process. Status register bits

SR6 and SR7 automatically clear and STS (in default

mode) returns to V^OL. After the ERASE RESUME com-

mand is completed, the device automatically outputs

status register data when read. V^PENmust remain at

V^PENH(the same VPEN level used for block erase) during

block erase suspension. Block erase cannot resume

during block erase suspend until PROGRAM opera-

tions are complete.

If an error occurs during a WRITE, the device stops

writing, and status register bit SR4 is set to a “1” to

indicate a program failure. The ISM only detects errors

for “1s” that do not successfully program to “0s.” When

a program error is detected, the status register should

be cleared. Note that the device does not accept any

more WRITE-to-BUFFER commands any time SR4 and/

or SR5 is set. In addition, if the user attempts to pro-

gram past an erase block boundary with a WRITE-to-

BUFFER command, the device aborts the WRITE-to-

BUFFER operation and generates an invalid command/

sequence error, and status register bits SR5 and SR4

are set to “1.”

Reliable BUFFERED WRITEs can only occur when

V^PEN= VPENH. If a BUFFERED WRITE is attempted while

V^PEN≤ VPENLK, status register bits SR4 and SR3 are set to

“1.” Buffered write attempts with invalid VCC and VPEN

voltages produce spurious results and should not be

attempted. Finally, the corresponding block lock bit

should be reset for successful programming. When a

BUFFERED WRITE is attempted while the correspond-

ing block lock bit is set, SR1 and SR4 are set to “1.”

WRITE-TO-BUFFERCOMMAND

The write-to-buffer command sequence is initiated

to program the Flash device via the write buffer. A buffer

can be loaded with a variable number of bytes, up to

the buffer size, before writing to the Flash device. First,

the WRITE-to-BUFFER SETUP command is issued,

along with the block address (see Figure 4). Then, the

extended status register (XSR; see Table 17) informa-

tion is loaded and XSR7 indicates “buffer available”

status. If XSR7 = 0, the write buffer is not available. To

retry, issue the WRITE-to-BUFFER SETUP command

with the block address and continue monitoring XSR7

until XSR7 = 1. When XSR7 transitions to “1,” the buffer

is ready for loading new data. Then the part is given a

word/byte count with the block address. On the next

write, a device start address is given, along with the

write buffer data. Depending on the count, subsequent

writes provide additional device addresses and data.

All subsequent addresses must lie within the start ad-

dress plus the count.

BYTE/WORDPROGRAMCOMMANDS

A two-cycle command sequence executes a byte/

word program setup. This program setup (standard

40h or alternate 10h) is written, followed by a second

write that specifies the address and data (latched on

the rising edge of WE#). Next, the ISM takes over to

internally control the programming and program verify

algorithms. When the program sequence is written,

the device automatically outputs status register data

when read (see Figure 5). The CPU can detect the

completion of the program event by analyzing the STS

pin or status register bit SR7.

Upon program completion, status register bit SR4

should be checked. The status register should be

cleared if a program error is detected. The ISM only

detects errors for “1s” that do not successfully program

to “0s.” The CEL remains in read status register mode

until it receives another command.

The device internally programs many Flash cells in

parallel. Due to this parallel programming, maximum

programming performance and lower power are ob-

tained by aligning the start address at the beginning of

a write buffer boundary (i.e., A0–A4 of the start address

= 0).

When the final buffer data is given, a WRITE CON-

FIRM command is issued, thus programming the ISM

to begin copying the buffer data to the Flash array. If

the device receives a command other than WRITE CON-

FIRM, an invalid command/sequence error is gener-

ated and status register bits SR5 and SR4 are set to “1.”

For additional BUFFER WRITEs, issue another WRITE-

to-BUFFER SETUP command and check XSR7.

Reliable byte/word programs can only occur when

V^CCand VPEN are valid. Status register bits SR4 and SR3

are set to “1” if a byte/word program is attempted while

VPEN ≤ VPENLK. The corresponding block lock bit should

be cleared for successful byte/word programs. If BYTE/

WORD is attempted while the corresponding block lock

bit is set, SR1 and SR4 are set to “1.”

PROGRAMSUSPENDCOMMAND

The PROGRAM SUSPEND command enables pro-

gram interruption to read data in other Flash memory

locations. After starting the programming process, writ-

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Q-FLASH MEMORY

ing the PROGRAM SUSPEND command requests that

the ISM suspend the program sequence at a predeter-

mined point in the algorithm. When the PROGRAM

SUSPEND command is written, the device continues

to output status register data when read. Polling status

register bit SR7 can determine when the programming

operation has been suspended. When SR7 = 1, SR2 is

also set to “1” to indicate that the device is in the pro-

gram suspend mode. STS in RY/BY# level mode also

READ CONFIGURATION

Micron’s Q-Flash devices support both asynchro-

nous page mode and standard word/byte READs with-

out configuration requirement. Status register and

identifier only support standard word/byte single

READ operations.

STSCONFIGURATIONCOMMAND

Using the CONFIGURATION command, the STS pin

can be configured to different states. Once configured,

the STS pin remains in that configuration until another

configuration command is issued, RP# is asserted LOW,

or the device is powered down. Initially, the STS pin

defaults to RY/BY# operation where RY/BY# goes LOW

to indicate that the state machine is busy. When HIGH,

RY/BY# indicates that either the state machine is ready

for a new operation or it is suspended. Table 18, Con-

figuration Coding Definitions, shows the possible STS

configurations. To change the STS pin to other modes,

the CONFIGURATION command is given, followed by

the desired configuration code. The three alternate

configurations are all pulse modes and may be used as

a system interrupt. With these configurations, bit 0

controls erase complete interrupt pulse, and bit 1 con-

trols program complete interrupt pulse. Providing the

00h configuration code with the CONFIGURATION

command resets the STS pin to the default RY/BY#

level mode. Table 18 describes possible configurations

and usage. The CONFIGURATION command can only

be given when the device is not busy or suspended.

When configured in one of the pulse modes, the STS

pin pulses LOW with a typical pulse width of 250ns.

Check SR7 for device status. An invalid configuration

code results in status register bits SR4 and SR5 being

set to “1.”

t

transitions to V^OH. Note that LPS defines the program

suspend latency.

Hence, a READ ARRAY command can be written to

read data from unsuspended locations. While pro-

gramming is suspended, the only other valid com-

mands are READ QUERY, READ STATUS REGISTER,

CLEAR STATUS REGISTER, CONFIGURE, and

PROGRAM RESUME. When the PROGRAM RESUME

command is written, the ISM continues the program-

ming process. Status register bits SR2 and SR7 auto-

matically clear and STS in RY/BY# mode returns to V^OL.

After the PROGRAM RESUME command is written, the

device automatically outputs status register data when

read. V^PENmust remain at VPENH and VCC must remain at

valid VCC levels (the same VPEN and VCC levels used for

programming) while in program suspend mode. Refer

to Figure 6 (PROGRAM SUSPEND/RESUME Flowchart).

SETREADCONFIGURATIONCOMMAND

Q-Flash memory does not support the SET READ

CONFIGURATION command. The devices default to

the asynchronous page mode. If this command is given,

the operation of the device will not be affected.

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Q-FLASH MEMORY

Table18

1

Configuration Coding Definitions

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

PULSE ON PULSE ON

PROGRAM ERASE

COMPLETE²COMPLETE²

DQ0

RESERVED

DQ1–DQ0 = STS Configuration Codes

NOTES

00 = Default, RY/BY# level mode

(device ready) indication

Used to control HOLD to a memory controller to prevent accessing

a Flash memory subsystem while any Flash device’s ISM is busy.

01 = Pulse on Erase Complete

Used to generate a system interrupt pulse when any Flash device in

an array has completed a BLOCK ERASE or sequence of queued

BLOCK ERASEs; helpful for reformatting blocks after file system free

space reclamation or “cleanup.”

10 = Pulse on Program Complete

Used to generate a system interrupt pulse when any Flash device in

an array has completed a PROGRAM operation. Provides highest

performance for enabling continuous BUFFER WRITE operations.

11 = Pulse on Erase or Program

Complete

Used to generate system interrupts to trigger enabling of Flash

arrays when either ERASE or PROGRAM operations are completed

and a common interrupt service routine is desired.

NOTE: 1. An invalid configuration code will result in both SR4 and SR5 being set.

2. When the device is configured in one of the pulse modes, the STS pin pulses LOW with a typical pulse width of 250ns.

SET BLOCK LOCK BITS COMMAND

A flexible block locking and unlocking scheme is

enabled via a combination of block lock bits. The block

lock bits gate PROGRAM and ERASE operations. Using

the SET BLOCK LOCK BITS command, individual block

lock bits can be set. This command is invalid when the

ISM is running or when the device is suspended. SET

BLOCK LOCK BITS commands are executed by a two-

cycle sequence. The set block lock bits setup, along

with appropriate block address, is followed by the set

block lock bits confirm and an address within the block

to be locked. The ISM then controls the set lock bit

algorithm. When the sequence is written, the device

automatically outputs status register data when read

(see Figure 9). The CPU can detect the completion of

the set block lock bit event by analyzing the STS pin

output or status register bit SR7. Upon completion of

set block lock bits operation, status register bit SR4

should be checked for error. If an error is detected, the

status register should be cleared. The CEL remains in

read status register mode until a new command is is-

sued. This two-step sequence of setup followed by ex-

ecution ensures that lock bits are not accidentally set.

An invalid SET BLOCK LOCK BITS command results in

status register bits SR4 and SR5 being set to “1.” Also,

reliable operation occurs only when V^CCand VPEN are

valid. When VPEN ≤ VPENLK, lock bit contents are protected

against any data change.

CLEAR BLOCK LOCK BITS COMMAND

The CLEAR BLOCK LOCK BITS command can clear

all set block lock bits in parallel. This command is in-

valid when the ISM is running or the device is sus-

pended. The CLEAR BLOCK LOCK BITS command is

executed by a two-cycle sequence. First, a clear block

lock bits setup is written, followed by a CLEAR BLOCK

LOCK BITS CONFIRM command. Then the device au-

tomatically outputs status register data when read (see

Figure 9). The CPU can detect completion of the clear

block lock bits event by analyzing the STS pin output or

the status register bit SR7. When the operation is com-

pleted, status register bit SR5 should be checked. If a

clear block lock bits error is detected, the status register

should be cleared. The CEL remains in read status reg-

ister mode until another command is issued.

This two-step setup sequence ensures that block

lock bits are not accidentally cleared. An invalid clear

block lock bits command sequence results in status

register bits SR4 and SR5 being set to “1.” Also, a reli-

able CLEAR BLOCK LOCK BITS operation can only oc-

cur when V^CCand VPEN are valid. If a CLEAR BLOCK

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LOCK BITS operation is attempted when VPEN ≤ VPENLK,

SR3 and SR5 are set to “1.” If a CLEAR BLOCK LOCK

BITSoperationisabortedduetoVPEN orVCC transitioning

out of valid range, block lock bit values are left in an

undetermined state. To initialize block lock bit con-

tents to known values, a repeat of CLEAR BLOCK LOCK

BITS is required.

protection register address space results in a status

register error (program error bit SR4 is set to “1”). At-

tempting to program a locked protection register seg-

ment results in a status register error (program error bit

SR4 and lock error bit SR1 are set to “1”).

LOCKING THE PROTECTION REGISTER

By programming bit 1 of the PR-LOCK location to

“0,” the user-programmable segment of the protection

register is lockable. To protect the unique device num-

ber, bit 0 of this location is programmed to “0” at the

Micron factory. Bit 1 is set using the PROTECTION PRO-

GRAM command to program “FFFDh” to the PR-LOCK

location. When these bits have been programmed, no

further changes can be made to the values stored in

the protection register. PROTECTION PROGRAM com-

mands to a locked section will result in a status register

error (program error bit SR4 and lock error bit SR1 are

set to “1”). Note that the protection register lockout

state is not reversible.

PROTECTIONREGISTERPROGRAM

COMMAND

The 3V Q-Flash memory includes a 128-bit protec-

tion register to increase the security of a system design.

For example, the number contained in the protection

register can be used for the Flash component to com-

municate with other system components, such as the

CPU or ASIC, to prevent device substitution. The 128

bits of the protection register are divided into two 64-

bit segments. One of the segments is programmed at

the Micron factory with a unique and unchangeable

64-bit number. The other segment is left blank for

customers to program as needed. After the customer

segment is programmed, it can be locked to prevent

reprogramming.

Figure 3

Protection Register Memory Map

READING THE PROTECTION REGISTER

The protection register is read in the identification

read mode. The device is switched to identification

read mode by writing the READ IDENTIFIER command

(90h). When in this mode, READ cycles from addresses

shown in Table 19 or Table 20 retrieve the specified

information. To return to read array mode, the READ

ARRAY command (FFh) must be written.

Word

Address

88h

4 Words

User-Programmed

85h

84h

4 Words

Factory-Programmed

PROGRAMMING THE PROTECTION REGISTER

The protection register bits are programmed with

two-cycle PROTECTION PROGRAM commands.

The 64-bit number is programmed 16 bits at a time

for word-wide parts and eight bits at a time for byte-

wide parts. First, the PROTECTION PROGRAM SETUP

command, C0h, is written. The next write to the device

latches in addresses and data, and programs the speci-

fied location. The allowable addresses are shown

in Table 19 and Table 20. Any attempt to address PRO-

TECTION PROGRAM commands outside the defined

81h

1 Word Lock

80h

0

NOTE: A0 is not used in x16 mode when accessing the

protection register map (see Table 19 for x16

addressing). A0 is used for x8 mode (see Table 20 for

x8 addressing).

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Table19

Word-Wide Protection Register Addressing

WORD USE

A8

1

A7

0

A6

0

A5

0

A4

0

A3

0

1

A2

0

1

0

1

A1

0

1

0

1

0

1

0

1

LOCK

Both

Factory

User

0

1

2

3

4

5

6

7

User

1

0

1

0

Table20

Byte-Wide Protection Register Addressing

BYTE

LOCK

USE

Both

A8

1

A7

0

A6

0

A5

0

A4

0

1

A3

0

1

0

A2

0

1

0

1

0

A1

0

1

0

1

0

1

0

1

0

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Factory

User

NOTE: 1. All address lines not specified in the above tables must be “0” when accessing the

protection register (i.e., A22–A9 = 0).

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Figure 4

WRITE-to-BUFFERFlowchart

BUS

OPERATION COMMAND COMMENTS

WRITE

WRITE-to-

BUFFER

Data = E8h

Block Address

Start

Set Timeout

READ

XSR7 = Valid

Addr = Block Address

Issue

No

WRITE-to-BUFFER

Command E8h,

Block Address

STANDBY

Check XSR7

1 = Write Buffer Available

0 = Write Buffer Not Available

Read Extended

Status Register

1, 2

WRITE

Data = N = Word/Byte Count

N = 0 Corresponds to Count = 1

Addr = Block Address

WRITE-to-

0

XSR7 =

BUFFER Timeout?

1

3, 4

Write Word or

Byte Count N,

Block Address

WRITE

Data = Write Buffer Data

Addr = Device Start Address

5, 6

WRITE

Data = Write Buffer Data

Addr = Device Address

Write Buffer Data,

Start Address

X = 0

Yes

WRITE

Program

Buffer to

Data = D0h

Addr = Block Address

Check

X = N?

Flash Confirm

7

READ

Status register data with the

device enabled, OE# LOW

updates SR

No

Yes

Abort

WRITE-to-BUFFER

Command?

Yes

Write to Another

Block Address

Addr = Block Address

Yes

No

Write to Buffer

Aborted

STANDBY

Check SR7

1 = ISM Ready

0 = ISM Busy

Write Next Buffer

Data, Device Address

X = X + 1

Full status check can be done after all erase and write

sequences complete. Write FFh after the last operation

to reset the device to read array mode.

Program Buffer to

Flash Confirm D0h

Yes

Another

WRITE-to-BUFFER

?

Issue

READ STATUS

Command

No

Read Status Register

1

0

SR7 =

1

Full Status

Check if Desired

Programming

Complete

NOTE: 1. Byte or word count values on DQ0–DQ7 are loaded into the count register. Count ranges on this device for byte mode

are n = 00h to 1Fh and for word mode are n = 0000h to 000Fh.

2. The device now outputs the status register when read (XSR is no longer available).

3. Write buffer contents will be programmed at the device start address or destination Flash address.

4. Align the start address on a write buffer boundary for maximum programming performance (i.e., A4–A0 of the start

address = 0).

5. The device aborts the WRITE-to-BUFFER command if the current address is outside of the original block address.

6. The status register indicates an “improper command sequence” if the WRITE-to-BUFFER command is aborted. Follow

this with aCLEAR STATUS REGISTER command.

7. Toggling OE# (LOW to HIGH to LOW) updates the status register. This can be done in place of issuing the READ STATUS

REGISTERcommand.

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Figure 5

Byte/Word Program Flowchart

BUS

OPERATION COMMAND COMMENTS

WRITE

SETUP BYTE/ Data = 40h

WORD

Addr = Location to be

Start

PROGRAM

Programmed

WRITE

BYTE/

WORD

Data = Data to be

Programmed

Write 40h,

Address

PROGRAM Addr = Location to be

Programmed

Write Data and

Address

READ

Status Register Data

STANDBY

Check SR7

1 = ISM Ready

0 = ISM Busy

Read Status

Register

Toggling OE# (LOW to HIGH to LOW) updates the status

register. This can be done in place of issuing the READ

STATUSREGISTERcommand.Repeatforsubsequent

programmingoperations.

0

SR7 =

1

After each program operation or after a sequence of

programming operations, an SR full status check can be

done.

Full Status

Check if Desired

Write FFh after the last program operation to place the

device in read array mode.

Byte/Word

Program Complete

FULL STATUS CHECK PROCEDURE

BUS

Read Status Register

Data (see above)

OPERATION COMMAND COMMENTS

STANDBY

Check SR3

1 = Programming to

Voltage Error Detect

1

Voltage Range Error

Device Protect Error

Programming Error

SR3 =

STANDBY

Check SR1

1 = Device Protect Detect

RP# = V^IH, Block Lock Bit is

Set

Only required for systems

implemeting lock bit

configuration

0

1

SR1 =

0

STANDBY

Check SR4

1 = Programming Error

SR4 =

0

Toggling OE# (LOW to HIGH to LOW) updates the status

register. This can be done in place of issuing the READ

STATUSREGISTERcommand.Repeatforsubsequent

programmingoperations.

Byte/Word

Program Successful

SR4, SR3, and SR1 are only cleared by the CLEAR STATUS

REGISTER command in cases where multiple locations are

programmed before full status is checked.

If an error is detected, clear the status register before

attempting retry or other error recovery.

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Figure 6

BUS

OPERATION COMMAND COMMENTS

PROGRAMSUSPEND/RESUMEFlowchart

WRITE

PROGRAM Data = B0h

SUSPEND

Addr = X

Start

READ

Status Register Data

Addr = X

Write B0h

STANDBY

Check SR7

1 = ISM Ready

0 = ISM Busy

Read Status

Register

STANDBY

Check SR6

1 = Programming

Suspended

0 = Programming

Completed

0

SR7 =

1

WRITE

READ

ARRAY

Data = FFh

Addr = X

0

Programming

Completed

SR2 =

Read array locations other

than that being

programmed

1

Write FFh

WRITE

PROGRAM Data = D0h

RESUME Addr = X

Read Data Array

1

No

Done Reading

Yes

Write D0h

Write FFh

Programming

Resumed

Read Data Array

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Figure 7

BLOCK ERASE Flowchart

BUS

OPERATION COMMAND COMMENTS

WRITE

READ

ERASE

BLOCK

Data = 20h

Addr = Block Address

Start

ERASE

Data = D0h

Issue Single BLOCK

ERASE Command 20h,

Block Address

CONFIRMED Addr = Block Address

Status register data with

the device enabled; OE#

LOW updates SR

Write Confirm D0h

Block Address

Addr = X

STANDBY

Check SR7

1 = ISM Ready

0 = ISM Busy

Read Status

Register

Suspend

Erase Loop

No

The erase confirm byte must follow erase setup.

This device does not support erase queuing.

No

SR7 =

1

Suspend Erase

Yes

Full status check can be done after all erase and write

sequences complete. Write FFh after the last operation to

reset the device to read array mode.

Full Status

Check if Desired

Erase Flash

Block(s) Complete

128Mb, 64Mb, 32MbQ-FlashMemory

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 8

BLOCKERASESUSPEND/RESUME

Flowchart

BUS

OPERATION COMMAND COMMENTS

WRITE

ERASE

Data = B0h

Addr = X

SUSPEND

Start

READ

Status Register Data

Addr = X

STANDBY

Check SR7

Write B0h

1 = ISM Ready

0 = ISM Busy

Read Status

Register

STANDBY

WRITE

Check SR6

1 = Block Erase Suspended

0 = Block Erase Completed

0

SR7 =

ERASE

RESUME

Data = D0h

Addr = X

1

0

BLOCK ERASE

Completed

SR6 =

1

Read

Read or

Program?

Program

Read Array

Data

Program

Loop

No

Done?

Yes

Write D0h

Write FFh

BLOCK ERASE

Resumed

Read Data Array

128Mb, 64Mb, 32MbQ-FlashMemory

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32

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 9

SET BLOCK LOCK BITS Flowchart

BUS

OPERATION COMMAND COMMENTS

WRITE

SET BLOCK Data = 60h

LOCK BITS Addr = Block Address

SETUP

Start

WRITE

SET BLOCK Data = 01h

LOCK BITS Addr = Block Address

CONFIRM

Write 60h,

Block Address

Write 01h,

Block Address

READ

Status Register Data

STANDBY

Check SR7

1 = ISM Ready

0 = ISM Busy

Read Status

Register

Repeat for subsequent lock bit operations.

0

Full status check can be done after each lock bit set

operation or after a sequence of lock bit set operations

SR7 =

1

Write FFh after the last lock bit set operation to place

device in read array mode.

Full Status

Check if Desired

SET BLOCK LOCK BITs

Complete

FULL STATUS CHECK PROCEDURE

BUS

Read Status Register

Data (see above)

OPERATION COMMAND COMMENTS

STANDBY

Check SR3

1 = Programming Voltage

Error Detect

1

Voltage Range Error

SR3 =

Check SR4, SR5

Both 1 = Command

Sequence Error

0

1

Command Sequence

Error

Check SR4

1 = Set Block Lock Bits

Error

SR4,5 =

0

SR5, SR4, and SR3 are only cleared by the CLEAR STATUS

REGISTER command in cases where multiple lock bits are set

before full status is checked.

SET BLOCK LOCK BITS

Error

SR4 =

0

If an error is detected, clear the status register before

attempting retry or other error recovery.

SET BLOCK LOCK BITS

Successful

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 10

CLEAR BLOCK LOCK BITS Flowchart

BUS

OPERATION COMMAND COMMENTS

WRITE

CLEAR

Data = 60h

BLOCK LOCK Addr = X

BITS SETUP

Start

WRITE

CLEAR BLOCK Data = D0h

LOCK BITS Addr = X

or CONFIRM

Write 60h

READ

Status Register Data

Write D0h

STANDBY

Check SR7

1 = ISM Ready

0 = ISM Busy

Read Status

Register

Write FFh after the CLEAR BLOCK LOCK BITS operation to

place device in read array mode.

0

SR7 =

1

Full Status

Check if Desired

CLEAR BLOCK LOCK

BITS Complete

FULL STATUS CHECK PROCEDURE

BUS

Read Status Register

Data (see above)

OPERATION COMMAND COMMENTS

STANDBY

Check SR3

1 = Programming Voltage

Error Detect

1

Voltage Range Error

SR3 =

Check SR4, 5

Both 1 = Command

Sequence Error

0

1

Command Sequence

Error

Check SR5

1 = Clear Block Lock Bits

Error

SR4,5 =

0

SR5, SR4, and SR3 are only cleared by the CLEAR STATUS

REGISTERcommand.

CLEAR BLOCK LOCK

BITS Error

SR5 =

0

If an error is detected, clear the status register before

attempting retry or other error recovery.

CLEAR BLOCK LOCK

BITS Successful

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 11

PROTECTIONREGISTERPROGRAMMING

Flowchart

BUS

OPERATION COMMAND COMMENTS

WRITE

READ

PROTECTION Data = C0h

PROGRAM

SETUP

Start

PROTECTION Data = Data to Program

PROGRAM Addr = Location to

Program

Write C0h

(Protection Register

Program Setup)

Status Register Data

Toggle CE# or OE# to

update status register data

Write Protect Register

Address/Data

STANDBY

Check SR7

1 = ISM Ready

0 = ISM Busy

Read Status

Register

PROTECTIONPROGRAMoperationscanonlybeaddressed

within the protection register address space. Addresses

outside the defined space will return an error.

No

SR7 = 1

Repeatforsubsequentprogrammingoperations.

SR full status check can be done after each program or after

asequenceofprogramoperations.

Yes

Full Status

Check if Desired

Write FFh after the last program operation to reset device

to read array mode.

PROGRAM

Complete

FULL STATUS CHECK PROCEDURE

BUS

COMMENTS

OPERATION COMMAND SR1 SR3 SR4

Read Status Register

Data (see above)

STANDBY

0

1

0

1

VPEN LOW

Protection

Register

Program

Error

1, 1

V

PEN Range Error

SR3, SR4 =

SR1, SR4 =

STANDBY

1

0

1

Register

Locked:

Aborted

0, 1

1, 1

PROTECTION REGISTER

PROGRAMMING Error

SR3, if set during a program attempt, MUST be cleared

before further attempts are allowed by the ISM.

Attempted Program to

Locked Register –

Aborted

SR1, SR3, and SR4 are only cleared by the CLEAR STAUS

REGISTER command, in cases of multiple protection register

program operations, before full status is checked.

If an error is detected, clear the status register before

attempting retry or other error recovery.

PROGRAM

Successful

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

DESIGNCONSIDERATIONS

FIVE-LINE OUTPUT CONTROL

Micron provides five control inputs (CE0, CE1, CE2,

OE#, and RP#) to accommodate multiple memory con-

nections in large memory arrays. This control provides

the lowest possible memory power dissipation and en-

sures that data bus contention does not occur.

To efficiently use these control inputs, an address

decoder should enable the device (see Table 2) while

OE# is connected to all memory devices and the

system’s READ# control line. This ensures that only

selected memory devices have active outputs while

deselected memory devices are in standby mode. Dur-

ing system power transitions, RP# should be connected

to the system POWERGOOD signal to prevent unin-

tended writes. POWERGOOD should also toggle dur-

ing system reset.

mand for alternate configurations of the STS pin. STS

can be connected to an interrupt input of the system

CPU or controller. STS is active at all times. In default

mode, it is also High-Z when the device is in block erase

suspend (with programming inactive), program sus-

pend, or reset/power-down mode.

POWERSUPPLYDECOUPLING

Device decoupling is required for Flash memory

power switching characteristics. There are three sup-

ply current issues to consider: standby current levels,

active current levels, and transient peaks produced by

falling and rising edges of CEx and OE#. Transient cur-

rent magnitudes depend on the device outputs’ ca-

pacitive and inductive loading. Two-line control and

proper decoupling capacitor selection suppresses tran-

sient voltage peaks. Because Micron Q-Flash memory

devices draw their power from three V^CCpins (these

devices do not include a V^PPpin), it is recommended

that systems without separate power and ground

planes attach a 0.1µF ceramic capacitor between each

of the device’s three V^CCpins (this includes VCCQ) and

GND. These high-frequency, low-inductance capaci-

tors should be placed as close as possible to package

leads on each Micron Q-Flash memory device. Addi-

tionally, for every eight devices, a 4.7µF electrolytic

capacitor should be placed between V^CCand GND at

the array’s power supply connection.

STS AND BLOCK ERASE, PROGRAM, AND

LOCKBITCONFIGURATION

POLLING

As an open drain output, STS should be connected

to V^CCQ by a pull-up resistor to provide a hardware

method of detecting block erase, program, and lock bit

configuration completion. It is recommended that a

2.5KΩ resistor be used between STS# and V^CCQ. In de-

fault mode, it transitions LOW after block erase, pro-

gram, or lock bit configuration commands and returns

to High-Z when the ISM has finished executing the

internal algorithm. See the CONFIGURATION com-

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Q-FLASH MEMORY

REDUCINGOVERSHOOTSANDUNDER-

SHOOTSWHENUSINGBUFFERSOR

TRANSCEIVERS

Overshoots and undershoots can sometimes cause

input signals to exceed Flash memory specifications as

faster, high-drive devices such as transceivers or buff-

ers drive input signals to Flash memory devices. Many

buffer/transceiver vendors now carry bus-interface

devices with internal output-damping resistors or

reduced-drive outputs. Internal output-damping

resistors diminish the nominal output drive currents,

while still leaving sufficient drive capability for most

applications. These internal output-damping resistors

help reduce unnecessary overshoots and undershoots

by diminishing output-drive currents. When consider-

ing a buffer/transceiver interface design to Flash, de-

vices with internal output-damping resistors or re-

duced-drive outputs should be used to minimize over-

shoots and undershoots.

upon power-up, upon exiting reset/power-down

mode, or after V^CCtransitions below VLKO. VCC must be

kept at or above V^PENduring VCC transitions.

After block erase, program, or lock bit configuration,

and after V^PENtransitions to VPENLK, the CEL must be

placed in read array mode via the READ ARRAY com-

mand if subsequent access to the memory array is de-

sired. During V^PENtransitions, VPEN must be kept at or

below V^CC.

POWER-UP/DOWNPROTECTION

During power transition, the device itself provides

protection against accidental block erasure, program-

ming, or lock bit configuration. Internal circuitry resets

the CEL to read array mode at power-up. A system

designer must watch out for spurious writes for V^CC

voltages above VLKO when VPEN is active. Because WE#

must be LOW and the device enabled (see Table 2) for

a command write, driving WE# to V^IHor disabling the

device inhibits WRITEs. The CEL’s two-step command

sequence architecture provides added protection

against data alteration. In-system block lock and un-

lock capability protects the device against inadvertent

programming. The device is disabled when RP# = V^IL

regardless of its control inputs. Keeping VPEN below

VPENLK prevents inadvertent data change.

VCC,VPEN,RP#TRANSITIONS

If VPEN or VCC falls outside of the specified operating

ranges, or RP# is not set to VIH, block erase, program,

and lock bit configuration are not guaranteed. If RP#

transitions to V^ILduring block erase, program, or lock

bit configuration, STS (in default mode) will remain

t

LOW for a maximum time of PLPH + PHRH, until the

RESET operation is complete and the device enters

reset/power-down mode. The aborted operation may

leave data partially corrupted after programming, or

partially altered after an erase or lock bit configuration.

Therefore, BLOCK ERASE and LOCK BIT CONFIGURA-

TION commands must be repeated after normal op-

eration is restored. Device power-off or RP# = V^ILclears

the status register. The CEL latches commands issued

by system software and is not altered by V^PENor CEx

transitions, or ISM actions. Its state is read array mode

POWERDISSIPATION

Designers must consider battery power consump-

tion not only during device operation, but also for data

retention during system idle time. Flash memory’s

nonvolatility increases usable battery life because data

is retained when system power is removed.

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

operation of the device at these or any other conditions

above those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

ABSOLUTEMAXIMUMRATINGS*

Temperature Under

Bias Expanded ................................... –40ºC to +85ºC

Storage Temperature ........................... –65ºC to +125ºC

For V^CCQ = +2.7V to +3.6V

**All specified voltages are with respect to GND. Mini-

mum DC voltage is –0.5V on input/output pins and

-0.2V on V^CCand VPEN pins. During transitions, this level

may undershoot to –2.0V for periods <20ns. Maximum

DC voltage on input/output pins, V^CC, and VPEN is VCC

+0.5V which, during transitions, may overshoot to VCC

+2.0V for periods <20ns.

Voltage On Any Pin ........................ –2.0V to +5.0V**

For V^CCQ = +4.5V to +5.5V

All Pins Except VCC .......................... –2.0V to +7.0V**

VCC ..................................................... –2.0V to +5.5V**

Output Short Circuit Current............................. 100mA^†

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

†Output shorted for no more than one second. No more

than one output shorted at a time.

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

TEMPERATUREANDRECOMMENDEDDCOPERATINGCONDITIONS

Commercial Temperature (0ºC ≤ T_A≤ +85ºC), Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

PARAMETER

SYMBOL

VCC1

MIN

2.7

MAX

3.6

UNITS

NOTES

VCC Supply Voltage (2.7V–3.6V)

VCCQ Supply Voltage (2.7V–3.6V)

VCCQ Supply Voltage (4.5V–5.5V)

V

VCCQ1

VCCQ2

2.7

3.6

4.5

5.5

INPUT AND VPEN LOAD CURRENT

VCC = VCC (MAX); VCCQ = VCCQ (MAX)

VIN = VCCQ or GND

ILI

1

µA

1

OUTPUT LEAKAGE CURRENT

V^CC= VCC (MAX); VCCQ = VCCQ (MAX)

VIN = VCCQ or GND

ILO

10

INPUT LOW VOLTAGE

INPUT HIGH VOLTAGE

VIL

VIH

-0.5

2

0.8

V

2

VCCQ + 0.5

OUTPUT LOW VOLTAGE (2.7V–3.6V)

VCCQ = VCCQ1 (MIN)

IOL = 2mA

VOL

0.4

0.2

V

2, 3

V^CCQ = VCCQ1 (MIN)

IOL = 100µA

OUTPUT LOW VOLTAGE (4.5V–5.5V)

VCCQ = VCCQ2 (MIN)

IOL = 2mA

VOL

0.45

0.25

V

4

2

OUTPUT LOW VOLTAGE (4.5V–5.5V)

VCCQ = VCCQ2 (MIN)

IOL = 100µA

OUTPUT HIGH VOLTAGE (2.7V–3.6V)

VCCQ = VCCQ (MIN)

IOH = -2.5mA

VOH

0.85 × VCC

Q

V

VCCQ = VCCQ (MIN)

IOH = -100µA

VCCQ - 0.2

OUTPUT HIGH VOLTAGE (4.5V–5.5V)

VCCQ = VCCQ2 (MIN)

IOH = -2.5mA

2.4

V

4

VCCQ = VCCQ2 (MIN)

IOH = -100µA

VCCQ - 0.2

NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).

2. Sampled, not 100% tested.

3. Includes STS.

4. MT28F320J3RG-11FandMT28F640J3RG-12Fonly.

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

CAPACITANCE

(T_A= +25ºC; f = 1 MHz)

PARAMETER/CONDITION

Input Capacitance

SYMBOL

C

TYP

5

MAX

8

UNITS

pF

Output Capacitance

BYTE#

COUT

10

5

12

pF

All other Pins

COUT

12

pF

RECOMMENDEDDCELECTRICALCHARACTERISTICS

Commercial Temperature (0ºC ≤ T_A≤ +85ºC), Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS NOTES

V^CCStandby

Current

CMOS Inputs; VCC = VCC (MAX);

Device is enabled;

ICC1

50

120

µA

1, 2, 3

RP# = VCCQ 0.2V

TTL inputs; VCC = VCC (MAX);

Device is enabled; RP# = VIH

0.71

50

2

mA

µA

VCC Power-Down

Current

RP# = GND 0.2V;

IOUT (STS) = 0mA

ICC2

ICC3

120

20

VCC Page Mode

Read Current

CMOS inputs; VCC = VCC (MAX);

VCCQ = VCCQ (MAX) using standard

4-word page mode READs;

Device is enabled;

11

mA

1, 3

f = 5 MHz; IOUT = 0mA

CMOS inputs; VCC = VCC (MAX);

V^CCQ = VCCQ (MAX) using standard

4-word page mode READs;

Device is enabled;

15

29

50

mA

f = 33 MHz; IOUT = 0mA

VCC Asynchronous Mode

Read Current

CMOS inputs; VCC = VCC (MAX);

VCCQ = VCCQ (MAX) using

standard word/byte single READs;

Device is enabled;

ICC4

12.5

1, 3

f = 5 MHz; IOUT = 0mA

NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).

2. Includes STS.

3. CMOS inputs are either VCC 0.2V or VSS 0.2V. TTL inputs are either VIL or VIH.

4. Sampled, not 100% tested.

5. ICCWS and ICCES are specified with the device deselected. If the device is read or written while in erase suspend mode,

the device’s current draw is ICCR or ICCW.

6. Block erase, programming, and lock bit configurations are inhibited when VPEN ≤ VPENLK, and they are not guaranteed in

the range between VPENLK (MAX) and VPENH (MIN), or above VPENH (MAX).

7. Typically, VPEN is connected to VCC.

8. Block erase, programming, and lock bit configurations are inhibited when VCC < VLKO, and they are not guaranteed in

the range between VLKO (MIN) and VCC (MIN), or above VCC (MAX).

(continued on next page)

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

RECOMMENDEDDCELECTRICALCHARACTERISTICS(continued)

Commercial Temperature (0ºC ≤ T_A≤ +85ºC), Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

DESCRIPTION

CONDITIONS

SYMBOL

TYP

22

MAX

60

UNITS NOTES

VCC Program or Set

Lock Bits Current

CMOS inputs, VPEN = VCC

TTL inputs, VPEN = VCC

CMOS inputs, VPEN = VCC

TTL inputs, VPEN = VCC

Device is disabled

ICC5

mA

1, 4

1

24

70

VCC Block Erase or Clear

Block Lock Bits Current

ICC6

ICC7

20

70

22

80

VCC Program Suspend or

Block Erase Suspend

10

Current

V^PENLockout during

Program, Erase, and

Lock Bit Operations

VPENLK

VPENH

VLKO

1

V

5, 6, 7

6, 7

8

VPEN during Block Erase,

Program, or Lock Bit

Operations

2.7

2.2

3.6

VCC Lockout Voltage

NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).

2. Includes STS.

3. CMOS inputs are either V^CC0.2V or VSS 0.2V. TTL inputs are either VIL or VIH.

4. Sampled, not 100% tested.

5. ICCWS and ICCES are specified with the device deselected. If the device is read or written while in erase suspend mode,

the device’s current draw is I^CCRor ICCW.

6. Block erase, programming, and lock bit configurations are inhibited when VPEN ≤ VPENLK, and they are not guaranteed in

the range between V^PENLK(MAX) and VPENH (MIN), or above VPENH (MAX).

7. Typically, VPEN is connected to VCC.

8. Block erase, programming, and lock bit configurations are inhibited when V^CC< VLKO, and they are not guaranteed in

the range between VLKO (MIN) and VCC (MIN), or above VCC (MAX).

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 12

Transient Input/Output Reference Waveform for

V^CCQ = 2.7V–3.6V, or VCCQ = 4.5V–5.5V

V

CCQ

Input VCCQ/2

Test Points

VCCQ/2 Output

0.0

NOTE: AC test inputs are driven at VCCQ for a logic 1 and 0.0V for a logic 0. Input timing begins, and output timing ends, at VCCQ/

2V (50% of V^CCQ). Input rise and fall times (10% to 90%) < 5ns.

Figure 13

Transient Equivalent Testing Load Circuit

1.3V

1N914

R_L= 3.3K

Ω

Device

Under Test

Out

C_L

NOTE: C_Lincludes jig capacitance

Test Configuration Capacitance Loading Value

Test Configuration

CC = 2.7V to 3.6V

CCQ = 4.5V to 5.5V

C_L(pF)

30

V

CCQ = V

V

30

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

ACCHARACTERISTICS–READ-ONLYOPERATIONS

(Notes: 1, 2, 4); Commercial Temperature (0ºC ≤ T_A≤ +85ºC), Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

VCC = 2.7V–3.6V

V^CCQ = 2.7V–3.6V

or 4.5V–5.5V

PARAMETER

READ/WRITECycleTime

SYMBOL DENSITY

MIN

110

120

150

MAX

UNITS

ns

NOTES

t

RC

32Mb

64Mb

128Mb

32Mb

64Mb

128Mb

32Mb

64Mb

128Mb

ALL

t

Address to Output Delay

CEx to Output Delay

AA

110

120

150

110

120

150

50

t

ACE

t

OE# to Non-Array Output Delay

OE# to Array Output Delay

RP# HIGH to Output Delay

AOE

AOA

RWH

3, 5

5

t

ALL

25

t

32Mb

64Mb

128Mb

ALL

150

180

210

t

CEx to Output in Low-Z

OE# to Output in Low-Z

CEx HIGHto Output in High-Z

OE#HIGH to Output in High-Z

OEC

OEO

ODC

ODO

0

6

t

35

15

t

ALL

t

Output Hold from Address, CEx, or OE#

Change, Whichever Occurs First

OH

ALL

0

t

CEx LOW to BYTE# HIGH or LOW

BYTE# to Output Delay

BYTE# to Output in High-Z

CEx HIGH to CEx LOW

CB

ALL

10

1,000

ns

6

t

ABY

ODB

CWH

APA

t

6

t

Page Address Access Time

25

NOTE: 1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined at the first edge

of CE0, CE1, or CE2 that disables the device (see Table 2).

2. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.

t

3. OE# may be delayed up to ACE - AOE after the first edge of CEx that enables the device (see Table 2) without impact

t

on ACE.

4. See Figures 12 and 13, Transient Input/Output Reference Waveform for VCCQ = 2.7V–3.6V or VCCQ = 4.5V–5.5V, and

Transient Equivalent Testing Load Circuit for testing characteristics.

t

5. When reading the Flash array, a faster AOE applies. Nonarray READs refer to status register READs, QUERY READs, or

DEVICEIDENTIFIERREADs.

6. Sampled, not 100% tested.

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

PAGEMODEANDSTANDARDWORD/BYTEREADOPERATIONS

V_IH

V_IL

ADDRESSES

(A22–A3)

t

RC

V_IH

V_IL

VALID

ADDRESS

VALID

ADDRESS

ADDRESSES

(A2–A0)

ADDRESS ADDRESS

t

CWH

V_IH

V_IL

Disabled

CEx

Enabled

t

ODC

ODO

t

AA

V_IH

V_IL

OE#

t

ACE

V_IH

V_IL

t

AOE/

AOA

WE#

OH

t

RWH

t

APA

t

OEC

V_OH

V_OL

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

DQ0–DQ15

High-Z

t

OEO

V_IH

V_IL

VCC

RP#

V_IH

V_IL

t

CB

ABY

t

ODB

V_IH

V_IL

BYTE

UNDEFINED

TIMING PARAMETERS

VCC = 2.7V–3.6V

V^CCQ = 2.7V–3.6V

or 4.5V–5.5V

V^CC= 2.7V–3.6V

V^CCQ = 2.7V–3.6V

or 4.5V–5.5V

SYMBOL

MIN

110

MAX

UNITS

ns

SYMBOL

MIN

MAX

180

UNITS

ns

t

RC (32Mb)

RWH (64Mb)

RWH (128Mb)

t

RC (64Mb)

120

ns

210

ns

t

RC (128Mb)

150

ns

OEC

0

ns

t

AA (32Mb)

110

120

150

110

120

150

50

ns

OEO

ns

t

AA (64Mb)

ns

ODC

35

15

ns

t

AA (128Mb)

ns

ODO

ns

t

ACE (32Mb)

ns

OH

0

ns

t

ACE (64Mb)

ns

CB

10

ns

t

ACE (128Mb)

ns

ABY

ODB

CWH

APA

1,000

ns

t

AOE

ns

t

AOA

25

ns

t

RWH (32Mb)

150

ns

25

ns

NOTE: CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined as the first edge of

CE0, CE1, or CE2 that disables the device.

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

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128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

ACCHARACTERISTICS–WRITEOPERATIONS

(Notes: 1, 2, 3); Commercial Temperature (0ºC ≤ T_A≤ +85ºC), Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

ACCHARACTERISTICS

PARAMETER

-11/-12/-15

MIN MAX

1

0

70

50

55

0

30

0

35

SYMBOL

UNITS

µs

ns

NOTES

t

RP# High Recovery to WE# (CEx) Going LOW

CEx (WE#) LOW to WE# (CEx) Going LOW

Write Pulse Width

Data Setup to WE# (CEx) Going HIGH

Address Setup to WE# (CEx) GoingHIGH

CEx (WE#) Hold from WE# (CEx) HIGH

Data Hold from WE# (CEx) HIGH

Address Hold from WE# (CEx)HIGH

Write Pulse Width HIGH

VPEN Setup to WE# (CEx) Going HIGH

Write Recovery Before Read

WE# (CEx) HIGH to STS Going LOW

VPEN Hold from Valid SRD, STS Going HIGH

WE# (CEx) HIGH to Status Register Busy

RS

4

5

6

t

CS ( WS)

t

WP( CP)

t

DS

t

AS

ns

t

CH( WH)

ns

t

DH

t

AH

t

WPH( CPH)

ns

7

t

VPS

WR

STS

VPH

ns

4

t

ns

8

t

200

ns

9

4, 9, 10

4

t

0

t

WB

NOTE: 1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined as the first edge

of CE0, CE1, or CE2 that disables the device.

2. Read timing characteristics during BLOCK ERASE, PROGRAM, and LOCK BIT CONFIGURATION operations are the same as

during READ-only operations. Refer to AC Characteristics – Read-Only Operations.

3. A WRITE operation can be initiated and terminated with either CEX or WE#.

4. Sampled, not 100% tested.

t

5. Write pulse width ( WP) is defined from CEx or WE# going LOW (whichever goes LOW last) to CEx or WE# going HIGH

(whichever goes HIGH first).

6. Refer to Table 4 for valid A^INand DIN for block erase, program, or lock bit configuration.

t

7. Write pulse width HIGH ( WPH) is defined from CEx or WE# going HIGH (whichever goes HIGH first) to CEx or WE# going

LOW (whichever goes LOW first).

t

8. For array access, AA is required in addition to WR for any accesses after a WRITE.

9. STS timings are based on STS configured in its RY/BY# default mode.

10. V^PENshould be held at VPENH until determination of block erase, program, or lock bit configuration success (SR1/3/4/5 =

0).

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

45

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

BLOCKERASE, PROGRAM, ANDLOCKBITCONFIGURATIONPERFORMANCE

(Notes: 1, 2, 3); Commercial Temperature (0ºC ≤ T_A≤ +85ºC), Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

CHARACTERISTICS

PARAMETER

Write Buffer Byte Program Time

-11/-12/-15

8

SYMBOL

WED1

TYP

MAX

UNITS

µs

NOTES

4, 5, 6, 7

t

150

654

(Time to Program 32 bytes/16 words)

t

Byte/WordProgramTime(UsingWORD/BYTEPROGRAMCommand)

BlockProgramTime(UsingWRITE-to-BUFFERCommand)

Block Erase Time

Set Lock Bits Time

Clear Block Lock Bits Time

WED2

14

0.6

0.75

64

0.5

25

630

1.7

5

75

0.7

30

35

µs

sec

µs

sec

µs

4

5

t

WED3

t

WED4

t

WED5

t

WED6

t

Program Suspend Latency Time to Read

Erase Suspend Latency Time to Read

LPS

t

LES

26

µs

NOTE: 1. Typical values measured at T = +25ºC and nominal voltages. Assumes corresponding lock bits are not set. Subject to

A

change based on device characterization.

2. These performance numbers are valid for all speed versions.

3. Sampled, but not 100% tested.

4. Excludes system-level overhead.

5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.

6. Effective per-byte program time is 4.7µs/byte (typical).

7. Effective per-word program time is 9.4µs/word (typical).

8. MAX values are measured at worst-case temperature and V^CCcorner after 100,000 cycles.

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

46

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

1

WRITEOPERATIONS

Note 2

Note 3

Note 4

Note 5

Note 6

Note 7

V_IH

V_IL

A

IN

AIN

Addresses

Disabled

t

AS

AH

V_IH

V_IL

CEx (WE#)

Enabled

t

WR

t

CH

RS

V_IH

V_IL

OE#

t

WPH

CS

V_IH

V_IL

Disabled

WE# (CEx)

Enabled

t

WP

t

VALID

DS

t

WB

BUSY SRD READY SRD

t

DH

V_IH

V_IL

DQ0–DQ15

D

IN

D

IN

DIN

t

STS

V_OH

V_OL

STS

V_IH

V_IL

RP#

t

VPS

VPH

V_PENH

V_PENLK

V

PEN

V_IL

UNDEFINED

TIMING PARAMETERS

-11/-12/-15

SYMBOL

MIN

1

MAX

UNITS

µs

SYMBOL

MIN

0

MAX

UNITS

ns

t

RS

AH

t

CS

0

ns

WPH

30

0

ns

t

WP

70

50

55

0

ns

VPS

ns

t

DS

ns

WR

35

ns

t

AS

ns

STS

200

ns

t

CH

ns

VPH

0

ns

t

DH

0

ns

WB

ns

NOTE: 1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined at the first edge

of CE0, CE1, or CE2 that disables the device (see Table 2). STS is shown in its default mode (RY/BY#).

2. VCC power-upandstandby.

3. Write block erase, write buffer, or program setup.

4. Write block erase or write buffer confirm, or valid address and data.

5. Automated erase delay.

6. Read status register or query data.

7. WRITEREADARRAYcommand.

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

47

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

1

RESUMEOPERATIONS

Note 2

Note 3

( (

V_IH

V_IL

) )

AIN

Addresses

Disabled

( (

) )

t

AS

AH

( (

) )

V_IH

V_IL

CEx (WE#)

Enabled

t

CH

( (

) )

V_IH

V_IL

OE#

t

WEH

CS

( (

) )

V_IH

V_IL

Disabled

WE# (CEx)

Enabled

t

WP

t

DS

t

DH

V_IH

V_IL

( (

DQ0–DQ15

Command

) )

Command

Note 4

t

STS

V_OH

V_OL

STS

( (

) )

( (

) )

V_IH

V_IL

RP#

( (

) )

V_PENH

V_PENLK

VPEN

V_IL

UNDEFINED

TIMING PARAMETERS

-11/-12/-15

SYMBOL

MIN

0

MAX

UNITS

ns

SYMBOL

MIN

MAX

UNITS

ns

t

CS

DH

0

t

WP

70

50

55

0

ns

AH

ns

t

DS

ns

STS

200

ns

t

AS

ns

WEH

200

ns

t

CH

ns

NOTE: 1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined at the first edge

of CE0, CE1, or CE2 that disables the device (see Table 2). STS is shown in its default mode (RY/BY#).

2. Erase resume, or program resume.

3. Read status, erase suspend or program suspend.

4. STS value will be:

VIH after ERASE SUSPEND and PROGRAM SUSPEND commands

VIL after READ STATUS command

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

48

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

RESETSPECIFICATIONS

(Note: 1); Commercial Temperature (0ºC ≤ T_A≤ +85ºC), Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

CHARACTERISTICS

PARAMETER

RP# Pulse Low Time

-11/-12/-15

SYMBOL

PLPH

MIN

35

MAX

UNITS

µs

NOTES

t

2

(If RP# is tied to V^CC, this specification is not applicable)

t

RP# HIGH to Reset during Block Erase, Program, or

LockBitConfiguration

PHRH

100

ns

3

4

RESETOPERATION

V_IH

V_IL

STS

t

PHRH

V_IH

V_IL

RP#

t

PLPH

NOTE: 1. STS is shown in its default mode (RY/BY#).

2. These specifications are valid for all product versions (packages and speeds).

3. If RP# is asserted while a BLOCK ERASE, PROGRAM, or LOCK BIT CONFIGURATION operation is not executing, then the

minimum required RP# pulse LOW time is 100ns.

t

4. A reset time, PHQV, is required from the latter of STS (in RY/BY# mode) or RP# going HIGH until outputs are valid.

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

49

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

56-PIN TSOP TYPE I

20.00 0.10

18.40 0.08

PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC

LEAD FINISH: TIN/LEAD PLATE

PACKAGE WIDTH AND LENGTH DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE PROTRUSION

IS 0.25 PER SIDE

PIN #1 INDEX

0.50 TYP

14.00 0.08

0.25

+0.03

-0.02

0.25

0.15

0.10

GAGE

PLANE

SEE DETAIL A

1.20 MAX

+0.10

-0.05

0.10

0.5 ±0.10

0.80 TYP

DETAIL A

NOTE: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

50

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

64-BALLFBGA

0.850 0.075

SEATING PLANE

C

0.08 C

7.00

BALL A8

1.20 MAX

64X ∅0.45

BALL A1 ID

BALL A1

BALL A1 ID

1.00 TYP

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE PRE-

REFLOW DIAMETER IS Ø 0.40

1.00 TYP

7.00 0.05

13.00 0.10

C

L

3.50 0.05

6.50 0.05

C

L

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

3.50 0.05

5.50 0.05

10.00 0.10

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or

62% Sn, 36% Pb, 2%Ag

SOLDER BALL PAD: Ø .33mm

NOTE: 1. All dimensions in millimeters.

DATASHEETDESIGNATIONS

Preliminary: This data sheet contains initial characterization limits that are subject to change upon full

characterization of production devices. This designation applies to the MT28F320J3 and MT28F128J3

devices.

No Marking: This data sheet contains minimum and maximum limits specified over the complete power supply

and temperature range for production devices. Although considered final, these specifications are

subject to change, as further product development and data characterization sometimes occur. This

designation applies to the MT28F640J3 device.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail:prodmktg@micron.com,Internet:http://www.micron.com,CustomerCommentLine:800-932-4992

Micron, the Micron and M logos and Q-Flash are trademarks and/or servicemarks of Micron Technology, Inc.

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

51

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

REVISIONHISTORY

Rev. 6 ......................................................................................................................................................................................... 8/02

• Added commercial temperature range

• Updated Configuration Coding Definitions table

• Removed 3.0V–3.6V V^CCQ voltage range option

t

• Updated V^LKO, VPENLK, AOA, ODC, APA, CH (^tWH), STS, and WB

• Added Resume Operations timing diagram

Rev. 5 ......................................................................................................................................................................................... 5/02

• Updated MT28F320J3 information

Rev. 4 ......................................................................................................................................................................................... 2/02

• Added VCCQ = 4.5V–5.5V parameter for 32Mb and 64Mb devices

• Updated erase and program timing parameters

• Removed Block Erase Status bit

Rev. 3 ......................................................................................................................................................................................... 6/01

• Updated package drawing and corresponding notes

Rev. 2 ......................................................................................................................................................................................... 5/01

• Added 128Mb device information

• Added 64-ball FBGA (1.0mm pitch) package

Original document, Rev. 1 .................................................................................................................................................. 12/00

128Mb, 64Mb, 32MbQ-FlashMemory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

52


型号：	MT28F320J3RG-11
厂家：	MICRON TECHNOLOGY
描述：	Q-FLASHTM MEMORY Q- FLASHTM记忆闪存内存集成电路光电二极管
文件：	总52页 (文件大小：540K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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