EDB8164B4PR-1DITF-D [MICRON]
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Features;型号: | EDB8164B4PR-1DITF-D |
厂家: | MICRON TECHNOLOGY |
描述: | 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Features 动态存储器 双倍数据速率 光电二极管 |
文件: | 总152页 (文件大小:2119K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Features
LPDDR2 SDRAM
EDB8164B4PR, EDB8164B4PK, EDB8164B4PT, EDBA164B2PR
Options
Marking
Features
• Ultra-low-voltage core and I/O power supplies
• Frequency range
– 533 MHz (data rate: 1066 Mb/s/pin)
• 4n prefetch DDR architecture
• 8 internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on each CK_t/CK_c
edge
• Bidirectional/differential data strobe per byte of
data (DQS_t/DQS_c)
• Programmable READ and WRITE latencies (RL/WL)
• Burst length: 4, 8, and 16
• Per-bank refresh for concurrent operation
• Auto temperature-compensated self refresh
(ATCSR) by built-in temperature sensor
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock-stop capability
• Density/Page Size
– 8Gb/2-CS – dual die
– 16Gb/4-CS – quad die
• Organization
81
A1
– x64
64
B
• VDD1/VDD2/VDDQ: 1.8V/1.2V/1.2V
• Revision
– Dual die
4
2
– Quad die
• FBGA “green” package
– 12mm x 12mm x 0.8mm, 216-ball
PoP FBGA package, dual die
– 12mm x 12mm x 0.8mm, 216-ball
PoP FBGA package, dual die
– 12mm x 12mm x 1.0mm, 216-ball
PoP FBGA package, quad die
– 14mm x 14mm x 0.7mm, 220-ball
PoP FBGA package, dual die
• Timing – cycle time
– 1.875ns @ RL = 8
PR
PT
PR
PK
-1D
• Lead-free (RoHS-compliant) and halogen-free
packaging
• Special options
– Non-Automotive
blank
• Operating temperature range
– From –30°C to +85°C
– From –40°C to +85°C
– From –40°C to +105°C
blank
IT
AT
Table 1: Key Timing Parameters
Speed
Grade
Clock Rate Data Rate
(MHz)
(Mb/s/pin)
RL
WL
1D
533
1066
8
4
Table 2: S4 Configuration Addressing
Architecture
128 Meg x 64
256 Meg x 64
Die configuration
Row addressing
Column addressing
Number of die
Die per rank
16 Meg x 32 x 8 banks x 2 channel
32 Meg x 32 x 8 banks x 2 channel
16K A[13:0]
16K A[13:0]
1K A[9:0]
1K A[9:0]
2
1
1
4
2
2
Ranks per channel
1. A channel is a complete LPDRAM interface, including command/address and data pins.
Note:
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
1
Products and specifications discussed herein are subject to change by Micron without notice.
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Features
Figure 1: LPDDR2 Part Numbering
-
D
E
D
B
81 64
B
4
PR -1D
IT
F
Micron Technology
Packing Media
D = Dry Pack (Tray)
R = Tape and Reel
Type
D = Packaged device
Environment Code
F = Lead-free (RoHS-compliant)
and halogen-free
Product Family
B = Mobile LPDDR2 SDRAM
Operating Temperature
Density/Chip Select
81 = 8Gb/2-CS
A1 = 16Gb/4-CS (2-CS/channel)
Blank = –30°C to +85°C
IT = –40°C to +85°C
AT = –40°C to +105°C
Organization
64 = x64
Special options
Blank = Non-Automotive
Power Supply Interface
B = VDD1 = 1.8V, VDD2 = VDDQ = 1.2V,
Speed
1D = 1066 Mb/s
S4B device, HSUL
Package
PR = BGA for Pop
PT = BGA for Pop
PK = BGA for Pop
Revision
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.
Table 3: Package Codes and Descriptions
Package
Code
Ball
Count
# Chan-
nels
Die per
Package
Solder Ball
Composition
# Ranks
Size (mm)
PR
PT
PR
PK
216
216
216
220
1
1
2
1
2
2
2
2
12mm x 12mm x 0.80mm, 0.40 pitch
12mm x 12mm x 0.80mm, 0.40 pitch
12mm x 12mm x 1.00mm, 0.40 pitch
14mm x 14mm x 0.70mm, 0.50 pitch
DDP
DDP
QDP
DDP
SAC302
SAC302
SAC302
SAC302
1. DDP = dual-die package, QDP = quad-die package
Notes:
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
2
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Features
Contents
LPDDR2 Array Configuration ............................................................................................................................ 9
General Notes .............................................................................................................................................. 9
I
DD Specifications ........................................................................................................................................... 10
Package Block Diagrams ................................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 18
Ball Assignments ............................................................................................................................................ 21
Ball Descriptions ............................................................................................................................................ 24
Functional Description ................................................................................................................................... 25
Simplified State Diagram ................................................................................................................................ 26
Power-Up and Initialization ............................................................................................................................ 28
Voltage Ramp and Device Initialization ....................................................................................................... 28
Initialization After RESET (Without Voltage Ramp) ...................................................................................... 30
Power-Off Sequence ....................................................................................................................................... 30
Uncontrolled Power-Off Sequence .............................................................................................................. 31
Mode Register Definition ................................................................................................................................ 31
Mode Register Assignments and Definitions ................................................................................................ 31
Commands and Timing .................................................................................................................................. 42
ACTIVATE Command ..................................................................................................................................... 43
8-Bank Device Operation ............................................................................................................................ 44
Read and Write Access Modes ......................................................................................................................... 45
Burst READ Command ................................................................................................................................... 45
READs Interrupted by a READ ..................................................................................................................... 52
Burst WRITE Command .................................................................................................................................. 52
WRITEs Interrupted by a WRITE ................................................................................................................. 55
BURST TERMINATE Command ...................................................................................................................... 55
Write Data Mask ............................................................................................................................................. 57
PRECHARGE Command ................................................................................................................................. 58
READ Burst Followed by PRECHARGE ......................................................................................................... 59
WRITE Burst Followed by PRECHARGE ....................................................................................................... 60
Auto Precharge operation ........................................................................................................................... 61
READ Burst with Auto Precharge ................................................................................................................. 61
WRITE Burst with Auto Precharge ............................................................................................................... 62
REFRESH Command ...................................................................................................................................... 64
REFRESH Requirements ............................................................................................................................. 66
SELF REFRESH Operation ............................................................................................................................... 73
Partial-Array Self Refresh – Bank Masking .................................................................................................... 75
Partial-Array Self Refresh – Segment Masking .............................................................................................. 75
MODE REGISTER READ ................................................................................................................................. 76
Temperature Sensor ................................................................................................................................... 78
DQ Calibration ........................................................................................................................................... 80
MODE REGISTER WRITE Command ............................................................................................................... 82
MRW RESET Command .............................................................................................................................. 82
MRW ZQ Calibration Commands ................................................................................................................ 83
ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 85
Power-Down .................................................................................................................................................. 85
Deep Power-Down ......................................................................................................................................... 92
Input Clock Frequency Changes and Stop Events ............................................................................................. 93
Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 93
Input Clock Frequency Changes and Clock Stop with CKE HIGH .................................................................. 94
NO OPERATION Command ............................................................................................................................ 94
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
3
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Features
Truth Tables ................................................................................................................................................... 94
Absolute Maximum Ratings ........................................................................................................................... 102
Input/Output Capacitance ............................................................................................................................. 102
Electrical Specifications – IDD Specifications and Conditions ........................................................................... 103
AC and DC Operating Conditions ................................................................................................................... 106
AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 107
VREF Tolerances ......................................................................................................................................... 108
Input Signal .............................................................................................................................................. 110
AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 112
Single-Ended Requirements for Differential Signals .................................................................................... 113
Differential Input Crosspoint Voltage ......................................................................................................... 115
Input Slew Rate ......................................................................................................................................... 116
Output Characteristics and Operating Conditions ........................................................................................... 116
Single-Ended Output Slew Rate .................................................................................................................. 117
Differential Output Slew Rate ..................................................................................................................... 118
HSUL_12 Driver Output Timing Reference Load ......................................................................................... 120
Output Driver Impedance .............................................................................................................................. 121
Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 122
Output Driver Temperature and Voltage Sensitivity ..................................................................................... 123
Output Impedance Characteristics Without ZQ Calibration ......................................................................... 123
Clock Specification ........................................................................................................................................ 126
tCK(abs), tCH(abs), and tCL(abs) ................................................................................................................ 128
Clock Period Jitter .......................................................................................................................................... 128
Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 128
Cycle Time Derating for Core Timing Parameters ........................................................................................ 129
Clock Cycle Derating for Core Timing Parameters ....................................................................................... 129
Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 129
Clock Jitter Effects on READ Timing Parameters .......................................................................................... 129
Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 130
Refresh Requirements Parameters .................................................................................................................. 131
AC Timing ..................................................................................................................................................... 131
CA and CS_n Setup, Hold, and Derating .......................................................................................................... 137
Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 145
Revision History ............................................................................................................................................ 152
Rev. F – 08/16 ............................................................................................................................................ 152
Rev. E – 05/16 ............................................................................................................................................ 152
Rev. D – 03/16 ............................................................................................................................................ 152
Rev. C – 02/16 ............................................................................................................................................ 152
Rev. B – 01/15 ............................................................................................................................................ 152
Rev. A – 09/14 ............................................................................................................................................ 152
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
4
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Features
List of Figures
Figure 1: LPDDR2 Part Numbering ................................................................................................................... 2
Figure 2: Dual Die Single Rank, Dual Channel Package Block Diagram ............................................................. 16
Figure 3: Quad Die Dual Rank, Dual Channel Package Block Diagram ............................................................. 17
Figure 4: 216-Ball FBGA (12mm x 12mm x 0.8mm) – EDB8164B4PR, EDB8164B4PT ......................................... 18
Figure 5: 216-Ball FBGA (12mm x 12mm x 1.0mm) – EDBA164B2PR ................................................................ 19
Figure 6: 220-Ball FBGA (14mm x 14mm x 0.7mm) – EDB8164B4PK ................................................................ 20
Figure 7: 216-Ball Dual-Channel FBGA – 2 x 4Gb Die ...................................................................................... 21
Figure 8: 220-Ball Dual-Channel FBGA – 2 x 4Gb Die ...................................................................................... 22
Figure 9: 216-Ball Dual-Channel FBGA – 4 x 4Gb Die ...................................................................................... 23
Figure 10: Functional Block Diagram ............................................................................................................. 26
Figure 11: Simplified State Diagram ............................................................................................................... 27
Figure 12: Voltage Ramp and Initialization Sequence ...................................................................................... 30
Figure 13: Command and Input Setup and Hold ............................................................................................. 43
Figure 14: CKE Input Setup and Hold ............................................................................................................. 43
Figure 15: ACTIVATE Command .................................................................................................................... 44
Figure 16: tFAW Timing (8-Bank Devices) ....................................................................................................... 45
Figure 17: READ Output Timing – tDQSCK (MAX) ........................................................................................... 46
Figure 18: READ Output Timing – tDQSCK (MIN) ........................................................................................... 46
Figure 19: Burst READ – RL = 5, BL = 4, tDQSCK > tCK ..................................................................................... 47
Figure 20: Burst READ – RL = 3, BL = 8, tDQSCK < tCK ..................................................................................... 47
Figure 21: tDQSCKDL Timing ........................................................................................................................ 48
Figure 22: tDQSCKDM Timing ....................................................................................................................... 49
Figure 23: tDQSCKDS Timing ......................................................................................................................... 50
Figure 24: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 ......................................................... 51
Figure 25: Seamless Burst READ – RL = 3, BL = 4, tCCD = 2 .............................................................................. 51
Figure 26: READ Burst Interrupt Example – RL = 3, BL = 8, tCCD = 2 ................................................................. 52
Figure 27: Data Input (WRITE) Timing ........................................................................................................... 53
Figure 28: Burst WRITE – WL = 1, BL = 4 ......................................................................................................... 53
Figure 29: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4 ......................................................... 54
t
Figure 30: Seamless Burst WRITE – WL = 1, BL = 4, CCD = 2 ............................................................................ 54
t
Figure 31: WRITE Burst Interrupt Timing – WL = 1, BL = 8, CCD = 2 ................................................................ 55
Figure 32: Burst WRITE Truncated by BST – WL = 1, BL = 16 ............................................................................ 56
Figure 33: Burst READ Truncated by BST – RL = 3, BL = 16 ............................................................................... 57
Figure 34: Data Mask Timing ......................................................................................................................... 57
Figure 35: Write Data Mask – Second Data Bit Masked .................................................................................... 58
Figure 36: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(tRTP(MIN)/tCK) = 2 ................................ 59
Figure 37: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 3 ................................ 60
Figure 38: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 .................................................................. 61
Figure 39: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 2 ........................................ 62
Figure 40: WRITE Burst with Auto Precharge – WL = 1, BL = 4 .......................................................................... 63
Figure 41: tSRF Definition .............................................................................................................................. 67
Figure 42: Regular Distributed Refresh Pattern ............................................................................................... 69
Figure 43: Supported Transition from Repetitive REFRESH Burst .................................................................... 70
Figure 44: Nonsupported Transition from Repetitive REFRESH Burst .............................................................. 71
Figure 45: Recommended Self Refresh Entry and Exit ..................................................................................... 72
Figure 46: All-Bank REFRESH Operation ........................................................................................................ 73
Figure 47: Per-Bank REFRESH Operation ....................................................................................................... 73
Figure 48: SELF REFRESH Operation .............................................................................................................. 74
Figure 49: MRR Timing – RL = 3, tMRR = 2 ...................................................................................................... 76
Figure 50: READ to MRR Timing – RL = 3, tMRR = 2 ......................................................................................... 77
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
5
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Features
Figure 51: Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4 ................................................................... 78
Figure 52: Temperature Sensor Timing ........................................................................................................... 80
Figure 53: MR32 and MR40 DQ Calibration Timing – RL = 3, tMRR = 2 ............................................................. 81
t
Figure 54: MODE REGISTER WRITE Timing – RL = 3, MRW = 5 ....................................................................... 82
Figure 55: ZQ Timings ................................................................................................................................... 84
Figure 56: Power-Down Entry and Exit Timing ................................................................................................ 86
Figure 57: CKE Intensive Environment ........................................................................................................... 86
Figure 58: REFRESH-to-REFRESH Timing in CKE Intensive Environments ...................................................... 86
Figure 59: READ to Power-Down Entry ........................................................................................................... 87
Figure 60: READ with Auto Precharge to Power-Down Entry ............................................................................ 88
Figure 61: WRITE to Power-Down Entry ......................................................................................................... 89
Figure 62: WRITE with Auto Precharge to Power-Down Entry .......................................................................... 90
Figure 63: REFRESH Command to Power-Down Entry .................................................................................... 91
Figure 64: ACTIVATE Command to Power-Down Entry ................................................................................... 91
Figure 65: PRECHARGE Command to Power-Down Entry ............................................................................... 91
Figure 66: MRR Command to Power-Down Entry ........................................................................................... 92
Figure 67: MRW Command to Power-Down Entry .......................................................................................... 92
Figure 68: Deep Power-Down Entry and Exit Timing ....................................................................................... 93
Figure 69: VREF DC Tolerance and VREF AC Noise Limits ................................................................................. 108
Figure 70: LPDDR2-466 to LPDDR2-1066 Input Signal ................................................................................... 110
Figure 71: LPDDR2-200 to LPDDR2-400 Input Signal ..................................................................................... 111
Figure 72: Differential AC Swing Time and tDVAC .......................................................................................... 112
Figure 73: Single-Ended Requirements for Differential Signals ....................................................................... 114
Figure 74: VIX Definition ............................................................................................................................... 115
Figure 75: Differential Input Slew Rate Definition for CK_t, CK_c, DQS_t, and DQS_c ...................................... 116
Figure 76: Single-Ended Output Slew Rate Definition ..................................................................................... 118
Figure 77: Differential Output Slew Rate Definition ........................................................................................ 119
Figure 78: Overshoot and Undershoot Definition ........................................................................................... 120
Figure 79: HSUL_12 Driver Output Reference Load for Timing and Slew Rate ................................................. 121
Figure 80: Output Driver ............................................................................................................................... 122
Figure 81: Output Impedance = 240 Ohms, I-V Curves After ZQRESET ............................................................ 125
Figure 82: Output Impedance = 240 Ohms, I-V Curves After Calibration ......................................................... 126
Figure 83: Typical Slew Rate and tVAC – tIS for CA and CS_n Relative to Clock ................................................. 141
Figure 84: Typical Slew Rate – tIH for CA and CS_n Relative to Clock ............................................................... 142
Figure 85: Tangent Line – tIS for CA and CS_n Relative to Clock ...................................................................... 143
Figure 86: Tangent Line – tIH for CA and CS_n Relative to Clock ..................................................................... 144
Figure 87: Typical Slew Rate and tVAC – tDS for DQ Relative to Strobe ............................................................. 148
Figure 88: Typical Slew Rate – tDH for DQ Relative to Strobe ........................................................................... 149
Figure 89: Tangent Line – tDS for DQ with Respect to Strobe .......................................................................... 150
Figure 90: Tangent Line – tDH for DQ with Respect to Strobe .......................................................................... 151
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
6
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Features
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: S4 Configuration Addressing ............................................................................................................... 1
Table 3: Package Codes and Descriptions ......................................................................................................... 2
Table 4: IDD Specifications – Dual Die, Dual Channel ...................................................................................... 10
Table 5: IDD6 Full-Array Self Refresh Current at 45°C for Dual die product ........................................................ 12
Table 6: IDD6 Partial-Array Self Refresh Current at 85°C for Dual die product .................................................... 12
Table 7: IDD Specifications – Dual Die, Dual Channel ...................................................................................... 13
Table 8: IDD6 Partial-Array Self Refresh Current at 105°C Dual die for Dual die prodct ....................................... 15
Table 9: Ball/Pad Descriptions ....................................................................................................................... 24
Table 10: Initialization Timing Parameters ...................................................................................................... 30
Table 11: Power-Off Timing ............................................................................................................................ 31
Table 12: Mode Register Assignments ............................................................................................................. 32
Table 13: MR0 Device Information (MA[7:0] = 00h) ......................................................................................... 33
Table 14: MR0 Op-Code Bit Definitions .......................................................................................................... 33
Table 15: MR1 Device Feature 1 (MA[7:0] = 01h) .............................................................................................. 33
Table 16: MR1 Op-Code Bit Definitions .......................................................................................................... 33
Table 17: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC) ................................. 34
Table 18: No-Wrap Restrictions ...................................................................................................................... 35
Table 19: MR2 Device Feature 2 (MA[7:0] = 02h) .............................................................................................. 35
Table 20: MR2 Op-Code Bit Definitions .......................................................................................................... 36
Table 21: MR3 I/O Configuration 1 (MA[7:0] = 03h) ......................................................................................... 36
Table 22: MR3 Op-Code Bit Definitions .......................................................................................................... 36
Table 23: MR4 Device Temperature (MA[7:0] = 04h) ........................................................................................ 36
Table 24: MR4 Op-Code Bit Definitions .......................................................................................................... 37
Table 25: MR5 Basic Configuration 1 (MA[7:0] = 05h) ...................................................................................... 37
Table 26: MR5 Op-Code Bit Definitions .......................................................................................................... 37
Table 27: MR6 Basic Configuration 2 (MA[7:0] = 06h) ...................................................................................... 38
Table 28: MR6 Op-Code Bit Definitions .......................................................................................................... 38
Table 29: MR7 Basic Configuration 3 (MA[7:0] = 07h) ...................................................................................... 38
Table 30: MR7 Op-Code Bit Definitions .......................................................................................................... 38
Table 31: MR8 Basic Configuration 4 (MA[7:0] = 08h) ...................................................................................... 38
Table 32: MR8 Op-Code Bit Definitions .......................................................................................................... 38
Table 33: MR9 Test Mode (MA[7:0] = 09h) ....................................................................................................... 39
Table 34: MR10 Calibration (MA[7:0] = 0Ah) ................................................................................................... 39
Table 35: MR10 Op-Code Bit Definitions ........................................................................................................ 39
Table 36: MR[11:15] Reserved (MA[7:0] = 0Bh–0Fh) ......................................................................................... 40
Table 37: MR16 PASR Bank Mask (MA[7:0] = 010h) .......................................................................................... 40
Table 38: MR16 Op-Code Bit Definitions ........................................................................................................ 40
Table 39: MR16 Bank and OP corresponding table .......................................................................................... 40
Table 40: MR17 PASR Segment Mask (MA[7:0] = 011h) .................................................................................... 41
Table 41: MR17 PASR Segment Mask Definitions (1Gb - 8Gb only) ................................................................... 41
Table 42: MR17 PASR Row Address Ranges in Masked Segments ...................................................................... 41
Table 43: Reserved Mode Registers ................................................................................................................. 42
Table 44: MR32 DQ Calibration Pattern A (MA[7:0] = 20H) ............................................................................... 42
Table 45: MR40 DQ Calibration Pattern B (MA[7:0] = 28H) ............................................................................... 42
Table 46: MR63 RESET (MA[7:0] = 3Fh) – MRW Only ....................................................................................... 42
Table 47: Bank Selection for PRECHARGE by Address Bits ............................................................................... 59
Table 48: PRECHARGE and Auto Precharge Clarification ................................................................................. 63
Table 49: REFRESH Command Scheduling Separation Requirements .............................................................. 65
Table 50: Bank and Segment Masking Example ............................................................................................... 75
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
7
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Features
Table 51: Temperature Sensor Definitions and Operating Conditions .............................................................. 79
Table 52: Data Calibration Pattern Description ............................................................................................... 82
Table 53: Truth Table for MRR and MRW ........................................................................................................ 82
Table 54: Command Truth Table .................................................................................................................... 94
Table 55: CKE Truth Table .............................................................................................................................. 96
Table 56: Current State Bank n to Command to Bank n Truth Table ................................................................. 97
Table 57: Current State Bank n to Command to Bank m Truth Table ................................................................ 99
Table 58: DM Truth Table .............................................................................................................................. 101
Table 59: Absolute Maximum DC Ratings ...................................................................................................... 102
Table 60: Input/Output Capacitance ............................................................................................................. 102
Table 61: Switching for CA Input Signals ........................................................................................................ 103
Table 62: Switching for IDD4R ......................................................................................................................... 103
Table 63: Switching for IDD4W ........................................................................................................................ 104
Table 64: IDD Specification Parameters and Operating Conditions .................................................................. 104
Table 65: Recommended DC Operating Conditions ....................................................................................... 106
Table 66: Input Leakage Current ................................................................................................................... 106
Table 67: Operating Temperature Range ........................................................................................................ 107
Table 68: Single-Ended AC and DC Input Levels for CA and CS_n Inputs ......................................................... 107
Table 69: Single-Ended AC and DC Input Levels for CKE ................................................................................ 107
Table 70: Single-Ended AC and DC Input Levels for DQ and DM ..................................................................... 108
Table 71: Differential AC and DC Input Levels ................................................................................................ 112
Table 72: CK_t/CK_c and DQS_t/DQS_c Time Requirements Before Ringback (tDVAC) ................................... 113
Table 73: Single-Ended Levels for CK_t, CK_c, DQS_t, DQS_c ......................................................................... 114
Table 74: Crosspoint Voltage for Differential Input Signals (CK_t, CK_c, DQS_t, DQS_c) .................................. 115
Table 75: Differential Input Slew Rate Definition ............................................................................................ 116
Table 76: Single-Ended AC and DC Output Levels .......................................................................................... 116
Table 77: Differential AC and DC Output Levels ............................................................................................. 117
Table 78: Single-Ended Output Slew Rate Definition ...................................................................................... 117
Table 79: Single-Ended Output Slew Rate ...................................................................................................... 118
Table 80: Differential Output Slew Rate Definition ......................................................................................... 119
Table 81: Differential Output Slew Rate ......................................................................................................... 119
Table 82: AC Overshoot/Undershoot Specification ......................................................................................... 120
Table 83: Output Driver DC Electrical Characteristics with ZQ Calibration ...................................................... 122
Table 84: Output Driver Sensitivity Definition ................................................................................................ 123
Table 85: Output Driver Temperature and Voltage Sensitivity ......................................................................... 123
Table 86: Output Driver DC Electrical Characteristics Without ZQ Calibration ................................................ 123
Table 87: I-V Curves ..................................................................................................................................... 124
Table 88: Definitions and Calculations .......................................................................................................... 127
Table 89: tCK(abs), tCH(abs), and tCL(abs) Definitions ................................................................................... 128
Table 90: Refresh Requirement Parameters (Per Density) ............................................................................... 131
Table 91: AC Timing ..................................................................................................................................... 131
Table 92: CA and CS_n Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) .......................................... 138
Table 93: CA and CS_n Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate) .......................................... 138
t
Table 94: Derating Values for AC/DC-Based IS/tIH (AC220) ........................................................................... 139
t
Table 95: Derating Values for AC/DC-Based IS/tIH (AC300) ........................................................................... 139
t
Table 96: Required Time for Valid Transition – VAC > VIH(AC) and < VIL(AC) ....................................................... 139
Table 97: Data Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) ....................................................... 145
Table 98: Data Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate) ....................................................... 146
t
Table 99: Derating Values for AC/DC-Based DS/tDH (AC220) ........................................................................ 146
t
Table 100: Derating Values for AC/DC-Based DS/tDH (AC300) ....................................................................... 147
t
Table 101: Required Time for Valid Transition – VAC > VIH(AC) or < VIL(AC) ....................................................... 147
09005aef85eb530a
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8
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
LPDDR2 Array Configuration
LPDDR2 Array Configuration
The 4Gb Mobile Low-Power DDR2 SDRAM (LPDDR2) is a high-speed CMOS, dynamic
random-access memory containing 4,294,967,296-bits. The device is internally config-
ured as an eight-bank DRAM. Each of the x16’s 536,870,912-bit banks is organized as
16,384 rows by 2048 columns by 16 bits. Each of the x32’s 536,870,912-bit banks is or-
ganized as 16,384 rows by 1024 columns by 32 bits.
General Notes
Throughout the data sheet, figures and text refer to DQs as “DQ.” DQ should be inter-
preted as any or all DQ collectively, unless specifically stated otherwise.
“DQS” and “CK” should be interpreted as DQS_t, DQS_c and CK_t, CK_c respectively,
unless specifically stated otherwise. “BA” includes all BA pins used for a given density.
Complete functionality may be described throughout the entire document. Any page or
diagram may have been simplified to convey a topic and may not be inclusive of all re-
quirements.
Any specific requirement takes precedence over a general statement.
Any functionality not specifically stated herein is considered undefined, illegal, is not
supported, and will result in unknown operation.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
DD Specifications
I
IDD Specifications
Table 4: IDD Specifications – Dual Die, Dual Channel
VDD2, VDDQ = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –40°C to +85°C
Speed
Symbol
IDD01
Supply
VDD1
1066
16
Unit Parameter/Condition
mA All devices in operating one bank active-precharge
Conditions for operating devices are:
tCK = tCK(avg) MIN; tRC = tRC (MIN);
IDD02
VDDQVDDQ
100
CKE is HIGH; CS_n is HIGH between valid commands;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD2P1
IDD2P2
VDD1
0.8
1.8
mA All devices in idle power-down standby current
tCK = tCK(avg) MIN; CKE is LOW;
CS_n is HIGH; All banks are idle;
VDDQVDDQ
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD2PS1
IDD2PS2
VDD1
0.8
1.8
mA All devices in idle power-down standby current with clock
stop
VDDQVDDQ
CK_t = LOW, CK_c = HIGH; CKE is LOW;
CS_n is HIGH; All banks are idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD2N1
IDD2N2
VDD1
1.2
26
mA All devices in idle non power-down standby current.
tCK = tCK(avg) MIN; CKE is HIGH;
CS_n is HIGH; All banks idle;
VDDQVDDQ
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD2NS1
IDD2NS2
VDD1
1.2
12
mA All devices in idle non power-down standby current with
clock stop
VDDQVDDQ
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
CS_n is HIGH; All banks are idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD3P1
IDD3P2
VDD1
1.6
10
mA All devices in active power-down standby current
tCK = tCK(avg) MIN; CKE is LOW;
VDDQVDDQ
CS_n is HIGH; One bank is active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD3PS1
IDD3PS2
VDD1
1.6
10
mA All devices in active power-down standby current with
clock stop
VDDQVDDQ
CK_t = LOW, CK_c = HIGH; CKE is LOW;
CS_n is HIGH; One bank is active;
CA bus inputs are STABLE;
Data bus inputs are STABLE
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
DD Specifications
I
Table 4: IDD Specifications – Dual Die, Dual Channel (Continued)
VDD2, VDDQ = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –40°C to +85°C
Speed
Symbol
IDD3N1
Supply
VDD1
1066
2.4
Unit Parameter/Condition
mA All devices in active non power-down standby current
tCK = tCK(avg) MIN; CKE is HIGH;
IDD3N2
VDDQVDDQ
38
CS_n is HIGH; One bank active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD3NS1
IDD3NS2
VDD1
2.4
24
mA All devices in active non power-down standby current
with clock stop
VDDQVDDQ
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
CS_n is HIGH; One bank is active;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD4R1
IDD4R2
VDD1
4
mA All devices in operating burst read
tCK = tCK(avg) MIN;
VDDQVDDQ
840
CS_n is HIGH between valid commands;
One bank is active; BL = 4; RL = RL (MIN);
CA bus inputs are SWITCHING;
50% data change occurs at each burst transfer
IDD4W1
IDD4W2
VDD1
4
mA All devices in operating burst write
tCK = tCK(avg) MIN;
VDDQVDDQ
300
CS_n is HIGH between valid commands;
One bank is active; BL = 4; WL = WL (MIN);
CA bus inputs are SWITCHING;
50% data change occurs at each burst transfer
IDD51
IDD52
VDD1
40
mA All devices in all bank auto-refresh
tCK = tCK(avg) MIN;
VDDQVDDQ
240
CKE is HIGH between valid commands;
tRC = tRFCab (MIN); Burst refresh;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD5AB1
IDD5AB2
VDD1
8
mA All devices in all bank auto-refresh
tCK = tCK(avg) MIN;
VDDQVDDQ
40
CKE is HIGH between valid commands;
tRC = tREFI;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD5PB1
IDD5PB2
VDD1
8
mA All devices in per bank auto-refresh
tCK = tCK(avg) MIN;
VDDQVDDQ
40
CKE is HIGH between valid commands;
tRC = tREFIpb;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
1. Published IDD values are the maximum of the distribution of the arithmetic mean.
2. IDD current specifications are tested after the device is properly initialized.
Notes:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
DD Specifications
I
3. VDD2 and VDDQ are connected internally in the package.
4. The Quad die product IDD for each channel will be the sum of the IDD's for the state of
operation for each rank (CS) in the channel.
Table 5: IDD6 Full-Array Self Refresh Current at 45°C for Dual die product
VDD2, VDDQ = 1.14–1.30V; VDD1 = 1.70–1.95V
PASR
Supply
Value
400
Unit
Parameters/Conditions
Full array
VDD1
μA
All devices in self refresh
CK_t = LOW, CK_c = HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE
V
DDQVDDQ
VDD1
VDDQVDDQ
VDD1
VDDQVDDQ
VDD1
1600
320
1/2 array
1/4 array
1/8 array
1000
260
600
240
VDDQVDDQ
400
1. IDD6 45°C is the typical of the distribution of the arithmetic mean, Quad die product will
be double these values when all die are in self refresh mode.
Note:
Table 6: IDD6 Partial-Array Self Refresh Current at 85°C for Dual die product
VDD2, VDDQ = 1.14–1.30V; VDD1 = 1.70–1.95V
PASR
Supply
Value
1800
6400
1300
4400
1100
3400
1000
2800
Unit
Parameters/Conditions
Full array
VDD1
μA
All devices in self refresh
CK_t = LOW, CK_c = HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE
V
DDQVDDQ
VDD1
VDDQVDDQ
VDD1
VDDQVDDQ
VDD1
1/2 array
1/4 array
1/8 array
VDDQVDDQ
1. IDD6 85°C is the maximum of the distribution of the arithmetic mean, Quad die product
will be double these values when all die are in self refresh mode.
Note:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
DD Specifications
I
Table 7: IDD Specifications – Dual Die, Dual Channel
VDD2, VDDQ = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –40°C to +105°C
Speed
Symbol
IDD01
Supply
VDD1
1066
16
Unit
Parameter/Condition
mA
All devices in operating one bank active-precharge
Conditions for operating devices are:
tCK = tCK(avg) MIN; tRC = tRC (MIN);
CKE is HIGH; CS_n is HIGH between valid commands;
CA bus inputs are SWITCHING;
IDD02
VDD2, VDDQ
100
Data bus inputs are STABLE
IDD2P1
IDD2P2
VDD1
0.8
1.8
mA
mA
All devices in idle power-down standby current
tCK = tCK(avg) MIN; CKE is LOW;
CS_n is HIGH; All banks are idle;
CA bus inputs are SWITCHING;
VDD2, VDDQ
Data bus inputs are STABLE
IDD2PS1
IDD2PS2
VDD1
0.8
1.8
All devices in idle power-down standby current with
clock stop
VDD2, VDDQ
CK_t = LOW, CK_c = HIGH; CKE is LOW;
CS_n is HIGH; All banks are idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD2N1
IDD2N2
VDD1
1.2
30
mA
mA
All devices in idle non power-down standby current.
tCK = tCK(avg) MIN; CKE is HIGH;
CS_n is HIGH; All banks idle;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
VDD2, VDDQ
IDD2NS1
IDD2NS2
VDD1
1.2
16
All devices in idle non power-down standby current
with clock stop
VDD2, VDDQ
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
CS_n is HIGH; All banks are idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD3P1
IDD3P2
VDD1
1.8
14
mA
mA
All devices in active power-down standby current
tCK = tCK(avg) MIN; CKE is LOW;
CS_n is HIGH; One bank is active;
CA bus inputs are SWITCHING;
VDD2, VDDQ
Data bus inputs are STABLE
IDD3PS1
IDD3PS2
VDD1
1.8
14
All devices in active power-down standby current with
clock stop
VDD2, VDDQ
CK_t = LOW, CK_c = HIGH; CKE is LOW;
CS_n is HIGH; One bank is active;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD3N1
IDD3N2
VDD1
2.8
44
mA
All devices in active non power-down standby current
tCK = tCK(avg) MIN; CKE is HIGH;
CS_n is HIGH; One bank active;
VDD2, VDDQ
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
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13
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
DD Specifications
I
Table 7: IDD Specifications – Dual Die, Dual Channel (Continued)
VDD2, VDDQ = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –40°C to +105°C
Speed
Symbol
IDD3NS1
IDD3NS2
Supply
VDD1
1066
2.8
Unit
Parameter/Condition
mA
All devices in active non power-down standby current
with clock stop
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
CS_n is HIGH; One bank is active;
CA bus inputs are STABLE;
VDD2, VDDQ
30
Data bus inputs are STABLE
IDD4R1
IDD4R2
VDD1
4
mA
mA
mA
mA
mA
All devices in operating burst read
tCK = tCK(avg) MIN;
CS_n is HIGH between valid commands;
One bank is active; BL = 4; RL = RL (MIN);
CA bus inputs are SWITCHING;
VDD2, VDDQ
840
50% data change occurs at each burst transfer
IDD4W1
IDD4W2
VDD1
4
All devices in operating burst write
tCK = tCK(avg) MIN;
CS_n is HIGH between valid commands;
One bank is active; BL = 4; WL = WL (MIN);
CA bus inputs are SWITCHING;
VDD2, VDDQ
300
50% data change occurs at each burst transfer
IDD51
IDD52
VDD1
40
All devices in all bank auto-refresh
tCK = tCK(avg) MIN;
CKE is HIGH between valid commands;
tRC = tRFCab (MIN); Burst refresh;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
VDD2, VDDQ
240
IDD5AB1
IDD5AB2
VDD1
12
56
All devices in all bank auto-refresh
tCK = tCK(avg) MIN;
CKE is HIGH between valid commands;
tRC = tREFI;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
VDD2, VDDQ
IDD5PB1
IDD5PB2
VDD1
12
56
All devices in per bank auto-refresh
tCK = tCK(avg) MIN;
CKE is HIGH between valid commands;
tRC = tREFIpb;
VDD2, VDDQ
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
1. Published IDD values are the maximum of the distribution of the arithmetic mean.
2. IDD current specifications are tested after the device is properly initialized.
3. VDD2 and VDDQ are connected internally in the package.
Notes:
4. The Quad die product IDD for each channel will be the sum of the IDD's for the state of
operation for each rank (CS) in the channel.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
DD Specifications
I
Table 8: IDD6 Partial-Array Self Refresh Current at 105°C Dual die for Dual die prodct
VDD2, VDDQ = 1.14–1.30V; VDD1 = 1.70–1.95V
PASR
Supply
Value
4800
28000
3200
15600
2200
9600
1800
6400
Unit
Parameters/Conditions
Full array
VDD1
μA
All devices in self refresh
CK_t = LOW, CK_c = HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE
V
DDQVDDQ
VDD1
VDDQVDDQ
VDD1
VDDQVDDQ
VDD1
1/2 array
1/4 array
1/8 array
VDDQVDDQ
1. IDD6 105°C is the maximum of the distribution of the arithmetic mean, Quad die product
will be double these values when all die are in self refresh mode.
Note:
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15
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Package Block Diagrams
Package Block Diagrams
Figure 2: Dual Die Single Rank, Dual Channel Package Block Diagram
_A/B V _A/B _A, _B V _A/B
V
V
DDQ
DD2
SS
DD1
V
_A, B
V
_A, B
REFCA
REFDQ
ZQ_A
CS_n_A
CKE_A
CK_t_A
CK_c_A
LPDDR2
Die 0
DM[3:0]_A
DDQ[31:0]_A,
DQS[3:0]_t_A,
DQS[3:0]_c_A
CA[9:0]_A
x32
ZQ_B
CS_n_B
CKE_B
CK_t_B
CK_c_B
LPDDR2
Die 1
DM[3:0]_B
DQ[31:0]_B,
DQS[3:0]_t_B,
DQS[3:0]_c_B
CA[9:0]_B
x32
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16
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Package Block Diagrams
Figure 3: Quad Die Dual Rank, Dual Channel Package Block Diagram
VDD1_A/B VDD2_A/B VDDQ_A, _B VSS_A/B
VREFCA_A, B
CS1_n_A
CKE1_A
VREFDQ_A, B
ZQ_A
CS0_n_A
CKE0_A
CK_t_A
CK_c_A
LPDDR2
Die 0
LPDDR2
Die 2
DM[3:0]_A
CA[9:0]_A
DQ[31:0]_A,
DQS[3:0]_t_A,
DQS[3:0]_c_A
x32
x32
CS1_n_B
CKE1_B
ZQ_B
CS0_n_B
CKE0_B
CK_t_B
CK_c_B
LPDDR2
Die 1
LPDDR2
Die 3
DM[3:0]_B
CA[9:0]_B
x32
x32
DQ[31:0]_B,
DQS[3:0]_t_B,
DQS[3:0]_c_B
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17
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Package Dimensions
Package Dimensions
Figure 4: 216-Ball FBGA (12mm x 12mm x 0.8mm) – EDB8164B4PR, EDB8164B4PT
12.00 0.10
0.15 S
B
Index mark
0.15 S
0.08
A
S
0.20
0.68 0.12
S
S
0.18 0.03
216- 0.25 0.05
M
S AB
0.06
B
A
Index mark
0.4
11.20
1. All dimensions are in millimeters.
Note:
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18
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Package Dimensions
Figure 5: 216-Ball FBGA (12mm x 12mm x 1.0mm) – EDBA164B2PR
12.00 0.10
Index mark
0.15 S
B
0.15 S
0.08
A
S
0.20
0.88 0.12
S
S
0.18 0.03
216- 0.25 0.05
M
S AB
0.06
B
A
Index mark
0.4
11.20
1. All dimensions are in millimeters.
Note:
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19
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Package Dimensions
Figure 6: 220-Ball FBGA (14mm x 14mm x 0.7mm) – EDB8164B4PK
14.0 0.1
Index mark
0.20
S B
0.20
S A
0.60 0.10
0.10
S
S
0.08
S
0.25 0.05
220- 0.325 0.05
0.05 M
S AB
B
A
Index mark
0.5
13.0
1. All dimensions are in millimeters.
Note:
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20
Ball Assignments
Figure 7: 216-Ball Dual-Channel FBGA – 2 x 4Gb Die
ꢄ
ꢃ
ꢈ
ꢋ
ꢉ
ꢅ
ꢊ
ꢌ
ꢆ
ꢄꢇ
ꢄꢄ
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ꢄꢈ
ꢄꢋ
ꢄꢉ
ꢄꢅ
ꢄꢊ
ꢄꢌ
ꢄꢆ
ꢃꢇ
ꢃꢄ
ꢃꢃ
ꢃꢈ
'46ꢇBWB$ '4ꢊB$
966
ꢃꢋ
ꢃꢉ
ꢃꢅ
ꢃꢊ
ꢃꢌ
966
ꢃꢆ
1&
9''ꢄ
$
%
&
'
(
)
*
+
-
1&
966
9''ꢃ
'4ꢈꢇB$ '4ꢃꢆB$
966
'4ꢃꢅB$ '4ꢃꢉB$
9''4 '4ꢃꢋB$
966
9''4
'46ꢈBFB$
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966
966
9''ꢃ
9''ꢃ
'4ꢄꢄB$ '4ꢄꢇB$ '4ꢆB$ '46ꢄBWB$ '0ꢄB$
9''4
'4ꢅB$
9''4
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'4ꢉB$
'4ꢈB$
'4ꢃB$
966
1&
'4ꢈꢄB$
9''4
'4ꢃꢌB$ '4ꢃꢊB$
'46ꢈBWB$ '0ꢈB$ '4ꢄꢉB$
9''4
95()'4B$
'4ꢄꢃB$
9''4
'4ꢌB$ '46ꢄBFB$
966
'0ꢇB$ '46ꢇBFB$
1&
966
9''ꢄ
'4ꢄꢊB%
'4ꢄꢅB%
9''4
9''ꢄ
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966
9''ꢃ
9''4
'4ꢇB$
9''4
'4ꢄꢌB% '4ꢄꢆB%
966
'4ꢃꢇB%
9''4
'0ꢃB$
'4ꢃꢄB%
'46ꢃBWB$ '46ꢃBFB$
'4ꢃꢃB% '4ꢃꢈB%
966 9''4
'46ꢃBFB% '46ꢃBWB%
966
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'4ꢃꢃB$
9''4
.
/
'4ꢃꢇB$ '4ꢃꢄB$
'0ꢃB%
'4ꢄB%
'4ꢃB%
966
'4ꢇB%
966
'4ꢄꢆB$
9''4
966
0
'4ꢄꢌB$
1
3
9''ꢄ
'4ꢄꢅB$ '4ꢄꢊB$
9''ꢄ
&$ꢇB%
&$ꢄB%
966
9''ꢃ
966
1&
95()'4B%
5
9''ꢄ
7
9''ꢃ
9''ꢃ
'4ꢈB%
966
8
9''4
95()&$B% &$ꢃB%
9
'4ꢋB%
'4ꢅB%
9''4
966
&$ꢋB%
&6BQB%
966
&$ꢈB%
1&
:
<
'4ꢉB%
'4ꢊB%
1&
$$
$%
$&
'46ꢇBWB% '46ꢇBFB%
&.(B%
'0ꢇB%
9''4
966
&.BWB% &.BFB%
1&
&$ꢊB%
&$ꢌB%
966
'0ꢄB%
&$ꢉB%
&$ꢅB%
1&
$' '46ꢄBFB% '46ꢄBWB%
$(
$)
$*
$+
$-
'4ꢌB%
'4ꢆB%
966
9''4
&$ꢆB%
=4B%
966
'4ꢄꢇB% '4ꢄꢄB%
9''ꢃ
9''ꢄ
966
966
1&
ꢄ
9''ꢄ
966
ꢃ
9''ꢃ
'4ꢄꢃB%
ꢈ
'4ꢄꢈB%
9''4
ꢋ
966
'4ꢄꢋB%
ꢉ
'4ꢄꢉB% '0ꢈB% '46ꢈBWB%
9''4 966
ꢅ ꢊ
9''4
'4ꢃꢅB% '4ꢃꢊB%
9''4
'4ꢈꢇB%
966
9''ꢃ
9''ꢄ
95()&$B$ &$ꢆB$
966
&$ꢌB$
ꢄꢌ
&$ꢊB$
1&
&$ꢅB$ &.BFB$
&$ꢉB$ &.BWB$
1&
966
ꢃꢃ
&.(B$ &6BQB$
&$ꢈB$
&$ꢋB$
ꢃꢉ
&$ꢃB$
1&
&$ꢄB$
&$ꢇB$
ꢃꢊ
'46ꢈBFB% '4ꢃꢋB% '4ꢃꢉB%
ꢄꢇ
966
ꢄꢄ
'4ꢃꢌB% '4ꢃꢆB% '4ꢈꢄB%
ꢄꢃ ꢄꢈ ꢄꢋ
966
ꢄꢅ
=4B$
ꢄꢊ
1&
ꢃꢈ
1&
ꢃꢋ
1&
ꢌ
ꢆ
ꢄꢉ
ꢄꢆ
ꢃꢇ
ꢃꢄ
ꢃꢅ
ꢃꢌ
ꢃꢆ
7RSꢀ9LHZꢀꢁEDOOꢀGRZQꢂ
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6XSSO\
*URXQG
Ball Assignments
Figure 8: 220-Ball Dual-Channel FBGA – 2 x 4Gb Die
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
V
V
V
V
V
V
V
A
B
NC
V
V
V
SS
DQ29_B DQ28_B
DQ25_B DQ24_B DQS3_c_B DM3_B DQ15_B
V
DQ13_B DQ11_B
DQ9_B DQS1_c_B DM1_B
SS
V
DQS0_c_B DQ7_B
NC
A
SS
SS
SS
SS
SS
SS
NC
DQ16_A DQ17_A
DD2
SS
DD2
V
V
V
DQ12_B
V
V
V
DQ6_B
NC
V
DD2
DQ31_B DQ30_B
V
DQ27_B DQ26_B
V
DQS3_t_B
V
DQ14_B
DQ10_B DQ8_B DQS1_t_B
REFDQ_B
DM0_B DQS0_t_B
V
DDQ
B
DD1
DDQ
SS
DDQ
DDQ
DD1
DDQ
DDQ
DDQ
DQ5_B
DQ4_B
C
C
V
DQ3_B
D
DQ18_A
V
DDQ
D
DDQ
V
DQ2_B
DM2_B
DQ1_B
V
E
DQ20_A DQ19_A
E
SS
SS
V
V
DQ21_A
F
DQ0_B
F
DDQ
DDQ
V
V
DQS2_t_B
DQS2_c_B
G
SS
DQ22_A DQ23_A
G
SS
H
DQS2_t_A DQS2_c_A
DM2_A DQ0_A
DQ23_B
H
V
J
V
DQ21_B DQ22_B
J
SS
SS
V
V
DQ20_B
K
DQ1_A
K
DDQ
DDQ
V
V
L
DQ2_A
DQ3_A
DQ6_A
DQ19_B DQ18_B
L
SS
SS
V
DQ17_B
M
N
DQ4_A
V
M
N
DDQ
DD2
V
V
V
DQ5_A
DQ16_B
CA1_A
DDQ
SS
SS
V
NC
CA0_A
P
DQ7_A
P
DDQ
V
DQS0_c_A DQS0_t_A
CA2_A
V
R
R
SS
SS
V
CA3_A
NC
CA4_A
T
DM0_A
DDQ
T
V
V
V
V
V
U
REFDQ_A
CS0_n_A
U
SS
SS
SS
NC
V
CKE0_A
V
V
DD2
DD1
V
V
V
W
Y
DM1_A
CK_c_A CK_t_A
NC
W
Y
SS
SS
DD2
CA5_A
DQS1_c_A DQS1_t_A
V
V
V
AA
AB
AC
AD
AE
AF
AG
DQ9_A DQ10_A
REFCA _A CA6_A
AA
AB
AC
AD
AE
AF
AG
SS
DD2
V
V
CA7_A
DQ8_A
SS
DDQ
V
V
DQ11_A DQ12_A
CA8_A
CA9_A
NC
SS
SS
V
DQ13_A DQ14_A
DD2
V
DQ15_A
V
SS
ZQ_A
DD1
V
V
V
CA9_B
CA8_B
14
V
V
REFCA_B
V
V
V
V
DM3_A DQS3_t_A DQS3_c_A DQ25_A DQ27_A
DQ29_A DQ31_A
DD2
NC
CA7_B
CA6_B
15
NC
CK_t_B
CK_c_B CKE0_B
19 20
NC
CS0_n_B
NC
CA4_B
NC
CA3_B
23
CA2_B
CA1_B
24
CA0_B
DDQ
DD1
DD2
DD2
SS
SS
DDQ
V
V
V
V
V
V
V
V
NC
1
DQ24_A DQ26_A
V
DQ28_A DQ30_A
V
V
ZQ_B
CA5_B
16
V
DDQ
4
NC
27
DD2
SS
SS
SS
SS
SS
DD1
SS
SS
SS
SS
2
3
5
6
7
8
9
10
11
12
13
17
18
21
22
25
26
Channel a (_A)
Channel b (_B)
Supply
Ground
Top View (ball down)
Ball Assignments
Figure 9: 216-Ball Dual-Channel FBGA – 4 x 4Gb Die
ꢄ
ꢃ
ꢈ
ꢋ
ꢉ
ꢅ
ꢊ
ꢌ
ꢆ
ꢄꢇ
ꢄꢄ
ꢄꢃ
ꢄꢈ
ꢄꢋ
ꢄꢉ
ꢄꢅ
ꢄꢊ
ꢄꢌ
ꢄꢆ
ꢃꢇ
ꢃꢄ
ꢃꢃ
ꢃꢈ
'46ꢇBWB$ '4ꢊB$
966
ꢃꢋ
ꢃꢉ
ꢃꢅ
ꢃꢊ
ꢃꢌ
966
ꢃꢆ
1&
9''ꢄ
$
%
&
'
(
)
*
+
-
1&
966
9''ꢃ
'4ꢈꢇB$ '4ꢃꢆB$
966
'4ꢃꢅB$ '4ꢃꢉB$
9''4 '4ꢃꢋB$
966
9''4
'46ꢈBFB$
966
'4ꢄꢋB$ '4ꢄꢈB$
966
966
9''ꢃ
9''ꢃ
'4ꢄꢄB$ '4ꢄꢇB$ '4ꢆB$ '46ꢄBWB$ '0ꢄB$
9''4
'4ꢅB$
9''4
'4ꢋB$
'4ꢉB$
'4ꢈB$
'4ꢃB$
966
1&
'4ꢈꢄB$
9''4
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'46ꢈBWB$ '0ꢈB$ '4ꢄꢉB$
9''4
95()'4B$
'4ꢄꢃB$
9''4
'4ꢌB$ '46ꢄBFB$
966
'0ꢇB$ '46ꢇBFB$
1&
966
9''ꢄ
'4ꢄꢊB%
'4ꢄꢅB%
9''4
9''ꢄ
'4ꢄB$
966
9''ꢃ
9''4
'4ꢇB$
9''4
'4ꢄꢌB% '4ꢄꢆB%
966
'4ꢃꢇB%
9''4
'0ꢃB$
'4ꢃꢄB%
'46ꢃBWB$ '46ꢃBFB$
'4ꢃꢃB% '4ꢃꢈB%
966 9''4
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966
'4ꢃꢈB$
'4ꢃꢃB$
9''4
.
/
'4ꢃꢇB$ '4ꢃꢄB$
'0ꢃB%
'4ꢄB%
'4ꢃB%
966
'4ꢇB%
966
'4ꢄꢆB$
9''4
966
0
'4ꢄꢌB$
1
3
9''ꢄ
'4ꢄꢅB$ '4ꢄꢊB$
9''ꢄ
966
9''ꢃ
966
1&
95()'4B%
5
9''ꢄ
&$ꢇB%
&$ꢄB%
7
9''ꢃ
9''ꢃ
'4ꢈB%
966
8
9''4
95()&$B% &$ꢃB%
966 &$ꢈB%
9
'4ꢋB%
'4ꢅB%
9''4
:
<
'4ꢉB%
'4ꢊB%
&$ꢋB% &6ꢄBQB%
&6ꢇBQB% &.(ꢄB%
$$
$%
$&
'46ꢇBWB% '46ꢇBFB%
966
&.(ꢇB%
'0ꢇB%
9''4
966
&.BWB% &.BFB%
'0ꢄB%
1&
&$ꢊB%
&$ꢌB%
966
&$ꢉB%
&$ꢅB%
1&
$' '46ꢄBFB% '46ꢄBWB%
$(
$)
$*
$+
$-
'4ꢌB%
'4ꢆB%
966
9''4
&$ꢆB%
=4B%
966
'4ꢄꢇB% '4ꢄꢄB%
9''ꢃ
9''ꢄ
966
966
1&
ꢄ
9''ꢄ
966
ꢃ
9''ꢃ
'4ꢄꢃB%
ꢈ
'4ꢄꢈB%
9''4
ꢋ
966
'4ꢄꢋB%
ꢉ
'4ꢄꢉB% '0ꢈB% '46ꢈBWB%
9''4 966
ꢅ ꢊ
9''4
'4ꢃꢅB% '4ꢃꢊB%
9''4
'4ꢈꢇB%
966
9''ꢃ
9''ꢄ
95()&$B$ &$ꢆB$
966
&$ꢌB$
ꢄꢌ
&$ꢊB$
1&
&$ꢅB$ &.BFB$
&$ꢉB$ &.BWB$
1&
966
ꢃꢃ
&.(ꢇB$ &6ꢇBQB$ &$ꢈB$
&.(ꢄB$ &6ꢄBQB$ &$ꢋB$
&$ꢃB$
1&
&$ꢄB$
&$ꢇB$
ꢃꢊ
'46ꢈBFB% '4ꢃꢋB% '4ꢃꢉB%
ꢄꢇ
966
ꢄꢄ
'4ꢃꢌB% '4ꢃꢆB% '4ꢈꢄB%
ꢄꢃ ꢄꢈ ꢄꢋ
966
ꢄꢅ
=4B$
ꢄꢊ
1&
ꢌ
ꢆ
ꢄꢉ
ꢄꢆ
ꢃꢇ
ꢃꢄ
ꢃꢈ
ꢃꢋ
ꢃꢉ
ꢃꢅ
ꢃꢌ
ꢃꢆ
7RSꢀ9LHZꢀꢁEDOOꢀGRZQꢂ
&KDQQHOꢀDꢀꢁB$ꢂ
&KDQQHOꢀEꢀꢁB%ꢂ
6XSSO\
*URXQG
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Ball Descriptions
Ball Descriptions
The ball/pad description table below is a comprehensive list of signals for the device
family. All signals listed may not be supported on this device. See Ball Assignments for
information specific to this device.
Table 9: Ball/Pad Descriptions
Symbol
Type
Description
CA[9:0]_A,
CA[9:0]_B
Input
Command/address inputs: Provide the command and address inputs according to the
command truth table. A separate CA[9:0] is provided for each channel (A and B).
CK_t_A, CK_t_B
CK_c_A, CK_c_B
Input
Input
Clock: Differential clock inputs. All CA inputs are sampled on both rising and falling
edges of CK. CS and CKE inputs are sampled at the rising edge of CK. AC timings are
referenced to clock. A separate CK_t/CK_c is provided for each channel (A and B).
CKE[1:0]_A,
CKE[1:0]_B
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals,
input buffers, and output drivers. Power-saving modes are entered and exited via CKE
transitions. CKE is considered part of the command code. CKE is sampled on the rising
edge of CK. A separate CKE is provided for each channel (A and B).
CS[1:0]_n_A,
CS[1:0]_n_B
Input
Input
Chip select: Considered part of the command code and is sampled on the rising edge
of CK. A separate CS_n is provided for each channel (A and B).
DM[3:0]_A,
DM[3:0]_B
Input data mask: Input mask signal for write data. Although DM balls are input-only,
the DM loading is designed to match that of DQ and DQS balls. DM[3:0] is DM for each
of the four data bytes, respectively. A separate DM[3:0] is provided for each channel (A
and B).
DQ[31:0]_A,
DQ[31:0]_B
I/O
I/O
Data input/output: Bidirectional data bus. A separate DQ[11:0] is provided for each
channel (A and B).
DQS[3:0]_t_A,
DQS[3:0]_t_B,
DQS[3:0]_c_A,
DQS[3:0]_c_B
Data strobe: Bidirectional (used for read and write data) and complementary (DQS_t
and DQS_c). It is edge-aligned output with read data and centered input with write da-
ta. DQS[3:0]_t/DQS[3:0]_c is DQS for each of the four data bytes, respectively. A sepa-
rate DQS[3:0]_t and DQS[3:0]_c is provided for each channel (A and B).
V
DDQ_A, VDDQ_B
Supply
Supply
Supply
Supply
Supply
Supply
DQ power supply: Isolated on the die for improved noise immunity.
DQ ground: Isolated on the die for improved noise immunity.
Core power: Supply 1.
VSSQ_A/B
VDD1 _A/B
VDD2_A/B
VSS_A/B
Core power: Supply 2.
Common ground.
VREFCA_A, VREFCA_B
Reference voltage: VREFCA is reference for command/address input buffers, VREFDQ is
reference for DQ input buffers. A separate VREFCA and VREFDQ provided for each channel
(A and B).
V
REFDQ_A, VREFDQ_B
ZQ_A, ZQ_B
Reference External reference ball for output drive calibration: This ball is tied to an external
240Ω resistor (RZQ), which is tied to VSSQ. A separate ZQ is provided for each channel (A
and B).
NU
NC
–
–
–
Not usable: Do not connect.
No connect: Not internally connected.
(NC)
No connect: Balls indicated as (NC) are no connects; however, they could be connected
together internally.
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
24
© 2014 Micron Technology, Inc. All rights reserved.
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Functional Description
Functional Description
Mobile LPDDR2 is a high-speed SDRAM internally configured as a 4- or 8-bank memory
device. The device uses a double data rate architecture on the command/address (CA)
bus to reduce the number of input pins in the system. The 10-bit CA bus is used to
transmit command, address, and bank information. Each command uses one clock cy-
cle, during which command information is transferred on both the rising and falling
edges of the clock.
The LPDDR2-S4 device uses a double data rate architecture on the DQ pins to achieve
high- speed operation. The double data rate architecture is essentially a 4n prefetch ar-
chitecture with an interface designed to transfer two data bits per DQ every clock cycle
at the I/O pins. A single read or write access for the LPDDR2-S4 effectively consists of a
single 4n-bit-wide, one-clock-cycle data transfer at the internal SDRAM core and four
corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write access is burst oriented; access starts at a selected location and contin-
ues for a programmed number of locations in a programmed sequence.
Access begins with the registration of an ACTIVATE command followed by a READ or
WRITE command. Registered address and BA bits that coincide with the ACTIVATE
command are used to select the row and bank to be accessed. Registered address bits
that coincide with the READ or WRITE command are used to select the bank and the
starting column location for the burst access.
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
25
© 2014 Micron Technology, Inc. All rights reserved.
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Simplified State Diagram
Figure 10: Functional Block Diagram
CK_t
CK_c
CKE
Bank n
Row
address
buffer
and
Memory cell array
Bank 0
refresh
counter
Mode
register
CS_n
Sense amp.
CA[9:0]
Column decoder
Column
address
buffer
and
burst
counter
Data control circuit
Latch circuit
DQS_t
DQS_c
DM
Input and Output buffer
DQ
1. 512Mb is a 4-bank only.
Note:
Simplified State Diagram
The state diagram provides a simplified illustration of allowed state transitions and the
related commands to control them. For a complete definition of the device behavior,
the information provided by the state diagram should be integrated with the truth ta-
bles and timing specification. The truth tables provide complementary information to
the state diagram, they clarify the device behavior and the applied restrictions when
considering the actual state of all the banks.
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
26
© 2014 Micron Technology, Inc. All rights reserved.
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Simplified State Diagram
Figure 11: Simplified State Diagram
Deep
power-down
DPDX
Power
applied
Power-on
Automatic sequence
Command sequence
Self
refreshing
MRR
Resetting
Resetting
MR reading
DPD
Resetting
power-down
MRR
REF
Idle
MR reading
1
Idle
Refreshing
Idle
power-down
MR writing
ACT
Active
power-down
Active
MR reading
PR,PRA
Active
BST
BST
WR
RD
PR = PRECHARGE
PRA = PRECHARGE ALL
ACT = ACTIVATE
Writing
Reading
WR(A) = WRITE (with auto precharge)
RD(A) = READ (with auto precharge)
BST = BURST TERMINATE
RESET = RESET is achieved through
MRW command
PR, PRA
WRA
RDA
MRW = MODE REGISTER WRITE
MRR = MODE REGISTER READ
PD = enter power-down
PDX = exit power-down
SREF = enter self refresh
SREFX = exit self refresh
DPD = enter deep power-down
DPDX = exit deep power-down
REF = REFRESH
Writing
with
auto precharge
Reading
with
auto precharge
Precharging
1. All banks are precharged in the idle state.
Note:
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
27
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Power-Up and Initialization
Power-Up and Initialization
The device must be powered up and initialized in a predefined manner. Power-up and
initialization by means other than those specified will result in undefined operation.
Voltage Ramp and Device Initialization
The following sequence must be used to power up the device. Unless specified other-
wise, this procedure is mandatory (see the Voltage Ramp and Initialization Sequence
figure). Power-up and initialization by means other than those specified will result in
undefined operation.
1.Voltage Ramp Beginning
While applying power (after Ta), CKE must be held LOW (≤0.2 × VDD2), and all other in-
puts must be between VILmin and VIHmax. The device outputs remain at High-Z while
CKE is held LOW.
On or before the completion of the voltage ramp (Tb), CKE must be held LOW. DQ, DM,
DQS_t, and DQS_c voltage levels must be between VSSQ and VDDQ during voltage ramp
to avoid latchup. CK_t, CK_c, CS_n, and CA input levels must be between VSS and VDD2
during voltage ramp to avoid latchup.
The following conditions apply for voltage ramp:
• Ta is the point when any power supply first reaches 300mV.
• Noted conditions apply between Ta and power-down (controlled or uncontrolled).
• Tb is the point at which all supply and reference voltages are within their defined op-
erating ranges.
• Power ramp duration tINIT0 (Tb - Ta) must not exceed 20ms.
• For supply and reference voltage operating conditions, see the Recommended DC
Operating Conditions table.
• The voltage difference between any of VSS, and VSSQ pins must not exceed 100mV.
2.Voltage Ramp Completion
After Ta is reached:
• VDD1 must be greater than VDD2 - 200mV
• VDD1 and VDD2 must be greater than VDDQ - 200mV
• VREF must always be less than all other supply voltages
Beginning at Tb, CKE must remain LOW for at least tINIT1 = 100ns, after which CKE can
be asserted HIGH. The clock must be stable at least tINIT2 = 5 × tCK prior to the first
CKE LOW-to-HIGH transition (Tc). CKE, CS_n, and CA inputs must observe setup and
hold requirements (tIS, tIH) with respect to the first rising clock edge (and to subse-
quent falling and rising edges).
If any MRRs are issued, the clock period must be within the range defined for tCKb
(18ns to 100ns). MRWs can be issued at normal clock frequencies as long as all AC tim-
ings are met. Some AC parameters (for example, tDQSCK) could have relaxed timings
(such as tDQSCKb) before the system is appropriately configured. While keeping CKE
HIGH, NOP commands must be issued for at least tINIT3 = 200μs (Td).
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Power-Up and Initialization
3. RESET Command
After tINIT3 is satisfied, the MRW RESET command must be issued (Td). An optional
PRECHARGE ALL command can be issued prior to the MRW RESET command. Wait at
least tINIT4 while keeping CKE asserted and issuing NOP commands.
4. MRRs and Device Auto Initialization (DAI) Polling
After tINIT4 is satisfied (Te), only MRR commands and power-down entry/exit com-
mands are supported. After Te, CKE can go LOW in alignment with power-down entry
and exit specifications (see Power-Down).
The MRR command can be used to poll the DAI bit, which indicates when device auto
initialization is complete; otherwise, the controller must wait a minimum of tINIT5 or
until the DAI bit is set before proceeding.
Because the memory output buffers are not properly configured by Te, some AC param-
eters must use relaxed timing specifications before the system is appropriately config-
ured.
After the memory device sets the DAI bit (MR0, DAI) to zero, indicating DAI complete,
the device is in the idle state (Tf). DAI status can be determined by issuing the MRR
command to MR0.
The device sets the DAI bit no later than tINIT5 after the RESET command. The control-
ler must wait at least tINIT5 or until the DAI bit is set before proceeding.
5. ZQ Calibration
After tINIT5 (Tf), the MRW initialization calibration (ZQ calibration) command can be
issued to the memory (MR10).
This command is used to calibrate output impedance over process, voltage, and tem-
perature. In systems where more than one Mobile LPDDR2 device exists on the same
bus, the controller must not overlap MRW ZQ calibration commands. The device is
ready for normal operation after tZQINIT.
6. Normal Operation
After (Tg), the MRW command must be used to properly configure the memory, includ-
ing, for example, output buffer drive strength, latencies,and so on. Specifically, MR1,
MR2, and MR3 must be set to configure the memory for the target frequency and mem-
ory configuration.
After the initialization sequence is complete, the device is ready for any valid command.
After Tg, the clock frequency can be changed using the procedure described in Input
Clock Frequency Changes and Stop Events.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Power-Off Sequence
Figure 12: Voltage Ramp and Initialization Sequence
Ta
Tb
Tc
Td
Te
Tf
Tg
t
INIT2
CK_c
CK_t
t
INIT0
Supplies
t
t
INIT3
INIT1
PD
CKE
CA
t
t
t
INIT4
ISCKE
ZQINIT
t
INIT5
RESET
MRR
ZQ_CAL
Valid
DQ
1. High-Z on the CA bus indicates valid NOP.
Note:
Table 10: Initialization Timing Parameters
Value
Parameter
tINIT0
Min
–
Max
20
–
Unit
ms
ns
Comment
Maximum voltage ramp time
tINIT1
tINIT2
tINIT3
tINIT4
tINIT5
tZQINIT
tCKb
100
5
Minimum CKE LOW time after completion of voltage ramp
Minimum stable clock before first CKE HIGH
Minimum idle time after first CKE assertion
Minimum idle time after RESET command
Maximum duration of device auto initialization
ZQ initial calibration (S4 devices only)
–
tCK
200
1
–
μs
–
μs
–
10
–
μs
1
μs
18
100
ns
Clock cycle time during boot
1. The tINIT0 maximum specification is not a tested limit and should be used as a general
guideline. For voltage ramp times exceeding tINIT0 MAX, contact the factory.
Note:
Initialization After RESET (Without Voltage Ramp)
If the RESET command is issued before or after the power-up initialization sequence,
the reinitialization procedure must begin at Td.
Power-Off Sequence
While powering off, CKE must be held LOW (≤0.2 × VDD2); all other inputs must be be-
tween VILmin and VIHmax. The device outputs remain at High-Z while CKE is held LOW.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Mode Register Definition
DQ, DM, DQS_t, and DQS_c voltage levels must be between VSSQ and VDDQ during the
power-off sequence to avoid latchup. CK_t, CK_c, CS_n, and CA input levels must be be-
tween VSS and VDD2 during the power-off sequence to avoid latchup.
Tx is the point where any power supply drops below the minimum value specified in
the Recommended DC Operating Conditions table.
Tz is the point where all power supplies are below 300mV. After Tz, the device is pow-
ered off.
Required Power Supply Conditions Between Tx and Tz:
• VDD1 must be greater than VDD2 - 200mV
• VDD1 must be greater than VDDQ - 200mV
• VREF must always be less than all other supply voltages
The voltage difference between VSS and VSSQ must not exceed 100mV.
For supply and reference voltage operating conditions, see Recommended DC Operat-
ing Conditions table.
Uncontrolled Power-Off Sequence
When an uncontrolled power-off occurs, the following conditions must be met:
• At Tx, when the power supply drops below the minimum values specified in the Rec-
ommended DC Operating Conditions table, all power supplies must be turned off and
all power-supply current capacity must be at zero, except for any static charge re-
maining in the system.
• After Tz, the point at which all power supplies first reach 300mV, the device must pow-
t
er off. The time between Tx and Tz must not exceed POFF. During this period, the rel-
ative voltage between power supplies is uncontrolled. VDD1 and VDD2 must decrease
with a slope lower than 0.5 V/μs between Tx and Tz.
An uncontrolled power-off sequence can occur a maximum of 400 times over the life of
the device.
Table 11: Power-Off Timing
Parameter
Symbol
Min
Max
Unit
Maximum power-off ramp time
tPOFF
–
2
sec
Mode Register Definition
The LPDDR2 device contains a set of mode registers used for programming device op-
erating parameters, reading device information and status, and for initiating special op-
erations such as DQ calibration, ZQ calibration, and device reset.
Mode Register Assignments and Definitions
The MRR command is used to read from a register. The MRW command is used to write
to a register. An “R” in the access column of the mode register assignment table indi-
cates read-only; a “W” indicates write-only; “R/W” indicates read or write capable or
enabled.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Mode Register Definition
Table 12: Mode Register Assignments
Notes 1–5 apply to all parameters and conditions
MR#
MA[7:0]
00h
Function
Device info
Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Link
0
1
2
3
4
R
W
W
W
R
RFU
nWR (for AP)
RFU
RZQI
WC BT
RFU
DI
DAI go to MR0
go to MR1
01h
Device feature 1
Device feature 2
I/O config-1
BL
02h
RL and WL
DS
go to MR2
03h
RFU
go to MR3
04h
SDRAM refresh
rate
TUF
RFU
Refresh rate
go to MR4
5
6
05h
06h
Basic config-1
Basic config-2
Basic config-3
Basic config-4
Test mode
R
R
LPDDR2 Manufacturer ID
Revision ID1
Revision ID2
Density
go to MR5
go to MR6
go to MR7
go to MR8
go to MR9
go to MR10
go to MR11
go to MR16
go to MR17
go to MR18
go to MR32
7
07h
R
8
08h
R
I/O width
Type
9
09h
W
W
–
Vendor-specific test mode
Calibration code
RFU
10
0Ah
I/O calibration
Reserved
11–15
16
0Bh ≈ 0Fh
10h
PASR_Bank
PASR_Seg
W
W
–
Bank mask
17
11h
Segment mask
RFU
18–31
32
12h–1Fh
20h
Reserved
DQ calibration
pattern A
R
See Data Calibration Pattern Description table
33–39
40
21h–27h
28h
Do not use
go to MR33
go to MR40
DQ calibration
pattern B
R
See Data Calibration Pattern Description table
41–47
48–62
63
29h–2Fh
30h–3Eh
3Fh
Do not use
Reserved
RESET
go to MR41
go to MR48
go to MR63
go to MR64
go to MR127
go to MR128
go to MR191
go to MR192
go to MR255
–
W
–
RFU
X
64–126
127
40h–7Eh
7Fh
Reserved
Do not use
RFU
128–190 80h–BEh
191 BFh
192–254 C0h–FEh
Reserved for vendor use
Do not use
RVU
RVU
Reserved for vendor use
Do not use
255
FFh
1. RFU bits must be set to 0 during MRW.
2. RFU bits must be read as 0 during MRR.
Notes:
3. For READs to a write-only or RFU register, DQS will be toggled and undefined data is
returned.
4. RFU mode registers must not be written.
5. WRITEs to read-only registers must have no impact on the functionality of the device.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Mode Register Definition
Table 13: MR0 Device Information (MA[7:0] = 00h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
RFU
RZQI
RFU
DI
DAI
Table 14: MR0 Op-Code Bit Definitions
Notes 1–4 apply to all parameters and conditions
Register Information
Tag
Type
OP
Definition
Device auto initialization
status
DAI
Read-only
OP0
0b: DAI complete
1b: DAI in progress
Device information
DI
Read-only
Read-only
OP1
0b:DDR2 Mobile RAM (S4 SDRAM)
Built-in self test for RZQ
information
RZQI
OP[4:3] 01b: ZQ pin might be connected to VDD2 or left floating
10b: ZQ pin might be shorted to ground
11b: ZQ pin self test complete; no error condition de-
tected(ZQ-pin may not connect to VDD or float nor
short to GND)
1. If RZQI is supported, it will be set upon completion of the MRW ZQ initialization calibra-
tion.
Notes:
2. If ZQ is connected to VDD2 to set default calibration, OP[4:3] must be set to 01. If ZQ is
not connected to VDD2, either OP[4:3] = 01 or OP[4:3] = 10 could indicate a ZQ-pin as-
sembly error. It is recommended that the assembly error be corrected.
3. In the case of a possible assembly error (either OP[4:3] = 01 or OP[4:3] = 10, as defined
above), the device will default to factory trim settings for RON(output impedance) and
will ignore ZQ calibration commands. In either case, the system might not function as
intended.
4. If a ZQ self test returns a value of 11b, this indicates that the device has detected a resis-
tor connection to the ZQ pin. Note that this result cannot be used to validate the ZQ
resistor value, nor does it indicate that the ZQ resistor tolerance meets the specified lim-
its (240 ohms 1%).
Table 15: MR1 Device Feature 1 (MA[7:0] = 01h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
nWR (for AP)
WC
BT
BL
Table 16: MR1 Op-Code Bit Definitions
Feature
Type
OP
OP[2:0]
Definition
Notes
BL = burst length
Write-only
010b: BL4 (default)
011b: BL8
1
100b: BL16
All others: Reserved
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Mode Register Definition
Table 16: MR1 Op-Code Bit Definitions (Continued)
Feature
Type
OP
Definition
Notes
BT = burst type
Write-only
OP3
0b: Sequential (default)
1b: Interleaved
WC = wrap control
Write-only
OP4
0b: Wrap (default)
1b: No wrap (allowed for BL4 only)
001b: nWR = 3 (default)
010b: nWR = 4
nWR = number of tWR clock Write-only
cycles
OP[7:5]
2
011b: nWR = 5
100b: nWR = 6
101b: nWR = 7
110b: nWR = 8
All others: Reserved
1. BL16, interleaved is not an official combination to be supported.
Notes:
2. The programmed value in nWR register is the number of clock cycles that determines
when to start internal precharge operation for a WRITE burst with AP enabled. It is de-
termined by RU (tWR/tCK).
Table 17: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC)
Notes 1–5 apply to all parameters and conditions
Burst Cycle Number and Burst Address Sequence
BL
BT
C3 C2 C1 C0
WC
1
0
2
y
2
1
3
3
2
0
4
3
1
5
6
7
8
9
10 11 12 13 14 15 16
4
Any
X
X
X
X
X
X
0b 0b Wrap
1b 0b
Any
Seq
X
0b
No
wrap
y + y + y +
1
1
3
5
7
1
3
5
7
2
2
4
6
0
2
0
6
4
3
3
5
7
1
3
1
7
5
8
X
X
X
X
X
X
X
X
X
0b 0b 0b Wrap
0b 1b 0b
1b 0b 0b
1b 1b 0b
0b 0b 0b
0b 1b 0b
1b 0b 0b
1b 1b 0b
0
2
4
6
0
2
4
6
4
6
0
2
4
6
0
2
5
7
1
3
5
7
1
3
6
0
2
4
6
4
2
0
7
1
3
5
7
5
3
1
Int
Any
X
X
0b
No
Illegal (not supported)
wrap
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Mode Register Definition
Table 17: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC) (Continued)
Notes 1–5 apply to all parameters and conditions
Burst Cycle Number and Burst Address Sequence
BL
BT
C3 C2 C1 C0
WC
1
0
2
4
6
8
A
C
E
2
1
3
5
7
9
B
D
F
3
2
4
6
8
A
C
E
0
4
3
5
7
9
B
D
F
5
4
6
8
A
C
E
0
2
6
5
7
9
B
D
F
7
6
8
A
C
E
0
2
4
8
7
9
B
D
F
9
8
A
C
E
0
2
4
6
10 11 12 13 14 15 16
16
Seq 0b 0b 0b 0b Wrap
0b 0b 1b 0b
0b 1b 0b 0b
0b 1b 1b 0b
1b 0b 0b 0b
1b 0b 1b 0b
1b 1b 0b 0b
1b 1b 1b 0b
9
B
D
F
A
C
E
0
2
4
6
8
B
D
F
C
E
0
2
4
6
8
A
D
F
E
0
2
4
6
8
A
C
F
1
3
5
7
9
B
D
1
3
5
7
9
B
1
3
5
7
9
1
3
5
7
1
3
5
1
3
1
Int
X
X
X
X
X
X
0b
0b
Illegal (not supported)
Illegal (not supported)
Any
No
wrap
1. C0 input is not present on CA bus. It is implied zero.
2. For BL = 4, the burst address represents C[1:0].
3. For BL = 8, the burst address represents C[2:0].
4. For BL = 16, the burst address represents C[3:0].
Notes:
5. For no-wrap, BL4, the burst must not cross the page boundary or the sub-page boun-
dary. The variable y can start at any address with C0 equal to 0, but must not start at any
address shown in the following table.
Table 18: No-Wrap Restrictions
Width
64Mb
128Mb/256Mb
512Mb/1Gb/2Gb
4Gb/8Gb
Cannot cross full-page boundary
x16
x32
FE, FF, 00, 01
7E, 7F, 00, 01
1FE, 1FF, 000, 001
FE, FF, 00, 01
3FE, 3FF, 000, 001
1FE, 1FF, 000, 001
7FE, 7FF, 000, 001
3FE, 3FF, 000, 001
Cannot cross sub-page boundary
x16
x32
7E, 7F, 80, 81
None
0FE, 0FF, 100, 101
None
1FE, 1FF, 200, 201
None
3FE, 3FF, 400, 401
None
1. No-wrap BL = 4 data orders shown are prohibited.
Note:
Table 19: MR2 Device Feature 2 (MA[7:0] = 02h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
RFU
RL and WL
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Mode Register Definition
Table 20: MR2 Op-Code Bit Definitions
Feature
Type
OP
Definition
RL and WL
Write-only
OP[3:0]
0001b: RL3/WL1 (default)
0010b: RL4/WL2
0011b: RL5/WL2
0100b: RL6/WL3
0101b: RL7/WL4
0110b: RL8/WL4
All others: Reserved
Table 21: MR3 I/O Configuration 1 (MA[7:0] = 03h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
RFU
DS
Table 22: MR3 Op-Code Bit Definitions
Feature
Type
OP
Definition
DS
Write-only
OP[3:0]
0000b: Reserved
0001b: 34.3 ohm typical
0010b: 40 ohm typical (default)
0011b: 48 ohm typical
0100b: 60 ohm typical
0101b: Reserved
0110b: 80 ohm typical
0111b: 120 ohm typical
All others: Reserved
Table 23: MR4 Device Temperature (MA[7:0] = 04h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
SDRAM refresh rate
OP0
TUF
RFU
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Mode Register Definition
Table 24: MR4 Op-Code Bit Definitions
Notes 1–8 apply to all parameters and conditions
Feature
Type
OP
Definition
SDRAM refresh
rate
Read-only
OP[2:0] 000b: SDRAM low temperature operating limit exceeded
001b: 4 × tREFI, 4 × tREFIpb, 4 × tREFW
010b: 2 × tREFI, 2 × tREFIpb, 2 × tREFW
011b: 1 × tREFI, 1 × tREFIpb, 1 × tREFW (≤85˚C)
100b: Reserved
101b: 0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW, do not derate SDRAM AC
timing
110b: 0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW, derate SDRAM AC timing
111b: SDRAM high temperature operating limit exceeded
Temperature up-
date flag (TUF)
Read-only
Notes:
OP7
0b: OP[2:0] value has not changed since last read of MR4
1b: OP[2:0] value has changed since last read of MR4
1. A MODE REGISTER READ from MR4 will reset OP7 to 0.
2. OP7 is reset to 0 at power-up.
3. If OP2 = 1, the device temperature is greater than 85˚C.
4. OP7 is set to 1 if OP[2:0] has changed at any time since the last MR4 read.
5. The device might not operate properly when OP[2:0] = 000b or 111b.
6. For specified operating temperature range and maximum operating temperature, refer
to the Operating Temperature Range table.
7. LPDDR2 devices must be derated by adding 1.875ns to the following core timing param-
eters: tRCD, tRC, tRAS, tRP, and tRRD. The tDQSCK parameter must be derated as speci-
fied in AC Timing. Prevailing clock frequency specifications and related setup and hold
timings remain unchanged.
8. The recommended frequency for reading MR4 is provided in Temperature Sensor.
Table 25: MR5 Basic Configuration 1 (MA[7:0] = 05h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
LPDDR2 Manufacturer ID
Table 26: MR5 Op-Code Bit Definitions
Feature
Type
OP
Definition
00000011b
All others: Reserved
Manufacturer ID
Read-only
OP[7:0]
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Mode Register Definition
Table 27: MR6 Basic Configuration 2 (MA[7:0] = 06h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Revision ID1 (Die Revision)
1. MR6 is vendor-specific.
Note:
Table 28: MR6 Op-Code Bit Definitions
Feature
Type
OP
Definition
Revision ID1 (Die Revision)
Read-only
OP[7:0]
0000 0000b: Version A
0000 0001b: Version B
0000 0010b: Version C
0000 0010b: Version D(512Mb only)
0000 0011b: Version D
Table 29: MR7 Basic Configuration 3 (MA[7:0] = 07h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Revision ID2 (RFU)
Table 30: MR7 Op-Code Bit Definitions
Feature
Type
OP
Definition
Revision ID2 (RFU)
Read-only
OP[7:0]
0000 0000b: Default Value
1. MR7 is vendor-specific.
Note:
Table 31: MR8 Basic Configuration 4 (MA[7:0] = 08h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
I/O width
Density
Type
Table 32: MR8 Op-Code Bit Definitions
Feature
Type
OP
OP[1:0]
Definition
Type
Read-only
00b: S4 SDRAM
01b: S2 SDRAM
10b: Reserved
11b: Reserved
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Mode Register Definition
Table 32: MR8 Op-Code Bit Definitions (Continued)
Feature
Type
OP
Definition
0000b: 64Mb
0001b: 128Mb
0010b: 256Mb
0011b: 512Mb
0100b: 1Gb
0101b: 2Gb
0110b: 4Gb
0111b: 8Gb
1000b: 16Gb
1001b: 32Gb
All others: Reserved
00b: x32
Density
Read-only
OP[5:2]
I/O width
Read-only
OP[7:6]
01b: x16
10b: x8
11b: not used
Table 33: MR9 Test Mode (MA[7:0] = 09h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP1
OP0
OP0
Vendor-specific test mode
Table 34: MR10 Calibration (MA[7:0] = 0Ah)
OP7
OP6
OP5
OP4
OP3
OP2
S4
Calibration code
Table 35: MR10 Op-Code Bit Definitions
Notes 1–6 apply to all parameters and conditions
Feature
Type
OP
Definition
Calibration code
Write-only
OP[7:0]
0xFF: Calibration command after initialization
0xAB: Long calibration
0x56: Short calibration
0xC3: ZQRESET
All others: Reserved
1. Host processor must not write MR10 with reserved values.
Notes:
2. The device ignores calibration commands when a reserved value is written into MR10.
3. See AC timing table for the calibration latency.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Mode Register Definition
4. If ZQ is connected to VSS through RZQ, either the ZQ calibration function (see MODE
REGISTER WRITE command) or default calibration (through the ZQRESET command) is
supported. If ZQ is connected to VDD2, the device operates with default calibration, and
ZQ calibration commands are ignored. In both cases, the ZQ connection must not
change after power is supplied to the device.
5. LPDDR2 devices that do not support calibration shall ignore the ZQ Calibration com-
mand.
6. Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate
RZQ pin connection.
Table 36: MR[11:15] Reserved (MA[7:0] = 0Bh–0Fh)
OP7
OP6
OP5
OP4
OP3
OP2
OP2
OP1
OP1
OP0
OP0
Reserved
Table 37: MR16 PASR Bank Mask (MA[7:0] = 010h)
OP7
OP6
OP5
OP4
OP3
Bank mask (4-bank or 8-bank)
Table 38: MR16 Op-Code Bit Definitions
Feature
Type
OP
Definition
Bank[7:0] mask
Write-only
OP[7:0]
0b: refresh enable to the bank = unmasked (default)
1b: refresh blocked = masked
1. For 4-bank devices, only OP[3:0] are used.
Note:
Table 39: MR16 Bank and OP corresponding table
4-Bank Mask
Bank
8-Bank Mask
Bank
Feature
Type
OP
0
Bank #
Address
Bank #
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Address
Bank 0
000b
001b
010b
011b
–
000b
001b
010b
011b
100b
101b
110b
111b
1
Bank 1
2
Bank 2
3
Bank 3
Bank[7:0] mask
Write-only
4
–
–
–
–
5
–
6
–
7
–
1. Each bank can be masked independently by setting each OP value.
Note:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Mode Register Definition
Table 40: MR17 PASR Segment Mask (MA[7:0] = 011h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Segment mask
1. This table applies for 1Gb to 8Gb devices only.
Note:
Table 41: MR17 PASR Segment Mask Definitions (1Gb - 8Gb only)
Feature
Type
OP
Definition
Segment[7:0] mask
Write-only
OP[7:0]
0b: refresh enable to the segment: = unmasked (default)
1b: refresh blocked: = masked
Table 42: MR17 PASR Row Address Ranges in Masked Segments
1Gb
2Gb, 4Gb
R[13:11]
000b
8Gb
R[14:12]
Segment
OP
0
Segment Mask
XXXXXXX1
XXXXXX1X
XXXXX1XX
XXXX1XXX
XXX1XXXX
XX1XXXXX
X1XXXXXX
1XXXXXXX
R[12:10]
0
1
2
3
4
5
6
7
1
001b
2
010b
3
011b
4
100b
5
101b
6
110b
7
111b
1. X is “Don’t Care” for the designated segment.
Note:
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41
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Commands and Timing
Table 43: Reserved Mode Registers
Mode Reg-
ister
MA
Address
Restriction OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
MR[18:19]
MR[20:31]
MR[33:39]
MR[41:47]
MR[48:62]
MR[64:126]
MR127
MA[7:0] 12h–13h
14h–1Fh
21h–27h
29h–2Fh
30h–3Eh
40h–7Eh
7Fh
RFU
Reserved
NVM1
DNU1
RFU
RFU
DNU
RVU1
DNU
RVU
DNU
MR[128:190]
MR191
80h–BEh
BFh
MR[192:254]
MR255
C0h–FEh
FFh
1. NVM = nonvolatile memory use only; DNU = Do not use; RVU = Reserved for vendor use.
Note:
Table 44: MR32 DQ Calibration Pattern A (MA[7:0] = 20H)
MR32 Reads
Reads to MR32 return DQ Calibration Pattern A
Table 45: MR40 DQ Calibration Pattern B (MA[7:0] = 28H)
MR40 Reads
Reads to MR40 return DQ Calibration Pattern B
Table 46: MR63 RESET (MA[7:0] = 3Fh) – MRW Only
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
X
1. For additional information on MRW RESET see MODE REGISTER WRITE Command.
Note:
Commands and Timing
The setup and hold timings shown in the figures below apply for all commands.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
ACTIVATE Command
Figure 13: Command and Input Setup and Hold
T0
T1
T2
T3
CK_c
CK_t
t
tIS IH
tIS tIH
V
IH(DC)
CS_n
CA[9:0]
CMD
V
IH(AC)
V
V
IL(DC)
IL(AC)
t
t
tIS IH
tIS IH
CA
CA
fall
CA
rise
CA
fall
CA
rise
CA
fall
CA
CA
rise
rise
fall
NOP
Command
NOP
Command
Don’t Care
Transitioning data
1. Setup and hold conditions also apply to the CKE pin. For timing diagrams related to the
CKE pin, see the Power-Down section.
Note:
Figure 14: CKE Input Setup and Hold
T0
CK_c
T1
Tx
Tx + 1
CK_t
tIHCKE tISCKE
tIHCKE tISCKE
CKE
VIHCKE
VIHCKE
VILCKE
VILCKE
HIGH or LOW, but defined
1. After CKE is registered LOW, the CKE signal level is maintained below VILCKE for tCKE
specification (LOW pulse width).
Notes:
2. After CKE is registered HIGH, the CKE signal level is maintained below VIHCKE for tCKE
specification (HIGH pulse width).
ACTIVATE Command
The ACTIVATE command is issued by holding CS_n LOW, CA0 LOW, and CA1 HIGH at
the rising edge of the clock. The bank addresses BA[2:0] are used to select the desired
bank. Row addresses are used to determine which row to activate in the selected bank.
The ACTIVATE command must be applied before any READ or WRITE operation can be
t
executed. The device can accept a READ or WRITE command at RCD after the ACTI-
VATE command is issued. After a bank has been activated, it must be precharged before
another ACTIVATE command can be applied to the same bank. The bank active and
precharge times are defined as tRAS and tRP, respectively. The minimum time interval
between successive ACTIVATE commands to the same bank is determined by the RAS
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
ACTIVATE Command
cycle time of the device (tRC). The minimum time interval between ACTIVATE com-
mands to different banks is tRRD.
Figure 15: ACTIVATE Command
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CK_c
CK_t
Bankn
row addr
Bankm
row addr
Bankn
col addr
Bankn
Row addr
Row addr
Col addr
Bankn
Row addr
row addr
CA[9:0]
tRRD
tRCD
tRAS
tRP
tRC
ACTIVATE
NOP
ACTIVATE
READ
PRECHARGE
NOP
NOP
ACTIVATE
CMD
1. tRCD = 3, tRP = 3, tRRD = 2.
Notes:
2. A PRECHARGE ALL command uses tRPab timing, and a single-bank PRECHARGE com-
mand uses tRPpb timing. In this figure, tRP is used to denote either an all-bank PRE-
CHARGE or a single-bank PRECHARGE.
8-Bank Device Operation
Two rules regarding 8-bank device operation must be observed: One rule restricts the
number of sequential ACTIVATE commands that can be issued; the second rule pro-
vides additional RAS precharge time for a PRECHARGE ALL command.
The 8-Bank Device Sequential Bank Activation Restriction: No more than four banks
can be activated (or refreshed, in the case of REFpb) in a rolling tFAW window. To con-
vert to clocks, divide tFAW[ns] by tCK[ns], and round up to the next integer value. For
example, if RU(tFAW/tCK) is 10 clocks, and an ACTIVATE command is issued in clock n,
no more than three further ACTIVATE commands can be issued at or between clock
n + 1 and n + 9. REFpb also counts as bank activation for purposes of tFAW.
The 8-Bank Device PRECHARGE ALL Provision: tRP for a PRECHARGE ALL command
must equal tRPab, which is greater than tRPpb.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Read and Write Access Modes
Figure 16: tFAW Timing (8-Bank Devices)
Tn
Tn+
Tm
Tm+
Tx
Tx+
Ty
Ty + 1
Ty + 2
Tz
Tz + 1
Tz + 2
CK_c
CK_t
Bank Bank
Bank Bank
Bank Bank
Bank Bank
Bank Bank
CA[9:0]
CMD
A
A
B
B
C
C
D
D
E
E
t
t
t
t
RRD
RRD
NOP
RRD
ACTIVATE
NOP
ACTIVATE
ACTIVATE
NOP
FAW
ACTIVATE
NOP
NOP
NOP
ACTIVATE
NOP
1. Exclusively for 8-bank devices.
Note:
Read and Write Access Modes
After a bank is activated, a READ or WRITE command can be issued with CS_n LOW,
CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at
this time to determine whether the access cycle is a READ operation (CA2 HIGH) or a
WRITE operation (CA2 LOW). A single READ or WRITE command initiates a burst
READ or burst WRITE operation on successive clock cycles.
A new burst access must not interrupt the previous 4-bit burst operation when BL = 4.
When BL = 8 or BL = 16, a READ can be interrupted by a READ and a WRITE can be
interrupted by a WRITE, provided that the interrupt occurs on a 4-bit boundary and
that tCCD is met.
Burst READ Command
The burst READ command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2
HIGH at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and
CA1f–CA9f, determine the starting column address for the burst. The read latency (RL)
is defined from the rising edge of the clock on which the READ command is issued to
the rising edge of the clock from which the tDQSCK delay is measured. The first valid
data is available RL × tCK + tDQSCK + tDQSQ after the rising edge of the clock when the
READ command is issued. The data strobe output is driven LOW tRPRE before the first
valid rising strobe edge. The first bit of the burst is synchronized with the first rising
edge of the data strobe. Each subsequent data-out appears on each DQ pin, edge-
aligned with the data strobe. The RL is programmed in the mode registers.
Pin input timings for the data strobe are measured relative to the crosspoint of DQS and
its complement, DQS#.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Burst READ Command
Figure 17: READ Output Timing – tDQSCK (MAX)
RL - 1
RL
RL + BL/2
t
t
CH
CL
CK#
CK
t
t
DQSCKmax
HZ(DQS)
t
t
t
LZ(DQS)
RPRE
RPST
DQS#
DQS
t
t
QH
QH
t
t
DQSQmax
DQSQmax
D
D
D
D
DQ
OUT
OUT
OUT
t
OUT
t
LZ(DQ)
HZ(DQ)
Transitioning data
1. tDQSCK can span multiple clock periods.
2. An effective burst length of 4 is shown.
Notes:
Figure 18: READ Output Timing – tDQSCK (MIN)
RL - 1
RL
RL + BL/2
t
t
CH
CL
CK#
CK
t
t
HZ(DQS)
DQSCKmin
t
t
t
LZ(DQS)
RPRE
RPST
DQS#
DQS
t
t
QH
QH
t
t
DQSQmax
DQSQmax
D
D
D
D
DQ
OUT
OUT
OUT
OUT
t
t
LZ(DQ)
HZ(DQ)
Transitioning data
1. An effective burst length of 4 is shown.
Note:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Burst READ Command
Figure 19: Burst READ – RL = 5, BL = 4, tDQSCK > tCK
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
RL = 5
Bank n
Col addr
CA[9:0]
CMD
col addr
READ
NOP
NOP
NOP
NOP
NOP
tDQSCK
NOP
NOP
NOP
DQS#
DQS
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DQ
Transitioning data
Figure 20: Burst READ – RL = 3, BL = 8, tDQSCK < tCK
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
RL = 3
Bank n
Col addr
CA[9:0]
CMD
col addr
READ
NOP
NOP
NOP
tDQSCK
NOP
NOP
NOP
NOP
NOP
DQS#
DQS
DOUT A0
DOUT A1
DOUT A2 DOUT A3 DOUT A4
DOUT A5
DOUT A6 DOUT A7
DQ
Transitioning data
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Burst READ Command
Figure 21: tDQSCKDL Timing
Tn
Tn + 1
Tn + 2
Tn + 3
Tn + 4
Tn + 5
Tn + 6
Tn + 7
Tn + 8
CK#
CK
RL = 5
CA
[9:0]
Bank n
col addr
Col addr
CMD
READ
NOP
NOP
NOP
NOP
NOP
tDQSCKn
NOP
NOP
NOP
DQS#
DQS
DOUT A0 DOUT A1 DOUT A2 DOUTA3
DQ
32ms maximum…
1
Tm
Tm + 1
Tm + 2
Tm + 3
Tm + 4
Tm + 5
Tm + 6
Tm + 7
Tm + 8
CK#
CK
RL = 5
CA
[9:0]
Bank n
col addr
Col addr
CMD
READ
NOP
NOP
NOP
NOP
NOP
tDQSCKm
NOP
NOP
NOP
DQS#
DQS
DOUT A0 DOUT A1 DOUT A2 DOUTA3
DQ
…32ms maximum
Transitioning data
1
1. tDQSCKDL = (tDQSCKn - tDQSCKm).
Notes:
2. tDQSCKDL (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any
(tDQSCKn, tDQSCKm) pair within any 32ms rolling window.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Burst READ Command
Figure 22: tDQSCKDM Timing
Tn
Tn + 1
Tn + 2
Tn + 3
Tn + 4
Tn + 5
Tn + 6
Tn + 7
Tn + 8
CK#
CK
RL = 5
CA
[9:0]
Bank n
col addr
Col addr
CMD
READ
NOP
NOP
NOP
NOP
NOP
tDQSCKn
NOP
NOP
NOP
DQS#
DQS
DOUT A0 DOUT A1 DOUT A2 DOUTA3
DQ
1.6μs maximum…
1
Tm
Tm + 1
Tm + 2
Tm + 3
Tm + 4
Tm + 5
Tm + 6
Tm + 7
Tm + 8
CK#
CK
RL = 5
CA
[9:0]
Bankn
col addr
Col addr
CMD
READ
NOP
NOP
NOP
NOP
NOP
tDQSCKm
NOP
NOP
NOP
DQS#
DQS
DOUT A0 DOUT A1 DOUT A2 DOUTA3
DQ
…1.6μs maximum
Transitioning data
1
1. tDQSCKDM = (tDQSCKn - tDQSCKm).
Notes:
2. tDQSCKDM (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any
(tDQSCKn, tDQSCKm) pair within any 1.6μs rolling window.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Burst READ Command
Figure 23: tDQSCKDS Timing
Tn
Tn + 1
Tn + 2
Tn + 3
Tn + 4
Tn + 5
Tn + 6
Tn + 7
Tn + 8
CK#
CK
RL = 5
CA
[9:0]
Bank n
col addr
Col addr
CMD
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t
DQSCKn
DQS#
DQS
DOUT A0 DOUT A1 DOUT A2 DOUTA3 DOUT A
DQ
160ns maximum…
1
Tm
Tm + 1
Tm + 2
Tm + 3
Tm + 4
Tm + 5
Tm + 6
Tm + 7
Tm + 8
CK#
CK
RL = 5
CA
[9:0]
Bankn
col addr
Col addr
CMD
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t
DQSCKm
DQS#
DQS
DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0
D
OUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A1
DQ
…160ns maximum
Transitioning data
1
1. tDQSCKDS = (tDQSCKn - tDQSCKm).
Notes:
2. tDQSCKDS (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any
(tDQSCKn, tDQSCKm) pair for READs within a consecutive burst, within any 160ns rolling
window.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Burst READ Command
Figure 24: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
RL = 3
WL = 1
Bank n
Bank n
Col addr
Col addr
CA[9:0]
CMD
col addr
col addr
READ
NOP
NOP
NOP
t
NOP
NOP
BL/2
WRITE
NOP
NOP
t
DQSCK
DQSSmin
DQS#
DQS
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DIN A0
DIN A1
D
DQ
Transitioning data
The minimum time from the burst READ command to the burst WRITE command is
defined by the read latency (RL) and the burst length (BL). Minimum READ-to-WRITE
latency is RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1 - WL clock cycles. Note that if a READ
burst is truncated with a burst TERMINATE (BST) command, the effective burst length
of the truncated READ burst should be used for BL when calculating the minimum
READ-to-WRITE delay.
Figure 25: Seamless Burst READ – RL = 3, BL = 4, tCCD = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
RL = 3
Bankn
Bankn
Col addr a
t
Col addr b
CA[9:0]
CMD
col addr a
col addr b
CCD = 2
READ
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
DQS#
DQS
DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT B0 DOUT B1 DOUT B2 DOUT B3
DQ
Transitioning data
A seamless burst READ operation is supported by enabling a READ command at every
other clock cycle for BL = 4 operation, every fourth clock cycle for BL = 8 operation, and
every eighth clock cycle for BL = 16 operation. This operation is supported as long as the
banks are activated, whether the accesses read the same or different banks.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Burst WRITE Command
READs Interrupted by a READ
A burst READ can be interrupted by another READ with a 4-bit burst boundary, provi-
ded that tCCD is met.
Figure 26: READ Burst Interrupt Example – RL = 3, BL = 8, tCCD = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
RL = 3
Bank n
col addr a
Bank n
col addr b
Col addr a
Col addr b
CA[9:0]
CMD
t
CCD = 2
READ
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
DQS#
DQS
DOUT A1 DOUT A2 DOUT A3 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B4 DOUT B5
DOUT A0
DQ
Transitioning data
1. READs can only be interrupted by other READs or the BST command.
Note:
Burst WRITE Command
The burst WRITE command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2
LOW at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and
CA1f–CA9f, determine the starting column address for the burst. Write latency (WL) is
defined from the rising edge of the clock on which the WRITE command is issued to the
rising edge of the clock from which the tDQSS delay is measured. The first valid data
t
must be driven WL × CK + tDQSS from the rising edge of the clock from which the
WRITE command is issued. The data strobe signal (DQS) must be driven LOW tWPRE
prior to data input. The burst cycle data bits must be applied to the DQ pins tDS prior to
the associated edge of the DQS and held valid until tDH after that edge. Burst data is
sampled on successive edges of the DQS until the 4-, 8-, or 16-bit burst length is com-
t
pleted. After a burst WRITE operation, WR must be satisfied before a PRECHARGE
command to the same bank can be issued.
Pin input timings are measured relative to the crosspoint of DQS and its complement,
DQS#.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Burst WRITE Command
Figure 27: Data Input (WRITE) Timing
tWPRE
tDQSH
tDQSL
tWPST
DQS
DQS#
DQS
DQS#
VIH(AC)
VIH(AC)
VIH(DC)
VIH(DC)
DIN
DIN
DIN
DIN
DQ
tDS tDH
tDS tDH
tDS tDH
tDS tDH
VIL(DC)
VIH(AC)
VIL(DC)
VIH(AC)
VIL(AC)
VIH(DC)
VIL(AC)
VIH(DC)
DM
VIL(AC)
VIL(DC)
VIL(AC)
VIL(DC)
Don’t Care
Ty + 1
Figure 28: Burst WRITE – WL = 1, BL = 4
T0
T1
T2
T3
T4
Tx
Tx + 1
Ty
CK#
CK
WL = 1
Bank n
Bank n
Col addr
Row addr
Bank n
CA[9:0]
CMD
col addr
row addr
WRITE
NOP
t
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVATE
NOP
Case 1: tDQSSmax
t
t
DQSSmax
DSS
DSS
Completion of burst WRITE
DQS#
DQS
t
WR
D
A0
D
A1
D
A2
D
A3
DQ
IN
IN
IN
IN
Case 2: tDQSSmin
DSH
DSH
t
t
t
t
DQSSmin
RP
DQS#
DQS
t
WR
D
A0
D
A1
D
A2
D
A3
IN
DQ
IN
IN
IN
Transitioning data
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53
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Burst WRITE Command
Figure 29: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
WL = 1
RL = 3
NOP
Bank n
col addr b
Bank m
col addr a
Col addr a
Col addr b
CA[9:0]
CMD
tWTR
WRITE
NOP
NOP
NOP
NOP
NOP
READ
NOP
DQS#
DQS
D
A0
D
A1
D
A2
D
A3
IN
DQ
IN
IN
IN
Transitioning data
1. The minimum number of clock cycles from the burst WRITE command to the burst READ
command for any bank is [WL + 1 + BL/2 + RU(tWTR/tCK)].
2. tWTR starts at the rising edge of the clock after the last valid input data.
Notes:
3. If a WRITE burst is truncated with a BST command, the effective burst length of the
truncated WRITE burst should be used as BL to calculate the minimum WRITE-to-READ
delay.
Figure 30: Seamless Burst WRITE – WL = 1, BL = 4, tCCD = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
WL = 1
Bank m
col addr a
Bank n
col addr b
Col addr a
Col addr b
CA[9:0]
CMD
t
CCD = 2
WRITE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
DQS#
DQS
D
A0
D
A1
D
A2
D
A3
D
B0
D
B1
D
B2
D
B3
DQ
IN
IN
IN
IN
IN
IN
IN
IN
Transitioning data
1. The seamless burst WRITE operation is supported by enabling a WRITE command every
other clock for BL = 4 operation, every four clocks for BL = 8 operation, or every eight
clocks for BL = 16 operation. This operation is supported for any activated bank.
Note:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
BURST TERMINATE Command
WRITEs Interrupted by a WRITE
A burst WRITE can only be interrupted by another WRITE with a 4-bit burst boundary,
provided that tCCD (MIN) is met.
A WRITE burst interrupt can occur on even clock cycles after the initial WRITE com-
mand, provided that tCCD (MIN) is met.
Figure 31: WRITE Burst Interrupt Timing – WL = 1, BL = 8, tCCD = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
WL = 1
Bank m
col addr a
Bank n
col addr b
Col addr a
Col addr b
CA[9:0]
CMD
t
CCD = 2
WRITE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
DQS#
DQS
D
A0
D
A1
D
A2
D
A3
D
B0
D
B1
D
B2
D
B3
D
B4
D
B5
D
B6
D
B7
DQ
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Transitioning data
1. WRITEs can only be interrupted by other WRITEs or the BST command.
Notes:
2. The effective burst length of the first WRITE equals two times the number of clock cycles
between the first WRITE and the interrupting WRITE.
BURST TERMINATE Command
The BURST TERMINATE (BST) command is initiated with CS_n LOW, CA0 HIGH, CA1
HIGH, CA2 LOW, and CA3 LOW at the rising edge of the clock. A BST command can be
issued only to terminate an active READ or WRITE burst. Therefore, a BST command
can be issued only up to and including BL/2 - 1 clock cycles after a READ or WRITE
command. The effective burst length of a READ or WRITE command truncated by a
BST command is as follows:
• Effective burst length = 2 × (number of clock cycles from the READ or WRITE com-
mand to the BST command).
• If a READ or WRITE burst is truncated with a BST command, the effective burst length
of the truncated burst should be used for BL when calculating the minimum READ-
to-WRITE or WRITE-to-READ delay.
• The BST command only affects the most recent READ or WRITE command. The BST
command truncates an ongoing READ burst RL × tCK + tDQSCK + tDQSQ after the ris-
ing edge of the clock where the BST command is issued. The BST command truncates
t
an ongoing WRITE burst WL × CK + tDQSS after the rising edge of the clock where the
BST command is issued.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
BURST TERMINATE Command
• The 4-bit prefetch architecture enables BST command assertion on even clock cycles
following a WRITE or READ command. The effective burst length of a READ or WRITE
command truncated by a BST command is thus an integer multiple of four.
Figure 32: Burst WRITE Truncated by BST – WL = 1, BL = 16
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK_c
CK_t
WL = 1
Bank m
col addr a
Col addr a
CA[9:0]
CMD
WRITE
NOP
NOP
NOP
BST
NOP
t
NOP
NOP
NOP
t
WL × CK + DQSS
DQS_c
DQS_t
D
A0
D
A1
D
A2
D
A3
D
A4
D
A5
D
A6
D
A7
DQ
IN
IN
IN
IN
IN
IN
IN
IN
BST prohibited
Transitioning data
1. The BST command truncates an ongoing WRITE burst WL × tCK + tDQSS after the rising
edge of the clock where the BST command is issued.
Notes:
2. BST can only be issued an even number of clock cycles after the WRITE command.
3. Additional BST commands are not supported after T4 and must not be issued until after
the next READ or WRITE command.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Write Data Mask
Figure 33: Burst READ Truncated by BST – RL = 3, BL = 16
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK_c
CK_t
RL = 3
Bank n
Col addr a
CA[9:0]
CMD
col addr a
NOP
NOP
NOP
BST
NOP
t
NOP
t
NOP
NOP
READ
t
RL × CK + DQSCK + DQSQ
DQS_c
DQS_t
D
A0
D
A1
D
A2
D
A3
D
A4
D
A5
D
A6
D
A7
OUT
DQ
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BST prohibited
Transitioning data
1. The BST command truncates an ongoing READ burst (RL × tCK + tDQSCK + tDQSQ) after
the rising edge of the clock where the BST command is issued.
Notes:
2. BST can only be issued an even number of clock cycles after the READ command.
3. Additional BST commands are not supported after T4 and must not be issued until after
the next READ or WRITE command.
Write Data Mask
On the LPDDR2 device, one write data mask (DM) pin for each data byte (DQ) is sup-
ported, consistent with the implementation on LPDDR SDRAM. Each DM can mask its
respective DQ for any given cycle of the burst. Data mask timings match data bit timing,
but are inputs only. Internal data mask loading is identical to data bit loading to ensure
matched system timing.
Figure 34: Data Mask Timing
DQS_c
DQS_t
DQ
t
t
t
t
DS
DH
DS
DH
V
V
V
V
V
V
IH(AC)
IH(DC)
IH(DC)
IH(AC)
DM
V
V
IL(AC)
IL(AC)
IL(DC)
IL(DC)
Don’t Care
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
PRECHARGE Command
Figure 35: Write Data Mask – Second Data Bit Masked
CK_c
CK_t
t
WR
t
WL = 2
WTR
WRITE
CMD
t
t
Case 1: DQSSmin
DQSSmin
DQS_c
DQS_t
D
1
D
0
D
2
D 3
IN
DQ
IN
IN
IN
DM
t
Case 2: DQSSmax
t
DQSSmax
DQS_c
DQS_t
D
0
D
1
D
2
D 3
IN
DQ
IN
IN
IN
DM
Don’t Care
1. For the data mask function, WL = 2, BL = 4 is shown; the second data bit is masked.
Note:
PRECHARGE Command
The PRECHARGE command is used to precharge or close a bank that has been activa-
ted. The PRECHARGE command is initiated with CS_n LOW, CA0 HIGH, CA1 HIGH,
CA2 LOW, and CA3 HIGH at the rising edge of the clock. The PRECHARGE command
can be used to precharge each bank independently or all banks simultaneously. For a 4-
bank device, the AB flag and bank address bits BA0 and BA1 are used to determine
which bank(s) to precharge. For an 8-bank device, the AB flag and the bank address bits
BA0, BA1, and BA2 are used to determine which bank(s) to precharge. The precharged
bank(s) will be available for subsequent row access tRPab after an all bank PRECHARGE
command is issued, or tRPpb after a single-bank PRECHARGE command is issued.
To ensure that an 8-bank device can meet the instantaneous current demand required
to operate, the row precharge time (tRP) for an all bank PRECHARGE in an 8-bank de-
vice (tRPab) will be longer than the row precharge time for a single-bank PRECHARGE
(tRPpb). For a 4-bank device, tRPab is equal to tRPpb.
ACTIVATE to PRECHARGE timing is shown in ACTIVATE Command.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
PRECHARGE Command
Table 47: Bank Selection for PRECHARGE by Address Bits
Precharged Bank(s) 4-
Precharged Bank(s) 8-
Bank Device
AB (CA4r)
BA2 (CA9r)
BA1 (CA8r)
BA0 (CA7r)
Bank Device
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
All banks
0
0
0
0
0
0
0
0
1
0
0
0
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
Bank 4 only
Bank 5 only
Bank 6 only
Bank 7 only
All banks
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Don’t Care
Don’t Care
Don’t Care
READ Burst Followed by PRECHARGE
For the earliest possible precharge, the PRECHARGE command can be issued BL/2
clock cycles after a READ command. A new bank ACTIVATE command can be issued to
the same bank after the row precharge time (tRP) has elapsed. A PRECHARGE com-
mand cannot be issued until after tRAS is satisfied.
The minimum READ-to-PRECHARGE time (tRTP) must also satisfy a minimum analog
time from the rising clock edge that initiates the last 4-bit prefetch of a READ com-
mand. tRTP begins BL/2 - 2 clock cycles after the READ command.
If the burst is truncated by a BST command, the effective BL value is used to calculate
when tRTP begins.
Figure 36: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(tRTP(MIN)/tCK) = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK_c
CK_t
RL = 3
BL/2
Bank m
Bank m
Col addr a
Bank m
Row addr
CA[9:0]
CMD
col addr a
row addr
t
t
RP
RTP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVATE
NOP
DQS_c
DQS_t
D
A0
D
A1
D
A2
D
A3
D
A4
D
A5
D
A6
D
A7
OUT
DQ
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Transitioning data
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59
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
PRECHARGE Command
Figure 37: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK_c
CK_t
BL/2
RL = 3
Bank m
Bank m
Col addr a
Bank m
Row addr
CA[9:0]
CMD
col addr a
row addr
t
t
RP
RTP = 3
READ
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVATE
NOP
NOP
DQS_c
DQS_t
D
A0
D
A1
D
A2
D
A3
OUT
DQ
OUT
OUT
OUT
Transitioning data
WRITE Burst Followed by PRECHARGE
For WRITE cycles, a WRITE recovery time (tWR) must be provided before a PRECHARGE
command can be issued. tWR delay is referenced from the completion of the burst
WRITE. The PRECHARGE command must not be issued prior to the tWR delay. For
WRITE-to-PRECHARGE timings, see the PRECHARGE and Auto Precharge Clarification
table.
These devices write data to the array in prefetch quadruples (prefetch = 4). An internal
WRITE operation can only begin after a prefetch group has been completely latched.
The minimum WRITE-to-PRECHARGE time for commands to the same bank is WL +
BL/2 + 1 + RU(tWR/tCK) clock cycles. For untruncated bursts, BL is the value set in the
mode register. For truncated bursts, BL is the effective burst length.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
PRECHARGE Command
Figure 38: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4
T0
T1
T2
T3
T4
Tx
Tx + 1
Ty
Ty + 1
CK_c
CK_t
WL = 1
Bank n
Bank n
row addr
Col addr
Row addr
Bank n
CA[9:0]
CMD
col addr
t
t
WR
≥ RP
WRITE
NOP
t
NOP
NOP
NOP
PRECHARGE
ACTIVATE
NOP
NO
t
Case 1: DQSSmax
DQSSmax
Completion of burst WRITE
DQS_c
DQS_t
D
A0
D
A1
D
A2
D
A3
IN
DQ
IN
IN
IN
t
t
Case 2: DQSSmin
DQSSmin
DQS_c
DQS_t
D
A0
D
A1
D
A2
D
A3
IN
DQ
IN
IN
IN
Transitioning data
Auto Precharge operation
Before a new row can be opened in an active bank, the active bank must be precharged
using either the PRECHARGE command or the auto precharge function. When a READ
or WRITE command is issued to the device, the auto precharge bit (AP) can be set to
enable the active bank to automatically begin precharge at the earliest possible mo-
ment during the burst READ or WRITE cycle.
If AP is LOW when the READ or WRITE command is issued, then normal READ or
WRITE burst operation is executed and the bank remains active at the completion of
the burst.
If AP is HIGH when the READ or WRITE command is issued, the auto precharge func-
tion is engaged. This feature enables the PRECHARGE operation to be partially or com-
pletely hidden during burst READ cycles (dependent upon READ or WRITE latency),
thus improving system performance for random data access.
READ Burst with Auto Precharge
If AP (CA0f) is HIGH when a READ command is issued, the READ with auto precharge
function is engaged.
This device starts an auto precharge on the rising edge of the clock BL/2 or BL/2 - 2 +
RU(tRTP/tCK) clock cycles later than the READ with auto precharge command, which-
ever is greater. For auto precharge calculations, see the PRECHARGE and Auto Pre-
charge Clarification table.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
PRECHARGE Command
Following an auto precharge operation, an ACTIVATE command can be issued to the
same bank if the following two conditions are satisfied simultaneously:
• The RAS precharge time (tRP) has been satisfied from the clock at which the auto pre-
charge begins.
• The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Figure 39: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK_c
CK_t
BL/2
RL = 3
Bankm
col addr a
Bankm
row addr
Col addr a
Row addr
CA[9:0]
t
t
≥ RPpb
RTP
CMD READ w/AP
NOP
NOP
NOP
NOP
ACTIVATE
NOP
NOP
NOP
DQS_c
DQS_t
D
A0
D
A1
D
A2
D
A3
DQ
OUT
OUT
OUT
OUT
Transitioning data
WRITE Burst with Auto Precharge
If AP (CA0f) is HIGH when a WRITE command is issued, the WRITE with auto precharge
function is engaged. The device starts an auto precharge at the clock rising edge tWR
cycles after the completion of the burst WRITE.
Following a WRITE with auto precharge, an ACTIVATE command can be issued to the
same bank if the following two conditions are met:
• The RAS precharge time (tRP) has been satisfied from the clock at which the auto pre-
charge begins.
• The RAS cycle time (tRC) from the previous bank activation has been satisfied.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
PRECHARGE Command
Figure 40: WRITE Burst with Auto Precharge – WL = 1, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK_c
CK_t
WL = 1
Bankn
Bankn
Col addr
Row addr
CA[9:0]
CMD
col addr
row addr
t
t
WR
≥ RPpb
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVATE
NOP
DQS_c
DQS_t
D
A0
D
A1
D
A2
D
A3
IN
DQ
IN
IN
IN
Transitioning data
Table 48: PRECHARGE and Auto Precharge Clarification
From
Command To Command
Minimum Delay Between Commands
BL/2 + MAX(2, RU(tRTP/tCK)) - 2
BL/2 + MAX(2, RU(tRTP/tCK)) - 2
1
Unit Notes
READ
BST
PRECHARGE to same bank as READ
CLK
CLK
CLK
CLK
CLK
CLK
CLK
1
1
PRECHARGE ALL
PRECHARGE to same bank as READ
PRECHARGE ALL
1
1
1
READ w/AP PRECHARGE to same bank as READ w/AP
PRECHARGE ALL
BL/2 + MAX(2, RU(tRTP/tCK)) - 2
BL/2 + MAX(2, RU(tRTP/tCK)) - 2
BL/2 + MAX(2, RU(tRTP/tCK)) - 2 + RU(tRPpb/
tCK)
1, 2
1
ACTIVATE to same bank as READ w/AP
1
WRITE or WRITE w/AP (same bank)
WRITE or WRITE w/AP (different bank)
READ or READ w/AP (same bank)
READ or READ w/AP (different bank)
Illegal
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
3
3
3
3
1
1
1
1
RL + BL/2 + RU(tDQSCKmax/tCK) - WL + 1
Illegal
BL/2
WRITE
BST
PRECHARGE to same bank as WRITE
PRECHARGE ALL
WL + BL/2 + RU(tWR/tCK) + 1
WL + BL/2 + RU(tWR/tCK) + 1
WL + RU(tWR/tCK) + 1
WL + RU(tWR/tCK) + 1
PRECHARGE to same bank as WRITE
PRECHARGE ALL
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63
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
REFRESH Command
Table 48: PRECHARGE and Auto Precharge Clarification (Continued)
From
Command To Command
Minimum Delay Between Commands
Unit Notes
WRITE w/AP PRECHARGE to same bank as WRITE w/AP WL + BL/2 + RU(tWR/tCK) + 1
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
1, 2
1
PRECHARGE ALL
WL + BL/2 + RU(tWR/tCK) + 1
ACTIVATE to same bank as WRITE w/AP
WRITE or WRITE w/AP (same bank)
WRITE or WRITE w/AP (different bank)
READ or READ w/AP (same bank)
READ or READ w/AP (different bank)
PRECHARGE PRECHARGE to same bank as PRECHARGE
PRECHARGE ALL
WL + BL/2 + RU(tWR/tCK) + 1 + RU(tRPpb/tCK)
1
Illegal
3
BL/2
3
Illegal
3
WL + BL/2 + RU(tWTR/tCK) + 1
3
1
1
1
1
1
1
PRECHARGE PRECHARGE
1
ALL
PRECHARGE ALL
1
1. For a given bank, the PRECHARGE period should be counted from the latest PRECHARGE
command—either a one-bank PRECHARGE or PRECHARGE ALL—issued to that bank.
The PRECHARGE period is satisfied after tRP, depending on the latest PRECHARGE com-
mand issued to that bank.
Notes:
2. Any command issued during the specified minimum delay time is illegal.
3. After READ with auto precharge, seamless READ operations to different banks are sup-
ported. After WRITE with auto precharge, seamless WRITE operations to different banks
are supported. READ with auto precharge and WRITE with auto precharge must not be
interrupted or truncated.
REFRESH Command
The REFRESH command is initiated with CS_n LOW, CA0 LOW, CA1 LOW, and CA2
HIGH at the rising edge of the clock. A per-bank REFRESH command is initiated with
CA3 LOW at the rising edge of the clock. The all-bank REFRESH command is initiated
with CA3 HIGH at the rising edge of the clock. A per-bank REFRESH is only supported
in devices with eight banks.
A per-bank REFRESH command (REFpb) performs a per-bank REFRESH operation to
the bank scheduled by the bank counter in the memory device. The bank sequence for
per-bank REFRESH is fixed to be a sequential round-robin: 0-1-2-3-4-5-6-7-0-1-.... The
bank count is synchronized between the controller and the SDRAM by resetting the
bank count to zero. Synchronization can occur upon issuing a RESET command or at
every exit from self refresh.
A bank must be idle before it can be refreshed. The controller must track the bank being
refreshed by the per-bank REFRESH command.
The REFpb command must not be issued to the device until the following conditions
have been met:
t
• RFCab has been satisfied after the prior REFab command
t
• RFCpb has been satisfied after the prior REFpb command
t
• RP has been satisfied after the prior PRECHARGE command to that bank
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
REFRESH Command
tRRD has been satisfied after the prior ACTIVATE command (when applicable, for ex-
ample after activating a row in a different bank than the one affected by the REFpb
command)
The target bank is inaccessible during per-bank REFRESH cycle time (tRFCpb); howev-
er, other banks within the device are accessible and can be addressed during the cycle.
During the REFpb operation, any of the banks other than the one being refreshed can
be maintained in an active state or accessed by a READ or WRITE command.
When the per-bank REFRESH cycle has completed, the affected bank will be in the idle
state.
After issuing REFpb, the following conditions must be met:
t
• RFCpb must be satisfied before issuing a REFab command
t
• RFCpb must be satisfied before issuing an ACTIVATE command to the same bank
t
• RRD must be satisfied before issuing an ACTIVATE command to a different bank
t
• RFCpb must be satisfied before issuing another REFpb command
An all-bank REFRESH command (REFab) issues a REFRESH command to all banks. All
banks must be idle when REFab is issued (for instance, by issuing a PRECHARGE ALL
command prior to issuing an all-bank REFRESH command). REFab also synchronizes
the bank count between the controller and the SDRAM to zero. The REFab command
must not be issued to the device until the following conditions have been met:
t
• RFCab has been satisfied following the prior REFab command
t
• RFCpb has been satisfied following the prior REFpb command
t
• RP has been satisfied following the prior PRECHARGE commands
After an all-bank REFRESH cycle has completed, all banks will be idle. After issuing RE-
Fab:
t
• RFCab latency must be satisfied before issuing an ACTIVATE command
t
• RFCab latency must be satisfied before issuing a REFab or REFpb command
Table 49: REFRESH Command Scheduling Separation Requirements
Minimum
Symbol
Delay From To
Notes
tRFCab
REFab
REFab
ACTIVATE command to any bank
REFpb
tRFCpb
REFpb
REFab
ACTIVATE command to same bank as REFpb
REFpb
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65
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
REFRESH Command
Table 49: REFRESH Command Scheduling Separation Requirements (Continued)
Minimum
Symbol
Delay From To
Notes
tRRD
REFpb
ACTIVATE command to a different bank than REFpb
ACTIVATE
REFpb affecting an idle bank (different bank than activate)
1
ACTIVATE command to a different bank than the prior ACTIVATE com-
mand
1. A bank must be in the idle state before it is refreshed, so REFab is prohibited following
an ACTIVATE command. REFpb is supported only if it affects a bank that is in the idle
state.
Note:
REFRESH Requirements
1. Minimum Number of REFRESH Commands
Mobile LPDDR2 requires a minimum number, R, of REFRESH (REFab) commands with-
in any rolling refresh window (tREFW = 32 ms @ MR4[2:0] = 011 or TC ≤ 85˚C). For actual
values per density and the resulting average refresh interval (tREFI), see Refresh Re-
quirements.
For tREFW and tREFI refresh multipliers at different MR4 settings, see the MR4 Device
Temperature (MA[7:0] = 04h) table.
For devices supporting per-bank REFRESH, a REFab command can be replaced by a full
cycle of eight REFpb commands.
2. Burst REFRESH Limitation
To limit current consumption, a maximum of eight REFab commands can be issued in
any rolling tREFBW (tREFBW = 4 × 8 × tRFCab). This condition does not apply if REFpb
commands are used.
3. REFRESH Requirements and Self Refresh
If any time within a refresh window is spent in self refresh mode, the number of re-
quired REFRESH commands in that window is reduced to the following:
t
t
SRF
REFW
SRF
R´ = R - RU
= R - RU R ×
t
t
REFI
Where RU represents the round-up function
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
REFRESH Command
Figure 41: tSRF Definition
tREFW
tSRF
Example A1
CKE
Enter self refresh mode
tREFW
Exit self refresh mode
Example B2
tSRF
CKE
Enter self refresh mode
tREFW
Exit self refresh mode
Example C3
tSRF
CKE
Exit self refresh mode
tREFW
Example D4
CKE
tSRF1
tSRF2
Enter self refresh mode
Exit self refresh mode
Enter self refresh mode
Exit self refresh mode
1. Time in self refresh mode is fully enclosed in the refresh window (tREFW).
2. At self refresh entry.
Notes:
3. At self refresh exit.
4. Several intervals in self refresh during one tREFW interval. In this example, tSRF = tSRF1 +
tSRF2.
The mobile LPDDR2 device provides significant flexibility in scheduling a REFRESH
command as long as the required boundary conditions are met (see the tSRF Definition
figure).
In the most straightforward implementations, a REFRESH command should be sched-
uled every tREFI. In this case, self refresh can be entered at any time.
Users may choose to deviate from this regular refresh pattern, for instance, to enable a
period in which no refresh is required. As an example, using a 1Gb LPDDR2 device, the
user can choose to issue a refresh burst of 4096 REFRESH commands at the maximum
supported rate (limited by tREFBW), followed by an extended period without issuing
any REFRESH commands, until the refresh window is complete. The maximum suppor-
ted time without REFRESH commands is calculated as follows: tREFW - (R/8) × tREFBW
= tREFW - R × 4 × tRFCab.
For example, a 1Gb device at TC ≤ 85˚C can be operated without a refresh for up to 32ms
- 4096 × 4 × 130ns ≈ 30ms.
Both the regular and the burst/pause patterns can satisfy refresh requirements if they
are repeated in every 32ms window. It is critical to satisfy the refresh requirement in
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
REFRESH Command
every rolling refresh window during refresh pattern transitions. The supported transi-
tion from a burst pattern to a regular distributed pattern is shown in the Supported
Transition from Repetitive REFRESH Burst figure. If this transition occurs immediately
after the burst refresh phase, all rolling tREFW intervals will meet the minimum re-
quired number of REFRESH commands.
A nonsupported transition is shown below. In this example, the regular refresh pattern
starts after the completion of the pause phase of the burst/pause refresh pattern. For
several rolling tREFW intervals, the minimum number of REFRESH commands is not
satisfied.
Understanding this pattern transition is extremely important, even when only one pat-
tern is employed. In self refresh mode, a regular distributed refresh pattern must be as-
sumed. Micron recommends entering self refresh mode immediately following the
burst phase of a burst/pause refresh pattern; upon exiting self refresh, begin with the
burst phase (see the Recommended Self Refresh Entry and Exit figure).
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
REFRESH Command
Figure 42: Regular Distributed Refresh Pattern
t
t
REFI
REFI
0ms
32ms
64ms
96ms
t
t
REFBW
REFBW
1. Compared to repetitive burst REFRESH with subsequent REFRESH pause.
Notes:
2. As an example, in a 1Gb LPDDR2 device at TC ≤ 85˚C, the distributed refresh pattern has
one REFRESH command per 7.8μs; the burst refresh pattern has one REFRESH command
per 0.52μs, followed by ≈ 30ms without any REFRESH command.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
REFRESH Command
Figure 43: Supported Transition from Repetitive REFRESH Burst
t
t
REFI
REFI
0ms
32ms
64ms
96ms
t
t
REFBW
REFBW
1. Shown with subsequent REFRESH pause to regular distributed refresh pattern.
Notes:
2. As an example, in a 1Gb LPDDR2 device at TC ≤ 85˚C, the distributed refresh pattern has
one REFRESH command per 7.8μs; the burst refresh pattern has one REFRESH command
per 0.52μs, followed by ≈ 30ms without any REFRESH command.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
REFRESH Command
Figure 44: Nonsupported Transition from Repetitive REFRESH Burst
t
t
REFI
REFI
0ms
32ms
64ms
96ms
2
t
REFW = 32ms
Insufficient REFRESH commands
in this refresh window!
t
t
REFBW
REFBW
1. Shown with subsequent REFRESH pause to regular distributed refresh pattern.
Notes:
2. There are only ≈ 2048 REFRESH commands in the indicated tREFW window. This does not
provide the required minimum number of REFRESH commands (R).
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
REFRESH Command
Figure 45: Recommended Self Refresh Entry and Exit
0ms
32ms
Self refresh
t
t
REFBW
REFBW
1. In conjunction with a burst/pause refresh pattern.
Note:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
SELF REFRESH Operation
Figure 46: All-Bank REFRESH Operation
T0
T1
T2
T3
T4
Tx
Tx + 1
Ty
Ty + 1
CK_c
CK_t
CA[9:0] AB
t
t
t
≥ RPab
≥ RFCab
≥ RFCab
CMD PRECHARGE
NOP
NOP
REFab
NO
REFab
NOP
Valid
NOP
Figure 47: Per-Bank REFRESH Operation
T0
T1
Tx
Tx + 1
Tx + 2
Ty
Ty + 1
Tz
Tz + 1
CK_c
CK_t
Bank 1
Row A
Row A
CA[9:0]
AB
t
t
t
≥ RPab
≥ RFCpb
≥ RFCpb
CMD PRECHARGE
NOP
NOP
REFpb
NO
REFpb
NOP
ACTIVATE
NOP
REFRESH to bank 0
REFRESH to bank 1
ACTIVATE command
to bank 1
1. Prior to T0, the REFpb bank counter points to bank 0.
Notes:
2. Operations to banks other than the bank being refreshed are supported during the
tRFCpb period.
SELF REFRESH Operation
The SELF REFRESH command can be used to retain data in the array, even if the rest of
the system is powered down. When in the self refresh mode, the device retains data
without external clocking. The device has a built-in timer to accommodate the SELF
REFRESH operation.
The SELF REFRESH command is executed by taking CKE LOW, CS_n LOW, CA0 LOW,
CA1 LOW, and CA2 HIGH at the rising edge of the clock. CKE must be HIGH during the
previous clock cycle. A NOP command must be driven in the clock cycle following the
POWER-DOWN command. Once the command is registered, CKE must be held LOW to
keep the device in self-refresh mode.
The mobile LPDDR2 device can operate in self refresh mode in both the standard and
extended temperature ranges. The device also manages self refresh power consumption
when the operating temperature changes, resulting in the lowest possible power con-
sumption across the operating temperature range (See IDD Specifications for details).
After the device has entered self refresh mode, all external signals other than CKE are
“Don’t Care.” For proper self refresh operation, power supply pins (VDD1, VDD2, and
VDDQ) must be at valid levels. VDDQ can be turned off during self refresh. If VDDQ is
turned off, VREFDQ must also be turned off. Prior to exiting self refresh, both VDDQ and
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
SELF REFRESH Operation
VREFDQ must be within their respective minimum/maximum operating ranges (see the
Single-Ended AC and DC Input Levels for DQ and DM table). VREFDQ can be at any level
between 0 and VDDQ; VREFCA can be at any level between 0 and VDD2 during self refresh.
Before exiting self refresh, VREFDQ and VREFCA must be within specified limits (See AC
and DC Logic Input Measurement Levels for Single-Ended Signals for details). After en-
tering self refresh mode, the device initiates at least one all-bank REFRESH command
internally during tCKESR. The clock is internally disabled during SELF REFRESH opera-
tion to save power. The device must remain in self refresh mode for at least tCKESR. The
user can change the external clock frequency or halt the external clock one clock after
self refresh entry is registered; however, the clock must be restarted and stable before
the device can exit SELF REFRESH operation.
Exiting self refresh requires a series of commands. First, the clock must be stable prior
to CKE returning HIGH. After the self refresh exit is registered, a minimum delay, at least
equal to the self refresh exit interval (tXSR), must be satisfied before a valid command
can be issued to the device. This provides completion time for any internal refresh in
progress. For proper operation, CKE must remain HIGH throughout tXSR. NOP com-
mands must be registered on each rising clock edge during tXSR.
Using self refresh mode introduces the possibility that an internally timed refresh event
could be missed when CKE is driven HIGH for exit from self refresh mode. Upon exiting
self refresh, at least one REFRESH command (one all-bank command or eight per-bank
commands) must be issued before issuing a subsequent SELF REFRESH command.
Figure 48: SELF REFRESH Operation
t
2 CK(MIN)
CK_c
CK_t
Input clock frequency can be changed
or clock can be stopped during self refresh.
t
t
IHCKE
IHCKE
CKE
CS_n
CMD
t
t
ISCKE
ISCKE
t
t
XSR (MIN)
CKESR (MIN)
Exit
SR
Enter
SR
Valid
NOP
NOP NOP Valid
Enter self refresh mode
Exit self refresh mode
Don’t Care
1. Input clock frequency can be changed or stopped during self refresh, provided that
upon exiting self-refresh, a minimum of two cycles of stable clocks are provided, and the
clock frequency is between the minimum and maximum frequencies for the particular
speed grade.
Notes:
2. The device must be in the all banks idle state prior to entering self refresh mode.
3. tXSR begins at the rising edge of the clock after CKE is driven HIGH.
4. A valid command can be issued only after tXSR is satisfied. NOPs must be issued during
tXSR.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
SELF REFRESH Operation
Partial-Array Self Refresh – Bank Masking
Any device of densities of 64Mb–512Mb is comprised of four banks; a device of 1Gb
density or higher is comprised of eight banks. Each bank can be configured independ-
ently whether or not a SELF REFRESH operation will occur in that bank. One 8-bit
mode register (accessible via the MRW command) is assigned to program the bank-
masking status of each bank up to eight banks. For bank masking bit assignments, see
the MR16 PASR Bank Mask (MA[7:0] = 010h) and MR16 Op-Code Bit Definitions tables.
The mask bit to the bank enables or disables a refresh operation of the entire memory
space within the bank. If a bank is masked using the bank mask register, a REFRESH op-
eration to the entire bank is blocked and bank data retention is not guaranteed in self
refresh mode. To enable a REFRESH operation to a bank, the corresponding bank mask
bit must be programmed as “unmasked.” When a bank mask bit is unmasked, the array
space being refreshed within that bank is determined by the programmed status of the
segment mask bits.
Partial-Array Self Refresh – Segment Masking
Programming segment mask bits is similar to programming bank mask bits. For a den-
sity of 1Gb or higher, eight segments are used for masking (see the MR17 PASR Segment
Mask (MA[7:0] = 011h) and MR17 PASR Segment Mask Definitions tables). A mode reg-
ister is used for programming segment mask bits up to eight bits. For a density of less
than 1Gb, segment masking is not supported.
When the mask bit to an address range (represented as a segment) is programmed as
“masked,” a REFRESH operation to that segment is blocked. Conversely, when a seg-
ment mask bit to an address range is unmasked, refresh to that segment is enabled.
A segment masking scheme can be used in place of or in combination with a bank
masking scheme. Each segment mask bit setting is applied across all banks. For seg-
ment masking bit assignments, see the tables noted above.
Table 50: Bank and Segment Masking Example
Segment Mask (MR17) Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
Bank Mask (MR16)
Segment 0
0
–
1
0
–
0
–
0
–
0
–
0
–
1
0
0
1
0
0
0
0
1
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
Segment 1
–
–
–
–
–
–
Segment 2
M
–
M
–
M
–
M
–
M
–
M
–
Segment 3
Segment 4
–
–
–
–
–
–
Segment 5
–
–
–
–
–
–
Segment 6
–
–
–
–
–
–
Segment 7
M
M
M
M
M
M
1. This table provides values for an 8-bank device with REFRESH operations masked to
banks 1 and 7, and segments 2 and 7.
Note:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
MODE REGISTER READ
MODE REGISTER READ
The MODE REGISTER READ (MRR) command is used to read configuration and status
data from SDRAM mode registers. The MRR command is initiated with CS_n LOW, CA0
LOW, CA1 LOW, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The mode reg-
ister is selected by CA1f–CA0f and CA9r–CA4r. The mode register contents are available
on the first data beat of DQ[7:0] after RL × tCK + tDQSCK + tDQSQ and following the ris-
ing edge of the clock where MRR is issued. Subsequent data beats contain valid but un-
defined content, except in the case of the DQ calibration function, where subsequent
data beats contain valid content as described in the Data Calibration Pattern Descrip-
tion table. All DQS_t,DQS_c are toggled for the duration of the mode register READ
burst.
The MRR command has a burst length of four. MRR operation (consisting of the MRR
command and the corresponding data traffic) must not be interrupted. The MRR com-
mand period (tMRR) is two clock cycles. The MRR command issued to reserved and
write-only registers should returns valid but undefined content on all data beats, and
DQS_t, DQS_c should be toggled.
Figure 49: MRR Timing – RL = 3, tMRR = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK_c
CK_t
RL = 3
Register Register
Register Register
CA[9:0]
CMD
A
A
B
B
tMRR = 2
tMRR = 2
MRR1
NOP2
MRR1
NOP2
Valid
DQS_c
DQS_t
DQ[7:0]3
D
A
D
B
OUT
OUT
DQ[MAX:8]
Transitioning data
Undefined
1. MRRs to DQ calibration registers MR32 and MR40 are described in the Data Calibration
Pattern Description table.
2. Only the NOP command is supported during tMRR.
Notes:
3. Mode register data is valid only on DQ[7:0] on the first beat. Subsequent beats contain
valid but undefined data. DQ[MAX:8] contain valid but undefined data for the duration
of the MRR burst.
4. Minimum MRR to write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 - WL clock cycles.
5. Minimum MRR to MRW latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 clock cycles.
READ bursts and WRITE bursts cannot be truncated by MRR. Following a READ com-
mand, the MRR command must not be issued before BL/2 clock cycles have completed.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
MODE REGISTER READ
Following a WRITE command, the MRR command must not be issued before WL + 1 +
BL/2 + RU(tWTR/tCK) clock cycles have completed. If a READ or WRITE burst is trunca-
ted with a BST command, the effective burst length of the truncated burst should be
used for the BL value.
Figure 50: READ to MRR Timing – RL = 3, tMRR = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK_c
CK_t
1
BL/2
RL = 3
Bank m
Register Register
Col addr a
CA[9:0]
CMD
col addr a
B
B
t
MRR = 2
NOP
2
READ
Valid
MRR
DQS_c
DQS_t
D
D
A0
A0
D
A1
A1
D
D
A2
A2
D
D
A3
A3
D
OUT
B
DQ[7:0]
OUT
OUT
OUT
OUT
OUT
OUT
OUT
D
DQ[MAX:8]
OUT
Transitioning data
Undefined
1. The minimum number of clock cycles from the burst READ command to the MRR com-
mand is BL/2.
2. Only the NOP command is supported during tMRR.
Notes:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
MODE REGISTER READ
Figure 51: Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK_c
CK_t
WL = 1
RL = 3
Bank n
col addr a
Register Register
Col addr a
CA[9:0]
CMD
B
B
t
t
WTR
MRR = 2
NOP2
MRR1
WRITE
Valid
DQS_c
DQS_t
D
A0
D
A1
D
A2
D
A3
IN
DQ
IN
IN
IN
Transitioning data
1. The minimum number of clock cycles from the burst WRITE command to the MRR com-
mand is [WL + 1 + BL/2 + RU(tWTR/tCK)].
2. Only the NOP command is supported during tMRR.
Notes:
Temperature Sensor
The mobile LPDDR2 device features a temperature sensor whose status can be read
from MR4. This sensor can be used to determine an appropriate refresh rate, determine
whether AC timing derating is required in the extended temperature range, and/or
monitor the operating temperature. Either the temperature sensor or the device operat-
ing temperature can be used to determine whether operating temperature require-
ments are being met (see Operating Temperature Range table).
Temperature sensor data can be read from MR4 using the mode register read protocol.
Upon exiting self-refresh or power-down, the device temperature status bits will be no
older than tTSI.
When using the temperature sensor, the actual device case temperature may be higher
than the operating temperature specification that applies for the standard or extended
temperature ranges (see table noted above). For example, TCASE could be above 85˚C
when MR4[2:0] equals 011b.
To ensure proper operation using the temperature sensor, applications must accommo-
date the parameters in the temperature sensor definitions table.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
MODE REGISTER READ
Table 51: Temperature Sensor Definitions and Operating Conditions
Parameter
Description
Symbol
Min/Max
Value
Unit
System temperature Maximum temperature gradient experi-
TempGradient
MAX
System-dependent ˚C/s
gradient
enced by the memory device at the temper-
ature of interest over a range of 2˚C
MR4 READ interval
Time period between MR4 READs from the
system
ReadInterval
tTSI
MAX
MAX
MAX
MAX
System-dependent ms
Temperature sensor Maximum delay between internal updates
interval
32
System-dependent ms
˚C
ms
of MR4
System response
delay
Maximum response time from an MR4 READ SysRespDelay
to the system response
Device temperature Margin above maximum temperature to
TempMargin
2
margin
support controller response
The mobile LPDDR2 device accommodates the temperature margin between the point
at which the device temperature enters the extended temperature range and the point
at which the controller reconfigures the system accordingly. To determine the required
MR4 polling frequency, the system must use the maximum TempGradient and the max-
imum response time of the system according to the following equation:
t
TempGradient × (ReadInterval + TSI + SysRespDelay) ≤ 2°C
For example, if TempGradient is 10˚C/s and the SysRespDelay is 1ms:
10°C
s
× (ReadInterval + 32ms + 1ms) ≤ 2°C
In this case, ReadInterval must not exceed 167ms.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
MODE REGISTER READ
Figure 52: Temperature Sensor Timing
Temp
t
< ( TSI + ReadInterval + SysRespDelay)
Device
Temp
Margin
2°C
MR4
Trip Level
t
TSI
MR4 = 0x03
Temperture sensor update
MR4 = 0x86
MR4 = 0x86
ReadInterval
MR4 = 0x86
MR4 = 0x06
Time
SysRespDelay
MRR MR4 = 0x86
Host MR4 READ
MRR MR4 = 0x03
DQ Calibration
The mobile LPDDR2 device features a DQ calibration function that outputs one of two
predefined system timing calibration patterns. For a x16 device, pattern A (MRR to
MRR32), and pattern B (MRR to MRR40), will return the specified pattern on DQ0 and
DQ8; a x32 device returns the specified pattern on DQ0, DQ8, DQ16, and DQ24.
For a x16 device, DQ[7:1] and DQ[15:9] drive the same information as DQ0 during the
MRR burst. For a x32 device, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] drive the
same information as DQ0 during the MRR burst. MRR DQ calibration commands can
occur only in the idle state.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
MODE REGISTER READ
Figure 53: MR32 and MR40 DQ Calibration Timing – RL = 3, tMRR = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK_c
CK_t
RL = 3
CA[9:0] Reg 32 Reg 32
Reg 40 Reg 40
MRR
tMRR = 2
tMRR = 2
MRR
NOP1
NOP
CMD
DQS_c
DQS_t
Pattern A
Pattern B
DQ0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DQ[7:1]
DQ8
x16
DQ[15:9]
DQ16
x32
DQ[23:17]
DQ24
DQ[31:25]
Transitioning data
Optionally driven the same as DQ0 or 0b
1. The MRR command has a burst length of four.
2. The MRR operation must not be interrupted.
Notes:
3. A MRR to MR32 and MR40 drives valid data on DQ[0] during the entire burst. For a x16
device, DQ[8] drives the same information as DQ[0] during the burst. For a x32 device,
DQ[8], DQ[16], and DQ[24] drive the same information as DQ[0] during the burst.
4. For a x16 device, DQ[7:1] and DQ[15:9] may optionally drive the same information as
DQ[0], or they may drive 0b during the burst. For a x32 device, DQ[7:1], DQ[15:9],
DQ[23:17], and DQ[31:25] may optionally drive the same information as DQ[0], or they
may drive 0b during the burst.
5. The MODE REGISTER command period is tMRR. No command (other than NOP) is al-
lowed during this period.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
MODE REGISTER WRITE Command
Table 52: Data Calibration Pattern Description
Bit Time Bit Time Bit Time Bit Time
Pattern
Pattern A
Pattern B
MR#
MR32
MR40
0
1
2
3
Description
1
0
1
0
Reads to MR32 return DQ calibration pattern A
Reads to MR40 return DQ calibration pattern B
0
0
1
1
MODE REGISTER WRITE Command
The MODE REGISTER WRITE (MRW) command is used to write configuration data to
the mode registers. The MRW command is initiated with CS_n LOW, CA0 LOW, CA1
LOW, CA2 LOW, and CA3 LOW at the rising edge of the clock. The mode register is selec-
ted by CA1f–CA0f, CA9r–CA4r. The data to be written to the mode register is contained
in CA9f–CA2f. The MRW command period is defined by tMRW. A MRW command to
read-only registers has no impact on the functionality of the device.
MRW can be issued only when all banks are in the idle precharge state. One method of
ensuring that the banks are in this state is to issue a PRECHARGE ALL command.
Figure 54: MODE REGISTER WRITE Timing – RL = 3, tMRW = 5
7ꢇ
7ꢄ
7ꢃ
7[
7[ꢀꢍꢀꢄ
7[ꢀꢍꢀꢃ
7\ꢄ
7\ꢀꢍꢀꢄ
7\ꢀꢍꢀꢃ
&.BF
&.BW
W
W
05:
05:
05ꢀDGGU 05ꢀGDWD
05ꢀDGGU 05ꢀGDWD
&$>ꢆꢎꢇ@
&0'
05:
123ꢃ
123ꢃ
05:
123ꢃ
123ꢃ
9DOLG
1. At time Ty, the device is in the idle state.
2. Only the NOP command is supported during tMRW.
Notes:
Table 53: Truth Table for MRR and MRW
Current State
Command
MRR
Intermediate State
Next State
All banks idle
All banks idle
All banks idle
Bank(s) active
Not allowed
Not allowed
All banks idle
Reading mode register, all banks idle
Writing mode register, all banks idle
Resetting, device auto initialization
Reading mode register, bank(s) active
Not allowed
MRW
MRW (RESET)
MRR
Bank(s) active
MRW
MRW (RESET)
Not allowed
MRW RESET Command
The MRW RESET command brings the device to the device auto initialization (reset-
ting) state in the power-on initialization sequence (see step 2. of the RESET Command
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
MODE REGISTER WRITE Command
under Voltage Ramp and Initialization Sequence). The MRW RESET command can be
issued from the idle state. This command resets all mode registers to their default val-
ues. Only the NOP command is supported during tINIT4. After MRW RESET, boot tim-
ings must be observed until the device initialization sequence is complete and the de-
vice is in the idle state. Array data is undefined after the MRW RESET command has
completed. For MRW RESET timing, see Voltage Ramp and Initialization Sequence.
MRW ZQ Calibration Commands
The MRW command is used to initiate a ZQ calibration command that calibrates output
driver impedance across process, temperature, and voltage. LPDDR2-S4 devices sup-
port ZQ calibration. To achieve tighter tolerances, proper ZQ calibration must be per-
formed.
There are four ZQ calibration commands and related timings: tZQINIT, tZQRESET,
tZQCL, and tZQCS. tZQINIT is used for initialization calibration; tZQRESET is used for
resetting ZQ to the default output impedance; tZQCL is used for long calibration(s); and
tZQCS is used for short calibration(s). See the MR10 Calibration (MA[7:0] = 0Ah) table
for ZQ calibration command code definitions.
ZQINIT must be performed for LPDDR2 devices. ZQINIT provides an output impe-
dance accuracy of 15ꢀ. After initialization, the ZQ calibration long (ZQCL) can be used
to recalibrate the system to an output impedance accuracy of 15ꢀ. A ZQ calibration
short (ZQCS) can be used periodically to compensate for temperature and voltage drift
in the system.
ZQRESET resets the output impedance calibration to a default accuracy of 30ꢀ across
process, voltage, and temperature. This command is used to ensure output impedance
accuracy to 30ꢀ when ZQCS and ZQCL commands are not used.
One ZQCS command can effectively correct at least 1.5ꢀ (ZQ correction) of output im-
pedance errors within tZQCS for all speed bins if maximum sensitivities are met as
specified in Output Driver Sensitivity Definition and Output Driver Temperature and
Voltage Sensitivity. The appropriate interval between ZQCS commands can be deter-
mined using these tables and system-specific parameters.
Mobile LPDDR2 devices are subject to temperature drift rate (Tdriftrate) and voltage drift
rate (Vdriftrate) in various applications. To accommodate drift rates and calculate the
necessary interval between ZQCS commands, apply the following formula:
ZQcorrection
(Tsens × Tdriftrate) + (Vsens × Vdriftrate
)
Where Tsens = MAX (dRONdT) and Vsens = MAX (dRONdV) define temperature and volt-
age sensitivities.
For example, if Tsens = 0.75ꢀ/˚C, Vsens = 0.20ꢀ/mV, Tdriftrate = 1˚C/sec, and Vdriftrate
15 mV/sec, then the interval between ZQCS commands is calculated as:
=
1.5
= 0.4s
(0.75 × 1) + (0.20 × 15)
A ZQ calibration command can only be issued when the device is in the idle state with
all banks precharged.
No other activities can be performed on the data bus during calibration periods
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
MODE REGISTER WRITE Command
(tZQINIT, tZQCL, or tZQCS). The quiet time on the data bus helps to calibrate output im-
pedance accurately. There is no required quiet time after the ZQRESET command. If
multiple devices share a single ZQ resistor, only one device can be calibrating at any giv-
en time. After calibration is complete, the ZQ ball circuitry is disabled to reduce power
consumption.
In systems sharing a ZQ resistor between devices, the controller must prevent tZQINIT,
tZQCS, and tZQCL overlap between the devices. ZQRESET overlap is acceptable. If the
ZQ resistor is absent from the system, ZQ must be connected to VDD2. In this situation,
the device must ignore ZQ calibration commands and the device will use the default
calibration settings.
Figure 55: ZQ Timings
7ꢇ
7ꢄ
7ꢃ
7ꢈ
7ꢋ
7ꢉ
7[
7[ꢀꢍꢀꢄ
7[ꢀꢍꢀꢃ
&.BF
&.BW
05ꢀDGGU 05ꢀGDWD
&$>ꢆꢎꢇ@
=4,1,7
&0'
W
=4,1,7
05:
05:
05:
05:
123
123
123
123
123
123
123
123
123
123
123
123
123
123
123
123
123
9DOLG
9DOLG
9DOLG
9DOLG
=4&6
&0'
W
=4&6
123
=4&/
&0'
W
=4&/
123
=45(6(7
&0'
W
=45(6(7
123
1. Only the NOP command is supported during ZQ calibrations
tZQINIT: ZQ calibration initialization period
tZQCS: ZQ calibration short period
Notes:
t ZQCL: ZQ calibration long period
tZQRESET: ZQ calibration reset period
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84
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Power-Down
2. CKE must be registered HIGH continuously during the calibration period.
3. All devices connected to the DQ bus should be High-Z during the calibration process.
ZQ External Resistor Value, Tolerance, and Capacitive Loading
To use the ZQ calibration function, a 240 ohm ( 1ꢀ tolerance) external resistor must be
connected between the ZQ pin and ground. A single resistor can be used for each device
or one resistor can be shared between multiple devices if the ZQ calibration timings for
each device do not overlap. The total capacitive loading on the ZQ pin must be limited
(see the Input/Output Capacitance table).
Power-Down
Power-down is entered synchronously when CKE is registered LOW and CS_n is HIGH
at the rising edge of clock. A NOP command must be driven in the clock cycle following
power-down entry. CKE must not go LOW while MRR, MRW, READ, or WRITE opera-
tions are in progress. CKE can go LOW while any other operation such as ACTIVATE,
PRECHARGE, auto precharge, or REFRESH are in progress, but the power-down IDD
specification will not be applied until such operations are complete.
If power-down occurs when all banks are idle, this mode is referred to as idle power-
down; if power-down occurs when there is a row active in any bank, this mode is refer-
red to as active power-down.
Entering power-down deactivates the input and output buffers, excluding CK_t, CK_c,
and CKE. In power-down mode, CKE must be held LOW; all other input signals are
“Don’t Care.” CKE LOW must be maintained until tCKE is satisfied. VREFCA must be
maintained at a valid level during power-down.
V
DDQ can be turned off during power-down. If VDDQ is turned off, VREFDQ must also be
turned off. Prior to exiting power-down, both VDDQ and VREFDQ must be within their re-
spective minimum/maximum operating ranges (see AC and DC Operating Conditions).
No refresh operations are performed in power-down mode. The maximum duration in
power-down mode is limited only by the refresh requirements outlined in REFRESH
Command.
The power-down state is exited when CKE is registered HIGH. The controller must drive
CS_n HIGH in conjunction with CKE HIGH when exiting the power-down state. CKE
HIGH must be maintained until tCKE is satisfied. A valid, executable command can be
applied with power-down exit latency tXP after CKE goes HIGH. Power-down exit laten-
cy is defined in the AC Timing section.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Power-Down
Figure 56: Power-Down Entry and Exit Timing
t
2 CK(MIN)
CK_c
CK_t
Input clock frequency can be changed
or the input clock can be stopped during power-down.
t
t
t
CKE(MIN)
IHCKE
IHCKE
1
CKE
t
t
ISCKE
ISCKE
CS_n
t
t
XP(MIN)
CKE(MIN)
Exit
PD
Enter
PD
CMD Valid
NOP
NP NOP Valid
Enter power-down mode
Exit power-down mode
Don’t Care
1. Input clock frequency can be changed or the input clock stopped during power-down,
provided that the clock frequency is between the minimum and maximum specified fre-
quencies for the speed grade in use, and that prior to power-down exit, a minimum of
two stable clocks complete.
Note:
Figure 57: CKE Intensive Environment
CK_c
CK_t
t
t
t
t
CKE
CKE
CKE
CKE
CKE
Figure 58: REFRESH-to-REFRESH Timing in CKE Intensive Environments
CK_c
CK_t
tCKE
tCKE
tCKE
tCKE
CKE
tXP
tXP
tREFI
CMD
REFRESH
REFRESH
1. The pattern shown can repeat over an extended period of time. With this pattern, all
AC and DC timing and voltage specifications with temperature and voltage drift are en-
sured.
Note:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Power-Down
Figure 59: READ to Power-Down Entry
BL = 4
T0
T1
T2
RL
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK_c
CK_t
tISCKE
CKE1, 2
CMD
DQ
READ
D
D
D
D
OUT
OUT
OUT OUT
DQS_c
DQS_t
BL = 8
T0
T1
T2
RL
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK_c
CK_t
tISCKE
CKE1, 2
CMD
DQ
READ
D
D
D
D
D
D
D
D
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT
DQS_c
DQS_t
1. CKE must be held HIGH until the end of the burst operation.
Notes:
2. CKE can be registered LOW at (RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1) clock cycles after
the clock on which the READ command is registered.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Power-Down
Figure 60: READ with Auto Precharge to Power-Down Entry
BL = 4
T0
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK_c
CK_t
BL/23
t
ISCKE
RL
CKE1, 2
CMD
DQ
PRE4
READ w/AP
DOUT DOUT DOUT DOUT
DQS_c
DQS_t
BL = 8
T0
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK_c
CK_t
RL
t
BL/23
ISCKE
CKE1, 2
CMD
DQ
PRE4
READ w/AP
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DQS_c
DQS_t
1. CKE must be held HIGH until the end of the burst operation.
Notes:
2. CKE can be registered LOW at (RL + RU(tDQSCK/tCK)+ BL/2 + 1) clock cycles after the
clock on which the READ command is registered.
3. BL/2 with tRTP = 7.5ns and tRAS (MIN) is satisfied.
4. Start internal PRECHARGE.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Power-Down
Figure 61: WRITE to Power-Down Entry
BL = 4
T0
T1
Tm
Tm + 1 Tm + 2 Tm + 3
Tx
Tx + 1
tISCKE
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
CK_c
CK_t
WL
CKE1
CMD
DQ
tWR
WRITE
BL/2
DIN DIN DIN DIN
DQS_c
DQS_t
BL = 8
T0
T1
Tm
Tm +m1 Tm + 2 Tm + 3 Tm + 4 Tm + 5
Tx
Tx + 1
tISCKE
Tx + 2
Tx + 3
Tx + 4
CK_c
CK_t
WL
CKE1
CMD
DQ
tWR
WRITE
BL/2
DIN DIN DIN DIN DIN DIN DIN DIN
DQS_c
DQS_t
1. CKE can be registered LOW at (WL + 1 + BL/2 + RU(tWR/tCK)) clock cycles after the clock
on which the WRITE command is registered.
Note:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Power-Down
Figure 62: WRITE with Auto Precharge to Power-Down Entry
BL = 4
T0
T1
Tm
Tm + 1 Tm + 2 Tm + 3
Tx
Tx + 1
Tx + 2
tISCKE
Tx + 3
Tx + 4
Tx + 5
Tx + 6
CK_c
CK_t
WL
CKE1
CMD
DQ
tWR
2
WRITE w/AP
BL/2
PRE
DIN DIN DIN DIN
DQS_c
DQS_t
BL = 8
T0
T1
Tm
Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5
Tx
Tx + 1
Tx + 2
tISCKE
Tx + 3
Tx + 4
CK_c
CK_t
WL
CKE1
CMD
DQ
tWR
2
WRITE w/AP
BL/2
PRE
DIN DIN DIN DIN DIN DIN DIN DIN
DQS_c
DQS_t
1. CKE can be registered LOW at (WL + 1 + BL/2 + RU(tWR/tCK + 1) clock cycles after the
WRITE command is registered.
Notes:
2. Start internal PRECHARGE.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Power-Down
Figure 63: REFRESH Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
tIHCKE
CKE1
CMD
REFRESH
1. CKE can go LOW tIHCKE after the clock on which the REFRESH command is registered.
Note:
Figure 64: ACTIVATE Command to Power-Down Entry
7ꢇ
7ꢄ
7ꢃ
7ꢈ
7ꢋ
7ꢉ
7ꢅ
7ꢊ
7ꢌ
7ꢆ
7ꢄꢇ
7ꢄꢄ
&.BF
&.BW
W,6&.(
W,+&.(
&.(ꢄ
&0'
$&7,9$7(
1. CKE can go LOW at tIHCKE after the clock on which the ACTIVATE command is regis-
tered.
Note:
Figure 65: PRECHARGE Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
tIHCKE
PRE
CKE1
CMD
1. CKE can go LOW tIHCKE after the clock on which the PRECHARGE command is regis-
tered.
Note:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Deep Power-Down
Figure 66: MRR Command to Power-Down Entry
T0
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK_c
CK_t
tISCKE
RL
CKE1
CMD
MRR
DOUT DOUT DOUT DOUT
DQ
DQS_c
DQS_t
1. CKE can be registered LOW at (RL + RU(tDQSCK/tCK)+ BL/2 + 1) clock cycles after the
clock on which the MRR command is registered.
Note:
Figure 67: MRW Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
t
ISCKE
CKE1
CMD
t
MRW
MRW
1. CKE can be registered LOW tMRW after the clock on which the MRW command is regis-
tered.
Note:
Deep Power-Down
Deep power-down (DPD) is entered when CKE is registered LOW with CS_n LOW, CA0
HIGH, CA1 HIGH, and CA2 LOW at the rising edge of the clock. The NOP command
must be driven in the clock cycle following power-down entry. CKE must not go LOW
while MRR or MRW operations are in progress. CKE can go LOW while other operations
such as ACTIVATE, auto precharge, PRECHARGE, or REFRESH are in progress; however,
deep power-down IDD specifications will not be applied until those operations com-
plete. The contents of the array will be lost upon entering DPD mode.
In DPD mode, all input buffers except CKE, all output buffers, and the power supply to
internal circuitry are disabled within the device. VREFDQ can be at any level between 0
and VDDQ, and VREFCA can be at any level between 0 and VDD2 during DPD. All power
supplies (including VREF) must be within the specified limits prior to exiting DPD (see
AC and DC Operating Conditions).
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Input Clock Frequency Changes and Stop Events
To exit DPD, CKE must be HIGH, tISCKE must be complete, and the clock must be sta-
ble. To resume operation, the device must be fully reinitialized using the power-up initi-
alization sequence.
Figure 68: Deep Power-Down Entry and Exit Timing
CK_c
CK_t
t
2 CK (MIN)
Input clock frequency can be changed
or the input clock can be stopped during DPD.
1, 2
t
t
IHCKE
INIT3
CKE
t
t
ISCKE
ISCKE
CS_n
t
t
RP
DPD
Exit
DPD
Enter
DPD
CMD NOP
NOP
NOP
RESET
Enter DPD mode
Exit DPD mode
Don’t Care
1. The initialization sequence can start at any time after Tx + 1.
Notes:
2. tINIT3 and Tx + 1 refer to timings in the initialization sequence. For details, see Mode
Register Definition.
Input Clock Frequency Changes and Stop Events
Input Clock Frequency Changes and Clock Stop with CKE LOW
During CKE LOW, the mobile LPDDR2 device supports input clock frequency changes
and clock stop under the following conditions:
• Refresh requirements are met
• Only REFab or REFpb commands can be in process
• Any ACTIVATE or PRECHARGE commands have completed prior to changing the fre-
quency
• Related timing conditions,tRCD and tRP, have been met prior to changing the fre-
quency
• The initial clock frequency must be maintained for a minimum of two clock cycles af-
ter CKE goes LOW
• The clock satisfies tCH(abs) and tCL(abs) for a minimum of two clock cycles prior to
CKE going HIGH
For input clock frequency changes, tCK(MIN) and tCK(MAX) must be met for each clock
cycle.
After the input clock frequency is changed and CKE is held HIGH, additional MRW
commands may be required to set the WR, RL, etc. These settings may require adjust-
ment to meet minimum timing requirements at the target clock frequency.
For clock stop, CK_t is held LOW and CK_c is held HIGH.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
NO OPERATION Command
Input Clock Frequency Changes and Clock Stop with CKE HIGH
During CKE HIGH, the LPDDR2 device supports input clock frequency changes and
clock stop under the following conditions:
• REFRESH requirements are met
• Any ACTIVATE, READ, WRITE, PRECHARGE, MRW, or MRR commands must have
completed, including any associated data bursts, prior to changing the frequency
• Related timing conditions, tRCD, tWR, tRP, tMRW, and tMRR, etc., are met
• CS_n must be held HIGH
• Only REFab or REFpb commands can be in process
The device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs)
for a minimum of 2 × tCK + tXP.
For input clock frequency changes, tCK(MIN) and tCK(MAX) must be met for each clock
cycle.
After the input clock frequency is changed, additional MRW commands may be re-
quired to set the WR, RL, etc. These settings may require adjustment to meet minimum
timing requirements at the target clock frequency.
For clock stop, CK_t is held LOW and CK_c is held HIGH.
NO OPERATION Command
The NO OPERATION (NOP) command prevents the device from registering any unwan-
ted commands issued between operations. A NOP command can be issued only at
clock cycle N when the CKE level is constant for clock cycle N-1 and clock cycle N. The
NOP command has two possible encodings: CS_n HIGH at the clock rising edge N; and
CS_n LOW with CA0, CA1, CA2 HIGH at the clock rising edge N.
The NOP command will not terminate a previous operation that is still in process, such
as a READ burst or WRITE burst cycle.
Truth Tables
Truth tables provide complementary information to the state diagram. They also clarify
device behavior and applicable restrictions when considering the actual state of the
banks.
Unspecified operations and timings are illegal. To ensure proper operation after an ille-
gal event, the device must be powered down and then restarted using the specified initi-
alization sequence before normal operation can continue.
Table 54: Command Truth Table
Notes 1–13 apply to all parameters conditions
Command Pins
CA Pins
CKE
CK
Command
CK(n-1) CK(n) CS_n CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 Edge
MRW
H
H
H
H
L
L
L
L
L
MA0 MA1 MA2 MA3 MA4 MA5
OP2 OP3 OP4 OP5 OP6 OP7
X
MA6 MA7 OP0 OP1
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Truth Tables
Table 54: Command Truth Table (Continued)
Notes 1–13 apply to all parameters conditions
Command Pins
CA Pins
CKE
CK
Command
CK(n-1) CK(n) CS_n CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 Edge
MRR
H
H
H
H
H
H
H
X
H
H
H
H
H
H
H
H
H
H
H
X
H
H
L
H
H
H
H
H
H
L
L
X
L
L
L
L
H
MA0 MA1 MA2 MA3 MA4 MA5
MA6 MA7
X
REFRESH
(per bank)
L
L
L
L
L
L
H
H
H
L
X
X
L
X
X
X
X
X
REFRESH
(all banks)
H
X
L
Enter self
refresh
L
X
L
ACTIVATE
(bank)
H
H
H
H
H
H
H
H
H
H
L
L
R0
H
H
R1
L
R8
R2
L
R9
R3
R10
R4
R11
R5
C1
C7
C1
C7
X
R12
R6
C2
C8
C2
C8
X
BA0
R7
BA1
R13
BA1
C10
BA1
C10
BA1
BA2
R14
BA2
C11
BA2
C11
BA2
X
L
WRITE (bank)
RFU
C5
RFU
C6
BA0
C9
X
L
AP
H
C3
L
C4
H
READ (bank)
RFU
C5
RFU
C6
BA0
C9
X
L
AP
H
C3
H
C4
L
PRECHARGE
(bank)
H
AB
BA0
X
L
X
X
X
X
X
BST
H
H
H
H
H
H
H
H
L
L
L
X
X
L
Enter DPD
NOP
X
X
X
L
X
L
H
H
L
H
H
X
L
Maintain PD,
SREF, DPD,
(NOP)
L
L
X
NOP
H
H
L
H
H
L
H
X
H
X
X
X
X
X
Maintain PD,
SREF, DPD,
(NOP)
L
L
Enter power-
down
H
X
L
L
H
X
X
X
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Truth Tables
Table 54: Command Truth Table (Continued)
Notes 1–13 apply to all parameters conditions
Command Pins
CA Pins
CKE
CK
Command
CK(n-1) CK(n) CS_n CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 Edge
Exit PD, SREF,
DPD
L
H
H
H
X
X
X
X
1. All commands are defined by the current state of CS_n, CA0, CA1, CA2, CA3, and CKE at
the rising edge of the clock.
Notes:
2. Bank addresses (BA) determine which bank will be operated upon.
3. AP HIGH during a READ or WRITE command indicates that an auto precharge will occur
to the bank associated with the READ or WRITE command.
4. X indicates a “Don’t Care” state, with a defined logic level, either HIGH (H) or LOW (L).
5. Self refresh exit and DPD exit are asynchronous.
6. VREF must be between 0 and VDDQ during self refresh and DPD operation.
7. CAxr refers to command/address bit “x” on the rising edge of clock.
8. CAxf refers to command/address bit “x” on the falling edge of clock.
9. CS_n and CKE are sampled on the rising edge of the clock.
10. Per-bank refresh is supported only in devices with eight banks.
11. The least-significant column address C0 is not transmitted on the CA bus, and is inferred
to be zero.
12. RFU needs to input “H” or “L“ (but a defined logic level).
13. AB “high”during Precharge command indicates that all bank Precharge will occur. In
this case, Bank Address is don’t care.
Table 55: CKE Truth Table
Notes 1–5 apply to all parameters and conditions; L = LOW, H = HIGH, X = “Don’t Care”
Current State
CKEn-1
CKEn
CS_n
Command n Operation n
Next State
Notes
6, 7
Active
power-down
L
L
X
X
Maintain active power-down
Active
power-down
L
L
H
L
H
X
NOP
X
Exit active power-down
Active
Idle power-
down
Maintain idle power-down
Idle
power-down
L
L
H
L
H
X
NOP
X
Exit idle power-down
Idle
6, 7
Resetting idle
power-down
Maintain resetting power-down
Resetting
power-down
L
L
H
L
H
X
NOP
X
Exit resetting power-down
Maintain deep power-down
Idle or resetting 6, 7, 8
Deep power-
down
Deep
power-down
L
L
H
L
H
X
H
H
NOP
X
Exit deep power-down
Maintain self refresh
Exit self refresh
Power-on
Self refresh
Idle
9
Self refresh
L
H
L
NOP
NOP
10, 11
Bank(s) active
H
Enter active power-down
Active
power-down
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Truth Tables
Table 55: CKE Truth Table (Continued)
Notes 1–5 apply to all parameters and conditions; L = LOW, H = HIGH, X = “Don’t Care”
Current State
CKEn-1
CKEn
CS_n
Command n Operation n
Next State
Notes
All banks idle
H
L
H
NOP
Enter idle power-down
Idle
power-down
H
H
H
H
L
L
L
L
Enter self re- Enter self refresh
fresh
Self refresh
DPD
Enter deep power-down
Deep
power-down
Resetting
L
H
NOP
Enter resetting power-down
Resetting
power-down
Other states
H
Refer to the command truth table
1. Current state = the state of the device immediately prior to the clock rising edge n.
Notes:
2. All states and sequences not shown are illegal or reserved unless explicitly described
elsewhere in this document.
3. CKEn = the logic state of CKE at clock rising edge n; CKEn-1 was the state of CKE at the
previous clock edge.
4. CS_n= the logic state of CS_n at the clock rising edge n.
5. Command n = the command registered at clock edge n, and operation n is a result of
command n.
6. Power-down exit time (tXP) must elapse before any command other than NOP is issued.
7. The clock must toggle at least twice prior to the tXP period.
8. Upon exiting the resetting power-down state, the device will return to the idle state if
tINIT5 has expired.
9. The DPD exit procedure must be followed as described in Deep Power Down.
10. Self refresh exit time (tXSR) must elapse before any command other than NOP is issued.
11. The clock must toggle at least twice prior to the tXSR time.
Table 56: Current State Bank n to Command to Bank n Truth Table
Notes 1–5 apply to all parameters and conditions
Current State
Command
NOP
Operation
Next State
Current state
Active
Notes
Any
Idle
Continue previous operation
Select and activate row
ACTIVATE
Refresh (per bank)
Refresh (all banks)
MRW
Begin to refresh
Refreshing (per bank)
Refreshing (all banks)
MR writing
6
7
7
Begin to refresh
Load value to mode register
Read value from mode register
Begin device auto initialization
Deactivate row(s) in bank or banks
Select column and start read burst
Select column and start write burst
Read value from mode register
Deactivate row(s) in bank or banks
MRR
Idle, MR reading
Resetting
RESET
7, 8
PRECHARGE
READ
Precharging
9, 10
Row active
Reading
WRITE
Writing
MRR
Active MR reading
Precharging
PRECHARGE
9
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Truth Tables
Table 56: Current State Bank n to Command to Bank n Truth Table (Continued)
Notes 1–5 apply to all parameters and conditions
Current State
Command
READ
WRITE
BST
Operation
Next State
Reading
Notes
11, 12
11, 12, 13
14
Reading
Select column and start new read burst
Select column and start write burst
Read burst terminate
Writing
Active
Writing
WRITE
READ
BST
Select column and start new write burst
Select column and start read burst
Write burst terminate
Writing
11, 12
11, 12, 15
14
Reading
Active
Power-on
Resetting
RESET
MRR
Begin device auto initialization
Read value from mode register
Resetting
Resetting MR reading
7, 9
1. Values in this table apply when both CKEn -1 and CKEn are HIGH, and after tXSR or tXP
Notes:
has been met, if the previous state was power-down.
2. All states and sequences not shown are illegal or reserved.
3. Current state definitions:
Idle: The bank or banks have been precharged, and tRP has been met.
Active: A row in the bank has been activated, and tRCD has been met. No data bursts or
accesses and no register accesses are in progress.
Reading: A READ burst has been initiated with auto precharge disabled and has not yet
terminated or been terminated.
Writing: A WRITE burst has been initiated with auto precharge disabled and has not yet
terminated or been terminated.
4. These states must not be interrupted by a command issued to the same bank. NOP com-
mands or supported commands to the other bank must be issued on any clock edge oc-
curring during these states. Supported commands to the other banks are determined by
that bank’s current state and the definitions given here.
Precharge: Starts with registration of a PRECHARGE command and ends when tRP is
met. After tRP is met, the bank is in the idle state.
Row activate: Starts with registration of an ACTIVATE command and ends when tRCD is
met. After tRCD is met, the bank is in the active state.
READ with AP enabled: Starts with registration of a READ command with auto pre-
charge enabled and ends when tRP is met. After tRP is met, the bank is in the idle state.
WRITE with AP enabled: Starts with registration of a WRITE command with auto pre-
charge enabled and ends when tRP is met. After tRP is met, the bank is in the idle state.
5. These states must not be interrupted by any executable command. NOP commands must
be applied to each rising clock edge during these states.
Refresh (per bank): Starts with registration of a REFRESH (per bank) command and ends
when tRFCpb is met. After tRFCpb is met, the bank is in the idle state.
Refresh (all banks): Starts with registration of a REFRESH (all banks) command and ends
when tRFCab is met. After tRFCab is met, the device is in the all banks idle state.
Idle MR reading: Starts with registration of the MRR command and ends when tMRR is
met. After tMRR is met, the device is in the all banks idle state.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Truth Tables
Resetting MR reading: Starts with registration of the MRR command and ends when
tMRR is met. After tMRR is met, the device is in the all banks idle state.
Active MR reading: Starts with registration of the MRR command and ends when tMRR
is met. After tMRR is met, the bank is in the active state.
MR writing: Starts with registration of the MRW command and ends when tMRW is met.
After tMRW is met, the device is in the all banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
tRP is met. After tRP is met, the device is in the all banks idle state.
6. Bank-specific; requires that the bank is idle and no bursts are in progress.
7. Not bank-specific; requires that all banks are idle and no bursts are in progress.
8. Not bank-specific.
9. This command may or may not be bank specific. If all banks are being precharged, they
must be in a valid state for precharging.
10. If a PRECHARGE command is issued to a bank in the idle state, tRP still applies.
11. A command other than NOP should not be issued to the same bank while a burst READ
or burst WRITE with auto precharge is enabled.
12. The new READ or WRITE command could be auto precharge enabled or auto precharge
disabled.
13. A WRITE command can be issued after the completion of the READ burst; otherwise, a
BST must be issued to end the READ prior to asserting a WRITE command.
14. Not bank-specific. The BST command affects the most recent READ/WRITE burst started
by the most recent READ/WRITE command, regardless of bank.
15. A READ command can be issued after completion of the WRITE burst; otherwise, a BST
must be used to end the WRITE prior to asserting another READ command.
Table 57: Current State Bank n to Command to Bank m Truth Table
Notes 1–6 apply to all parameters and conditions
Current State
of Bank n
Command to Bank m Operation
Next State for Bank m
Notes
Any
NOP
Any
Continue previous operation
Current state of bank m
Idle
Any command supported to bank m
Select and activate row in bank m
–
7
8
9
Row activating,
active, or pre-
charging
ACTIVATE
READ
Active
Reading
Select column and start READ burst
from bank m
WRITE
Select column and start WRITE burst to
Writing
9
bank m
PRECHARGE
MRR
Deactivate row(s) in bank or banks
READ value from mode register
Precharging
10
Idle MR reading or active 11, 12, 13
MR reading
BST
READ or WRITE burst terminates an on-
Active
7
going READ/WRITE from/to bank m
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Truth Tables
Table 57: Current State Bank n to Command to Bank m Truth Table (Continued)
Notes 1–6 apply to all parameters and conditions
Current State
of Bank n
Command to Bank m Operation
Next State for Bank m
Notes
Reading
READ
Select column and start READ burst
Reading
9
(auto precharge
disabled)
from bank m
WRITE
Select column and start WRITE burst to
Writing
9, 14
bank m
ACTIVATE
PRECHARGE
READ
Select and activate row in bank m
Active
Precharging
Reading
Deactivate row(s) in bank or banks
10
Writing
Select column and start READ burst
9, 15
(auto precharge
disabled)
from bank m
WRITE
Select column and start WRITE burst to
Writing
9
bank m
ACTIVATE
PRECHARGE
READ
Select and activate row in bank m
Active
Precharging
Reading
Deactivate row(s) in bank or banks
10
Reading with
Select column and start READ burst
9, 16
auto precharge
from bank m
WRITE
Select column and start WRITE burst to
Writing
9, 14, 16
bank m
ACTIVATE
PRECHARGE
READ
Select and activate row in bank m
Active
Precharging
Reading
Deactivate row(s) in bank or banks
10
Writing with
Select column and start READ burst
9, 15, 16
auto precharge
from bank m
WRITE
Select column and start WRITE burst to
Writing
9, 16
bank m
ACTIVATE
PRECHARGE
RESET
Select and activate row in bank m
Deactivate row(s) in bank or banks
Begin device auto initialization
Read value from mode register
Active
Precharging
10
Power-on
Resetting
Resetting
17, 18
MRR
Resetting MR reading
1. This table applies when: the previous state was self refresh or power-down; after tXSR
Notes:
or tXP has been met; and both CKEn -1 and CKEn are HIGH.
2. All states and sequences not shown are illegal or reserved.
3. Current state definitions:
Idle: The bank has been precharged and tRP has been met.
Active: A row in the bank has been activated, tRCD has been met, no data bursts or ac-
cesses and no register accesses are in progress.
Read: A READ burst has been initiated with auto precharge disabled and the READ has
not yet terminated or been terminated.
Write: A WRITE burst has been initiated with auto precharge disabled and the WRITE
has not yet terminated or been terminated.
4. Refresh, self refresh, and MRW commands can be issued only when all banks are idle.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Truth Tables
5. A BST command cannot be issued to another bank; it applies only to the bank represen-
ted by the current state.
6. These states must not be interrupted by any executable command. NOP commands must
be applied during each clock cycle while in these states:
Idle MRR: Starts with registration of the MRR command and ends when tMRR has been
met. After tMRR is met, the device is in the all banks idle state.
Reset MRR: Starts with registration of the MRR command and ends when tMRR has been
met. After tMRR is met, the device is in the all banks idle state.
Active MRR: Starts with registration of the MRR command and ends when tMRR has
been met. After tMRR is met, the bank is in the active state.
MRW: Starts with registration of the MRW command and ends when tMRW has been
met. After tMRW is met, the device is in the all banks idle state.
7. BST is supported only if a READ or WRITE burst is ongoing.
8. tRRD must be met between the ACTIVATE command to bank n and any subsequent
ACTIVATE command to bank m.
9. READs or WRITEs listed in the command column include READs and WRITEs with or
without auto precharge enabled.
10. This command may or may not be bank-specific. If all banks are being precharged, they
must be in a valid state for precharging.
11. MRR is supported in the row-activating state.
12. MRR is supported in the precharging state.
13. The next state for bank m depends on the current state of bank m (idle, row-activating,
precharging, or active).
14. A WRITE command can be issued after the completion of the READ burst; otherwise a
BST must be issued to end the READ prior to asserting a WRITE command.
15. A READ command can be issued after the completion of the WRITE burst; otherwise, a
BST must be issued to end the WRITE prior to asserting another READ command.
16. A READ with auto precharge enabled or a WRITE with auto precharge enabled can be
followed by any valid command to other banks provided that the timing restrictions in
the PRECHARGE and Auto Precharge Clarification table are met.
17. Not bank-specific; requires that all banks are idle and no bursts are in progress.
18. RESET command is achieved through MODE REGISTER WRITE command.
Table 58: DM Truth Table
Functional Name
Write enable
DM
L
DQ
Valid
X
Notes
1
1
Write inhibit
H
1. Used to mask write data, and is provided simultaneously with the corresponding input
data.
Note:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses greater than those listed below may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other
conditions outside those indicated in the operational sections of this document is not
implied. Exposure to absolute maximum rating conditions for extended periods may
adversely affect reliability.
Table 59: Absolute Maximum DC Ratings
Parameter
Symbol
VDD1
Min
–0.4
–0.4
–0.4
–0.4
–55
Max
+2.3
+1.6
+1.6
+1.6
+125
Unit
V
Notes
VDD1 supply voltage relative to VSS
VDD2 supply voltage relative to VSS
VDDQ supply voltage relative to VSSQ
Voltage on any ball relative to VSS
Storage temperature
1
1
VDD2 (1.2V)
VDDQ
V
V
1, 3
VIN, VOUT
TSTG
V
˚C
4
1. See 1. Voltage Ramp under Power Up.
2. VREFCA 0.6 ≤ VDD2; however, VREFCA may be ≥ VDD2 provided that VREFCA ≤ 300mV.
Notes:
3. VREFDQ 0.6 ≤ VDDQ; however, VREFDQ may be ≥ VDDQ provided that VREFDQ ≤ 300mV.
4. Storage temperature is the case surface temperature on the center/top side of the de-
vice. For measurement conditions, refer to the JESD51-2 standard.
Input/Output Capacitance
Table 60: Input/Output Capacitance
Note 1 applies to all parameters and conditions
Parameter
Symbol
CL1
MIN
1.0
MAX
3.0
Unit
pF
Notes
2
Input capacitance, CK and CK#
Input capacitance, all other LPDDR2 input only balls
Input/output capacitance, DQ, DM, DQS, DQS#
Input/output capacitance, ZQ
CL2
1.0
3.0
pF
2
CI/O
2.0
3.5
pF
2, 3
2, 3
CZQ
2.0
3.0
pF
1. This parameter is not subject to production testing. It is verified by design and character-
ization. The capacitance is measured according to JEP147 (procedure for measuring in-
put capacitance using a vector network analyzer), with VDD1, VDD2, VDDQ, VSS, and VSSQ
applied; all other pins are left floating.
Notes:
2. These parameters are measured on f = 100 MHz, VOUT = VDDQ2, TA = 25°C.
3. DOUT circuits are disabled.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Electrical Specifications – IDD Specifications and Conditions
The following definitions and conditions are used in the IDD measurement tables unless
stated otherwise:
• LOW: VIN ≤ VIL(DC)max
• HIGH: VIN ≥ VIH(DC)min
• STABLE: Inputs are stable at a HIGH or LOW level
• SWITCHING: See the following three tables
Table 61: Switching for CA Input Signals
Notes 1–3 apply to all parameters and conditions
CK_t Rising/ CK_t Fall- CK_t Rising/ CK_t Fall- CK_t Rising/ CK_t Fall- CK_t Rising/ CK_t Fall-
CK_c Fall-
ing
ing/ CK_c
Rising
CK_c Fall-
ing
ing/ CK_c
Rising
CK_c Fall-
ing
ing/ CK_c
Rising
CK_c Fall-
ing
ing/ CK_c
Rising
Cycle
CS_n
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
N
N + 1
HIGH
N + 2
HIGH
N + 3
HIGH
HIGH
H
H
H
H
H
H
H
H
H
H
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
1. CS# must always be driven HIGH.
2. For each clock cycle, 50% of the CA bus is changing between HIGH and LOW.
Notes:
3. The noted pattern (N, N + 1, N + 2, N + 3...) is used continuously during IDD measure-
ment for IDD values that require switching on the CA bus.
Table 62: Switching for IDD4R
Clock Cycle
Number
Clock
Rising
Falling
Rising
Falling
Rising
Falling
Rising
CKE
H
CS_n
Command
Read_Rising
Read_Falling
NOP
CA[2:0]
HLH
LLL
CA[9:3]
LHLHLHL
LLLLLLL
All DQ
L
L
N
L
L
H
N
H
H
H
L
N +1
N + 1
N + 2
N + 2
N + 3
LLL
LLLLLLL
H
L
H
NOP
HLH
HLH
LLL
HLHLLHL
HLHLLHL
HHHHHHH
HHHHHHH
H
Read_Rising
Read_Falling
NOP
H
H
H
H
L
H
H
LLL
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 62: Switching for IDD4R (Continued)
Clock Cycle
Number
Clock
CKE
CS_n
Command
CA[2:0]
CA[9:3]
All DQ
Falling
H
H
N + 3
NOP
HLH
LHLHLHL
L
1. Data strobe (DQS) is changing between HIGH and LOW with every clock cycle.
2. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4R
Notes:
.
Table 63: Switching for IDD4W
Clock Cycle
Number
Clock
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
CKE
H
CS_n
Command
Write_Rising
Write_Falling
NOP
CA[2:0]
HLL
CA[9:3]
LHLHLHL
LLLLLLL
All DQ
L
L
N
L
L
H
N
LLL
H
H
H
L
N +1
N + 1
N + 2
N + 2
N + 3
N + 3
LLL
LLLLLLL
H
L
H
NOP
HLH
HLL
HLHLLHL
HLHLLHL
HHHHHHH
HHHHHHH
LHLHLHL
H
Write_Rising
Write_Falling
NOP
H
H
H
L
H
L
LLL
H
H
H
LLL
H
NOP
HLH
1. Data strobe (DQS) is changing between HIGH and LOW with every clock cycle.
2. Data masking (DM) must always be driven LOW.
Notes:
3. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4W
.
Table 64: IDD Specification Parameters and Operating Conditions
Notes 1–3 apply to all parameters and conditions
Parameter/Condition
Symbol
IDD01
Power Supply Notes
Operating one bank active-precharge current (SDRAM): tCK = tCKmin;
tRC = tRCmin; CKE is HIGH; CS_n is HIGH between valid commands; CA bus in-
puts are switching; Data bus inputs are stable
VDD1
VDD2
IDD02
IDD0in
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
4
4
4
4
Idle power-down standby current: tCK = tCKmin; CKE is LOW; CS_n is
HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are sta-
ble
IDD2P1
IDD2P2
IDD2P,in
IDD2PS1
IDD2PS2
IDD2PS,in
IDD2N1
IDD2N2
IDD2N,in
Idle power-down standby current with clock stop: CK_t = LOW, CK_c =
HIGH; CKE is LOW; CS_n is HIGH; All banks are idle; CA bus inputs are stable;
Data bus inputs are stable
Idle non-power-down standby current: tCK = tCKmin; CKE is HIGH; CS_n is
HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are sta-
ble
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 64: IDD Specification Parameters and Operating Conditions (Continued)
Notes 1–3 apply to all parameters and conditions
Parameter/Condition
Symbol
IDD2NS1
IDD2NS2
IDD2NS,in
IDD3P1
Power Supply Notes
Idle non-power-down standby current with clock stopped: CK_t = LOW;
CK_c = HIGH; CKE is HIGH; CS_n is HIGH; All banks are idle; CA bus inputs are
stable; Data bus inputs are stable
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
4
4
4
4
4
Active power-down standby current: tCK = tCKmin; CKE is LOW; CS_n is
HIGH; One bank is active; CA bus inputs are switching; Data bus inputs are
stable
IDD3P2
IDD3P,in
IDD3PS1
IDD3PS2
IDD3PS,in
IDD3N1
Active power-down standby current with clock stop: CK_t = LOW, CK_c
= HIGH; CKE is LOW; CS_n is HIGH; One bank is active; CA bus inputs are sta-
ble; Data bus inputs are stable
Active non-power-down standby current: tCK = tCKmin; CKE is HIGH;
CS_n is HIGH; One bank is active; CA bus inputs are switching; Data bus inputs
are stable
IDD3N2
IDD3N,in
IDD3NS1
IDD3NS2
IDD3NS,in
IDD4R1
Active non-power-down standby current with clock stopped: CK_t =
LOW, CK_c = HIGH CKE is HIGH; CS_n is HIGH; One bank is active; CA bus in-
puts are stable; Data bus inputs are stable
Operating burst READ current: tCK = tCKmin; CS_n is HIGH between valid
commands; One bank is active; BL = 4; RL = RL (MIN); CA bus inputs are
switching; 50% data change each burst transfer
IDD4R2
Operating burst WRITE current: tCK = tCKmin; CS_n is HIGH between valid
commands; One bank is active; BL = 4; WL = WLmin; CA bus inputs are switch-
ing; 50% data change each burst transfer
IDD4W1
IDD4W2
IDD4W,in
IDD51
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
4
4
All-bank REFRESH burst current: tCK = tCKmin; CKE is HIGH between valid
commands; tRC = tRFCabmin; Burst refresh; CA bus inputs are switching; Data
bus inputs are stable
IDD52
IDD5IN
All-bank REFRESH average current: tCK = tCKmin; CKE is HIGH between
valid commands; tRC = tREFI; CA bus inputs are switching; Data bus inputs are
stable
IDD5AB1
IDD5AB2
IDD5AB,in
IDD5PB1
IDD5PB2
IDD5PB,in
IDD61
4
5
Per-bank REFRESH average current: tCK = tCKmin; CKE is HIGH between
valid commands; tRC = tREFI/8; CA bus inputs are switching; Data bus inputs
are stable
5
4, 5
6
Self refresh current (–30˚C to +85˚C): CK_t = LOW, CK_c = HIGH; CKE is
LOW; CA bus inputs are stable; Data bus inputs are stable; Maximum 1x self
refresh rate
IDD62
6
IDD6IN
4, 6
6, 7
6, 7
4, 6, 7
Self refresh current (+85˚C to +105˚C): CK_t = LOW, CK_c = HIGH; CKE is
LOW; CA bus inputs are stable; Data bus inputs are stable
IDD6ET1
IDD6ET2
IDD6ET,in
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC and DC Operating Conditions
Table 64: IDD Specification Parameters and Operating Conditions (Continued)
Notes 1–3 apply to all parameters and conditions
Parameter/Condition
Symbol
IDD81
Power Supply Notes
Deep power-down current: CK_t = LOW, CK_c = HIGH; CKE is LOW; CA bus
inputs are stable; Data bus inputs are stable
VDD1
VDD2
VDDQ
7
7
IDD82
IDD8IN
4, 7
1. IDD values are the maximum of the distribution of the arithmetic mean.
2. IDD current specifications are tested after the device is properly initialized.
Notes:
3. The 1x self refresh rate is the rate at which the device is refreshed internally during self
refresh before going into the extended temperature range.
4. Measured currents are the sum of VDDQ and VDD2
.
5. Per-bank REFRESH is only applicable for LPDDR2-S4 device densities 1Gb or higher.
6. This is the general definition that applies to full-array self refresh. Refer to "IDD6 Full
and Partial Array Self-Refresh Current" for details of Partial Array Self Refresh IDD6
specification.
7. IDD6ET and IDD8 are typical values, sampled only and not tested.
AC and DC Operating Conditions
An operation or timing that is not specified is illegal. To ensure proper operation, the
device must be initialized properly.
Table 65: Recommended DC Operating Conditions
LPDDR2-S4B
Symbol
Min
1.70
1.14
1.14
Typ
1.80
1.20
1.20
Max
1.95
1.30
1.30
Power Supply
Core power 1
Unit
V
1
VDD1
VDD2
VDDQ
Core power 2
V
I/O buffer power
V
1. VDD1 uses significantly less power than VDD2
.
Note:
Table 66: Input Leakage Current
Parameter/Condition
Symbol
Min
Max
Unit Notes
Input leakage current: For CA, CKE, CS_n, CK_t, CK_c; Any input 0V ≤
VIN ≤ VDD2; (All other pins not under test = 0V)
IL
–2
2
μA
1
VREF supply leakage current: VREFDQ = VDDQ/2, or VREFCA = VDD2/2; (All
IVREF
–1
1
μA
2
other pins not under test = 0V)
1. Although DM is for input only, the DM leakage must match the DQ and DQS_t/DQS_c
output leakage specification.
Notes:
2. The minimum limit requirement is for testing purposes. The leakage current on VREFCA
and VREFDQ pins should be minimal.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
Table 67: Operating Temperature Range
Parameter/Condition
Symbol
Min
–30
–40
–40
Max
+85
Unit
˚C
1
Standard (WT) temperature range
Industrial (IT) temperature range
Automotive (AT) temperature range
TCASE
+85
˚C
+105
˚C
1. Operating temperature is the case surface temperature at the center of the top side of
the device. For measurement conditions, refer to the JESD51-2 standard.
Notes:
2. Some applications require operation in the maximum case temperature range, between
85˚C and 105˚C. For some LPDDR2 devices, derating may be necessary to operate in this
range (see the MR4 Device Temperature (MA[7:0] = 04h) table).
3. Either the device operating temperature or the temperature sensor can be used to set
an appropriate refresh rate, determine the need for AC timing derating, and/or monitor
the operating temperature (see Temperature Sensor). When using the temperature sen-
sor, the actual device case temperature may be higher than the TCASE rating that applies
for the operating temperature range. For example, TCASE could be above 85˚C when the
temperature sensor indicates a temperature of less than 85˚C.
AC and DC Logic Input Measurement Levels for Single-Ended Signals
Table 68: Single-Ended AC and DC Input Levels for CA and CS_n Inputs
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Symbol
VIHCA(AC)
VILCA(AC)
VIHCA(DC)
VILCA(DC)
Parameter
Min
VREF + 0.220
Note 2
Max
Min
VREF + 0.300
Note 2
Max
Unit Notes
AC input logic HIGH
AC input logic LOW
DC input logic HIGH
DC input logic LOW
Note 2
Note 2
V
V
V
V
V
1, 2
1, 2
1
VREF - 0.220
VDD2
VREF - 0.300
VDD2
VREF + 0.130
VSS
VREF + 0.200
VSS
VREF - 0.130
0.51 × VDD2
VREF - 0.200
0.51 × VDD2
1
VREFCA(DC) Reference voltage for
CA and CS_n inputs
0.49 × VDD2
0.49 × VDD2
3, 4
1. For CA and CS_n input-only pins. VREF = VREFCA(DC)
2. See Overshoot and Undershoot Definition.
.
Notes:
3. The AC peak noise on VREFCA could prevent VREFCA from deviating more than 1% VDD2
from VREFCA(DC) (for reference, approximately 12mV).
4. For reference, approximately VDD2/2 12mV.
Table 69: Single-Ended AC and DC Input Levels for CKE
Symbol
VIHCKE
Parameter
Min
Max
Note 1
Unit Notes
CKE input HIGH level
CKE input LOW level
0.8 × VDD2
Note 1
V
V
1
1
VILCKE
0.2 × VDD2
1. See Overshoot and Undershoot Definition.
Note:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
Table 70: Single-Ended AC and DC Input Levels for DQ and DM
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Symbol
VIHDQ(AC)
VILDQ(AC)
VIHDQ(DC)
VILDQ(DC)
Parameter
Min
VREF + 0.220
Note 2
Max
Min
VREF + 0.300
Note 2
Max
Unit Notes
AC input logic HIGH
AC input logic LOW
DC input logic HIGH
DC input logic LOW
Note 2
Note 2
V
V
V
V
V
1, 2
1, 2
1
VREF - 0.220
VDDQ
VREF - 0.300
VDDQ
VREF + 0.130
VSS
VREF + 0.200
VSS
VREF - 0.130
0.51 × VDDQ
VREF - 0.200
0.51 × VDDQ
1
VREFDQ(DC) Reference voltage for
DQ and DM inputs
0.49 × VDDQ
0.49 × VDDQ
3, 4
1. For DQ input-only pins. VREF = VREFDQ(DC)
.
Notes:
2. See Overshoot and Undershoot Definition.
3. The AC peak noise on VREFDQ could prevent VREFDQ from deviating more than 1% VDDQ
from VREFDQ(DC) (for reference, approximately 12mV).
4. For reference, approximately. VDDQ/2 12mV.
VREF Tolerances
The DC tolerance limits and AC noise limits for the reference voltages VREFCA and
VREFDQ are illustrated below. This figure shows a valid reference voltage VREF(t) as a
function of time. VDD is used in place of VDD2 for VREFCA, and VDDQ for VREFDQ. VREF(DC)
is the linear average of VREF(t) over a very long period of time (for example, 1 second)
and is specified as a fraction of the linear average of VDDQ or VDD2, also over a very long
period of time (for example, 1 second). This average must meet the MIN/MAX require-
ments in the Single-Ended AC and DC Input Levels for CA and CS_n Inputs table. Addi-
tionally, VREF(t) can temporarily deviate from VREF(DC) by no more than 1ꢀ VDD. VREF(t)
cannot track noise on VDDQ or VDD2 if doing so would force VREF outside these specifica-
tions.
Figure 69: VREF DC Tolerance and VREF AC Noise Limits
VDD
VREF(AC) noise
VREF(t)
VREF(DC)max
VREF(DC)
VDD/2
VREF(DC)min
VSS
Time
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and
VIL(DC) are dependent on VREF
.
V
REF DC variations affect the absolute voltage a signal must reach to achieve a valid
HIGH or LOW, as well as the time from which setup and hold times are measured. When
VREF is outside the specified levels, devices will function correctly with appropriate tim-
ing deratings as long as:
• VREF is maintained between 0.44 x VDDQ (or VDD2) and 0.56 x VDDQ (or VDD2), and
• the controller achieves the required single-ended AC and DC input levels from instan-
taneous VREF (see the Single-Ended AC and DC Input Levels for CA and CS_n Inputs
table).
System timing and voltage budgets must account for VREF deviations outside this range.
The setup/hold specification and derating values must include time and voltage associ-
ated with VREF AC noise. Timing and voltage effects due to AC noise on VREF up to the
specified limit ( 1ꢀ VDD) are included in LPDDR2 timings and their associated derat-
ings.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
Input Signal
Figure 70: LPDDR2-466 to LPDDR2-1066 Input Signal
V
and V levels with ringback
IH
IL
V
+ 0.35V
1.550V
DD
narrow pulse width
1.200V
V
DD
Minimum V and V levels
IL
IH
V
IH(AC)
0.820V
0.730V
0.820V
0.730V
V
IH(AC)
V
IH(DC)
V
IH(DC)
V
V
+ AC noise
+ DC error
0.624V
0.612V
0.600V
0.588V
0.576V
0.624V
0.612V
0.600V
0.588V
0.576V
REF
REF
V
V
- DC error
- AC noise
REF
REF
0.470V
0.380V
V
0.470V
0.380V
IL(DC)
IL(AC)
V
V
IL(DC)
V
IL(AC)
0.000V
V
SS
–0.350V
V
- 0.35V
SS
narrow pulse width
1. Numbers reflect typical values.
2. For CA[9:0], CK_t, CK_c, and CS_n VDD stands for VDD2. For DQ, DM, DQS_t, and DQS_c,
DD stands for VDDQ
3. For CA[9:0], CK_t, CK_c, and CS_n are VSS . For DQ, DM, DQS_t, and DQS_c, VSS stands for
VSSQ
Notes:
V
.
.
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110
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
Figure 71: LPDDR2-200 to LPDDR2-400 Input Signal
V
and V levels with ringback
IH
IL
V
+ 0.35V
1.550V
DD
narrow pulse width
1.200V
V
DD
Minimum V and V levels
IL
IH
V
IH(AC)
0.900V
0.800V
0.900V
0.800V
V
IH(AC)
V
IH(DC)
V
IH(DC)
V
V
+ AC noise
+ DC error
0.624V
0.612V
0.600V
0.588V
0.576V
0.624V
0.612V
0.600V
0.588V
0.576V
REF
REF
V
V
- DC error
- AC noise
REF
REF
0.400V
0.300V
V
0.400V
0.300V
IL(DC)
IL(AC)
V
V
IL(DC)
V
IL(AC)
0.000V
V
SS
V
- 0.35V
–0.350V
SS
narrow pulse width
1. Numbers reflect typical values.
2. For CA[9:0], CK_t, CK_c, and CS_n VDD stands for VDD2. For DQ, DM, DQS_t, and DQS_c,
DD stands for VDDQ
3. For CA[9:0], CK_t, CK_c, and CS_n are VSS. For DQ, DM, DQS_t, and DQS_c, VSS stands for
VSSQ
Notes:
V
.
.
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111
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC and DC Logic Input Measurement Levels for Differential
Signals
AC and DC Logic Input Measurement Levels for Differential Signals
Figure 72: Differential AC Swing Time and tDVAC
tDVAC
V
IH,diff(AC)min
V
IH,diff(DC)min
CK_t, CK_c
DQS_t, DQS_c
0.0
V
IL,diff(DC)max
tDVAC
1/2 cycle
V
IL,diff(AC)max
Time
Table 71: Differential AC and DC Input Levels
For CK_t and CK_c, VREF = VREFCA(DC); For DQS_t and DQS_c VREF = VREFDQ(DC)
LPDDR2-1066 to LPDDR2-466
LPDDR2-400 to LPDDR2-200
Symbol Parameter
Min
Max
Min
Max
Unit Notes
VIH,diff(AC) Differential input 2 × (VIH(AC) - VREF
HIGH AC
)
)
Note 1
2 × (VIH(AC) - VREF
)
Note 1
V
V
V
V
2
2
3
3
VIL,diff(AC) Differential input
LOW AC
Note 1
2 × (VIL(AC) - VREF
)
)
Note 1
2 × (VIH(DC) - VREF
Note 1
2 × (VIL(AC) - VREF
)
)
VIH,diff(DC) Differential input 2 × (VIH(DC) - VREF
HIGH
Note 1
)
Note 1
VIL,diff(DC) Differential input
LOW
Note 1
2 × (VIL(DC) - VREF
2 × (VIL(DC) - VREF
1. These values are not defined, however the single-ended signals CK_t, CK_c, DQS_t, and
DQS_c must be within the respective limits (VIH(DC)max, VIL(DC)min) for single-ended signals
and must comply with the specified limitations for overshoot and undershoot (see Over-
shoot and Undershoot Definitions).
Notes:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC and DC Logic Input Measurement Levels for Differential
Signals
2. For CK_t and CK_c, use VIH/VIL(AC) of CA and VREFCA; for DQS_t and DQS_c, use VIH/VIL(AC)
of DQ and VREFDQ. If a reduced AC HIGH or AC LOW is used for a signal group, the re-
duced voltage level also applies.
3. Used to define a differential signal slew rate. For CK_t - CK_c use VIH/VIL(dc) of CA and
VREFCA; for DQS_t - DQS_c, use VIH/VIL(dc) of DQs and VREFDQ; if a reduced dc-high or
dc-low level is used for a signal group,then the reduced level applies also here.
Table 72: CK_t/CK_c and DQS_t/DQS_c Time Requirements Before Ringback (tDVAC)
tDVAC (ps) at VIH/VILdiff(AC) = 440mV
tDVAC (ps) at VIH/VILdiff(AC) = 600mV
Slew Rate (V/ns)
Min
175
170
167
163
162
161
159
155
150
150
Min
75
57
50
38
34
29
22
13
0
> 4.0
4.0
3.0
2.0
1.8
1.6
1.4
1.2
1.0
< 1.0
0
Single-Ended Requirements for Differential Signals
Each individual component of a differential signal (CK_t, CK_c, DQS_t, and DQS_c)
must also comply with certain requirements for single-ended signals.
CK_t and CK_c must meet VSEH(AC)min/VSEL(AC)max in every half cycle. DQS_t, DQS_c
must meet VSEH(AC)min/VSEL(AC)max in every half cycle preceding and following a valid
transition.
The applicable AC levels for CA and DQ differ by speed bin.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC and DC Logic Input Measurement Levels for Differential
Signals
Figure 73: Single-Ended Requirements for Differential Signals
V
or V
DDQ
DD2
V
SEH(AC)
V
SEH(AC)min
V
/2 or V
/2
DDQ
DD2
CK or DQS
V
SEL(AC)max
or V
V
SEL(AC)
V
SS
SSQ
Time
While CA and DQ signal requirements are referenced to VREF, the single-ended compo-
nents of differential signals also have a requirement with respect to
VDDQ/2 for DQS, and VDD2/2 for CK.
The transition of single-ended signals through the AC levels is used to measure setup
time. For single-ended components of differential signals, the requirement to reach
VSEL(AC)max or VSEH(AC)min has no bearing on timing. This requirement does, however,
add a restriction on the common mode characteristics of these signals (see Single-
Ended AC and DC Input Levels for CA and CS_n Inputs for CK_t/CK_c single-ended re-
quirements, and Single-Ended AC and DC Input Levels for DQ and DM for DQ and
DQM single-ended requirements).
Table 73: Single-Ended Levels for CK_t, CK_c, DQS_t, DQS_c
LPDDR2-1066 to LPDDR2-466
LPDDR2-400 to LPDDR2-200
Symbol Parameter
Min
Max
Min
Max
Unit Notes
VSEH(AC) Single-ended HIGH
level for strobes
(VDDQ/2) + 0.220
Note 1
(VDDQ/2) + 0.300
Note 1
V
V
V
V
2, 3
2, 3
2, 3
2, 3
Single-ended HIGH
level for CK_t, CK_c
(VDD2/2) + 0.220
Note 1
Note 1
(VDD2/2) + 0.300
Note 1
Note 1
VSEL(AC) Single-ended LOW
level for strobes
(VDDQ/2) - 0.220
(VDD2/2) - 0.220
(VDDQ/2) + 0.300
(VDD2/2) + 0.300
Single-ended LOW
level for CK_t, CK_c
Note 1
Note 1
1. These values are not defined; however, the single-ended signals CK_t, CK_c, DQS0_t,
DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c must be within the respec-
tive limits (VIH(DC)max/ VIL(DC)min) for single-ended signals, and must comply with the
Notes:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC and DC Logic Input Measurement Levels for Differential
Signals
specified limitations for overshoot and undershoot (see Overshoot and Undershoot Defi-
nition).
2. For CK_t and CK_c, use VSEH/VSEL(AC) of CA; for strobes (DQS[3:0]_t and DQS[3:0]_c), use
VIH/VIL(AC) of DQ.
3. VIH(AC) and VIL(AC) for DQ are based on VREFDQ; VSEH(AC) and VSEL(AC) for CA are based on
V
REFCA. If a reduced AC HIGH or AC LOW is used for a signal group, the reduced level
applies.
Differential Input Crosspoint Voltage
To ensure tight setup and hold times as well as output skew parameters with respect to
clock and strobe, each crosspoint voltage of differential input signals (CK_t, CK_c,
DQS_t, and DQS_c) must meet the specifications listed in the Single-Ended Levels for
CK_t, CK_c, DQS_t, DQS_c table. The differential input crosspoint voltage (VIX) is meas-
ured from the actual crosspoint of the true signal and its and complement to the midle-
vel between VDD and VSS
.
Figure 74: VIX Definition
9
ꢏꢀ9
9
ꢏꢀ9
''ꢃ
''4
''ꢃ ''4
&.BFꢏꢀ'46BF
&.BFꢏꢀ'46BF
9
;
,;
9
,;
9
ꢐꢃꢏ
ꢐꢃ
9
ꢐꢃꢏ
ꢐꢃ
''ꢃ
''ꢃ
;
;
9
9
''4
''4
9
,;
9
,;
;
&.BWꢏꢀ'46BW
ꢏꢀ9
&.BWꢏꢀ'46BW
9
9
ꢏꢀ9
66
664
66 664
Table 74: Crosspoint Voltage for Differential Input Signals (CK_t, CK_c, DQS_t, DQS_c)
LPDDR2-1066 to LPDDR2-200
Symbol
Parameter
Min
Max
Unit
Notes
VIXCA(AC)
Differential input crosspoint voltage rela-
tive to VDD2/2 for CK_t and CK_c
–120
120
mV
1, 2
VIXDQ(AC)
Differential input crosspoint voltage rela-
tive to VDDQ/2 for DQS_t and DQS_c
–120
120
mV
1, 2
1. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device,
and it is expected to track variations in VDD. VIX(AC) indicates the voltage at which differ-
ential input signals must cross.
Notes:
2. For CK_t and CK_c, VREF = VREFCA(DC). For DQS_t and DQS_c, VREF = VREFDQ(DC)
.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Output Characteristics and Operating Conditions
Input Slew Rate
Table 75: Differential Input Slew Rate Definition
Measured1
From
VIL,diff,max
Description
To
Defined by
Differential input slew rate for rising
edge (CK_t/CK_c and DQS_t/DQS_c)
VIH,diff,min
[VIH,diff,min - VIL,diff,maxΔTRdiff
Differential input slew rate for falling
edge (CK_t/CK_c and DQS_t/DQS_c)
VIH,diff,min
VIL,diff,max
[VIH,diff,min - VIL,diff,maxΔTFdiff
1. The differential signals (CK_t/CK_c and DQS_t/DQS_c) must be linear between these
thresholds.
Note:
Figure 75: Differential Input Slew Rate Definition for CK_t, CK_c, DQS_t, and DQS_c
ΔTF ΔTR
diff
diff
V
IH,diff,min
0
V
IL,diff,max
Time
Output Characteristics and Operating Conditions
Table 76: Single-Ended AC and DC Output Levels
Symbol Parameter
Value
VREF + 0.12
VREF - 0.12
0.9 x VDDQ
0.1 x VDDQ
–5
Unit Notes
VOH(AC)
VOL(AC)
VOH(DC)
VOL(DC)
IOZ
AC output HIGH measurement level (for output slew rate)
AC output LOW measurement level (for output slew rate)
DC output HIGH measurement level (for I-V curve linearity)
DC output LOW measurement level (for I-V curve linearity)
V
V
V
V
1
2
Output leakage current (DQ, DM, DQS_t, DQS_c);
MIN
μA
μA
DQ, DQS_t, DQS_c are disabled; 0V ≤ VOUT ≤ VDDQ
MAX
+5
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Output Characteristics and Operating Conditions
Table 76: Single-Ended AC and DC Output Levels (Continued)
Symbol Parameter
Value
–15
Unit Notes
MMpupd Delta output impedance between pull-up and pull-
down for DQ/DM
MIN
%
%
MAX
+15
1. IOH = –0.1mA.
2. IOL = 0.1mA.
Notes:
Table 77: Differential AC and DC Output Levels
Symbol Parameter
Value
Unit
V
VOHdiff(AC) AC differential output HIGH measurement level (for output SR)
VOLdiff(AC) AC differential output LOW measurement level (for output SR)
+ 0.2 x VDDQ
- 0.2 x VDDQ
V
Single-Ended Output Slew Rate
With the reference load for timing measurements, the output slew rate for falling and
rising edges is defined and measured between VOL(AC) and VOH(AC) for single-ended
signals.
Table 78: Single-Ended Output Slew Rate Definition
Measured
From
VOL(AC)
VOH(AC)
Description
To
Defined by
Single-ended output slew rate for rising edge
Single-ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC) - VOL(AC)ΔTRSE
[VOH(AC) - VOL(AC)ΔTFSE
1. Output slew rate is verified by design and characterization and may not be subject to
production testing.
Note:
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Output Characteristics and Operating Conditions
Figure 76: Single-Ended Output Slew Rate Definition
ΔTFSE
ΔTRSE
VOH(AC)
VREF
VOL(AC)
Time
Table 79: Single-Ended Output Slew Rate
Notes 1–5 apply to all parameters conditions
Value
Parameter
Symbol
Min
1.5
Max
Unit
V/ns
V/ns
–
Single-ended output slew rate (output impedance = 40Ω
Single-ended output slew rate (output impedance = 60Ω
Output slew-rate-matching ratio (pull-up to pull-down)
SRQSE
SRQSE
3.5
2.5
1.4
1.0
0.7
1. Definitions: SR = slew rate; Q = output (similar to DQ = data-in, data-out); SE = single-
ended signals.
Notes:
2. Measured with output reference load.
3. The ratio of pull-up to pull-down slew rate is specified for the same temperature and
voltage over the entire temperature and voltage range. For a given output, the ratio
represents the maximum difference between pull-up and pull-down drivers due to proc-
ess variation.
4. The output slew rate for falling and rising edges is defined and measured between
V
OL(AC) and VOH(AC).
5. Slew rates are measured under typical simultaneous switching output (SSO) conditions,
with one-half of DQ signals per data byte driving HIGH and one-half of DQ signals per
data byte driving LOW.
Differential Output Slew Rate
With the reference load for timing measurements, the output slew rate for falling and
rising edges is defined and measured between VOL,diff(AC) and VOH,diff(AC) for differential
signals.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Output Characteristics and Operating Conditions
Table 80: Differential Output Slew Rate Definition
Measured
From
VOL,diff(AC)
VOH,diff(AC)
Description
To
Defined by
Differential output slew rate for rising edge
Differential output slew rate for falling edge
VOH,diff(AC)
VOL,diff(AC)
[VOH,diff(AC) - VOL,diff(AC)ΔTRdiff
[VOH,diff(AC) - VOL,diff(AC)ΔTFdiff
1. Output slew rate is verified by design and characterization and may not be subject to
production testing.
Note:
Figure 77: Differential Output Slew Rate Definition
∆TF
∆TR
diff
diff
V
OH,diff(AC)
OL,diff(AC)
0
V
Time
Table 81: Differential Output Slew Rate
Value
Parameter
Symbol
Min
3.0
Max
7.0
Unit
V/ns
V/ns
Differential output slew rate (output impedance = 40Ω
Differential output slew rate (output impedance = 60Ω
SRQdiff
SRQdiff
2.0
5.0
1. Definitions: SR = slew rate; Q = output (similar to DQ = data-in, data-out); SE = single-
ended signals.
Notes:
2. Measured with output reference load.
3. The output slew rate for falling and rising edges is defined and measured between
V
OL(AC) and VOH(AC).
4. Slew rates are measured under typical simultaneous switching output (SSO) conditions,
with one-half of DQ signals per data byte driving HIGH and one-half of DQ signals per
data byte driving LOW.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Output Characteristics and Operating Conditions
Table 82: AC Overshoot/Undershoot Specification
Applies for CA[9:0], CS_n, CKE, CK_t, CK_c, DQ, DQS_t, DQS_c, DM
Parameter
1066
933 800 667 533 466 400 333 266 200 Unit
Maximum peak amplitude provided for over-
shoot area
0.35
0.35 0.35 0.35 0.35 0.35 0.35 0.35 0.35 0.35
V
Maximum peak amplitude provided for under-
shoot area
0.35
0.35 0.35 0.35 0.35 0.35 0.35 0.35 0.35 0.35
V
1
Maximum area above VDD
0.15
0.15
0.17 0.20 0.24 0.30 0.35 0.40 0.48 0.60 0.80 V-ns
0.17 0.20 0.24 0.30 0.35 0.40 0.48 0.60 0.80 V-ns
2
Maximum area below VSS
1. VDD stands for VDD2 for CA[9:0], CK_t, CK_c, CS_n, and CKE. VDD stands for VDDQ for DQ,
DM, DQS_t, and DQS_c.
Notes:
2. VSS is for CA[9:0], CK_t, CK_c, CS_n, and CKE. VSS stands for VSSQ for DQ, DM, DQS_t, and
DQS_c.
Figure 78: Overshoot and Undershoot Definition
Maximum amplitude
Overshoot area
V
DD
Time (ns)
V
SS
Undershoot area
Maximum amplitude
1. VDD stands for VDD2 for CA[9:0], CK_t, CK_c, CS_n, and CKE. VDD stands for VDDQ for DQ,
DM, DQS_t, and DQS_c.
Notes:
2. VSS is for CA[9:0], CK_t, CK_c, CS_n, and CKE. VSS stands for VSSQ for DQ, DM, DQS_t, and
DQS_c.
HSUL_12 Driver Output Timing Reference Load
The timing reference loads are not intended as a precise representation of any particu-
lar system environment or a depiction of the actual load presented by a production test-
er. System designers should use IBIS or other simulation tools to correlate the timing
reference load to a system environment. Manufacturers correlate to their production
test conditions, generally with one or more coaxial transmission lines terminated at the
tester electronics.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Output Driver Impedance
Figure 79: HSUL_12 Driver Output Reference Load for Timing and Slew Rate
LPDDR2
V
0.5 × V
DDQ
REF
50Ω
Output
V
= 0.5 × V
TT DDQ
C
= 5pF
LOAD
1. All output timing parameter values (tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc.) are reported
with respect to this reference load. This reference load is also used to report slew rate.
Note:
Output Driver Impedance
Output driver impedance is selected by a mode register during initialization. To achieve
tighter tolerances, ZQ calibration is required. Output specifications refer to the default
output drive unless specifically stated otherwise. The output driver impedance RON is
defined by the value of the external reference resistor RZQ as follows:
VDDQ - VOUT
=
RONPU
ABS(IOUT
)
When RONPD is turned off.
VOUT
ABS(IOUT
RONPD
=
)
When RONPU is turned off.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Output Driver Impedance
Figure 80: Output Driver
Chip in Drive Mode
Output Driver
V
DDQ
To other
circuitry
I
PU
(RCV, etc.)
R
ONPU
DQ
I
OUT
R
I
ONPD
V
OUT
PD
V
SSQ
Output Driver Impedance Characteristics with ZQ Calibration
Output driver impedance is defined by the value of the external reference resistor RZQ
.
Typical RZQ is 240 ohms.
Table 83: Output Driver DC Electrical Characteristics with ZQ Calibration
Notes 1–4 apply to all parameters and conditions
RONnom
Resistor
RON34PD
RON34PU
RON40PD
RON40PU
RON48PD
RON48PU
RON60PD
RON60PU
RON80PD
RON80PU
RON120PD
RON120PU
MMPUPD
VOUT
Min
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
–15.00
Typ
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
Max
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
+15.00
Unit
RZQ/7
RZQ/7
RZQ/6
RZQ/6
RZQ/5
RZQ/5
RZQ/4
RZQ/4
RZQ/3
RZQ/3
RZQ/2
RZQ/2
%
Notes
Ω
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
Ω
Ω
Ω
Ω
Ω
(optional)
Mismatch between
5
pull-up and pull-down
1. Applies across entire operating temperature range after calibration.
Notes:
2. RZQ Ω
3. The tolerance limits are specified after calibration, with fixed voltage and temperature.
For behavior of the tolerance limits if temperature or voltage changes after calibration,
see Output Driver Temperature and Voltage Sensitivity.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Output Driver Impedance
4. Pull-down and pull-up output driver impedances should be calibrated at 0.5 x VDDQ
5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD
Measure RONPU and RONPD, both at 0.5 × VDDQ
.
:
:
RONPU
R
–
MMPUPD
=
ONPD × 100
RON,nom
For example, with MMPUPD (MAX) = 15% and RONPD = 0.85, RONPU must be less than 1.0.
Output Driver Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen.
Table 84: Output Driver Sensitivity Definition
Resistor
RONPD
VOUT
Min
Max
Unit
0.5 × VDDQ
85 – (dRONdT ΔT|) – (dRONdV ΔV|)
115 + (dRONdT ΔT|) + (dRONdV ΔV|)
%
RONPU
1. ΔT = T - T (at calibration). ΔV = V - V (at calibration).
Notes:
2. dRONdT and dRONdV are not subject to production testing; they are verified by design
and characterization.
Table 85: Output Driver Temperature and Voltage Sensitivity
Symbol
RONdT
Parameter
Min
0.00
0.00
Max
0.75
0.20
Unit
%/˚C
RON temperature sensitivity
RON voltage sensitivity
RONdV
%/mV
Output Impedance Characteristics Without ZQ Calibration
Output driver impedance is defined by design and characterization as the default set-
ting.
Table 86: Output Driver DC Electrical Characteristics Without ZQ Calibration
RONnom
Resistor
RON34PD
RON34PU
RON40PD
RON40PU
RON48PD
RON48PU
RON60PD
RON60PU
RON80PD
RON80PU
VOUT
Min
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
Typ
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
Max
1.30
1.30
1.30
1.30
1.30
1.30
1.30
1.30
1.30
1.30
Unit
RZQ/7
RZQ/7
RZQ/6
RZQ/6
RZQ/5
RZQ/5
RZQ/4
RZQ/4
RZQ/3
RZQ/3
Ω
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
0.5 × VDDQ
Ω
Ω
Ω
Ω
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Output Driver Impedance
Table 86: Output Driver DC Electrical Characteristics Without ZQ Calibration (Continued)
RONnom
Resistor
RON120PD
RON120PU
VOUT
Min
0.70
0.70
Typ
1.00
1.00
Max
1.30
1.30
Unit
RZQ/2
RZQ/2
Ω
(optional)
0.5 × VDDQ
0.5 × VDDQ
1. Applies across entire operating temperature range without calibration.
Notes:
2. RZQ Ω
Table 87: I-V Curves
RON Ω (RZQ
)
Pull-Down
Pull-Up
Current (mA) / RON (ohms)
Current (mA) / RON (ohms)
Default Value after
ZQRESET
Default Value after
ZQRESET
With Calibration
With Calibration
Voltage (V) Min (mA) Max (mA) Min (mA) Max (mA) Min (mA) Max (mA) Min (mA) Max (mA)
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
0.00
0.19
0.38
0.56
0.74
0.92
1.08
1.25
1.40
1.54
1.68
1.81
1.92
2.02
2.11
2.19
2.25
2.30
2.34
2.37
2.41
2.43
2.46
2.48
2.50
0.00
0.32
0.64
0.94
1.26
1.57
1.86
2.17
2.46
2.74
3.02
3.30
3.57
3.83
4.08
4.31
4.54
4.74
4.92
5.08
5.20
5.31
5.41
5.48
5.55
0.00
0.21
0.40
0.60
0.79
0.98
1.17
1.35
1.52
1.69
1.86
2.02
2.17
2.32
2.46
2.58
2.70
2.81
2.89
2.97
3.04
3.09
3.14
3.19
3.23
0.00
0.26
0.53
0.78
1.04
1.29
1.53
1.79
2.03
2.26
2.49
2.72
2.94
3.15
3.36
3.55
3.74
3.91
4.05
4.23
4.33
4.44
4.52
4.59
4.65
0.00
0.00
0.00
0.00
–0.19
–0.38
–0.56
–0.74
–0.92
–1.08
–1.25
–1.40
–1.54
–1.68
–1.81
–1.92
–2.02
–2.11
–2.19
–2.25
–2.30
–2.34
–2.37
–2.41
–2.43
–2.46
–2.48
–2.50
–0.32
–0.64
–0.94
–1.26
–1.57
–1.86
–2.17
–2.46
–2.74
–3.02
–3.30
–3.57
–3.83
–4.08
–4.31
–4.54
–4.74
–4.92
–5.08
–5.20
–5.31
–5.41
–5.48
–5.55
–0.21
–0.40
–0.60
–0.79
–0.98
–1.17
–1.35
–1.52
–1.69
–1.86
–2.02
–2.17
–2.32
–2.46
–2.58
–2.70
–2.81
–2.89
–2.97
–3.04
–3.09
–3.14
–3.19
–3.23
–0.26
–0.53
–0.78
–1.04
–1.29
–1.53
–1.79
–2.03
–2.26
–2.49
–2.72
–2.94
–3.15
–3.36
–3.55
–3.74
–3.91
–4.05
–4.23
–4.33
–4.44
–4.52
–4.59
–4.65
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Output Driver Impedance
Figure 81: Output Impedance = 240 Ohms, I-V Curves After ZQRESET
6
PD (MAX)
PD (MIN)
PU (MIN)
PU (MAX)
4
2
0
–2
–4
–6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
Voltage
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Clock Specification
Figure 82: Output Impedance = 240 Ohms, I-V Curves After Calibration
6
PD (MAX)
PD (MIN)
PU (MIN)
PU (MAX)
4
2
0
–2
–4
–6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
Voltage
Clock Specification
The specified clock jitter is a random jitter with Gaussian distribution. Input clocks vio-
lating minimum or maximum values may result in device malfunction.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Clock Specification
Table 88: Definitions and Calculations
Symbol
Description
Calculation
Notes
tCK(avg) and
nCK
The average clock period across any consecutive
200-cycle window. Each clock period is calculated CK(avg) =
from rising clock edge to rising clock edge.
N
t
t
CKj /N
Σ
j = 1
Where N = 200
Unit tCK(avg) represents the actual clock average
tCK(avg)of the input clock under operation. Unit
nCK represents one clock cycle of the input clock,
counting from actual clock edge to actual clock
edge.
tCK(avg)can change no more than 1% within a
100-clock-cycle window, provided that all jitter
and timing specifications are met.
tCK(abs)
tCH(avg)
The absolute clock period, as measured from one
rising clock edge to the next consecutive rising
clock edge.
1
N
The average HIGH pulse width, as calculated
across any 200 consecutive HIGH pulses.
t
t
t
CH(avg) =
CL(avg) =
Σ
CHj /(N × CK(avg))
j = 1
Where N = 200
tCL(avg)
The average LOW pulse width, as calculated
across any 200 consecutive LOW pulses.
N
t
t
t
Σ
CLj /(N × CK(avg))
j = 1
Where N = 200
t
tJIT(per)
The single-period jitter defined as the largest de-
viation of any signal tCK from tCK(avg).
1
t
t
JIT(per) = min/max of CKi – CK(avg)
Where i = 1 to 200
tJIT(per),act
tJIT(per),
allowed
The actual clock jitter for a given system.
The specified clock period jitter allowance.
tJIT(cc)
The absolute difference in clock periods between
two consecutive clock cycles. tJIT(cc) defines the
cycle-to-cycle jitter.
1
1
t
t
t
t
JIT(cc) = max of CKi + 1 – CKi
tERR(nper)
The cumulative error across n multiple consecu-
tive cycles from tCK(avg).
i + n – 1
t
t
ERR(nper) =
Σ
CKj – (n × CK(avg))
j = i
tERR(nper),act The actual cumulative error over n cycles for a
given system.
tERR(nper),
allowed
The specified cumulative error allowance over n
cycles.
tERR(nper),min The minimum tERR(nper).
2
2
t
t
t
ERR(nper),min = (1 + 0.68LN(n)) × JIT(per),min
tERR(nper),max The maximum tERR(nper).
t
ERR(nper),max = (1 + 0.68LN(n)) × JIT(per),max
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Clock Period Jitter
Table 88: Definitions and Calculations (Continued)
Symbol
Description
Calculation
Notes
tJIT(duty)
Defined with absolute and average specifications tJIT(duty),min =
for tCH and tCL, respectively.
MIN((tCH(abs),min – tCH(avg),min),
(tCL(abs),min – tCL(avg),min)) × tCK(avg)
tJIT(duty),max =
MAX((tCH(abs),max – tCH(avg),max),
(tCL(abs),max – tCL(avg),max)) × tCK(avg)
1. Not subject to production testing.
2. Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value.
Notes:
tCK(abs), tCH(abs), and tCL(abs)
These parameters are specified with their average values; however, the relationship be-
tween the average timing and the absolute instantaneous timing (defined in the follow-
ing table) is applicable at all times.
Table 89: tCK(abs), tCH(abs), and tCL(abs) Definitions
Parameter
Symbol
Minimum
Unit
ps1
Absolute clock period
tCK(abs) tCK(avg),min + tJIT(per),min
Absolute clock HIGH pulse width
Absolute clock LOW pulse width
tCH(abs) tCH(avg),min + tJIT(duty),min2/tCK(avg)min
tCL(abs) tCL(avg),min + tJIT(duty),min2/tCK(avg)min
tCK(avg)
tCK(avg)
1. tCK(avg),min is expressed in ps for this table.
2. tJIT(duty),min is a negative value.
Notes:
Clock Period Jitter
The LPDDR2 device can tolerate some clock period jitter without core timing parameter
derating. This section describes device timing requirements with clock period jitter
(tJIT(per)) in excess of the values found in the AC Timing section. Calculating cycle time
derating and clock cycle derating are also described.
Clock Period Jitter Effects on Core Timing Parameters
Core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) ex-
tend across multiple clock cycles. Clock period jitter impacts these parameters when
measured in numbers of clock cycles. Within the specification limits, the device is char-
acterized and verified to support tnPARAM = RU[tPARAM/tCK(avg)]. During device op-
eration where clock jitter is outside specification limits, the number of clocks or
tCK(avg), may need to be increased based on the values for each core timing parameter.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Clock Period Jitter
Cycle Time Derating for Core Timing Parameters
For a given number of clocks (tnPARAM), when tCK(avg) and tERR(tnPARAM),act exceed
tERR(tnPARAM),allowed, cycle time derating may be required for core timing parame-
ters.
t
t
t
t
t
PARAM + ERR( nPARAM),act – ERR( nPARAM),allowed
t
– CK(avg) , 0
CycleTimeDerating = max
t
nPARAM
Cycle time derating analysis should be conducted for each core timing parameter. The
amount of cycle time derating required is the maximum of the cycle time deratings de-
termined for each individual core timing parameter.
Clock Cycle Derating for Core Timing Parameters
For each core timing parameter and a given number of clocks (tnPARAM), clock cycle
derating should be specified with tJIT(per).
For a given number of clocks (tnPARAM), when tCK(avg) plus (tERR(tnPARAM),act) ex-
ceed the supported cumulative tERR(tnPARAM),allowed, derating is required. If the
equation below results in a positive value for a core timing parameter (tCORE), the re-
quired clock cycle derating will be that positive value (in clocks).
t
t
t
t
t
PARAM + ERR( nPARAM),act – ERR( nPARAM),allowed
t
ClockCycleDerating = RU
– nPARAM
t
CK(avg)
Cycle-time derating analysis should be conducted for each core timing parameter.
Clock Jitter Effects on Command/Address Timing Parameters
Command/address timing parameters (tIS, tIH, tISCKE, tIHCKE, tISb, tIHb, tISCKEb,
tIHCKEb) are measured from a command/address signal (CKE, CS_n, or CA[9:0]) transi-
tion edge to its respective clock signal (CK_t/CK_c) crossing. The specification values
are not affected by the tJIT(per) applied, because the setup and hold times are relative to
the clock signal crossing that latches the command/address. Regardless of clock jitter
values, these values must be met.
Clock Jitter Effects on READ Timing Parameters
tRPRE
When the device is operated with input clock jitter, tRPRE must be derated by the
tJIT(per),act,max of the input clock that exceeds tJIT(per),allowed,max. Output derat-
ings are relative to the input clock:
t
t
JIT(per),act,max – JIT(per),allowed,max
t
RPRE(min,derated) = 0.9 –
t
CK(avg)
For example, if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500ps,
tJIT(per),act,min = –172ps, and tJIT(per),act,max = +193ps, then tRPRE,min,derated =
0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500 =
0.8628 tCK(avg).
tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS)
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Clock Period Jitter
These parameters are measured from a specific clock edge to a data signal transition
(DMn or DQm, where: n = 0, 1, 2, or 3; and m = DQ[31:0]), and specified timings must be
met with respect to that clock edge. Therefore, they are not affected by tJIT(per).
tQSH, tQSL
These parameters are affected by duty cycle jitter, represented by tCH(abs)min and
tCL(abs)min. These parameters determine the absolute data valid window at the device
pin. The absolute minimum data valid window at the device pin = min [(tQSH(abs)min
× tCK(avg)min - tDQSQmax - tQHSmax), (tQSL(abs)min × tCK(avg)min - tDQSQmax -
tQHSmax)]. This minimum data valid window must be met at the target frequency re-
gardless of clock jitter.
tRPST
tRPST is affected by duty cycle jitter, represented by tCL(abs). Therefore, tRPST(abs)min
can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min.
Clock Jitter Effects on WRITE Timing Parameters
tDS, tDH
These parameters are measured from a data signal (DMn or DQm, where n = 0, 1, 2, 3;
and m = DQ[31:0]) transition edge to its respective data strobe signal (DQSn_t, DQSn_c:
n = 0,1,2,3) crossing. The specification values are not affected by the amount of tJIT(per)
applied, because the setup and hold times are relative to the clock signal crossing that
latches the command/address. Regardless of clock jitter values, these values must be
met.
tDSS, tDSH
These parameters are measured from a data strobe signal crossing (DQSx_t, DQSx_c) to
its clock signal crossing (CK_t/CK_c). The specification values are not affected by the
amount of tJIT(per)) applied, because the setup and hold times are relative to the clock
signal crossing that latches the command/address. Regardless of clock jitter values,
these values must be met.
tDQSS
tDQSS is measured from the clock signal crossing (CK_t/CK_c) to the first latching data
strobe signal crossing (DQSx_t, DQSx_c). When the device is operated with input clock
jitter, this parameter must be derated by the actual tJIT(per),act of the input clock in ex-
cess of tJIT(per),allowed.
t
t
JIT(per),act,min – JIT(per),allowed, min
t
DQSS(min,derated) = 0.75 -
DQSS(max,derated) = 1.25 –
t
CK(avg)
t
t
JIT(per),act,max – JIT(per),allowed, max
t
t
CK(avg)
For example, if the measured jitter into an LPDDR2-800 device has tCK(avg) = 2500ps,
tJIT(per),act,min = -172ps, and tJIT(per),act,max = +193ps, then:
tDQSS,(min,derated) = 0.75 - (tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) =
0.75 - (-172 + 100)/2500 = 0.7788 tCK(avg), and
tDQSS,(max,derated) = 1.25 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) =
1.25 - (193 - 100)/2500 = 1.2128 tCK(avg).
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Refresh Requirements Parameters
Refresh Requirements Parameters
Table 90: Refresh Requirement Parameters (Per Density)
Parameter
Symbol 64Mb 128Mb 256Mb 512Mb
1Gb
8
2Gb
8
4Gb
8
8Gb
8
Unit
Number of banks
Refresh window: TCASE ≤ 85˚
4
32
8
4
32
8
4
32
8
4
32
8
tREFW
tREFW
32
8
32
8
32
8
32
8
ms
ms
Refresh window:
85˚C < TCASE ≤ 105˚C
Required number of REFRESH
commands (MIN)
R
2048
2048
4096
4096
4096
8192
8192
8192
Average time be-
REFab
tREFI
15.6
15.6
7.8
7.8
7.8
3.9
3.9
3.9
μs
μs
tween REFRESH com-
mands (for reference
only) TCASE ≤ 85˚C
REFpb tREFIpb (REFpb not supported below 1Gb)
0.975
0.4875 0.4875 0.4875
Refresh cycle time
tRFCab
tRFCpb
tREFBW
90
90
90
90
130
60
130
60
130
60
210
90
ns
ns
μs
Per-bank REFRESH cycle time
na
Burst REFRESH window =
4 × 8 × tRFCab
2.88
2.88
2.88
2.88
4.16
4.16
4.16
6.72
AC Timing
Table 91: AC Timing
Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul-
tiples of tCK) as well as the timing specifications when values for both are indicated.
Data Rate
Min/ tCK
Parameter
Symbol
Max Min 1066 933 800 667 533 400 333 Unit Notes
Maximum frequency
Clock Timing
–
–
533
466 400 333 266 200 166 MHz
Average clock period
tCK(avg)
tCH(avg)
tCL(avg)
tCK(abs)
MIN
MAX
MIN
–
–
–
–
–
–
–
–
–
–
–
–
–
1.875 2.15 2.5
3
3.75
5
6
ns
100 100 100 100 100 100 100
0.45 0.45 0.45 0.45 0.45 0.45 0.45 tCK
Average HIGH pulse width
Average LOW pulse width
Absolute clock period
(avg)
MAX
MIN
0.55 0.55 0.55 0.55 0.55 0.55 0.55
0.45 0.45 0.45 0.45 0.45 0.45 0.45 tCK
(avg)
MAX
MIN
0.55 0.55 0.55 0.55 0.55 0.55 0.55
tCK(avg)min tJIT(per)min
0.43 0.43 0.43 0.43 0.43 0.43 0.43 tCK
ps
Absolute clock HIGH pulse width
(with allowed jitter)
tCH(abs),
allowed
MIN
(avg)
MAX
MIN
0.57 0.57 0.57 0.57 0.57 0.57 0.57
0.43 0.43 0.43 0.43 0.43 0.43 0.43 tCK
Absolute clock LOW pulse width
(with allowed jitter)
tCL(abs),
allowed
(avg)
MAX
MIN
0.57 0.57 0.57 0.57 0.57 0.57 0.57
Clock period jitter
(with supported jitter)
tJIT(per),
allowed
-90
90
-95 -100 -110 -120 -140 -150
95 100 110 120 140 150
ps
MAX
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC Timing
Table 91: AC Timing (Continued)
Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul-
tiples of tCK) as well as the timing specifications when values for both are indicated.
Data Rate
Min/ tCK
Parameter
Symbol
Max Min 1066 933 800 667 533 400 333 Unit Notes
Maximum clock jitter between
two consectuive clock cycles
(with allowed jitter)
tJIT(cc),
allowed
MAX
–
180
190 200 220 240 280 300
ps
ps
Duty cycle jitter
(with allowed jitter)
tJIT(duty),
allowed
MIN
–
–
MIN ((tCH(abs),min - tCH(avg),min),
(tCL(abs),min - tCL(avg),min)) × tCK(avg)
MAX ((tCH(abs),max - tCH(avg),max),
(tCL(abs),max - tCL(avg),max)) × tCK(avg)
MAX
Cumulative errors across 2 cycles
Cumulative errors across 3 cycles
Cumulative errors across 4 cycles
Cumulative errors across 5 cycles
Cumulative errors across 6 cycles
Cumulative errors across 7 cycles
Cumulative errors across 8 cycles
Cumulative errors across 9 cycles
tERR(2per), MIN
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-132 -140 -147 -162 -177 -206 -221
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
allowed
MAX
132
-157 -166 -175 -192 -210 -245 -262
157 166 175 192 210 245 262
-175 -185 -194 -214 -233 -272 -291
175 185 194 214 233 272 291
-188 -199 -209 -230 -251 -293 -314
188 199 209 230 251 293 314
-200 -211 -222 -244 -266 -311 -333
200 211 222 244 266 311 333
-209 -221 -232 -256 -279 -325 -348
209 221 232 256 279 325 348
-217 -229 -241 -266 -290 -338 -362
217 229 241 266 290 338 362
-224 -237 -249 -274 -299 -349 -374
224 237 249 274 299 349 374
-231 -244 -257 -282 -308 -359 -385
231 244 257 282 308 359 385
-237 -250 -263 -289 -316 -368 -395
237 250 263 289 316 368 395
-242 -256 -269 -296 -323 -377 -403
242 256 269 296 323 377 403
140 147 162 177 206 221
tERR(3per), MIN
allowed
MAX
tERR(4per), MIN
allowed
MAX
tERR(5per), MIN
allowed
MAX
tERR(6per), MIN
allowed
MAX
tERR(7per), MIN
allowed
MAX
tERR(8per), MIN
allowed
MAX
tERR(9per), MIN
allowed
MAX
Cumulative errors across 10 cycles tERR(10per), MIN
allowed
MAX
Cumulative errors across 11 cycles tERR(11per), MIN
allowed
MAX
Cumulative errors across 12 cycles tERR(12per), MIN
allowed
MAX
Cumulative errors across n = 13,
14, 15…, 49, 50 cycles
tERR(nper), MIN
allowed
tERR(nper),allowed,min = (1 + 0.68ln(n)) ×
tJIT(per),allowed,min
MAX
tERR(nper), allowed,max = (1 + 0.68ln(n)) ×
tJIT(per),allowed,max
ZQ Calibration Parameters
Initialization calibration time
Long calibration time
tZQINIT
tZQCL
tZQCS
MIN
MIN
MIN
–
6
6
1
1
1
1
1
1
1
μs
ns
ns
360
90
360 360 360 360 360 360
90 90 90 90 90 90
Short calibration time
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC Timing
Table 91: AC Timing (Continued)
Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul-
tiples of tCK) as well as the timing specifications when values for both are indicated.
Data Rate
Min/ tCK
Parameter
Symbol
Max Min 1066 933 800 667 533 400 333 Unit Notes
Calibration RESET time
READ Parameters3
tZQRESET
MIN
3
50
50
50
50
50
50
50
ns
DQS output access time from
CK_t/CK_c
tDQSCK
MIN
–
–
–
–
–
–
–
–
2500 2500 2500 2500 2500 2500 2500 ps
5500 5500 5500 5500 5500 5500 5500
MAX
DQSCK delta short
tDQSCKDS MAX
tDQSCKDM MAX
tDQSCKDL MAX
tDQSQ
tQHS
330
680
380 450 540 670 900 1080 ps
780 900 1050 1350 1800 1900 ps
4
5
6
DQSCK delta medium
DQSCK delta long
920 1050 1200 1400 1800 2400
–
ps
ps
ps
DQS-DQ skew
MAX
MAX
MIN
200
230
220 240 280 340 400 500
Data-hold skew factor
DQS output HIGH pulse width
260 280 340 400 480 600
tCH(abs) - 0.05
tQSH
tCK
(avg)
DQS output LOW pulse width
Data half period
tQSL
tQHP
tQH
MIN
MIN
MIN
MIN
MIN
–
–
–
–
–
tCL(abs) - 0.05
MIN (tQSH, tQSL)
tQHP - tQHS
tCK
(avg)
tCK
(avg)
DQ/DQS output hold time from
DQS
ps
READ preamble
tRPRE
tRPST
0.9
0.9
0.9
0.9
0.9
0.9
0.9
tCK
(avg)
tCK
7
8
READ postamble
tCL(abs) - 0.05
(avg)
DQS Low-Z from clock
DQ Low-Z from clock
DQS High-Z from clock
DQ High-Z from clock
WRITE Parameters3
tLZ(DQS)
tLZ(DQ)
tHZ(DQS)
tHZ(DQ)
MIN
MIN
–
–
–
–
tDQSCK (MIN) - 300
tDQSCK(MIN) - (1.4 × tQHS(MAX))
tDQSCK (MAX) - 100
ps
ps
ps
ps
MAX
MAX
tDQSCK(MAX) + (1.4 × tDQSQ(MAX))
DQ and DM input hold time (VREF
based)
tDH
tDS
MIN
MIN
MIN
MIN
MAX
MIN
–
–
–
–
–
–
210
210
235 270 350 430 480 600
235 270 350 430 480 600
ps
ps
DQ and DM input setup time (VREF
based)
DQ and DM input pulse width
tDIPW
tDQSS
0.35 0.35 0.35 0.35 0.35 0.35 0.35 tCK
(avg)
0.75 0.75 0.75 0.75 0.75 0.75 0.75 tCK
(avg)
1.25 1.25 1.25 1.25 1.25 1.25 1.25 tCK
(avg)
Write command to first DQS latch-
ing transition
DQS input high-level width
tDQSH
0.4
0.4
0.4
0.4
0.4
0.4
0.4
tCK
(avg)
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133
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC Timing
Table 91: AC Timing (Continued)
Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul-
tiples of tCK) as well as the timing specifications when values for both are indicated.
Data Rate
Min/ tCK
Parameter
Symbol
Max Min 1066 933 800 667 533 400 333 Unit Notes
DQS input low-level width
tDQSL
MIN
MIN
MIN
MIN
MIN
–
–
–
–
–
0.4
0.2
0.2
0.4
0.4
0.2
0.2
0.4
0.4
0.2
0.2
0.4
0.4
0.2
0.2
0.4
0.4
0.2
0.2
0.4
0.4
0.2
0.2
0.4
0.4
0.2
0.2
0.4
tCK
(avg)
tCK
(avg)
tCK
(avg)
tCK
(avg)
DQS falling edge to CK setup time
tDSS
tDSH
DQS falling edge hold time from
CK
Write postamble
tWPST
tWPRE
Write preamble
0.35 0.35 0.35 0.35 0.35 0.35 0.35 tCK
(avg)
CKE Input Parameters
CKE minimum pulse width (HIGH
and LOW pulse width)
tCKE
tISCKE
tIHCKE
MIN
MIN
MIN
3
–
–
3
3
3
3
3
3
3
tCK
(avg)
CKE input setup time
0.25 0.25 0.25 0.25 0.25 0.25 0.25 tCK
(avg)
0.25 0.25 0.25 0.25 0.25 0.25 0.25 tCK
(avg)
9
CKE input hold time
10
Command Address Input Parameters3
Address and control input setup
time ( Vref based )
tIS
MIN
MIN
MIN
–
–
–
220
220
250 290 370 460 600 740
250 290 370 460 600 740
ps
ps
11
11
Address and control input hold
time ( Vref based )
tIH
Address and control input pulse
width
tIPW
0.40 0.40 0.40 0.40 0.40 0.40 0.40 tCK
(avg)
Boot Parameters (10 MHz–55 MHz)12, 13, 14
Clock cycle time
tCKb
MAX
MIN
MIN
MIN
MIN
–
–
–
–
–
100
18
100 100 100 100 100 100
ns
18
2.5
2.5
18
2.5
2.5
18
2.5
2.5
18
2.5
2.5
18
2.5
2.5
18
2.5
2.5
CKE input setup time
CKE input hold time
tISCKEb
tIHCKEb
tISb
2.5
2.5
ns
ns
Address and control input setup
time
1150 1150 1150 1150 1150 1150 1150 ps
Address and control input hold
time
tIHb
MIN
–
1150 1150 1150 1150 1150 1150 1150 ps
DQS output data access time from
CK_t/CK_c
tDQSCKb
MIN
MAX
MAX
–
–
–
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
10.0 10.0 10.0 10.0 10.0 10.0 10.0
Data strobe edge to output data
edge tDQSQb - 1.2
tDQSQb
tQHSb
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
ns
ns
Data hold skew factor
MAX
–
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134
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC Timing
Table 91: AC Timing (Continued)
Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul-
tiples of tCK) as well as the timing specifications when values for both are indicated.
Data Rate
Min/ tCK
Parameter
Symbol
Max Min 1066 933 800 667 533 400 333 Unit Notes
Mode Register Parameters
MODE REGISTER WRITE
command period
tMRW
tMRR
MIN
MIN
5
2
5
2
5
2
5
2
5
2
5
2
5
2
5
2
tCK
(avg)
tCK
(avg)
MODE REGISTER READ
command period
Core Parameters15
READ latency
RL
WL
MIN
MIN
MIN
MIN
3
1
–
3
8
4
7
4
6
3
5
2
4
2
3
1
3
1
tCK
(avg)
tCK
(avg)
WRITE latency
ACTIVATE-to-ACTIVATE
command period
tRC
tRAS + tRPab (with all-bank precharge),
tRAS + tRPpb (with per-bank precharge)
ns
17
CKE minimum pulse width during
SELF REFRESH (low pulse width
during SELF REFRESH)
tCKESR
15
15
15
15
15
15
15
ns
SELF REFRESH exit to next valid
command delay
tXSR
tXP
MIN
MIN
MIN
MIN
2
2
2
2
tRFCab + 10
ns
ns
Exit power-down to next valid
command delay
7.5
2
7.5
2
7.5
2
7.5
2
7.5
2
7.5
2
7.5
2
CAS-to-CAS delay
tCCD
tRTP
tCK
(avg)
Internal READ to PRECHARGE
command delay
7.5
7.5
7.5
7.5
7.5
7.5
7.5
ns
RAS-to-CAS delay
tRCD
tRPpb
tRPab
MIN
MIN
MIN
3
3
3
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
ns
ns
ns
Row precharge time (single bank)
Row precharge time (all banks)
4-bank
Row precharge time (all banks)
Row active time
tRPab
8-bank
tRAS
MIN
3
21
21
21
21
21
21
21
ns
MIN
MAX
MIN
MIN
3
–
3
2
42
70
15
7.5
42
70
15
7.5
42
70
15
7.5
42
70
15
7.5
42
70
15
7.5
42
70
15
10
42
70
15
10
ns
μs
ns
ns
WRITE recovery time
tWR
tWTR
Internal WRITE-to-READ
command delay
Active bank a to active bank b
Four-bank activate window
Minimum deep power-down time
Temperature Derating16
tRRD
tFAW
tDPD
MIN
MIN
MIN
2
8
–
10
50
10
50
10
50
10
50
10
50
10
50
10
60
ns
ns
μs
500
500 500 500 500 500 500
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135
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC Timing
Table 91: AC Timing (Continued)
Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul-
tiples of tCK) as well as the timing specifications when values for both are indicated.
Data Rate
Min/ tCK
Parameter
Symbol
Max Min 1066 933 800 667 533 400 333 Unit Notes
tDQSCK derating
tDQSCK
(derated)
tRCD
(derated)
tRC
(derated)
tRAS
(derated)
MAX
MIN
MIN
MIN
MIN
MIN
–
–
–
–
–
–
5620 6000 6000 6000 6000 6000 6000 ps
Core timing temperature
derating
tRCD + 1.875
tRC + 1.875
tRAS + 1.875
tRP + 1.875
tRRD + 1.875
ns
ns
ns
ns
ns
tRP
(derated)
tRRD
(derated)
1. Frequency values are for reference only. Clock cycle time (tCK) is used to determine de-
vice capabilities.
Notes:
2. All AC timings assume an input slew rate of 1 V/ns.
3. READ, WRITE, and input setup and hold values are referenced to VREF
.
4. tDQSCKDS is the absolute value of the difference between any two tDQSCK measure-
ments (in a byte lane) within a contiguous sequence of bursts in a 160ns rolling window.
tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is
<10˚C/s. Values do not include clock jitter.
5. tDQSCKDM is the absolute value of the difference between any two tDQSCK measure-
ments (in a byte lane) within a 1.6μs rolling window. tDQSCKDM is not tested and is
guaranteed by design. Temperature drift in the system is <10˚C/s. Values do not include
clock jitter.
6. tDQSCKDL is the absolute value of the difference between any two tDQSCK measure-
ments (in a byte lane) within a 32ms rolling window. tDQSCKDL is not tested and is
guaranteed by design. Temperature drift in the system is <10˚C/s. Values do not include
clock jitter.
For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point
when the signal crosses the transition threshold (VTT). tHZ and tLZ transitions occur in
the same access time (with respect to clock) as valid data transitions. These parameters
are not referenced to a specific voltage level but to the time when the device output is
no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ)), or begins driving (for tRPRE,
tLZ(DQS), tLZ(DQ)). The figure below shows a method to calculate the point when the
device is no longer driving tHZ(DQS) and tHZ(DQ) or begins driving tLZ(DQS) and tLZ(DQ)
by measuring the signal at two different voltages. The actual voltage measurement
points are not critical as long as the calculation is consistent. The parameters tLZ(DQS),
tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters
tRPRE and tRPST are determined from the differential signal DQS_t/DQS_c.
Output Transition Timing
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
CA and CS_n Setup, Hold, and Derating
VOH
X
VOH - X mV
OH - 2x X mV
2x X
V
TT + 2x Y mV
V
t
t
V
TT + Y mV
LZ(DQS), LZ(DQ)
l
t
t
VTT
VTT
HZ(DQS), HZ(DQ)
Y
2x Y
VTT - Y mV
VTT - 2x Y mV
VOL + 2x X mV
OL + X mV
V
VOL
T1 T2
Start driving point = 2 × T1 - T2
T1 T2
End driving point = 2 × T1 - T2
7. Measured from the point when DQS_t/DQS_c begins driving the signal, to the point
when DQS_t/DQS_c begins driving the first rising strobe edge.
8. Measured from the last falling strobe edge of DQS_t/DQS_c to the point when DQS_t/
DQS_c finishes driving the signal.
9. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to
CK_t/CK_c crossing.
10. CKE input hold time is measured from CK_t/CK_n crossing to CKE reaching a HIGH/LOW
voltage level.
11. Input setup/hold time for signal (CA[9:0], CS_n).
12. To ensure device operation before the device is configured, a number of AC boot timing
parameters are defined in this table. The letter b is appended to the boot parameter
symbols (for example, tCK during boot is tCKb).
13. Mobile LPDDR2 devices set some mode register default values upon receiving a RESET
(MRW) command, as specified in Mode Register Definition.
14. The output skew parameters are measured with default output impedance settings
using the reference load.
15. The minimum tCK column applies only when tCK is greater than 6ns.
16. Timing derating applies for operation at 85˚C to 105˚C when the requirement to derate
is indicated by mode register 4 op-code (see the MR4 Device Temperature (MA[7:0] =
04h) table).
17. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
cesses to a particular row address may result in reduction of the product lifetime.
CA and CS_n Setup, Hold, and Derating
For all input signals (CA and CS_n), the total required setup time (tIS) and hold time
(tIH) are calculated by adding the data sheet tIS (base) and tIH (base) values to the ΔtIS
and ΔtIH derating values, respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS.
(See the series of tables following this section.)
The typical setup slew rate (tIS) for a rising signal is defined as the slew rate between the
last crossing of VREF(DC) and the first crossing of VIH(AC)min. The typical setup slew rate
for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and
the first crossing of VIL(AC)max. If the actual signal is consistently earlier than the typical
slew rate line between the shaded VREF(DC)-to-(AC) region, use the typical slew rate for
the derating value (see Figure 83 (page 141)). If the actual signal is later than the typical
slew rate line anywhere between the shaded VREF(DC)-to-AC region, the slew rate of a
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
CA and CS_n Setup, Hold, and Derating
tangent line to the actual signal from the AC level to the DC level is used for the derating
value (see Figure 85 (page 143)).
The hold (tIH) typical slew rate for a rising signal is defined as the slew rate between the
last crossing of VIL(DC)max and the first crossing of VREF(DC). The hold (tIH) typical slew
rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min
and the first crossing of VREF(DC). If the actual signal is consistently later than the typical
slew rate line between the shaded DC-to-VREF(DC) region, use the typical slew rate for
the derating value (see Figure 84 (page 142)). If the actual signal is earlier than the typi-
cal slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a
tangent line to the actual signal from the DC level to VREF(DC) level is used for the derat-
ing value (see Figure 86 (page 144)).
For a valid transition, the input signal must remain above or below VIH/VIL(AC) for a
specified time, tVAC (see Table 96 (page 139)).
For slow slew rates the total setup time could be a negative value; that is, a valid input
signal will not have reached VIH/VIL(AC) at the time of the rising clock transition. A valid
input signal is still required to complete the transition and reach VIH/VIL(AC)
.
For slew rates between the values listed in Table 94, the derating values are obtained us-
ing linear interpolation. Typically, slew rate values are not subject to production testing.
They are verified by design and characterization.
Table 92: CA and CS_n Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate)
Data Rate
Parameter
tIS (base)
tIH (base)
1066
0
933
30
800
667
150
240
533
240
330
466
300
390
Reference
70
VIH/VIL(AC) = VREF(DC) 220mV
VIH/VIL(DC) = VREF(DC) 130mV
90
120
160
1. AC/DC referenced for 1 V/ns CA and CS_n slew rate, and 2 V/ns differential CK_t/CK_c
Note:
slew rate.
Table 93: CA and CS_n Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate)
Data Rate
Parameter
tIS (base)
tIH (base)
400
300
400
333
440
540
266
600
700
200
850
950
Reference
VIH/VIL(AC) = VREF(DC) 300mV
VIH/VIL(DC) = VREF(DC) 200mV
1. AC/DC referenced for 1 V/ns CA and CS_n slew rate, and 2 V/ns differential CK_t/CK_c
Note:
slew rate.
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
CA and CS_n Setup, Hold, and Derating
Table 94: Derating Values for AC/DC-Based tIS/tIH (AC220)
ΔtIS, ΔtIH derating in ps
AC220 Threshold -> VIH(ac)=VREF(dc)+220mV, VIL(ac)=VREF(dc)-220mV
DC100 Threshold -> VIH(dc)=VREF(dc)+130mV, VIL(dc)=VREF(dc)-130mV
CK_t, CK_c Differential Slew Rate
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
4.0 V/ns
3.0 V/ns
1.2 V/ns
1.0 V/ns
CA, CS_n slew 2.0
110
74
0
65
43
0
110
73
0
65
43
0
110
73
0
65
43
0
rate V/ns
1.5
89
16
13
8
59
16
11
3
1.0
0.9
0.8
0.7
0.6
0.5
0.4
32
29
24
18
10
32
27
19
10
-3
-3
-5
-3
-5
45
40
34
26
4
43
35
26
13
-4
-8
-13
56
50
42
20
-7
55
46
33
16
2
2
-6
66
58
36
17
78
65
48
34
1. Shaded cells are not supported.
Note:
Table 95: Derating Values for AC/DC-Based tIS/tIH (AC300)
ΔtIS, ΔtIH derating in ps
AC300 Threshold -> VIH(ac)=VREF(dc)+300mV, VIL(ac)=VREF(dc)-300mV
DC200 Threshold -> VIH(dc)=VREF(dc)+200mV, VIL(dc)=VREF(dc)-200mV
CK_t, CK_c Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns
1.2 V/ns
1.0 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
CA, CS_n slew 2.0
150 100 150 100 150 100
rate V/ns
1.5
100
0
67
0
100
0
67
0
100
0
67
0
116
16
12
4
83
16
8
1.0
0.9
0.8
0.7
0.6
0.5
0.4
32
28
20
13
2
32
24
12
-2
-4
-8
-4
-8
44
36
29
18
40
28
14
-5
-12 -20
-4
52
45
34
4
48
34
-3
-18
61
50
20
66
47
20
-8
-21
15
-12 -32
-12
-35 -40 -11
1. Shaded cells are not supported.
Note:
Table 96: Required Time for Valid Transition – tVAC > VIH(AC) and < VIL(AC)
tVAC at 300mV (ps)
tVAC at 220mV (ps)
Slew Rate
(V/ns)
Min
Max
Min
Max
>2.0
75
–
175
–
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
CA and CS_n Setup, Hold, and Derating
Table 96: Required Time for Valid Transition – tVAC > VIH(AC) and < VIL(AC) (Continued)
tVAC at 300mV (ps)
tVAC at 220mV (ps)
Slew Rate
(V/ns)
Min
57
50
38
34
29
22
13
0
Max
Min
170
167
163
162
161
159
155
150
150
Max
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
<0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
09005aef85eb530a
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
CA and CS_n Setup, Hold, and Derating
Figure 83: Typical Slew Rate and tVAC – tIS for CA and CS_n Relative to Clock
CK_c
CK_t
t
t
t
t
IS
IH
IS
IH
V
DD2
V
V
t
IH(AC)min
VAC
V
to AC
REF
region
IH(DC)min
Typical
slew rate
V
REF(DC)
Typical
slew rate
V
V
IL(DC)max
V
to AC
REF
region
IL(AC)max
t
VAC
V
SS
TF
TR
V
- V
REF(DC)
V
- V
IL(AC)max
Setup slew rate
rising signal
Setup slew rate
falling signal
IH(AC)min
REF(DC)
=
=
TF
TR
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
CA and CS_n Setup, Hold, and Derating
Figure 84: Typical Slew Rate – tIH for CA and CS_n Relative to Clock
CK_c
CK_t
tIS
tIH
tIS
tIH
VDD2
VIH(AC)min
VIH(DC)min
DC to VREF
region
Typical slew rate
VREF(DC)
Typical slew rate
DC to VREF
region
VIL(DC)max
VIL(AC)max
VSS
TF
TR
VIH(DC)min- VREF(DC)
VREF(DC)- VIL(DC)max
Hold slew rate
falling signal
Hold slew rate
rising signal
=
=
TF
TR
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
CA and CS_n Setup, Hold, and Derating
Figure 85: Tangent Line – tIS for CA and CS_n Relative to Clock
CK_c
CK_t
tIS
tIH
tIS
tIH
VDD2
VIH(AC)min
tVAC
VREF to AC
region
Typical
line
VIH(DC)min
Tangent
line
VREF(DC)
Tangent
line
VIL(DC)max
Typical
line
VREF to AC
region
VIL(AC)max
TF
TR
VSS
tVAC
- V
tangent line [V
]
tangent line [V
- V
]
Setup slew rate
falling signal
Setup slew rate
rising signal
REF(DC)
IL(AC)]max
IH(AC)min
REF(DC)
=
=
TF
TR
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
CA and CS_n Setup, Hold, and Derating
Figure 86: Tangent Line – tIH for CA and CS_n Relative to Clock
CK_c
CK_t
t
t
t
t
IS
IH
IS
IH
V
DD2
V
V
IH(AC)min
Typical
line
IH(DC)min
DC to V
region
REF
Tangent
line
V
REF(DC)
Tangent
line
DC to V
Typical line
REF
region
V
V
IL(DC)max
IL(AC)max
V
SS
TR
TF
tangent line [V
- V
]
tangent line [V
- V
]
REF(DC)
IL(DC)max
Hold slew rate
falling signal
IH(DC)min
REF(DC)
Hold slew rate
rising signal
=
=
TR
TF
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Data Setup, Hold, and Slew Rate Derating
Data Setup, Hold, and Slew Rate Derating
For all input signals (DQ, DM) the total required setup time (tDS) and hold time (tDH)
are calculated by adding the data sheet tDS(base) and tDH(base) values (see the follow-
ing table) to the ΔtDS and ΔtDH derating values, respectively (see the following derating
tables). Example: tDS = tDS(base) + ΔtDS.
The typical tDS slew rate for a rising signal is defined as the slew rate between the last
crossing of VREF(DC) and the first crossing of VIH(AC)min. The typical tDS slew rate for a
falling signal is defined as the slew rate between the last crossing of VREF(DC) and the
first crossing of VIL(AC)max (see the Typical Slew Rate and tVAC – tDS for DQ Relative to
Strobe figure).
If the actual signal is consistently earlier than the typical slew rate line in the figure,
"Typical Slew Rate and tVAC – tIS for CA and CS_n Relative to Clock (CA and CS_n Setup,
Hold, and Derating), the area shaded gray between the VREF(DC) region and the AC re-
gion, use the typical slew rate for the derating value. If the actual signal is later than the
typical slew rate line anywhere between the shaded VREF(DC) region and the AC region,
the slew rate of a tangent line to the actual signal from the AC level to the DC level is
used for the derating value (see figure "Tangent Line – tIS for CA and CS_n Relative to
Clock" in CA and CS_n Setup, Hold, and Derating).
The typical tDH slew rate for a rising signal is defined as the slew rate between the last
crossing of VIL(DC)max and the first crossing of VREF(DC). The typical tDH slew rate for a
falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the
first crossing of VREF(DC) (see the Typical Slew Rate – DH for DQ Relative to Strobe fig-
ure).
If the actual signal is consistently later than the typical slew rate line between the
shaded DC-level-to-VREF(DC) region, the typical slew rate should be used for the derating
value. If the actual signal is earlier than the typical slew rate line anywhere between sha-
ded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual signal from the
DC level to the VREF(DC) level is used for the derating value (see the Tangent Line – tDH
for DQ with Respect to Strobe figure).
For a valid transition, the input signal must remain above or below VIH/VIL(AC) for the
t
specified time, tVAC (see the Required Time for Valid Transition – VAC > VIH(AC) or <
VIL(AC) table).
The total setup time for slow slew rates could be negative; that is, a valid input signal
may not have reached VIH/VIL(AC) at the time of the rising clock transition. A valid input
signal is still required to complete the transition and reach VIH/VIL(AC)
.
For slew rates between the values listed in the following tables, the derating values can
be obtained using linear interpolation. Typically, slew rate values are not subject to pro-
duction testing. They are verified by design and characterization.
Table 97: Data Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate)
Data Rate
Parameter
tDS (base)
1066
933
800
50
667
533
466
Reference
-10
15
130
210
230
VIH/VIL(AC) = VREF(DC) 220mV
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Data Setup, Hold, and Slew Rate Derating
Table 97: Data Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) (Continued)
Data Rate
Parameter
1066
933
800
667
533
466
Reference
tDH (base)
80
105
140
220
300
320
VIH/VIL(DC) = VREF(DC) 130mV
1. AC/DC referenced for 1 V/ns DQ, DM slew rate, and 2 V/ns differential DQS_t/DQS_c slew
rate.
Note:
Table 98: Data Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate)
Data Rate
Parameter
tDS (base)
tDH (base)
400
180
280
333
300
400
266
450
550
200
700
800
Reference
VIH/VIL(AC) = VREF(DC) 300mV
VIH/VIL(DC) = VREF(DC) 200mV
1. AC/DC referenced for 1 V/ns DQ, DM slew rate, and 2 V/ns differential DQS_t/DQS_c slew
Note:
rate.
Table 99: Derating Values for AC/DC-Based tDS/tDH (AC220)
ΔtDS, ΔtDH derating in ps
AC220 Threshold -> VIH(ac)=VREF(dc)+220mV, VIL(ac)=VREF(dc)-220mV
DC130 Threshold -> VIH(dc)=VREF(dc)+130mV, VIL(dc)=VREF(dc)-130mV
DQS_t, DQS_c Differential Slew Rate
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
4.0 V/ns
3.0 V/ns
1.2 V/ns
1.0 V/ns
DQ, DM 2.0
110
74
0
65
43
0
110
73
0
65
43
0
110
73
0
65
43
0
slew
1.5
89
16
13
8
59
16
11
3
rate
1.0
32
29
24
18
10
32
27
19
10
-3
V/ns
0.9
0.8
0.7
0.6
0.5
0.4
-3
-5
-3
-5
45
40
34
26
4
43
35
26
13
-4
-8
-13
56
50
42
20
-7
55
46
33
16
2
2
-6
66
58
36
17
78
65
48
34
1. Shaded cells are not supported.
Note:
09005aef85eb530a
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Data Setup, Hold, and Slew Rate Derating
Table 100: Derating Values for AC/DC-Based tDS/tDH (AC300)
ΔtDS, ΔtDH derating in ps
AC300 Threshold -> VIH(ac)=VREF(dc)+300mV, VIL(ac)=VREF(dc)-300mV
DC200 Threshold -> VIH(dc)=VREF(dc)+200mV, VIL(dc)=VREF(dc)-200mV
DQS_t, DQS_c Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns
1.2 V/ns
1.0 V/ns
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
DQ, DM 2.0
150 100 150 100 150 100
slew
rate V/ns
1.0
1.5
100
0
67
0
100
0
67
0
100
0
67
0
116
16
12
4
83
16
8
32
28
20
13
2
32
24
12
-2
0.9
0.8
0.7
0.6
0.5
0.4
-4
-8
-4
-8
44
36
29
18
-12
40
28
14
-5
-12
-20
-4
52
45
34
4
48
34
-3
-18
61
50
66
47
20
-8
-21
15
-32
-12
-40
20
-35
-11
1. Shaded cells are not supported.
Note:
Table 101: Required Time for Valid Transition – tVAC > VIH(AC) or < VIL(AC)
tVAC at 300mV (ps)
tVAC at 220mV (ps)
Slew Rate (V/ns)
Min
75
57
50
38
34
29
22
13
0
Max
Min
175
170
167
163
162
161
159
155
150
150
Max
>2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
<0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
09005aef85eb530a
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Data Setup, Hold, and Slew Rate Derating
Figure 87: Typical Slew Rate and tVAC – tDS for DQ Relative to Strobe
DQS_c
DQS_t
t
t
t
t
DS
DH
DS
DH
V
DDQ
V
V
IH(AC)min
t
VAC
V
to AC
REF
region
IH(DC)min
Typical
slew rate
V
REF(DC)
Typical
slew rate
V
V
IL(DC)max
V
to AC
REF
region
IL(AC)max
t
VAC
V
SSQ
TF
TR
Setup slew rate
V
- V
V
- V
Setup slew rate
falling signal
REF(DC)
IL(AC)max
IH(AC)min REF(DC)
=
=
rising signal
TR
TF
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Data Setup, Hold, and Slew Rate Derating
Figure 88: Typical Slew Rate – tDH for DQ Relative to Strobe
DQS_c
DQS_t
tDS
tDH
tDS
tDH
VDDQ
VIH(AC)min
VIH(DC)min
DC to VREF
region
Typical
slew rate
VREF(DC)
Typical
slew rate
DC to VREF
region
VIL(DC)max
VIL(AC)max
VSSQ
TR
TF
VIH(DC)min - VREF(DC)
V
REF(DC) - VIL(DC)max
Hold slew rate
falling signal
Hold slew rate
rising signal
=
=
TF
TR
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Data Setup, Hold, and Slew Rate Derating
Figure 89: Tangent Line – tDS for DQ with Respect to Strobe
DQS_c
DQS_t
t
t
t
t
DS
DH
DS
DH
V
DDQ
V
V
IH(AC)min
t
VAC
Typical
line
V
to AC
REF
region
IH(DC)min
Tangent line
V
REF(DC)
Tangent line
Typical line
V
V
IL(DC)max
IL(AC)max
V
to AC
REF
region
TR
TF
t
VAC
VSSQ
tangent line [V
- V
]
tangent line [V
- V
]
REF(DC)
Setup slew rate
falling signal
Setup slew rate
rising signal
REF(DC)
IL(AC)max
IH(AC)min
=
=
TF
TR
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Data Setup, Hold, and Slew Rate Derating
Figure 90: Tangent Line – tDH for DQ with Respect to Strobe
DQS_c
DQS_t
tDS
tDH
tDS
tDH
VDDQ
VIH(AC)min
Nominal
line
VIH(DC)min
DC to V
region
REF
Tangent
line
VREF(DC)
Tangent
line
DC to V
Typical line
REF
region
VIL(DC)max
VIL(AC)max
VSSQ
∆TR
∆TF
tangent line [VIH(DC)min - VREF(DC)
]
tangent line [VREF(DC) - VIL(DC)max]
Hold slew rate
falling signal
Hold slew rate
=
=
rising signal
TF
TR
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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Revision History
Revision History
Rev. F – 08/16
• Updated legal status to Production
• Removed "Embedded" from title
• Corrected Revision information in Options
Rev. E – 05/16
Rev. D – 03/16
• Updated IDD table
• Updated Ballout Diagrams for 216-Ball Dual-Channel FBGA – 2 x 4Gb Die and 4 x 4Gb
Die to match Ball Description table
Rev. C – 02/16
Rev. B – 01/15
Rev. A – 09/14
• Preliminary DDP release
• Added 220-ball ballout and a 14x14 package
• Initial release created from the 216b_2c0e_2channel Rev. A data sheet
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000
www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
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152
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