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USB4712-I/PNXVAA [MICROCHIP]

USB 2.0 Hi-Speed Retimer Hub Family with Auto-FlexConnect Capability;
USB4712-I/PNXVAA
型号： USB4712-I/PNXVAA
厂家： MICROCHIP    MICROCHIP
描述：

USB 2.0 Hi-Speed Retimer Hub Family with Auto-FlexConnect Capability
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USB4712  
USB 2.0 Hi-Speed Retimer Hub Family  
with Auto-FlexConnect Capability  
Highlights  
Product Features  
• Single-chip USB 2.0 Hi-Speed hub retimer  
• Auto-FlexConnect  
-
-
1 upstream port for USB Host / OTG connection  
1 downstream port with FlexConnect  
-
Downstream port able to swap with upstream port,  
allowing USB host swapping  
-
Triggering FlexConnect  
• USB Battery Charging, revision 1.2, support on  
downstream ports (DCP, CDP, SDP)  
• Battery charging support for China and Apple®  
profiles  
-
USB4712 and USB4712LS execute  
FlexConnect when new USB host is detected  
USB4712PF executes FlexConnect via a   
package pin or USB command  
-
• USB to SMBus, SPI, UART, and GPIO  
• MultiTRAK™  
-
Apple authentication chip support  
-
Dedicated Transaction Translator per port  
• Retimer provides increased noise immunity,  
reducing the risk of compliance failure and  
interoperability issues  
• PortSwap  
-
Configurable differential intra-pair signal swapping  
• PHYBoost  
• Enables longer distance between USB host and  
USB device  
-
Programmable USB transceiver drive strength for  
recovering signal integrity  
• VariSense™  
Target Applications  
-
Programmable USB receiver sensitivity  
• Media hubs  
• USB Link Power Management (LPM) support  
• Vendor Specific Messaging (VSM) support  
• Enhanced OEM configuration options available  
• 3.3 V supply voltage  
• Infotainment head units  
• Automotive breakout boxes  
• Point of sale  
• Host switch for diagnostic mode applications  
• Host switch for field firmware upgrades  
• AEC-Q100 compliance  
-
Microchip parts are tested to meet or exceed the  
requirements of the AEC-Q100 automotive qualifi-  
cation standards  
• Packaging  
-
40-pin VQFN (5 x 5 mm)  
• Environmental  
-
Grade 3 automotive temperature range  
(-40° to +85°C)  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 1  
USB4712  
TO OUR VALUED CUSTOMERS  
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip  
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and  
enhanced as new volumes and updates are introduced.  
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via  
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Most Current Data Sheet  
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http://www.microchip.com  
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.  
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).  
Errata  
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-  
rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the  
revision of silicon and revision of document to which it applies.  
To determine if an errata sheet exists for a particular device, please check with one of the following:  
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Microchip’s Worldwide Web site; http://www.microchip.com  
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are  
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Register on our web site at www.microchip.com to receive the most current information on all of our products.  
DS00002774G-page 2  
2018-2021 Microchip Technology Inc.  
USB4712  
Table of Contents  
1.0 Preface ............................................................................................................................................................................................ 4  
2.0 Introduction ..................................................................................................................................................................................... 7  
3.0 Pin Descriptions and Configuration ................................................................................................................................................. 8  
4.0 Device Connections ...................................................................................................................................................................... 14  
5.0 Modes of Operation ...................................................................................................................................................................... 16  
6.0 Device Configuration ..................................................................................................................................................................... 18  
7.0 Device Interfaces .......................................................................................................................................................................... 19  
8.0 Functional Descriptions ................................................................................................................................................................. 21  
9.0 Operational Characteristics ........................................................................................................................................................... 26  
10.0 Package Information ................................................................................................................................................................... 34  
Appendix A: Data sheet Revision History ........................................................................................................................................... 38  
The Microchip Web Site ...................................................................................................................................................................... 40  
Customer Change Notification Service ............................................................................................................................................... 40  
Customer Support ............................................................................................................................................................................... 40  
Product Identification System ............................................................................................................................................................. 41  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 3  
USB4712  
1.0  
1.1  
PREFACE  
General Terms  
TABLE 1-1:  
Term  
GENERAL TERMS  
Description  
ADC  
Analog-to-Digital Converter  
Byte  
8 bits  
CDC  
Communication Device Class  
End of Packet  
Endpoint  
EOP  
EP  
FIFO  
First In First Out buffer  
Full-Speed  
FS  
GPIO  
General Purpose I/O  
Hi-Speed  
HS  
Hub Feature Controller  
The Hub Feature Controller, sometimes called a Hub Controller for short is the internal  
processor used to enable the unique features of the USB Controller Hub. This is not to  
be confused with the USB Hub Controller that is used to communicate the hub status  
back to the Host during a USB session.  
I2C  
Inter-Integrated Circuit  
Low-Speed  
LS  
lsb  
Least Significant Bit  
Least Significant Byte  
Most Significant Bit  
Most Significant Byte  
Not Applicable  
LSB  
msb  
MSB  
N/A  
NC  
No Connect  
OTP  
PCB  
PHY  
PLL  
One Time Programmable  
Printed Circuit Board  
Physical Layer  
Phase Lock Loop  
RESERVED  
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must  
always be zero for write operations. Unless otherwise noted, values are not guaran-  
teed when reading reserved bits. Unless otherwise noted, do not read or write to  
reserved addresses.  
SDK  
Software Development Kit  
System Management Bus  
Universally Unique IDentifier  
16 bits  
SMBus  
UUID  
WORD  
DS00002774G-page 4  
2018-2021 Microchip Technology Inc.  
USB4712  
1.2  
Buffer Types  
TABLE 1-2:  
Buffer  
BUFFER TYPE DESCRIPTIONS  
Description  
I
Input.  
IS  
Input with Schmitt trigger.  
O4  
O12  
OD12  
PU  
Output buffer with 4mA sink and 4mA source.  
Output buffer with 12mA sink and 12mA source.  
Open-drain output with 12mA sink.  
Internal pull-up. Unless otherwise noted in the pin description, internal pull-ups are  
always enabled.  
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on  
internal resistors to drive signals external to the device. When connected to a load that  
must be pulled high, an external resistor must be added.  
PD  
Internal pull-down. Unless otherwise noted in the pin description, internal pull-downs  
are always enabled.  
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on  
internal resistors to drive signals external to the device. When connected to a load that  
must be pulled low, an external resistor must be added.  
ICLK  
OCLK  
I/O-U  
I-R  
Crystal oscillator input pin.  
Crystal oscillator output pin.  
Analog input/output defined in USB specification.  
RBIAS.  
A
Analog.  
P
Power pin.  
1.3  
Pin Reset States  
The pin reset state definitions are detailed in Table 1-3. Refer to Section 3.0, "Pin Descriptions and Configuration" for  
details on individual pin reset states.  
TABLE 1-3:  
PIN RESET STATE LEGEND  
Symbol  
Description  
A/P  
Z
Analog/Power Input  
Hardware disables output driver (high impedance)  
Hardware enables internal 15kΩ pull-down  
Hardware enables internal 67kΩ pull-down  
Hardware enables internal 67kΩ pull-up  
USB line  
PD-15k  
PD-67k  
PU-67k  
USB  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 5  
USB4712  
1.4  
Reference Documents  
1. Universal Serial Bus Revision 2.0 Specification, http://www.usb.org  
2. USB4712 Auto-FlexConnect Operation Application Note, http://www.microchip.com  
3. USB to GPIO Bridging with USB4712 Hub, http://www.microchip.com  
4. USB to I2C Bridging with USB4712 Hub, http://www.microchip.com  
5. Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org  
6. I2C-Bus Specification, Version 1.1, http://www.nxp.com/documents/user_manual/UM10204.pdf  
7. System Management Bus Specification, Version 1.0, http://smbus.org/specs  
DS00002774G-page 6  
2018-2021 Microchip Technology Inc.  
USB4712  
2.0  
2.1  
INTRODUCTION  
General Description  
The Microchip family of USB4712 USB 2.0 Hi-Speed hub retimers are single-chip devices targeted for automotive appli-  
cations. Primary functions of the devices include: single downstream USB port supporting USB 2.0 Low Speed/Full  
Speed/Hi-Speed, single USB 2.0 Hi-Speed upstream connection to a USB host / OTG port, battery charging support for  
BC1.2, Apple and China charging profiles, USB I/O bridging, and an on-chip microcontroller.  
The USB4712 family employs unique Auto-FlexConnect USB functionality, whereby the downstream port can be recon-  
figured to become an upstream port, allowing the host or master capability to be switched between ports. This port/host  
becomes the master of the new USB bus, while the other port can connect as USB device.  
Note:  
Auto-FlexConnect requires Battery Charging v1.2 to always be enabled to function. BC1.2 on USB4712PF  
may be optionally enabled or disabled without any negative effect.  
The USB4712 devices are available in an Automotive Grade 3 (-40°C to +85°C) temperature range. An internal block  
diagram of the USB4712 is shown in Figure 2-1.  
FIGURE 2-1:  
INTERNAL BLOCK DIAGRAM  
USB Host / OTG Port 0  
3.3V  
USB4712  
Flex USB 2.0  
FlexHub Controller  
Hub Feature  
Controller  
OTP  
25 MHz  
I2C/SPI/GPIO  
Flex  
Port 1  
I/O Multiplexer  
USB  
I/O  
The USB4712 family of devices offer different feature sets depending upon the system needs. Specifically, FlexConnect  
can be executed automatically via a package pin or USB command. In some cases, the chip is capable of being cas-  
caded. Additionally, the Hub Feature Controller, which can be used for bridging, can be enabled/on or disabled/off.  
Table 2-1 provides a summary of the feature differences between family members.  
TABLE 2-1:  
Part Number  
FAMILY FEATURE MATRIX  
Supports  
Target  
Head Unit  
Suspend  
State  
Hub Feature  
Controller  
Cascadeable Trigger FlexConnect  
Applications  
USB4712  
Passenger Port  
Automatic when new  
host detected  
On when not flexed  
(turns off when flexed)  
Yes  
Yes  
No  
No  
USB4712PF  
USB4712LS  
Passenger Port or  
Cable Extender  
Executed via package Always off  
pin or USB command  
Yes  
Yes  
Passenger Port or   
Cable Extender  
Automatic when new  
host detected  
On when not flexed  
(turns off when flexed)  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 7  
USB4712  
3.0  
PIN DESCRIPTIONS AND CONFIGURATION  
The pin assignments for the USB4712 family are detailed in Section 3.1, "USB4712 Pin Assignments". Pin descriptions  
are provided in Section 3.2, "Pin Descriptions".  
3.1  
USB4712 Pin Assignments  
The device pin diagram for the USB4712 can be seen in Figure 3-1. Table 3-1 provides a USB4712 pin assignments  
table. Pin descriptions are provided in Section 3.2, "Pin Descriptions".  
FIGURE 3-1:  
USB4712 PIN ASSIGNMENTS  
20  
19  
18  
17  
16  
15  
14  
13  
12  
SQI_D2  
31  
SMB1_DAT  
32  
33  
34  
35  
36  
37  
38  
39  
40  
VDDIO33  
SMB1_CLK  
VDDIO33  
SPI_CE_N/SQI_CE_N/CFG_NON_REM  
SPI_DI/SQI_D1/CFG_BC_EN  
SPI_DO/SQI_D0  
SPI_CLK/SQI_CLK  
VDDIO33  
USBH_DP0  
USBH_DM0  
VSS  
Microchip  
USB4712  
(Top View 40-VQFN)  
XTALO  
VDDCR12  
XTALI/CLK_IN  
VDDPLLREF33  
RBIAS  
Ground Pad  
(must be connected to VSS)  
PRT_CTL1/OCS1  
NC  
11  
*FLEX_CMD available by default on  
USB4712PF only  
Indicates pins on the bottom of the device.  
Note:  
Configuration straps are identified by an underlined symbol name. Signals that function as configuration  
straps must be augmented with an external resistor when connected to a load.  
DS00002774G-page 8  
2018-2021 Microchip Technology Inc.  
USB4712  
TABLE 3-1:  
Pin  
USB4712 PIN ASSIGNMENTS  
Pin Name  
Reset  
Pin  
Pin Name  
Reset  
1
2
NC  
FLEX_USB_DP1  
FLEX_USB_DM1  
VDDIO33  
PD-67k  
PD-15k  
PD-15k  
A/P  
A/P  
Z
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
SQI_D3  
SMB2_CLK  
SMB2_DAT  
GPIO6  
Z
Z
3
Z
4
Z
5
VDDIO33  
VDDIO33  
UART_RX  
UART_TX  
RESET_N  
VBUS_DET  
VDDIO33  
SMB1_DAT  
SMB1_CLK  
VDDIO33  
USBH_DP0  
USBH_DM0  
VSS  
A/P  
Z
6
FLEX_CMD/GPIO11  
VDDIO33  
7
A/P  
Z
Z
8
TEST1  
PD-67k  
Z
9
TEST2  
Z
10  
11  
12  
13  
14  
15  
16  
17  
18  
TEST3  
Z
A/P  
Z
NC  
PD-67k  
PD-67k  
A/P  
A/P  
Z
PRT_CTL1/OCS1  
VDDCR12  
Z
A/P  
USB  
USB  
A/P  
A/P  
A/P  
VDDIO33  
SPI_CLK/SQI_CLK  
SPI_DO/SQI_D0  
SPI_DI/SQI_D1/CFG_BC_EN  
PD-67k  
Z
XTALO  
SPI_CE_N/SQI_CE_N/  
CFG_NON_REM  
PU-67k  
XTALI/CLK_IN  
19  
20  
VDDIO33  
SQI_D2  
A/P  
Z
39  
40  
VDDPLLREF33  
RBIAS  
A/P  
A/P  
Exposed Pad (VSS) must be connected to ground.  
Note:  
FLEX_CMD function (pin 6) available by default on USB4712PF only.  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 9  
USB4712  
3.2  
Pin Descriptions  
TABLE 3-2:  
Name  
PIN DESCRIPTIONS  
Symbol  
Buffer  
Type  
Description  
USB Interface  
USB Upstream D+  
USB Upstream D-  
USBH_DP0  
USBH_DM0  
I/O-U  
I/O-U  
I/O-U  
Upstream USB 2.0 Data Plus (D+)  
Upstream USB 2.0 Data Minus (D-)  
Downstream USB 2.0 Port 1 Data Plus (D+)  
USB  
Downstream Port  
1 D+  
FLEX_USB_DP1  
USB  
Downstream Port  
1 D-  
FLEX_USB_DM1  
I/O-U  
Downstream USB 2.0 Port 1 Data Minus (D-)  
USB Port Control Pins  
USB Port 1 Power  
Enable  
PRT_CTL1  
OCS1  
I/O12  
Active high control signal to enable power to downstream  
port 1.  
USB Port 1 Over-  
current Sense  
I/O12  
Overcurrent sense for port 1.  
SPI Interface Pins  
SPI Clock  
SPI_CLK  
SPI_DO  
I/O4  
I/O4  
SPI clock.  
SPI Data Out  
SPI output data. If the SPI interface is enabled, this signal  
is the data out for the SPI port.  
SPI Data In  
SPI_DI  
I/O4  
SPI input data. If the SPI interface is enabled, this signal  
must have a weak pull-down applied at all times to pre-  
vent floating.  
Note:  
If SPI interface is not utilized, this pin cannot  
be left floating. It must be connected per the  
CFG_BC_EN pin description.  
SPI Chip  
Enable  
SPI_CE_EN  
I/O4  
Active low SPI chip enable input. If the SPI interface is  
enabled, this pin must be driven high in powerdown  
states.  
Note:  
If SPI interface is not utilized, this pin cannot  
be left floating. It must be connected per the  
CFG_NON_REM pin description.  
SQI Interface Pins  
SQI Clock  
SQI_CLK  
I/O4  
I/O4  
SQI clock.  
SQI Data 0-3  
SQI_D[0:3]  
SQI Data 0-3. If the SQI interface is enabled, these sig-  
nals function as Data 0 through 3.  
SQI Chip  
Enable  
SQI_CE_EN  
I/O4  
Active low SQI chip enable input. If the SQI interface is  
enabled, this pin requires an external pull-up resistor.  
Note:  
If SQI interface is not utilized, this pin cannot  
be left floating. It must be connected per the  
CFG_NON_REM pin description.  
SMBus Interface Pins  
I/OD12 SMBus 1 Master Clock  
SMBus 1 Clock  
SMB1_CLK  
Note:  
Not available on USB4712PF - HFC is dis-  
abled by default.  
DS00002774G-page 10  
2018-2021 Microchip Technology Inc.  
USB4712  
TABLE 3-2:  
Name  
PIN DESCRIPTIONS (CONTINUED)  
Buffer  
Symbol  
Type  
Description  
SMBus 1 Data  
SMB1_DAT  
SMB2_CLK  
SMB2_DAT  
I/OD12  
I/OD12  
I/OD12  
SMBus 1 Master Data  
Note:  
Not available on USB4712PF - HFC is dis-  
abled by default.  
SMBus 2 Clock  
SMBus 2 Data  
SMBus 2 SLAVE  
Note: Disabled on USB4712PF to prevent interfer-  
ence with FlexConnect operation.  
SMBus 2 SLAVE  
Note: Disabled on USB4712PF to prevent interfer-  
ence with FlexConnect operation.  
UART Interface Pins  
UART Transmit  
UART Receive  
UART_TX  
UART_RX  
O12  
UART Transmit  
Note:  
Not available on USB4712PF - HFC is dis-  
abled by default.  
I
UART Receive  
Note: Not available on USB4712PF - HFC is dis-  
abled by default.  
Miscellaneous  
I/O12 General purpose inputs/outputs 6, 11.  
Note: GPIOs not available on USB4712PF - HFC is  
disabled by default.  
General  
Purpose  
Input/Output  
6, 11  
GPIO6  
GPIO11  
VBUS  
Detection  
VBUS_DET  
I
This signal detects the state of the upstream bus power.  
When designing a detachable hub, this pin must be con-  
nected to the VBUS power pin of the upstream USB port  
through a resistor divider (50 kΩ by 100 kΩ) to provide  
3.3 V.  
For self-powered applications with a permanently  
attached host, this pin must be connected to either 3.3 V  
or 5.0 V through a resistor divider to provide 3.3 V. In  
embedded applications, VBUS_DET may be controlled  
(toggled) when the host desires to renegotiate a connec-  
tion without requiring a full reset of the device.  
Reset Input  
RESET_N  
RBIAS  
I
This active low signal is used by the system to reset the  
device. The active low pulse should be at least 1 s wide.  
Bias Resistor  
I-R  
A 12.0 k 1.0% resistor is attached from ground to this  
pin to set the transceiver’s internal bias settings. Place  
the resistor as close to the device as possible with a dedi-  
cated, low impedance connection to the GND plane.  
External 25 MHz  
Crystal Input  
XTALI  
ICLK  
ICLK  
External 25 MHz crystal input.  
External 25 MHz  
Reference Clock  
Input  
CLK_IN  
External reference clock input.  
The device may alternatively be driven by a single-ended  
clock oscillator. When this method is used, XTALO  
should be left unconnected.  
External 25 MHz  
Crystal Output  
XTALO  
OCLK  
External 25 MHz crystal output.  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 11  
USB4712  
TABLE 3-2:  
Name  
PIN DESCRIPTIONS (CONTINUED)  
Buffer  
Type  
Symbol  
Description  
Test 1  
TEST1  
A
Test 1 pin.  
This signal is used for test purposes and must always be  
pulled-up to resistor (4.7 kOhm recommended).  
Test 2  
Test 3  
TEST2  
TEST3  
A
Test 2 pin.  
This signal is used for test purposes and may be pulled  
up to 3.3V or pulled-down to ground via a resistor  
(4.7kOhm recommended).  
A
Test 3 pin.  
This signal is used for test purposes and may be pulled  
up to 3.3V or pulled-down to ground via a resistor  
(4.7kOhm recommended).  
No Connect  
NC  
-
I
No Connect.  
This pin should be left unconnected for proper operation.  
Flex Command  
FLEX_CMD  
Flex Command (USB4712PF Only)  
Controls state of FlexConnect.  
0 = Not Flexed (Port 0 is UFP)  
1 = Flexed (Port 1 is UFP)  
Configuration Straps  
Non-Removable  
Port  
Configuration  
Strap  
CFG_NON_REM  
CFG_BC_EN  
I
Non-Removable Ports Configuration Strap.  
This configuration strap controls selection of the non-  
removable port. See Note 3-1.  
Battery Charging  
Configuration  
Strap  
I
Battery Charging Configuration Strap.  
This configuration strap controls the BC 1.2 enabling on  
the downstream port. See Note 3-1.  
Power/Ground  
+3.3V I/O Power  
Supply Input  
VDDIO33  
P
+3.3V I/O power supply input.  
+3.3V Analog  
Power Supply  
Input  
VDDPLLREF33  
P
+3.3V master bias / PLL regulator supply input.  
+1.2V Core Power  
Supply Output  
VDDCR12  
P
P
+1.2V digital core power supply output.  
Note:  
This signal requires connection of a 1uF low-  
ESR capacitor to ground.  
Ground  
VSS  
Ground pins.  
Note 3-1  
Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N  
(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that  
function as configuration straps must be augmented with an external resistor when connected to a  
load. For additional information, refer to Section 3.3, "Configuration Straps and Programmable  
Functions".  
DS00002774G-page 12  
2018-2021 Microchip Technology Inc.  
USB4712  
3.3  
Configuration Straps and Programmable Functions  
Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset  
(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following de-  
assertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various  
device configuration straps and associated programmable pin functions.  
Note:  
The system designer must guarantee that configuration straps meet the timing requirements specified in  
Section 9.6.2, "Power-On and Configuration Strap Timing" and Section 9.6.3, "Reset and Configuration  
Strap Timing". If configuration straps are not at the correct voltage level prior to being latched, the device  
may capture incorrect strap values.  
3.3.1  
NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)  
The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of  
two settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The  
resistor options are a 200 kΩ pull-down and 200 kΩ pull-up as shown in Table 3-3.  
TABLE 3-3:  
CFG_NON_REM RESISTOR ENCODING  
CFG_NON_REM Resistor Value  
Setting  
200 kΩ Pull-Down  
200 kΩ Pull-Up  
Port 1 removable  
Port 1 non-removable  
3.3.2  
BATTERY CHARGING CONFIGURATION (CFG_BC_EN)  
The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of two  
settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor  
options are a 200 kΩ pull-down and 200 kΩ pull-up as shown in Table 3-4.  
TABLE 3-4:  
CFG_BC_EN RESISTOR ENCODING  
CFG_NON_REM Resistor Value  
Setting  
200 kΩ Pull-Down  
200 kΩ Pull-Up  
No battery charging  
Port 1 battery charging  
Note:  
The standard port does not support battery charging and OCS (Port 2). See Note 3-2.  
Note 3-2  
BC1.2 must be enabled for Auto-FlexConnect feature to operate. USB4712PF may optionally leave  
BC1.2 enabled or disabled with no negative effect to standard (non-Automatic) FlexConnect  
operation.  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 13  
USB4712  
4.0  
4.1  
DEVICE CONNECTIONS  
Power Connections  
Figure 4-1 illustrates the device power connections.  
FIGURE 4-1:  
POWER CONNECTIONS  
+3.3V  
Supply  
VDDIO33  
VDDCR12  
3.3V Internal Logic  
1.2V Internal Logic  
VDDPLLREF33  
1uF  
VSS  
USB4712  
4.2  
SPI Flash Connections  
Figure 4-2 illustrates the device SPI Flash connections.  
FIGURE 4-2:  
SPI FLASH CONNECTIONS  
+3.3V  
SPI_CE_N/SQI_CE_N  
CE#  
SPI_CLK/SQI_CLK  
SPI_DO/SQI_D0  
SPI_DI/SQI_D1  
CLK  
SIO0  
SIO1  
SQI_D2  
SQI_D3  
SIO2/WPn  
SIO3/HOLDn  
SPI Flash  
USB4712  
DS00002774G-page 14  
2018-2021 Microchip Technology Inc.  
USB4712  
4.3  
SMBus Connections  
Figure 4-3 illustrates the device SMBus Connections.  
FIGURE 4-3:  
SMBUS CONNECTIONS  
+3.3V  
10K  
SMBx_CLK  
Clock  
Data  
+3.3V  
10K  
SMBus  
USB4712  
SMBx_DAT  
4.4  
UART Connections  
Figure 4-4 illustrates the device UART connections.  
FIGURE 4-4:  
UART CONNECTIONS  
UART  
Transceiver  
UART  
Connector  
USB4712  
UART_TX  
UART_RX  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 15  
USB4712  
5.0  
MODES OF OPERATION  
The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the  
RESET_N pin, as shown in Table 5-1.  
TABLE 5-1:  
MODES OF OPERATION  
RESET_N Input  
0
Summary  
Standby Mode: This is the lowest power mode of the device. No functions are active other than  
monitoring the RESET_N input. All port interfaces are high impedance and the PLL is halted.  
Refer to Section 8.9, "Resets" for additional information on RESET_N.  
1
Hub (Normal) Mode: The device operates as a configurable USB hub. This mode has various  
sub-modes of operation, as detailed in Figure 5-1. Power consumption is based on the number  
of active ports, their speed, and amount of data received.  
The flowchart in Figure 5-1 details the modes of operation and details how the device traverses through the Hub Mode  
stages (shown in bold). The remaining sub-sections provide more detail on each stage of operation.  
FIGURE 5-1:  
HUB MODE FLOWCHART  
RESET_N deasserted  
(SPI_INIT)  
(CFG_ROM)  
In SPI Mode &  
Ext. SPI ROM  
present?  
NO  
Load Config from  
Internal ROM  
YES  
(CFG_STRAP)  
Modify Config  
Based on Config  
Straps  
Run From  
External SPI ROM  
YES  
Configuration 5?  
NO  
Perform SMBus/I2C  
Initialization  
YES  
SMBus2 Pull-ups?  
NO  
(SMBUS_CHECK)  
NO  
SOC Done?  
YES  
(CFG_SOC)  
Combine OTP  
Config Data  
(CFG_OTP)  
Hub Connect  
(USB_ATTACH)  
Normal Operation  
(NORMAL_MODE)  
DS00002774G-page 16  
2018-2021 Microchip Technology Inc.  
USB4712  
5.1  
Boot Sequence  
5.1.1  
STANDBY MODE  
If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maxi-  
mum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream  
ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no  
states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order  
to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode  
and must be re-initialized after RESET_N is negated high.  
5.1.2  
SPI INITIALIZATION STAGE (SPI_INIT)  
The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset,  
the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal  
firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid  
signature of “2DFU” (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the SPI  
Firmware/external SPI ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If  
a valid signature is not found, then execution continues from internal ROM (CFG_ROM stage).  
When using an external SPI ROM, a minimum of 2.2 Mbit is required, and 60 MHz or faster SPI ROM must be used.  
Both 1- and 2-bit SPI ROM are supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0  
and mode 3 SPI flashes are supported.  
If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_ROM stage).  
5.1.3  
CONFIGURATION FROM INTERNAL ROM STAGE (CFG_ROM)  
In this stage, the internal firmware loads the default values from the internal ROM. Most of the hub configuration regis-  
ters, USB descriptors, electrical settings, etc. will be initialized in this state even when running from SPI.  
5.1.4  
OTP CONFIGURATION STAGE (CFG_OTP)  
Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The  
default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is pro-  
grammed.  
5.1.5  
HUB CONNECT STAGE (USB_ATTACH)  
Once the hub registers are updated through default values, SMBus master, and OTP, the device firmware will enable  
attaching the USB host by setting the USB_ATTACH bit in the HUB_CMD_STAT register. The device will remain in the  
Hub Connect stage indefinitely until the VBUS function is deasserted/assertion of external RESET_N pin.  
5.1.6  
NORMAL MODE (NORMAL_MODE)  
Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB  
Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the USB  
Host.  
If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any of the designated  
hub stages. Asserting a soft disconnect on the upstream port will cause the hub to return to the Hub Connect stage until  
the soft disconnect is negated.  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 17  
USB4712  
6.0  
DEVICE CONFIGURATION  
The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly  
function when attached to a USB host controller. The hub can be configured either internally or externally depending on  
the implemented interface.  
Microchip provides a comprehensive software programming tool, MPLAB Connect (formerly ProTouch2), for OTP con-  
figuration of various USB4712 functions and registers. All configuration is to be performed via the MPLAB Connect Con-  
figurator programming tool. For additional information on this tool, refer to the MPLAB Connect Configurator  
programming tool product page at http://www.microchip.com/design-centers/usb/mplab-connect-configurator.  
Note:  
Device configuration straps and programmable pins are detailed in Section 3.3, "Configuration Straps and  
Programmable Functions," on page 13.  
Refer to Section 7.0, "Device Interfaces" for detailed information on each device interface.  
DS00002774G-page 18  
2018-2021 Microchip Technology Inc.  
USB4712  
7.0  
DEVICE INTERFACES  
The USB4712 provides multiple interfaces for configuration, external memory access, etc. This section details the var-  
ious device interfaces and their usage:  
• SPI/SQI Master Interface  
• SMBus/I2C Master/Slave Interfaces  
• UART Interface  
Note:  
For details on how to enable each interface, refer to Section 3.3, "Configuration Straps and Programmable  
Functions".  
For information on device connections, refer to Section 4.0, "Device Connections". For information on  
device configuration, refer to Section 6.0, "Device Configuration".  
Microchip provides a comprehensive software programming tool, MPLAB Connect (formerly ProTouch2),  
for configuring the USB4712 functions, registers and OTP memory. All configuration is to be performed via  
the MPLAB Connect Configurator programming tool. For additional information on this tool, refer to th  
MPLAB Connect Configurator programming tool product page at http://www.microchip.com/design-cen-  
ters/usb/mplab-connect-configurator.  
7.1  
SPI/SQI Master Interface  
The SPI/SQI controller has two basic modes of operation: execution of an external hub firmware image, or the USB to  
SPI bridge. On power up, the firmware looks for an external SPI flash device that contains a valid signature of 2DFU  
(device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the external ROM mode is  
enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found,  
then execution continues from internal ROM and the SPI interface can be used as a USB to SPI bridge.  
The second mode of operation is the USB to SPI bridge operation. Additional details on this feature can be found in  
Section 8.5, "USB to SPI Bridging" as well as the AN2430 - USB to SPI Bridging with USB4715 and USB49xx application  
note.  
Table 7-1 details how the associated pins are mapped in SPI vs. SQI mode  
TABLE 7-1:  
SPI/SQI PIN USAGE  
SPI Mode  
SQI Mode  
Description  
SPI_CE_N  
SPI_CLK  
SPI_DO  
SPI_DI  
-
SQI_CE_N  
SQI_CLK  
SQI_D0  
SPI/SQI Chip Enable (Active Low)  
SPI/SQI Clock  
SPI Data Out; SQI Data I/O 0  
SPI Data In; SQI Data I/O 1  
SQI Data I/O 2  
SQI_D1  
SQI_D2  
-
SQI_D3  
SQI Data I/O 3  
Note:  
For SPI timing information, refer to Section 9.6.7, "SPI/SQI Timing".  
7.2  
SMBus/I2C Master/Slave Interfaces  
The USB4712 provides two independent SMBus/I2C controllers SMBus 1 and SMBus 2, which can be used to access  
internal device run time registers or program the internal OTP memory. SMBus 1 is used as the USB to SMBus/I2C  
bridge, and SMBus 2 is used as the slave interface. The device contains two 128 byte buffers to enable simultaneous  
master/slave operation and to minimize firmware overhead in processed SMBus/I2C packets.  
Note:  
For SMBus/I2C timing information, refer to Section 9.6.5, "SMBus Timing" and Section 9.6.6, "I2C Timing".  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 19  
USB4712  
7.3  
UART Interface  
The device incorporates a configurable universal asynchronous receiver/transmitter (UART) that is functionally compat-  
ible with the NS 16550AF, 16450, 16450 ACE registers and the 16C550A. The UART performs serial-to-parallel con-  
version on received characters and parallel-to-serial conversion on transmit characters. Two sets of baud rates are  
provided: 24 Mhz and 16 MHz. When the 24 Mhz source clock is selected, standard baud rates from 50 to 115.2 K are  
available. When the source clock is 16 MHz, baud rates from 125 K to 1,000 K are available. The character options are  
programmable for the transmission of data in word lengths of from five to eight, 1 start bit; 1, 1.5 or 2 stop bits; even,  
odd, sticky or no parity; and prioritized interrupts. The UART contains a programmable baud rate generator that is capa-  
ble of dividing the input clock or crystal by a number from 1 to 65535. The UART is also capable of supporting the MIDI  
data rate.  
7.3.1  
TRANSMIT OPERATION  
Transmission is initiated by writing the data to be sent to the TX Holding Register or TX FIFO (if enabled). The data is  
then transferred to the TX Shift Register together with a start bit and parity and stop bits as determined by settings in  
the Line Control Register. The bits to be transmitted are then shifted out of the TX Shift Register in the order Start bit,  
Data bits (LSB first), Parity bit, Stop bit, using the output from the Baud Rate Generator (divided by 16) as the clock.  
If enabled, a TX Holding Register Empty interrupt will be generated when the TX Holding Register or the TX FIFO (if  
enabled) becomes empty.  
When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of data for  
transmission at a time. Transmission will continue until the TX FIFO is empty. The FIFO’s readiness to accept more data  
is indicated by interrupt.  
7.3.2  
RECEIVE OPERATION  
Data is sampled into the RX Shift Register using the Receive clock, divided by 16. The Receive clock is provided by the  
Baud Rate Generator. A filter is used to remove spurious inputs that last for less than two periods of the Receive clock.  
When the complete word has been clocked into the receiver, the data bits are transferred to the RX Buffer Register or  
to the RX FIFO (if enabled) to be read by the CPU. (The first bit of the data to be received is placed in bit 0 of this reg-  
ister.) The receiver also checks that the parity bit and stop bits are as specified by the Line Control Register.  
If enabled, an RX Data Received interrupt will be generated when the data has been transferred to the RX Buffer Reg-  
ister or, if FIFOs are enabled, when the RX Trigger Level has been reached. Interrupts can also be generated to signal  
RX FIFO Character Timeout, incorrect parity, a missing stop bit (frame error) or other Line Status errors.  
When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of received  
data at a time. Depending on the selected RX Trigger Level, interrupt will go active to indicate that data is available when  
the RX FIFO contains 1, 4, 8 or 14 bytes of data.  
DS00002774G-page 20  
2018-2021 Microchip Technology Inc.  
USB4712  
8.0  
FUNCTIONAL DESCRIPTIONS  
This section details various USB4712 functions, including:  
• Downstream Battery Charging  
• Auto-FlexConnect  
• USB to GPIO Bridging  
• USB to SMBus/I2C Bridging  
• USB to SPI Bridging  
• USB to UART Bridging  
• Link Power Management (LPM)  
• Port Power Control  
• Resets  
8.1  
Downstream Battery Charging  
The device can be configured by an OEM to have the downstream port support battery charging. The hub’s role in bat-  
tery charging is to provide acknowledgment to a device’s query as to whether the hub system supports USB battery  
charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the  
device. Those components must be provided externally by the OEM.  
FIGURE 8-1:  
BATTERY CHARGING EXTERNAL POWER SUPPLY  
DC Power  
Microchip  
Hub  
PRT_CTL1  
VBUS[n]  
If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can  
be configured to indicate the presence of such a supply from the device. This indication, via a handshake on the D+ and  
D- at the start of the connection with the device, is on a per port basis.  
For detailed information on utilizing the USB4712 battery charging feature, refer to the application note “USB Battery  
Charging with Microchip USB4712 Hub”, which can be found on the Microchip USB4712 product page at www.micro-  
chip.com/USB4712.  
8.2  
Auto-FlexConnect  
The USB4712 employs unique Auto-FlexConnect USB functionality, whereby the downstream port can be reconfigured  
to become an upstream port, allowing the host or master capability to be switched between ports. This port/host  
becomes the master of the new USB bus, while the other port can connect as USB device. The Auto-FlexConnect capa-  
bility enables the host/device swap to take place automatically. When the USB4712 detects a USB device disconnect,  
the Auto-FlexConnect feature attempts to detect a newly connected host on the downstream port. FlexConnect acti-  
vates if a new host on the downstream port is detected. If a new host is not detected, the hub remains in the default  
“unflexed” state.  
FlexConnect can also be manually enabled through any of the following three methods. (See Note 8-1.)  
• SMBus Control: An embedded SMBus master can manually control the state of the FlexConnect feature through  
basic write/read operations.  
• USB Command: FlexConnect can be manually initiated via a special USB command directed to the hub’s internal  
Hub Feature Controller device.  
• Direct Pin Control: Any available GPIO pin on the hub can be assigned the role of a manual FlexConnect control  
pin.  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 21  
USB4712  
Note 8-1  
The Auto-FlexConnect feature requires that USB Battery Charging (BC1.2) be enabled.  
For detailed information on utilizing the USB4712 FlexConnect feature, refer to the application note “USB4712 Auto-  
FlexConnect Operation”.  
8.3  
USB to GPIO Bridging  
The USB to GPIO bridging feature of the USB4712 provides system designers expanded system control and potential  
BOM reduction. General Purpose Input/Outputs (GPIOs) may be used for any general 3.3V level digital control and input  
functions.  
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-  
form the following functions:  
• Set the direction of the GPIO (input or output)  
• Enable a pull-up resistor  
• Enable a pull-down resistor  
• Read the state  
• Set the state  
For detailed information on utilizing the USB4712 USB to GPIO bridging feature, refer to the application note “USB to  
GPIO Bridging with Microchip USB4712 Hub”.  
8.4  
USB to SMBus/I2C Bridging  
The USB to SMBus/I2C bridging feature of the USB4712 provides system designers expanded system control and  
potential BOM reduction. The use of a separate USB to SMBus/I2C device is no longer required and a downstream USB  
port is not lost, as occurs when a standalone USB to SMBus/I2C device is implemented.  
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-  
form the following functions:  
• Configure SMBus/I2C Pass-Through Interface  
• SMBus/I2C Write  
• SMBus/I2C Read  
For detailed information on utilizing the USB4712 USB to SMBus/I2C bridging feature, refer to the application note  
“AN2438 - USB to I2C Bridging with Microchip USB4712 Hub”.  
8.5  
USB to SPI Bridging  
The USB to SPI bridging feature of the USB4712 provides system designers expanded system control and potential  
BOM reduction. The use of a separate USB to SPI device is no longer required and a downstream USB port is not lost,  
as occurs when a standalone USB to SPI device is implemented.  
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-  
form the following functions:  
• Enable SPI Pass-Through Interface  
• SPI Write/Read  
• Disable SPI Pass-Through Interface  
For detailed information on utilizing the USB4712 USB to SPI bridging feature, refer to the application note “USB to SPI  
Bridging with Microchip USB4712 Hub”.  
DS00002774G-page 22  
2018-2021 Microchip Technology Inc.  
USB4712  
8.6  
USB to UART Bridging  
The USB to UART bridging feature of the USB4712 provides system designers with expanded system control and  
potential BOM reduction. When using Microchip’s USB hubs, a separate USB to UART device is no longer required and  
a downstream USB port is not lost, as occurs when a standalone USB to UART device is implemented.  
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-  
form the following functions:  
• Enable/Disable UART Interface  
• Set UART Interface Baud Rate  
• UART Write  
• UART Read  
For detailed information on utilizing the USB4712 USB to UART bridging feature, refer to the application note “USB to  
UART Bridging with Microchip USB4712 Hub”.  
8.7  
Link Power Management (LPM)  
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM  
states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB  
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1.  
TABLE 8-1:  
State  
LPM STATE DEFINITIONS  
Description  
Entry/Exit Time to L0  
L2  
Suspend  
Entry: ~3 ms  
Exit: ~2 ms (from start of RESUME)  
L1  
L0  
Sleep  
Entry: <10 us  
Exit: <50 us  
Fully Enabled (On)  
-
8.8  
Port Power Control  
Port power and over-current sense share the same pin (PRT_CTL1/OCS1) for each port. These functions can be con-  
trolled directly from the USB hub, or via the processor.  
8.8.1  
PORT CONNECTION IN COMBINED MODE  
Port Power Control using USB Power Switch  
8.8.1.1  
When operating in combined mode, the device will have one port power control and over-current sense pin for each  
downstream port. When disabling port power, the driver will actively drive a '0'. To avoid unnecessary power dissipation,  
the pull-up resistor will be disabled at that time. When port power is enabled, it will disable the output driver and enable  
the pull-up resistor, making it an open drain output. If there is an over-current situation, the USB Power Switch will assert  
the open drain OCS signal. The Schmidt trigger input will recognize that as a low. The open drain output does not inter-  
fere. The over-current sense filter handles the transient conditions such as low voltage while the device is powering up.  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 23  
USB4712  
FIGURE 8-2:  
PORT POWER CONTROL WITH USB POWER SWITCH  
Pull‐Up Enable  
50k  
5V  
PRT_CTL1  
OCS  
USB Power  
Switch  
EN  
PRTPWR  
USB  
Device  
FILTER  
OCS  
8.8.1.2  
Port Power Control using Poly Fuse  
When using the device with a poly fuse, there is no need for an output power control. To maintain consistency, the same  
circuit will be used. A single port power control and over-current sense for each downstream port is still used from the  
Hub's perspective. When disabling port power, the driver will actively drive a '0'. This will have no effect as the external  
diode will isolate pin from the load. When port power is enabled, it will disable the output driver and enable the pull-up  
resistor. This means that the pull-up resistor is providing 3.3 volts to the anode of the diode. If there is an over-current  
situation, the poly fuse will open. This will cause the cathode of the diode to go to 0 volts. The anode of the diode will  
be at 0.7 volts, and the Schmidt trigger input will register this as a low resulting in an over-current detection. The open  
drain output does not interfere.  
FIGURE 8-3:  
PORT POWER CONTROL USING A POLY FUSE  
5V  
Pull-Up Enable  
Poly Fuse  
50k  
PRT_CTL1  
USB  
Device  
PRTPWR  
FILTER  
OCS  
DS00002774G-page 24  
2018-2021 Microchip Technology Inc.  
USB4712  
8.9  
Resets  
The device includes the following chip-level reset sources:  
• Power-On Reset (POR)  
• External Chip Reset (RESET_N)  
• USB Bus Reset  
8.9.1  
POWER-ON RESET (POR)  
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the  
device. A timer within the device will assert the internal reset per the specifications listed in Section 9.6.2, "Power-On  
and Configuration Strap Timing," on page 29.  
8.9.2  
EXTERNAL CHIP RESET (RESET_N)  
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the  
specifications in Section 9.6.3, "Reset and Configuration Strap Timing," on page 30. While reset is asserted, the device  
(and its associated external circuitry) enters Standby Mode and consumes minimal current.  
Assertion of RESET_N causes the following:  
1. The PHY is disabled and the differential pairs will be in a high-impedance state.  
2. All transactions immediately terminate; no states are saved.  
3. All internal registers return to the default state.  
4. The external crystal oscillator is halted.  
5. The PLL is halted.  
Note:  
All power supplies must have reached the operating levels mandated in Section 9.2, "Operating Condi-  
tions**," on page 26, prior to (or coincident with) the assertion of RESET_N.  
8.9.3  
USB BUS RESET  
In response to the upstream port signaling a reset to the device, the device performs the following:  
1. Sets default address to 0.  
2. Sets configuration to Unconfigured.  
3. Moves device from suspended to active (if suspended).  
4. Complies with the USB Specification for behavior after completion of a reset sequence.  
The host then configures the device in accordance with the USB Specification.  
Note:  
The device does not propagate the upstream USB reset to downstream devices.  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 25  
USB4712  
9.0  
9.1  
OPERATIONAL CHARACTERISTICS  
Absolute Maximum Ratings*  
+3.3 V Supply Voltage (VDDIO33, VDDPLLREF33) (Note 9-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +4.6 V  
Positive voltage on input signal pins, with respect to ground (Note 9-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.6 V  
Negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V  
Positive voltage on XTALI/CLK_IN, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.1 V  
Positive voltage on USB DP/DM signal pins, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0 V  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +150oC  
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125oC  
Lead Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020  
HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 kV  
Note 9-1  
When powering this device from laboratory or system power supplies, it is important that the absolute  
maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage  
spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the  
AC power line may appear on the DC output. If this possibility exists, it is suggested to use a clamp  
circuit.  
Note 9-2  
This rating does not apply to the following pins: All USB DM/DP pins, XTAL1/CLK_IN, and XTALO  
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating  
only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional  
operation of the device at any condition exceeding those indicated in Section 9.2, "Operating Conditions**", Section 9.5,  
"DC Specifications", or any other applicable section of this specification is not implied.  
9.2  
Operating Conditions**  
+3.3 V Supply Voltage (VDDIO33, VDDPLLREF33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V  
Input Signal Pins Voltage (Note 9-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +3.6 V  
XTALI/CLK_IN Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +1.5 V  
USB 2.0 DP/DM Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +5.5 V  
Ambient Operating Temperature in Still Air (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC  
+3.3 V Supply Voltage Rise Time (TRT in Figure 9-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ms  
**Proper operation of the device is guaranteed only within the ranges specified in this section.  
Note:  
Do not drive input signals without power supplied to the device.  
FIGURE 9-1:  
POWER SUPPLY RISE TIME MODEL  
Voltage  
TRT  
3.3 V  
VDDIO33/  
VDDPLLREF33  
100%  
90%  
10%  
VSS  
t90%  
Time  
t10%  
DS00002774G-page 26  
2018-2021 Microchip Technology Inc.  
USB4712  
Note:  
The rise time for the 3.3V supply can be extended to 100ms max if RESET_N is actively driven low, typi-  
cally by another IC, until 1 μs after all supplies are within operating range.  
9.3  
Package Thermal Specifications  
TABLE 9-1:  
PACKAGE THERMAL PARAMETERS  
Symbol  
°C/W  
Velocity (Meters/s)  
35  
31  
0
1
0
0
0
JA  
JB  
JT  
JC  
19  
0.3  
2.4  
Note:  
Thermal parameters are measured or estimated for devices in a multi-layer 2S2P PCB per JESDN51.  
9.4  
Power Consumption  
This section details the power consumption of the device as measured during various modes of operation. Power dis-  
sipation is determined by temperature, supply voltage, and external source/sink requirements.  
TABLE 9-2:  
DEVICE POWER CONSUMPTION  
Description  
Typical Current  
(mA)  
Maximum  
Current (mA)  
Reset Current (mA)  
0.40  
3.60  
Suspend Current (mA)  
0.40  
3.60  
Idle  
56  
57  
73  
67  
58  
74  
Active Operation (1 Full-Speed Device)  
Active Operation (1 Hi-Speed Device)  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 27  
USB4712  
9.5  
DC Specifications  
TABLE 9-3:  
I/O DC ELECTRICAL CHARACTERISTICS  
Parameter  
Symbol  
Min  
Typical  
Max  
Units  
Notes  
I Type Input Buffer  
Low Input Level  
VIL  
VIH  
-0.3  
0.9V  
V
V
High Input Level  
1.25  
VDDIO33+0.3  
IS Type Input Buffer  
Low Input Level  
VIL  
VIH  
-0.3  
1.25  
100  
0.9V  
VDDIO33+0.3  
240  
V
V
High Input Level  
Schmitt Trigger Hysteresis  
VHYS  
160  
mV  
(VIHT - VILT  
)
O4 Type Output Buffer  
Low Output Level  
VOL  
VOH  
0.4  
0.4  
0.4  
V
V
IOL = 4 mA  
IOH = -4 mA  
High Output Level  
VDD33-0.4  
VDD33-0.4  
O12 Type Output Buffer  
Low Output Level  
VOL  
VOH  
V
V
IOL = 12 mA  
IOH = -12 mA  
High Output Level  
OD12 Type Output Buffer  
Low Output Level  
VOL  
V
IOL = 12 mA  
Note 9-3  
ICLK Type Input Buffer  
(XTALI/CLK_IN Input)  
Low Input Level  
High Input Level  
Input Capacitance  
VIL  
VIH  
CIN  
-0.2  
0.9  
0.35  
1.2  
2
V
V
pF  
I/O-U Type Buffer  
Note 9-4  
(See Note 9-4)  
Note 9-3  
Note 9-4  
XTALI can optionally be driven from a 25 MHz singled-ended clock oscillator.  
Refer to the Universal Serial Bus Revision 2.0 Specification for USB DC electrical characteristics.  
DS00002774G-page 28  
2018-2021 Microchip Technology Inc.  
USB4712  
9.6  
AC Specifications  
This section details the various AC timing specifications of the device.  
9.6.1 POWER SUPPLY AND RESET_N SEQUENCE TIMING  
Figure 9-2 illustrates the recommended power supply sequencing and timing for the device. RESET_N and/or VBUS_-  
DET should rise after or at the same rate as VDDIO33/VDDPLLREF33. VBUS_DET and RESET_N do not have any  
other timing dependencies.  
FIGURE 9-2:  
POWER SUPPLY AND RESET_N SEQUENCE TIMING  
VDDIO33/  
VDDPLLREF33  
treset  
RESET_N/  
VBUS_DET  
TABLE 9-4:  
Symbol  
treset  
POWER SUPPLY AND RESET_N SEQUENCE TIMING  
Description  
Min  
Typ  
Max  
Units  
VDDIO33/VDDPLLREF33 to RESET_N/VBUS_DET rise time  
0
ms  
9.6.2  
POWER-ON AND CONFIGURATION STRAP TIMING  
Figure 9-3 illustrates the configuration strap valid timing requirements in relation to power-on, for applications where  
RESET_N is not used at power-on. In order for valid configuration strap values to be read at power-on, the following  
timing requirements must be met. The operational levels (Vopp) for the external power supplies are detailed in Section  
9.2, "Operating Conditions**," on page 26.  
FIGURE 9-3:  
POWER-ON CONFIGURATION STRAP VALID TIMING  
All External  
Power Supplies  
Vopp  
tcsh  
Configuration  
Straps  
TABLE 9-5:  
Symbol  
tcsh  
POWER-ON CONFIGURATION STRAP LATCHING TIMING  
Description  
Min  
Typ  
Max  
Units  
Configuration strap hold after external power supplies at opera-  
tional levels  
1
ms  
Device configuration straps are also latched as a result of RESET_N assertion. Refer to Section 9.6.3, "Reset and Con-  
figuration Strap Timing" for additional details.  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 29  
USB4712  
9.6.3  
RESET AND CONFIGURATION STRAP TIMING  
Figure 9-4 illustrates the RESET_N pin timing requirements and its relation to the configuration strap pins. Assertion of  
RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to Section  
8.9, "Resets" for additional information on resets. Refer to Section 3.3, "Configuration Straps and Programmable Func-  
tions" for additional information on configuration straps.  
FIGURE 9-4:  
RESET_N CONFIGURATION STRAP TIMING  
trstia  
RESET_N  
tcsh  
Configuration  
Straps  
TABLE 9-6:  
Symbol  
RESET_N CONFIGURATION STRAP TIMING  
Description  
Min  
Typ  
Max  
Units  
trstia  
tcsh  
RESET_N input assertion time  
5
1
s  
Configuration strap pins hold after RESET_N deassertion  
ms  
Note:  
The clock input must be stable prior to RESET_N deassertion.  
Configuration strap latching and output drive timings shown assume that the Power-On reset has finished  
first otherwise the timings in Section 9.6.2, "Power-On and Configuration Strap Timing" apply.  
9.6.4  
USB TIMING  
All device USB signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Uni-  
versal Serial Bus 2.0 Specification. Please refer to the Universal Serial Bus Revision 2.0 Specification, available at http:/  
/www.usb.org/developers/docs/usb20_docs/.  
9.6.5  
SMBUS TIMING  
All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Sys-  
tem Management Bus Specification. Please refer to the System Management Bus Specification, Version 1.0, available  
at http://smbus.org/specs.  
2
9.6.6  
I C TIMING  
All device I2C signals conform to the 400KHz Fast Mode (Fm) voltage, power, and timing characteristics/specifications  
as set forth in the I2C-Bus Specification. Please refer to the I2C-Bus Specification, available at http://www.nxp.com/doc-  
uments/user_manual/UM10204.pdf.  
DS00002774G-page 30  
2018-2021 Microchip Technology Inc.  
USB4712  
9.6.7  
SPI/SQI TIMING  
This section specifies the SPI/SQI timing requirements for the device.  
FIGURE 9-5:  
SPI/SQI TIMING  
tceh  
tceh  
SPI_CE_N/  
SQI_CE_N  
tfc  
tcel  
SPI_CLK/  
SQI_CLK  
tclq  
tdh  
SPI_DI/  
SQI_D[3:0] (in)  
Input  
data valid  
tos toh  
tov  
toh  
Output  
data valid  
SPI_DO/  
SQI_D[3:0] (out)  
Output  
data valid  
TABLE 9-7:  
Symbol  
SPI/SQI TIMING (60 MHZ OPERATION)  
Description  
Min  
Typ  
Max  
Units  
tfc  
tceh  
tclq  
tdh  
tos  
Clock frequency  
60  
MHz  
ns  
Chip enable (SPI_CE_N/SQI_CE_N) high time  
Clock to input data  
50  
9
ns  
Input data hold time  
0
5
ns  
Output setup time  
ns  
toh  
tov  
tcel  
tceh  
Output hold time  
5
ns  
Clock to output valid  
4
ns  
Chip enable (SPI_CE_N/SQI_CE_N) low to first clock  
Last clock to chip enable (SPI_CE_N/SQI_CE_N) high  
12  
12  
ns  
ns  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 31  
USB4712  
9.7  
Clock Specifications  
The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator input. If the single-ended clock  
oscillator method is implemented, XTALO should be left unconnected and XTALI/CLK_IN should be driven with a  
nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.  
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals  
(XTALI/XTALO). The following circuit design (Figure 9-6) and specifications (Table 9-8) are required to ensure proper  
operation.  
FIGURE 9-6:  
25MHZ CRYSTAL CIRCUIT  
USB4712  
XTALO  
Y1  
XTALI  
C1  
C2  
9.7.1  
CRYSTAL SPECIFICATIONS  
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals  
(XTALI/XTALO). Refer to Table 9-8 for the recommended crystal specifications.  
TABLE 9-8:  
CRYSTAL SPECIFICATIONS  
Parameter  
Symbol  
Min  
Nom  
Max  
Units  
Notes  
Crystal Cut  
AT, typ  
Crystal Oscillation Mode  
Crystal Calibration Mode  
Frequency  
Frequency Tolerance @ 25oC  
Frequency Stability Over Temp  
Frequency Deviation Over Time  
Total Allowable PPM Budget  
Shunt Capacitance  
Fundamental Mode  
Parallel Resonant Mode  
Ffund  
Ftol  
-
25.000  
-
MHz  
PPM  
PPM  
PPM  
PPM  
pF  
-
-
±50  
Ftemp  
Fage  
-
-
±50  
-
±3 to 5  
-
Note 9-5  
-
-
7 typ  
20 typ  
-
±100  
CO  
CL  
-
-
Load Capacitance  
-
-
-
pF  
Drive Level  
PW  
R1  
100  
uW  
Equivalent Series Resistance  
Operating Temperature Range  
XTALI/CLK_IN Pin Capacitance  
XTALO Pin Capacitance  
-
-40  
-
-
50  
+85  
-
Ω
oC  
-
3 typ  
3 typ  
pF  
Note 9-6  
Note 9-6  
-
-
pF  
Note 9-5  
Frequency Deviation Over Time is also referred to as Aging.  
DS00002774G-page 32  
2018-2021 Microchip Technology Inc.  
USB4712  
Note 9-6  
This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included  
in this value. The XTALI/CLK_IN pin, XTALO pin and PCB capacitance values are required to  
accurately calculate the value of the two external load capacitors. These two external load capacitors  
determine the accuracy of the 25.000 MHz frequency.  
9.7.2  
EXTERNAL REFERENCE CLOCK (CLK_IN)  
When using an external reference clock, the following input clock specifications are suggested:  
• 25 MHz  
• 50% duty cycle ±10%, ±100 ppm  
• Jitter < 100 ps RMS  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 33  
USB4712  
10.0 PACKAGE INFORMATION  
Note:  
Package offerings are currently under review and are subject to change.  
40-VQFN (5x5 mm)  
PIN 1  
U4712XXi  
e3  
VRnnn e3  
VCOO  
YYWWNNN  
Legend: XX  
FlexConnect special feature designator (if applicable)  
Temperature range designator  
Automotive  
i
V
R
Product revision  
nnn  
e3  
V
Internal code  
Pb-free JEDEC® designator for Matte Tin (Sn)  
Plant of assembly  
COO Country of origin  
YY  
Year code (last two digits of calendar year)  
WW Week code (week of January 1 is week ‘01’)  
Note:  
In the event the full Microchip part number cannot be marked on one line, it  
will be carried over to the next line, thus limiting the number of available  
characters for customer-specific information.  
* Standard device marking consists of Microchip part number, year code, week code and traceability code.  
For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.  
For QTP devices, any special marking adders are included in QTP price.  
DS00002774G-page 34  
2018-2021 Microchip Technology Inc.  
USB4712  
10.1 40-VQFN  
FIGURE 10-1:  
40-VQFN PACKAGE (DRAWING)  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
D
A
B
NOTE 1  
N
1
2
E
(DATUM B)  
(DATUM A)  
2X  
0.10 C  
2X  
0.10 C  
TOP VIEW  
A1  
0.10 C  
C
A
SEATING  
PLANE  
40X  
(A3)  
0.05 C  
SIDE VIEW  
0.10  
C A B  
D2  
0.10  
C A B  
E2  
e
2
2
1
NOTE 1  
N
K
L
40X b  
0.07  
0.05  
C A B  
C
e
BOTTOM VIEW  
Microchip Technology Drawing C04-236A Sheet 1 of 2  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 35  
USB4712  
FIGURE 10-1:  
40-VQFN PACKAGE (DRAWING) (CONTINUED)  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
Units  
Dimension Limits  
MILLIMETERS  
NOM  
MIN  
MAX  
Number of Terminals  
Pitch  
Overall Height  
Standoff  
Terminal Thickness  
Overall Length  
Exposed Pad Length  
Overall Width  
Exposed Pad Width  
Terminal Width  
Terminal Length  
N
40  
0.40 BSC  
0.90  
0.02  
0.200 REF  
5.00 BSC  
3.50  
5.00 BSC  
3.50  
e
A
A1  
A3  
D
D2  
E
E2  
b
L
0.80  
0.00  
1.00  
0.05  
3.40  
3.60  
3.40  
0.15  
0.35  
0.20  
3.60  
0.25  
0.45  
-
0.20  
0.40  
-
Terminal-to-Exposed-Pad  
K
Notes:  
1. Pin 1 visual index feature may vary, but must be located within the hatched area.  
2. Package is saw singulated  
3. Dimensioning and tolerancing per ASME Y14.5M  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
REF: Reference Dimension, usually without tolerance, for information purposes only.  
Microchip Technology Drawing C04-236A Sheet 2 of 2  
DS00002774G-page 36  
2018-2021 Microchip Technology Inc.  
USB4712  
FIGURE 10-2:  
40-VQFN PACKAGE (LAND PATTERN)  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
C1  
X2  
EV  
40  
G2  
1
2
ØV  
C2 Y2  
EV  
G1  
Y1  
X1  
E
SILK SCREEN  
Contact Pitch  
RECOMMENDED LAND PATTERN  
Units  
Dimension Limits  
E
MILLIMETERS  
NOM  
0.40 BSC  
MIN  
MAX  
Optional Center Pad Width  
Optional Center Pad Length  
Contact Pad Spacing  
X2  
Y2  
C1  
C2  
X1  
Y1  
G1  
G1  
V
3.60  
3.60  
4.90  
4.90  
Contact Pad Spacing  
Contact Pad Width (X40)  
Contact Pad Length (X40)  
Contact Pad to Center Pad (X40)  
Contact Pad to Contact Pad (X36)  
Thermal Via Diameter  
0.20  
0.85  
0.20  
0.20  
0.33  
1.20  
Thermal Via Pitch  
EV  
Notes:  
1. Dimensioning and tolerancing per ASME Y14.5M  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during  
reflow process  
Microchip Technology Drawing C04-236A  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 37  
USB4712  
APPENDIX A: DATA SHEET REVISION HISTORY  
TABLE A-1:  
Revision Level & Date  
DS00002774G (06-01-21)  
REVISION HISTORY  
Section/Figure/Entry  
Correction  
Figure 3-1, "USB4712 Pin Assign-  
ments", Table 3-1, "USB4712 Pin  
Assignments"  
Added FLEX_CMD pin function to GPIO11  
pin and note regarding availability.  
Table 3-2, "Pin Descriptions"  
• Added FLEX_CMD pin definition to  
Miscellaneous section of table.  
• Added notes to SMB1_CLK, SMB1_-  
DAT, SMB2_CLK, SMB2_DAT,  
UART_TX, UART_RX, GPIO6, GPIO11  
pin descriptions regarding availability in  
USB4712PF.  
DS00002774F (08-17-20)  
Section 2.1, "General Description"  
Table 3.2, "Pin Descriptions"  
Note added: “Auto-FlexConnect requires  
Battery Charging v1.2 to always be enabled  
to function. BC1.2 on USB4712PF may be  
optionally enabled or disabled without any  
negative effect.”  
Description modified for Test 1, Test 2 and  
Test 3.  
Section 3.3.2, "Battery Charging  
Configuration (CFG_BC_EN)"  
Note added: “BC1.2 must be enabled for  
Auto-FlexConnect feature to operate.  
USB4712PF may optionally leave BC1.2  
enabled or disabled with no negative effect  
to standard (non-Automatic) FlexConnect  
operation.”  
Section 8.2, "Auto-FlexConnect"  
Note added: “The Auto-FlexConnect feature  
requires that USB Battery Charging (BC1.2)  
be enabled.”  
Section 9.2, "Operating Condi-  
tions**"  
Supply Voltage Rise Time modified.  
Table 9-3, "I/O DC Electrical Char-  
acteristics"  
• MAX values added for I Type Input Buf-  
fer and IS Type Input Buffer  
• The following note removed: “0.42V for  
interfaces using open drain with pull-  
ups to voltages up to 2.1V,   
0.34V for interfaces using open drain  
with pull-ups to voltages greater than  
2.1V”  
DS00002774E (06-01-20)  
Table 2-1, "Family Feature Matrix"  
Figure 5-1, "Hub Mode Flowchart"  
Hub Feature Controller for USB4712LS  
modified.  
Diagram updated.  
DS00002774G-page 38  
2018-2021 Microchip Technology Inc.  
USB4712  
TABLE A-1:  
Revision Level & Date  
DS00002774D (04-15-20)  
REVISION HISTORY (CONTINUED)  
Section/Figure/Entry  
Correction  
All  
Updated document to include family of new  
SKUs: USB4712PF and USB4712LS.  
Cover  
• Updated title to indicate family of  
devices  
• Added additional bullets under Auto-  
FlexConnect to clarify differences  
between SKUs.  
Section 2.1, General Description  
Updated to include information on the differ-  
ences between SKUs  
Section 10.0, Package Information Updated top marking information to include  
the differences between SKUs.  
Product Identification System  
Updated to include ordering information for  
additional SKUs.  
DS00002774C (07-30-19)  
Package Information on page 34  
Data Sheet Package Top Marking changed  
from “USB4712i” to “U4712i” to match  
actual production marking.  
Table 3-2, "Pin Descriptions"  
Description for SMBus 2 Clock and SMBus  
2 Data changed to SMBus 2 SLAVE.  
DS00002774B (01-28-19)  
DS00002774A (08-07-18)  
Public Release  
All  
Initial Release  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 39  
USB4712  
THE MICROCHIP WEB SITE  
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make  
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-  
tains the following information:  
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s  
guides and hardware support documents, latest software releases and archived software  
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion  
groups, Microchip consultant program member listing  
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-  
nars and events, listings of Microchip sales offices, distributors and factory representatives  
CUSTOMER CHANGE NOTIFICATION SERVICE  
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive  
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or  
development tool of interest.  
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-  
cation” and follow the registration instructions.  
CUSTOMER SUPPORT  
Users of Microchip products can receive assistance through several channels:  
• Distributor or Representative  
• Local Sales Office  
• Field Application Engineer (FAE)  
• Technical Support  
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales  
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-  
ment.  
Technical support is available through the web site at: http://microchip.com/support  
DS00002774G-page 40  
2018-2021 Microchip Technology Inc.  
USB4712  
PRODUCT IDENTIFICATION SYSTEM  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.  
[X](1)  
X
XXX  
PART NO.  
Device  
-
/
XXX  
Examples:  
a)  
b)  
c)  
d)  
USB4712-I/PNXVAA  
Tray, -40C to+85C, 40-pin VQFN  
Tape and Reel Temperature  
Option  
Range  
Package  
Automotive  
Code  
USB4712T-I/PNXVAA  
Tape & reel, -40C to+85C, 40-pin VQFN  
Device:  
USB4712 = 1 Downstream Port, 1 Upstream Port  
USB4712LS = 1 Downstream Port, 1 Upstream Port  
USB4712PF = 1 Downstream Port, 1 Upstream Port  
USB4712LS-I/PNXVAA  
Tray, -40C to+85C, 40-pin VQFN  
USB4712PFT-I/PNXVAA  
Tape and Reel  
Option:  
Blank = Standard packaging (tray)  
T
Tape & reel, -40C to+85C, 40-pin VQFN  
(
)
= Tape and Reel Note 1  
Temperature  
Range:  
I
=
-40C to +85C  
Package:  
PNX  
TBD  
=
=
40-pin VQFN  
40-pin VQFN (Wettable Flanks)  
Note 1: Tape and Reel identifier only appears in the  
catalog part number description. This identi-  
fier is used for ordering purposes and is not  
printed on the device package. Check with  
your Microchip Sales Office for package  
Automotive Code: Vxx  
=
3 character code with “V” prefix,   
specifying automotive product.  
availability with the Tape and Reel option.  
2018-2021 Microchip Technology Inc.  
DS00002774G-page 41  
USB4712  
Note the following details of the code protection feature on Microchip devices:  
•
•
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.  
Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.  
There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip  
devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications  
contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished  
without violating Microchip's intellectual property rights.  
•
•
Microchip is willing to work with any customer who is concerned about the integrity of its code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not  
mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are  
committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection  
feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or  
other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Information  
regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsi-  
bility to ensure that your application meets with your specifications.  
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF  
ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMA-  
TION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FIT-  
NESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.  
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS,  
DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER  
CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE  
FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFOR-  
MATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR  
THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer  
agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use.  
No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.  
Trademarks  
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,  
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,  
MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,  
PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,  
TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other  
countries.  
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,  
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion,  
SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology  
Incorporated in the U.S.A.  
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom,  
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average  
Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip  
Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK,  
NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker,  
RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II,  
Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and  
ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.  
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.  
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in  
other countries.  
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other  
countries.  
All other trademarks mentioned herein are property of their respective companies.  
© 2018-2021, Microchip Technology Incorporated, All Rights Reserved.  
ISBN: 9781522483182  
For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.  
DS00002774G-page 42  
2018-2021 Microchip Technology Inc.  
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2018-2021 Microchip Technology Inc.  
DS00002774G-page 43  
02/28/20  

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