UCS1003-2-BP-TR_技术文档

UCS1003-1/2/3

USB Port Power Controller with Charger Emulation

Features

Description

• Port Power Switch with Two Current Limit Behaviors:

- 2.9V to 5.5V source voltage range

- Up to 3.0A current (2.85A typical) with 55 m

on resistance

- Overcurrent trip or Constant-Current Limiting

- Soft turn-on circuitry

- Selectable current limit

The UCS1003-1/2/3 family of devices provides a USB

port power switch for precise control of up to 3.0A

continuous current (2.85A typical) with Overcurrent

Limit (OCL), dynamic thermal management, latch or

auto-recovery (low test current) Fault handling, select-

able active-high or active-low enable, Undervoltage

and Overvoltage Lockout, backdrive protection and

back-voltage protection.

- UCS1003-1 has programmable current limit via

the SMBus 2.0/I²C protocol

- Dynamic thermal management

- Undervoltage Lockout (UVLO) and Overvoltage

Lockout (OVLO)

- Backdrive, back-voltage protection

- Latch or auto-recovery (low test current) Fault handling

- Selectable active-high or active-low power

switch enable

Split supply support for V and V is an option for low

S

DD

power in system standby states. This gives battery-

operated applications (such as on-board computers) the

ability to detect attachments from a Sleep or OFF state.

After the Attach Detection is flagged, the system can

decide to wake-up and/or provide charging.

- BC1.2 V_BUSdischarge port renegotiation function

• Selectable/Automatic Cycling of Universal Serial Bus

(USB) Data Line Charger Emulation Profiles:

- USB-IF BC1.2 Charging Downstream Port (CDP)

and Dedicated Charging Port (DCP) modes,

Chinese Telecommunications Industry Standard

YD/T 1591-2009 and most Apple^®Inc.,

Samsung and RIM^®protocols standard

- UCS1003-1 supports other charger emulation

profiles as defined via the SMBus 2.0/I²C protocol

- Supports 12W charging emulation

In addition to Power Switching and Current-Limiting

modes, the UCS1003-1/2/3 will automatically charge a

wide variety of portable devices, including USB-IF

BC1.2, YD/T-1591 (2009), most Apple Inc., Samsung,

RIM and many others. Nine preloaded charger emula-

tion profiles maximize the compatibility coverage of the

peripheral devices. Additionally,

a

customizable

charger emulation profile is available in UCS1003-1 to

accommodate unique existing and future portable

device handshaking/signature requirements.

- USB 2.0 compliant high-speed data switch (in

Data Pass-Through, SDP and CDP modes)

- Nine preloaded charger emulation profiles for

maximum compatibility coverage of the

peripheral devices

- UCS1003-1 has one custom programmable

charger emulation profile for portable device

support for fully host-controlled charger emulation

• Supports Active Cables

The UCS1003-1 also provides current monitoring to

allow intelligent management of system power and

charge rationing for controlled delivery of current, regard-

less of the host power state. This is especially important

for battery-operated applications that want to provide

power and do not want to drain the battery excessively.

The UCS1003-1/2/3 family is available in

4 mm x 4 mm 20-pin QFN package.

a

• UCS1003-1 Supports Self-Contained Current Monitoring

and Rationing for Power Allocation Applications

• UCS1003-1 and UCS1003-3 have Low-Power

Attach Detection and Open-Drain (A_DET#) Pin

• UCS1003-2 has Charging Active (CHRG#)

Open-Drain Pin

Applications

• Notebook and Netbook Computers

• Tablets and E-Book Readers

• Desktops and Monitors

• Ultra Low-Power Sleep State

• Optional Split Supply Support for V_Sand V_DDfor

Low Power in System Standby States

• Wake on Attach USB (UCS1003-1 and UCS1003-3)

• UCS1003-1 Supports SMBus 2.0/I²C Communications:

- Supports block write and read

• Docking Stations and Printers

• AC-DC Wall Adapters

- Multiple SMBus addresses

• Wide Operating Temperature Range: -40°C to +85°C

• IEC61000-4-2 8/15 kV Electrostatic Discharge (ESD)

Immunity

• UL Recognized and EN/IEC 60950-1 (CB) Certified

 2014-2015 Microchip Technology Inc.

DS20005346B-page 1

UCS1003-1/2/3

Package Type

UCS1003-1

4x4 QFN*

UCS1003-2

4x4 QFN*

20 19 18 17 16

D

M1

M2

M1

M2

1

2

3

4

5

15

14

1

2

3

4

5

15

14

13

MIN

EP

21

EP

21

V

13 ALERT#

V

ALERT#

BUS1

BUS2

BUS1

BUS2

12 S0

12 SMCLK/S0

11 SMDATA/LATCH

11 LATCH

I

COMM_SEL/I

LIM

6

7

8

9

10

6

7

8

9

10

UCS1003-3

4x4 QFN*

20 19 18 17 16

D

M1

1

15

MIN

D

14

M2

2

3

4

5

EP

21

13 ALERT#

12 S0

V

BUS1

BUS2

LATCH

11

I

LIM

6

7

8

9

10

*

Includes Exposed Thermal Pad (EP); see Table 3-1.

DS20005346B-page 2

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

Block Diagram

D_PIN

D_POUT

USB 2.0 HS Data Switch &

Charger Emulator

D_MOUT

D_MIN

V_DD

V_S

Attach Detector

V_BUS

UVLO,

OVLO

GND

Power

Switch

COMM_SEL⁽¹⁾/I_LIM

ALERT#

A_DET#^(1,3)

V_DD

CHRG#⁽²⁾

PWR_EN

Temp

Charger Control,

Measurement,

OCL

Interface,

Logic

SEL

EM_EN

M1

M2

SMCLK⁽¹⁾/S0

SMDATA⁽¹⁾/LATCH

Note 1: Available for UCS1003-1 only.

2: Available for UCS1003-2 only.

3: Available for UCS1003-3 only.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 3

UCS1003-1/2/3

NOTES:

DS20005346B-page 4

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

1.0

ELECTRICAL

CHARACTERISTICS

†

Absolute Maximum Ratings

Voltage on V , V and V

Pins....................................................................................................................-0.3 to 6V

DD

S

BUS

Pull-up Voltage (V

)....................................................................................................................-0.3 to V + 0.3V

DD

PULLUP

Data Switch Current (I

), Switch On...........................................................................................................±50 mA

HSW_ON

Port Power Switch Current ....................................................................................................................Internally Limited

Data Switch Pin Voltage To Ground (D

, D , D

, D ); (V powered or unpowered).......-0.3 to V + 0.3V

POUT PIN

MOUT MIN DD DD

Differential Voltage Across Open Data Switch (D

– D , D

– D

, D

– D

) .........V

DD

POUT

MOUT

MIN

POUT MIN

MOUT

Voltage on any Other Pin to Ground ...................................................................................................-0.3 to V + 0.3V

DD

Current on any Other Pin......................................................................................................................................±10 mA

Package Power Dissipation ............................................................................................................................... Table 1-1

Operating Ambient Temperature Range .....................................................................................................-40 to +125°C

Storage Temperature Range.......................................................................................................................-55 to +150°C

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at those or any other conditions above those indicated in

the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods

may affect device reliability.

TABLE 1-1:

Board

POWER DISSIPATION SUMMARY

Derating

Factor Above

+25°C

T < +25°C

Power

Rating

T < +70°C T < +85°C

A A

A

Package



Power

JC

JA

Rating

High K

(see Note 1)

20-pin QFN

4 x 4 mm

6°C/W

41°C/W

60°C/W

24.4 mW°/C

2193 mW

1095 mW

729 mW

Low K

(see Note 1)

20-pin QFN

4 x 4 mm

16.67 mW°/C

1498 mW

748 mW

498 mW

Note 1: Junction to ambient ( ) is dependent on the design of the thermal vias. A High K board uses a thermal

JA

via design with a thermal landing soldered to the PCB ground plane, with 0.3 mm (12 mil) diameter vias in

a 3x3 matrix (9 total) at 0.5 mm (20 mil) pitch. The board is multilayer with 1-ounce internal power and

ground planes and 2-ounce copper traces on top and bottom. A Low K board is a two-layer board without

thermal via design, with 2-ounce copper traces on the top and bottom.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 5

UCS1003-1/2/3

TABLE 1-2:

Electrical Characteristics: Unless otherwise specified, V = 4.5V to 5.5V, V = 2.9V to 5.5V, V = 3V to 5.5V,

PULLUP

ELECTRICAL CHARACTERISTICS

DD

S

T = -40°C to +85°C; all Typical values at V = V = 5V, T = +27°C.

A

DD

S

A

Characteristic

Sym.

Min.

Typ.

Max.

Unit

Conditions

Power Supply

Supply Voltage

V

4.5

2.9

—

5

5.5

750

V

(Note 1)

DD

Source Voltage

V

S

Supply Current in Active

I

650

µA

Average current, I

= 0 mA

BUS

ACTIVE

(I

+ I

)

DD_ACTIVE

VS_ACT

Supply Current in Sleep

(I + I

I

—

5

15

—

µA

Average current,

SLEEP

)

V

 V

DD_SLEEP

VS_SLEEP

PULLUP DD

Supply Current in Detect

(I + I

I

185

Average current,

no portable device attached

DETECT

)

VS_DETECT

DD_DETECT

Power-on Reset

V Low Threshold

V

—

2.5

100

4

—

V

mV

V

V voltage increasing

S

S_UVLO

V Low Hysteresis

V

V voltage decreasing

S

S_UVLO_HYST

V

Low Threshold

Low Hysteresis

V

voltage increasing

voltage decreasing

DD

DD_TH

DD

V

500

mV

DD_TH_HYST

I/O Pins – SMCLK (UCS1003-1), SMDATA (UCS1003-1), EM_EN, M1, M2, PWR_EN, S0, LATCH, ALERT#, A_DET#

(UCS1003-1 and UCS1003-3), CHRG# (UCS1003-2) – DC Parameters

Output Low Voltage

V

—

0.4

V

I

= 8 mA,

OL

SINK_IO

SMDATA, ALERT#,

A_DET#, CHRG#

Input High Voltage

V

2.0

—

0.8

±5

V

PWR_EN, EM_EN, M1, M2,

LATCH, S0, SMDATA, SMCLK

IH

Input Low Voltage

V

PWR_EN, EM_EN, M1, M2,

LATCH, S0, SMDATA, SMCLK

IL

Leakage Current

I

—

µA

Powered or unpowered,

LEAK

V

 V

PULLUP

DD

Interrupt Pins – AC Parameters

ALERT#, A_DET# Pins

Blanking Time

t

—

25

5

—

ms

BLANK

ALERT# Pin

t

MASK

Interrupt Masking Time

2

SMBus/I C Timing (UCS1003-1 only)

Input Capacitance

C

—

5

—

400

50

pF

kHz

ns

IN

Clock Frequency

f

10

—

SMB

Spike Suppression

Bus Free Time Stop to Start

t

(Note 2)

SP

t

1.3

—

µs

BUF

Note 1: For split supply systems using the Attach Detection feature, V must not exceed V + 150 mV.

S

DD

2: This parameter is ensured by design and not 100% tested.

3: This parameter is characterized, but not 100% production tested.

4: The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report

values above I (if I  I ) or above I (if I > I and I 1.68A).

LIM

BUS_R2MIN

LIM

BUS_R2MIN

LIM

5: The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value

in the range is typical.

DS20005346B-page 6

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

TABLE 1-2:

Electrical Characteristics: Unless otherwise specified, V = 4.5V to 5.5V, V = 2.9V to 5.5V, V = 3V to 5.5V,

PULLUP

ELECTRICAL CHARACTERISTICS (CONTINUED)

DD

S

T = -40°C to +85°C; all Typical values at V = V = 5V, T = +27°C.

A

DD

S

A

Characteristic

Sym.

Min.

Typ.

Max.

Unit

Conditions

Start Setup Time

Start Hold Time

Stop Setup Time

Data Hold Time

Data Setup Time

Clock Low Period

Clock High Period

Clock/Data Fall Time

Clock/Data Rise Time

Capacitive Load

Time-out

t

0.6

0

—

µs

ns

pF

ms

µs

SU:STA

HD:STA

SU:STO

t

—

t

—

When transmitting to the master

When receiving from the master

HD:DAT

0.3

0.6

1.3

0.6

—

t

—

SU:DAT

t

—

LOW

t

—

HIGH

t

300

400

35

—

Min = 20 + 0.1 C

ns (Note 3)

FALL

LOAD

—

RISE

LOAD

C

—

Per bus line (Note 2)

LOAD

TIMEOUT

t

25

Disabled by default (Note 2)

Idle Reset

t

350

IDLE_RESET

High-Speed Data Switch

High-Speed Data Switch – DC Parameters

Switch Leakage Current

Charger Resistance

I

—

±0.5

—

µA

Switch open – D

to D

,

HSW_OFF

POUT

D

to D

or all four pins to

MIN

MOUT

ground; V  V

DD

S

R

—

2

—

M

D

or D

to V

or

CHG

POUT

MOUT

BUS,

ground (see Figure 1-2),

BC1.2 DCP charger

emulation is active

On Resistance

R

—

2

5

—



Switch closed, V = 5V

ON_HSW

DD

Test Current = 8 mA,

Test Voltage = 0.4V

(see Figure 1-2)

On Resistance

R

Switch closed, V = 5V,

ON_HSW_1

DD

Test Current = 8 mA,

Test Voltage = 3.0V

(see Figure 1-2)

Delta-On Resistance

R

±0.3

Switch closed, V = 5V,

ON_HSW

DD

I

= 8 mA, V

= 0 to 1.5V

TST

(see Figure 1-2)

High-Speed Data Switch – AC Parameters

D , D Capacitance to Ground

C

—

4

2

—

pF

Switch closed, V = 5V

DD

P

M

HSW_ON

D , D Capacitance to Ground

C

Switch open, V = 5V

DD

P

M

HSW_OFF

Note 1: For split supply systems using the Attach Detection feature, V must not exceed V + 150 mV.

S

DD

2: This parameter is ensured by design and not 100% tested.

3: This parameter is characterized, but not 100% production tested.

4: The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report

values above I (if I  I ) or above I (if I > I and I 1.68A).

LIM

BUS_R2MIN

LIM

BUS_R2MIN

LIM

5: The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value

in the range is typical.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 7

UCS1003-1/2/3

TABLE 1-2:

Electrical Characteristics: Unless otherwise specified, V = 4.5V to 5.5V, V = 2.9V to 5.5V, V = 3V to 5.5V,

PULLUP

ELECTRICAL CHARACTERISTICS (CONTINUED)

DD

S

T = -40°C to +85°C; all Typical values at V = V = 5V, T = +27°C.

A

DD

S

A

Characteristic

Sym.

Min.

—

Typ.

400

Max.

Unit

Conditions

Turn-Off Time

t

—

µs

Time from state control (EM_EN,

M1, M2) switch on to switch off,

HSW_OFF

R

= 50, C

= 5 pF

TERM

LOAD

Turn-On Time

t

—

400

—

µs

Time from state control (EM_EN,

M1, M2) switch off to switch on,

HSW_ON

R

= 50, C

= 5 pF

= 5 pF,

TERM

LOAD

Propagation Delay

Propagation Delay Skew

Rise/Fall Time

t

—

0.25

25

—

ns

ps

ns

dB

R

= 50, C

PD

TERM

LOAD

t

PD

t

10

F/R

D – D Crosstalk

X

-40

-30

P

M

TALK

Off Isolation

-3 dB Bandwidth

Total Jitter

O

IRR

f = 240 MHz

BW

—

1100

200

—

MHz

ps

R

= 50, C

= 5 pF,

TERM

LOAD

V

= V

= 350 mV DC

= 50, C = 5 pF,

TERM LOAD

DPOUT

DMOUT

t

R

J

Rise Time = Fall Time = 500 ps

15

at 480 Mbps (PRBS = 2 – 1)

Skew of Opposite Transitions

of the Same Output

t

—

20

—

ps

R

= 50, C

= 5 pF

SK(P)

TERM

LOAD

Port Power Switch

Port Power Switch – DC Parameter

Overvoltage Lockout

On Resistance

V

—

6

—

V

S_OV

R

55

m

µA

4.75V < V < 5.25V

S

ON_PSW

LEAK_VS

V Leakage Current

I

2.2

150

Sleep state into V pin

S

Back-Voltage Protection

Threshold

V

mV

V > V , V > V

BUS S S S_UVLO

BV_TH

Backdrive Current

I

—

0

3

µA

V

< V

,

DD_TH

BD_1

BD_2

DD

Any powered power pin to any

unpowered power pin; current

out of unpowered pin (Note 3)

I

—

0

2

V

< V

,

DD_TH

DD

Any powered power pin to any

unpowered power pin, except

for V to V

in Detect power

DD

BUS

state and V to V

in Active

S

BUS

power state; current out of

unpowered pin (Note 3)

Note 1: For split supply systems using the Attach Detection feature, V must not exceed V + 150 mV.

S

DD

2: This parameter is ensured by design and not 100% tested.

3: This parameter is characterized, but not 100% production tested.

4: The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report

values above I (if I  I ) or above I (if I > I and I 1.68A).

LIM

BUS_R2MIN

LIM

BUS_R2MIN

LIM

5: The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value

in the range is typical.

DS20005346B-page 8

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

TABLE 1-2:

Electrical Characteristics: Unless otherwise specified, V = 4.5V to 5.5V, V = 2.9V to 5.5V, V = 3V to 5.5V,

PULLUP

ELECTRICAL CHARACTERISTICS (CONTINUED)

DD

S

T = -40°C to +85°C; all Typical values at V = V = 5V, T = +27°C.

A

DD

S

A

Characteristic

Sym.

Min.

—

Typ.

570

Max.

Unit

Conditions

Selectable Current Limits

I

—

mA

I

Resistor = 0 or 47 k

LIM1

LIM

(UCS1003-1 only)

I

Resistor = 47 k

LIM

(UCS1003-2/3)

(minimum mA setting)

I

—

1000

1130

1350

1680

2050

2280

2850

—

I

Resistor = 10 k or 56 k

LIM

LIM2

(UCS1003-1 only)

I

Resistor = 56 k

LIM

(UCS1003-2/3)

I

LIM

Resistor = 12 k or 68 k

LIM3

(UCS1003-1 only)

I

Resistor = 68 k

LIM

(UCS1003-2/3)

I

—

I

LIM

Resistor = 15 k or 82 k

LIM4

(UCS1003-1 only)

I

Resistor = 82 k

LIM

(UCS1003-2/3)

I

—

I

LIM

Resistor = 18 k or 100 k

LIM5

(UCS1003-1 only)

I

Resistor = 100 k

LIM

(UCS1003-2/3)

I

—

I

LIM

Resistor = 22 k or 120 k

LIM6

(UCS1003-1 only)

I

Resistor = 120 k

LIM

(UCS1003-2/3)

I

—

I

LIM

Resistor = 27 k or 150 k

LIM7

(UCS1003-1 only)

I

Resistor = 150 k

LIM

(UCS1003-2/3)

I Resistor = 33 k or V

LIM

I

2700

3000

LIM8

DD

(UCS1003-1 only)

I

Resistor = V

LIM

DD

(UCS1003-2/3)

Pin Wake Time

SMBus Wake Time

Idle Sleep Time

t

—

3

4

—

ms

PIN_WAKE

t

(UCS1003-1 only)

SMB_WAKE

t

200

IDLE_SLEEP

Note 1: For split supply systems using the Attach Detection feature, V must not exceed V + 150 mV.

S

DD

2: This parameter is ensured by design and not 100% tested.

3: This parameter is characterized, but not 100% production tested.

4: The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report

values above I (if I  I ) or above I (if I > I and I 1.68A).

LIM

BUS_R2MIN

LIM

BUS_R2MIN

LIM

5: The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value

in the range is typical.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 9

UCS1003-1/2/3

TABLE 1-2:

Electrical Characteristics: Unless otherwise specified, V = 4.5V to 5.5V, V = 2.9V to 5.5V, V = 3V to 5.5V,

PULLUP

ELECTRICAL CHARACTERISTICS (CONTINUED)

DD

S

T = -40°C to +85°C; all Typical values at V = V = 5V, T = +27°C.

A

DD

S

A

Characteristic

Sym.

Min.

—

Typ.

110

Max.

Unit

Conditions

Thermal Regulation Limit

T

—

°C

Die temperature at which

current limit will be reduced

REG

Thermal Regulation

Hysteresis

T

—

10

—

Hysteresis for t

functionality;

REG

REG_HYST

temperature must drop by this

value before I value is

LIM

restored to normal operation

Thermal Shutdown

Threshold

T

—

135

35

—

°C

Die temperature at which port

power switch will turn off

TSD

Thermal Shutdown

Hysteresis

T

After shutdown, due to T

TSD

TSD_HYST

being reached, die temperature

drop required before port power

switch can be turned on again

Auto-Recovery Test Current

Auto-Recovery Test Voltage

I

—

190

750

—

mA

mV

Portable device attached,

TEST

V

= 0V, Die Temp < T

BUS

TSD

V

Portable device attached,

= 0V before application,

TEST

V

BUS

Die Temp < T

programmable

TSD

(UCS1003-1 only),

250-1000 mV, default listed

Discharge Impedance

Turn-On Delay

R

—

100

—



DISCHARGE

Port Power Switch – AC Parameters

t

—

0.75

—

ms

PWR_EN active toggle to switch

ON_PSW

on time, V

active

discharge is not

BUS

Turn-Off Time

t

—

0.75

1

—

ms

PWR_EN inactive toggle to

switch off time, C = 120 μF

OFF_PSW_INA

BUS

t

Overcurrent error, V

min

BUS

OFF_PSW_ERR

error or discharge error to

switch off, C = 120 μF

BUS

Turn-Off Time

t

—

100

1.1

—

ns

TSD or backdrive error to switch

off, C = 120 μF

OFF_PSW_ERR

BUS

V

Output Rise Time

t

ms

Measured from 10% to 90% of

, C = 220 μF,

BUS

R_BUS

V

BUS

LOAD

I

= 1.0A

LIM

Soft Turn-on Rate

I

/

—

100

200

—

mA/µs

ms

BUS

t

Temperature Update Time

t

Programmable

(UCS1003-1 only)

200-1600 ms, default listed

DC_TEMP

Note 1: For split supply systems using the Attach Detection feature, V must not exceed V + 150 mV.

S

DD

2: This parameter is ensured by design and not 100% tested.

3: This parameter is characterized, but not 100% production tested.

4: The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report

values above I (if I  I ) or above I (if I > I and I 1.68A).

LIM

BUS_R2MIN

LIM

BUS_R2MIN

LIM

5: The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value

in the range is typical.

DS20005346B-page 10

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

TABLE 1-2:

Electrical Characteristics: Unless otherwise specified, V = 4.5V to 5.5V, V = 2.9V to 5.5V, V = 3V to 5.5V,

PULLUP

ELECTRICAL CHARACTERISTICS (CONTINUED)

DD

S

T = -40°C to +85°C; all Typical values at V = V = 5V, T = +27°C.

A

DD

S

A

Characteristic

Sym.

Min.

—

Typ.

1.5

Max.

Unit

Conditions

Short-Circuit Response Time

Short-Circuit Detection Time

Latched Mode Cycle Time

t

—

µs

ms

Time from detection of short to

current limit applied; no C

applied

SHORT_LIM

BUS

t

—

6

7

—

Time from detection of short to

port power switch disconnect

and ALERT# pin assertion

SHORT

t

From PWR_EN edge transition

from inactive to active to begin

error recovery

UL

Auto-Recovery Mode

Cycle Time

t

25

Time delay before error

condition check, programmable

(UCS1003-1 only) 10-25 ms,

default listed

CYCLE

Auto-Recovery Delay

Discharge Time

t

—

20

—

ms

Portable device attached, V

BUS

RST

must be  V

after this time,

TEST

programmable (UCS1003-1

only) 10-25 ms, default listed

t

200

Amount of time discharge

resistor applied, programmable

(UCS1003-1 only) 100-400 ms,

default listed

DISCHARGE

Port Power Switch Operation with Trip Mode Current Limiting

Region 2 Current Keep-out

I

—

0.12

2.0

—

A

V

BUS_R2MIN

Minimum V

Output

Allowed at

V

1.5

2.25

BUS

BUS_MIN

Port Power Switch Operation with Constant-Current Limiting (Variable Slope)

Region 2 Current Keep-out

I

—

1.68

2.0

—

A

V

BUS_R2MIN

Minimum V

Output

Allowed at

V

1.5

2.25

BUS

BUS_MIN

Current Measurement (UCS1003-1 only) – DC

Current Measurement Range

I

0

—

2988.6

—

mA

Range 0-255 LSB (Note 4)

BUS_M

Reported Current

D

—

11.72

1 LSB

IBUS_M

Measurement Resolution

Current Measurement

Accuracy

—

±2

—

%

180 mA < I

< I

BUS LIM

LSB

I

< 180 mA

BUS

Current Measurement (UCS1003-1 only) – AC

500 µs

Sampling Rate

—

Note 1: For split supply systems using the Attach Detection feature, V must not exceed V + 150 mV.

S

DD

2: This parameter is ensured by design and not 100% tested.

3: This parameter is characterized, but not 100% production tested.

4: The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report

values above I (if I  I ) or above I (if I > I and I 1.68A).

LIM

BUS_R2MIN

LIM

BUS_R2MIN

LIM

5: The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value

in the range is typical.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 11

UCS1003-1/2/3

TABLE 1-2:

Electrical Characteristics: Unless otherwise specified, V = 4.5V to 5.5V, V = 2.9V to 5.5V, V = 3V to 5.5V,

PULLUP

ELECTRICAL CHARACTERISTICS (CONTINUED)

DD

S

T = -40°C to +85°C; all Typical values at V = V = 5V, T = +27°C.

A

DD

S

A

Characteristic

Sym.

Min.

Typ.

Max.

Unit

Conditions

Charge Rationing (UCS1003-1 only) - DC

±4.5 %

Accumulated Current

—

Measurement Accuracy

Charge Rationing (UCS1003-1 only) – AC

Current Measurement

Update Time

t

—

1

—

s

PCYCLE

Attach/Removal Detection

V

Bypass – DC

BUS

On Resistance

Leakage Current

Current Limit

R

—

50

—

2

—

3



ON_BYP

I

µA

mA

Switch off (Note 2)

= 5V and V > 4.75V

BUS

LEAK_BYP

I

/

—

V

DET_CHG

DD

I

BUS_BYP

Attach/Removal Detection – DC

Attach Detection Threshold

I

—

800

700

800

—

µA

Programmable (UCS1003-1

only) 200-1000 µA, default

listed

DET_QUAL

Primary Removal Detection

Threshold

I

Programmable (UCS1003-1

only) 100-900 µA, default listed,

Active power state

REM_QUAL_ACT

Programmable (UCS1003-1

only) 200-1000 µA, default

listed, Detect power state (see

Section 8.4 “Removal

Detection”)

REM_QUAL_DET

Attach/Removal Detection – AC

Attach Detection Time

t

—

100

—

ms

Time from attach to A_DET#

assert (UCS1003-1 and

UCS1003-3 only)

DET_QUAL

Removal Detection Time

Allowed Charge Time

t

—

1000

800

—

ms

REM_QUAL

t

C

= 500 µF maximum,

DET_CHARGE

BUS

programmable 200-2000 ms,

default listed

Charger Emulation Profile

General Emulation – DC

Charging Current Threshold

I

—

46.9

—

mA

Default value for UCS1003-1

UCS1003-2 and UCS1003-3

BUS_CHG

175.8

Note 1: For split supply systems using the Attach Detection feature, V must not exceed V + 150 mV.

S

DD

2: This parameter is ensured by design and not 100% tested.

3: This parameter is characterized, but not 100% production tested.

4: The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report

values above I (if I  I ) or above I (if I > I and I 1.68A).

LIM

BUS_R2MIN

LIM

BUS_R2MIN

LIM

5: The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value

in the range is typical.

DS20005346B-page 12

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

TABLE 1-2:

Electrical Characteristics: Unless otherwise specified, V = 4.5V to 5.5V, V = 2.9V to 5.5V, V = 3V to 5.5V,

PULLUP

ELECTRICAL CHARACTERISTICS (CONTINUED)

DD

S

T = -40°C to +85°C; all Typical values at V = V = 5V, T = +27°C.

A

DD

S

A

Characteristic

Sym.

Min.

11.72

Typ.

—

Max.

Unit

Conditions

Charging Current

Threshold Range

I

175.8

mA

(Note 5)

Connected between D

BUS_CHG_RNG

DP-DM Shunt Resistor Value

R

—

200



and

POUT

DCP_RES

D

,

MOUT

0V < D

= D

< 3V

POUT

MOUT

Response Magnitude

(voltage divider option

resistance range)

SX_RXMAG_

DVDR

93

k

(Note 5)

Resistor Ratio Range

(voltage divider option)

SX_RATIO

0.25

—

±0.5

—

0.66

—

V/V

%

(Note 5)

Resistor Ratio Accuracy

(voltage divider option)

SX_RATIO_ ACC

Average over range

(Note 5)

Response Magnitude

(resistor option range)

SX_RXMAG_

RES

1.8

—

150

—

k

%

Internal Resistor Tolerance

(resistor option)

SX_RXMAG_

RES_ACC

±10

—

Average over range

(Note 5)

Response Magnitude

(voltage option range)

SX_RXMAG_

VOLT

0.4

—

2.2

—

V

Voltage Option Accuracy

Voltage Option Output

SX_RXMAG_

VOLT_ACC

±1

%

No load, average over range

SX_RXMAG_

VOLT_ACC_ 150

—

-6

—

%

150 µA load,

average over range

SX_RXMAG_

VOLT_ACC_ 250

—

-10

—

%

250 µA load,

average over range

SX_RXMAG_

VOLT_BC

0.5

10

—

V

D

= 0.6V, 250 µA load

MOUT

(Note 3)

Response Magnitude

(zero volt option range)

SX_PUPD

—

150

—

µA

%

SX_RXMAG_VOLT = 0

(Note 5)

Pull-Down Current Accuracy

SX_PUPD _

ACC_3p6

±5

D

or D

= 3.6V,

MOUT

POUT

compliance voltage

Pull-Down Current

SX_PUPD _

ACC_BC

50

—

µA

Setting = 100 µA,

D

or D

= 0.15V

MOUT

POUT

compliance voltage (Note 3)

Stimulus Voltage

Threshold Range

SX_TH

0.3

—

2.2

V

(Note 5)

Stimulus Voltage Accuracy

SX_TH_ ACC

—

±2

—

%

V

Average over range

SX_TH_ACC_

BC

0.25

At SX_TH = 0.3V (Note 3)

Note 1: For split supply systems using the Attach Detection feature, V must not exceed V + 150 mV.

S

DD

2: This parameter is ensured by design and not 100% tested.

3: This parameter is characterized, but not 100% production tested.

4: The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report

values above I (if I  I ) or above I (if I > I and I 1.68A).

LIM

BUS_R2MIN

LIM

BUS_R2MIN

LIM

5: The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value

in the range is typical.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 13

UCS1003-1/2/3

TABLE 1-2:

Electrical Characteristics: Unless otherwise specified, V = 4.5V to 5.5V, V = 2.9V to 5.5V, V = 3V to 5.5V,

PULLUP

ELECTRICAL CHARACTERISTICS (CONTINUED)

DD

S

T = -40°C to +85°C; all Typical values at V = V = 5V, T = +27°C.

A

DD

S

A

Characteristic

Sym.

Min.

Typ.

Max.

Unit

Conditions

General Emulation – AC

Emulation Reset Time

t

—

50

0.8

0

50

—

ms

s

Default

EM_RESET

Emulation Reset Time Range t_{EM_RESET_ RNG}

175

12.8

100

(Note 5)

Emulation Time-out Range

t

EM_ TIMEOUT

Stimulus Delay,

SX_TD Range

t

ms

STIM_DEL

Emulation Delay

t

—

0.5

s

Time from set impedance to

RES_EM

impedance appearing on D /D

P

M

(Note 3)

Note 1: For split supply systems using the Attach Detection feature, V must not exceed V + 150 mV.

S

DD

2: This parameter is ensured by design and not 100% tested.

3: This parameter is characterized, but not 100% production tested.

4: The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report

values above I (if I  I ) or above I (if I > I and I 1.68A).

LIM

BUS_R2MIN

LIM

BUS_R2MIN

LIM

5: The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value

in the range is typical.

Rise Time

Fall Time

90%

VCRS

10%

Differential

Data Lines

t

F

R

Data Signal Rise and Fall Time

FIGURE 1-1:

USB Rise Time/Fall Time Measurement.

DS20005346B-page 14

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

V_BUS

R_CHG

D_POUT

D_PIN

R_CHG

I_TST

V_TST

V_BUS

R_CHG

D_MOUT

D_MIN

R_CHG

I_TST

V_TST

FIGURE 1-2:

Description of DC Terms.

TABLE 1-3:

TEMPERATURE SPECIFICATIONS

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges

Operating Temperature Range

Storage Temperature Range

T

-40

-55

—

+85

°C

A

T

+150

A

Thermal Package Resistances (see Table 1-1)

 2014-2015 Microchip Technology Inc.

DS20005346B-page 15

UCS1003-1/2/3

NOTES:

DS20005346B-page 16

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

2.0

TYPICAL PERFORMANCE

CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, V = V = 5V, T = +27°C

.

DD

S

A

V_S= V_DD= 5V, short applied at 16 ms

6

5

4

3

2

1

0

V_DD

6

5

4

3

2

1

0

ALERT# Pin

5

I_BUSCurrent

10

0

20

30

40

50

Time (ms)

FIGURE 2-1:

USB-IF High-Speed Eye

FIGURE 2-4:

Power-up Into a Short.

Diagram (Without Data Switch).

6

14

V_BUS

V_S= V_DD= 5V,

I_LIM= 2.05A (typical),

short applied at 17.2 µs

5

4

3

2

1

12

10

8

6

4

0

2

I_BUS

-1

0

-2

0

-2

20

40

Time (µs)

FIGURE 2-2:

USB-IF High-Speed Eye

FIGURE 2-5:

Internal Power Switch Short

Diagram (With Data Switch).

Response.

6

V_S= V_DD= 5V

I_LIM= 3A max. (2.85A typical), short applied at 2 ms

6

5

6

5

4

3

2

1

0

-1

5

ALERT #

V_BUS

4

V_S= V_DD= 5V

M2 = 0,

M1 = PWR_EN = 1

4

3

2

3

I_BUS

V_BUS

4

2

1

EM_EN

0

-1

0

-1

100

200

300

400

500

0

2

6

8

10

Time (ms)

FIGURE 2-3:

Short Applied After

FIGURE 2-6:

V_BUSDischarge Behavior.

Power-up.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 17

UCS1003-1/2/3

Note: Unless otherwise indicated, V = V = 5V, T = +27°C

.

DD

S

A

90

80

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

D_POUT= D_MOUT= 0.35V

-40

-15

10

35

60

85

0.01

0.1

1

10

100

1000

Frequency (MHz)

Temperature (°C)

FIGURE 2-7:

Data Switch Off Isolation vs.

FIGURE 2-10:

Power Switch On

Frequency.

Resistance vs. Temperature.

200

0

-2

-4

-6

-8

-10

-12

-14

-16

-18

-20

D_POUT= D_MOUT= 3V

180

160

140

120

100

80

60

40

20

0

D_POUT= D_MOUT= 0.15V

D_POUT= D_MOUT= 0.35V

-40

-15

10

35

60

85

0.01

1

100

10000

Temperature (°C)

Frequency (MHz)

FIGURE 2-8:

Data Switch Bandwidth vs.

FIGURE 2-11:

R_{DCP_RES}Resistance vs.

Frequency.

Temperature.

2.5

2.0

1.5

1.0

0.5

1

0.95

0.9

0.85

0.8

0.75

0.7

0.65

0.6

V_S= V_DD= 5V

Turn off time

Turn on time

D_POUT= D_MOUT= 0.4V

0.55

0.5

0.0

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

FIGURE 2-9:

Data Switch On Resistance

FIGURE 2-12:

Power Switch On/Off Time

vs. Temperature.

DS20005346B-page 18

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

Note: Unless otherwise indicated, V = V = 5V, T = +27°C

.

DD

S

A

6

5.99

5.98

5.97

5.96

5.95

5.94

5.93

5.92

5.91

5.9

0

-1

-2

-3

-4

-5

-6

-7

-8

V_S= V_DD= 5V

V_DD= 5V

I_LIM= 3.0 A max. (2.85A typical)

Note: Specification is 0% maximum

and -10% minimum

-9

-10

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

FIGURE 2-13:

V_SOvervoltage Threshold

FIGURE 2-16:

Trip Current Limit Operation

vs. Temperature.

3

2.9

2.8

2.7

2.6

5

4

3

2

1

0

V_DD= 5V

V_S= V_DD= 5V

Threshold

2.5

2.4

2.3

2.2

2.1

2

-1

-2

-3

-4

-5

Hysteresis

-40

-15

10

35

60

85

0

0.5

1

1.5

2

2.5

3

Current (A)

Temperature (°C)

FIGURE 2-14:

V_SUndervoltage Threshold

FIGURE 2-17:

I_BUSMeasurement

vs. Temperature.

Accuracy.

800

700

600

500

400

300

200

100

5.5

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

I_DD+ I_S

I_S

I_DD

V_S= V_DD= 5V

S0 = '1'

PWR_EN disabled

V_S= V_DD= 5V

0

500 1000 1500 2000 2500 3000 3500 4000

Current (µA)

-40

-15

10

35

60

85

Temperature (°C)

FIGURE 2-15:

Detect State V_BUSvs. I_BUS

.

FIGURE 2-18:

Active State Current vs.

Temperature.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 19

UCS1003-1/2/3

Note: Unless otherwise indicated, V = V = 5V, T = +27°C

.

DD

S

A

250

200

150

100

50

40%

35%

30%

25%

20%

15%

10%

5%

V_S= V_DD= 5V

I_DD+ I_S

I_DD

I_S

0%

0

-40

-15

10

35

60

85

Temperature (°C)

V_BUSCurrent (A)

FIGURE 2-19:

Detect State Current vs.

FIGURE 2-22:

I_LIM2Trip Current

Temperature.

Distribution.

30%

25%

20%

15%

10%

5%

10

V_S= V_DD= 5V

9

8

7

6

5

4

3

2

1

0

I_DD+ I_S

I_DD

I_S

0%

-40

-15

10

35

60

85

V_BUSCurrent (A)

Temperature (°C)

FIGURE 2-20:

Sleep State Current vs.

FIGURE 2-23:

I_LIM3Trip Current

Temperature.

Distribution.

30%

25%

20%

15%

10%

5%

35%

30%

25%

20%

15%

10%

5%

0%

V_BUSCurrent (A)

FIGURE 2-21:

I_LIM1Trip Current

FIGURE 2-24:

I_LIM4Trip Current

Distribution.

DS20005346B-page 20

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

Note: Unless otherwise indicated, V = V = 5V, T = +27°C

.

DD

S

A

30%

25%

20%

15%

10%

5%

40%

35%

30%

25%

20%

15%

10%

5%

0%

V_BUSCurrent (A)

FIGURE 2-25:

I_LIM5Trip Current

FIGURE 2-27:

I_LIM7Trip Current

Distribution.

30%

25%

20%

15%

10%

5%

30%

25%

20%

15%

10%

5%

0%

V_BUSCurrent (A)

FIGURE 2-26:

I_LIM6Trip Current

FIGURE 2-28:

I_LIM8Trip Current

Distribution.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 21

UCS1003-1/2/3

NOTES:

DS20005346B-page 22

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

TABLE 3-2:

Pin Type

Power

PIN TYPES DESCRIPTION

Description

This pin is used to supply power or

ground to the device.

Hi-Power This pin is a high-current pin.

AIO

Analog Input/Output – This pin is used

as an I/O for analog signals.

DI

Digital Input – This pin is used as a

digital input. This pin will be glitch-free.

DIOD

Open-Drain Digital Input/Output – This

pin is bidirectional. It is open-drain and

requires a pull-up resistor. This pin will

be glitch-free.

OD

EP

Open-Drain Digital Output – Used as a

digital output. It is open-drain and

requires a pull-up resistor. This pin will

be glitch-free.

Exposed Thermal Pad.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 25

UCS1003-1/2/3

NOTES:

DS20005346B-page 26

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

4.0

TERMS AND ABBREVIATIONS

Note:

In the case of UCS1003-1, the M1, M2, PWR_EN and EM_EN pins each have Configuration bits

(<pin name>_SET in Section 10.4.3 “Switch Configuration Register”) that may be used to perform the

2

same function as the external pin state. These bits are accessed via the SMBus/I C and are OR’d with the

respective pin. This OR’d combination of pin state and register bit is referenced as the <pin name> control.

TABLE 4-1:

TERMS AND ABBREVIATIONS

Term/Abbreviation

Description

Active Mode

Active Power State Operation mode: Data Pass-Through, BC1.2 SDP, BC1.2 CDP, BC1.2

DCP or Dedicated Charger Emulation Cycle mode.

Attach Detection

An Attach Detection event occurs when the current drawn by a portable device is greater than

I

for longer than t

.

DET_QUAL

Attachment

CC

The physical insertion of a portable device into a USB port that UCS1003-1/2/3 is controlling.

Constant Current.

CDM

Charged Device Model. JEDEC model for characterizing susceptibility of a device to damage

from ESD.

CDP or USB-IF

BC1.2 CDP

Charging Downstream Port. The combination of the UCS1003-1/2/3 CDP handshake and an

active standard USB host comprises a CDP. This enables a BC1.2 compliant portable device

to simultaneously draw current up to 1.5A while data communication is active. The USB

high-speed data switch is closed in this mode.

Charge Enable

When a charger emulation profile has been accepted by a portable device and charging

commences.

Charger Emulation

Profile

Representation of a charger comprised of D

a defined set of signatures or handshaking protocols.

, D

and V

signaling, which make up

POUT MOUT

BUS

Connection

USB-IF term which refers to establishing active USB communications between a USB host

and a USB device.

Current-Limiting

Mode

Determines the action that is performed when the I

opens the port power switch. Constant Current (variable slope) allows V

the portable device.

current reaches the I

threshold. Trip

to be dropped by

BUS

LIM

BUS

DCE

Dedicated Charger Emulation. Charger emulation in which the UCS1003-1/2/3 can deliver

power only (by default). No active USB data communication is possible when charging in this

mode (by default).

DCP or USB-IF

BC1.2 DCP

Dedicated Charging Port. This functions as a dedicated charger for a BC1.2 portable device.

This allows the portable device to draw currents up to 1.5A with Constant-Current Limiting

(and beyond 1.5A with trip current limiting). No USB communications are possible (by default).

DC

Dedicated Charger. A charger which inherently does not have USB communications, such as

an A/C wall adapter.

Disconnection

USB-IF term which refers to the loss of active USB communications between a USB host and

a USB device.

Dynamic Thermal

Management

The UCS1003-1/2/3 automatically adjusts port power switch limits and modes to lower internal

power dissipation when the thermal regulation temperature value is approached.

Enumeration

Handshake

A USB-specific term indicating that a host is detecting and identifying USB devices.

Application of a charger emulation profile that requires a response. Two-way communication

between the UCS1003-1/2/3 and the portable device.

HBM

HSW

Human Body Model.

High-Speed Switch.

I

Current Limiter mode boundary.

BUS_R2MIN

 2014-2015 Microchip Technology Inc.

DS20005346B-page 27

UCS1003-1/2/3

TABLE 4-1:

TERMS AND ABBREVIATIONS (CONTINUED)

Term/Abbreviation

Description

I

The I

current threshold used in current limiting. In Trip mode, when I

is reached, the

LIM

BUS

port power switch is opened. In Constant-Current mode, when the current exceeds I , oper-

LIM

ation continues at a reduced voltage and increased current; if V

voltage drops below

BUS

V

, the port power switch is opened.

BUS_MIN

Legacy

USB devices that require non-BC1.2 signatures to be applied on the D

to enable charging.

and D

pins

POUT

MOUT

OCL

Overcurrent Limit.

POR

Power-on Reset.

Portable Device

Power Thief

USB device attached to the USB port.

A USB device that does not follow the handshaking conventions of a BC1.2 device or legacy

devices and draws current immediately upon receiving power (i.e., a USB book light, portable

fan, etc).

Removal Detection

A Removal Detection event occurs when the current load on the V

pin drops to less than

BUS

I

for longer than t

.

REM_QUAL

Removal

The physical removal of a portable device from a USB port that the UCS1003-1/2/3 is controlling.

Response

An action, usually in response to a stimulus, in charger emulation performed by the

UCS1003-1/2/3 device via the USB data lines.

SDP or USB-IF SDP Standard Downstream Port. The combination of the UCS1003-1/2/3 High-Speed Switch being

closed with an upstream USB host present comprises a BC1.2 SDP. This enables a BC1.2

compliant portable device to simultaneously draw current up to 0.5A while data communication

is active.

Signature

Application of a charger emulation profile without waiting for a response. One-way

communication from the UCS1003-1/2/3 to the portable device.

Stand-Alone Mode

Indicates that the communication protocol is not active and all communications between the

UCS1003-1/2/3 and a controller are done via the external pins only (M1, M2, EM_EN,

PWR_EN, S0 and LATCH as inputs, and ALERT# and A_DET# as outputs).

Stimulus

An event in charger emulation detected by the UCS1003-1/2/3 device via the USB data lines.

DS20005346B-page 28

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

The UCS1003-1 also provides current monitoring to allow

intelligent management of system power and charge

rationing for controlled delivery of current, regardless of

the host power state. This is especially important for

battery-operated applications that need to provide power

without excessively draining the battery or that require

power allocation depending on application activities.

5.0

GENERAL DESCRIPTION

The UCS1003-1/2/3 family of devices provides a single

USB port power switch for precise control of up to 3.0A

continuous current with Overcurrent Limit (OCL),

dynamic thermal management, latch or auto-recovery

Fault handling, selectable active-high or active-low

enable, Undervoltage and Overvoltage Lockout, and

back-voltage protection.

Figure 5-1 shows a UCS1003-1 full-featured system

configuration in which the UCS1003-1 provides a port

power switch and low-power Attach Detection with

wake-up signaling (wake on USB). The current limit is

established at power-up. It can be lowered, if required,

Split supply support for V

low power in system standby states.

and V is an option for

DD

BUS

In addition to power switching and current limiting, the

UCS1003-1/2/3 provides charger emulation profiles to

charge a wide variety of portable devices, including

USB-IF BC1.2 (CDP or DCP modes), YD/T-1591 (2009),

12W charging, most Apple, Samsung and RIM portable

devices, and many others (refer to Section 9.0 “Active

State” for more information on preloaded charger

emulation profiles). The UCS1003-1 has a custom

programmable charger emulation profile for portable

device support for fully host controlled charger emulation.

2

after power-up via the SMBus/I C. This configuration

also provides configurable USB data line charger emu-

lation, programmable current limiting (as determined

by the accepted charger emulation profile), active

current monitoring and port charge rationing.

D_POUT

D_MOUT

V_BUS1

V_BUS2

D_PIN

USB Host

D_MIN

V_S1

V_S2

5V Host

C_IN

Device

C_BUS

5V

UCS1003-1

V_DD

EM_EN

M1

3V-5.5V

M2

PWR_EN

SMDATA

A_DET#

ALERT#

SMCLK

V_DD

COMM_SEL/I_LIM

SEL

GND

FIGURE 5-1:

UCS1003-1 System Configuration (with Charger Emulation, SMBus Control and

USB Host).

 2014-2015 Microchip Technology Inc.

DS20005346B-page 29

UCS1003-1/2/3

Figure 5-2 shows a system configuration in which the

UCS1003-1/2/3 devices provide a USB data switch,

port power switch, low-power Attach Detection and por-

table device Attach/Removal Detection signaling. This

configuration does not include configurable data line

charger emulation, programmable current limiting or

current monitoring and rationing.

5V

V_DD

D_PIN

D_POUT

D_MOUT

V_BUS1

V_BUS2

USB Host

D_MIN

V_S1

V_S2

5V Host

Device

C_IN

C_BUS

UCS1003-X

EM_EN

3V-5.5V

M1

3V-5.5V

Enable

Detect

State

Latch

Upon

Fault

M2

PWR_EN

A_DET#/CHRG#

LATCH

S0

ALERT#

V_DD

Disable

Detect

State

Auto-Recovery

Upon Fault

SEL

COMM_SEL/I_LIM

GND

FIGURE 5-2:

UCS1003-1/2/3 System Configuration (Charger Emulation, No SMBus and with

USB Host).

DS20005346B-page 30

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

Figure 5-3 shows a system configuration in which the

UCS1003-1/2/3 devices provide a port power switch,

low-power Attach Detection and portable device

Attachment Detection signaling. This configuration is

useful for applications that already provide USB BC1.2

and/or legacy data line handshaking on the USB data

lines, but still require port power switching and current

limiting.

D_PIN

D_MIN

D_POUT

D_MOUT

V_BUS1

V_BUS2

USB Host

(DP, DM)

5V Host

C_IN

V_S1

V_S2

Device

C_BUS

EM_EN

UCS1003-X

3V-5.5V

Latch

M1

Enable

Detect

State

M2

Upon

Fault

PWR_EN

SEL

3V-5.5V

LATCH

S0

V_DD

COMM_SEL/I_LIM

Disable

Detect

State

5V

Auto-Recovery

Upon Fault

A_DET#/CHRG#

V_DD

GND

ALERT#

FIGURE 5-3:

UCS1003-1/2/3 System Configuration (No SMBus, No Charger Emulation).

 2014-2015 Microchip Technology Inc.

DS20005346B-page 31

UCS1003-1/2/3

Figure 5-4 shows a system configuration in which the

UCS1003-1/2/3 devices provide a port power switch,

low-power Attach Detection, charger emulation (with

no USB host) and portable device Attachment

Detection signaling. This configuration is useful for

wall adapter-type applications.

15 k

D_PIN

D_POUT

D_MOUT

V_BUS1

V_BUS2

15 k

D_MIN

5V

V_S1

V_S2

Device

C_IN

C_BUS

EM_EN

M1

3V-5.5V

Latch

UCS1003-X

M2

Enable

Detect

State

Upon

Fault

PWR_EN

SEL

3V-5.5V

LATCH

S0

V_DD

COMM_SEL/I_LIM

Disable

Detect

State

5V

Auto-Recovery

Upon Fault

A_DET#/CHRG#

V_DD

GND

ALERT#

FIGURE 5-4:

UCS1003-1/2/3 System Configuration (No SMBus, No USB Host and with

Charger Emulation).

DS20005346B-page 32

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

5.1

UCS1003-1/2/3 Power States

The UCS1003-1/2/3 has the following power states

listed in Table 5-1.

TABLE 5-1:

State

POWER STATES DESCRIPTION

Description

Off

This power state is entered when the voltage at the V pin voltage is < V

. In this state, the device

DD_TH

DD

is considered “off”. The UCS1003-1/2/3 devices will not retain their digital states. UCS1003-1 will not

2

retain register contents, nor respond to SMBus/I C communications. The port power switch, bypass

switch and the high-speed data switches will be off. See Section 5.1.1 “OFF State Operation”.

Sleep This is the lowest power state available. While in this state, the UCS1003-1/2/3 devices will retain digital

2

functionality and respond to changes in emulation controls. UCS1003-1 will wake to respond to SMBus/I C

communications. The high-speed switch and all other functionality will be disabled. See Section 5.1.2

“Sleep State Operation”.

Detect This is a low-current power state. In this state, the device is actively looking for a portable device to be

attached. The high-speed switch is disabled by default. While in this state, the UCS1003-1 will retain the

2

configuration and charge rationing data, but it will not monitor the bus current. SMBus/I C

communications will be fully functional. See Section 5.1.3 “Detect State Operation”.

Error

This power state is entered when a Fault condition exists. See Section 5.1.5 “Error State Operation”.

Active This power state provides full functionality. While in this state, operations include activation of the port

power switch, USB data line handshaking/charger emulation, current limiting and charge rationing. See

Section 5.1.4 “Active State Operation”.

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DS20005346B-page 33

UCS1003-1/2/3

Table 5-2 shows the settings for the various power

states, except for the OFF and Error states. If

V

< V

, the UCS1003-1/2/3 devices are in the

DD

DD_TH

OFF state. To determine the mode of operation in the

Active state, see Table 9-1.

Note:

Using configurations not listed in

Table 5-2 are not recommended and may

produce undesirable results.

TABLE 5-2:

Power State

Sleep

POWER STATE CONTROL SETTINGS

M1, M2,

Portable

Device

Attached

V

PWR_EN

S0

Behavior

S

EM_EN

N/A

Disabled

0

Not set to Data

Pass-Through

mode (Note 1)

N/A

• All switches disabled

• V

will be near ground potential

BUS

• The UCS1003-1 wakes to respond

to SMBus communications

N/A

Enabled

Disabled

Enabled

0

1

All = 0b

N/A

Detect

(seeSection 8.0

“Detect State”)

N/A

• High-speed switch disabled (by

default)

< V

All  0b

S_UVLO

• Port power switch disabled

• Host-controlled transition to

Active state (see Section 5.1.3.2

“Host-Controlled Transition

from Detect to Active”)

> V

Enabled

1

All  0b

No

• High-speed switch disabled (by

default)

S_UVLO

• Automatic transition to Active

state when conditions met (see

Section 5.1.3.1 “Automatic

Transition from Detect to

Active”)

Active

(seeSection 9.0

“Active State”)

> V

Enabled

0

1

All  0b

N/A

Yes

• High-speed switch enabled/

disabled based on mode

S_UVLO

• Port power switch is on at all times

• Attach and Removal Detection

disabled (Note 2)

• Port power switch is on

S_UVLO

• Removal Detection enabled

Note 1: In order to transition from Active State Data Pass-Through mode into Sleep with these settings, change the

M1, M2 and EM_EN pins before changing the PWR_EN pin. See Section 9.4 “Data Pass-Through (No

Charger Emulation)”.

2: If S0 = 0and a portable device is not attached in DCE Cycle mode, the UCS1003-1/2/3 devices will be

cycling through charger emulation profiles (by default). There is no assurance which charger emulation

profile will be applied first when a portable device attaches.

DS20005346B-page 34

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

The first data byte read from the UCS1003-1, when in

the Sleep state, will wake the device; however, the data

to be read will return all ‘0’s and should be considered

invalid. This is a “dummy” read byte meant to wake the

UCS1003-1. Subsequent read or write bytes will be

accepted normally. After the dummy read, the

UCS1003-1 will be in a higher power state (see

Figure 5-6). The device will return to Sleep after the last

communication or if no further communication has

occurred.

5.1.1

OFF STATE OPERATION

The device is in the OFF state if V

is less than

DD

V

. When the UCS1003-1/2/3 devices are in the

DD_TH

OFF state, it does nothing and all circuitry is disabled.

In the case of UCS1003-1, the digital register values

are not stored and the device will not respond to

SMBus commands.

5.1.2

SLEEP STATE OPERATION

When the UCS1003-1/2/3 devices are in the Sleep

state, the device is in its lowest power state. The high-

speed switch, bypass switch and the port power switch

are disabled. The Attach and Removal Detection

Figure 5-5 shows the timing diagrams for waking the

UCS1003-1/2/3 family via external pins. Figure 5-6

shows the timing for waking the UCS1003-1 device via

SMBus.

feature is disabled. V

will be near ground potential.

BUS

The ALERT# pin is not asserted. If asserted prior to

entering the Sleep state, the ALERT# pin will be

released. The A_DET# pin is released. In the case of

UCS1003-1, SMBus activity is limited to single byte

read or write.

Wake with M1 or M2 to Active State Data Pass-Through Mode

(PWR_EN enabled, S0 = 0, EM_EN = 0, V_S> V_{S_UVLO}

)

M1 or M2

t_{PIN_WAKE}

Port Power Switch Closed

(Active state)

Wake with S0

(V_S> V_{S_UVLO}, M1 & M2 & EM_EN not all ‘0’s and not set to data pass-through)

S0

t_{PIN_WAKE}

Bypass Switch Closed

(Detect state)

FIGURE 5-5:

Wake Timing via External Pins.

SMBus Read

Dummy Read Returns Invalid Data and Places Device in

Read Returns Valid Data

Temporary Active State

invalid

data

0101_1110 0001_0000

0101_1111

0101_1110

0001_0000

0101_1111

valid data

A N P

S

A

A S

A

N P

S

A

A S

t_{SMB_WAKE}

t_{IDLE_SLEEP}

Power State

Temporary Active State

Sleep

(not all functionality available)

FIGURE 5-6:

Wake via SMBus Read with S0 = 0.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 35

UCS1003-1/2/3

5.1.3

DETECT STATE OPERATION

5.1.3.3

State Change from Detect to Active

When the UCS1003-1/2/3 is in the Detect state, the

port power switch will be disabled. The high-speed

When conditions cause the UCS1003-1/2/3 to

transition from the Detect state to the Active state, the

following occurs:

switch is also disabled by default. The V

output will

BUS

be connected to the V

bypass switch (see Section 8.0 “Detect State”).

voltage by a secondary

DD

1. The Attach Detection feature will be disabled;

the Removal Detection feature remains enabled

unless S0 is changed to ‘0’.

There is one non-recommended configuration which

places the UCS1003-1/2/3 in the Detect state, but V

2. The bypass switch will be turned off.

BUS

will not be discharged and

a portable device

3. The discharge switch will be turned on briefly for

attachment will not be detected. For the recommended

configurations, see Table 5-2.

t

.

DISCHARGE

4. The port power switch will be turned on.

There are two methods for transitioning from the Detect

state to the Active state: automatic and host-controlled.

5.1.4 ACTIVE STATE OPERATION

Every time that the UCS1003-1/2/3 enters the Active

state and the port power switch is closed, it will enter

the mode as instructed by the host controller (see

Section 9.0 “Active State”). The UCS1003-1/2/3

cannot be in the Active state (and therefore, the port

power switch cannot be turned on) if any of the

following conditions exist:

5.1.3.1

Automatic Transition

from Detect to Active

For the Detect state, set S0 to ‘1’, enable PWR_EN, set

the EM_EN, M1 and M2 controls to the desired Active

mode (Table 9-1), and supply V > V

portable device is attached and an Attach Detection

event occurs, the UCS1003-1/2/3 will automatically

transition to the Active state and operate according to

the selected Active mode.

. When a

S

S_UVLO

• V < V

S

S_UVLO

• PWR_EN is disabled

• M1, M2 and EM_EN are all set to ‘0’

• S0 is set to ‘1’ and an Attach Detection event has

not occurred

5.1.3.2

Host-Controlled Transition from

Detect to Active

For the Detect state, set S0 to ‘1’, set the EM_EN, M1

and M2 controls to the desired Active mode (Table 9-1),

and configure one of the following:

5.1.5

ERROR STATE OPERATION

The UCS1003-1/2/3 will enter the Error state from the

Active state when any of the following events are

detected:

• Disable PWR_EN and supply V

S

OR

• The maximum allowable internal die temperature

• Enable PWR_EN and don’t supply V ; when a

(T

) has been exceeded (see Section 7.2.1.2

S

TSD

portable device is attached and an Attach

Detection event occurs, the host must respond to

transition to the Active state.

“Thermal Shutdown”).

• An overcurrent condition has been detected (see

Section 7.1.1 “Current Limit Setting”).

Depending on the control settings in the Detect state,

this could entail:

• An undervoltage condition on V

detected (see Section 5.2.5 “Undervoltage

has been

BUS

Lockout on V ”).

S

• Enabling PWR_EN

• A backdrive condition has been detected (see

Section 5.2.3 “Back-Voltage Detection”).

OR

• Supplying V above the threshold.

S

• A discharge error has been detected (see

Section 7.3 “V

Discharge”).

BUS

Note:

If S0 is ‘1’, PWR_EN is enabled and V is

not present, the A_DET# pin will cycle if

S

• An overvoltage condition on the V pins.

S

The UCS1003-1/2/3 will enter the Error state from the

Detect state when a backdrive condition has been

detected or when the maximum allowable internal die

temperature has been exceeded.

the current draw exceeds the current

capacity of the bypass switch.

The UCS1003-1/2/3 will enter the Error state from the

Sleep state when a backdrive condition has been

detected.

DS20005346B-page 36

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

When the UCS1003-1/2/3 enters the Error state, the

port power switch, V bypass switch and the high-

5.2.3

BACK-VOLTAGE DETECTION

BUS

Whenever the following conditions are true, the port

power switch will be disabled, the V bypass switch

will be disabled, the high-speed data switch will be dis-

abled and a back-voltage event will be flagged. This will

cause the UCS1003-1/2/3 to enter the Error power

state (see Section 5.1.5 “Error State Operation”).

speed switch are turned off, and the ALERT# pin is

asserted (by default). They will remain off while in this

power state. The UCS1003-1/2/3 will leave this state as

determined by the Fault handling selection (see

Section 7.5 “Fault Handling Mechanism”).

BUS

When using the latch Fault handler and the user has re-

activated the device by clearing the ERR bit (for

UCS1003-1 only, see Section 10.3 “Status Registers”)

or toggling the PWR_EN control, the UCS1003-1/2/3 will

check that all of the error conditions have been removed.

• The V

voltage exceeds the V voltage by

S

and the port power switch is closed. The

BUS

V

BV_TH

port power switch will be opened immediately. If

the condition lasts for longer than t , then the

UCS1003-1/2/3 will enter the Error state. Other-

wise, the port power switch will be turned on as

soon as the condition is removed.

MASK

If using the auto-recovery Fault handler, after the t

CYCLE

time period, the UCS1003-1/2/3 will check that all of the

error conditions have been removed.

• The V

voltage exceeds the V voltage by

DD

BUS

If all of the error conditions have been removed, the

UCS1003-1/2/3 will return to the Active state or Detect

state, as applicable. Returning to the Active state will

cause the UCS1003-1/2/3 to restart the selected mode

(see Section 9.2 “Active Mode Selection”).

V

and the V

bypass switch is closed.

BV_TH

BUS

The bypass switch will be opened immediately. If

the condition lasts for longer than t , then the

UCS1003-1/2/3 will enter the Error state. Other-

wise, the bypass switch will be turned on as soon

as the condition is removed.

MASK

If the device is in the Error state and a Removal

Detection event occurs, it will check the error

conditions and then return to the power state defined

by the PWR_EN, M1, M2, EM_EN and S0 controls.

5.2.4

BACKDRIVE CURRENT

PROTECTION

If a self-powered portable device is attached, it may

5.2

Supply Voltages

drive the V

port to its power supply voltage level;

BUS

however, the UCS1003-1/2/3 family is designed such

that leakage current from the V pins to the V or

5.2.1

V_DDSUPPLY VOLTAGE

BUS

DD

V

pins shall not exceed I

(if the V

voltage is

S

BD_1

DD

The UCS1003-1/2/3 family requires 4.5V to 5.5V to be

present on the V pin for core device functionality.

zero), or I

(if the V voltage exceeds V

).

BD_2

DD

DD_TH

DD

Core device functionality consists of maintaining

register states, wake-up upon SMBus/I C query and

5.2.5

UNDERVOLTAGE LOCKOUT ON V_S

2

Attach Detection.

The UCS1003-1/2/3 family requires a minimum voltage

(V

state.

) be present on the V pin for the Active power

S_UVLO

S

5.2.2

V_SSOURCE VOLTAGE

V can be a separate supply and can be greater than

S

5.2.6

OVERVOLTAGE DETECTION AND

LOCKOUT ON V_S

V

to accommodate high-current applications in

DD

which current path resistances result in unacceptable

voltage drops that may prevent optimal charging of

some portable devices.

The UCS1003-1/2/3 port power switch will be disabled

if the voltage on the V pin exceeds a voltage (V

)

S_OV

S

for longer than the specified time (t

). This will

MASK

cause the device to enter the Error state.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 37

UCS1003-1/2/3

5.3.4

PWR_EN INPUT

5.3

Discrete Input Pins

The PWR_EN control enables the port power switch to

be turned on if conditions are met and affects the power

state (see Table 5-2). The port power switch cannot be

closed if PWR_EN is disabled. However, if PWR_EN is

enabled, the port power switch is not necessarily

closed (see Section 5.1.4 “Active State Operation”).

Polarity is controlled by the SEL pin. In the case of the

UCS1003-1 configured in SMBus mode, the PWR_EN

pin state will be ignored by the UCS1003-1 if the

PIN_IGN Configuration bit is set (see Section 10.4.3

“Switch Configuration Register”); otherwise, the

PWR_ENS Configuration bit (see Section 10.4.3

“Switch Configuration Register”) is checked along

with the pin.

Note:

If it is necessary to connect any of the

control pins, except the COMM_SEL/I

LIM

or SEL pins, via a resistor to V or GND,

DD

the resistor value should not exceed

100 k in order to meet the V and V

IH

IL

specifications.

5.3.1

COMM_SEL/I_LIMINPUT

The COMM_SEL/I

settings and the Communications mode, as shown in

Table 11-1.

input determines the initial I

LIM

5.3.2

SEL INPUT

The SEL pin selects the polarity of the PWR_EN

control. If the SEL pin is high, the PWR_EN control is

active-high enable. If the SEL pin is low, the PWR_EN

control is active-low enable. In addition, if the

UCS1003-1 is not configured to operate in Stand-Alone

mode, the SEL pin determines the SMBus address.

See Table 11-2. The SEL pin state is latched upon

device power-up and further changes will have no

effect.

5.3.5

LATCH INPUT

The latch input control determines the behavior of the

Fault handling mechanism (see Section 7.5 “Fault

Handling Mechanism”).

When the UCS1003-1 is configured to operate in

Stand-Alone mode (see Section 11.3 “Stand-Alone

Operating Mode”), the latch control is available

exclusively via the LATCH pin (see Table 11-10). When

the UCS1003-1 is configured to operate in SMBus

mode, the latch control is available exclusively via the

LATCHS Configuration bit (see Section 10.4.3

“Switch Configuration Register”).

5.3.3

M1, M2 AND EM_EN INPUTS

The M1, M2 and EM_EN input controls determine the

Active mode and affect the power state (see Table 5-2

and Table 9-1). When these controls are all set to ‘0’

and PWR_EN is enabled, the UCS1003-1/2/3 Attach

and Removal Detection feature is disabled. In case of

the UCS1003-1 configured in SMBus mode, the M1,

M2 and EM_EN pin states will be ignored by the

UCS1003-1 if the PIN_IGN Configuration bit is set (see

Section 10.4.3 “Switch Configuration Register”);

otherwise, the M1_SET, M2_SET and EM_EN_SET

Configuration bits (see Section 10.4.3 “Switch

Configuration Register”) are checked along with the

pins.

5.3.6

S0 INPUT

The S0 control enables the Attach and Removal

Detection feature, and affects the power state (see

Table 5-2). When S0 is set to ‘1’, an Attach Detection

event must occur before the port power switch can be

turned on. When S0 is set to ‘0’, the Attach and

Removal Detection feature is not enabled.

When the UCS1003-1 is configured to operate in

SMBus mode (see Section 11.3 “Stand-Alone Oper-

ating Mode”), the S0 control is available exclusively

via the S0_SET Configuration bit (see Section 10.4.3

“Switch Configuration Register”). Otherwise, the S0

control is available exclusively via the S0 pin since the

SMBus protocol will be disabled.

DS20005346B-page 38

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UCS1003-1/2/3

The CHRG# pin (UCS1003-2) provides an active-low,

open-drain output indication that charging of an

attached device is active. It will remain asserted until

this condition no longer exists and then will be

automatically released.

5.4

Discrete Output Pins

5.4.1

ALERT# AND A_DET#

OUTPUT PINS

The ALERT# pin is an active-low, open-drain interrupt

to the host controller. The ALERT# pin is asserted (by

default – see ALERT_MASK in Section 10.4.1 “Gen-

eral Configuration Register”) when an error occurs

(see Register 10-3). In the case of UCS1003-1, the

ALERT# pin can also be asserted when the LOW_CUR

(portable device is pulling less current and may be

finished charging) or TREG (thermal regulation

temperature exceeded) bits are set and linked. Also,

when charge rationing is enabled in UCS1003-1, the

ALERT# pin is asserted by default when the current

rationing threshold is reached (as determined by

RATION_BEH<1:0> – see Table 7-2). The ALERT# pin

is released when all error conditions that may assert

the ALERT# pin (such as an error condition, charge

rationing, and TREG and LOW_CHG if linked) have

been removed or reset as necessary.

5.4.2

INTERRUPT BLANKING

The ALERT#, A_DET# (UCS1003-1 and UCS1003-3)

and CHRG# (UCS1003-2) pins will not be asserted for

a specified time (up to t

) after power-up.

BLANK

Additionally, an error condition (except for the thermal

shutdown) must be present for longer than a specified

time (t

) before the ALERT# pin is asserted.

MASK

The A_DET# pin (UCS1003-1, UCS1003-3) provides

an active-low, open-drain output indication that a valid

Attach Detection event has occurred. It will remain

asserted until the UCS1003-1 or UCS1003-3 is placed

into the Sleep state, or a Removal Detection event

occurs. For wake on USB, the A_DET# pin assertion

can be utilized by the system. If the S0 control is ‘0’ and

the UCS1003-1 or UCS1003-3 is in the Active state,

the A_DET# pin will be asserted regardless if a

portable device is attached or not. If S0 is ‘1’, PWR_EN

is enabled and V is not present; the A_DET# pin will

S

cycle if the current draw exceeds the current capacity

of the bypass switch.

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DS20005346B-page 39

UCS1003-1/2/3

NOTES:

DS20005346B-page 40

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UCS1003-1/2/3

6.0

USB HIGH-SPEED DATA

SWITCH

Note:

If the V voltage is less than V

high-speed data switch will be disabled

and opened.

, the

DD_TH

DD

The UCS1003-1/2/3 family contains a series USB 2.0

compliant, high-speed switch between the D

and

pins.

6.1

USB-IF High-Speed Compliance

D

pins, and between the D

and D

MIN

POUT

MOUT

This switch is designed for high-speed, low-latency

functionality to allow USB 2.0 full-speed and high-speed

communications with minimal interference.

The USB data switch will not significantly degrade the

signal integrity through the device D /D pins with

USB high-speed communications.

P

M

Nominally, the switch is closed in the Active state,

allowing uninterrupted USB communications between

the upstream host and the portable device. The switch

is opened when:

• The UCS1003-1/2/3 family is actively emulating,

using any of the charger emulation profiles

except CDP (by default – see Section 10.4.5

“High-Speed Switch Configuration Register”)

• The UCS1003-1/2/3 family is operating as a

dedicated charger unless the HSW_DCE

Configuration bit is set (see Section 10.4.5

“High-Speed Switch Configuration Register”)

• The UCS1003-1/2/3 family is in the Detect state

(by default) or in the Sleep state

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DS20005346B-page 41

UCS1003-1/2/3

NOTES:

DS20005346B-page 42

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UCS1003-1/2/3

7.1.2

SHORT-CIRCUIT OUTPUT

CURRENT LIMITING

7.0

USB PORT POWER SWITCH

To ensure compliance to various charging specifica-

tions, the UCS1003-1/2/3 family contains a USB port

power switch that supports two Current-Limiting modes:

Trip and Constant-Current (variable slope) modes. The

Short-circuit current limiting occurs when the output

current is above the selectable current limit (I ). This

event will be detected and the current will immediately

be limited (within t time). If the condition

remains, the port power switch will flag an error condi-

tion and enter the Error state (see Section 5.1.5 “Error

State Operation”).

LIMx

SHORT_LIM

Current-Limit mode (I ) is pin-selectable (and may be

LIM

updated via the register set). The switch also includes

soft-start circuitry and a separate short-circuit current

limit.

The port power switch is on in the Active state (except

7.1.3

SOFT START

when V

is discharging).

BUS

When the PWR_EN control changes states to enable

the port power switch, or an Attach Detection event

occurs in the Detect power state and the PWR_EN

control is already enabled, the UCS1003-1/2/3 family

7.1

Current Limiting

7.1.1

CURRENT LIMIT SETTING

invokes a soft-start routine for the duration of the V

BUS

The UCS1003-1/2/3 hardware set current limit (I

)

rise time (t

). This soft-start routine will limit

LIM

R_BUS

can be one of eight values (see Table 11-1, which

applies to UCS1003-1, and Table 7-1, which applies to

UCS1003-2 and UCS1003-3). This resistor value is

read once upon the UCS1003-1/2/3 devices’ power-up.

current flow from V into V

circuitry will prevent current spikes due to a step in the

portable device current draw.

while it is active. This

S

BUS

In the case when a portable device is attached while the

PWR_EN pin is already enabled, if the bus current

TABLE 7-1:

UCS1003-2 AND UCS1003-3

_LIMSELECTION^(1,2)

exceeds I , the UCS1003-1/2/3 current limiter will

LIM

I

respond within a specified time (t

ate normally at this point. The C

the extra current, if any, as required by the load change.

) and will oper-

SHORT_LIM

capacitor will deliver

BUS

I

Resistor ±5% Setting

I

LIM

47 k Pull-Down

56 k Pull-Down

68 k Pull-Down

82 k Pull-Down

570 mA

7.1.4 CURRENT-LIMITING MODES

1000 mA

1130 mA

1350 mA

1680 mA

2050 mA

2280 mA

2850 mA

The UCS1003-1/2/3 current limiting has two modes: Trip

and Constant-Current (variable slope) modes. Either

mode functions at all times when the port power switch

is closed. The Current-Limiting mode used depends on

the Active state mode (see Section 9.9 “Current Limit

Mode Associations”). When operating in the Detect

power state (see Section 5.1.3 “Detect State Opera-

100 k Pull-Down

120 k Pull-Down

150 k Pull-Down

V

DD

tion”), the current capacity at V

is limited to

BUS

(if a pull-up resistor is

used, its value must not

exceed 100 k)

(3000 mA maximum)

I

as described in Section 8.2 “V

Bypass

BUS_BYP,

BUS

Switch”.

Note 1: Unless otherwise indicated, the values

7.1.4.1

Trip Mode

specified above are the typical I

Table 1-2.

in

LIM

When using Trip Current-Limiting mode, the

UCS1003-1/2/3 USB port power switch functions as a

low-resistance switch and rapidly turns off if the current

limit is exceeded. While operating using Trip Current-

Limiting mode, the V

relatively constant (equal to the V voltage minus the

2:

I

pull-down resistors with values less

LIM

than 33 k, connected to UCS1003-2 or

UCS1003-3, will cause unexpected

behavior.

output voltage will be held

BUS

S

R

x I

current) for all current values up to the I

.

In the case of UCS1003-1, the current limit can be

changed via the SMBus/I C after power-up; however,

the programmed current limit cannot exceed the

hardware set current limit.

ON

BUS

LIM

2

If the current drawn by a portable device exceeds I

the following occurs:

,

LIM

1. The port power switch will be turned off (Trip

mode action).

At power-up, the hardware current limit (I ) and

LIM

Communication mode, in the case of UCS1003-1 (Stand-

2. The UCS1003-1/2/3 will enter the Error state

and assert the ALERT# pin.

2

Alone or SMBus/I C), are determined via the pull-down

resistor (or pull-up resistor if connected to V ) on the

DD

3. The Fault handling circuitry will then determine

subsequent actions.

COMM_SEL/I

pin, as shown in Table 11-1.

LIM

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DS20005346B-page 43

UCS1003-1/2/3

Trip Current-Limiting mode is used by default when the

UCS1003-1/2/3 family is in Data Pass-Through and

Dedicated Charger Emulation Cycle mode (except

when the BC1.2 DCP charger emulation profile is

accepted), and when there’s no handshake. This

method is also used when charger emulation is active.

Note 1: If the temperature exceeds the T

REG

threshold while operating in the DCE Cycle

mode, after a charger emulation profile has

been accepted, the profile will be removed.

The UCS1003-1/2/3 will not restart the

DCE Cycle mode until one of the control

inputs changes states to restart emulation.

Note:

To avoid cycling in Trip mode, set I

LIM

higher than the highest expected portable

device current draw.

2: The UCS1003-1/2/3 will not actively

discharge V

as a result of the

BUS

temperature exceeding T

; however,

REG

7.1.4.2

Constant-Current Limiting

(Variable Slope)

any load current provided by a portable

device or other load will cause V to be

BUS

discharged when the port power switch is

opened, possibly resulting in an attached

portable device resetting.

Constant-Current Limiting is used when a portable

device handshakes using the BC1.2 DCP charger

emulation profile and the current drawn is greater than

I

(and I

< 1.68A). It is also used in BC1.2 CDP

LIM

If the UCS1003-1/2/3 is operating using Constant-

mode and during the DCE Cycle when a charger

emulation profile is being applied, and the emulation

time-out is active.

Current Limiting (variable slope) and the I

setting

LIM

has been reduced to its minimum set point, and the

temperature is still above T , the UCS1003-1/2/3 will

REG

switch to operating using Trip Current-Limiting mode.

In CC mode, the port power switch allows the attached

This will be done by reducing the I

setting to

portable device to reduce V

output voltage to less

BUS_R2MIN

BUS

120 mA and restoring the I

setting to the value

than the input V voltage, while maintaining current

LIM

S

immediately below the programmed setting (e.g., if the

programmed I is 2.05A, the value will be set to

delivery. The V/I slope depends on the user set I

LIM

value. This slope is held constant for a given I

value.

LIM

1.68A). If the temperature continues to remain above

, the UCS1003-1/2/3 will continue this cycle (open

T

REG

7.2

Thermal Management and

Voltage Protection

the port power switch and reduce the I

one step).

setting by

LIM

If the UCS1003-1/2/3 internal temperature drops below

– T , the UCS1003-1/2/3 will take action

based on the following:

7.2.1

THERMAL MANAGEMENT

T

REG

REG_HYST

The UCS1003-1/2/3 family utilizes two-stage internal

thermal management. The first is named Dynamic

Thermal Management and the second is a Fixed

Thermal Shutdown.

1. If the Current Limit mode changed from CC

mode to Trip mode, then a timer is started. When

this timer expires, the UCS1003-1/2/3 will reset

the port power switch operation to its original

configuration, allowing it to operate using

Constant-Current Limiting (variable slope).

7.2.1.1

Dynamic Thermal Management

For the first stage (active in both Current-Limiting

modes), referred to as Dynamic Thermal Management,

the UCS1003-1/2/3 devices automatically adjust port

power switch limits and modes to lower power dissipa-

tion when the thermal regulation temperature value is

approached, as described below.

2. If the Current Limit mode did not change from CC

mode to Trip mode, or was already operating in

Trip mode, the UCS1003-1/2/3 will reset the port

power switch operation to its original configuration.

If the UCS1003-1/2/3 family is operating using Trip

If the internal temperature exceeds the T

port power switch is opened, the current limit (I ) is low-

value, the

REG

Current-Limiting mode and the I

setting has been

LIM

reduced to its minimum set point, and the temperature

is above T , the port power switch will be closed and

ered by one step and a timer is started (t

). When

DC_TEMP

this timer expires, the port power switch is closed and the

internal temperature is checked again. If it remains above

REG

the current limit will be held at its minimum setting until

the temperature drops below T – T

.

REG_HYST

the T

threshold, the UCS1003-1/2/3 devices repeat

REG

this cycle (open port power switch and reduce the I

LIM

7.2.1.2

Thermal Shutdown

setting by one step) until I

reaches its minimum value.

LIM

The second stage consists of a hardware implemented

thermal shutdown corresponding to the maximum

allowable internal die temperature (T

). If the internal

TSD

temperature exceeds this value, the port power switch

will immediately be turned off until the temperature is

below T

– T

.

TSD

TSD_HYST

DS20005346B-page 44

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UCS1003-1/2/3

7.3

V

Discharge

7.4

Battery Full (UCS1003-1 Only)

BUS

The UCS1003-1/2/3 will discharge V

internal 100 resistor when at least one of the following

conditions occurs:

through an

Delivery of bus current to a portable device can be

rationed by the UCS1003-1. When this functionality is

enabled, the host system must provide the UCS1003-1

with an accumulated charge maximum limit (in mAh).

The charge rationing functionality works only in the

Active power state. It continuously monitors the current

delivered, as well as the time elapsed since the mode

was activated (or since the data was updated). This

information is compiled to generate a charge rationing

number that is checked against the host limit.

BUS

• The PWR_EN control is disabled (triggered on the

inactive edge of the PWR_EN control).

• A portable device Removal Detection event is flagged.

• The V voltage drops below a specified threshold

S

(V

) that causes the port power switch to be

S_UVLO

disabled.

• When commanded into the Sleep power state via

the EM_EN, M1 and M2 controls.

Once the programmed current rationing limit has been

reached, the UCS1003-1 will take action as determined

by the RATION_BEH<1:0> bits, as described in

Table 7-2. Note that this does not cause the device to

enter the Error state.

• Before each charger emulation profile is applied.

• Upon recovery from the Error state.

• When commanded via the SMBus (for UCS1003-1

only, see Section 10.4 “Configuration Registers”)

in the Active state.

Once the charge rationing circuitry has reached the

programmed threshold, the UCS1003-1 will maintain

the desired behavior until charge rationing is reset.

Once charge rationing has been reset or disabled, the

UCS1003-1 will recover, as shown in Table 7-3.

• Any time that the port power switch is activated

after the V

whenever V

bypass switch has been on (i.e.,

voltage transitions from being

BUS

driven from V to being driven from V , such as

DD

S

going from Detect to Active power state).

• Any time that the V bypass switch is activated

BUS

after the port power switch has been on (i.e.,

going from Active to Detect power state).

When the V

discharge circuitry is activated, at the

BUS

end of the t

time, the UCS1003-1/2/3 will

DISCHARGE

confirm that V

was discharged. If the V

voltage

BUS

is not below the V

level, a discharge error will be

TEST

flagged (by setting the DISCH_ERR status bit in the

case of UCS1003-1) and the UCS1003-1/2/3 will enter

the Error state.

TABLE 7-2:

CHARGE RATIONING BEHAVIOR

RATION_BEH<1:0>

Behavior

Actions taken

Notes

1

0

1

Report

ALERT# pin asserted.

Report and 1. ALERT# pin asserted.

The HSW will not be affected.

Disconnect

(default)

All bus monitoring is still active.

2. Charger emulation

profile removed.

Changing the M1, M2, EM_EN, S0 and

PWR_EN controls will cause the device to

change power states as defined by the pin com-

binations; however, the port power switch will

remain off until the rationing circuitry is reset.

Furthermore, the bypass switch will not be

turned on if enabled via the S0 control.

3. Port power switch

disconnected.

1

0

1

Disconnect 1. Port power switch

The HSW will be disabled.

and

disconnected.

All V

and V monitoring will be stopped.

BUS S

Go to Sleep

Changing the M1, M2, EM_EN, S0 and

PWR_EN controls will have no effect on the

power state until the rationing circuitry is reset.

2. Charger emulation

profile removed.

3. Device will enter the

Sleep state.

Ignore

Take no further action.

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DS20005346B-page 45

UCS1003-1/2/3

TABLE 7-3:

Behavior

Report

CHARGE RATIONING RESET BEHAVIOR

Reset Actions

1. Reset the Total Accumulated Charge registers.

2. Clear the RATION status bit.

3. Release the ALERT# pin.

Report

and Disconnect

1. Reset the Total Accumulated Charge registers.

2. Clear the RATION status bit.

3. Release the ALERT# pin.

4. Check the M1, M2, EM_EN, S0 and PWR_EN controls and enter the indicated power state

if the controls changed (see Note 1).

Disconnect

and Go to Sleep

1. Reset the Total Accumulated Charge registers.

2. Clear the RATION status bit.

3. Check the M1, M2, EM_EN, S0 and PWR_EN controls and enter the indicated power state

if the controls changed (see Note 1).

Ignore

1. Reset the Total Accumulated Charge registers.

2. Clear the RATION status bit.

Note 1: Any time the charge rationing circuitry checks the pin conditions when changing rationing behavior or

resetting charge rationing, if the external pin conditions have changed, then charger emulation will be

restarted (provided emulation is enabled via the pin states). If the pin conditions have not changed, the

UCS1003-1 returns to the previous power state as if the rationing threshold had not been reached (e.g., it

will not discharge V

or restart emulation).

BUS

Changing the charge rationing behavior will have no

effect on the Charge Rationing Data registers. If the

behavior is changed prior to reaching the charge

rationing threshold, this change will occur and be

transparent to the user. When the charge rationing

threshold is reached, the UCS1003-1 will take action,

as shown in Table 7-2. If the behavior is changed after

the charge rationing threshold has been reached, the

UCS1003-1 will immediately adopt the newly

programmed behavior, clearing the ALERT# pin and

restoring switch operation respectively (see Table 7-4).

7.4.1

CHARGE RATIONING

INTERACTIONS

When charge rationing is active, regardless of the

specified behavior, the UCS1003-1 will function nor-

mally until the charge rationing threshold is reached.

Note that charge rationing is only active when the

UCS1003-1 is in the Active state and it does not auto-

matically reset when a Removal or Attach Detection

event occurs. Charger emulation will start over if a

Removal Detection event and Attach Detection event

occur while charge rationing is active, and the charge

rationing threshold has not been reached. This allows

charging of sequential portable devices while charge is

being rationed, which means that the accumulated

power given to several portable devices will still be held

to the stated rationing limit.

DS20005346B-page 46

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UCS1003-1/2/3

TABLE 7-4:

EFFECTS OF CHANGING RATIONING BEHAVIOR AFTER THRESHOLD REACHED

New

Actions taken

Behavior

Ignore

Report

Assert ALERT# pin.

Report

and

1. Assert ALERT# pin.

2. Remove charger emulation profile.

Disconnect

3. Open port power switch. See the Report and Disconnect (default) in Table 7-2.

Disconnect 1. Remove charger emulation profile.

and

2. Open port power switch.

Go to Sleep

3. Enter the Sleep state. See the Disconnect and Go to Sleep entry in Table 7-2.

Report

Ignore

Release ALERT# pin.

Report

and

Open port power switch. See the Report and Disconnect (default) entry in Table 7-2.

Disconnect

Disconnect 1. Release the ALERT# pin.

and

2. Remove charger emulation profile.

Go to Sleep

3. Open the port power switch.

4. Enter the Sleep state. See the Disconnect and Go to Sleep entry in Table 7-2.

Report and

Disconnect

Ignore

Report

1. Release the ALERT# pin.

2. Check the M1, M2, EM_EN, S0 and PWR_EN controls, and enter the indicated

power state if the controls changed (see Note 1).

Check the M1, M2, EM_EN, S0 and PWR_EN controls, and enter the indicated

power state if the controls changed (see Note 1).

Disconnect 1. Release the ALERT# pin.

and

2. Enter the Sleep state. See the Disconnect and Go to Sleep entry in Table 7-2.

Go to Sleep

Disconnect

and Go to

Sleep

Ignore

Report

Check the M1, M2, EM_EN, S0 and PWR_EN controls, and enter the indicated

power state if the controls changed (see Note 1).

1. Assert the ALERT# pin.

2. Check the M1, M2, EM_EN, S0 and PWR_EN controls, and enter the indicated

power state if the controls changed (see Note 1).

Report

and

Disconnect

1. Assert the ALERT# pin.

2. Check the M1, M2, EM_EN, S0 and PWR_EN controls to determine the power

state, then enter that state, except that the port power switch and bypass

switch will not be closed (see Note 1).

Note 1: Any time the charge rationing circuitry checks the pin conditions when changing rationing behavior or

resetting charge rationing, if the external pin conditions have changed, then charger emulation will be

restarted (provided emulation is enabled via the pin states). If the pin conditions have not changed, the

UCS1003-1 returns to the previous power state as if the rationing threshold had not been reached (e.g., it

will not discharge V

or restart emulation).

BUS

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DS20005346B-page 47

UCS1003-1/2/3

If the RTN_EN control bit is set to ‘0’ prior to reaching

the charge rationing threshold, rationing will be dis-

abled and the Total Accumulated Charge registers will

be cleared. If the RTN_EN bit is set to ‘0’ after the

charge rationing threshold has been reached, the

following will be done:

7.5

Fault Handling Mechanism

The UCS1003-1/2/3 has two modes for handling

Faults:

• Latch (latch-upon-Fault)

• Auto-Recovery (automatically attempt to restore

the Active power state after a Fault occurs).

1. RATION status bit will be cleared.

2. The ALERT# pin will be released if asserted by

the rationing circuitry and no other conditions

are present.

If the SMBus is actively utilized, auto-recovery Fault

handling is the default error handler, as determined by

the LATCHS bit (see Section 10.4.3 “Switch

Configuration Register”). Otherwise, the Fault

handling mechanism used depends on the state of the

LATCH pin. Faults include overcurrent, overvoltage (on

3. The M1, M2, EM_EN, S0 and PWR_EN controls

are checked to determine the power state. See

Note 1 in Table 7-4.

V ), undervoltage (on V

), back-voltage (V

to V

S

BUS

BUS S

Note:

If the rationing behavior was set to “Report

and Disconnect” when the charge rationing

threshold was reached, and then the

RTN_EN bit is cleared, the portable device

may start charging sub-optimally because

the charger emulation profile has been

removed. Toggle the PWR_EN control to

restart charger emulation.

or V

to V ), discharge error and maximum

BUS DD

allowable internal die temperature (T

(see Section 5.1.5 “Error State Operation”).

) exceeded

TSD

7.5.1

AUTO-RECOVERY FAULT

HANDLING

When the LATCH control is low, auto-recovery Fault

handling is used. When an error condition is detected,

the UCS1003-1/2/3 will immediately enter the Error

state and assert the ALERT# pin (see Section 5.1.5

“Error State Operation”). Independently from the host

controller, the UCS1003-1/2/3 will wait a preset time

Setting the RTN_RST control bit to ‘1’ will automatically

reset the Total Accumulated Charge registers to

00_00h. If this is done prior to reaching the charge

rationing threshold, the data will continue to be accu-

mulated, restarting from 00_00h. If this is done after the

charge rationing threshold is reached, the UCS1003-1

will take action, as shown in Table 7-3.

(t

), check error conditions (t

) and restore

CYCLE

TST

Active operation if the error condition(s) no longer exist.

If all other conditions that may cause the ALERT# pin

to be asserted have been removed, the ALERT# pin

will be released.

DS20005346B-page 48

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UCS1003-1/2/3

enabled to disabled or by clearing the ERR bit via

SMBus), the UCS1003-1/2/3 will check error conditions

once and restore Active operation if error conditions no

longer exist. If an error condition still exists, the host

controller is required to issue the command again to

check error conditions.

7.5.2

LATCHED FAULT HANDLING

When the LATCH control is high, latch Fault handling is

used. When an error condition is detected, the

UCS1003-1/2/3 will enter the Error power state and

assert the ALERT# pin. Upon command from the host

controller (by toggling the PWR_EN control from

t_CYCLE

V_TEST

V_BUS

t_RST

t_CYCLE

t_RST

t_DISCHARGE

Short Applied

I_BUS

I_TST

Check Short Condition,

Short Removed,

Return to Normal

Operation

Wait t_CYCLE

Short Detected,

V_BUSDischarged,

Enter Error State

Check Short Condition,

Short Still Present,

Return to Error State

FIGURE 7-1:

Error Recovery Timing (Short-Circuit Example).

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DS20005346B-page 49

UCS1003-1/2/3

NOTES:

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UCS1003-1/2/3

Until the port power switch is enabled, the current avail-

able to a portable device will be limited to that used to

8.0

8.1

DETECT STATE

detect device attachment (I

). Once an Attach

DET_QUAL

Device Attach/Removal Detection

Detection event occurs, the UCS1003-1/2/3 will wait for

the PWR_EN control to be enabled (if not already).

The UCS1003-1/2/3 can detect the attachment and

removal of a portable device on the USB port. Attach

and Removal Detection does not perform any charger

emulation or qualification of the device. The high-speed

switch is “off” (by default) during the Detect power state.

When PWR_EN is enabled and V is above the thresh-

S

old, the UCS1003-1/2/3 will activate the USB port

power switch and operate in the selected Active mode

(see Section 9.0 “Active State”).

8.4

Removal Detection

8.2

V

Bypass Switch

BUS

The UCS1003-1/2/3 family contains circuitry to provide

current, as shown in Figure 8-1. In the Detect

The Removal Detection feature will be active in the

Active and Detect power states if S0 = 1. This feature

V

BUS

monitors the current load on the V

pin. If this load

state, V is the voltage source; in the Active state, V

BUS

DD

S

drops to less than I

for longer than

is the voltage source. The bypass switch and the port

power switch are never both on at the same time.

REM_QUAL_DET

t

, a Removal Detection event is flagged.

REM_QUAL

When this event occurs, the following will be

performed:

While the V

available to a portable device will be limited to I

and the Attach Detection feature is active.

bypass switch is active, the current

BUS

BUS_BYP

1. Disable the port power switch and the bypass

switch.

2. Deassert the A_DET# pin (UCS1003-1 and

UCS1003-3 only) and set the REM status

register bit (UCS1003-1 only).

Bypass

Switch

V_DD

3. Enable an internal discharging device that will

discharge the V

line within t

.

BUS

DISCHARGE

4. Once the V

pin has been discharged, the

BUS

V_S

V_BUS

device will return to the Detect state regardless

of the PWR_EN control state.

Port Power

Switch

V_S

FIGURE 8-1:

Detect State V_BUSBiasing.

8.3

Attach Detection

The primary Attach Detection feature is only active in

the Detect power state. When active, this feature

constantly monitors the current load on the V

pin. If

BUS

the current drawn by a portable device is greater than

for longer than t , an Attach

I

DET_QUAL,

DET_QUAL

Detection event occurs. This will cause the UCS1003-1

or UCS1003-3 to assert the A_DET# pin low and the

ADET_PIN and ATT status bits to be set in the

UCS1003-1 registers. The UCS1003-2 internally flags

the event.

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UCS1003-1/2/3

NOTES:

DS20005346B-page 52

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UCS1003-1/2/3

9.0

9.1

ACTIVE STATE

Note 1: If it is desired that the Data Pass-Through

mode operates as a traditional/standard

port power switch, the S0 control should be

set to ‘0’ to allow the port power switch to

be closed without requiring an Attach

Detection event. When entering this mode,

Active State Overview

The UCS1003-1/2/3 family has the following modes of

operation in the Active state: Data Pass-Through,

BC1.2 DCP, BC1.2 SDP, BC1.2 CDP and Dedicated

Charger Emulation Cycle. The Current-Limiting mode

depends on the Active mode behavior (see Table 9-2).

there is no automatic V

discharge.

BUS

2: When the M1, M2 and EM_EN controls

are set to ‘0’, ‘1’, ‘0’ or to ‘1’, ‘1’, ‘0’,

respectively, Data Pass-Through mode

will persist if the PWR_EN control is

disabled; however, the UCS1003-1/2/3

will draw more current. To leave the Data

Pass-Through mode, the PWR_EN

control must be enabled before the M1,

M2 and EM_EN controls are changed to

the desired mode.

9.2

Active Mode Selection

The Active mode selection is controlled by three

controls: EM_EN, M1 and M2, as shown in Table 9-1.

TABLE 9-1:

ACTIVE MODE SELECTION

M1

M2 EM_EN Active mode

0

1

Dedicated Charger Emulation

Cycle

9.5

BC1.2 SDP (No Charger

Emulation)

0

1

0

1

0

1

Data Pass-Through

BC1.2 DCP

When commanded to BC1.2 SDP mode, UCS1003-1/2/3

devices will discharge V , close their USB high-speed

BC1.2 SDP (Note 1)

BUS

Dedicated Charger Emulation

Cycle

data switch to allow USB communications between a por-

table device and host controller, and will operate using

Trip Current-Limiting mode. No charger emulation profiles

are applied in this mode. BC1.2 SDP mode will persist

until commanded otherwise by the M1, M2, EM_EN and

PWR_EN controls.

1

0

1

Data Pass-Through

BC1.2 CDP

Note 1: BC1.2 SDP behaves the same as the

Data Pass-Through mode with the

exception that it is preceded by a V

discharge when the mode is entered per

the BC1.2 specification.

Note:

If it is desired that the BC1.2 SDP mode

operates as a traditional/standard port

power switch, the S0 control should be set

to ‘0’ to allow the port power switch to be

closed without requiring an Attach

Detection event.

BUS

9.3

BC1.2 Detection Renegotiation

The BC1.2 specification allows a charger to act as an

SDP, CDP or DCP and to change between these roles.

To force an attached portable device to repeat the

9.6

BC1.2 CDP

Charging Detection procedure, V

compliance with this specification, the UCS1003-1/2/3

family automatically cycles V when switching

between the BC1.2 SDP, BC1.2 DCP and BC1.2 CDP

modes.

must be cycled. In

BUS

When BC1.2 CDP is selected as the Active mode,

UCS1003-1/2/3 devices will discharge V , close their

BUS

USB high-speed data switch (by default) and apply the

BC1.2 CDP charger emulation profile, which performs

handshaking per the specification. The combination of

the UCS1003-1/2/3 CDP handshake, along with a

standard USB host, comprises a charging downstream

port. In BC1.2 CDP mode, there is no emulation time-out.

9.4

Data Pass-Through

(No Charger Emulation)

If the handshake is successful, the UCS1003-1/2/3 will

operate using Constant-Current Limiting (variable

slope). If the handshake is not successful, the

UCS1003-1/2/3 will leave the applied CDP profile in

place, leave the high-speed switch closed, enable

Constant-Current Limiting and persist in this condition

until commanded otherwise by the M1, M2, EM_EN

and PWR_EN controls.

When commanded to Data Pass-Through mode, the

UCS1003-1/2/3 devices will close their USB high-

speed data switch to allow USB communications

between a portable device and host controller, and will

operate using Trip Current-Limiting mode. No charger

emulation profiles are applied in this mode. Data Pass-

Through mode will persist until commanded otherwise

by the M1, M2 and EM_EN controls.

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DS20005346B-page 53

UCS1003-1/2/3

The UCS1003-1/2/3 will respond per the BC1.2

specification to the portable device initiated charger

renegotiation requests.

If the portable device is charging after the DCP charger

emulation profile is applied, the UCS1003-1/2/3 will

leave in place the resistive short, leave the high-speed

switch open and enable Constant-Current Limiting

(variable slope).

Note 1: BC1.2 compliance testing may require

the S0 control to be set to ‘0’ (Attach and

Removal Detection feature disabled)

while testing is in progress.

Note:

BC1.2 compliance testing may require the

S0 control to be set to ‘0’ (Attach and

Removal Detection feature disabled)

while testing is in progress.

2: When the UCS1003-1/2/3 devices are in

BC1.2 CDP mode and the Attach and

Removal Detection feature is enabled, if

a power thief (such as a USB light or fan)

9.7.1

BC1.2 DCP CHARGER

EMULATION PROFILE

attaches but does not assert the D pin,

P

a removal event will not occur when the

portable device is removed. However, if a

standard USB device is subsequently

attached, Removal Detection will again

be fully functional. As well, if PWR_EN is

cycled or M1, M2 and/or EM_EN change

state, a removal event will occur and

Attach Detection will be reactivated.

The BC1.2 DCP charger emulation profile is described

as follows:

1.

V

voltage is applied. A resistor (R

) is

DCP_RES

BUS

connected between the D

and D

pins.

POUT

MOUT

2. Primary Detection – If the portable device drives

0.6V (nominal) onto the pin, the

UCS1003-1/2/3 will take no other action than to

leave the resistor connected between D

D

POUT

and D

. This will cause the portable device

MOUT

9.6.1

BC1.2 CDP CHARGER

EMULATION PROFILE

to see 0.6V (nominal) on the D

pin and

MOUT

know that it is connected to a DCP.

3. Optional Secondary Detection – If the portable

device drives 0.6V (nominal) onto the D

The BC1.2 CDP charger emulation profile acts in a

reactionary manner based on stimulus from the portable

device, as described below and shown in Figure 2-1.

MOUT

pin, the UCS1003-1/2/3 will take no other action

than to leave the resistor connected between

Note:

All CDP handshaking is performed with

the high-speed switch closed.

D

and D

. This will cause the portable

POUT

MOUT

device to see 0.6V (nominal) on the D

POUT

and know that it is connected to a DCP.

1.

V

voltage is applied.

BUS

2. Primary Detection – When the portable device

drives a voltage between 0.4V and 0.8V onto the

9.8

Dedicated Charger Emulation

Cycle

D

pin, the UCS1003-1/2/3 will drive 0.6V

POUT

onto the D

pin within 20 ms.

MOUT

When commanded to Dedicated Charger Emulation

Cycle mode, the UCS1003-1/2/3 family enables an

attached portable device to enter its Charging mode by

applying specific charger emulation profiles in a

predefined sequence. Using these profiles, the

UCS1003-1/2/3 family is capable of generating and

3. When the portable device drives the D

POUT

back to ‘0’, the UCS1003-1/2/3 will then drive

the D pin back to ‘0’ within 20 ms.

MOUT

4. Optional Secondary Detection – If the portable

device then drives a voltage of 0.6V (nominal)

onto the D

pin, the UCS1003-1/2/3 will

recognizing several signal levels on the D

and

MOUT

POUT

take no other action. This will cause the portable

device to observe a ‘0’ on the D pin and

D

pins. The preloaded charger emulation profiles

MOUT

include those compatible with YD/T-1591 (2009), 12W

charging, Samsung and many RIM portable devices. In

the case of UCS1003-1, other levels, sequences and

POUT

know that it is connected to a CDP.

2

protocols are configurable via the SMBus/I C.

9.7

BC1.2 DCP

When a charger emulation profile is applied, a

programmable timer for the emulation profile is started.

When emulation time-out occurs, the UCS1003-1/2/3

When BC1.2 DCP is selected as the Active mode,

UCS1003-1/2/3 will discharge V and apply the

BUS

BC1.2 DCP charger emulation profile per the

specification. In BC1.2 DCP mode, the emulation time-

out and requirement for portable device current draw

are automatically disabled. In the case of UCS1003-1,

when the BC1.2 DCP charger emulation profile is

applied within the Dedicated Charger Emulation Cycle

mode (see Section 9.11.1 “BC1.2 DCP Charger

Emulation Profile within DCE Cycle”), the time-out

and current draw requirement are enabled.

family checks the I

current against a programmable

BUS

threshold. If the current is above the threshold, the

charger emulation profile is accepted and the associated

Current-Limiting mode is applied. No active USB data

communication is possible when charging in this mode

(by default – see Section 10.4.5 “High-Speed Switch

Configuration Register”).

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UCS1003-1/2/3

In the case of UCS1003-1, emulation time-outs can be

programmed for each charger emulation profile (see

Section 10.11 “Preloaded Emulation Time-out Con-

figuration Registers” and Register 10-35).

9.8.1

EMULATION RESET

Prior to applying any of the charger emulation profiles,

the UCS1003-1/2/3 will perform an emulation Reset.

This means that the UCS1003-1/2/3 family resets the

V

line by disconnecting the port power switch and

BUS

9.8.3

DCE CYCLE RETRY

connecting V

to ground via an internal 100 resis-

BUS

If none of the charger emulation profiles cause a

charge current to be drawn, the UCS1003-1/2/3 will

perform emulation Reset and cycle through the profiles

again (if the EM_RETRY bit is set in the UCS1003-1

default – see Section 10.4.2 “Emulation Configura-

tion Register”). The UCS1003-1/2/3 will continue to

cycle through the profiles as long as charging current is

not drawn and the PWR_EN control is enabled. If the

emulation retry is not enabled, the UCS1003-1 will flag,

“No Handshake”, and end the DCE Cycle mode using

Trip Current-Limiting mode.

tor for t

held open for a time equal to t

the port power switch will be closed and the V

voltage applied. The D

time. The port power switch will be

DISCHARGE

at which point,

EM_RESET,

BUS

and D

pins will be

POUT

MOUT

pulled low using internal 15 k pull-down resistors.

Note: To help prevent possible damage to a

portable device, the D and D

POUT

MOUT

pins have current limiting in place when

the emulation profiles are applied.

9.8.2

EMULATION CYCLING

In Dedicated Charger Emulation Cycle mode, the

charger emulation profiles (if enabled) will be applied in

the following order:

1. Legacy 1

2. Legacy 2

3. Legacy 3

4. Legacy 4

5. Legacy 5

6. Legacy 6

7. Legacy 7

8. Custom (UCS1003-1 only; disabled by default).

If the CS_FRST Configuration bit is set, then the

custom charger emulation profile will be tested

first and the order will proceed as given.

If S0 = 0and a portable device is not attached in DCE

Cycle mode, the UCS1003-1/2/3 will be cycling through

charger emulation profiles (by default). There is no

assurance which charger emulation profile will be

applied first when a portable device attaches.

The UCS1003-1/2/3 will apply a charger emulation

profile until one of the following exit conditions occurs:

• Current greater than I

is detected flowing

BUS_CHG

out of V

at the respective emulation time-out

BUS

time. In this case, the profile is assumed to be

accepted and no other profiles will be applied.

• The respective emulation time-out (t

)

EM_TIMEOUT

time is reached without current that exceeds the

limit flowing out of V (the emulation

I

BUS_CHG

BUS

time-out is enabled by default, see Section 10.4.2

“Emulation Configuration Register” and

Register 10-35). The profile is assumed to be

rejected, and the UCS1003-1/2/3 will perform

emulation Reset and apply the next profile if there

is one.

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DS20005346B-page 55

UCS1003-1/2/3

9.9

Current Limit Mode Associations

The UCS1003-1/2/3 will close the port power switch and

use the Current-Limiting mode, as shown in Table 9-2.

TABLE 9-2:

CURRENT LIMIT MODE OPTIONS

Active Mode

Current Limit Mode

(See Section 10.14 “Current-Limiting Behavior

Configuration Registers”)

Data Pass-Through

BC1.2 SDP

Trip mode

CC mode if I

BC1.2 CDP

< 1.68A; otherwise, Trip mode

LIM

BC1.2 DCP

CC mode if I

DCE Cycle Mode

UCS1003-1

During DCE Cycle, when a charger emulation profile is CC mode if I

being applied and the emulation time-out is active

< 1.68A; otherwise, Trip mode

LIM

BC1.2 DCP charger emulation profile accepted or the CC mode if I

emulation time-out is disabled

Legacy 2 charger emulation profile accepted or the

emulation time-out is disabled

CC mode if I

Legacy 1 or Legacy 3 – Legacy 7 charger emulation

Trip mode if I

< I

or I

> 1.68A

LIM

BUS_R2MIN

LIM

profile accepted or the emulation time-out is disabled (normal operation); otherwise, CC mode

(see Register 10-49)(Note 1)

Custom charger emulation profile accepted or the

emulation time-out is disabled

Trip mode if I

(normal operation); otherwise, CC mode

< I

or I

> 1.68A

LIM

BUS_R2MIN

LIM

(see Register 10-49)(Note 1)

No handshake

Trip mode if I

< I

or I

> 1.68A

LIM

BUS_R2MIN

LIM

(DCE Cycle with emulation retry not enabled)

(normal operation); otherwise, CC mode

(see Register 10-49)(Note 1)

UCS1003-2/3

During DCE Cycle, when a charger emulation profile is CC mode if I

being applied and the emulation time-out is active

< 1.68A; otherwise, Trip mode

LIM

Legacy 3 charger emulation profile accepted

CC mode if I

Trip mode

Legacy 1, Legacy 2 or Legacy 4 – Legacy 7 charger

emulation profile accepted

Note 1: In the case of UCS1003-1, under these specific conditions with I

< 1.68A, it is the relationship of I

LIM

and I

that determines the Current-Limiting mode. In these cases, the value of I

is

BUS_R2MIN

determined by the CS_R2_IMIN<2:0> bits, Custom Current-Limiting Behavior Configuration<4:2>

(Register 10-49).

DS20005346B-page 56

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UCS1003-1/2/3

9.11.2

LEGACY 2 CHARGER

EMULATION PROFILE

9.10 No Handshake (UCS1003-1 only)

In DCE Cycle mode with emulation retry disabled, a

“no handshake” condition is flagged. The NO_HS

status bit stays set when the end of the DCE Cycle is

reached without a handshake and without drawing

current (see Register 10-5).

The Legacy 2 charger emulation profile does the

following:

1. The UCS1003-1 will connect

(R ) between D and D .

MOUT

a

resistor

DCP_RES

POUT

2.

V

is applied.

BUS

All signatures/handshaking placed on the D

and

POUT

3. If the portable device draws more than I

BUS_CHG

timer expires

D

pins are removed. The UCS1003-1 will operate

MOUT

current when the t

EM_TIMEOUT

with the high-speed switch opened or closed, as deter-

mined by the high-speed switch configuration, and will

use Trip or Constant-Current Limiting as determined by

(enabled by default), the UCS1003-1 will accept

that this is the correct charger emulation profile

for the attached portable device and charging

commences. The resistive short between the

the I

setting (CS_R2_IMIN<2:0> bits, Custom

BUS_R2MIN

Current-Limiting Behavior Configuration<4:2>).

D

and D

pins will be left in place.

POUT

MOUT

The portable devices that can cause this are generally

4. If the portable device does not draw more than

current when the t timer

the ones that pull up D

to some voltage and leave

POUT

I

BUS_CHG

EM_TIMEOUT

it there or apply the wrong voltage.

expires, the UCS1003-1 will stop the Legacy 2

charger emulation. This will cause the resistive

9.11 Preloaded Charger Emulation

Profiles in UCS1003-1

short between the D

removed. Emulation Reset occurs and UCS1003-1

will initiate the next charger emulation profile.

and D

pins to be

POUT

MOUT

The following charger emulation profiles are resident to

the UCS1003-1:

9.11.3

LEGACY 1, 3, 4 AND 6 CHARGER

EMULATION PROFILES

• BC1.2 DCP Charger Emulation Profile within DCE

Cycle

Legacy 1, 3, 4 and 6 charger emulation profiles follow

the same pattern of operation, although the voltage that

• Legacy 2 Charger Emulation Profile

• Legacy 1, 3, 4 and 6 Charger Emulation Profiles

• Legacy 5 Charger Emulation Profile

• Legacy 7 Charger Emulation Profile

• BC1.2 CDP Charger Emulation Profile

• BC1.2 DCP Charger Emulation Profile

is applied on the D

do the following:

and D

pins will vary. They

POUT

MOUT

1. The UCS1003-1 will apply a voltage on the D

POUT

pin using either a current-limited voltage source or

a voltage divider between V

the center tap on the D

and ground, with

BUS

pin.

POUT

9.11.1

BC1.2 DCP CHARGER EMULATION

PROFILE WITHIN DCE CYCLE

2. The UCS1003-1 will apply a possibly different

voltage on the D pin, using either a current-

MOUT

limited voltage source or a voltage divider

When the BC1.2 DCP charger emulation profile (see

Section 9.7.1 “BC1.2 DCP Charger Emulation Pro-

file”) is applied within the DCE Cycle (dedicated charger

emulation cycle is selected as the Active mode), the

behavior after the profile is applied differentiates from the

Active mode BC1.2 DCP (BC1.2 DCP in Table 9-1)

between V

and ground, with the center tap

BUS

on the D

pin.

MOUT

3.

V

voltage is applied.

BUS

4. If the portable device draws more than I

BUS_CHG

current when the t

timer expires, the

EM_TIMEOUT

UCS1003-1 will accept that the currently applied

profile is the correct charger emulation profile for

the attached portable device; charging com-

because the t

during the DCE Cycle.

timer is enabled (by default)

EM_TIMEOUT

During the DCE Cycle, after the DCP charger

emulation profile is applied, the UCS1003-1 will

perform one of the following:

mences. The voltages applied to the D

and

POUT

D

pins will remain in place (unless

MOUT

EM_RESP is set to ‘0b’). The UCS1003-1 will

1. If the portable device is drawing more than

begin operating in Trip mode or CC mode, as

I

current when the t

timer

determined by the I

setting (see

BUS_CHG

EM_TIMEOUT

BUS_R2MIN

expires, the UCS1003-1 will flag that a BC1.2

DCP was detected. The UCS1003-1 will leave in

place the resistive short, leave the high-speed

switch open and then enable Constant-Current

Limiting (variable slope).

Section 10.14 “Current-Limiting Behavior

Configuration Registers”).

5. If the portable device does not draw more than

I

current when the t

timer

BUS_CHG

EM_TIMEOUT

expires, the UCS1003-1 will stop the currently

applied charger emulation profile. This will cause

2. If the portable device does not draw more than

all voltages put onto the D

and D

pins to

I

current when the t

timer

POUT

MOUT

BUS_CHG

EM_TIMEOUT

be removed. Emulation Reset occurs, and the

UCS1003-1 will initiate the next charger emulation

profile.

expires, the UCS1003-1 will stop applying the

DCP charger emulation profile and proceed to the

next charger emulation profile in the DCE Cycle.

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DS20005346B-page 57

UCS1003-1/2/3

9.11.4

LEGACY 5 CHARGER

EMULATION PROFILE

9.12 Preloaded Charger

Emulation Profiles in UCS1003-2

and UCS1003-3

Legacy 5 charger emulation profile does the following:

1. The UCS1003-1 will apply 900 mV to both the

The following charger emulation profiles are resident to

the UCS1003-2/3:

D

and the D

pins.

POUT

MOUT

2.

V

voltage is applied.

BUS

• Legacy 1 Charger Emulation Profile

• Legacy 2, 4, 5 and 7 Charger Emulation Profiles

• Legacy 3 Charger Emulation Profile

• Legacy 6 Charger Emulation Profile

• BC1.2 CDP Charger Emulation Profile

• BC1.2 DCP Charger Emulation Profile

3. If the portable device draws more than I

BUS_CHG

timer expires, the

current when the t

EM_TIMEOUT

UCS1003-1 will accept that the currently applied

profile is the correct charger emulation profile

for the attached portable device; charging

commences. The voltages applied to the D

POUT

and D

pins will remain in place (unless

MOUT

9.12.1

LEGACY 1 CHARGER

EMULATION PROFILE

EM_RESP is set to ‘0b’). The UCS1003-1 will

begin operating in Trip mode or CC mode, as

determined by the I

setting (see

BUS_R2MIN

Legacy 1 charger emulation profile does the following:

Section 10.14 “Current-Limiting Behavior

Configuration Registers”).

1. The UCS1003-2/3 will apply 900 mV to both the

D

V

and the D

pins.

POUT

MOUT

4. If the portable device does not draw more than

2.

voltage is applied.

I

current when the t

timer

BUS

BUS_CHG

EM_TIMEOUT

expires, the UCS1003-1 will stop the currently

applied charger emulation profile. This will

3. If the portable device is charging, the

UCS1003-2/3 will accept that the currently

applied profile is the correct charger emulation

profile for the attached portable device; charging

cause all voltages put onto the D

and

POUT

D

pins to be removed. Emulation Reset

MOUT

occurs and the UCS1003-1 will initiate the next

charger emulation profile.

commences. The voltages applied to the D

POUT

and D

pins will remain in place. The

MOUT

UCS1003-2/3 will begin operating in Trip mode.

9.11.5

LEGACY 7 CHARGER

EMULATION PROFILE

4. If the portable device is not charging, the

UCS1003-2/3 will stop the currently applied

charger emulation profile. This will cause all volt-

The Legacy 7 charger emulation profile does the

following:

ages put onto the D

and D

pins to be

POUT

MOUT

removed. Emulation Reset occurs and the

UCS1003-2/3 will initiate the next charger

emulation profile.

1. The UCS1003-1 will apply a voltage on the

D

pin using a voltage divider between V

POUT

BUS

and ground with the center tap on the D

pin.

POUT

2.

V

voltage is applied.

BUS

3. If the portable device draws more than I

BUS_CHG

current when the t

timer expires, the

EM_TIMEOUT

UCS1003-1 will accept that Legacy 7 is the

correct charger emulation profile for the

attached

portable

device.

Charging

commences. The voltage applied to the D

POUT

pin will remain in place (unless EM_RESP is set

to 0b). The UCS1003-1 will begin operating in

Trip mode or CC mode, as determined by the

I

setting

(see

Section 10.14

BUS_R2MIN

“Current-Limiting Behavior Configuration

Registers”).

4. If the portable device does not draw more than

I

current when

t

timer

BUS_CHG

EM_TIMEOUT

expires, the UCS1003-1 will stop the Legacy 7

charger emulation profile. This will cause the

voltage put onto the D

pin to be removed.

POUT

Emulation reset occurs, and the UCS1003-1 will

initiate the next charger emulation profile.

DS20005346B-page 58

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

9.12.2

LEGACY 2, 4, 5 AND 7 CHARGER

EMULATION PROFILES

9.12.4

LEGACY 6 CHARGER

EMULATION PROFILE

Legacy 2, 4, 5 and 7 charger emulation profiles follow

the same pattern of operation, although the voltage that

The Legacy 6 charger emulation profile does the

following:

is applied on the D

do the following:

and D

pins will vary. They

POUT

MOUT

1. The UCS1003-2/3 will apply a voltage on the

D

pin using a voltage divider between V

POUT

BUS

1. The UCS1003-2/3 will apply a voltage on the

pin using either a current-limited voltage

and ground, with the center tap on the D

pin.

POUT

D

POUT

source or a voltage divider between V

and

pin.

2.

V

voltage is applied.

BUS

ground, with the center tap on the D

POUT

3. If the portable device is charging, the

UCS1003-2/3 will accept that Legacy 6 is the

correct charger emulation profile for the

attached portable device; charging commences.

2. The UCS1003-2/3 will apply a possibly different

voltage on the D pin, using either a

MOUT

current-limited voltage source or a voltage

divider between V

center tap on the D

and ground. with the

pin.

The voltage applied to the D

in place. The UCS1003-2/3 will begin operating

in Trip mode.

pin will remain

BUS

POUT

MOUT

3.

V

voltage is applied.

BUS

4. If the portable device is charging, the

UCS1003-2/3 will accept that the currently applied

profile is the correct charger emulation profile for

the attached portable device; charging

4. If the portable device is not charging, the

UCS1003-2/3 will stop the Legacy 6 charger

emulation profile. This will cause the voltage put

onto the D

pin to be removed. Emulation

POUT

commences. The voltages applied to the D

Reset occurs and the UCS1003-2/3 will initiate

the next charger emulation profile.

POUT

and D

pins will remain in place. The

MOUT

UCS1003-2/3 will begin operating in Trip mode

(see Section 10.14 “Current-Limiting Behavior

Configuration Registers”).

9.13 Custom Charger Emulation Profile

(UCS1003-1 only)

5. If the portable device is not charging, the

UCS1003-2/3 will stop the currently applied

charger emulation profile. This will cause all volt-

The UCS1003-1 allows the user to create a custom

charger emulation profile to handshake as any type of

charger. This profile can be included in the DCE Cycle.

In addition, it can be placed first or last in the profile

sequence in the DCE Cycle (see Register 10-35).

ages put onto the D

and D

pins to be

POUT

MOUT

removed. Emulation Reset occurs and the

UCS1003-2/3 will initiate the next charger

emulation profile.

The custom charger emulation profile uses a number of

registers to define stimuli and behaviors. The custom

charger emulation profile uses three separate

stimulus/response pairs that will be detected and

applied in sequence, allowing flexibility to “build” any of

the preloaded emulation profiles, or tailor the profile to

match a specific charger application.

9.12.3

LEGACY 3 CHARGER

EMULATION PROFILE

The Legacy 3 charger emulation profile does the

following:

1. The UCS1003-2/3 will connect

(R ) between D and D .

MOUT

a resistor

For details, see Application Note 24.14 – “UCS1002

Fundamentals of Custom Charger Emulation”.

DCP_RES

POUT

2.

V

is applied.

BUS

3. If the portable device is charging, the

UCS1003-2/3 will accept that this is the correct

charger emulation profile for the attached

portable device; charging commences. The

resistive short between the D

pins will be left in place.

and D

POUT

MOUT

4. If the portable device is not charging, the

UCS1003-2/3 will stop the Legacy 3 charger

emulation. This will cause a resistive short

between the D

and D

pins to be

POUT

MOUT

removed. Emulation Reset occurs and the

UCS1003-2/3 will initiate the next charger

emulation profile.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 59

UCS1003-1/2/3

NOTES:

DS20005346B-page 60

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

10.0 UCS1003-1 REGISTER

DESCRIPTION

The registers shown in Table 10-1 are accessible

2

through the SMBus or I C protocol. While in the Sleep

state, the UCS1003-1 will retain configuration and

charge rationing data as indicated in the text. If a regis-

ter does not indicate that data will be retained in the

Sleep power state, this information will be lost when the

UCS1003-1 enters the Sleep power state.

TABLE 10-1: REGISTER SET IN HEXADECIMAL ORDER

Register

Default Page

Register Name

R/W

Function

Address

Value

No.

00h

01h

Current Measurement

R

Stores the current measurement

00h

62

63

Total Accumulated Charge

High Byte

Stores the total accumulated charge

delivered high byte

02h

03h

04h

0Fh

10h

Total Accumulated Charge

Middle High Byte

R

Stores the total accumulated charge

delivered middle high byte

00h

63

64

65

Total Accumulated Charge

Middle Low Byte

Stores the total accumulated charge

delivered middle low byte

Total Accumulated Charge

Low Byte

Stores the total accumulated charge

delivered low byte

Other Status

Indicates emulation status as well as the

ALERT# and A_DET# pin status

Interrupt Status

See

Indicates why ALERT# pin is asserted

Register 10-3

11h

12h

13h

14h

General Status

Profile Status 1

Profile Status 2

Pin Status

R/R-C

Indicates general status

00h

67

68

70

72

R

Indicates which charger emulation

profile was accepted

Indicates the pin states of the internal

control pins

15h

16h

17h

18h

19h

1Ah

General Configuration

Emulation Configuration

Switch Configuration

Attach Detect Configuration

Current Limit

R/W

Controls basic functionality

01h

8Ch

04h

46h

00h

FFh

67

74

76

77

79

80

Controls emulation functionality

Controls advanced switch functions

Controls Attach Detect functionality

Controls the maximum current limit

Charge Rationing Threshold

High Byte

Controls the current threshold, I

THRESH,

used by the charge rationing circuitry

1Bh

Charge Rationing Threshold

Low Byte

R/W

Controls the current threshold, I

used by the charge rationing circuitry

FFh

80

THRESH,

1Ch

1Eh

Auto-Recovery Configuration

R/W

Controls the auto-recovery functionality

2Ah

04h

81

82

I

Configuration

Stores the limit for I

used to

BUS_CHG

determine if emulation is successful

1Fh

t

Configuration

R/W

Stores bits that define the t

time

03h

83

DET_CHARGE

20h

21h

BCS Emulation Enable

R/W

Enables BCS charger emulation profiles

06h

00h

84

85

Legacy Emulation Enable

Enables Legacy charger emulation

profiles

22h

BCS Emulation Time-out

Configuration

R/W

Controls time-out for each BCS charger

emulation profile

10h

86

 2014-2015 Microchip Technology Inc.

DS20005346B-page 61

UCS1003-1/2/3

TABLE 10-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED)

Register

Default Page

Register Name

R/W

Function

Address

Value

No.

23h

Legacy Emulation Time-out

Configuration 1

R/W

Controls time-out for Legacy Charger

Emulation Profiles 1–4

B0h

87

24h

25h

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

Legacy Emulation Time-out

Configuration 2

R/W

R

Controls time-out for Legacy Charger

Emulation Profiles 5–7

04h

14h

00h

88

78

High-Speed Switch

Configuration

Controls when the high-speed switch is

enabled

Applied Charger Emulation

Indicates which charger emulation

profile is being applied

90

Preloaded Emulation

Stimulus 1 – Configuration 1

R

Indicates the stimulus and timing for

Stimulus 1

91

Preloaded Emulation

Stimulus 1 – Configuration 2

R

Indicates the response and magnitude

for Stimulus 1

92

Preloaded Emulation

Stimulus 1 – Configuration 3

R

Indicates the threshold and

pull-up/pull-down settings for Stimulus 1

94

Preloaded Emulation

Stimulus 1 – Configuration 4

R

Indicates the resistor ratio for Stimulus 1

95

Preloaded Emulation

Stimulus 2 – Configuration 1

R

Indicates the stimulus and timing for

Stimulus 2

96

Preloaded Emulation

Stimulus 2 – Configuration 2

R

Indicates the response and magnitude

for Stimulus 2

97

Preloaded Emulation

Stimulus 2 – Configuration 3

R

Indicates the threshold and

pull-up/pull-down settings for Stimulus 2

99

Preloaded Emulation

Stimulus 2 – Configuration 4

R

Indicates the resistor ratio for Stimulus 2

100

101

102

104

Preloaded Emulation

Stimulus 3 – Configuration 1

R

Indicates the stimulus and timing for

Stimulus 3 (CDP only)

Preloaded Emulation

Stimulus 3 – Configuration 2

R

Indicates the response and magnitude

for Stimulus 3 (CDP only)

Preloaded Emulation

Stimulus 3 – Configuration 3

R

Indicates the threshold and

pull-up/pull-down settings for Stimulus 3

(CDP only)

40h

41h

42h

43h

44h

45h

46h

47h

48h

Custom Emulation

Configuration

R/W

Controls general configuration of the

custom charger emulation profile

01h

00h

106

107

108

110

111

112

113

115

116

Custom Stimulus/Response

Pair 1 – Configuration 1

Sets the stimulus and timing for

Stimulus 1

Custom Stimulus/Response

Pair 1 – Configuration 2

Sets the response and magnitude for

Stimulus 1

Custom Stimulus/Response

Pair 1 – Configuration 3

Sets the threshold and pull-up/pull-down

settings for Stimulus 1

Custom Stimulus/Response

Pair 1 – Configuration 4

Sets the resistor ratio for Stimulus 1

Custom Stimulus/Response

Pair 2 – Configuration 1

Sets the stimulus and timing for

Stimulus 2

Custom Stimulus/Response

Pair 2 – Configuration 2

Sets the response and magnitude for

Stimulus 2

Custom Stimulus/Response

Pair 2 – Configuration 3

Sets the threshold and pull-up/pull-down

settings for Stimulus 2

Custom Stimulus/Response

Pair 2 – Configuration 4

Sets the resistor ratio for Stimulus 2

DS20005346B-page 62

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

TABLE 10-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED)

Register

Address

Default Page

Register Name

R/W

Function

Value

No.

49h

4Ah

4Bh

4Ch

50h

51h

FDh

FEh

FFh

Custom Emulation

Stimulus 3 – Configuration 1

R/W

Sets the stimulus and timing for

Stimulus 3

00h

117

Custom Stimulus/Response

Pair 3 – Configuration 2

R/W

R

Sets the response and magnitude for

Stimulus 3

00h

82h

4Eh

5Dh

82h

118

120

121

122

123

Custom Stimulus/Response

Pair 3 – Configuration 3

Sets the threshold and pull-up/pull-down

settings for Stimulus 3

Custom Stimulus/Response

Pair 3 – Configuration 4

Sets the resistor ratio for Stimulus 3

Applied Current-Limiting

Behavior

Indicates the applied current-limiting

behavior

Custom Current-Limiting

Behavior Configuration

R/W

R

Controls the custom current-limiting

behavior

Product ID

Stores a fixed value that identifies each

product

Manufacturer ID

Revision

R

Stores a fixed value that identifies

Microchip

R

Stores a fixed value that represents the

revision number

During Power-on Reset (POR), the default values are

stored in the registers. A POR is initiated when power

10.1 Current Measurement Register

(Address 00h)

is first applied to the part and the voltage on the V

DD

Name

Bits Address Cof Default

00h 00h

supply surpasses the V

level, as specified in the

DD_TH

electrical characteristics. Any reads to undefined

registers will return 00h. Writes to undefined registers

will not have an effect.

Current Measurement

8

R

The Current Measurement register stores the measured

current value delivered to the portable device (I ). This

BUS

When a bit is “set”, this means that the user writes a

logic ‘1’ to it. When a bit is “cleared”, this means that the

user writes a logic ‘0’ to it.

value is updated continuously while the device is in the

Active power state. The bit weights are in mA and the

range is from 0 mA to 2988.6 (the maximum value

corresponds to 255 LSBs, where1 LSB = 11.72 mA).

This data will be cleared when the device enters the

Sleep or Detect states. This data will also be cleared

whenever the port power switch is turned off (including

during emulation or any time that V

is discharged).

BUS

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DS20005346B-page 63

UCS1003-1/2/3

The Total Accumulated Charge registers store the total

10.2 Total Accumulated

Charge Registers

accumulated charge delivered from the V source to a

S

portable device. The bit weighting of the registers is

given in mAh. The register value is reset to 00_00h only

when the RTN_RST bit is set or if the RTN_EN bit is

cleared. This value will be retained when the device

transitions out of the Active state, and resumes accu-

mulation if the device returns to the Active state and

charge rationing is still enabled.

Name

Bits Address Cof Default

Total Accumulated

Charge High Byte

8

01h

R

00h

Total Accumulated

Charge Middle High

Byte

8

02h

R

00h

These registers are updated every second while the

UCS1003-1 is in the Active power state. Every time

the value is updated, it is compared against the

target value in the Charge Rationing Threshold

registers (see Section 10.6 “Charge Rationing

Threshold Registers”).

Total Accumulated

Charge Middle Low

Byte

8

03h

04h

R

00h

Total Accumulated

Charge Low Byte

REGISTER 10-1: TOTAL ACCUMULATED CHARGE REGISTERS (ADDRESSES 01h-04h)

R-0

bit 31

R-0

bit 23

R-0

bit 15

R-0

bit 24

R-0

bit 26

ACC<25:18>

R-0

ACC<17:10>

R-0

ACC<9:2>

bit 8

bit 0

R-0

ACC<1:0>

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

-n = Value at POR

x = Bit is unknown

bit 31-6

bit 5-0

ACC<25:0>: Total Accumulated Charge bits

1 LSB = 0.00325 mAh

Unimplemented: Read as ‘0’

DS20005346B-page 64

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

The Status registers store bits that indicate error

conditions, as well as Attach Detection and Removal

Detection. Unless otherwise noted, these bits will

operate as described when the UCS1003-1 is

operating in Stand-Alone mode.

10.3 Status Registers

Name

Bits Address

Cof

Default

Other Status

8

0Fh

10h

11h

12h

13h

14h

R

R/W

R/R-C

R

00h

Interrupt Status

General Status

Profile Status 1

Profile Status 2

Pin Status

R

REGISTER 10-2: OTHER STATUS REGISTER (ADDRESS 0Fh)

U-0

—

U-0

—

R-0

(1)

(2)

(3)

ALERT_PIN ADET_PIN

CHG_ACT

EM_ACT

EM_STEP<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

-n = Value at POR

x = Bit is unknown

bit 7-6

bit 5

Unimplemented: Read as ‘0’

ALERT_PIN: ALERT# Pin Status bit

This bit is set and cleared as the ALERT# pin changes states.

1= ALERT# pin is asserted low

0= ALERT# pin is released

(1)

bit 4

ADET_PIN: A_DET# Pin Status bit

When set, indicates that the A_DET# pin is asserted low. This bit is set and cleared as the A_DET# pin

changes states.

1= A_DET# pin is asserted low

0= A_DET# pin is released

(2)

bit 3

bit 2

CHG_ACT: I

Set/Clear Status bit

BUS

This bit is automatically set when I

> I

and cleared when I

< I

.

BUS_CHG

BUS

BUS_CHG

BUS

1= I

0= I

> I

< I

BUS

BUS_CHG

(3)

EM_ACT: UCS1003-1 Active State and Emulating Status bit

The actual profile that is being applied is identified by PRE_EM_SEL<3:0> (see Section 10.12.1

“Applied Charger Emulation Register”). This bit is set and cleared automatically.

1= Device is in the Active state and emulating

0= Device is not emulating

bit 1-0

EM_STEP<1:0>: Charger Emulation Stimulus/Response Pair Application bits

Indicates which stimulus/response pair is currently being applied by the charger emulation profile as

shown below. These bits are set and cleared automatically. Note that the Legacy charger emulation

profiles and the BC1.2 DCP charger emulation profile do not use Stimulus/Response Pair #3.

00= None applied, waiting for current.

01= Stimulus/Response #1

10= Stimulus/Response #2

00= Stimulus/Response #3 if applicable

Note 1: If S0 is ‘1’, PWR_EN is enabled and V is not present; the ADET_PIN bit will cycle if the current draw

S

exceeds the current capacity of the bypass switch.

2: The CHG_ACT bit does not indicate that a portable device has accepted one of the charger emulation

profiles. This bit will cycle during the Dedicated Charger Emulation Cycle mode.

3: The EM_ACT bit does not indicate that a portable device has accepted one of the emulation profiles. This

bit will cycle during the Dedicated Charger Emulation Cycle mode

 2014-2015 Microchip Technology Inc.

DS20005346B-page 65

UCS1003-1/2/3

REGISTER 10-3: INTERRUPT STATUS REGISTER (ADDRESS 10h)

R/W-0

R-0

(1,2)

ERR

bit 7

DISCH_ERR

RESET

KEEP_OUT

TSD

OV_VOLT

BACK_V

OV_LIM

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

(1,2)

bit 7

ERR: Error Detection Status bit

Indicates that an error was detected and the device has entered the Error state. Writing this bit to a ‘0’

will clear the Error state and allows the device to be returned to the Active state. When written to ‘0’, all

error conditions are checked. If all error conditions have been removed, the UCS1003-1 returns to the

Active state. This bit is set automatically by the UCS1003-1 when the Error state is entered. Regardless

of the Fault handling mechanism used, if any other bit is set in the Interrupt Status register (10h), the

device will not leave the Error state.

This bit is cleared automatically by the UCS1003-1 if the auto-recovery Fault handling functionality is

active and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN control is

disabled.

1= One or more errors have been detected and the UCS1003-1 has entered the Error state

0= There are no errors detected.

bit 6

bit 5

bit 4

bit 3

DISCH_ERR: Discharge V

Error Status bit

BUS

Indicates that the UCS1003-1 was unable to discharge the V

if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT# pin

to be asserted and the device to enter the Error state.

node. This bit will be cleared when read

BUS

1= UCS1003-1 was unable to discharge the V

node

BUS

0= No V

discharge error.

BUS

RESET: Reset Status bit

Indicates that UCS1003-1 has just been reset and should be reprogrammed. This bit will be set at

power-up. This bit is cleared when read or when the PWR_EN control is toggled. The ALERT# pin is not

asserted when this bit is set. This data is retained in the Sleep state.

1= UCS1003-1 has just been reset

0= Reset did not occur.

KEEP_OUT: V-I Output on V

Pins Status bit

BUS

Indicates that the V-I output on the V

read if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT#

pin to be asserted and the device to enter the Error state.

pins has dropped below V

This bit will be cleared when

BUS

BUS_MIN.

1= V

0= V

< V

> V

BUS

BUS_MIN

TSD: T

Threshold Internal Temperature Status bit

TSD

Indicates that the internal temperature has exceeded the T

threshold and the device has entered the

TSD

Error state. This bit will be cleared when read if the error condition has been removed or if the ERR bit

is cleared. This bit will cause the ALERT# pin to be asserted and the device to enter the Error state.

1= Internal temperature > T

0= Internal temperature < T

TSD

Note 1: If the auto-recovery Fault handling is not used, the ERR bit must be written to a logic ‘0’ to be cleared. It

will also be cleared when the PWR_EN control is disabled.

2: Note that the ERR bit does not necessarily reflect the ALERT# pin status. The ALERT# pin may be

cleared or asserted without the ERR bit changing states.

DS20005346B-page 66

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UCS1003-1/2/3

REGISTER 10-3: INTERRUPT STATUS REGISTER (ADDRESS 10h) (CONTINUED)

bit 2

bit 1

bit 0

OV_VOLT: V

Threshold Voltage Status bit

S_OV

Indicates that the V voltage has exceeded the V

state. This bit will be cleared when read if the error condition has been removed or if the ERR bit is

cleared. This bit will cause the ALERT# pin to be asserted and the device to enter the Error state.

threshold and the device has entered the Error

S_OV

S

1= V > V

S

S_OV

0= V < V

S

BACK_V: V

Voltage Status bit

BUS

Indicates that the V

voltage has exceeded the V or V voltages by more than 150 mV. This bit will

S DD

BUS

be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will

cause the ALERT# pin to be asserted and the device to enter the Error state.

1= V

0= V

> V , or V

> V by more than 150 mV

BUS

S

BUS DD

voltage has not exceeded the V and V voltages by more than 150 mV

S

DD

OV_LIM: I

Current Threshold Status bit

BUS

Indicates that the I

current has exceeded both the I

threshold and the I

threshold set-

BUS_R2MIN

BUS

LIM

tings. This bit will be cleared when read if the error condition has been removed or if the ERR bit is

cleared. This bit will cause the ALERT# pin to be asserted and the device to enter the Error state.

1= I

0= I

> I

and I

BUS

LIM BUS_R2MIN

has not exceeded both I

threshold and the I

threshold settings

LIM

BUS_R2MIN

Note 1: If the auto-recovery Fault handling is not used, the ERR bit must be written to a logic ‘0’ to be cleared. It

will also be cleared when the PWR_EN control is disabled.

2: Note that the ERR bit does not necessarily reflect the ALERT# pin status. The ALERT# pin may be

cleared or asserted without the ERR bit changing states.

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REGISTER 10-4: GENERAL STATUS REGISTER (ADDRESS 11h)

R-0

U-0

—

U-0

—

R-0

R/C-0

REM

R/C-0

ATT

RATION

CC_MODE

TREG

LOW_CUR

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

C = Clear on Read bit

x = Bit is unknown

bit 7

RATION: Programmed Power Amount Delivery Status bit

Indicates that the UCS1003-1 has delivered the programmed amount of power to a portable device. If

the RATION_BEH<1:0> bits are set to interrupt the host, this bit will cause the ALERT# pin to be

asserted. This bit is cleared when read. This bit is also cleared automatically when the RTN_RST bit is

set or the RTN_EN bit is cleared (see Section 10.4.1 “General Configuration Register”).

1= UCS1003-1 has delivered the programmed amount of power to a portable device

0= UCS1003-1 has not delivered the programmed amount of power to a portable device

bit 6-5

bit 4

Unimplemented: Read as ‘0’

CC_MODE: I

Current Indication Status bit

BUS

Indicates that the I

current has exceeded I . Current is in Region 2 (I

).

BUS

LIM

BUS_R2MIN

1= I

0= I

> I

< I

BUS

LIM

bit 3

bit 2

bit 1

bit 0

TREG: T

Internal Temperature Indication Status bit

REG

Indicates that the internal temperature has exceeded T

This bit is cleared when read and will not cause the ALERT# pin to be asserted unless the ALERT_LINK

bit is set.

1= Internal temperature > T

0= Internal temperature < T

and that the current limit has been reduced.

REG

LOW_CUR: Portable Device Charge Current Indication Status bit

Indicates that a portable device has reduced its charge current to below ~6.4 mA and may be finished

charging. This bit is cleared when read and will not cause the ALERT# pin to be asserted unless the

ALERT_LINK bit is set.

1= I

0= I

< 6.4 mA

> 6.4 mA

BUS

REM: Removal Detection Event Status bit

Indicates that a Removal Detection event has occurred and there is no longer a portable device present.

This bit is cleared when read and will not cause the ALERT# pin to be asserted. It will cause the A_DET#

pin to be released.

1= Removal detected

0= No removal detected

ATT: Attach Detection Event Status bit

Indicates that an Attach Detection event has occurred and there is a new portable device present. This

bit is cleared when read and will not cause the ALERT# pin to be asserted. It will cause the A_DET# pin

to be asserted.

1= Attach detected

0= No attach detected

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• The PWR_EN control is disabled

10.3.1

PROFILE STATUS 1 REGISTER

• A new Active mode is selected

These bits are indicators only and will not cause the

ALERT# pin or A_DET# pin to change states. The

CUST, DCP, CDP and PT bits are cleared under the

following circumstances:

• A Removal Detection event occurs

REGISTER 10-5: PROFILE STATUS 1 REGISTER (ADDRESS 12h)

R-0

U-0

—

U-0

—

R-0

(1)

(2)

NO_HS

VS_LOW

CUST

DCP

CDP

PT

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

(1)

bit 7

NO_HS: No Handshake Status bit

The NO_HS bit is only set during the Dedicated Charger Emulation Cycle mode (see Section 9.10 “No

Handshake (UCS1003-1 only)”). This bit is automatically cleared whenever a new charger emulation

profile is applied.

1= No handshake at the end of the DCE Cycle

0= A new charger emulation profile has been applied

bit 6-5

bit 4

Unimplemented: Read as ‘0’

VS_LOW: V

Voltage Threshold Status bit

S_UVLO

Indicates that the V voltage is below the V

threshold and the port power switch is held off. This

S

S_UVLO

bit is cleared automatically when the V voltage is above the V

threshold.

S

S_UVLO

1= V < V

S

S_UVLO

0= V > V

S

bit 3

CUST: Custom Charger Emulation Profile Status bit

Indicates that the portable device successfully performed a handshake with the user-defined custom

charger emulation profile during the DCE Cycle and is charging. Based on the custom charger emulation

profile configuration, the high-speed switch will either be open or closed (see Section 10.13 “Custom

Emulation Configuration Registers”). The port power switch Current-Limiting mode is determined by

the Custom Current Limiting Behavior Configuration register settings (see Section 10.14.2 “Custom

Current-Limiting Behavior Configuration Register”).

1= Custom profile handshake completed

0= No custom profile handshake

bit 2

DCP: DCP Charger Emulation Profile Status bit

Indicates that the portable device accepted the BC1.2 DCP charger emulation profile and is charging.

The high-speed switch will be controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed

Switch Configuration Register”) and the port power switch will use Constant-Current Limiting.

1= DCP handshake completed

0= No DCP handshake

Note 1: The NO_HS bit does not indicate that a portable device is drawing current and it may be cleared to ‘0’

(indicating a handshake), and a portable device not charge. This bit is set at the end of each charger emu-

lation profile if a portable device does not handshake with it. This bit will not be set at the same time that

any other Profile Status register bits are set.

2: When the UCS1003-1 is configured as a data pass-through and a removal event and then an Attach event

occurs without changing the Active mode, the PT bit will not be set again, even though the UCS1003-1 is still

operating as a data pass-through as configured. Toggling the M1 control will re-enable the PT status bit.

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UCS1003-1/2/3

REGISTER 10-5: PROFILE STATUS 1 REGISTER (ADDRESS 12h) (CONTINUED)

bit 1

CDP: CDP Charger Emulation Profile Status bit

Indicates that the portable device successfully performed a handshake with the BC1.2 CDP charger

emulation profile and is charging. The high-speed switch will be closed and the port power switch will

use Trip Current Limiting.

1= CDP handshake completed

0= No CDP handshake

(2)

bit 0

PT: Data Pass-Through/SDP Active Mode Status bit

Indicates that the UCS1003-1 is in the Data Pass-Through or BC1.2 SDP Active mode. The high-speed

switch will be closed and the port power switch will use Trip Current Limiting.

1= UCS1003-1 is in the Data Pass-Through or BC1.2 SDP Active mode.

0= UCS1003-1 is not in the Data Pass-Through or BC1.2 SDP Active mode.

Note 1: The NO_HS bit does not indicate that a portable device is drawing current and it may be cleared to ‘0’

(indicating a handshake), and a portable device not charge. This bit is set at the end of each charger emu-

lation profile if a portable device does not handshake with it. This bit will not be set at the same time that

any other Profile Status register bits are set.

2: When the UCS1003-1 is configured as a data pass-through and a removal event and then an Attach event

occurs without changing the Active mode, the PT bit will not be set again, even though the UCS1003-1 is still

operating as a data pass-through as configured. Toggling the M1 control will re-enable the PT status bit.

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• The PWR_EN control is disabled

10.3.2

PROFILE STATUS 2 REGISTER

• A new Active mode is selected

These bits indicate which profile was accepted. These

bits are indicators only and will not cause the ALERT#

pin or A_DET# pin to change states. These bits are

cleared under the following circumstances:

• A Removal Detection event occurs

REGISTER 10-6: PROFILE STATUS 2 REGISTER (ADDRESS 13h)

U-0

—

R-0

LG7

LG6

LG5

LG4

LG3

LG2

LG1

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

LG7: Legacy 7 Charger Emulation Profile Status bit

Indicates that the portable device successfully performed a handshake with the Legacy 7 charger emula-

tion profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see

Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting

mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2

“Custom Current-Limiting Behavior Configuration Register”).

1= Handshake successful with the Legacy 7 charger emulation profile and charging

0= Not charging with Legacy 7 charger emulation profile

bit 5

bit 4

bit 3

LG6: Legacy 6 Charger Emulation Profile Status bit

Indicates that the portable device successfully performed a handshake with the Legacy 6 charger emula-

tion profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see

Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting

mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2

“Custom Current-Limiting Behavior Configuration Register”).

1= Handshake successful with the Legacy 6 charger emulation profile and charging

0= Not charging with Legacy 6 charger emulation profile

LG5: Legacy 5 Charger Emulation Profile Status bit

Indicates that the portable device successfully performed a handshake with the Legacy 5 charger emula-

tion profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see

Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting

mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2

“Custom Current-Limiting Behavior Configuration Register”).

1= Handshake successful with the Legacy 5 charger emulation profile and charging

0= Not charging with Legacy 5 charger emulation profile

LG4: Legacy 4 Charger Emulation Profile Status bit

Indicates that the portable device successfully performed a handshake with the Legacy 4 charger emula-

tion profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see

Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting

mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2

“Custom Current-Limiting Behavior Configuration Register”).

1= Handshake successful with the Legacy 4 charger emulation profile and charging

0= Not charging with Legacy 4 charger emulation profile

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UCS1003-1/2/3

REGISTER 10-6: PROFILE STATUS 2 REGISTER (ADDRESS 13h) (CONTINUED)

bit 2

bit 1

bit 0

LG3: Legacy 3 Charger Emulation Profile Status bit

Indicates that the portable device successfully performed a handshake with the Legacy 3 charger emula-

tion profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see

Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting

mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2

“Custom Current-Limiting Behavior Configuration Register”).

1= Handshake successful with the Legacy 3 charger emulation profile and charging

0= Not charging with Legacy 3 charger emulation profile

LG2: Legacy 2 Charger Emulation Profile Status bit

Indicates that the portable device successfully performed a handshake with the Legacy 2 charger emula-

tion profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see

Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting

mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2

“Custom Current-Limiting Behavior Configuration Register”).

1= Handshake successful with the Legacy 2 charger emulation profile and charging

0= Not charging with Legacy 2 charger emulation profile

LG1: Legacy 1 Charger Emulation Profile Status bit

Indicates that the portable device successfully performed a handshake with the Legacy 1 charger emula-

tion profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see

Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting

mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2

“Custom Current-Limiting Behavior Configuration Register”).

1= Handshake successful with the Legacy 1 charger emulation profile and charging

0= Not charging with Legacy 1 charger emulation profile

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10.3.3

PIN STATUS REGISTER

The Pin Status register reflects the current pin state of the

external control pins, as well as identifying the power

state. These bits are linked to the X_SET bits (see

Section 10.4.3 “Switch Configuration Register”).

REGISTER 10-7: PIN STATUS REGISTER (ADDRESS 14h)

U-0

—

R-0

(1)

PWR_EN_PIN

M2_PIN

M1_PIN

EM_EN_PIN

SEL_PIN

PWR_STATE<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

PWR_EN_PIN: PWR_EN Pin Control Status bit

Reflects the PWR_EN control state. This bit is set and cleared automatically as the PWR_EN

pin/PWR_ENS bit state changes.

1= PWR_EN is logic ‘1’

0= PWR_EN is logic ‘0’

bit 5

bit 4

bit 3

M2_PIN: M2 Pin Control Status bit

Reflects the M2 pin state. This bit is set and cleared automatically as the M2 pin/M2_SET state changes.

1= M2 is logic ‘1’

0= M2 is logic ‘0’

M1_PIN: M1 Pin Control Status bit

Reflects the M1 pin state. This bit is set and cleared automatically as the M1 pin/M1_SET state changes.

1= M1 is logic ‘1’

0= M1 is logic ‘0’

EM_EN_PIN: EM_EN Pin Control Status bit

Reflects the EM_EN pin state. This bit is set and cleared automatically as the EM_EN pin/EM_EN_SET

state changes.

1= EM_EN is logic ‘1’

0= EM_EN logic ‘0’

bit 2

SEL_PIN: SEL Pin Control Status bit

Reflects the polarity settings determined by the SEL pin decode. This bit is set or cleared automatically

upon device power-up as the SEL pin is decoded.

1= The PWR_EN control is active-high

0= The PWR_EN control is active-low

(1)

bit 1-0

PWR_STATE<1:0>: Power State Control Status bits

Indicates the current power state. These bits are set and cleared automatically as the power state

changes.

00= Sleep

01= Detect

10= Active

11= Error

2

Note 1: Accessing the SMBus/I C causes the UCS1003-1 to leave the Sleep state. As a result, the

PWR_STATE<1:0> bits will never read as ‘00b’.

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UCS1003-1/2/3

10.4 Configuration Registers

Name

Bits

Address

Cof

Default

General Configuration

8

15h

16h

17h

18h

25h

R/W

01h

8Ch

04h

46h

14h

Emulation Configuration

Switch Configuration

Attach Detect Configuration

High-Speed Switch Configuration

The Configuration registers control basic device

functionality.

10.4.1

GENERAL CONFIGURATION

REGISTER

The contents of this register are retained in Sleep.

REGISTER 10-8: GENERAL CONFIGURATION REGISTER (ADDRESS 15h)

R/W-0

ALERT_MASK

bit 7

U-0

—

R/W-0

RATION_BEH<1:0>

bit 0

R/W-1

ALERT_LINK

DSCHG

RTN_EN

RTN_RST

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

ALERT_MASK: ALERT# Pin Assertion bit

1= The ALERT# pin will not be asserted in the event of an error condition

0= The ALERT# pin will be asserted if an error condition or indicator event is detected

bit 6

bit 5

Unimplemented: Read as ‘0’

ALERT_LINK: ALERT# Pin LOW_CUR/TREG Link Assertion bit

1= The ALERT# pin will be asserted if the LOW_CUR or TREG indicator bit is set

0= The ALERT# pin will not be asserted if the LOW_CUR or TREG indicator bit is set

bit 4

bit 3

DSCHG: V

Discharge bit

BUS

Forces the V

to be reset and discharged when the UCS1003-1 is in the Active state. Writing this bit to

BUS

a logic ‘1’ will cause the port power switch to be opened and the discharge circuitry to activate to discharge

. The port power switch will remain open while this bit is ‘1’. This bit is not self-clearing.

V

BUS

RTN_EN: Charge Rationing Enable bit

1= Charge rationing is enabled (see Section 7.4 “Battery Full (UCS1003-1 Only)”)

0= Charge rationing is disabled. The Total Accumulated Charge registers will be cleared to 00_00h

and current data will no longer be accumulated. If the Total Accumulated Charge registers have

already reached the Charge Rationing Threshold (see Section 10.6 “Charge Rationing

Threshold Registers”), the applied response will be removed as if the charge rationing had

been reset. This will also clear the RATION status bit (if set).

bit 2

RTN_RST: Charge Rationing Reset bit

When this bit is set to ‘1’, the Total Accumulated Charge registers are reset to 00_00h. In addition,

when this bit is set, the RATION status bit will be cleared, and if there are no other errors or active

indicators, the ALERT# pin will be released.

1= EM_EN is logic ‘1’

0= EM_EN is logic ‘0’

bit 1-0

RATION_BEH<1:0>: Power Rationing Threshold Control bit (see Table 7-2)

00= Report

01= Report and disconnect

10= Disconnect and go to Sleep

11= Ignore

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10.4.2

EMULATION CONFIGURATION

REGISTER

The contents of this register are retained in Sleep.

REGISTER 10-9: EMULATION CONFIGURATION REGISTER (ADDRESS 16h)

R/W-1

U-0

—

U-0

—

R/W-0

R/W-1

R/W-0

EM_RESET_TIME<1:0>

bit 0

R/W-0

(1)

(2)

DIS_TO

EM_TO_DIS

EM_RETRY EM_RESP

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

DIS_TO: Disable Time-out and Idle Reset bit (see Section 11.2.1.6 “SMBus Time-out and Idle Reset”)

2

1= The Time-out and Idle Reset functionality is disabled; this is used for I C compliance

0= The Time-out and Idle Reset functionality is enabled

bit 6-5

bit 4

Unimplemented: Read as ‘0’

(1)

EM_TO_DIS: Emulation Time-out Disable bit

Disables the emulation circuitry time-out for all charger emulation profiles in the DCE Cycle. There is a

separate bit to enable/disable the emulation time-out for the custom charger emulation profile

(Register 10-35); however, if the EM_TO_DIS bit is set, the emulation time-out will also be disabled for

the custom charger emulation profile.

1= Emulation time-out is disabled during the DCE Cycle. The applied charger emulation profile will not

exit as a result of an emulation time-out event. The I

current will be checked continuously, and

BUS

if it exceeds the I

threshold for any reason, the charger emulation profile will be accepted.

BUS_CHG

0= Emulation time-out is enabled during the DCE Cycle. An individual charger emulation profile will be

applied and maintained for the duration of the t value. When this timer expires, the

EM_TIMEOUT

UCS1003-1 will determine whether the charger emulation profile was successful and take appropriate

action.

bit 3

EM_RETRY: Dedication Charger Emulation bit

Configures whether the DCE Cycle will reset and restart if it reaches the final profile without the portable

device drawing charging current, and accepting one of the profiles. This bit is only used if the UCS1003-1

is configured to emulate a dedicated charger.

1= Once the DCE Cycle is completed, it will perform emulation Reset and restart from the first enabled

charger emulation profile in the DCE Cycle.

0= Once the DCE Cycle is completed, it will not restart. The D

and D

will be left as High Z

POUT

MOUT

pins and the port power switch will be closed. The Current-Limiting mode is determined by the

Custom Current Limiting Behavior settings (see Section 10.14.2 “Custom Current-Limiting

Behavior Configuration Register”).

Note 1: If the EM_TO_DIS bit is set and the Legacy 1, Legacy 3 or custom charger emulation profiles were

accepted during the DCE cycle, a removal is not detected. To avoid this issue, re-enable the emulation

time-out after applying any test profiles and charging with the ‘final’ profile.

2: If the HSW_DCE bit is set, the high-speed switch will be closed regardless of the status of the EM_RESP

bit. Leaving the emulation response applied will not allow normal USB traffic. Therefore, prior to setting the

HSW_DCE bit, this bit should be cleared.

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UCS1003-1/2/3

REGISTER 10-9: EMULATION CONFIGURATION REGISTER (ADDRESS 16h) (CONTINUED)

(2)

bit 2

EM_RESP: Leave Emulation Response bit

Enables the Dedicated Charger Emulation Cycle mode to hold the D

and D

stimulus response

POUT

MOUT

after the UCS1003-1 has finished emulation using the Legacy, BC1.2 DCP or custom charger emulation

profiles.

1= If a portable device begins drawing charging current while the UCS1003-1 is applying the BC1.2

DCP, Custom or any of the Legacy charger emulation profiles during the DCE Cycle, the last

response applied will be kept in place until a Removal Detection event occurs, the internal tempera-

ture exceeds the T

value or emulation is restarted. In the case of the BC1.2 DCP or Legacy 2

REG

charger emulation profiles, this will be the short (R

). In the case of the Legacy 1 or

DCP_RES

Legacy 3-7 profiles, this will be the D

and D

pin voltages. If a portable device does not

POUT

MOUT

draw charging current, the DCE Cycle will behave normally.

0= The dedicated emulation circuitry will behave normally. It will remove the short condition when the

t

timer has expired, regardless if the portable device has drawn charging current or not.

EM_TIMEOUT

bit 1-0

EM_RESET_TIME<1:0>: t

Length Time bit

EM_RESET

Determines the length of the t

time (see Section 9.8.1 “Emulation Reset”) as shown below.

EM_RESET

The value selected does not include discharge time; however, this value plus discharge result in the

actual Reset time.

00= 50 ms

01= 75 ms

10= 125 ms

11= 175 ms

Note 1: If the EM_TO_DIS bit is set and the Legacy 1, Legacy 3 or custom charger emulation profiles were

accepted during the DCE cycle, a removal is not detected. To avoid this issue, re-enable the emulation

time-out after applying any test profiles and charging with the ‘final’ profile.

2: If the HSW_DCE bit is set, the high-speed switch will be closed regardless of the status of the EM_RESP

bit. Leaving the emulation response applied will not allow normal USB traffic. Therefore, prior to setting the

HSW_DCE bit, this bit should be cleared.

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10.4.3

SWITCH CONFIGURATION

REGISTER

The contents of this register are retained in Sleep.

REGISTER 10-10: SWITCH CONFIGURATION REGISTER (ADDRESS 17h)

R/W-0

U-0

—

R/W-0

R/W-1

R/W-0

PIN_IGN

EM_EN_SET

M2_SET

M1_SET

S0_SET

PWR_ENS

LATCHS

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

-n = Value at POR

x = Bit is unknown

bit 7

PIN_IGN: Pin Ignore Selection Mode Determination bit

Ignores the M1, M2, PWR_EN and EM_EN pin states when determining the Active mode selection and

power state.

1= The Active mode selection and power state will be set by the individual control bits and not by the

M1, M2, PWR_EN and EM_EN pin states; these pin states are ignored.

0= The Active mode selection and power state will be set by the OR’d combination of the M1, M2,

PWR_EN and EM_EN pin states and the corresponding bit states.

bit 6

bit 5

Unimplemented: Read as ‘0’

EM_EN_SET: EM_EN Pin Selection Mode Determination bit

In conjunction with other controls, determines the Active mode that is selected (see Section 9.2 “Active

Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the EM_EN pin.

bit 4

bit 3

bit 2

M2_SET: M2 Pin Selection Mode Determination bit

In conjunction with other controls, determines the Active mode that is selected (see Section 9.2 “Active

Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the M2 pin.

M1_SET: M1 Pin Selection Mode Determination bit

In conjunction with other controls, determines the Active mode that is selected (see Section 9.2 “Active

Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the M1 pin.

S0_SET: SMBus Mode Attach/Removal Detection bit

In SMBus mode, enables the Attach and Removal Detection feature and affects the power state (see

Section 9.2 “Active Mode Selection”).

1= Detection is enabled; also see Table 5-2

0= Detection is not enabled; also see Table 5-2

bit 1

bit 0

PWR_ENS: Port Power Switch State bit

Controls whether the port power switch may be turned on or not and affects the power state (see

Section 5.3.4 “PWR_EN Input”). This bit is OR’d with the PWR_EN pin and the polarity of both are

controlled by SEL pin decode. Thus, if the polarity is set to active-high, either the PWR_EN pin or this

bit must be ‘1’ to enable the port power switch.

LATCHS: SMBus Mode Fault Handling Routine Control bit

In SMBus mode, controls the Fault handling routine that is used in the case that an error is detected (see

Section 5.3.5 “Latch Input”).

1= The UCS1003-1 will latch its error conditions; in order for the device to return to normal Active state,

the ERR bit must be cleared by the user

0= The UCS1003-1 will automatically retry when an error condition is detected

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10.4.4

ATTACH DETECTION

CONFIGURATION RESISTER

The contents of this register are retained in Sleep.

REGISTER 10-11: ATTACH DETECTION CONFIGURATION REGISTER (ADDRESS 18h)

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

(1)

RESERVED

DISCHG_TIME_SEL<1:0>

ATT_TH<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

-n = Value at POR

x = Bit is unknown

bit 7-4

bit 3-2

Reserved: Do not change

DISCHG_TIME_SEL<1:0>: t

Time Setting bits

DISCHARGE

00= 100 ms

01= 200 ms

10= 300 ms

11= 400 ms

(1)

bit 1-0

ATT_TH<1:0>: Attach/Removal Detection Threshold bits

Determines the Attach Detection threshold (I

) and Removal Detection thresholds

DET_QUAL

(I

and I

) as shown below.

REM_QUAL_DET

REM_QUAL_ACT

00= 200 µA Attach, 100 µA Removal Threshold

01= 400 µA Attach, 300 µA Removal Threshold

10= 800 µA Attach, 700 µA Removal Threshold

11= 1000 µA Attach, 900 µA Removal Threshold

Note 1: The Removal Threshold is different when operating in the Active power state versus when operating in the

Detect power state.

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10.4.5

HIGH-SPEED SWITCH

CONFIGURATION REGISTER

The contents of this register are retained in Sleep.

REGISTER 10-12: HIGH-SPEED SWITCH CONFIGURATION REGISTER (ADDRESS 25h)

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

R/W-1

R/W-0

RESERVED HSW_CUST

HSW_CDP HSW_DET HSW_DCE

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-5

bit 4

Unimplemented: Read as ‘0’

Reserved: Do not change

bit 3

HSW_CUST: Custom Handshake USB High-Speed Data Switch Enable bit

Enables the USB high-speed data switch to be active during the custom handshake. This control is

checked at the beginning of charger emulation. Therefore, changing this control during emulation will

have no immediate effect. Upon restarting charger emulation (as a result of the EM_RETRY bit being set,

a Removal Detection event or change of emulation controls), the high-speed switch will close.

1= The USB high-speed data switch is enabled while the custom charger emulation profile is applied;

also, if the custom charger emulation profile is accepted during the Dedicated Charger Emulation

Cycle mode, the high-speed switch will stay closed

0= The USB high-speed data switch is disabled while the custom charger emulation profile is applied

bit 2

HSW_CDP: CDP Handshake USB High-Speed Data Switch Enable bit

Enables the USB high-speed data switch to be active during the CDP handshake. This control is

checked at the beginning of charger emulation. Therefore, changing this control during emulation will

have no immediate effect. Upon restarting charger emulation (as a result of a Removal Detection event

or change of emulation controls), the high-speed switch will close.

1= The USB high-speed data switch is enabled during the CDP handshake

0= The USB high-speed data switch is disabled during the CDP handshake

bit 1

bit 0

HSW_DET: Detect Power State USB High-Speed Data Switch Enable bit

Enables the USB high-speed data switch to be active during the Detect power state. If the S0 control is

set to ‘0’, this bit is ignored.

1= The USB high-speed data switch will be closed during the Detect power state

0= The USB high-speed data switch is open during the Detect power state

HSW_DCE: DCP Charger Emulation Profile USB High-Speed Data Switch Enable bit

Enables the USB high-speed data switch after the DCP charger emulation profile or one of the Legacy

charger emulation profiles was accepted during the DCE Cycle and the portable device is charging. This

bit is ignored if the UCS1003-1 is not in the Active state. This bit will not cause the high-speed switch to

be closed during emulation when the DCP and Legacy profiles are applied, only after the DCP or a

Legacy charger emulation profile has been accepted.

1= The USB high-speed data switch will be closed

0= The USB high-speed data switch will be open

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UCS1003-1/2/3

The Current Limit register controls the I

port power switch. The default setting is based on the

used by the

10.5 Current Limit Register

LIM

resistor on the COMM_SEL/I pin and this value cannot

be changed to be higher than the hardware set value.

Name

Bits Address Cof Default

19h R/W 00h

LIM

Current Limit

8

The contents of this register are retained in Sleep.

REGISTER 10-13: CURRENT LIMIT REGISTER (ADDRESS 19h)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

bit 0

(1)

ILIM_SW<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

(1)

ILIM_SW<2:0>: I

Value Setting bits

LIM

000= 0.57A

001= 1.00A

010= 1.13A

011= 1.35A

100= 1.68A

101= 2.05A

110= 2.28A

111= 2.85A (3.0A maximum)

Note 1: Unless otherwise indicated, the values specified are the typical I

in Table 1-2.

LIM

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The Charge Rationing Threshold registers set the

maximum allowed charge that will be delivered to a

portable device. Every time the Total Accumulated

Charge registers are updated, the value is checked

against this limit. If the value meets or exceeds this

limit, the RATION bit is set (see Section 10.4.1 “Gen-

eral Configuration Register”) and action taken

according to the RATION_BEH<1:0> bits (see

Section 10.4.1 “General Configuration Register”).

10.6 Charge Rationing Threshold

Registers

Name

Bits Address Cof Default

Charge Rationing

8

1Ah

R/W

FFh

Threshold High Byte

Charge Rationing

8

1Bh

R/W

FFh

Threshold Low Byte

The units are in mAh, with a range from 0 to ~218429.

The contents of this register are retained in Sleep.

REGISTER 10-14: CHARGE RATIONING THRESHOLD (ADDRESS 1Ah-1Bh)

R/W-1

CHTHR<15:8>

bit 15

R/W-1

bit 8

R/W-1

CHTHR<7:0>

R/W-1

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-0

CHTHR<15:0>: Charge Rationing Threshold bits

LSB = 3.333 mAh

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UCS1003-1/2/3

Once the auto-recovery Fault handling algorithm has

checked the overtemperature and backdrive condi-

10.7 Auto-Recovery Configuration

Register

tions, it will set the I

value to I

and then turn on

LIM

TEST,

the port power switch and start the t timer. If, after

Name

Bits Address Cof Default

1Ch R/W 2Ah

RST

the timer has expired, the V

voltage is less than

BUS

Auto-Recovery Configuration

8

V

, then it is assumed that a short-circuit condition

TEST

is present and the Error state is reset.

The contents of this register are retained in Sleep.

The Auto-Recovery Configuration register sets the

parameters used when the auto-recovery Fault

handling algorithm is invoked (see Section 7.5.1

“Auto-Recovery Fault Handling”).

REGISTER 10-15: AUTO-RECOVERY CONFIGURATION REGISTER (ADDRESS 1Ch)

U-0

—

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

TCYCLE<2:0>

TRST_SW<1:0>

VTST_SW<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

TCYCLE<2:0>: Delay Cycle Time bits

Defines the delay (t ) after the Error state is entered before the auto-recovery Fault handling

bit 6-4

CYCLE

algorithm is started, as shown below.

000= 15 ms

001= 20 ms

010= 25 ms

011= 30 ms

101= 40 ms

110= 45 ms

111= 50 ms

bit 3-2

bit 1-0

TRST_SW<1:0>: t

Setting Time bits

RST

00= 10 ms

01= 15 ms

10= 20 ms

11= 25 ms

VTST_SW<1:0>: V

Value Setting bits

TEST

00= 250 mV

01= 500 mV

10= 750 mV

11= 1000 mV

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The IBUS_CHG Configuration register sets the

10.8 IBUS_CHG Configuration Register

I

current value. If current greater than

BUS_CHG

Name

Bits Address Cof Default

1Eh R/W 04h

is detected flowing out of V

, emulation is

BUS_CHG

BUS

successful. The bit weights are in mA, and the range is

from 11.72 mA to 175.8 mA.

IBUS_CHG

8

Configuration

The contents of this register are not retained in Sleep.

REGISTER 10-16: IBUS_CHG CONFIGURATION REGISTER (ADDRESS 1Eh)

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

R/W-1

R/W-0

bit 0

ICHG<3:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

ICHG<3:0>P: I Current Value bits

BUS_CHG

1 LSB = 11.72 mA

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UCS1003-1/2/3

again. The t

timer is started whenever the

10.9 TDET_CHARGE Configuration

Register

DET_CHARGE

V

voltage is discharged and the bypass switch is

BUS

reactivated. This timer is meant to be a delay to allow

the V capacitor to charge before detecting an

Name

Bits Address Cof Default

1Fh R/W 03h

BUS

Attach Detection event.

TDET_CHARGE

Configuration

8

If t time is increased greater than 800 ms,

DET_CHARGE

larger bus capacitors can be accommodated;

however, with a portable device present and PWR_EN

disabled, a Removal Detection event, and then

another Attach Detection event will occur.

The TDET_CHARGE Configuration register controls

the t and t timing. The t

DC_TEMP

DET_CHARGE

timer is started whenever the temperature exceeds

. This timer is meant to give the system time to

T

REG

The contents of this register are retained in Sleep.

cool at the lower I

setting before changing I

LIM

REGISTER 10-17: TDET_CHARGE CONFIGURATION REGISTER (ADDRESS 1Fh)

U-0

—

U-0

—

U-0

—

R/W-0

R/W-1

DC_TEMP_SET<1:0>

DET_CHARGE_SET<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-5

bit 4-3

Unimplemented: Read as ‘0’

DC_TEMP_SET<1:0>: t

Time Determination bits

DC_TEMP

00= 200 ms

01= 400 ms

10= 800 ms

11= 1600 ms

bit 2-0

DET_CHARGE_SET<2:0>: t

Time Determination bits

DET_CHARGE

000= 200 ms

001= 400 ms

010= 600 ms

011= 800 ms

100= 1000 ms

101= 1200 ms

110= 1400 ms

111= 2000 ms

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The Preloaded Emulation Enable registers enable the

charger emulation profiles used by the emulation circuitry.

10.10 Preloaded Emulation Enable

Registers

The contents of these registers are retained in Sleep.

Name

Bits Address Cof Default

BCS Emulation Enable

8

20h

21h

R/W

06h

00h

Legacy Emulation

Enable

REGISTER 10-18: BCS EMULATION ENABLE REGISTER (ADDRESS 20h)

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

R/W-1

R/W-0

bit 0

DCP_EM_DIS

RESERVED

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-5

bit 4

Unimplemented: Read as ‘0’

DCP_EM_DIS: DCP Charger Emulation Profile in the DCE Cycle Disable bit

This bit is ignored if the M1, M2 and EM_EN control settings have selected DCP mode (see Table 9-1).

1= The BC1.2 DCP charger emulation profile is not enabled during the DCE Cycle

0= The BC1.2 DCP charger emulation profile is enabled during the Dedicated Charger Emulation

Cycle mode

bit 3

Unimplemented: Read as ‘0’

Reserved: Do not change

bit 2-0

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UCS1003-1/2/3

REGISTER 10-19: LEGACY EMULATION ENABLE REGISTER (ADDRESS 21h)

U-0

—

R/W-0

L7EM_DIS

L6EM_DIS

L5EM_DIS

L4EM_DIS

L3EM_DIS L2EM_DIS L1EM_DIS

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

L7EM_DIS: Legacy 7 charger emulation profile Disable bit

1= The Legacy 7 charger emulation profile is not enabled

0= The Legacy 7 charger emulation profile is enabled

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

L6EM_DIS: Legacy 6 charger emulation profile Disable bit

1= The Legacy 6 charger emulation profile is not enabled

0= The Legacy 6 charger emulation profile is enabled

L7EM_DIS: Legacy 5 charger emulation profile Disable bit

1= The Legacy 5 charger emulation profile is not enabled

0= The Legacy 5 charger emulation profile is enabled

L7EM_DIS: Legacy 4 charger emulation profile Disable bit

1= The Legacy 4 charger emulation profile is not enabled

0= The Legacy 4 charger emulation profile is enabled

L7EM_DIS: Legacy 3 charger emulation profile Disable bit

1= The Legacy 3 charger emulation profile is not enabled

0= The Legacy 3 charger emulation profile is enabled

L7EM_DIS: Legacy 2 charger emulation profile Disable bit

1= The Legacy 2 charger emulation profile is not enabled

0= The Legacy 2 charger emulation profile is enabled

L7EM_DIS: Legacy 1 charger emulation profile Disable bit

1= The Legacy 1 charger emulation profile is not enabled

0= The Legacy 1 charger emulation profile is enabled

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10.11 Preloaded Emulation Time-out

Configuration Registers

Name

Bits Address Cof Default

Legacy Emulation Time-out

Configuration 2

8

24h

R/W 04h

Name

Bits Address Cof Default

The Preloaded Emulation Time-out Configuration reg-

isters control the t setting that is applied

BCS Emulation Time-out

Configuration

8

22h

R/W 10h

EM_TIMEOUT

whenever the indicated preloaded charger emulation

profile is applied during the DCE Cycle. These settings

are not used if the EM_TO_DIS bit is set.

Legacy Emulation Time-out

Configuration 1

8

23h

R/W B0h

The contents of this registers are retained in Sleep.

REGISTER 10-20: BCS EMULATION TIME-OUT CONFIGURATION REGISTER (ADDRESS 22h)

U-0

—

U-0

—

R/W-0

R/W-1

R/W-0

DCP_EM_TO<1:0>

RESERVED

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

DCP_EM_TO<1:0>: BC1.2 DCP t

Setting Definition bits

EM_TIMEOUT

These bits are applied when the BC1.2 DCP charger emulation profile is used during the DCE Cycle.

00= 0.8s

01= 1.6s

10= 6.4s

00= 12.8s

bit 3-0

Reserved: Do not change

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UCS1003-1/2/3

REGISTER 10-21: LEGACY EMULATION TIME-OUT CONFIGURATION 1 REGISTER

(ADDRESS 23h)

R/W-1

R/W-0

R/W-1

R/W-0

L1EM_TO<1:0>

L2EM_TO<1:0>

L3EM_TO<1:0>

L4EM_TO<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

L1EM_TO<1:0>: Legacy 1 t

Setting Definition bits

EM_TIMEOUT

These bits are applied when the Legacy 1 charger emulation profile is used during the DCE Cycle.

00= 0.8s

01= 1.6s

10= 6.4s

11= 12.8s

bit 5-4

bit 3-2

bit 1-0

L2EM_TO<1:0>: Legacy 2 t

Setting Definition bits

EM_TIMEOUT

These bits are applied when the Legacy 2 charger emulation profile is used during the DCE Cycle.

00= 0.8s

01= 1.6s

10= 6.4s

11= 12.8s

L3EM_TO<1:0>: Legacy 3 t

Setting Definition bits

EM_TIMEOUT

These bits are applied when the Legacy 3 charger emulation profile is used during the DCE Cycle.

00= 0.8s

01= 1.6s

10= 6.4s

11= 12.8s

L4EM_TO<1:0>: LEGACY 4 t

Setting Definition bits

EM_TIMEOUT

These bits are applied when the Legacy 4 charger emulation profile is used during the DCE Cycle.

00= 0.8s

01= 1.6s

10= 6.4s

11= 12.8s

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REGISTER 10-22: LEGACY EMULATION TIME-OUT CONFIGURATION 2 REGISTER

(ADDRESS 24h)

U-0

—

U-0 R/W-0

R/W-0

R/W-1

R/W-0

—

L5EM_TO<1:0>

L6EM_TO<1:0>

L7EM_TO<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

L5EM_TO<1:0>: Legacy 5 t

Setting Definition bits

EM_TIMEOUT

These bits are applied when the Legacy 5 charger emulation profile is used during the DCE Cycle.

00= 0.8s

01= 1.6s

10= 6.4s

11= 12.8s

bit 3-2

bit 1-0

L6EM_TO<1:0>: Legacy 6 t

Setting Definition bits

EM_TIMEOUT

These bits are applied when the Legacy 6 charger emulation profile is used during the DCE Cycle.

00= 0.8s

01= 1.6s

10= 6.4s

11= 12.8s

L5EM_TO<1:0>: Legacy 7 t

Setting Definition bits

EM_TIMEOUT

These bits are applied when the Legacy 7 charger emulation profile is used during the DCE Cycle.

00= 0.8s

01= 1.6s

10= 6.4s

11= 12.8s

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The Preloaded Emulation Configuration registers store

the settings loaded from internal memory as required

for the preloaded charger emulation profile that is

actively being applied. These registers are read-only.

10.12 Preloaded Emulation

Configuration Registers

Name

Bits Address Cof Default

Applied Charger Emulation

8

30h

31h

R

00h

The Legacy charger emulation profiles, the BC1.2 SDP,

and the BC1.2 DCP charger emulation profiles do not

use the Stimulus 3 Configuration registers (39h-3Bh).

Whenever these charger emulation profiles are

applied, registers 39h-3Bh will not be updated and their

contents should be ignored.

Preloaded Emulation

Stimulus 1 – Configuration 1

Preloaded Emulation

Stimulus 1 – Configuration 2

8

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

R

00h

Preloaded Emulation

Stimulus 1 – Configuration 3

Whenever a Legacy charger emulation profile is

applied within the DCE Cycle, these controls will not be

updated and should be ignored. These settings are

only used by the BC1.2 CDP and BC1.2 DCP charger

emulation profiles.

Preloaded Emulation

Stimulus 1 – Configuration 4

Preloaded Emulation

Stimulus 2 – Configuration 1

The contents of registers 31h, 35h and 39h are not

retained in Sleep. They are updated as needed.

Preloaded Emulation

Stimulus 2 – Configuration 2

The contents of registers 32h, 33h, 34h, 36h, 37h, 38h,

3Ah, 3Bh and 40h are retained in Sleep.

Preloaded Emulation

Stimulus 2 – Configuration 3

Preloaded Emulation

Stimulus 2 – Configuration 4

Preloaded Emulation

Stimulus 3 – Configuration 1

Preloaded Emulation

Stimulus 3 – Configuration 2

Preloaded Emulation

Stimulus 3 – Configuration 3

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10.12.1 APPLIED CHARGER EMULATION

REGISTER

The contents of this register are not retained in Sleep.

The contents are updated as the charger emulation

profile being applied changes.

REGISTER 10-23: APPLIED CHARGER EMULATION REGISTER (ADDRESS 30h)

U-0

—

U-0

—

U-0

—

U-0

—

R-0

PRE_EM_SEL<3:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

PRE_EM_SEL<3:0>: Active Charger Emulation Profile Selection bits

Indicates which of the charger emulation profiles is being actively applied, as shown below.

0000= Data Pass-Through or BC1.2 SDP mode

0001= BC1.2 CDP

0010= BC1.2 DCP

0011= Legacy 1

0100= Legacy 2

0101= Legacy 3

0110= Legacy 4

0111= Legacy 5

1000= Legacy 6

1001= Legacy 7

1010= Custom profile

All others = Not used

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REGISTER 10-24: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 1 REGISTER

(ADDRESS 31h)

U-0

—

R-0

bit 0

S1_TD_TYPE

S1_TD<2:0>

STIM1<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

S1_TD_TYPE: Stimulus 1 Timer Behavior Determination bit

1= The stimulus timer controls how long the response is applied after the stimulus is detected; the response

is applied immediately and held for the duration of the timer then removed (if the stimulus has been

removed)

0= The stimulus timer is a delay from when the stimulus is detected until the response is performed

bit 5-3

S1_TD<2:0>: Stimulus 1 t

Value Determination bits

STIM_DEL

000= 0 ms

001= 1 ms

010= 5 ms

011= 10 ms

100= 20 ms

101= 40 ms

110= 80 ms

111= 100 ms

bit 2-0

STIM1<2:0>: Stimulus 1 Determination Usage bits

Determines the Stimulus 1 that is used as shown below. Note that the lower threshold for the window

comparator option is fixed at 400 mV and only applies to the D

pin. This setting cannot be used for

POUT

the D

port.

MOUT

000= (default) V

voltage is ready to be applied before port power switch is closed; next stimulus

BUS

will not wait for this to be removed

001= D voltage is higher than the threshold (S1_TH)

POUT

010= Window comparator; D

voltage is lower than the threshold (S1_TH) and D

voltage

POUT

higher than the fixed threshold

011= D voltage is higher than the threshold (S1_TH)

MOUT

100= Do not use

101= Do not use

110= D

111= V

voltage is higher than the threshold (S1_TH)

voltage is present after port power switch is closed; next stimulus will not wait for this to be

POUT

BUS

removed.

DS20005346B-page 92

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REGISTER 10-25: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 2 REGISTER

(ADDRESS 32h)

R-0

S1_R1<3:0>

R-0

S1_R1MAG<3:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

S1_R1MAG<3:0>: Stimulus 1 Response Magnitude bits

Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on

which response was selected. Data written to any field that is identified as ‘Do not use’ will not be

accepted. The data will not be updated and the settings will remain set at the previous value.

For S1_R1 Settings 0000-0011:

The response is a voltage applied on the D

voltage relative to ground:.

/D

pins. The S1_R1MAG>3:0> bits specify the

POUT MOUT

0000 = Pull-down

0001 = 400 mV

0010 = 400 mV

0011 = 400 mV

0100 = 400 mV

0101 = 500 mV

0110 = 600 mV

0111 = 700 mV

1100 = 1800 mV

1101 = 2000 mV

1110 = 2200 mV

1111 = Do not use

1000 = 800 mV

1001 = 900 mV

1010 = 1400 mV

1011 = 1600 mV

For S1_R1 Settings 0100, 0111, 1101-1111:

The response is a resistor connected on D

the resistor value.

/D

to GND or V

. The S1_R1MAG bits specify

POUT MOUT

BUS

0000 = 1.8 k

0001 = 10 k

0010 = 15 k

0011 = 20 k

0100 = 25 k

0101 = 30 k

0110 = 40 k

0111 = 43 k

1100 = 100 k

1101 = 120 k

1110 = 150 k

1111 = Do not use

1000 = 50 k

1001 = 60 k

1010 = 75 k

1011 = 80 k

For S1_R1 Settings 0110, 1001, 1100:

The response is a voltage divider applied from V

to GND with the “center” at D

/D

. The

BUS

POUT MOUT

S1_R1MAG bits specify the minimum resistance of the voltage divider (sum of R1 + R2).

0000 = 93 k

0001 = 100 k

0010 = 125 k

0011 = 150 k

0100 = 200 k

0101 = 200 k

0110 = 200 k

0111 = 200 k

1000 = 93 k

1001 = 100 k

1010 = 125 k

1011 = 150 k

1100 = 200 k

1101 = 200 k

1110 = 200 k

1111 = Do not use

Note 1: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

POUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

POUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

POUT

2: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

MOUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

MOUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

MOUT

 2014-2015 Microchip Technology Inc.

DS20005346B-page 93

UCS1003-1/2/3

REGISTER 10-25: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 2 REGISTER

(ADDRESS 32h) (CONTINUED)

bit 3-0

S1_R1<3:0>: Stimulus 1 Response Definition bits

0000= Removes previous response on D and D

POUT

MOUT

(1)

0001= Applies voltage on D

0010= Applies voltage on D

0011= Applies voltage on D

POUT

MOUT

POUT

(2)

and D

MOUT

(1)

0100= Connects resistor from D

0101= Do not use

to GND

POUT

(1)

(2)

0110= Connects voltage divider from V

to GND with ‘center’ at D

POUT

BUS

(2)

0111= Connects resistor from D

1000= Do not use

to GND

MOUT

1001= Connects voltage divider from V

1010= Connects  200resistor from D

1011= Do not use

to GND with ‘center’ at D

to D

BUS

MOUT

POUT

MOUT

1100= Connects voltage divider from V

to GND with ‘center’ at D

and D

MOUT

BUS

1101= Connects resistor from D

to GND and D

to GND

POUT

MOUT

1110= If STIM1<2:0> = 000, the 15 kpull-down resistors applied to D

and D

during emu-

POUT

MOUT

lation Reset are not removed. If STIM1<2:0> = 111, the 15 kpull-down resistors applied to

and D during emulation Reset are removed. For all other STIM1<2:0> settings,

D

POUT

MOUT

whatever was applied is not changed.

1111= Same as ‘1110’ definition above

Note 1: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

POUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

POUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

POUT

2: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

MOUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

MOUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

MOUT

DS20005346B-page 94

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-26: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 3 REGISTER

(ADDRESS 33h)⁽¹⁾

U-0

—

U-0 R-0

R-0

S1_TH<3:0>

R-0

—

S1_PUPD<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

S1_PUPD<1:0>: Stimulus 1 Pull-Down Current Magnitude bits

Determines the magnitude of the pull-down current applied on the D

and D

pins when the

POUT

MOUT

stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (‘0000b’). The bit

decode is given below.

00= 10 µA

01= 50 µA

10= 100 µA

11= 150 µA

bit 3-0

S1_TH<3:0>: Stimulus 1 Threshold Value Definition bits

Defines the threshold value, as shown below, for the specified stimulus. If the stimulus V

voltage is

BUS

ready to be applied or applied (i.e., STIM1<2:0> = 000bor 111b), the threshold value is ignored.

0000= 400 mV

0001= 400 mV

0010= 400 mV

0011= 300 mV

0100= 400 mV

0101= 500 mV

0110= 600 mV

0111= 700 mV

1000= 800 mV

1001= 900 mV

1010= 1400 mV

1011= 1600 mV

1100= 1800 mV

1101= 2000 mV

1110= 2200 mV

1111= Do not use

Note 1: The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation

profile is applied within the DCE Cycle, these controls will not be updated and should be ignored. These

settings are only used by the BC1.2 CDP and DCP charger emulation profiles.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 95

UCS1003-1/2/3

REGISTER 10-27: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 4 REGISTER

(ADDRESS 34h)⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0

S1_RATIO<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

S1_RATIO<2:0>: Stimulus 1 Voltage Divider Ratio bits

Determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a

voltage divider (i.e., S1_R1<3:0> = 0110b, 1001bor 1100b).

000= 0.25

001= 0.33

010= 0.4

011= 0.5

100= 0.54

101= 0.6

110= 0.66

111= Do not use

Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or

DCP charger emulation profile is applied, these controls will not be updated and should be ignored. These

settings are only used by the Legacy charger emulation profiles.

DS20005346B-page 96

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-28: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 1 REGISTER

(ADDRESS 35h)

U-0

—

R-U

S2_TD_TYPE

R-0

bit 0

S2_TD<2:0>

STIM2<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

S2_TD_TYPE: Stimulus 2 Timer Behavior Determination bit

1= The stimulus timer controls how long the response is applied after the stimulus is detected; the

response is applied immediately and held for the duration of the timer, then removed (if the stimulus

has been removed)

0= The stimulus timer is a delay from when the stimulus is detected until the response is performed

bit 5-3

S2_TD<2:0>: Stimulus 2 t

Determination Value bits

STIM_DEL

000= 0 ms

001= 1 ms

010= 5 ms

011= 10 ms

100= 20 ms

101= 40 ms

110= 80 ms

111= 100 ms

bit 2-0

STIM2<2:0>: Stimulus 2 Determination Usage bits

Determines the Stimulus 2 that is used, as shown below. Note that the lower threshold for the window

comparator option is fixed at 400 mV and only applies to the D

pin. This setting cannot be used for

POUT

the D

port.

MOUT

000= V

voltage is ready to be applied before port power switch is closed; next stimulus will not wait

BUS

for this to be removed

001= D

voltage is greater than the threshold (S2_TH)

POUT

010= Window comparator; D

voltage is lower than the threshold (S2_TH) and D

voltage is

POUT

greater than the fixed threshold

011= D voltage is greater than the threshold (S2_TH)

MOUT

100= Do not use

101= Do not use

110= D

voltage is greater than the threshold (S2_TH)

POUT

111= Voltage is present after the port power switch is closed; next stimulus will not wait for this to be

removed

 2014-2015 Microchip Technology Inc.

DS20005346B-page 97

UCS1003-1/2/3

REGISTER 10-29: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 2 REGISTER

(ADDRESS 36h)

R-0

S2_R2<3:0>

R-0

S2_R2MAG<3:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

S2_R2MAG<3:0>: Stimulus 2 Response Magnitude bits

Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on

which response was selected. Data written to any field that is identified as “Do not use” will not be

accepted. The data will not be updated and the settings will remain set at the previous value.

For S2_R2 Settings 0000-0011:

The response is a voltage applied on the D

relative to ground.

/D

pins. The S2_R2MAG bits specify the voltage

POUT MOUT

0000 = Pull-down

0001 = 400 mV

0010 = 400 mV

0011 = 400 mV

0100 = 400 mV

0101 = 500 mV

0110 = 600 mV

0111 = 700 mV

1100 = 1800 mV

1101 = 2000 mV

1110 = 2200 mV

1111 = Do not use

1000 = 800 mV

1001 = 900 mV

1010 = 1400 mV

1011 = 1600 mV

For S2_R2 settings 0100, 0111, 1101-1111:

The response is a resistor connected on D

specify the resistor value.

/D

to GND or V

. The S2_R2MAG<3:0> bits

POUT MOUT

BUS

0000 = 1.8 k

0001 = 10 k

0010 = 15 k

0011 = 20 k

0100 = 25 k

0101 = 30 k

0110 = 40 k

0111 = 43 k

1100 = 100 k

1101 = 120 k

1110 = 150 k

1111 = Do not use

1000 = 50 k

1001 = 60 k

1010 = 75 k

1011 = 80 k

For S2_R2 Settings 0110, 1001, 1100:

The response is a voltage divider applied from V

to GND with the ‘center’ at D

/D

. The

BUS

POUT MOUT

S2_R2MAG bits<3:0> specify the minimum resistance of the voltage divider (sum of R1 + R2).

0000 = 93 k

0001 = 100 k

0010 = 125 k

0011 = 150 k

0100 = 200 k

0101 = 200 k

0110 = 200 k

0111 = 200 k

1000 = 93 k

1001 = 100 k

1010 = 125 k

1011 = 150 k

1100 = 200 k

1101 = 200 k

1110 = 200 k

1111 = Do not use

Note 1: If STIM2<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

POUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

POUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

POUT

2: If STIM2<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

MOUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

MOUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

MOUT

DS20005346B-page 98

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-29: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 2 REGISTER

(ADDRESS 36h) (CONTINUED)

bit 3-0

S2_R2<3:0>: Stimulus 2 Response Definition bits

0000= Removes previous response on D

and D

MOUT

POUT

(1)

0001= Applies voltage on D

0010= Applies voltage on D

0011= Applies voltage on D

POUT

MOUT

POUT

(2)

and D

MOUT

(1)

0100= Connects resistor from D

0101= Do not use

to GND

POUT

(1)

(2)

0110= Connects voltage divider from V

to GND with ‘center’ at D

POUT

BUS

(2)

0111= Connects resistor from D

1000= Do not use

to GND

MOUT

1001= Connects voltage divider from V

1010= Connects  200resistor from D

1011= Do not use

to GND with ‘center’ at D

to D

BUS

MOUT

POUT

MOUT

1100= Connects voltage divider from V

to GND with ‘center’ at D

and D

MOUT

BUS

1101= Connects resistor from D

to GND and D

to GND

POUT

MOUT

1110= If STIM2<2:0> = 000, the 15 kpull-down resistors applied to D

and D

during emu-

POUT

MOUT

lation Reset are not removed. If STIM2<2:0> = 111, the 15 kpull-down resistors applied to

and D during emulation Reset are removed. For all other STIM2<2:0> settings,

D

POUT

MOUT

whatever was applied is not changed.

1111= Same as ‘1110’ definition above

Note 1: If STIM2<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

POUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

POUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

POUT

2: If STIM2<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

MOUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

MOUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

MOUT

 2014-2015 Microchip Technology Inc.

DS20005346B-page 99

UCS1003-1/2/3

REGISTER 10-30: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 3 REGISTER

(ADDRESS 37h)⁽¹⁾

U-0

—

U-0

—

R-0

S2_TH<3:0>

R-0

S2_PUPD<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

S2_PUPD<1:0>: Stimulus 2 Pull-Down Current Magnitude bits

Determines the magnitude of the pull-down current applied on the D

and D

pins when the

POUT

MOUT

stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (‘0000b’). The bit

decode is as follows:

00= 10 µA

01= 50 µA

10= 100 µA

11= 150 µA

bit 3-0

S2_TH<3:0>: Stimulus 2 Threshold Value Definition bits

Defines the threshold value, as shown below, for the specified stimulus. If the stimulus V

voltage is

BUS

ready to be applied or applied (i.e., STIM2<2:0> = 000bor 111b), the threshold value is ignored.

0000= 400 mV

0001= 400 mV

0010= 400 mV

0011= 300 mV

0100= 400 mV

0101= 500 mV

0110= 600 mV

0111= 700 mV

1000= 800 mV

1001= 900 mV

1010= 1400 mV

1011= 1600 mV

1100= 1800 mV

1101= 2000 mV

1110= 2200 mV

1111= Do not use

Note 1: The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation

profile is applied within the DCE Cycle, these controls will not be updated and should be ignored. These

settings are only used by the BC1.2 CDP and DCP charger emulation profiles.

DS20005346B-page 100

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-31: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 4 REGISTER

(ADDRESS 38h)⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

R-0

—

S2_RATIO<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

S2_RATIO<2:0>: Stimulus 2 Voltage Divider Ratio bits

Determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a

voltage divider (i.e., S2_R2<3:0> = 0110b, 1001bor 1100b).

000= 0.25

001= 0.33

010= 0.4

011= 0.5

100= 0.54

101= 0.6

110= 0.66

111= Do not use

Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or

DCP charger emulation profile is applied, these controls will not be updated and should be ignored. These

settings are only used by the Legacy charger emulation profiles.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 101

UCS1003-1/2/3

REGISTER 10-32: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 1 REGISTER

(ADDRESS 39h)

U-0

—

R-0

bit 0

S3_TD_TYPE

S3_TD<2:0>

STIM3<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

S3_TD_TYPE: Stimulus 3 Timer Behavior Determination bit

1= The stimulus timer controls how long the response is applied after the stimulus is detected; the

response is applied immediately and held for the duration of the timer, then removed (if the stimulus

has been removed)

0= The stimulus timer is a delay from when the stimulus is detected until the response is performed

bit 5-3

S3_TD<2:0>: Stimulus 3 t

Determination Value bits

STIM_DEL

000= 0 ms

001= 1 ms

010= 5 ms

011= 10 ms

100= 20 ms

101= 40 ms

110= 80 ms

111= 100 ms

bit 2-0

STIM3<2:0>: Stimulus 3 Determination Usage bits

Determines the Stimulus 3 that is used as shown below. Note that the lower threshold for the window

comparator option is fixed at 400 mV and only applies to the D

pin. This setting cannot be used for

POUT

the D

port.

MOUT

000= V

voltage is ready to be applied before port power switch is closed; next stimulus will not wait

BUS

for this to be removed

001= D

voltage is greater than the threshold (S3_TH)

POUT

010= Window comparator; D

voltage is less than the threshold (S3_TH) and D

voltage is

POUT

greater than the fixed threshold

011= D voltage is greater than the threshold (S3_TH)

MOUT

100= Do not use

101= Do not use

110= D

voltage is greater than the threshold (S3_TH)

POUT

111= Voltage is present after the port power switch is closed; next stimulus will not wait for this to be

removed

DS20005346B-page 102

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-33: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 2 REGISTER

(ADDRESS 3Ah)

R-0

S3_R3<3:0>

R-0

S3_R3MAG<3:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

S3_R3MAG<3:0>: Stimulus 3 Response Magnitude bits

Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on

which response was selected. Data written to any field that is identified as “Do not use” will not be

accepted. The data will not be updated and the settings will remain set at the previous value.

For S3_R3 Settings 0000-0011:

The response is a voltage applied on the D

voltage relative to ground.

/D

pins. The S3_R3MAG<3:0> bits specify the

POUT MOUT

0000 = Pull Down

0001 = 400 mV

0010 = 400 mV

0011 = 400 mV

0100 = 400 mV

0101 = 500 mV

0110 = 600 mV

0111 = 700 mV

1100 = 1800 mV

1101 = 2000 mV

1110 = 2200 mV

1111 = Do not use

1000 = 800 mV

1001 = 900 mV

1010 = 1400 mV

1011 = 1600 mV

For S3_R3 Settings 0100, 0111, 1101-1111:

The response is a resistor connected on D

specify the resistor value.

/D

to GND or V

. The S3_R3MAG<3:0> bits

POUT MOUT

BUS

0000 = 1.8 k

0001 = 10 k

0010 = 15 k

0011 = 20 k

0100 = 25 k

0101 = 30 k

0110 = 40 k

0111 = 43 k

1100 = 100 k

1101 = 120 k

1110 = 150 k

1111 = Do not use

1000 = 50 k

1001 = 60 k

1010 = 75 k

1011 = 80 k

For S3_R3 settings 0110, 1001, 1100:

The response is a voltage divider applied from V

to GND with the ‘center’ at D

/D

. The

BUS

POUT MOUT

S3_R3MAG<3:0> bits specify the minimum resistance of the voltage divider (sum of R1 + R2).

0000 = 93 k

0001 = 100 k

0010 = 125 k

0011 = 150 k

0100 = 200 k

0101 = 200 k

0110 = 200 k

0111 = 200 k

1000 = 93 k

1001 = 100 k

1010 = 125 k

1011 = 150 k

1100 = 200 k

1101 = 200 k

1110 = 200 k

1111 = Do not use

Note 1: If STIM3<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

POUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

POUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

POUT

2: If STIM3<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

MOUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

MOUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

MOUT

 2014-2015 Microchip Technology Inc.

DS20005346B-page 103

UCS1003-1/2/3

REGISTER 10-33: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 2 REGISTER

(ADDRESS 3Ah) (CONTINUED)

bit 3-0

S3_R3<3:0>: Stimulus 3 Response Definition bits

0000= Removes previous response on D and D

POUT

MOUT

(1)

0001= Applies voltage on D

0010= Applies voltage on D

0011= Applies voltage on D

0100= Connects resistor from D

0101= Do not use

POUT

MOUT

POUT

(2)

and D

MOUT

to GND

(1)

POUT

(1)

to GND with ‘center’ at D

POUT

0110= Connects voltage divider from V

BUS

(2)

0111= Connects resistor from D

1000= Do not use

to GND

MOUT

(2)

1001= Connects voltage divider from V

to GND with “center” at D

BUS

MOUT

POUT

1010= Connects  200resistor from D

1011= Do not use

to D

POUT

MOUT

1100= Connects voltage divider from V

to GND with ‘center’ at D

and D

BUS

MOUT

1101= Connects resistor from D

to GND and D

to GND

POUT

MOUT

1110= If STIM3 = 000, the 15 kpull-down resistors applied to D

and D

during emulation

MOUT

POUT

reset are not removed. If STIM3<2:0> = 111, the 15 kpull-down resistors applied to D

POUT

and D

during emulation reset are removed. For all other STIM3 settings, whatever was

MOUT

applied is not changed.

1111= Same as ‘1110’ definition above

Note 1: If STIM3<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

POUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

POUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

POUT

2: If STIM3<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

MOUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

MOUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

MOUT

DS20005346B-page 104

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-34: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 3 REGISTER

(ADDRESS 3Bh)⁽¹⁾

U-0

—

U-0 R-0

R-0

S3_TH<3:0>

R-0

—

S3_PUPD<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

S3_PUPD<1:0>: Stimulus 3 Pull-Down Current Magnitude bits

Determines the magnitude of the pull-down current applied on the D

and D

pins when the

POUT

MOUT

stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (‘0000b’). The bit

decode is as follows:

00= 10 µA

01= 50 µA

10= 100 µA

11= 150 µA

bit 3-0

S3_TH<3:0>: Stimulus 3 Threshold Value Definition bits

Defines the threshold value, as shown below, for the specified stimulus. If the stimulus V

voltage is

BUS

ready to be applied or applied (i.e., STIM3<2:0> = 000bor 111b), the threshold value is ignored.

0000= 400 mV

0001= 400 mV

0010= 400 mV

0011= 300 mV

0100= 400 mV

0101= 500 mV

0110= 600 mV

0111= 700 mV

1000= 800 mV

1001= 900 mV

1010= 1400 mV

1011= 1600 mV

1100= 1800 mV

1101= 2000 mV

1110= 2200 mV

1111= Do not use

Note 1: The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation

profile is applied within the DCE Cycle, these controls will not be updated and should be ignored. These

settings are only used by the BC1.2 CDP and DCP charger emulation profiles.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 105

UCS1003-1/2/3

10.13 Custom Emulation Configuration Registers

Name

Bits

Address

Cof

Default

Custom Emulation Configuration

8

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

4Ch

R/W

01h

00h

Custom Emulation Stimulus 1 – Configuration 1

Custom Emulation Stimulus 1 – Configuration 2

Custom Emulation Stimulus 1 – Configuration 3

Custom Emulation Stimulus 1 – Configuration 4

Custom Emulation Stimulus 2 – Configuration 1

Custom Emulation Stimulus 2 – Configuration 2

Custom Emulation Stimulus 2 – Configuration 3

Custom Emulation Stimulus 2 – Configuration 4

Custom Emulation Stimulus 3 – Configuration 1

Custom Emulation Stimulus 3 – Configuration 2

Custom Emulation Stimulus 3 – Configuration 3

The Custom Emulation Configuration registers store

the values used by the custom charger emulation

circuitry. The custom charger emulation profile is set up

as three stimuli and the respective responses.

The contents of registers 40h to 4Ch are retained in

Sleep.

DS20005346B-page 106

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-35: CUSTOM EMULATION CONFIGURATION REGISTER (ADDRESS 40h)

U-0

—

U-0

—

R/W-0

R-0

R/W-1

CS_TO_DIS

CS_EM_TO<1:0>

CS_FRST

RESERVED CSEM_DIS

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5

Unimplemented: Read as ‘0’

CS_TO_DIS: Emulation Time-out Timer Disable bit

Disables the emulation time-out timer when the custom charger emulation profile is applied during the

(1)

DCE Cycle. If the EM_TO_DIS is set, this bit will have no effect.

1= The emulation time-out timer is disabled when the custom charger emulation profile is applied during

the DCE Cycle. When the custom charger emulation profile is being applied, the UCS1003-1 will be

constantly monitoring the I

current. When the I

current is greater than I

, regardless

BUS

BUS_CHG

of the reason, then the custom charger emulation profile will be accepted. If the portable device does

not draw more than I

cleared.

current, then the UCS1003-1 will continue waiting until this bit is

BUS_CHG

0= The emulation time-out timer is enabled when the custom charger emulation profile is applied during

the DCE Cycle and the EM_TO_DIS bit is not set

bit 4-3

CS_EM_TO<1:0>: t

Value During Custom Charger Emulation Value bits

EM_TIMEOUT

These bits are used when the custom charger emulation profile is used during the DCE Cycle.

00= 0.8s

01= 1.6s

10= 6.4s

11= 12.8s

bit 2

CS_FRST: Custom Charger Emulation Profile Disable bit

1= The custom charger emulation profile is the first of the profiles applied during the DCE Cycle

0= The custom charger emulation profile is the last of the profiles applied during the DCE Cycle

bit 1

bit 0

Reserved: Do not change. This bit will read ‘0’ and should not be written to a logic ‘1’.

CSEM_DIS: Custom Charger Emulation Profile Placement in DCE Cycle bit

1= The custom charger emulation profile is not enabled

0= The custom charger emulation profile is enabled

Note 1: If the CS_TO_DIS bit is set and the custom charger emulation profile was accepted during the DCE Cycle,

a removal is not detected. To avoid this issue, re-enable the emulation time-out after applying any test

profiles and charging with the ‘final’ profile.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 107

UCS1003-1/2/3

REGISTER 10-36: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 1 REGISTER

(ADDRESS 41h)

U-0

—

R/W-0

CS_S1TYPE

CS_S1_TD<2:0>

CS_STIM1<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

CS_S1TYPE: Stimulus 1 Timer Behavior Determination bit

1= The stimulus timer controls how long the response is applied after the stimulus is detected; the

response is applied immediately and held for the duration of the timer, then removed (if the stimulus

has been removed)

0= The stimulus timer is a delay from when the stimulus is detected until the response is performed

bit 5-3

CS_S1_TD<2:0>: Stimulus 1 t

Value Determination bits

STIM_DEL

000= 0 ms

001= 1 ms

010= 5 ms

011= 10 ms

100= 20 ms

101= 40 ms

110= 80 ms

111= 100 ms

bit 2-0

CS_STIM1<2:0>: Stimulus 1 Usage Determination bits

Determines the Stimulus 1 that is used as shown below. Note that the lower threshold for the window

comparator option is fixed at 400 mV and only applies to the D

pin. This setting cannot be used for

POUT

the D

port.

MOUT

000= V

voltage is ready to be applied before port power switch is closed; next stimulus will not wait

BUS

for this to be removed

001= D

voltage is greater than the threshold (CS_S1_TH)

POUT

010= Window comparator; D

voltage is lower than the threshold (CS_S1_TH) and D

voltage

POUT

is greater than the fixed threshold

011= D voltage is greater than the threshold (CS_S1_TH)

MOUT

100= Do not use

101= Do not use

110= D

111= V

voltage is greater than the threshold (CS_S1_TH)

voltage is present after port power switch is closed; next stimulus will not wait for this to be

POUT

BUS

removed

DS20005346B-page 108

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-37: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 2 REGISTER

(ADDRESS 42h)

R/W-0

bit 0

CS_S1_R1MAG<3:0>

CS_S1_R1<3:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

CS_S1_R1MAG<3:0>: Stimulus 1 Response Magnitude bits

Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on

which response was selected. Data written to any field that is identified as ‘Do not use’ will not be

accepted. The data will not be updated and the settings will remain set at the previous value.

For CS_S1_R1 Settings 0000-0011:

The response is a voltage applied on the D

voltage relative to ground.

/D

pins. The CS_S1_R1MAG<3:0> bits specify the

POUT MOUT

0000 = Pull-down

0001 = 400 mV

0010 = 400 mV

0011 = 400 mV

0100 = 400 mV

0101 = 500 mV

0110 = 600 mV

0111 = 700 mV

1100 = 1800 mV

1101 = 2000 mV

1110 = 2200 mV

1111 = Do not use

1000 = 800 mV

1001 = 900 mV

1010 = 1400 mV

1011 = 1600 mV

For CS_S1_R1 Settings 0100, 0111, 1101-1111:

The response is a resistor connected on D

specify the resistor value.

/D

to GND or V

. The CS_S1_R1MAG<3:0> bits

BUS

POUT MOUT

0000 = 1.8 k

0001 = 10 k

0010 = 15 k

0011 = 20 k

0100 = 25 k

0101 = 30 k

0110 = 40 k

0111 = 43 k

1100 = 100 k

1101 = 120 k

1110 = 150 k

1111 = Do not use

1000 = 50 k

1001 = 60 k

1010 = 75 k

1011 = 80 k

For CS_S1_R1 Settings 0110, 1001, 1100:

The response is a voltage divider applied from V

to GND with the ‘center’ at D

/D

. The

BUS

POUT MOUT

CS_S1_R1MAG<3:0> bits specify the minimum resistance of the voltage divider (sum of R1 + R2).

0000 = 93 k

0001 = 100 k

0010 = 125 k

0011 = 150 k

0100 = 200 k

0101 = 200 k

0110 = 200 k

0111 = 200 k

1000 = 93 k

1001 = 100 k

1010 = 125 k

1011 = 150 k

1100 = 200 k

1101 = 200 k

1110 = 200 k

1111 = Do not use

Note 1: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

POUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

POUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

POUT

2: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

MOUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

MOUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

MOUT

 2014-2015 Microchip Technology Inc.

DS20005346B-page 109

UCS1003-1/2/3

REGISTER 10-37: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 2 REGISTER

(ADDRESS 42h) (CONTINUED)

bit 3-0

CS_S1_R1<3:0>: Stimulus 1 Response Definition bits

0000= Removes previous response on D and D

POUT

MOUT

(1)

0001= Applies voltage on D

0010= Applies voltage on D

0011= Applies voltage on D

POUT

MOUT

POUT

(2)

and D

MOUT

(1)

0100= Connects resistor from D

0101= Do not use

to GND

POUT

(1)

(2)

0110= Connects voltage divider from V

to GND with ‘center’ at D

POUT

BUS

(2)

0111= Connects resistor from D

1000= Do not use

to GND

MOUT

1001= Connects voltage divider from V

1010= Connects  200resistor from D

1011= Do not use

to GND with ‘center’ at D

to D

BUS

MOUT

POUT

MOUT

1100= Connects voltage divider from V

to GND with ‘center’ at D

and D

MOUT

BUS

1101= Connects resistor from D

to GND and D

to GND

POUT

MOUT

1110= If CS_STIM1<2:0> = 000, the 15 kpull-down resistors applied to D

and D

during emu-

POUT

MOUT

lation Reset are not removed. If CS_STIM1<2:0> = 111, the 15 kpull-down resistors applied to

and D during emulation Reset are removed. For all other CS_STIM1<2:0> settings,

D

POUT

MOUT

whatever was applied is not changed.

1111= Same as ‘1110’ definition above

Note 1: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

POUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

POUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

POUT

2: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

MOUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

MOUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

MOUT

DS20005346B-page 110

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-38: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 3 REGISTER

(ADDRESS 43h)⁽¹⁾

U-0

—

U-0 R/W-0

R/W-0

bit 0

—

CS_S1_PUPD<1:0>

CS_S1_TH<3:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

CS_S1_PUPD<1:0>: Stimulus 1 Pull-Down Current Magnitude bits

Determines the magnitude of the pull-down current applied on the D

and D

pins when the

POUT

MOUT

stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (‘0000b’). The bit

decode is given below.

00= 10 µA

01= 50 µA

10= 100 µA

11= 150 µA

bit 3-0

CS_S1_TH<3:0>: Stimulus 3 Threshold Value Definition bits

Defines the threshold value, as shown below, for the specified stimulus. If the stimulus V

voltage is

BUS

ready to be applied or applied (i.e., CS_STIM1<2:0> = 000bor 111b), the threshold value is ignored.

0000= 400 mV

0001= 400 mV

0010= 400 mV

0011= 300 mV

0100= 400 mV

0101= 500 mV

0110= 600 mV

0111= 700 mV

1000= 800 mV

1001= 900 mV

1010= 1400 mV

1011= 1600 mV

1100= 1800 mV

1101= 2000 mV

1110= 2200 mV

1111= Do not use

Note 1: The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation

profile is applied within the DCE Cycle, these controls will not be updated and should be ignored. These

settings are only used by the BC1.2 CDP and DCP charger emulation profiles.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 111

UCS1003-1/2/3

REGISTER 10-39: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 4 REGISTER

(ADDRESS 44h)⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

bit 0

CS_S1_RATIO<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

CS_S1_RATIO<2:0>: Stimulus 1 Voltage Divider Ratio bits

Determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a

voltage divider (i.e., CS_S1_R1<3:0> = 0110b, 1001bor 1100b).

000= 0.25

001= 0.33

010= 0.4

011= 0.5

100= 0.54

101= 0.6

110= 0.66

111= Do not use

Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or

DCP charger emulation profile is applied, these controls will not be updated and should be ignored. These

settings are only used by the Legacy charger emulation profiles.

DS20005346B-page 112

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-40: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 1 REGISTER

(ADDRESS 45h)

U-0

—

R/W-0 R/W-0

CS_S2TYPE

R/W-0

bit 0

CS_S2_TD<2:0>

CS_STIM2<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

CS_S2TYPE: Stimulus 2 Timer Behavior Determination bit

1= The stimulus timer controls how long the response is applied after the stimulus is detected; the

response is applied immediately and held for the duration of the timer, then removed (if the stimulus

has been removed)

0= The stimulus timer is a delay from when the stimulus is detected until the response is performed

bit 5-3

CS_S2_TD<2:0>: Stimulus 2 t

Value Determination bits

STIM_DEL

000= 0 ms

001= 1 ms

010= 5 ms

011= 10 ms

100= 20 ms

101= 40 ms

110= 80 ms

111= 100 ms

bit 2-0

CS_STIM2<2:0>: Stimulus 2 Usage Determination bits

Determines the Stimulus 2 that is used as shown below. Note that the lower threshold for the window

comparator option is fixed at 400 mV and only applies to the D

pin. This setting cannot be used for

POUT

the D

port.

MOUT

000= V

voltage is ready to be applied before port power switch is closed; next stimulus will not wait

BUS

for this to be removed (default)

001= D voltage is greater than the threshold (CS_S2_TH)

POUT

010= Window comparator; D

voltage is less than the threshold (S1_TH) and D

voltage

POUT

greater than the fixed threshold

011= D voltage is greater than the threshold (CS_S2_TH)

MOUT

100= Do not use

101= Do not use

110= D

voltage is greater than the threshold (CS_S2_TH)

POUT

111= Voltage is present after the port power switch is closed; next stimulus will not wait for this to be

removed.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 113

UCS1003-1/2/3

REGISTER 10-41: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 2 REGISTER

(ADDRESS 46h)

R/W-0

bit 0

CS_S2_R2MAG<3:0>

CS_S2_R2<3:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

CS_S2_R2MAG<3:0>: Stimulus 2 Response Magnitude bits

Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on

which response was selected. Data written to any field that is identified as “Do not use” will not be

accepted. The data will not be updated and the settings will remain set at the previous value.

For CS_S2_R2 Settings 0000-0011:

The response is a voltage applied on the D

voltage relative to ground.

/D

pins. The CS_S2_R2MAG bits specify the

POUT MOUT

0000 = Pull Down

0001 = 400 mV

0010 = 400 mV

0011 = 400 mV

0100 = 400 mV

0101 = 500 mV

0110 = 600 mV

0111 = 700 mV

1100 = 1800 mV

1101 = 2000 mV

1110 = 2200 mV

1111 = Do not use

1000 = 800 mV

1001 = 900 mV

1010 = 1400 mV

1011 = 1600 mV

For CS_S2_R2 Settings 0100, 0111, 1101-1111:

The response is a resistor connected on D

specify the resistor value.

/D

to GND or V

. The CS_S2_R2MAG bits

POUT MOUT

BUS

0000 = 1.8 k

0001 = 10 k

0010 = 15 k

0011 = 20 k

0100 = 25 k

0101 = 30 k

0110 = 40 k

0111 = 43 k

1100 = 100 k

1101 = 120 k

1110 = 150 k

1111 = Do not use

1000 = 50 k

1001 = 60 k

1010 = 75 k

1011 = 80 k

For CS_S2_R2 Settings 0110, 1001, 1100:

The response is a voltage divider applied from V

to GND with “center” at D

/D

. The

BUS

POUT MOUT

CS_S2_R2MAG bits specify the minimum resistance of the voltage divider (Sum of R1 + R2):

0000 = 93 k

0001 = 100 k

0010 = 125 k

0011 = 150 k

0100 = 200 k

0101 = 200 k

0110 = 200 k

0111 = 200 k

1000 = 93 k

1001 = 100 k

1010 = 125 k

1011 = 150 k

1100 = 200 k

1101 = 200 k

1110 = 200 k

1111 = Do not use

Note 1: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

POUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

POUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

POUT

2: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

MOUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

MOUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

MOUT

DS20005346B-page 114

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-41: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 2 REGISTER

(ADDRESS 46h) (CONTINUED)

bit 3-0

CS_S2_R2<3:0>: Stimulus 2 Response Definition bits

0000= Removes previous response on D

and D

MOUT

POUT

(1)

0001= Applies voltage on D

0010= Applies voltage on D

0011= Applies voltage on D

POUT

MOUT

POUT

(2)

and D

.

MOUT

(1)

0100= Connects resistor from D

0101= Do not use

to GND

POUT

(1)

(2)

0110= Connects voltage divider from V

to GND with ‘center’ at D

POUT

BUS

(2)

0111= Connects resistor from D

1000= Do not use

to GND

MOUT

1001= Connects voltage divider from V

1010= Connects  200resistor from D

1011= Do not use

to GND with ‘center’ at D

to D

BUS

MOUT

POUT

MOUT

1100= Connects voltage divider from V

to GND with ‘center’ at D

and D

MOUT

BUS

1101= Connects resistor from D

to GND and D

to GND

POUT

MOUT

1110= If CS_STIM2<2:0> = 000, the 15 kpull-down resistors applied to D

and D

during emu-

POUT

MOUT

lation Reset are not removed. If CS_STIM2<2:0> = 111, the 15 kpull-down resistors applied to

and D during emulation Reset are removed. For all other CS_STIM2<2:0> settings,

D

POUT

MOUT

whatever was applied is not changed.

1111= Same as ‘1110’ definition above

Note 1: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

POUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

POUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

POUT

2: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

MOUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

MOUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

MOUT

 2014-2015 Microchip Technology Inc.

DS20005346B-page 115

UCS1003-1/2/3

REGISTER 10-42: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 3 REGISTER

(ADDRESS 47h)⁽¹⁾

U-0

—

U-0

—

R/W-0

bit 0

CS_S2_PUPD<1:0>

CS_S2_TH<3:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

CS_S2_PUPD<1:0>: Stimulus 2 Pull-Down Current Magnitude bits

Determines the magnitude of the pull-down current applied on the D

and D

pins when the

POUT

MOUT

stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (‘0000b’). The bit

decode is as follows:

00= 10 µA

01= 50 µA

10= 100 µA

11= 150 µA

bit 3-0

CS_S2_TH<3:0>: Stimulus 2 Threshold Value Definition bits

Defines the threshold value, as shown below, for the specified stimulus. If the stimulus V

voltage is

BUS

ready to be applied or applied (i.e., CS_STIM2<2:0> = 000bor 111b), the threshold value is ignored.

0000= 400 mV

0001= 400 mV

0010= 400 mV

0011= 300 mV

0100= 400 mV

0101= 500 mV

0110= 600 mV

0111= 700 mV

1000= 800 mV

1001= 900 mV

1010= 1400 mV

1011= 1600 mV

1100= 1800 mV

1101= 2000 mV

1110= 2200 mV

1111= Do not use

Note 1: The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation

profile is applied within the DCE Cycle, these controls will not be updated and should be ignored. These

settings are only used by the BC1.2 CDP and DCP charger emulation profiles.

DS20005346B-page 116

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-43: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 4 REGISTER

(ADDRESS 48h)⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

bit 0

—

CS_S2_RATIO<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

CS_S2_RATIO<2:0>: Stimulus 2 Voltage Divider Ratio bits

Determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a

voltage divider (i.e., CS_S2_R2<3:0> = 0110b, 1001bor 1100b).

000= 0.25

001= 0.33

010= 0.4

011= 0.5

100= 0.54

101= 0.6

110= 0.66

111= Do not use

Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or

DCP charger emulation profile is applied, these controls will not be updated and should be ignored. These

settings are only used by the Legacy charger emulation profiles.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 117

UCS1003-1/2/3

REGISTER 10-44: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 1 REGISTER

(ADDRESS 49h)

U-0

—

R/W-0

CS_S3TYPE

CS_S3_TD<2:0>

CS_STIM3<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

CS_S3TYPE: Stimulus 3 Timer Behavior Determination bit

1= The stimulus timer controls how long the response is applied after the stimulus is detected; the

response is applied immediately and held for the duration of the timer, then removed (if the stimulus

has been removed)

0= The stimulus timer is a delay from when the stimulus is detected until the response is performed

bit 5-3

CS_S3_TD<2:0>: Stimulus 3 t

Value Determination bits

STIM_DEL

000= 0 ms

001= 1 ms

010= 5 ms

011= 10 ms

100= 20 ms

101= 40 ms

110= 80 ms

111= 100 ms

bit 2-0

CS_STIM3<2:0>: Stimulus 3 Usage Determination bits

Determines the Stimulus 3 that is used as shown below. Note that the lower threshold for the window

comparator option is fixed at 400 mV and only applies to the D

pin. This setting cannot be used for

POUT

the D

port.

MOUT

000= V

voltage is ready to be applied before port power switch is closed; next stimulus will not wait

BUS

for this to be removed (default)

001= D

voltage is greater than the threshold (CS_S3_TH)

POUT

010= Window comparator; D

voltage is lower than the threshold (CS_S3_TH) and D

voltage

POUT

greater than the fixed threshold

011= D voltage is greater than the threshold (CS_S3_TH)

MOUT

100= Do not use

101= Do not use

110= D

voltage is greater than the threshold (CS_S3_TH)

POUT

111= Voltage is present after the port power switch is closed; next stimulus will not wait for this to be

removed.

DS20005346B-page 118

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-45: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 2 REGISTER

(ADDRESS 4Ah)

R/W-0

bit 0

CS_S3_R3MAG<3:0>

CS_S3_R3<3:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

CS_S3_R3MAG<3:0>: Stimulus 3 Response Magnitude bits

Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on

which response was selected. Data written to any field that is identified as “Do not use” will not be

accepted. The data will not be updated and the settings will remain set at the previous value.

For CS_S3_R3 Settings 0000-0011:

The response is a voltage applied on the D

voltage relative to ground.

/D

pins. The CS_S3_R3MAG<3:0> bits specify the

POUT MOUT

0000 = Pull-down

0001 = 400 mV

0010 = 400 mV

0011 = 400 mV

0100 = 400 mV

0101 = 500 mV

0110 = 600 mV

0111 = 700 mV

1100 = 1800 mV

1101 = 2000 mV

1110 = 2200 mV

1111 = Do not use

1000 = 800 mV

1001 = 900 mV

1010 = 1400 mV

1011 = 1600 mV

For CS_S3_R3 Settings 0100, 0111, 1101-1111:

The response is a resistor connected on D

specify the resistor value.

/D

to GND or V

. The CS_S3_R3MAG<3:0> bits

BUS

POUT MOUT

0000 = 1.8 k

0001 = 10 k

0010 = 15 k

0011 = 20 k

0100 = 25 k

0101 = 30 k

0110 = 40 k

0111 = 43 k

1100 = 100 k

1101 = 120 k

1110 = 150 k

1111 = Do not use

1000 = 50 k

1001 = 60 k

1010 = 75 k

1011 = 80 k

For CS_S3_R3 Settings 0110, 1001, 1100:

The response is a voltage divider applied from V

to GND with the ‘center’ at D

/D

. The

BUS

POUT MOUT

CS_S3_R3MAG<3:0> bits specify the minimum resistance of the voltage divider (sum of R1 + R2).

0000 = 93 k

0001 = 100 k

0010 = 125 k

0011 = 150 k

0100 = 200 k

0101 = 200 k

0110 = 200 k

0111 = 200 k

1000 = 93 k

1001 = 100 k

1010 = 125 k

1011 = 150 k

1100 = 200 k

1101 = 200 k

1110 = 200 k

1111 = Do not use

Note 1: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

POUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

POUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

POUT

2: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

MOUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

MOUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

MOUT

 2014-2015 Microchip Technology Inc.

DS20005346B-page 119

UCS1003-1/2/3

REGISTER 10-45: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 2 REGISTER

(ADDRESS 4Ah) (CONTINUED)

bit 3-0

CS_S3_R3<3:0>: Stimulus 3 Response Definition bits

0000= Removes previous response on D and D

POUT

MOUT

(1)

0001= Applies voltage on D

0010= Applies voltage on D

0011= Applies voltage on D

POUT

MOUT

POUT

(2)

and D

MOUT

(1)

0100= Connects resistor from D

0101= Do not use

to GND

POUT

(1)

(2)

0110= Connects voltage divider from V

to GND with ‘center’ at D

POUT

BUS

(2)

0111= Connects resistor from D

1000= Do not use

to GND

MOUT

1001= Connects voltage divider from V

1010= Connects  200resistor from D

1011= Do not use

to GND with ‘center’ at D

to D

BUS

MOUT

POUT

MOUT

1100= Connects voltage divider from V

to GND with ‘center’ at D

and D

MOUT

BUS

1101= Connects resistor from D

to GND and D

to GND

POUT

MOUT

1110= If CS_STIM3<2:0> = 000, the 15 kpull-down resistors applied to D

and D

during emu-

POUT

MOUT

lation Reset are not removed. If CS_STIM3<2:0> = 111, the 15 kpull-down resistors applied to

and D during emulation Reset are removed. For all other CS_STIM3<2:0> settings,

D

POUT

MOUT

whatever was applied is not changed.

1111= Same as ‘1110’ definition above

Note 1: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

POUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

POUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

POUT

2: If STIM1<2:0> = 000band no other response was applied to the D

pin, the 15 k pull-down resistor

MOUT

applied to the D

pin during emulation Reset is not removed. Otherwise, the previous response is left

MOUT

on the D

pin (if applicable) or the 15 k pull-down resistor is removed.

MOUT

DS20005346B-page 120

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

REGISTER 10-46: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 3 REGISTER

(ADDRESS 4Bh)⁽¹⁾

U-0

—

U-0 R/W-0

R/W-0

bit 0

—

CS_S3_PUPD<1:0>

CS_S3_TH<3:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

CS_S3_PUPD<1:0>: Stimulus 3 Pull-Down Current Magnitude bits

Determines the magnitude of the pull-down current applied on the D

and D

pins when the

POUT

MOUT

stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (‘0000b’). The bit

decode is as follows:

00= 10 µA

01= 50 µA

10= 100 µA

11= 150 µA

bit 3-0

CS_S3_TH<3:0>: Stimulus 3 Threshold Value Definition bits

Defines the threshold value, as shown below, for the specified stimulus. If the stimulus V

voltage is

BUS

ready to be applied or applied (i.e., CS_STIM3<2:0> = 000bor 111b), the threshold value is ignored.

0000= 400 mV

0001= 400 mV

0010= 400 mV

0011= 300 mV

0100= 400 mV

0101= 500 mV

0110= 600 mV

0111= 700 mV

1000= 800 mV

1001= 900 mV

1010= 1400 mV

1011= 1600 mV

1100= 1800 mV

1101= 2000 mV

1110= 2200 mV

1111= Do not use

Note 1: The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation

profile is applied within the DCE Cycle, these controls will not be updated and should be ignored. These

settings are only used by the BC1.2 CDP and DCP charger emulation profiles.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 121

UCS1003-1/2/3

REGISTER 10-47: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 4 REGISTER

(ADDRESS 4Ch)⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

bit 0

CS_S3_RATIO<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

CS_S3_RATIO<2:0>: Stimulus 3 Voltage Divider Ratio bits

Determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a

voltage divider (i.e., CS_S3_R3<3:0> = 0110b, 1001bor 1100b).

000= 0.25

001= 0.33

010= 0.4

011= 0.5

100= 0.54

101= 0.6

110= 0.66

111= Do not use

Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or

DCP charger emulation profile is applied, these controls will not be updated and should be ignored. These

settings are only used by the Legacy charger emulation profiles.

DS20005346B-page 122

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

10.14.1 APPLIED CURRENT-LIMITING

BEHAVIOR REGISTER

10.14 Current-Limiting Behavior

Configuration Registers

The Applied Current-Limiting Behavior register stores

the values used by the applied Current-Limiting mode

(Trip or CC) when the custom settings are not used.

The contents of this register are updated automatically

when charger emulation is completed.

Name

Bits Address Cof Default

Applied Current-Limiting

Behavior

8

50h

51h

R

82h

Custom Current-Limiting

Behavior Configuration

R/W

REGISTER 10-48: APPLIED CURRENT-LIMITING BEHAVIOR REGISTER (ADDRESS 50h)⁽¹⁾

R-1

SEL_VBUS_MIN<1:0>

bit 7

R-0

U-0

—

R-0

R-1

R-0

(1)

SEL_R2_IMIN<2:0>

RESERVED

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

SEL_VBUS_MIN<1:0>: V

Voltage Definition bits

BUS_MIN

00= 1.5V

01= 1.75V

10= 2.0V

11= 2.25V

bit 5

Unimplemented: Read as ‘0’

bit 4-2

SEL_R2_IMIN<2:0>: I

Current Definition bits

BUS_R2MIN

000= 120 mA

001= 570 mA

010= 1000 mA

011= 1350 mA

100= 1680 mA

101= 2050 mA

bit 1-0

Reserved: Do not change

Note 1: The values specified in this register are typical.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 123

UCS1003-1/2/3

(except Legacy 2), the custom charger emulation profile

or does not handshake as a dedicated charger (i.e., a

power thief).

10.14.2 CUSTOM CURRENT-LIMITING

BEHAVIOR CONFIGURATION

REGISTER

The contents of this register are retained in Sleep.

The Custom Current Limiting Behavior Configuration

Register allows programming of current limit parameters.

These controls are used when a portable device hand-

shakes using the Legacy charger emulation profiles

REGISTER 10-49: CUSTOM CURRENT-LIMITING BEHAVIOR CONFIGURATION REGISTER

(ADDRESS 51h)⁽¹⁾

R/W-1

CS_VBUS_MIN<1:0>

bit 7

R/W-0

U-0

—

R/W-0

R/W-1

R/W-0

CS_R2_IMIN<2:0>

RESERVED

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

CS_VBUS_MIN<1:0>: Custom V

Voltage Definition bits

BUS_MIN

Note that V

00= 1.5V

01= 1.75V

10= 2.0V

11= 2.25V

is checked even when operating with Trip Current Limiting.

BUS_MIN

bit 5

Unimplemented: Read as ‘0’

CS_R2_IMIN<2:0>: Custom I

bit 4-2

Threshold Definition bits

BUS_R2MIN

The default is 120 mA. This value is used under the following conditions: when a portable device handshakes

using the Legacy charger emulation profiles (except Legacy 2), the custom charger emulation profile or when

it does not handshake in DCE Cycle (i.e., a power thief). Under these conditions, the Current-Limiting mode

is determined by the relative value of I

and I . When I

< I

or I

> 1.68A, Trip

BUS_R2MIN

LIM

BUS_R2MIN

LIM

Current-Limiting mode is used; otherwise, CC mode is used.

Define the I current as follows:

BUS_R2MIN

000= 120 mA

001= 570 mA

010= 1000 mA

011= 1350 mA

100= 1680 mA

101= 2050 mA

bit 1-0

Reserved: Do not change

Note 1: The values specified in this register are typical.

10.15 Product ID Register

10.17 Revision Register

Name

Product ID

Bits Address Cof Default

FDh 4Eh

Name

Revision

Bits Address Cof Default

FFh 82h

8

R

8

R

The Product ID register stores a unique 8-bit value that

identifies the UCSXXXX Device Family.

The Revision register stores an 8-bit value that

represents the part revision.

10.16 Manufacturer ID Register

Name

Bits Address Cof Default

FEh 5Dh

Manufacturer ID

8

R

The Manufacturer ID register stores a unique 8-bit

value that identifies Microchip Technology Inc.

DS20005346B-page 124

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

11.0 UCS1003-1 COMMUNICATIONS

11.1 Operating Mode

Note:

If it is necessary to connect the

COMM_SEL/I

pin to V

via a pull-up

LIM

DD

resistor, it is recommended that this

resistor value not exceed 100 k.

The UCS1003-1 can operate in SMBus mode (see

Section 11.2 “SMBus Operating Mode”) or

Stand-Alone mode (see Section 11.3 “Stand-Alone

Operating Mode”). The resistor on the COMM_SEL/I

LIM

pin determines the operating mode and the hardware

setting, as shown in Table 11-1. Unless connected to

I

LIM

GND or V , the resistors in Table 11-1 are pull-down

DD

resistors.

TABLE 11-1: UCS1003-1 COMMUNICATION MODE AND I_LIMSELECTION

(1)

Selection Resistor ±5%

I

Setting

Communications Mode

LIM

GND

570 mA

1000 mA

1130 mA

1350 mA

1680 mA

2050 mA

2280 mA

SMBus – see Section 11.2.1.2

Stand-Alone mode

10 k pull-down

12 k pull-down

15 k pull-down

18 k pull-down

22 k pull-down

27 kpull-down

33 k pull-down

47 k pull-down

56 k pull-down

68 k pull-down

82 k pull-down

100 k pull-down

120 k pull-down

150 k pull-down

(If a pull-up resistor is used, its

2850 mA (3000 mA maximum)

570 mA

1000 mA

Stand-Alone mode

1130 mA

Stand-Alone mode

1350 mA

Stand-Alone mode

1680 mA

Stand-Alone mode

2050 mA

Stand-Alone mode

2280 mA

Stand-Alone mode

V

2850 mA (3000 mA maximum)

Stand-Alone mode

DD

value must not exceed 100 k.)

Note 1: Unless otherwise indicated, the values specified in this column are the typical I

in the Table 1-2.

LIM

 2014-2015 Microchip Technology Inc.

DS20005346B-page 125

UCS1003-1/2/3

11.2.1

SYSTEM MANAGEMENT BUS

11.2 SMBus Operating Mode

In SMBus mode, the UCS1003-1 communicates with a

host controller. The SMBus is a two-wire serial commu-

nication protocol between a computer host and its

peripheral devices. A detailed timing diagram is shown

in Figure 11-1. Stretching of the SMCLK signal is

supported; however, the UCS1003-1 will not stretch the

clock signal.

When the COMM_SEL/I

ground, or though a pull-down resistor with a value of

33 k or below as listed in Table 11-1, the UCS1003-1

communicates via the SMBus or I C communication

pin is connected directly to

LIM

2

protocols.

Note 1: Upon power-up, the UCS1003-1 will not

respond to any SMBus communications for

5.5 ms. After this time, full functionality is

available.

2: When in the Sleep state, the first SMBus

read command sent to the UCS1003-1

device address will wake it. Any data sent

to the UCS1003-1 will be ignored and any

data read from the UCS1003-1 should be

considered invalid. The UCS1003-1 will

be fully functional 3 ms after this first read

command is sent. See Section 5.1.2

“Sleep State Operation”.

T

LOW

T

HIGH

T

SU:STO

HD:STA

T

FALL

SMCLK

T

RISE

T

SU:DAT

SU:STA

T

HD:DAT

T

HD:STA

SMDATA

T_BUF

S

P

S - Start Condition

P - Stop Condition

FIGURE 11-1:

SMBus Timing Diagram.

The SMBus address is determined based on the resistor

connected on the SEL pin, as shown in Table 11-2.

11.2.1.1 SMBus Start Bit

The SMBus Start bit is defined as a transition of the

SMBus data line from a logic ‘1’ state to a logic ‘0’ state

while the SMBus clock line is in a logic ‘1’ state.

Note:

If it is necessary to connect the SEL pin to

via a resistor, the pull-up resistor may

V

DD

be any value up to 100 k.

11.2.1.2

SMBus Address and RD/WR Bit

The SMBus address byte consists of the 7-bit client

address followed by the RD/WR indicator bit. If this

RD/WR bit is a logic ‘0’, the SMBus host is writing data

to the client device. If this RD/WR bit is a logic ‘1’, the

SMBus host is reading data from the client device.

DS20005346B-page 126

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

TABLE 11-2: SEL PIN DECODE

Resistor (±5%)

PWR_EN Polarity

SMBus Address

GND

Active-Low

Active-High

1010_111 (R/W)

1010_110 (R/W)

1010_101 (R/W)

1010_100 (R/W)

0110_000 (R/W)

0110_001 (R/W)

0110_010 (R/W)

0110_011 (R/W)

0110_010 (R/W)

0110_001 (R/W)

0110_000 (R/W)

1010_100 (R/W)

1010_101 (R/W)

1010_110 (R/W)

1010_111 (R/W)

10 k pull-down

12 k pull-down

15 k pull-down

18 k pull-down

22 k pull-down

27 k pull-down

33 k pull-down

47 k pull-down

56 k pull-down

68 k pull-down

82 k pull-down

100 k pull-down

120 k pull-down

150 k pull-down

V

(If a pull-up resistor is used,

DD

its value must not exceed 100 k)

functionality defaults to disabled and can be enabled by

clearing the DIS_TO bit in the Emulation Configuration

register (Register 10-9).

11.2.1.3

SMBus Data Bytes

All SMBus data bytes are sent Most Significant bit

(MSb) first and composed of eight bits of information.

11.2.2

SMBUS AND I²C COMPATIBILITY

11.2.1.4

SMBus ACK and NACK Bits

2

The major differences between SMBus and I C devices

are highlighted in this section. For more information, refer

to the SMBus 2.0 and I C specifications.

The SMBus client will Acknowledge all data bytes that

it receives. This is done by the client device pulling the

SMBus data line low after the eighth bit of each byte

that is transmitted. This applies to both the write byte

and block write protocols.

2

• UCS1003-1 supports I C Fast mode at 400 kHz.

This covers the SMBus maximum time of 100 kHz.

• Minimum frequency for SMBus communications

is 10 kHz.

• The SMBus client protocol will reset if the clock is

held at a logic ‘0’ for longer than 30 ms. This time-

out functionality is disabled by default in the

UCS1003-1 and can be enabled by clearing the

By holding the SMBus data line high after the eighth data

bit has been sent, the host will NACK (not Acknowledge)

the last data byte to be received from the client. For the

block read protocol, the host will ACK each data byte

that it receives, except the last data byte.

2

DIS_TO bit. I C does not have a time-out.

11.2.1.5

SMBus Stop Bit

• Except when operating in Sleep mode, the

SMBus client protocol will reset if both the clock

and data lines are held at a logic ‘1’ for longer

than 200 µs (Idle condition). This function is dis-

abled by default in the UCS1003-1 device and

The SMBus Stop bit is defined as a transition of the

SMBus data line from a logic ‘0’ state to a logic ‘1’ state

while the SMBus clock line is in a logic ‘1’ state. When

the UCS1003-1 detects an SMBus Stop bit, and it has

been communicating with the SMBus protocol, it will

reset its client interface and prepare to receive further

communications.

2

can be enabled by clearing the DIS_TO bit. I C

does not have an Idle condition.

2

• I C devices do not support the Alert Response

Address functionality (which is optional for SMBus).

11.2.1.6

SMBus Time-out and Idle Reset

2

• I C devices support block read and write

The UCS1003-1 includes an SMBus time-out feature.

If the clock is held at logic ‘0’ for t , the device

can time-out and reset the SMBus interface. The

SMBus interface can also reset if both the clock and

data lines are held at a logic ‘1’ for t

Communication is restored with a Start condition. This

2

differently. I C protocol allows for an unlimited

TIMEOUT

number of bytes to be sent in either direction. The

SMBus protocol requires that an additional data

byte, indicating the number of bytes to read/write,

.

2

IDLE_RESET

is transmitted. The UCS1003-1 supports I C

formatting only.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 127

UCS1003-1/2/3

11.2.3

SMBUS PROTOCOLS

The UCS1003-1 is SMBus 2.0 protocol-compatible and

supports write byte, read byte, send byte and receive byte

as valid protocols, as shown in the following sections.

All protocols in these sections use the convention in

Table 11-3.

TABLE 11-3: PROTOCOL FORMAT

Data Sent to Device

Data Sent to the Host

Data Sent

11.2.3.1

SMBus Write Byte

The write byte is used to write one byte of data to a

specific register, as shown in Table 11-4.

TABLE 11-4: WRITE BYTE PROTOCOL

Client

Address

Register

Address

Register

Data

Start

WR

ACK

Stop

1  0

YYYY_YYY

0

XXh

0

XXh

0

0  1

11.2.3.2

SMBus Read Byte

The read byte protocol is used to read one byte of data

from the registers, as shown in Table 11-5.

TABLE 11-5: READ BYTE PROTOCOL

Client

Address

Register

Address

Client

Address

Register

Data

Start

WR ACK

ACK

Start



RD ACK

NACK

Stop

1



0

YYYY_YYY

0

XXh

0

1

0

YYYY_YYY

1

0

XXh

1

0  1

11.2.3.3

SMBus Send Byte

The send byte protocol is used to set the internal

address register pointer to the correct address location.

No data is transferred during the send byte protocol, as

shown in Table 11-6.

TABLE 11-6: SEND BYTE PROTOCOL

Register

Address

Start

Client Address

WR

ACK

Stop

1  0

YYYY_YYY

0

XXh

0

0  1

11.2.3.4

SMBus Receive Byte

The receive byte protocol is used to read data from a

register when the Internal Register Address Pointer is

known to be at the right location (e.g., set via send

byte). This is used for consecutive reads of the same

register, as shown in Table 11-7.

TABLE 11-7: RECEIVE BYTE PROTOCOL

Start

Client Address

RD

ACK

Register Data

NACK

Stop

1  0

YYYY_YYY

1

0

XXh

1

0  1

DS20005346B-page 128

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

11.2.4

I²C PROTOCOLS

Note:

When using the block write protocol, the

Internal Address Pointer will be automati-

cally incremented after every data byte is

received; it will wrap from FFh to 00h.

2

The UCS1003-1 supports I C block read and block

write. The protocols listed below use the convention

shown in Table 11-3.

11.2.4.1

Block Write

The block write is used to write multiple data bytes to a

group of contiguous registers, as shown in Table 11-8.

TABLE 11-8: BLOCK WRITE PROTOCOL

Client

Register

Address

Register

Data

Start

WR

ACK

0

Address

1  0

YYYY_YYY

0

XXh

0

XXh

Register

Data

Register

Data

Register

Data

ACK

0

. . .

ACK

Stop

0  1

XXh

0

XXh

. . .

XXh

0

11.2.4.2

Block Read

Note:

When using the block read protocol, the

Internal Address Pointer will be automati-

cally incremented after every data byte is

received; it will wrap from FFh to 00h.

The block read is used to read multiple data bytes from

a group of contiguous registers, as shown in Table 11-9.

TABLE 11-9: BLOCK READ PROTOCOL

Client

Address

Register

Address

Client

Address

Register

Data

Start

WR

0

ACK

Start

1  0

ACK

0

RD

ACK

1  0 YYYY_YYY

0

XXh

ACK

0

YYYY_YYY

1

0

NACK

1

XXh

Stop

0  1

Register

Data

Register

Data

Register

Data

ACK

Data

ACK

0

. . .

0

XXh

. . .

XXh

 2014-2015 Microchip Technology Inc.

DS20005346B-page 129

UCS1003-1/2/3

11.3 Stand-Alone Operating Mode

Note:

If it is necessary to connect the S0 or

LATCH pins to V via a pull-up resistor,

the pull-up resistor value should be

DD

Stand-Alone mode allows the UCS1003-1 to operate

without active SMBus/I C communications. Stand-Alone

mode can be enabled by connecting a pull-down resistor,

2

100 k in order to ensure the

V

IH

specification. Similarly, if it is necessary to

connect the S0 or LATCH pins to GND via

a pull-down resistor, the pull-down resistor

value should be 100 k in order to ensure

greater or equal to 47 k on the COMM_SEL/I pin, as

LIM

shown in Table 11-1.

When the device is configured to operate in Stand-

Alone mode, the Fault handling and Attach Detection

controls are determined via the LATCH and S0 pins, as

shown in Table 11-10.

the V specification.

IL

TABLE 11-10: STAND-ALONE FAULT AND ATTACH DETECTION SELECTION

LATCH Pin

S0 Pin

Command

Low

High

Low

High

Low

No Attach Detection. Auto-recovery upon Error Detection.

Attach Detection in the Detect power state. Auto-recovery upon Error Detection.

No Attach Detection. Error states are latched and require host to change the

PWR_EN control to recover from the Error state.

High

Attach Detection in the Detect power state. Error states are latched and

require host to change the PWR_EN control to recover from the Error state.

Note:

In the Stand-Alone operating mode, communications from and to the UCS1003-1 are limited to the

PWR_EN, EM_EN, M2, M1, ALERT# and A_DET# pins.

DS20005346B-page 130

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

12.0 PACKAGING INFORMATION

12.1 Package Marking Information

20-Lead QFN (4x4 mm)

Example

U1003-2

424KS9A

CTW

U1003-X

YWWNNNA

R<COO>

Legend:

X

Device version

Y

Year code (last digit of calendar year)

WW

NNN

R

Week code (week of January 1 is week “01”)

Alphanumeric traceability code

Revision

<COO>

Country of origin

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

e

3

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it

will be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 131

UCS1003-1/2/3

APPENDIX A: REVISION HISTORY

Revision B (December 2015)

The following is the list of modifications:

1. Updated Features to indicate EN/IEC 60950-1

(CB) certification.

Revision A (September 2014)

• Original Release of this Document.

 2014-2015 Microchip Technology Inc.

DS20005346B-page 133

UCS1003-1/2/3

NOTES:

DS20005346B-page 134

 2014-2015 Microchip Technology Inc.

UCS1003-1/2/3

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office

.

(1)

[X]

PART NO.

Device

-XX

Examples:

a) UCS1003-1-BP:

20-pin 4x4 QFN Lead-Free

ROHS Compliant Package.

Tape and

Reel

Package

b) UCS1003-1-BP-TR: 20-pin 4x4 QFN Lead-Free

ROHS Compliant Package,

Tape and Reel.

Device:

UCS1003-1:

UCS1003-2:

UCS1003-3:

USB Port Power Controller with Charger

Emulation

USB Port Power Controller with Charger

Emulation

USB Port Power Controller with Charger

Emulation

Note 1:

Tape and Reel identifier only appears in the

catalog part number description. This identi-

fier is used for ordering purposes and is not

printed on the device package. Check with

your Microchip sales office for package

availability for the Tape and Reel option.

Package:

BP = 20-pin, QFN Lead-Free ROHS Compliant Package

Tape and Reel Option: Blank = Standard packaging (tube or tray)

TR = Tape and Reel⁽¹⁾

 2014-2015 Microchip Technology Inc.

DS20005346B-page 135

UCS1003-1/2/3

NOTES:

DS20005346B-page 136

 2014-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,

LANCheck, MediaLB, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

32

The Embedded Control Solutions Company and mTouch are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,

CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit

Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,

KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,

Total Endurance, TSHARC, USBCheck, VariSense,

ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-0075-2

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEE OQ^®code hopping

L

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TS 16949 ==

 2014-2015 Microchip Technology Inc.

DS20005346B-page 137

Worldwide Sales and Service

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ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

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Tel: 480-792-7200

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Technical Support:

http://www.microchip.com/

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Tel: 86-592-2388138

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Tel: 852-2943-5100

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Tel: 949-462-9523

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07/14/15

DS20005346B-page 138

 2014-2015 Microchip Technology Inc.


型号：	UCS1003-2-BP-TR
厂家：	MICROCHIP
描述：	USB Port Power Controller with Charger Emulation
文件：	总138页 (文件大小：1647K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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