TN5325K1GP002 [MICROCHIP]
N-Channel Enhancement-Mode Vertical DMOS FET;
| 型号： | TN5325K1GP002 |
| 厂家： | 
MICROCHIP |
| 描述： | N-Channel Enhancement-Mode Vertical DMOS FET |
| 文件： | 总14页 (文件大小：596K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TN5325
N-Channel Enhancement-Mode Vertical DMOS FET
Features
General Description
• Low Threshold (2V Maximum)
The TN5325 is a low-threshold, Enhancement-mode
(normally-off) transistor that utilizes a vertical DMOS
structure and a well-proven silicon gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors and
the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of
all MOS structures, this device is free from thermal
runaway and thermally induced secondary breakdown.
• High Input Impedance and High Gain
• Free from Secondary Breakdown
• Low CISS and Fast Switching Speeds
Applications
• Logic-level Interfaces (Ideal for TTL and CMOS)
• Solid State Relays
Microchip’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications
where very low threshold voltage, high breakdown
voltage, high input impedance, low input capacitance
and fast switching speeds are desired.
• Battery-operated Systems
• Photo-voltaic Drives
• Analog Switches
• General Purpose Line Drivers
• Telecommunication Switches
Package Types
3-lead SOT-23 (TO-236AB)
3-lead TO-92
(Top view)
3-lead SOT-89 (243AA)
(Top view)
(Top view)
DRAIN
DRAIN
SOURCE
DRAIN
GATE
SOURCE
DRAIN
GATE
SOURCE
GATE
See Table 2-1, Table 2-2 and Table 2-3 for pin information.
2017 Microchip Technology Inc.
DS20005709A-page 1
TN5325
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Drain-to-source Voltage ....................................................................................................................................... BVDSX
Drain-to-gate Voltage .......................................................................................................................................... BVDGX
Gate-to-source Voltage ......................................................................................................................................... ±20V
Operating Ambient Temperature, TA ................................................................................................... –55°C to +150°C
Storage Temperature, TS ..................................................................................................................... –55°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, for all specifications TA = TJ = +25°C.
Parameter
Sym.
Min. Typ. Max. Unit
Conditions
Drain-to-source Breakdown Voltage
Gate Threshold Voltage
BVDSS
VGS(th)
∆VGS(th)
IGSS
250
0.6
—
—
—
—
—
—
—
—
2
V
V
VGS = 0V, ID = 100 µA
VGS = VDS, ID = 1 mA
Change in VGS(th) with Temperature
Gate Body Leakage
–4.5 mV/°C VGS = VDS, ID = 1 mA (Note 2)
—
100
1
nA
VGS = ± 20V, VDS = 0V
VGS = 0V, VDS = 100V
—
µA
—
10
VGS = 0V, VDS = Maximum Rating
Zero-gate Voltage Drain Current
IDSS
VDS = 0.8 Maximum Rating,
VGS = 0V, TA = 125°C (Note 2)
—
—
1
mA
A
0.6
1.2
—
—
—
—
—
—
—
—
8
VGS = 4.5V, VDS = 25V
On-state Drain Current
ID(ON)
V
GS = 10V, VDS = 25V
VGS = 4.5V, ID = 150 mA
GS = 10V, ID = 1A
Static Drain-to-source On-state
Resistance
RDS(ON)
Ω
—
7
V
Change in RDS(ON) with Temperature
∆
—
1
%/°C VGS = 4.5V, ID = 150 mA (Note 2)
RDS(ON)
Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty
cycle.
2: Specification is obtained by characterization and is not 100% tested.
DS20005709A-page 2
2017 Microchip Technology Inc.
TN5325
2
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, for all specifications TA = TJ = +25°C.
Parameter
Sym.
Min. Typ. Max. Unit
Conditions
mmho VDS = 25V, ID = 200 mA
GS = 0V,
Forward Transconductance
Input Capacitance
GFS
CISS
COSS
CRSS
td(ON)
tr
150
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
110
60
23
20
15
25
25
V
Common Source Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
pF
VDS = 25V,
f = 1 MHz
VDD = 25V,
Rise Time
ns
ID = 150 mA,
Turn-off Delay Time
td(OFF)
tf
RGEN = 25Ω
Fall Time
DIODE PARAMETER
Diode Forward Voltage Drop
Reverse Recovery Time
VSD
trr
—
—
—
1.8
—
V
VGS = 0V, ISD = 200 mA (Note 1)
VGS = 0V, ISD = 200 mA (Note 2)
300
ns
Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty
cycle.
2: Specification is obtained by characterization and is not 100% tested.
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min. Typ. Max. Unit
Conditions
TEMPERATURE RANGE
Operating Ambient Temperature
Storage Temperature
TA
TS
–55
–55
—
—
+150
+150
°C
°C
PACKAGE THERMAL RESISTANCE
3-lead SOT-23
JA
JC
JA
JC
JA
JC
—
—
—
—
—
—
350
200
170
125
78
—
—
—
—
—
—
°C/W
°C/W
3-lead TO-92
°C/W
°C/W
3-lead SOT-89
°C/W Note 1
°C/W
15
Note 1: Mounted on FR5 25 mm x 25 mm x 1.57 mm
THERMAL CHARACTERISTICS
( 1)
ID
ID
Power Dissipation at
TA = 25°C
( 1)
IDR
IDRM
(A)
Package
(Continuous)
(mA)
(Pulsed)
(A)
(mA)
(W)
3-lead SOT-23
150
215
316
0.4
0.8
1.5
0.36
150
215
316
0.4
0.8
1.5
3-lead TO-92
0.74
1.6 ( 2)
3-lead SOT-89
Note 1: ID (continuous) is limited by maximum TJ.
2: Mounted on FR5 board, 25 mm x 25 mm x 1.57 mm
2017 Microchip Technology Inc.
DS20005709A-page 3
TN5325
2.0
PIN DESCRIPTION
Table 2-1, Table 2-2 and Table 2-3 show the
description of pins in TN5325 3-lead SOT-23, 3-lead
TO-92 and 3-lead SOT-89, respectively. Refer to
Package Types for the location of pins.
TABLE 2-1:
Pin Number
SOT-23 PIN FUNCTION TABLE
Pin Name
Description
Description
Description
1
2
3
Gate
Source
Drain
Gate
Source
Drain
TABLE 2-2:
Pin Number
TO-92 PIN FUNCTION TABLE
Pin Name
1
2
3
Source
Gate
Source
Gate
Drain
Drain
TABLE 2-3:
Pin Number
SOT-89 PIN FUNCTION TABLE
Pin Name
1
2
3
4
Gate
Drain
Gate
Drain
Source
Drain
Source
Drain
DS20005709A-page 4
2017 Microchip Technology Inc.
TN5325
3.0
FUNCTIONAL DESCRIPTION
Figure 3-1 illustrates the switching waveforms and test
circuit for TN5325.
10V
VDD
RL
90%
INPUT
Pulse
10%
Generator
OUTPUT
0V
t(ON)
td(ON)
t(OFF)
td(OFF)
RGEN
tf
tr
VDD
OUTPUT
0V
INPUT
D.U.T.
10%
10%
90%
90%
FIGURE 3-1:
Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
RDS(ON)
(Maximum)
(Ω)
ID(ON)
(Minimum)
(A)
VGS(th)
(Maximum)
(V)
BVDSS/BVDGS
(V)
250V
7
1.2
2
2017 Microchip Technology Inc.
DS20005709A-page 5
TN5325
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
Example
N3C232
3-lead SOT-23
XXXNNN
3-lead TO-92
XXXXXX
Example
TN5325
e3
e3
XXXX
N3
YWWNNN
725698
3-lead SOT-89
Example
XXXXYWW
TN3C714
NNN
478
Legend: XX...X Product Code or Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( )
e
3
*
e
3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
DS20005709A-page 6
2017 Microchip Technology Inc.
TN5325
3-Lead TO-236AB (SOT-23) Package Outline (K1/T)
2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch
D
3
E1
E
Gauge
Plane
0.25
Seating
Plane
L
1
2
L1
e
b
e1
View B
Top View
View B
A
A2
A
Seating
Plane
A1
View A - A
Side View
A
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Symbol
A
0.89
-
A1
0.01
-
A2
b
0.30
-
D
E
2.10
-
E1
e
e1
L
L1
ș
0O
-
MIN
NOM
MAX
0.88
0.95
1.02
2.80
2.90
3.04
1.20
1.30
1.40
0.20†
0.50
0.60
Dimension
(mm)
0.95
BSC
1.90
BSC
0.54
REF
1.12
0.10
0.50
2.64
8O
JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
2017 Microchip Technology Inc.
DS20005709A-page 7
TN5325
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
DS20005709A-page 8
2017 Microchip Technology Inc.
TN5325
3-Lead TO-243AA (SOT-89) Package Outline (N8)
D
D1
C
H
E
E1
1
2
3
L
b
b1
A
e
e1
Top View
Side View
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Symbol
A
1.40
-
b
0.44
-
b1
0.36
-
C
0.35
-
D
4.40
-
D1
1.62
-
E
2.29
-
E1
2.00†
-
e
e1
H
3.94
-
L
0.73†
-
MIN
NOM
MAX
Dimensions
(mm)
1.50
BSC
3.00
BSC
1.60
0.56
0.48
0.44
4.60
1.83
2.60
2.29
4.25
1.20
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.
† This dimension differs from the JEDEC drawing
Drawings not to scale.
2017 Microchip Technology Inc.
DS20005709A-page 9
TN5325
NOTES:
DS20005709A-page 10
2017 Microchip Technology Inc.
TN5325
APPENDIX A: REVISION HISTORY
Revision A (April 2017)
• Converted Supertex Doc# DSFP-TN5325 to
Microchip DS20005709A
• Changed the part marking format
• Removed the N3 P003, N3 P005, N3 P013 and
N3 P014 media types
• Made minor text changes throughout the docu-
ment
2017 Microchip Technology Inc.
DS20005709A-page 11
TN5325
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Examples:
XX
PART NO.
Device
-
X
-
X
Package
Options
Environmental
Media Type
a) TN5325K1-G:
N-Channel Enhancement-
Mode Vertical DMOS FET,
3-lead SOT-23, 3000/Reel
Device:
TN5325
=
N-Channel Enhancement-Mode Vertical
DMOS FET
b) TN5325N3-G:
c) TN5325N3-G-P002:
d) TN5325N8-G:
N-Channel Enhancement-
Mode Ver-tical DMOS FET,
3-lead TO-92, 1000/Bag
Packages:
K1
N3
N8
=
=
=
3-lead SOT-23
3-lead TO-92
3-lead SOT-89
N-Channel Enhancement-
Mode Vertical DMOS FET,
3-lead TO-92, 2000/Reel
Environmental:
Media Types:
G
=
Lead (Pb)-free/RoHS-compliant Package
N-Channel Enhancement-
Mode Vertical DMOS FET,
3-lead SOT-89, 2000/Reel
(blank)
=
=
=
=
3000/Reel for a K1 Package
1000/Bag for an N3 Package
2000/Reel for an N8 Package
2000/Reel for an N3 Package
P002
DS20005709A-page 12
2017 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
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•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
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•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
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•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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Information contained in this publication regarding device
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CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
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QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ
CERTIFIEDꢀBYꢀDNVꢀ
© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-1556-5
== ISO/TSꢀ16949ꢀ==ꢀ
2017 Microchip Technology Inc.
DS20005709A-page 13
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11/07/16
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