TC835CBU_技术文档

TC835

Personal Computer Data Acquisition A/D Converter

Features

General Description

• Upgrade of Pin-Compatible TC7135, ICL7135

• 200kHz Operation

The TC835 is a low power, 4-1/2 digit (0.005%

resolution), BCD analog to digital converter (ADC) that

has been characterized for 200kHz clock rate opera-

tion. The five conversions per second rate is nearly

twice as fast as the ICL7135 or TC7135. The TC835,

like the TC7135, does not use the external diode resis-

tor rollover error compensation circuits required by the

ICL7135.

• Single 5V Operation With TC7660

• Multiplexed BCD Data Output

• UART and Microprocessor Interface

• Control Outputs for Auto-Ranging

• Input Sensitivity: 100µV

• No Sample and Hold Required

The multiplexed BCD data output is perfect for interfac-

ing to personal computers. The low cost, greater than

14-bit high-resolution and 100µV sensitivity makes the

TC835 exceptionally cost-effective.

Applications

• Personal Computer Data Acquisition

• Scales, Panel Meters, Process Controls

• HP-IL Bus Instrumentation

Microprocessor-based data acquisition systems are

supported by the BUSY and STROBE outputs, along

with the RUN/HOLD input of the TC835. The

OVERRANGE, UNDERRANGE, BUSY and RUN/

HOLD control functions, plus multiplexed BCD data

outputs, make the TC835 the ideal converter for µP-

based scales, measurement systems and intelligent

panel meters.

Device Selection Table

Part Number

Package

Temperature Range

TC835CBU

64-PinPQFP

0°C to +70°C

TC835CKW 44-PinPQFP

TC835CPI 28-PinPDIP

The TC835 interfaces with full function LCD and LED

display decoder/drivers. The UNDERRANGE and

OVERRANGE outputs may be used to implement an

auto-ranging scheme or special display functions.

Note: Tape and Reel available for 44-Pin PQFP

package.

2002 Microchip Technology Inc.

DS21478B-page 1

TC835

Package Type

28-Pin PDIP

44-Pin PQFP

UNDERRANGE

28

V-

1

2

27 OVERRANGE

REF IN

ANALOG

26

25

24

23

22

21

20

19

STROBE

RUN/HOLD

DIGTAL GND

POLARITY

CLOCK IN

BUSY

3

COM

44 43 42 41 40 39 38 37 36 35 34

INT OUT

AZ IN

4

NC

33

32

31

30

29

28

27

26

25

24

1

2

3

4

NC

5

NC

INT OUT

AZ IN

BUFF OUT

6

RUN/HOLD

DGND

POLARITY

CLK IN

BUSY

D1 (LSD)

D2

C

-

7

REF

TC835CPI

BUFF OUT

REF CAP–

C

REF

+

8

9

D1 (LSD)

D2

5

6

–INPUT

+INPUT

10

11

12

13

14

REF CAP+

–INPUT

+INPUT

V+

TC835CKW

18

17

16

D3

7

V+

(MSD) D5

(LSB) B1

B2

D4

8

B8 (MSD)

B4

9

15

NC

10

11

NC

23 NC

19 20 21 22

12 13 14 15 16 17 18

64-Pin PQFP

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

NC

1

2

48 NC

47

NC

3

46

NC

4

45

44

43

42

41

40

39

38

37

36

35

34

33

D3

D4

B3

5

6

7

B4

OVERRANGE

UNDERRANGE

SUB

8

B2

TC835CBU

9

SUB

B1

10

11

12

13

14

15

16

V–

REF IN

D5

NC

ANALOG COM

NC

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

1. NC = No internal connection.

NOTES:

2. Pins 9, 25, 40 and 56 are connected to the die substrate. The potential at these pins is approximately V+.

No external connections should be made.

DS21478B-page 2

2002 Microchip Technology Inc.

TC835

Typical Application

Address Bus

Control

+

5V

Data Bus

V+ REF CAP

BUF

-15V

+15V

HCTS157

AZ

POL

PA0

PA1

PA2

1Y

2Y

3Y

1B

2B

3B

S

OR

INT

UR

D5

B8

B4

B2

DG529

Channel 1

INPUT+

D

1A

2A

3A

A

B

Channel 2

Channel 3

Channel 4

TC835

R 6522 P

D

PA3

PA4

PA5

PA6

PA7

CA1

CA2

B1

WR

A A EN

D1

V

R

REF Voltage

D2

1 0

Input

D3

Differential

Multiplexer

D4

Analog

Common

STB

R/H

F

IN DGND

F

IN

-

5V

PB0

PB1 PB2 PB3

Channel Selection

2002 Microchip Technology Inc.

DS21478B-page 3

TC835

*Stresses above those listed under "Absolute Maximum Rat-

ings" may cause permanent damage to the device. These are

stress ratings only and functional operation of the device at

these or any other conditions above those indicated in the

operation sections of the specifications is not implied. Expo-

sure to Absolute Maximum Rating conditions for extended

periods may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings*

Positive Supply Voltage......................................... +6V

Negative Supply Voltage ........................................ -9V

Analog Input Voltage (Pin 9 or 10) ... V+ to V– (Note 2)

Reference Input Voltage (Pin 2) ..................... V+ to V–

+

Clock Input Voltage ........................................ 0V to V

Operating Temperature Range................0°C to +70°C

Storage Temperature Range ............. -65°C to +150°C

Package Power Dissipation (T ≤ 70°C)

A

28-Pin Plastic DIP ............................ 1.14Ω

44-Pin PQFP .................................... 1.00Ω

64-Pin PQFP .................................... 1.14Ω

TC835 ELECTRICAL SPECIFICATIONS

Electrical Characteristics: T_A= +25°C, F_CLOCK= 200kHz, V+ = +5V, V- = -5V, unless otherwise specified.

Symbol

Analog

Parameter

Min

Typ

Max

Unit

Test Conditions

Display Reading with Zero Volt Input

Zero Reading Temperature Coefficient

-0.0000 ±0.0000 +0.0000 Display Reading Note 3, Note 4

TC_Z

—

0.5

—

2

5

µV/°C

V_IN= 0V, (Note 5)

TC_FSFull-Scale Temperature Coefficient

ppm/°C

V_IN= 2V;

(Note 5, Note 6

NL

Nonlinearity Error

—

0.5

1

Count

LSB

Note 7

DNL

Differential Linearity Error

0.01

—

Display Reading in Ratiometric Operation

+0.9996 +0.9998 +1.0000 Display Reading V_IN= V_REF, (Note 3)

±FSE ± Full Scale Symmetry Error (Rollover Error)

—

0.5

1

Count

pA

–V_IN= +V_IN, (Note 8)

I_IN

e_N

Input Leakage Current

Noise

10

—

Note 4

15

µV_P-P

Peak to Peak Value not

Exceeded 95% of Time

Digital

I_IL

I_IH

Input Low Current

Input High Current

Output Low Voltage

—

10

0.08

0.2

100

10

0.4

5

µA

V

V_IN= 0V

V_IN= +5V

I_OL= 1.6mA

I_OH= 1mA

I_OH= 10µA

V_OL

V_OH

—

Output High Voltage;

B₁, B₂, B₄, B₈, D_{1 –}D₅

Busy, Polarity, Overrange,

Underrange, Strobe

2.4

4.9

4.4

V

4.99

5

V

f_CLK

Clock Frequency

0

200

1200

kHz

Note 10

Note 1: Functional operation is not implied.

2: Limit input current to under 100 µA if input voltages exceed supply voltage.

3: Full scale voltage = 2V.

4: V_IN= 0V.

5: 0°C ≤ T_A≤ +70°C.

6: External reference temperature coefficient less than 0.01ppm/°C.

7: -2V ≤ V_IN≤ +2V. Error of reading from best fit straight line.

8: |V_IN| = 1.9959.

9: Test circuit shown in Figure 1-1.

10: Specification related to clock frequency range over which the TC835 correctly performs its various functions. Increased

errors result at higher operating frequencies.

DS21478B-page 4

2002 Microchip Technology Inc.

TC835

TC835 ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: T_A= +25°C, F_CLOCK= 200kHz, V+ = +5V, V- = -5V, unless otherwise specified.

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Power Supply

V+

V–

I+

Positive Supply Voltage

Negative Supply Voltage

4

5

-5

6

-8

3

V

-3

—

V

Positive Supply Current

Negative Supply Current

Power Dissipation

1

mA

mΩ

f_CLK= 0Hz

I–

0.7

8.5

3

PD

30

Note 1: Functional operation is not implied.

2: Limit input current to under 100 µA if input voltages exceed supply voltage.

3: Full scale voltage = 2V.

4: V_IN= 0V.

5: 0°C ≤ T_A≤ +70°C.

6: External reference temperature coefficient less than 0.01ppm/°C.

7: -2V ≤ V_IN≤ +2V. Error of reading from best fit straight line.

8: |V_IN| = 1.9959.

9: Test circuit shown in Figure 1-1.

10: Specification related to clock frequency range over which the TC835 correctly performs its various functions. Increased

errors result at higher operating frequencies.

2002 Microchip Technology Inc.

DS21478B-page 5

TC835

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

Pin Number

28-Pin PDIP

Symbol

Description

1

2

V-

Negative power supply input.

External reference input.

REF IN

3

ANALOG COMMON Reference point for REF IN.

4

INT OUT

AZ IN

Integrator output. Integrator capacitor connection.

Auto zero input. Auto zero capacitor connection.

Analog input buffer output. Integrator resistor connection.

Reference capacitor input. Reference capacitor negative connection.

Reference capacitor input. Reference capacitor positive connection.

Analog input. Analog input negative connection.

Analog input. Analog input positive connection.

Positive power supply input.

5

6

BUFF OUT

7

C_REF

-

8

+

9

-INPUT

+INPUT

V+

10

11

12

13

14

15

16

17

18

19

20

21

D5

Digit drive output. Most Significant Digit (MSD)

Binary Coded Decimal (BCD) output. Least Significant Bit (LSB)

BCD output.

B1

B2

B4

BCD output.

B8

BCD output. Most Significant Bit (MSB)

Digit drive output.

D4

D3

Digit drive output.

D2

Digit drive output.

D1

Digit drive output. Least Significant Digit (LSD)

BUSY

Busy output. At the beginning of the signal-integration phase, BUSY goes High and

remains High until the first clock pulse after the integrator zero crossing.

22

23

CLOCK IN

POLARITY

Clock input. Conversion clock connection.

Polarity output. A positive input is indicated by a logic High output. The polarity output is

valid at the beginning of the reference integrate phase and remains valid until determined

during the next conversion.

24

25

DGND

Digital logic reference input.

RUN/HOLD

Run / Hold input. When at a logic High, conversions are performed continuously. A logic

Low holds the current data as long as the Low condition exists.

26

27

STROBE

Strobe output. The STROBE output pulses low in the center of the digit drive outputs.

OVERRANGE

Over range output. A logic High indicates that the analog input exceeds the full scale input

range.

28

UNDERRANGE

Under range output. A logic High indicates that the analog input is less than 9% of the full

scale input range.

DS21478B-page 6

2002 Microchip Technology Inc.

TC835

FIGURE 3-1:

BASIC DUAL SLOPE

CONVERTER

3.0

DETAILED DESCRIPTION

(All Pin Designations Refer to 28-Pin DIP)

Analog Input

Signal

Integrator

-

3.1

Dual Slope Conversion Principles

Comparator

-

The TC835 is a dual slope, integrating analog to digital

converter. An understanding of the dual slope conver-

sion technique will aid in following the detailed TC835

operational theory.

+

Switch

Drive

Clock

Phase

The conventional dual slope converter measurement

cycle has two distinct phases:

REF

Control

Logic

Control

Voltage

Polarity Control

1. Input signal integration

2. Reference voltage integration (de-integration)

Counter

Display

The input signal being converted is integrated for a fixed

time period, with time being measured by counting clock

pulses. An opposite polarity constant reference voltage

is then integrated until the integrator output voltage

returns to zero. The reference integration time is directly

proportional to the input signal.

V

IN

V

IN

≈ V

REF

≈ 1/2 V

REF

Fixed Variable

Signal Reference

Integrate Integrate

Time Time

In

a simple dual slope converter, a complete

conversion requires the integrator output to "ramp-up"

and "ramp-down."

3.2

TC835 Operational Theory

The TC835 incorporates a system zero phase and

integrator output voltage zero phase to the normal two

phase dual slope measurement cycle. Reduced sys-

tem errors, fewer calibration steps and a shorter over-

range recovery time result.

A simple mathematical equation relates the input sig-

nal, reference voltage and integration time:

EQUATION 3-1:

T

V

T

1

INT

REF DEINT

R

The TC835 measurement cycle contains four phases:

V

(T)DT =

IN

R

C

0

INT INT

1. System zero

where:

2. Analog input signal integration

3. Reference voltage integration

4. Integrator output zero

V

= Reference voltage

REF

T

= Signal integration time (fixed)

INT

Internal analog gate status for each phase is shown in

Table 3-1.

= Reference voltage integration time

(variable).

DEINT

For a constant V

:

3.2.1

SYSTEM ZERO

IN

During this phase, errors due to buffer, integrator and

comparator offset voltages are compensated for by

EQUATION 3-2:

V

T

REF DEINT

charging C (auto zero capacitor) with a compensat-

AZ

V

=

IN

t

ing error voltage. With a zero input voltage the

integrator output will remain at zero.

INT

The dual slope converter accuracy is unrelated to the

integrating resistor and capacitor values, as long as

they are stable during a measurement cycle. An

inherent benefit is noise immunity. Noise spikes are

integrated, or averaged, to zero during the integration

periods. Integrating ADCs are immune to the large

conversion errors that plague successive approxima-

tion converters in high noise environments (see

Figure 3-1).

The external input signal is disconnected from the inter-

nal circuitry by opening the two SW switches. The

I

internal input points connect to ANALOG COMMON.

The reference capacitor charges to the reference

voltage potential through SW . A feedback loop,

R

closed around the integrator and comparator, charges

the C

capacitor with a voltage to compensate for

AZ

buffer amplifier, integrator and comparator offset

voltages (see Figure 3-2).

2002 Microchip Technology Inc.

DS21478B-page 7

TC835

FIGURE 3-2:

SYSTEM ZERO PHASE

FIGURE 3-4:

REFERENCE VOLTAGE

INTEGRATION CYCLE

Analog

Input Buffer

SW

I

Analog

C

R

INT

+

+IN

SW

I

Input Buffer

C

R

INT

+

+IN

-

SW - SW

RI

+

RI

C

SZ

-

SW - SW

RI

+

RI

C

SW

IZ

SW

Z

SZ

-

C

Comparator

SW

REF

R

SW

IZ

SW

Z

+

REF

IN

-

+

Comparator

C

SW

R

REF

+

-

REF

IN

To Digital

Section

+

Integrator

SW

Z

-

SW

Z

To Digital

Section

Integrator

SW + SW

RI RI

-

SW

Z

Analog

Common

SW + SW

RI RI

-

Analog

Common

SW

1

SW

I

Switch Open

SW

1

–

IN

Switch Closed

SW

I

Switch Open

–

IN

Switch Closed

3.2.2

ANALOG INPUT SIGNAL

INTEGRATION

3.2.4

INTEGRATOR OUTPUT ZERO

The TC835 integrates the differential voltage between

the +INPUT and -INPUT pins. The differential voltage

must be within the device Common mode range (-1V

from either supply rail, typically). The input signal polarity

is determined at the end of this phase (see Figure 3-3).

This phase guarantees the integrator output is at 0V

when the system zero phase is entered and that the

true system offset voltages are compensated for. This

phase normally lasts 100 to 200 clock cycles. If an

overrange condition exists, the phase is extended to

6200 clock cycles (see Figure 3-5).

FIGURE 3-3:

INPUT SIGNAL

FIGURE 3-5:

INTEGRATOR OUTPUT

ZERO PHASE

INTEGRATION PHASE

Analog

Input Buffer

SW

I

C

R

INT

+

+IN

Analog

SW

I

Input Buffer

+

-

R

INT

C

INT

SW - SW

RI RI

+

IN

C

SZ

-

SW - SW

RI RI

+

SW

Z

IZ

C

SZ

-

C

Comparator

REF

SW

R

+

REF

IN

SW

Z

SW

IZ

+

-

C

SW

REF

Comparator

-

R

To

+

-

REF

IN

Integrator

Digital

Section

+

SW

Z

SW

Z

To Digital

Section

Integrator

SW + SW

RI RI

-

SW

Z

Analog

Common

Z

SW + SW

RI RI

-

SW

1

Analog

Common

SW

I

Switch Open

Switch Closed

–

IN

SW

1

SW

I

Switch Open

Switch Closed

–

IN

3.2.3

REFERENCE VOLTAGE

INTEGRATION

The previously charged reference capacitor is con-

nected with the proper polarity to ramp the integrator

output back to zero (see Figure 3-4). The digital reading

displayed is:

[Differential Input]

Reading = 10,000

V

REF

TABLE 3-1:

INTERNAL ANALOG GATE STATUS

Conversion Cycle Phase

SW_I

SW_RI

+

SW_RI

-

SW_Z

Closed

SW_R

SW₁

SW_IZ

Reference Figures

System Zero

Closed

Figure 3-2

Figure 3-3

Figure 3-4

Figure 3-5

Input Signal Integration

Reference Voltage Integration

Integrator Output Zero

Closed

Closed*

Closed

*Note:

Assumes a positive polarity input signal. SW_RIwould be closed for a negative input signal.

DS21478B-page 8

2002 Microchip Technology Inc.

TC835

4.3

Reference Voltage Input

(REF IN (Pin 2))

4.0

ANALOG SECTION

FUNCTIONAL DESCRIPTION

The REF IN input must be a positive voltage with

respect to ANALOG COMMON. A reference voltage

circuit is shown in Figure 4-1.

(In Reference to the 28-Pin Plastic Package)

4.1

Differential Inputs

(+INPUT (Pin 10) and

–INPUT (Pin 9))

FIGURE 4-1:

USING AN EXTERNAL

REFERENCE

The TC835 operates with differential voltages within

the input amplifier Common mode range. The input

amplifier Common mode range extends from 0.5V

below the positive supply to 1V above the negative

supply. Within this Common mode voltage range, an

86dB Common mode rejection ratio is typical.

V+

10k

MCP1525

TC835

2.5 V

REF

IN

The integrator output also follows the Common mode

voltage. The integrator output must not be allowed to

saturate. An example of a worst case condition would

be when a large positive Common mode voltage with a

near full scale negative differential input voltage is

applied. The negative input signal drives the integrator

positive when most of its swing has been used up by

the positive Common mode voltage. For these critical

applications, the integrator swing can be reduced to

less than the recommended 4V full scale swing, with

the effect of reduced accuracy. The integrator output

can swing within 0.3V of either supply without loss of

linearity.

10k

1µF

ANALOG

COMMON

Analog Ground

4.2

Analog Common Input (Pin 3)

ANALOG COMMON is used as the -INPUT return dur-

ing auto zero and de-integrate. If -INPUT is different

from ANALOG COMMON, a Common mode voltage

exists in the system. This signal is rejected by the

excellent CMRR of the converter. In most applications,

-INPUT will be set at a fixed, known voltage (power

supply common, for instance). In this application,

ANALOG COMMON should be tied to the same point,

thus removing the common-mode voltage from the

converter. The reference voltage is referenced to

ANALOG COMMON.

2002 Microchip Technology Inc.

DS21478B-page 9

TC835

5.0

DIGITAL SECTION

FUNCTIONAL DESCRIPTION

The major digital subsystems within the TC835 are

illustrated in Figure 5-1, with timing relationships

shown in Figure 5-2. The multiplexed BCD output data

can be displayed on LCD or LED. The digital section is

best described through a discussion of the control sig-

nals and data outputs.

FIGURE 5-1:

DIGITAL SECTION FUNCTIONAL DIAGRAM

Polarity

D5

MSB

D4

Digit

D3

Drive

D2

D1

13 B1

14 B2

15 B4

16 B8

Signal

LSB

Data

Multiplexer

Output

From

Analog

Section

Latch

Polarity

FF

Counters

Zero

Cross

Detect

Control Logic

27

24

22

Clock

25

RUN/

28

26

21

Busy

DGND

Overrange Underrange STROBE

In

HOLD

DS21478B-page 10

2002 Microchip Technology Inc.

TC835

FIGURE 5-2:

TIMING DIAGRAMS FOR

OUTPUTS

5.2

STROBE Output (Pin 26)

During the measurement cycle, the STROBE control

line is pulsed low five times. The five low pulses occur

Integrator

Output

in the center of the digit drive signals (D , D , D , D )

(see Figure 5-3).

1

2

3

5

Signal

Integrate

10,000

Counts

(Fixed)

System

Zero

Reference

Integrate

10,001

Counts

20,001

D₅(MSD) goes high for 201 counts when the measure-

ment cycles end. In the center of the D₅pulse, 101

clock pulses after the end of the measurement cycle,

the first STROBE occurs for one-half clock pulse. After

the D₅digit strobe, D₄goes high for 200 clock pulses.

The STROBE goes low 100 clock pulses after D₄goes

high. This continues through the D₁digit drive pulse.

Counts (Max)

Full Measurement Cycle

40,002 Counts

Busy

Overrange when

Applicable

Underrange when

Applicable

The digit drive signals will continue to permit display

scanning. STROBE pulses are not repeated until a new

measurement is completed. The digit drive signals will

not continue if the previous signal resulted in an

overrange condition.

Expanded Scale Below

Digit Scan

D5

D4

D3

D2

The active low STROBE pulses aid BCD data transfer

to UARTs, processors and external latches.

D1

100

First D5 of System Zero and

Reference Integrate One Count

Longer

*

Counts

STROBE

FIGURE 5-3:

STROBE SIGNAL LOW

FIVE TIMES PER

CONVERSION

Reference

Integrate

Signal

Integrate

Auto Zero

*

Digit Scan

D5

D4

D3

D2

D1

for Overrange

TC835

Outputs

*

Busy

End of Conversion

*

B1–B8

D3

Data

D2

Data

D1 (LSD)

Data

D5

Data

D5 (MSD)

Data

D4

Data

STROBE

Note Absence of

STROBE

200

Counts

5.1

RUN/HOLD Input (Pin 25)

201

Counts

200

D5

D4

D3

Counts

When left open, this pin assumes a logic "1" level. With

a RUN/HOLD = 1, the TC835 performs conversions

continuously, with a new measurement cycle beginning

every 40,002 clock pulses.

200

Counts

200

Counts

When RUN/HOLD changes to a logic "0," the measure-

ment cycle in progress will be completed, and data held

and displayed as long as the logic "0" condition exists.

200

Counts

D2

D1

A positive pulse (>300nsec) at RUN/HOLD initiates a

new measurement cycle. The measurement cycle in

progress when RUN/HOLD initially assumed the logic

"0" state must be completed before the positive pulse

200

Counts

*Delay between Busy going Low and First STROBE pulse is

dependent on Analog Input.

can be recognized as

command.

a single conversion run

5.3

BUSY Output

The new measurement cycle begins with a 10,001-

count auto zero phase. At the end of this phase, the

busy signal goes high.

At the beginning of the signal integration phase, BUSY

goes high and remains high until the first clock pulse

after the integrator zero crossing. BUSY returns to the

logic "0" state after the measurement cycle ends in an

overrange condition. The internal display latches are

loaded during the first clock pulse after BUSY and are

latched at the clock pulse end. The BUSY signal does

not go high at the beginning of the measurement cycle,

which starts with the auto zero cycle.

2002 Microchip Technology Inc.

DS21478B-page 11

TC835

5.4

OVERRANGE Output

6.0

6.1

TYPICAL APPLICATIONS

Component Value Selection

If the input signal causes the reference voltage integra-

tion time to exceed 20,000 clock pulses, the

OVERRANGE output is set to a logic "1." The over-

range output register is set when BUSY goes low, and

is reset at the beginning of the next reference

integration phase.

The integrating resistor is determined by the full-scale

input voltage and the output current of the buffer used

to charge the integrator capacitor. Both the buffer

amplifier and the integrator have a class A output

stage, with 100µA of quiescent current. A 20µA drive

current gives negligible linearity errors. Values of 5µA

to 40µA give good results. The exact value of an

integrating resistor for a 20µA current is easily calcu-

lated.

5.5

UNDERRANGE Output

If the output count is 9% of full scale or less (-1800

counts), the underrange register bit is set at the end of

BUSY. The bit is set low at the next signal integration

phase.

EQUATION 6-1:

5.6

POLARITY Output

Full scale voltage

R

=

INT

20µA

A positive input is registered by a logic "1" polarity

signal. The POLARITY bit is valid at the beginning of

Reference Integrate and remains valid until determined

during the next conversion.

6.1.1

INTEGRATING CAPACITOR

The product of integrating resistor and capacitor should

be selected to give the maximum voltage swing that

ensures the tolerance buildup will not saturate the inte-

grator swing (approximately 0.3V from either supply).

For ±5V supplies and ANALOG COMMON tied to sup-

ply ground, a ±3.5V to ±4V full-scale integrator swing is

adequate. A 0.10µF to 0.47µF is recommended. In

The POLARITY bit is valid even for a zero reading.

Signals less than the converter's LSB will have the sig-

nal polarity determined correctly. This is useful in null

applications.

5.7

Digit Drive Outputs

general, the value of C

is given by:

INT

Digit drive signals are positive going signals. The scan

sequence is D₅to D₁. All positive pulses are 200 clock

pulses wide, except D₅, which is 201 clock pulses wide.

EQUATION 6-2:

[10,000 x clock period] x I

All five digits are scanned continuously, unless an over-

range condition occurs. In an overrange condition, all

digit drives are held low from the final STROBE pulse

until the beginning of the next reference integrate

phase. The scanning sequence is then repeated. This

provides a blinking visual display indication.

INT

C

=

INT

Integrator output voltage swing

(10,000) (clock period) (20µA)

=

Integrator output voltage swing

A very important characteristic of the integrating capac-

itor is that it has low dielectric absorption to prevent

rollover or ratiometric errors. A good test for dielectric

absorption would be to use the capacitor with the input

tied to the reference. This ratiometric condition should

read half scale 0.9999, with any deviation probably due

to dielectric absorption. Polypropylene capacitors give

undetectable errors at reasonable cost. Polystyrene

and polycarbonate capacitors may also be used in less

critical applications.

5.8

BCD Data Outputs

The binary coded decimal (BCD) bits B , B , B , B are

8

4

2

1

positive-true logic signals. The data bits become active

simultaneously with the digit drive signals. In an

overrange condition, all data bits are at a logic "0" state.

6.1.2

AUTO ZERO AND REFERENCE

CAPACITORS

The size of the auto zero capacitor has some influence

on the noise of the system. A large capacitor reduces

the noise. The reference capacitor should be large

enough such that stray capacitance to ground from its

nodes is negligible.

The dielectric absorption of the reference capacitor and

auto zero capacitor are only important at power-on or

when the circuit is recovering from an overload.

DS21478B-page 12

2002 Microchip Technology Inc.

TC835

Smaller or cheaper capacitors can be used if accurate

readings are not required for the first few seconds of

recovery.

The conversion rate is easily calculated:

EQUATION 6-3:

Clock Frequency (Hz)

4000

6.1.3

REFERENCE VOLTAGE

Reading 1/sec =

The analog input required to generate a full scale out-

put is V = 2V

.

REF

IN

6.3

Power Supplies and Grounds

The stability of the reference voltage is a major factor in

the overall absolute accuracy of the converter. For this

reason, it is recommended that a high-quality reference

be used where high-accuracy absolute measurements

are being made.

6.3.1

POWER SUPPLIES

The TC835 is designed to work from ±5V supplies. For

single +5V operation, a TC7660 can provide a

–5V supply.

6.2

Conversion Timing

6.3.2

GROUNDING

6.2.1

LINE FREQUENCY REJECTION

Systems should use separate digital and analog

ground systems to avoid loss of accuracy.

A signal integration period at a multiple of the 60Hz line

frequency will maximize 60Hz "line noise" rejection. A

200kHz clock frequency will reject 60Hz and 400Hz

noise. This corresponds to five readings per second

(see Table 6-1 and Table 6-2).

6.4

High-Speed Operation

The maximum conversion rate of most dual-slope A/D

converters is limited by the frequency response of the

comparator. The comparator in this circuit follows the

integrator ramp with a 3µsec delay, and at a clock fre-

quency of 200kHz (5µsec period), half of the first refer-

ence integrate clock period is lost in delay. This means

that the meter reading will change from 0 to 1 with a

50µV input, 1 to 2 with 150µV, 2 to 3 at 250µV, etc. This

transition at midpoint is considered desirable by most

users, however, if the clock frequency is increased

appreciably above 200kHz, the instrument will flash "1"

on noise peaks even when the input is shorted.

TABLE 6-1:

CONVERSION RATE VS.

CLOCK FREQUENCY

Oscillator Frequency

(kHz)

Conversion Rate

(Conv./Sec.)

100

120

200

300

400

800

1200

2.5

3

5

7.5

10

20

30

For many dedicated applications where the input signal

is always of one polarity, the delay of the comparator

need not be a limitation. Since the nonlinearity and

noise do not increase substantially with frequency,

clock rates of up to ~1MHz may be used. For a fixed

clock frequency, the extra count or counts caused by

comparator delay will be a constant and can be

subtracted out digitally.

TABLE 6-2:

LINE FREQUENCY VS.

CLOCK FREQUENCY

Line Frequency Rejection

The clock frequency may be extended above 200kHz

without this error, however, by using a low-value resis-

tor in series with the integrating capacitor. The effect of

the resistor is to introduce a small pedestal voltage onto

the integrator output at the beginning of the reference

integrate phase. By careful selection of the ratio

between this resistor and the integrating resistor (a few

tens of ohms in the recommended circuit), the compar-

ator delay can be compensated and the maximum

clock frequency extended by approximately a factor of

3. At higher frequencies, ringing and second-order

breaks will cause significant nonlinearities in the first

few counts of the instrument.

Oscillator Frequency

(kHz)

60Hz

50Hz

400Hz

50.000

53.333

•

—

•

—

•

66.667

80.000

—

•

83.333

100.000

125.000

133.333

166.667

200.000

250.000

•

—

•

—

The minimum clock frequency is established by leak-

age on the auto zero and reference capacitors. With

most devices, measurement cycles as long as 10 sec-

onds give no measurable leakage error.

2002 Microchip Technology Inc.

DS21478B-page 13

TC835

The clock used should be free from significant phase or

frequency jitter. Several suitable low-cost oscillators

are shown in Section 6.0, Typical Applications. The

multiplexed output means that if the display takes sig-

nificant current from the logic supply, the clock should

have good PSRR.

course, the flip flop delays the true zero crossing by up

to one count in every instance. If a correction were not

made, the display would always be one count too high.

Therefore, the counter is disabled for one clock pulse

at the beginning of the reference integrate (de-inte-

grate) phase. This one-count delay compensates for

the delay of the zero crossing flip flop and allows the

correct number to be latched into the display. Similarly,

a one-count delay at the beginning of auto zero gives

an overload display of 0000 instead of 0001. No delay

occurs during signal integrate, so that true ratiometric

readings result.

6.5

Zero Crossing Flip-Flop

The flip flop interrogates the data once every clock

pulse after the transients of the previous clock pulse

and half-clock pulse have died down. False zero cross-

ings caused by clock pulses are not recognized. Of

FIGURE 6-1:

4-1/2 DIGIT ADC MULTIPLEXED COMMON ANODE LED DISPLAY

+5V

20 19 18 17 12

D1 D2 D3 D4 D5

INT OUT

4

5

0.33µF

1µF

AZ IN

4.7kΩ

1µF

23

7

POL

6

BUFF

b

c

7

OUT

C

-

100kΩ

REF

22

10

TC835

F

IN

200kHz

100kΩ

X7

8

C

+

REF

Blank MSD On Zero

+

+INPUT

9–15

5

Analog

16

15

14

13

6

2

1

7

1µF

Input

B8

D

C

B

A

9

3

RBI

DM7447A

–INPUT

–

B4

B2

B1

16

+5V

ANALOG

COMMON

REF

V–

IN

V+

1

2

11

V+

–5V

100kΩ

MCP1525

1µF

DS21478B-page 14

2002 Microchip Technology Inc.

TC835

FIGURE 6-2:

RC OSCILLATOR CIRCUIT

FIGURE 6-3:

COMPARATOR CLOCK

CIRCUITS

R

2

R

1

+5V

C

F

O

16kΩ

1kΩ

56kΩ

Gates are 74C04

2

3

+

8

V

OUT

0.22µF

7

LM311

-

1

R R

1

2

30kΩ

390pF

, R =

1. f

=

4

P

O

R + R

2C(0.41R + 0.7R )

1

2

P

1

a. If R₁= R₂= R₁, F≅ 0.55/RC

b. If R₂>> R₁, f ≅ 0.45/R₁C

c. If R₂<< R₁, f ≅ 0.72/R₁C

+5V

R2

100kΩ

R4

2kΩ

2. Examples:

a. f = 120kHz, C = 420pF

R₁= R₂≈ 10.9kΩ

C2

10pF

2

3

+

6

7

R2

100kΩ

V

LM311

-

OUT

b. f = 120kHz, C = 420pF, R₂= 50kΩ

R₁= 8.93kΩ

4

R3

50kΩ

1

C1

0.1µF

c. f = 120kHz, C = 220pF, R₂= 5kΩ

R = 27.3kΩ

1

FIGURE 6-4:

4-1/2 DIGIT ADC WITH MULTIPLEXED COMMON CATHODE LED DISPLAY

+5V

SET V

REF

= 1V

–5V

28

27

26

1

2

3

V-

UR

OR

TC835

MCP1525

100

REF IN

kΩ

150Ω

1µF

ANALOG

GND

STROBE

47

kΩ

10

11

9

8

7

6

5

4

3

2

1

Analog

GND

150Ω

25

24

23

22

21

20

4

5

6

7

8

9

INT

OUT

RUN/HOLD

DGND

POLARITY

CLK IN

BUSY

1µF

0.33µF

12

13

14

15

AZ IN

BUFF

OUT

MC14513

100 kΩ

1µF

C

+

REF

100

kΩ

+

SIG

C

-

+5V

16

17

(LSD) D1

D2

–INPUT

0.1

µF

10

11

12

19

18

17

+INPUT

IN

–

18

+5V

D3

V+

D4

D5 (MSD)

13

14

16

15

(MSB) B8

B4

B1 (LSB)

B2

F

OSC

= 200kHz

2002 Microchip Technology Inc.

DS21478B-page 15

TC835

FIGURE 6-5:

TEST CIRCUIT

–5V

TC835

SET V

= 1V

REF

IN

1

2

3

4

V

REF

V-

28

27

26

25

24

23

22

UNDERRANGE

100kΩ

REF IN

OVERRANGE

ANALOG

STROBE

COMMON

INT OUT

ANALOG GND

RUN/HOLD

DIGTAL GND

POLARITY

CLOCK IN

BUSY

0.47

1µF

5

6

µF

AZ IN

BUFF OUT

Clock

Input

100 kΩ

7

8

9

C

-

REF

100

Signal

Input

21 120kHz

1µF

kΩ

+

20

19

18

–INPUT

(LSD) D1

D2

0.1µF

10

11

12

13

14

+INPUT

V+

D3

+

5V

17

16

15

D5 (MSD)

D4

B1 (LSB)

B2

(MSB) B8

B4

DS21478B-page 16

2002 Microchip Technology Inc.

TC835

7.0

7.1

PACKAGING INFORMATION

Package Marking Information

Package marking data not available at this time.

7.2

Taping Forms

Component Taping Orientation for 64-Pin PQFP Devices

User Direction of Feed

PIN 1

W

P

Standard Reel Component Orientation

for TR Suffix Device

Carrier Tape, Number of Components Per Reel and Reel Size

Package

Carrier Width (W)

Pitch (P)

Part Per Full Reel

Reel Size

64-Pin PQFP

32 mm

24 mm

250

13 in

NOTE: Drawing does not represent total number of pins.

Component Taping Orientation for 44-Pin PQFP Devices

User Direction of Feed

PIN 1

W

P

Standard Reel Component Orientation

for TR Suffix Device

Carrier Tape, Number of Components Per Reel and Reel Size

Package

Carrier Width (W)

24 mm

Pitch (P)

16 mm

Part Per Full Reel

500

Reel Size

13 in

44-Pin PQFP

NOTE: Drawing does not represent total number of pins.

2002 Microchip Technology Inc.

DS21478B-page 17

TC835

7.3

Package Dimensions

28-Pin PDIP (Wide)

PIN 1

.555 (14.10)

.530 (13.46)

1.465 (37.21)

1.435 (36.45)

.610 (15.49)

.590 (14.99)

.200 (5.08)

.140 (3.56)

.040 (1.02)

.020 (0.51)

.015 (0.38)

.008 (0.20)

3˚MIN.

.150 (3.81)

.115 (2.92)

.700 (17.78)

.610 (15.50)

.110 (2.79)

.090 (2.29)

.070 (1.78)

.045 (1.14)

.022 (0.56)

.015 (0.38)

Dimensions: inches (mm)

44-Pin PQFP

7 ˚MAX.

.009 (0.23)

.005 (0.13)

PIN 1

.041 (1.03)

.026 (0.65)

.018 (0.45)

.012 (0.30)

.398 (10.10)

.390 (9.90)

.557 (14.15)

.537 (13.65)

.031 (0.80) TYP.

.010 (0.25) TYP.

.398 (10.10)

.390 (9.90)

.083 (2.10)

.075 (1.90)

.557 (14.15)

.537 (13.65)

.096 (2.45) MAX.

Dimensions: inches (mm)

DS21478B-page 18

2002 Microchip Technology Inc.

TC835

7.3

Package Dimensions (Continued)

7˚ MAX.

64-Pin PQFP

.009 (0.23)

.005 (0.13)

.041 (1.03)

.031 (0.78)

PIN 1

.018 (0.45)

.012 (0.30)

.555 (14.10)

.547 (13.90)

.687 (17.45)

.667 (16.95)

.031 (0.80) TYP.

.010 (0.25) TYP.

.555 (14.10)

.547 (13.90)

.120 (3.05)

.100 (2.55)

.687 (17.45)

.667 (16.95)

.130 (3.30) MAX.

Dimensions: inches (mm)

2002 Microchip Technology Inc.

DS21478B-page 19

TC835

NOTES:

DS21478B-page 20

2002 Microchip Technology Inc.

TC835

SALES AND SUPPORT

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

 2002 Microchip Technology Inc.

DS21478B-page 21

TC835

NOTES:

DS21478B-page 22

 2002 Microchip Technology Inc.

TC835

Information contained in this publication regarding device

applications and the like is intended through suggestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microchip Technology Incorporated with respect

to the accuracy or use of such information, or infringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,

KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip Tech-

nology Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode

and Total Endurance are trademarks of Microchip Technology

Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999

and Mountain View, California in March 2002.

The Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals,

non-volatile memory and analog products. In

addition, Microchip’s quality system for the

design and manufacture of development

systems is ISO 9001 certified.

2002 Microchip Technology Inc.

DS21478B-page 23

WORLDWIDE SALES AND SERVICE

Japan

AMERICAS

ASIA/PACIFIC

Microchip Technology Japan K.K.

Benex S-1 6F

3-18-20, Shinyokohama

Kohoku-Ku, Yokohama-shi

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Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Corporate Office

Australia

2355 West Chandler Blvd.

Microchip Technology Australia Pty Ltd

Suite 22, 41 Rawson Street

Epping 2121, NSW

Chandler, AZ 85224-6199

Tel: 480-792-7200 Fax: 480-792-7277

Technical Support: 480-792-7627

Web Address: http://www.microchip.com

Australia

Tel: 61-2-9868-6733 Fax: 61-2-9868-6755

Korea

Rocky Mountain

China - Beijing

Microchip Technology Korea

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Samsung-Dong, Kangnam-Ku

Seoul, Korea 135-882

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Tel: 480-792-7966 Fax: 480-792-7456

Microchip Technology Consulting (Shanghai)

Co., Ltd., Beijing Liaison Office

Unit 915

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Tel: 770-640-0034 Fax: 770-640-0307

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Co., Ltd., Shenzhen Liaison Office

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China - Hong Kong SAR

Italy

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Microchip Technology SRL

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India

Tel: 39-039-65791-1 Fax: 39-039-6899883

Microchip Technology Inc.

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Divyasree Chambers

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No. 11, O’Shaugnessey Road

Bangalore, 560 025, India

Tel: 91-80-2290061 Fax: 91-80-2290062

04/20/02

DS21478B-page 24

2002 Microchip Technology Inc.


型号：	TC835CBU
厂家：	MICROCHIP
描述：	Personal Computer Data Acquisition A/D Converter 个人计算机数据采集A / D转换器转换器计算机
文件：	总24页 (文件大小：543K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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