SST39WF800B-70-4I-MAQE-T [MICROCHIP]
IC,EEPROM,NOR FLASH,512KX16,CMOS,BGA,48PIN,PLASTIC;
| 型号： | SST39WF800B-70-4I-MAQE-T |
| 厂家： | 
MICROCHIP |
| 描述： | IC,EEPROM,NOR FLASH,512KX16,CMOS,BGA,48PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 闪存 |
| 文件： | 总33页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
The SST39WF800B is a 512K x16 CMOS Multi-Purpose Flash (MPF) manufac-
tured with proprietary, high-performance CMOS SuperFlash technology. The split-
gate cell design and thick-oxide tunneling injector attain better reliability and man-
ufacturability compared to alternate approaches. The SST39WF800B writes (Pro-
gram or Erase) with a 1.65-1.95V power supply. This device conforms to JEDEC
standard pin assignments for x16 memories
Features
• Organized as 512K x16
• Fast Erase and Word-Program
– Sector-Erase Time: 36 ms (typical)
– Block-Erase Time: 36 ms (typical)
– Chip-Erase Time: 140 ms (typical)
– Word-Program Time: 28 µs (typical)
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Superior Reliability
• Automatic Write Timing
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
– Internal VPP Generation
• End-of-Write Detection
• Low Power Consumption (typical values at 5 MHz)
– Toggle Bit
– Data# Polling
– Active Current: 5 mA (typical)
– Standby Current: 5 µA (typical)
• CMOS I/O Compatibility
• Sector-Erase Capability
– Uniform 2 KWord sectors
• JEDEC Standard
• Block-Erase Capability
– Flash EEPROM Pinouts and command sets
– Uniform 32 KWord blocks
• Packages Available
• Fast Read Access Time
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm) Micro-Package
– 48-ball XFLGA (5mm x 6mm) Micro-Package
– 48-ball XFLGA (4mm x 6mm) Micro-Package
– 70 ns
• Latched Address and Data
• All devices are RoHS compliant
www.microchip.com
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Product Description
The SST39WF800B is a 512K x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST proprie-
tary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tun-
neling injector attain better reliability and manufacturability compared to alternate approaches. The
SST39WF800B writes (Program or Erase) with a 1.65-1.95V power supply. This device conforms to
JEDEC standard pin assignments for x16 memories.
The SST39WF800B features high-performance Word-Programming which provides a typical Word-
Program time of 28 µsec. It uses Toggle Bit or Data# Polling to detect the completion of the Program or
Erase operation. On-chip hardware and software data protection schemes protects against inadvertent
writes. Designed, manufactured, and tested for a wide spectrum of applications, the SST39WF800B is
offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than
100 years.
The SST39WF800B is suited for applications that require convenient and economical updating of pro-
gram, configuration, or data memory. It significantly improves performance and reliability of all system
applications while lowering power consumption. It inherently uses less energy during Erase and Pro-
gram than alternative flash technologies. When programming a flash device, the total energy con-
sumed is a function of the applied voltage, current, and time of application. For any given voltage
range, SuperFlash technology uses less current to program and has a shorter erase time; therefore,
the total energy consumed during any Erase or Program operation is less than alternative flash tech-
nologies. These devices also improve flexibility while lowering the cost for program, data, and configu-
ration storage applications.
SuperFlash technology provides fixed Erase and Program times independent of the number of Erase/
Program cycles that have occurred. Consequently, the system software or hardware does not have to
be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program
times increase with accumulated Erase/Program cycles.
To meet surface mount requirements, the SST39WF800B is offered in 48-ball TFBGA, 48-ball
WFBGA, and a 48-ball XFLGA packages. See Figures 2 and 3 for pin assignments and Table 1 for pin
descriptions.
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
2
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Block Diagram
SuperFlash
X-Decoder
Memory
Memory Address
Address Buffer Latches
Y-Decoder
CE#
I/O Buffers and Data Latches
Control Logic
OE#
WE#
DQ - DQ
15
0
1344 B1.0
Figure 1: Functional Block Diagram
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
3
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Pin Assignments
TOP VIEW (balls facing down)
SST39WF800B
6
5
4
3
2
1
A2
A1
A0
A4
A3
A6
A7
A17 NC
NC
NC WE# NC
NC A10 A13 A14
A8 A12 A15
A9
A11
A5 A18
CE# DQ8 DQ10
OE# DQ9 NC
DQ0 DQ1 DQ2 DQ3
DQ4 DQ11 A16
V
NC DQ5 DQ6 DQ7
SS
V
DD
DQ12 DQ13 DQ14 DQ15
V
SS
A B C D
E
F
G H
J
K
L
1344 48-wfbga M2Q P02.0
Figure 2: Pin Assignments for 48-Ball WFBGA and 48-Ball XFLGA
TOP VIEW (balls facing down)
SST39WF800B
6
A12 A14 A15 A16 NC
A8 A10 A11 DQ7 DQ14
A13
A9
DQ15
V
SS
5
4
3
2
1
DQ13 DQ6
NC
NC
NC DQ5 DQ12
V
WE#
NC
DQ4
DD
NC A18 NC DQ2 DQ10
DQ11 DQ3
A5 DQ0 DQ8
DQ9 DQ1
A17 A6
A7
A4
A2
A1
A0
CE#
A3
OE#
V
SS
A
B
C
D
E
F
G
H
1344 48-tfbga P01.0
Figure 3: Pin Assignments for 48-ball TFBGA
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
4
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Table 1: Pin Description
Symbol
AMS1-A0
Pin Name
Functions
Address Inputs
To provide memory addresses. During Sector-Erase AMS-A11 address lines will
select the sector. During Block-Erase AMS-A15 address lines will select the
block.
DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
OE#
WE#
VDD
VSS
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage:
1.65-1.95V for SST39WF800B
No Connection
Unconnected pins.
T1.0 25031
1. AMS = Most significant address
AMS = A18 for SST39WF800B
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
5
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Device Operation
Commands, which are used to initiate the memory operation functions of the device, are written to the
device using standard microprocessor write sequences. A command is written by asserting WE# low
while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39WF800B is controlled by CE# and OE#; both have to be low for the
system to obtain data from the outputs.
CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is
consumed.
OE# is the output control and is used to gate data from the output pins. The data bus is in high imped-
ance state when either CE# or OE# is high. See Figure 5.
Word-Program Operation
The SST39WF800B is programmed on a word-by-word basis. The sector where the word exists must
be fully erased before programming.
Programming is accomplished in three steps:
1. Load the three-byte sequence for Software Data Protection.
2. Load word address and word data. During the Word-Program operation, the addresses
are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever occurs first.
3. Initiate the internal Program operation after the rising edge of the fourth WE# or CE#,
whichever occurs first. Once initiated, the Program operation will be completed within 40
µs. See Figures 6 and 7 for WE# and CE# controlled Program operation timing diagrams
and Figure 17 for flowcharts.
During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the inter-
nal Program operation, the host is free to perform additional tasks. Any commands issued during the
internal Program operation are ignored.
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
6
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Sector-/Block-Erase Operation
The SST39WF800B offers both Sector-Erase and Block-Erase modes which allow the system to erase
the device on a sector-by-sector, or block-by-block, basis.
The sector architecture is based on uniform sector size of 2 KWord. Initiate the Sector-Erase operation
by executing a six-byte command sequence with Sector-Erase command (30H) and sector address
(SA) in the last bus cycle.
The Block-Erase mode is based on uniform block size of 32 KWord. Initiate the Block-Erase operation
by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA)
in the last bus cycle.
The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command
(30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins
after the sixth WE# pulse.
The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See
Figures 10 and 11 for timing waveforms. Any commands issued during the Sector- or Block-Erase
operation are ignored.
Chip-Erase Operation
The SST39WF800B provides a Chip-Erase operation, which allows the user to erase the entire mem-
ory array to the ‘1’ state. This is useful when the entire device must be quickly erased.
Initiate the Chip-Erase operation by executing a six-byte command sequence with Chip-Erase com-
mand (10H) at address 5555H in the last byte sequence.
The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. Dur-
ing the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command
sequence, Figure 9 for the timing diagram, and Figure 20 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Write Operation Status Detection
To optimize the system write cycle time, the SST39WF800B provides two software means to detect the
completion of a Program or Erase write cycle. The software detection includes two status bits—Data#
Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge
of WE#, which initiates the internal Program or Erase operation.
The completion of the nonvolatile Write is asynchronous with the system; therefore, either a Data#
Polling or Toggle Bit read may occur simultaneously with the completion of the Write cycle. If this
occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either DQ7
or DQ6. To prevent spurious rejection in the event of an erroneous result, the software routine must
include a loop to read the accessed location an additional two (2) times. If both Reads are valid, then
the device has completed the Write cycle, otherwise the rejection is valid.
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
7
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Data# Polling (DQ7)
When the SST39WF800B is in the internal Program operation, any attempt to read DQ7 will produce
the complement of the true data. Once the Program operation is complete, DQ7 will produce true data.
Although DQ7 may have valid data immediately following the completion of an internal Write operation,
the remaining data outputs may still be invalid. Valid data on the entire data bus will appear in subse-
quent successive Read cycles after an interval of 1 µs. During an internal Erase operation, any attempt
to read DQ7 will produce a ‘0’. Once the internal Erase operation is complete, DQ7 will produce a ‘1’.
The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 8 for Data# Polling timing diagram and Figure 18 for a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce
alternating ‘1’s and ‘0’s, i.e., toggling between ‘1’ and ‘0’.
When the Program or Erase operation is complete, the DQ6 bit will stop toggling and the device is
ready for the next operation.
The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse.
See Figure 0-1 for Toggle Bit timing diagram and Figure 18 for a flowchart.
Data Protection
The SST39WF800B provides both hardware and software features to protect nonvolatile data from
inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.0V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39WF800B provides the JEDEC approved Software Data Protection scheme for all data alter-
ation operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-
byte sequence. The three-byte load sequence is used to initiate the Program operation, providing opti-
mal protection from inadvertent Write operations, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of six-byte sequence. This group of devices are shipped
with the Software Data Protection permanently enabled. See Table 4 for the specific software com-
mand codes. During SDP command sequence, invalid commands will abort the device to Read mode
within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command
sequence.
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
8
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Common Flash Memory Interface (CFI)
The SST39WF800A contains the CFI information that describes the characteristics of the device, and
supports both the original SST CFI Query mode implementation for compatibility with existing SST
devices, as well as the general CFI Query mode.
To enter the SST CFI Query mode, the system must write the three-byte sequence, same as the Prod-
uct ID Entry command, with 98H (CFI Query command) to address 5555H in the last byte sequence.
To enter the general CFI Query mode, the system must write a one-byte sequence using the Entry
command with 98H to address 55H.
Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in
Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI
Query mode.
Product Identification
The Product Identification mode identifies the device as the SST39WF800B and manufacturer as SST.
This mode is accessed by software operations. Use Software Product Identification operation to iden-
tify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For
details, see Table 4 for software operation, Figure 12 for the Software ID Entry and Read timing dia-
gram, and Figure 19 for the Software ID Entry command sequence flowchart.
Table 2: Product Identification Table
Address
Data
Manufacturer’s ID
Device ID
0000H
00BFH
SST39WF800B
0001H
273EH
T2.0 25031
Product Identification Mode Exit/CFI Mode Exit
To return to the standard Read mode, exit the Software Product Identification mode. Issue the Soft-
ware ID Exit command sequence which returns the device to the Read mode.
The Software ID Exit command may also be used to reset the device to the Read mode after any inad-
vertent transient condition that causes the device to behave abnormally, e.g., not read correctly.
The Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See
Table 4 for software command codes, Figure 14 for timing waveform, and Figure 19 for a flowchart.
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
9
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Operations
Table 3: Operation Modes Selection
Mode
CE#
VIL
OE#
VIL
WE# DQ
Address
AIN
Read
VIH
VIL
VIL
DOUT
Program
Erase
VIL
VIH
VIH
DIN
X1
AIN
VIL
Sector or Block address,
XXH for Chip-Erase
Standby
VIH
X
X
VIL
X
X
X
High Z
X
X
X
Write Inhibit
High Z/ DOUT
High Z/ DOUT
X
VIH
Product Identification
Software Mode
VIL
VIL
VIH
See Table 4
T3.0 25031
1. X can be VIL or VIH, but no other value.
Table 4: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
5555H AAH 2AAAH 55H 5555H A0H Data
WA3
Word-Program
Sector-Erase
Block-Erase
Chip-Erase
4
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
SAX
30H
50H
4
BAX
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry5,6 5555H AAH 2AAAH 55H 5555H 90H
SST CFI Query
Entry5
5555H AAH 2AAAH 55H 5555H 98H
General CFI Query
Mode
Software ID Exit7/
CFI Exit
55H
98H
F0H
XXH
Software ID Exit7/
CFI Exit
5555H AAH 2AAAH 55H 5555H F0H
T4.0 25031
1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence.
AMS = Most significant address
AMS = A18 for SST39WF800B
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence
3. WA = Program word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX for Block-Erase; uses AMS-A15 address lines
5. The device does not remain in Software Product ID mode if powered down.
6. With AMS-A1 = 0;
SST Manufacturer’s ID = 00BFH, is read with A0 = 0,
SST39WF800B Device ID = 273EH, is read with A0 = 1.
7. Both Software ID Exit operations are equivalent
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
10
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Table 5: CFI Query Identification String1 for SST39WF800B
Address
Data
Data
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
0051H
0052H
0059H
0001H
0007H
0000H
0000H
0000H
0000H
0000H
0000H
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T5.0 25031
1. Refer to CFI publication 100 for more details.
Table 6: System Interface Information for SST39WF800B
Address
Data Data
1BH
0016H VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
0020H VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
0000H VPP min (00H = no VPP pin)
0000H VPP max (00H = no VPP pin)
0005H Typical time out for Word-Program 2N µs (25 = 32 µs)
0000H Typical time out for min size buffer program 2N µs (00H = not supported)
0005H Typical time out for individual Sector/Block-Erase 2N ms (25 = 32 ms)
0007H Typical time out for Chip-Erase 2N ms (27 = 128 ms)
0001H Maximum time out for Word-Program 2N times typical (21 x 25 = 64 µs)
0000H Maximum time out for buffer program 2N times typical
0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 25 = 64 ms)
0001H Maximum time out for Chip-Erase 2N times typical (21 x 27 = 256 ms)
T6.0 25031
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
11
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Table 7: Device Geometry Information for SST39WF800B
Address
Data
Data
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
0014H Device size = 2N Byte (14H = 20; 220 = 1 MByte)
0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
0000H
0000H Maximum number of byte in multi-byte write = 2N (00H = not supported)
0000H
0002H Number of Erase Sector/Block sizes supported by device
00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
0000H y = 255 + 1 = 256 sectors (00FFH = 255)
0010H
0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
000FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
0000H y = 15 + 1 = 16 blocks (000FH = 15)
0000H
0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T7.0 25031
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
12
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Electrical Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-
ditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 11V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest
information.
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
Table 8: Operating Range
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
1.65-1.95V
1.65-1.95V
-40°C to +85°C
T8.1 25031
Table 9: AC Conditions of Test1
Input Rise/Fall Time
Output Load
5ns
CL = 30 pF
T9.1 25031
1. See Figures 15 and 16
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
13
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Power-Up Specifications
All functionalities and DC specifications are specified for a VDD ramp rate faster than 1V per 100 ms
(0V to 1.8V in less than 180 ms). In addition, a VDD ramp rate slower than 1V per 20 µs is recom-
mended. See Table 10 and Figure 4 for more information.
Table 10:Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
VDD Min to Read Operation
VDD Min to Write Operation
1
TPU-WRITE
100
µs
T10.0 25031
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
T
PU-READ
V
min
V
DD
DD
0V
CE#
1344 F37.1
Figure 4:Power-Up Reset Diagram
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
14
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
DC Characteristics
Table 11:DC Operating Characteristics, VDD = 1.65-1.95V1
Limits
Max
Symbol Parameter
Min
Units Test Conditions
Address input=VILT/VIHT, at f=5 MHz, VDD=VDD Max
IDD
Power Supply Current
Read
15
20
mA CE#=VIL, OE#=WE#=VIH, all I/Os open
mA CE#=WE#=VIL, OE#=VIH
Program and Erase
Standby VDD Current2
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
ISB
ILI
40
µA
µA
µA
CE#=VDD, VDD=VDD Max
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
1
ILO
VIL
VIH
VOL
VOH
1
0.2VDD
0.8VDD
V
V
V
VDD=VDD Max
0.1
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
VDD-0.1
T11.0 25031
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 1.8V. Not 100% tested.
2. 40 µA is the maximum ISB for all SST39WF800B commercial grade devices. 40 µA is the maximum ISB for all
39WF800A industrial grade devices. For all SST39WF800B commercial and industrial devices, ISB typical is under 5
µA.
Table 12:Capacitance (TA = 25°C, f=1 MHz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
12 pF
1
CI/O
I/O Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
6 pF
T12.0 25031
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 13:Reliability Characteristics
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Cycles
Years
mA
Test Method
1,2
NEND
10,000
100
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1
TDR
1
ILTH
100 + IDD
T13.0 25031
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would
result in a higher minimum specification.
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
15
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
AC Characteristics
Table 14:Read Cycle Timing Parameters
70 ns
Symbol
TRC
Parameter
Min
Max
Units
ns
Read Cycle Time
70
TCE
Chip Enable Access Time
Address Access Time
70
70
35
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
TCLZ
0
0
ns
1
TOLZ
ns
1
TCHZ
40
40
ns
1
TOHZ
ns
1
TOH
0
ns
T14.0 25031
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 15:Program/Erase Cycle Timing Parameters
Symbol
TBP
Parameter
Min
Max
Units
µs
Word-Program Time
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
40
TAS
0
50
0
ns
TAH
ns
TCS
ns
TCH
0
ns
TOES
TOEH
TCP
0
ns
10
50
50
30
30
50
0
ns
ns
TWP
WE# Pulse Width
ns
1
TWPH
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
ns
TDS
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
50
ns
TSE
ms
ms
ms
TBE
Block-Erase
50
TSCE
Chip-Erase
200
T15.0 25031
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
16
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
T
T
AA
RC
ADDRESS A
MS-0
CE#
T
CE
T
OE
OE#
WE#
T
OHZ
T
OLZ
V
IH
T
T
T
CHZ
OH
CLZ
HIGH-Z
HIGH-Z
DQ
DATA VALID
DATA VALID
15-0
1344 F03.0
Note: AMS = Most significant address
AMS = A18 for SST39WF800B
Figure 5: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
WP
WE#
OE#
T
T
T
WPH
DS
T
AS
CH
CE#
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
1344 F04.0
Note: AMS = Most significant address
AMS = A18 for SST39WF800B
X can be VIL or VIH, but no other value.
Figure 6: WE# Controlled Program Cycle Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
17
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
CP
CE#
OE#
WE#
T
T
DS
CPH
T
AS
T
CH
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
1344 F05.0
Note: AMS = Most significant address
AMS = A18 for SST39WF800B
X can be VIL or VIH, but no other value.
Figure 7: CE# Controlled Program Cycle Timing Diagram
ADDRESS A
MS-0
CE#
OE#
T
CE
T
T
OES
OEH
T
OE
WE#
DQ
DATA
DATA#
DATA#
DATA
7
1344 F06.0
Note: AMS = Most significant address
AMS = A18 for SST39WF800B
Figure 8: Data# Polling Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
18
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
ADDRESS A
MS-0
T
CE
CE#
T
T
OES
OEH
T
OE
OE#
WE#
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
1344 F07.0
Note: AMS = Most significant address
AMS = A18 for SST39WF800B
FIGURE
0-1: TOGGLE BIT TIMING DIAGRAM
T
SIX-BYTE CODE FOR CHIP-ERASE
5555 5555 2AAA
SCE
ADDRESS A
5555
2AAA
5555
MS-0
CE#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
1344 F08.0
Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are inter-
changeable as long as minimum timings are met. (See Table 15)
AMS = Most significant address
AMS = A18 for SST39WF800B
X can be VIL or VIH, but no other value.
Figure 9: WE# Controlled Chip-Erase Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
19
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
T
SIX-BYTE CODE FOR BLOCK-ERASE
BE
ADDRESS A
5555
2AAA
5555
5555
2AAA
BA
X
MS-0
CE#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX50
SW5
1344 F09.0
Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 15)
AMS = Most significant address
AMS = A18 for SST39WF800B
X can be VIL or VIH, but no other value.
Figure 10:WE# Controlled Block-Erase Timing Diagram
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
SA
ADDRESS A
5555
2AAA
5555
5555
2AAA
X
MS-0
CE#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
1344 F10.0
Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals
are interchangeable as long as minimum timings are met. (See Table 15)
AMS = Most significant address
AMS = A18 for SST39WF800B
X can be VIL or VIH, but no other value.
Figure 11:WE# Controlled Sector-Erase Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
20
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
14-0
5555
2AAA
5555
0000
0001
CE#
OE#
T
T
IDA
WP
WE#
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX90
SW2
00BF
Device ID
1344 F11.0
Note: Device ID = 273FH for SST39WF800B
X can be VIL or VIH, but no other value.
Figure 12:Software ID Entry and Read
THREE-BYTE SEQUENCE FOR
SST CFI QUERY ENTRY
ADDRESS A
14-0
5555
2AAA
5555
CE#
OE#
WE#
T
T
WP
IDA
T
T
AA
WPH
DQ
15-0
XXAA
SW0
XX55
SW1
XX98
SW2
1344 F12.0
Note: X can be VIL or VIH, but no other value.
Figure 13:SST CFI Query Entry and Read
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
21
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
2AAA
5555
ADDRESS A
14-0
DQ
XXAA
XX55
XXF0
15-0
T
IDA
CE#
OE#
WE#
T
T
WHP
WP
SW0
SW1
SW2
1344 F13.0
Note: X can be VIL or VIH, but no other value.
Figure 14:Software ID Exit/CFI Exit
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
1344 F14.0
AC test inputs are driven at VIHT (VDD) for a logic ‘1’ and VILT (VSS) for a logic ‘0’.
Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input
rise and fall times are (10% 90%) <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
Figure 15:AC Input/Output Reference Waveforms
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
22
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
V
DD
TO TESTER
25K
TO DUT
C
25K
L
1344 F15.0
Figure 16:A Test Load Example
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
23
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Start
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XXA0H
Address: 5555H
Load Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
Note:
X can be V or V , but no other value.
IL IH
1344 F16.0
Figure 17:Word-Program Algorithm
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
24
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
,
BP
T
T
SCE, SE
or T
BE
Read same
word
Is DQ =
7
No
true data
Program/Erase
Completed
Yes
No
Does DQ
match
Program/Erase
Completed
6
Yes
Program/Erase
Completed
1344 F17.0
Figure 18:Wait Options
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
25
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
CFI Query Entry
Command Sequence
Software ID Entry
Command Sequence
Software ID Exit/CFI Exit
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Wait T
IDA
Load data: XX98H
Address: 5555H
Load data: XX90H
Address: 5555H
Load data: XXF0H
Address: 5555H
Return to normal
operation
Wait T
Wait T
Wait T
IDA
IDA
IDA
Return to normal
operation
Read CFI data
Read Software ID
Note:
X can be V or V , but no other value.
IL IH
1344 F18.0
Figure 19:Software ID/CFI Command Flowcharts
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
26
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
Note:
X can be V or V , but no other value.
IL IH
1344 F19.0
Figure 20:Erase Command Sequence
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
27
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Product Ordering Information
SST 39 WF 800B
-
70
-
4C
-
B3KE
-
XX XX XXXX
-
XX
-
XX
XXXX
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls
Q = 48 balls (66 possible positions)
Package Type
B3 = TFBGA (0.8mm pitch, 6mm x 8mm)
C2 = XFLGA (0.5mm pitch, 5mm x 6mm)
MA= WFBGA (0.5mm pitch, 4mm x 6mm)
CA = XFLGA (0.5mm pitch, 4mm x 6mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Device Density
800 = 8 Mbit
Voltage
W = 1.65-1.95V
Product Series
39 = Multi-Purpose Flash
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid combinations for SST39WF800B
SST39WF800B-70-4C-B3KE
SST39WF800B-70-4C-C2QE
SST39WF800B-70-4C-MAQE
SST39WF800B-70-4C-CAQE
SST39WF800B-70-4I-B3KE
SST39WF800B-70-4I-C2QE
SST39WF800B-70-4I-MAQE
SST39WF800B-70-4I-CAQE
Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST
sales representative to confirm availability of valid combinations and to determine availability of new combi-
nations.
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
28
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Packaging Diagrams
TOP VIEW
BOTTOM VIEW
5.60
8.00 0.10
0.45 0.05
0.80
(48X)
6
5
6
5
4
3
2
1
4.00
4
3
6.00 0.10
2
1
0.80
A
B C D E F G H
H
G F E D C B A
A1 CORNER
A1 CORNER
1.10 0.10
SIDE VIEW
0.12
SEATING PLANE
1mm
0.35 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
48-tfbga-B3K-6x8-450mic-5
Figure 21:48-Ball Thin-Profile, Fine-Pitch Ball Grid Array (TFBGA) 6mm x 8mm
SST Package Code: B3K
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
29
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
TOP VIEW
BOTTOM VIEW
6.00 0.08
5.00
0.50
0.29 0.05
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
5.00 0.08
2.50
0.50
A
B
C
D
E
F
G
H
J
K
L
L K J H G F E D C B A
A1 CORNER
A1 INDICATOR4
0.52 max.
0.473 nom.
DETAIL
SIDE VIEW
0.08
SEATING PLANE
0.04 + 0.025/ - 0.015
1mm
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-222, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. For low-profile mounting on PCB, SST recommends underfill for best solder joint reliability.
4. Coplanarity: 0.08 mm
5. No bump is present in position A1; a gold-colored indicator is present.
48-xflga-C2Q-5x6-29mic-NR
Figure 22: 48-Ball Extremely Thin-Profile, Fine-Pitch Land Grid Array (XFLGA) 5mm x 6mm
SST Package Code: C2Q
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
30
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
TOP VIEW
BOTTOM VIEW
5.00
6.00
0.08
0.50
0.32 0.05
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
4.00
0.08
2.50
0.50
A
B
C
D
E
F
G
H
J
K
L
L K J H G F E D C B A
A1 CORNER
A1 INDICATOR
0.73 max.
0.636 nom.
DETAIL
SIDE VIEW
0.08
SEATING PLANE
0.20 0.06
1mm
Note:
1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger
and bottom side A1 indicator is triangle at corner.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. Ball opening size is 0.29 mm ( 0.05 mm)
48-wfbga-MAQ-4x6-32mic-2.0
Figure 23:48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) 4mm x 6mm
SST Package Code: MAQ
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
31
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
TOP VIEW
BOTTOM VIEW
6.00
0.08
5.00
0.29
0.50
0.05
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
4.00
2.50
0.08
0.50
A
B
C
D
E
F
G
H
J
K
L
L K J H G F E D C B A
A1 INDICATOR
A1 CORNER
0.52 max.
DETAIL
SIDE VIEW
0.473 nom.
0.08
SEATING PLANE
1mm
0.04
+0.025/-0.015
Note: 1. Complies with JEDEC Publication 95, MO-207, variant CZB-4, dimensions except the bump height
is much less, and the A1 indicator is different.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm.
4. For low-profile mounting on PCB, SST recommends underfill for best solder joint reliability.
48-xflga-CAQ-4x6-29mic-6.0
Figure 24: 48-Ball Extremely Thin-Profile, Fine-Pitch Land Grid Array (XFLGA) 4mm x 6mm
SST Package Code: CAQ
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
32
8 Mbit (x16) Multi-Purpose Flash
SST39WF800B
A Microchip Technology Company
Data Sheet
Table 16:Revision History
Number
00
Description
Date
Feb 2007
Jul 2007
•
•
•
•
•
Initial release of data sheet
01
Added “Power-Up Specifications” on page 14
Removed the M2QE and MBQE packages
Added Y1QE package information
02
A
Dec 2009
Aug 2011
EOL of all Y1QE parts. Replacement parts are MAQE parts listed in
this document.
Added information for the MAQE and CAQE packages.
Applied new document format
Released document under letter revision system
Updated spec number from S71344 to DS25031
•
•
•
•
ISBN:978-1-61341-405-7
© 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved.
SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Tech-
nology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and
registered trademarks mentioned herein are the property of their respective owners.
Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current
package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.
Memory sizes denote raw storage capacity; actual usable capacity may be less.
SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of
Sale.
For sales office(s) location and information, please see www.microchip.com.
Silicon Storage Technology, Inc.
A Microchip Technology Company
www.microchip.com
©2011 Silicon Storage Technology, Inc.
DS25031A
08/11
33
相关型号：
SST402-SOIC-8
TRANSISTOR 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, JFET, SOIC-8, FET General Purpose Small Signal
MICROSS
©2020 ICPDF网 联系我们和版权申明