SST26VF032BEUIT-104I/SM [MICROCHIP]
FLASH 3V PROM;型号: | SST26VF032BEUIT-104I/SM |
厂家: | MICROCHIP |
描述: | FLASH 3V PROM 可编程只读存储器 时钟 光电二极管 内存集成电路 |
文件: | 总76页 (文件大小:2600K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SST26VF032BEUI
32 Mbit Serial Quad I/O (SQI) Flash Memory with EUI-48™
and EUI-64™ Identifier
- 64 KByte blocks, two 32 KByte blocks, and
eight 8 KByte parameter blocks
Features
• Factory-Programmed with EUI-48 and EUI-64
- Read Protection on top and bottom 8 KByte
Globally Unique Identifier
parameter blocks
- Secure, read-only access in Serial Flash
• Security ID
Discoverable Parameter (SFDP) table
- One-Time Programmable (OTP) 2 KByte, Secure ID
• Single Voltage Read and Write Operations
- 64 bit unique, factory pre-programmed identifier
- 2.7-3.6V or 2.3-3.6V
- User-programmable area
• Serial Interface Architecture
• Temperature Range
- Nibble-wide multiplexed I/O’s with SPI-like serial
command structure
- Industrial: -40°C to +85°C
• Automotive AECQ-100 Qualified
- Mode 0 and Mode 3
• Packages Available
- x1/x2/x4 Serial Peripheral Interface (SPI) Protocol
- 8-lead SOIJ (5.28 mm)
• High Speed Clock Frequency
• All devices are RoHS compliant
- 2.7-3.6V: 104 MHz max
- 2.3-3.6V: 80 MHz max
Product Description
• Burst Modes
- Continuous linear burst
- 8/16/32/64 Byte linear burst with wrap-around
The Serial Quad I/O™ (SQI™) family of flash-memory
devices features a six-wire, 4-bit I/O interface that allows for
low-power, high-performance operation in a low pin-count
package. SST26VF032BEUI also support full command-set
compatibility to traditional Serial Peripheral Interface (SPI)
protocol. System designs using SQI flash devices occupy
less board space and ultimately lower system costs.
• Superior Reliability
- Endurance: 100,000 Cycles (min)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read current: 15 mA (typical @ 104 MHz)
- Standby Current: 15 µA (typical)
All members of the 26 Series, SQI family are manufactured
with proprietary, high-performance CMOS SuperFlash®
technology. The split-gate cell design and thick-oxide tun-
neling injector attain better reliability and manufacturability
compared with alternate approaches.
• Fast Erase Time
- Sector/Block Erase: 18 ms (typ), 25 ms (max)
- Chip Erase: 35 ms (typ), 50 ms (max)
• Page-Program
SST26VF032BEUI significantly improve performance and
reliability, while lowering power consumption. These devices
write (Program or Erase) with a single power supply of 2.3-
3.6V. The total energy consumed is a function of the applied
voltage, current, and time of application. Since for any given
voltage range, the SuperFlash technology uses less current
to program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less
than alternative flash memory technologies.
- 256 Bytes per page in x1 or x4 mode
• End-of-Write Detection
- Software polling the BUSY bit in status register
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Four 8 KByte top and bottom parameter overlay
blocks
- One 32 KByte top and bottom overlay block
- Uniform 64 KByte overlay blocks
SST26VF032BEUI is offered in 8-lead SOIJ (5.28 mm).
See Figure 2-1 for pin assignments.
• Write-Suspend
SST26VF032BEUI default at power-up has the WP#
and HOLD# pins enabled, and the SIO2 and SIO3
pins disabled, to initiate SPI-protocol operations.See
“I/O Configuration (IOC)” on page 11 for more
information about configuring WP#/HOLD# and SIO2/
SIO3 pins.
- Suspend Program or Erase operation to access
another block/sector
• Software Reset (RST) mode
• Software Write Protection
- Individual-Block Write Protection with permanent
lock-down capability
2019 Microchip Technology Inc.
DS20006152A-page 1
SST26VF032BEUI
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
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DS20006152A-page 2
2019 Microchip Technology Inc.
SST26VF032BEUI
1.0
BLOCK DIAGRAM
FIGURE 1-1:
FUNCTIONAL BLOCK DIAGRAM
OTP
SuperFlash
Memory
X - Decoder
Address
Buffers
and
Latches
Y - Decoder
Page Buffer,
I/O Buffers
and
Control Logic
Data Latches
Serial Interface
WP# HOLD# SCK CE# SIO [3:0]
20005218 B1.0
2019 Microchip Technology Inc.
DS20006152A-page 3
SST26VF032BEUI
2.0
PIN DESCRIPTION
FIGURE 2-1:
PIN DESCRIPTION FOR
8-LEAD SOIJ
1
2
3
4
8
7
6
5
CE#
SO/SIO1
V
DD
HOLD/SIO3
SCK
Top View
WP#/SIO2
V
SS
SI/SIO0
20005218 08-soic S2A P1.0
TABLE 2-1:
Symbol
SCK
PIN DESCRIPTION
Pin Name
Functions
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SIO[3:0]
SI
Serial Data
Input/Output
To transfer commands, addresses, or data serially into the device or data out of
the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)
command instruction configures these pins for Quad I/O mode.
Serial Data Input
for SPI mode
To transfer commands, addresses or data serially into the device. Inputs are
latched on the rising edge of the serial clock. SI is the default state after a power
on reset.
SO
Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge
for SPI mode
of the serial clock. SO is the default state after a power on reset.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence; or in the case of Write operations,
for the command/data input sequence.
WP#
Write Protect
Hold
The WP# is used in conjunction with the WPEN and IOC bits in the Configura-
tion register to prohibit write operations to the Block-Protection register. This pin
only works in SPI, single-bit and dual-bit Read mode.
HOLD#
Temporarily stops serial communication with the SPI Flash memory while the
device is selected. This pin only works in SPI, single-bit and dual-bit Read mode
and must be tied high when not in use.
VDD
VSS
Power Supply
Ground
To provide power supply voltage.
DS20006152A-page 4
2019 Microchip Technology Inc.
SST26VF032BEUI
3.0
MEMORY ORGANIZATION
The SST26VF032BEUI SQI memory array is organized
in uniform, 4 KByte erasable sectors with the following
erasable blocks: eight 8 KByte parameter, two 32
KByte overlay, and sixty-two 64 KByte overlay blocks.
See Figure 3-1.
FIGURE 3-1:
MEMORY MAP
Top of Memory Block
8 KByte
8 KByte
8 KByte
8 KByte
32 KByte
64 KByte
2 Sectors for 8 KByte blocks
8 Sectors for 32 KByte blocks
16 Sectors for 64 KByte blocks
4 KByte
4 KByte
64 KByte
64 KByte
4 KByte
4 KByte
32 KByte
8 KByte
8 KByte
8 KByte
8 KByte
Bottom of Memory Block
20005218 F41.0
2019 Microchip Technology Inc.
DS20006152A-page 5
SST26VF032BEUI
4.0
DEVICE OPERATION
SST26VF032BEUI supports both Serial Peripheral
Interface (SPI) bus protocol and a 4-bit multiplexed SQI
bus protocol. To provide backward compatibility to tra-
ditional SPI Serial Flash devices, the device’s initial
state after a power-on reset is SPI mode which sup-
ports multi-I/O (x1/x2/x4) Read/Write commands. A
command instruction configures the device to SQI
mode. The dataflow in the SQI mode is similar to the
SPI mode, except it uses four multiplexed I/O signals
for command, address, and data sequence.
SCK clock signal for input, and driven after the falling
edge of the SCK clock signal for output. The traditional
SPI protocol uses separate input (SI) and output (SO)
data signals as shown in Figure 4-1. The SQI protocol
uses four multiplexed signals, SIO[3:0], for both data in
and data out, as shown in Figure 4-2. This means the
SQI protocol quadruples the traditional bus transfer
speed at the same clock frequency, without the need
for more pins on the package.
The SST26VF032BEUI is pre-programmed with a
globally unique EUI-48 and EUI-64 identifiers. The
addresses are located in the Serial Flash Discoverable
Parameters (SFDP) table and accessible via the SFDP
read instruction. Refer to See “Pre-Programmed EUI-
48 and EUI-64 Address” on page 72 for address loca-
tions and description.
SQI Flash Memory supports both Mode 0 (0,0) and
Mode 3 (1,1) bus operations. The difference between
the two modes is the state of the SCK signal when the
bus master is in stand-by mode and no data is being
transferred. The SCK signal is low for Mode 0 and SCK
signal is high for Mode 3. For both modes, the Serial
Data I/O (SIO[3:0]) is sampled at the rising edge of the
FIGURE 4-1:
SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON'T CARE
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
20005218 F03.0
FIGURE 4-2:
SQI SERIAL QUAD I/O PROTOCOL
CE#
MODE 3
MODE 3
MODE 0
CLK
MODE 0
SIO(3:0)
C1 C0 A5 A4 A3 A2 A1 A0
H0 L0 H1 L1 H2 L2 H3 L3
MSB
20005218 F04.0
erased. Data that had been previously programmed
into these blocks cannot be altered by programming or
erase and is not reversible
4.1
Device Protection
SST26VF032BEUI offer a flexible memory protection
scheme that allows the protection state of each individ-
ual block to be controlled separately. In addition, the
Write-Protection Lock-Down register prevents any
change of the lock status during device operation. To
avoid inadvertent writes during power-up, the device is
write-protected by default after a power-on reset cycle.
A Global Block-Protection Unlock command offers a
single command cycle that unlocks the entire memory
array for faster manufacturing throughput.
4.1.1
INDIVIDUAL BLOCK PROTECTION
SST26VF032BEUI have a Block-Protection register
which provides a software mechanism to write-lock the
individual memory blocks and write-lock, and/or read-
lock, the individual parameter blocks. The Block-Pro-
tection register is 80 bits wide: two bits each for the
eight 8 KByte parameter blocks (write-lock and read-
lock), and one bit each for the remaining 32 KByte and
64 KByte overlay blocks (write-lock). See Table 5-6 for
address range protected per register bit.
For extra protection, there is an additional non-volatile
register that can permanently write-protect the Block-
Protection register bits for each individual block. Each
of the corresponding lock-down bits are one time pro-
grammable (OTP)—once written, they cannot be
Each bit in the Block-Protection register (BPR) can be
written to a ‘1’ (protected) or ‘0’ (unprotected). For the
parameter blocks, the most significant bit is for read-
DS20006152A-page 6
2019 Microchip Technology Inc.
SST26VF032BEUI
lock, and the least significant bit is for write-lock. Read-
locking the parameter blocks provides additional secu-
rity for sensitive data after retrieval (e.g., after initial
boot). If a block is read-locked all reads to the block
return data 00H.
method provides write-protection for the corresponding
memory-array block by protecting it from future pro-
gram or erase operations.
Writing a ‘0’ in any location in the nVWLDR has no
effect on either the nVWLDR or the corresponding
Write-Lock bit in the BPR.
The Write Block-Protection Register command is a
two-cycle command which requires that Write-Enable
(WREN) is executed prior to the Write Block-Protection
Register command. The Global Block-Protection
Unlock command clears all write protection bits in the
Block-Protection register.
Note that if the Block-Protection register had been pre-
viously locked down, see “Write-Protection Lock-Down
(Volatile)”, the device must be power cycled before
using the nVWLDR. If the Block-Protection register is
locked down and the Write nVWLDR command is
accessed, the command will be ignored.
4.1.2
WRITE-PROTECTION LOCK-DOWN
(VOLATILE)
4.2
Hardware Write Protection
To prevent changes to the Block-Protection register,
use the Lock-Down Block-Protection Register (LBPR)
command to enable Write-Protection Lock-Down.
Once Write-Protection Lock-Down is enabled, the
Block-Protection register can not be changed. To avoid
inadvertent lock down, the WREN command must be
executed prior to the LBPR command.
The hardware Write Protection pin (WP#) is used in
conjunction with the WPEN and IOC bits in the config-
uration register to prohibit write operations to the Block-
Protection and Configuration registers. The WP# pin
function only works in SPI single-bit and dual-bit read
mode when the IOC bit in the configuration register is
set to ‘0’.
To reset Write-Protection Lock-Down, performing a power
cycle on the device is required. The Write-Protection
Lock-Down status may be read from the Status register.
The WP# pin function is disabled when the WPEN bit
in the configuration register is ‘0’. This allows installa-
tion of the SST26VF032BEUI in a system with a
grounded WP# pin while still enabling Write to the
Block-Protection register. The Lock-Down function of
the Block-Protection Register supersedes the WP# pin,
see Table 4-1 for Write Protection Lock-Down states.
4.1.3
WRITE-LOCK LOCK-DOWN (NON-
VOLATILE)
The non-Volatile Write-Lock Lock-Down register is an
alternate register that permanently prevents changes
to the block-protect bits. The non-Volatile Write-Lock
Lock-Down register (nVWLDR) is 72 bits wide per
device: one bit each for the eight 8-KByte parameter
blocks, and one bit each for the remaining 32 KByte
and 64 KByte overlay blocks. See Table 5-6 for address
range protected per register bit.
The factory default setting at power-up of the WPEN bit
is ‘0’, disabling the Write Protect function of the WP#
after power-up. WPEN is a non-volatile bit; once the bit
is set to ‘1’, the Write Protect function of the WP# pin
continues to be enabled after power-up. The WP# pin
only protects the Block-Protection Register and Config-
uration Register from changes. Therefore, if the WP#
pin is set to low before or after a Program or Erase
command, or while an internal Write is in progress, it
will have no effect on the Write command.
Writing ‘1’ to any or all of the nVWLDR bits disables the
change mechanism for the corresponding Write-Lock
bit in the BPR, and permanently sets this bit to a ‘1’
(protected) state. After this change, both bits will be set
to ‘1’, regardless of the data entered in subsequent
writes to either the nVWLDR or the BPR. Subsequent
writes to the nVWLDR can only alter available locations
that have not been previously written to a ‘1’. This
The IOC bit takes priority over the WPEN bit in the con-
figuration register. When the IOC bit is ‘1’, the function
of the WP# pin is disabled and the WPEN bit serves no
function. When the IOC bit is ‘0’ and WPEN is ‘1’, set-
ting the WP# pin active low prohibits Write operations
to the Block Protection Register.
2019 Microchip Technology Inc.
DS20006152A-page 7
SST26VF032BEUI
TABLE 4-1:
WRITE PROTECTION LOCK-DOWN STATES
WP#
L
IOC
0
WPEN
WPLD
Execute WBPR Instruction
Not Allowed
Not Allowed
Not Allowed
Allowed
Configuration Register
Protected
Writable
1
0
1
1
0
0
1
0
1
0
L
0
L
0
01
1
Protected
Writable
L
02
X
X
X
02
H
0
Not Allowed
Allowed
Writable
H
0
Writable
X
1
13
Not Allowed
Allowed
Writable
X
Writable
1. Default at power-up Register settings for SST26VF032BEUI
2. Factory default setting is ‘0’. This is a non-volatile bit; default at power-up is the value set prior to power-down.
3. Default at power-up Register settings for SST26VF032BEUI
IOC bit set to ‘0’ and the HOLD# pin function enabled;
4.3
Security ID
SST26VF032BEUI ships with the IOC bit set to ‘1’ and
the HOLD# pin function disabled. The HOLD# pin is
always disabled in SQI mode and only works in SPI sin-
gle-bit and dual-bit read mode.
SST26VF032BEUI offers a 2 KByte Security ID (Sec
ID) feature. The Security ID space is divided into two
parts – one factory-programmed, 64-bit segment and
one user-programmable segment. The factory-pro-
grammed segment is programmed during manufactur-
ing with a unique number and cannot be changed. The
user-programmable segment is left unprogrammed for
the customer to program as desired.
To activate the Hold mode, CE# must be in active low
state. The Hold mode begins when the SCK active low
state coincides with the falling edge of the HOLD# sig-
nal. The Hold mode ends when the HOLD# signal’s ris-
ing edge coincides with the SCK active low state.
Use the Program Security ID (PSID) command to pro-
gram the Security ID using the address shown in Table
5-5. The Security ID can be locked using the Lockout
Security ID (LSID) command. This prevents any future
write operations to the Security ID.
If the falling edge of the HOLD# signal does not coin-
cide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the
active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active
low state, then the device exits Hold mode when the
SCK next reaches the active low state. See Figure 4-3.
The factory-programmed portion of the Security ID
can’t be programmed by the user; neither the factory-
programmed nor user-programmable areas can be
erased.
Once the device enters Hold mode, SO will be in high
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, it
resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold
condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be
driven active low.
4.4
Hold Operation
The HOLD# pin pauses active serial sequences with-
out resetting the clocking sequence. This pin is active
after every power up and only operates during SPI
single-bit and dual-bit modes. Two factory configura-
tions are available: SST26VF032BEUI ships with the
FIGURE 4-3:
HOLD CONDITION WAVEFORM.
SCK
HOLD#
Active
Hold
Active
Hold
Active
20005218 F46.0
DS20006152A-page 8
2019 Microchip Technology Inc.
SST26VF032BEUI
4.5
Status Register
The Status register is a read-only register that provides
the following status information: whether the flash
memory array is available for any Read or Write oper-
ation, if the device is write-enabled, whether an erase
or program operation is suspended, and if the Block-
Protection register and/or Security ID are locked down.
During an internal Erase or Program operation, the Sta-
tus register may be read to determine the completion of
an operation in progress. Table 4-2 describes the func-
tion of each bit in the Status register.
TABLE 4-2:
STATUS REGISTER
Default at
Power-up
Read/Write (R/
W)
Bit
Name
Function
0
BUSY
Write operation status
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
R
R
R
R
R
1
2
3
4
5
WEL
Write-Enable Latch status
1 = Device is write-enabled
0 = Device is not write-enabled
0
WSE
WSP
WPLD
SEC1
Write Suspend-Erase status
1 = Erase suspended
0 = Erase is not suspended
0
Write Suspend-Program status
1 = Program suspended
0 = Program is not suspended
0
Write Protection Lock-Down status
1 = Write Protection Lock-Down enabled
0 = Write Protection Lock-Down disabled
0
Security ID status
01
1 = Security ID space locked
0 = Security ID space not locked
6
7
RES
Reserved for future use
0
0
R
R
BUSY
Write operation status
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1. The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout Security ID instruction, oth-
erwise default at power-up is ‘0’.
2019 Microchip Technology Inc.
DS20006152A-page 9
SST26VF032BEUI
4.5.1
WRITE-ENABLE LATCH (WEL)
4.5.3
WRITE SUSPEND PROGRAM
STATUS (WSP)
The Write-Enable Latch (WEL) bit indicates the status
of the internal memory’s Write-Enable Latch. If the
WEL bit is set to ‘1’, the device is write enabled. If the
bit is set to ‘0’ (reset), the device is not write enabled
and does not accept any memory Program or Erase,
Protection Register Write, or Lock-Down commands.
The Write-Enable Latch bit is automatically reset under
the following conditions:
The Write Suspend-Program status (WSP) bit indicates
when a Program operation has been suspended. The
WSP is ‘1’ after the host issues a suspend command
during the Program operation. Once the suspended
Program resumes, the WSP bit is reset to ‘0’.
4.5.4
WRITE PROTECTION LOCK-DOWN
STATUS (WPLD)
• Power-up
The Write Protection Lock-Down status (WPLD) bit
indicates when the Block-Protection register is locked-
down to prevent changes to the protection settings.
The WPLD is ‘1’ after the host issues a Lock-Down
Block-Protection command. After a power cycle, the
WPLD bit is reset to ‘0’.
• Reset
• Write-Disable (WRDI) instruction
• Page-Program instruction completion
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
• Write-Block-Protection register instruction
• Lock-Down Block-Protection register instruction
• Program Security ID instruction completion
• Lockout Security ID instruction completion
• Write-Suspend instruction
4.5.5
SECURITY ID STATUS (SEC)
The Security ID Status (SEC) bit indicates when the
Security ID space is locked to prevent a Write com-
mand. The SEC is ‘1’ after the host issues a Lockout
SID command. Once the host issues a Lockout SID
command, the SEC bit can never be reset to ‘0.’
• SPI Quad Page program instruction completion
• Write Status Register
4.5.6
BUSY
The Busy bit determines whether there is an internal
Erase or Program operation in progress. If the BUSY
bit is ‘1’, the device is busy with an internal Erase or
Program operation. If the bit is ‘0’, no Erase or Program
operation is in progress.
4.5.2
WRITE SUSPEND ERASE STATUS
(WSE)
The Write Suspend-Erase status (WSE) indicates
when an Erase operation has been suspended. The
WSE bit is ‘1’ after the host issues a suspend command
during an Erase operation. Once the suspended Erase
resumes, the WSE bit is reset to ‘0’.
4.5.7
CONFIGURATION REGISTER
The Configuration register is a Read/Write register that
stores a variety of configuration information. See Table
4-3 for the function of each bit in the register.
TABLE 4-3:
CONFIGURATION REGISTER
Bit
Name
Function
Default at Power-up Read/Write (R/W)
0
RES
IOC
Reserved
0
01
R
I/O Configuration for SPI Mode
1 = WP# and HOLD# pins disabled
0 = WP# and HOLD# pins enabled
R/W
1
2
3
RES
Reserved
0
1
R
R
BPNV
Block-Protection Volatility State
1 = No memory block has been permanently locked
0 = Any block has been permanently locked
4
5
6
RES
Reserved
Reserved
Reserved
0
0
R
R
RES
RES
0
02
R
WPEN
Write-Protection Pin (WP#) Enable
1 = WP# enabled
R/W
7
0 = WP# disabled
1. SST26VF032BEUI default at Power-up is ‘0’
SST26VF032BEUI default at Power-up is ‘1’
2. Factory default setting. This is a non-volatile bit; default at power-up will be the setting prior to power-down.
DS20006152A-page 10
2019 Microchip Technology Inc.
SST26VF032BEUI
4.5.8
I/O CONFIGURATION (IOC)
The I/O Configuration (IOC) bit re-configures the I/O
pins. The IOC bit is set by writing a ‘1’ to Bit 1 of the
Configuration register. When IOC bit is ‘0’ the WP# pin
and HOLD# pin are enabled (SPI or Dual Configuration
setup). When IOC bit is set to ‘1’ the SIO2 pin and SIO3
pin are enabled (SPI Quad I/O Configuration setup).
The IOC bit must be set to ‘1’ before issuing the follow-
ing SPI commands: SQOR (6BH), SQIOR (EBH),
RBSPI (ECH), and SPI Quad page program (32H).
Without setting the IOC bit to ‘1’, those SPI commands
are not valid. The I/O configuration bit does not apply
when in SQI mode. The default at power-up for
SST26VF032BEUI is ‘0’ and for SST26VF032BEUI is
‘1’.
4.5.9
BLOCK-PROTECTION VOLATILITY
STATE (BPNV)
The Block-Protection Volatility State bit indicates
whether any block has been permanently locked with
the nVWLDR. When no bits in the nVWLDR have been
set, the BPNV is ‘1’; this is the default state from the
factory. When one or more bits in the nVWLDR are set
to ‘1’, the BPNV bit will also be ‘0’ from that point for-
ward, even after power-up.
4.5.10
WRITE-PROTECT ENABLE (WPEN)
The Write-Protect Enable (WPEN) bit is a non-volatile
bit that enables the WP# pin.
The Write-Protect (WP#) pin and the Write-Protect
Enable (WPEN) bit control the programmable hard-
ware write-protect feature. Setting the WP# pin to low,
and the WPEN bit to ‘1’, enables Hardware write-pro-
tection. To disable Hardware write protection, set either
the WP# pin to high or the WPEN bit to ‘0’. There is
latency associated with writing to the WPEN bit. Poll
the BUSY bit in the Status register, or wait TWPEN, for
the completion of the internal, self-timed Write opera-
tion. When the chip is hardware write protected, only
Write operations to Block-Protection and Configuration
registers are disabled. See “Hardware Write Protec-
tion” on page 7 and Table 4-1 on page 8 for more infor-
mation about the functionality of the WPEN bit.
2019 Microchip Technology Inc.
DS20006152A-page 11
SST26VF032BEUI
5.0
INSTRUCTIONS
Instructions are used to read, write (erase and pro-
gram), and configure the SST26VF032BEUI. The com-
plete list of the instructions is provided in Table 5-1.
TABLE 5-1:
DEVICE OPERATION INSTRUCTIONS FOR SST26VF032BEUI
Mode
SPI SQI Cycle(s)2, 3 Cycle(s)3 Cycle(s)3
Command
Cycle1
Address
Dummy
Data
Max
Instruction Description
Configuration
Freq4
NOP
No Operation
00H
66H
99H
38H
FFH
05H
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
104MHz
/ 80 MHz
RSTEN
RST5
Reset Enable
0
0
Reset Memory
Enable Quad I/O
Reset Quad I/O
Read Status Register
EQIO
RSTQIO6
0
X
0
RDSR
1 to
1 to
2
X
X
WRSR
RDCR
Write Status Register
01H
35H
X
X
Read Configuration
Register
1 to
1 to
X
X
Read
Read
Read Memory
03H
0BH
X
3
3
3
3
3
3
3
0
3
3
0
3
1
1
3
1
1
0
3
3
1 to
1 to
1 to
1 to
1 to
1 to
1 to
1
40 MHz
High-Speed Read Memory at Higher
Read
104MHz
/ 80 MHz
Speed
X
X
X
X
X
X
SQOR7
SQIOR8
SDOR9
SDIOR10
SB
SPI Quad Output Read
SPI Quad I/O Read
6BH
EBH
3BH
BBH
C0H
0CH
ECH
SPI Dual Output Read
SPI Dual I/O Read
Set Burst Length
X
X
RBSQI
RBSPI8
SQI Read Burst with Wrap
SPI Read Burst with Wrap
n to
n to
X
X
X
Identification
JEDEC-ID JEDEC-ID Read
Quad J-ID Quad I/O J-ID Read
9FH
AFH
5AH
0
0
3
0
1
1
3 to
3 to
1 to
104MHz
/ 80 MHz
X
SFDP
Serial Flash Discoverable
Parameters
Write
WREN
WRDI
SE11
Write Enable
Write Disable
06H
04H
20H
X
X
X
X
X
X
0
0
3
0
0
0
0
0
0
104MHz
/ 80 MHz
Erase 4 KBytes of Memory
Array
BE12
Erase 64, 32 or 8 KBytes of
Memory Array
D8H
X
X
3
0
0
CE
PP
Erase Full Array
Page Program
C7H
02H
32H
X
X
X
X
X
0
3
3
0
0
0
0
1 to 256
1 to 256
SPI Quad
PP7
SQI Quad Page
Program
DS20006152A-page 12
2019 Microchip Technology Inc.
SST26VF032BEUI
TABLE 5-1:
DEVICE OPERATION INSTRUCTIONS FOR SST26VF032BEUI
Mode
SPI SQI Cycle(s)2, 3 Cycle(s)3 Cycle(s)3
Command
Cycle1
Address
Dummy
Data
Max
Instruction Description
Freq4
WRSU
Suspends Program/Erase
B0H
30H
X
X
X
X
0
0
0
0
0
0
104MHz
/ 80 MHz
WRRE
Resumes Program/Erase
Protection
RBPR
Read Block-Protection
Register
72H
X
0
0
0
0
1
0
1 to18
1 to18
1 to 18
104MHz
/ 80 MHz
X
X
WBPR
LBPR
Write Block-Protection
Register
42H
8DH
X
X
Lock Down
Block-Protection
Register
X
0
0
0
nVWLDR
ULBPR
RSID
non-Volatile Write Lock-
Down Register
E8H
98H
88H
X
X
X
X
X
0
0
0
0
1 to 18
0
Global Block Protection
Unlock
Read Security ID
2
2
2
1
3
0
1 to 2048
1 to 2048
1 to 256
X
X
PSID
LSID
Program User
Security ID area
A5H
85H
X
X
Lockout Security ID Pro-
gramming
X
0
0
0
1. Command cycle is two clock periods in SQI mode and eight clock periods in SPI mode.
2. Address bits above the most significant bit of each density can be V or V
IL
IH.
3. Address, Dummy/Mode bits, and Data cycles are two clock periods in SQI and eight clock periods in SPI mode.
4. The max frequency for all instructions is up to 104 MHz from 2.7-3.6V and up to 80 MHz from 2.3-3.6V unless otherwise noted.
5. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
6. Device accepts eight-clock command in SPI mode, or two-clock command in SQI mode.
7. Data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command.
8. Address, Dummy/Mode bits, and data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command.
9. Data cycles are four clock periods.
10. Address, Dummy/Mode bits, and Data cycles are four clock periods.
11. Sector Addresses: Use A
- A , remaining address are don’t care, but must be set to V or V .
MS
12 IL IH
12. Blocks are 64 KByte, 32 KByte, or 8KByte, depending on location. Block Erase Address: A
- A for 64 KByte; A
- A
MS 15
MS
16
for 32 KByte; A
- A for 8 KByte. Remaining addresses are don’t care, but must be set to V or V .
MS
1
3
I
L
I
H
2019 Microchip Technology Inc.
DS20006152A-page 13
SST26VF032BEUI
The Reset operation requires the Reset-Enable com-
mand followed by the Reset command. Any command
other than the Reset command after the Reset-Enable
command will disable the Reset-Enable.
5.1
No Operation (NOP)
The No Operation command only cancels a Reset
Enable command. NOP has no impact on any other
command.
Once the Reset-Enable and Reset commands are suc-
cessfully executed, the device returns to normal opera-
tion Read mode and then does the following: resets the
protocol to SPI mode, resets the burst length to 8
Bytes, clears all the bits, except for bit 4 (WPLD) and
bit 5 (SEC), in the Status register to their default states,
and clears bit 1 (IOC) in the configuration register to its
default state. A device reset during an active Program
or Erase operation aborts the operation, which can
cause the data of the targeted address range to be cor-
rupted or lost. Depending on the prior operation, the
reset timing may vary. Recovery from a Write operation
requires more latency time than recovery from other
operations. See Table 8-2 on page 45 for Rest timing
parameters.
5.2
Reset-Enable (RSTEN) and Reset
(RST)
The Reset operation is used as a system (software)
reset that puts the device in normal operating Ready
mode. This operation consists of two commands:
Reset-Enable (RSTEN) followed by Reset (RST).
To reset the SST26VF032BEUI, the host drives CE#
low, sends the Reset-Enable command (66H), and
drives CE# high. Next, the host drives CE# low again,
sends the Reset command (99H), and drives CE# high,
see Figure 5-1.
FIGURE 5-1:
RESET SEQUENCE
T
CPH
CE#
MODE 3
MODE 0
MODE 3
MODE 0
MODE 3
MODE 0
CLK
SIO(3:0)
C1 C0
C3 C2
20005218 F05.0
Note: C[1:0] = 66H; C[3:2] = 99H
will automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically return
to the beginning (wrap-around) of the address space.
5.3
Read (40 MHz)
The Read instruction, 03H, is supported in SPI bus pro-
tocol only with clock frequencies up to 40 MHz. This
command is not supported in SQI bus protocol. The
device outputs the data starting from the specified
address location, then continuously streams the data
output through all addresses until terminated by a low-
to-high transition on CE#. The internal address pointer
Initiate the Read instruction by executing an 8-bit com-
mand, 03H, followed by address bits A[23:0]. CE# must
remain active low for the duration of the Read cycle.
See Figure 5-2 for Read Sequence.
FIGURE 5-2:
READ SEQUENCE (SPI)
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
70
MODE 0
SCK
03
ADD.
MSB
HIGH IMPEDANCE
ADD.
ADD.
SI
MSB
N
OUT
N+1
N+2
N+3
N+4
D
OUT
D
D
OUT
D
OUT
D
OUT
SO
MSB
20005218 F29.0
DS20006152A-page 14
2019 Microchip Technology Inc.
SST26VF032BEUI
5.4
Enable Quad I/O (EQIO)
The Enable Quad I/O (EQIO) instruction, 38H, enables
the flash device for SQI bus operation. Upon comple-
tion of the instruction, all instructions thereafter are
expected to be 4-bit multiplexed input/output (SQI
mode) until a power cycle or a “Reset Quad I/O instruc-
tion” is executed. See Figure 5-3.
FIGURE 5-3:
ENABLE QUAD I/O SEQUENCE
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
SCK
SIO0
38
SIO[3:1]
20005218 F43.0
Note: SIO[3:1] must be driven V
IH
where it can accept new command instruction. An addi-
tional RSTQIO is required to reset the device to SPI
mode.
5.5
Reset Quad I/O (RSTQIO)
The Reset Quad I/O instruction, FFH, resets the device
to 1-bit SPI protocol operation or exits the Set Mode
configuration during a read sequence. This command
allows the flash device to return to the default I/O state
(SPI) without a power cycle, and executes in either 1-
bit or 4-bit mode. If the device is in the Set Mode con-
figuration, while in SQI High-Speed Read mode, the
RSTQIO command will only return the device to a state
To execute a Reset Quad I/O operation, the host drives
CE# low, sends the Reset Quad I/O command cycle
(FFH) then, drives CE# high. Execute the instruction in
either SPI (8 clocks) or SQI (2 clocks) command
cycles. For SPI, SIO[3:1] are don’t care for this com-
mand, but should be driven to VIH or VIL. See Figures
5-4 and 5-5.
FIGURE 5-4:
RESET QUAD I/O SEQUENCE (SPI)
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
SCK
SIO0
FF
SIO[3:1]
20005218 F73.0
Note: SIO[3:1]
FIGURE 5-5:
RESET QUAD I/O SEQUENCE (SQI)
CE#
MODE 3
MODE 0
0
1
F
SCK
SIO(3:0)
F
20005218 F74.0
2019 Microchip Technology Inc.
DS20006152A-page 15
SST26VF032BEUI
Initiate High-Speed Read by executing an 8-bit com-
mand, 0BH, followed by address bits A[23-0] and a
dummy byte. CE# must remain active low for the dura-
tion of the High-Speed Read cycle. See Figure 5-6 for
the High-Speed Read sequence for SPI bus protocol.
5.6
High-Speed Read
The High-Speed Read instruction, 0BH, is supported in
both SPI bus protocol and SQI protocol. This instruc-
tion supports frequencies of up to 104 MHz from 2.7-
3.6V and up to 80 MHz from 2.3-3.6V. On power-up,
the device is set to use SPI.
FIGURE 5-6:
HIGH-SPEED READ SEQUENCE (SPI) (C[1:0] = 0BH)
CE#
MODE 3
MODE 0
0
1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
SCK
0B
ADD.
ADD.
ADD.
X
SI/SIO0
N
N+1
N+2
N+3
N+4
HIGH IMPEDANCE
SO/SIO1
D
D
OUT
D
OUT
D
OUT
D
OUT
OUT
MSB
20005218 F31.0
In SQI protocol, the host drives CE# low then send the
Read command cycle command, 0BH, followed by
three address cycles, a Set Mode Configuration cycle,
and two dummy cycles. Each cycle is two nibbles
(clocks) long, most significant nibble first.
mand, 0BH, and does not require the op-code to be
entered again. The host may initiate the next Read
cycle by driving CE# low, then sending the four-bits
input for address A[23:0], followed by the Set Mode
configuration bits M[7:0], and two dummy cycles. After
the two dummy cycles, the device outputs the data
starting from the specified address location. There are
no restrictions on address location access.
After the dummy cycles, the device outputs data on the
falling edge of the SCK signal starting from the speci-
fied address location. The device continually streams
data output through all addresses until terminated by a
low-to-high transition on CE#. The internal address
pointer automatically increments until the highest mem-
ory address is reached, at which point the address
pointer returns to address location 000000H. During
this operation, blocks that are Read-locked will output
data 00H.
When M[7:0] is any value other than AXH, the device
expects the next instruction initiated to be a command
instruction. To reset/exit the Set Mode configuration,
execute the Reset Quad I/O command, FFH. While in
the Set Mode configuration, the RSTQIO command will
only return the device to a state where it can accept
new command instruction. An additional RSTQIO is
required to reset the device to SPI mode. See Figure 5-
10 for the SPI Quad I/O Mode Read sequence when
M[7:0] = AXH.
The Set Mode Configuration bit M[7:0] indicates if the
next instruction cycle is another SQI High-Speed Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another Read com-
FIGURE 5-7:
HIGH-SPEED READ SEQUENCE (SQI)
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
20
21
MODE 3
SCK
MODE 0
MSN
LSN
L0
H0
Data Byte 0
C0 C1 A5 A4 A3 A2
Command Address
A0 M1 M0
Mode
X
X
X
X
H8 L8
SIO(3:0)
A1
Dummy
Data Byte 7
20005218 F47.0
Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble
Hx = High Data Nibble, Lx = Low Data Nibble C[1:0]=0BH
DS20006152A-page 16
2019 Microchip Technology Inc.
SST26VF032BEUI
5.7
SPI Quad-Output Read
The SPI Quad-Output Read instruction supports fre-
quencies of up to 104 MHz from 2.7-3.6V and up to 80
MHz from 2.3-3.6V. SST26VF032BEUI requires the
IOC bit in the configuration register to be set to ‘1’ prior
to executing the command. Initiate SPI Quad-Output
Read by executing an 8-bit command, 6BH, followed
by address bits A[23-0] and a dummy byte. CE# must
remain active low for the duration of the SPI Quad
Mode Read. See Figure 5-8 for the SPI Quad Output
Read sequence.
Following the dummy byte, the device outputs data
from SIO[3:0] starting from the specified address loca-
tion. The device continually streams data output
through all addresses until terminated by a low-to-high
transition on CE#. The internal address pointer auto-
matically increments until the highest memory address
is reached, at which point the address pointer returns
to the beginning of the address space.
FIGURE 5-8:
SPI QUAD OUTPUT READ
CE#
MODE 3
MODE 0
31 32
0
1
2
3
4
5
6
7
8
15 16
23 24
39 40 41
b4 b0
SCK
6BH
A[23:16] A[15:8]
Address
A[7:0]
b4 b0
Data
Byte N
SIO0
X
Data
OP Code
Byte 0
Dummy
SIO1
SIO2
SIO3
b5 b1
b6 b2
b5 b1
b6 b2
b7 b3
b7 b3
20005218 F48.3
Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble
2019 Microchip Technology Inc.
DS20006152A-page 17
SST26VF032BEUI
5.8
SPI Quad I/O Read
The SPI Quad I/O Read (SQIOR) instruction supports
frequencies of up to 104 MHz from 2.7-3.6V and up to
80 MHz from 2.3-3.6V. SST26VF032BEUI requires the
IOC bit in the configuration register to be set to ‘1’ prior
to executing the command. Initiate SQIOR by execut-
ing an 8-bit command, EBH. The device then switches
to 4-bit I/O mode for address bits A[23-0], followed by
the Set Mode configuration bits M[7:0], and two dummy
bytes.CE# must remain active low for the duration of
the SPI Quad I/O Read. See Figure 5-9 for the SPI
Quad I/O Read sequence.
The Set Mode Configuration bit M[7:0] indicates if the
next instruction cycle is another SPI Quad I/O Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another Read com-
mand, EBH, and does not require the op-code to be
entered again. The host may set the next SQIOR cycle
by driving CE# low, then sending the four-bit wide input
for address A[23:0], followed by the Set Mode configu-
ration bits M[7:0], and two dummy cycles. After the two
dummy cycles, the device outputs the data starting
from the specified address location. There are no
restrictions on address location access.
Following the dummy bytes, the device outputs data
from the specified address location. The device contin-
ually streams data output through all addresses until
terminated by a low-to-high transition on CE#. The
internal address pointer automatically increments until
the highest memory address is reached, at which point
the address pointer returns to the beginning of the
address space.
When M[7:0] is any value other than AXH, the device
expects the next instruction initiated to be a command
instruction. To reset/exit the Set Mode configuration,
execute the Reset Quad I/O command, FFH. See Fig-
ure 5-10 for the SPI Quad I/O Mode Read sequence
when M[7:0] = AXH.
FIGURE 5-9:
SPI QUAD I/O READ SEQUENCE
CE#
MODE 3
MODE 0
16
0
1
2
3
4
5
6
7
8 9 10 11 12 13 14 15
17 23
18 19 20 21 22
SCK
SIO0
SIO1
SIO2
SIO3
EBH
b4 b0
b5 b1
b6 b2
A20 A16 A12 A8
A21 A17 A13 A9
A22 A18 A14 A10
A23 A19 A15 A11
X
X
X
X
X
X
X
X
b4 b0
b5 b1
b6 b2
b7 b3
A4 A0 M4 M0
A5 A1 M5 M1
A6 A2 M6 M2
X
X
X
X
X
X
X
X
LSN
MSN
b7 b3
A7 A3 M7 M3
Set
Data
Byte 1
Data
Byte 0
Address
Dummy
Mode
20005218 F49.2
Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble
DS20006152A-page 18
2019 Microchip Technology Inc.
SST26VF032BEUI
FIGURE 5-10:
BACK-TO-BACK SPI QUAD I/O READ SEQUENCES WHEN M[7:0] = AXH
CE#
SCK
SIO0
SIO1
SIO2
SIO3
9
0
1 2
3
4
5 6
7
8
10
11 12 13
b4 b0 b4
b5 b1 b5
b6 b2 b6
M4
M5
M6
X
X
X
X
X
X
X
X
X
X
b4 b0
b5 b1
b6 b2
b0
b1
b2
A20 A16 A12 A8 A4
A21 A17 A13 A9 A5
A22 A18 A14 A10 A6
A0
A1
A2
M0
M1
M2
X
X
LSN
MSN
b7 b3 b7
M7
X
X
X
X
b7 b3
b3
A23 A19 A15 A11 A7
A3
M3
Set
Mode
Data Data
Byte Byte
Data
Dummy
Address
Byte 0
N
N+1
20005218 F50.2
Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble
sends the Set Burst command cycle (C0H) and one
data cycle, then drives CE# high. After power-up or
reset, the burst length is set to eight Bytes (00H). See
Table 5-2 for burst length data and Figures 5-11 and 5-
12 for the sequences.
5.9
Set Burst
The Set Burst command specifies the number of bytes
to be output during a Read Burst command before the
device wraps around. It supports both SPI and SQI pro-
tocols. To set the burst length the host drives CE# low,
TABLE 5-2:
BURST LENGTH DATA
Burst Length
8 Bytes
High Nibble (H0)
Low Nibble (L0)
0h
0h
0h
0h
0h
1h
2h
3h
16 Bytes
32 Bytes
64 Bytes
FIGURE 5-11:
SET BURST LENGTH SEQUENCE (SQI)
CE#
MODE 3
MODE 0
0
1
2
3
SCK
SIO(3:0)
C1 C0 H0 L0
MSN LSN
20005218 F32.0
Note: MSN = Most Significant
Nibble, LSN = Least Significant Nibble, C[1:0]=C0H
2019 Microchip Technology Inc.
DS20006152A-page 19
SST26VF032BEUI
FIGURE 5-12:
SET BURST LENGTH SEQUENCE (SPI)
CE#
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MODE 3
MODE 0
SCK
SIO0
C0
D
IN
SIO[3:1]
20005218 F51.0
Note: SIO[3:1] must be driven V
.
IH
5.10 SQI Read Burst with Wrap (RBSQI)
5.11 SPI Read Burst with Wrap (RBSPI)
SQI Read Burst with wrap is similar to High Speed
Read in SQI mode, except data will output continuously
within the burst length until a low-to-high transition on
CE#. To execute a SQI Read Burst operation, drive
CE# low then send the Read Burst command cycle
(0CH), followed by three address cycles, and then
three dummy cycles. Each cycle is two nibbles (clocks)
long, most significant nibble first.
SPI Read Burst with Wrap (RBSPI) is similar to SPI
Quad I/O Read except the data will output continuously
within the burst length until a low-to-high transition on
CE#. To execute a SPI Read Burst with Wrap opera-
tion, drive CE# low, then send the Read Burst com-
mand cycle (ECH), followed by three address cycles,
and then three dummy cycles.
After the dummy cycle, the device outputs data on the
falling edge of the SCK signal starting from the speci-
fied address location. The data output stream is contin-
uous through all addresses until terminated by a low-to-
high transition on CE#.
After the dummy cycles, the device outputs data on the
falling edge of the SCK signal starting from the speci-
fied address location. The data output stream is contin-
uous through all addresses until terminated by a low-to-
high transition on CE#.
During RBSPI, the internal address pointer automati-
cally increments until the last byte of the burst is
reached, then it wraps around to the first byte of the
burst. All bursts are aligned to addresses within the
burst length, see Table 5-3. For example, if the burst
length is eight Bytes, and the start address is 06h, the
burst sequence would be: 06h, 07h, 00h, 01h, 02h,
03h, 04h, 05h, 06h, etc. The pattern repeats until the
command is terminated by a low-to-high transition on
CE#.
During RBSQI, the internal address pointer automati-
cally increments until the last byte of the burst is
reached, then it wraps around to the first byte of the
burst. All bursts are aligned to addresses within the
burst length, see Table 5-3. For example, if the burst
length is eight Bytes, and the start address is 06h, the
burst sequence would be: 06h, 07h, 00h, 01h, 02h,
03h, 04h, 05h, 06h, etc. The pattern repeats until the
command is terminated by a low-to-high transition on
CE#.
During this operation, blocks that are Read-locked will
output data 00H.
During this operation, blocks that are Read-locked will
output data 00H.
TABLE 5-3:
BURST ADDRESS RANGES
Burst Address Ranges
Burst Length
8 Bytes
00-07H, 08-0FH, 10-17H, 18-1FH...
00-0FH, 10-1FH, 20-2FH, 30-3FH...
00-1FH, 20-3FH, 40-5FH, 60-7FH...
00-3FH, 40-7FH, 80-BFH, C0-FFH
16 Bytes
32 Bytes
64 Bytes
0
DS20006152A-page 20
2019 Microchip Technology Inc.
SST26VF032BEUI
Following the dummy byte, the SST26VF032BEUI out-
puts data from SIO[1:0] starting from the specified
address location. The device continually streams data
output through all addresses until terminated by a low-
to-high transition on CE#. The internal address pointer
automatically increments until the highest memory
address is reached, at which point the address pointer
returns to the beginning of the address space.
5.12 SPI Dual-Output Read
The SPI Dual-Output Read instruction supports fre-
quencies of up to 104 MHz from 2.7-3.6V and up to 80
MHz from 2.3-3.6V. Initiate SPI Dual-Output Read by
executing an 8-bit command, 3BH, followed by address
bits A[23-0] and a dummy byte. CE# must remain
active low for the duration of the SPI Dual-Output Read
operation. See Figure 5-13 for the SPI Quad Output
Read sequence.
FIGURE 5-13:
FAST READ, DUAL-OUTPUT SEQUENCE
CE#
MODE 3
MODE 0
31 32
41
39 40
0
1
2
3
4
5
6
7
8
15 16
23 24
SCK
SIO0
SIO1
3BH
A[23:16] A[15:8]
Address
A[7:0]
b6 b5 b3 b1
X
b6 b5 b3 b1
MSB
b7 b4 b2 b0
b7
b4 b2 b0
Data
Byte N
Data
Byte 0
OP Code
Dummy
20005218 F52.3
Note: MSB = Most Significant Bit.
When M[7:0] is any value other than AXH, the device
expects the next instruction initiated to be a command
instruction. To reset/exit the Set Mode configuration,
execute the Reset Quad I/O command, FFH. See Fig-
ure 5-15 for the SPI Dual I/O Read sequence when
M[7:0] = AXH.
5.13 SPI Dual I/O Read
The SPI Dual I/O Read (SDIOR) instruction supports
up to 80 MHz frequency. Initiate SDIOR by executing
an 8-bit command, BBH. The device then switches to
2-bit I/O mode for address bits A[23-0], followed by the
Set Mode configuration bits M[7:0]. CE# must remain
active low for the duration of the SPI Dual I/O Read.
See Figure 5-14 for the SPI Dual I/O Read sequence.
Following the Set Mode configuration bits, the
SST26VF032BEUI outputs data from the specified
address location. The device continually streams data
output through all addresses until terminated by a low-
to-high transition on CE#. The internal address pointer
automatically increments until the highest memory
address is reached, at which point the address pointer
returns to the beginning of the address space.
The Set Mode Configuration bit M[7:0] indicates if the
next instruction cycle is another SPI Dual I/O Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another SDIOR com-
mand, BBH, and does not require the op-code to be
entered again. The host may set the next SDIOR cycle
by driving CE# low, then sending the two-bit wide input
for address A[23:0], followed by the Set Mode configu-
ration bits M[7:0]. After the Set Mode configuration bits,
the device outputs the data starting from the specified
address location. There are no restrictions on address
location access.
2019 Microchip Technology Inc.
DS20006152A-page 21
SST26VF032BEUI
FIGURE 5-14:
SPI DUAL I/O READ SEQUENCE
CE#
MODE 3
MODE 0
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SIO0
SIO1
BBH
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
A[23:16]
A[15:8]
A[7:0]
M[7:0]
CE#(cont’)
SCK(cont’)
23 2425 26 27 28 29 30 31 32 33 34 35 36 37 38 39
I/O Switches from Input to Output
SIO0(cont’)
SIO1(cont’)
6
4
0
6
4
2
0
6
4
2
0
6
4
2
0
6
2
MSB
MSB
7
MSB
7
MSB
7
5
3
1
5
3
1
5
3
1
5
3
1
7
7
Byte 0
Byte 1
Byte 2
Byte 3
20005218 F53.1
Note: MSB= Most Significant Bit, LSB = Least Significant Bit
FIGURE 5-15:
BACK-TO-BACK SPI DUAL I/O READ SEQUENCES WHEN M[7:0] = AXH
CE#
MODE 3
MODE 0
0
1
2
3 4 5 6 7
8
9 10 11 12 13 14 15
SCK
SIO0
SIO1
I/O Switch
6
4
6
4
2
0
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
MSB
MSB
7
5
7
5
5
3
1
A[23:16]
A[15:8]
A[7:0]
M[7:0]
CE#(cont’)
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
I/O Switches from Input to Output
SCK(cont’)
SIO0(cont’)
SIO1(cont’)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
MSB
MSB
7
MSB
7
MSB
7
5
3
1
5
3
1
5
3
1
5
3
1
7
7
Byte 0
Byte 1
Byte 2
Byte 3
20005218 F54.1
Note: MSB=
Most Significant Bit, LSB = Least Significant Bit
DS20006152A-page 22
2019 Microchip Technology Inc.
SST26VF032BEUI
Immediately
following
the
command
cycle,
5.14 JEDEC-ID Read (SPI Protocol)
SST26VF032BEUI output data on the falling edge of
the SCK signal. The data output stream is continuous
until terminated by a low-to-high transition on CE#. The
device outputs three bytes of data: manufacturer,
device type, and device ID, see Table 5-4. See Figure
5-16 for instruction sequence.
Using traditional SPI protocol, the JEDEC-ID Read
instruction identifies the device as SST26VF032BEUI
and the manufacturer as Microchip®. To execute a
JECEC-ID operation the host drives CE# low then
sends the JEDEC-ID command cycle (9FH).
TABLE 5-4:
DEVICE ID DATA OUTPUT
Device ID
Product
SST26VF032BEUI
Manufacturer ID (Byte 1)
Device Type (Byte 2)
Device ID (Byte 3)
BFH
26H
42H
FIGURE 5-16:
JEDEC-ID SEQUENCE (SPI)
CE#
MODE 3
MODE 0
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCK
SI
9F
HIGH IMPEDANCE
26
Device ID
BF
SO
MSB
MSB
20005218 F38.0
Immediately following the command cycle and one
dummy cycle, SST26VF032BEUI output data on the
falling edge of the SCK signal. The data output stream
is continuous until terminated by a low-to-high transi-
tion of CE#. The device outputs three bytes of data:
manufacturer, device type, and device ID, see Table 5-
4. See Figure 5-17 for instruction sequence.
5.15 Read Quad J-ID Read (SQI
Protocol)
The Read Quad J-ID Read instruction identifies the
device as SST26VF032BEUI and manufacturer as
Microchip. To execute a Quad J-ID operation the host
drives CE# low and then sends the Quad J-ID com-
mand cycle (AFH). Each cycle is two nibbles (clocks)
long, most significant nibble first.
FIGURE 5-17:
QUAD J-ID READ SEQUENCE
CE#
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
MODE 3
SCK
MODE 0
MSN
LSN
C0 C1
X
X
H0 L0
BFH
L1 H2 L2 H0 L0 H1 L1
HN LN
N
SIO(3:0)
H1
26H
Dummy
Device ID
BFH
26H
20005218 F55.0
Note: MSN = Most significant Nibble; LSN= Least Significant Nibble. C{1:0]=AFH
2019 Microchip Technology Inc.
DS20006152A-page 23
SST26VF032BEUI
ware support for all future Serial Flash device families.
See Table 11-1 on page 53 for address and data val-
ues.
5.16 Serial Flash Discoverable
Parameters (SFDP)
The Serial Flash Discoverable Parameters (SFDP)
contain information describing the characteristics of the
device. This allows device-independent, JEDEC ID-
independent, and forward/backward compatible soft-
Initiate SFDP by executing an 8-bit command, 5AH, fol-
lowed by address bits A[23-0] and a dummy byte. CE#
must remain active low for the duration of the SFDP
cycle. For the SFDP sequence, see Figure 5-18.
FIGURE 5-18:
SERIAL FLASH DISCOVERABLE PARAMETERS SEQUENCE
CE#
MODE 3
0
1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
SCK
MODE 0
5A
ADD.
ADD.
ADD.
X
SI
N
N+1
N+2
N+3
N+4
HIGH IMPEDANCE
SO
D
D
D
D
D
OUT
OUT
OUT
OUT
OUT
MSB
20005218 F56.0
To execute a Sector-Erase operation, the host drives
CE# low, then sends the Sector Erase command cycle
(20H) and three address cycles, and then drives CE#
high. Address bits [AMS:A12] (AMS = Most Significant
Address) determine the sector address (SAX); the
remaining address bits can be VIL or VIH. To identify the
completion of the internal, self-timed, Write operation,
poll the BUSY bit in the Status register, or wait TSE. See
Figures 5-19 and 5-20 for the Sector-Erase sequence.
5.17 Sector-Erase
The Sector-Erase instruction clears all bits in the
selected 4 KByte sector to ‘1,’ but it does not change a
protected memory area. Prior to any write operation,
the Write-Enable (WREN) instruction must be exe-
cuted.
FIGURE 5-19:
4 KBYTE SECTOR-ERASE SEQUENCE– SQI MODE
CE#
MODE 3
MODE 0
0
1
2
4
6
SCK
SIO(3:0)
C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
20005218 F07.0
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 20H
FIGURE 5-20:
4 KBYTE SECTOR-ERASE SEQUENCE (SPI)
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
24
MODE 0
SCK
20
ADD.
MSB
ADD.
ADD.
SI
MSB
HIGH IMPEDANCE
SO
20005218 F57.0
DS20006152A-page 24
2019 Microchip Technology Inc.
SST26VF032BEUI
To execute a Block-Erase operation, the host drives
CE# low then sends the Block-Erase command cycle
(D8H), three address cycles, then drives CE# high.
Address bits AMS-A13 determine the block address
(BAX); the remaining address bits can be VIL or VIH. For
32 KByte blocks, A14:A13 can be VIL or VIH; for 64
KByte blocks, A15:A13 can be VIL or VIH. Poll the BUSY
bit in the Status register, or wait TBE, for the completion
of the internal, self-timed, Block-Erase operation. See
Figures 5-21 and 5-22 for the Block-Erase sequence.
5.18 Block-Erase
The Block-Erase instruction clears all bits in the
selected block to ‘1’. Block sizes can be 8 KByte, 32
KByte or 64 KByte depending on address, see Figure
3-1, Memory Map, for details. A Block-Erase instruction
applied to a protected memory area will be ignored.
Prior to any write operation, execute the WREN instruc-
tion. Keep CE# active low for the duration of any com-
mand sequence.
FIGURE 5-21:
BLOCK-ERASE SEQUENCE (SQI)
CE#
MODE 3
MODE 0
0
1
2
4
6
SCK
SIO(3:0)
C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
20005218 F08.0
Note: MSN = Most Significant Nibble,
LSN = Least Significant Nibble
C[1:0] = D8H
FIGURE 5-22:
BLOCK-ERASE SEQUENCE (SPI)
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
24
MODE 0
SCK
D8
ADDR
MSB
ADDR
ADDR
SI
MSB
HIGH IMPEDANCE
SO
20005218 F58.0
2019 Microchip Technology Inc.
DS20006152A-page 25
SST26VF032BEUI
To execute a Chip-Erase operation, the host drives
CE# low, sends the Chip-Erase command cycle (C7H),
then drives CE# high. Poll the BUSY bit in the Status
register, or wait TSCE, for the completion of the internal,
self-timed, Write operation. See Figures 5-23 and 5-24
for the Chip Erase sequence.
5.19 Chip-Erase
The Chip-Erase instruction clears all bits in the device
to ‘1.’ The Chip-Erase instruction is ignored if any of the
memory area is protected. Prior to any write operation,
execute the WREN instruction.
FIGURE 5-23:
CHIP-ERASE SEQUENCE (SQI)
CE#
MODE 3
MODE 0
0
1
SCK
SIO(3:0)
C1 C0
20005218 F09.1
Note: C[1:0] = C7H
FIGURE 5-24:
CHIP-ERASE SEQUENCE (SPI)
CE#
MODE 3
0
1
2
3
4
5
6
7
SCK
MODE 0
C7
SI
MSB
HIGH IMPEDANCE
SO
20005218 F59.0
DS20006152A-page 26
2019 Microchip Technology Inc.
SST26VF032BEUI
partial Byte to be ignored. Poll the BUSY bit in the Sta-
tus register, or wait TPP, for the completion of the inter-
nal, self-timed, Write operation. See Figures 5-25 and
5-26 for the Page-Program sequence.
5.20 Page-Program
The Page-Program instruction programs up to 256
Bytes of data in the memory, and supports both SPI
and SQI protocols. The data for the selected page
address must be in the erased state (FFH) before initi-
ating the Page-Program operation. A Page-Program
applied to a protected memory area will be ignored.
Prior to the program operation, execute the WREN
instruction.
When executing Page-Program, the memory range for
the SST26VF032BEUI is divided into 256 Byte page
boundaries. The device handles shifting of more than
256 Bytes of data by maintaining the last 256 Bytes of
data as the correct data to be programmed. If the target
address for the Page-Program instruction is not the
beginning of the page boundary (A[7:0] are not all
zero), and the number of bytes of data input exceeds or
overlaps the end of the address of the page boundary,
the excess data inputs wrap around and will be pro-
grammed at the start of that target page.
To execute a Page-Program operation, the host drives
CE# low then sends the Page Program command cycle
(02H), three address cycles followed by the data to be
programmed, then drives CE# high. The programmed
data must be between 1 to 256 Bytes and in whole Byte
increments; sending less than a full Byte will cause the
FIGURE 5-25:
PAGE-PROGRAM SEQUENCE (SQI)
CE#
SCK
MODE 3
MODE 0
0
2
4
6
8
10
12
SIO(3:0)
C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2
HN LN
MSN LSN
Data Byte 0
Data Byte 1 Data Byte 2
Data Byte 255
20005218 F10.1
Note:
MSN = Most Significant Nibble, LSN = Least Significant Nibble
FIGURE 5-26:
PAGE-PROGRAM SEQUENCE (SPI)
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39
SCK
SI
02
ADD.
MSB
ADD.
ADD.
LSB
Data Byte 0
LSB
MSB
MSB
LSB
SO
HIGH IMPEDANCE
CE#(cont’)
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK(cont’)
SI(cont’)
Data Byte 255
Data Byte 1
Data Byte 2
MSB
MSB
MSB
LSB
LSB
LSB
SO(cont’)
HIGH IMPEDANCE
20005218 F60.1
2019 Microchip Technology Inc.
DS20006152A-page 27
SST26VF032BEUI
mand cycle is eight clocks long, the address and data
cycles are each two clocks long, most significant bit
first. Poll the BUSY bit in the Status register, or wait TPP,
for the completion of the internal, self-timed, Write
operation.See Figure 5-27.
5.21 SPI Quad Page-Program
The SPI Quad Page-Program instruction programs up
to 256 Bytes of data in the memory. The data for the
selected page address must be in the erased state
(FFH) before initiating the SPI Quad Page-Program
operation. A SPI Quad Page-Program applied to a pro-
When executing SPI Quad Page-Program, the memory
range for the SST26VF032BEUI is divided into 256
Byte page boundaries. The device handles shifting of
more than 256 Bytes of data by maintaining the last 256
Bytes of data as the correct data to be programmed. If
the target address for the SPI Quad Page-Program
instruction is not the beginning of the page boundary
(A[7:0] are not all zero), and the of bytes of data input
exceeds or overlaps the end of the address of the page
boundary, the excess data inputs wrap around and will
be programmed at the start of that target page.
tected
memory
area
will
be
ignored.
SST26VF032BEUI requires the ICO bit in the configu-
ration register to be set to ‘1’ prior to executing the com-
mand. Prior to the program operation, execute the
WREN instruction.
To execute a SPI Quad Page-Program operation, the
host drives CE# low then sends the SPI Quad Page-
Program command cycle (32H), three address cycles
followed by the data to be programmed, then drives
CE# high. The programmed data must be between 1 to
256 Bytes and in whole Byte increments. The com-
FIGURE 5-27:
SPI QUAD PAGE-PROGRAM SEQUENCE
CE#
MODE 3
MODE 0
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SCK
SIO0
SIO1
SIO2
SIO3
32H
A20A16A12 A8
A4 A0 b4 b0 b4 b0
b4 b0
b5 b1
b6 b2
b7 b3
A13
b5 b1
A21 A17
A9
A5 A1 b5 b1
b6 b2
A22 A18A14A10
A6 A2 b6 b2
MSN LSN
b7 b3
A23 A19 A15 A11
A7 A3 b7 b3
Data Data
Byte 0 Byte 1
Data
Byte
255
Address
20005218 F61.0
5.22 Write-Suspend and Write-Resume
5.23 Write-Suspend During Sector-
Erase or Block-Erase
Write-Suspend allows the interruption of Sector-Erase,
Block-Erase, SPI Quad Page-Program, or Page-Pro-
gram operations in order to erase, program, or read
data in another portion of memory. The original opera-
tion can be continued with the Write-Resume com-
mand. This operation is supported in both SQI and SPI
protocols.
Issuing a Write-Suspend instruction during Sector-
Erase or Block-Erase allows the host to program or
read any sector that was not being erased. The device
will ignore any programming commands pointing to the
suspended sector(s). Any attempt to read from the sus-
pended sector(s) will output unknown data because the
Sector- or Block-Erase will be incomplete.
Only one write operation can be suspended at a time;
if an operation is already suspended, the device will
ignore the Write-Suspend command. Write-Suspend
during Chip-Erase is ignored; Chip-Erase is not a valid
command while a write is suspended. The Write-
Resume command is ignored until any write operation
(Program or Erase) initiated during the Write-Suspend
is complete. The device requires a minimum of 500 µs
between each Write-Suspend command.
To execute a Write-Suspend operation, the host drives
CE# low, sends the Write Suspend command cycle
(B0H), then drives CE# high. The Status register indi-
cates that the erase has been suspended by changing
the WSE bit from ‘0’ to ‘1,’ but the device will not accept
another command until it is ready. To determine when
the device will accept a new command, poll the BUSY
bit in the Status register or wait TWS
.
DS20006152A-page 28
2019 Microchip Technology Inc.
SST26VF032BEUI
a Read Security ID operation in SQI mode, the host
drives CE# low and then sends the Read Security ID
command, two address cycles, and three dummy
cycles.
5.24 Write Suspend During Page
Programming or SPI Quad Page
Programming
Issuing a Write-Suspend instruction during Page Pro-
gramming allows the host to erase or read any sector
that is not being programmed. Erase commands point-
ing to the suspended sector(s) will be ignored. Any
attempt to read from the suspended page will output
unknown data because the program will be incomplete.
After the dummy cycles, the device outputs data on the
falling edge of the SCK signal, starting from the speci-
fied address location. The data output stream is contin-
uous through all SID addresses until terminated by a
low-to-high transition on CE#. See Table 5-5 for the
Security ID address range.
To execute a Write Suspend operation, the host drives
CE# low, sends the Write Suspend command cycle
(B0H), then drives CE# high. The Status register indi-
cates that the programming has been suspended by
changing the WSP bit from ‘0’ to ‘1,’ but the device will
not accept another command until it is ready. To deter-
mine when the device will accept a new command, poll
5.27 Program Security ID
The Program Security ID instruction programs one to
2040 Bytes of data in the user-programmable, Security
ID space. This Security ID space is one-time program-
mable (OTP). The device ignores a Program Security
ID instruction pointing to an invalid or protected
address, see Table 5-5. Prior to the program operation,
execute WREN.
the BUSY bit in the Status register or wait TWS
.
5.25 Write-Resume
To execute a Program SID operation, the host drives
CE# low, sends the Program Security ID command
cycle (A5H), two address cycles, the data to be pro-
grammed, then drives CE# high. The programmed data
must be between 1 to 256 Bytes and in whole Byte
increments.
Write-Resume restarts a Write command that was sus-
pended, and changes the suspend status bit in the Sta-
tus register (WSE or WSP) back to ‘0’.
To execute a Write-Resume operation, the host drives
CE# low, sends the Write Resume command cycle
(30H), then drives CE# high. To determine if the inter-
nal, self-timed Write operation completed, poll the
BUSY bit in the Status register, or wait the specified
time TSE, TBE or TPP for Sector-Erase, Block-Erase, or
Page-Programming, respectively. The total write time
before suspend and after resume will not exceed the
The device handles shifting of more than 256 Bytes of
data by maintaining the last 256 Bytes of data as the
correct data to be programmed. If the target address for
the Program Security ID instruction is not the beginning
of the page boundary, and the number of data input
exceeds or overlaps the end of the address of the page
boundary, the excess data inputs wrap around and will
be programmed at the start of that target page.
uninterrupted write times TSE, TBE or TPP
.
5.26 Read Security ID
The Program Security ID operation is supported in both
SPI and SQI mode. To determine the completion of the
internal, self-timed Program SID operation, poll the
BUSY bit in the software status register, or wait TPSID
for the completion of the internal self-timed Program
Security ID operation.
The Read Security ID operation is supported in both
SPI and SQI modes. To execute a Read Security ID
(SID) operation in SPI mode, the host drives CE# low,
sends the Read Security ID command cycle (88H), two
address cycles, and then one dummy cycle. To execute
TABLE 5-5:
PROGRAM SECURITY ID
Program Security ID
Address Range
0000 – 0007H
0008H – 07FFH
Unique ID Pre-Programmed at factory
User Programmable
2019 Microchip Technology Inc.
DS20006152A-page 29
SST26VF032BEUI
mands function in both SPI and SQI modes. The Status
register may be read at any time, even during a Write
operation. When a Write is in progress, poll the BUSY
bit before sending any new commands to assure that
the new commands are properly received by the
device.
5.28 Lockout Security ID
The Lockout Security ID instruction prevents any future
changes to the Security ID, and is supported in both
SPI and SQI modes. Prior to the operation, execute
WREN.
To execute a Lockout SID, the host drives CE# low,
sends the Lockout Security ID command cycle (85H),
then drives CE# high. Poll the BUSY bit in the software
status register, or wait TPSID, for the completion of the
Lockout Security ID operation.
To Read the Status or Configuration registers, the host
drives CE# low, then sends the Read-Status-Register
command cycle (05H) or the Read Configuration Reg-
ister command (35H). A dummy cycle is required in
SQI mode. Immediately after the command cycle, the
device outputs data on the falling edge of the SCK sig-
nal. The data output stream continues until terminated
by a low-to-high transition on CE#. See Figures 5-28
and 5-29 for the instruction sequence.
5.29 Read-Status Register (RDSR) and
Read-Configuration Register
(RDCR)
The Read-Status Register (RDSR) and Read-Configu-
ration Register (RDCR) commands output the contents
of the Status and Configuration registers. These com-
FIGURE 5-28:
READ-STATUS-REGISTER AND READ-CONFIGURATION REGISTER
SEQUENCE (SQI)
CE#
MODE 3
0
2
4
6
8
SCK MODE 0
MSN LSN
SIO(3:0)
C1 C0
X
X
H0 L0 H0 L0
H0 L0
Dummy Data Byte Data Byte
Data Byte
20005218 F11.1
Note: MSN = Most Significant Nibble; LSN = Least Significant Nibble, C[1:0]=05H or 35H
FIGURE 5-29:
READ-STATUS-REGISTER AND READ-CONFIGURATION REGISTER
SEQUENCE (SPI)
CE#
MODE 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK
SI
MODE 0
05 or 35
HIGH IMPEDANCE
MSB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
Status or Configuration
Register Out
20005218 F62.1
DS20006152A-page 30
2019 Microchip Technology Inc.
SST26VF032BEUI
low, then sends the Write-Status Register command
cycle (01H), two cycles of data, and then drives CE#
high. Values in the second data cycle will be accepted
by the device. See Figures 5-30 and 5-31.
5.30 Write-Status Register (WRSR)
The Write-Status Register (WRSR) command writes
new values to the Configuration register. To execute a
Write-Status Register operation, the host drives CE#
FIGURE 5-30:
WRITE-STATUS-REGISTER SEQUENCE (SQI)
CE#
MODE 3
MODE 0
0
1
2
3
4
5
SCK
MSN LSN
SIO[3:0]
C1 C0 XX XX H0 L0
Status Config-
Command
Byte
uration
Byte
20005218 F63.1
Note: MSN = Most Significant Nibble; LSN = Least Significant Nibble, XX = Don’t Care, C[1:0]=01H
FIGURE 5-31:
WRITE-STATUS-REGISTER SEQUENCE (SPI)
CE#
SCK
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
MODE 3
MODE 0
STATUS
REGISTER
CONFIGURATION
REGISTER
01
XX XX XX XX XX XX XX XX 7 6 5 4 3 2 1 0
SI
MSB
HIGH IMPEDANCE
MSB
MSB
SO
20005218 F64.2
Note: XX = Don’t Care
2019 Microchip Technology Inc.
DS20006152A-page 31
SST26VF032BEUI
Protection Register, Lock-Down Block-Protection Reg-
ister, Non-Volatile Write-Lock Lock-Down Register, SPI
Quad Page program, and Write-Status Register. To
execute a Write Enable the host drives CE# low then
sends the Write Enable command cycle (06H) then
drives CE# high. See Figures 5-32 and 5-33 for the
WREN instruction sequence.
5.31 Write-Enable (WREN)
The Write Enable (WREN) instruction sets the Write-
Enable-Latch bit in the Status register to ‘1,’ allowing
Write operations to occur. The WREN instruction must
be executed prior to any of the following operations:
Sector Erase, Block Erase, Chip Erase, Page Program,
Program Security ID, Lockout Security ID, Write Block-
FIGURE 5-32:
WRITE-ENABLE SEQUENCE (SQI)
CE#
MODE 3
MODE 0
0
1
SCK
SIO[3:0]
0
6
20005218 F12.1
FIGURE 5-33:
WRITE-ENABLE SEQUENCE (SPI)
CE#
MODE 3
0
1
2
3
4
5
6
7
SCK
MODE 0
SI
06
MSB
HIGH IMPEDANCE
SO
20005218 F18.0
DS20006152A-page 32
2019 Microchip Technology Inc.
SST26VF032BEUI
during any internal write operations. Any Write opera-
tion started before executing WRDI will complete. Drive
CE# high before executing WRDI.
5.32 Write-Disable (WRDI)
The Write-Disable (WRDI) instruction sets the Write-
Enable-Latch bit in the Status register to ‘0,’ preventing
Write operations. The WRDI instruction is ignored
To execute a Write-Disable, the host drives CE# low,
sends the Write Disable command cycle (04H), then
drives CE# high. See Figures 5-34 and 5-35.
FIGURE 5-34:
WRITE-DISABLE (WRDI) SEQUENCE (SQI)
CE#
MODE 3
MODE 0
0
1
SCK
SIO(3:0)
0
4
20005218 F33.1
FIGURE 5-35:
WRITE-DISABLE (WRDI) SEQUENCE (SPI)
CE#
MODE 3
0
1
2
3
4
5
6
7
SCK
MODE 0
04
SI
MSB
HIGH IMPEDANCE
SO
20005218 F19.0
2019 Microchip Technology Inc.
DS20006152A-page 33
SST26VF032BEUI
After the command cycle, the device outputs data on
the falling edge of the SCK signal starting with the most
significant bit(s), see Table 5-6 for definitions of each bit
in the Block-Protection register. The RBPR command
does not wrap around. After all data has been output,
the device will output 0H until terminated by a low-to-
high transition on CE#. Figures 5-36 and 5-37.
5.33 Read Block-Protection Register
(RBPR)
The Read Block-Protection Register instruction outputs
the Block-Protection register data which determines
the protection status. To execute a Read Block-Protec-
tion Register operation, the host drives CE# low, and
then sends the Read Block-Protection Register com-
mand cycle (72H). A dummy cycle is required in SQI
mode.
FIGURE 5-36:
READ BLOCK-PROTECTION REGISTER SEQUENCE (SQI)
CE#
MODE 3
0
2
4
6
8
10
12
SCK
SIO[3:0]
C1 C0
X
X
H0 L0 H1 L1 H2 L2 H3 L3 H4 L4
HN LN
MSN LSN
BPR [m:m-7]
BPR [7:0]
20005218 F34.2
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble
Block-Protection Register (BPR), m = 79 for SST26VF032BEUI, C[1:0]=72H
FIGURE 5-37:
READ BLOCK-PROTECTION REGISTER SEQUENCE (SPI)
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23 24
32 33
MODE 0
SCK
72H
SIO0
OP Code
Data Byte 0 Data Byte 1 Data Byte 2
Data Byte N
20005218 F48.0
SIO
DS20006152A-page 34
2019 Microchip Technology Inc.
SST26VF032BEUI
To execute a Write Block-Protection Register operation
the host drives CE# low, sends the Write Block-Protec-
tion Register command cycle (42H), sends 18 cycles of
data, and finally drives CE# high. Data input must be
most significant bit(s) first. See Table 5-6 for definitions
of each bit in the Block-Protection register. See Figures
5-38 and 5-39.
5.34 Write Block-Protection Register
(WBPR)
The Write Block-Protection Register (WBPR) com-
mand changes the Block-Protection register data to
indicate the protection status. Execute WREN before
executing WBPR.
FIGURE 5-38:
WRITE BLOCK-PROTECTION REGISTER SEQUENCE (SQI)
CE#
SCK
MODE 3
MODE 0
0
2
4
6
8
10
12
SIO(3:0)
C1 C0 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5
HN LN
MSN LSN
BPR [79:72]
BPR [7:0]
20005218 F35.1
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble
Block-Protection Register (BPR) C[1:0]=42H
FIGURE 5-39:
WRITE BLOCK-PROTECTION REGISTER SEQUENCE (SPI).
CE#
SCK
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
OP Code
42H
Data Byte0 Data Byte1 Data Byte2
Data ByteN
SI
SO
20005218 F66.1
Note: C[1:0]=42H
2019 Microchip Technology Inc.
DS20006152A-page 35
SST26VF032BEUI
cycling; this allows the Block-Protection register to be
changed. Execute WREN before initiating the Lock-
Down Block-Protection Register instruction.
5.35 Lock-Down Block-Protection
Register (LBPR)
The Lock-Down Block-Protection Register instruction
prevents changes to the Block-Protection register
during device operation. Lock-Down resets after power
To execute a Lock-Down Block-Protection Register, the
host drives CE# low, then sends the Lock-Down Block-
Protection Register command cycle (8DH), then drives
CE# high.
FIGURE 5-40:
LOCK-DOWN BLOCK-PROTECTION REGISTER (SQI)
CE#
SCK
MODE 3
MODE 0
0
1
SIO(3:0)
C1 C0
20005218 F30.1
Note: C[1:0]=8DH
FIGURE 5-41:
LOCK-DOWN BLOCK-PROTECTION REGISTER (SPI)
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
SCK
SIO0
8D
SIO[3:1]
20005218 F67.0
DS20006152A-page 36
2019 Microchip Technology Inc.
SST26VF032BEUI
After CE# goes high, the non-volatile bits are pro-
grammed and the programming time-out must com-
plete before any additional commands, other than
Read Status Register, can be entered. Poll the BUSY
bit in the Status register, or wait TPP, for the completion
of the internal, self-timed, Write operation. Data inputs
must be most significant bit(s) first.
5.36 Non-Volatile Write-Lock Lock-
Down Register (nVWLDR)
The Non-Volatile Write-Lock Lock-Down Register
(nVWLDR) instruction controls the ability to change the
Write-Lock bits in the Block-Protection register. Exe-
cute WREN before initiating the nVWLDR instruction.
To execute nVWLDR, the host drives CE# low, then
sends the nVWLDR command cycle (E8H), followed by
18 cycles of data, and then drives CE# high.
FIGURE 5-42:
WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SQI)
CE#
MODE 3
MODE 0
0
2
4
6
8
10
12
SCK
SIO(3:0)
E
8
H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5
HN LN
MSN LSN
BPR [m:m-7]
BPR [7:0]
20005218 F36.0
Note:
MSN= Most Significant Nibble; LSN = Least Significant Nibble
Write-Lock Lock-Down Register (nVWLDR) m = 79
FIGURE 5-43:
WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SPI)
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
SCK
SI
OP Code
E8H
Data Byte0 Data Byte1 Data Byte2
Data ByteN
SO
20005218 F69.1
2019 Microchip Technology Inc.
DS20006152A-page 37
SST26VF032BEUI
To execute a ULBPR instruction, the host drives CE#
low, then sends the ULBPR command cycle (98H), and
then drives CE# high.
5.37 Global Block-Protection Unlock
(ULBPR)
The Global Block-Protection Unlock (ULBPR) instruc-
tion clears all write-protection bits in the Block-Protec-
tion register, except for those bits that have been
locked down with the nVWLDR command. Execute
WREN before initiating the ULBPR instruction.
FIGURE 5-44:
GLOBAL BLOCK-PROTECTION UNLOCK (SQI)
CE#
SCK
MODE 3
MODE 0
0
1
SIO(3:0)
C1 C0
20005218 F20.1
Note: C[1:0]=98H
FIGURE 5-45:
GLOBAL BLOCK-PROTECTION UNLOCK (SPI)
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
SCK
SIO0
98
SIO[3:1]
20005218 F68.0
DS20006152A-page 38
2019 Microchip Technology Inc.
SST26VF032BEUI
TABLE 5-6:
BLOCK-PROTECTION REGISTER FOR SST26VF032BEUI (1 OF 2)1
BPR Bits
Write Lock/
nVWLDR2
Protected Block
Size
Read Lock
Address Range
3FE000H - 3FFFFFH
3FC000H - 3FDFFFH
3FA000H - 3FBFFFH
3F8000H - 3F9FFFH
006000H - 007FFFH
004000H - 005FFFH
002000H - 003FFFH
000000H - 001FFFH
3F0000H - 3F7FFFH
008000H - 00FFFFH
3E0000H - 3EFFFFH
3D0000H - 3DFFFFH
3C0000H - 3CFFFFH
3B0000H - 3BFFFFH
3A0000H - 3AFFFFH
390000H - 39FFFFH
380000H - 38FFFFH
370000H - 37FFFFH
360000H - 36FFFFH
350000H - 35FFFFH
340000H - 34FFFFH
330000H - 33FFFFH
320000H - 32FFFFH
310000H - 31FFFFH
300000H - 30FFFFH
2F0000H - 2FFFFFH
2E0000H - 2EFFFFH
2D0000H - 2DFFFFH
2C0000H - 2CFFFFH
2B0000H - 2BFFFFH
2A0000H - 2AFFFFH
290000H - 29FFFFH
280000H - 28FFFFH
270000H - 27FFFFH
260000H - 26FFFFH
250000H - 25FFFFH
240000H - 24FFFFH
230000H - 23FFFFH
220000H - 22FFFFH
210000H - 21FFFFH
200000H - 20FFFFH
1F0000H - 1FFFFFH
1E0000H - 1EFFFFH
79
77
75
73
71
69
67
65
78
76
74
72
70
68
66
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
8 KByte
8 KByte
8 KByte
8 KByte
8 KByte
8 KByte
8 KByte
8 KByte
32 KByte
32 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
2019 Microchip Technology Inc.
DS20006152A-page 39
SST26VF032BEUI
TABLE 5-6:
BLOCK-PROTECTION REGISTER FOR SST26VF032BEUI (CONTINUED) (2 OF 2)1
BPR Bits
Write Lock/
nVWLDR2
Protected Block
Size
Read Lock
Address Range
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
1D0000H - 1DFFFFH
1C0000H - 1CFFFFH
1B0000H - 1BFFFFH
1A0000H - 1AFFFFH
190000H - 19FFFFH
180000H - 18FFFFH
170000H - 17FFFFH
160000H - 16FFFFH
150000H - 15FFFFH
140000H - 14FFFFH
130000H - 13FFFFH
120000H - 12FFFFH
110000H - 11FFFFH
100000H - 10FFFFH
0F0000H - 0FFFFFH
0E0000H - 0EFFFFH
0D0000H - 0DFFFFH
0C0000H - 0CFFFFH
0B0000H - 0BFFFFH
0A0000H - 0AFFFFH
090000H - 09FFFFH
080000H - 08FFFFH
070000H - 07FFFFH
060000H - 06FFFFH
050000H - 05FFFFH
040000H - 04FFFFH
030000H - 03FFFFH
020000H - 02FFFFH
010000H - 01FFFFH
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
64 KByte
8
7
6
5
4
3
2
1
0
1. The default state after a power-on reset is write-protected BPR[79:0] = 5555 FFFFFFFF FFFFFFFF FFFFFFFF
2. nVWLDR bits are one-time-programmable. Once a nVWLDR bit is set, the protection state of that particular block is perma-
nently write-locked.
DS20006152A-page 40
2019 Microchip Technology Inc.
SST26VF032BEUI
6.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maxi-
mum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these conditions or conditions greater than those defined in the operational
sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may
affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
TABLE 6-2:
AC CONDITIONS OF TEST1
TABLE 6-1:
OPERATING RANGE
Input Rise/Fall Time
Output Load
Range
Ambient Temp
VDD
3ns
CL = 30 pF
Industrial
-40°C to +85°C
2.3-3.6V
1. See Figure 8-5.
When VDD drops from the operating voltage to below
the minimum VDD threshold at power-down, all opera-
tions are disabled and the device does not respond to
commands. Data corruption may result if a power-down
occurs while a Write-Registers, program, or erase
operation is in progress. See Figure 6-2.
6.1
Power-Up Specifications
All functionalities and DC specifications are specified
for a VDD ramp rate of greater than 1V per 100 ms (0V
to 3.0V in less than 300 ms). See Table 6-3 and Figure
6-1 for more information.
TABLE 6-3:
Symbol
RECOMMENDED SYSTEM POWER-UP/DOWN TIMINGS
Parameter
Minimum
100
Max
Units
µs
Condition
1
TPU-READ
VDD Min to Read Operation
VDD Min to Write Operation
Power-down Duration
VDD off time
1
TPU-WRITE
100
µs
1
TPD
100
ms
V
VOFF
0.3
0V recommended
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2019 Microchip Technology Inc.
DS20006152A-page 41
SST26VF032BEUI
FIGURE 6-1:
VDD
POWER-UP TIMING DIAGRAM
VDD Max
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
VDD Min
TPU-READ
TPU-WRITE
Device fully accessible
Time
20005218 F27.0
FIGURE 6-2:
POWER-DOWN AND VOLTAGE DROP DIAGRAM
VDD
VDD Max
No Device Access Allowed
VDD Min
TPU
Device
Access
Allowed
VOFF
TPD
Time
20005218 F72.0
DS20006152A-page 42
2019 Microchip Technology Inc.
SST26VF032BEUI
7.0
DC CHARACTERISTICS
TABLE 7-1:
DC OPERATING CHARACTERISTICS (VDD = 2.3 - 3.6V)
Limits
Symbol Parameter
Min
Typ
Max
Units Test Conditions
IDDR1
IDDR2
IDDW
Read Current
8
15
mA
mA
mA
VDD=VDD Max,
CE#=0.1 VDD/0.9 VDD@40 MHz,
SO=open
Read Current
20
25
VDD = VDD Max,
CE#=0.1 VDD/0.9 VDD@104 MHz,
SO=open
Program and Erase Cur-
rent
CE#=VDD Max
ISB
ILI
Standby Current
15
45
2
µA
µA
µA
V
CE#=VDD, VIN=VDD or VSS
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
Input Leakage Current
Output Leakage Current
Input Low Voltage
ILO
VIL
VIH
VOL
VOH
2
0.8
Input High Voltage
Output Low Voltage
Output High Voltage
0.7 VDD
VDD-0.2
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
V
TABLE 7-2:
Parameter
CAPACITANCE (TA = 25°C, F=1 MHZ, OTHER PINS OPEN)
Description
Test Condition
VOUT = 0V
VIN = 0V
Maximum
8 pF
1
COUT
Output Pin Capacitance
Input Capacitance
1
CIN
6 pF
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7-3:
RELIABILITY CHARACTERISTICS
Parameter Minimum Specification
Symbol
Units
Cycles
Years
mA
Test Method
1
NEND
Endurance
Data Retention
Latch Up
100,000
100
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1
TDR
1
ILTH
100 + IDD
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7-4:
WRITE TIMING PARAMETERS (VDD = 2.3-3.6V)
Symbol
TSE
Parameter
Minimum
Maximum
Units
ms
ms
ms
ms
ms
µs
Sector-Erase
25
25
50
1.5
1.5
25
25
TBE
Block-Erase
TSCE
Chip-Erase
1
TPP
Page-Program
TPSID
TWS
Program Security-ID
Write-Suspend Latency
Write-Protection Enable Bit Latency
TWpen
ms
1. Estimate for typical conditions less than 256 bytes: Programming Time (µs) = 55 + (3.75 x # of bytes)
2019 Microchip Technology Inc.
DS20006152A-page 43
SST26VF032BEUI
8.0
AC CHARACTERISTICS
TABLE 8-1:
AC OPERATING CHARACTERISTICS (VDD1 = 2.3 - 3.6V)
Limits - 40 MHz Limits - 80 MHz
Limits - 104 MHz
Symbol
Parameter
Min
Max
40
Min
Max
80
Min
Max
104
9.6
Units
MHz
ns
FCLK
Serial Clock Frequency
Serial Clock Period
TCLK
25
12.5
TSCKH
TSCKL
TSCKR
Serial Clock High Time
Serial Clock Low Time
11
11
0.1
0.1
8
5.5
5.5
0.1
0.1
5
4.5
4.5
0.1
0.1
5
ns
ns
2
Serial Clock Rise Time (slew rate)
Serial Clock Fall Time (slew rate)
CE# Active Setup Time
CE# Active Hold Time
V/ns
V/ns
ns
2
TSCKF
3
TCES
3
TCEH
8
5
5
ns
3
TCHS
CE# Not Active Setup Time
CE# Not Active Hold Time
CE# High Time
8
5
5
ns
3
TCHH
TCPH
TCHZ
TCLZ
THLS
THHS
THLH
THHH
THZ
8
5
5
ns
25
12.5
12
ns
CE# High to High-Z Output
SCK Low to Low-Z Output
HOLD# Low Setup Time
HOLD# High Setup Time
HOLD# Low Hold Time
HOLD# High Hold Time
HOLD# Low-to-High-Z Output
HOLD# High-to-Low-Z Output
Data In Setup Time
19
12.5
12
ns
0
8
8
8
8
0
5
5
5
5
0
5
5
5
5
ns
ns
ns
ns
ns
8
8
8
8
8
8
ns
TLZ
ns
TDS
3
4
0
3
4
0
3
4
0
ns
TDH
Data In Hold Time
ns
TOH
TV
Output Hold from SCK Change
Output Valid from SCK
ns
8/5 4
8/5 4
8/5 4
ns
1. Maximum operating frequency for 2.3-3.6V is 80 MHz and for 2.7-3.6V is 104 MHz.
4
2. Maximum Rise and Fall time may be limited by T
3. Relative to SCK.
and T
requirements
SCKH
SCKL
4. 30 pF/10 pF
DS20006152A-page 44
2019 Microchip Technology Inc.
SST26VF032BEUI
FIGURE 8-1:
HOLD TIMING DIAGRAM
CE#
T
T
T
HLS
HHS
HHH
SCK
T
HLH
T
HZ
T
LZ
SO
SI
HOLD#
20005218 F43.1
FIGURE 8-2:
SERIAL INPUT TIMING DIAGRAM
T
CPH
CE#
T
CHH
T
T
CEH
T
CHS
CES
T
SCKF
SCK
T
T
DH
DS
T
SCKR
SIO[3:0]
LSB
MSB
20005218 F70.1
FIGURE 8-3:
SERIAL OUTPUT TIMING DIAGRAM
CE#
T
T
SCKH
SCKL
SCK
T
OH
T
T
CLZ
CHZ
SIO[3:0]
MSB
LSB
T
V
20005218 F25.1
TABLE 8-2:
RESET TIMING PARAMETERS
TR(i)
TR(o)
TR(p)
TR(e)
Parameter
Minimum
Maximum
Units
ns
Reset to Read (non-data operation)
Reset Recovery from Program or Suspend
Reset Recovery from Erase
20
100
1
µs
ms
2019 Microchip Technology Inc.
DS20006152A-page 45
SST26VF032BEUI
FIGURE 8-4:
RESET TIMING DIAGRAM
T
CPH
CE#
CLK
MODE 3
MODE 0
MODE 3
MODE 0
MODE 3
MODE 0
SIO(3:0)
C1 C0
C3 C2
20005218 F14.0
Note: C[1:0] = 66H; C[3:2] = 99H
FIGURE 8-5:
AC INPUT/OUTPUT REFERENCE WAVEFORMS
V
IHT
V
HT
V
HT
INPUT
REFERENCE POINTS
OUTPUT
V
V
LT
LT
V
ILT
20005218 F28.0
AC test inputs are driven at VIHT (0.9VDD) for a logic ‘1’ and VILT (0.1VDD) for a logic ‘0’. Measure-
ment reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and
fall times (10% 90%) are <3 ns.
Note: V - V
Test
Test
HT
HIGH
- V
LOW
V
V
V
LT
- V
- V
HIGH Test
LOW Test
IHT
ILT
INPUT
INPUT
DS20006152A-page 46
2019 Microchip Technology Inc.
SST26VF032BEUI
9.0
9.1
PACKAGING INFORMATION
Package Marking
8-Lead SOIJ (5.28 mm)
Example
26F032B
e
3
SM
1506343
1st Line Marking
Codes
Part Number
SOIJ
SST26VF032BEUI
26F032B
Legend: XX...X Part number or part number code)
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
Note: For very small packages with no room for the Pb-free JEDEC® designator
, the marking will only appear on the outer carton or reel label.
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2019 Microchip Technology Inc.
DS20006152A-page 47
SST26VF032BEUI
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006152A-page 48
2019 Microchip Technology Inc.
SST26VF032BEUI
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006152A-page 49
SST26VF032BEUI
TABLE 9-1:
Revision
A
REVISION HISTORY
Initial release of data sheet
Description
Date
Jan 2019
•
DS20006152A-page 50
2019 Microchip Technology Inc.
SST26VF032BEUI
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQs), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2019 Microchip Technology Inc.
DS20006152A-page 51
SST26VF032BEUI
10.0 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
–
/
X
XXX
XX
Valid Combinations:
PART NO.
Device
SST26VF032BEUI-104I/SM
SST26VF032BEUIT-104I/SM
Tape/Reel
Indicator
Operating
Frequency
Package
Temperature
Device:
SST26VF032BEUI =32 Mbit, 2.5/3.0V, SQI Flash Mem-
ory WP#/Hold# pin Enable at power-up
Tape and
Reel Flag:
T
= Tape and Reel
= Tube or Tray
(blank)
Operating
Frequency:
104
I
= 104 MHz
Temperature:
Package:
= -40°C to +85°C
= SOIJ (5.28 mm), 8-lead
SM
NOTE: Contact your Microchip Sales Office for Automotive AECQ-100 ordering
information. Valid automotive part numbers are not listed on this page.
DS20006152A-page 52
2019 Microchip Technology Inc.
SST26VF032BEUI
11.0 APPENDIX
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (1 OF 16)
Bit Address
Data
Comments
SFDP Header
SFDP Header: 1st DWORD
00H
01H
02H
03H
A7:A0
A15:A8
A23:A16
A31:A24
53H
46H
44H
50H
SFDP Signature
SFDP Signature=50444653H
SFDP Header: 2nd DWORD
04H
05H
06H
07H
A7:A0
A15:A8
A23:A16
A31:A24
06H
01H
02H
FFH
SFDP Minor Revision Number
SFDP Major Revision Number
Number of Parameter Headers (NPH)=3
Unused. Contains FF and can not be changed.
Parameter Headers
JEDEC Flash Parameter Header: 1st DWORD
Parameter ID Least Significant Bit (LSB) Number.
When this field is set to 00H, it indicates a JEDEC-specified header. For
vendor-specified headers, this field must be set to the vendor’s manufac-
turer ID.
08H
09H
A7:A0
00H
06H
Parameter Table Minor Revision Number
Minor revisions are either clarifications or changes that add parameters
in existing Reserved locations. Minor revisions do NOT change overall
structure of SFDP. Minor Revision starts at 00H.
A15:A8
Parameter Table Major Revision Number
Major revisions are changes that reorganize or add parameters to loca-
tions that are NOT currently Reserved. Major revisions would require
code (BIOS/firmware) or hardware change to get previously defined dis-
coverable parameters. Major Revision starts at 01H
0AH
0BH
A23:A16
A31:A24
01H
10H
Parameter Table Length
Number of DWORDs that are in the Parameter table
JEDEC Flash Parameter Header: 2nd DWORD
Parameter Table Pointer (PTP)
A 24-bit address that specifies the start of this header’s Parameter table
in the SFDP structure. The address must be DWORD-aligned.
0CH
0DH
0EH
0FH
A7:A0
A15:A8
A23:A16
A31:A24
30H
00H
00H
FFH
Parameter ID Most Significant Bit (MSB) Number
JEDEC Sector Map Parameter Header: 3rd DWORD
Parameter ID LSB Number.
Sector-Map, Function-Specific table is assigned 81H
10H
11H
A7:A0
81H
00H
Parameter Table Minor Revision Number
Minor revisions are either clarifications or changes that add parameters
in existing Reserved locations. Minor revisions do NOT change overall
structure of SFDP. Minor Revision starts at 00H.
A15:A8
Parameter Table Major Revision Number
Major revisions are changes that reorganize or add parameters to loca-
tions that are NOT currently Reserved. Major revisions would require
code (BIOS/firmware) or hardware change to get previously defined dis-
coverable parameters. Major Revision starts at 01H
12H
A23:A16
01H
2019 Microchip Technology Inc.
DS20006152A-page 53
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (2 OF 16)
Bit Address
Data
Comments
Parameter Table Length
Number of DWORDs that are in the Parameter table
13H
A31:A24
06H
JEDEC Flash Parameter Header: 4th DWORD
Parameter Table Pointer (PTP)
This 24-bit address specifies the start of this header’s Parameter Table in
the SFDP structure. The address must be DWORD-aligned.
14H
15H
16H
17H
A7:A0
A15:A8
A23:A16
A31:A24
00H
01H
00H
FFH
Parameter ID MSB Number
Microchip (Vendor) Parameter Header: 5th DWORD
ID Number
Manufacture ID (vendor specified header)
18H
A7:A0
BFH
19H
1AH
1BH
A15:A8
A23:A16
A31:A24
00H
02H
1CH
Parameter Table Minor Revision Number
Parameter Table major Revision Number, Revision 2.0
Parameter Table Length, 28 Double Words
Microchip (Vendor) Parameter Header: 6th DWORD
1CH
1DH
1EH
1FH
A7:A0
A15:A8
A23:A16
A31:A24
00H
02H
00H
01H
Parameter Table Pointer (PTP)
This 24-bit address specifies the start of this header’s Parameter Table in
the SFDP structure. The address must be DWORD-aligned.
Used to indicate bank number (vendor specific)
JEDEC Flash Parameter Table
JEDEC Flash Parameter Table: 1st DWORD
Block/Sector Erase Sizes
00: Reserved
A1:A0
01: 4 KByte Erase
10: Reserved
11: Use this setting only if the 4 KByte erase is unavailable.
Write Granularity
0:
Single-byte programmable devices or buffer programmable devices
with buffer is less than 64 bytes (32 Words).
A2
A3
1:
For buffer programmable devices when the buffer size is 64
bytes (32 Words) or larger.
30H
FDH
Volatile Status Register
0:
Target flash has nonvolatile status bit. Write/Erase commands do
not require status register to be written on every power on.
Target flash has volatile status bits
1:
Write Enable Opcode Select for Writing to Volatile Status Register
0:
0x50. Enables a status register write when bit 3 is set to 1.
A4
1:
0x06 Enables a status register write when bit 3 is set to 1.
A7:A5
Unused. Contains 111b and can not be changed
DS20006152A-page 54
2019 Microchip Technology Inc.
SST26VF032BEUI
TABLE 11-1:
Address
31H
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (3 OF 16)
Bit Address
Data
Comments
A15:A8
20H
4 KByte Erase Opcode
Supports (1-1-2) Fast Read
A16
0:
(1-1-2) Fast Read NOT supported
1:
(1-1-2) Fast Read supported
Address Bytes
Number of bytes used in addressing flash array read, write and erase
00: 3-Byte only addressing
01: 3- or 4-Byte addressing (e.g. defaults to 3-Byte mode; enters 4-Byte
mode on command)
A18:A17
10: 4-Byte only addressing
11: Reserved
Supports Double Transfer Rate (DTR) Clocking
Indicates the device supports some type of double transfer rate clocking.
A19
A20
0:
DTR NOT supported
1:
DTR Clocking supported
Supports (1-2-2) Fast Read
Device supports single input opcode, dual input address, and dual output
data Fast Read.
32H
F1H
0:
(1-2-2) Fast Read NOT supported.
1:
(1-2-2) Fast Read supported.
Supports (1-4-4) Fast Read
Device supports single input opcode, quad input address, and quad out-
put data Fast Read
A21
A22
0:
(1-4-4) Fast Read NOT supported.
1:
(1-4-4) Fast Read supported.
Supports (1-1-4) Fast Read
Device supports single input opcode & address and quad output data
Fast Read.
0:
(1-1-4) Fast Read NOT supported.
1:
(1-1-4) Fast Read supported.
A23
Unused. Contains ‘1’ can not be changed.
33H
A31:A24
FFH
Unused. Contains FF can not be changed
JEDEC Flash Parameter Table: 2nd DWORD
34H
35H
36H
37H
A7:A0
A15:A8
A23:A16
A31:A24
FFH
FFH
FFH
01H
Flash Memory Density
SST26VF032BEUI = 01FFFFFFH
JEDEC Flash Parameter Table: 3rd DWORD
(1-4-4) Fast Read Number of Wait states (dummy clocks) needed
before valid output
00100b: 4 dummy clocks (16 dummy bits) are needed with a quad input
address phase instruction
A4:A0
38H
39H
44H
Quad Input Address Quad Output (1-4-4) Fast Read Number of Mode
Bits
010b: 2 dummy clocks (8 mode bits) are needed with a single input
opcode, quad input address and quad output data Fast Read Instruction.
A7:A5
(1-4-4) Fast Read Opcode
Opcode for single input opcode, quad input address, and quad output
data Fast Read.
A15:A8
EBH
2019 Microchip Technology Inc.
DS20006152A-page 55
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (4 OF 16)
Bit Address
Data
Comments
(1-1-4) Fast Read Number of Wait states (dummy clocks) needed
before valid output
01000b: 8 dummy bits are needed with a single input opcode & address
and quad output data Fast Read Instruction
A20:A16
3AH
08H
(1-1-4) Fast Read Number of Mode Bits
A23:A21
A31:A24
000b: No mode bits are needed with a single input opcode & address and
quad output data Fast Read Instruction
(1-1-4) Fast Read Opcode
Opcode for single input opcode & address and quad output data Fast
Read.
3BH
6BH
JEDEC Flash Parameter Table: 4th DWORD
(1-1-2) Fast Read Number of Wait states (dummy clocks) needed
before valid output
01000b: 8 dummy clocks are needed with a single input opcode, address
and dual output data fast read instruction.
A4:A0
3CH
08H
(1-1-2) Fast Read Number of Mode Bits
A7:A5
A15:A8
A20:A16
A23:A21
A31:A24
000b: No mode bits are needed with a single input opcode & address and
quad output data Fast Read Instruction
(1-1-2) Fast Read Opcode
Opcode for single input opcode& address and dual output data Fast Read.
3DH
3EH
3BH
80H
(1-2-2) Fast Read Number of Wait states (dummy clocks) needed
before valid output
00010b: 0 clocks of dummy cycle.
(1-2-2) Fast Read Number of Mode Bits (in clocks)
010b: 4 clocks of mode bits are needed
(1-2-2) Fast Read Opcode
Opcode for single input opcode, dual input address, and dual output data
Fast Read.
3FH
BBH
JEDEC Flash Parameter Table: 5th DWORD
Supports (2-2-2) Fast Read
Device supports dual input opcode& address and dual output data Fast
Read.
A0
A3:A1
A4
0:
(2-2-2) Fast Read NOT supported.
1:
(2-2-2) Fast Read supported.
Reserved. Bits default to all 1’s.
40H
FEH
Supports (4-4-4) Fast Read
Device supports Quad input opcode & address and quad output data
Fast Read.
0:
(4-4-4) Fast Read NOT supported.
1:
(4-4-4) Fast Read supported.
A7:A5
A15:A8
A23:A16
A31:A24
Reserved. Bits default to all 1’s.
Reserved. Bits default to all 1’s.
Reserved. Bits default to all 1’s.
Reserved. Bits default to all 1’s.
41H
42H
43H
FFH
FFH
FFH
DS20006152A-page 56
2019 Microchip Technology Inc.
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (5 OF 16)
Bit Address
Data
Comments
JEDEC Flash Parameter Table: 6th DWORD
44H
45H
A7:A0
FFH
FFH
Reserved. Bits default to all 1’s.
Reserved. Bits default to all 1’s.
A15:A8
(2-2-2) Fast Read Number of Wait states (dummy clocks) needed
before valid output
00000b: No dummy bit is needed
A20:A16
A23:A21
A31:A24
46H
47H
00H
FFH
(2-2-2) Fast Read Number of Mode Bits
000b: No mode bits are needed
(2-2-2) Fast Read Opcode
Opcode for dual input opcode& address and dual output data Fast Read.
(not supported)
JEDEC Flash Parameter Table: 7th DWORD
48H
49H
A7:A0
FFH
FFH
Reserved. Bits default to all 1’s.
Reserved. Bits default to all 1’s.
A15:A8
(4-4-4) Fast Read Number of Wait states (dummy clocks) needed
before valid output
00100b: 4 clocks dummy are needed with a quad input opcode &
address and quad output data Fast Read Instruction
A20:A16
4AH
44H
(4-4-4) Fast Read Number of Mode Bits
A23:A21
A31:A24
010b: 2 clocks mode bits are needed with a quad input opcode & address
and quad output data Fast Read Instruction
(4-4-4) Fast Read Opcode
Opcode for quad input opcode/address, quad output data Fast Read
4BH
0BH
JEDEC Flash Parameter Table: 8th DWORD
Sector Type 1 Size
4CH
4DH
4EH
4FH
A7:A0
A15:A8
A23:A16
A31:A24
0CH
20H
0DH
D8H
4 KByte, Sector/block size = 2N bytes
Sector Type 1 Opcode
Opcode used to erase the number of bytes specified by Sector Type 1
Size.
Sector Type 2 Size
8 KByte, Sector/block size = 2N bytes
Sector Type 2 Opcode
Opcode used to erase the number of bytes specified by Sector Type 2
Size.
JEDEC Flash Parameter Table: 9th DWORD
Sector Type 3 Size
50H
51H
52H
53H
A7:A0
A15:A8
A23:A16
A31:A24
0FH
D8H
10H
D8H
32 KByte, Sector/block size = 2N bytes
Sector Type 3 Opcode
Opcode used to erase the number of bytes specified by Sector Type 3
Size.
Sector Type 4 Size
64 KByte, Sector/block size = 2N bytes
Sector Type 4 Opcode
Opcode used to erase the number of bytes specified by Sector Type 4
Size
2019 Microchip Technology Inc.
DS20006152A-page 57
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (6 OF 16)
Bit Address Data Comments
JEDEC Flash Parameter Table: 10th DWORD
Multiplier from typical erase time to maximum erase time
Maximum time = 2*(count + 1)*Typical erase time
Count = 0
A3:A0
A3:A0= 0000b
Erase Type 1 Erase, Typical time
Typical Time = (count +1)*units
54H
20H
1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s
10:9 units (00b:1ms, 01b: 16ms, 10b:128ms, 11b:1s)
A8:A4 count = 12 = 10010b
A7:A4
A10:A8
A15:A11
A17:A16
A10:A9 unit = 1ms = 00b
A10:A8=001b
Erase Type 2 Erase, Typical time
Typical time = (count+1)*units
1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s
17:16 units (00b:1ms, 01b:16ms, 10b:128ms, 11b:1s)
A15:A11 count = 12 =10010b
55H
56H
91H
48H
A17:A16 unit = 1ms =00b
A17:A16=00b
Erase Type 3 Erase, Typical time
Typical time = (count+1)*units
1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s
24:23 units (00b: 1ms, 01b: 16ms, 10b:128ms, 11b:1s)
A22:A18 count = 12 = 10010b
A24:A23 unit = 1ms = 00b
A23:A18
A24
A24=0b
Erase Type 4 Erase, Typical time
Typical time = (count+1)*units
1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s
31:30 units (00b: 1ms, 01b: 16ms, 10b:128ms, 11b:1s)
57H
24H
A31:A25
A29:A25 count=12=10010b
A31:A30 unit = 1ms =00b
JEDEC Flash Parameter Table: 11th DWORD
Multiplier from Typical Program Time to Maximum Program Time
Maximum time = 2*(count +1)*Typical program time.
Count =0.
A3:A0=0000b
A3:A0
A7:A4
58H
80H
Page Size
Page size = 2N bytes.
N=8
A7:A4 =1000b
Page Program Typical time
Program time = (count+1)*units
13 units (0b: 8µs, 1b: 64µs)
A13:A8
A12:A8 count=11 = 01111b
A13 unit = 64µs = 1b
59H
6FH
Byte Program Typical time, first byte
Typical time = (count+1)*units
18 units (0b: 1µs, 1b: 8µs)
A15:A14
A17:A14 count = 5 = 0101b
A18 =8µs=1b
DS20006152A-page 58
2019 Microchip Technology Inc.
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (7 OF 16)
Bit Address
Data
Comments
A18:A16
A18:A16=101b
Byte Program Typical time, Additional Byte
Typical time = (count+1)*units
23 units (0b: 1µs, 1b: 8µs)
5AH
1DH
A23:A19
A22:A19 count = 0011b
A23=1μs=0b
Chip Erase Typical Time
Typical time = (count+1)*units
16ms to 512ms, 256ms to 8192ms, 4s to 128s, 64s to 2048s
A28:A24 count =1=00001b
A30:A29 units =16ms=00b
A30:A:24
A31
5BH
81H
Reserved
A31=1b
JEDEC Flash Parameter Table: 12th DWORD
Prohibited Operations During Program Suspend
xxx0b: May not initiate a new erase anywhere
xxx1b:May not initiate a new erase in the program suspended page size
xx0xb:May not initiate a new page program anywhere
xx1xb: May not initiate a new page program in program suspended page size.
x0xxb:Refer to the Data Sheet
A3:A0
x1xxb: May not initiate a read in the program suspended page size
0xxxb: Additional erase or program restrictions apply
1xxxb: The erase and program restrictions in bits 1:0 are sufficient
Prohibited Operation During Erase Suspend
xxx0b: May not initiate a new erase anywhere
xxx1b:May not initiate a new erase in the erase suspended page size
xx0xb:May not initiate a new page program anywhere
xx1xb: May not initiate a new page program in erase suspended
erase type size.
5CH
EDH
A7:A4
x0xxb:Refer to the Data Sheet
x1xxb: May not initiate a read in the erase suspended page size
0xxxb: Additional erase or program restrictions apply
1xxxb: The erase and program restrictions in bits 5:4 are sufficient
A8
Reserved = 1b
Program Resume to Suspend Interval
The device requires this typical amount of time to make progress on the
program operation before allowing another suspend.
Interval =500µs
A12:A9
Program resume to suspend interval =(count+1)*64µs
A12:A9= 7 =0111b
Suspend in-progress program max latency
Maximum time required by the flash device to suspend an in-progress
program and be ready to accept another command which accesses the
flash array.
5DH
0FH
A15:A13
Max latency = 25µs
program max latency =(count+1)*units
units (00b:128ns, 01b:1µs, 10b:8µs, 11b:64µs)
A17:A13= count = 24 = 11000b
A19:A18 = 1µs =01b
2019 Microchip Technology Inc.
DS20006152A-page 59
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (8 OF 16)
Bit Address
Data
Comments
0111b
A19:A16
Erase Resume to Suspend Interval
The device requires this typical amount of time to make progress on the
erase operation before allowing another suspend.
Interval = 500µs
5EH
77H
A23:A20
Erase resume to suspend interval =(count+1)*64µs
A23:A20= 7 =0111b
Suspend in-progress erase max latency
Maximum time required by the flash device to suspend an in-progress
erase and be ready to accept another command which accesses the
flash array.
A30:A24
Max latency = 25µs
Erase max latency =(count+1)*units
units (00b:128ns, 01b:1µs, 10b:8µs, 11b:64µs)
5FH
38H
A28:A24= count = 24 = 11000b
A30:A29 = 1µs =01b
Suspend/Resume supported
0:supported
A31
1:not supported
JEDEC Flash Parameter Table: 13th DWORD
60H
61H
62H
63H
A7:A0
A15:A8
A23:A16
A31:A24
30H
B0H
30H
B0H
Program Resume Instruction
Program Suspend Instruction
Resume Instruction
Suspend Instruction
JEDEC Flash Parameter Table: 14th DWORD
A1:A0
Reserved = 11b
Status Register Polling Device Busy
111101b: Use of legacy polling is supported by reading the status register
with 05h instruction and checking WIP bit [0] (0=ready, 1=busy)
64H
F7H
A7:A2
A14:A8
A15
Exit Deep Power-down to next operation delay
Exit Power-down Instruction
65H
66H
FFH
FFH
A22:A16
A23
Enter Power-down instruction
A30:A24
Deep Power-down Supported
0:supported
1:not supported
67H
FFH
A31
JEDEC Flash Parameter Table: 15th DWORD
4-4-4 mode disable sequences
A3:A0
A7:A4
Xxx1b: issue FF instruction
1xxxb: issue the Soft Reset 66/99 sequence.
68H
29H
4-4-4 mode enable sequences
X_xx1xb: issue instruction 38h
DS20006152A-page 60
2019 Microchip Technology Inc.
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (9 OF 16)
Bit Address
Data
Comments
4-4-4 mode enable sequences
A8 = 0
A8
0-4-4 mode supported
0:not supported
1:supported
A9
69H
C2H
0-4-4 Mode Exit Method
X1_xxxx:Mode Bit[7:0] Not= AXh
1x_xxxx Reserved = 1
A15:A10
0-4-4 Mode Entry Method
X1xxb: M[7:0]=AXh
1xxxb:Reserved =1
A19:A16
A22:A20
6AH
6BH
5CH
FFH
Quad Enable Requirements (QER)
101b: Quad Enable is bit 1 of the configuration register.
HOLD and Reset Disable
0:feature is not supported
A23
A31:A24
Reserved bits = 0xFF
JEDEC Flash Parameter Table: 16th DWORD
Volatile or Non-Volatile Register and Write Enable Instructions for
Status Register 1
Xx1_xxxxb:Status Register 1 contains a mix of volatile and non-volatile
bits. The 06h instruction is used to enable writing to the register.
X1x_xxxxb: Reserved = 1
A6:A0
6C
6D
F0H
30H
1xx_xxxxb: Reserved = 1
A7
Reserved =1b
Soft Reset and Rescue Sequence Support
X1_xxxxb: reset enable instruction 66h is issued followed by reset
instruction 99h.
A13:A8
1x_xxxxb: exit 0-4-4 mode is required prior to other reset sequences.
Exit 4-Byte Addressing
Not supported
A15:A14
A23:A16
Exit 4-Byte Addressing
Not supported
A23 and A22 are Reserved bits which are = 1
6E
6F
C0H
80H
Enter 4-Byte Addressing
Not supported
A31:A24
1xxx_xxxx: Reserved = 1
JEDEC Sector Map Parameter Table
Sector Map
A7:A2=Reserved=111111b
A1=Descriptor Type = Map=1b
A0=Last map = 1b
100H
A7:A0
FFH
101H
102H
103H
A15:A8
A23:A16
A31:A24
00H
04H
FFH
Configuration ID = 00h
Region Count = 5 Regions
Reserved = FFH
Region 0 supports 4KByte erase and 8KByte erase
A3:A0=0011b
104H
A7:A0
F3H
A7:A4=Reserved=1111b
2019 Microchip Technology Inc.
DS20006152A-page 61
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (10 OF 16)
Bit Address
Data
Comments
Region 0 Size
4 * 8 KBytes = 32 KBytes
Count=32 KBytes/256 Bytes= 128
Value = count -1 =127
A31:A8 = 00007Fh
105H
A15:A8
7FH
106H
107H
A23:A16
A31:A24
00H
00H
Region 1 supports 4 KByte erase and 32 KByte erase
A3:A0 = 0101b
108H
A7:A0
F5H
A7:A4=Reserved = 1111b
Region 1 size
1 * 32Kbytes = 32Kbytes
Count=32Kbytes/256 bytes= 128
Value = count -1 =127
A31:A8 = 00007Fh
109H
A15:A8
7FH
10AH
10BH
A23:A16
A31:A24
00H
00H
Region 2 supports 4 KByte erase and 64 KByte erase
A3:A0 = 1001b
10CH
A7:A0
F9H
A7:A4=Reserved = 1111b
Region 2 size
62 * 64 KBytes = 3968 KBytes
Count=3968 KBytes/256 Bytes= 15872
Value = count -1 =15871
A31:A8 = 003DFFh
10DH
A15:A8
FFH
10EH
10FH
A23:A16
A31:A24
3DH
00H
Region 3 supports 4 KByte erase and 32 KByte erase
A3:A0 = 0101b
110H
A7:A0
F5H
A7:A4=Reserved = 1111b
Region 3 size
1 * 32 KBytes = 32 KBytes
Count=32 KBytes/256 bytes= 128
Value = count -1 =127
A31:A8 = 00007Fh
111H
A15:A8
7FH
112H
113H
A23:A16
A31:A24
00H
00H
Region 4 supports 4 KByte erase and 8 KByte erase
A3:A0=0011b
114H
A7:A0
F3H
A7:A4=Reserved=1111b
Region 4 Size
4 * 8 KBytes = 32 KBytes
Count=32 KBytes/256 bytes= 128
Value = count -1 =127
A31:A8 = 00007Fh
115H
A15:A8
7FH
116H
117H
A23:A16
A31:A24
00H
00H
DS20006152A-page 62
2019 Microchip Technology Inc.
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (11 OF 16)
Bit Address
Data
Comments
SST26VF032BEUI (Vendor) Parameter Table
SST26VF032BEUI Identification
200H
201H
202H
A7:A0
A15:A8
A23:A16
BFH
Manufacturer ID
Memory Type
26H
42H
Device ID
SST26VF032BEUI=42H
203H
A31:A24
FFH
Reserved. Bits default to all 1’s.
SST26VF032BEUI Interface
Interfaces Supported
000: SPI only
001: Power up default is SPI; Quad can be enabled/disabled
010: Reserved
A2:A0
:
:
111: Reserved
Supports Enable Quad
0:
not supported
A3
1:
supported
204H
B9H
Supports Hold#/Reset# Function
000: Hold#
A6:A4
A7
001: Reset#
010: HOLD/Reset#
011: Hold# & I/O when in SQI(4-4-4), 1-4-4 or 1-1-4 Read
Supports Software Reset
0:
not supported
1:
supported
Supports Quad Reset
A8
0:
not supported
1:
supported
A10:A9
Reserved. Bits default to all 1’s
Byte-Program or Page-Program (256 Bytes)
011: Byte Program/Page Program in SPI and Quad Page Program once
Quad is enabled
A13:A11
205H
5FH
Program-Erase Suspend Supported
A14
A15
0:
1:
Not Supported
Program/Erase Suspend Supported
Deep Power-Down Mode Supported
0:
Not Supported
1:
Deep Power-Down Mode Supported
2019 Microchip Technology Inc.
DS20006152A-page 63
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (12 OF 16)
Bit Address
Data
Comments
OTP Capable (Security ID) Supported
A16
0:
not supported
1:
supported
Supports Block Group Protect
A17
A18
0:
1:
not supported
supported
Supports Independent Block Protect
0:
206H
FDH
not supported
1:
supported
Supports Independent non Volatile Lock (Block or Sector becomes
OTP)
A19
0:
not supported
1:
supported
A23:A20
A31:A24
A7:A0
Reserved. Bits default to all 1’s.
Reserved. Bits default to all 1’s.
207H
208H
209H
20AH
20BH
FFH
30H
F2H
60H
F3H
VDD Minimum Supply Voltage
2.3V (F270H)
A15:A8
A23:A16
A31:A24
VDD Maximum Supply Voltage
3.6V (F360H)
Typical time out for Byte-Program: 50 µs
20CH
A7:A0
32H
Typical time out for Byte Program is in µs. Represented by conversion of
the actual time from the decimal to hexadecimal number.
20DH
20EH
A15:A8
FFH
0AH
Reserved. Bits default to all 1’s.
A23:A16
Typical time out for page program: 1.0ms (xxH*(0.1ms)
Typical time out for Sector-Erase/Block-Erase: 18 ms
20FH
210H
211H
A31:A24
A7:A0
12H
23H
46H
Typical time out for Sector/Block-Erase is in ms. Represented by conversion
of the actual time from the decimal to hexadecimal number.
Typical time out for Chip-Erase: 35 ms
Typical time out for Chip-Erase is in ms. Represented by conversion of
the actual time from the decimal to hexadecimal number.
Max. time out for Byte-Program: 70 µs
Typical time out for Byte Program is in µs. Represented by conversion of
the actual time from the decimal to hexadecimal number.
A15:A8
212H
213H
A23:A16
A31:A24
FFH
0FH
Reserved. Bits default to all 1’s.
Max time out for Page-Program: 1.5ms.
Typical time out for Page Program in xxH * (0.1ms) ms
Max. time out for Sector Erase/Block Erase: 25ms.
Max time out for Sector/Block Erase in ms
214H
215H
216H
A7:A0
A15:A8
A23:A16
19H
32H
0FH
Max. time out for Chip Erase: 50ms.
Max time out for Chip Erase in ms.
Max. time out for Program Security ID: 1.5 ms
Max time out for Program Security ID in xxH*(0.1ms) ms
Max. time out for Write-Protection Enable Latency: 25 ms
217H
A31:A24
19H
Max time out for Write-Protection Enable Latency is in ms. Represented by con-
version of the actual time from the decimal to hexadecimal number.
Max. time Write-Suspend Latency: 25 µs
218H
219H
A23:A16
A31:A24
19H
FFH
Max time out for Write-Suspend Latency is in µs. Represented by conversion of
the actual time from the decimal to hexadecimal number.
Max. time to Deep Power-Down
0FFH = Reserved
DS20006152A-page 64
2019 Microchip Technology Inc.
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (13 OF 16)
Bit Address
Data
Comments
Max. time out from Deep Power-Down mode to Standby mode
0FFH = Reserved
21AH
A23:A16
FFH
21BH
21CH
21DH
21EH
21FH
A31:A24
A23:A16
A31:A24
A23:A16
A31:A24
FFH
FFH
FFH
FFH
FFH
Reserved. Bits default to all 1’s.
Reserved. Bits default to all 1’s.
Reserved. Bits default to all 1’s.
Reserved. Bits default to all 1’s.
Reserved. Bits default to all 1’s.
Supported Instructions
220H
221H
222H
223H
224H
225H
226H
227H
228H
229H
22AH
22BH
22CH
22DH
22EH
22FH
230H
231H
232H
233H
234H
235H
236H
237H
238H
239H
A7:A0
A15:A8
A23:A16
A31:A24
A7:A0
00H
66H
99H
38H
FFH
05H
01H
35H
06H
04H
02H
32H
B0H
30H
72H
42H
8DH
E8H
98H
88H
A5H
85H
C0H
9FH
AFH
5AH
No Operation
Reset Enable
Reset Memory
Enable Quad I/O
Reset Quad I/O
A15:A8
A23:A16
A31:A24
A7:A0
Read Status Register
Write Status Register
Read Configuration Register
Write Enable
A15:A8
A23:A16
A31:A24
A7:A0
Write Disable
Byte Program or Page Program
SPI Quad Page Program
Suspends Program/Erase
Resumes Program/Erase
Read Block-Protection register
Write Block Protection Register
Lock Down Block Protection Register
non-Volatile Write-Lock Down Register
Global Block Protection Unlock
Read Security ID
A15:A8
A23:A16
A31:A24
A7:A0
A15:A8
A23:A16
A31:A24
A7:A0
Program User Security ID Area
Lockout Security ID Programming
Set Burst Length
A15:A8
A23:A16
A31:A24
A7:A0
JEDEC-ID
Quad J-ID
A15:A8
SFDP
Deep Power-Down Mode
FFH = Reserved
23AH
23BH
A23:A16
A31:A24
FFH
FFH
Release Deep Power-Down Mode
FFH = Reserved
(1-4-4) SPI nB Burst with Wrap Number of Wait states (dummy
clocks) needed before valid output
A4:A0
00110b: 6 clocks of dummy cycle
23CH
23DH
06H
(1-4-4) SPI nB Burst with Wrap Number of Mode Bits
000b: Set Mode bits are not supported
A7:A5
A15:A8
ECH
(1-4-4) SPI nB Burst with Wrap Opcode
2019 Microchip Technology Inc.
DS20006152A-page 65
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (14 OF 16)
Bit Address
Data
06H
0CH
00H
03H
08H
Comments
(4-4-4) SQI nB Burst with Wrap Number of Wait states (dummy
clocks) needed before valid output
A20:A16
00110b: 6 clocks of dummy cycle
23EH
23FH
240H
241H
242H
(4-4-4) SQI nB Burst with Wrap Number of Mode Bits
000b: Set Mode bits are not supported
A23:A21
A31:A24
(4-4-4) SQI nB Burst with Wrap Opcode
(1-1-1) Read Memory Number of Wait states (dummy clocks) needed
before valid output
A4:A0
00000b: Wait states/dummy clocks are not supported.
(1-1-1) Read Memory Number of Mode Bits
000b: Mode bits are not supported,
A7:A5
A15:A8
(1-1-1) Read Memory Opcode
(1-1-1) Read Memory at Higher Speed Number of Wait states
(dummy clocks) needed before valid output
01000: 8 clocks (8 bits) of dummy cycle
A20:A16
(1-1-1) Read Memory at Higher Speed Number of Mode Bits
000b: Mode bits are not supported,
A23:A21
243H
244H
A31:A24
A7:A0
0BH
FFH
FFH
FFH
FFH
(1-1-1) Read Memory at Higher Speed Opcode
Reserved. Bits default to all 1’s.
245H
A15:A8
A23:A16
A31:A24
Reserved. Bits default to all 1’s.
246H
Reserved. Bits default to all 1’s.
247H
Reserved. Bits default to all 1’s.
Security ID
248H
A7:A0
FFH
Security ID size in bytes
Example: If the size is 2 KBytes, this field would be 07FFH
Security ID Range
249H
A15:A8
07H
Unique ID
(Pre-programmed at factory)
0000H - 0007H
User Programmable
0008H - 07FFH
24AH
24BH
A23:A16
A31:A24
FFH
FFH
Reserved. Bits default to all 1’s.
Reserved. Bits default to all 1’s.
Memory Organization/Block Protection Bit Mapping 1
Section 1: Sector Type Number:
Sector type in JEDEC Parameter Table (bottom, 8 KByte)
24CH
24DH
A7:A0
02H
02H
Section 1 Number of Sectors
A15:A8
Four of 8KB block (2n)
Section 1 Block Protection Bit Start
((2m) +1)+ c, c=FFH or -1, m= 6 for 32 Mb
Address bits are Read Lock bit locations and Even Address bits are Write
Lock bit locations. The most significant (left-most) bit indicates the sign of
the integer; it is sometimes called the sign bit. If the sign bit is zero, then
the number is greater than or equal to zero, or positive. If the sign bit is
one then the number is less than zero or negative.
24EH
A23:A16
FFH
DS20006152A-page 66
2019 Microchip Technology Inc.
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (15 OF 16)
Bit Address
Data
Comments
Section 1 (bottom) Block Protection Bit End
((2m) +1)+ c, c=06H or 6, m= 6 for 32 Mb
Address bits are Read Lock bit locations and Even Address bits are Write
Lock bit locations. The most significant (left-most) bit indicates the sign of
the integer; it is sometimes called the sign bit. If the sign bit is zero, then
the number is greater than or equal to zero, or positive. If the sign bit is
one then the number is less than zero or negative.
24FH
A31:A24
06H
Section 2: Sector Type Number
Sector type in JEDEC Parameter Table (32KB Block)
250H
251H
A7:A0
03H
00H
Section 2 Number of Sectors
A15:A8
One of 32KB Block (2n, n=0)
Section 2 Block Protection Bit Start
((2m) +1)+ c, c=FDH or -3, m= 6 for 32 Mb
The most significant (left-most) bit indicates the sign of the integer; it is
sometimes called the sign bit. If the sign bit is zero, then the number is
greater than or equal to zero, or positive. If the sign bit is one then the
number is less than zero or negative.
252H
253H
A23:A16
A31:A24
FDH
FDH
Section 2 Block Protection Bit End
((2m) +1)+ c, c=FDH or -3, m= 6 for 32 Mb
The most significant (left-most) bit indicates the sign of the integer; it is
sometimes called the sign bit. If the sign bit is zero, then the number is
greater than or equal to zero, or positive. If the sign bit is one then the
number is less than zero or negative.
Section 3: Sector Type Number
Sector type in JEDEC Parameter Table (64KB Block)
254H
255H
256H
257H
258H
259H
A7:A0
A15:A8
A23:A16
A31:A24
A7:A0
04H
06H
00H
FCH
03H
00H
Section 3 Number of Sectors
62 of 64KB Blocks (2m-2, m= 6 for 32 Mb)
Section 3 Block Protection Bit Start
Section 3 Block Protection Bit starts at 00H
Section 3 Block Protection Bit End
((2m) +1)+ c, c=FCH or -4, m= 6 for 32 Mb
Section 4: Sector Type Number
Sector type in JEDEC Parameter Table (32KB Block)
Section 4 Number of Sectors
One of 32KB Block (2^n, n=0)
A15:A8
Section 4 Block Protection Bit Start
((2m) +1)+ c, c=FEH or -2, m= 6 for 32 Mb
The most significant (left-most) bit indicates the sign of the integer; it is
sometimes called the sign bit. If the sign bit is zero, then the number is
greater than or equal to zero, or positive. If the sign bit is one then the
number is less than zero or negative.
25AH
25BH
A23:A16
A31:A24
FEH
FEH
Section 4 Block Protection Bit End
((2m) +1)+ c, c=FEH or -2, m= 6 for 32 Mb
The most significant (left-most) bit indicates the sign of the integer; it is
sometimes called the sign bit. If the sign bit is zero, then the number is
greater than or equal to zero, or positive. If the sign bit is one then the
number is less than zero or negative.
Section 5 Sector Type Number:
Sector type in JEDEC Parameter Table (top, 8 KByte)
25CH
25DH
A7:A0
02H
02H
Section 5 Number of Sectors
A15:A8
Four of 8KB block (2n)
2019 Microchip Technology Inc.
DS20006152A-page 67
SST26VF032BEUI
TABLE 11-1:
Address
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (16 OF 16)
Bit Address
Data
Comments
Section 5 Block Protection Bit Start
((2m) +1)+ c, c=07H or 7, m= 6 for 32 Mb
Address bits are Read Lock bit locations and Even Address bits are Write
Lock bit locations. The most significant (left-most) bit indicates the sign of
the integer; it is sometimes called the sign bit. If the sign bit is zero, then
the number is greater than or equal to zero, or positive. If the sign bit is
one then the number is less than zero or negative.
25EH
25FH
A23:A16
07H
Section 5 (Top) Block Protection Bit End
(((2m) +1)+ c, c=0EH or 14, m= 6 for 32 Mb,
Address bits are Read Lock bit locations and Even Address bits are Write
Lock bit locations. The most significant (left-most) bit indicates the sign of
the integer; it is sometimes called the sign bit. If the sign bit is zero, then
the number is greater than or equal to zero, or positive. If the sign bit is
one then the number is less than zero or negative.
A31:A24
0EH
30H
EUI-48 and EUI-64 Information
Indicates if EUI48 Mac address is being programmed in the next 6
address locations.
30H=48 bits is programmed
260H
A7:A0
FFH=Not being programmed
261H
262H
263H
264H
265H
266H
A15:A8
A23:A16
A31:A24
A7:A0
Octet 5
Octet 4
Octet 3
Octet 2
Octet 1
Octet 0
Mac address LSB-Octet 5
Octet 4
Octet 3
Octet 2
A15:A8
A23:A16
Octet 1
Mac address MSB-Octet 0
Indicates if EUI64 Mac address is being programmed in the next 8
address locations.
40H=64 bits is programmed
267H
A31:A24
40H
FFH=Not being programmed
268H
269H
26AH
26BH
26CH
26DH
26EH
26FH
A7:A0
A15:A8
A23:A16
A31:A24
A7:A0
Octet 7
Octet 6
Octet 5
Octet 4
Octet 3
Octet 2
Octet 1
Octet 0
Mac address LSB-Octet 7
Octet 6
Octet 5
Octet 4
Octet 3
A15:A8
A23:A16
A31:A24
Octet 2
Octet 1
Mac address MSB-Octet 0
1. See “Mapping Guidance Details” for more detailed mapping information
11.1 Mapping Guidance Details
The SFDP Memory Organization/Block Protection Bit
Mapping defines the memory organization including
uniform sector/block sizes and different contiguous
sectors/blocks sizes. In addition, this bit defines the
number of these uniform and different sectors/blocks
from address 000000H to the full range of Memory and
the associated Block Locking Register bits of each sec-
tor/block.
Each major Section is defined as follows:
DS20006152A-page 68
2019 Microchip Technology Inc.
SST26VF032BEUI
TABLE 11-2: SECTION DEFINITION
Major Section X Section X: Sector Type Number
Section X: Number of Sectors
Section X: Block-Protection Register Bit Start Location
Section X: Block-Protection Register Bit End Location
A Major Section consists of Sector Type Number, Num-
ber of Sector of this type, and the Block-Protection Bit
Start/End locations. This is tied directly to JEDEC Flash
Parameter Table Sector Size Type (in 7th DWORD and
8th DWORD section). Note that the contiguous 4KByte
Sectors across the full memory range are not included
on this section because they are not defined in the
JEDEC Flash Parameter Table Sector Size Type sec-
tion. Only the sectors/blocks that are dependently tied
with the Block-Protection Register bits are defined. A
major section is a partition of contiguous same-size
sectors/blocks. There will be several Major Sections as
you dissect across memory from 000000h to the full
range. Similar sector/block size that re-appear may be
defined as a different Major Section.
11.1.1
SECTOR TYPE NUMBER
Sector Type Number is the sector/block size type
defined in JEDEC Flash Parameter Table: SFDP
address locations 4CH, 4EH, 50H, and 52H. Sector
Type 1, which is represented by 01H, is located at
address 4CH. Sector Type 2, which is represented by
02H, is located at address location 4EH. Sector Type 3,
which is represented by 03H, is located at address
location 50H. Sector Type 4, represented by 04H, is
located at address location 52H. Contiguous Same
Sector Type # Size can re-emerge across the memory
range and this Sector Type # will indicate that it is a
separate/independent Major Section from the previous
contiguous sectors/blocks.
11.1.2
NUMBER OF SECTORS
Number of Sectors represents the number of contigu-
ous sectors/blocks with similar size. A formula calcu-
lates the contiguous sectors/blocks with similar size.
Given the sector/block size, type, and the number of
sectors, the address range of these sectors/blocks can
be determined along with specific Block Locking Reg-
ister bits that control the read/write protection of each
sectors/blocks.
2019 Microchip Technology Inc.
DS20006152A-page 69
SST26VF032BEUI
11.1.3
BLOCK-PROTECTION REGISTER
BIT START LOCATION (BPSL)
11.1.4
BLOCK PROTECTION REGISTER
BIT END LOCATION (BPEL)
Block-Protection Register Bit Start Location (BPSL)
designates the start bit location in the Block-Protection
Register where the first sector/block of this Major Sec-
tion begins. If the value of BPSL is 00H, this location is
the 0 bit location. If the value is other than 0, then this
value is a constant value adder (c) for a given formula,
(2m + 1) + (c). See “Memory Configuration”.
Block Protection Register Bit End Location designates
the end bit location in the Block Protection Register bit
where the last sector/block of this Major Section ends.
The value in this field is a constant value adder (c) for
a given formula or equation, (2m + 1) + (c). See “Mem-
ory Configuration”
11.1.5
MEMORY CONFIGURATION
From the initial location, there will be a bit location for
every increment by 1 until it reaches the Block Protec-
tion Register Bit End Location (BPEL). This number
range from BPSL to BPEL will correspond to, and be
equal to, the number of sectors/blocks on this Major
Section.
For the SST26VF032BEUI family, the memory configu-
ration is setup with different contiguous block sizes
from bottom to the top of the memory. For example,
starting from bottom of memory it has four 8KByte
blocks, one 32KByte block, x number of 64KByte
blocks depending on memory size, then one 32KByte
block, and four 8KByte block on the top of memory. See
Table 11-3.
TABLE 11-3: MEMORY BLOCK DIAGRAM REPRESENTATION
8 KByte Bottom Block
(from 000000H)
Section 1: Sector Type Number
Section 1: Number of Sectors
Section 1: Block-Protection Register Bit Start Location
Section 1: Block-Protection Register Bit End Location
Section 2: Sector Type Number
32 KByte
Section 2: Number of Sectors
Section 2: Block-Protection Register Bit Start Location
Section 2: Block-Protection Register Bit End Location
Section 3: Sector Type Number
64 KByte
Section 3: Number of Sectors
Section 3: Block-Protection Register Bit Start Location
Section 3: Block-Protection Register Bit End Location
Section 4: Sector Type Number
32 KByte
Section 4: Number of Sectors
Section 4: Block-Protection Register Bit Start Location
Section 4: Block-Protection Register Bit End Location
Section 5: Sector Type Number
8 KByte (Top Block)
Section 5: Number of Sectors
Section 5: Block-Protection Register Bit Start Location
Section 5: Block-Protection Register Bit End Location
Classifying these sector/block sizes via the Sector
Type derived from JEDEC Flash Parameter Table:
SFDP address locations 4EH, 50H, and 52H are as fol-
lows:
For the Number of Sectors associated with the contig-
uous sectors/blocks, a formula is used to determine the
number of sectors/blocks of these Sector Types:
• 8KByte Block (Type 2) is calculated by 2n. n is a byte.
• 32KByte Block (Type 3) is calculated by 2n. n is a byte.
• 8KByte Blocks are classified as Sector Type 2
(@4EH of SFDP)
• 64KByte Block (Type 4) is calculated by (2m - 2). m
can either be a 4, 5, 6, 7 or 8 depending on the mem-
ory size. This m field is going to be used for the
64KByte Block Section and will also be used for the
Block Protection Register Bit Location formula.
• 32KByte Blocks are classified as Sector Type 3
(@50H of SFDP)
• 64KByte Blocks are classified as Sector Type 4
(@52H of SFDP)
DS20006152A-page 70
2019 Microchip Technology Inc.
SST26VF032BEUI
m will have a constant value for specific densities and
is defined as:
going to be placed in the Block Protection Bit Start/End
field table are the constant value adder (c) in the for-
mula and are represented in two’s compliment except
when the value is 00H. If the value is 00H, this location
is the 0 bit location. If the value is other than 0, then this
is a constant value adder (c) that will be used in the for-
mula. The most significant (left most) bit indicates the
sign of the integer; it is sometimes called the sign bit.
If the sign bit is zero, then the number is greater than or
equal to zero, or positive. If the sign bit is one, then the
number is less than zero, or negative.
• 8Mbit = 4
• 16Mbit = 5
• 32Mbit = 6
• 64Mbit = 7
• 128Mbit = 8
Block Protect Register Start/End Bits are mapped in the
SFDP by using the formula (2m + 1) + (c). “m” is a con-
stant value that represents the different densities from
8Mbit to 128Mbit (used also in the formula calculating
number of 64Kbyte Blocks above). The values that are
See Table 11-4 for an example of this formula.
TABLE 11-4: BPSL/BPEL EQUATION WITH ACTUAL CONSTANT ADDER DERIVED FROM THE
FORMULA (2M + 1) + (C)
Block Size
8 Mbit to 128 Mbit
Comments
BPSL = (2m + 1) + 0FFH
0FFH = -1; 06H = 6
8 KByte (Type 2) Bottom
BPEL = (2m + 1) + 04H
Odd address bits are Read-Lock bit
locations and even address bits are
Write-Lock bit locations.
32 KByte (Type 3)
64 KByte (Type 4)
BPSL = BPEL= (2m + 1) + 0FDH
0FDH= -3
BPSL = 00H
00H is Block-Protection Register bit 0
location; 0FCH = -4
BPEL = (2m + 1) + 0FCH
32 KByte (Type 3)
BPSL = BPEL= (2m + 1) + 0FEH
0FEH=-2
8 KByte (Type 2) Top
BPSL = (2m + 1) + 07H
07H = 7; 0EH = 14
BPEL = (2m + 1) + 0EH
Odd address bits are Read-Lock bit
locations and even address bits are
Write-Lock bit locations.
2019 Microchip Technology Inc.
DS20006152A-page 71
SST26VF032BEUI
current OUIs, see “Organizationally Unique Identifiers
for Preprogrammed EUI-48 and EUI-64 Address
Devices” Technical Brief, (DS90003187).
11.2 Pre-Programmed EUI-48 and EUI-
64 Address
The SST26VF032BEUI is programmed at the factory
with a globally unique address stored in the SFDP ven-
dor parameter table and it is permanently write-
protected.
Note:
The OUI will change as addresses are
exhausted. Customers are not guaran-
teed to receive a specific OUI and should
design their application to accept new
OUIs as they are introduced.
11.2.1
The
EUI-48 ADDRESS
6
byte EUI-48 address value of the
SST26VF032BEUI is stored in the SFDP table at
address locations 0x261 through 0x266, as shown in
Figure 11-1. The first three bytes are the Organization-
ally Unique Identifier (OUI) assigned to Microchip by
the IEEE® Registration Authority. The remaining three
bytes are the Extension Identifier and are generated by
Microchip to ensure a globally unique, 48-bit value.
11.2.3
EUI-64 SUPPORT USING THE EUI-
48
The pre-programmed EUI-48 address of the
SST26VF032BEUI can easily be encapsulated at the
application level to form a globally unique, 64-bit
address for systems utilizing the EUI-64 standard. This
is done by adding 0xFFFE between the OUI and the
Extension Identifier, as shown below in Figure 11-1.
11.2.2
ORGANIZATIONALLY UNIQUE
IDENTIFIERS (OUIS)
Each OUI provides roughly 16M (224) addresses. Once
the address pool for an OUI is exhausted, Microchip
will acquire a new OUI from IEEE to use for program-
ming this model. For more information on past and
Note:
As an alternative, SST26VF032BEUI
features an EUI-64 address that can be
used in EUI-64 applications directly with-
out the need for encapsulation, thereby
simplifying
system
software.
See
Section 11.2.4, EUI-64 Address for
details.
FIGURE 11-1:
Octet
EUI-48™ ADDRESS PHYSICAL MEMORY MAP EXAMPLE
0
1
2
3
4
5
Description
24-bit Organizationally Unique
Identifier
24-bit Extension Identifier
Data
00h
04h
A3h
12h
34h
56h
SFDP Address
266h
261h
Corresponding EUI-48™ Address: 00-04-A3-12-34-56
Corresponding EUI-64™ Address after Encapsulation: 00-04-A3-FF-FE 12-34-56
DS20006152A-page 72
2019 Microchip Technology Inc.
SST26VF032BEUI
11.2.4
EUI-64 ADDRESS
The 8-byte EUI-64 address value of the
SST26VF032BEUI is stored in the SFDP table at
address locations 0x268 through 0x26F, as shown in
Figure 11-2. The first three bytes are the Organization-
ally Unique Identifier (OUI) assigned to Microchip by
the IEEE Registration Authority. The remaining five
bytes are the Extension Identifier and are generated by
Microchip to ensure a globally unique, 64-bit value.
Note:
In conformance with IEEE guidelines,
Microchip will not use the values 0xFFFE
and 0xFFFF for the first two bytes of the
EUI-64 Extension Identifier. These two
values and specially reserved to allow
applications to encapsulate EUI-48
addresses into EUI-64 addresses.
FIGURE 11-2:
Octet
EUI-64™ ADDRESS PHYSICAL MEMORY MAP EXAMPLE
0
1
2
3
4
5
6
7
Description
24-bit Organizationally
Unique Identifier
40-bit Extension Identifier
Data
00h
04h
A3h
12h
34h
56h
78h
90h
SFDP Address
26Fh
268h
Corresponding EUI-64™ Address: 00-04-A3-12-34-56-78-90
2019 Microchip Technology Inc.
DS20006152A-page 73
SST26VF032BEUI
NOTES:
DS20006152A-page 74
2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4107-6
== ISO/TS 16949 ==
2019 Microchip Technology Inc.
DS20006152A-page 75
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08/15/18
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