PIC32MM0032GPL020_技术文档

PIC32MM0064GPL036 FAMILY

32-Bit Flash Microcontroller with MIPS32^®microAptiv™ UC Core

with Low Power and Low Pin Count

Operating Conditions

Peripheral Features

•

2.0V to 3.6V, -40°C to +125°C, DC to 25 MHz

2.0V to 3.6V, -40°C to +85°C, DC to 25 MHz

•

Atomic Set, Clear and Invert Operation on Select

Peripheral Registers

•

High-Current Sink/Source 11 mA/16 mA on All Ports

Independent, Low-Power 32 kHz Timer Oscillator

Low-Power Modes

Two 4-Wire SPI modules (up to 25 MHz non-PPS, 

•

Low-Power modes:

20 MHz PPS):

-

Idle: CPU off, peripherals run from system clock

Sleep: CPU and peripherals off:

-

16-byte FIFO

2

I S mode

- Fast wake-up Sleep with retention

- Low-power Sleep with retention

•

Two UARTs:

-

RS-232, RS-485 and LIN/J2602 support

•

0.5 μA Sleep Current for Regulator Retention mode and

5 μA for Regulator Standby mode

®

IrDA with on-chip hardware encoder and decoder

•

External Edge and Level Change Interrupt on All Ports

CRC module

•

On-Chip 1.8V Voltage Regulator (VREG)

On-Chip Ultra Low-Power Retention Regulator

Hardware Real-Time Clock and Calendar (RTCC)

Up to 20 Peripheral Pin Select (PPS) Remappable Pins

Seven Total 16-Bit Timers:

High-Performance 32-Bit RISC CPU

•

microAptiv™ UC 32-Bit Core with 5-Stage Pipeline

microMIPS™ Instruction Set for 35% Smaller Code and

98% Performance compared to MIPS32 Instructions

-

Timer1: Dedicated 16-bit timer/counter

Two additional 16-bit timers in each MCCP and SCCP

module

•

DC-25 MHz Operating Frequency

®

3.17 CoreMark /MHz (79 CoreMark) Performance

•

Capture/Compare/PWM/Timer modules:

1.53 DMIPS/MHz (37 DMIPS) (Dhrystone 2.1) Performance

16-Bit/32-Bit Wide Instructions with 32-Bit Wide Data Path

-

Two 16-bit timers or one 32-bit timer in each module

PWM resolution down to 21 ns

Two Sets of 32 Core Register Files (32-bit) to Reduce

Interrupt Latency

One Multiple Output (MCCP) module:

- Flexible configuration as PWM, input capture, output

compare or timers

•

Single-Cycle 32x16 Multiply and Two-Cycle 32x32 Multiply

Hardware Divide Unit

- Six PWM outputs

64-Bit, Zero Wait State Flash with ECC to Maximize

Endurance/Retention

- Programmable dead time

- Auto-shutdown

-

Two Single Output (SCCP) modules:

Microcontroller Features

- Flexible configuration as PWM, input capture, output

compare or timers

•

Low Pin Count Packages, Ranging from 20 to 36 Pins,

including UQFN as Small as 4x4 mm

- Single PWM output

•

Up to 64K Flash Memory:

•

Reference Clock Output (REFO)

-

20,000 erase/write cycle endurance

20 years minimum data retention

Two Configurable Logic Cells (CLC) with Internal

Connections to Select Peripherals and PPS

Self-programmable under software control

Debug Features

•

Up to 8K Data Memory

®

Pin-Compatible with Most PIC24 MCU/dsPIC DSC Devices

•

Two Programming and Debugging Interfaces:

Multiple Interrupt Vectors with Individually

Programmable Priority

-

2-wire ICSP™ interface with non-intrusive access

and real-time data exchange with application

®

•

Fail-Safe Clock Monitor mode

-

4-wire MIPS standard Enhanced JTAG interface

Configurable Watchdog Timer with On-Chip, Low-Power

RC Oscillator

IEEE Standard 1149.2 Compatible (JTAG) Boundary Scan

•

Programmable Code Protection

Selectable Oscillator Options including:

-

High-precision, 8 MHz internal Fast RC (FRC) oscillator

High-speed crystal/resonator oscillator or external clock

2x/3x/4x/6x/12x/24x PLL, which can be clocked from the

FRC or primary oscillator

 2015-2018 Microchip Technology Inc.

DS60001324C-page 1

PIC32MM0064GPL036 FAMILY

•

Up to 14-Channel, Software-Selectable 10/12-Bit SAR

Analog-to-Digital Converter (ADC):

Analog Features

•

Two Analog Comparators with Input Multiplexing

Programmable High/Low-Voltage Detect (HLVD)

5-Bit DAC with Output Pin

-

12-bit, up to 222k samples/second conversion rate

10-bit, up to 250k samples/second conversion rate

Sleep mode operation

Band gap reference input feature

Windowed threshold compare feature

Auto-scan feature

•

Brown-out Reset (BOR)

TABLE 1:

PIC32MM0064GPL036 FAMILY DEVICES

Remappable

Peripherals

Device

PIC32MM0016GPL020

PIC32MM0032GPL020

PIC32MM0064GPL020

PIC32MM0016GPL028

20

28

16

32

64

16

4

8

4

16/16

22/19

7

8

2

1

2

11

12

2

Yes Yes Yes

SSOP/QFN

Yes Yes Yes SSOP/SOIC/

QFN/UQFN

PIC32MM0032GPL028

PIC32MM0064GPL028

28

32

64

8

22/19

7

8

2

1

2

12

2

Yes Yes Yes SSOP/ SOIC/

QFN/UQFN

Yes Yes Yes SPDIP/SSOP/

SOIC/QFN/

UQFN

PIC32MM0016GPL036 36/40 16

PIC32MM0032GPL036 36/40 32

PIC32MM0064GPL036 36/40 64

4

8

29/20

7

8

2

1

2

14

2

Yes Yes Yes VQFN/UQFN

Note 1: UART1 has assigned pins. UART2 is remappable.

2: SPI1 has assigned pins. SPI2 is remappable.

3: MCCP can be configured as a PWM with up to 6 outputs, input capture, output compare, 2 x 16-bit timers or 

1 x 32-bit timer.

4: SCCP can be configured as a PWM with 1 output, input capture, output compare, 2 x 16-bit timers or 1 x 32-bit timer.

DS60001324C-page 2

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

Pin Diagrams

20-Pin SSOP

MCLR

PGEC2/RP1/RA0

PGED2/RP2/RA1

PGED1/RP14/RB0

PGEC1/RP15/RB1

RP16/RB2

1

20

19

18

17

16

15

14

13

12

11

AVDD/VDD

AVSS/VSS

2

(1)

3

RP10/RB15

RP9/RB14

RP13/RB13

RP12/RB12

4

5

6

CLKI/RP3/RA2

7

VCAP

(1)

8

CLKO/RP4/RA3

RP8/RB9

RP7/RB8

PGED3/SOSCI/RP5/RB4

PGEC3/SOSCO/RP6/RA4

9

10

RP11/RB7

Legend: Shaded pins are up to 5V tolerant.

Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.

TABLE 2:

COMPLETE PIN FUNCTION DESCRIPTIONS FOR 20-PIN SSOP DEVICES

Function

1

2

3

MCLR

11 RP11/RB7

PGEC2/VREF+/AN0/RP1/OCM1E/INT3/RA0

PGED2/VREF-/AN1/RP2/OCM1F/RA1

12 TCK/RP7/U1CTS/SCK1/OCM1A/RB8⁽¹⁾

13 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/

INT2/RB9⁽¹⁾

4

5

6

7

8

9

PGED1/AN2/C1IND/C2INB/RP14/RB0

PGEC1/AN3/C1INC/C2INA/RP15/RB1

AN4/RP16/RB2

14 VCAP

15 TDO/AN7/LVDIN/RP12/RB12

16 TDI/AN8/RP13/RB13

OSC1/CLKI/AN5/C1INB/RP3/OCM1C/RA2

OSC2/CLKO/AN6/C1INA/RP4/OCM1D/RA3⁽¹⁾

PGED3/SOSCI/RP5/RB4

17 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14

18 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15⁽¹⁾

19 AVSS/VSS

10 PGEC3/SOSCO/SCLKI/RP6/PWRLCLK/RA4

Note 1: Pin has an increased current drive strength.

20 AVDD/VDD

 2015-2018 Microchip Technology Inc.

DS60001324C-page 3

PIC32MM0064GPL036 FAMILY

Pin Diagrams (Continued)

20-Pin QFN⁽²⁾

20 19 18 17 16

(1)

PGED1/RP14/RB0

PGEC1/RP15/RB1

RP16/RB2

1

2

3

4

5

15

14

13

RP10/RB15

RP9/RB14

RP13/RB13

PIC32MMXXXXGPL020

CLKI/RP3/RA2

12 RP12/RB12

11

(1)

V

CAP

CLKO/RP4/RA3

6

7

8

9 10

Legend: Shaded pins are up to 5V tolerant.

Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.

2: The back side thermal pad is not electrically connected.

TABLE 3:

COMPLETE PIN FUNCTION DESCRIPTIONS FOR 20-PIN QFN DEVICES

Function

1

2

3

4

5

6

7

8

9

PGED1/AN2/C1IND/C2INB/RP14/RB0

PGEC1/AN3/C1INC/C2INA/RP15/RB1

AN4/RP16/RB2

11

VCAP

12 TDO/AN7/LVDIN/RP12/RB12

13 TDI/AN8/RP13/RB13

OSC1/CLKI/AN5/C1INB/RP3/OCM1C/RA2

OSC2/CLKO/AN6/C1INA/RP4/OCM1D/RA3⁽¹⁾

PGED3/SOSCI/RP5/RB4

14 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14

15 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15⁽¹⁾

16 AVSS/VSS

PGEC3/SOSCO/SCLKI/RP6/PWRLCLK/RA4

17 AVDD/VDD

RP11/RB7

18 MCLR

TCK/RP7/U1CTS/SCK1/OCM1A/RB8⁽¹⁾

19 PGEC2/VREF+/AN0/RP1/OCM1E/INT3/RA0

20 PGED2/VREF-/AN1/RP2/OCM1F/RA1

10 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/

C2OUT/OCM1B/INT2/RB9⁽¹⁾

Note 1: Pin has an increased current drive strength.

DS60001324C-page 4

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

Pin Diagrams (Continued)

28-Pin SPDIP⁽²⁾/SSOP/SOIC

28

27

26

25

24

23

22

21

20

19

18

17

16

15

V

DD/AVDD

SS/AVSS

MCLR

1

RP1/RA0

RP2/RA1

2

(1)

3

RP10/RB15

RP9/RB14

RP13/RB13

RP12/RB12

PGED1/RP14/RB0

PGEC1/RP15/RB1

RP16/RB2

4

5

6

RB3

PGEC2/RP18/RB11

PGED2/RP17/RB10

7

VSS

8

CLKI/RP3/RA2

9

VCAP

(1)

10

11

12

13

14

RP19/RC9

CLKO/RP4/RA3

(1)

SOSCI/RP5/RB4

SOSCO/RP6/RA4

RP8/RB9

RP7/RB8

(1)

VDD

RP11/RB7

PGED3/RB5

PGEC3/RB6

Legend: Shaded pins are up to 5V tolerant.

Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.

2: Only PIC32MM0064GPL028 comes in a 28-pin SPDIP package.

TABLE 4:

COMPLETE PIN FUNCTION DESCRIPTIONS FOR 28-PIN SPDIP/SSOP/SOIC DEVICES

Function

1

2

3

4

5

6

7

8

9

MCLR

15 PGEC3/RB6

V

REF+/AN0/RP1/OCM1E/INT3/RA0

REF-/AN1/RP2/OCM1F/RA1

16 RP11/RB7

V

17 TCK/RP7/U1CTS/SCK1/OCM1A/RB8⁽¹⁾

PGED1/AN2/C1IND/C2INB/RP14/RB0

PGEC1/AN3/C1INC/C2INA/RP15/RB1

AN4/C1INB/RP16/RB2

18 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/INT2/RB9⁽¹⁾

19 RP19/RC9

20

VCAP

AN11/C1INA/RB3

21 PGED2/TDO/RP17/RB10

V

SS

22 PGEC2/TDI/RP18/RB11

OSC1/CLKI/AN5/RP3/OCM1C/RA2

23 AN7/LVDIN/RP12/RB12

10 OSC2/CLKO/AN6/RP4/OCM1D/RA3⁽¹⁾

24 AN8/RP13/RB13

11 SOSCI/RP5/RB4

25 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14

26 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15⁽¹⁾

12 SOSCO/SCLKI/RP6/PWRLCLK/RA4

13

V

DD

27

28

V

SS/AVSS

DD/AVDD

14 PGED3/RB5

Note 1: Pin has an increased current drive strength.

 2015-2018 Microchip Technology Inc.

DS60001324C-page 5

PIC32MM0064GPL036 FAMILY

Pin Diagrams (Continued)

28-Pin QFN/UQFN⁽²⁾

28 27 26 25 24 23 22

PGED1/RP14/RB0

PGEC1/RP15/RB1

RP16/RB2

1

2

3

4

5

6

7

RP13/RB13

21

20

RP12/RB12

19

PGEC2/RP18/RB11

PGED2/RP17/RB10

RB3

PIC32MMXXXXGPL028 18

V

SS

17

16

15

VCAP

CLKI/RP3/RA2

RP19/RC9

(1)

CLKO/RP4/RA3

RP8/RB9

8

9 10 11 12 13 14

Legend: Shaded pins are up to 5V tolerant.

Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.

2: The back side thermal pad is not electrically connected.

TABLE 5:

COMPLETE PIN FUNCTION DESCRIPTIONS FOR 28-PIN QFN/UQFN DEVICES

Function

1

PGED1/AN2/C1IND/C2INB/RP14/RB0

15 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/

INT2/RB9⁽¹⁾

2

3

PGEC1/AN3/C1INC/C2INA/RP15/RB1

AN4/C1INB/RP16/RB2

16 RP19/RC9

17

VCAP

4

AN11/C1INA/RB3

18 PGED2/TDO/RP17/RB10

5

V

SS

19 PGEC2/TDI/RP18/RB11

6

OSC1/CLKI/AN5/RP3/OCM1C/RA2

OSC2/CLKO/AN6/RP4/OCM1D/RA3⁽¹⁾

SOSCI/RP5/RB4

20 AN7/LVDIN/RP12/RB12

7

21 AN8/RP13/RB13

8

22 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14

23 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15⁽¹⁾

9

SOSCO/SCLKI/RP6/PWRLCLK/RA4

10

V

DD

24

25

V

SS/AVSS

DD/AVDD

11 PGED3/RB5

12 PGEC3/RB6

26 MCLR

13 RP11/RB7

27

28

V

REF+/AN0/RP1/OCM1E/INT3/RA0

REF-/AN1/RP2/OCM1F/RA1

14 TCK/RP7/U1CTS/SCK1/OCM1A/RB8⁽¹⁾

V

Note 1: Pin has an increased current drive strength.

DS60001324C-page 6

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

Pin Diagrams (Continued)

36-Pin VQFN⁽²⁾

RP16/RB2

RB3

1

2

3

4

5

6

7

8

9

27 RP13/RB13

26 RP12/RB12

RC0

25 PGEC2/RP18/RB11

24 PGED2/RP17/RB10

RC1

PIC32MMXXXXGPL036

RC2

23

22

V

DD

VSS

VCAP

CLKI/RP3/RA2

21 RP19/RC9

(1)

20 RC8

CLKO/RP4/RA3

(1)

SOSCI/RP5/RB4

19

RP8/RB9

Legend: Shaded pins are up to 5V tolerant.

Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.

2: The back side thermal pad is not electrically connected.

TABLE 6:

COMPLETE PIN FUNCTION DESCRIPTIONS FOR 36-PIN VQFN DEVICES

Function

1

2

3

4

5

6

7

8

9

AN4/C1INB/RP16/RB2

19 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/INT2/RB9⁽¹⁾

AN11/C1INA/RB3

AN12/RC0

AN13/RC1

RC2

20 RC8

21 RP19/RC9

22

23

V

CAP

DD

V

SS

24 PGED2/TDO/RP17/RB10

OSC1/CLKI/AN5/RP3/OCM1C/RA2

OSC2/CLKO/AN6/RP4/OCM1D/RA3⁽¹⁾

SOSCI/RP5/RB4

25 PGEC2/TDI/RP18/RB11

26 AN7/LVDIN/RP12/RB12

27 AN8/RP13/RB13

10 SOSCO/SCLKI/RP6/PWRLCLK/RA4

11 RP20/RA9

28 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14

29 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15⁽¹⁾

12

13

V

SS

DD

30

31

V

SS/AVSS

DD/AVDD

14 RC3

32 MCLR

15 PGED3/RB5

33

34

V

REF+/AN0/RP1/OCM1E/INT3/RA0

REF-/AN1/RP2/OCM1F/RA1

16 PGEC3/RB6

V

17 RP11/RB7

35 PGED1/AN2/C1IND/C2INB/RP14/RB0

36 PGEC1/AN3/C1INC/C2INA/RP15/RB1

18 TCK/RP7/U1CTS/SCK1/OCM1A/RB8⁽¹⁾

Note 1: Pin has an increased current drive strength.

 2015-2018 Microchip Technology Inc.

DS60001324C-page 7

PIC32MM0064GPL036 FAMILY

Pin Diagrams (Continued)

40-Pin UQFN⁽²⁾

RP16/RB2

RB3

1

2

3

4

5

6

7

8

9

RP13/RB13

30

29 RP12/RB12

RC0

28 RP18/RB11/PGEC2

27 RP17/RB10/PGED2

RC1

V

DD

RC2

26

25 N/C

24

PIC32MMXXXXGPL036

V

SS

OSCI/RP3/RA2

OSCO/RP4/RA3⁽¹⁾

SOSCI/RP5/RB4

VCAP

23 N/C

22 RP19/RC9

21 RC8

SOSCO/RP6/RA4 10

Legend: Shaded pins are up to 5V tolerant.

Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.

2: The back side thermal pad is not electrically connected.

TABLE 7:

COMPLETE PIN FUNCTION DESCRIPTIONS FOR 40-PIN UQFN DEVICES

Function

1

2

3

4

5

6

7

8

9

AN4/C1INB/RP16/RB2

AN11/C1INA/RB3

AN12/RC0

21 RC8

22 RP19/RC9

23 N/C

AN13/RC1

24

25 N/C

26

V

CAP

RC2

V

SS

V

DD

OSC1/CLKI/AN5/RP3/OCM1C/RA2

OSC2/CLKO/AN6/RP4/OCM1D/RA3⁽¹⁾

SOSCI/RP5/RB4

27 PGED2/TDO/RP17/RB10

28 PGEC2/TDI/RP18/RB11

29 AN7/LVDIN/RP12/RB12

30 AN8/RP13/RB13

10 SOSCO/SCLKI/RP6/PWRLCLK/RA4

11 RP20/RA9

31 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14

32 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15⁽¹⁾

12

13

V

SS

DD

33

34

V

SS/AVSS

DD/AVDD

14 RC3

15 PGED3/RB5

35 MCLR

16 PGEC3/RB6

36

37

V

REF+/AN0/RP1/OCM1E/INT3/RA0

REF-/AN1/RP2/OCM1F/RA1

17 RP11/RB7

V

18 TCK/RP7/U1CTS/SCK1/OCM1A/RB8⁽¹⁾

38 PGED1/AN2/C1IND/C2INB/RP14/RB0

39 PGEC1/AN3/C1INC/C2INA/RP15/RB1

40 N/C

19 N/C

20 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/

C2OUT/OCM1B/INT2/RB9⁽¹⁾

Note 1: Pin has an increased current drive strength.

DS60001324C-page 8

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 13

2.0 Guidelines for Getting Started with 32-Bit Microcontrollers........................................................................................................ 19

3.0 CPU............................................................................................................................................................................................ 23

4.0 Memory Organization................................................................................................................................................................. 33

5.0 Flash Program Memory.............................................................................................................................................................. 37

6.0 Resets ........................................................................................................................................................................................ 45

7.0 CPU Exceptions and Interrupt Controller ................................................................................................................................... 51

8.0 Oscillator Configuration.............................................................................................................................................................. 65

9.0 I/O Ports ..................................................................................................................................................................................... 79

10.0 Timer1 ........................................................................................................................................................................................ 89

11.0 Watchdog Timer (WDT) ............................................................................................................................................................. 93

12.0 Capture/Compare/PWM/Timer Modules (MCCP and SCCP) .................................................................................................... 97

2

13.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I S)....................................................................................................... 111

14.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 119

15.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 125

16.0 12-Bit Analog-to-Digital Converter with Threshold Detect........................................................................................................ 135

17.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator........................................................................................ 149

18.0 Configurable Logic Cell (CLC).................................................................................................................................................. 153

19.0 Comparator .............................................................................................................................................................................. 165

20.0 Control Digital-to-Analog Converter (CDAC)............................................................................................................................ 171

21.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 175

22.0 Power-Saving Features ........................................................................................................................................................... 179

23.0 Special Features ...................................................................................................................................................................... 183

24.0 Development Support............................................................................................................................................................... 201

25.0 Instruction Set .......................................................................................................................................................................... 205

26.0 Electrical Characteristics.......................................................................................................................................................... 207

27.0 Packaging Information.............................................................................................................................................................. 235

Appendix A: Revision History............................................................................................................................................................. 259

Index .................................................................................................................................................................................................. 261

The Microchip Web Site..................................................................................................................................................................... 265

Customer Change Notification Service .............................................................................................................................................. 265

Customer Support.............................................................................................................................................................................. 265

Product Identification System ............................................................................................................................................................ 267

 2015-2018 Microchip Technology Inc.

DS60001324C-page 9

PIC32MM0064GPL036 FAMILY

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

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devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

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To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Web site; http://www.microchip.com

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

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DS60001324C-page 10

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

Referenced Sources

This device data sheet is based on the following

individual sections of the “PIC32 Family Reference

Manual”. These documents should be considered as

the general reference for the operation of a particular

module or device feature.

Note:

To access the documents listed below,

browse the documentation section of the

Microchip web site (www.microchip.com).

• Section 1. “Introduction” (DS60001127)

• Section 5. “Flash Programming” (DS60001121)

• Section 7. “Resets” (DS60001118)

• Section 8. “Interrupts” (DS60001108)

• Section 10. “Power-Saving Modes” (DS60001130)

• Section 14. “Timers” (DS60001105)

• Section 19. “Comparator” (DS60001110)

• Section 21. “UART” (DS60001107)

• Section 23. “Serial Peripheral Interface (SPI)” (DS61106)

• Section 25. “12-Bit Analog-to-Digital Converter (ADC) with Threshold Detect” (DS60001359)

• Section 28. “RTCC with Timestamp” (DS60001362)

• Section 30. “Capture/Compare/PWM/Timer (MCCP and SCCP)” (DS60001381)

• Section 33. “Programming and Diagnostics” (DS61129)

• Section 36. “Configurable Logic Cell” (DS60001363)

• Section 45. “Control Digital-to-Analog Converter (CDAC)” (DS60001327)

®

• Section 50. “CPU for Devices with MIPS32 microAptiv™ and M-Class Cores” (DS60001192)

• Section 59. “Oscillators with DCO” (DS60001329)

• Section 60. “32-Bit Programmable Cyclic Redundancy Check (CRC)” (DS60001336)

• Section 62. “Dual Watchdog Timer” (DS60001365)

 2015-2018 Microchip Technology Inc.

DS60001324C-page 11

PIC32MM0064GPL036 FAMILY

NOTES:

DS60001324C-page 12

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

This data sheet contains device-specific information for

the PIC32MM0064GPL036 family devices.

1.0

DEVICE OVERVIEW

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

devices. It is not intended to be a compre-

hensive reference source. To complement

the information in this data sheet, refer to

the “PIC32 Family Reference Manual”,

which is available from the Microchip

web site (www.microchip.com/PIC32). The

information in this data sheet supersedes

the information in the FRM.

Figure 1-1 illustrates a general block diagram of the core

and peripheral modules in the PIC32MM0064GPL036

family of devices.

Table 1-1 lists the pinout I/O descriptions for the pins

shown in the device pin tables.

FIGURE 1-1:

PIC32MM0064GPL036 FAMILY BLOCK DIAGRAM

Power-up

Timer

AVDD, AVSS

DD,VSS

MCLR

Oscillator

Start-up Timer

Primary

Oscillator

OSC2/CLKO

OSC1/CLKI

V

Power-on

Reset

FRC/LPRC

Oscillators

SOSCO/SCLKI

SOSCI

Secondary

Oscillator

Watchdog

Timer

Dividers

PLL

Brown-out

Reset

V

CAP

Voltage

Regulator

SYSCLK

PBCLK (1:1 with SYSCLK)

I/O Change

Notification

Timing

Generation

Precision

Band Gap

Reference

Timer1

MCCP1

SCCP2,3

SPI1,2

Peripheral Bus Clocked by PBCLK

PORTA

JTAG

Boundary

Scan

Priority

Interrupt

Controller

ICD

32

EJTAG

MIPS32^®microAptiv™ UC

CPU Core

INT

PORTB

5-Bit DAC

CRC

IS

DS

32

Bus Matrix

32

12-Bit ADC

UART1,2

RTCC

PORTC

32

Line Buffer

Module

RAM

Peripheral Bridge

64

Comparators

HLVD

64-Bit Wide

Program Flash Memory

Flash

Controller

 2015-2018 Microchip Technology Inc.

DS60001324C-page 13

PIC32MM0064GPL036 FAMILY

TABLE 1-1:

PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION

Pin Number

Pin Buffer

Type Type

28-Pin

QFN/

UQFN SSOP/SOIC

28-Pin

SPDIP/

Pin Name

Description

20-Pin 20-Pin

QFN SSOP

36-Pin 40-Pin

VQFN UQFN

AN0

19

20

1

2

3

27

28

1

2

3

33

34

35

36

1

36

37

38

39

1

I

ANA Analog-to-Digital Converter input channels

AN1

ANA

AN2

4

I

AN3

2

5

2

5

I

AN4

3

6

3

6

I

AN5

4

7

6

9

7

I

AN6

5

8

7

10

23

24

25

26

7

8

I

AN7

12

13

14

15

—

17

16

5

15

16

17

18

—

20

19

8

20

21

22

23

4

26

27

28

29

2

29

30

31

32

2

I

AN8

I

AN9

I

AN10

AN11

I

AN12

AN13

AVDD

—

25

24

4

—

28

27

7

3

I

4

I

ANA

(1)

31

30

2

34

33

2

P

I

—

Analog modules power supply

(2)

AVSS

Analog modules ground

C1INA

C1INB

C1INC

C1IND

C1OUT

C2INA

C2INB

C2OUT

CLKI

ANA Comparator 1 Input A

ANA Comparator 1 Input B

ANA Comparator 1 Input C

ANA Comparator 1 Input D

DIG Comparator 1 output

ANA Comparator 2 Input A

ANA Comparator 2 Input B

DIG Comparator 2 output

4

7

3

6

1

I

2

5

2

5

36

35

28

36

35

19

7

39

38

31

39

38

20

7

I

1

4

1

4

I

14

2

17

5

22

2

25

5

O

I

1

4

1

4

I

10

4

13

7

15

6

18

9

O

I

ST

External Clock input (EC mode)

CLKO

CDAC1

FSYNC1

INT0

5

8

7

10

25

26

25

18

2

8

O

DIG System clock output

ANA Digital-to-Analog Converter output

14

15

14

10

19

12

18

9

17

18

17

13

2

22

23

22

15

27

20

26

14

15

6

28

29

28

19

33

26

32

18

19

7

31

32

31

20

36

29

35

18

20

7

I/O ST/DIG SPI1 frame signal input or output

I

ST

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

INT1

INT2

I

INT3

I

LVDIN

MCLR

OCM1A

OCM1B

OCM1C

OCM1D

OCM1E

OCM1F

OSC1

OSC2

15

1

23

1

I

ANA High/Low-Voltage Detect input

ST Master Clear (device Reset)

I

12

13

7

17

18

9

O

—

DIG MCCP1 Output A

DIG MCCP1 Output B

DIG MCCP1 Output C

DIG MCCP1 Output D

DIG MCCP1 Output E

DIG MCCP1 Output F

10

4

5

8

7

10

2

8

19

20

4

2

27

28

6

33

34

7

36

37

7

3

7

9

—

Primary Oscillator crystal

5

8

7

10

8

Primary Oscillator crystal

Legend:

Note 1:

2:

ST = Schmitt Trigger input buffer

DIG = Digital input/output

ANA = Analog level input/output

VDD and AVDD are internally connected.

SS and AVSS are internally connected.

V

DS60001324C-page 14

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

TABLE 1-1:

PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION (CONTINUED)

Pin Number

Pin Buffer

Type Type

28-Pin

QFN/

UQFN SSOP/SOIC

28-Pin

SPDIP/

Pin Name

Description

20-Pin 20-Pin

QFN SSOP

36-Pin 40-Pin

VQFN UQFN

PGEC1

PGEC2

PGEC3

PGED1

PGED2

PGED3

PWRLCLK

RA0

2

19

7

5

2

5

36

25

16

35

24

15

10

33

34

7

39

28

16

38

27

15

10

36

37

7

I

ST

ICSP™ Port 1 programming clock input

ICSP Port 2 programming clock input

ICSP Port 3 programming clock input

19

12

1

22

15

4

10

4

1

I/O ST/DIG ICSP Port 1 programming data

I/O ST/DIG ICSP Port 2 programming data

I/O ST/DIG ICSP Port 3 programming data

20

6

3

18

11

9

21

14

12

2

9

7

10

2

I

ST

Real-Time Clock 50/60 Hz clock input

19

20

4

27

28

6

I/O ST/DIG PORTA digital I/O

I/O ST/DIG PORTB digital I/O

I/O ST/DIG PORTC digital I/O

RA1

3

RA2

7

9

RA3

5

8

7

10

12

—

4

8

RA4

7

10

—

4

9

10

11

35

36

1

10

11

38

39

1

RA9

—

1

—

1

RB0

RB1

2

5

2

5

RB2

3

6

3

6

RB3

—

6

—

9

4

7

2

RB4

8

11

14

15

16

17

18

21

22

23

24

25

26

—

19

18

26

9

RB5

—

8

—

11

12

13

—

15

16

17

18

—

13

18

11

12

13

14

15

18

19

20

21

22

23

—

16

15

23

15

16

17

18

19

24

25

26

27

28

29

3

15

16

17

18

20

27

28

29

30

31

32

3

RB6

RB7

RB8

9

RB9

10

—

12

13

14

15

—

10

15

RB10

RB11

RB12

RB13

RB14

RB15

RC0

RC1

4

RC2

5

RC3

14

20

21

19

29

14

21

22

20

32

RC8

RC9

REFCLKI

REFCLKO

I

ST

DIG Reference clock output

ANA = Analog level input/output

Reference clock input

O

Legend:

Note 1:

2:

ST = Schmitt Trigger input buffer

DIG = Digital input/output

V

DD and AVDD are internally connected.

SS and AVSS are internally connected.

V

 2015-2018 Microchip Technology Inc.

DS60001324C-page 15

PIC32MM0064GPL036 FAMILY

TABLE 1-1:

PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION (CONTINUED)

Pin Number

Pin Buffer

Type Type

28-Pin

QFN/

UQFN SSOP/SOIC

28-Pin

SPDIP/

Pin Name

Description

20-Pin 20-Pin

QFN SSOP

36-Pin 40-Pin

VQFN UQFN

RP1

19

20

4

2

27

28

6

2

33

34

7

36

37

7

I/O ST/DIG Remappable peripherals (input or output)

I/O ST/DIG

RP2

3

RP3

7

9

I/O ST/DIG

RP4

5

8

7

10

11

12

17

18

25

26

16

23

24

4

8

I/O ST/DIG

RP5

6

9

8

9

I/O ST/DIG

RP6

7

10

12

13

17

18

11

15

16

4

9

10

18

19

28

29

17

26

27

35

36

1

10

18

20

31

32

17

29

30

38

39

1

I/O ST/DIG

RP7

9

14

15

22

23

13

20

21

1

I/O ST/DIG

RP8

10

14

15

8

I/O ST/DIG

RP9

I/O ST/DIG

RP10

RP11

RP12

RP13

RP14

RP15

RP16

RP17

RP18

RP19

RP20

RTCC

SCK1

SCLKI

SDI1

SDO1

SOSCI

SOSCO

SS1

I/O ST/DIG

12

13

1

I/O ST/DIG

2

5

2

5

I/O ST/DIG

3

6

3

6

I/O ST/DIG

—

14

9

—

17

12

10

17

13

9

18

19

16

—

22

14

9

21

22

19

—

25

17

12

25

18

11

12

26

18

17

22

21

18

17

18

26

25

24

25

21

11

28

18

10

28

19

9

27

28

22

11

31

18

10

31

20

9

I/O ST/DIG

O

DIG Real-Time Clock alarm/seconds output

I/O ST/DIG SPI1 clock (input or output)

7

I

ST

Secondary Oscillator external clock input

SPI1 data input

14

10

6

22

15

8

O

—

I

DIG SPI1 data output

—

Secondary Oscillator crystal

7

10

18

13

12

16

15

13

12

13

18

17

9

10

29

19

18

25

24

19

18

19

29

28

10

32

20

18

28

27

20

18

20

32

31

Secondary Oscillator crystal

SPI1 slave select input

Timer1 external clock input

Timer1 clock gate input

JTAG clock input

15

10

9

23

15

14

19

18

15

14

15

23

22

ST

T1CK

T1G

I

TCK

I

TDI

13

12

10

9

I

JTAG data input

TDO

O

I

DIG JTAG data output

ST JTAG mode select input

DIG UART1 IrDA 16x baud clock output

ST UART1 transmission control input

DIG UART1 reception control output

ST UART1 receive data input

TMS

®

U1BCLK

U1CTS

U1RTS

U1RX

U1TX

O

I

10

15

14

O

I

O

DIG UART1 transmit data output

ANA = Analog level input/output

Legend:

Note 1:

2:

ST = Schmitt Trigger input buffer

DIG = Digital input/output

V

DD and AVDD are internally connected.

SS and AVSS are internally connected.

V

DS60001324C-page 16

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

TABLE 1-1:

PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION (CONTINUED)

Pin Number

Pin Buffer

Type Type

28-Pin

QFN/

UQFN SSOP/SOIC

28-Pin

SPDIP/

Pin Name

Description

20-Pin 20-Pin

QFN SSOP

36-Pin 40-Pin

VQFN UQFN

V

CAP

DD

11

17

14

20

17

20

22

24

P

—

Core voltage regulator filter capacitor 

connection

(1)

V

10,25

13,28

13,23,31 13,26,

34

Digital modules power supply

VREF

VSS

-

20

19

16

3

2

28

27

3

2

34

33

37

36

I

ANA ADC negative reference

+

ANA ADC and DAC positive reference

(2)

19

5,24

8,27

6,12,30 6,12,

33

P

—

Digital modules ground

Legend:

Note 1:

2:

ST = Schmitt Trigger input buffer

DIG = Digital input/output

ANA = Analog level input/output

VDD and AVDD are internally connected.

SS and AVSS are internally connected.

V

 2015-2018 Microchip Technology Inc.

DS60001324C-page 17

PIC32MM0064GPL036 FAMILY

NOTES:

DS60001324C-page 18

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

2.2

Decoupling Capacitors

2.0

GUIDELINES FOR GETTING

STARTED WITH 32-BIT

MICROCONTROLLERS

The use of decoupling capacitors on power supply

pins, such as VDD, VSS, AVDD and AVSS, is required.

See Figure 2-1.

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

devices. It is not intended to be a compre-

hensive reference source. To complement

the information in this data sheet, refer to

the “PIC32 Family Reference Manual”,

which is available from the Microchip

web site (www.microchip.com/PIC32).

The information in this data sheet

supersedes the information in the FRM.

Consider the following criteria when using decoupling

capacitors:

• Value and type of capacitor: A value of 0.1 µF

(100 nF), 10-20V is recommended. The capacitor

should be a low Equivalent Series Resistance 

(low-ESR) capacitor and have resonance frequency

in the range of 20 MHz and higher. It is further

recommended that ceramic capacitors be used.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close to

the pins as possible. It is recommended that the

capacitors be placed on the same side of the board

as the device. If space is constricted, the capacitor

can be placed on another layer on the PCB using a

via; however, ensure that the trace length from the

pin to the capacitor is within one-quarter inch

(6 mm) in length.

2.1

Basic Connection Requirements

Getting started with the PIC32MM0064GPL036 family

of 32-bit Microcontrollers (MCUs) requires attention to

a minimal set of device pin connections before

proceeding with development. The following is a list of

pin names, which must always be connected:

• All VDD and VSS pins (see Section 2.2

“Decoupling Capacitors”)

• Handling high-frequency noise: If the board is

experiencing high-frequency noise, upward of tens

of MHz, add a second ceramic-type capacitor in par-

allel to the above described decoupling capacitor.

The value of the second capacitor can be in the

range of 0.01 µF to 0.001 µF. Place this second

capacitor next to the primary decoupling capacitor.

In high-speed circuit designs, consider implement-

ing a decade pair of capacitances, as close to the

power and ground pins as possible. For example,

0.1 µF in parallel with 0.001 µF.

• All AVDD and AVSS pins, even if the ADC module

is not used (see Section 2.2 “Decoupling

Capacitors”)

• MCLR pin (see Section 2.3 “Master Clear

(MCLR) Pin”)

• VCAP pin (see Section 2.4 “Capacitor on

Internal Voltage Regulator (VCAP)”)

• PGECx/PGEDx pins, used for In-Circuit Serial

Programming™ (ICSP™) and debugging 

purposes (see Section 2.6 “ICSP Pins”)

• Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first, and

then to the device pins. This ensures that the 

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a 

minimum, thereby reducing PCB track inductance.

• OSC1 and OSC2 pins, when external oscillator

source is used (see Section 2.8 “External

Oscillator Pins”)

The following pin(s) may be required as well:

VREF+/VREF- pins, used when external voltage

reference for the ADC module is implemented.

Note:

The AVDD and AVSS pins must be

connected, regardless of ADC use and

the ADC voltage reference source.

The back side thermal pad, if present, is

not electrically connected.

 2015-2018 Microchip Technology Inc.

DS60001324C-page 19

PIC32MM0064GPL036 FAMILY

Place the components illustrated in Figure 2-2 within

one-quarter inch (6 mm) from the MCLR pin.

FIGURE 2-1:

RECOMMENDED

MINIMUM CONNECTION

FIGURE 2-2:

EXAMPLE OF MCLR PIN

CONNECTIONS^(1,2,3)

0.1 µF

Ceramic

V

DD

10 µF

C

EFC

V

DD

R

R1

10k

MCLR

R1⁽¹⁾

MCLR

1 k

R

C

0.1 µF⁽²⁾

C

PIC32

1

5

4

2

3

6

V

SS/AVSS

PGECx⁽³⁾

PGEDx⁽³⁾

V

NC

DD

SS

DD/AVDD

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

Note 1: 470 R1  1 k will limit any current flowing into

MCLR from the external capacitor, C, in the event of

MCLR pin breakdown, due to Electrostatic Discharge

(ESD) or Electrical Overstress (EOS). Ensure that the

MCLR pin VIH and VIL specifications are met without

interfering with the debug/programmer tools.

2.2.1

BULK CAPACITORS

2: The capacitor can be sized to prevent unintentional

Resets from brief glitches or to extend the device

Reset period during POR.

The use of a bulk capacitor is recommended to improve

power supply stability. Typical values range from 4.7 µF

to 47 µF. This capacitor should be located as close to

the device as possible.

3: No pull-ups or bypass capacitors are allowed on active

debug/program PGECx/PGEDx pins.

2.3

Master Clear (MCLR) Pin

2.4

Capacitor on Internal Voltage

Regulator (VCAP

)

The MCLR pin provides for two specific device

functions:

A low-ESR (<1 Ohm) capacitor is required on the VCAP

pin, which is used to stabilize the internal voltage regu-

lator output. The VCAP pin must not be connected to

• Device Reset

• Device Programming and Debugging

V

DD and must have a CEFC capacitor, with at least a 6V

Pulling The MCLR pin low generates a device Reset.

Figure 2-2 illustrates a typical MCLR circuit. During

device programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR pin. Consequently, specific voltage

levels (VIH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R and C will need to be adjusted based on the

application and PCB requirements.

rating, connected to ground. The type can be ceramic

or tantalum. The recommended value of the CEFC

capacitor is 10 μF. On the printed circuit board, it should

be placed as close to the VCAP pin as possible. If the

board is experiencing high-frequency noise, upward of

tens of MHz, add a second ceramic-type capacitor in

parallel to this capacitor. The value of the second

capacitor can be in the range of 0.01 μF to 0.001 μF.

For example, as illustrated in Figure 2-2, it is

recommended that the capacitor, C, be isolated from

the MCLR pin during programming and debugging

operations.

DS60001324C-page 20

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

FIGURE 2-3:

FREQUENCY vs. ESR

PERFORMANCE FOR

SUGGESTED VCAP

2.5

Voltage Regulator Pin (VCAP)

A low-ESR (< 5Ω) capacitor is required on the VCAP pin

to stabilize the output voltage of the on-chip voltage

regulator. The VCAP pin must not be connected to VDD

and must use a capacitor of 10 µF connected to ground.

The type can be ceramic or tantalum. Suitable examples

of capacitors are shown in Table 2-1. Capacitors with

equivalent specifications can be used.

10

1

0.1

The placement of this capacitor should be close to VCAP

.

It is recommended that the trace length not exceed

0.25 inch (6 mm). Refer to Section 26.0 “Electrical

Characteristics” for additional information.

0.01

Designers may use Figure 2-3 to evaluate ESR

equivalence of candidate devices.

0.001

0.01

0.1

1

10

100

1000 10,000

Frequency (MHz)

Note: Typical data measurement at +25°C, 0V DC bias.

.

TABLE 2-1:

Make

SUITABLE CAPACITOR EQUIVALENTS

Nominal

Part #

Base Tolerance Rated Voltage Temp. Range

Capacitance

TDK

C3216X7R1C106K

C3216X5R1C106K

ECJ-3YX1C106K

10 µF

±10%

16V

-55 to +125°C

-55 to +85°C

-55 to +125°C

-55 to +85°C

Panasonic

Murata

ECJ-4YB1C106K

GRM319R61C106KE15D

 2015-2018 Microchip Technology Inc.

DS60001324C-page 21

PIC32MM0064GPL036 FAMILY

2.6

ICSP Pins

2.8

External Oscillator Pins

The PGECx and PGEDx pins are used for In-Circuit

Serial Programming™ (ICSP™) and debugging pur-

poses. It is recommended to keep the trace length

between the ICSP connector and the ICSP pins on

the device as short as possible. If the ICSP connec-

tor is expected to experience an ESD event, a series

resistor is recommended, with the value in the range

of a few tens of Ohms, not to exceed 100 Ohms.

The PIC32MM0064GPL036 family has options for two

external oscillators: a high-frequency primary oscillator

and a low-frequency secondary oscillator (refer to

Section 8.0 “Oscillator Configuration” for details).

The oscillator circuit should be placed on the same side

of the board as the device. Also, place the oscillator

circuit close to the respective oscillator pins, not

exceeding one-half inch (12 mm) distance between

them. The load capacitors should be placed next to the

oscillator itself, on the same side of the board. Use a

grounded copper pour around the oscillator circuit to

isolate them from surrounding circuits. The grounded

copper pour should be routed directly to the MCU

ground. Do not run any signal traces or power traces

inside the ground pour. Also, if using a two-sided board,

avoid any traces on the other side of the board where

the crystal is placed. A suggested layout is illustrated in

Figure 2-4.

Pull-up resistors, series diodes and capacitors on the

PGECx and PGEDx pins are not recommended as they

will interfere with the programmer/debugger communi-

cations to the device. If such discrete components are

an application requirement, they should be removed

from the circuit during programming and debugging.

Alternatively, refer to the AC/DC characteristics and

timing requirements information in the respective

device Flash programming specification for information

on capacitive loading limits and pin Input Voltage High

(VIH) and Input Voltage Low (VIL) requirements.

FIGURE 2-4:

SUGGESTED OSCILLATOR

CIRCUIT PLACEMENT

Ensure that the “Communication Channel Select”

(i.e., PGECx/PGEDx pins) programmed into the device

matches the physical connections for the ICSP to

®

MPLAB ICD 3 or MPLAB REAL ICE™ In-Circuit

Emulator.

For more information on MPLAB ICD 3 and REAL ICE

connection requirements, refer to the following

documents that are available from the Microchip web site.

Oscillator

Secondary

®

• “Using MPLAB ICD 3 In-Circuit Debugger”

Guard Trace

Guard Ring

(poster) (DS51765)

• “Development Tools Design Advisory” (DS51764)

• “MPLAB REAL ICE™ In-Circuit Emulator User’s

®

Guide” (DS51616)

• “Using MPLAB REAL ICE™ In-Circuit Emulator”

Main Oscillator

®

(poster) (DS51749)

2.9

Unused I/Os

2.7

JTAG

To minimize power consumption, unused I/O pins

should not be allowed to float as inputs. They can be

configured as outputs and driven to a logic low or logic

high state.

The TMS, TDO, TDI and TCK pins are used for testing

and debugging according to the Joint Test Action Group

(JTAG) standard. It is recommended to keep the trace

length between the JTAG connector, and the JTAG pins

on the device, as short as possible. If the JTAG connector

is expected to experience an ESD event, a series resistor

is recommended, with the value in the range of a few tens

of Ohms, not to exceed 100 Ohms.

Alternatively, inputs can be reserved by ensuring the pin

is always configured as an input and externally connect-

ing the pin to VSS or VDD. A current-limiting resistor may

be used to create this connection if there is any risk of

inadvertently configuring the pin as an output with the

logic output state opposite of the chosen power rail.

Pull-up resistors, series diodes and capacitors on the

TMS, TDO, TDI and TCK pins are not recommended as

they will interfere with the programmer/debugger com-

munications to the device. If such discrete components

are an application requirement, they should be removed

from the circuit during programming and debugging.

Alternatively, refer to the AC/DC characteristics and

timing requirements information in the respective device

Flash programming specification for information on

capacitive loading limits, and pin Input Voltage High (VIH

)

and Input Voltage Low (VIL) requirements.

DS60001324C-page 22

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

• Memory Management Unit with Simple Fixed

Mapping Translation (FMT) Mechanism

3.0

CPU

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

• Multiply/Divide Unit (MDU):

- Configurable using high-performance 

multiplier array.

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 50. “CPU for

- Maximum issue rate of one 32x16 multiply

per clock.

®

- Maximum issue rate of one 32x32 multiply

every other clock.

Devices with MIPS32 microAptiv™

and M-Class Cores” (DS60001192) in

the “PIC32 Family Reference Manual”,

which is available from the Microchip

web site (www.microchip.com/PIC32).

- Early-in iterative divide. Minimum 11 and

maximum 33 clock latency (dividend (rs) sign

extension dependent).

®

MIPS32 microAptiv™ UC microproces-

• Power Control:

sor core resources are available at:

www.imgtec.com. The information in this

data sheet supersedes the information in

the FRM.

- No minimum frequency: 0 MHz.

- Power-Down mode (triggered by WAIT

instruction).

• EJTAG Debug/Profiling:

®

The MIPS32 microAptiv™ UC microprocessor core is

the heart of the PIC32MM0064GPL036 family devices.

The CPU fetches instructions, decodes each

instruction, fetches source operands, executes each

instruction and writes the results of the instruction

execution to the proper destinations.

- CPU control with start, stop and single

stepping.

- Software breakpoints via the SDBBP

instruction.

- Optional simple hardware breakpoints on

virtual addresses, 4 instruction and 2 data

breakpoints.

3.1

Features

- PC and/or load/store address sampling for

profiling.

The PIC32MM0064GPL036 family processor core key

features include:

- Performance counters.

- Supports Fast Debug Channel (FDC).

• 5-Stage Pipeline

• 32-Bit Address and Data Paths

• MIPS32 Enhanced Architecture:

- Multiply-add and multiply-subtract instructions

- Targeted multiply instruction

- Zero and one detect instructions

- WAITinstruction

A block diagram of the PIC32MM0064GPL036 family

processor core is shown in Figure 3-1.

- Conditional move instructions

- Vectored interrupts

- Atomic interrupt enable/disable

- One GPR shadow set to minimize latency of

interrupts

- Bit field manipulation instructions

• microMIPS™ Instruction Set:

- microMIPS allows improving the code size

density over MIPS32, while maintaining

MIPS32 performance.

- microMIPS supports all MIPS32 instructions

(except for branch-likely instructions) with

new optimized 32-bit encoding. Frequent

MIPS32 instructions are available as 16-bit

instructions.

- Added seventeen new and thirty-five

®

MIPS32 corresponding commonly used

instructions in 16-bit opcode format.

- Stack Pointer implicit in instruction.

- MIPS32 assembly and ABI compatible.

 2015-2018 Microchip Technology Inc.

DS60001324C-page 23

PIC32MM0064GPL036 FAMILY

FIGURE 3-1:

PIC32MM0064GPL036 FAMILY MICROPROCESSOR CORE BLOCK DIAGRAM

MIPS32^®microAptiv™ UC Microprocessor Core

Decode

(microMIPS™)

MMU

System Bus

SYSCLK

GPR

(2 sets)

Execution Unit

Enhanced MDU

ALU/Shift

Atomic/LdSt

MCU ASE

Debug/Profiling

System

Coprocessor

System

Power

Management

Breakpoints

Interface

Fast Debug Channel

Performance Counters

Interrupt

Interface

2-Wire Debug

EJTAG

DS60001324C-page 24

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

3.2.2

MULTIPLY/DIVIDE UNIT (MDU)

3.2

Architecture Overview

®

The microAptiv UC core includes a Multiply/Divide Unit

(MDU) that contains a separate pipeline for multiply

and divide operations. This pipeline operates in parallel

with the Integer Unit (IU) pipeline and does not stall

when the IU pipeline stalls. This allows the long-

running MDU operations to be partially masked by

system Stalls and/or other Integer Unit instructions.

The MIPS32 microAptiv™ UC microprocessor core in

the PIC32MM0064GPL036 family devices contains

several logic blocks, working together in parallel, pro-

viding an efficient high-performance computing engine.

The following blocks are included with the core:

• Execution Unit

• General Purpose Register (GPR)

• Multiply/Divide Unit (MDU)

• System Control Coprocessor (CP0)

• Memory Management Unit (MMU)

• Power Management

The high-performance MDU consists of a 32x16 booth

recoded multiplier, Result/Accumulation registers (HI

and LO), a divide state machine, and the necessary

multiplexers and control logic. The first number shown

(‘32’ of 32x16) represents the rs operand. The second

number (‘16’ of 32x16) represents the rt operand. The

microAptiv UC core only checks the value of the rt

operand to determine how many times the operation

must pass through the multiplier. The 16x16 and 32x16

operations pass through the multiplier once. A 32x32

operation passes through the multiplier twice.

• microMIPS Instructions Decoder

• Enhanced JTAG (EJTAG) Controller

3.2.1

EXECUTION UNIT

The processor core execution unit implements a load/

store architecture with single-cycle ALU operations

(logical, shift, add, subtract) and an autonomous Multiply/

Divide Unit (MDU). The core contains thirty-two 32-bit

General Purpose Registers (GPRs) used for integer

operations and address calculation. One additional

register file shadow set (containing thirty-two registers) is

added to minimize context switching overhead during

interrupt/exception processing. The register file consists

of two read ports and one write port, and is fully bypassed

to minimize operation latency in the pipeline.

The MDU supports execution of one 16x16 or 32x16

multiply operation every clock cycle; 32x32 multiply

operations can be issued every other clock cycle. Appro-

priate interlocks are implemented to stall the issuance of

back-to-back, 32x32 multiply operations. The multiply

operand size is automatically determined by logic built

into the MDU. Divide operations are implemented with a

simple 1-bit-per-clock iterative algorithm. An early-in

detection checks the sign extension of the dividend (rs)

operand. If rs is 8 bits wide, 23 iterations are skipped.

For a 16-bit wide rs, 15 iterations are skipped, and for a

24-bit wide rs, 7 iterations are skipped. Any attempt to

issue a subsequent MDU instruction while a divide is still

active causes an IU pipeline Stall until the divide

operation has completed.

The execution unit includes:

• 32-bit adder used for calculating the data address

• Address unit for calculating the next instruction address

• Logic for branch determination and branch target

address calculation

• Load aligner

Table 3-1 lists the repeat rate (peak issue rate of cycles

until the operation can be re-issued), and latency

(number of cycles until a result is available) for the

microAptiv UC core multiply and divide instructions.

The approximate latency and repeat rates are listed in

terms of pipeline clocks.

• Bypass multiplexers used to avoid Stalls when

executing instruction streams where data produc-

ing instructions are followed closely by consumers

for their results

• Leading zero/one detect unit for implementing the

CLZand CLOinstructions

• Arithmetic Logic Unit (ALU) for performing 

arithmetic and bitwise logical operations

• Shifter and store aligner

TABLE 3-1:

MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES

Opcode

Operand Size (mul rt) (div rs)

Latency

Repeat Rate

MULT/MULTU, MADD/MADDU,

MSUB/MSUBU

16 bits

32 bits

16 bits

32 bits

8 bits

1

2

1

2

MUL(GPR destination)

2

1

3

2

DIV/DIVU

12

19

26

33

11

18

25

32

16 bits

24 bits

32 bits

 2015-2018 Microchip Technology Inc.

DS60001324C-page 25

PIC32MM0064GPL036 FAMILY

®

The MIPS architecture defines that the result of a

multiply or divide operation be placed in the HI and LO

registers. Using the Move-From-HI (MFHI) and Move-

From-LO (MFLO) instructions, these values can be

transferred to the General Purpose Register file.

3.2.3

SYSTEM CONTROL 

COPROCESSOR (CP0)

In the MIPS architecture, CP0 is responsible for the

virtual-to-physical address translation, the exception

control system, the processor’s diagnostics capability,

the operating modes (Kernel, User and Debug) and

whether interrupts are enabled or disabled. These

configuration options and other system information is

available by accessing the CP0 registers listed in

Table 3-2.

In addition to the HI/LO targeted operations, the MIPS

architecture also defines a Multiply instruction, MUL,

which places the least significant results in the primary

register file instead of the HI/LO register pair. By avoid-

ing the explicit MFLOinstruction, required when using the

LO register, and by supporting multiple destination

registers, the throughput of multiply-intensive operations

is increased.

Two other instructions, Multiply-Add (MADD) and

Multiply-Subtract (MSUB), are used to perform the

multiply-accumulate and multiply-subtract operations.

The MADDinstruction multiplies two numbers and then

adds the product to the current contents of the HI and

LO registers. Similarly, the MSUBinstruction multiplies

two operands and then subtracts the product from the

HI and LO registers. The MADD and MSUB operations

are commonly used in DSP algorithms.

DS60001324C-page 26

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

TABLE 3-2:

COPROCESSOR 0 REGISTERS

Register

Number

Register

Name

Function

0-3

4

Reserved

UserLocal

Reserved in the microAptiv™ UC.

User information that can be written by privileged software and read via 

RDHWR, Register 29.

5-6

7

Reserved

HWREna

Reserved in the microAptiv UC.

Enables access via the RDHWRinstruction to selected hardware registers in 

Non-Privileged mode.

(1)

8

BadVAddr

Reports the address for the most recent address related exception.

Processor cycle count.

(1)

9

Count

10

11

12

Reserved

Reserved in the microAptiv UC.

(1)

Compare

Timer interrupt control.

Status/

IntCtl/

Processor status and control; interrupt control and shadow set control.

SRSCtl/

SRSMap1/

View_IPL/

SRSMAP2

(1)

13

Cause

/

Cause of last exception.

View_RIPL

(1)

14

15

EPC

Program Counter at last exception.

PRId/

Processor identification and revision; exception base address; Common Device 

EBase/

Memory Map Base register.

CDMMBase

16

CONFIG/

CONFIG1/

CONFIG2/

CONFIG3/

CONFIG7

Configuration registers.

7-22

23

Reserved

Reserved in the microAptiv UC.

Debug/

EJTAG Debug register.

Debug2/

TraceControl/

TraceControl2/

EJTAG Debug Register 2.

EJTAG Trace Control register.

EJTAG Trace Control Register 2.

UserTraceData1/ EJTAG User Trace Data 1 register.

(2)

TraceBPC

EJTAG Trace Breakpoint register.

(2)

24

25

DEPC

/

Program Counter at last debug exception.

UserTraceData2 EJTAG User Trace Data 2 register.

PerfCtl0/

PerfCnt0/

PerfCtl1/

PerfCnt1

Performance Counter 0 control.

Performance Counter 0.

Performance Counter 1 control.

Performance Counter 1.

26

27

ErrCtl

Software parity check enable.

CacheErr

Records information about SRAM parity errors.

Reserved in the PIC32 core.

28-29 Reserved

(1)

30

31

ErrorEPC

Program Counter at last error.

(2)

DeSAVE

Debug Handler Scratchpad register.

Note 1: Registers used in exception processing.

2: Registers used in debug.

 2015-2018 Microchip Technology Inc.

DS60001324C-page 27

PIC32MM0064GPL036 FAMILY

The EJTAG interface operates through the Test

Access Port (TAP), a serial communication port used

for transferring test data in and out of the microAptiv

UC core. In addition to the standard JTAG instructions,

special instructions defined in the EJTAG specification

specify which registers are selected and how they are

used.

3.3

Power Management

The processor core offers a number of power

management features, including low-power design,

active power management and Power-Down modes

of operation. The core is a static design that

supports slowing or halting the clocks, which reduces

system power consumption during Idle periods.

®

3.5

MIPS32 microAptiv™ UC Core

Configuration

The mechanism for invoking Power-Down mode is

implemented through execution of the WAIT

instruction. The majority of the power consumed by

the processor core is in the clock tree and clocking

registers. The PIC32MM family makes extensive use

of local gated clocks to reduce this dynamic power

consumption.

Register 3-1 through Register 3-4 show the default

configuration of the microAptiv UC core, which is

included on PIC32MM0064GPL036 family devices.

3.4

EJTAG Debug Support

The microAptiv UC core has an Enhanced JTAG

(EJTAG) interface for use in the software debug. In

addition to the standard mode of operation, the

microAptiv UC core provides a Debug mode that is

entered after a debug exception (derived from a hard-

ware breakpoint, single-step exception, etc.) is taken

and continues until a Debug Exception Return (DERET)

instruction is executed. During this time, the processor

executes the debug exception handler routine.

DS60001324C-page 28

 2015-2018 Microchip Technology Inc.

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REGISTER 3-1:

CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

r-1

—

R/W-0

R/W-1

K23<2:0>

R-1

R/W-0

R/W-1

KU<2:0>

r-0

R/W-0

r-0

31:24

23:16

15:8

7:0

—

r-0

R-0

UDI

R-0

MDU

R-0

r-0

—

r-0

—

R-1

DS

R-1

—

SB

—

R-0

R-1

R-0

BE

AT<1:0>

AR<2:0>

r-0

MT<2:1>

R-1

r-0

R/W-0

R/W-1

R/W-0

MT<0>

—

K0<2:0>

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31

Reserved: This bit is hardwired to ‘1’ to indicate the presence of the CONFIG1 register

bit 30-28 K23<2:0>: Cacheability of the kseg2 and kseg3 Segments bits

010= Cache is not implemented

bit 27-25 KU<2:0>: Cacheability of the kuseg and useg Segments bits

010= Cache is not implemented

bit 24-23 Reserved: Must be written as zeros; returns zeros on reads

bit 22

bit 21

bit 20

UDI: User-Defined bit

0= CorExtend user-defined instructions are not implemented

SB: SimpleBE bit

1= Only simple byte enables are allowed on the internal bus interface

MDU: Multiply/Divide Unit bit

0= Fast, high-performance MDU

bit 19-17 Reserved: Must be written as zeros; returns zeros on reads

bit 16

DS: Dual SRAM Interface bit

1= Dual instruction/data SRAM interface

BE: Endian Mode bit

bit 15

0= Little-endian

bit 14-13 AT<1:0>: Architecture Type bits

®

00= MIPS32

bit 12-10 AR<2:0>: Architecture Revision Level bits

001= MIPS32 Release 2

bit 9-7

MT<2:0>: MMU Type bits

011= Fixed mapping

bit 6-3

bit 2-0

Reserved: Must be written as zeros; returns zeros on reads

K0<2:0>: kseg0 Coherency Algorithm bits

010= Cache is not implemented

 2015-2018 Microchip Technology Inc.

DS60001324C-page 29

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REGISTER 3-2:

CONFIG1: CONFIGURATION REGISTER 1; CP0 REGISTER 16, SELECT 1

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

r-1

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R-1

R-0

R-1

R-0

FP

—

PC

WR

CA

EP

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31

Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the CONFIG2 register

bit 30-5 Unimplemented: Read as ‘0’

bit 4

bit 3

bit 2

bit 1

bit 0

PC: Performance Counter bit

1= The processor core contains performance counters

WR: Watch Register Presence bit

0= No Watch registers are present

CA: Code Compression Implemented bit

®

0= No MIPS16e are present

EP: EJTAG Present bit

1= Core implements EJTAG

FP: Floating-Point Unit bit

0= Floating-Point Unit is not implemented

DS60001324C-page 30

 2015-2018 Microchip Technology Inc.

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REGISTER 3-3:

CONFIG3: CONFIGURATION REGISTER 3; CP0 REGISTER 16, SELECT 3

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

r-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

R-0

R-1

R-0

MMAR<2:0>

U-0

R-0

R-1

MCU

U-0

—

R-1

—

IPLW<1:0>

ISAONEXC

R-0

R-1

ULRI

R-1

RXI

R-0

U-0

—

R-0

ITL

R-0

TL

ISA<1:0>

—

U-0

R-1

U-0

—

VEIC

VINT

SP

CDMM

—

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31

Reserved: This bit is hardwired as ‘0’

bit 30-23 Unimplemented: Read as ‘0’

bit 22-21 IPLW<1:0>: Width of the Status IPL and Cause RIPL bits

01= IPL and RIPL bits are 8 bits in width

bit 20-18 MMAR<2:0>: microMIPS™ Architecture Revision Level bits

000= Release 1

®

bit 17

bit 16

MCU: MIPS MCU ASE Implemented bit

1= MCU ASE is implemented

ISAONEXC: ISA on Exception bit

1= microMIPS is used on entrance to an exception vector

bit 15-14 ISA<1:0>: Instruction Set Availability bits

01= Only microMIPS is implemented

bit 13

ULRI: UserLocal Register Implemented bit

1= UserLocal Coprocessor 0 register is implemented

RXI: RIE and XIE Implemented in PageGrain bit

1= RIE and XIE bits are implemented

Unimplemented: Read as ‘0’

bit 12

bit 11-9

bit 8

ITL: Indicates that iFlowtrace™ Hardware is Present bit

0= The iFlowtrace hardware is not implemented in the core

Unimplemented: Read as ‘0’

bit 7

bit 6

VEIC: External Vector Interrupt Controller bit

1= Support for an external interrupt controller is implemented.

VINT: Vector Interrupt bit

bit 5

bit 4

bit 3

1= Vector interrupts are implemented

SP: Small Page bit

0= 4-Kbyte page size

CDMM: Common Device Memory Map bit

1= CDMM is implemented

bit 2-1

bit 0

Unimplemented: Read as ‘0’

TL: Trace Logic bit

0= Trace logic is not implemented

 2015-2018 Microchip Technology Inc.

DS60001324C-page 31

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REGISTER 3-4:

CONFIG5: CONFIGURATION REGISTER 5; CP0 REGISTER 16, SELECT 5

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R-1

NF

—

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-1 Unimplemented: Read as ‘0’

bit 0

NF: Nested Fault bit

1= Nested Fault feature is implemented

DS60001324C-page 32

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The Fixed Mapping Translation (FMT) unit translates

the memory segments into corresponding physical

address regions. Figure 4-1 through Figure 4-3 illus-

trate the fixed mapping scheme, implemented by the

PIC32MM0064GPL036 family core, between the virtual

and physical address space.

4.0

MEMORY ORGANIZATION

PIC32MM microcontrollers provide 4 Gbytes of unified

virtual memory address space. All memory regions,

including program, data memory, SFRs and Configura-

tion registers, reside in this address space at their

respective unique addresses. The data memory can be

made executable, allowing the CPU to execute code

from data memory.

The mapping of the memory segments depends on the

CPU error level, set by the ERL bit in the CPU STATUS

Register (SR). Error level is set (ERL = 1) by the CPU

on a Reset, Soft Reset or NMI. In this mode, the CPU

can access memory by the physical address. This

Key features include:

• 32-Bit Native Data Width

®

mode is provided for compatibility with other MIPS

• Separate Boot Flash Memory (BFM) for 

Protected Code

processor cores that use a TLB-based MMU. The C

start-up code clears the ERL bit to zero, so that when

application software starts up, it sees the proper virtual

to physical memory mapping.

• Robust Bus Exception Handling to Intercept 

Runaway Code

• Simple Memory Mapping with Fixed Mapping

Translation (FMT) Unit

4.1

Alternate Configuration Bits

Space

The PIC32MM0064GPL036 family devices implement

two address spaces: virtual and physical. All hardware

resources, such as program memory, data memory and

peripherals, are located at their respective physical

addresses. Virtual addresses are exclusively used by the

CPU to fetch and execute instructions. Physical

addresses are used by peripherals, such as Flash

controllers, that access memory independently of the

CPU.

Every Configuration Word has an associated Alternate

Word (designated by the letter A as the first letter in the

name of the word). During device start-up, Primary

Words are read, and if uncorrectable ECC errors are

found, the BCFGERR (RCON<27>) flag is set and

Alternate Words are used. If uncorrectable ECC errors

are found in Primary and Alternate Words, the

BCFGFAIL (RCON<26>) flag is set, and the default

configuration is used. The Primary Configuration bits

area is located at the address range, from 0x1FC01780

to 0x1FC017E8. The Alternate Configuration bits area

is located at the address range, from 0x1FC01700 to

0x1FC01768.

The virtual address space is divided into two segments

of 512 Mbytes each, labeled kseg0 and kseg1. The

Program Flash Memory (PFM) and Data RAM Memory

(DRM) are accessible from either kseg0 or kseg1, while

the Boot Flash Memory (BFM) and peripheral SFRs are

accessible only from kseg1.

 2015-2018 Microchip Technology Inc.

DS60001324C-page 33

PIC32MM0064GPL036 FAMILY

FIGURE 4-1:

MEMORY MAP FOR DEVICES WITH 16 Kbytes OF PROGRAM MEMORY⁽¹⁾

Virtual

Memory Map

0x00000000

0x7FFFFFFF

0x80000000

0x80000FFF

0x80001000

0x9CFFFFFF

0x9D000000

0x9D003FFF

0x9D004000

0x9F7FFFFF

Reserved

4 Kbytes RAM

Reserved

16 Kbytes Flash

Reserved

Physical

Memory Map

0x9F800000

0x9F80FFFF

0x9F810000

0x9FBFFFFF

0x9FC00000

0x9FC016FF

0x9FC01700

0x9FC017FF

0x9FC01800

0x9FFFFFFF

0xA0000000

0xA0000FFF

0xA0001000

0xBCFFFFFF

0xBD000000

0xBD003FFF

0xBD004000

0xBF7FFFFF

0xBF800000

0xBF80FFFF

0xBF810000

0xBFBFFFFF

0xBFC00000

0xBFC016FF

0xBFC01700

0xBFC017FF

0xBFC01800

0xFFFFFFFF

0x00000000

0x00000FFF

0x00001000

0x1CFFFFFF

0x1D000000

0x1D003FFF

0x1D004000

0x1F7FFFFF

0x1F800000

0x1F80FFFF

0x1F810000

0x1FBFFFFF

0x1FC00000

0x1FC016FF

0x1FC01700

0x1FC017FF

0x1FC01800

0xFFFFFFFF

SFRs⁽²⁾

4 Kbytes RAM

Reserved

Boot Flash⁽²⁾

Configuration Bits^(2,3)

Reserved

16 Kbytes Flash

Reserved

SFRs

4 Kbytes RAM

Reserved

Boot Flash

16 Kbytes Flash

Reserved

Configuration Bits⁽³⁾

Reserved

SFRs

Reserved

Boot Flash

Configuration Bits⁽³⁾

Reserved

Note 1: Memory areas are not shown to scale.

2: This region should be accessed from kseg1 space only.

3: Primary Configuration bits area is located at the address range, from 0x1FC01780 to 0x1FC017E8.

Alternate Configuration bits area is located at the address range, from 0x1FC01700 to 0x1FC01768.

Refer to Section 4.1 “Alternate Configuration Bits Space” for more information.

DS60001324C-page 34

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PIC32MM0064GPL036 FAMILY

FIGURE 4-2:

MEMORY MAP FOR DEVICES WITH 32 Kbytes OF PROGRAM MEMORY⁽¹⁾

Virtual

Memory Map

0x00000000

Reserved

8 Kbytes RAM

Reserved

0x7FFFFFFF

0x80000000

0x80001FFF

0x80002000

0x9CFFFFFF

0x9D000000

0x9D007FFF

0x9D008000

0x9F7FFFFF

32 Kbytes Flash

Reserved

Physical

Memory Map

0x9F800000

0x9F80FFFF

0x9F810000

0x9FBFFFFF

0x9FC00000

0x9FC016FF

0x9FC01700

0x9FC017FF

0x9FC01800

0x9FFFFFFF

0xA0000000

0xA0001FFF

0xA0002000

0xBCFFFFFF

0xBD000000

0xBD007FFF

0xBD008000

0xBF7FFFFF

0xBF800000

0xBF80FFFF

0xBF810000

0xBFBFFFFF

0xBFC00000

0xBFC016FF

0xBFC01700

0xBFC017FF

0xBFC01800

0xFFFFFFFF

0x00000000

0x00001FFF

0x00002000

0x1CFFFFFF

0x1D000000

0x1D007FFF

0x1D008000

0x1F7FFFFF

0x1F800000

0x1F80FFFF

0x1F810000

0x1FBFFFFF

0x1FC00000

0x1FC016FF

0x1FC01700

0x1FC017FF

0x1FC01800

0xFFFFFFFF

SFRs⁽²⁾

8 Kbytes RAM

Reserved

Boot Flash⁽²⁾

Configuration Bits^(2,3)

Reserved

32 Kbytes Flash

Reserved

SFRs

8 Kbytes RAM

Reserved

Boot Flash

32 Kbytes Flash

Reserved

Configuration Bits⁽³⁾

Reserved

SFRs

Reserved

Boot Flash

Configuration Bits⁽³⁾

Reserved

Note 1: Memory areas are not shown to scale.

2: This region should be accessed from kseg1 space only.

3: Primary Configuration bits area is located at the address range, from 0x1FC01780 to 0x1FC017E8.

Alternate Configuration bits area is located at the address range, from 0x1FC01700 to 0x1FC01768.

Refer to Section 4.1 “Alternate Configuration Bits Space” for more information.

 2015-2018 Microchip Technology Inc.

DS60001324C-page 35

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FIGURE 4-3:

MEMORY MAP FOR DEVICES WITH 64 Kbytes OF PROGRAM MEMORY⁽¹⁾

Virtual

Memory Map

0x00000000

0x7FFFFFFF

0x80000000

0x80001FFF

0x80002000

0x9CFFFFFF

0x9D000000

0x9D00FFFF

0x9D010000

0x9F7FFFFF

Reserved

8 Kbytes RAM

Reserved

64 Kbytes Flash

Reserved

Physical

Memory Map

0x9F800000

0x9F80FFFF

0x9F810000

0x9FBFFFFF

0x9FC00000

0x9FC016FF

0x9FC01700

0x9FC017FF

0x9FC01800

0x9FFFFFFF

0xA0000000

0xA0001FFF

0xA0002000

0xBCFFFFFF

0xBD000000

0xBD00FFFF

0xBD010000

0xBF7FFFFF

0xBF800000

0xBF80FFFF

0xBF810000

0xBFBFFFFF

0xBFC00000

0xBFC016FF

0xBFC01700

0xBFC017FF

0xBFC01800

0xFFFFFFFF

0x00000000

0x00001FFF

0x00002000

0x1CFFFFFF

0x1D000000

0x1D00FFFF

0x1D010000

0x1F7FFFFF

0x1F800000

0x1F80FFFF

0x1F810000

0x1FBFFFFF

0x1FC00000

0x1FC016FF

0x1FC01700

0x1FC017FF

0x1FC01800

0xFFFFFFFF

SFRs⁽²⁾

8 Kbytes RAM

Reserved

Boot Flash⁽²⁾

Configuration Bits^(2,3)

Reserved

64 Kbytes Flash

Reserved

SFRs

8 Kbytes RAM

Reserved

Boot Flash

64 Kbytes Flash

Reserved

Configuration Bits⁽³⁾

Reserved

SFRs

Reserved

Boot Flash

Configuration Bits⁽³⁾

Reserved

Note 1: Memory areas are not shown to scale.

2: This region should be accessed from kseg1 space only.

3: Primary Configuration bits area is located at the address range, from 0x1FC01780 to 0x1FC017E8.

Alternate Configuration bits area is located at the address range, from 0x1FC01700 to 0x1FC01768.

Refer to Section 4.1 “Alternate Configuration Bits Space” for more information.

DS60001324C-page 36

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PIC32MM0064GPL036 FAMILY

There are three methods by which the user can

program this memory:

5.0

FLASH PROGRAM MEMORY

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to Section 5. “Flash Programming”

(DS60001121) in the “PIC32 Family Refer-

ence Manual”, which is available from the

Microchip web site (www.microchip.com/

PIC32). The information in this data sheet

supersedes the information in the FRM.

• Run-Time Self-Programming (RTSP)

• EJTAG Programming

• In-Circuit Serial Programming™ (ICSP™)

RTSP is performed by software executing from either

Flash or RAM memory. Information about RTSP tech-

niques is described in Section 5. “Flash Program-

ming” in the “PIC32 Family Reference Manual”.

EJTAG programming is performed using the JTAG port

of the device. ICSP programming requires fewer con-

nections than for EJTAG programming. The EJTAG

and ICSP methods are described in the “PIC32 Flash

Programming Specification” (DS60001145), which is

available for download from the Microchip web site.

PIC32MM0064GPL036 family devices contain an

internal Flash program memory for executing user

code. The Program and Boot Flash Memory can be

write-protected. The erase page size is 512 32-bit

words. The program row size is 64 32-bit words. The

memory can be programmed by rows or by two 32-bit

words.

5.1

Flash Controller Registers Write

Protection

The NVMPWP and NVMBWP registers, and the WR bit

in the NVMCON register are protected (locked) from an

accidental write. A special unlock sequence is required

to modify the content of these registers or bits.

The devices implement an Error Correcting Code

(ECC). The memory control block contains a logic to

write and read ECC bits to and from the Flash memory.

The Flash is programmed at the same time as the cor-

responding ECC bits. The ECC provides improved

resistance to Flash errors. The ECC single-bit error will

be transparently corrected. The ECC double-bit error

results in a bus error exception.

To unlock, the following steps should be done:

1. Disable interrupts prior to the unlock sequence.

2. Execute the system unlock sequence by writ-

ing the key values of 0xAA996655 and

0x556699AA to the NVMKEY register in two

back-to-back Assembly or ‘C’ instructions.

3. Write the new value to the required bits.

4. Re-enable interrupts.

 2015-2018 Microchip Technology Inc.

DS60001324C-page 37

PIC32MM0064GPL036 FAMILY

REGISTER 5-1:

NVMCON: NVM PROGRAMMING CONTROL REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5

28/20/12/4

27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

—

R/W-0, HC

R/W-0

R-0, HS, HC

r-0

U-0

—

U-0

—

U-0

(1,4)

(1)

(1,2)

WR

WREN

U-0

WRERR

U-0

LVDERR

U-0

—

U-0

R/W-0

(3)

—

NVMOP<3:0>

Legend:

HS = Hardware Settable bit HC = Hardware Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared r = Reserved bit

bit 31-16 Unimplemented: Read as ‘0’

(1,4)

bit 15

WR: Write Control bit

This bit cannot be cleared and can be set only when WREN = 1, and the unlock sequence has been performed.

1= Initiates a Flash operation

0= Flash operation is complete or inactive

(1)

bit 14

bit 13

WREN: Write Enable bit

1= Enables writes to the WR bit and disables writes to the NVMOP<3:0> bits

0= Disables writes to the WR bit and enables writes to the NVMOP<3:0> bits

(1,2)

WRERR: Write Error bit

This bit can be cleared only by setting the NVMOP<3:0> bits = 0000and initiating a Flash operation.

1= Program or erase sequence did not complete successfully

0= Program or erase sequence completed normally

(1,2)

bit 12

LVDERR: Low-Voltage Detect Error bit

This bit can be cleared only by setting the NVMOP<3:0> bits = 0000and initiating a Flash operation.

1= Low voltage is detected (possible data corruption if WRERR is set)

0= Voltage level is acceptable for programming

bit 11

Reserved: Maintain as ‘0’

bit 10-4 Unimplemented: Read as ‘0’

Note 1: These bits are only reset by a Power-on Reset (POR) and are not affected by other Reset sources.

2: These bits are cleared by setting NVMOP<3:0> = 0000and initiating a Flash operation (i.e., WR).

3: NVMOP<3:0> bits are write-protected if the WREN bit is set.

4: Writes to the WR bit require an unlock sequence. Refer to Section 5.1 “Flash Controller Registers Write

Protection” for details.

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REGISTER 5-1:

NVMCON: NVM PROGRAMMING CONTROL REGISTER (CONTINUED)

(3)

bit 3-0 NVMOP<3:0>: NVM Operation bits

These bits are only writable when WREN = 0.

1111= Reserved

•

1000= Reserved

0111= Program Erase Operation: Erases all of Program Flash Memory (all pages must be unprotected in

the NVMPWP register, Boot Flash Memory is not erased)

0110= Reserved

0101= Reserved

0100= Page Erase Operation: Erases page selected by NVMADDR (erases Boot or Program Flash

Memory, page must be unprotected in the NVMBWP or NVMPWP register)

0011= Row Program Operation: Programs row selected by NVMADDR (programs Boot or Program Flash

Memory, page must be unprotected in the NVMBWP or NVMPWP register)

0010= Double-Word Program Operation: Programs two words to the address selected by NVMADDR

(programs Boot or Program Flash Memory, page must be unprotected in the NVMBWP or

NVMPWP register)

0001= Reserved

0000= No operation, clears WRERR and LVDERR bits

Note 1: These bits are only reset by a Power-on Reset (POR) and are not affected by other Reset sources.

2: These bits are cleared by setting NVMOP<3:0> = 0000and initiating a Flash operation (i.e., WR).

3: NVMOP<3:0> bits are write-protected if the WREN bit is set.

4: Writes to the WR bit require an unlock sequence. Refer to Section 5.1 “Flash Controller Registers Write

Protection” for details.

DS60001324C-page 40

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REGISTER 5-2:

NVMKEY: NVM PROGRAMMING UNLOCK REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

W-0

31:24

23:16

15:8

7:0

NVMKEY<31:24>

W-0

NVMKEY<23:16>

W-0

NVMKEY<15:8>

W-0

NVMKEY<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMKEY<31:0>: NVM Unlock Register bits

These bits are write-only and read as ‘0’ on any read.

REGISTER 5-3:

NVMADDR: NVM FLASH ADDRESS REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

R/W-0

31:24

23:16

15:8

7:0

NVMADDR<31:24>

R/W-0

NVMADDR<23:16>

R/W-0

NVMADDR<15:8>

R/W-0

NVMADDR<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-0 NVMADDR<31:0>: NVM Flash Address bits

NVMOP<3:0>

Selection

Flash Address Bits (NVMADDR<31:0>)

Page Erase

Address identifies the page to erase (NVMADDR<10:0> are ignored).

Address identifies the row to program (NVMADDR<7:0> are ignored).

Row Program

Double-Word Program Address identifies the double-word (64-bit) to program (NVMADDR<1:0> bits are ignored).

 2015-2018 Microchip Technology Inc.

DS60001324C-page 41

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REGISTER 5-4:

NVMDATAx: NVM FLASH DATA x REGISTER (x = 0-1)

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

R/W-0

31:24

23:16

15:8

7:0

NVMDATAx<31:24>

R/W-0

NVMDATAx<23:16>

R/W-0

NVMDATAx<15:8>

R/W-0

NVMDATAx<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMDATAx<31:0>: NVM Flash Data x bits

Double-Word Program: Writes NVMDATA1:NVMDATA0 to the target Flash address defined in NVMADDR.

NVMDATA0 contains the least significant instruction word.

REGISTER 5-5:

NVMSRCADDR: NVM SOURCE DATA ADDRESS REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

R/W-0

31:24

23:16

15:8

7:0

NVMSRCADDR<31:24>

R/W-0

NVMSRCADDR<23:16>

R/W-0

NVMSRCADDR<15:8>

R/W-0

NVMSRCADDR<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMSRCADDR<31:0>: NVM Source Data Address bits

The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits

(NVMCON<3:0>) are set to perform row programming.

DS60001324C-page 42

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REGISTER 5-6:

NVMPWP: NVM PROGRAM FLASH WRITE-PROTECT REGISTER⁽¹⁾

Bit

Range

31/23/15/7

30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

R/W-1

PWPULOCK

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

R/W-0

(2)

PWP<23:16>

R/W-0

(2)

R/W-0

PWP<15:8>

R/W-0

(2)

PWP<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31

PWPULOCK: Program Flash Memory Page Write-Protect Unlock bit

1= Register is not locked and can be modified

0= Register is locked and cannot be modified

This bit is only clearable and cannot be set except by any Reset.

bit 30-24 Unimplemented: Read as ‘0’

(2)

bit 23-0 PWP<23:0>: Flash Program Write-Protect (Page) Address bits

Physical memory below address, 0x1DXXXXXX, is write-protected, where ‘XXXXXX’ is specified by

PWP<23:0>. When the PWP<23:0> bits have a value of ‘0’, write protection is disabled for the entire

Program Flash Memory. If the specified address falls within the page, the entire page and all pages below

the current page will be protected.

Note 1: Writes to this register require an NVMKEY unlock sequence. Refer to Section 5.1 “Flash Controller

Registers Write Protection” for details.

2: These bits can be modified only when the unlock bit (PWPULOCK) is set.

 2015-2018 Microchip Technology Inc.

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REGISTER 5-7:

NVMBWP: NVM BOOT FLASH (PAGE) WRITE-PROTECT REGISTER⁽¹⁾

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

—

R/W-1

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

(2)

BWPULOCK

U-0

BWP2

U-0

BWP1

BWP0

U-0

—

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15

BWPULOCK: Boot Alias Write-Protect Unlock bit

1= BWPx bits are not locked and can be modified

0= BWPx bits are locked and cannot be modified

This bit is only clearable and cannot be set except by any Reset.

bit 14-11 Unimplemented: Read as ‘0’

(2)

bit 10

bit 9

BWP2: Boot Alias Page 2 Write-Protect bit

1= Write protection for physical address, 0x1FC01000 through 0x1FC017FF, is enabled

0= Write protection for physical address, 0x1FC01000 through 0x1FC017FF, is disabled

(2)

BWP1: Boot Alias Page 1 Write-Protect bit

1= Write protection for physical address, 0x1FC00800 through 0x1FC00FFF, is enabled

0= Write protection for physical address, 0x1FC00800 through 0x1FC00FFF, is disabled

(2)

bit 8

BWP0: Boot Alias Page 0 Write-Protect bit

1= Write protection for physical address, 0x1FC00000 through 0x1FC007FF, is enabled

0= Write protection for physical address, 0x1FC00000 through 0x1FC007FF, is disabled

bit 7-0

Unimplemented: Read as ‘0’

Note 1: Writes to this register require an NVMKEY unlock sequence. Refer to Section 5.1 “Flash Controller

Registers Write Protection” for details.

2: These bits can be modified only when the associated unlock bit (BWPULOCK) is set.

DS60001324C-page 44

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

6.0

RESETS

Note:

This data sheet summarizes the features of

the PIC32MM0064GPL036 family of

devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to Section 7. “Resets” (DS60001118)

in the “PIC32 Family Reference Manual”,

which is available from the Microchip

web site (www.microchip.com/PIC32).

The information in this data sheet

supersedes the information in the FRM.

device Reset sources are as follows:

• Power-on Reset (POR)

• Master Clear Reset Pin (MCLR)

• Software Reset (SWR)

• Watchdog Timer Reset (WDTR)

• Brown-out Reset (BOR)

• Configuration Mismatch Reset (CMR)

A simplified block diagram of the Reset module is

illustrated in Figure 6-1.

FIGURE 6-1:

SYSTEM RESET BLOCK DIAGRAM

MCLR

WDTR

Glitch Filter

Sleep or Idle

WDT

Time-out

NMI

Time-out

Voltage Regulator

Enabled

POR

Power-up

Timer

SYSRST

V

DD

V

DD Rise

Detect

BOR

Brown-out

Reset

Configuration

Mismatch

Reset

CMR

SWR

Software Reset

 2015-2018 Microchip Technology Inc.

DS60001324C-page 45

PIC32MM0064GPL036 FAMILY

REGISTER 6-1:

RCON: RESET CONTROL REGISTER⁽¹⁾

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5

28/20/12/4

27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0

R/W-1, HS

PORIO

U-0

R/W-1, HS

PORCORE

U-0

—

U-0

R/W-0, HS

U-0

—

U-0

—

31:24

23:16

15:8

7:0

—

BCFGERR BCFGFAIL

U-0

—

U-0

—

U-0

R/W-0, HS

CMR

R/W-1, HS

BOR

U-0

—

R/W-0, HS

U-0

R/W-0, HS

R/W-1, HS

(2)

EXTR

SWR

—

WDTO

SLEEP

IDLE

POR

Legend:

HS = Hardware Settable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 31

PORIO: VDD POR Flag bit

Set by hardware at detection of a VDD POR event.

1= A Power-on Reset has occurred due to VDD voltage

0= A Power-on Reset has not occurred due to VDD voltage

bit 30

PORCORE: Core Voltage POR Flag bit

Set by hardware at detection of a core POR event.

1= A Power-on Reset has occurred due to core voltage

0= A Power-on Reset has not occurred due to core voltage

bit 29-28 Unimplemented: Read as ‘0’

bit 27

BCFGERR: Primary Configuration Registers Error Flag bit

1= An error occurred during a read of the Primary Configuration registers

0= No error occurred during a read of the Primary Configuration registers

bit 26

BCFGFAIL: Primary/Secondary Configuration Registers Error Flag bit

1= An error occurred during a read of the Primary and Alternate Configuration registers

0= No error occurred during a read of the Primary and Alternate Configuration registers

bit 25-10 Unimplemented: Read as ‘0’

bit 9

CMR: Configuration Mismatch Reset Flag bit

1= A Configuration Mismatch Reset has occurred

0= A Configuration Mismatch Reset has not occurred

bit 8

bit 7

Unimplemented: Read as ‘0’

EXTR: External Reset (MCLR) Pin Flag bit

1= Master Clear (pin) Reset has occurred

0= Master Clear (pin) Reset has not occurred

bit 6

SWR: Software Reset Flag bit

1= Software Reset was executed

0= Software Reset was not executed

bit 5

bit 4

Unimplemented: Read as ‘0’

WDTO: Watchdog Timer Time-out Flag bit

1= WDT time-out has occurred

0= WDT time-out has not occurred

Note 1: User software must clear bits in this register to view the next detection.

2: The IDLE bit will also be set when the device wakes from Sleep mode.

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REGISTER 6-1:

RCON: RESET CONTROL REGISTER⁽¹⁾(CONTINUED)

SLEEP: Wake from Sleep Flag bit

1= Device was in Sleep mode

bit 3

bit 2

bit 1

bit 0

0= Device was not in Sleep mode

(2)

IDLE: Wake from Idle Flag bit

1= Device was in Idle mode

0= Device was not in Idle mode

BOR: Brown-out Reset Flag bit

1= Brown-out Reset has occurred

0= Brown-out Reset has not occurred

POR: Power-on Reset Flag bit

1= Power-on Reset has occurred

0= Power-on Reset has not occurred

Note 1: User software must clear bits in this register to view the next detection.

2: The IDLE bit will also be set when the device wakes from Sleep mode.

REGISTER 6-2:

RSWRST: SOFTWARE RESET REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

W-0, HC

(1,2)

—

SWRST

Legend:

HC = Hardware Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-1 Unimplemented: Read as ‘0’

(1,2)

bit 0

SWRST: Software Reset Trigger bit

1= Enables Software Reset event

0= No effect

Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to

Section 23.4 “System Registers Write Protection” for details.

2: Once this bit is set, any read of the RSWRST register will cause a Reset to occur.

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REGISTER 6-3:

RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER⁽¹⁾

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R/W-0/HS

WDTR

R/W-0/HS

WDTS

R/W-0

31:24

23:16

15:8

7:0

—

R/W-0/HS

SWNMI

R/W-0

U-0

R/W-0/HS

GNMI

R/W-0

U-0

R/W-0/HS

CF

—

R/W-0

NMICNT<15:8>

R/W-0

NMICNT<7:0>

Legend:

HS = Hardware Settable bits

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-25 Unimplemented: Read as ‘0’

bit 24

WDTR: Watchdog Timer Time-out in Run Mode Flag bit

1= A Run mode WDT time-out has occurred and caused an NMI

0= WDT time-out has not occurred

Setting this bit will cause a WDT NMI event and NMICNT<15:0> will begin counting.

bit 23

SWNMI: Software NMI Trigger bit

1= An NMI has been generated

0= An NMI was not generated

bit 22-20 Unimplemented: Read as ‘0’

bit 19

GNMI: Software General NMI Trigger bit

1= A general NMI has been generated

0= A general NMI was not generated

bit 18

bit 17

Unimplemented: Read as ‘0’

CF: Clock Fail Detect bit

1= FSCM has detected clock failure and caused an NMI

0= FSCM has not detected clock failure

Setting this bit will cause a CF NMI event, but will not cause a clock switch to the FRC.

bit 16

WDTS: Watchdog Timer Time-out in Sleep Mode Flag bit

1= WDT time-out has occurred during Sleep mode and caused a wake-up from Sleep

0= WDT time-out has not occurred during Sleep mode

Setting this bit will cause a WDT NMI.

bit 15-0 NMICNT<15:0>: NMI Reset Counter Value bits

These bits specify the reload value used by the NMI Reset counter.

FFFFh-0001h= Number of SYSCLK cycles before a device Reset occurs

0000h= No delay between NMI assertion and device Reset event

(2)

Note 1: Writes to this register require an unlock sequence. Refer to Section 23.4 “System Registers Write

Protection” for details.

2: If a Watchdog Timer NMI event (when not in Sleep mode) is cleared before this counter reaches ‘0’, no

device Reset is asserted. This NMI Reset counter is only applicable to the Watchdog Timer NMI event.

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REGISTER 6-4:

PWRCON: POWER CONTROL REGISTER⁽¹⁾

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R/W-0

(3)

(2)

—

SBOREN

RETEN

VREGS

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-3 Unimplemented: Read as ‘0’

(3)

bit 2

bit 1

bit 0

SBOREN: BOR During Sleep Control bit

1= BOR is turned on

0= BOR is turned off

(2)

RETEN: Output Level of the Regulator During Sleep Selection bit

1= Writing a ‘1’ to this bit will cause the main regulator to be put in a low-power state during Sleep mode

0= Writing a ‘0’ to this bit will have no effect

(2)

VREGS: Voltage Regulator Standby Enable bit

1= Voltage regulator will remain active during Sleep mode

0= Voltage regulator will go to Standby mode during Sleep mode

Note 1: Writes to this register require an unlock sequence. Refer to Section 23.4 “System Registers Write

Protection” for details.

2: Refer to Section 22.4 “On-Chip Voltage Regulator Low-Power Modes” for details.

3: This bit is enabled only when the BOREN<1:0> Configuration bits (FPOR<1:0>) are set to ‘01’.

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The PIC32MM0064GPL036 family device interrupt

module includes the following features:

7.0

CPU EXCEPTIONS AND

INTERRUPT CONTROLLER

• Single Vector or Multivector mode Operation

• Five External Interrupts with Edge Polarity Control

• Interrupt Proximity Timer

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to Section 8. “Interrupts”

(DS60001108) and Section 50. “CPU for

• Module Freeze in Debug mode

• Seven User-Selectable Priority Levels for each

Vector

• Four User-Selectable Subpriority Levels within

each Priority

®

Devices with MIPS32 microAptiv™ and

M-Class Cores” (DS60001192) in the

“PIC32 Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32). The informa-

tion in this data sheet supersedes the

information in the FRM

• One Shadow Register Set that can be used for

any Priority Level, Eliminating Software Context

Switching and Reducing Interrupt Latency

• Software can Generate any Interrupt

• User-Configurable Interrupt Vectors’ Offset and

Vector Table Location

PIC32MM0064GPL036 family devices generate inter-

rupt requests in response to interrupt events from

peripheral modules. The interrupt control module exists

externally to the CPU logic and prioritizes the interrupt

events before presenting them to the CPU.

Figure 7-1 shows the block diagram for the interrupt

controller and CPU exceptions.

The CPU handles interrupt events as part of the excep-

tion handling mechanism, which is described in

Section 7.1 “CPU Exceptions”.

FIGURE 7-1:

CPU EXCEPTIONS AND INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM

Vector Number and Offset

Priority Level

Interrupt Controller

CPU Core

(Exception Handling)

Shadow Set Number

SYSCLK

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REGISTER 7-1:

INTCON: INTERRUPT CONTROL REGISTER

Bit

Range

Bit

25/17/9/1

Bit

24/16/8/0

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

U-0

R/W-0

VS<6:0>

U-0

R/W-0

—

U-0

—

U-0

—

U-0

—

R/W-0

MVEC

R/W-0

TPC<2:0>

R/W-0

—

U-0

R/W-0

—

INT4EP

INT3EP

INT2EP

INT1EP

INT0EP

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-23 Unimplemented: Read as ‘0’

bit 22-16 VS<6:0>: Vector Spacing bits

Spacing Between Vectors:

0000000= 0 Bytes

0000001= 8 Bytes

0000010= 16 Bytes

0000100= 32 Bytes

0001000= 64 Bytes

0010000= 128 Bytes

0100000= 256 Bytes

1000000= 512 Bytes

All other values are reserved. The operation of this device is undefined if a reserved value is written to this

field. If MVEC = 0, this field is ignored.

bit 15-13 Unimplemented: Read as ‘0’

bit 12

MVEC: Multivector Configuration bit

1= Interrupt controller configured for Multivectored mode

0= Interrupt controller configured for Single Vectored mode

bit 11

Unimplemented: Read as ‘0’

bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits

111= Interrupts of Group Priority 7 or lower start the interrupt proximity timer

110= Interrupts of Group Priority 6 or lower start the interrupt proximity timer

101= Interrupts of Group Priority 5 or lower start the interrupt proximity timer

100= Interrupts of Group Priority 4 or lower start the interrupt proximity timer

011= Interrupts of Group Priority 3 or lower start the interrupt proximity timer

010= Interrupts of Group Priority 2 or lower start the interrupt proximity timer

001= Interrupts of Group Priority 1 start the interrupt proximity timer

000= Disables interrupt proximity timer

bit 7-5

bit 4

Unimplemented: Read as ‘0’

INT4EP: External Interrupt 4 Edge Polarity Control bit

1= Rising edge

0= Falling edge

bit 3

INT3EP: External Interrupt 3 Edge Polarity Control bit

1= Rising edge

0= Falling edge

DS60001324C-page 58

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REGISTER 7-1:

INTCON: INTERRUPT CONTROL REGISTER (CONTINUED)

bit 2

bit 1

bit 0

INT2EP: External Interrupt 2 Edge Polarity Control bit

1= Rising edge

0= Falling edge

INT1EP: External Interrupt 1 Edge Polarity Control bit

1= Rising edge

0= Falling edge

INT0EP: External Interrupt 0 Edge Polarity Control bit

1= Rising edge

0= Falling edge

REGISTER 7-2:

PRISS: PRIORITY SHADOW SELECT REGISTER

Bit

Range

Bit

25/17/9/1

Bit

24/16/8/0

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

R/W-0

31:24

23:16

15:8

7:0

(1)

PRI7SS<3:0>

PRI6SS<3:0>

R/W-0

(1)

PRI5SS<3:0>

PRI4SS<3:0>

R/W-0

(1)

PRI3SS<3:0>

PRI2SS<3:0>

R/W-0

U-0

R/W-0

(1)

PRI1SS<3:0>

—

SS0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

(1)

bit 31-28 PRI7SS<3:0>: Interrupt with Priority Level 7 Shadow Set bits

11111= Reserved

•

0010= Reserved

0001= Interrupt with a priority level of 7 uses Shadow Set 1

0000= Interrupt with a priority level of 7 uses Shadow Set 0

(1)

bit 27-24 PRI6SS<3:0>: Interrupt with Priority Level 6 Shadow Set bits

1111= Reserved

•

0010= Reserved

0001= Interrupt with a priority level of 6 uses Shadow Set 1

0000= Interrupt with a priority level of 6 uses Shadow Set 0

Note 1: These bits are ignored if the MVEC bit (INTCON<12>) = 0.

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REGISTER 7-2:

PRISS: PRIORITY SHADOW SELECT REGISTER (CONTINUED)

(1)

bit 23-20 PRI5SS<3:0>: Interrupt with Priority Level 5 Shadow Set bits

1111= Reserved

•

0010= Reserved

0001= Interrupt with a priority level of 5 uses Shadow Set 1

0000= Interrupt with a priority level of 5 uses Shadow Set 0

bit 19-16 PRI4SS<3:0>: Interrupt with Priority Level 4 Shadow Set bits

1111= Reserved

•

0010= Reserved

0001= Interrupt with a priority level of 4 uses Shadow Set 1

0000= Interrupt with a priority level of 4 uses Shadow Set 0

bit 15-12 PRI3SS<3:0>: Interrupt with Priority Level 3 Shadow Set bits

1111= Reserved

•

0010= Reserved

0001= Interrupt with a priority level of 3 uses Shadow Set 1

0000= Interrupt with a priority level of 3 uses Shadow Set 0

bit 11-8 PRI2SS<3:0>: Interrupt with Priority Level 2 Shadow Set bits

1111= Reserved

•

0010= Reserved

0001= Interrupt with a priority level of 2 uses Shadow Set 1

0000= Interrupt with a priority level of 2 uses Shadow Set 0

bit 7-4

PRI1SS<3:0>: Interrupt with Priority Level 1 Shadow Set bits

1111= Reserved

•

0010= Reserved

0001= Interrupt with a priority level of 1 uses Shadow Set 1

0000= Interrupt with a priority level of 1 uses Shadow Set 0

bit 3-1

bit 0

Unimplemented: Read as ‘0’

SS0: Single Vector Shadow Register Set bit

1= Single vector is presented with a shadow set

0= Single vector is not presented with a shadow set

Note 1: These bits are ignored if the MVEC bit (INTCON<12>) = 0.

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REGISTER 7-3:

INTSTAT: INTERRUPT STATUS REGISTER

Bit

Range 31/23/15/7 30/22/14/6

29/21/13/5

28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R-0, HS, HC

(1)

—

SRIPL<2:0>

R-0, HS, HC

SIRQ<7:0>

Legend:

HS = Hardware Settable bit

W = Writable bit

HC = Hardware Clearable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-11 Unimplemented: Read as ‘0’

(1)

bit 10-8 SRIPL<2:0>: Requested Priority Level for Single Vector Mode bits

111-000= The priority level of the latest interrupt presented to the CPU

bit 7-0

SIRQ<7:0>: Last Interrupt Request Serviced Status bits

11111111-00000000= The last interrupt request number serviced by the CPU

Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode.

REGISTER 7-4:

IPTMR: INTERRUPT PROXIMITY TIMER REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

R/W-0

31:24

23:16

15:8

7:0

IPTMR<31:24>

R/W-0

IPTMR<23:16>

R/W-0

IPTMR<15:8>

R/W-0

IPTMR<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 IPTMR<31:0>: Interrupt Proximity Timer Reload bits

Used by the interrupt proximity timer as a reload value when the interrupt proximity timer is triggered by an

interrupt event.

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REGISTER 7-5:

IFSx: INTERRUPT FLAG STATUS REGISTER x⁽¹⁾

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

R/W-0

31:24

23:16

15:8

7:0

IFS<31:24>

R/W-0

IFS<23:16>

R/W-0

IFS<15:8>

R/W-0

IFS<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 IFS<31:0>: Interrupt Flag Status bits

1= Interrupt request has occurred

0= No interrupt request has occurred

Note 1: This register represents a generic definition of the IFSx register. Refer to Table 7-3 for the exact bit

definitions.

REGISTER 7-6:

IECx: INTERRUPT ENABLE CONTROL REGISTER x⁽¹⁾

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

R/W-0

31:24

23:16

15:8

7:0

IEC<31:24>

R/W-0

IEC<23:16>

R/W-0

IEC<15:8>

R/W-0

IEC<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 IEC<31-0>: Interrupt Enable bits

1= Interrupt is enabled

0= Interrupt is disabled

Note 1: This register represents a generic definition of the IECx register. Refer to Table 7-3 for the exact bit

definitions.

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REGISTER 7-7:

IPCx: INTERRUPT PRIORITY CONTROL REGISTER x⁽¹⁾

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

R/W-0

31:24

23:16

15:8

7:0

IP3<2:0>

R/W-0

IS3<1:0>

U-0

R/W-0

—

IP2<2:0>

R/W-0

IS2<1:0>

U-0

—

U-0

—

U-0

—

R/W-0

IP1<2:0>

R/W-0

IS1<1:0>

IS0<1:0>

U-0

R/W-0

—

IP0<2:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as ‘0’

bit 28-26 IP3<2:0>: Interrupt Priority bits

111= Interrupt priority is 7

•

010= Interrupt priority is 2

001= Interrupt priority is 1

000= Interrupt is disabled

bit 25-24 IS3<1:0>: Interrupt Subpriority bits

11= Interrupt subpriority is 3

10= Interrupt subpriority is 2

01= Interrupt subpriority is 1

00= Interrupt subpriority is 0

bit 23-21 Unimplemented: Read as ‘0’

bit 20-18 IP2<2:0>: Interrupt Priority bits

111= Interrupt priority is 7

•

010= Interrupt priority is 2

001= Interrupt priority is 1

000= Interrupt is disabled

bit 17-16 IS2<1:0>: Interrupt Subpriority bits

11= Interrupt subpriority is 3

10= Interrupt subpriority is 2

01= Interrupt subpriority is 1

00= Interrupt subpriority is 0

bit 15-13 Unimplemented: Read as ‘0’

Note 1: This register represents a generic definition of the IPCx register. Refer to Table 7-3 for the exact bit

definitions.

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REGISTER 7-7:

IPCx: INTERRUPT PRIORITY CONTROL REGISTER x⁽¹⁾(CONTINUED)

bit 12-10 IP1<2:0>: Interrupt Priority bits

111= Interrupt priority is 7

•

010= Interrupt priority is 2

001= Interrupt priority is 1

000= Interrupt is disabled

bit 9-8

IS1<1:0>: Interrupt Subpriority bits

11= Interrupt subpriority is 3

10= Interrupt subpriority is 2

01= Interrupt subpriority is 1

00= Interrupt subpriority is 0

bit 7-5

bit 4-2

Unimplemented: Read as ‘0’

IP0<2:0>: Interrupt Priority bits

111= Interrupt priority is 7

•

010= Interrupt priority is 2

001= Interrupt priority is 1

000= Interrupt is disabled

bit 1-0

IS0<1:0>: Interrupt Subpriority bits

11= Interrupt subpriority is 3

10= Interrupt subpriority is 2

01= Interrupt subpriority is 1

00= Interrupt subpriority is 0

Note 1: This register represents a generic definition of the IPCx register. Refer to Table 7-3 for the exact bit

definitions.

DS60001324C-page 64

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8.1

Fail-Safe Clock Monitor (FSCM)

8.0

OSCILLATOR

CONFIGURATION

The PIC32MM0064GPL036 family oscillator system

includes a Fail-Safe Clock Monitor (FSCM). The FSCM

monitors the SYSCLK for continuous operation. If it

detects that the SYSCLK has failed, it switches the

SYSCLK over to the FRC oscillator and triggers a Non-

Maskable Interrupt (NMI). When the NMI is executed,

software can attempt to restart the main oscillator or

shut down the system.

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 59. “Oscillators

with DCO” (DS60001329) in the “PIC32

Family Reference Manual”, which is avail-

able from the Microchip web site

(www.microchip.com/PIC32). The infor-

mation in this data sheet supersedes the

information in the FRM.

In Sleep mode, both the SYSCLK and the FSCM halt,

which prevents FSCM detection.

8.2

Clock Switching Operation

With few limitations, applications are free to switch

between any of the four clock sources (POSC, SOSC,

FRC and LPRC) under software control and at any

time. To limit the possible side effects that could result

from this flexibility, PIC32 devices have a safeguard

lock built into the switching process.

The PIC32MM0064GPL036 family oscillator system

has the following modules and features:

• On-Chip PLL with User-Selectable Multiplier and

Output Divider to Boost Operating Frequency on

Select Internal and External Oscillator Sources

Note:

The Primary Oscillator mode has three

different submodes (XT, HS and EC), which

are determined by the POSCMOD<1:0>

Configuration bits. While an application

can switch to and from Primary Oscillator

mode in software, it cannot switch

between the different primary submodes

without reprogramming the device.

• Primary High-Frequency Crystal Oscillator

• Secondary Low-Frequency and Low-Power 

Crystal Oscillator

• On-Chip Fast RC (FRC) Oscillator with 

User-Selectable Output Divider

• Software-Controllable Switching between Various

Clock Sources

• Fail-Safe Clock Monitor (FSCM) that Detects

Clock Failure and Permits Safe Application

Recovery or Shutdown

8.2.1

ENABLING CLOCK SWITCHING

To enable clock switching, the FCKSM1 Configuration

bit in FOSC must be programmed to ‘0’. (Refer to

Section 23.1 “Configuration Bits” for further details.)

If the FCKSM1 Configuration bit is unprogrammed (‘1’),

the clock switching function and Fail-Safe Clock

Monitor function are disabled; this is the default setting.

• Flexible Reference Clock Output (REFO)

A block diagram of the oscillator system is provided in

Figure 8-1. A block diagram of the REFO clock is

provided in Figure 8-2.

The NOSC<2:0> control bits (OSCCON<10:8>) do not

control the clock selection when clock switching is

disabled.

However,

the

COSC<2:0>

bits

(OSCCON<14:12>) will reflect the clock source

selected by the FNOSC<2:0> Configuration bits.

The OSWEN control bit (OSCCON<0>) has no effect

when clock switching is disabled; it is held at ‘0’ at all

times.

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A recommended code sequence for a clock switch

includes the following:

8.2.2

OSCILLATOR SWITCHING

SEQUENCE

1. Disable interrupts during the OSCCON register

unlock and write sequence.

At a minimum, performing a clock switch requires this

basic sequence:

2. Execute the unlock sequence for OSCCON by

writing 0xAA996655 and 0x556699AA to the

SYSKEY register.

1. If desired, read the COSC<2:0> bits

(OSCCON<14:12>) to determine the current

oscillator source.

3. Write the new oscillator source to the

NOSC<2:0> bits.

2. Perform the unlock sequence to allow a write to

the OSCCON register.

4. Set the OSWEN bit.

3. Write the appropriate value to the NOSC<2:0>

bits (OSCCON<10:8>) for the new oscillator

source.

5. Relock the OSCCON register.

6. Continue to execute code that is not clock-sensitive

(optional).

4. Set the OSWEN bit to initiate the oscillator

switch.

The core sequence for unlocking the OSCCON register

and initiating a clock switch is shown in Example 8-1.

Once the basic sequence is completed, the system

clock hardware responds automatically as follows:

EXAMPLE 8-1:

BASIC CODE SEQUENCE

FOR CLOCK SWITCHING

1. The clock switching hardware compares the

COSCx bits with the new value of the NOSCx

bits. If they are the same, then the clock switch

is a redundant operation. In this case, the

OSWEN bit is cleared automatically and the

clock switch is aborted.

SYSKEY = 0x00000000;

SYSKEY = 0xAA996655;

SYSKEY = 0x556699AA;

// force lock

// unlock

OSCCONbits.NOSC = 3;

// select the new

2. If a valid clock switch has been initiated,

the SPLLRDY (CLKSTAT<7>) and CF

(OSCCON<3>) bits are cleared.

clock source

OSCCONSET = 1;

// set the OSWEN bit

// force lock

3. The new oscillator is turned on by the hardware

if it is not currently running. If a crystal oscillator

must be turned on, the hardware will wait until

the OST expires. If the new source is using the

PLL, then the hardware waits until a PLL lock is

detected (SPLLRDY = 1).

SYSKEY = 0x00000000;

while (OSCCONbits.OSWEN); // optional wait for

switch operation



4. The hardware waits for 10 clock cycles from the

new clock source and then performs the clock

switch.

5. The hardware clears the OSWEN bit to indicate a

successful clock transition. In addition, the

NOSC<2:0> bits values are transferred to the

COSC<2:0> bits.

6. The old clock source is turned off if it is not being

used by a peripheral, or enabled by device

configuration or a control register.

Note 1: The processor will continue to execute

code throughout the clock switching

sequence. Timing-sensitive code should

not be executed during this time.

2: Direct clock switches between any

Primary Oscillator mode with PLL and

FRCPLL mode are not permitted. This

applies to clock switches in either direc-

tion. In these instances, the application

must switch to FRC mode as a transi-

tional clock source between the two PLL

modes.

DS60001324C-page 66

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FIGURE 8-1:

PIC32MM0064GPL036 FAMILY OSCILLATOR DIAGRAM

Reference Clock

2 MHz ≤ FIN ≤ 24 MHz

REFO1CON REFO1TRIM

16 MHz ≤ FVCO ≤ 96 MHz

ROTRIM<8:0> (M)

OE

REFCLKI

SPLLVCO

POSC

FRC

LPRC

System PLL

M

512





2

 ^_^{N + ---------}



SOSC

(1)

IN

Fvco⁽¹⁾

REFCLKO

F

PLL x M

PLLODIV<2:0>

(N)

SYSCLK

RODIV<14:0> (N)

To MCCP, SCCP

and SPIx

PLLMULT<6:0>

(M)

(1)

PLL

PLLICLK

F



N

ROSEL<3:0>

SPLL

Primary

Oscillator (POSC)

POSC (HS, EC)

OSC1/

CLKI

POSCMOD<1:0>

OSC2

To ADC, WDT, UART

and Flash Controller

SYSCLK (FSYS

)

8 MHz

32 kHz

FRCDIV

N

FRC

Oscillator

Postscaler 

FRCDIV<2:0>

(N)

TUN<5:0>

LPRC

SOSC

PBCLK (FPB

)

LPRC

Oscillator

Secondary Oscillator (SOSC)

32.768 kHz

SOSCEN

SOSCO/

SCLKI

SOSCSEL

Clock Control Logic

Fail-Safe

Clock

Monitor

SOSCI

NOSC<2:0>

COSC<2:0>

FNOSC<2:0>

FCKSM<1:0>

OSWEN

To Timer1, WDT, RTCC

To Timer1, RTCC, MCCP/SCCP and CLC

Note 1: Refer to Table 26-18 in Section 26.0 “Electrical Characteristics” for frequency limitations.



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FIGURE 8-2:

REFERENCE OSCILLATOR CLOCK DIAGRAM

25 MHz Max

REFCLKO



N

SPI Module

OE

RODIV<14:0>

ROSEL<3:0>

ROTRIM<8:0>

SPI

Module

(Note 1)

SYSCLK

PBCLK

25 MHz Max

50 MHz Max



N

MCLKSEL

PLLMULT<6:0>

COSC<2:0>

PLLODIV<2:0>

PLLICLK

MCCP/SCCP

Module

FRC

CLKSEL<1:0>

UART

Module

CLKSEL<1:0>

Note 1: Support circuitry for crystal is not shown.

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REGISTER 8-1:

OSCCON: OSCILLATOR CONTROL REGISTER⁽¹⁾

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5

28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

31:24

23:16

15:8

7:0

—

FRCDIV<2:0>

U-0

—

U-0

—

U-0

R-y, HS, HC

COSC<2:0>

U-0

R-y, HS, HC

U-0

R/W-y

(3)

—

NOSC<2:0>

R/W-0

U-0

R/W-0

R/W-0, HS

U-0

R/W-y

R/W-y, HC

(4)

(2)

CLKLOCK

—

SLPEN

CF

—

SOSCEN

OSWEN

Legend:

HC = Hardware Clearable bit

R = Readable bit

HS = Hardware Settable bit y = Value set from Configuration bits on Reset

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 31-27 Unimplemented: Read as ‘0’

bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits

111= FRC divided by 256

110= FRC divided by 64

101= FRC divided by 32

100= FRC divided by 16

011= FRC divided by 8

010= FRC divided by 4

001= FRC divided by 2

000= FRC divided by 1 (default setting)

bit 23-15 Unimplemented: Read as ‘0’

(3)

bit 14-12 COSC<2:0>: Current Oscillator Selection bits

111and 110= Reserved (selects internal Fast RC (FRC) Oscillator divided by the FRCDIV<2:0> bits (FRCDIV))

101= Internal Low-Power RC (LPRC) Oscillator

100= Secondary Oscillator (SOSC)

011= Reserved

010= Primary Oscillator (POSC) (XT, HS or EC)

001= System PLL (SPLL)

000= Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)

bit 11

Unimplemented: Read as ‘0’

Note 1: Writes to this register require an unlock sequence. Refer to Section 23.4 “System Registers Write

Protection” for details.

2: The Reset value for this bit depends on the setting of the IESO (FOSCSEL<7>) Configuration bit. When

IESO = 1, the Reset value is ‘1’. When IESO = 0, the Reset value is ‘0’.

3: The Reset value for these bits matches the setting of the FNOSC<2:0> (FOSCSEL<2:0>) Configuration bits.

4: The Reset value for this bit matches the setting of the SOSCEN (FOSCSEL<6>) Configuration bit.

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REGISTER 8-1:

OSCCON: OSCILLATOR CONTROL REGISTER⁽¹⁾(CONTINUED)

(3)

bit 10-8 NOSC<2:0>: New Oscillator Selection bits

111and 110= Reserved (selects internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV))

101= Internal Low-Power RC (LPRC) Oscillator

100= Secondary Oscillator (SOSC)

011= Reserved

010= Primary Oscillator (POSC) (XT, HS or EC)

001= System PLL (SPLL)

000= Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)

On Reset, these bits are set to the value of the FNOSC<2:0> Configuration bits (FOSCSEL<2:0>).

bit 7

CLKLOCK: Clock Selection Lock Enable bit

1= Clock and PLL selections are locked

0= Clock and PLL selections are not locked and may be modified

bit 6-5

bit 4

Unimplemented: Read as ‘0’

SLPEN: Sleep Mode Enable bit

1= Device will enter Sleep mode when a WAITinstruction is executed

0= Device will enter Idle mode when a WAITinstruction is executed

bit 3

CF: Clock Fail Detect bit

1= FSCM has detected a clock failure

0= No clock failure has been detected

bit 2

bit 1

Unimplemented: Read as ‘0’

(4)

SOSCEN: Secondary Oscillator (SOSC) Enable bit

1= Enables Secondary Oscillator

0= Disables Secondary Oscillator

(2)

bit 0

OSWEN: Oscillator Switch Enable bit

1= Initiates an oscillator switch to a selection specified by the NOSC<2:0> bits

0= Oscillator switch is complete

Note 1: Writes to this register require an unlock sequence. Refer to Section 23.4 “System Registers Write

Protection” for details.

2: The Reset value for this bit depends on the setting of the IESO (FOSCSEL<7>) Configuration bit. When

IESO = 1, the Reset value is ‘1’. When IESO = 0, the Reset value is ‘0’.

3: The Reset value for these bits matches the setting of the FNOSC<2:0> (FOSCSEL<2:0>) Configuration bits.

4: The Reset value for this bit matches the setting of the SOSCEN (FOSCSEL<6>) Configuration bit.



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REGISTER 8-2:

SPLLCON: SYSTEM PLL CONTROL REGISTER⁽¹⁾

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R/W-0

PLLODIV<2:0>

R/W-0

31:24

23:16

15:8

7:0

—

U-0

R/W-0

R/W-1

—

PLLMULT<6:0>

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-y

U-0

PLLICLK

—

Legend:

y = Values set from Configuration bits on Reset

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-27 Unimplemented: Read as ‘0’

bit 26-24 PLLODIV<2:0>: System PLL Output Clock Divider bits

111= PLL divide-by-256

110= PLL divide-by-64

101= PLL divide-by-32

100= PLL divide-by-16

011= PLL divide-by-8

010= PLL divide-by-4

001= PLL divide-by-2

000= PLL divide-by-1 (default setting)

bit 23

Unimplemented: Read as ‘0’

bit 22-16 PLLMULT<6:0>: System PLL Multiplier bits

111111-0000111= Reserved

0000110= 24x

0000101= 12x

0000100= 8x

0000011= 6x

0000010= 4x

0000001= 3x (default setting)

0000000= 2x

bit 15-8 Unimplemented: Read as ‘0’

bit 7

PLLICLK: System PLL Input Clock Source bit

1= FRC is selected as the input to the system PLL (not divided)

0= POSC is selected as the input to the system PLL

The POR default value is specified by the PLLSRC Configuration bit in the FOSCSEL register. Refer to

Register 23-9 in Section 23.0 “Special Features” for more information.

bit 6-0

Unimplemented: Read as ‘0’

Note 1: Writes to this register require an unlock sequence. Refer to Section 23.4 “System Registers Write

Protection” for details. All bits in this register must be modified only if the PLL is not used.

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REGISTER 8-3:

REFO1CON: REFERENCE OSCILLATOR CONTROL REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5

28/20/12/4

27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

R/W-0

RODIV<14:8>

R/W-0

31:24

23:16

15:8

7:0

R/W-0

RODIV<7:0>

R/W-0

U-0

—

R/W-0

SIDL

U-0

R/W-0

U-0

—

R/W-0, HC

R-0, HS, HC

(1)

(4)

(2,4)

(1)

ON

OE

RSLP

DIVSWEN ACTIVE

U-0

R/W-0

(3)

—

ROSEL<3:0>

Legend:

HC = Hardware Clearable bit

W = Writable bit

HS = Hardware Settable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

‘1’ = Bit is set

bit 31

Unimplemented: Read as ‘0’

bit 30-16 RODIV<14:0> Reference Clock Divider bits

The value selects the reference clock divider bits (see Figure 8-1 for details). A value of ‘0’ selects no divider.

(1)

bit 15

ON: Reference Oscillator Output Enable bit

1= Reference oscillator module is enabled

0= Reference oscillator module is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

SIDL: Peripheral Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

(4)

bit 12

bit 11

OE: Reference Clock Output Enable bit

1= Reference clock is driven out on the REFCLKO pin

0= Reference clock is not driven out on the REFCLKO pin

(2,4)

RSLP: Reference Oscillator Module Run in Sleep bit

1= Reference oscillator module output continues to run in Sleep

0= Reference oscillator module output is disabled in Sleep

bit 10

bit 9

Unimplemented: Read as ‘0’

DIVSWEN: Divider Switch Enable bit

1= Divider switch is in progress

0= Divider switch is complete

(1)

bit 8

ACTIVE: Reference Clock Request Status bit

1= Reference clock request is active

0= Reference clock request is not active

bit 7-4

Unimplemented: Read as ‘0’

Note 1: Do not write to this register when the ON bit is not equal to the ACTIVE bit.

2: This bit is ignored when the ROSEL<3:0> bits = 0000.

3: The ROSEL<3:0> bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.

4: Operation with output enabled in Retention Sleep mode is not recommended.



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REGISTER 8-3:

REFO1CON: REFERENCE OSCILLATOR CONTROL REGISTER (CONTINUED)

(3)

bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits

1111= Reserved

•

1010= Reserved

1001= REFCLKI pin

1000= Reserved

0111= System PLL output (not divided)

0110= Reserved

0101= Secondary Oscillator (SOSC)

0100= Low-Power RC Oscillator (LPRC)

0011= Fast RC Oscillator (FRC)

0010= Primary Oscillator (POSC)

0001= Instruction/System Clock (SYSCLK)

0000= Instruction/System Clock (SYSCLK)

Note 1: Do not write to this register when the ON bit is not equal to the ACTIVE bit.

2: This bit is ignored when the ROSEL<3:0> bits = 0000.

3: The ROSEL<3:0> bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.

4: Operation with output enabled in Retention Sleep mode is not recommended.

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REGISTER 8-4:

REFO1TRIM: REFERENCE OSCILLATOR TRIM REGISTER^(1,2,3)

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

R/W-0

31:24

23:16

15:8

7:0

ROTRIM<8:1>

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

ROTRIM<0>

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits

111111111= 511/512 divisor added to the RODIVx value

111111110= 510/512 divisor added to the RODIVx value

•

100000000= 256/512 divisor added to the RODIVx value

•

000000010= 2/512 divisor added to the RODIVx value

000000001= 1/512 divisor added to the RODIVx value

000000000= 0 divisor added to the RODIVx value

bit 22-0 Unimplemented: Read as ‘0’

Note 1: While the ON bit (REFO1CON<15>) is ‘1’, writes to this register do not take effect until the DIVSWEN bit

is also set to ‘1’.

2: Do not write to this register when the ON bit (REFO1CON<15>) is not equal to the ACTIVE bit

(REFO1CON<8>).

3: Specified values in this register do not take effect if RODIV<14:0> (REFO1CON<30:16>) = 0.



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REGISTER 8-5:

CLKSTAT: CLOCK STATUS REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5

28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0, HS, HC

U-0

R-0, HS, HC

U-0

R-0, HS, HC

SPLLRDY

—

LPRCRDY

SOSCRDY

—

POSCRDY SPDIVRDY FRCRDY

Legend:

HS = Hardware Settable bit HC = Hardware Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7

SPLLRDY: PLL Lock bit

1= PLL is locked and ready

0= PLL is not locked

bit 6

bit 5

Unimplemented: Read as ‘0’

LPRCRDY: LPRC Oscillator Ready bit

1= LPRC oscillator is stable and ready

0= LPRC oscillator is not stable

bit 4

SOSCRDY: Secondary Oscillator (SOSC) Ready bit

1= SOSC is stable and ready

0= SOSC is not stable

bit 3

bit 2

Unimplemented: Read as ‘0’

POSCRDY: Primary Oscillator (POSC) Ready bit

1= POSC is stable and ready

0= POSC is not stable

bit 1

bit 0

SPDIVRDY: System PLL (with postscaler, SPLLDIV) Clock Ready Status bit

1= SPLLDIV is stable and ready

0= SPLLDIV is not stable

FRCRDY: Fast RC (FRC) Oscillator Ready bit

1= FRC oscillator is stable and ready

0= FRC oscillator is not stable

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REGISTER 8-6:

OSCTUN: FRC TUNING REGISTER⁽¹⁾

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R/W-0

(2)

—

TUN<5:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-6 Unimplemented: Read as ‘0’

(2)

bit 5-0

TUN<5:0>: FRC Oscillator Tuning bits

100000= Center frequency – 1.5%

100001

•

111111

000000= Center frequency; oscillator runs at 8 MHz

000001

•

011110

011111= Center frequency + 1.5%

Note 1: Writes to this register require an unlock sequence. Refer to Section 23.4 “System Registers Write

Protection” for details.

2: OSCTUN functionality has been provided to help customers compensate for temperature effects on the

FRC frequency over a wide range of temperatures. The tuning step-size is an approximation and is

neither characterized nor tested.



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NOTES:

DS60001324C-page 78

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Many of the device pins are shared among the periph-

erals and the Parallel I/O (PIO) ports. All I/O input ports

9.0

I/O PORTS

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 12. “I/O Ports”

(DS60001120) in the “PIC32 Family

Reference Manual”, which is available

feature Schmitt Trigger inputs for improved noise

immunity. Some pins in the devices are 5V tolerant

pins. Some of the key features of the I/O ports are:

• Individual Output Pin Open-Drain Enable/Disable

• Individual Input Pin Weak Pull-up and Pull-Down

• Monitor Selective Inputs and Generate Interrupt

when Change-in-Pin State is Detected

• Operation during Sleep and Idle modes

from

the

Microchip

web

site

• Fast Bit Manipulation using the CLR, SET and

INV registers

(www.microchip.com/PIC32). The infor-

mation in this data sheet supersedes the

information in the FRM.

Figure 9-1 illustrates a block diagram of a typical

multiplexed I/O port.

FIGURE 9-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Peripheral Module

Peripheral Input Data

Output Multiplexers

Peripheral Module Enable

Peripheral Output Enable

Peripheral Output Data

I/O

1

0

Output Enable

Output Data

1

0

PIO Module

Read TRISx

Data Bus

D

Q

I/O Pin

WR TRISx

CK

TRISx Latch

D

Q

WR LATx +

WR PORTx

CK

Data Latch

Read LATx

Input Data

Read PORTx



2015-2018 Microchip Technology Inc.

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PIC32MM0064GPL036 FAMILY

9.1

CLR, SET and INV Registers

9.5

I/O Port Write/Read Timing

Every I/O module register has a corresponding CLR

(Clear), SET (Set) and INV (Invert) register designed to

provide fast atomic bit manipulations. As the name of the

register implies, a value written to a SET, CLR or INV reg-

ister effectively performs the implied operation, but only

on the corresponding base register and only bits specified

as ‘1’ are modified. Bits specified as ‘0’ are not modified.

Three instructions cycles are required between a port

direction change or port write operation and a read

operation of the same port. Typically, this instruction

would be a NOP.

9.6

Input Change Notification (ICN)

The Input Change Notification function of the I/O ports

allows the PIC32MM devices to generate interrupt

requests to the processor in response to a Change-of-

State (COS) on selected input pins. This feature can

detect input Change-of-States even in Sleep mode,

when the clocks are disabled. Every I/O port pin can be

selected (enabled) for generating an interrupt request on

a Change-of-State. Five control registers are associated

with the Change Notification (CN) functionality of each

I/O port. To enable the Change Notification feature for

the port, the ON bit (CNCONx<15>) must be set.

Reading SET, CLR and INV registers returns undefined

values. To see the affects of a write operation to a SET,

CLR or INV register, the base register must be read.

9.2

Parallel I/O (PIO) Ports

All port pins have 14 registers directly associated with

their operation as digital I/Os. The Data Direction register

(TRISx) determines whether the pin is an input or an out-

put. If the data direction bit is a ‘1’, then the pin is an input.

All port pins are defined as inputs after a Reset. The LATx

register controls the pin level when it is configured as an

output. Reads from the PORTx register read the port pins,

while writes to the port pins write the latch, LATx. The I/O

state reflected in the PORTx register is synchronized with

the system clock and delayed by 3 system clock cycles.

The CNEN0x and CNEN1x registers contain the CN

interrupt enable control bits for each of the input pins.

The setting of these bits enables a CN interrupt for the

corresponding pins. Also, these bits, in combination

with the CNSTYLE bit (CNCONx<11>), define a type of

transition when the interrupt is generated. Possible CN

event options are listed in Table 9-1.

9.3

Open-Drain Configuration

In addition to the PORTx, LATx and TRISx registers for

data control, the port pins can also be individually config-

ured for either digital or open-drain outputs. This is

controlled by the Open-Drain Control register, ODCx,

associated with each port. Setting any of the bits

configures the corresponding pin to act as an open-drain

output.

TABLE 9-1:

CHANGE NOTIFICATION

EVENT OPTIONS

CNSTYLE Bit CNEN1x CNEN0x Change Notification Event

(CNCONx<11>)

Bit

Description

0

Doesnot

matter

0

Disabled

The open-drain feature allows the generation of

outputs higher than VDD (e.g., 5V), on any desired 5V

tolerant pins, by using external pull-up resistors. The

maximum open-drain voltage allowed is the same as

the maximum VIH specification.

0

Doesnot

matter

1

Detects a mismatch between

the last read state and the

current state of the pin

1

0

1

Disabled

Detects a positive transition

only (from ‘

Detects a negative transition

only (from ‘ ’ to ‘ ’)

0’ to ‘1’)

9.4

Configuring Analog and Digital

Port Pins

1

0

1

0

When the PORTx register is read, all pins configured as

analog input channels are read as cleared (a low level).

Detects both positive and

negative transitions

Pins configured as digital inputs do not convert an

analog input. Analog levels on any pin defined as a

digital input (including the ANx pins) can cause the input

buffer to consume current that exceeds the device spec-

ifications. The ANSELx register controls the operation of

the analog port pins. The port pins that are to function as

analog inputs must have their corresponding ANSELx

and TRISx bits set. In order to use port pins for I/O func-

tionality with digital modules, such as timers, UARTs,

etc., the corresponding ANSELx bit must be cleared.

The ANSELx register has a default value of 0xFFFF.

Therefore, all pins that share analog functions are

analog (not digital) by default. If the TRISx bit is cleared

(output) while the ANSELx bit is set, the digital output

level (VOH or VOL) is used by an analog peripheral, such

as the ADC or comparator module.

The CNSTATx register indicates whether a change

occurred on the corresponding pin since the last read

of the PORTx bit. In addition to the CNSTATx register,

the CNFx register is implemented for each port. This

register contains flags for Change Notification events.

These flags are set if the valid transition edge, selected

in the CNEN0x and CNEN1x registers, is detected.

CNFx stores the occurrence of the event. CNFx bits

must be cleared in software to get the next Change

Notification interrupt. The CN interrupt is generated

only for the I/Os configured as inputs (corresponding

TRISx bits must be set).

DS60001324C-page 80

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9.8.2

AVAILABLE PERIPHERALS

9.7

Pin Pull-up and Pull-Down

The peripherals managed by the PPS are all digital

only peripherals. These include general serial commu-

nications (UART and SPI), general purpose timer clock

inputs, timer related peripherals (MCCP, SCCP) and

others.

Each I/O pin also has a weak pull-up and a weak pull-

down connected to it. The pull-ups act as a current

source, or sink source, connected to the pin and

eliminate the need for external resistors when push

button or keypad devices are connected. The pull-ups

and pull-downs are enabled separately using the

CNPUx and the CNPDx registers, which contain the

control bits for each of the pins. Setting any of the control

bits enables the weak pull-ups and/or pull-downs for the

corresponding pins.

In comparison, some digital only peripheral modules are

never included in the PPS feature. This is because the

peripheral’s function requires special I/O circuitry on a

specific port and cannot be easily connected to multiple

pins. A similar requirement excludes all modules with

analog inputs, such as the Analog-to-Digital Converter

(ADC).

9.8

Peripheral Pin Select (PPS)

A key difference between remappable and non-

remappable peripherals is that remappable peripherals

are not associated with a default I/O pin. The peripheral

must always be assigned to a specific I/O pin before it

can be used. In contrast, non-remappable peripherals

are always available on a default pin, assuming that the

peripheral is active and not conflicting with another

peripheral.

A major challenge in general purpose devices is provid-

ing the largest possible set of peripheral features, while

minimizing the conflict of features on I/O pins. The

challenge is even greater on low pin count devices. In

an application where more than one peripheral needs

to be assigned to a single pin, inconvenient work

arounds in application code, or a complete redesign,

may be the only option.

When a remappable peripheral is active on a given I/O

pin, it takes priority over all other digital I/Os and digital

communication peripherals associated with the pin.

Priority is given regardless of the type of peripheral that

is mapped. Remappable peripherals never take priority

over any analog functions associated with the pin.

PPS configuration provides an alternative to these

choices by enabling peripheral set selection and their

placement on a wide range of I/O pins. By increasing

the pinout options available on a particular device,

users can better tailor the device to their entire

application, rather than trimming the application to fit

the device.

9.8.3

CONTROLLING PPS

The PPS configuration feature operates over a fixed

subset of digital I/O pins. Users may independently

map the input and/or output of most digital peripherals

to these I/O pins. PPS is performed in software

and generally does not require the device to be

reprogrammed. Hardware safeguards are included that

prevent accidental or spurious changes to the

peripheral mapping once it has been established.

PPS features are controlled through two sets of SFRs:

one to map peripheral inputs and one to map outputs.

Because they are separately controlled, a particular

peripheral’s input and output (if the peripheral has both)

can be placed on any selectable function pin without

constraint.

The association of a peripheral to a peripheral-selectable

pin is handled in two different ways, depending on

whether an input or output is being mapped.

9.8.1

AVAILABLE PINS

The number of available pins is dependent on the

particular device and its pin count. Pins that support the

PPS feature include the designation, “RPn”, in their full

pin designation, where “RP” designates a Remappable

Peripheral and “n” is the remappable port number.



2015-2018 Microchip Technology Inc.

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PIC32MM0064GPL036 FAMILY

9.8.4

INPUT MAPPING

FIGURE 9-2:

REMAPPABLE INPUT

EXAMPLE FOR U2RX

The RPINRx registers are used to assign the peripheral

input to the required remappable pin, RPn (refer to the

peripheral inputs and the corresponding RPINRx regis-

ters listed in Table 9-2). Each RPINRx register contains

sets of 5-bit fields. Programming these bits with the

remappable pin number will connect the peripheral to

this RPn pin. Example 9-1 and Figure 9-2 illustrate the

remappable pin selection for the U2RX input.

U2RXR<4:0>

1

RP1

RP2

RP3

2

U2RX Input

to Peripheral

3

EXAMPLE 9-1:

UART2 RX INPUT

ASSIGNMENT TO 

RP9/RB14 PIN

RPINR9bits.U2RXR = 9; // connect UART2 RX

// input to RP9 pin

n

RPn

Note:

For input only, PPS functionality does not

have priority over TRISx settings. Therefore,

when configuring an RPn pin for input, the

corresponding bit in the TRISx register must

also be configured for input (set to ‘1’).

TABLE 9-2:

INPUT PIN SELECTION

Function Name

INT4

Input Name

Register

RPINR1

Function Bits

External Interrupt 4

MCCP1 Input Capture

SCCP2 Input Capture

SCCP3 Input Capture

Output Compare Fault A

Output Compare Fault B

CCP Clock Input A

CCP Clock Input B

UART2 Receive

INT4R<4:0>

ICM1R<4:0>

ICM2R<4:0>

ICM3R<4:0>

OCFAR<4:0>

OCFBR<4:0>

TCKIAR<4:0>

TCKIBR<4:0>

U2RXR<4:0>

U2CTSR<4:0>

SDI2R<4:0>

ICM1

ICM2

RPINR2

RPINR3

RPINR5

RPINR6

RPINR9

RPINR11

RPINR12

ICM3

OCFA

OCFB

TCKIA

TCKIB

U2RX

UART2 Clear-to-Send

SPI2 Data Input

U2CTS

SDI2

SPI2 Clock Input

SCK2IN

SS2IN

CLCINA

CLCINB

SCK2INR<4:0>

SS2INR<4:0>

CLCINAR<4:0>

CLCINBR<4:0>

SPI2 Slave Select Input

CLC Input A

CLC Input B

DS60001324C-page 82

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9.8.5

OUTPUT MAPPING

9.8.6

CONTROLLING CONFIGURATION

CHANGES

The RPORx registers are used to assign the peripheral

output to the required remappable pin, RPn. Each

RPORx register contains 4-bit fields corresponding to

the remappable pins. A special value is defined for

each peripheral output. This value should be written to

the remappable pin bit field in the RPORx register to

connect the peripheral output to the RPn pin. All

possible (implemented) values for the peripheral’s

outputs are listed in Table 9-3.

Because peripheral remapping can be changed during

run time, some restrictions on peripheral remapping

are needed to prevent accidental configuration

changes. PIC32MM0064GPL036 family devices

include two features to prevent alterations to the

peripheral map:

• Control register lock sequence

• Configuration bit select lock

Example 9-2 and Figure 9-3 illustrate the peripheral’s

output selection for the remappable pin.

9.8.6.1

Control Register Lock

Under normal operation, the RPORx and RPINRx

registers can be written, but they can also be locked

to prevent accidental writes. This feature is con-

trolled by the IOLOCK bit in the RPCON register. If

the IOLOCK bit is set, then the contents of the

RPORx and RPINRx registers cannot be changed.

EXAMPLE 9-2:

UART2 TX OUTPUT

ASSIGNMENT TO 

RP13/RB13 PIN

RPOR4bits.RP13R = 1;

// connect UART2 TX (= 1)

// to RP13 pin

To modify the IOLOCK bit, an unlock sequence must be

executed. Refer to Section 23.4 “System Registers

Write Protection” for details.

FIGURE 9-3:

EXAMPLE OF

MULTIPLEXING OF

REMAPPABLE OUTPUT

FOR RP1

RP1R<3:0>

Default

U2TX Output

SDO2 Output

0

1

2

RP1

Output Data

CLC2OUT

9

TABLE 9-3:

OUTPUT PIN SELECTION

Output Function Number

Function

Output Name

0

1

2

3

4

5

6

7

8

9

None (not connected)

U2TX

—

UART2 Transmit

U2RTS

UART2 Request-to-Send

SPI2 Data Output

SPI2 Clock Output

SPI2 Slave Select Output

SCCP2 Output Compare

SCCP3 Output Compare

CLC1 Output

SDO2

SCK2OUT

SS2OUT

OCM2

OCM3

CLC1OUT

CLC2OUT

CLC2 Output



2015-2018 Microchip Technology Inc.

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REGISTER 9-1:

CNCONx: CHANGE NOTIFICATION CONTROL FOR PORTx REGISTER (x = A-C)

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

R/W-0

ON

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CNSTYLE

U-0

—

U-0

—

U-0

—

U-0

—

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Change Notification (CN) Control On bit

1= CN is enabled

0= CN is disabled

bit 14-12 Unimplemented: Read as ‘0’

bit 11 CNSTYLE: Change Notification Style Selection bit

1= Edge style (detects edge transitions, CNFx bits are used for a Change Notice event)

0= Mismatch style (detects change from last PORTx read, CNSTATx bits are used for a Change Notification

event)

bit 10-0 Unimplemented: Read as ‘0’

DS60001324C-page 88

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

PIC32MM0064GPL036 family devices feature one

synchronous/asynchronous 16-bit timer that can operate

10.0 TIMER1

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

as a free-running interval timer for various timing

applications and counting external events. This timer

can be clocked from different sources, such as the

Peripheral Bus Clock (PBCLK, 1:1 with SYSCLK),

Secondary Oscillator (SOSC), T1CK pin or LPRC

oscillator.

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 14. “Timers”

(DS60001105) in the “PIC32 Family

Reference Manual”, which is available

The following modes are supported by Timer1:

• Synchronous Internal Timer

• Synchronous Internal Gated Timer

• Synchronous External Timer

• Asynchronous External Timer

from

the

Microchip

web

site

(www.microchip.com/PIC32). The infor-

mation in this data sheet supersedes the

information in the FRM.

The timer has a selectable clock prescaler and can

operate in Sleep and Idle modes.

FIGURE 10-1:

TIMER1 BLOCK DIAGRAM

PR1

Equal

Trigger

to ADC

TSYNC

16-Bit Comparator

1

0

Sync

TMR1

Reset

0

T1IF

Event Flag

1

Q

D

TGATE

TCS

TGATE

ON

00

SOSC

T1CK

LPRC

x1

10

00

01

10

Prescaler

Gate

Sync

1, 8, 64, 256

TECS<1:0>

PBCLK

2

(1:1 with SYSCLK)

TCKPS<1:0>



2015-2018 Microchip Technology Inc.

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REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

U-0

—

R/W-0

U-0

—

R/W-0

SIDL

R/W-0

TWDIS

R/W-0

R-0

U-0

R/W-0

ON

TWIP

U-0

—

TECS<1:0>

R/W-0

TGATE

U-0

R/W-0

U-0

—

TCKPS<1:0>

—

TSYNC

TCS

—

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15

ON: Timer1 On bit

1= Timer1 is enabled

0= Timer1 is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

SIDL: Timer1 Stop in Idle Mode bit

1= Discontinues operation when device enters Idle mode

0= Continues operation even in Idle mode

bit 12

bit 11

TWDIS: Asynchronous Timer1 Write Disable bit

1= Writes to TMR1 are ignored until pending write operation completes

0= Back-to-back writes are enabled (Legacy Asynchronous Timer mode functionality)

TWIP: Asynchronous Timer1 Write in Progress bit

In Asynchronous Timer1 mode:

1= Asynchronous write to TMR1 register is in progress

0= Asynchronous write to TMR1 register is complete

In Synchronous Timer1 mode:

This bit is read as ‘0’.

bit 10

Unimplemented: Read as ‘0’

bit 9-8

TECS<1:0>: Timer1 External Clock Selection bits

11= Reserved

10= External clock comes from the LPRC

01= External clock comes from the T1CK Pin

00= External clock comes from the Secondary Oscillator (SOSC)

bit 7

TGATE: Timer1 Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation is enabled

0= Gated time accumulation is disabled

bit 6

Unimplemented: Read as ‘0’

bit 5-4

TCKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:256 prescale value

10= 1:64 prescale value

01= 1:8 prescale value

00= 1:1 prescale value



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REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER (CONTINUED)

bit 3

bit 2

Unimplemented: Read as ‘0’

TSYNC: Timer1 External Clock Input Synchronization Selection bit

When TCS = 1:

1= External clock input is synchronized

0= External clock input is not synchronized

When TCS = 0:

This bit is ignored.

bit 1

bit 0

TCS: Timer1 Clock Source Select bit

1= External clock is defined by the TECS<1:0> bits

0= Internal peripheral clock

Unimplemented: Read as ‘0’

DS60001324C-page 92

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Some of the key features of the WDT module are:

• Configuration or Software Controlled

11.0 WATCHDOG TIMER (WDT)

Note:

This data sheet summarizes the features

• User-Configurable Time-out Period

of the PIC32MM0064GPL036 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 62. “Dual Watch-

dog Timer” (DS60001365) in the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32). The infor-

mation in this data sheet supersedes the

information in the FRM.

• Different Time-out Periods for Run and Sleep/Idle

modes

• Operates from LPRC Oscillator in Sleep/Idle

modes

• Different Clock Sources for Run mode

• Can Wake the Device from Sleep or Idle

The Watchdog Timer can be cleared by writing the 16-bit

value, 0x5743, to the upper half of the WDTCON

register.

When enabled, the Watchdog Timer (WDT) can be

used to detect system software malfunctions by

resetting the device if the WDT is not cleared

periodically in software. Various WDT time-out periods

can be selected using the WDT postscaler. The WDT

can also be used to wake the device from Sleep or Idle

mode.

EXAMPLE 11-1:

CODE SEQUENCE TO

CLEAR THE WDT

unsigned short *pWdtClr;

// create a pointer to the upper half of WDTCON

pWdtClr = (unsigned short*)&WDTCON + 1;

// 16-bit variable

main()

{

...user code

*pWdtClr = 0x5743;

}

// clear the WDT

FIGURE 11-1:

WATCHDOG TIMER BLOCK DIAGRAM

Power Save

Mode WDT

LPRC Oscillator

Power Save

Wake-up and

NMI

25-Bit Counter

Comparator

CLKSEL<1:0>

Reset

Power Save

ON

SLPDIV<4:0>

Run Mode WDT

25-Bit Counter

SYSCLK

Reserved

00

01

10

11

NMI and Start

NMI Counter

Power Save

Comparator

FRC Oscillator

LPRC Oscillator

Reset

RUNDIV<4:0>

WDTCLRKEY<15:0> = 5743h

ON

All Resets

System Clock Switching



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REGISTER 11-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

W-0

R-y

W-0

R-y

31:24

23:16

15:8

7:0

WDTCLRKEY<15:8>

W-0

WDTCLRKEY<7:0>

R/W-0

U-0

—

U-0

—

R-y

RUNDIV<4:0>

R-y

(1)

ON

R-y

R/W-y

CLKSEL<1:0>

SLPDIV<4:0>

WDTWINEN

Legend:

y = Values set from Configuration bits on Reset

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 WDTCLRKEY<15:0>: Watchdog Timer Clear Key bits

To clear the Watchdog Timer to prevent a time-out, software must write the value, 0x5743, to this location

using a single 16-bit write.

(1)

bit 15

ON: Watchdog Timer Enable bit

1= The WDT is enabled

0= The WDT is disabled

bit 14-13 Unimplemented: Read as ‘0’

bit 12-8 RUNDIV<4:0>: Shadow Copy of Watchdog Timer Postscaler Value for Run Mode from Configuration bits

On Reset, these bits are set to the values of the RWDTPS<4:0> Configuration bits in FWDT.

bit 7-6

bit 5-1

bit 0

CLKSEL<1:0>: Shadow Copy of Watchdog Timer Clock Selection Value for Run Mode from Configuration bits

On Reset, these bits are set to the values of the RCLKSEL<1:0> Configuration bits in FWDT.

SLPDIV<4:0>: Shadow Copy of Watchdog Timer Postscaler Value for Sleep/Idle Mode from Configuration bits

On Reset, these bits are set to the values of the SWDTPS<4:0> Configuration bits in FWDT.

WDTWINEN: Watchdog Timer Window Enable bit

On Reset, this bit is set to the inverse of the value of the inverse of the WINDIS Configuration bit in FWDT.

1= Windowed mode is enabled

0= Windowed mode is disabled

Note 1: This bit only has control when FWDTEN (FWDT<15>) = 0.



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NOTES:

DS60001324C-page 96

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

• Fully Asynchronous Operation in All Modes and in

Low-Power Operation

12.0 CAPTURE/COMPARE/PWM/

TIMER MODULES (MCCP AND

SCCP)

• Special Output Trigger for ADC Conversions

• 16-Bit and 32-Bit General Purpose Timer modes

with Optional Gated Operation for Simple Time

Measurements

Note:

This data sheet summarizes the features of

the PIC32MM0064GPL036 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 30. “Cap-

ture/Compare/PWM/Timer (MCCP and

SCCP)” (DS60001381) in the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32). The infor-

mation in this data sheet supersedes the

information in the FRM.

• Capture modes:

- Backward compatible with previous input

capture peripherals of the PIC32 family

- 16-bit or 32-bit capture of time base on 

external event

- Up to four-level deep FIFO capture buffer

- Capture source input multiplexer

- Gated capture operation to reduce 

noise-induced false captures

• Output Compare/PWM modes:

- Backward compatible with previous output

compare peripherals of the PIC32 family

12.1 Introduction

- Single Edge and Dual Edge Compare modes

- External Input mode

PIC32MM0064GPL036 family devices include three

Capture/Compare/PWM/Timer (CCP) modules. These

modules are similar to the multipurpose timer modules

found on many other 32-bit microcontrollers. They also

provide the functionality of the comparable input

capture, output compare and general purpose timer

peripherals found in all earlier PIC32 devices.

MCCP modules also include these extended PWM 

features:

• Single Output Steerable mode

• Brush DC Motor (Forward and Reverse) modes

• Half-Bridge with Dead-Time Delay mode

• Push-Pull PWM mode

CCP modules can operate in one of three major modes:

• General Purpose Timer

• Input Capture

• Output Scan mode

• Auto-Shutdown with Programmable Source and

Shutdown State

• Output Compare/PWM

There are two different forms of the module, distinguished

by the number of PWM outputs that the module can

generate. Single Capture/Compare/PWM/Timer (SCCPs)

output modules provide only one PWM output. Multiple

Capture/Compare/PWM/Timer (MCCPs) output modules

can provide up to six outputs and an extended range of

output control features, depending on the pin count of the

particular device.

• Programmable Output Polarity

• Center-Aligned Compare mode

• Variable Frequency Pulse mode

The SCCP and MCCP modules can be operated in

only one of the three major modes (Capture, Compare

or Timer) at any time. The other modes are not

available unless the module is reconfigured.

A conceptual block diagram for the module is shown in

Figure 12-1. All three modes use the time base gener-

ator and the common Timer register pair (CCPxTMR).

Other shared hardware components, such as

comparators and buffer registers, are activated and

used as a particular mode requires.

All modules (SCCP and MCCP) include these features:

• User-Selectable Clock Inputs, including System

Clock and External Clock Input Pins

• Input Clock Prescaler for Time Base

• Output Postscaler for module Interrupt Events or

Triggers

• Synchronization Output Signal for Coordinating

other MCCP/SCCP modules with 

User-Configurable Alternate and Auxiliary Source

Options



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FIGURE 12-1:

MCCP/SCCP CONCEPTUAL BLOCK DIAGRAM

CCPxIF

CCTxIF

External

Capture

Input

Input Capture

CCPxTMR

CCP Sync Out

Special Event Trigger Out (ADC)

Auxiliary Output

Time Base

Clock

Sources

(1)

Generator

T32

CCSEL

MOD<3:0>

Compare/PWM

Output(s)

Output Compare/

PWM

16/32-Bit

Timer

Sync and

Gating

Sources

OCFA/OCFB

Note 1: Refer to Figure 8-2 for REFO connection.

Each module also includes eight buffer/counter

registers that serve as Timer Value registers or data

holding buffers:

12.2 Registers

Each MCCP/SCCP module has up to seven control

and status registers:

• CCPxTMR is the 32-Bit Timer/Counter register

• CCPxPR is the 32-Bit Timer Period register

• CCPxCON1 (Register 12-1) controls many of the

features common to all modes, including input

clock selection, time base prescaling, timer

synchronization, Trigger mode operations and

postscaler selection for all modes. The module is

also enabled and the operational mode is

selected from this register.

• CCPxR is the 32-bit primary data buffer for output

compare operations

• CCPxBUF(H/L) registers are the 32-bit buffer 

register pair, which are used in input capture FIFO

operations

• CCPxCON2 (Register 12-2) controls auto-

shutdown and restart operation, primarily for

PWM operations, and also configures other input

capture and output compare features, and 

configures auxiliary output operation.

• CCPxCON3 (Register 12-3) controls multiple 

output PWM dead time, controls the output of the

output compare and PWM modes, and configures

the PWM Output mode for the MCCP modules.

• CCPxSTAT (Register 12-4) contains read-only

status bits showing the state of module operations.

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REGISTER 12-1: CCPxCON1: CAPTURE/COMPARE/PWMx CONTROL 1 REGISTER

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

R/W-0

OPSSRC

R/W-0

RTRGEN

R/W-0

U-0

—

U-0

—

R/W-0

31:24

23:16

15:8

7:0

(1)

(2)

(3)

OPS<3:0>

R/W-0

SYNC<4:0>

R/W-0

TRIGEN

ONESHOT ALTSYNC

R/W-0

U-0

—

R/W-0

SIDL

R/W-0

T32

R/W-0

CLKSEL<2:0>

R/W-0

(1)

ON

CCPSLP TMRSYNC

R/W-0

TMRPS<1:0>

CCSEL

MOD<3:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

(1)

bit 31

bit 30

OPSSRC: Output Postscaler Source Select bit

1= Output postscaler scales the Special Event Trigger output events

0= Output postscaler scales the timer interrupt events

(2)

RTRGEN: Retrigger Enable bit

1= Time base can be retriggered when CCPTRIG = 1

0= Time base may not be retriggered when CCPTRIG = 1

bit 29-28 Unimplemented: Read as ‘0’

(3)

bit 27-24 OPS<3:0>: CCPx Interrupt Output Postscale Select bits

1111= Interrupt every 16th time base period match

1110= Interrupt every 15th time base period match

. . .

0100= Interrupt every 5th time base period match

0011= Interrupt every 4th time base period match or 4th input capture event

0010= Interrupt every 3rd time base period match or 3rd input capture event

0001= Interrupt every 2nd time base period match or 2nd input capture event

0000= Interrupt after each time base period match or input capture event

bit 23

bit 22

bit 21

TRIGEN: CCPx Triggered Enable bit

1= Triggered operation of the timer is enabled

0= Triggered operation of the timer is disabled

ONESHOT: One-Shot Mode Enable bit

1= One-Shot Triggered mode is enabled; trigger duration is set by OSCNT<2:0>

0= One-Shot Triggered mode is disabled

ALTSYNC: CCPx Clock Select bit

1= An alternate signal is used as the module synchronization output signal

0= The module synchronization output signal is the Time Base Reset/rollover event

Note 1: This control bit has no function in Input Capture modes.

2: This control bit has no function when TRIGEN = 0.

3: Values greater than ‘0011’ will cause a FIFO buffer overflow in Input Capture mode.

4: Refer to Figure 8-2 for REFO connection.

5: Not available on SCCP modules.

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REGISTER 12-1: CCPxCON1: CAPTURE/COMPARE/PWMx CONTROL 1 REGISTER (CONTINUED)

bit 20-16 SYNC<4:0>: CCPx Synchronization Source Select bits

11111= Timer is in the Free-Running mode and rolls over at FFFFh (Timer Period register is ignored)

11110= Reserved

. . .

11100= Reserved

11011= Time base is synchronized to the start of ADC conversion

11010= Reserved

11001= Time base is synchronized to Comparator 2

11000= Time base is synchronized to Comparator 1

10111= Reserved

. . .

10010= Reserved

10001= Time base is synchronized to CLC2

10001= Time base is synchronized to CLC1

01111= Reserved

01110= Reserved

01101= Time base is synchronized to the INT4 pin (remappable)

01100= Time base is synchronized to the INT3 pin

01011= Time base is synchronized to the INT2 pin

01010= Time base is synchronized to the INT1 pin

01001= Time base is synchronized to the INT0 pin

01000= Reserved

. . .

00101= Reserved

00100= Time base is synchronized to SCCP3

00011= Time base is synchronized to SCCP2

00010= Time base is synchronized to MCCP1

00001= Time base is synchronized to this MCCP/SCCP

00000= No external synchronization; timer rolls over at FFFFh or matches with the Timer Period register

(1)

bit 15

ON: CCPx Module Enable bit

1= Module is enabled with the operating mode specified by the MOD<3:0> bits

0= Module is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

SIDL: CCPx Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

bit 12

bit 11

CCPSLP: CCPx Sleep Mode Enable bit

1= Module continues to operate in Sleep modes

0= Module does not operate in Sleep modes

TMRSYNC: Time Base Clock Synchronization bit

1= Module time base clock is synchronized to internal system clocks; timing restrictions apply

0= Module time base clock is not synchronized to internal system clocks

Note 1: This control bit has no function in Input Capture modes.

2: This control bit has no function when TRIGEN = 0.

3: Values greater than ‘0011’ will cause a FIFO buffer overflow in Input Capture mode.

4: Refer to Figure 8-2 for REFO connection.

5: Not available on SCCP modules.

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REGISTER 12-1: CCPxCON1: CAPTURE/COMPARE/PWMx CONTROL 1 REGISTER (CONTINUED)

bit 10-8 CLKSEL<2:0>: CCPx Time Base Clock Select bits

111= TCKIA pin (remappable)

110= TCKIB pin (remappable)

101= Reserved

100= Reserved

011= CLC1 output for MCCP1 and SCCP2/CLC2 output for SCCP3

010= Secondary Oscillator (SOSC) clock

(4)

001= REFCLKO output clock

000= System clock (FSYS

)

bit 7-6

TMRPS<1:0>: CCPx Time Base Prescale Select bits

11= 1:64 prescaler

10= 1:16 prescaler

01= 1:4 prescaler

00= 1:1 prescaler

bit 5

T32: 32-Bit Time Base Select bit

1= 32-bit time base for timer, single edge output compare or input capture function

0= 16-bit time base for timer, single edge output compare or input capture function

bit 4

CCSEL: Capture/Compare Mode Select bit

1= Input Capture mode

0= Output Compare/PWM or Timer mode (exact function is selected by the MOD<3:0> bits)

bit 3-0

MOD<3:0>: CCPx Mode Select bits

CCSEL = 1(Input Capture modes):

1xxx= Reserved

011x= Reserved

0101= Capture every 16th rising edge

0100= Capture every 4th rising edge

0011= Capture every rising and falling edge

0010= Capture every falling edge

0001= Capture every rising edge

0000= Capture every rising and falling edge (Edge Detect mode)

CCSEL = 0(Output Compare modes):

1111= External Input mode: Pulse generator is disabled, source is selected by ICS<2:0>

1110= Reserved

110x= Reserved

10xx= Reserved

(5)

0111= Variable Frequency Pulse mode

(5)

0110= Center-Aligned PWM mode, buffered

0101= Dual Edge PWM mode, buffered

0100= Dual Edge Compare mode

0011= 16-Bit/32-Bit Single Edge mode: Toggles output on compare match

0010= 16-Bit/32-Bit Single Edge mode: Drives output low on compare match

0001= 16-Bit/32-Bit Single Edge mode: Drives output high on compare match

0000= 16-Bit/32-Bit Timer mode: Output functions are disabled

Note 1: This control bit has no function in Input Capture modes.

2: This control bit has no function when TRIGEN = 0.

3: Values greater than ‘0011’ will cause a FIFO buffer overflow in Input Capture mode.

4: Refer to Figure 8-2 for REFO connection.

5: Not available on SCCP modules.

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REGISTER 12-2: CCPxCON2: CAPTURE/COMPARE/PWMx CONTROL 2 REGISTER

Bit

Range

31/23/15/7

30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

R/W-0

OENSYNC

R/W-0

U-0

—

R/W-0

OCFEN

U-0

R/W-0

OCEEN

R/W-0

OCDEN

R/W-0

OCCEN

R/W-0

OCBEN

R/W-0

R/W-1

OCAEN

R/W-0

31:24

23:16

15:8

7:0

(1)

R/W-0

ICGSM<1:0>

—

AUXOUT<1:0>

ICS<2:0>

U-0

R/W-0

PWMRSEN

R/W-0

ASDGM

R/W-0

U-0

R/W-0

U-0

—

U-0

—

SSDG

—

R/W-0

ASDG<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31

OENSYNC: Output Enable Synchronization bit

1= Update by output enable bits occurs on the next Time Base Reset or rollover

0= Update by output enable bits occurs immediately

bit 30

Unimplemented: Read as ‘0’

(1)

bit 29-24 OC<F:A>EN: Output Enable/Steering Control bits

1= OCx pin is controlled by the CCPx module and produces an output compare or PWM signal

0= OCx pin is not controlled by the CCPx module; the pin is available to the port logic or another peripheral

multiplexed on the pin

bit 23-22 ICGSM<1:0>: Input Capture Gating Source Mode Control bits

11= Reserved

10= One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)

01= One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)

00= Level-Sensitive mode: A high level from gating source will enable future capture events; a low level

will disable future capture events

bit 21

Unimplemented: Read as ‘0’

bit 20-19 AUXOUT<1:0>: Auxiliary Output Signal on Event Selection bits

11= Input capture or output compare event; no signal in Timer mode

10= Signal output depends on module operating mode

01= Time base rollover event (all modes)

00= Disabled

bit 18-16 ICS<2:0>: Input Capture Source Select bits

111= Reserved

110= Reserved

101= CLC2 output

100= CLC1 output

011= Reserved

010= Comparator 2 output

001= Comparator 1 output

000= ICMx pin (remappable)

bit 15

PWMRSEN: CCPx PWM Restart Enable bit

1= ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has ended

0= ASEVT must be cleared in software to resume PWM activity on output pins

Note 1: OCFEN through OCBEN (bits<29:25>) are implemented in MCCP modules only.

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REGISTER 12-2: CCPxCON2: CAPTURE/COMPARE/PWMx CONTROL 2 REGISTER (CONTINUED)

bit 14

ASDGM: CCPx Auto-Shutdown Gate Mode Enable bit

1= Waits until the next Time Base Reset or rollover for shutdown to occur

0= Shutdown event occurs immediately

bit 13

bit 12

Unimplemented: Read as ‘0’

SSDG: CCPx Software Shutdown/Gate Control bit

1= Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting the ASDGM

bit still applies)

0= Normal module operation

bit 11-8 Unimplemented: Read as ‘0’

bit 7-0 ASDG<7:0>: CCPx Auto-Shutdown/Gating Source Enable bits

1xxx xxxx= Auto-shutdown is controlled by the OCFB pin (remappable)

x1xx xxxx= Auto-shutdown is controlled by the OCFA pin (remappable)

xx1x xxxx= Auto-shutdown is controlled by CLC1 for MCCP1/SCCP2 and by CLC2 for SCCP3

xxx1 xxxx= Auto-shutdown is controlled by the SCCP2 output for MCCP1 and by MCCP1 for

SCCP2/SCCP3

xxxx 1xxx= Auto-shutdown is controlled by the SCCP3 output for MCCP1/SCCP2 and by SCCP2 for

SCCP3

xxxx x1xx= Reserved

xxxx xx1x= Auto-shutdown is controlled by Comparator 2

xxxx xxx1= Auto-shutdown is controlled by Comparator 1

Note 1: OCFEN through OCBEN (bits<29:25>) are implemented in MCCP modules only.



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REGISTER 12-3: CCPxCON3: CAPTURE/COMPARE/PWMx CONTROL 3 REGISTER

Bit

24/16/8/0

Bit Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

R/W-0

OETRIG

U-0

R/W-0

OSCNT<2:0>

R/W-0

U-0

—

R/W-0

OUTM<2:0>

R/W-0

31:24

23:16

15:8

7:0

(1)

U-0

—

R/W-0

(1)

—

POLACE POLBDF

PSSACE<1:0>

PSSBDF<1:0>

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

(1)

—

DT<5:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31

OETRIG: PWM Dead-Time Select bit

1= For Triggered mode (TRIGEN = 1), the module does not drive enabled output pins until triggered

0= Normal output pin operation

bit 30-28

OSCNT<2:0>: One-Shot Event Count bits

Extends the duration of a one-shot trigger event by an additional n clock cycles (n+1 total cycles).

111= 7 timer count periods (8 cycles total)

110= 6 timer count periods (7 cycles total)

101= 5 timer count periods (6 cycles total)

100= 4 timer count periods (5 cycles total)

011= 3 timer count periods (4 cycles total)

010= 2 timer count periods (3 cycles total)

001= 1 timer count period (2 cycles total)

000= Does not extend the one-shot trigger event (the event takes 1 timer count period)

bit 27

Unimplemented: Read as ‘0’

(1)

bit 26-24

OUTM<2:0>: PWMx Output Mode Control bits

111= Reserved

110= Output Scan mode

101= Brush DC Output mode, forward

100= Brush DC Output mode, reverse

011= Reserved

010= Half-Bridge Output mode

001= Push-Pull Output mode

000= Steerable Single Output mode

bit 23-22

bit 21

Unimplemented: Read as ‘0’

POLACE: CCPx Output Pins, OCxA, OCxC and OCxE, Polarity Control bit

1= Output pin polarity is active-low

0= Output pin polarity is active-high

(1)

bit 20

POLBDF: CCPx Output Pins, OCxB, OCxD and OCxF, Polarity Control bit

1= Output pin polarity is active-low

0= Output pin polarity is active-high

bit 19-18

PSSACE<1:0>: PWMx Output Pins, OCxA, OCxC and OCxE, Shutdown State Control bits

11= Pins are driven active when a shutdown event occurs

10= Pins are driven inactive when a shutdown event occurs

0x= Pins are in a high-impedance state when a shutdown event occurs

Note 1: These bits are implemented in MCCP modules only.

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REGISTER 12-3: CCPxCON3: CAPTURE/COMPARE/PWMx CONTROL 3 REGISTER (CONTINUED)

(1)

bit 17-16

PSSBDF<1:0>: PWMx Output Pins, OCxB, OCxD and OCxF, Shutdown State Control bits

11= Pins are driven active when a shutdown event occurs

10= Pins are driven inactive when a shutdown event occurs

0x= Pins are in a high-impedance state when a shutdown event occurs

bit 15-6

bit 5-0

Unimplemented: Read as ‘0’

(1)

DT<5:0>: PWM Dead-Time Select bits

111111= Inserts 63 dead-time delay periods between complementary output signals

111110= Inserts 62 dead-time delay periods between complementary output signals

. . .

000010= Inserts 2 dead-time delay periods between complementary output signals

000001= Inserts 1 dead-time delay period between complementary output signals

000000= Dead-time logic is disabled

Note 1: These bits are implemented in MCCP modules only.



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REGISTER 12-4: CCPxSTAT: CAPTURE/COMPARE/PWMx STATUS REGISTER

Bit

24/16/8/0

Bit Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

—

U-0

R-0

—

PRLWIP

U-0

TMRHWIP TMRLWIP

RBWIP

U-0

RAWIP

U-0

—

R/C-0

ICGARM

R/C-0

(1)

—

R-0

W1-0

TRSET

W1-0

TRCLR

R/C-0

ASEVT

R/C-0

SCEVT

R/C-0

ICOV

R/C-0

ICBNE

CCPTRIG

ICDIS

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-21

bit 20

Unimplemented: Read as ‘0’

PRLWIP: CCPxPRL Write in Progress Status bit

1= An update to the CCPxPRL register with the buffered contents is in progress

0= An update to the CCPxPRL register is not in progress

bit 19

bit 18

bit 17

bit 16

TMRHWIP: CCPxTMRH Write in Progress Status bit

1= An update to the CCPxTMRH register with the buffered contents is in progress

0= An update to the CCPxTMRH register is not in progress

TMRLWIP: CCPxTMRL Write in Progress Status bit

1= An update to the CCPxTMRL register with the buffered contents is in progress

0= An update to the CCPxTMRL register is not in progress

RBWIP: CCPxRB Write in Progress Status bit

1= An update to the CCPxRB register with the buffered contents is in progress

0= An update to the CCPxRB register is not in progress

RAWIP: CCPxRA Write in Progress Status bit

1= An update to the CCPxRA register with the buffered contents is in progress

0= An update to the CCPxRA register is not in progress

bit 15-11

bit 10

Unimplemented: Read as ‘0’

(1)

ICGARM: Input Capture Gate Arm bit

A write of ‘1’ to this location will arm the input capture gating logic for a one-shot gate event when

ICGSM<1:0> = 01or 10. The bit location reads as ‘0’.

bit 9-8

bit 7

Unimplemented: Read as ‘0’

CCPTRIG: CCPx Trigger Status bit

1= Timer has been triggered and is running (set by hardware or writing to TRSET)

0= Timer has not been triggered and is held in Reset (cleared by writing to TRCLR)

bit 6

bit 5

bit 4

TRSET: CCPx Trigger Set Request bit

Write ‘1’ to this location to trigger the timer when TRIGEN = 1(location always reads ‘0’).

TRCLR: CCPx Trigger Clear Request bit

Write ‘1’ to this location to cancel the timer trigger when TRIGEN = 1(location always reads ‘0’).

ASEVT: CCPx Auto-Shutdown Event Status/Control bit

1= A shutdown event is in progress; CCPx outputs are in the shutdown state

0= CCPx outputs operate normally

Note 1: This is not a physical bit location and will always read as ‘0’. A write of ‘1’ will initiate the hardware event.

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REGISTER 12-4: CCPxSTAT: CAPTURE/COMPARE/PWMx STATUS REGISTER (CONTINUED)

bit 3

bit 2

bit 1

bit 0

SCEVT: Single Edge Compare Event Status bit

1= A single edge compare event has occurred

0= A single edge compare event has not occurred

ICDIS: Input Capture Disable bit

1= Event on input capture pin does not generate a capture event

0= Event on input capture pin will generate a capture event

ICOV: Input Capture Buffer Overflow Status bit

1= The input capture FIFO buffer has overflowed

0= The input capture FIFO buffer has not overflowed

ICBNE: Input Capture Buffer Status bit

1= The input capture buffer has data available

0= The input capture buffer is empty

Note 1: This is not a physical bit location and will always read as ‘0’. A write of ‘1’ will initiate the hardware event.



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NOTES:

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as digital audio devices. These peripheral devices may

be serial EEPROMs, shift registers, display drivers,

Analog-to-Digital Converters (ADC), etc.

13.0 SERIAL PERIPHERAL

INTERFACE (SPI) AND

INTER-IC SOUND (I²S)

2

The SPI/I S module is compatible with Motorola^®SPI

and SIOP interfaces.

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to Section 23. “Serial Peripheral

Interface (SPI)” (DS61106) in the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32). The informa-

tion in this data sheet supersedes the

information in the FRM.

Some of the key features of the SPI module are:

• Master and Slave modes Support

• Four Different Clock Formats

• Enhanced Framed SPI Protocol Support

• User-Configurable 8-Bit, 16-Bit and 32-Bit Data Width

• Separate SPI FIFO Buffers for Receive and Transmit:

- FIFO buffers act as 4/8/16-level deep FIFOs

based on 32/16/8-bit data width

• Programmable Interrupt Event on Every 8-Bit, 

16-Bit and 32-Bit Data Transfer

• Operation during Sleep and Idle modes

• Audio Codec Support:

- I S protocol

2

The SPI/I S module is a synchronous serial interface

that is useful for communicating with external

peripherals and other microcontroller devices, as well

2

FIGURE 13-1:

SPI/I²S MODULE BLOCK DIAGRAM

Internal

Data Bus

(1)

SPIxBUF

Read

Write

FIFOs Share Address SPIxBUF

SPIxRXB FIFO SPIxTXB FIFO

Transmit

Receive

SPIxSR

SDIx

bit 0

Shift

MCLKSEL

SDOx

Control

Slave Select

and Frame

Sync Control

Clock

Control

Edge

Select

(2)

SSx/FSYNC1

SCKx

REFOCLK

Baud Rate

Generator

PBCLK

(1:1 with SYSCLK)

MSTEN

Note 1: Access the SPIxTXB and SPIxRXB FIFOs via the SPIxBUF register.

2: Refer to Figure 8-2 for REFO connection.



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REGISTER 13-1: SPIxCON: SPIx CONTROL REGISTER

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

R/W-0

FRMEN

R/W-0

MSSEN

U-0

R/W-0

FRMSYPW

U-0

R/W-0

FRMCNT<2:0>

R/W-0

31:24

23:16

15:8

7:0

FRMSYNC FRMPOL

U-0

—

R/W-0

(1)

MCLKSEL

R/W-0

—

SPIFE

ENHBUF

U-0

R/W-0

SIDL

R/W-0

MSTEN

R/W-0

(4)

(2)

ON

—

DISSDO

MODE32

R/W-0

MODE16

R/W-0

SMP

CKE

R/W-0

(3)

(4)

SSEN

CKP

DISSDI

STXISEL<1:0>

SRXISEL<1:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31

bit 30

bit 29

bit 28

FRMEN: Framed SPI Support bit

1= Framed SPI support is enabled (SSx pin is used as the FSYNC1 input/output)

0= Framed SPI support is disabled

FRMSYNC: Frame Sync Pulse Direction Control on SSx Pin bit (Framed SPI mode only)

1= Frame sync pulse input (Slave mode)

0= Frame sync pulse output (Master mode)

FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)

1= Frame pulse is active-high

0= Frame pulse is active-low

MSSEN: Master Mode Slave Select Enable bit

1= Slave select SPI support is enabled; the SSx pin is automatically driven during transmission in Master

mode, polarity is determined by the FRMPOL bit

0= Slave select SPI support is disabled

bit 27

FRMSYPW: Frame Sync Pulse-Width bit

1= Frame sync pulse is one character wide

0= Frame sync pulse is one clock wide

bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits

Controls the number of data characters transmitted per pulse. This bit is only valid in Framed mode.

111= Reserved

110= Reserved

101= Generates a frame sync pulse on every 32 data characters

100= Generates a frame sync pulse on every 16 data characters

011= Generates a frame sync pulse on every 8 data characters

010= Generates a frame sync pulse on every 4 data characters

001= Generates a frame sync pulse on every 2 data characters

000= Generates a frame sync pulse on every data character

Note 1: These bits can only be written when the ON bit = 0. Refer to Section 26.0 “Electrical Characteristics” for

maximum clock frequency requirements.

2: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI

mode (FRMEN = 1).

2

3: When AUDEN = 1, the SPI/I S module functions as if the CKP bit is equal to ‘1’, regardless of the actual

value of the CKP bit.

4: These bits are present for legacy compatibility and are superseded by PPS functionality on these devices

(see Section 9.8 “Peripheral Pin Select (PPS)” for more information).

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REGISTER 13-1: SPIxCON: SPIx CONTROL REGISTER (CONTINUED)

(1)

bit 23

MCLKSEL: Master Clock Enable bit

1= REFCLKO is used by the Baud Rate Generator

0= PBCLK is used by the Baud Rate Generator (1:1 with SYSCLK)

bit 22-18 Unimplemented: Read as ‘0’

bit 17

bit 16

bit 15

SPIFE: SPIx Frame Sync Pulse Edge Select bit (Framed SPI mode only)

1= Frame synchronization pulse coincides with the first bit clock

0= Frame synchronization pulse precedes the first bit clock

(1)

ENHBUF: Enhanced Buffer Enable bit

1= Enhanced Buffer mode is enabled

0= Enhanced Buffer mode is disabled

ON: SPIx Module On bit

1= SPIx module is enabled

0= SPIx module is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

SIDL: SPIx Stop in Idle Mode bit

1= Discontinues operation when CPU enters Idle mode

0= Continues operation in Idle mode

(4)

bit 12

DISSDO: Disable SDOx Pin bit

1= SDOx pin is not used by the module; the pin is controlled by the associated PORTx register

0= SDOx pin is controlled by the module

bit 11-10 MODE<32,16>: 32/16/8-Bit Communication Select bits

When AUDEN = 1:

MODE32

MODE16

Communication

1

0

1

0

1

0

24-bit data, 32-bit FIFO, 32-bit channel/64-bit frame

32-bit data, 32-bit FIFO, 32-bit channel/64-bit frame

16-bit data, 16-bit FIFO, 32-bit channel/64-bit frame

16-bit data, 16-bit FIFO, 16-bit channel/32-bit frame

When AUDEN = 0:

MODE32

MODE16

Communication

32-bit

16-bit

1

0

x

1

0

8-bit

bit 9

bit 8

SMP: SPIx Data Input Sample Phase bit

Master mode (MSTEN = 1):

1= Input data is sampled at the end of data output time

0= Input data is sampled at the middle of data output time

Slave mode (MSTEN = 0):

SMP value is ignored when SPIx is used in Slave mode. The module always uses SMP = 0.

(2)

CKE: SPIx Clock Edge Select bit

1= Serial output data changes on transition from active clock state to Idle clock state (see the CKP bit)

0= Serial output data changes on transition from Idle clock state to active clock state (see the CKP bit)

Note 1: These bits can only be written when the ON bit = 0. Refer to Section 26.0 “Electrical Characteristics” for

maximum clock frequency requirements.

2: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI

mode (FRMEN = 1).

2

3: When AUDEN = 1, the SPI/I S module functions as if the CKP bit is equal to ‘1’, regardless of the actual

value of the CKP bit.

4: These bits are present for legacy compatibility and are superseded by PPS functionality on these devices

(see Section 9.8 “Peripheral Pin Select (PPS)” for more information).

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REGISTER 13-1: SPIxCON: SPIx CONTROL REGISTER (CONTINUED)

bit 7

bit 6

bit 5

bit 4

bit 3-2

SSEN: Slave Select Enable (Slave mode) bit

1= SSx pin is used for Slave mode

0= SSx pin is not used for Slave mode, pin is controlled by port function

(3)

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level; active state is a low level

0= Idle state for clock is a low level; active state is a high level

MSTEN: Master Mode Enable bit

1= Master mode

0= Slave mode

(4)

DISSDI: Disable SDIx bit

1= SDIx pin is not used by the SPIx module (pin is controlled by port function)

0= SDIx pin is controlled by the SPIx module

STXISEL<1:0>: SPIx Transmit Buffer Empty Interrupt Mode bits

11= Interrupt is generated when the buffer is not full (has one or more empty elements)

10= Interrupt is generated when the buffer is empty by one-half or more

01= Interrupt is generated when the buffer is completely empty

00= Interrupt is generated when the last transfer is shifted out of SPIxSR and transmit operations are complete

bit 1-0

SRXISEL<1:0>: SPIx Receive Buffer Full Interrupt Mode bits

11= Interrupt is generated when the buffer is full

10= Interrupt is generated when the buffer is full by one-half or more

01= Interrupt is generated when the buffer is not empty

00= Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)

Note 1: These bits can only be written when the ON bit = 0. Refer to Section 26.0 “Electrical Characteristics” for

maximum clock frequency requirements.

2: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI

mode (FRMEN = 1).

2

3: When AUDEN = 1, the SPI/I S module functions as if the CKP bit is equal to ‘1’, regardless of the actual

value of the CKP bit.

4: These bits are present for legacy compatibility and are superseded by PPS functionality on these devices

(see Section 9.8 “Peripheral Pin Select (PPS)” for more information).

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REGISTER 13-2: SPIxCON2: SPIx CONTROL REGISTER 2

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4

27/19/11/3

26/18/10/2 25/17/9/1 24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

—

U-0

—

R/W-0

—

R/W-0

SPISGNEXT

R/W-0

U-0

—

U-0

—

R/W-0

FRMERREN

U-0

SPIROVEN SPITUREN IGNROV IGNTUR

U-0

R/W-0

U-0

R/W-0

(1)

(1,2)

AUDEN

—

AUDMONO

—

AUDMOD<1:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 SPISGNEXT: SPIx Sign-Extend Read Data from the RX FIFO bit

1= Data from RX FIFO is sign-extended

0= Data from RX FIFO is not sign-extended

bit 14-13 Unimplemented: Read as ‘0’

bit 12

bit 11

bit 10

bit 9

FRMERREN: Enable Interrupt Events via FRMERR bit

1= Frame error overflow generates error events

0= Frame error does not generate error events

SPIROVEN: Enable Interrupt Events via SPIROV bit

1= Receive Overflow (ROV) generates error events

0= Receive Overflow does not generate error events

SPITUREN: Enable Interrupt Events via SPITUR bit

1= Transmit Underrun (TUR) generates error events

0= Transmit Underrun does not generate error events

IGNROV: Ignore Receive Overflow (ROV) bit (for audio data transmissions)

1= A ROV is not a critical error; during ROV, data in the FIFO is not overwritten by receive data

0= A ROV is a critical error which stops SPIx operation

bit 8

IGNTUR: Ignore Transmit Underrun (TUR) bit (for audio data transmissions)

1= A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty

0= A TUR is a critical error which stops SPIx operation

(1)

bit 7

AUDEN: Enable Audio Codec Support bit

1= Audio protocol is enabled

0= Audio protocol is disabled

bit 6-4

bit 3

Unimplemented: Read as ‘0’

(1,2)

AUDMONO: Transmit Audio Data Format bit

1= Audio data is mono (each data word is transmitted on both left and right channels)

0= Audio data is stereo

bit 2

Unimplemented: Read as ‘0’

(1,2)

bit 1-0

AUDMOD<1:0>: Audio Protocol Mode bits

11= PCM/DSP mode

10= Right Justified mode

01= Left Justified mode

2

00= I S mode

Note 1: These bits can only be written when the ON bit = 0.

2: These bits are only valid for AUDEN = 1.

DS60001324C-page 116

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REGISTER 13-3: SPIxSTAT: SPIx STATUS REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5

28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

R-0

RXBUFELM<4:0>

R-0

31:24

23:16

15:8

7:0

U-0

R-0

—

TXBUFELM<4:0>

U-0

R/C-0, HS

FRMERR

U-0

—

R-0

—

SPIBUSY

R-1

—

U-0

—

SPITUR

R-0

R/W-0

R-0

SRMT

SPIROV

SPIRBE

—

SPITBE

SPITBF

SPIRBF

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HS = Hardware Settable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

bit 31-29 Unimplemented: Read as ‘0’

bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1)

bit 23-21 Unimplemented: Read as ‘0’

bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)

bit 15-13 Unimplemented: Read as ‘0’

bit 12

FRMERR: SPIx Frame Error status bit

1= Frame error is detected

0= No frame error is detected

This bit is only valid when FRMEN = 1.

bit 11

SPIBUSY: SPIx Activity Status bit

1= SPIx peripheral is currently busy with some transactions

0= SPIx peripheral is currently Idle

bit 10-9 Unimplemented: Read as ‘0’

bit 8

SPITUR: SPIx Transmit Underrun (TUR) bit

1= Transmit buffer has encountered an underrun condition

0= Transmit buffer has no underrun condition

This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling

the module.

bit 7

bit 6

SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)

1= When the SPIx Shift register is empty

0= When the SPIx Shift register is not empty

SPIROV: SPIx Receive Overflow (ROV) Flag bit

1= New data is completely received and discarded; the user software has not read the previous data in the

SPIxBUF register

0= No overflow has occurred

This bit is set in hardware; it can only be cleared (= 0) in software.

bit 5

bit 4

SPIRBE: SPIx RX FIFO Empty bit (valid only when ENHBUF = 1)

1= RX FIFO is empty (CPU Read Pointer (CRPTR) = SPI Write Pointer (SWPTR))

0= RX FIFO is not empty (CRPTR SWPTR)

Unimplemented: Read as ‘0’

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REGISTER 13-3: SPIxSTAT: SPIx STATUS REGISTER (CONTINUED)

bit 3

SPITBE: SPIx Transmit Buffer Empty Status bit

1= Transmit buffer, SPIxTXB, is empty

0= Transmit buffer, SPIxTXB, is not empty

Automatically set in hardware when SPIx transfers data from SPIxTXB to SPIxSR. Automatically cleared in

hardware when SPIxBUF is written to, loading SPIxTXB.

bit 2

bit 1

Unimplemented: Read as ‘0’

SPITBF: SPIx Transmit Buffer Full Status bit

1= Transmit has not yet started, SPIxTXB is full

0= Transmit buffer is not full

Standard Buffer mode:

Automatically set in hardware when the core writes to the SPIxBUF location, loading SPIxTXB. Automatically

cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.

Enhanced Buffer mode:

Set when the CPU Write Pointer (CWPTR) + 1 = SPI Read Pointer (SRPTR); cleared otherwise.

bit 0

SPIRBF: SPIx Receive Buffer Full Status bit

1= Receive buffer, SPIxRXB, is full

0= Receive buffer, SPIxRXB, is not full

Standard Buffer mode:

Automatically set in hardware when the SPIx module transfers data from SPIxSR to SPIxRXB. Automatically

cleared in hardware when SPIxBUF is read from, reading SPIxRXB.

Enhanced Buffer mode:

Set when SWPTR + 1 = CRPTR; cleared otherwise.

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The primary features of the UART module are:

14.0 UNIVERSAL ASYNCHRONOUS

• Full-Duplex, 8-Bit or 9-Bit Data Transmission

• Even, Odd or No Parity Options (for 8-bit data)

• One or Two Stop Bits

RECEIVER TRANSMITTER

(UART)

Note:

This data sheet summarizes the features of

the PIC32MM0064GPL036 family of

devices. It is not intended to be a compre-

hensive reference source. To complement

the information in this data sheet, refer to

Section 21. “UART” (DS60001107) in the

“PIC32 Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32). The informa-

tion in this data sheet supersedes the

information in the FRM.

• Hardware Auto-Baud Feature

• Hardware Flow Control Option

• Fully Integrated Baud Rate Generator (BRG) with

16-Bit Prescaler

• Baud Rates Ranging from 47.7 bps to 6.26 Mbps

at 25 MHz

• 8-Level Deep First-In-First-Out (FIFO) Transmit

Data Buffer

• 8-Level Deep FIFO Receive Data Buffer

• Parity, Framing and Buffer Overrun Error 

Detection

The UART module is one of the serial I/O modules

available in the PIC32MM0064GPL036 family

devices. The UART is a full-duplex, asynchronous

communication channel that communicates with

peripheral devices and personal computers through

protocols, such as RS-232, RS-485, LIN/J2602 and

IrDA^®. The module also supports the hardware flow

control option with the UxCTS and UxRTS pins, and

also includes an IrDA encoder and decoder.

• Support for Interrupt Only on Address Detect 

(9th bit = 1)

• Separate Transmit and Receive Interrupts

• Loopback mode for Diagnostic Support

• LIN/J2602 Protocol Support

• IrDA Encoder and Decoder with 16x Baud Clock

Output for External IrDA Encoder/Decoder Support

• Supports Separate UART Baud Clock Input

• Ability to Continue to Run when a Receive 

Overflow (ROV) Condition Exists

• Ability to Run and Receive Data during Sleep mode

Figure 14-1 illustrates a simplified block diagram of the

UART module.

FIGURE 14-1:

UARTx SIMPLIFIED BLOCK DIAGRAM

PBCLK

(1:1 with SYSCLK)

Baud Rate Generator

IrDA^®

UxRTS/BCLKx

UxCTS

Hardware Flow Control

UARTx Receiver

UARTx Transmitter

UxRX

UxTX



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REGISTER 14-1: UxMODE: UARTx MODE REGISTER

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

R/W-0

SLPEN

R/W-0

ON

R/W-0

ACTIVE

U-0

R/W-0

OVFDIS

—

CLKSEL<1:0>

R/W-0

SIDL

R/W-0

ABAUD

R/W-0

IREN

R/W-0

RXINV

R/W-0

RTSMD

R/W-0

BRGH

U-0

R/W-0

(2)

—

UEN<1:0>

R/W-0

WAKE

LPBACK

PDSEL<1:0>

STSEL

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23

SLPEN: Run During Sleep Enable bit

1= UARTx clock runs during Sleep

0= UARTx clock is turned off during Sleep

bit 22

ACTIVE: UARTx Running Status bit

1= UARTx is active (UxMODE register shouldn’t be updated)

0= UARTx is not active (UxMODE register can be updated)

bit 21-19 Unimplemented: Read as ‘0’

(1)

bit 18-17 CLKSEL<1:0>: UARTx Clock Selection bits

11= The UARTx clock is the Reference Clock Output (REFCLKO)

10= The UARTx clock is the FRC oscillator clock

01= The UARTx clock is the SYSCLK

00= The UARTx clock is the PBCLK (1:1 with SYSCLK)

bit 16

bit 15

OVFDIS: Run During Overflow Condition Mode bit

1= When an Overflow Error (OERR) condition is detected, the Shift register continues to run to remain

synchronized

0= When an Overflow Error (OERR) condition is detected, the Shift register stops accepting new data

(Legacy mode)

ON: UARTx Enable bit

1= UARTx is enabled; UARTx pins are controlled by UARTx, as defined by the UEN<1:0> and UTXEN

control bits

0= UARTx is disabled; all UARTx pins are controlled by the corresponding bits in the PORTx, TRISx and

LATx registers; UARTx power consumption is minimal

bit 14

bit 13

Unimplemented: Read as ‘0’

SIDL: UARTx Stop in Idle Mode bit

1= Discontinues operation when device enters Idle mode

0= Continues operation in Idle mode

®

bit 12

IREN: IrDA Encoder and Decoder Enable bit

1= IrDA is enabled

0= IrDA is disabled

Note 1: Refer to Figure 8-2 for REFO connection.

2: These bits are present for legacy compatibility and are superseded by PPS functionality on these devices

(see Section 9.8 “Peripheral Pin Select (PPS)” for more information).



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REGISTER 14-1: UxMODE: UARTx MODE REGISTER (CONTINUED)

bit 11

RTSMD: Mode Selection for UxRTS Pin bit

1= UxRTS pin is in Simplex mode

0= UxRTS pin is in Flow Control mode

bit 10

Unimplemented: Read as ‘0’

(2)

bit 9-8

UEN<1:0>: UARTx Enable bits

11= UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits

in the PORTx register

10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits

in the PORTx register

00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by

corresponding bits in the PORTx register

bit 7

bit 6

bit 5

WAKE: Enable Wake-up on Start Bit Detect During Sleep Mode bit

1= Wake-up is enabled

0= Wake-up is disabled

LPBACK: UARTx Loopback Mode Select bit

1= Loopback mode is enabled

0= Loopback mode is disabled

ABAUD: Auto-Baud Enable bit

1= Enables baud rate measurement on the next character – requires reception of a Sync character (0x55);

cleared by hardware upon completion

0= Baud rate measurement is disabled or has completed

bit 4

RXINV: Receive Polarity Inversion bit

1= UxRX Idle state is ‘0’

0= UxRX Idle state is ‘1’

bit 3

BRGH: High Baud Rate Enable bit

1= High-Speed mode – 4x baud clock is enabled

0= Standard Speed mode – 16x baud clock is enabled

bit 2-1

PDSEL<1:0>: Parity and Data Selection bits

11= 9-bit data, no parity

10= 8-bit data, odd parity

01= 8-bit data, even parity

00= 8-bit data, no parity

bit 0

STSEL: Stop Selection bit

1= 2 Stop bits

0= 1 Stop bit

Note 1: Refer to Figure 8-2 for REFO connection.

2: These bits are present for legacy compatibility and are superseded by PPS functionality on these devices

(see Section 9.8 “Peripheral Pin Select (PPS)” for more information).

DS60001324C-page 122

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REGISTER 14-2: UxSTA: UARTx STATUS AND CONTROL REGISTER

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

R/W-0

31:24

23:16

15:8

7:0

MASK<7:0>

R/W-0

ADDR<7:0>

R/W-0

UTXINV

R/W-0

URXEN

R-1

R/W-0

UTXBRK

R-0

R/W-0

UTXEN

R-0

R-1

TRMT

R-0

UTXISEL<1:0>

UTXBF

R/W-0

URXISEL<1:0>

ADDEN

RIDLE

PERR

FERR

OERR

URXDA

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 MASK<7:0>: UARTx Address Match Mask bits

Used to mask the ADDR<7:0> bits.

For MASK<x>:

1= ADDR<x> is used to detect the address match

0= ADDR<x> is not used to detect the address match

bit 23-16 ADDR<7:0>: UARTx Automatic Address Mask bits

When the ADDEN bit is ‘1’, this value defines the address character to use for automatic address detection.

bit 15-14 UTXISEL<1:0>: UARTx TX Interrupt Mode Selection bits

11= Reserved, do not use

10= Interrupt is generated and asserted while the transmit buffer is empty

01= Interrupt is generated and asserted when all characters have been transmitted

00= Interrupt is generated and asserted while the transmit buffer contains at least one empty space

bit 13

UTXINV: UARTx Transmit Polarity Inversion bit

If IrDA mode is Disabled (i.e., IREN (UxMODE<12>) is ‘0’):

1= UxTX Idle state is ‘0’

0= UxTX Idle state is ‘1’

If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is ‘1’):

®

1= IrDA encoded UxTX Idle state is ‘1’

0= IrDA encoded UxTX Idle state is ‘0’

bit 12

bit 11

URXEN: UARTx Receiver Enable bit

1= UARTx receiver is enabled, UxRX pin is controlled by UARTx (if ON = 1)

0= UARTx receiver is disabled, UxRX pin is ignored by the UARTx module

UTXBRK: UARTx Transmit Break bit

1= Sends Break on next transmission; Start bit, followed by twelve ‘0’ bits, followed by Stop bit, cleared by

hardware upon completion

0= Break transmission is disabled or has completed

bit 10

bit 9

bit 8

UTXEN: UARTx Transmit Enable bit

1= UARTx transmitter is enabled, UxTX pin is controlled by UARTx (if ON = 1)

0= UARTx transmitter is disabled, any pending transmission is aborted and the buffer is reset

UTXBF: UARTx Transmit Buffer Full Status bit (read-only)

1= Transmit buffer is full

0= Transmit buffer is not full, at least one more character can be written

TRMT: Transmit Shift Register (TSR) is Empty bit (read-only)

1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)

0= Transmit Shift Register is not empty, a transmission is in progress or queued in the transmit buffer

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REGISTER 14-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)

bit 7-6

URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits

11= Reserved

10= Interrupt flag bit is asserted while receive buffer is 3/4 or more full

01= Interrupt flag bit is asserted while receive buffer is 1/2 or more full

00= Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character)

bit 5

bit 4

bit 3

bit 2

bit 1

ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1= Address Detect mode is enabled; if 9-bit mode is not selected, this control bit has no effect

0= Address Detect mode is disabled

RIDLE: Receiver Idle bit (read-only)

1= Receiver is Idle

0= Data is being received

PERR: Parity Error Status bit (read-only)

1= Parity error has been detected for the current character

0= Parity error has not been detected

FERR: Framing Error Status bit (read-only)

1= Framing error has been detected for the current character

0= Framing error has not been detected

OERR: Receive Buffer Overrun Error Status bit

This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit

resets the receiver buffer and RSR to the empty state.

1= Receive buffer has overflowed

0= Receive buffer has not overflowed

bit 0

URXDA: UARTx Receive Buffer Data Available bit (read-only)

1= Receive buffer has data, at least one more character can be read

0= Receive buffer is empty

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Key features of the RTCC module are:

15.0 REAL-TIME CLOCK AND

CALENDAR (RTCC)

• Time: Hours, Minutes and Seconds

• 24-Hour Format (military time)

Note:

This data sheet summarizes the features

• Visibility of One-Half Second Period

of the PIC32MM0064GPL036 family of

devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to Section 28. “RTCC with

Timestamp” (DS60001362) in the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32). The informa-

tion in this data sheet supersedes the

information in the FRM.

• Provides Calendar: Weekday, Date, Month and Year

• Alarm Intervals are Configurable for Half of a

second, One Second, 10 Seconds, One Minute, 

10 Minutes, One Hour, One Day, One Week, 

One Month and One Year

• Alarm Repeat with Decrementing Counter

• Alarm with Indefinite Repeat: Chime

• Year Range: 2000 to 2099

• Leap Year Correction

• BCD Format for Smaller Firmware Overhead

• Optimized for Long-Term Battery Operation

• Fractional Second Synchronization

The RTCC module is intended for applications in which

accurate time must be maintained for extended periods

of time with minimal or no CPU intervention. Low-

power optimization provides extended battery lifetime

while keeping track of time.

• User Calibration of the Clock Crystal Frequency

with Auto-Adjust

• Uses External 32.768 kHz Crystal, 32 kHz Internal

Oscillator, PWRLCLK Input Pin or Peripheral Clock

• Alarm Pulse, Seconds Clock or Internal Clock 

Output on RTCC Pin

FIGURE 15-1:

RTCC BLOCK DIAGRAM

CLKSEL<1:0>

PWRLCLK Input Pin

Peripheral Clock

(PBCLK, 1.1 with SYSCLK)

32.768 kHz Input from

Secondary Oscillator (SOSC)

32 kHz Input from

Internal Oscillator (LPRC)

TRTC

RTCC Prescalers

0.5 seconds

YEAR, MTH, DAY

RTCC Timer

RTCTIME/ALMTIME

WKDAY

HR, MIN, SEC

Alarm

Event

Comparator

MTH, DAY

WKDAY

Compare Registers

with Masks

HR, MIN, SEC

Repeat Counter

RTCC Interrupt

Alarm Pulse

RTCC Interrupt Logic

Seconds Pulse

RTCC Pin

TRTC

RTCOE

OUTSEL<2:0>

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REGISTER 15-1: RTCCON1: RTCC CONTROL 1 REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5

28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

R/W-0

ALRMEN

R/W-0

CHIME

R/W-0

U-0

—

U-0

—

R/W-0

31:24

23:16

15:8

7:0

AMASK<3:0>

R/W-0

(1)

ALMRPT<7:0>

R/W-0

ON

U-0

—

U-0

—

U-0

R/W-0

U-0

—

U-0

—

U-0

—

(2)

—

WRLOCK

R/W-0

U-0

RTCOE

OUTSEL<2:0>

—

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31

bit 30

ALRMEN: Alarm Enable bit

1= Alarm is enabled

0= Alarm is disabled

CHIME: Chime Enable bit

1= Chime is enabled; ALMRPT<7:0> bits are allowed to underflow from ‘00’ to ‘FF’

0= Chime is disabled; ALMRPT<7:0> bits stop once they reach ‘00’

bit 29-28 Unimplemented: Read as ‘0’

bit 27-24 AMASK<3:0>: Alarm Mask Configuration bits

11xx= Reserved, do not use

101x= Reserved, do not use

1001= Once a year (or once every 4 years when configured for February 29th)

1000= Once a month

0111= Once a week

0110= Once a day

0101= Every hour

0100= Every 10 minutes

0011= Every minute

0010= Every 10 seconds

0001= Every second

0000= Every half second

(1)

bit 23-16 ALMRPT<7:0>: Alarm Repeat Counter Value bits

11111111= Alarm will repeat 255 more times

11111110= Alarm will repeat 254 more times

• • •

00000010= Alarm will repeat 2 more times

00000001= Alarm will repeat 1 more time

00000000= Alarm will not repeat

bit 15

ON: RTCC Enable bit

1= RTCC is enabled and counts from selected clock source

0= RTCC is disabled

bit 14-12 Unimplemented: Read as ‘0’

Note 1: The counter decrements on any alarm event. The counter is prevented from rolling over from ‘00’ to ‘FF’

unless CHIME = 1.

2: To clear this bit, an unlock sequence is required. Refer to Section 23.4 “System Registers Write

Protection” for details.

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REGISTER 15-1: RTCCON1: RTCC CONTROL 1 REGISTER (CONTINUED)

(2)

bit 11

WRLOCK: RTCC Registers Write Lock bit

1= Registers associated with accurate timekeeping are locked

0= Registers associated with accurate timekeeping may be written to by user

bit 10-8 Unimplemented: Read as ‘0’

bit 7

RTCOE: RTCC Output Enable bit

1= RTCC clock output is enabled; signal selected by OUTSEL<2:0> is presented on the RTCC pin

0= RTCC clock output is disabled

bit 6-4

OUTSEL<2:0>: RTCC Signal Output Selection bits

111= Reserved

• • •

011= Reserved

010= RTCC input clock source (user-defined divided output based on the combination of the RTCCON2

bits, DIV<15:0> and PS<1:0>)

001= Seconds clock

000= Alarm event

bit 3-0

Unimplemented: Read as ‘0’

Note 1: The counter decrements on any alarm event. The counter is prevented from rolling over from ‘00’ to ‘FF’

unless CHIME = 1.

2: To clear this bit, an unlock sequence is required. Refer to Section 23.4 “System Registers Write

Protection” for details.

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REGISTER 15-2: RTCCON2: RTCC CONTROL 2 REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

R/W-0

31:24

23:16

15:8

7:0

DIV<15:8>

R/W-0

DIV<7:0>

R/W-0

FDIV<4:0>

U-0

R/W-0

U-0

—

U-0

—

U-0

—

U-0

R/W-0

—

CLKSEL<1:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 DIV<15:0>: Clock Divide bits

Sets the period of the clock divider counter; value should cause a nominal 1/2 second underflow.

bit 15-11 FDIV<4:0>: Fractional Clock Divide bits

11111= Clock period increases by 31 RTCC input clock cycles every 16 seconds

11101= Clock period increases by 30 RTCC input clock cycles every 16 seconds

• • •

00010= Clock period increases by 2 RTCC input clock cycles every 16 seconds

00001= Clock period increases by 1 RTCC input clock cycle every 16 seconds

00000= No fractional clock division

bit 10-2 Unimplemented: Read as ‘0’

bit 1-0

CLKSEL<1:0>: Clock Select bits

11= Peripheral clock (FCY

10= PWRLCLK input pin

01= LPRC

)

00= SOSC

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REGISTER 15-3: RTCSTAT: RTCC STATUS REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5

28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R-0, HS, HC

U-0

R-0, HS, HC

—

ALMEVT

—

SYNC

ALMSYNC HALFSEC

Legend:

HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-6 Unimplemented: Read as ‘0’

bit 5

ALMEVT: Alarm Event bit

1= An alarm event has occurred

0= An alarm event has not occurred

bit 4-3

bit 2

Unimplemented: Read as ‘0’

SYNC: Synchronization Status bit

1= Time registers may change during software read

0= Time registers may be read safely

bit 1

bit 0

ALMSYNC: Alarm Synchronization status bit

1= Alarm registers (ALMTIME and ALMDATE) and RTCCON1 should not be modified; the ALRMEN and

ALMRPT<7:0> bits may change during software read

0= Alarm registers and Alarm Control registers may be modified safely

HALFSEC: Half Second Status bit

1= Second half of 1-second period

0= First half of 1-second period

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REGISTER 15-4: RTCTIME/ALMTIME: RTCC/ALARM TIME REGISTERS

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

R/W-0

HRTEN<2:0>

R/W-0

31:24

23:16

15:8

7:0

HRONE<3:0>

U-0

R/W-0

—

MINTEN<2:0>

R/W-0

MINONE<3:0>

R/W-0

SECTEN<3:0>

SECONE<3:0>

U-0

—

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31

Unimplemented: Read as ‘0’

bit 30-28 HRTEN<2:0>: Binary Coded Decimal Value of Hours 10-Digit bits

Contains a value from 0 to 2.

bit 27-24 HRONE<3:0>: Binary Coded Decimal Value of Hours 1-Digit bits

Contains a value from 0 to 9.

bit 23

Unimplemented: Read as ‘0’

bit 22-20 MINTEN<2:0>: Binary Coded Decimal Value of Minutes 10-Digit bits

Contains a value from 0 to 5.

bit 19-16 MINONE<3:0>: Binary Coded Decimal Value of Minutes 1-Digit bits

Contains a value from 0 to 9.

bit 15-12 SECTEN<3:0>: Binary Coded Decimal Value of Seconds 10-Digit bits

Contains a value from 0 to 5.

bit 11-8 SECONE<3:0>: Binary Coded Decimal Value of Seconds 1-Digit bits

Contains a value from 0 to 9.

bit 7-0

Unimplemented: Read as ‘0’

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REGISTER 15-5: RTCDATE: RTCC DATE REGISTERS

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

R/W-0

31:24

23:16

15:8

7:0

YRTEN<3:0>

YRONE<3:0>

U-0

—

U-0

R/W-0

MTHTEN

R/W-0

—

MTHONE<3:0>

U-0

—

R/W-0

—

DAYTEN<1:0>

DAYONE<3:0>

U-0

—

U-0

R/W-0

—

WDAY<2:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 YRTEN<3:0>: Binary Coded Decimal Value of Years 10-Digit bits

bit 27-24 YRONE<3:0>: Binary Coded Decimal Value of Years 1-Digit bits

bit 23-21 Unimplemented: Read as ‘0’

bit 20

MTHTEN: Binary Coded Decimal Value of Months 10-Digit bit

Contains a value from 0 to 1.

bit 19-16 MTHONE<3:0>: Binary Coded Decimal Value of Months 1-Digit bits

Contains a value from 0 to 9.

bit 15-14 Unimplemented: Read as ‘0’

bit 13-12 DAYTEN<1:0>: Binary Coded Decimal Value of Days 10-Digit bits

Contains a value from 0 to 3.

bit 11-8 DAYONE<3:0>: Binary Coded Decimal Value of Days 1-Digit bits

Contains a value from 0 to 9.

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

WDAY<2:0>: Binary Coded Decimal Value of Weekdays Digit bits

Contains a value from 0 to 6.

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REGISTER 15-6: ALMDATE: ALARM DATE REGISTERS

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

U-0

R/W-0

—

MTHTEN

R/W-0

MTHONE<3:0>

U-0

—

U-0

—

R/W-0

DAYTEN<1:0>

DAYONE<3:0>

U-0

R/W-0

—

WDAY<2:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-21 Unimplemented: Read as ‘0’

bit 20 MTHTEN: Binary Coded Decimal Value of Months 10-Digit bit

Contains a value from 0 to 1.

bit 19-16 MTHONE<3:0>: Binary Coded Decimal Value of Months 1-Digit bits

Contains a value from 0 to 9.

bit 15-14 Unimplemented: Read as ‘0’

bit 13-12 DAYTEN<1:0>: Binary Coded Decimal Value of Days 10-Digit bits

Contains a value from 0 to 3.

bit 11-8 DAYONE<3:0>: Binary Coded Decimal Value of Days 1-Digit bits

Contains a value from 0 to 9.

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

WDAY<2:0>: Binary Coded Decimal Value of Weekdays Digit bits

Contains a value from 0 to 6.

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NOTES:

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• External Voltage Reference Input Pins

16.0 12-BIT ANALOG-TO-DIGITAL

• Unipolar Differential Sample-and-Hold Amplifier

(SHA)

CONVERTER WITH

THRESHOLD DETECT

• Automated Threshold Scan and Compare 

Operation to Pre-Evaluate Conversion Results

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

devices. It is not intended to be a compre-

hensive reference source. To complement

the information in this data sheet, refer to

Section 25. “12-Bit Analog-to-Digital

Converter (ADC) with Threshold

Detect” (DS60001359) in the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32). The informa-

tion in this data sheet supersedes the

information in the FRM.

• Selectable Conversion Trigger Source

• Fixed-Length Configurable Conversion Result

Buffer

• Eight Options for Result Alignment and Encoding

• Configurable Interrupt Generation

• Operation during CPU Sleep and Idle modes

Figure 16-1 illustrates a block diagram of the 12-bit

ADC. The 12-bit ADC has 14 external analog inputs,

AN0 through AN13, and 3 internal analog inputs con-

nected to VDD, VSS and band gap. In addition, there are

two analog input pins for external voltage reference

connections.

16.1 Introduction

The analog inputs are connected through a multiplexer

to the SHA. Unipolar differential conversions are

possible on all inputs (see Figure 16-1).

The 12-bit ADC Converter with Threshold Detect

includes the following features:

The Automatic Input Scan mode sequentially converts

multiple analog inputs. A special control register speci-

fies which inputs will be included in the scanning

sequence. The 12-bit ADC is connected to a 16-word

result buffer. The 12-bit result is converted to one of

eight output formats in either 32-bit or 16-bit word

widths.

• Successive Approximation Register (SAR) 

Conversion

• User-Selectable Resolution of 10 or 12 Bits

• Conversion Speeds of up to 222 ksps for 

12-bit mode and 250 ksps for 10-bit mode

• Up to 17 Analog Inputs (internal and external)

FIGURE 16-1:

ADC BLOCK DIAGRAM

VREF

+

AVDD

VREF

-

AVSS

VCFG<2:0>

AVDD

AVSS

ADC1BUF0

ADC1BUF1

ADC1BUF2

Band Gap

AN13

V

REFH

VREFL

AN0

SHA

Channel

Scan

SAR ADC

+

–

CH0SA<4:0>

CSCNA

AVss

ADC1BUF14

ADC1BUF15



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• AD1CSS: ADC Input Scan Select Register

16.2 Control Registers

The AD1CSS register selects inputs to be

sequentially scanned.

The ADC module has the following Special Function

Registers (SFRs):

• AD1CHIT: ADC Compare Hit Register

• AD1CON1: ADC Control Register 1

• AD1CON2: ADC Control Register 2

• AD1CON3: ADC Control Register 3

• AD1CON5: ADC Control Register 5

The AD1CHIT register indicates the channels

meeting specified comparison requirements.

Table 16-1 provides a summary of all ADC module

related registers, including their addresses and

formats. Corresponding registers appear after the

summary, followed by a detailed description of each

register. All unimplemented registers and/or bits within

a register read as zero.

The AD1CON1, AD1CON2, AD1CON3 and

AD1CON5 registers control the operation of the

ADC module.

• AD1CHS: ADC Input Select Register

The AD1CHS register selects the input pins to be

connected to the SHA.

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REGISTER 16-1: AD1CON1: ADC CONTROL REGISTER 1

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4

27/19/11/3

26/18/10/2 25/17/9/1 24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

U-0

—

R/W-0

ON

R/W-0

U-0

—

R/W-0

SIDL

R/W-0

U-0

—

U-0

R/W-0

—

FORM<2:0>

R/W-0, HSC

R/W-0

R/W-0, HSC

(1,3)

(2)

SSRC<3:0>

MODE12

ASAM

SAMP

DONE

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15

ON: ADC Operating Mode bit

1= ADC module is operating

0= ADC is off

bit 14

bit 13

Unimplemented: Read as ‘0’

SIDL: ADC Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

bit 12-11 Unimplemented: Read as ‘0’

bit 10-8 FORM<2:0>: Data Output Format bits

For 12-Bit Operation (MODE12 bit = 1):

111= Signed Fractional 32-bit (DOUT = sddd dddd dddd 0000 0000 0000 0000)

110= Fractional 32-bit (DOUT = dddd dddd dddd 0000 0000 0000 0000 0000)

101= Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sddd dddd dddd)

100= Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 dddd dddd dddd)

011= Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dddd 0000)

010= Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dddd 0000)

001= Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sddd dddd dddd)

000= Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 dddd dddd dddd)

For 10-Bit Operation (MODE12 bit = 0):

111= Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000)

110= Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000)

101= Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd)

100= Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)

011= Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000)

010= Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000)

001= Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd)

000= Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)

Note 1: The SAMP bit is cleared and cannot be written if the ADC is disabled (ON bit = 0).

2: The DONE bit is not persistent in Automatic modes; it is cleared by hardware at the beginning of the 

next sample.

3: In Manual Sample/Manual Convert mode, the sample time must be greater than 3 TAD

.

4: This mode is not available as a trigger when in Threshold Detect mode (ASEN = 1).

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REGISTER 16-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED)

bit 7-4

SSRC<3:0>: Conversion Trigger Source Select bits

1111-1101= Reserved

1100= CLC2 module event ends sampling and starts conversion

1011= CLC1 module event ends sampling and starts conversion

1010= SCCP3 module event ends sampling and starts conversion

1001= SCCP2 module event ends sampling and starts conversion

1000= MCCP1 module event ends sampling and starts conversion

0111= Internal counter ends sampling and starts conversion (auto-convert)

0110= Timer1 period match ends sampling and starts conversion (can trigger during Sleep mode)

0101= Timer1 period match ends sampling and starts conversion (will not trigger during Sleep mode)

0100-0010= Reserved

0001= Active transition on INT0 pin ends sampling and starts conversion

(4)

0000= Clearing the SAMP bit ends sampling and starts conversion

bit 3

bit 2

bit 1

bit 0

MODE12: 12-Bit Operation Mode bit

1= 12-bit ADC operation

0= 10-bit ADC operation

ASAM: ADC Sample Auto-Start bit

1= Sampling begins immediately after last conversion completes; SAMP bit is automatically set

0= Sampling begins when SAMP bit is set

(1,3)

SAMP: ADC Sample Enable bit

1= The ADC Sample-and-Hold Amplifier (SHA) is sampling

0= The ADC Sample-and-Hold Amplifier is holding

(2)

DONE: ADC Conversion Status bit

1= Analog-to-Digital conversion is done

0= Analog-to-Digital conversion is not done or has not started

Clearing this bit will not affect any operation in progress.

Note 1: The SAMP bit is cleared and cannot be written if the ADC is disabled (ON bit = 0).

2: The DONE bit is not persistent in Automatic modes; it is cleared by hardware at the beginning of the 

next sample.

3: In Manual Sample/Manual Convert mode, the sample time must be greater than 3 TAD

.

4: This mode is not available as a trigger when in Threshold Detect mode (ASEN = 1).

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REGISTER 16-2: AD1CON2: ADC CONTROL REGISTER 2

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4

27/19/11/3

26/18/10/2 25/17/9/1 24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

R/W-0

—

R/W-0

—

R/W-0

—

R/W-0

—

R/W-0

—

U-0

—

U-0

—

R/W-0

CSCNA

R/W-0

(1)

VCFG<2:0>

U-0

OFFCAL BUFREGEN

R/W-0

—

R/W-0

U-0

BUFS

—

SMPI<3:0>

BUFM

—

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits

ADC V

R

+

ADC VR-

000

001

010

011

1xx

AVDD

AVSS

External VREF- Pin

AVSS

External VREF+ Pin

External VREF- Pin

Unimplemented; do not use

bit 12

bit 11

bit 10

OFFCAL: Input Offset Calibration Mode Select bit

1= Enables Offset Calibration mode: The inputs of the SHA are connected to the negative reference

0= Disables Offset Calibration mode: The inputs to the SHA are controlled by AD1CHS or AD1CSS

(1)

BUFREGEN: ADC Buffer Register Enable bit

1= Conversion result is loaded into the buffer location determined by the converted channel

0= ADC result buffer is treated as a FIFO

CSCNA: Scan Mode bit

1= Scans inputs

0= Does not scan inputs

bit 9-8

bit 7

Unimplemented: Read as ‘0’

BUFS: Buffer Fill Status bit

Only valid when BUFM = 1(ADC buffers split into 2 x 8-word buffers).

1= ADC is currently filling Buffers 8-15, user should access data in 0-7

0= ADC is currently filling Buffers 0-7, user should access data in 8-15

bit 6

Unimplemented: Read as ‘0’

bit 5-2

SMPI<3:0>: Sample/Convert Sequences per Interrupt Selection bits

th

1111= Interrupts at the completion of conversion for each 16 sample/convert sequence

th

1110= Interrupts at the completion of conversion for each 15 sample/convert sequence

•

nd

0001= Interrupts at the completion of conversion for each 2 sample/convert sequence

0000= Interrupts at the completion of conversion for each sample/convert sequence

bit 1

bit 0

BUFM: ADC Result Buffer Mode Select bit

1= Buffer configured as two 8-word buffers, ADC1BUF(0...7), ADC1BUF(8...15)

0= Buffer configured as one 16-word buffer, ADC1BUF(0...15)

Unimplemented: Read as ‘0’

Note 1: This bit only takes effect when the auto-scan feature is enabled (ASEN (AD1CON5<15>) = 1).

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REGISTER 16-3: AD1CON3: ADC CONTROL REGISTER 3

Bit

25/17/9/1

Bit

24/16/8/0

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

—

R/W-0

ADRC

R/W-0

EXTSAM

R/W-0

U-0

—

R/W-0

SAMC<4:0>

R/W-0

ADCS<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15

bit 14

bit 13

ADRC: ADC Conversion Clock Source (TSRC) bit

1= Clock derived from Fast RC (FRC) oscillator

0= Clock derived from Peripheral Bus Clock (PBCLK, 1:1 with SYSCLK)

EXTSAM: Extended Sampling Time bit

1= ADC is still sampling after SAMP bit = 0

0= ADC stops sampling when SAMP bit = 0

Unimplemented: Read as ‘0’

bit 12-8 SAMC<4:0>: Auto-Sample Time bits

11111= 31 TAD

•

00001= 1 TAD

00000= 0 TAD (not allowed)

bit 7-0

ADCS<7:0>: ADC Conversion Clock Select bits

11111111= 2 • TSRC • ADCS<7:0> = 510 • TSRC = TAD

•

00000001= 2 • TSRC • ADCS<7:0> = 2 • TSRC = TAD

00000000= 1 • TSRC = TAD

Where TSRC is a period of clock selected by the ADRC bit (AD1CON3<15>).

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REGISTER 16-4: AD1CON5: ADC CONTROL REGISTER 5

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

U-0

—

R/W-0

LPEN

U-0

—

R/W-0

BGREQ

U-0

—

U-0

—

R/W-0

(1)

(2)

ASEN

U-0

ASINT<1:0>

U-0

R/W-0

—

WM<1:0>

CM<1:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

(1)

bit 15

ASEN: Auto-Scan Enable bit

1= Auto-scan is enabled

0= Auto-scan is disabled

bit 14

LPEN: Low-Power Enable bit

1= Low power is enabled after scan

0= Full power is enabled after scan

bit 13

bit 12

Unimplemented: Read as ‘0’

BGREQ: Band Gap Request bit

1= Band gap is enabled when the ADC is enabled and active

0= Band gap is not enabled by the ADC

bit 11-10 Unimplemented: Read as ‘0’

(2)

bit 9-8

ASINT<1:0>: Auto-Scan (Threshold Detect) Interrupt Mode bits

11= Interrupt after Threshold Detect sequence has completed and a valid compare has occurred

10= Interrupt after valid compare has occurred

01= Interrupt after Threshold Detect sequence has completed

00= No interrupt

bit 7-4

bit 3-2

Unimplemented: Read as ‘0’

WM<1:0>: Write Mode bits

11= Reserved

10= Auto-compare only (conversion results are not saved, but interrupts are generated when a valid match

occurs, as defined by the CM<1:0> and ASINT<1:0> bits)

01= Convert and save (conversion results saved to ADC1BUFx registers when a match occurs, as defined

by the CM<1:0> bits)

00= Threshold (Comparison) mode is disabled, legacy operation (conversion data saved to ADC1BUFx

registers)

Note 1: When auto-scan is enabled (ASEN (AD1CON5<15>) = 1), the CSCNA (AD1CON2<10>) and SMPI<3:0>

(AD1CON2<5:2>) bits are ignored.

2: The ASINT<1:0> bits setting only takes effect when ASEN (AD1CON5<15>) = 1. Interrupt generation is

governed by the SMPI<3:0> bits field.

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REGISTER 16-4: AD1CON5: ADC CONTROL REGISTER 5 (CONTINUED)

bit 1-0

CM<1:0>: Compare Mode bits

11= Outside Window mode (valid match occurs if the conversion result is outside of the window defined

by the corresponding buffer pair)

10= Inside Window mode (valid match occurs if the conversion result is inside the window defined by the

corresponding buffer pair)

01= Greater Than mode (valid match occurs if the result is greater than the value in the corresponding

buffer register)

00= Less Than mode (valid match occurs if the result is less than the value in the corresponding buffer

register)

Note 1: When auto-scan is enabled (ASEN (AD1CON5<15>) = 1), the CSCNA (AD1CON2<10>) and SMPI<3:0>

(AD1CON2<5:2>) bits are ignored.

2: The ASINT<1:0> bits setting only takes effect when ASEN (AD1CON5<15>) = 1. Interrupt generation is

governed by the SMPI<3:0> bits field.

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REGISTER 16-5: AD1CHS: ADC INPUT SELECT REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

(1)

CH0NA<2:0>

CH0SA<4:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-5

CH0NA<2:0>: Negative Input Select bits

111-001= Reserved

000= Negative input is AVSS

(1)

bit 4-0

CH0SA<4:0>: Positive Input Select bits

11111= Reserved

11110= Positive input is AVDD

11101= Positive input is AVSS

11100= Positive input is Band Gap Reference (VBG

11011-01110= Reserved

)

(2,3)

01101= Positive input is AN13

01100= Positive input is AN12

(2,3)

(2)

01011= Positive input is AN11

01010= Positive input is AN10

01001= Positive input is AN9

01000= Positive input is AN8

00111= Positive input is AN7

00110= Positive input is AN6

00101= Positive input is AN5

00100= Positive input is AN4

00011= Positive input is AN3

00010= Positive input is AN2

00001= Positive input is AN1

00000= Positive input is AN0

Note 1: The CH0SA<4:0> positive input selection is only used when CSCNA (AD1CON2<10>) = 0and 

ASEN (AD1CON5<15>) = 0. The AD1CSS bits specify the positive inputs when CSCNA = 1or ASEN = 1.

2: This option is not implemented in the 20-pin devices.

3: This option is not implemented in the 28-pin devices.

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)

REGISTER 16-6: AD1CSS: ADC INPUT SCAN SELECT REGISTER

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

R/W-0

CSS<30:28>

U-0

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R/W-0

(1,2)

—

CSS<13:8>

R/W-0

CSS<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31

Unimplemented: Read as ‘0’

bit 30-28 CSS<30:28>: ADC Input Pin Scan Selection bits

1= Selects ANx for the input scan

0= Skips ANx for the input scan

bit 27-14 Unimplemented: Read as ‘0’

(1,2)

bit 13-0 CSS<13:0>: ADC Input Pin Scan Selection bits

1= Selects ANx for the input scan

0= Skips ANx for the input scan

Note 1: The CSS<13:11> bits are not implemented in 20-pin devices.

2: The CSS<13:12> bits are not implemented in 28-pin devices.

DS60001324C-page 146

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REGISTER 16-7: AD1CHIT: ADC COMPARE HIT REGISTER

Bit

31/23/15/7

Bit

Bit Range

30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

U-0

—

R/W-0

CHH<13:8>

R/W-0

(1,2)

—

R/W-0

CHH<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-14

bit 13-0

Unimplemented: Read as ‘0’

CHH<13:0>: ADC Compare Hit bits

If CM<1:0> = 11:

(1,2)

1= ADC Result Buffer x has been written with data or a match has occurred

0= ADC Result Buffer x has not been written with data

For All Other Values of CM<1:0>:

1= A match has occurred on ADC Result Channel n

0= No match has occurred on ADC Result Channel n

Note 1: The CHH<13:11> bits are not implemented in 20-pin devices.

2: The CHH<13:12> bits are not implemented in 28-pin devices.

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NOTES:

DS60001324C-page 148

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The 32-bit programmable CRC generator provides a

hardware implemented method of quickly generating

checksums for various networking and security

applications. It offers the following features:

17.0 32-BIT PROGRAMMABLE

CYCLIC REDUNDANCY CHECK

(CRC) GENERATOR

• User-Programmable CRC Polynomial Equation,

up to 32 Bits

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

devices. It is not intended to be a compre-

hensive reference source. To complement

the information in this data sheet, refer to

Section 60. “32-Bit Programmable Cyclic

Redundancy Check” (DS60001336) in the

“PIC32 Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32). The informa-

tion in this data sheet supersedes the

information in the FRM.

• Programmable Shift Direction (little or big-endian)

• Independent Data and Polynomial Lengths

• Configurable Interrupt Output

• Data FIFO

Figure 17-1 displays a simplified block diagram of the

CRC generator.

FIGURE 17-1:

CRC BLOCK DIAGRAM

CRCDAT

FIFO Empty

Variable FIFO

(4x32, 8x16 or 16x8)

Event

CRCISEL

1

0

CRCWDAT

CRC

Interrupt

LENDIAN

1

0

Shift Buffer

CRC Shift Engine

Shift

Complete

Event

Shifter Clock

PBCLK

(1:1 with SYSCLK)

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REGISTER 17-1: CRCCON: CRC CONTROL REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5

28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

R/W-0

DWIDTH<4:0>

R/W-0

31:24

23:16

15:8

7:0

U-0

R/W-0

—

PLEN<4:0>

R-0, HS, HC

VWORD<4:0>

R/W-0

U-0

—

R/W-0

SIDL

R/W-0

CRCISEL

R-0, HS, HC

ON

R-0, HS, HC R-1, HS, HC

R/W-0

U-0

CRCFUL CRCMPT

CRCGO

LENDIAN

MOD

—

Legend:

HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as ‘0’

bit 28-24 DWIDTH<4:0>: Data Word Width Configuration bits

Configures the width of the data word (Data Word Width – 1).

bit 23-21 Unimplemented: Read as ‘0’

bit 20-16 PLEN<4:0>: Polynomial Length Configuration bits

Configures the length of the polynomial (Polynomial Length – 1).

bit 15

ON: CRC Enable bit

1= Enables module

0= Disables module

bit 14

bit 13

Unimplemented: Read as ‘0’

SIDL: CRC Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

bit 12-8 VWORD<4:0>: Counter Value bits

Indicates the number of valid words in the FIFO. Has a maximum value of 16 when DWIDTH<4:0> < (data words,

8-bit wide or less). Has a maximum value of 8 when DWIDTH<4:0> < 15 (data words from 9 to 16-bit wide). Has

a maximum value of 4 when DWIDTH<4:0> < 31 (data words from 17 to 32-bit wide).

bit 7

bit 6

bit 5

bit 4

bit 3

CRCFUL: CRC FIFO Full bit

1= FIFO is full

0= FIFO is not full

CRCMPT: CRC FIFO Empty bit

1= FIFO is empty

0= FIFO is not empty

CRCISEL: CRC Interrupt Selection bit

1= Interrupt on FIFO is empty; final word of data is still shifted through CRC

0= Interrupt on shift is complete (FIFO is empty and no data is shifted from the shift buffer)

CRCGO: Start CRC bit

1= Starts CRC serial shifter; clearing the bit aborts shifting

0= CRC serial shifter is turned off

LENDIAN: Data Word Little-Endian Configuration bit

1= Data word is shifted into the CRC, starting with the LSb (little-endian); reflected input data

0= Data word is shifted into the CRC, starting with the MSb (big-endian); non-reflected input data

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REGISTER 17-1: CRCCON: CRC CONTROL REGISTER (CONTINUED)

bit 2

MOD: CRC Calculation Mode bit

1= Alternate mode

0= Legacy mode

bit 1-0

Unimplemented: Read as ‘0’

REGISTER 17-2: CRCXOR:CRC XOR REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

R/W-0

31:24

23:16

15:8

7:0

X<31:24>

R/W-0

X<23:16>

R/W-0

X<15:8>

R/W-0

U-0

X<7:1>

—

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

n

bit 31-1 X<31:1>: XOR of Polynomial Term X Enable bits

bit 0

Unimplemented: Read as ‘0’

DS60001324C-page 152

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The Configurable Logic Cell (CLC) module allows the

18.0 CONFIGURABLE LOGIC CELL

(CLC)

user to specify combinations of signals as inputs to a

logic function and to use the logic output to control

other peripherals or I/O pins. This provides greater flex-

ibility and potential in embedded designs since the CLC

module can operate outside the limitations of software

execution, and supports a vast amount of output

designs.

Note:

This data sheet summarizes the features of

the PIC32MM0064GPL036 family of

devices. It is not intended to be a compre-

hensive reference source. To complement

the information in this data sheet, refer to

Section 36. “Configurable Logic Cell”

(DS60001363) in the “PIC32 Family Refer-

ence Manual”, which is available from the

Microchip web site (www.microchip.com/

PIC32). The information in this data sheet

supersedes the information in the FRM.

There are four input gates to the selected logic func-

tion. These four input gates select from a pool of up to

32 signals that are selected using four data source

selection multiplexers. Figure 18-1 shows an overview

of the module. Figure 18-3 shows the details of the data

source multiplexers and logic input gate connections.

FIGURE 18-1:

CLCx MODULE

CLCIN[0]

CLCIN[1]

CLCIN[2]

CLCIN[3]

CLCIN[4]

CLCIN[5]

CLCIN[6]

CLCIN[7]

CLCIN[8]

CLCIN[9]

CLCIN[10]

CLCIN[11]

CLCIN[12]

CLCIN[13]

CLCIN[14]

CLCIN[15]

CLCIN[16]

CLCIN[17]

CLCIN[18]

CLCIN[19]

CLCIN[20]

CLCIN[21]

CLCIN[22]

CLCIN[23]

CLCIN[24]

CLCIN[25]

CLCIN[26]

CLCIN[27]

CLCIN[28]

CLCIN[29]

CLCIN[30]

CLCIN[31]

See Figure 18-2

LCOE

ON

Gate 1

Gate 2

Gate 3

Gate 4

CLCx

Output

Logic

CLCx

Logic

Output

Function

LCPOL

Interrupt

det

MODE<2:0>

INTP

INTN

Sets

CLCxIF

Flag

Interrupt

det

See Figure 18-3

Note:

All register bits shown in this figure can be found in the CLCxCON register.



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FIGURE 18-2:

CLCx LOGIC FUNCTION COMBINATORIAL OPTIONS

AND – OR

OR – XOR

Gate 1

Gate 2

Gate 3

Gate 4

Gate 1

Gate 2

Gate 3

Gate 4

Logic Output

MODE<2:0> = 000

MODE<2:0> = 001

4-Input AND

S-R Latch

Gate 1

Gate 2

Gate 3

Gate 4

Logic Output

S

R

Q

Gate 2

Gate 3

Gate 4

Logic Output

MODE<2:0> = 011

MODE<2:0> = 010

1-Input D Flip-Flop with S and R

2-Input D Flip-Flop with R

Gate 4

Gate 2

D

Q

Logic Output

S

R

Logic Output

Gate 2

Gate 1

Gate 3

D

Q

Gate 1

Gate 3

R

MODE<2:0> = 101

MODE<2:0> = 100

J-K Flip-Flop with R

1-Input Transparent Latch with S and R

Gate 4

Gate 2

Gate 1

Gate 4

Gate 3

J

Q

Logic Output

S

Gate 2

Gate 1

Gate 3

D

Q

Logic Output

K

R

LE

R

MODE<2:0> = 110

MODE<2:0> = 111

DS60001324C-page 154

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FIGURE 18-3:

CLCx INPUT SOURCE SELECTION DIAGRAM

Data Selection

000

CLCIN[0]

CLCIN[1]

CLCIN[2]

CLCIN[3]

CLCIN[4]

CLCIN[5]

CLCIN[6]

CLCIN[7]

Data Gate 1

Data 1 Non-Inverted

G1D1T

G1D1N

G1D2T

Data 1

Inverted

111

000

DS1x (CLCxSEL<2:0>)

G1D2N

G1D3T

G1D3N

G1D4T

Gate 1

CLCIN[8]

CLCIN[9]

G1POL

(CLCxCON<16>)

CLCIN[10]

CLCIN[11]

CLCIN[12]

CLCIN[13]

CLCIN[14]

CLCIN[15]

Data 2 Non-Inverted

Data 2

Inverted

111

000

G1D4N

DS2x (CLCxSEL<6:4>)

CLCIN[16]

CLCIN[17]

CLCIN[18]

CLCIN[19]

CLCIN[20]

CLCIN[21]

CLCIN[22]

CLCIN[23]

Data Gate 2

Gate 2

Gate 3

Gate 4

Data 3 Non-Inverted

(Same as Data Gate 1)

Data Gate 3

Data 3

Inverted

111

000

DS3x (CLCxSEL<10:8>)

(Same as Data Gate 1)

Data Gate 4

CLCIN[24]

CLCIN[25]

CLCIN[26]

CLCIN[27]

CLCIN[28]

CLCIN[29]

CLCIN[30]

CLCIN[31]

(Same as Data Gate 1)

Data 4 Non-Inverted

Data 4

Inverted

111

DS4x (CLCxSEL<14:12>)

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The CLCx Input MUX Select register (CLCxSEL)

18.1 Control Registers

allows the user to select up to 4 data input sources

using the 4 data input selection multiplexers. Each

multiplexer has a list of 8 data sources available.

The CLCx module is controlled by the following registers:

• CLCxCON

• CLCxSEL

• CLCxGLS

The CLCx Gate Logic Input Select register (CLCxGLS)

allows the user to select which outputs from each of the

selection MUXes are used as inputs to the input gates

of the logic cell. Each data source MUX outputs both a

true and a negated version of its output. All of these

8 signals are enabled, ORed together by the logic cell

input gates.

The CLCx Control register (CLCxCON) is used to

enable the module and interrupts, control the output

enable bit, select output polarity and select the logic

function. The CLCx Control registers also allow the user

to control the logic polarity of not only the cell output, but

also some intermediate variables.

DS60001324C-page 156

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REGISTER 18-1: CLCxCON: CLCx CONTROL REGISTER

Bit

Range 31/23/15/7 30/22/14/6

29/21/13/5

28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

U-0

R/W-0

G4POL

R/W-0

G3POL

R/W-0

G1POL

U-0

—

G2POL

U-0

R/W-0

U-0

—

(1)

ON

—

INTP

INTN

—

R/W-0

LCOE

R-0, HS, HC

R/W-0

U-0

R/W-0

LCOUT

LCPOL

—

MODE<2:0>

Legend:

HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-20 Unimplemented: Read as ‘0’

bit 19

bit 18

bit 17

bit 16

bit 15

G4POL: Gate 4 Polarity Control bit

1= The output of Channel 4 logic is inverted when applied to the logic cell

0= The output of Channel 4 logic is not inverted

G3POL: Gate 3 Polarity Control bit

1= The output of Channel 3 logic is inverted when applied to the logic cell

0= The output of Channel 3 logic is not inverted

G2POL: Gate 2 Polarity Control bit

1= The output of Channel 2 logic is inverted when applied to the logic cell

0= The output of Channel 2 logic is not inverted

G1POL: Gate 1 Polarity Control bit

1= The output of Channel 1 logic is inverted when applied to the logic cell

0= The output of Channel 1 logic is not inverted

ON: CLCx Enable bit

1= CLCx is enabled and mixing input signals

0= CLCx is disabled and has logic zero outputs

bit 14-12 Unimplemented: Read as ‘0’

(1)

bit 11

INTP: CLCx Positive Edge Interrupt Enable bit

1= Interrupt will be generated when a rising edge occurs on LCOUT

0= Interrupt will not be generated

(1)

bit 10

INTN: CLCx Negative Edge Interrupt Enable bit

1= Interrupt will be generated when a falling edge occurs on LCOUT

0= Interrupt will not be generated

bit 9-8

bit 7

Unimplemented: Read as ‘0’

LCOE: CLCx Port Enable bit

1= CLCx port pin output is enabled

0= CLCx port pin output is disabled

bit 6

LCOUT: CLCx Data Output Status bit

1= CLCx output high

0= CLCx output low

Note 1: The INTP and INTN bits should not be set at the same time for proper interrupt functionality.

DS60001324C-page 158

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REGISTER 18-1: CLCxCON: CLCx CONTROL REGISTER (CONTINUED)

bit 5

LCPOL: CLCx Output Polarity Control bit

1= The output of the module is inverted

0= The output of the module is not inverted

bit 4-3

bit 2-0

Unimplemented: Read as ‘0’

MODE<2:0>: CLCx Mode bits

111= Cell is a 1-input transparent latch with S and R

110= Cell is a JK flip-flop with R

101= Cell is a 2-input D flip-flop with R

100= Cell is a 1-input D flip-flop with S and R

011= Cell is an SR latch

010= Cell is a 4-input AND

001= Cell is an OR-XOR

000= Cell is a AND-OR

Note 1: The INTP and INTN bits should not be set at the same time for proper interrupt functionality.



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REGISTER 18-2: CLCxSEL: CLCx INPUT MUX SELECT REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

U-0

—

U-0

—

R/W-0

U-0

—

R/W-0

DS4<2:0>

R/W-0

DS3<2:0>

R/W-0

U-0

R/W-0

U-0

R/W-0

—

DS2<2:0>

—

DS1<2:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-15 Unimplemented: Read as ‘0’

bit 14-12 DS4<2:0>: Data Selection MUX 4 Signal Selection bits

For CLC1:

111= SCCP3 compare match event

110= MCCP1 compare match event

101= RTCC event

100= Reserved

011= SPI1 SDI input

010= SCCP3 OCM3 output

001= CLC2 output

000= CLCINB I/O pin

For CLC2:

111= SCCP3 compare match event

110= MCCP1 compare match event

101= RTCC event

100= Reserved

011= SPI2 SDI input

010= SCCP3 OCM3 output

001= CLC1 output

000= CLCINB I/O pin

bit 11

Unimplemented: Read as ‘0’

DS60001324C-page 160

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REGISTER 18-2: CLCxSEL: CLCx INPUT MUX SELECT REGISTER (CONTINUED)

bit 10-8 DS3<2:0>: Data Selection MUX 3 Signal Selection bits

For CLC1:

111= SCCP3 compare match event

110= SCCP2 compare match event

101= SCCP2 OCM2 output

100= UART1 RX input

011= SPI1 SDO output

010= Comparator 2 output

001= CLC1 output

000= CLCINA I/O pin

For CLC2:

111= SCCP3 compare match event

110= SCCP2 compare match event

101= SCCP2 OCM2 output

100= UART2 RX input

011= SPI2 SDO output

010= Comparator 2 output

001= CLC2 output

000= CLCINA I/O pin

bit 7

Unimplemented: Read as ‘0’

bit 6-4

DS2<2:0>: Data Selection MUX 2 Signal Selection bits

For CLC1:

111= Reserved

110= MCCP1 compare match event

101= Reserved

100= ADC End-of-Conversion (EOC) event

011= UART1 TX output

010= Comparator 1 output

001= CLC2 output

000= CLCINB I/O pin

For CLC2:

111= Reserved

110= MCCP1 compare match event

101= Reserved

100= ADC End-of-Conversion event

011= UART2 TX output

010= Comparator 1 output

001= CLC1 output

000= CLCINB I/O pin

bit 3

Unimplemented: Read as ‘0’

bit 2-0

DS1<2:0>: Data Selection MUX 1 Signal Selection bits

111= MCCP1 OCM1C output

110= MCCP1 OCM1B output

101= MCCP1 OCM1A output

100= REFCLKO output

011= LPRC clock source

010= SOSC clock source

001= System clock (FSYS

)

000= CLCINA I/O pin



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REGISTER 18-3: CLCxGLS: CLCx GATE LOGIC INPUT SELECT REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

R/W-0

G4D4T

R/W-0

G4D4N

R/W-0

G4D3T

R/W-0

G4D3N

R/W-0

G4D2T

R/W-0

G4D2N

R/W-0

G4D1T

R/W-0

G4D1N

R/W-0

31:24

23:16

15:8

7:0

G3D4T

R/W-0

G3D4N

R/W-0

G3D3T

R/W-0

G3D3N

R/W-0

G3D2T

R/W-0

G3D2N

R/W-0

G3D1T

R/W-0

G3D1N

R/W-0

G2D4T

R/W-0

G2D4N

R/W-0

G2D3T

R/W-0

G2D3N

R/W-0

G2D2T

R/W-0

G2D2N

R/W-0

G2D1T

R/W-0

G2D1N

R/W-0

G1D4T

G1D4N

G1D3T

G1D3N

G1D2T

G1D2N

G1D1T

G1D1N

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31

bit 30

bit 29

bit 28

bit 27

bit 26

bit 25

bit 24

bit 23

bit 22

bit 21

G4D4T: Gate 4 Data Source 4 True Enable bit

1= The Data Source 4 signal is enabled for Gate 4

0= The Data Source 4 signal is disabled for Gate 4

G4D4N: Gate 4 Data Source 4 Negated Enable bit

1= The Data Source 4 inverted signal is enabled for Gate 4

0= The Data Source 4 inverted signal is disabled for Gate 4

G4D3T: Gate 4 Data Source 3 True Enable bit

1= The Data Source 3 signal is enabled for Gate 4

0= The Data Source 3 signal is disabled for Gate 4

G4D3N: Gate 4 Data Source 3 Negated Enable bit

1= The Data Source 3 inverted signal is enabled for Gate 4

0= The Data Source 3 inverted signal is disabled for Gate 4

G4D2T: Gate 4 Data Source 2 True Enable bit

1= The Data Source 2 signal is enabled for Gate 4

0= The Data Source 2 signal is disabled for Gate 4

G4D2N: Gate 4 Data Source 2 Negated Enable bit

1= The Data Source 2 inverted signal is enabled for Gate 4

0= The Data Source 2 inverted signal is disabled for Gate 4

G4D1T: Gate 4 Data Source 1 True Enable bit

1= The Data Source 1 signal is enabled for Gate 4

0= The Data Source 1 signal is disabled for Gate 4

G4D1N: Gate 4 Data Source 1 Negated Enable bit

1= The Data Source 1 inverted signal is enabled for Gate 4

0= The Data Source 1 inverted signal is disabled for Gate 4

G3D4T: Gate 3 Data Source 4 True Enable bit

1= The Data Source 4 signal is enabled for Gate 3

0= The Data Source 4 signal is disabled for Gate 3

G3D4N: Gate 3 Data Source 4 Negated Enable bit

1= The Data Source 4 inverted signal is enabled for Gate 3

0= The Data Source 4 inverted signal is disabled for Gate 3

G3D3T: Gate 3 Data Source 3 True Enable bit

1= The Data Source 3 signal is enabled for Gate 3

0= The Data Source 3 signal is disabled for Gate 3

DS60001324C-page 162

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REGISTER 18-3: CLCxGLS: CLCx GATE LOGIC INPUT SELECT REGISTER (CONTINUED)

bit 20

bit 19

bit 18

bit 17

bit 16

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

G3D3N: Gate 3 Data Source 3 Negated Enable bit

1= The Data Source 3 inverted signal is enabled for Gate 3

0= The Data Source 3 inverted signal is disabled for Gate 3

G3D2T: Gate 3 Data Source 2 True Enable bit

1= The Data Source 2 signal is enabled for Gate 3

0= The Data Source 2 signal is disabled for Gate 3

G3D2N: Gate 3 Data Source 2 Negated Enable bit

1= The Data Source 2 inverted signal is enabled for Gate 3

0= The Data Source 2 inverted signal is disabled for Gate 3

G3D1T: Gate 3 Data Source 1 True Enable bit

1= The Data Source 1 signal is enabled for Gate 3

0= The Data Source 1 signal is disabled for Gate 3

G3D1N: Gate 3 Data Source 1 Negated Enable bit

1= The Data Source 1 inverted signal is enabled for Gate 3

0= The Data Source 1 inverted signal is disabled for Gate 3

G2D4T: Gate 2 Data Source 4 True Enable bit

1= The Data Source 4 signal is enabled for Gate 2

0= The Data Source 4 signal is disabled for Gate 2

G2D4N: Gate 2 Data Source 4 Negated Enable bit

1= The Data Source 4 inverted signal is enabled for Gate 2

0= The Data Source 4 inverted signal is disabled for Gate 2

G2D3T: Gate 2 Data Source 3 True Enable bit

1= The Data Source 3 signal is enabled for Gate 2

0= The Data Source 3 signal is disabled for Gate 2

G2D3N: Gate 2 Data Source 3 Negated Enable bit

1= The Data Source 3 inverted signal is enabled for Gate 2

0= The Data Source 3 inverted signal is disabled for Gate 2

G2D2T: Gate 2 Data Source 2 True Enable bit

1= The Data Source 2 signal is enabled for Gate 2

0= The Data Source 2 signal is disabled for Gate 2

G2D2N: Gate 2 Data Source 2 Negated Enable bit

1= The Data Source 2 inverted signal is enabled for Gate 2

0= The Data Source 2 inverted signal is disabled for Gate 2

G2D1T: Gate 2 Data Source 1 True Enable bit

1= The Data Source 1 signal is enabled for Gate 2

0= The Data Source 1 signal is disabled for Gate 2

bit 8

G2D1N: Gate 2 Data Source 1 Negated Enable bit

1= The Data Source 1 inverted signal is enabled for Gate 2

0= The Data Source 1 inverted signal is disabled for Gate 2

bit 7

G1D4T: Gate 1 Data Source 4 True Enable bit

1= The Data Source 4 signal is enabled for Gate 1

0= The Data Source 4 signal is disabled for Gate 1

bit 6

G1D4N: Gate 1 Data Source 4 Negated Enable bit

1= The Data Source 4 inverted signal is enabled for Gate 1

0= The Data Source 4 inverted signal is disabled for Gate 1

bit 5

G1D3T: Gate 1 Data Source 3 True Enable bit

1= The Data Source 3 signal is enabled for Gate 1

0= The Data Source 3 signal is disabled for Gate 1



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REGISTER 18-3: CLCxGLS: CLCx GATE LOGIC INPUT SELECT REGISTER (CONTINUED)

bit 4

bit 3

bit 2

bit 1

bit 0

G1D3N: Gate 1 Data Source 3 Negated Enable bit

1= The Data Source 3 inverted signal is enabled for Gate 1

0= The Data Source 3 inverted signal is disabled for Gate 1

G1D2T: Gate 1 Data Source 2 True Enable bit

1= The Data Source 2 signal is enabled for Gate 1

0= The Data Source 2 signal is disabled for Gate 1

G1D2N: Gate 1 Data Source 2 Negated Enable bit

1= The Data Source 2 inverted signal is enabled for Gate 1

0= The Data Source 2 inverted signal is disabled for Gate 1

G1D1T: Gate 1 Data Source 1 True Enable bit

1= The Data Source 1 signal is enabled for Gate 1

0= The Data Source 1 signal is disabled for Gate 1

G1D1N: Gate 1 Data Source 1 Negated Enable bit

1= The Data Source 1 inverted signal is enabled for Gate 1

0= The Data Source 1 inverted signal is disabled for Gate 1

DS60001324C-page 164

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The comparator module provides two dual input

comparators. The inputs to the comparator can be

19.0 COMPARATOR

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

configured to use any one of five external analog inputs

(CxINA, CxINB, CxINC, CxIND and VREF+). The

comparator outputs may be directly connected to the

CxOUT pins. When the respective COE bit equals ‘1’,

the I/O pad logic makes the unsynchronized output of

the comparator available on the pin.

devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to Section 19. “Comparator”

(DS60001110) in the “PIC32 Family Refer-

ence Manual”, which is available from the

Microchip web site (www.microchip.com/

PIC32). The information in this data sheet

supersedes the information in the FRM.

A simplified block diagram of the module is shown in

Figure 19-1. Each comparator has its own control

register, CMxCON (Register 19-2), for enabling and

configuring its operation. The output and event status

of two comparators is provided in the CMSTAT register

(Register 19-1).

FIGURE 19-1:

DUAL COMPARATOR MODULE BLOCK DIAGRAM

EVPOL<1:0>

CCH<1:0>

CEVT

COUT

CEVT

COUT

Trigger/Interrupt

Logic

Input

Select

Logic

CPOL

COE

V

IN

-

C1

00

01

10

11

V

+

CxINB

C1OUT

(1)

CxINC

–

(1)

CxIND

EVPOL<1:0>

Band Gap

Trigger/Interrupt

Logic

CPOL

COE

V

IN

-

C2

V

+

C2OUT

0

1

CxINA

+

0

1

CDAC1 Output

V

REF+ Pin

CVREFSEL

CREF

Note 1: This input is not available for Comparator 2.



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REGISTER 19-1: CMSTAT: COMPARATOR MODULE STATUS REGISTER

Bit

Range 31/23/15/7 30/22/14/6

29/21/13/5

28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

R-0, HS, HC

C2EVT

U-0

R-0, HS, HC

C1EVT

R/W-0

—

U-0

—

U-0

—

R/W-0

SIDL

U-0

—

U-0

—

U-0

—

CVREFSEL

R-0, HS, HC

C1OUT

U-0

R-0, HS, HC

—

C2OUT

Legend:

HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-18 Unimplemented: Read as ‘0’

bit 17

C2EVT: Comparator 2 Event Status bit (read-only)

Shows the current event status of Comparator 2 (CM2CON<9>).

bit 16

C1EVT: Comparator 1 Event Status bit (read-only)

Shows the current event status of Comparator 1 (CM1CON<9>).

bit 15-14 Unimplemented: Read as ‘0’

bit 13

SIDL: Comparator Stop in Idle Mode bit

1= Discontinues operation of all comparators when device enters Idle mode

0= Continues operation of all enabled comparators in Idle mode

bit 12-9 Unimplemented: Read as ‘0’

bit 8

CVREFSEL: Comparator Reference Voltage Select Enable bit

1= External voltage reference from the VREF+ pin is selected

0= Voltage from CDAC1 is selected

bit 7-2

bit 1

Unimplemented: Read as ‘0’

C2OUT: Comparator 2 Output Status bit (read-only)

Shows the current output of Comparator 2 (CM2CON<8>).

C1OUT: Comparator 1 Output Status bit (read-only)

Shows the current output of Comparator 1 (CM1CON<8>).

bit 0

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REGISTER 19-2: CMxCON: COMPARATOR x CONTROL REGISTERS 

(COMPARATORS 1 AND 2)

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5

28/20/12/4

27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

—

R/W-0

ON

R/W-0

COE

R/W-0

CPOL

U-0

—

U-0

—

R-0, HS, HC

CEVT

R/W-0

R-0, HS, HC

COUT

R/W-0

—

R/W-0

U-0

EVPOL<1:0>

—

CREF

—

CCH<1:0>

Legend:

HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15

bit 14

bit 13

ON: Comparator Enable bit

1= Comparator is enabled

0= Comparator is disabled

COE: Comparator Output Enable bit

1= Comparator output is present on the CxOUT pin

0= Comparator output is internal only

CPOL: Comparator Output Polarity Select bit

1= Comparator output is inverted

0= Comparator output is not inverted

bit 12-10 Unimplemented: Read as ‘0’

bit 9

CEVT: Comparator Event bit

1= Comparator event that is defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are

disabled until the bit is cleared

0= Comparator event has not occurred

bit 8

COUT: Comparator Output bit

When CPOL = 0:

1= VIN+ > VIN

0= VIN+ < VIN

-

When CPOL = 1:

1= VIN+ < VIN

0= VIN+ > VIN

-

DS60001324C-page 168

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REGISTER 19-2: CMxCON: COMPARATOR x CONTROL REGISTERS 

(COMPARATORS 1 AND 2) (CONTINUED)

bit 7-6

EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits

11= Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)

10= Trigger/event/interrupt is generated on transition of the comparator output:

If CPOL = 0(non-inverted polarity):

High-to-low transition only.

If CPOL = 1(inverted polarity):

Low-to-high transition only.

01= Trigger/event/interrupt is generated on transition of the comparator output:

If CPOL = 0(non-inverted polarity):

Low-to-high transition only.

If CPOL = 1(inverted polarity):

High-to-low transition only.

00= Trigger/event/interrupt generation is disabled

Unimplemented: Read as ‘0’

bit 5

bit 4

CREF: Comparator Reference Select bit (non-inverting input)

1= Non-inverting input connects to the internal reference defined by the CVREFSEL bit in the CMSTAT register

0= Non-inverting input connects to the CxINA pin

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

CCH<1:0>: Comparator Channel Select bits

11= Inverting input of the comparator connects to the band gap reference voltage

10= Inverting input of the comparator connects to the CxIND pin

01= Inverting input of the comparator connects to the CxINC pin

00= Inverting input of the comparator connects to the CxINB pin



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NOTES:

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The Control Digital-to-Analog Converter (CDAC)

generates analog voltage corresponding to the digital

input.

20.0 CONTROL 

DIGITAL-TO-ANALOG

CONVERTER (CDAC)

The CDAC has the following features:

Note:

This data sheet summarizes the

features of the PIC32MM0064GPL036

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 45. “Control

Digital-to-Analog Converter (CDAC)”

(DS60001327) in the “PIC32 Family

Reference Manual”, which is available

• 32 Output Levels are Available

• Internally Connected to Comparators to Conserve

Device Pins

• Output can be Connected to a Pin

A block diagram of the CDAC module is illustrated in

Figure 20-1.

from

the

Microchip

web

site

(www.microchip.com/PIC32). The infor-

mation in this data sheet supersedes

the information in the FRM.

FIGURE 20-1:

CDAC BLOCK DIAGRAM

REFSEL<1:0>

VREF+

AVDD

DACDAT<4:0>

R

Output to

Comparators

32 Steps

CDAC1

DACOE

R

AVSS



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REGISTER 20-1: DAC1CON: CDAC CONTROL REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5

28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

R/W-0

—

DACDAT<4:0>

R/W-0

ON

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

DACOE

R/W-0

—

U-0

—

R/W-0

—

REFSEL<1:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-21 Unimplemented: Read as ‘0’

bit 20-16 DACDAT<4:0>: CDAC Voltage Reference Selection bits

11111= (DACDAT<4:0> * VREF+/32) or (DACDAT<4:0> * AVDD/32) volts depending on the REFSEL<1:0> bits

•

00000= 0.0 volts

bit 15

ON: Voltage Reference Enable bit

1= Voltage reference is enabled

0= Voltage reference is disabled

bit 14-9 Unimplemented: Read as ‘0’

bit 8

DACOE: CDAC Voltage Reference Output Enable bit

1= Voltage level is output on the CDAC1 pin

0= Voltage level is disconnected from the CDAC1 pin

bit 7-2

bit 1-0

Unimplemented: Read as ‘0’

REFSEL<1:0>: CDAC Voltage Reference Source Select bits

11= Reference voltage is AVDD

10= No reference is selected – output is AVSS

01= Reference voltage is the VREF+ input pin voltage

00= No reference is selected – output is AVSS



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NOTES:

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The HLVD Control register (see Register 21-1)

21.0 HIGH/LOW-VOLTAGE DETECT

completely controls the operation of the HLVD module.

This allows the circuitry to be “turned off” by the user

under software control, which minimizes the current

consumption for the device.

(HLVD)

The High/Low-Voltage Detect (HLVD) module is a

programmable circuit that allows the user to specify

both the device voltage trip point and the direction of

change.

An interrupt flag is set if the device experiences an

excursion past the trip point in the direction of change.

If the interrupt is enabled, the program execution will

branch to the interrupt vector address and the software

can then respond to the interrupt.

FIGURE 21-1:

HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM

Externally Generated

Trip Point

VDD

V

DD

HLVDL<3:0>

LVDIN

ON VDIR

Set

HLVDIF

Band Gap

1.2V Typical

ON



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REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5

28/20/12/4

27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

R/W-0

ON

U-0

—

U-0

—

R/W-0

SIDL

U-0

R/W-0

VDIR

R/W-0

R-0, HS, HC

BGVST

R/W-0

R-0, HS, HC R-0, HS, HC

—

IRVST

HLEVT

U-0

—

R/W-0

—

HLVDL<3:0>

Legend:

HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15

ON: HLVD Power Enable bit

1= HLVD is enabled

0= HLVD is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

SIDL: HLVD Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

bit 12

bit 11

Unimplemented: Read as ‘0’

VDIR: Voltage Change Direction Select bit

1= Event occurs when voltage equals or exceeds the trip point (HLVDL<3:0>)

0= Event occurs when voltage equals or falls below the trip point (HLVDL<3:0>)

bit 10

bit 9

BGVST: Band Gap Voltage Stable Flag bit

1= Indicates that the band gap voltage is stable

0= Indicates that the band gap voltage is unstable

IRVST: Internal Reference Voltage Stable Flag bit

1= Internal reference voltage is stable; the High-Voltage Detect logic generates the interrupt flag at the

specified voltage range

0= Internal reference voltage is unstable; the High-Voltage Detect logic will not generate the interrupt flag

at the specified voltage range and the HLVD interrupt should not be enabled

bit 8

HLEVT: High/Low-Voltage Detection Event Status bit

1= Indicates HLVD event is active

0= Indicates HLVD event is not active

bit 7-4

Unimplemented: Read as ‘0’

Note 1: The voltage is typical. It is for design guidance only and not tested. Refer to Table 26-13 in Section 26.0

“Electrical Characteristics” for minimum and maximum values.



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REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER (CONTINUED)

bit 3-0

HLVDL<3:0>: High/Low-Voltage Detection Limit bits

1111= External analog input is used (input comes from the LVDIN pin and is compared with 1.2V band gap)

(1)

1110= VDD trip point is 2.11V

(1)

1101= VDD trip point is 2.21V

(1)

1100= VDD trip point is 2.30V

(1)

1011= VDD trip point is 2.40V

(1)

1010= VDD trip point is 2.52V

(1)

1001= VDD trip point is 2.63V

(1)

1000= VDD trip point is 2.82V

(1)

0111= VDD trip point is 2.92V

(1)

0110= VDD trip point is 3.13V

(1)

0101= VDD trip point is 3.44V

0100-0000= Reserved; do not use

Note 1: The voltage is typical. It is for design guidance only and not tested. Refer to Table 26-13 in Section 26.0

“Electrical Characteristics” for minimum and maximum values.

DS60001324C-page 178

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The processor will exit, or “wake-up”, from Sleep on

one of the following events:

22.0 POWER-SAVING FEATURES

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to Section 10. “Power-Saving

Modes” (DS60001130) in the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32). The infor-

mation in this data sheet supersedes the

information in the FRM.

• On any interrupt from an enabled source that is

operating in Sleep. The interrupt priority must be

greater than the current CPU priority.

• On any form of device Reset.

• On a WDT time-out.

If the interrupt priority is lower than, or equal to, the

current priority, the CPU will remain halted, but the

Peripheral Bus Clock (PBCLK) will start running and

the device will enter into Idle mode. To set or clear the

SLPEN bit, an unlock sequence must be executed.

Refer to Section 23.4 “System Registers Write

Protection” for details.

This section describes power-saving features for the

PIC32MM0064GPL036 family devices. These devices

offer various methods and modes that allow the appli-

cation to balance power consumption with device

performance. In all of the methods and modes

described in this section, power saving is controlled by

software. The peripherals and CPU can be halted or

disabled to reduce power consumption.

22.2 Idle Mode

In Idle mode, the CPU is halted; however, all clocks are

still enabled. This allows peripherals to continue to

operate. Peripherals can be individually configured to

halt when entering Idle by setting their respective SIDL

bit. Latency, when exiting Idle mode, is very low due to

the CPU oscillator source remaining active.

22.1 Sleep Mode

The device enters Idle mode when the SLPEN bit

(OSCCON<4>) is clear and a WAIT instruction is

executed.

In Sleep mode, the CPU and most peripherals are

halted, and the associated clocks are disabled. Some

peripherals can continue to operate in Sleep mode and

can be used to wake the device from Sleep. See the

individual peripheral module sections for descriptions

of behavior in Sleep. The device enters Sleep mode

when the SLPEN bit (OSCCON<4>) is set and a WAIT

instruction is executed.

The processor will wake or exit from Idle mode on the

following events:

• On any interrupt event for which the interrupt

source is enabled. The priority of the interrupt

event must be greater than the current priority of

the CPU. If the priority of the interrupt event is

lower than, or equal to, the current priority of the

CPU, the CPU will remain halted and the device

will remain in Idle mode.

Sleep mode includes the following characteristics:

• There can be a wake-up delay based on the

oscillator selection.

• The Fail-Safe Clock Monitor (FSCM) does not

operate during Sleep mode.

• On any form of device Reset.

• On a WDT time-out interrupt.

• The BOR circuit remains operative during Sleep mode.

To set or clear the SLPEN bit, an unlock sequence

must be executed. Refer to Section 23.4 “System

Registers Write Protection” for details.

• If WDT is enabled, the Run mode counter is not

cleared upon entry to Sleep and the Sleep mode

counter is reset upon entering Sleep.

• Some peripherals can continue to operate at

limited functionality in Sleep mode. These periph-

erals include I/O pins that detect a change in the

input signal, WDT, ADC, UART and peripherals

that use an external clock input or the internal

LPRC oscillator (e.g., RTCC and Timer1).

• I/O pins continue to sink or source current in the same

manner as they do when the device is not in Sleep.

• The on-chip regulator enters Standby mode if the

VREGS bit (PWRCON<0>) is set.

• A separate special low-power, low-voltage/

retention regulator is activated if the RETVR 

Configuration bit (FPOR<2>) is programmed to

zero and the RETEN bit (PWRCON<1>) is set.



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To prevent accidental configuration changes under

22.3 Peripheral Module Disable

normal operation, writes to the PMDx registers are not

allowed. Attempted writes appear to execute normally,

but the contents of the registers remain unchanged. To

change these registers, they must be unlocked in

hardware. The register lock is controlled by the

PMDLOCK bit in PMDCON register (PMDCON<11>).

Setting PMDLOCK prevents writes to the control

registers; clearing PMDLOCK allows writes. To set or

clear PMDLOCK, an unlock sequence must be

executed. Refer to Section 23.4 “System Registers

Write Protection” for details.

The Peripheral Module Disable (PMD) registers

provide a method to disable a peripheral module by

stopping all clock sources supplied to that module.

When a peripheral is disabled using the appropriate

PMD control bit, the peripheral is in a minimum power

consumption state. The control and status registers

associated with the peripheral are also disabled, so

writes to those registers do not take effect and read

values are invalid.

To disable a peripheral, the associated PMDx bit must

be set to ‘1’. To enable a peripheral, the associated

PMDx bit must be cleared (default).

Table 22-1 lists the module disable bits and locations

for all modules.

TABLE 22-1: PERIPHERAL MODULE DISABLE BITS AND LOCATIONS

Peripheral

PMDx Bit Name

Register Name and Bit Location

Analog-to-Digital Converter (ADC)

Voltage Reference (VR)

ADCMD

VREFMD

HLVDMD

CMP1MD

CMP2MD

CLC1MD

CLC2MD

CCP1MD

PMD1<0>

PMD1<12>

PMD1<20>

PMD2<0>

PMD2<1>

PMD2<24>

PMD2<25>

PMD3<8>

High/Low-Voltage Detect (HLVD)

Comparator 1 (CMP1)

Comparator 2 (CMP2)

Configurable Logic Cell 1 (CLC1)

Configurable Logic Cell 2 (CLC2)

Multiple Outputs Capture/Compare/PWM/

Timer1 (MCCP1)

Single Output Capture/Compare/PWM/Timer2

(SCCP2)

CCP2MD

CCP3MD

PMD3<9>

Single Output Capture/Compare/PWM/Timer3

(SCCP3)

PMD3<10>

Timer1 (TMR1)

T1MD

U1MD

PMD4<0>

PMD5<0>

Universal Asynchronous Receiver 

Transmitter 1 (UART1)

Universal Asynchronous Receiver 

U2MD

PMD5<1>

Transmitter 2 (UART2)

Serial Peripheral Interface 1 (SPI1)

Serial Peripheral Interface 2 (SPI2)

Real-Time Clock and Calendar (RTCC)

Reference Clock Output (REFCLKO)

SPI1MD

SPI2MD

RTCCMD

REFOMD

CRCMD

PMD5<8>

PMD5<9>

PMD6<0>

PMD6<8>

PMD7<3>

Programmable Cyclic Redundancy Check

(CRC)

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and/or Retention mode. Standby mode is controlled by

the VREGS bit (PWRCON<0>), and Retention mode is

controlled by the RETEN (PWRCON<1>) and RETVR

22.4 On-Chip Voltage Regulator 

Low-Power Modes

The main on-chip regulator always consumes an incre-

mental amount of current over IDD/IPD, including when

the device is in Sleep mode, even though the core digital

logic does not require power. To provide additional

savings in applications where power resources are

critical, the regulator can be made to enter Standby mode

(FPOR<2>) bits. The available Regulator Low-Power

modes are listed in Table 22-2. For more information

about the wake-up time and the current consumption for

different modes, refer to the electrical specifications listed

in Table 26-6 and Table 26-22.

TABLE 22-2: VOLTAGE REGULATOR LOW-POWER MODES

VREGS Bit

(PWRCON<0>)

RETEN Bit

(PWRCON<1>)

RETVR Bit

(FPOR<2>)

Wake-up Time

(Table 26-22)

Current

(Table 26-6)

Mode

Normal

1

0

1

0

1

0

Fastest

Medium

Slowest

Highest

Medium

Lowest

Standby Only

Retention Only

Standby and

Retention

and the RTCC, while all other core digital logic is

powered down. The low-voltage/retention regulator is

available only when Sleep mode is invoked. It is con-

trolled by the RETVR Configuration bit (FPOR<2>) and

in firmware by the RETEN bit (PWRCON<1>). RETVR

must be programmed to zero (= 0) and the RETEN bit

must be set (= 1) for the retention regulator to be

enabled.

22.4.1

REGULATOR STANDBY MODE

Whenever the device goes into Sleep mode, the

regulator can be made to enter Standby mode. This

feature is controlled by the VREGS bit (PWRCON<0>).

Clearing the VREGS bit enables Standby mode. If

Standby mode is used, the voltage regulator needs

some time to switch to normal operation mode and

generate output. During this time, the code execution is

disabled. The delay is applied every time the device

resumes operation after Standby mode.

22.5 Low-Power Brown-out Reset

The PIC32MM0064GPL036 family devices have a

second low-power Brown-out Reset circuit with a

reduced precision of the trip point. This low-power BOR

circuit can be activated when the main BOR is disabled.

The circuit is enabled by programming the LPBOREN

Configuration bit (FPOR<3>) to ‘1’.

22.4.2

REGULATOR RETENTION MODE

When in Sleep mode, the device can use a separate

low-power, low-voltage/retention regulator to power

critical circuits. This regulator, which operates at 1V

nominal, maintains power to data RAM, WDT, Timer1



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23.4 System Registers Write Protection

23.0 SPECIAL FEATURES

The critical registers in the PIC32MM0064GPL036 family

devices are protected (locked) from an accidental write.

If the registers are locked, a special unlock sequence is

required to modify the content of these registers.

Note:

This data sheet summarizes the features

of the PIC32MM0064GPL036 family of

devices. However, it is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 33. “Programming

and Diagnostics” (DS61129) in the

“PIC32 Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32). The informa-

tion in this data sheet supersedes the

information in the FRM.

To unlock the registers, the following steps should be

done:

1. Disable interrupts prior to the system unlock

sequence.

2. Execute the system unlock sequence by writing

the key values of 0xAA996655 and

0x556699AA to the SYSKEY register, in two

back-to-back assembly or ‘C’ instructions.

3. Write the new value to the required register.

23.1 Configuration Bits

4. Write a non-key value (such as 0x00000000) to

the SYSKEY register to perform a lock.

PIC32MM0064GPL036 family devices contain a

Boot Flash Memory (BFM) with an associated con-

figuration space. All Configuration Words are listed

in Table 23-3 and Table 23-4; Register 23-1 through

Register 23-6 describe the configuration options.

5. Re-enable interrupts.

The registers that require this unlocking sequence are

listed in Table 23-2.

TABLE 23-2: SYSTEM LOCKED REGISTERS

Register

23.2 Code Execution from RAM

Register Description

Peripheral

PIC32MM0064GPL036 family devices allow executing

the code from RAM. The starting boundary of this

special RAM space can be adjusted using the

EXECADDR<7:0> bits in the CFGCON register with a

1-Kbyte step. Writing a non-zero value to these bits will

move the boundary, effectively reducing the total

amount of program memory space in RAM. Refer to

Table 23-5 and Register 23-7 for more information.

Name

OSCCON

SPLLCON

OSCTUN

PMDCON

Oscillator Control

System PLL Control

FRC Tuning

Oscillator

PMD

Peripheral Module

Disable Control

RSWRST

RPCON

Software Reset

Reset

Peripheral Pin Select

Configuration

I/O Ports

23.3 Device ID

The Device ID identifies the device used. The ID can be

read from the DEVID register. The Device IDs for

PIC32MM0064GPL036 family devices are listed in

Table 23-1. Also refer to Table 23-5 and Register 23-8

for more information.

RNMICON

Non-Maskable Interrupt

Control

Reset

PWRCON

RTCCON1

Power Control

Reset

RTCC

RTCC Control 1

The SYSKEY register read value indicates the status.

A value of ‘0’ indicates the system registers are locked.

A value of ‘1’ indicates the system registers are

unlocked. For more information about the SYSKEY

register, refer to Table 23-5 and Register 23-9.

TABLE 23-1: DEVICE IDs FOR

PIC32MM0064GPL036FAMILY

DEVICES

Device

DEVID

PIC32MM0016GPL020

PIC32MM0032GPL020

PIC32MM0064GPL020

PIC32MM0016GPL028

PIC32MM0032GPL028

PIC32MM0064GPL028

PIC32MM0016GPL036

PIC32MM0032GPL036

PIC32MM0064GPL036

0x06B04053

0x06B0C053

0x06B14053

0x06B02053

0x06B0A053

0x06B12053

0x06B06053

0x06B0E053

0x06B16053



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23.5 Band Gap Voltage Reference

23.7 Unique Device Identifier (UDID)

PIC32MM0064GPL036 family devices have a precision

voltage reference band gap circuit used by many

modules. The analog buffers are implemented between

the band gap circuit and these modules. The buffers

are automatically enabled by the hardware if some part

of the device needs the band gap reference. The stabi-

lization time is required when the buffer is switched on.

The software can enable these buffers in advance to

allow the band gap voltage to stabilize before the

module uses it. The ANCFG register contains bits to

enable the band gap buffers for the comparators

(VBGCMP bit) and ADC (VBGADC bit). Refer to

Table 23-6 and Register 23-10 for more information.

PIC32MM0064GPL036 family devices are individually

encoded during final manufacturing with a Unique

Device Identifier or UDID. The UDID cannot be erased

by a bulk erase command or any other user accessible

means. This feature allows for manufacturing trace-

ability of Microchip Technology devices in applications

where this is a requirement. It may also be used by the

application manufacturer for any number of things that

may require unique identification, such as:

• Tracking the device

• Unique serial number

• Unique security key

The UDID comprises five 32-bit program words. When

taken together, these fields form a unique 160-bit

identifier.

23.6 Programming and Diagnostics

PIC32MM0064GPL036 family devices provide

a

The UDID is stored in five read-only locations, located

from 0xBFC41840 to 0xBFC41854 in the device

configuration space. Table 23-7 lists the addresses of

the Identifier Words.

complete range of programming and diagnostic

features:

• Simplified Field Programmability using Two-Wire 

In-Circuit Serial Programming™ (ICSP™) 

Interfaces

23.8 Reserved Registers

• Debugging using ICSP

PIC32MM0064GPL036 family devices have 3 reserved

registers, located at 0xBF800400, 0xBF800480 and

0xBF802280. The application code must not modify

these reserved locations. Table 23-8 lists the addresses

of these reserved registers.

• Programming and Debugging Capabilities using

the EJTAG Extension of JTAG

• JTAG Boundary Scan Testing for Device and

Board Diagnostics

DS60001324C-page 184

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REGISTER 23-1: FDEVOPT/AFDEVOPT: DEVICE OPTIONS CONFIGURATION REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

R/P

31:24

23:16

15:8

7:0

USERID<15:8>

R/P

USERID<7:0>

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

R/P

SOSCHP

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

P = Programmable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

bit 31-16 USERID<15:0>: User ID bits (2 bytes which can be programmed to any value)

bit 15-4 Reserved: Program as ‘1’

bit 3

SOSCHP: Secondary Oscillator (SOSC) High-Power Enable bit

1= SOSC operates in Normal Power mode

0= SOSC operates in High-Power mode

bit 2-0

Reserved: Program as ‘1’



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REGISTER 23-2: FICD/AFICD: ICD/DEBUG CONFIGURATION REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

R/P

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

31:24

23:16

15:8

7:0

r-1

—

r-1

—

r-1

—

R/P

—

R/P

ICS<1:0>

JTAGEN

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

P = Programmable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

bit 31-5

bit 4-3

Reserved: Program as ‘1’

ICS<1:0>: ICE/ICD Communication Channel Selection bits

11= Communicates on PGEC1/PGED1

10= Communicates on PGEC2/PGED2

01= Communicates on PGEC3/PGED3

00= Not connected

bit 2

JTAGEN: JTAG Enable bit

1= JTAG is enabled

0= JTAG is disabled

bit 1-0

Reserved: Program as ‘1’

DS60001324C-page 188

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REGISTER 23-3: FPOR/AFPOR: POWER-UP SETTINGS CONFIGURATION REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3

26/18/10/2

25/17/9/1

24/16/8/0

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

R/P

31:24

23:16

15:8

7:0

—

r-1

—

r-1

—

r-1

—

R/P

LPBOREN

RETVR

BOREN<1:0>

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

P = Programmable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

bit 31-4 Reserved: Program as ‘1’

bit 3

LPBOREN: Low-Power BOR Enable bit

1= Low-Power BOR is enabled when the main BOR is disabled

0= Low-Power BOR is disabled

bit 2

RETVR: Retention Voltage Regulator Enable bit

1= Retention regulator is disabled

0= Retention regulator is enabled and controlled by the RETEN bit during Sleep

bit 1-0

BOREN<1:0>: Brown-out Reset Enable bits

11= Brown-out Reset is enabled in hardware; SBOREN bit is disabled

10= Brown-out Reset is enabled only while device is active and is disabled in Sleep; SBOREN bit is disabled

01= Brown-out Reset is controlled with the SBOREN bit setting

00= Brown-out Reset is disabled in hardware; SBOREN bit is disabled

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REGISTER 23-4: FWDT/AFWDT: WATCHDOG TIMER CONFIGURATION REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

31:24

23:16

15:8

7:0

—

r-1

—

R/P

—

R/P

—

R/P

—

R/P

—

R/P

—

R/P

FWDTEN

R/P

RCLKSEL<1:0>

RWDTPS<4:0>

R/P

WINDIS

FWDTWINSZ<1:0>

SWDTPS<4:0>

Legend:

r = Reserved bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

bit 31-16 Reserved: Program as ‘1’

bit 15 FWDTEN: Watchdog Timer Enable bit

1= WDT is enabled

0= WDT is disabled

bit 14-13 RCLKSEL<1:0>: Run Mode Watchdog Timer Clock Source Selection bits

11= Clock source is the LPRC oscillator (same as for Sleep mode)

10= Clock source is the FRC oscillator

01= Reserved

00= Clock source is the system clock

bit 12-8 RWDTPS<4:0>: Run Mode Watchdog Timer Postscale Select bits

From 10100to 11111= 1:1048576.

10011= 1:524288

10010= 1:262144

10001= 1:131072

10000= 1:65536

01111= 1:32768

01110= 1:16384

01101= 1:8192

01100= 1:4096

01011= 1:2048

01010= 1:1024

01001= 1:512

01000= 1:256

00111= 1:128

00110= 1:64

00101= 1:32

00100= 1:16

00011= 1:8

00010= 1:4

00001= 1:2

00000= 1:1

bit 7

WINDIS: Windowed Watchdog Timer Disable bit

1= Windowed mode is disabled

0= Windowed mode is enabled

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REGISTER 23-4: FWDT/AFWDT: WATCHDOG TIMER CONFIGURATION REGISTER (CONTINUED)

bit 6-5

FWDTWINSZ<1:0>: Watchdog Timer Window Size bits

11= Watchdog Timer window size is 25%

10= Watchdog Timer window size is 37.5%

01= Watchdog Timer window size is 50%

00= Watchdog Timer window size is 75%

bit 4-0

SWDTPS<4:0>: Sleep Mode Watchdog Timer Postscale Select bits

From 10100to 11111= 1:1048576.

10011= 1:524288

10010= 1:262144

10001= 1:131072

10000= 1:65536

01111= 1:32768

01110= 1:16384

01101= 1:8192

01100= 1:4096

01011= 1:2048

01010= 1:1024

01001= 1:512

01000= 1:256

00111= 1:128

00110= 1:64

00101= 1:32

00100= 1:16

00011= 1:8

00010= 1:4

00001= 1:2

00000= 1:1

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REGISTER 23-5: FOSCSEL/AFOSCSEL: OSCILLATOR SELECTION CONFIGURATION 

REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

31:24

23:16

15:8

7:0

—

r-1

—

r-1

—

R/P

—

R/P

—

R/P

—

R/P

—

R/P

FCKSM<1:0>

SOSCSEL

R/P

OSCIOFNC

R/P

POSCMOD<1:0>

R/P

IESO

SOSCEN

PLLSRC

FNOSC<2:0>

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

P = Programmable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

bit 31-16 Reserved: Program as ‘1’

bit 15-14 FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Enable bits

11= Clock switching is enabled; Fail-Safe Clock Monitor is enabled

10= Clock switching is disabled; Fail-Safe Clock Monitor is enabled

01= Clock switching is enabled; Fail-Safe Clock Monitor is disabled

00= Clock switching is disabled; Fail-Safe Clock Monitor is disabled

bit 13

bit 12

Reserved: Program as ‘1’

SOSCSEL: Secondary Oscillator (SOSC) External Clock Enable bit

1= Crystal is used (RA4 and RB4 pins are controlled by SOSC)

0= External clock is connected to the SOSCO pin (RA4 and RB4 pins are controlled by I/O PORTx registers)

bit 11

bit 10

Reserved: Program as ‘1’

OSCIOFNC: System Clock on CLKO Pin Enable bit

1= OSC2/CLKO pin operates as normal I/O

0= System clock is connected to the OSC2/CLKO pin

bit 9-8

POSCMOD<1:0>: Primary Oscillator (POSC) Mode Selection bits

11= Primary Oscillator is disabled

10= HS Oscillator mode is selected

01= XT Oscillator mode is selected

00= External Clock (EC) mode is selected

bit 7

bit 6

IESO: Two-Speed Start-up Enable bit

1= Two-Speed Start-up is enabled

0= Two-Speed Start-up is disabled

SOSCEN: Secondary Oscillator (SOSC) Enable bit

1= Secondary Oscillator is enabled

0= Secondary Oscillator is disabled

bit 5

bit 4

Reserved: Program as ‘1’

PLLSRC: System PLL Input Clock Selection bit

1= FRC oscillator is selected as the PLL reference input on a device Reset

0= Primary Oscillator (POSC) is selected as the PLL reference input on a device Reset

bit 3

Reserved: Program as ‘1’

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REGISTER 23-5: FOSCSEL/AFOSCSEL: OSCILLATOR SELECTION CONFIGURATION 

REGISTER (CONTINUED)

bit 2-0

FNOSC<2:0>: Oscillator Selection bits

110and 111= Reserved (selects Fast RC (FRC) Oscillator with Divide-by-N)

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Reserved

010= Primary Oscillator (XT, HS, EC)

001= Primary or FRC Oscillator with PLL

000= Fast RC (FRC) Oscillator with Divide-by-N

REGISTER 23-6: FSEC/AFSEC: CODE-PROTECT CONFIGURATION REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

R/P

CP

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

r-1

—

31:24

23:16

15:8

7:0

—

r-1

—

r-1

—

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

P = Programmable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

bit 31

CP: Code Protection Enable bit

1= Code protection is disabled

0= Code protection is enabled

bit 30-0

Reserved: Program as ‘1’

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REGISTER 23-7: CFGCON: CONFIGURATION CONTROL REGISTER

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

r-0

—

U-0

—

r-0

—

r-0

—

31:24

23:16

15:8

7:0

R/W-0

EXECADDR<7:0>

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

r-1

U-0

—

r-1

—

U-0

—

R/W-y

U-0

—

JTAGEN

—

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

y = Value set from Configuration bits on Reset

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-28 Unimplemented: Read as ‘0’

bit 27

bit 26

Reserved: Must be written as ‘0’

Unimplemented: Read as ‘0’

bit 25-24 Reserved: Must be written as ‘0’

bit 23-16 EXECADDR<7:0>: RAM Program Space Start Address bits

11111111= RAM program space starts at the 255-Kbyte boundary (from 0xA003FC00)

•

00000010= RAM program space starts at the 2-Kbyte boundary (from 0xA0000800)

00000001= RAM program space starts at the 1-Kbyte boundary (from 0xA0000400)

00000000= All data RAM is allocated to program space (from 0xA0000000)

bit 15-4 Unimplemented: Read as ‘0’

bit 3

JTAGEN: JTAG Enable bit

1= JTAG port is enabled

0= JTAG port is disabled

The Reset value of this bit is the value of the JTAGEN (FICD<2>) Configuration bit.

bit 2

Unimplemented: Read as ‘0’

bit 1-0

Reserved: Must be written as ‘1’

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REGISTER 23-8: DEVID: DEVICE ID REGISTER

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

R-x

(1)

R-x

(1)

R-x

31:24

23:16

15:8

7:0

VER<3:0>

ID<27:24>

R-x

(1)

ID<23:16>

R-x

(1)

ID<15:8>

R-x

(1)

ID<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

(1)

bit 31-28 VER<3:0>: Revision Identifier bits

(1)

bit 27-0 DEVID<27:0>: Device ID bits

Note 1: Reset values are dependent on the device variant.

REGISTER 23-9: SYSKEY: SYSTEM UNLOCK REGISTER

Bit

Range

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

24/16/8/0

W-0

31:24

23:16

15:8

7:0

SYSKEY<31:24>

W-0

SYSKEY<23:16>

W-0

SYSKEY<15:8>

W-0

SYSKEY<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-0 SYSKEY<31:0>: Unlock and Lock Key bits

DS60001324C-page 196

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REGISTER 23-10: ANCFG: BAND GAP CONTROL REGISTER

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5

28/20/12/4 27/19/11/3 26/18/10/2

25/17/9/1

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

31:24

23:16

15:8

7:0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R/W-0, HS, HC R/W-0, HS, HC

U-0

—

VBGADC

VBGCMP

Legend:

HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-3 Unimplemented: Read as ‘0’

bit 2

bit 1

bit 0

VBGADC: ADC Band Gap Enable bit

1= ADC band gap is enabled

0= ADC band gap is disabled

VBGCMP: Comparator Band Gap Enable bit

1= Comparator band gap is enabled

0= Comparator band gap is disabled

Unimplemented: Read as ‘0’

DS60001324C-page 198

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NOTES:

DS60001324C-page 200

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24.1 MPLAB X Integrated Development

Environment Software

24.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers (MCU) and dsPIC^®digital

signal controllers (DSC) are supported with a full range

of software and hardware development tools:

The MPLAB X IDE is a single, unified graphical user

interface for Microchip and third-party software, and

®

hardware development tool that runs on Windows ,

• Integrated Development Environment

- MPLAB^®X IDE Software

• Compilers/Assemblers/Linkers

- MPLAB XC Compiler

®

Linux and Mac OS X. Based on the NetBeans IDE,

MPLAB X IDE is an entirely new IDE with a host of free

software components and plug-ins for high-

performance application development and debugging.

Moving between tools and upgrading from software

simulators to hardware debugging and programming

tools is simple with the seamless user interface.

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

With complete project management, visual call graphs,

a configurable watch window and a feature-rich editor

that includes code completion and context menus,

MPLAB X IDE is flexible and friendly enough for new

users. With the ability to support multiple tools on

multiple projects with simultaneous debugging, MPLAB

X IDE is also suitable for the needs of experienced

users.

• Simulators

- MPLAB X SIM Software Simulator

• Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers/Programmers

- MPLAB ICD 3

Feature-Rich Editor:

- PICkit™ 3

• Color syntax highlighting

• Device Programmers

- MPLAB PM3 Device Programmer

• Smart code completion makes suggestions and

provides hints as you type

• Low-Cost Demonstration/Development Boards,

Evaluation Kits and Starter Kits

• Automatic code formatting based on user-defined

rules

• Third-party development tools

• Live parsing

User-Friendly, Customizable Interface:

• Fully customizable interface: toolbars, toolbar

buttons, windows, window placement, etc.

• Call graph window

Project-Based Workspaces:

• Multiple projects

• Multiple tools

• Multiple configurations

• Simultaneous debugging sessions

File History and Bug Tracking:

• Local file history feature

• Built-in support for Bugzilla issue tracker



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24.2 MPLAB XC Compilers

24.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB XC Compilers are complete ANSI C

compilers for all of Microchip’s 8, 16 and 32-bit MCU

and DSC devices. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use. MPLAB XC Compilers run on Windows,

Linux or MAC OS X.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler. It can link

relocatable objects from precompiled libraries, using

directives from a linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

debug information that is optimized to the MPLAB X

IDE.

The free MPLAB XC Compiler editions support all

devices and commands, with no time or memory

restrictions, and offer sufficient code optimization for

most applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

MPLAB XC Compilers include an assembler, linker and

utilities. The assembler generates relocatable object

files that can then be archived or linked with other

relocatable object files and archives to create an exe-

cutable file. MPLAB XC Compiler uses the assembler

to produce its object file. Notable features of the

assembler include:

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

24.5 MPLAB Assembler, Linker and

Librarian for Various Device

Families

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC DSC devices. MPLAB XC Compiler

uses the assembler to produce its object file. The

assembler generates relocatable object files that can

then be archived or linked with other relocatable object

files and archives to create an executable file. Notable

features of the assembler include:

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

24.3 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code, and COFF files for

debugging.

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

The MPASM Assembler features include:

• Integration into MPLAB X IDE projects

• User-defined macros to streamline 

assembly code

• Conditional assembly for multipurpose 

source files

• Directives that allow complete control over the

assembly process

DS60001324C-page 202

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24.6 MPLAB X SIM Software Simulator

24.8 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB X SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB ICD 3 In-Circuit Debugger System is

Microchip’s most cost-effective, high-speed hardware

debugger/programmer for Microchip Flash DSC and

MCU devices. It debugs and programs PIC Flash

microcontrollers and dsPIC DSCs with the powerful,

yet easy-to-use graphical user interface of the MPLAB

IDE.

The MPLAB ICD 3 In-Circuit Debugger probe is

connected to the design engineer’s PC using a high-

speed USB 2.0 interface and is connected to the target

with a connector compatible with the MPLAB ICD 2 or

MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3

supports all MPLAB ICD 2 headers.

The MPLAB X SIM Software Simulator fully supports

symbolic debugging using the MPLAB XC Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

24.9 PICkit 3 In-Circuit Debugger/

Programmer

The MPLAB PICkit 3 allows debugging and program-

ming of PIC and dsPIC Flash microcontrollers at a most

affordable price point using the powerful graphical user

interface of the MPLAB IDE. The MPLAB PICkit 3 is

connected to the design engineer’s PC using a full-

speed USB interface and can be connected to the

target via a Microchip debug (RJ-11) connector (com-

patible with MPLAB ICD 3 and MPLAB REAL ICE). The

connector uses two device I/O pins and the Reset line

to implement in-circuit debugging and In-Circuit Serial

Programming™ (ICSP™).

24.7 MPLAB REAL ICE In-Circuit

Emulator System

The MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs all 8, 16 and 32-bit MCU, and DSC devices

with the easy-to-use, powerful graphical user interface of

the MPLAB X IDE.

The emulator is connected to the design engineer’s

PC using a high-speed USB 2.0 interface and is

connected to the target with either a connector

compatible with in-circuit debugger systems (RJ-11)

or with the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

24.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at

VDDMIN and VDDMAX for

The emulator is field upgradable through future firmware

downloads in MPLAB X IDE. MPLAB REAL ICE offers

significant advantages over competitive emulators

including full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, logic

probes, a ruggedized probe interface and long (up to

three meters) interconnection cables.

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages, and a mod-

ular, detachable socket assembly to support various

package types. The ICSP cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices, and incorporates an MMC card for file

storage and data applications.



2015-2018 Microchip Technology Inc.

DS60001324C-page 203

PIC32MM0064GPL036 FAMILY

24.11 Demonstration/Development

Boards, Evaluation Kits and

Starter Kits

24.12 Third-Party Development Tools

Microchip also offers a great collection of tools from

third-party vendors. These tools are carefully selected

to offer good value and unique functionality.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully

functional systems. Most boards include prototyping

areas for adding custom circuitry and provide applica-

tion firmware and source code for examination and

modification.

• Device Programmers and Gang Programmers

from companies, such as SoftLog and CCS

• Software Tools from companies, such as Gimpel

and Trace Systems

• Protocol Analyzers from companies, such as

Saleae and Total Phase

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

• Demonstration Boards from companies, such as

MikroElektronika, Digilent and Olimex

®

• Embedded Ethernet Solutions from companies,

®

such as EZ Web Lynx, WIZnet and IPLogika

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™

demonstration/development board series of circuits,

Microchip has a line of evaluation kits and demonstra-

tion software for analog filter design, KEEL

OQ^®security

ICs, CAN, IrDA^®, PowerSmart battery management,

SEEVAL^®evaluation system, Sigma-Delta ADC, flow

rate sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS60001324C-page 204

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

25.0 INSTRUCTION SET

The PIC32MM0064GPL036 family instruction set

®

complies with the MIPS Release 3 instruction set

architecture. Only microMIPS32™ instructions are

supported. The PIC32MM0064GPL036 family does not

have the following features:

• Core extend instructions

• Coprocessor 1 instructions

• Coprocessor 2 instructions

®

Note:

Refer to the “MIPS Architecture for

Programmers

Volume

II-B:

The

microMIPS32™ Instruction Set” at

www.imgtec.com for more information.



2015-2018 Microchip Technology Inc.

DS60001324C-page 205

PIC32MM0064GPL036 FAMILY

NOTES:

DS60001324C-page 206

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

26.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of the PIC32MM0064GPL036 family electrical characteristics. Additional information

will be provided in future revisions of this document as it becomes available.

Absolute maximum ratings for the PIC32MM0064GPL036 family are listed below. Exposure to these maximum rating

conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other

conditions above the parameters indicated in the operation listings of this specification, is not implied.

(†)

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V

Voltage on any general purpose digital or analog pin (not 5.5V tolerant) with respect to VSS....... -0.3V to (VDD + 0.3V)

Voltage on any general purpose digital or analog pin (5.5V tolerant) with respect to VSS

:

When VDD = 0V: .......................................................................................................................... -0.3V to +4.0V

When VDD  2.0V: ....................................................................................................................... -0.3V to +6.0V

Voltage on AVDD with respect to VSS ..........................................................................................................................VDD

Voltage on AVSS with respect to VSS ..........................................................................................................................VSS

Maximum current out of VSS pin ...........................................................................................................................100 mA

(1)

Maximum current into VDD pin ...........................................................................................................................300 mA

Maximum output current sunk by I/O pin ................................................................................................................11 mA

Maximum output current sourced by I/O pin ...........................................................................................................16 mA

Maximum output current sunk by I/O pin with increased current drive strength (RA3, RB8, RB9 and RB15)........17 mA

Maximum output current sourced by I/O pin with increased current drive strength (RA3, RB8, RB9 and RB15) ..........24 mA

Maximum current sunk by all ports .......................................................................................................................300 mA

(1)

Maximum current sourced by all ports ...............................................................................................................300 mA

Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 26-1).

†

NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above

those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions

for extended periods may affect device reliability.



2015-2018 Microchip Technology Inc.

DS60001324C-page 207

PIC32MM0064GPL036 FAMILY

26.1 DC Characteristics

FIGURE 26-1:

PIC32MM0064GPL036 FAMILY VOLTAGE-FREQUENCY GRAPH

3.6V

PIC32MM00XXGPL0XX

(1)

2.0V

DC

25 MHz

Frequency

Note 1: Lower operating boundary is 2.0V or VBOR when BOR is enabled.

TABLE 26-1: THERMAL OPERATING CONDITIONS

Rating

Symbol

Min

Typ

Max

Unit

PIC32MM00XXGPL0XX:

(1)

Operating Junction Temperature Range

T

J

-40

—

+100

+140

°C

(2)

°C

PIC32MM00XXGPL0XX:

(1)

Operating Ambient Temperature Range

T

A

-40

—

+85

°C

(2)

TA

+125

°C

Power Dissipation:

Internal Chip Power Dissipation:

P

INT = VDD x (IDD –  IOH

I/O Pin Power Dissipation:

=  ({VDD – VOH} x IOH) +  (VOL x IOL)

)

P

D

P

INT + P

I

/

O

W

P

I/O

Maximum Allowed Power Dissipation

Note 1: 85°C rated parts.

2: 125°C rated parts.

P

DMAX

(TJ – TA)/JA

DS60001324C-page 208

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

TABLE 26-2: PACKAGE THERMAL RESISTANCE⁽¹⁾

Package Symbol

20-Pin SSOP

Typ

Unit

JA

87.3

43.0

60.0

71.0

69.7

27.5

20.0

31.1

41.0

°C/W

20-Pin QFN

28-Pin SPDIP

28-Pin SSOP

28-Pin SOIC

28-Pin UQFN

28-Pin QFN

36-Pin VQFN

40-Pin UQFN

Note 1: Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations.

TABLE 26-3: OPERATING VOLTAGE SPECIFICATIONS

Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated)

Param

No.

Symbol

Characteristic

Supply Voltage

Min

Max

Units

Conditions

BOR disabled

DC10

VDD

2.0

3.6

—

V

VBOR

BOR enabled

(1)

DC16

VPOR

VDD Start Voltage

V

SS

0.05

1.94

to Ensure Internal

Power-on Reset Signal

DC17A SVDD

VDD Rise Rate

—

V/ms

V

0-3.3V in 66 ms,

0-2.0V in 40 ms

to Ensure Internal

Power-on Reset Signal

DC17B

VBOR

Brown-out Reset 

2.22

Voltage on VDD



Transition, High-to-Low

Note 1: If the VPOR or SVDD parameters are not met, or the application experiences slow power-down VDD ramp

rates, it is recommended to enable and use BOR.



2015-2018 Microchip Technology Inc.

DS60001324C-page 209

PIC32MM0064GPL036 FAMILY

(2)

TABLE 26-4: OPERATING CURRENT (IDD

Operating Conditions: -40°C < T

)

A

< +85°C (unless otherwise stated)

(1)

Parameter No.

Typical

Max

Units

V

DD

Conditions

SYS = 1 MHz

DC19

0.45

2.5

0.65

3.5

mA

2.0V

3.3V

2.0V

3.3V

2.0V

3.3V

2.0V

3.3V

F

DC23

SYS = 8 MHz

SYS = 25 MHz

2.5

3.5

DC24

7.0

9.2

7.0

9.2

DC25A

0.26

0.70

0.35

0.90

F

SYS = 32 kHz

DS25B

SYS = 32 kHz, +125°C

Note 1: Data in the “Typical” column is at +25°C unless otherwise stated. Parameters are for design 

guidance only and are not tested.

2: Base IDD current is measured with:

• Oscillator is configured in EC mode without PLL (FNOSC<2:0> (FOSCSEL<2:0>) = 010and 

POSCMOD<1:0> (FOSCSEL<9:8>) = 00)

• OSC1 pin is driven with external square wave with levels from 0.3V to VDD – 0.3V

• OSC2 is configured as an I/O in Configuration Words (OSCIOFNC (FOSCSEL<10>) = 1)

• FSCM is disabled (FCKSM<1:0> (FOSCSEL<15:14>) = 00)

• Secondary Oscillator circuits are disabled (SOSCEN (FOSCSEL<6>) = 0and 

SOSCSEL (FOSCSEL<12>) = 0)

• Main and low-power BOR circuits are disabled (BOREN<1:0> (FPOR<1:0>) = 00and 

LPBOREN (FPOR<3>) = 0)

• Watchdog Timer is disabled (FWDTEN (FWDT<15>) = 0)

• All I/O pins (except OSC1) are configured as outputs and driving low

• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)

• NOPinstructions are executed

DS60001324C-page 210

 2015-2018 Microchip Technology Inc.

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(2)

TABLE 26-5: IDLE CURRENT (IIDLE

)

Operating Conditions: -40°C < T < +85°C (unless otherwise stated)

A

(1)

Parameter No.

Typical

Max

Units

V

DD

Conditions

SYS = 1 MHz

DC40A

0.26

0.85

2.3

0.46

1.5

3.7

0.34

1

mA

2.0V

3.3V

2.0V

3.3V

2.0V

3.3V

2.0V

3.3V

2.0V

3.3V

2.0V

3.3V

2.0V

3.3V

2.0V

3.3V

F

DC41A

DC42A

DC44A

DC40B

DC41B

DC42B

DC44B

SYS = 8 MHz

SYS = 25 MHz

2.3

0.18

0.6

SYS = 32 kHz

SYS = 1 MHz, +125°C

SYS = 8 MHz, +125°C

SYS = 25 MHz, +125°C

SYS = 32 kHz, +125°C

0.6

1

1.4

2.1

4.3

0.64

1.4

2.9

0.4

Note 1: Data in the “Typical” column is at +25°C unless otherwise stated. Parameters are for design 

guidance only and are not tested.

2: Base IIDLE current is measured with:

• Oscillator is configured in EC mode without PLL (FNOSC<2:0> (FOSCSEL<2:0>) = 010and 

POSCMOD<1:0> (FOSCSEL<9:8>) = 00)

• OSC1 pin is driven with external square wave with levels from 0.3V to VDD – 0.3V

• OSC2 is configured as I/O in Configuration Words (OSCIOFNC (FOSCSEL<10>) = 1)

• FSCM is disabled (FCKSM<1:0> (FOSCSEL<15:14>) = 00)

• Secondary Oscillator circuits are disabled (SOSCEN (FOSCSEL<6>) = 0and 

SOSCSEL (FOSCSEL<12>) = 0)

• Main and low-power BOR circuits are disabled (BOREN<1:0> (FPOR<1:0>) = 00and 

LPBOREN (FPOR<3>) = 0)

• Watchdog Timer is disabled (FWDTEN (FWDT<15>) = 0)

• All I/O pins (excepting OSC1) are configured as outputs and driving low

• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)



2015-2018 Microchip Technology Inc.

DS60001324C-page 211

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(2)

TABLE 26-6: POWER-DOWN CURRENT (IPD

)

Parameter

No.

Operating

Temperature

(1)

Typical

Max

Units

VDD

Conditions

DC60

134

136

141

350

139

141

143

400

4.3

198

208

217

640

209

217

231

650

11.7

15.6

55

µA

-40°C

+25°C

+85°C

+125°C

-40°C

2.0V

3.3V

2.0V

Sleep with active main voltage regulator

(VREGS (PWRCON<0>) = 1, 

RETEN (PWRCON<1>) =0)

+25°C

+85°C

+125°C

-40°C

DC61

5.1

+25°C

+85°C

+125°C

-40°C

35

Sleep with main voltage regulator in

Standby mode 

(VREGS (PWRCON<0>) = 0, 

RETEN (PWRCON<1>) = 0)

40

90

6.1

16.8

20.1

36.0

100

—

6.9

+25°C

+85°C

+125°C

-40°C

3.3V

2.0V

3.3V

2.0V

3.3V

12.7

60

DC62

2.3

2.7

—

+25°C

+85°C

-40°C

Sleep with enabled retention voltage

regulator (VREGS (PWRCON<0>) = 1,

RETEN (PWRCON<1>) = 1, 

RETVR (FPOR<2>) = 0)

5.2

—

2.3

—

2.7

—

+25°C

+85°C

+125°C

-40°C

5.4

—

10.1

0.28

0.44

2.52

0.29

0.44

2.62

10.1

—

DC63

—

+25°C

+85°C

-40°C

Sleep with enabled retention voltage

regulator (VREGS (PWRCON<0>) = 0,

RETEN (PWRCON<1>) = 1, 

RETVR (FPOR<2>) = 0)

—

+25°C

+85°C

+125°C

—

Note 1: Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design 

guidance only and are not tested.

2: Base IPD is measured with:

• Oscillator is configured in FRC mode without PLL (FNOSC<2:0> (FOSCSEL<2:0>) = 000)

• OSC2 is configured as I/O in Configuration Words (OSCIOFNC (FOSCSEL<10>) = 1)

• FSCM is disabled (FCKSM<1:0> (FOSCSEL<15:14>) = 00)

• Secondary Oscillator circuits are disabled (SOSCEN (FOSCSEL<6>) = 0and 

SOSCSEL (FOSCSEL<12>) = 0)

• Main and low-power BOR circuits are disabled (BOREN<1:0> (FPOR<1:0>) = 00and 

LPBOREN (FPOR<3>) = 0)

• Watchdog Timer is disabled (FWDTEN (FWDT<15>) = 0)

• All I/O pins are configured as outputs and driving low

• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)

DS60001324C-page 212

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PIC32MM0064GPL036 FAMILY

TABLE 26-7: INCREMENTAL PERIPHERALCURRENT⁽²⁾

< +85°C (unless otherwise stated)

Conditions

Operating Conditions: 2.0V < VDD < 3.6V, -40°C < T

A

(1)

Parameter No.

Typ

Units

Brown-out Reset Incremental Current (BOR)

DC71A

DC71B

2.7

3.4

µA

+125°C

Watchdog Timer Incremental Current (WDT)

DC72A

DC72B

80

nA

with LPRC

140

+125°C with LPRC

High/Low-Voltage Detect Incremental Current (HLVD)

DC73 2.1 µA

Real-Time Clock and Calendar Incremental Current (RTCC)

DC74A

DC74B

DC75A

DC75B

1.0

2.0

µA

with SOSC

+125°C with SOSC

with LPRC

0.4

0.65

+125°C with LPRC

ADC Incremental Current (ADC

DC76A

DC76B

450

590

µA

12-bit, 100 ksps, with FRC

+125°C, 12-bit, 100 ksps, with FRC

FRC Oscillator Incremental Current (FRC)

DC78A

DC78B

305

350

µA

+125°C

PLL Incremental Current (PLL)

DC79A

DC79B

DC80A

DC80B

1230

1550

1850

µA

F

VCO = 24 MHz

VCO = 24MHz +125°C

VCO = 48 MHz

VCO = 48MHz +125°C

Digital-to-Analog Converter Incremental Current, CDAC (DAC)

DC81A

DC81B

27.5

40.0

µA

+125°C

Low-Power BOR Incremental Current (LPBOR)

DC82A

DC82B

200

420

nA

Comparator Incremental Current (CMP)

DC83A

DC83B

24.0

38.0

µA

Note 1: Data in the “Typ” column is for design guidance only and is not tested.

2: The  current is an additional current consumed when the module is enabled. This current should be

added to the base IPD current.



2015-2018 Microchip Technology Inc.

DS60001324C-page 213

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TABLE 26-8:

I/O PIN INPUT SPECIFICATIONS

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

 +125°C (unless otherwise stated)

Param

No.

(1)

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

(2)

VIL

Input Low Voltage

DI10

DI15

DI16

DI17

I/O Pins with ST Buffer

MCLR

VSS

—

0.2 VDD

V

OSC1/CLKI (XT mode)

OSC1/CLKI (HS mode)

(2)

VIH

Input High Voltage

DI20

I/O Pins with ST Buffer:

without 5V Tolerance

with 5V Tolerance

0.8 VDD

—

V

5.5

DD

V

DI25

DI26

DI27

DI30

DI30A

MCLR

0.8 VDD

0.7 VDD

—

V

DD

V

OSCI/CLKI (XT mode)

OSC1/CLKI (HS mode)

CNPUx Pull-up Current

CNPDx Pull-Down Current

Input Leakage Current

I/O Pins – 5V Tolerant

V

—

V

I

CNPU

CNPD

IL

350

300

—

µA

V

PIN = 0V, VDD = 3.3V

PIN = 3.3V, VDD = 3.3V

—

V

DI50

DI51

—

0.1

1.0

µA

VPIN = 3.3V, VDD = 3.3V,

pin at high-impedance

PIN = 3.3V, VDD = 3.3V,

pin at high-impedance

I/O Pins – Not 5V Tolerant

V

µA

DI55

DI56

MCLR

—

0.1

1.0

V

PIN = 3.3V, VDD = 3.3V

OSC1/CLKI

V

Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Refer to Table 1-1 for I/O pin buffer types.

DS60001324C-page 214

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

TABLE 26-9: I/O PIN INPUT INJECTION CURRENT SPECIFICATIONS

 +125°C (unless otherwise stated)

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

Param.

No.

Symbol

Characteristics

Min.

Max.

Units

Conditions

(1,4)

DI60a

I

ICL

Input Low Injection

Current

0

-5

mA This parameter applies to all pins,

except VDD, VSS, MCLR and

VCAP.

(2,3,4)

DI60b

ICH

Input High Injection

Current

0

+5

mA This parameter applies to all pins,

except VDD, VSS, MCLR, VCAP

and all 5V tolerant pins.

(2,3,4)

(5)

+0

mA 5V tolerant pins.

(5)

DI60c

IICT

Total Input Injection

Current (sum of all I/O

and control pins)

-20

+20

mA Absolute instantaneous sum of 

all ± input injection currents from

all I/O pins,

( | IICL + | IICH | )  IICT

Note 1:

2:

V

IL Source < (VSS – 0.3). Characterized but not tested.

IH Source > (VDD + 0.3) for non-5V tolerant pins only.

V

3: Digital 5V tolerant pins do not have an internal high-side diode to VDD, and therefore, cannot tolerate any

“positive” input injection current.

4: Injection currents can affect the ADC results.

5: Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted 

provided the “absolute instantaneous” sum of the input injection currents from all pins do not 

exceed the specified limit.



2015-2018 Microchip Technology Inc.

DS60001324C-page 215

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TABLE 26-10: I/O PIN OUTPUT SPECIFICATIONS

Operating Conditions: 2.0V  VDD  3.6V, -40°C  TA  +125°C (unless otherwise stated)

Param

No.

Symbol

Characteristic

Min

Max

Units

Conditions

VOL

Output Low Voltage

DO10

DO16

I/O Ports

—

0.36

0.21

0.16

0.12

V

I

OL = 6.0 mA, VDD = 3.6V

OL = 3.0 mA, VDD = 2V

OL = 6.0 mA, VDD = 3.6V

OL = 3.0 mA, VDD = 2V

RA3, RB8, RB9 and RB15 I/O Ports

VOH

Output High Voltage

DO20

DO26

I/O Ports

3.25

1.4

—

V

I

OH = -6.0 mA, VDD = 3.6V

OH = -3.0 mA, VDD = 2V

OH = -6.0 mA, VDD = 3.6V

OH = -3.0 mA, VDD = 2V

RA3, RB8, RB9 and RB15 I/O Ports

3.3

1.55

TABLE 26-11: PROGRAM FLASH MEMORY SPECIFICATIONS

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

 +125°C (unless otherwise stated)

Param

No.

(1)

Symbol

Characteristic

Min Typ

Max

Units

Conditions

D130

D131

E

P

Cell Endurance

DD for In-Circuit Serial

Programming™ (ICSP™)

DD for Run-Time 

10000 20000

—

E/W

V

VICSP

V

VBOR

—

3.6

D132

D133

VRTSP

V

2.0

19.7

1.3

—

3.6

22.3

1.5

V

Self-Programming (RTSP)

TIW

Self-Timed Double-Word

Write Cycle Time

21.0

1.4

µs

8 bytes, data is not all ‘1’s

Self-Timed Row Write

Cycle Time

ms 256 bytes, data is not all ‘1’s,

SYSCLK > 2 MHz

D133

TIE

Self-Timed Page Erase

Time

15.0

16.0

17.0

ms 2048 bytes

D134

D136

T

RETD

Characteristic Retention

20

—

Year If no other specifications are violated

ms

TCE

Self-Timed Chip Erase

Time

16.0

17.0

18.0

Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

DS60001324C-page 216

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TABLE 26-12: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

 +125°C (unless otherwise stated)

Param

No.

(1)

Symbol

Characteristics

Min Typ

Max Units

Comments

DVR10

DVR20

DVR21

V

BG

Band Gap Reference Voltage

1.163

—

1.2 1.237

V

VRGOUT Regulator Output Voltage

1.8

10

—

V

VDD > 1.9V

C

EFC

External Filter Capacitor Value

4.7

µF Series Resistance < 3

recommended; < 5 required

DVR30

VLVR

Low-Voltage Regulator 

0.9

—

1.2

V

RETEN = 1, 

Output Voltage

RETVR (FPOR<2>) = 0

Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

TABLE 26-13: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

Operating Conditions: 2.0V  VDD  3.6V, -40°C  TA  +125°C (unless otherwise stated)

Param

No.

(2)

Symbol

Characteristic

Min

Typ

Max

Units

(1)

HLVDL<3:0> = 0110

HLVDL<3:0> = 0111

HLVDL<3:0> = 1000

HLVDL<3:0> = 1001

HLVDL<3:0> = 1010

HLVDL<3:0> = 1011

HLVDL<3:0> = 1100

HLVDL<3:0> = 1101

HLVDL<3:0> = 1110

HLVDL<3:0> = 1111

2.95

2.75

2.65

2.45

2.35

2.25

2.15

2.08

2.00

—

1.2

3.45

3.13

3.01

2.83

2.72

2.57

2.46

2.35

2.24

—

V

DC18

V

HLVD

HLVD Voltage on VDD

Transition

DC101

VTHL

HLVD Voltage on 

LVDIN Pin Transition

Note 1: Trip points for values of HLVD<3:0>, from ‘0000’ to ‘0101’, are not implemented.

2: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.



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TABLE 26-14: COMPARATOR SPECIFICATIONS

Operating Conditions: 2.0V < VDD < 3.6V, -40°C < T

A

< +125°C (unless otherwise stated)

Param

No.

(2)

Symbol

Characteristic

Input Offset Voltage

Min

Typ

Max

Units

D300

VIOFF

-60

0

12

—

60

mV

(1)

D301

D307

VICM

Input Common-Mode Voltage

Response Time

VDD

V

(1)

T

RESP

—

150

—

ns

Note 1: Measured with one input at VDD/2 and the other transitioning from VSS to VDD

.

2: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

TABLE 26-15: VOLTAGE REFERENCE (CDAC) SPECIFICATIONS

Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated)

Param

No.

(2)

Symbol

Characteristic

Min

Typ

Max

Units

(1)

VRD310

VRD311

VRD312

T

SET

Settling Time

Accuracy

—

-1

—

10

1

µs

LSb

k

VR

A

VRUR

Unit Resistor Value (R)

4.5

—

Note 1: Measures the interval while VRDAT<4:0> transitions from ‘11111’ to ‘00000’.

2: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

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26.2 AC Characteristics and Timing Parameters

FIGURE 26-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 – for all pins except OSC2/CLKO Load Condition 2 – for OSC2/CLKO

DD/2

V

C

L

R

L

VSS

C

R

C

L

= 464

= 50 pF for all pins except OSC2/CLKO

15 pF for OSC2/CLKO output

VSS

TABLE 26-16: CAPACITIVE LOADING CONDITIONS ON OUTPUT PINS

Param

Symbol

Characteristic

Min

Max

Units

Conditions

No.

DO50

COSCO

OSC2/CLKO Pin

—

15

pF

In XT and HS modes when

external clock is used to drive

OSC1/CLKI

DO56

CIO

All I/O Pins and OSC2

—

50

pF

EC mode



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FIGURE 26-3:

EXTERNAL CLOCK TIMING

OSCI

OS10

OS30

OS31 OS31

CLKO

OS40

OS41

TABLE 26-17: EXTERNAL CLOCK TIMING REQUIREMENTS

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

 +125°C (unless otherwise stated)

Param

No.

(1)

Symbol

Characteristic

Min

Typ

Max

Units

MHz EC

Conditions

OS10

F

OSC

External CLKI Frequency

DC

2

—

25

12.5

(2)

MHz ECPLL

Oscillator Frequency

3.5

10

31

—

10

25

50

MHz XT

MHz XTPLL

MHz HS

(2)

MHz HSPLL

kHz

SOSC

OS30 TosL,

TosH

External Clock in (OSC1) 0.45 x TOSC

High or Low Time

—

0.55 x TOSC

ns

EC

OS31 TosR, External Clock in (OSC1)

—

20

ns

EC

TosF

OS40 TckR

OS41 TckF

Rise or Fall Time

(3)

CLKO Rise Time

—

15

20

ns

(3)

CLKO Fall Time

Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: PLL dividers and postscalers must be configured so that the system clock frequency does not exceed the

maximum operating frequency.

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.

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TABLE 26-18: PLL CLOCK TIMING SPECIFICATIONS

 +125°C (unless otherwise stated)

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

Param

No.

Symbol

Characteristic

Min

Max

Units

(1)

OS50

F

T

PLLI

PLL Input Frequency Range

2

16

24

96

MHz

µs

(1)

OS54

OS52

OS53

PLLO

LOCK

PLL Output Frequency Range

PLL Start-up Time (Lock Time)

CLKO Stability (Jitter)

—

24

D

CLK

-0.12

0.12

%

Note 1: These parameters are characterized but not tested in manufacturing.

TABLE 26-19: INTERNAL OSCILLATOR ACCURACY⁽¹⁾

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

 +125°C (unless otherwise stated)

(2)

Param No.

Characteristic

FRC Accuracy @ 8 MHz

Min

Typ

Max

Units

F20A

F20B

F21A

F21B

F22

-5

-3

—

5

%

(3)

FRC Accuracy @ 8 MHz

3

(3)

LPRC @ 32 kHz

-20

-30

—

20

30

—

%

LPRC @ 32 kHz

—

%

FRC Tune Step-Size (in OSCTUN register)

0.05

%/Bit

Note 1: To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB)

must be kept to a minimum.

2: Data in the “Typ” column is 3.3V unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: -40°C to +85°C.

TABLE 26-20: INTERNAL OSCILLATOR START-UP TIME

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

 +125°C (unless otherwise stated)

Param

No.

Symbol

Characteristic

Max

Units

FR0

FR1

T

FRC

LPRC

FRC Oscillator Start-up Time

Low-Power RC Oscillator Start-up Time

2

µs

T

70

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FIGURE 26-4:

CLKO AND I/O TIMING CHARACTERISTICS

I/O Pin

(Input)

DI35

DI40

I/O Pin

(Output)

New Value

Old Value

DO31

DO32

Note:

Refer to Figure 26-2 for load conditions.

TABLE 26-21: CLKO AND I/O TIMING REQUIREMENTS

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

 +125°C (unless otherwise stated)

Param

No.

(1)

Symbol

Characteristic

Min

Typ

Max

Units

DO31

T

IO

R

F

Port Output Rise Time

—

10

—

25

—

ns

DO32

DI35

DI40

TIO

Port Output Fall Time

TINP

INTx Input Pin High or Low Time

CNx Input Pin High or Low Time

TRBP

Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

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TABLE 26-22: RESET, BROWN-OUT RESET AND SLEEP MODES TIMING SPECIFICATIONS

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

 +125°C (unless otherwise stated)

Param

No.

(1)

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

SY10

SY13

T

MCL

MCLR Pulse Width (Low)

2

—

1

—

µs

TIOZ

I/O High-Impedance from

MCLR Low

—

SY25

T

BOR

Brown-out Reset Pulse

Width

1

—

µs

VDD VBOR

SY45

SY71

T

RST

Reset State Time

—

25

22

—

µs

(2)

TWAKE

Wake-up Time with Main

Voltage Regulator

Sleep wake-up with 

VREGS = 0, RETEN = 0,

RETVR = 1

—

3.8

163

23

—

µs

Sleep wake-up with 

VREGS = 1, RETEN = 0,

RETVR = 1

(2)

SY72

TWAKELVR

Wake-up Time with

Retention Low-Voltage

Regulator

Sleep wake-up with 

VREGS = 0, RETEN = 1,

RETVR = 0

Sleep wake-up with 

VREGS = 1, RETEN = 1,

RETVR = 0

Note 1: Data in the “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: The parameters are measured with the external clock source (EC). To get the full wake-up time, the

oscillator start-up time must be added.

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FIGURE 26-5:

TIMER1 EXTERNAL CLOCK TIMING CHARACTERISTICS

T1CK

TA11

TA10

TA15

TA20

TMR1

TABLE 26-23: MCCP/SCCP TIMER1 EXTERNAL CLOCK TIMING CHARACTERISTICS

 +125°C (unless otherwise stated)

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

Param.

No.

(1)

Symbol

Characteristics

Min

Max

Units

Conditions

TA10

TA11

TA15

TA20

T

CKH

T1CK High Time Synchronous

Asynchronous

1

10

1

—

3

T

PBCLK Must also meet Parameter TA15

ns

TCKL

T1CK Low Time Synchronous

Asynchronous

PBCLK Must also meet Parameter TA15

10

2

ns

TCKP

T1CK Input

Period

Synchronous

Asynchronous

PBCLK

20

—

ns

TCKEXTMRL Delay from External T1CK Clock

PBCLK Synchronous mode

Edge to Timer Increment

Note 1: These parameters are characterized but not tested in manufacturing.

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FIGURE 26-6:

MCCP/SCCP TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS

TCKIx

TMR10

TMR11

TMR15

TMR20

CCPxTMR

TABLE 26-24: MCCP/SCCP TIMING REQUIREMENTS

 +125°C (unless otherwise stated)

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

Param.

No.

(1)

Symbol

Characteristics

Min

Max

Units

Conditions

TMR10

TCKH

TCKIx High Time Synchronous

1

—

T

PBCLK Must also meet 

Parameter TMR15

Asynchronous

10

1

—

ns

TMR11

TCKL

TCKIx Low Time Synchronous

T

PBCLK Must also meet 

Parameter TMR15

Asynchronous

TCKIx Input Period Synchronous

Asynchronous

10

2

—

1

ns

TMR15

TMR20

T

CKP

T

PBCLK

ns

20

—

T

CKEXTMRL Delay from External TCKIx Clock Edge

to Timer Increment

Note 1: These parameters are characterized but not tested in manufacturing.

PBCLK



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FIGURE 26-7:

MCCP AND SCCP INPUT CAPTURE x MODE TIMING CHARACTERISTICS

ICMx

IC10

IC11

IC15

TABLE 26-25: MCCP AND SCCP INPUT CAPTURE x MODE TIMING REQUIREMENTS

 +125°C (unless otherwise stated)

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

Param.

No.

(1)

Symbol

Characteristics

Min

Max

Units

Conditions

IC10

IC11

IC15

T

ICL

ICH

ICP

ICMx Input Low Time

25

50

—

ns

Must also meet Parameter IC15

T

ICMx Input High Time

ICMx Input Period

T

Note 1: These parameters are characterized but not tested in manufacturing.

FIGURE 26-8:

MCCP AND SCCP OUTPUT COMPARE x MODE TIMING CHARACTERISTICS

OCMx

OC11

OC10

Note: Refer to Figure 26-2 for load conditions.

TABLE 26-26: MCCP AND SCCP OUTPUT COMPARE x MODE TIMING REQUIREMENTS

 +125°C (unless otherwise stated)

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

Param.

No.

(1)

Symbol

Characteristics

Min

Typ

Max

Units

OC10

OC11

T

OCF

OCMx Output Fall Time

OCMx Output Rise Time

—

10

25

ns

TOCR

Note 1: These parameters are characterized but not tested in manufacturing.

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FIGURE 26-9:

MCCP AND SCCP PWMx MODE TIMING CHARACTERISTICS

OC20

OCFA/OCFB

OC15

OCMx is Tri-Stated

OCMx

TABLE 26-27: MCCP AND SCCP PWM MODE TIMING REQUIREMENTS

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

 +125°C (unless otherwise stated)

Param

No.

(1)

Symbol

Characteristics

Min

Max

Units

OC15

OC20

T

FD

FLT

Fault Input to PWM I/O Change

Fault Input Pulse Width

—

30

—

ns

10

Note 1: These parameters are characterized but not tested in manufacturing.



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FIGURE 26-10:

SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS

SCKx

(CKP = 0)

SP10

SP35

SP10

SCKx

(CKP = 1)

SDOx

SDIx

MSb

LSb

MSb In

SP40 SP41

LSb In

FIGURE 26-11:

SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS

SP36

SCKx

(CKP = 0)

SP10

SCKx

(CKP = 1)

SP35

SDOx

SDIx

MSb

LSb

MSb In

SP41

LSb In

SP40

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TABLE 26-28: SPIx MODULE MASTER MODE TIMING REQUIREMENTS

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

 +125°C (unless otherwise stated)

Param.

No.

(1)

Symbol

Characteristics

Min

Max

Units

SP10

T

SCL, TSC

SCH2DOV,

SCL2DO

H

SCKx Output Low or High Time

10

—

7

ns

SP35

SP36

SP40

SP41

T

SDOx Data Output Valid after SCKx Edge

V

TDOV2SC

,

L

SDOx Data Output Setup to First SCKx Edge

Setup Time of SDIx Data Input to SCKx Edge

Hold Time of SDIx Data Input to SCKx Edge

7

—

ns

TDOV2SC

T

DIV2SCH,

DIV2SC

L

TSCH2DIL,

T

SCL2DI

L

Note 1: These parameters are characterized but not tested in manufacturing.

FIGURE 26-12:

SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS

SSx

SP52

SP50

SCKx

(CKP = 0)

SP71

SP70

SCKx

(CKP = 1)

SP35

SDOx

SDIx

MSb

LSb

SP51

MSb In

SP41

LSb In

SP40



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FIGURE 26-13:

SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS

SP60

SSx

SP52

SP50

SCKx

(CKP = 0)

SP71

SP70

SCKx

(CKP = 1)

SP35

MSb

LSb

SDOx

SDIx

SP51

MSb In

SP41

LSb In

SP40

TABLE 26-29: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS

 +125°C (unless otherwise stated)

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

(1)

Param.No.

Symbol

Characteristics

SCKx Input Low Time

SCKx Input High Time

Min

Max

Units

SP70

SP71

SP35

T

SC

SCH2DOV,

SCL2DO

L

10

—

10

ns

T

H

T

SDOx Data Output Valid after SCKx Edge

Setup Time of SDIx Data Input to SCKx Edge

Hold Time of SDIx Data Input to SCKx Edge

SSx  to SCKx  or SCKx  Input

V

SP40

SP41

SP50

T

DIV2SCH,

DIV2SC

0

7

—

ns

L

T

SCH2DIL,

SCL2DI

L

T

SSL2SCH,

40

T

SSL2SC

L

SP51

SP52

T

SSH2DO

Z

SSx  to SDOx Output High-Impedance

SSx  after SCKx Edge

2.5

10

12

—

ns

TSCH2SS

H

T

SCL2SS

H

SP60

TSSL2DO

V

SDOx Data Output Valid after SSx Edge

—

12.5

ns

Note 1: These parameters are characterized but not tested in manufacturing.

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TABLE 26-30: ADC MODULE INPUTS SPECIFICATIONS

 +125°C (unless otherwise stated)

Operating Conditions: 2.2V  VDD  3.6V, -40°C  T

A

Param

No.

Symbol

Characteristic

Min

Max

Units

Reference Inputs

AD01

AVDD

AVSS

Module VDD Supply

Module VSS Supply

V

DD

V

DD

V

AD02

V

SS

V

SS

Analog Inputs

AD10

AD11

AD12

AD17

V

INH-VINL

Full-Scale Input Span

V

REFL

V

REFH

V



V

IN

Absolute Input Voltage

Absolute VINL Input Voltage

V

SS – 0.3

VDD + 0.3

INL

IN

V

SS – 0.3

V

DD + 0.3

R

Recommended Impedance of Analog

Voltage Source

—

1.2K

TABLE 26-31: ADC ACCURACY AND CONVERSION TIMING REQUIREMENTS FOR 12-BIT MODE⁽¹⁾

< +125°C

Operating Conditions: VDD = AVDD = VREFH  2.9V, AVSS = VREFL = 0V, -40°C < T

A

Param

No.

(2)

Symbol

Characteristic

Min

Typ

Max

Units

ADC Accuracy

AD20B

AD21B

AD22B

AD23B

AD24B

Nr

Resolution

—

–

12

±2.5

±0.75

±2

—

bits

LSb

INL

Integral Nonlinearity

Differential Nonlinearity

Gain Error

±3.5

DNL

+1.75/-0.95

GERR

±3

±2

EOFF

Offset Error

—

±1

Clock Parameters

250

AD50B

T

AD

ADC Clock Period

—

ns

(3)

AD50B

AD56B

T

F

AD

300

—

(3)

CNV

FCNV Throughput Rate

185

222

ksps

Throughput Rate

—

Conversion Rate

AD55B

AD61B

t

CONV

PSS

Conversion Time

—

2

16

—

3

T

AD

t

Sample Start Delay from Setting

Sample bit (SAMP)

TAD

Note 1: Measurements are taken with the external VREF+ and VREF- used as the ADC voltage reference.

2: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

3: 2.2V < (VDD = AVDD = VREFH) < 2.9V, AVSS = VREFL = 0V, -40°C < TA < +125°C

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TABLE 26-32: ADC ACCURACY AND CONVERSION TIMING REQUIREMENTS FOR 10-BIT MODE⁽¹⁾

Operating Conditions: VDD = AVDD = VREFH 2.9V, AVSS = VREFL = 0V, -40°C < T

A

< +125°C

Param

No.

(2)

Symbol

Characteristic

ADC Accuracy

Min

Typ

Max

Units

AD20A

AD21A

AD22A

AD23A

AD24A

Nr

Resolution

—

10

±2.5

±0.75

±2

—

±3.5

bits

LSb

INL

Integral Nonlinearity

Differential Nonlinearity

Gain Error

DNL

+1.75/-0.95

±3

GERR

EOFF

Offset Error

±1

±2

Clock Parameters

250

AD50A

T

AD

PSS

ADC Clock Period

—

3

ns

(3)

AD50A

AD61A

T

300

2

t

Sample Start Delay from Setting

Sample bit (SAMP)

TAD

Conversion Rate

AD55A

AD56A

t

CONV

Conversion Time

Throughput Rate

—

14

—

TAD

F

CNV

250

187

ksps

(3)

AD56A

F

Note 1: Measurements are taken with the external VREF+ and VREF- used as the ADC voltage reference.

2: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

3: 2.2V < (VDD = AVDD = VREFH) < 2.9V, AVSS = VREFL = 0V, -40°C < TA < +125°C

DS60001324C-page 232

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

FIGURE 26-14:

EJTAG TIMING CHARACTERISTICS

T

TCKcyc

T

TCKlow

TCKhigh

T

rf

TCK

T

rf

TMS

TDI

T

rf

Tsetup

Thold

T

rf

TDO

TRST*

T

TRST*low

T

TDOout

T

TDOzstate

Undefined

Defined

T

rf

TABLE 26-33: EJTAG TIMING REQUIREMENTS

 +125°C (unless otherwise stated)

Operating Conditions: 2.0V  VDD  3.6V, -40°C  T

A

Param.

No.

(1)

Symbol

Description

Min

Max

Units

Conditions

EJ1

EJ2

EJ3

EJ4

TTCKCYC

TTCKHIGH

TTCKLOW

TTSETUP

TCK Cycle Time

25

10

5

—

ns

TCK High Time

TCK Low Time

TAP Signals Setup Time before

Rising TCK

EJ5

EJ6

EJ7

T

THOLD

TAP Signals Hold Time after

Rising TCK

3

—

5

ns

TDOOUT

TDO Output Delay Time from

Falling TCK

—

TDOZSTATE TDO 3-State Delay Time from

Falling TCK

5

EJ8

EJ9

TRSTLOW

RF

TRST Low Time

25

—

ns

T

TAP Signals Rise/Fall Time, 

All Input and Output

Note 1: These parameters are characterized but not tested in manufacturing.



2015-2018 Microchip Technology Inc.

DS60001324C-page 233

PIC32MM0064GPL036 FAMILY

NOTES:

DS60001324C-page 234

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

27.0 PACKAGING INFORMATION

27.1 Package Marking Information

20-Lead SSOP

Example

XXXXXXXXXXX

PIC32MM0016

GPL020

1810017

YYWWNNN

20-Lead QFN

Example

XXXXXXXX

YYWWNNN

32MM0016

GPL020

1810017

28-Lead SPDIP

Example

PIC32MM0064GPL028

1810017

XXXXXXXXXXXXXXXXX

YYWWNNN

28-Lead SOIC (7.5 mm)

Example

XXXXXXXXXXXXXXXXXXXX

PIC32MM0032GPL028

1810017

YYWWNNN

Legend: XX...X Customer-specific information

YY

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code



*

All packages are Pb-free

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.



2015-2018 Microchip Technology Inc.

DS60001324C-page 235

PIC32MM0064GPL036 FAMILY

27.1 Package Marking Information (Continued)

28-Lead SSOP

Example

XXXXXXXXXXXX

PIC32MM0064

GPL028

1810017

YYWWNNN

28-Lead QFN

Example

XXXXXXXX

YYWWNNN

32MM0032

GPL028

1810017

28-Lead UQFN

Example

XXXXXXXX

YYWWNNN

32MM0032

GPL028

1810017

36-Lead VQFN

Example

XXXXXXXX

YYWWNNN

32MM0064

GPL036

1810017

40-Lead UQFN

Example

XXXXXXXX

YYWWNNN

32MM0064

GPL036

1810017

DS60001324C-page 236

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

27.2 Package Details

The following sections give the technical details of the packages.

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢐꢌꢑꢒꢇꢎꢓꢅꢉꢉꢇꢔꢕꢋꢉꢌꢑꢄꢇꢖꢎꢎꢗꢇꢘꢇꢙꢚꢛꢁꢇꢓꢓꢇꢜꢝꢆꢞꢇꢟꢎꢎꢔꢈꢠꢇ

ꢡꢝꢋꢄꢢ ꢫꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢜꢉꢖꢬꢉꢠꢌꢅꢋꢐꢉꢗꢃꢄꢠꢇꢓꢅꢜꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢝꢃꢖꢐꢕꢖꢘꢃꢜꢅꢂꢉꢖꢬꢉꢠꢃꢄꢠꢅꢢꢜꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢜꢨꢭꢭꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢜꢁꢖꢕꢑꢭꢜꢉꢖꢬꢉꢠꢃꢄꢠ

D

N

E

E1

NOTE 1

1

2

e

b

c

A2

A

φ

A1

L1

ꢮꢄꢃꢏꢇꢝꢯꢰꢰꢯꢝꢛꢩꢛꢪꢢ

L

ꢚꢃꢑꢌꢄꢇꢃꢕꢄꢅꢰꢃꢑꢃꢏꢇ

ꢝꢯꢱ

ꢱꢲꢝ

ꢝꢡꢳ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢙꢞ

ꢌ

ꢞꢁꢴꢥꢅꢦꢢꢧ

ꢲꢆꢌꢐꢉꢊꢊꢅꢵꢌꢃꢠꢘꢏ

ꢝꢕꢊꢋꢌꢋꢅꢂꢉꢖꢬꢉꢠꢌꢅꢩꢘꢃꢖꢬꢄꢌꢇꢇ

ꢢꢏꢉꢄꢋꢕꢎꢎꢅ

ꢲꢆꢌꢐꢉꢊꢊꢅꢹꢃꢋꢏꢘ

ꢝꢕꢊꢋꢌꢋꢅꢂꢉꢖꢬꢉꢠꢌꢅꢹꢃꢋꢏꢘ

ꢲꢆꢌꢐꢉꢊꢊꢅꢰꢌꢄꢠꢏꢘ

ꢫꢕꢕꢏꢅꢰꢌꢄꢠꢏꢘ

ꢫꢕꢕꢏꢜꢐꢃꢄꢏ

ꢰꢌꢉꢋꢅꢩꢘꢃꢖꢬꢄꢌꢇꢇ

ꢫꢕꢕꢏꢅꢡꢄꢠꢊꢌ

ꢡ

ꢶ

ꢀꢁꢷꢥ

ꢶ

ꢷꢁꢸꢞ

ꢥꢁꢟꢞ

ꢷꢁꢙꢞ

ꢞꢁꢷꢥ

ꢀꢁꢙꢥꢅꢪꢛꢫ

ꢶ

ꢙꢁꢞꢞ

ꢀꢁꢸꢥ

ꢶ

ꢸꢁꢙꢞ

ꢥꢁꢴꢞ

ꢷꢁꢥꢞ

ꢞꢁꢺꢥ

ꢡꢙ

ꢡꢀ

ꢛ

ꢛꢀ

ꢚ

ꢰ

ꢰꢀ

ꢖ

ꢀꢁꢴꢥ

ꢞꢁꢞꢥ

ꢷꢁꢤꢞ

ꢥꢁꢞꢞ

ꢴꢁꢺꢞ

ꢞꢁꢥꢥ

ꢞꢁꢞꢺ

ꢞꢻ

ꢞꢁꢙꢥ

ꢸꢻ

ꢀ

ꢤꢻ

ꢰꢌꢉꢋꢅꢹꢃꢋꢏꢘ

ꢔ

ꢞꢁꢙꢙ

ꢶ

ꢞꢁꢟꢸ

ꢡꢝꢋꢄꢊꢢ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢚꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢚꢅꢉꢄꢋꢅꢛꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢜꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢝꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢜꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢞꢁꢙꢞꢅꢑꢑꢅꢜꢌꢐꢅꢇꢃꢋꢌꢁ

ꢟꢁ ꢚꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢠꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢠꢅꢜꢌꢐꢅꢡꢢꢝꢛꢅꢣꢀꢤꢁꢥꢝꢁ

ꢦꢢꢧꢨ ꢦꢉꢇꢃꢖꢅꢚꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢩꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢪꢛꢫꢨ ꢪꢌꢎꢌꢐꢌꢄꢖꢌꢅꢚꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢜꢈꢐꢜꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ

ꢝꢃꢖꢐꢕꢖꢘꢃꢜ ꢩꢌꢖꢘꢄꢕꢊꢕꢠꢒ ꢚꢐꢉꢗꢃꢄꢠ ꢧꢞꢤꢼꢞꢷꢙꢦ



2015-2018 Microchip Technology Inc.

DS60001324C-page 237

PIC32MM0064GPL036 FAMILY

20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

0.65

0.45

SILK SCREEN

c

Y1

G

X1

E

RECOMMENDED LAND PATTERN

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Contact Pitch

Contact Pad Spacing

Contact Pad Width (X20)

E

C

X1

0.65 BSC

7.20

0.45

1.75

Contact Pad Length (X20)

Distance Between Pads

Y1

G

0.20

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2072B

DS60001324C-page 238

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢣꢕꢅꢆꢇꢤꢉꢅꢋꢥꢇꢡꢝꢇꢃꢄꢅꢆꢇꢈꢅꢍꢒꢅꢦꢄꢇꢖꢧꢃꢗꢇꢘꢇꢨꢩꢨꢩꢁꢚꢪꢇꢓꢓꢇꢜꢝꢆꢞꢇꢟꢣꢤꢡꢠ

ꢡꢝꢋꢄꢢ ꢫꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢜꢉꢖꢬꢉꢠꢌꢅꢋꢐꢉꢗꢃꢄꢠꢇꢓꢅꢜꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢝꢃꢖꢐꢕꢖꢘꢃꢜꢅꢂꢉꢖꢬꢉꢠꢃꢄꢠꢅꢢꢜꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢜꢨꢭꢭꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢜꢁꢖꢕꢑꢭꢜꢉꢖꢬꢉꢠꢃꢄꢠ

ꢅ

D

D2

EXPOSED

PAD

e

E2

E

2

1

b

2

1

K

N

NOTE 1

L

BOTTOM VIEW

TOP VIEW

A

A1

A3

ꢮꢄꢃꢏꢇꢝꢯꢰꢰꢯꢝꢛꢩꢛꢪꢢ

ꢚꢃꢑꢌꢄꢇꢃꢕꢄꢅꢰꢃꢑꢃꢏꢇ

ꢝꢯꢱ

ꢱꢲꢝ

ꢝꢡꢳ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢙꢞ

ꢌ

ꢞꢁꢥꢞꢅꢦꢢꢧ

ꢞꢁꢺꢞ

ꢞꢁꢞꢙ

ꢞꢁꢙꢞꢅꢪꢛꢫ

ꢤꢁꢞꢞꢅꢦꢢꢧ

ꢙꢁꢷꢞ

ꢤꢁꢞꢞꢅꢦꢢꢧ

ꢙꢁꢷꢞ

ꢲꢆꢌꢐꢉꢊꢊꢅꢵꢌꢃꢠꢘꢏ

ꢢꢏꢉꢄꢋꢕꢎꢎꢅ

ꢧꢕꢄꢏꢉꢖꢏꢅꢩꢘꢃꢖꢬꢄꢌꢇꢇ

ꢲꢆꢌꢐꢉꢊꢊꢅꢹꢃꢋꢏꢘ

ꢛꢍꢜꢕꢇꢌꢋꢅꢂꢉꢋꢅꢹꢃꢋꢏꢘ

ꢲꢆꢌꢐꢉꢊꢊꢅꢰꢌꢄꢠꢏꢘ

ꢛꢍꢜꢕꢇꢌꢋꢅꢂꢉꢋꢅꢰꢌꢄꢠꢏꢘ

ꢧꢕꢄꢏꢉꢖꢏꢅꢹꢃꢋꢏꢘ

ꢧꢕꢄꢏꢉꢖꢏꢅꢰꢌꢄꢠꢏꢘ

ꢧꢕꢄꢏꢉꢖꢏꢼꢏꢕꢼꢛꢍꢜꢕꢇꢌꢋꢅꢂꢉꢋ

ꢡ

ꢞꢁꢸꢞ

ꢞꢁꢞꢞ

ꢀꢁꢞꢞ

ꢞꢁꢞꢥ

ꢡꢀ

ꢡꢟ

ꢛ

ꢛꢙ

ꢚ

ꢚꢙ

ꢔ

ꢰ

ꢙꢁꢴꢞ

ꢙꢁꢸꢞ

ꢙꢁꢴꢞ

ꢞꢁꢀꢸ

ꢞꢁꢟꢞ

ꢞꢁꢙꢞ

ꢙꢁꢸꢞ

ꢞꢁꢟꢞ

ꢞꢁꢥꢞ

ꢶ

ꢞꢁꢙꢥ

ꢞꢁꢤꢞ

ꢶ

ꢽ

ꢡꢝꢋꢄꢊꢢ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢂꢉꢖꢬꢉꢠꢌꢅꢃꢇꢅꢇꢉꢗꢅꢇꢃꢄꢠꢈꢊꢉꢏꢌꢋꢁ

ꢟꢁ ꢚꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢠꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢠꢅꢜꢌꢐꢅꢡꢢꢝꢛꢅꢣꢀꢤꢁꢥꢝꢁ

ꢦꢢꢧꢨ ꢦꢉꢇꢃꢖꢅꢚꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢩꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢪꢛꢫꢨ ꢪꢌꢎꢌꢐꢌꢄꢖꢌꢅꢚꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢜꢈꢐꢜꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ

ꢝꢃꢖꢐꢕꢖꢘꢃꢜ ꢩꢌꢖꢘꢄꢕꢊꢕꢠꢒ ꢚꢐꢉꢗꢃꢄꢠ ꢧꢞꢤꢼꢀꢙꢴꢦ



2015-2018 Microchip Technology Inc.

DS60001324C-page 239

PIC32MM0064GPL036 FAMILY

ꢡꢝꢋꢄꢢ ꢫꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢜꢉꢖꢬꢉꢠꢌꢅꢋꢐꢉꢗꢃꢄꢠꢇꢓꢅꢜꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢝꢃꢖꢐꢕꢖꢘꢃꢜꢅꢂꢉꢖꢬꢉꢠꢃꢄꢠꢅꢢꢜꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢜꢨꢭꢭꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢜꢁꢖꢕꢑꢭꢜꢉꢖꢬꢉꢠꢃꢄꢠ

DS60001324C-page 240

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

ꢀꢫꢂꢃꢄꢅꢆꢇꢎꢒꢌꢑꢑꢞꢇꢈꢉꢅꢊꢋꢌꢍꢇꢬꢕꢅꢉꢇꢭꢑꢂꢃꢌꢑꢄꢇꢖꢎꢈꢗꢇꢘꢇꢛꢁꢁꢇꢓꢌꢉꢇꢜꢝꢆꢞꢇꢟꢎꢈꢬꢭꢈꢠ

ꢡꢝꢋꢄꢢ ꢫꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢜꢉꢖꢬꢉꢠꢌꢅꢋꢐꢉꢗꢃꢄꢠꢇꢓꢅꢜꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢝꢃꢖꢐꢕꢖꢘꢃꢜꢅꢂꢉꢖꢬꢉꢠꢃꢄꢠꢅꢢꢜꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢜꢨꢭꢭꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢜꢁꢖꢕꢑꢭꢜꢉꢖꢬꢉꢠꢃꢄꢠ

N

NOTE 1

E1

1

2 3

D

E

A2

A

L

c

b1

A1

b

e

eB

ꢮꢄꢃꢏꢇꢯꢱꢧꢵꢛꢢ

ꢚꢃꢑꢌꢄꢇꢃꢕꢄꢅꢰꢃꢑꢃꢏꢇ

ꢙꢸ

ꢝꢯꢱ

ꢱꢲꢝ

ꢝꢡꢳ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢩꢕꢜꢅꢏꢕꢅꢢꢌꢉꢏꢃꢄꢠꢅꢂꢊꢉꢄꢌ

ꢝꢕꢊꢋꢌꢋꢅꢂꢉꢖꢬꢉꢠꢌꢅꢩꢘꢃꢖꢬꢄꢌꢇꢇ

ꢦꢉꢇꢌꢅꢏꢕꢅꢢꢌꢉꢏꢃꢄꢠꢅꢂꢊꢉꢄꢌ

ꢢꢘꢕꢈꢊꢋꢌꢐꢅꢏꢕꢅꢢꢘꢕꢈꢊꢋꢌꢐꢅꢹꢃꢋꢏꢘ

ꢝꢕꢊꢋꢌꢋꢅꢂꢉꢖꢬꢉꢠꢌꢅꢹꢃꢋꢏꢘ

ꢲꢆꢌꢐꢉꢊꢊꢅꢰꢌꢄꢠꢏꢘ

ꢩꢃꢜꢅꢏꢕꢅꢢꢌꢉꢏꢃꢄꢠꢅꢂꢊꢉꢄꢌ

ꢰꢌꢉꢋꢅꢩꢘꢃꢖꢬꢄꢌꢇꢇ

ꢮꢜꢜꢌꢐꢅꢰꢌꢉꢋꢅꢹꢃꢋꢏꢘ

ꢰꢕꢗꢌꢐꢅꢰꢌꢉꢋꢅꢹꢃꢋꢏꢘ

ꢲꢆꢌꢐꢉꢊꢊꢅꢪꢕꢗꢅꢢꢜꢉꢖꢃꢄꢠꢅꢅꢾ

ꢌ

ꢡ

ꢡꢙ

ꢡꢀ

ꢛ

ꢛꢀ

ꢚ

ꢰ

ꢁꢀꢞꢞꢅꢦꢢꢧ

ꢶ

ꢁꢀꢟꢥ

ꢶ

ꢁꢟꢀꢞ

ꢁꢙꢸꢥ

ꢀꢁꢟꢴꢥ

ꢁꢀꢟꢞ

ꢁꢞꢀꢞ

ꢁꢞꢥꢞ

ꢁꢞꢀꢸ

ꢶ

ꢁꢙꢞꢞ

ꢁꢀꢥꢞ

ꢶ

ꢁꢀꢙꢞ

ꢁꢞꢀꢥ

ꢁꢙꢺꢞ

ꢁꢙꢤꢞ

ꢀꢁꢟꢤꢥ

ꢁꢀꢀꢞ

ꢁꢞꢞꢸ

ꢁꢞꢤꢞ

ꢁꢞꢀꢤ

ꢶ

ꢁꢟꢟꢥ

ꢁꢙꢺꢥ

ꢀꢁꢤꢞꢞ

ꢁꢀꢥꢞ

ꢁꢞꢀꢥ

ꢁꢞꢷꢞ

ꢁꢞꢙꢙ

ꢁꢤꢟꢞ

ꢖ

ꢔꢀ

ꢔ

ꢌꢦ

ꢡꢝꢋꢄꢊꢢ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢾꢅꢢꢃꢠꢄꢃꢎꢃꢖꢉꢄꢏꢅꢧꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ

ꢟꢁ ꢚꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢚꢅꢉꢄꢋꢅꢛꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢜꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢝꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢜꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢁꢞꢀꢞꢿꢅꢜꢌꢐꢅꢇꢃꢋꢌꢁ

ꢤꢁ ꢚꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢠꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢠꢅꢜꢌꢐꢅꢡꢢꢝꢛꢅꢣꢀꢤꢁꢥꢝꢁ

ꢦꢢꢧꢨ ꢦꢉꢇꢃꢖꢅꢚꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢩꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢝꢃꢖꢐꢕꢖꢘꢃꢜ ꢩꢌꢖꢘꢄꢕꢊꢕꢠꢒ ꢚꢐꢉꢗꢃꢄꢠ ꢧꢞꢤꢼꢞꢷꢞꢦ



2015-2018 Microchip Technology Inc.

DS60001324C-page 241

PIC32MM0064GPL036 FAMILY

ꢀꢫꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢐꢌꢑꢒꢇꢎꢓꢅꢉꢉꢇꢔꢕꢋꢉꢌꢑꢄꢇꢖꢎꢎꢗꢇꢘꢇꢙꢚꢛꢁꢇꢓꢓꢇꢜꢝꢆꢞꢇꢟꢎꢎꢔꢈꢠ

ꢡꢝꢋꢄꢢ ꢫꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢜꢉꢖꢬꢉꢠꢌꢅꢋꢐꢉꢗꢃꢄꢠꢇꢓꢅꢜꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢝꢃꢖꢐꢕꢖꢘꢃꢜꢅꢂꢉꢖꢬꢉꢠꢃꢄꢠꢅꢢꢜꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢜꢨꢭꢭꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢜꢁꢖꢕꢑꢭꢜꢉꢖꢬꢉꢠꢃꢄꢠ

D

N

E

E1

1

2

b

NOTE 1

e

c

A2

A

φ

A1

L

L1

ꢮꢄꢃꢏꢇꢝꢯꢰꢰꢯꢝꢛꢩꢛꢪꢢ

ꢚꢃꢑꢌꢄꢇꢃꢕꢄꢅꢰꢃꢑꢃꢏꢇ

ꢝꢯꢱ

ꢱꢲꢝ

ꢝꢡꢳ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢙꢸ

ꢌ

ꢞꢁꢴꢥꢅꢦꢢꢧ

ꢲꢆꢌꢐꢉꢊꢊꢅꢵꢌꢃꢠꢘꢏ

ꢝꢕꢊꢋꢌꢋꢅꢂꢉꢖꢬꢉꢠꢌꢅꢩꢘꢃꢖꢬꢄꢌꢇꢇ

ꢢꢏꢉꢄꢋꢕꢎꢎꢅ

ꢲꢆꢌꢐꢉꢊꢊꢅꢹꢃꢋꢏꢘ

ꢝꢕꢊꢋꢌꢋꢅꢂꢉꢖꢬꢉꢠꢌꢅꢹꢃꢋꢏꢘ

ꢲꢆꢌꢐꢉꢊꢊꢅꢰꢌꢄꢠꢏꢘ

ꢫꢕꢕꢏꢅꢰꢌꢄꢠꢏꢘ

ꢫꢕꢕꢏꢜꢐꢃꢄꢏ

ꢰꢌꢉꢋꢅꢩꢘꢃꢖꢬꢄꢌꢇꢇ

ꢫꢕꢕꢏꢅꢡꢄꢠꢊꢌ

ꢡ

ꢶ

ꢀꢁꢷꢥ

ꢶ

ꢷꢁꢸꢞ

ꢥꢁꢟꢞ

ꢀꢞꢁꢙꢞ

ꢞꢁꢷꢥ

ꢀꢁꢙꢥꢅꢪꢛꢫ

ꢶ

ꢙꢁꢞꢞ

ꢀꢁꢸꢥ

ꢶ

ꢸꢁꢙꢞ

ꢥꢁꢴꢞ

ꢀꢞꢁꢥꢞ

ꢞꢁꢺꢥ

ꢡꢙ

ꢡꢀ

ꢛ

ꢛꢀ

ꢚ

ꢰ

ꢰꢀ

ꢖ

ꢀꢁꢴꢥ

ꢞꢁꢞꢥ

ꢷꢁꢤꢞ

ꢥꢁꢞꢞ

ꢺꢁꢺꢞ

ꢞꢁꢥꢥ

ꢞꢁꢞꢺ

ꢞꢻ

ꢞꢁꢙꢥ

ꢸꢻ

ꢀ

ꢤꢻ

ꢰꢌꢉꢋꢅꢹꢃꢋꢏꢘ

ꢔ

ꢞꢁꢙꢙ

ꢶ

ꢞꢁꢟꢸ

ꢡꢝꢋꢄꢊꢢ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢚꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢚꢅꢉꢄꢋꢅꢛꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢜꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢝꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢜꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢞꢁꢙꢞꢅꢑꢑꢅꢜꢌꢐꢅꢇꢃꢋꢌꢁ

ꢟꢁ ꢚꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢠꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢠꢅꢜꢌꢐꢅꢡꢢꢝꢛꢅꢣꢀꢤꢁꢥꢝꢁ

ꢦꢢꢧꢨ ꢦꢉꢇꢃꢖꢅꢚꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢩꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢪꢛꢫꢨ ꢪꢌꢎꢌꢐꢌꢄꢖꢌꢅꢚꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢜꢈꢐꢜꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ

ꢝꢃꢖꢐꢕꢖꢘꢃꢜ ꢩꢌꢖꢘꢄꢕꢊꢕꢠꢒ ꢚꢐꢉꢗꢃꢄꢠ ꢧꢞꢤꢼꢞꢷꢟꢦ

DS60001324C-page 242

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging



2015-2018 Microchip Technology Inc.

DS60001324C-page 243

PIC32MM0064GPL036 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS60001324C-page 244

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging



2015-2018 Microchip Technology Inc.

DS60001324C-page 245

PIC32MM0064GPL036 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS60001324C-page 246

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY



2015-2018 Microchip Technology Inc.

DS60001324C-page 247

PIC32MM0064GPL036 FAMILY

DS60001324C-page 248

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

ꢀꢫꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢣꢕꢅꢆꢇꢤꢉꢅꢋꢥꢇꢡꢝꢇꢃꢄꢅꢆꢇꢈꢅꢍꢒꢅꢦꢄꢇꢖꢧꢃꢗꢇꢘꢇꢮꢩꢮꢇꢓꢓꢇꢜꢝꢆꢞꢇꢟꢣꢤꢡꢠ

ꢯꢌꢋꢏꢇꢁꢚꢙꢙꢇꢓꢓꢇꢰꢝꢑꢋꢅꢍꢋꢇꢃꢄꢑꢦꢋꢏ

ꢡꢝꢋꢄꢢ ꢫꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢜꢉꢖꢬꢉꢠꢌꢅꢋꢐꢉꢗꢃꢄꢠꢇꢓꢅꢜꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢝꢃꢖꢐꢕꢖꢘꢃꢜꢅꢂꢉꢖꢬꢉꢠꢃꢄꢠꢅꢢꢜꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢜꢨꢭꢭꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢜꢁꢖꢕꢑꢭꢜꢉꢖꢬꢉꢠꢃꢄꢠ



2015-2018 Microchip Technology Inc.

DS60001324C-page 249

PIC32MM0064GPL036 FAMILY

28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M6) - 4x4x0.6 mm Body [UQFN]

With Corner Anchors

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

N

NOTE 1

1

2

E

(DATUM B)

(DATUM A)

2X

0.10 C

2X

TOP VIEW

0.10 C

A1

0.10 C

0.08 C

C

A

SEATING

PLANE

28X

(A3)

SIDE VIEW

0.10

C A B

4x b2

4x b1

D2

4x b2

0.10

C A B

E2

NOTE 1

e

2

1

K

N

4x b1

L

28X b

0.07

0.05

C A B

C

e

BOTTOM VIEW

Microchip Technology Drawing C04-333-M6 Rev B Sheet 1 of 2

DS60001324C-page 250

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M6) - 4x4x0.6 mm Body [UQFN]

With Corner Anchors

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Pins

Pitch

Overall Height

Standoff

Terminal Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Terminal Width

Corner Anchor Pad

Corner Pad, Metal Free Zone

Terminal Length

Terminal-to-Exposed-Pad

N

28

0.40 BSC

-

e

A

A1

A3

E

E2

D

D2

b

b1

-

0.60

0.05

0.00

0.02

0.152 REF

4.00 BSC

1.90

4.00 BSC

1.90

1.80

2.00

1.80

0.15

0.40

0.18

0.30

-

2.00

0.25

0.50

0.28

0.50

-

0.20

0.45

0.23

0.45

b2

L

K

0.60

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-333-M6 Rev A Sheet 2 of 2

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28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M6) - 4x4x0.6 mm Body [UQFN]

With Corner Anchors

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

C1

X2

EV

28

G3

1

2

ØV

G2

C2 Y2 EV

G1

Y1

Y3

X1

X3

SILK SCREEN

E

RECOMMENDED LAND PATTERN

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Contact Pitch

E

0.40 BSC

Center Pad Width

Center Pad Length

Contact Pad Spacing

Contact Pad Width (X28)

Contact Pad Length (X28)

Contact Pad to Center Pad (X28)

Contact Pad to Pad (X24)

Contact Pad to Corner Pad (X8)

Corner Anchor Width (X4)

Corner Anchor Length (X4)

Thermal Via Diameter

X2

Y2

C1

C2

X1

Y1

G1

G2

G3

X3

Y3

V

2.00

3.90

0.20

0.85

0.52

0.20

0.78

0.30

1.00

Thermal Via Pitch

EV

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2333-M6 Rev B

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36-Terminal Very Thin Plastic Quad Flatpack No-Lead (M2) - 6x6x1.0mm Body [VQFN]

SMSC Legacy "Sawn Quad Flatpack No-Lead [SQFN]"

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

N

NOTE 1

1

2

(DATUM B)

(DATUM A)

2X

0.10 C

2X

TOP VIEW

0.10 C

A1

0.10 C

C

A

SEATING

PLANE

36X

0.08 C

SIDE VIEW

(A3)

0.10

C A B

D2

0.10

C A B

E2

K

2

1

NOTE 1

N

L

36X b

0.10

0.05

C A B

C

e

BOTTOM VIEW

Microchip Technology Drawing C04-272B-M2 Sheet 1 of 2

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36-Terminal Very Thin Plastic Quad Flatpack No-Lead (M2) - 6x6x1.0mm Body [VQFN]

SMSC Legacy "Sawn Quad Flatpack No-Lead [SQFN]"

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Terminals

Pitch

Overall Height

Standoff

Terminal Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Terminal Width

Terminal Length

N

36

0.50 BSC

0.90

e

A

A1

A3

E

E2

D

D2

b

L

0.80

0.00

1.00

0.05

0.02

0.20 REF

6.00 BSC

3.70

6.00 BSC

3.70

0.25

0.60

0.55

3.60

3.80

3.60

0.18

0.50

0.45

3.80

0.30

0.75

-

Terminal-to-Exposed-Pad

K

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-272B-M2 Sheet 2 of 2

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36-Terminal Very Thin Plastic Quad Flatpack No-Lead (M2) - 6x6x0.9 mm Body [VQFN]

SMSC Legacy "Sawn Quad Flatpack No-Lead [SQFN]"

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

C1

X2

EV

36

G2

1

2

Y2

ØV

EV

C2

G1

Y1

X1

E

SILK SCREEN

RECOMMENDED LAND PATTERN

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Contact Pitch

E

0.50 BSC

Optional Center Pad Width

Optional Center Pad Length

Contact Pad Spacing

Contact Pad Width (X36)

Contact Pad Length (X36)

X2

Y2

C1

C2

X1

Y1

3.80

5.60

0.30

1.10

Contact Pad to Center Pad (X36)

Space Between Contact Pads (X32)

Thermal Via Diameter

G1

G2

V

0.35

0.20

0.30

1.00

Thermal Via Pitch

EV

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during

reflow process

Microchip Technology Drawing C04-2272B-M2

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Revision C (April 2018)

APPENDIX A: REVISION HISTORY

This revision incorporates the following updates:

Adds +125ºC specifications.

• Sections:

Revision A (February 2015)

This is the initial version of the document.

- Updates “Operating Conditions”,

“Peripheral Features” and “Analog

Features” on the first two pages.

Revision B (May 2016)

This revision incorporates the following updates:

• Registers:

- Updates Section 2.5 “Voltage Regulator

Pin (VCAP)”, Section 9.5 “I/O Port Write/

Read Timing”, Section 12.1 “Introduction”

and Section 26.0 “Electrical

- Updates Register 5-1, Register 5-3,

Register 5-6, Register 5-7, Register 6-3,

Register 6-4, Register 7-2, Register 8-2,

Register 8-3, Register 8-5, Register 8-6,

Register 11-1, Register 13-1, Register 14-1,

Register 15-1, Register 15-5, Register 15-6,

Register 16-1, Register 16-2, Register 16-3,

Register 16-5, Register 18-2, Register 19-1,

Register 19-2 and Register 23-7

Characteristics”.

- Adds Section 9.2 “Parallel I/O (PIO) Ports”.

• Tables:

- Updates Table 8-1, Table 26-1, Table 26-3,

Table 26-4, Table 26-5, Table 26-6, 

Table 26-7, Table 26-8, Table 26-9, 

Table 26-10, Table 26-11, Table 26-12,

Table 26-13, Table 26-14, Table 26-15,

Table 26-17, Table 26-18, Table 26-19,

Table 26-20, Table 26-21, Table 26-22,

Table 26-23, Table 26-24, Table 26-25,

Table 26-26, Table 26-27, Table 26-28,

Table 26-29, Table 26-30, Table 26-31,

Table 26-32 and Table 26-33.

• Tables:

- Updates Table 1-1, Table 5-1, Table 6-1,Table 7-2,

Table 7-3, Table 9-3, Table 9-7, Table 15-1,

Table 16-1, Table 19-1, Table 22-1, Table 23-4,

Table 23-5 Table 26-2, Table 26-3, Table 26-4

and Table 26-6 through Table 26-33

- Adds Table 23-8

• Figures:

• Registers:

- Updates Figure 1-1, Figure 3-1, Figure 8-1,

Figure 10-1, Figure 14-1, Figure 13-1,

Figure 14-1, Figure 14-1, Figure 15-1,

Figure 17-1, Figure 18-1, Figure 18-3,

Figure 26-1, Figure 26-3, Figure 26-4,

Figure 26-9, Figure 26-10, Figure 26-11 and

Figure 26-12

- Updates Register 5-7, Register 6-3,

Register 8-1, Register 8-3, Register 11-1,

Register 12-1, Register 15-1 and

Register 16-1.

- Adds Register 8-2.

• Figures:

- Updates Figure 8-2.

• Examples:

• Updates pin function descriptions in Section 1.0

“Device Overview”

- Adds Example 11-1.

- Updates Example 8-1.

• Updates text in Section 9.6 “Input Change Notifi-

cation (ICN)”, Section 9.8.4 “Input Mapping”,

Section 23.7 “Unique Device Identifier (UDID)”,

Section 22.5 “Low-Power Brown-out Reset”

and Section 27.0 “Packaging Information”

• Adds Section 5.1 “Flash Controller Registers

Write Protection”, Section 8.0 “Oscillator Con-

figuration”, Section 23.4 “System Registers

Write Protection”, reference to Section 22.1

“Sleep Mode”, Section 22.2 “Idle Mode” and

Section 23.8 “Reserved Registers”

• Updates the Absolute Maximum Ratings in

Section 26.0 “Electrical Characteristics”

This revision also includes minor typographical and

formatting changes throughout the data sheet text.

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NOTES:

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C

INDEX

C Compilers

A

MPLAB XC Compilers .............................................. 202

AC Characteristics

Capture/Compare/PWM/Timer Modules 

10-Bit ADC Accuracy and Conversion

Requirements ................................................... 232

12-Bit ADC Accuracy and Conversion



(MCCP, SCCP)........................................................... 97

CLC



Control Registers...................................................... 156

Requirements ................................................... 231

ADC Inputs Specifications ........................................ 231

and Timing Parameters............................................. 219

Capacitive Loading on Output Pins........................... 219

CLKO and I/O Timing Requirements ........................ 222

EJTAG Requirements............................................... 233

External Clock Timing Requirements........................ 220

Internal Oscillator Accuracy ...................................... 221

Internal Oscillator Start-up Time ............................... 221

Load Conditions for Device Timing........................... 219

CLR, SET and INV Registers ............................................. 80

Code Examples

Basic Clock Switching ................................................ 66

Sequence to Clear the WDT....................................... 93

UART2 RX Input Assignment to RP9/RB14 Pin......... 82

UART2 TX Output Assignment to



RP13/RB13 Pin .................................................. 83

Code Execution from RAM ............................................... 183

Comparator....................................................................... 165

Configurable Logic Cell (CLC).......................................... 153

Configurable Logic Cell. See CLC.

Configuration Bits ............................................................. 183

Control Digital-to-Analog Converter (CDAC) .................... 171

Control Digital-to-Analog Converter. See CDAC.

CP0 Register 16, Select 1) ................................................. 30

CP0 Register 16, Select 3) ................................................. 31

CP0 Register 16, Select 5) ................................................. 32

CPU

Architecture Overview ................................................ 25

Coprocessor 0 Registers............................................ 27

Core Exception Types ................................................ 52

EJTAG Debug Support............................................... 28

Exceptions, Interrupt Controller.................................. 51

Interrupts .................................................................... 54

Power Management ................................................... 28

CPU Module ....................................................................... 23

Customer Change Notification Service............................. 264

Customer Notification Service .......................................... 264

Customer Support............................................................. 264

Cyclic Redundancy Check. See CRC.

MCCP/SCCP Input Capture x Mode

Requirements ................................................... 226

MCCP/SCCP Output Compare x Mode



Requirements ................................................... 226

MCCP/SCCP PWM Mode Requirements ................. 227

MCCP/SCCP Timer1 External Clock Timing



Characteristics.................................................. 224

MCCP/SCCP Timing Requirements ......................... 225

PLL Clock Timing Specifications............................... 221

Reset, Brown-out Reset and Sleep Modes



Timing Specifications........................................ 223

SPIx Master Mode Requirements............................. 229

SPIx Module Slave Mode Timing Requirements ...... 230

ADC Converter

Control Registers ...................................................... 136

Introduction ............................................................... 135

Assembler

MPASM Assembler................................................... 202

B

Band Gap Voltage Reference ........................................... 184

Block Diagrams

D

ADC Module.............................................................. 135

CDAC Module........................................................... 171

CLCx Input Source Selection.................................... 155

CLCx Logic Function Combinatorial Options............ 154

CLCx Module ............................................................ 153

CPU Exceptions and Interrupt Controller.................... 51

CRC Module ............................................................. 149

Dual Comparator Module.......................................... 165

High/Low-Voltage Detect (HLVD) ............................. 175

MCCP/SCCP Module.................................................. 98

MCLR Pin Connections............................................... 20

Microprocessor Core................................................... 24

Multiplexing Remappable Output for RP1................... 83

Oscillator Circuit Placement........................................ 22

Oscillator System........................................................ 67

PIC32MM0064GPL036 Family ................................... 13

Recommended Minimum Connection......................... 20

Reference Oscillator Clock ......................................... 68

Remappable Input Example for U2RX........................ 82

Reset System.............................................................. 45

RTCC Module ........................................................... 125

DC Characteristics

Comparator Specifications ....................................... 218

High/Low-Voltage Detect.......................................... 217

I/O Pin Input Injection Current Specifications........... 215

I/O Pin Input Specifications ...................................... 214

I/O Pin Output Specifications.................................... 216

Idle Current (IIDLE).................................................... 211

Incremental Peripheral

 Current ............................. 213

Internal Voltage Regulator Specifications................. 217

Operating Current (IDD) ............................................ 210

Operating Voltage Specifications ............................. 209

Power-Down Current (IPD)........................................ 212

Program Flash Memory Specifications..................... 216

Thermal Operating Conditions.................................. 208

Voltage Reference (CDAC) Specifications............... 218

Demo/Development Boards, Evaluation and



Starter Kits................................................................ 204

Development Support....................................................... 201

Third-Party Tools...................................................... 204

Device IDs ........................................................................ 183

E

2

SPI/I S Module ......................................................... 111

Electrical Characteristics .................................................. 207

Absolute Maximum Ratings...................................... 207

V/F Graph (Industrial)............................................... 208

Errata.................................................................................. 10

Timer1 Module............................................................ 89

Typical Shared Port Structure..................................... 79

UARTx Module.......................................................... 119

Watchdog Timer (WDT).............................................. 93

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F

P

Fail-Safe Clock Monitor (FSCM) .........................................65

Flash Program Memory.......................................................37

Write Protection ..........................................................37

Package Thermal Resistance........................................... 209

Packaging......................................................................... 235

Details....................................................................... 237

Marking..................................................................... 235

Peripheral Pin Select (PPS)................................................ 81

PICkit 3 In-Circuit Debugger/Programmer........................ 203

Pinout Description............................................................... 14

Power-Saving Features .................................................... 179

Idle Mode.................................................................. 179

Low-Power Brown-out Reset.................................... 181

On-Chip Voltage Regulator Low-Power Modes........ 181

Regulator Retention.......................................... 181

Regulator Standby............................................ 181

Peripheral Module Disable........................................ 180

Bits and Locations ............................................ 180

Sleep Mode .............................................................. 179

PPS

Available Peripherals.................................................. 81

Available Pins ............................................................. 81

Controlling .................................................................. 81

Controlling Configuration Changes............................. 83

Input Mapping............................................................. 82

Input Pin Selection...................................................... 82

Output Mapping .......................................................... 83

Output Pin Selection................................................... 83

Programming and Diagnostics.......................................... 184

G

Getting Started with PIC32 MCUs.......................................19

Connection Requirements ..........................................19

Decoupling Capacitors................................................19

External Oscillator Pins...............................................22

ICSP Pins....................................................................22

Internal Voltage Regulator Capacitor (VCAP) ..............20

JTAG...........................................................................22

Master Clear (MCLR) Pin............................................20

Unused I/Os................................................................22

Voltage Regulator Pin (VCAP) .....................................21

H

High/Low-Voltage Detect (HLVD) .....................................175

High/Low-Voltage Detect. See HLVD.

I

I/O Ports..............................................................................79

Analog/Digital Port Pins Configuration........................80

Open-Drain Configuration ...........................................80

Parallel I/O (PIO).........................................................80

Pull-up/Pull-Down Pins ...............................................81

Write/Read Timing ......................................................80

Input Change Notification (ICN) ..........................................80

Instruction Set ...................................................................205

R

Real-Time Clock and Calendar (RTCC) ........................... 125

Real-Time Clock and Calendar. See RTCC.

Register Maps

2

Inter-IC Sound. See I S.

Internet Address................................................................264

ADC .......................................................................... 137

Alternate Configuration Words Summary ................. 186

Band Gap ................................................................. 197

CDAC ....................................................................... 172

CLC1 and CLC2 ....................................................... 157

Comparator 1 and 2.................................................. 166

Configurations Words Summary............................... 185

CRC.......................................................................... 150

Flash Controller .......................................................... 38

High/Low Voltage Detect.......................................... 176

Interrupts .................................................................... 56

MCCP/SCCP .............................................................. 99

Oscillator Configuration .............................................. 69

Peripheral Module Disable........................................ 182

Peripheral Pin Select .................................................. 87

PORTA ....................................................................... 84

PORTB ....................................................................... 85

PORTC ....................................................................... 86

M

MCCP/SCCP

Introduction .................................................................97

Registers.....................................................................98

Memory Maps

Devices with 16 Kbytes Program Memory ..................34

Devices with 32 Kbytes Program Memory ..................35

Devices with 64 Kbytes Program Memory ..................36

Memory Organization..........................................................33

Alternate Configuration Bits Space .............................33

Microchip Internet Web Site..............................................264

®

MIPS32 microAptiv™ UC Core Configuration ..................28

MPLAB Assembler, Linker, Librarian ................................202

MPLAB ICD 3 In-Circuit Debugger....................................203

MPLAB PM3 Device Programmer.....................................203

MPLAB REAL ICE In-Circuit Emulator System.................203

MPLAB X Integrated Development



Environment Software...............................................201

MPLAB X SIM Software Simulator....................................203

MPLIB Object Librarian.....................................................202

MPLINK Object Linker.......................................................202

Multiply/Divide Unit Latencies and Repeat Rates ...............25

RAM Configuration, Device ID and



System Lock..................................................... 194

Reserved Registers.................................................. 199

Resets ........................................................................ 46

RTCC........................................................................ 126

SPI1 and SPI2 .......................................................... 112

Timer1 ........................................................................ 90

UART1 and UART2 .................................................. 120

UDID......................................................................... 199

Watchdog Timer ......................................................... 94

O

Oscillator Configuration.......................................................65

Clock Switching...........................................................65

Sequence............................................................66

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Registers

AD1CHIT (ADC Compare Hit) .................................. 147

AD1CHS (ADC Input Select) .................................... 145

PRISS (Priority Shadow Select) ................................. 59

PWRCON (Power Control)......................................... 50

RCON (Reset Control)................................................ 47

REFO1CON (Reference Oscillator Control)............... 73

REFO1TRIM (Reference Oscillator Trim)................... 75

AD1CON1 (ADC Control 1) ...................................... 139

AD1CON2 (ADC Control 2) ...................................... 141

AD1CON3 (ADC Control 3) ...................................... 142

AD1CON5 (ADC Control 5) ...................................... 143

AD1CSS (ADC Input Scan Select) ........................... 146

ALMDATE (Alarm Date)............................................ 133

ANCFG (Band Gap Control) ..................................... 198

RNMICON (Non-Maskable Interrupt (NMI)



Control)............................................................... 49

RSWRST (Software Reset)........................................ 48

RTCCON1 (RTCC Control 1) ................................... 127

RTCCON2 (RTCC Control 2) ................................... 129

RTCDATE (RTCC Date)........................................... 132

RTCSTAT (RTCC Status Register).......................... 130

RTCTIME/ALMTIME (RTCC/Alarm Time)................ 131

SPIxCON (SPIx Control) .......................................... 113

SPIxCON2 (SPIx Control 2) ..................................... 116

SPIxSTAT (SPIx Status)........................................... 117

SPLLCON (System PLL Control) ............................... 72

SYSKEY (System Unlock)........................................ 196

T1CON (Timer1 Control) ............................................ 91

UxMODE (UARTx Mode) ......................................... 121

UxSTA (UARTx Status and Control) ........................ 123

WDTCON (Watchdog Timer Control)......................... 95

Reserved Registers.......................................................... 184

Resets ................................................................................ 45

Brown-out Reset (BOR).............................................. 45

Configuration Mismatch Reset (CMR)........................ 45

Master Clear Reset Pin (MCLR)................................. 45

Power-on Reset (POR)............................................... 45

Software Reset (SWR) ............................................... 45

Watchdog Timer Reset (WDTR)................................. 45

Revision History................................................................ 259

CCPxCON1 (Capture/Compare/PWMx

Control 1).......................................................... 101

CCPxCON2 (Capture/Compare/PWMx

Control 2).......................................................... 104

CCPxCON3 (Capture/Compare/PWMx



Control 3).......................................................... 106

CCPxSTAT (Capture/Compare/PWMx Status)......... 108

CFGCON (Configuration Control)............................. 195

CLCxCON (CLCx Control)........................................ 158

CLCxGLS (CLCx Gate Logic Input Select)............... 162

CLCxSEL (CLCx Input MUX Select)......................... 160

CLKSTAT (Clock Status) ............................................ 76

CMSTAT (Comparator Status).................................. 167

CMxCON (Comparator x Control)............................. 168

CNCONx (Change Notification Control

for PORTx).......................................................... 88

CONFIG

(CP0 Register 16, Select 0) ................................ 29

CONFIG1

(Configuration Register 1.................................... 30

CONFIG3

(Configuration Register 3.................................... 31

CONFIG5



S

Serial Peripheral Interface (SPI)....................................... 111

Serial Peripheral Interface. See SPI.

Special Features............................................................... 183

(Configuration Register 5.................................... 32

CRCCON (CRC Control) .......................................... 151

CRCXOR (CRC XOR) .............................................. 152

DAC1CON (CDAC Control) ...................................... 173

DEVID (Device ID).................................................... 196

T

Timer1 Module.................................................................... 89

Timing Diagrams

FDEVOPT/AFDEVOPT

(Device Options Configuration)......................... 187

FICD/AFICD (ICD/Debug Configuration) .................. 188

FOSCSEL/AFOSCSEL

(Oscillator Selection Configuration) .................. 192

FPOR/AFPOR (Power-up Settings

Configuration) ................................................... 189

FSEC/AFSEC (Code-Protect Configuration) ............ 193



CLKO and I/O Characteristics .................................. 222

EJTAG Characteristics ............................................. 233

External Clock .......................................................... 220

MCCP/SCCP Input Capture x Mode ........................ 226

MCCP/SCCP Output Compare x Mode.................... 226

MCCP/SCCP PWMx Mode Characteristics.............. 227

MCCP/SCCP Timerx External Clock Timing............ 225

SPIx Master Mode (CKE = 0)................................... 228

SPIx Master Mode (CKE = 1)................................... 228

SPIx Slave Mode (CKE = 0)..................................... 229

SPIx Slave Mode (CKE = 1)..................................... 230

Timer1 External Clock Characteristics ..................... 224



FWDT/AFWDT (Watchdog Timer



Configuration) ................................................... 190

HLVDCON (High/Low Voltage Detect Control)......... 177

IECx (Interrupt Enable Control x)................................ 62

IFSx (Interrupt Flag Status x)...................................... 62

INTCON (Interrupt Control)......................................... 58

INTSTAT (Interrupt Status)......................................... 61

IPCx (Interrupt Priority Control x)................................ 63

IPTMR (Interrupt Proximity Timer).............................. 61

NVMADDR (NVM Flash Address) .............................. 41

U

UART................................................................................ 119

Unique Device Identifier (UDID) ....................................... 184

Universal Asynchronous Receiver Transmitter. See UART.

NVMBWP (NVM Boot Flash (Page)



Write-Protect)...................................................... 44

NVMCON (NVM Programming Control) ..................... 39

NVMDATAx (NVM Flash Data x)................................ 42

NVMKEY (NVM Programming Unlock)....................... 41

NVMPWP (NVM Program Flash Write-Protect).......... 43

NVMSRCADDR (NVM Source Data Address)............ 42

OSCCON (Oscillator Control) ..................................... 70

OSCTUN (FRC Tuning).............................................. 77

W

Watchdog Timer (WDT)...................................................... 93

Write Protection

System Registers ..................................................... 183

WWW Address ................................................................. 264

WWW, On-Line Support ..................................................... 10

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THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

Customers

should

contact

their

distributor,

representative or Field Application Engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://microchip.com/support

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.



2015-2018 Microchip Technology Inc.

DS60001324C-page 265

PIC32MM0064GPL036 FAMILY

NOTES:

DS60001324C-page 266

 2015-2018 Microchip Technology Inc.

PIC32MM0064GPL036 FAMILY

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office

.

PIC32 MM XXXX GP L XXX T - XXX

Example:

PIC32MM0064GPL036-I/M2:



Microchip Brand

Architecture

Flash Memory Size

Family

PIC32 General Purpose Device



with MIPS32^®microAptiv™ UC

Core, 64-Kbyte Program Memory,

36-Pin Package.



Key Feature Set

Pin Count

Tape and Reel Flag (if applicable)

Pattern

Architecture

MM = MIPS32^®microAptiv™ UC CPU Core

Flash Memory Size

0016 = 16 Kbytes

0032 = 32 Kbytes

0064 = 64 Kbytes

Family

GP = General Purpose Family

Key Feature

L

= Up to 25 MHz operating frequency with basic peripheral set of 2 UART

and 2 SPI modules

Pin Count

Pattern

020 = 20-pin

028 = 28-pin

036 = 36/40-pin

Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)

ES = Engineering Sample



2015-2018 Microchip Technology Inc.

DS60001324C-page 267

PIC32MM0064GPL036 FAMILY

NOTES:

DS60001324C-page 268

 2015-2018 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR,

AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,

CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEE

LOQ,

K

EEL

OQ logo, Kleer, LANCheck, LINK MD, maXStylus,

maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip

Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST

Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

and other countries.

ClockWorks, The Embedded Control Solutions Company,

EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,

mTouch, Precision Edge, and Quiet-Wire are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,

CodeGuard, CryptoAuthentication, CryptoCompanion,

CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average

Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,

KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,

MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple

Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,

SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,

USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and

ZENA are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

Silicon Storage Technology is a registered trademark of Microchip

Technology Inc. in other countries.

are for its PIC^®MCUs and dsPIC^®DSCs, KEE OQ^®code hopping

L

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip Technology

Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Reserved.

ISBN: 978-1-5224-2850-3

== ISO/TS 16949 ==



2015-2018 Microchip Technology Inc.

DS60001324C-page 269

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Australia - Sydney

Tel: 61-2-9868-6733

India - Bangalore

Tel: 91-80-3090-4444

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

China - Beijing

Tel: 86-10-8569-7000

India - New Delhi

Tel: 91-11-4160-8631

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

China - Chengdu

Tel: 86-28-8665-5511

India - Pune

Tel: 91-20-4121-0141

Finland - Espoo

Tel: 358-9-4520-820

China - Chongqing

Tel: 86-23-8980-9588

Japan - Osaka

Tel: 81-6-6152-7160

Web Address:

www.microchip.com

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

China - Dongguan

Tel: 86-769-8702-9880

Japan - Tokyo

Tel: 81-3-6880- 3770

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Guangzhou

Tel: 86-20-8755-8029

Korea - Daegu

Tel: 82-53-744-4301

Germany - Garching

Tel: 49-8931-9700

China - Hangzhou

Tel: 86-571-8792-8115

Korea - Seoul

Tel: 82-2-554-7200

Germany - Haan

Tel: 49-2129-3766400

Austin, TX

Tel: 512-257-3370

China - Hong Kong SAR

Tel: 852-2943-5100

Malaysia - Kuala Lumpur

Tel: 60-3-7651-7906

Germany - Heilbronn

Tel: 49-7131-67-3636

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

China - Nanjing

Tel: 86-25-8473-2460

Malaysia - Penang

Tel: 60-4-227-8870

Germany - Karlsruhe

Tel: 49-721-625370

China - Qingdao

Philippines - Manila

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Tel: 86-532-8502-7355

Tel: 63-2-634-9065

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

China - Shanghai

Tel: 86-21-3326-8000

Singapore

Tel: 65-6334-8870

Germany - Rosenheim

Tel: 49-8031-354-560

China - Shenyang

Tel: 86-24-2334-2829

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Israel - Ra’anana

Tel: 972-9-744-7705

China - Shenzhen

Tel: 86-755-8864-2200

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Suzhou

Tel: 86-186-6233-1526

Taiwan - Taipei

Tel: 886-2-2508-8600

Detroit

Novi, MI

Tel: 248-848-4000

China - Wuhan

Tel: 86-27-5980-5300

Thailand - Bangkok

Tel: 66-2-694-1351

Italy - Padova

Tel: 39-049-7625286

Houston, TX

Tel: 281-894-5983

China - Xian

Tel: 86-29-8833-7252

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

China - Xiamen

Tel: 86-592-2388138

Norway - Trondheim

Tel: 47-7289-7561

China - Zhuhai

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Raleigh, NC

Tel: 919-844-7510

Sweden - Gothenberg

Tel: 46-31-704-60-40

New York, NY

Tel: 631-435-6000

Sweden - Stockholm

Tel: 46-8-5090-4654

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

DS60001324C-page 270



2015-2018 Microchip Technology Inc.

10/25/17


型号：	PIC32MM0032GPL020
厂家：	MICROCHIP
描述：	32-Bit Flash Microcontroller with MIPS32Â® microAptivâ¢ UC Core with Low Power and Low Pin Count 微控制器
文件：	总270页 (文件大小：4883K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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