PIC18LF248EPSQTP_技术文档

M

PIC18FXX8

Data Sheet

High Performance, 28/40-Pin

Enhanced FLASH Microcontrollers

with CAN

 2002 Microchip Technology Inc.

Preliminary

DS41159B

®

Note the following details of the code protection feature on PICmicro MCUs.

•

The PICmicro family meets the specifications contained in the Microchip Data Sheet.

Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,

when used in the intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.

The person doing so may be engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable”.

•

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

Information contained in this publication regarding device

applications and the like is intended through suggestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microchip Technology Incorporated with respect

to the accuracy or use of such information, or infringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,

KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip Tech-

nology Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

MXDEV, MXLAB, PICC, PICDEM, PICDEM.net, rfPIC, Select

Mode and Total Endurance are trademarks of Microchip

Technology Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999

and Mountain View, California in March 2002.

The Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals,

non-volatile memory and analog products. In

addition, Microchip’s quality system for the

design and manufacture of development

systems is ISO 9001 certified.

DS41159B - page ii

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

M

High Performance, 28/40-Pin Enhanced FLASH

Microcontrollers with CAN

High Performance RISC CPU:

Advanced Analog Features:

• 10-bit, up to 8-channel Analog-to-Digital Converter

module (A/D) with:

• Linear program memory addressing up to

2 Mbytes

- Conversion available during SLEEP

- Up to 8 channels available

• Linear data memory addressing to 4 Kbytes

• Up to 10 MIPs operation

• Analog Comparator Module:

• DC - 40 MHz clock input

- Programmable input and output multiplexing

• Comparator Voltage Reference Module

• Programmable Low Voltage Detection (LVD) module

- Supports interrupt on low voltage detection

• Programmable Brown-out Reset (BOR)

• 4 MHz - 10 MHz osc./clock input with PLL active

• 16-bit wide instructions, 8-bit wide data path

• Priority levels for interrupts

• 8 x 8 Single Cycle Hardware Multiplier

Peripheral Features:

CAN bus Module Features:

• High current sink/source 25 mA/25 mA

• Three external interrupt pins

• Message bit rates up to 1 Mbps

• Conforms to CAN 2.0B ACTIVE Spec with:

- 29-bit Identifier Fields

• Timer0 module: 8-bit/16-bit timer/counter with

8-bit programmable prescaler

- 8-byte message length

• Timer1 module: 16-bit timer/counter

- 3 Transmit Message Buffers with prioritiza-

tion

• Timer2 module: 8-bit timer/counter with 8-bit

period register (time-base for PWM)

- 2 Receive Message Buffers

• Timer3 module: 16-bit timer/counter

- 6 full 29-bit Acceptance Filters

- Prioritization of Acceptance Filters

• Secondary oscillator clock option - Timer1/Timer3

• Capture/Compare/PWM (CCP) modules CCP

pins can be configured as:

- Multiple Receive Buffers for High Priority

Messages to prevent loss due to overflow

- Capture input: 16-bit, max resolution 6.25 ns

- Compare: 16-bit, max resolution 100 ns (TCY)

- Advanced Error Management Features

- PWM output: PWM resolution is 1- to 10-bit

Max. PWM freq. @:8-bit resolution = 156 kHz

10-bit resolution = 39 kHz

Special Microcontroller Features:

• Power-on Reset (POR), Power-up Timer (PWRT),

and Oscillator Start-up Timer (OST)

• Enhanced CCP module which has all the features

of the standard CCP module, but also has the

following features for advanced motor control:

• Watchdog Timer (WDT) with its own on-chip RC

oscillator

- 1, 2, or 4 PWM outputs

• Programmable code protection

- Selectable PWM polarity

- Programmable PWM deadtime

• Power saving SLEEP mode

• Selectable oscillator options, including:

- 4X Phase Lock Loop (of primary oscillator)

- Secondary Oscillator (32 kHz) clock input

• Master Synchronous Serial Port (MSSP) with two

modes of operation:

In-Circuit Serial Programming^TM(ICSP^TM) via two pins

- 3-wire SPI™ (Supports all 4 SPI modes)

- I²C™ Master and Slave mode

•

FLASH Technology:

• Addressable USART module: Supports Interrupt

on Address bit

• Low power, high speed Enhanced FLASH technology

• Fully static design

• Wide operating voltage range (2.0V to 5.5V)

• Industrial and Extended temperature ranges

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 1

PIC18FXX8

Program Memory

Data Memory

MSSP

10-bit

A/D

(ch)

CCP/

ECCP

(PWM)

Timers

8/16-bit

# Single

Word

Instructions

Device

FLASH

I/O

USART

SRAM EEPROM

(bytes) (bytes)

Master

I C

SPI

2

(bytes)

PIC18F248

PIC18F258

PIC18F448

PIC18F458

16K

32K

16K

32K

8192

16384

8192

768

1536

768

256

22

33

5

8

—

2

1/0

1/1

Y

1/3

16384

1536

2

Pin Diagrams

PDIP

MCLR/VPP

1

2

3

4

5

6

7

8

40

RB7/PGD

RB6/PGC

RB5/PGM

RB4

RB3/CANRX

RB2/CANTX/INT2

RB1/INT1

RB0/INT0

VDD

RA0/AN0/CVREF

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4/SS/LVDIN

RE0/AN5/RD

RE1/AN6/WR/C1OUT

RE2/AN7/CS/C2OUT

VDD

VSS

OSC1/CLKI

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI

9

10

11

12

13

14

15

16

17

18

19

20

VSS

RD7/PSP7/P1D

RD6/PSP6/P1C

RD5/PSP5/P1B

RD4/PSP4/ECCP1/P1A

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3/C2IN-

RD2/PSP2/C2IN+

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0/C1IN+

RD1/PSP1/C1IN-

PLCC

RA4/T0CKI

RA5/AN4/SS/LVDIN

RE0/AN5/RD

RE1/AN6/WR/C1OUT

7

8

9

10

11

12

13

14

15

39

RB3/CANRX

RB2/CANTX/INT2

RB1/INT1

RB0/INT0

VDD

38

37

36

35

34

33

32

31

30

29

RE2/AN7/CS/C2OUT

PIC18F448

PIC18F458

VDD

VSS

RD7/PSP7/P1D

RD6/PSP6/P1C

RD5/PSP5/P1B

RD4/PSP4/ECCP1/P1A

RC7/RX/DT

OSC1/CLKI

OSC2/CLKO/RA6

RC0/T1OSO/T1CK1

NC

16

17

DS41159B-page 2

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Pin Diagrams (Continued)

TQFP

RC7/RX/DT

RD4/PSP4/ECCP1/P1A

1

2

3

4

5

6

7

8

33

32

31

30

29

28

27

26

25

24

23

NC

RC0/T1OSO/T1CKI

OSC2/CLKO/RA6

OSC1/CLKI

VSS

VDD

RD5/PSP5/P1B

RD6/PSP6/P1C

RD7/PSP7/P1D

VSS

PIC18F448

PIC18F458

VDD

RB0/INT0

RB1/INT1

RE2/AN7/CS/C2OUT

RE1/AN6/WR/C1OUT

RE0//AN5/RD

RA5/AN4/SS/LVDIN

RA4/T0CKI

9

10

11

RB2/CANTX/INT2

RB3/CANRX

SPDIP, SOIC

MCLR/VPP

RA0/AN0/CVREF

1

2

3

4

5

6

28

27

26

25

24

23

RB7/PGD

RB6/PGC

RB5/PGM

RB4

RB3/CANRX

RB2/CANTX/INT2

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4/SS/LVDIN

VSS

22

21

RB1/INT1

RB0/INT0

7

8

OSC1/CLKI

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

20

19

18

17

16

VDD

9

10

11

12

13

14

VSS

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

15

RC4/SDI/SDA

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 3

PIC18FXX8

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Oscillator Configurations ............................................................................................................................................................ 17

3.0 Reset.......................................................................................................................................................................................... 25

4.0 Memory Organization................................................................................................................................................................. 37

5.0 Data EEPROM Memory ............................................................................................................................................................ 59

6.0 FLASH Program Memory........................................................................................................................................................... 65

7.0 8 X 8 Hardware Multiplier........................................................................................................................................................... 75

8.0 Interrupts .................................................................................................................................................................................... 77

9.0 I/O Ports ..................................................................................................................................................................................... 93

10.0 Parallel Slave Port.................................................................................................................................................................... 105

11.0 Timer0 Module ......................................................................................................................................................................... 107

12.0 Timer1 Module ......................................................................................................................................................................... 111

13.0 Timer2 Module ......................................................................................................................................................................... 115

14.0 Timer3 Module ......................................................................................................................................................................... 117

15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 121

16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 129

17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 141

18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 181

19.0 CAN Module ............................................................................................................................................................................. 197

20.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module................................................................................................... 237

21.0 Comparator Module.................................................................................................................................................................. 245

22.0 Comparator Voltage Reference Module................................................................................................................................... 251

23.0 Low Voltage Detect .................................................................................................................................................................. 255

24.0 Special Features of the CPU.................................................................................................................................................... 261

25.0 Instruction Set Summary.......................................................................................................................................................... 277

26.0 Development Support............................................................................................................................................................... 319

27.0 Electrical Characteristics.......................................................................................................................................................... 325

28.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 355

29.0 Packaging Information.............................................................................................................................................................. 357

Appendix A: Data Sheet Revision History.......................................................................................................................................... 365

Appendix B: Device Differences......................................................................................................................................................... 365

Appendix C: Device Migrations.......................................................................................................................................................... 366

Appendix D: Migrating from other PICmicro Devices......................................................................................................................... 366

Appendix E: Development Tool Version Requirements..................................................................................................................... 367

Index .................................................................................................................................................................................................. 369

On-Line Support................................................................................................................................................................................. 379

Reader Response .............................................................................................................................................................................. 380

PIC18FXX8 Product Identification System......................................................................................................................................... 381

DS41159B-page 4

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.

We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Web site; http://www.microchip.com

Your local Microchip sales office (see last page)

The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include

literature number) you are using.

Customer Notification System

Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 5

PIC18FXX8

NOTES:

DS41159B-page 6

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

2. PIC18F2X8 devices implement 5 A/D channels,

as opposed to 8 for PIC18F4X8 devices.

1.0

DEVICE OVERVIEW

This document contains device specific information for

the following devices:

3. PIC18F2X8 devices implement 3 I/O ports,

while PIC18F4X8 devices implement 5.

1. PIC18F248

2. PIC18F258

3. PIC18F448

4. PIC18F458

4. Only PIC18F4X8 devices implement the

Enhanced CCP module, analog comparators

and the Parallel Slave Port.

All other features for devices in the PIC18FXX8 family,

including the serial communications modules, are

identical. These are summarized in Table 1-1.

These devices are available in 28-pin, 40-pin and

44-pin packages. They are differentiated from each

other in four ways:

Block diagrams of the PIC18F2X8 and PIC18F4X8

devices are provided in Figure 1-1 and Figure 1-2,

respectively. The pinouts for these device families are

listed in Table 1-2.

1. PIC18FX58 devices have twice the FLASH pro-

gram memory and data RAM of PIC18FX48

devices (32 Kbytes and 1536 bytes vs.

16 Kbytes and 768 bytes, respectively).

TABLE 1-1:

PIC18FXX8 DEVICE FEATURES

Features

PIC18F248

PIC18F258

PIC18F448

PIC18F458

Operating Frequency

DC - 40 MHz

32K

DC - 40 MHz

32K

DC - 40 MHz

16K

DC - 40 MHz

16K

Internal Program Bytes

Memory

# of Single Word

Instructions

8192

16384

8192

16384

Data Memory (Bytes)

Data EEPROM Memory (Bytes)

Interrupt Sources

768

1536

768

256

21

1536

256

21

256

17

I/O Ports

Ports A, B, C

Ports A, B, C, D, E Ports A, B, C, D, E

Timers

4

1

4

1

4

1

4

1

Capture/Compare/PWM Modules

Enhanced Capture/Compare/PWM

Modules

—

Serial Communications

MSSP, CAN,

Addressable

USART

MSSP, CAN,

Addressable

USART

MSSP, CAN,

Addressable

USART

MSSP, CAN,

Addressable

USART

Parallel Communications (PSP)

10-bit Analog-to-Digital Converter

Analog Comparators

No

Yes

8 input channels

2

Yes

8 input channels

2

5 input channels 5 input channels

No

N/A

No

N/A

Analog Comparators VREF Output

RESETS (and Delays)

Yes

POR, BOR,

RESETInstruction, RESETInstruction, RESETInstruction, RESETInstruction,

Stack Full,

Stack Underflow

(PWRT, OST)

Stack Full,

Stack Underflow

(PWRT, OST)

Stack Full,

Stack Underflow

(PWRT, OST)

Stack Full,

Stack Underflow

(PWRT, OST)

Programmable Low Voltage Detect

Programmable Brown-out Reset

CAN Module

Yes

In-Circuit Serial Programming™

(ICSP™)

Instruction Set

Packages

75 Instructions

28-pin SPDIP

28-pin SOIC

28-pin SPDIP

28-pin SOIC

40-pin PDIP

44-pin PLCC

44-pin TQFP

40-pin PDIP

44-pin PLCC

44-pin TQFP

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 7

PIC18FXX8

FIGURE 1-1:

PIC18F248/258 BLOCK DIAGRAM

Data Bus<8>

PORTA

RA0/AN0/CVREF

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

Table Pointer<21>

inc/dec logic

Data Latch

21

8

Data RAM

up to 1536 bytes

21

RA5/AN4/SS/LVDIN

OSC2/CLKO/RA6

Address Latch

21

PCLATU

PCU

PCLATH

PORTB

12

RB0/INT0

RB1/INT1

RB2/CANTX/INT2

RB3/CANRX

RB4

RB5/PGM

RB6/PGC

RB7/PGD

Address<12>

PCH PCL

Program Counter

4

12

FSR0

4

BSR

Bank0, F

Address Latch

FSR1

FSR2

Program Memory

up to 32 Kbytes

31 Level Stack

12

Data Latch

inc/dec

logic

Decode

PORTC

Table Latch

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

8

16

ROM Latch

IR

RC6/TX/CK

RC7/RX/DT

8

PRODH PRODL

8 x 8 Multiply

Instruction

Decode &

Control

8

3

OSC2/CLKO/RA6

OSC1/CLKI

W

8

BITOP

8

Power-up

Timer

Timing

Generation

Oscillator

Start-up Timer

8

T1OSI

T1OSO

ALU<8>

8

Power-on

Reset

4X PLL

Watchdog

Timer

Brown-out

Reset

Test Mode

Select

Precision

Bandgap

Reference

Bandgap

MCLR

VDD, VSS

PBOR

PLVD

10-bit

ADC

Timer0

Timer1

Timer2

Timer3

Synchronous

Serial Port

Data EEPROM

CCP1

USART

CAN Module

DS41159B-page 8

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 1-2:

PIC18F448/458 BLOCK DIAGRAM

Data Bus<8>

PORTA

RA0/AN0/CVREF

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

Table Pointer<21>

inc/dec logic

Data Latch

21

8

Data RAM

up to 1536 Kbytes

21

RA5/AN4/SS/LVDIN

OSC2/CLKO/RA6

Address Latch

21

PCLATU

PCU

PCLATH

PORTB

12

RB0/INT0

RB1/INT1

RB2/CANTX/INT2

RB3/CANRX

RB4

RB5/PGM

RB6/PGC

RB7/PGD

Address<12>

PCH PCL

Program Counter

12

4

Bank0, F

BSR

Address Latch

FSR0

FSR1

FSR2

Program Memory

up to 32 Kbytes

31 Level Stack

12

Data Latch

inc/dec

logic

Decode

PORTC

Table Latch

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

8

16

ROM Latch

IR

8

PORTD

RD0/PSP0/C1IN+

RD1/PSP1/C1IN-

RD2/PSP2/C2IN+

RD3/PSP3/C2IN-

RD4/PSP4/ECCP1/P1A

RD5/PSP5/P1B

PRODH PRODL

8 x 8 Multiply

Instruction

Decode &

Control

8

3

OSC2/CLKO/RA6

OSC1/CLKI

W

8

BITOP

8

RD6/PSP6/P1C

RD7/PSP7/P1D

8

Power-up

Timer

Timing

Generation

Oscillator

Start-up Timer

PORTE

8

RE0/AN5/RD

RE1/AN6/WR//C1OUT

RE2/AN7/CS/C2OUT

T1OSI

T1OSO

ALU<8>

Power-on

Reset

4X

8

PLL

Watchdog

Timer

Brown-out

Reset

Test Mode

Select

Precision

Bandgap

Reference

Bandgap

MCLR

VDD, VSS

USART

PBOR

PLVD

10-bit

ADC

Parallel

Slave Port

Timer0

Timer1

CCP1

Timer2

Timer3

Synchronous

Serial Port

Enhanced

CCP

Data EEPROM

USART

Comparators

CAN Module

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 9

PIC18FXX8

TABLE 1-2:

PIC18FXX8 PINOUT I/O DESCRIPTIONS

Pin Number

PIC18F248/258 PIC18F448/458

SPDIP, SOIC PDIP TQFP PLCC

Type

Buffer

Type

Pin Name

Description

MCLR/VPP

MCLR

1

18

2

Master Clear (input) or

programming voltage (output).

Master Clear (Reset) input.

This pin is an active low

RESET to the device.

I

ST

VPP

NC

P

—

Programming voltage input.

—

12, 13, 1, 17,

33, 34 28, 40

—

These pins should be left

unconnected.

OSC1/CLKI

OSC1

9

13

30

14

Oscillator crystal or external clock

input.

I

CMOS/ST

CMOS

Oscillator crystal input or

external clock source input. ST

buffer when configured in RC

mode. Otherwise CMOS.

External clock source input.

Always associated with pin

function OSC1 (see OSC1/

CLKI, OSC2/CLKO pins).

CLKI

OSC2/CLKO/RA6

OSC2

10

14

31

15

Oscillator crystal or clock output.

Oscillator crystal output.

Connects to crystal or

resonator in Crystal Oscillator

mode.

O

—

CLKO

In RC mode, OSC2 pin outputs

CLKO, which has 1/4 the

frequency of OSC1 and

denotes the instruction cycle

rate.

RA6

I/O

TTL

General purpose I/O pin.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I

P

=

Input

Power

O

OD

=

Output

Open Drain (no P diode to VDD)

DS41159B-page 10

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 1-2:

PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

PIC18F248/258

PIC18F448/458

Description

SPDIP, SOIC PDIP TQFP PLCC

PORTA is a bi-directional I/O port.

RA0/AN0/CVREF

RA0

2

19

3

I/O

I

O

TTL

Analog

Digital I/O.

AN0

CVREF

Analog input 0.

Comparator voltage reference

output.

RA1/AN1

RA1

3

4

3

4

20

21

4

5

I/O

I

TTL

Analog

Digital I/O.

Analog input 1.

AN1

RA2/AN2/VREF-

RA2

I/O

TTL

Digital I/O.

AN2

VREF-

I

Analog

Analog input 2.

A/D reference voltage

(Low) input.

RA3/AN3/VREF+

RA3

5

6

7

5

6

7

22

23

24

6

7

8

I/O

I

TTL

Analog

Digital I/O.

AN3

VREF+

Analog input 3.

A/D reference voltage

(High) input.

RA4/T0CKI

RA4

I/O

I

TTL/OD

ST

Digital I/O - open drain when

configured as output.

Timer0 external clock input.

T0CKI

RA5/AN4/SS/LVDIN

RA5

AN4

SS

I/O

TTL

Analog

ST

Digital I/O.

Analog input 4.

SPI slave select input.

Low voltage detect input.

I

LVDIN

Analog

RA6

See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I

P

=

Input

Power

O

OD

=

Output

Open Drain (no P diode to VDD)

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 11

PIC18FXX8

TABLE 1-2:

PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

PIC18F248/258 PIC18F448/458

SPDIP, SOIC PDIP TQFP PLCC

Type

Buffer

Type

Pin Name

Description

PORTB is a bi-directional I/O port.

PORTB can be software

programmed for internal weak

pull-ups on all inputs.

RB0/INT0

RB0

21

22

23

33

34

35

8

9

36

37

38

I/O

I

TTL

ST

Digital I/O.

External interrupt 0.

INT0

RB1/INT1

RB1

I/O

I

TTL

ST

Digital I/O.

External interrupt 1.

INT1

RB2/CANTX/INT2

RB2

10

I/O

O

I

TTL

ST

Digital I/O.

Transmit signal for CAN bus.

External interrupt 2.

CANTX

INT2

RB3/CANRX

RB3

24

36

11

39

I/O

I

TTL

Digital I/O.

Receive signal for CAN bus.

CANRX

RB4

25

26

37

38

14

15

41

42

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

RB5/PGM

RB5

I/O

I

TTL

ST

Digital I/O.

Interrupt-on-change pin.

Low voltage ICSP

programming enable.

PGM

RB6/PGC

RB6

27

28

39

40

16

17

43

44

I/O

I

TTL

ST

Digital I/O. In-Circuit

Debugger pin.

Interrupt-on-change pin.

ICSP programming clock.

PGC

RB7/PGD

RB7

I/O

TTL

ST

Digital I/O. In-Circuit

Debugger pin.

Interrupt-on-change pin.

ICSP programming data.

PGD

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I

P

=

Input

Power

O

OD

=

Output

Open Drain (no P diode to VDD)

DS41159B-page 12

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 1-2:

PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

PIC18F248/258

PIC18F448/458

Description

SPDIP, SOIC PDIP TQFP PLCC

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI

RC0

11

15

32

16

I/O

O

I

ST

—

ST

Digital I/O.

T1OSO

T1CKI

Timer1 oscillator output.

Timer1/Timer3 external clock

input.

RC1/T1OSI

RC1

12

13

14

16

17

18

35

36

37

18

19

20

I/O

I

ST

CMOS

Digital I/O.

Timer1 oscillator input.

T1OSI

RC2/CCP1

RC2

I/O

ST

Digital I/O.

Capture1 input/Compare1

output/PWM1 output.

CCP1

RC3/SCK/SCL

RC3

I/O

ST

Digital I/O.

SCK

Synchronous serial clock

input/output for SPI mode.

Synchronous serial clock

input/output for I²C mode.

SCL

I/O

ST

RC4/SDI/SDA

RC4

15

23

42

25

I/O

I

I/O

ST

Digital I/O.

SPI data in.

I²C data I/O.

SDI

SDA

RC5/SDO

RC5

16

17

24

25

43

44

26

27

I/O

O

ST

—

Digital I/O.

SPI data out.

SDO

RC6/TX/CK

RC6

I/O

O

ST

—

Digital I/O.

USART asynchronous

transmit.

TX

CK

I/O

ST

USART synchronous clock

(see RX/DT).

RC7/RX/DT

RC7

18

26

1

29

I/O

I

I/O

ST

Digital I/O.

RX

DT

USART asynchronous receive.

USART synchronous data

(see TX/CK).

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I

P

=

Input

Power

O

OD

=

Output

Open Drain (no P diode to VDD)

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 13

PIC18FXX8

TABLE 1-2:

PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

PIC18F248/258 PIC18F448/458

SPDIP, SOIC PDIP TQFP PLCC

Type

Buffer

Type

Pin Name

Description

PORTD is a bi-directional I/O port.

These pins have TTL input buffers

when external memory is enabled.

RD0/PSP0/C1IN+

RD0

—

19

20

21

22

27

38

39

40

41

2

21

22

23

24

30

I/O

I

ST

TTL

Analog

Digital I/O.

Parallel slave port data.

Comparator 1 input.

PSP0

C1IN+

RD1/PSP1/C1IN-

RD1

I/O

I

ST

TTL

Analog

Digital I/O.

Parallel slave port data.

Comparator 1 input.

PSP1

C1IN-

RD2/PSP2/C2IN+

RD2

I/O

I

ST

TTL

Analog

Digital I/O.

Parallel slave port data.

Comparator 2 input.

PSP2

C2IN+

RD3/PSP3/C2IN-

RD3

I/O

I

ST

TTL

Analog

Digital I/O.

Parallel slave port data.

Comparator 2 input.

PSP3

C2IN-

RD4/PSP4/ECCP1/

P1A

RD4

I/O

O

ST

TTL

ST

—

Digital I/O.

PSP4

ECCP1

P1A

Parallel slave port data.

ECCP1 capture/compare.

ECCP1 PWM output A.

RD5/PSP5/P1B

RD5

—

28

29

30

3

4

5

31

32

33

I/O

O

ST

TTL

—

Digital I/O.

Parallel slave port data.

ECCP1 PWM output B.

PSP5

P1B

RD6/PSP6/P1C

RD6

I/O

O

ST

TTL

—

Digital I/O.

Parallel slave port data.

ECCP1 PWM output C.

PSP6

P1C

RD7/PSP7/P1D

RD7

I/O

O

ST

TTL

—

Digital I/O.

Parallel slave port data.

ECCP1 PWM output D.

PSP7

P1D

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I

P

=

Input

Power

O

OD

=

Output

Open Drain (no P diode to VDD)

DS41159B-page 14

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 1-2:

PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

PIC18F248/258

PIC18F448/458

Description

SPDIP, SOIC PDIP TQFP PLCC

PORTE is a bi-directional I/O port.

RE0/AN5/RD

RE0

—

8

9

25

26

9

I/O

I

ST

Analog

TTL

Digital I/O.

Analog input 5.

Read control for parallel slave

port (see WR and CS pins).

AN5

RD

RE1/AN6/WR/C1OUT

10

RE1

AN6

WR

I/O

I

ST

Analog

TTL

Digital I/O.

Analog input 6.

Write control for parallel slave

port (see CS and RD pins).

Comparator 1 output.

C1OUT

O

Analog

RE2/AN7/CS/C2OUT

—

10

27

11

RE2

AN7

CS

I/O

I

ST

Analog

TTL

Digital I/O.

Analog input 7.

Chip select control for parallel

slave port (see RD and WR

pins).

C2OUT

VSS

O

—

Analog

—

Comparator 2 output.

19, 8

20

12, 31 6, 29 13, 34

11, 32 7, 28 12, 35

Ground reference for logic and

I/O pins.

VDD

—

Positive supply for logic and I/O

pins.

Legend: TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

Input Output

Power Open Drain (no P diode to VDD)

CMOS = CMOS compatible input or output

I

=

O

=

P

=

OD

=

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 15

PIC18FXX8

NOTES:

DS41159B-page 16

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 2-1:

CRYSTAL/CERAMIC

RESONATOROPERATION

(HS, XT OR LP OSC

CONFIGURATION)

2.0

2.1

OSCILLATOR

CONFIGURATIONS

Oscillator Types

(1)

The PIC18FXX8 can be operated in one of eight Oscil-

lator modes, programmable by three configuration bits

(FOSC2, FOSC1, and FOSC0).

C1

OSC1

To

Internal

Logic

(3)

RF

XTAL

1. LP

2. XT

3. HS

4. HS4

Low Power Crystal

Crystal/Resonator

SLEEP

(2)

RS

High Speed Crystal/Resonator

(1)

PIC18FXX8

C2

OSC2

High Speed Crystal/Resonator with

PLL enabled

5. RC

External Resistor/Capacitor

Note 1: See Table 2-1 and Table 2-2 for recommended

values of C1 and C2.

6. RCIO

External Resistor/Capacitor with I/O

pin enabled

2: A series resistor (RS) may be required for AT

strip cut crystals.

7. EC

External Clock

3: RF varies with the crystal chosen.

8. ECIO

External Clock with I/O pin enabled

2.2

Crystal Oscillator/Ceramic

Resonators

TABLE 2-1:

CERAMIC RESONATORS

Ranges Tested:

In XT, LP, HS or HS4 (PLL) Oscillator modes, a crystal

or ceramic resonator is connected to the OSC1 and

OSC2 pins to establish oscillation. Figure 2-1 shows

the pin connections. An external clock source may also

be connected to the OSC1 pin, as shown in Figure 2-3

and Figure 2-4.

Mode

Freq

OSC1

OSC2

XT

455 kHz

2.0 MHz

4.0 MHz

68 - 100 pF 68 - 100 pF

15 - 68 pF

HS

8.0 MHz

16.0 MHz

20.0 MHz

25.0 MHz

10 - 68 pF

10 - 22 pF

TBD

10 - 68 pF

10 - 22 pF

TBD

The PIC18FXX8 oscillator design requires the use of a

parallel cut crystal.

TBD

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturer’s

specifications.

HS+PLL

4.0 MHz

8.0 MHz

10.0 MHz

TBD

10 - 68 pF

TBD

10 - 68 pF

TBD

These values are for design guidance only.

See notes following Table 2-2.

Resonators Used:

455 kHz Panasonic EFO-A455K04B

0.3%

2.0 MHz

4.0 MHz

8.0 MHz

Murata Erie CSA2.00MG

Murata Erie CSA4.00MG

Murata Erie CSA8.00MT

0.5%

16.0 MHz Murata Erie CSA16.00MX

All resonators used did not have built-in capacitors.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 17

PIC18FXX8

TABLE 2-2:

CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

2.3

RC Oscillator

For timing insensitive applications, the “RC” and

"RCIO" device options offer additional cost savings.

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) val-

ues and the operating temperature. In addition to this,

the oscillator frequency will vary from unit to unit due to

normal process parameter variation. Furthermore, the

difference in lead frame capacitance between package

types will also affect the oscillation frequency, espe-

cially for low CEXT values. The user also needs to take

into account variation due to tolerance of external R

and C components used. Figure 2-2 shows how the RC

combination is connected.

Crystal Cap. Range Cap. Range

Osc Type

Freq

C1

C2

LP

32.0 kHz

200 kHz

1.0 MHz

4.0 MHz

8.0 MHz

20.0 MHz

25.0 MHz

4.0 MHz

8.0 MHz

10.0 MHz

33 pF

15 pF

33 pF

15 pF

XT

HS

47-68 pF

15 pF

47-68 pF

15 pF

15-33 pF

TBD

15-33 pF

TBD

In the RC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic.

HS+PLL

15 pF

15-33 pF

TBD

15-33 pF

TBD

FIGURE 2-2:

RC OSCILLATOR MODE

These values are for design guidance only.

See notes on this page.

VDD

Crystals Used

PIC18FXX8

Internal

OSC1

REXT

32.0 kHz Epson C-001R32.768K-A ± 20 PPM

Clock

200 kHz

1.0 MHz

4.0 MHz

STD XTL 200.000KHz

ECS ECS-10-13-1

ECS ECS-40-20-1

± 20 PPM

± 50 PPM

CEXT

VSS

OSC2/CLKO

8.0 MHz EPSON CA-301 8.000M-C ± 30 PPM

FOSC/4

20.0 MHz EPSON CA-301 20.000M- ± 30 PPM

C

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

CEXT > 20 pF

Note 1: Recommended values of C1 and C2 are

identical to the ranges tested (Table 2-1).

2: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

The RCIO Oscillator mode functions like the RC mode,

except that the OSC2 pin becomes an additional

general purpose I/O pin.

3: Since each resonator/crystal has its own

characteristics, the user should consult the

resonator/crystal manufacturer for

appropriate values of external components.

4: Rs may be required in HS mode, as well as

XT mode, to avoid overdriving crystals with

low drive level specification.

DS41159B-page 18

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 2-4:

EXTERNAL CLOCK INPUT

OPERATION (ECIO

CONFIGURATION)

2.4

External Clock Input

The EC and ECIO Oscillator modes require an external

clock source to be connected to the OSC1 pin. The

feedback device between OSC1 and OSC2 is turned

off in these modes to save current. There is no oscilla-

tor start-up time required after a Power-on Reset or

after a recovery from SLEEP mode.

PIC18FXX8

OSC1

Clock from

Ext. System

I/O (OSC2)

In the EC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic. Figure 2-3 shows the pin connections for the EC

Oscillator mode.

2.5

HS4 (PLL)

A Phase Locked Loop circuit is provided as a program-

mable option for users that want to multiply the fre-

quency of the incoming crystal oscillator signal by 4.

For an input clock frequency of 10 MHz, the internal

clock frequency will be multiplied to 40 MHz. This is

useful for customers who are concerned with EMI due

to high frequency crystals.

FIGURE 2-3:

EXTERNAL CLOCK INPUT

OPERATION (EC OSC

CONFIGURATION)

PIC18FXX8

OSC1

Clock from

The PLL can only be enabled when the oscillator con-

figuration bits are programmed for HS mode. If they are

programmed for any other mode, the PLL is not

enabled and the system clock will come directly from

OSC1.

Ext. System

OSC2

FOSC/4

The ECIO Oscillator mode functions like the EC mode,

except that the OSC2 pin becomes an additional gen-

eral purpose I/O pin. Figure 2-4 shows the pin connec-

tions for the ECIO Oscillator mode.

The PLL is one of the modes of the FOSC2:FOSC0

configuration bits. The Oscillator mode is specified dur-

ing device programming.

A PLL lock timer is used to ensure that the PLL has

locked before device execution starts. The PLL lock

timer has a time-out referred to as TPLL.

FIGURE 2-5:

PLL BLOCK DIAGRAM

FOSC2:FOSC0 = ‘110’

Phase

OSC2

Comparator

FIN

Loop

Filter

VCO

Crystal

FOUT

Osc

SYSCLK

Divide by 4

OSC1

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 19

PIC18FXX8

2.6.1

SYSTEM CLOCK SWITCH BIT

2.6

Oscillator Switching Feature

The system clock source switching is performed under

software control. The system clock switch bit, SCS

(OSCCON register), controls the clock switching. When

the SCS bit is ’0’, the system clock source comes from

the main oscillator selected by the FOSC2:FOSC0 con-

figuration bits. When the SCS bit is set, the system clock

source comes from the Timer1 oscillator. The SCS bit is

cleared on all forms of RESET.

The PIC18FXX8 devices include a feature that allows

the system clock source to be switched from the main

oscillator to an alternate low frequency clock source.

For the PIC18FXX8 devices, this alternate clock source

is the Timer1 oscillator. If a low frequency crystal

(32 kHz, for example) has been attached to the Timer1

oscillator pins and the Timer1 oscillator has been

enabled, the device can switch to a Low Power Execu-

tion mode. Figure 2-6 shows a block diagram of the sys-

tem clock sources. The clock switching feature is

enabled by programming the Oscillator Switching

Enable (OSCSEN) bit in Configuration register,

CONFIG1H, to a ’0’. Clock switching is disabled in an

erased device. See Section 12.2 for further details of

the Timer1 oscillator, and Section 24.1 for Configuration

Register details.

Note: The Timer1 oscillator must be enabled to

switch the system clock source. The

Timer1 oscillator is enabled by setting the

T1OSCEN bit in the Timer1 control register

(T1CON). If the Timer1 oscillator is not

enabled, any write to the SCS bit will be

ignored (SCS bit forced cleared) and the

main oscillator continues to be the system

clock source.

FIGURE 2-6:

DEVICE CLOCK SOURCES

PIC18FXX8

Main Oscillator

OSC2

TOSC/4

4 x PLL

SLEEP

TOSC

TT1P

TSCLK

OSC1

Timer 1 Oscillator

T1OSO

T1OSCEN

Clock

Source

Enable

Oscillator

T1OSI

Clock Source Option

for Other Modules

Note:

I/O pins have diode protection to VDD and VSS.

REGISTER 2-1:

OSCCON REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SCS

bit 7

bit 0

bit 7-1 Unimplemented: Read as '0'

bit 0

SCS: System Clock Switch bit

When OSCSEN configuration bit = ’0’ and T1OSCEN bit is set:

1= Switch to Timer1 oscillator/clock pin

0= Use primary oscillator/clock input pin

When OSCSEN is clear or T1OSCEN is clear:

Bit is forced clear

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

DS41159B-page 20

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

The sequence of events that takes place when switch-

ing from the Timer1 oscillator to the main oscillator will

depend on the mode of the main oscillator. In addition

to eight clock cycles of the main oscillator, additional

delays may take place.

2.6.2

OSCILLATOR TRANSITIONS

The PIC18FXX8 devices contain circuitry to prevent

"glitches" when switching between oscillator sources.

Essentially, the circuitry waits for eight rising edges of

the clock source that the processor is switching to. This

ensures that the new clock source is stable and that its

pulse width will not be less than the shortest pulse

width of the two clock sources.

If the main oscillator is configured for an external crys-

tal (HS, XT, LP), the transition will take place after an

oscillator start-up time (TOST) has occurred. A timing

diagram indicating the transition from the Timer1 oscil-

lator to the main oscillator for HS, XT, and LP modes is

shown in Figure 2-8.

Figure 2-7 shows a timing diagram indicating the tran-

sition from the main oscillator to the Timer1 oscillator.

The Timer1 oscillator is assumed to be running all the

time. After the SCS bit is set, the processor is frozen at

the next occurring Q1 cycle. After eight synchronization

cycles are counted from the Timer1 oscillator, opera-

tion resumes. No additional delays are required after

the synchronization cycles.

FIGURE 2-7:

TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR

Q4

Q1 Q2 Q3

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

TT1P

2

1

3

4

5

6

7

8

T1OSI

OSC1

Tscs

TOSC

Internal

System

Clock

TDLY

SCS

(OSCCON<0>)

Program

Counter

PC

PC + 2

PC + 4

Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.

FIGURE 2-8:

TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)

Q3

Q4

Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3

TT1P

T1OSI

OSC1

1

2

3

4

5

6

7

8

TOST

TSCS

OSC2

TOSC

Internal System

Clock

SCS

(OSCCON<0>)

Program

Counter

PC

PC + 2

PC + 4

Note 1: TOST = 1024 TOSC (drawing not to scale).

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 21

PIC18FXX8

If the main oscillator is configured for HS4 (PLL) mode,

an oscillator start-up time (TOST) plus an additional PLL

time-out (TPLL) will occur. The PLL time-out is typically

2 ms and allows the PLL to lock to the main oscillator

frequency. A timing diagram indicating the transition

from the Timer1 oscillator to the main oscillator for HS4

mode is shown in Figure 2-9.

If the main oscillator is configured in the RC, RCIO, EC

or ECIO modes, there is no oscillator start-up time-out.

Operation will resume after eight cycles of the main

oscillator have been counted. A timing diagram indicat-

ing the transition from the Timer1 oscillator to the main

oscillator for RC, RCIO, EC and ECIO modes is shown

in Figure 2-10.

FIGURE 2-9:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)

TT1P

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q4

Q1

T1OSI

OSC1

TOST

TPLL

OSC2

TSCS

TOSC

PLL Clock

Input

1

2

3

4

5

6

8

7

Internal System

Clock

SCS

(OSCCON<0>)

Program

Counter

PC

PC + 2

PC + 4

Note 1: TOST = 1024 TOSC (drawing not to scale).

FIGURE 2-10:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)

Q3

Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1

TT1P

T1OSI

OSC1

TOSC

6

1

4

5

7

8

2

3

OSC2

Internal System

Clock

SCS

(OSCCON<0>)

TSCS

Program

Counter

PC

PC + 2

PC + 4

Note 1: RC Oscillator mode assumed.

DS41159B-page 22

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

RESET until the device power supply and clock are sta-

ble. For additional information on RESET operation,

see Section 3.0.

2.7

Effects of SLEEP Mode on the

On-Chip Oscillator

When the device executes a SLEEP instruction, the

on-chip clocks and oscillator are turned off and the

device is held at the beginning of an instruction cycle

(Q1 state). With the oscillator off, the OSC1 and OSC2

signals will stop oscillating. Since all the transistor

switching currents have been removed, SLEEP mode

achieves the lowest current consumption of the device

(only leakage currents). Enabling any on-chip feature

that will operate during SLEEP will increase the current

consumed during SLEEP. The user can wake from

SLEEP through external RESET, Watchdog Timer

Reset, or through an interrupt.

The first timer is the Power-up Timer (PWRT), which

optionally provides a fixed delay of TPWRT (parameter

#D033) on power-up only (POR and BOR). The second

timer is the Oscillator Start-up Timer (OST), intended to

keep the chip in RESET until the crystal oscillator is

stable.

With the PLL enabled (HS4 Oscillator mode), the time-

out sequence following a Power-on Reset is different

from other Oscillator modes. The time-out sequence is

as follows: the PWRT time-out is invoked after a POR

time delay has expired, then the Oscillator Start-up

Timer (OST) is invoked. However, this is still not a suf-

ficient amount of time to allow the PLL to lock at high

frequencies. The PWRT timer is used to provide an

additional time-out. This time is called TPLL (parameter

#7) to allow the PLL ample time to lock to the incoming

clock frequency.

2.8

Power-up Delays

Power-up delays are controlled by two timers, so that

no external RESET circuitry is required for most appli-

cations. The delays ensure that the device is kept in

TABLE 2-3:

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

OSC1 Pin

OSC Mode

OSC2 Pin

RC

Floating, external resistor should pull high At logic low

RCIO

Floating, external resistor should pull high Configured as PORTA, bit 6

ECIO

Floating

Configured as PORTA, bit 6

At logic low

EC

LP, XT, and HS

Feedback inverter disabled, at quiescent

voltage level

Feedback inverter disabled, at quiescent

voltage level

Note: See Table 3-1 in Section 3.0, for time-outs due to SLEEP and MCLR Reset.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 23

PIC18FXX8

NOTES:

DS41159B-page 24

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

state on Power-on Reset, MCLR, WDT Reset, Brown-

out Reset, MCLR Reset during SLEEP and by the

RESETinstruction.

3.0

RESET

The PIC18FXX8 differentiates between various kinds

of RESET:

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal oper-

ation. Status bits from the RCON register, RI, TO, PD,

POR and BOR are set or cleared differently in different

RESET situations, as indicated in Table 3-2. These bits

are used in software to determine the nature of the

RESET. See Table 3-3 for a full description of the

RESET states of all registers.

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during SLEEP

d) Watchdog Timer (WDT) Reset during normal

operation

e) Programmable Brown-out Reset (PBOR)

f) RESETInstruction

A simplified block diagram of the on-chip RESET circuit

is shown in Figure 3-1.

g) Stack Full Reset

h) Stack Underflow Reset

The Enhanced MCU devices have a MCLR noise filter

in the MCLR Reset path. The filter will detect and

ignore small pulses.

Most registers are unaffected by a RESET. Their status

is unknown on POR and unchanged by all other

RESETS. The other registers are forced to a “RESET”

A WDT Reset does not drive MCLR pin low.

FIGURE 3-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET

Instruction

Stack Full/Underflow Reset

External Reset

Stack

Pointer

MCLR

SLEEP

WDT

Time-out

Reset

WDT

Module

VDD Rise

Detect

Power-on Reset

VDD

Brown-out

Reset

BOREN

S

OST/PWRT

OST

Chip_Reset

10-bit Ripple Counter

Q

R

OSC1

PWRT

On-chip

(1)

RC OSC

Enable PWRT

(2)

Enable OST

Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.

2: See Table 3-1 for time-out situations.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 25

PIC18FXX8

3.1

Power-on Reset (POR)

3.3

Power-up Timer (PWRT)

A Power-on Reset pulse is generated on-chip when a

VDD rise is detected. To take advantage of the POR cir-

cuitry, connect the MCLR pin directly (or through a

resistor) to VDD. This eliminates external RC compo-

nents usually needed to create a Power-on Reset

delay. A minimum rise rate for VDD is specified (refer to

parameter D004). For a slow rise time, see Figure 3-2.

The Power-up Timer provides a fixed nominal time-out

(parameter #33), only on power-up from the POR. The

Power-up Timer operates on an internal RC oscillator.

The chip is kept in RESET as long as the PWRT is

active. The PWRT’s time delay allows VDD to rise to an

acceptable level. A configuration bit (PWRTEN in

CONFIG2L register) is provided to enable/disable the

PWRT.

When the device starts normal operation (exits the

RESET condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in RESET until the operating con-

ditions are met. Brown-out Reset may be used to meet

the voltage start-up condition.

The power-up time delay will vary from chip to chip due

to VDD, temperature and process variation. See DC

parameter #33 for details.

3.4

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over (parameter #32). This additional

delay ensures that the crystal oscillator or resonator

has started and stabilized.

3.2

MCLR

PIC18FXX8 devices have a noise filter in the MCLR

Reset path. The filter will detect and ignore small

pulses.

The OST time-out is invoked only for XT, LP, HS and

HS4 modes and only on Power-on Reset or wake-up

from SLEEP.

It should be noted that a WDT Reset does not drive

MCLR pin low.

The behavior of the ESD protection on the MCLR pin

differs from previous devices of this family. Voltages

applied to the pin that exceed its specification can

result in both resets and current draws outside of

device specification during the RESET event. For this

reason, Microchip recommends that the MCLR pin no

longer be tied directly to VDD. The use of an RC

network, as shown in Figure 3-2, is suggested.

3.5

PLL Lock Time-out

With the PLL enabled, the time-out sequence following

a Power-on Reset is different from other oscillator

modes. A portion of the Power-up Timer is used to pro-

vide a fixed time-out that is sufficient for the PLL to lock

to the main oscillator frequency. This PLL lock time-out

(TPLL) is typically 2 ms and follows the oscillator

start-up time-out (OST).

FIGURE 3-2:

RECOMMENDED MCLR

CIRCUIT

3.6

Brown-out Reset (BOR)

A configuration bit, BOREN, can disable (if clear/

programmed), or enable (if set), the Brown-out Reset

circuitry. If VDD falls below parameter D005 for greater

than parameter #35, the brown-out situation resets the

chip. A RESET may not occur if VDD falls below param-

eter D005 for less than parameter #35. The chip will

remain in Brown-out Reset until VDD rises above BVDD.

The Power-up Timer will then be invoked and will keep

the chip in RESET an additional time delay (parameter

#33). If VDD drops below BVDD while the Power-up

Timer is running, the chip will go back into a Brown-out

Reset and the Power-up Timer will be initialized. Once

VDD rises above BVDD, the Power-up Timer will

execute the additional time delay.

VDD

PIC18FXX8

R1

1 kΩ (or greater)

MCLR

C1

0.1 µF

(not critical)

DS41159B-page 26

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire.

Bringing MCLR high will begin execution immediately

(Figure 3-5). This is useful for testing purposes or to

synchronize more than one PIC18FXX8 device

operating in parallel.

3.7

Time-out Sequence

On power-up, the time-out sequence is as follows:

First, PWRT time-out is invoked after the POR time

delay has expired, then OST is activated. The total

time-out will vary based on oscillator configuration and

the status of the PWRT. For example, in RC mode with

the PWRT disabled, there will be no time-out at all.

Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and

Figure 3-7 depict time-out sequences on power-up.

Table 3-2 shows the RESET conditions for some

Special Function Registers, while Table 3-3 shows the

RESET conditions for all registers.

TABLE 3-1:

TIME-OUT IN VARIOUS SITUATIONS

Power-up⁽²⁾

Wake-up from

SLEEP or

Oscillator

Configuration

Brown-out⁽²⁾

PWRTEN = 0

PWRTEN = 1

Oscillator Switch

HS with PLL enabled⁽¹⁾72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms 72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms

HS, XT, LP

EC

External RC

72 ms + 1024 TOSC

72 ms

1024 TOSC

72 ms + 1024 TOSC

72 ms

1024 TOSC

—

72 ms

Note 1: 2 ms = Nominal time required for the 4X PLL to lock.

2: 72 ms is the nominal power-up timer delay.

REGISTER 3-1:

RCON REGISTER BITS AND POSITIONS

R/W-0

IPEN

U-0

R/W-1

RI

R/W-1

TO

R/W-1

PD

R/W-1

POR

R/W-1

BOR

—

bit 7

bit 0

TABLE 3-2:

STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR

RCON REGISTER

Program

Counter

RCON

Register

Condition

RI TO PD POR BOR STKFUL STKUNF

Power-on Reset

0000h

0--1 1100

0--u uuuu

1

u

1

u

1

u

0

u

0

u

MCLR Reset during normal

operation

Software Reset during normal

operation

0000h

0--0 uuuu

0--u uu11

0

u

1

u

1

u

1

u

1

u

Stack Full Reset during normal

operation

Stack Underflow Reset during

normal operation

MCLR Reset during SLEEP

WDT Reset

0000h

PC + 2

0000h

0--u 10uu

0--u 01uu

u--u 00uu

0--1 11u0

u

1

u

1

0

1

0

1

0

1

0

u

0

u

WDT Wake-up

Brown-out Reset

Interrupt Wake-up from SLEEP

PC + 2⁽¹⁾u--u 00uu

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as '0'

Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (0x000008h or 0x000018h).

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 27

PIC18FXX8

FIGURE 3-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA RC NETWORK)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 3-4:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 3-5:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

DS41159B-page 28

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 3-6:

SLOW RISE TIME (MCLR TIED TO VDD VIA RC NETWORK)

5V

0V

1V

VDD

MCLR

TDEADTIME

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

FIGURE 3-7:

TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD

VIA RC NETWORK)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

TPLL

PLL TIME-OUT

INTERNAL RESET

TOST = 1024 clock cycles.

TPLL ≈ 2 ms max. First three stages of the PWRT timer.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 29

PIC18FXX8

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS

MCLR Reset

WDT Reset

RESETInstruction

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Register

Applicable Devices

TOSU

PIC18F2X8 PIC18F4X8

---0 0000

0000 0000

00-0 0000

---0 0000

0000 0000

--00 0000

0000 0000

xxxx xxxx

0000 000x

111- -1-1

11-- 0-00

N/A

---0 0000

0000 0000

uu-0 0000

---0 0000

0000 0000

--00 0000

0000 0000

uuuu uuuu

0000 000u

111- -1-1

11-- 0-00

N/A

---0 uuuu⁽³⁾

uuuu uuuu⁽³⁾

uu-u uuuu⁽³⁾

---u uuuu

uuuu uuuu

PC + 2⁽²⁾

--uu uuuu

uuuu uuuu

uuuu uuuu⁽¹⁾

uuuu -u-u⁽¹⁾

uu-u u-uu⁽¹⁾

N/A

TOSH

TOSL

STKPTR

PCLATU

PCLATH

PCL

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

PRODH

PRODL

INTCON

INTCON2

INTCON3

INDF0

POSTINC0

POSTDEC0

PREINC0

PLUSW0

FSR0H

N/A

---- 0000

xxxx xxxx

N/A

---- 0000

uuuu uuuu

N/A

---- uuuu

uuuu uuuu

N/A

FSR0L

WREG

INDF1

POSTINC1

POSTDEC1

PREINC1

PLUSW1

N/A

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008hor 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ’0’.

6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4).

DS41159B-page 30

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 3-3:

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Reset

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESETInstruction

Stack Resets

FSR1H

PIC18F2X8 PIC18F4X8

---- 0000

xxxx xxxx

---- 0000

N/A

---- 0000

uuuu uuuu

---- 0000

N/A

---- uuuu

uuuu uuuu

---- uuuu

N/A

FSR1L

BSR

INDF2

POSTINC2

POSTDEC2

PREINC2

PLUSW2

FSR2H

N/A

---- 0000

xxxx xxxx

---x xxxx

xxxx xxxx

1111 1111

---- ---0

--00 0101

---- ---0

0--1 11q0

xxxx xxxx

0-00 0000

xxxx xxxx

1111 1111

-000 0000

xxxx xxxx

0000 0000

---- 0000

uuuu uuuu

---u uuuu

uuuu uuuu

1111 1111

---- ---0

--00 0101

---- ---0

0--1 qquu

uuuu uuuu

u-uu uuuu

uuuu uuuu

1111 1111

-000 0000

uuuu uuuu

0000 0000

---- uuuu

uuuu uuuu

---u uuuu

uuuu uuuu

---- ---u

--uu uuuu

---- ---u

u--u qquu

uuuu uuuu

u-uu uuuu

uuuu uuuu

1111 1111

-uuu uuuu

uuuu uuuu

FSR2L

STATUS

TMR0H

TMR0L

T0CON

OSCCON

LVDCON

WDTCON

RCON⁽⁴⁾

TMR1H

TMR1L

T1CON

TMR2

PR2

T2CON

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008hor 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ’0’.

6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4).

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 31

PIC18FXX8

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Reset

WDT Reset

RESETInstruction

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Register

Applicable Devices

ADRESH

ADRESL

ADCON0

ADCON1

CCPR1H

CCPR1L

CCP1CON

ECCPR1H

ECCPR1L

ECCP1CON

ECCP1DEL

ECCPAS

CVRCON

CMCON

TMR3H

PIC18F2X8 PIC18F4X8

xxxx xxxx

0000 00-0

00-- 0000

xxxx xxxx

--00 0000

xxxx xxxx

0000 0000

xxxx xxxx

0000 0000

xxxx xxxx

0000 -01x

0000 000x

xxxx xxxx

xx-0 x000

1111 1111

0000 0000

uuuu uuuu

0000 00-0

00-- 0000

uuuu uuuu

--00 0000

uuuu uuuu

0000 0000

uuuu uuuu

0000 -01u

0000 000u

uuuu uuuu

uu-0 u000

1111 1111

0000 0000

uuuu uuuu

uuuu uu-u

uu-- uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

0000 0000

uuuu uuuu

uuuu -uuu

uuuu uuuu

uu-0 u000

uuuu uuuu

TMR3L

T3CON

SPBRG

RCREG

TXREG

TXSTA

RCSTA

EEADR

EEDATA

EECON2

EECON1

IPR3

PIR3

PIE3

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008hor 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ’0’.

6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4).

DS41159B-page 32

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 3-3:

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Reset

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESETInstruction

Stack Resets

IPR2

PIC18F2X8 PIC18F4X8

-1-1 1111

-0-0 0000

1111 1111

0000 0000

0000 -111

1111 1111

-111 1111⁽⁵⁾

---- -xxx

xxxx xxxx

-xxx xxxx⁽⁵⁾

---- -xxx

xxxx xxxx

-x0x 0000⁽⁵⁾

0000 0000

1000 ----

-0-- -000

0000 0000

xxxx xxx-

xxx- xxx-

-1-1 1111

-0-0 0000

1111 1111

0000 0000

0000 -111

1111 1111

-111 1111⁽⁵⁾

---- -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

---- -000

uuuu uuuu

-u0u 0000⁽⁵⁾

0000 0000

1000 ----

-0-- -000

0000 0000

uuuu uuu-

uuu- uuu-

-u-u uuuu

-u-u uuuu⁽¹⁾

-u-u uuuu

uuuu uuuu

uuuu uuuu⁽¹⁾

uuuu uuuu

uuuu -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

---- -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

---- -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

uuuu uuuu

uuuu ----

-u-- -uuu

uuuu uuuu

uuuu uuu-

uuu- uuu-

PIR2

PIE2

IPR1

PIR1

PIE1

TRISE

TRISD

TRISC

TRISB

TRISA⁽⁵⁾

LATE

LATD

LATC

LATB

LATA⁽⁵⁾

PORTE

PORTD

PORTC

PORTB

PORTA⁽⁵⁾

TXERRCNT

RXERRCNT

COMSTAT

CIOCON

BRGCON3

BRGCON2

BRGCON1

CANCON

CANSTAT⁽⁶⁾

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008hor 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ’0’.

6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4).

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 33

PIC18FXX8

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Reset

WDT Reset

RESETInstruction

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Register

Applicable Devices

RXB0D7

RXB0D6

RXB0D5

RXB0D4

RXB0D3

RXB0D2

RXB0D1

RXB0D0

RXB0DLC

RXB0EIDL

RXB0EIDH

RXB0SIDL

RXB0SIDH

RXB0CON

RXB1D7

RXB1D6

RXB1D5

RXB1D4

RXB1D3

RXB1D2

RXB1D1

RXB1D0

RXB1DLC

RXB1EIDL

RXB1EIDH

RXB1SIDL

RXB1SIDH

RXB1CON

TXB0D7

PIC18F2X8 PIC18F4X8

xxxx xxxx

0xxx xxxx

xxxx xxxx

xxxx x-xx

xxxx xxxx

000- 0000

xxxx xxxx

0xxx xxxx

xxxx xxxx

xxxx x0xx

xxxx xxxx

0000 0000

xxxx xxxx

uuuu uuuu

0uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

000- 0000

uuuu uuuu

0uuu uuuu

uuuu uuuu

uuuu u0uu

uuuu uuuu

0000 0000

uuuu uuuu

uuuu u-uu

uuuu uuuu

uuu- uuuu

uuuu uuuu

TXB0D6

TXB0D5

TXB0D4

TXB0D3

TXB0D2

TXB0D1

TXB0D0

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008hor 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ’0’.

6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4).

DS41159B-page 34

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 3-3:

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Reset

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESETInstruction

Stack Resets

TXB0DLC

TXB0EIDL

TXB0EIDH

TXB0SIDL

TXB0SIDH

TXB0CON

TXB1D7

PIC18F2X8 PIC18F4X8

0x00 xxxx

xxxx xxxx

xxx0 x0xx

xxxx xxxx

0000 0000

xxxx xxxx

0x00 xxxx

xxxx xxxx

xxx0 x0xx

xxxx xxxx

0000 0000

xxxx xxxx

0x00 xxxx

xxxx xxxx

xxx0 x0xx

xxxx xxxx

0000 0000

0u00 uuuu

uuuu uuuu

uuu0 u0uu

uuuu uuuu

0000 0000

uuuu uuuu

0u00 uuuu

uuuu uuuu

uuu0 u0uu

uuuu uuuu

0000 0000

uuuu uuuu

0u00 uuuu

uuuu uuuu

uuu0 u0uu

uuuu uuuu

0000 0000

uuuu uuuu

TXB1D6

TXB1D5

TXB1D4

TXB1D3

TXB1D2

TXB1D1

TXB1D0

TXB1DLC

TXB1EIDL

TXB1EIDH

TXB1SIDL

TXB1SIDH

TXB1CON

TXB2D7

TXB2D6

TXB2D5

TXB2D4

TXB2D3

TXB2D2

TXB2D1

TXB2D0

TXB2DLC

TXB2EIDL

TXB2EIDH

TXB2SIDL

TXB2SIDH

TXB2CON

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008hor 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ’0’.

6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4).

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 35

PIC18FXX8

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Reset

WDT Reset

RESETInstruction

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Register

Applicable Devices

RXM1EIDL

RXM1EIDH

RXM1SIDL

RXM1SIDH

RXM0EIDL

RXM0EIDH

RXM0SIDL

RXM0SIDH

RXF5EIDL

RXF5EIDH

RXF5SIDL

RXF5SIDH

RXF4EIDL

RXF4EIDH

RXF4SIDL

RXF4SIDH

RXF3EIDL

RXF3EIDH

RXF3SIDL

RXF3SIDH

RXF2EIDL

RXF2EIDH

RXF2SIDL

RXF2SIDH

RXF1EIDL

RXF1EIDH

RXF1SIDL

RXF1SIDH

RXF0EIDL

RXF0EIDH

RXF0SIDL

RXF0SIDH

PIC18F2X8 PIC18F4X8

xxxx xxxx

xxx- --xx

xxxx xxxx

xxx- --xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

uuuu uuuu

uuu- --uu

uuuu uuuu

uuu- --uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- --uu

uuuu uuuu

uuu- --uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008hor 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ’0’.

6: Values for CANSTAT also apply to to its other instances (CANSTATRO1 through CANSTATRO4).

DS41159B-page 36

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Figure 4-1 shows the diagram for program memory

map and stack for the PIC18F258 and PIC18F458.

Figure 4-2 shows the the diagram for the program

memory map and stack for the PIC18F248 and

PIC18F448.

4.0

MEMORY ORGANIZATION

There are three memory blocks in Enhanced MCU

devices. These memory blocks are:

• Enhanced FLASH Program Memory

• Data Memory

4.1.1

INTERNAL PROGRAM MEMORY

OPERATION

• EEPROM Data Memory

Data and program memory use separate busses,

which allows concurrent access of these blocks. Addi-

tional detailed information on Data EEPROM and

FLASH program memory is provided in Section 5.0 and

Section 6.0, respectively.

The PIC18F258 and the PIC18F458 have 32 Kbytes of

internal Enhanced FLASH program memory. This

means that the PIC18F258 and the PIC18F458 can

store up to 16K of single word instructions. The

PIC18F248 and PIC18F448 have 16 Kbytes of

Enhanced FLASH program memory. This translates

into 8192 single-word instructions, which can be stored

in the Program memory. Accessing a location between

the physically implemented memory and the 2 Mbyte

address will cause a read of all '0's (a NOPinstruction).

4.1

Program Memory Organization

The PIC18F258/458 devices have a 21-bit program

counter that is capable of addressing a 2 Mbyte

program memory space.

The RESET vector address is at 0000h and the

interrupt vector addresses are at 0008h and 0018h.

FIGURE 4-2:

PROGRAM MEMORY MAP

AND STACK FOR

PIC18F248/448

FIGURE 4-1:

PROGRAM MEMORY MAP

AND STACK FOR

PIC18F258/458

PC<20:0>

21

CALL,RCALL,RETURN

RETFIE,RETLW

CALL,RCALL,RETURN

RETFIE,RETLW

Stack Level 1

•

Stack Level 31

RESET Vector

Stack Level 31

RESET Vector

0000h

0008h

0000h

High Priority Interrupt Vector

Low Priority Interrupt Vector

0008h

0018h

Low Priority Interrupt Vector 0018h

On-Chip

Program Memory

3FFFh

4000h

On-Chip

Program Memory

7FFFh

8000h

Read ’0’

1FFFFFh

200000h

1FFFFFh

200000h

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 37

PIC18FXX8

4.2.2

RETURN STACK POINTER

(STKPTR)

4.2

Return Address Stack

The return address stack allows any combination of up

to 31 program calls and interrupts to occur. The PC

(Program Counter) is pushed onto the stack when a

PUSH, CALLor RCALLinstruction is executed, or an

interrupt is acknowledged. The PC value is pulled off

the stack on a RETURN, RETLWor a RETFIEinstruc-

tion. PCLATU and PCLATH are not affected by any of

the return instructions.

The STKPTR register contains the stack pointer value,

the STKFUL (stack full) status bit, and the STKUNF

(stack underflow) status bits. Register 4-1 shows the

STKPTR register. The value of the stack pointer can be

0 through 31. The stack pointer increments when val-

ues are pushed onto the stack and decrements when

values are popped off the stack. At RESET, the stack

pointer value will be 0. The user may read and write the

stack pointer value. This feature can be used by a Real

Time Operating System for return stack maintenance.

The stack operates as a 31-word by 21-bit stack mem-

ory and a 5-bit stack pointer, with the stack pointer ini-

tialized to 00000bafter all RESETS. There is no RAM

associated with stack pointer 00000b. This is only a

RESET value. During a CALLtype instruction causing

a push onto the stack, the stack pointer is first incre-

mented and the RAM location pointed to by the stack

pointer is written with the contents of the PC. During a

RETURNtype instruction causing a pop from the stack,

the contents of the RAM location indicated by the

STKPTR is transferred to the PC and then the stack

pointer is decremented.

After the PC is pushed onto the stack 31 times (without

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit can only be cleared in software or

by a POR.

The action that takes place when the stack becomes

full depends on the state of the STVREN (Stack Over-

flow Reset Enable) configuration bit. Refer to

Section 21.0 for a description of the device configura-

tion bits. If STVREN is set (default), the 31st push will

push the (PC + 2) value onto the stack, set the STKFUL

bit, and reset the device. The STKFUL bit will remain

set and the stack pointer will be set to 0.

The stack space is not part of either program or data

space. The stack pointer is readable and writable, and

the data on the top of the stack is readable and writable

through SFR registers. Status bits indicate if the stack

pointer is at or beyond the 31 levels provided.

If STVREN is cleared, the STKFUL bit will be set on the

31st push and the stack pointer will increment to 31.

The 32nd push will overwrite the 31st push (and so on),

while STKPTR remains at 31.

4.2.1

TOP-OF-STACK ACCESS

The top of the stack is readable and writable. Three

register locations, TOSU, TOSH and TOSL allow

access to the contents of the stack location indicated by

the STKPTR register. This allows users to implement a

software stack, if necessary. After a CALL, RCALLor

interrupt, the software can read the pushed value by

reading the TOSU, TOSH and TOSL registers. These

values can be placed on a user defined software stack.

At return time, the software can replace the TOSU,

TOSH and TOSL and do a return.

When the stack has been popped enough times to

unload the stack, the next pop will return a value of zero

to the PC and sets the STKUNF bit, while the stack

pointer remains at 0. The STKUNF bit will remain set

until cleared in software or a POR occurs.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the

program to the RESET vector, where the

stack conditions can be verified and

appropriate actions can be taken.

The user should disable the global interrupt enable bits

during this time to prevent inadvertent stack

operations.

DS41159B-page 38

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 4-1:

STKPTR - STACK POINTER REGISTER

R/C-0

STKFUL

bit 7

R/C-0

U-0

R/W-0

SP4

R/W-0

SP3

R/W-0

SP2

R/W-0

SP1

R/W-0

SP0

STKUNF

—

bit 0

bit 7

bit 6

bit 5

STKFUL: Stack Full Flag bit

1= Stack became full or overflowed

0= Stack has not become full or overflowed

STKUNF: Stack Underflow Flag bit

1= Stack underflow occurred

0= Stack underflow did not occur

Unimplemented: Read as '0'

bit 4-0 SP4:SP0: Stack Pointer Location bits

Note: Bit 7 and bit 6 need to be cleared following a stack underflow or a stack overflow.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared C = Clearable bit

’1’ = Bit is set

FIGURE 4-3:

RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

Return Address Stack

11111

11110

11101

STKPTR<4:0>

00010

TOSU

00h

TOSH

1Ah

TOSL

34h

00011

001A34h 00010

000D58h 00001

000000h 00000⁽¹⁾

Top-of-Stack

Note 1: No RAM associated with this address; always maintained ‘0’s.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 39

PIC18FXX8

4.2.3

PUSHAND POPINSTRUCTIONS

EXAMPLE 4-1:

FAST REGISTER STACK

CODE EXAMPLE

Since the Top-of-Stack (TOS) is readable and writable,

the ability to push values onto the stack and pull values

off the stack without disturbing normal program execu-

tion is a desirable option. To push the current PC value

onto the stack, a PUSH instruction can be executed.

This will increment the stack pointer and load the cur-

rent PC value onto the stack. TOSU, TOSH and TOSL

can then be modified to place a return address on the

stack.

CALL SUB1, FAST

;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK

•

SUB1

•

RETURN FAST

;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

The POPinstruction discards the current TOS by decre-

menting the stack pointer. The previous value pushed

onto the stack then becomes the TOS value.

4.4

PCL, PCLATH and PCLATU

4.2.4

STACK FULL/UNDERFLOW RESETS

The program counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21-bits

wide. The low byte is called the PCL register. This reg-

ister is readable and writable. The high byte is called

the PCH register. This register contains the PC<15:8>

bits and is not directly readable or writable. Updates to

the PCH register may be performed through the

PCLATH register. The upper byte is called PCU. This

register contains the PC<20:16> bits and is not directly

readable or writable. Updates to the PCU register may

be performed through the PCLATU register.

These RESETS are enabled by programming the

STVREN configuration bit. When the STVREN bit is

disabled, a full or underflow condition will set the appro-

priate STKFUL or STKUNF bit, but not cause a device

RESET. When the STVREN bit is enabled, a full or

underflow condition will set the appropriate STKFUL or

STKUNF bit and then cause a device RESET. The

STKFUL or STKUNF bits are only cleared by the user

software or a POR.

4.3

Fast Register Stack

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the LSb of PCL is fixed to a value of ’0’.

The PC increments by 2 to address sequential instruc-

tions in the program memory.

A “fast return” option is available for interrupts and

calls. A fast register stack is provided for the STATUS,

WREG and BSR registers and is only one layer in

depth. The stack is not readable or writable and is

loaded with the current value of the corresponding reg-

ister when the processor vectors for an interrupt. The

values in the fast register stack are then loaded back

The CALL, RCALL, GOTO and program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

into the working registers if the fast

return

instruction is used to return from the interrupt.

The contents of PCLATH and PCLATU will be trans-

ferred to the program counter by an operation that

writes PCL. Similarly, the upper two bytes of the pro-

gram counter will be transferred to PCLATH and

PCLATU by an operation that reads PCL. This is useful

for computed offsets to the PC (see Section 4.8.1).

A low or high priority interrupt source will push values

into the stack registers. If both low and high priority

interrupts are enabled, the stack registers cannot be

used reliably for low priority interrupts. If a high priority

interrupt occurs while servicing a low priority interrupt,

the stack register values stored by the low priority

interrupt will be overwritten.

If high priority interrupts are not disabled during low pri-

ority interrupts, users must save the key registers in

software during a low priority interrupt.

If no interrupts are used, the fast register stack can be

used to restore the STATUS, WREG and BSR registers

at the end of a subroutine call. To use the fast register

stack for a subroutine call, a fast call instruction

must be executed.

Example 4-1 shows a source code example that uses

the fast register stack.

DS41159B-page 40

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clocks and instruction execution flow

are shown in Figure 4-4.

4.5

Clocking Scheme/Instruction

Cycle

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-

gram counter (PC) is incremented every Q1, the

FIGURE 4-4:

CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Internal

Phase

Clock

Q2

Q3

Q4

PC

PC+2

PC+4

OSC2/CLKO

(RC Mode)

Fetch INST (PC)

Execute INST (PC-2)

Fetch INST (PC+2)

Execute INST (PC)

Fetch INST (PC+4)

Execute INST (PC+2)

4.6

Instruction Flow/Pipelining

4.7

Instructions in Program Memory

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute take another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO),

two cycles are required to complete the instruction

(Example 4-2).

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte of an instruction

word is always stored in a program memory location

with an even address (LSB = ’0’). Figure 4-3 shows an

example of how instruction words are stored in the pro-

gram memory. To maintain alignment with instruction

boundaries, the PC increments in steps of 2 and the

LSB will always read ’0’ (see Section 4.4).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

The CALLand GOTOinstructions have an absolute pro-

gram memory address embedded into the instruction.

Since instructions are always stored on word bound-

aries, the data contained in the instruction is a word

address. The word address is written to PC<20:1>,

which accesses the desired byte address in program

memory. Instruction #2 in Example 4-3 shows how the

instruction “GOTO 000006h” is encoded in the program

memory. Program branch instructions that encode a

relative address offset operate in the same manner.

The offset value stored in a branch instruction repre-

sents the number of single word instructions by which

the PC will be offset. Section 25.0 provides further

details of the instruction set.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register” (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 41

PIC18FXX8

EXAMPLE 4-2:

INSTRUCTION PIPELINE FLOW

TCY0

TCY1

TCY2

TCY3

TCY4

TCY5

1. MOVLW 55h

2. MOVWF PORTB

3. BRA SUB_1

Fetch 1

Execute 1

Fetch 2

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

PORTA, BIT3 (Forced NOP)

Flush

5. Instruction @ address SUB_1

Fetch SUB_1

Execute SUB_1

Note:

All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction

is “flushed” from the pipeline while the new instruction is being fetched and then executed.

EXAMPLE 4-3:

INSTRUCTIONS IN PROGRAM MEMORY

Instruction

Opcode

Memory

Address

—

000007h

000008h

000009h

00000Ah

00000Bh

00000Ch

00000Dh

00000Eh

00000Fh

000010h

000011h

000012h

MOVLW 055h

0E55h

55h

0Eh

03h

EFh

00h

F0h

23h

C1h

56h

F4h

GOTO 000006h

EF03h, F000h

MOVFF 123h, 456h

C123h, F456h

—

DS41159B-page 42

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

A lookup table can be formed with an ADDWF PCL

instruction and a group of RETLW 0xnn instructions.

WREG is loaded with an offset into the table before

executing a call to that table. The first instruction of the

called routine is the ADDWF PCLinstruction. The next

instruction executed will be one of the RETLW 0xnn

instructions that returns the value 0xnn to the calling

function.

4.7.1

TWO-WORD INSTRUCTIONS

The PIC18FXX8 devices have 4 two-word instructions:

MOVFF, CALL, GOTOand LFSR. The 4 Most Signifi-

cant bits of the second word are set to ‘1’s, and indicate

a special NOPinstruction. The lower 12 bits of the sec-

ond word contain the data to be used by the instruction.

If the first word of the instruction is executed, the data

in the second word is accessed. If the second word of

the instruction is executed by itself (first word was

skipped), it will execute as a NOP. This action is neces-

sary when the two-word instruction is preceded by a

conditional instruction that changes the PC. A program

example that demonstrates this concept is shown in

Example 4-4. Refer to Section 25.0 for further details of

the instruction set.

The offset value (value in WREG) specifies the number

of bytes that the program counter should advance.

In this method, only one data byte may be stored in

each instruction location and room on the return

address stack is required.

Warning: The LSb of PCL is fixed to a value of ‘0’.

Hence, computed GOTO to an odd

address is not possible.

4.8

Lookup Tables

4.8.2

TABLE READS/TABLE WRITES

Lookup tables are implemented two ways. These are:

• Computed GOTO

• Table Reads

A better method of storing data in program memory

allows 2 bytes of data to be stored in each instruction

location.

4.8.1

COMPUTED GOTO

Lookup table data may be stored as 2 bytes per pro-

gram word by using table reads and writes. The table

pointer (TBLPTR) specifies the byte address and the

table latch (TABLAT) contains the data that is read

from, or written to, program memory. Data is

transferred to/from program memory, one byte at a

time.

A computed GOTOis accomplished by adding an offset

to the program counter (ADDWF PCL).

The ADDWF PCLinstruction does not update PCLATH/

PCLATU. A read operation on PCL must be performed

prior to the ADDWF PCL.

A description of the Table Read/Table Write operation

is shown in Section 6.1.

EXAMPLE 4-4:

CASE 1:

TWO-WORD INSTRUCTIONS

Object Code

Source Code

0110 0110 0000 0000 TSTFSZ

1100 0001 0010 0011 MOVFF

1111 0100 0101 0110

REG1

; is RAM location 0?

REG1, REG2 ; No, execute 2-word instruction

; 2nd operand holds address of REG2

0010 0100 0000 0000 ADDWF

REG3

; continue code

CASE 2:

Object Code

Source Code

0110 0110 0000 0000 TSTFSZ

1100 0001 0010 0011 MOVFF

1111 0100 0101 0110

REG1

; is RAM location 0?

REG1, REG2 ; Yes

; 2nd operand becomes NOP

REG3 ; continue code

0010 0100 0000 0000 ADDWF

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 43

PIC18FXX8

4.9.1

GENERAL PURPOSE REGISTER

FILE

4.9

Data Memory Organization

The data memory is implemented as static RAM. Each

register in the data memory has a 12-bit address,

allowing up to 4096 bytes of data memory. Figure 4-6

shows the data memory organization for the

PIC18FXX8 devices.

The register file can be accessed either directly, or indi-

rectly. Indirect addressing operates through the File

Select Registers (FSR). The operation of indirect

addressing is shown in Section 4.12.

The data memory map is divided into as many as 16

banks that contain 256 bytes each. The lower 4 bits of

the Bank Select Register (BSR<3:0>) select which

bank will be accessed. The upper 4 bits for the BSR are

not implemented.

Enhanced MCU devices may have banked memory in

the GPR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other RESETS.

Data RAM is available for use as GPR registers by all

instructions. Bank 15 (F00h to FFFh) contains SFRs.

All other banks of data memory contain GPR registers,

starting with bank 0.

The data memory contains Special Function Registers

(SFRs) and General Purpose Registers (GPRs). The

SFRs are used for control and status of the controller

and peripheral functions, while GPR’s are used for data

storage and scratch pad operations in the user’s appli-

cation. The SFR’s start at the last location of Bank 15

(FFFh) and grow downwards. GPRs start at the first

location of Bank 0 and grow upwards. Any read of an

unimplemented location will read as ’0’s.

4.9.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and Peripheral Modules for control-

ling the desired operation of the device. These regis-

ters are implemented as static RAM. A list of these

registers is given in Table 4-1.

The entire data memory may be accessed directly, or

indirectly. Direct addressing may require the use of the

BSR register. Indirect addressing requires the use of

the File Select Register (FSR). Each FSR holds a

12-bit address value that can be used to access any

location in the Data Memory map without banking.

The SFRs can be classified into two sets: those asso-

ciated with the “core” function and those related to the

peripheral functions. Those registers related to the

“core” are described in this section, while those related

to the operation of the peripheral features are

described in the section of that peripheral feature.

The instruction set and architecture allow operations

across all banks. This may be accomplished by indirect

addressing or by the use of the MOVFFinstruction. The

MOVFF instruction is a two-word/two-cycle instruction,

that moves a value from one register to another.

The SFRs are typically distributed among the

peripherals whose functions they control.

The unused SFR locations will be unimplemented and

read as '0's. See Table 4-1 for addresses for the SFRs.

To ensure that commonly used registers (SFRs and

select GPRs) can be accessed in a single cycle,

regardless of the current BSR values, an Access Bank

is implemented. A segment of Bank 0 and a segment of

Bank 15 comprise the Access RAM. Section 4.10

provides a detailed description of the Access RAM.

DS41159B-page 44

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 4-5:

BSR<3:0>

= 0000

DATA MEMORY MAP FOR PIC18F248/448

Data Memory Map

000h

05Fh

00h

Access RAM

GPR

Bank 0

Bank 1

060h

0FFh

100h

FFh

00h

= 0001

GPR

1FFh

200h

FFh

00h

FFh

300h

Access Bank

00h

Access RAM

5Fh

60h

= 0010

= 1110

SFR

FFh

Bank 2

to

Bank 14

Unused

Read ’00h’

When a = 0,

the BSR is ignored and

the Access Bank is used.

The first 96 bytes are

General Purpose RAM

(from Bank 0).

The next 160 bytes are

Special Function

Registers (from Bank 15).

When a = 1,

EFFh

F00h

F5Fh

F60h

FFFh

the BSR is used to specify

the RAM location that the

instruction uses.

00h

FFh

Unused

SFR

= 1111

Bank 15

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 45

PIC18FXX8

FIGURE 4-6:

BSR<3:0>

= 0000

DATA MEMORY MAP FOR PIC18F258/458

Data Memory Map

000h

05Fh

060h

0FFh

00h

Access RAM

GPR

Bank 0

FFh

00h

100h

= 0001

= 0010

GPR

Bank 1

Bank 2

Bank 3

1FFh

200h

FFh

00h

2FFh

300h

FFh

00h

= 0011

= 0100

= 0101

GPR

FFh

3FFh

400h

Access Bank

Bank 4

Bank 5

GPR

4FFh

500h

00h

5Fh

Access Bank low

(GPR)

00h

FFh

5FFh

600h

60h

FFh

Access Bank high

(SFR)

= 0110

= 1110

When a = 0,

Bank 6

to

Bank 14

Unused

Read ‘00h’

the BSR is ignored and the

Access Bank is used.

The first 96 bytes are

General Purpose RAM

(from Bank 0).

EFFh

F00h

F5Fh

F60h

FFFh

The next 160 bytes are

SpecialFunctionRegisters

(from Bank 15).

00h

FFh

SFR

= 1111

Bank 15

When a = 1,

the BSR is used to specify

the RAM location that the

instruction uses.

DS41159B-page 46

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 4-1:

Address

SPECIAL FUNCTION REGISTER MAP

Name

Address

Name

Address

Name

Address

Name

FFFh TOSU

FDFh INDF2⁽²⁾

FBFh CCPR1H

F9Fh IPR1

FFEh TOSH

FDEh POSTINC2⁽²⁾

FDDh POSTDEC2⁽²⁾

FDCh PREINC2⁽²⁾

FDBh PLUSW2⁽²⁾

FDAh FSR2H

FBEh CCPR1L

F9Eh PIR1

F9Dh PIE1

F9Ch

FFDh TOSL

FBDh CCP1CON

FBCh ECCPR1H⁽⁵⁾

FBBh ECCPR1L⁽⁵⁾

FBAh ECCP1CON⁽⁵⁾

FFCh STKPTR

FFBh PCLATU

FFAh PCLATH

FF9h PCL

—

F9Bh

F9Ah

FD9h FSR2L

FB9h

—

F99h

FF8h TBLPTRU

FF7h TBLPTRH

FF6h TBLPTRL

FF5h TABLAT

FF4h PRODH

FF3h PRODL

FD8h STATUS

FD7h TMR0H

FB8h

—

F98h

FB7h ECCP1DEL⁽⁵⁾

FB6h ECCPAS⁽⁵⁾

FB5h CVRCON⁽⁵⁾

FB4h CMCON⁽⁵⁾

FB3h TMR3H

F97h

FD6h TMR0L

F96h TRISE⁽⁵⁾

F95h TRISD⁽⁵⁾

F94h TRISC

F93h TRISB

F92h TRISA

FD5h T0CON

FD4h

—

FD3h OSCCON

FD2h LVDCON

FD1h WDTCON

FD0h RCON

FF2h INTCON

FF1h INTCON2

FF0h INTCON3

FEFh INDF0⁽²⁾

FEEh POSTINC0⁽²⁾

FEDh POSTDEC0⁽²⁾

FECh PREINC0⁽²⁾

FEBh PLUSW0⁽²⁾

FEAh FSR0H

FB2h TMR3L

FB1h T3CON

F91h

F90h

F8Fh

F8Eh

—

FB0h

—

FCFh TMR1H

FCEh TMR1L

FCDh T1CON

FCCh TMR2

FAFh SPBRG

FAEh RCREG

FADh TXREG

FACh TXSTA

FABh RCSTA

F8Dh LATE⁽⁵⁾

F8Ch LATD⁽⁵⁾

F8Bh LATC

F8Ah LATB

F89h LATA

FCBh PR2

FCAh T2CON

FC9h SSPBUF

FC8h SSPADD

FC7h SSPSTAT

FC6h SSPCON1

FC5h SSPCON2

FC4h ADRESH

FC3h ADRESL

FC2h ADCON0

FC1h ADCON1

FAAh

—

FE9h FSR0L

FA9h EEADR

FA8h EEDATA

FA7h EECON2

FA6h EECON1

FA5h IPR3

FA4h PIR3

FA3h PIE3

FA2h IPR2

FA1h PIR2

FA0h PIE2

FE8h WREG

F88h

F87h

F86h

F85h

—

FE7h INDF1⁽²⁾

FE6h POSTINC1⁽²⁾

FE5h POSTDEC1⁽²⁾

FE4h PREINC1⁽²⁾

FE3h PLUSW1⁽²⁾

FE2h FSR1H

F84h PORTE⁽⁵⁾

F83h PORTD⁽⁵⁾

F82h PORTC

F81h PORTB

F80h PORTA

FE1h FSR1L

FE0h BSR

FC0h

—

Note 1: Unimplemented registers are read as ’0’.

2: This is not a physical register.

3: Contents of register are dependent on WIN2:WIN0 bits in CANCON register.

4: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given

for each instance of the CANSTAT register, due to the Microchip Header file requirement.

5: These registers are not implemented on the PIC18F248 and PIC18F258.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 47

PIC18FXX8

TABLE 4-1:

SPECIAL FUNCTION REGISTER MAP (CONTINUED)

Address

Name

Address

Name

Address

Name

Address

Name

F7Fh

F7Eh

F7Dh

F7Ch

F7Bh

F7Ah

F79h

F78h

F77h

—

F5Fh

—

F3Fh

—

F1Fh RXM1EIDL

F1Eh RXM1EIDH

F1Dh RXM1SIDL

F1Ch RXM1SIDH

F1Bh RXM0EIDL

F1Ah RXM0EIDH

F19h RXM0SIDL

F18h RXM0SIDH

F17h RXF5EIDL

F16h RXF5EIDH

F15h RXF5SIDL

F14h RXF5SIDH

F13h RXF4EIDL

F12h RXF4EIDH

F11h RXF4SIDL

F10h RXF4SIDH

F0Fh RXF3EIDL

F0Eh RXF3EIDH

F0Dh RXF3SIDL

F0Ch RXF3SIDH

F0Bh RXF2EIDL

F0Ah RXF2EIDH

F09h RXF2SIDL

F08h RXF2SIDH

F07h RXF1EIDL

F06h RXF1EIDH

F05h RXF1SIDL

F04h RXF1SIDH

F03h RXF0EIDL

F02h RXF0EIDH

F01h RXF0SIDL

F00h RXF0SIDH

F5Eh CANSTATRO1⁽⁴⁾

F5Dh RXB1D7

F5Ch RXB1D6

F5Bh RXB1D5

F5Ah RXB1D4

F59h RXB1D3

F58h RXB1D2

F57h RXB1D1

F56h RXB1D0

F55h RXB1DLC

F54h RXB1EIDL

F53h RXB1EIDH

F52h RXB1SIDL

F51h RXB1SIDH

F50h RXB1CON

F3Eh CANSTATRO3⁽⁴⁾

F3Dh TXB1D7

F3Ch TXB1D6

F3Bh TXB1D5

F3Ah TXB1D4

F39h TXB1D3

F38h TXB1D2

F37h TXB1D1

F36h TXB1D0

F35h TXB1DLC

F34h TXB1EIDL

F33h TXB1EIDH

F32h TXB1SIDL

F31h TXB1SIDH

F30h TXB1CON

F76h TXERRCNT

F75h RXERRCNT

F74h COMSTAT

F73h CIOCON

F72h BRGCON3

F71h BRGCON2

F70h BRGCON1

F6Fh CANCON

F4Fh

—

F2Fh

—

F6Eh CANSTAT

F6Dh RXB0D7⁽³⁾

F6Ch RXB0D6⁽³⁾

F6Bh RXB0D5⁽³⁾

F6Ah RXB0D4⁽³⁾

F69h RXB0D3⁽³⁾

F68h RXB0D2⁽³⁾

F67h RXB0D1⁽³⁾

F66h RXB0D0⁽³⁾

F65h RXB0DLC⁽³⁾

F64h RXB0EIDL⁽³⁾

F63h RXB0EIDH⁽³⁾

F62h RXB0SIDL⁽³⁾

F61h RXB0SIDH⁽³⁾

F60h RXB0CON⁽³⁾

F4Eh CANSTATRO2⁽⁴⁾

F4Dh TXB0D7

F4Ch TXB0D6

F4Bh TXB0D5

F4Ah TXB0D4

F49h TXB0D3

F48h TXB0D2

F47h TXB0D1

F46h TXB0D0

F45h TXB0DLC

F44h TXB0EIDL

F43h TXB0EIDH

F42h TXB0SIDL

F41h TXB0SIDH

F40h TXB0CON

F2Eh CANSTATRO4⁽⁴⁾

F2Dh TXB2D7

F2Ch TXB2D6

F2Bh TXB2D5

F2Ah TXB2D4

F29h TXB2D3

F28h TXB2D2

F27h TXB2D1

F26h TXB2D0

F25h TXB2DLC

F24h TXB2EIDL

F23h TXB2EIDH

F22h TXB2SIDL

F21h TXB2SIDH

F20h TXB2CON

Note: Shaded registers are available in Bank 15, while the rest are in Access Bank low.

Note 1: Unimplemented registers are read as ’0’.

2: This is not a physical register.

3: Contents of register are dependent on WIN2:WIN0 bits in CANCON register.

4: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given

for each instance of the CANSTAT register, due to the Microchip Header file requirement.

5: These registers are not implemented on the PIC18F248 and PIC18F258.

DS41159B-page 48

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 4-2:

REGISTER FILE SUMMARY

Value on Details on

Bit 0

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

POR, BOR

Page:

TOSU

TOSH

TOSL

—

Top-of-Stack Upper Byte (TOS<20:16>)

---0 0000

0000 0000

00-0 0000

30, 38

30, 39

Top-of-Stack High Byte (TOS<15:8>)

Top-of-Stack Low Byte (TOS<7:0>)

STKPTR

STKFUL

STKUNF

—

Return Stack Pointer

(2)

PCLATU

PCLATH

PCL

—

bit21

Holding Register for PC<20:16>

---0 0000

0000 0000

30, 40

Holding Register for PC<15:8>

PC Low Byte (PC<7:0>)

(2)

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

PRODH

PRODL

—

bit21

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

--00 0000

0000 0000

xxxx xxxx

0000 000x

111- -1-1

30, 68

30, 75

30, 79

30, 80

30, 81

30, 55

31, 55

31, 54

31, 55

31, 57

Program Memory Table Pointer High Byte (TBLPTR<15:8>)

Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

Program Memory Table Latch

Product Register High Byte

Product Register Low Byte

INTCON

INTCON2

INTCON3

INDF0

GIE/GIEH PEIE/GIEL

TMR0IE

INTEDG1

—

INT0IE

—

RBIE

—

TMR0IF

TMR0IP

—

INT0IF

—

RBIF

RBIP

RBPU

INTEDG0

INT1IP

INT2IP

INT2IE

INT1IE

INT2IF

INT1IF 11-1 0-00

Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)

Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)

Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)

Uses contents of FSR0 to address data memory - value of FSR0 offset by W (not a physical register)

n/a

POSTINC0

POSTDEC0

PREINC0

PLUSW0

FSR0H

n/a

—

Indirect Data Memory Address Pointer 0 High

---- xxxx

xxxx xxxx

uuuu uuuu

n/a

FSR0L

Indirect Data Memory Address Pointer 0 Low Byte

Working Register

WREG

INDF1

Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)

Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register)

Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)

Uses contents of FSR1 to address data memory - value of FSR1 offset by W (not a physical register) -

POSTINC1

POSTDEC1

PREINC1

PLUSW1

FSR1H

n/a

—

Indirect Data Memory Address Pointer 1 High

---- xxxx

xxxx xxxx

---- 0000

n/a

FSR1L

Indirect Data Memory Address Pointer 1 Low Byte

BSR

—

Bank Select Register

INDF2

Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)

Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)

Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)

Uses contents of FSR2 to address data memory - value of FSR2 offset by W (not a physical register) -

POSTINC2

POSTDEC2

PREINC2

PLUSW2

FSR2H

n/a

—

Indirect Data Memory Address Pointer 2 High

---- xxxx

xxxx xxxx

---x xxxx

FSR2L

Indirect Data Memory Address Pointer 2 Low Byte

STATUS

TMR0H

—

N

OV

Z

DC

C

Timer0 Register High Byte

Timer0 Register Low Byte

0000 0000 31, 109

xxxx xxxx 31, 109

TMR0L

T0CON

TMR0ON

T08BIT

—

T0CS

—

T0SE

—

PSA

—

T0PS2

—

T0PS1

—

T0PS0 1111 1111 31, 107

SCS ---- ---0 31, 20

OSCCON

LVDCON

WDTCON

—

IRVST

—

LVDEN

—

LVDL3

—

LVDL2

—

LVDL1

—

LVDL0 --00 0101 31, 257

SWDTEN ---- ---0 31, 268

—

RCON

IPEN

—

RI

TO

PD

POR

BOR

0--1 11qq 31, 58, 91

Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition

Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ’0’s.

2: Bit21 of the TBLPTRU allows access to the device configuration bits.

3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other Oscillator

modes.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 49

PIC18FXX8

TABLE 4-2:

REGISTER FILE SUMMARY (CONTINUED)

Value on Details on

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR

Page:

TMR1H

TMR1L

Timer1 Register High Byte

Timer1 Register Low Byte

xxxx xxxx

31, 113

T1CON

RD16

—

T1CKPS1

T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000

31, 111

31, 116

31, 115

TMR2

Timer2 Register

0000 0000

1111 1111

PR2

Timer2 Period Register

TOUTPS3 TOUTPS2

T2CON

—

TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

ADRESH

ADRESL

ADCON0

ADCON1

CCPR1H

CCPR1L

CCP1CON

SSP Receive Buffer/Transmit Register

2

xxxx xxxx 31, 144

0000 0000 31, 150

0000 0000 31, 142, 151

2

SSP Address Register in I C Slave mode. SSP Baud Rate Reload Register in I C Master mode.

SMP

WCOL

GCEN

CKE

D/A

P

S

R/W

SSPM2

PEN

UA

BF

SSPOV

ACKSTAT

SSPEN

ACKDT

CKP

SSPM3

RCEN

SSPM1

RSEN

SSPM0 0000 0000 31, 143, 152

ACKEN

SEN

0000 0000 31, 153

xxxx xxxx 32, 239

0000 00-0 32, 237

A/D Result Register High Byte

A/D Result Register Low Byte

ADCS1

ADFM

ADCS0

ADCS2

CHS2

CHS1

CHS0

GO/DONE

PCFG2

—

ADON

—

PCFG3

PCFG1

PCFG0 00-- 0000 32, 238

xxxx xxxx 32, 122

Capture/Compare/PWM Register1 High Byte

Capture/Compare/PWM Register1 Low Byte

xxxx xxxx 32, 122

—

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 32, 121

xxxx xxxx 32, 131

(1)

ECCPR1H

Enhanced Capture/Compare/PWM Register1 High Byte

Enhanced Capture/Compare/PWM Register1 Low Byte

(1)

ECCPR1L

xxxx xxxx 32, 131

(1)

ECCP1CON

EPWM1M1 EPWM1M0 EDC1B1

EPDC7 EPDC6 EPDC5

ECCPASE ECCPAS2 ECCPAS1

EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 32, 129

(1)

ECCP1DEL

EPDC4

ECCPAS0

CVRSS

C1INV

EPDC3

PSSAC1

CVR3

EPDC2

PSSAC0

CVR2

EPDC1

EPDC0 0000 0000 32, 138

(1)

ECCPAS

PSSBD1 PSSBD0 0000 0000 32, 140

(1)

CVRCON

CVREN

C2OUT

CVROE

C1OUT

CVRR

C2INV

CVR1

CM1

CVR0

CM0

0000 0000 32, 251

0000 0000 32, 245

(1)

CMCON

CIS

CM2

TMR3H

TMR3L

T3CON

SPBRG

RCREG

TXREG

TXSTA

RCSTA

EEADR

EEDATA

EECON2

EECON1

IPR3

Timer3 Register High Byte

Timer3 Register Low Byte

xxxx xxxx

32, 119

32, 117

RD16

T3ECCP1

T3CKPS1

T3CKPS0

T3CCP1

T3SYNC TMR3CS TMR3ON 0000 0000

USART1 Baud Rate Generator

USART1 Receive Register

USART1 Transmit Register

0000 0000 32, 183

0000 0000 32, 189

0000 0000 32, 187

0000 -010 32, 181

0000 000X 32, 182

CSRC

SPEN

TX9

RX9

TXEN

SREN

SYNC

CREN

—

BRGH

FERR

TRMT

OERR

TX9D

RX9D

ADDEN

EEPROM Address Register

EEPROM Data Register

xxxx xxxx

32, 59

EEPROM Control Register2 (not a physical register)

EEPGD

IRXIP

IRXIF

IRXIE

—

CFGS

WAKIP

WAKIF

WAKIE

CMIP

—

ERRIP

ERRIF

ERRIE

—

FREE

TXB2IP

TXB2IF

TXB2IE

EEIP

WRERR

TXB1IP

TXB1IF

TXB1IE

BCLIP

WREN

TXB0IP

TXB0IF

TXB0IE

LVDIP

WR

RD

xx-0 x000 32, 60, 67

RXB1IP

RXB1IF

RXB1IE

RXB0IP 1111 1111

RXB0IF 0000 0000

32, 90

32, 84

32, 87

33, 89

33, 83

33, 86

PIR3

PIE3

RXB0IE 0000 0000

(1)

IPR2

TMR3IP ECCP1IP -1-1 1111

(1)

PIR2

—

CMIF

—

EEIF

BCLIF

LVDIF

TMR3IF ECCP1IF -0-0 0000

(1)

PIE2

—

CMIE

—

EEIE

BCLIE

LVDIE

TMR3IE ECCP1IE -0-0 0000

Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition

Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ’0’s.

2: Bit21 of the TBLPTRU allows access to the device configuration bits.

3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other Oscillator

modes.

DS41159B-page 50

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 4-2:

REGISTER FILE SUMMARY (CONTINUED)

Value on Details on

Bit 0

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

POR, BOR

Page:

IPR1

PIR1

PIE1

PSPIP

PSPIF

PSPIE

IBF

ADIP

ADIF

ADIE

OBF

RCIP

RCIF

RCIE

IBOV

TXIP

TXIF

TXIE

SSPIP

SSPIF

SSPIE

—

CCP1IP

CCP1IF

CCP1IE

TMR2IP

TMR2IF

TMR2IE

TMR1IP 1111 1111

TMR1IF 0000 0000

33, 88

33, 82

TMR1IE 0000 0000

33, 85

(1)

TRISE

PSPMODE

Data Direction bits for PORTE

0000 -111 33, 103

1111 1111 33, 100

(1)

TRISD

Data Direction Control Register for PORTD

TRISC

TRISB

Data Direction Control Register for PORTC

Data Direction Control Register for PORTB

1111 1111

33, 98

33, 95

(3)

TRISA

—

Data Direction Control Register for PORTA

--11 1111

33, 93

(1)

LATE

—

Read PORTE Data Latch, Write

PORTE Data Latch

---- -xxx 33, 102

(1)

LATD

Read PORTD Data Latch, Write PORTD Data Latch

Read PORTC Data Latch, Write PORTC Data Latch

Read PORTB Data Latch, Write PORTB Data Latch

xxxx xxxx 33, 100

LATC

LATB

xxxx xxxx

33, 98

33, 95

(3)

LATA

—

Read PORTA Data Latch, Write PORTA Data Latch

-xxx xxxx

33, 93

(1)

PORTE

—

Read PORTE pins, Write PORTE

Data Latch

---- -000 33, 102

(1)

PORTD

Read PORTD pins, Write PORTD Data Latch

Read PORTC pins, Write PORTC Data Latch

Read PORTB pins, Write PORTB Data Latch

xxxx xxxx 33, 100

PORTC

PORTB

xxxx xxxx

33, 98

33, 95

(3)

PORTA

—

Read PORTA pins, Write PORTA Data Latch

-x0x 0000

33, 93

TXERRCNT

RXERRCNT

COMSTAT

CIOCON

TEC7

REC7

TEC6

REC6

TEC5

REC5

TEC4

REC4

TXBP

CANCAP

—

TEC3

REC3

RXBP

—

TEC2

REC2

TEC1

REC1

TEC0

REC0

0000 0000 33, 207

0000 0000 33, 212

RXB0OVFL RXB1OVFL

TXBO

TXWARN RXWARN EWARN 0000 0000 33, 203

--00 ---- 33, 217

SEG2PH2 SEG2PH1 SEG2PH0 -0-- -000 33, 217

—

ENDRHI

—

BRGCON3

BRGCON2

BRGCON1

CANCON

CANSTAT

RXB0D7

WAKFIL

SAM

—

SEG2PHTS

SJW1

SEG1PH2

BRP5

SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 0000 0000 33, 216

SJW0

BRP4

ABAT

—

BRP3

WIN2

BRP2

WIN1

BRP1

WIN0

BRP0

—

0000 0000 33, 215

xxxx xxx- 33, 199

xxx- xxx- 33, 200

REQOP2

REQOP1

REQOP0

OPMODE2 OPMODE1 OPMODE0

ICODE2

ICODE1

ICODE0

—

RXB0D77

RXB0D67

RXB0D57

RXB0D47

RXB0D37

RXB0D27

RXB0D17

RXB0D07

—

RXB0D76

RXB0D66

RXB0D56

RXB0D46

RXB0D36

RXB0D26

RXB0D16

RXB0D06

RXRTR

EID6

RXB0D75

RXB0D65

RXB0D55

RXB0D45

RXB0D35

RXB0D25

RXB0D15

RXB0D05

RB1

RXB0D74 RXB0D73 RXB0D72 RXB0D71 RXB0D70 xxxx xxxx

RXB0D64 RXB0D63 RXB0D62 RXB0D61 RXB0D60 xxxx xxxx

RXB0D54 RXB0D53 RXB0D52 RXB0D51 RXB0D50 xxxx xxxx

RXB0D44 RXB0D43 RXB0D42 RXB0D41 RXB0D40 xxxx xxxx

RXB0D34 RXB0D33 RXB0D32 RXB0D31 RXB0D30 xxxx xxxx

RXB0D24 RXB0D23 RXB0D22 RXB0D21 RXB0D20 xxxx xxxx

RXB0D14 RXB0D13 RXB0D12 RXB0D11 RXB0D10 xxxx xxxx

RXB0D04 RXB0D03 RXB0D02 RXB0D01 RXB0D00 xxxx xxxx

34, 211

RXB0D6

RXB0D5

RXB0D4

RXB0D3

RXB0D2

RXB0D1

RXB0D0

RXB0DLC

RXB0EIDL

RXB0EIDH

RXB0SIDL

RXB0SIDH

RXB0CON

RB0

EID4

EID12

SRR

SID7

—

DLC3

EID3

EID11

EXID

SID6

DLC2

EID2

EID10

—

DLC1

EID1

EID9

EID17

SID4

DLC0

EID0

EID8

EID16

SID3

-xxx xxxx

EID7

EID5

xxxx xxxx 34, 210

xxxx x-xx 34, 210

xxxx xxxx 34, 209

EID15

EID14

EID13

SID2

SID1

SID0

SID10

SID9

SID8

SID5

RXFUL

RXM1

RXM0

RXRTRRO RXB0DBEN JTOFF

FILHIT0 000- 0000 34, 208

Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition

Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ’0’s.

2: Bit21 of the TBLPTRU allows access to the device configuration bits.

3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other Oscillator

modes.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 51

PIC18FXX8

TABLE 4-2:

REGISTER FILE SUMMARY (CONTINUED)

Value on Details on

POR, BOR Page:

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CANSTATRO1 OPMODE2 OPMODE1 OPMODE0

—

ICODE2

ICODE1

ICODE0

—

xxx- xxx- 33, 200

RXB1D7

RXB1D77

RXB1D67

RXB1D57

RXB1D47

RXB1D37

RXB1D27

RXB1D17

RXB1D07

—

RXB1D76

RXB1D66

RXB1D56

RXB1D46

RXB1D36

RXB1D26

RXB1D16

RXB1D06

RXRTR

EID6

RXB1D75

RXB1D65

RXB1D55

RXB1D45

RXB1D35

RXB1D25

RXB1D15

RXB1D05

RB1

RXB1D74 RXB1D73 RXB1D72 RXB1D71 RXB1D70 xxxx xxxx

RXB1D64 RXB1D63 RXB1D62 RXB1D61 RXB1D60 xxxx xxxx

RXB1D54 RXB1D53 RXB1D52 RXB1D51 RXB1D50 xxxx xxxx

RXB1D44 RXB1D43 RXB1D42 RXB1D41 RXB1D40 xxxx xxxx

RXB1D34 RXB1D33 RXB1D32 RXB1D31 RXB1D30 xxxx xxxx

RXB1D24 RXB1D23 RXB1D22 RXB1D21 RXB1D20 xxxx xxxx

RXB1D14 RXB1D13 RXB1D12 RXB1D11 RXB1D10 xxxx xxxx

RXB1D04 RXB1D03 RXB1D02 RXB1D01 RXB1D00 xxxx xxxx

34, 211

RXB1D6

RXB1D5

RXB1D4

RXB1D3

RXB1D2

RXB1D1

RXB1D0

RXB1DLC

RXB1EIDL

RXB1EIDH

RXB1SIDL

RXB1SIDH

RXB1CON

RB0

EID4

EID12

SRR

SID7

—

DLC3

EID3

EID11

EXID

SID6

DLC2

EID2

EID10

—

DLC1

EID1

DLC0

EID0

EID8

EID16

SID3

-xxx xxxx

EID7

EID5

xxxx xxxx 34, 210

xxxx x-xx 34, 210

xxxx xxxx 34, 209

EID15

EID14

EID13

EID9

SID2

SID1

SID0

EID17

SID4

SID10

SID9

SID8

SID5

RXFUL

RXM1

RXM0

RXRTRRO FILHIT2

ICODE2 ICODE1

FILHIT1

ICODE0

FILHIT0 000- 0000 34, 209

xxx- xxx- 33, 200

CANSTATRO2 OPMODE2 OPMODE1 OPMODE0

—

TXB0D7

TXB0D77

TXB0D67

TXB0D57

TXB0D47

TXB0D37

TXB0D27

TXB0D17

TXB0D07

—

TXB0D76

TXB0D66

TXB0D56

TXB0D46

TXB0D36

TXB0D26

TXB0D16

TXB0D06

TXRTR

EID6

TXB0D75

TXB0D65

TXB0D55

TXB0D45

TXB0D35

TXB0D25

TXB0D15

TXB0D05

—

TXB0D74 TXB0D73 TXB0D72 TXB0D71 TXB0D70 xxxx xxxx 34, 206

TXB0D64 TXB0D63 TXB0D62 TXB0D61 TXB0D60 xxxx xxxx 34, 206

TXB0D54 TXB0D53 TXB0D52 TXB0D51 TXB0D50 xxxx xxxx 34, 206

TXB0D44 TXB0D43 TXB0D42 TXB0D41 TXB0D40 xxxx xxxx 34, 206

TXB0D34 TXB0D33 TXB0D32 TXB0D31 TXB0D30 xxxx xxxx 34, 206

TXB0D24 TXB0D23 TXB0D22 TXB0D21 TXB0D20 xxxx xxxx 34, 206

TXB0D14 TXB0D13 TXB0D12 TXB0D11 TXB0D10 xxxx xxxx 34, 206

TXB0D04 TXB0D03 TXB0D02 TXB0D01 TXB0D00 xxxx xxxx 34, 206

TXB0D6

TXB0D5

TXB0D4

TXB0D3

TXB0D2

TXB0D1

TXB0D0

TXB0DLC

TXB0EIDL

TXB0EIDH

TXB0SIDL

TXB0SIDH

TXB0CON

—

EID4

EID12

—

DLC3

EID3

DLC2

EID2

EID10

—

DLC1

EID1

DLC0

EID0

EID8

EID16

SID3

-x-- xxxx 35, 207

xxxx xxxx 35, 206

xxxx xxxx 35, 205

xxx- x-xx 35, 205

xxxx xxxx 35, 205

EID7

EID5

EID15

EID14

EID13

EID11

EXIDE

SID6

EID9

SID2

SID1

SID0

EID17

SID4

SID10

SID9

SID8

SID7

TXERR

—

SID5

—

TXABT

TXLARB

TXREQ

ICODE2

TXPRI1

ICODE0

TXPRI0 -000 0-00 35, 204

xxx- xxx- 33, 200

CANSTATRO3 OPMODE2 OPMODE1 OPMODE0

ICODE1

—

TXB1D7

TXB1D77

TXB1D67

TXB1D57

TXB1D47

TXB1D37

TXB1D27

TXB1D17

TXB1D07

—

TXB1D76

TXB1D66

TXB1D56

TXB1D46

TXB1D36

TXB1D26

TXB1D16

TXB1D06

TXRTR

EID6

TXB1D75

TXB1D65

TXB1D55

TXB1D45

TXB1D35

TXB1D25

TXB1D15

TXB1D05

—

TXB1D74 TXB1D73 TXB1D72 TXB1D71 TXB1D70 xxxx xxxx 35, 206

TXB1D64 TXB1D63 TXB1D62 TXB1D61 TXB1D60 xxxx xxxx 35, 206

TXB1D54 TXB1D53 TXB1D52 TXB1D51 TXB1D50 xxxx xxxx 35, 206

TXB1D44 TXB1D43 TXB1D42 TXB1D41 TXB1D40 xxxx xxxx 35, 206

TXB1D34 TXB1D33 TXB1D32 TXB1D31 TXB1D30 xxxx xxxx 35, 206

TXB1D24 TXB1D23 TXB1D22 TXB1D21 TXB1D20 xxxx xxxx 35, 206

TXB1D14 TXB1D13 TXB1D12 TXB1D11 TXB1D10 xxxx xxxx 35, 206

TXB1D04 TXB1D03 TXB1D02 TXB1D01 TXB1D00 xxxx xxxx 35, 206

TXB1D6

TXB1D5

TXB1D4

TXB1D3

TXB1D2

TXB1D1

TXB1D0

TXB1DLC

TXB1EIDL

TXB1EIDH

TXB1SIDL

TXB1SIDH

TXB1CON

—

EID4

EID12

—

DLC3

EID3

DLC2

EID2

EID10

—

DLC1

EID1

DLC0

EID0

EID8

EID16

SID3

-x-- xxxx 35, 207

xxxx xxxx 35, 206

xxxx xxxx 35, 205

xxx- x-xx 35, 205

xxxx xxxx 35, 205

EID7

EID5

EID15

EID14

EID13

EID11

EXIDE

SID6

EID9

SID2

SID1

SID0

EID17

SID4

SID10

SID9

SID8

SID7

TXERR

SID5

—

TXABT

TXLARB

TXREQ

TXPRI1

TXPRI0 0000 0000 35, 204

Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition

Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ’0’s.

2: Bit21 of the TBLPTRU allows access to the device configuration bits.

3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other Oscillator

modes.

DS41159B-page 52

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 4-2:

REGISTER FILE SUMMARY (CONTINUED)

Value on Details on

Bit 0

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

POR, BOR

Page:

CANSTATRO4 OPMODE2 OPMODE1 OPMODE0

—

ICODE2

ICODE1

ICODE0

—

xxx- xxx- 33, 200

TXB2D7

TXB2D77

TXB2D67

TXB2D57

TXB2D47

TXB2D37

TXB2D27

TXB2D17

TXB2D07

—

TXB2D76

TXB2D66

TXB2D56

TXB2D46

TXB2D36

TXB2D26

TXB2D16

TXB2D06

TXRTR

EID6

TXB2D75

TXB2D65

TXB2D55

TXB2D45

TXB2D35

TXB2D25

TXB2D15

TXB2D05

—

TXB2D74 TXB2D73 TXB2D72 TXB2D71 TXB2D70 xxxx xxxx 35, 206

TXB2D64 TXB2D63 TXB2D62 TXB2D61 TXB2D60 xxxx xxxx 35, 206

TXB2D54 TXB2D53 TXB2D52 TXB2D51 TXB2D50 xxxx xxxx 35, 206

TXB2D44 TXB2D43 TXB2D42 TXB2D41 TXB2D40 xxxx xxxx 35, 206

TXB2D34 TXB2D33 TXB2D32 TXB2D31 TXB2D30 xxxx xxxx 35, 206

TXB2D24 TXB2D23 TXB2D22 TXB2D21 TXB2D20 xxxx xxxx 35, 206

TXB2D14 TXB2D13 TXB2D12 TXB2D11 TXB2D10 xxxx xxxx 35, 206

TXB2D04 TXB2D03 TXB2D02 TXB2D01 TXB2D00 xxxx xxxx 35, 206

TXB2D6

TXB2D5

TXB2D4

TXB2D3

TXB2D2

TXB2D1

TXB2D0

TXB2DLC

TXB2EIDL

TXB2EIDH

TXB2SIDL

TXB2SIDH

TXB2CON

—

EID4

EID12

—

DLC3

EID3

DLC2

EID2

EID10

—

DLC1

EID1

DLC0

EID0

EID8

EID16

SID3

-x-- xxxx 35, 207

xxxx xxxx 35, 206

xxxx xxxx 35, 205

xxx- x-xx 35, 205

xxxx xxxx 35, 205

EID7

EID5

EID15

EID14

EID13

EID11

EXIDE

SID6

EID9

SID2

SID1

SID0

EID17

SID4

SID10

SID9

SID8

SID7

TXERR

SID5

—

TXABT

TXLARB

TXREQ

TXPRI1

TXPRI0 -000 0-00 35, 204

RXM1EIDL

RXM1EIDH

RXM1SIDL

RXM1SIDH

RXM0EIDL

RXM0EIDH

RXM0SIDL

RXM0SIDH

RXF5EIDL

RXF5EIDH

RXF5SIDL

RXF5SIDH

RXF4EIDL

RXF4EIDH

RXF4SIDL

RXF4SIDH

EID7

EID15

SID2

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID4

EID12

—

EID3

EID11

—

EID2

EID10

—

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

xxxx xxxx 36, 214

xxx- --xx 36, 214

xxxx xxxx 36, 213

xxxx xxxx 36, 214

xxx- --xx 36, 214

xxxx xxxx 36, 213

xxx- x-xx 36, 212

xxxx xxxx 36, 212

xxxx xxxx 36, 213

xxx- x-xx 36, 212

xxxx xxxx 36, 212

SID10

EID7

SID7

EID4

EID12

—

SID6

EID3

EID11

—

SID5

EID2

EID10

—

EID15

SID2

SID10

EID7

SID7

EID4

EID12

—

SID6

EID3

EID11

EXIDEN

SID6

EID3

EID11

EXIDEN

SID6

SID5

EID2

EID10

—

EID15

SID2

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

EID15

SID2

SID10

SID7

SID5

RXF3EIDL

RXF3EIDH

RXF3SIDL

RXF3SIDH

RXF2EIDL

RXF2EIDH

RXF2SIDL

RXF2SIDH

RXF1EIDL

RXF1EIDH

RXF1SIDL

RXF1SIDH

RXF0EIDL

RXF0EIDH

RXF0SIDL

RXF0SIDH

EID7

EID15

SID2

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID4

EID12

—

EID3

EID11

EXIDEN

SID6

EID2

EID10

—

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

xxxx xxxx 36, 213

xxx- x-xx 36, 212

xxxx xxxx 36, 212

xxxx xxxx 36, 213

xxx- x-xx 36, 212

xxxx xxxx 36, 212

xxxx xxxx 36, 213

xxx- x-xx 36, 212

xxxx xxxx 36, 212

xxxx xxxx 36, 213

xxx- x-xx 36, 212

xxxx xxxx 36, 212

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

EID3

EID15

SID2

EID11

EXIDEN

SID6

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

EID3

EID15

SID2

EID11

EXIDEN

SID6

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

EID3

EID15

SID2

EID11

EXIDEN

SID6

SID10

SID7

SID5

Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition

Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ’0’s.

2: Bit21 of the TBLPTRU allows access to the device configuration bits.

3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other Oscillator

modes.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 53

PIC18FXX8

4.10 Access Bank

4.11 Bank Select Register (BSR)

The Access Bank is an architectural enhancement that

is very useful for C compiler code optimization. The

techniques used by the C compiler are also useful for

programs written in assembly.

The need for a large general purpose memory space

dictates a RAM banking scheme. The data memory is

partitioned into sixteen banks. When using direct

addressing, the BSR should be configured for the

desired bank.

This data memory region can be used for:

BSR<3:0> holds the upper 4 bits of the 12-bit RAM

address. The BSR<7:4> bits will always read ’0’s, and

writes will have no effect.

• Intermediate computational values

• Local variables of subroutines

• Faster context saving/switching of variables

• Common variables

A

MOVLB instruction has been provided in the

instruction set to assist in selecting banks.

• Faster evaluation/control of SFRs (no banking)

If the currently selected bank is not implemented, any

read will return all '0's and all writes are ignored. The

STATUS register bits will be set/cleared as appropriate

for the instruction performed.

The Access Bank is comprised of the upper 160 bytes

in Bank 15 (SFRs) and the lower 96 bytes in Bank 0.

These two sections will be referred to as Access Bank

High and Access Bank Low, respectively. Figure 4-6

indicates the Access Bank areas.

Each Bank extends up to FFh (256 bytes). All data

memory is implemented as static RAM.

A bit in the instruction word specifies if the operation is

to occur in the bank specified by the BSR register, or in

the Access Bank.

A MOVFFinstruction ignores the BSR, since the 12-bit

addresses are embedded into the instruction word.

Section 4.12 provides a description of indirect address-

ing, which allows linear addressing of the entire RAM

space.

When forced in the Access Bank (a = ’0’), the last

address in Access Bank Low is followed by the first

address in Access Bank High. Access Bank High maps

most of the Special Function Registers so that these

registers can be accessed without any software

overhead.

FIGURE 4-7:

DIRECT ADDRESSING

Direct Addressing

(3)

From Opcode

BSR<3:0>

7

0

(2)

(3)

Bank Select

Location Select

00h

000h

01h

100h

0Eh

E00h

0Fh

F00h

Data

Memory⁽¹⁾

0FFh

1FFh

EFFh

FFFh

Bank 0

Bank 1

Bank 14 Bank 15

Note 1: For register file map detail, see Table 4-1.

2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the

registers of the Access Bank.

3: The MOVFFinstruction embeds the entire 12-bit address in the instruction.

DS41159B-page 54

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

If INDF0, INDF1 or INDF2 are read indirectly via an

FSR, all ’0’s are read (zero bit is set). Similarly, if

INDF0, INDF1 or INDF2 are written to indirectly, the

operation will be equivalent to a NOPinstruction and the

STATUS bits are not affected.

4.12 Indirect Addressing, INDF and

FSR Registers

Indirect addressing is a mode of addressing data mem-

ory, where the data memory address in the instruction

is not fixed. A SFR register is used as a pointer to the

data memory location that is to be read or written. Since

this pointer is in RAM, the contents can be modified by

the program. This can be useful for data tables in the

data memory and for software stacks. Figure 4-8

shows the operation of indirect addressing. This shows

the moving of the value to the data memory address

specified by the value of the FSR register.

4.12.1

INDIRECT ADDRESSING

OPERATION

Each FSR register has an INDF register associated with

it, plus four additional register addresses. Performing an

operation on one of these five registers determines how

the FSR will be modified during indirect addressing.

• When data access is done to one of the five

INDFn locations, the address selected will

configure the FSRn register to:

Indirect addressing is possible by using one of the INDF

registers. Any instruction using the INDF register actually

accesses the register indicated by the File Select Regis-

ter, FSR. Reading the INDF register itself, indirectly (FSR

= ’0’), will read 00h. Writing to the INDF register indirectly,

results in a no operation. The FSR register contains a

12-bit address, which is shown in Figure 4-8.

- Do nothing to FSRn after an indirect access

(no change) - INDFn

- Auto-decrement FSRn after an indirect

access (post-decrement) - POSTDECn

- Auto-increment FSRn after an indirect

access (post-increment) - POSTINCn

The INDFn (0 ≤ n ≤ 2) register is not a physical register.

Addressing INDFn actually addresses the register

whose address is contained in the FSRn register

(FSRn is a pointer). This is indirect addressing.

- Auto-increment FSRn before an indirect

access (pre-increment) - PREINCn

- Use the value in the WREG register as an off-

set to FSRn. Do not modify the value of the

WREG or the FSRn register after an indirect

access (no change) - PLUSWn

Example 4-5 shows a simple use of indirect addressing

to clear the RAM in Bank 1 (locations 100h-1FFh) in a

minimum number of instructions.

EXAMPLE 4-5:

HOW TO CLEAR RAM

(BANK 1) USING

INDIRECT ADDRESSING

FSR0, 100h ;

When using the auto-increment or auto-decrement fea-

tures, the effect on the FSR is not reflected in the

STATUS register. For example, if the indirect address

causes the FSR to equal '0', the Z bit will not be set.

LFSR

POSTINC0

; Clear INDF

; register

Incrementing or decrementing an FSR affects all 12

bits. That is, when FSRnL overflows from an increment,

FSRnH will be incremented automatically.

; & inc pointer

; All done

; w/ Bank1?

; NO, clear next

;

BTFSS

BRA

CONTINUE

:

FSR0H, 1

software stack pointer, in addition to its uses for table

operations in data memory.

; YES, continue

Each FSR has an address associated with it that per-

forms an indexed indirect access. When a data access to

this INDFn location (PLUSWn) occurs, the FSRn is con-

figured to add the 2’s complement value in the WREG

register and the value in FSR to form the address before

an indirect access. The FSR value is not changed.

There are three indirect addressing registers. To

address the entire data memory space (4096 bytes),

these registers are 12-bits wide. To store the 12 bits of

addressing information, two 8-bit registers are

required. These indirect addressing registers are:

1. FSR0: composed of FSR0H:FSR0L

2. FSR1: composed of FSR1H:FSR1L

3. FSR2: composed of FSR2H:FSR2L

If an FSR register contains a value that indicates one of

the INDFn, an indirect read will read 00h (zero bit is

set), while an indirect write will be equivalent to a NOP

(STATUS bits are not affected).

In addition, there are registers INDF0, INDF1 and

INDF2, which are not physically implemented. Reading

or writing to these registers activates indirect address-

ing, with the value in the corresponding FSR register

being the address of the data.

If an indirect addressing operation is done where the

target address is an FSRnH or FSRnL register, the

write operation will dominate over the pre- or post-

increment/decrement functions.

If an instruction writes a value to INDF0, the value will

be written to the address indicated by FSR0H:FSR0L.

A read from INDF1 reads the data from the address

indicated by FSR1H:FSR1L. INDFn can be used in

code anywhere an operand can be used.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 55

PIC18FXX8

FIGURE 4-8:

INDIRECT ADDRESSING

Indirect Addressing

FSR Register

11

8

7

0

FSRnH

FSRnL

Location Select

0000h

Data

Memory⁽¹⁾

0FFFh

Note 1: For register file map detail, see Table 4-1.

DS41159B-page 56

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

4.13 STATUS Register

The STATUS register, shown in Register 4-2, contains

the arithmetic status of the ALU. The STATUS register

can be the destination for any instruction, as with any

other register. If the STATUS register is the destination

for an instruction that affects the Z, DC, C, OV, or N bits,

then the write to these five bits is disabled. These bits

are set or cleared according to the device logic. There-

fore, the result of an instruction with the STATUS

register as destination may be different than intended.

It is recommended, therefore, that only BCF, BSF,

SWAPF, MOVFF and MOVWF instructions are used to

alter the STATUS register, because these instructions

do not affect the Z, C, DC, OV, or N bits from the

STATUS register. For other instructions which do not

affect the status bits, see Table 25-2.

Note: The C and DC bits operate as a borrow and

digit borrow bit respectively, in subtraction.

REGISTER 4-2:

STATUS REGISTER

U-0

R/W-x

N

R/W-x

OV

R/W-x

Z

R/W-x

DC

R/W-x

C

—

bit 7

bit 0

bit 7-5 Unimplemented: Read as '0'

bit 4

bit 3

N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result of the ALU

operation was negative (ALU MSb = 1).

1= Result was negative

0= Result was positive

OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit

magnitude, which causes the sign bit (bit 7) to change state.

1= Overflow occurred for signed arithmetic (in this arithmetic operation)

0= No overflow occurred

bit 2

bit 1

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit

For ADDWF, ADDLW, SUBLW,and SUBWFinstructions

1= A carry-out from the 4th low order bit of the result occurred

0= No carry-out from the 4th low order bit of the result

Note:

For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s com-

plement of the second operand. For rotate (RRCF, RRNCF, RLCF, and RLNCF)

instructions, this bit is loaded with either the bit 4 or bit 3 of the source register.

bit 0

C: Carry/borrow bit

For ADDWF, ADDLW, SUBLW,and SUBWF instructions

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note:

For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s com-

plement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the high or low order bit of the source register.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 57

PIC18FXX8

4.14 RCON Register

Note 1: If the BOREN configuration bit is set,

BOR is ’1’ on Power-on Reset. If the

BOREN configuration bit is clear, BOR is

unknown on Power-on Reset.

The Reset Control (RCON) register contains flag bits

that allow differentiation between the sources of a

device RESET. These flags include the TO, PD, POR,

BORandRIbits. Thisregisterisreadableandwritable.

The BOR status bit is a “don't care” and is

not necessarily predictable if the brown-

out circuit is disabled (the BOREN config-

uration bit is clear). BOR must then be set

by the user and checked on subsequent

RESETS to see if it is clear, indicating a

brown-out has occurred.

2: It is recommended that the POR bit be set

after

a Power-on Reset has been

detected, so that subsequent Power-on

Resets may be detected.

REGISTER 4-3:

RCON REGISTER

R/W-0

IPEN

U-0

R/W-1

RI

R-1

TO

R-1

PD

R/W-0

POR

R/W-0

BOR

—

bit 7

bit 0

bit 7

IPEN: Interrupt Priority Enable bit

1= Enable priority levels on interrupts

0= Disable priority levels on interrupts (16CXXX Compatibility mode)

bit 6-5 Unimplemented: Read as '0'

bit 4

RI: RESETInstruction Flag bit

1= The RESETinstruction was not executed

0= The RESETinstruction was executed causing a device RESET

(must be set in software after a Brown-out Reset occurs)

bit 3

bit 2

bit 1

bit 0

TO: Watchdog Time-out Flag bit

1= After power-up, CLRWDTinstruction, or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down Detection Flag bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

POR: Power-on Reset Status bit

1= A Power-on Reset has not occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

BOR: Brown-out Reset Status bit

1= A Brown-out Reset has not occurred

0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

DS41159B-page 58

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

5.1

EEADR Register

5.0

DATA EEPROM MEMORY

The address register can address up to a maximum of

256 bytes of data EEPROM.

The Data EEPROM is readable and writable during

normal operation over the entire VDD range. The data

memory is not directly mapped in the register file

space. Instead, it is indirectly addressed through the

Special Function Registers (SFR).

5.2

EECON1 and EECON2 Registers

EECON1 is the control register for EEPROM memory

accesses.

There are four SFRs used to read and write the

program and data EEPROM memory. These registers

are:

EECON2 is not a physical register. Reading EECON2

will read all '0's. The EECON2 register is used

exclusively in the EEPROM write sequence.

• EECON1

• EECON2

• EEDATA

• EEADR

Control bits RD and WR initiate read and write opera-

tions, respectively. These bits cannot be cleared, only

set, in software. They are cleared in hardware at the

completion of the read or write operation. The inability

to clear the WR bit in software prevents the accidental

or premature termination of a write operation.

The EEPROM data memory allows byte read and write.

When interfacing to the data memory block, EEDATA

holds the 8-bit data for read/write and EEADR holds the

address of the EEPROM location being accessed. The

PIC18FXX8 devices have 256 bytes of data EEPROM,

with an address range from 00h to FFh.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset, during normal oper-

ation. In these situations, following RESET, the user

can check the WRERR bit and rewrite the location. The

data and address registers (EEDATA and EEADR)

remain unchanged.

The EEPROM data memory is rated for high erase/

write cycles. A byte write automatically erases the loca-

tion and writes the new data (erase-before-write). The

write time is controlled by an on-chip timer. The write

time will vary with voltage and temperature, as well as

from chip-to-chip. Please refer to the specifications for

exact limits.

Note: Interrupt flag bit EEIF in the PIR2 register

is set when write is complete. It must be

cleared in software.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 59

PIC18FXX8

REGISTER 5-1:

EECON1 REGISTER

R/W-x

CFGS

U-0

R/W-0

FREE

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

EEPGD

—

WRERR

bit 7

bit 0

bit 7

bit 6

EEPGD: FLASH Program or Data EEPROM Memory Select bit

1= Access program FLASH memory

0= Access data EEPROM memory

CFGS: FLASH Program/Data EE or Configuration Select bit

1= Access configuration registers

0= Access program FLASH or data EEPROM memory

bit 5

bit 4

Unimplemented: Read as '0'

FREE: FLASH Row Erase Enable bit

1= Erase the program memory row addressed by TBLPTR on the next WR command

(reset by hardware)

0= Perform write only

bit 3

WRERR: Write Error Flag bit

1= A write operation is prematurely terminated

(any MCLR or any WDT Reset during self-timed programming in normal operation)

0= The write operation completed

Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing

of the error condition.

bit 2

bit 1

WREN: Write Enable bit

1= Allows write cycles

0= Inhibits write to the EEPROM or FLASH memory

WR: Write Control bit

1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle

(The operation is self-timed and the bit is cleared by hardware once write is complete. The

WR bit can only be set (not cleared) in software.)

0= Write cycle is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)

in software. RD bit cannot be set when EEPGD = 1.)

0= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

DS41159B-page 60

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

5.3

Reading the Data EEPROM

Memory

5.4

Writing to the Data EEPROM

Memory

To read a data memory location, the user must write the

address to the EEADR register, clear the EEPGD and

CFGS control bits (EECON1<7:6>) and then set con-

trol bit RD (EECON1<0>). The data is available in the

very next instruction cycle of the EEDATA register;

therefore, it can be read by the next instruction.

EEDATA will hold this value until another read opera-

tion, or until it is written to by the user (during a write

operation).

To write an EEPROM data location, the address must

first be written to the EEADR register and the data writ-

ten to the EEDATA register. Then, the sequence in

Example 5-2 must be followed to initiate the write cycle.

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write 0AAh to

EECON2, then set WR bit) for each byte. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in EECON1 must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code exe-

cution (i.e., runaway programs). The WREN bit should

be kept clear at all times, except when updating the

EEPROM. The WREN bit is not cleared by hardware.

EXAMPLE 5-1:

MOVLW DATA_EE_ADDR

MOVWF EEADR

DATA EEPROM READ

;

;Data Memory Address

;to read

BCF

BCS

BSF

MOVF

EECON1, EEPGD ;Point to DATA memory

After a write sequence has been initiated, clearing the

WREN bit will not affect the current write cycle. The WR

bit will be inhibited from being set unless the WREN bit

is set. The WREN bit must be set on a previous instruc-

tion. Both WR and WREN cannot be set with the same

instruction.

EECON1, CFGS

EECON1, RD

EEDATA, W

;

;EEPROM Read

;W = EEDATA

At the completion of the write cycle, the WR bit is

cleared in hardware and the EEPROM Write Complete

Interrupt Flag bit (EEIF) is set. The user may either

enable this interrupt, or roll this bit. EEIF must be

cleared by software.

EXAMPLE 5-2:

DATA EEPROM WRITE

MOVLW

DATA_EE_ADDR

EEADR

DATA_EE_DATA

EEDATA

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

;

MOVWF

MOVLW

MOVWF

BCF

BCS

BSF

; Data Memory Address to write

;

; Data Memory Value to write

; Point to DATA memory

;

; Enable writes

BCF

INTCON, GIE

55h

EECON2

0AAh

EECON2

; Disable Interrupts

;

; Write 55h

;

; Write 0AAh

; Set WR bit to begin write

; Enable Interrupts

MOVLW

MOVWF

MOVLW

MOVWF

BSF

Required

Sequence

EECON1, WR

INTCON, GIE

BSF

; User code execution

; Disable writes

BCF

EECON1, WREN

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 61

PIC18FXX8

5.5

Write Verify

5.7

Operation During Code Protect

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

Data EEPROM memory has its own code protect

mechanism. External read and write operations are

disabled if either of these mechanisms are enabled.

The microcontroller itself can both read and write to the

internal data EEPROM, regardless of the state of the

code protect configuration bit. Refer to Section 24.0,

Special Features of the CPU for additional information.

Generally, a write failure will be a bit which was written

as a ’1’, but reads back as a ’0’ (due to leakage off the

cell).

5.8

Using the Data EEPROM

5.6

Protection Against Spurious Write

The data EEPROM is a high-endurance, byte address-

able array that has been optimized for the storage of

frequently changing information (e.g., program vari-

ables or other data that are updated often). Frequently

changing values will typically be updated more often

than specification D124 or D124A. If this is not the

case, an array refresh must be performed. For this rea-

son, variables that change infrequently (such as con-

stants, IDs, calibration, etc.) should be stored in FLASH

program memory. A simple data EEPROM refresh

routine is shown in Example 5-3.

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared.

Also, the Power-up Timer (72 ms duration) prevents

EEPROM write.

The write initiate sequence and the WREN bit together

reduce the probability of an accidental write during

brown-out, power glitch, or software malfunction.

Note: If Data EEPROM is only used to store con-

stants and/or data that changes rarely, an

array refresh is likely not required. See

specification D124 or D124A.

EXAMPLE 5-3:

DATA EEPROM REFRESH ROUTINE

clrf

bcf

bsf

EEADR

; Start at address 0

EECON1,CFGS

EECON1,EEPGD

INTCON,GIE

EECON1,WREN

; Set for memory

; Set for Data EEPROM

; Disable interrupts

; Enable writes

; Loop to refresh array

; Read current address

;

; Write 55h

;

; Write AAh

; Set WR bit to begin write

; Wait for write to complete

Loop

bsf

EECON1,RD

55h

EECON2

AAh

EECON2

EECON1,WR

$-2

movlw

movwf

movlw

movwf

bsf

btfsc

bra

incfsz

bra

EEADR,F

Loop

; Increment address

; Not zero, do it again

bcf

bsf

EECON1,WREN

INTCON,GIE

; Disable writes

; Enable interrupts

DS41159B-page 62

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 5-1:

REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Value on

Value on:

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

RESETS

INTCON

EEADR

GIE/GIEH PEIE/GIEL TMR0IE

EEPROM Address Register

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

xxxx xxxx uuuu uuuu

EEDATA EEPROM Data Register

EECON2 EEPROM Control Register2 (not a physical register)

—

EECON1

IPR2

EEPGD

CFGS

CMIP

CMIF

CMIE

—

FREE

EEIP

EEIF

EEIE

WRERR

BCLIP

BCLIF

BCLIE

WREN

LVDIP

LVDIF

LVDIE

WR

RD

xx-0 x000 uu-0 u000

—

TMR3IP ECCP1IP -1-1 1111 -1-1 1111

TMR3IF ECCP1IF -0-0 0000 -0-0 0000

TMR3IE ECCP1IE -0-0 0000 -0-0 0000

PIR2

PIE2

Legend: x= unknown, u= unchanged, r = reserved, -= unimplemented, read as '0'.

Shaded cells are not used during FLASH/EEPROM access.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 63

PIC18FXX8

NOTES:

DS41159B-page 64

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

6.1

Table Reads and Table Writes

6.0

FLASH PROGRAM MEMORY

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data

RAM:

The FLASH Program Memory is readable, writable,

and erasable during normal operation over the entire

VDD range.

A read from program memory is executed on one byte

at a time. A write to program memory is executed on

blocks of 8 bytes at a time. Program memory is erased

in blocks of 64 bytes at a time. A bulk erase operation

may not be issued from user code.

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16-bits wide, while the

data RAM space is 8-bits wide. Table Reads and Table

Writes move data between these two memory spaces

through an 8-bit register (TABLAT).

Writing or erasing program memory will cease instruc-

tion fetches until the operation is complete. The pro-

gram memory cannot be accessed during the write or

erase, therefore, code cannot execute. An internal pro-

gramming timer terminates program memory writes

and erases.

Table Read operations retrieve data from program

memory and places it into the data RAM space.

Figure 6-1 shows the operation of a Table Read with

program memory and data RAM.

A value written to program memory does not need to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP.

Table Write operations store data from the data mem-

ory space into holding registers in program memory.

The procedure to write the contents of the holding reg-

isters into program memory is detailed in Section 6.5,

Writing to FLASH Program Memory. Figure 6-2 shows

the operation of a Table Write with program memory

and data RAM.

Table operations work with byte entities. A table block

containing data, rather than program instructions, is not

required to be word aligned. Therefore, a table block

can start and end at any byte address. If a Table Write

is being used to write executable code into program

memory, program instructions will need to be word

aligned.

FIGURE 6-1:

TABLE READ OPERATION

Instruction: TBLRD*

Program Memory

(1)

Table Pointer

Table Latch (8-bit)

TABLAT

TBLPTRU TBLPTRH TBLPTRL

Program Memory

(TBLPTR)

Note 1: Table Pointer points to a byte in program memory.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 65

PIC18FXX8

FIGURE 6-2:

TABLE WRITE OPERATION

Instruction: TBLWT*

Program Memory

Holding Registers

(1)

Table Pointer

Table Latch (8-bit)

TABLAT

TBLPTRU TBLPTRH TBLPTRL

Program Memory

(TBLPTR)

Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>.

The process for physically writing data to the Program Memory Array is discussed in Section 6.5.

The FREE bit, when set, will allow a program memory

6.2

Control Registers

erase operation. When the FREE bit is set, the erase

operation is initiated on the next WR command. When

FREE is clear, only writes are enabled.

Several control registers are used in conjunction with

the TBLRDand TBLWTinstructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset or a WDT Time-out Reset during normal opera-

tion. In these situations, the user can check the

WRERR bit and rewrite the location. It is necessary to

reload the data and address registers (EEDATA and

EEADR), due to RESET values of zero.

6.2.1

EECON1 AND EECON2 REGISTERS

EECON1 is the control register for memory accesses.

EECON2 is not a physical register. Reading EECON2

will read all '0's. The EECON2 register is used

exclusively in the memory write and erase sequences.

Control bits RD and WR initiate read and write opera-

tions, respectively. These bits cannot be cleared, only

set, in software. They are cleared in hardware at the

completion of the read or write operation. The inability

to clear the WR bit in software prevents the accidental

or premature termination of a write operation. The RD

bit cannot be set when accessing program memory

(EEPGD = 1).

Control bit EEPGD determines if the access will be a

program or data EEPROM memory access. When

clear, any subsequent operations will operate on the

data EEPROM memory. When set, any subsequent

operations will operate on the program memory.

Control bit CFGS determines if the access will be to the

configuration/calibration registers or to program

memory/data EEPROM memory. When set, subse-

quent operations will operate on configuration regis-

ters, regardless of EEPGD (see Section 24.0, Special

Features of the CPU). When clear, memory selection

access is determined by EEPGD.

Note: If interrupts are enabled before the WR

command, interrupt flag bit EEIF in the

PIR2 register, is set when the write is com-

plete. It must be cleared in software. This

interrupt is not required to determine the

end of a FLASH program memory write

cycle.

DS41159B-page 66

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 6-1:

EECON1 REGISTER

R/W-x

CFGS

U-0

R/W-0

FREE

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

EEPGD

—

WRERR

bit 7

bit 0

bit 7

bit 6

EEPGD: FLASH Program or Data EEPROM Memory Select bit

1= Access program FLASH memory

0= Access data EEPROM memory

CFGS: FLASH Program/Data EE or Configuration Select bit

1= Access configuration registers

0= Access program FLASH or data EEPROM memory

bit 5

bit 4

Unimplemented: Read as '0'

FREE: FLASH Row Erase Enable bit

1= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0= Perform write only

bit 3

WRERR: Write Error Flag bit

1= A write operation is prematurely terminated

(any MCLR or any WDT Reset during self-timed programming in normal operation)

0= The write operation completed

Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows

tracing of the error condition.

bit 2

bit 1

WREN: Write Enable bit

1= Allows write cycles

0= Inhibits write to the EEPROM or FLASH memory

WR: Write Control bit

1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self timed and the bit is cleared by hardware once write is complete. The

WR bit can only be set (not cleared) in software.)

0= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)

in software. RD bit cannot be set when EEPGD = 1.)

0= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 67

PIC18FXX8

6.2.2

TABLAT - TABLE LATCH REGISTER

6.2.4

TABLE POINTER BOUNDARIES

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR space. The Table Latch is used to hold

8-bit data during data transfers between program

memory and data RAM.

TBLPTR is used in reads, writes, and erases of the

FLASH program memory.

When a TBLRD is executed, all 22 bits of the Table

Pointer determine which byte is read from program

memory into TABLAT.

6.2.3

TBLPTR - TABLE POINTER

REGISTER

When a TBLWTis executed, the three LSbs of the Table

Pointer (TBLPTR<2:0>) determine which of the eight

program memory holding registers is written to. When

the timed write to program memory (long write) begins,

the 19 MSbs of the Table Pointer, TBLPTR

(TBLPTR<21:3>), will determine which program mem-

ory block of 8 bytes is written to. For more detail, see

Section 6.5,Writing to FLASH Program Memory.

The Table Pointer (TBLPTR) addresses a byte within

the program memory. The TBLPTR is comprised of

three SFR registers: Table Pointer Upper Byte, Table

Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-

ters join to form a 22-bit wide pointer. The low order 21

bits allow the device to address up to 2 Mbytes of pro-

gram memory space. The 22nd bit allows access to the

Device ID, the User ID and the Configuration bits.

When an erase of program memory is executed, the 16

MSbs of the Table Pointer (TBLPTR<21:6>) point to the

64-byte block that will be erased. The Least Significant

bits (TBLPTR<5:0>) are ignored.

The table pointer, TBLPTR, is used by the TBLRDand

TBLWTinstructions. These instructions can update the

TBLPTR in one of four ways, based on the table oper-

ation. These operations are shown in Table 6-1. These

operations on the TBLPTR only affect the low order 21

bits.

Figure 6-3 describes the relevant boundaries of

TBLPTR based on FLASH program memory

operations.

TABLE 6-1:

Example

TABLE POINTER OPERATIONS WITH TBLRDAND TBLWTINSTRUCTIONS

Operation on Table Pointer

TBLRD*

TBLWT*

TBLPTR is not modified

TBLRD*+

TBLWT*+

TBLPTR is incremented after the read/write

TBLPTR is decremented after the read/write

TBLPTR is incremented before the read/write

TBLRD*-

TBLWT*-

TBLRD+*

TBLWT+*

FIGURE 6-3:

TABLE POINTER BOUNDARIES BASED ON OPERATION

21

16 15

TBLPTRH

8

7

TBLPTRL

0

TBLPTRU

ERASE - TBLPTR<21:6>

WRITE - TBLPTR<21:3>

READ - TBLPTR<21:0>

DS41159B-page 68

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TBLPTR points to a byte address in program space.

Executing TBLRD places the byte pointed to into

TABLAT. In addition, TBLPTR can be modified

automatically for the next Table Read operation.

6.3

Reading the FLASH Program

Memory

The TBLRDinstruction is used to retrieve data from pro-

gram memory and place into data RAM. Table Reads

from program memory are performed one byte at a

time.

The internal program memory is typically organized by

words. The Least Significant bit of the address selects

between the high and low bytes of the word. Figure 6-4

shows the interface between the internal program

memory and the TABLAT.

FIGURE 6-4:

READS FROM FLASH PROGRAM MEMORY

Program Memory

(Even Byte Address)

(Odd Byte Address)

TBLPTR = xxxxx1

TBLPTR = xxxxx0

Instruction Register

(IR)

TABLAT

Read Register

FETCH

TBLRD

EXAMPLE 6-1:

READING A FLASH PROGRAM MEMORY WORD

MOVLW CODE_ADDR_UPPER

MOVWF TBLPTRU

; Load TBLPTR with the base

; address of the word

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

READ_WORD

TBLRD*+

; read into TABLAT and increment

; get data

MOVF TABLAT, W

MOVWF WORD_LSB

TBLRD*+

MOVF TABLAT, W

MOVWF WORD_MSB

; read into TABLAT and increment

; get data

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 69

PIC18FXX8

6.4.1

FLASH PROGRAM MEMORY

ERASE SEQUENCE

6.4

Erasing FLASH Program memory

The minimum erase block is 32 words or 64 bytes. Only

through the use of an external programmer, or through

ICSP control, can larger blocks of program memory be

bulk erased. Word erase in the FLASH array is not

supported.

The sequence of events for erasing a block of internal

program memory location is:

1. Load table pointer with address of row being

erased.

When initiating an erase sequence from the micro-

controller itself, a block of 64 bytes of program memory

is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased.

TBLPTR<5:0> are ignored.

2. Set the EECON1 register for the erase operation:

• set the EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set the WREN bit to enable writes;

• set the FREE bit to enable the erase.

3. Disable interrupts.

The EECON1 register commands the erase operation.

The EEPGD bit must be set to point to the FLASH pro-

gram memory. The WREN bit must be set to enable

write operations. The FREE bit is set to select an erase

operation.

4. Write 55h to EECON2.

5. Write 0AAh to EECON2.

6. Set the WR bit. This will begin the row erase

cycle.

For protection, the write initiate sequence for EECON2

must be used.

7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).

A long write is necessary for erasing the internal

FLASH. Instruction execution is halted while in a long

write cycle. The long write will be terminated by the

internal programming timer.

8. Execute a NOP.

9. Re-enable interrupts.

Note: A NOPis needed after the WR command to

ensure proper code execution.

EXAMPLE 6-2:

ERASING A FLASH PROGRAM MEMORY ROW

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

upper (CODE_ADDR)

TBLPTRU

high (CODE_ADDR)

TBLPTRH

low (CODE_ADDR)

TBLPTRL

; load TBLPTR with the base

; address of the memory block

ERASE_ROW

BSF

BCF

BSF

EECON1,EEPGD

EECON1,CFGS

EECON1,WREN

EECON1,FREE

INTCON,GIE

55h

EECON2

0AAh

EECON2

EECON1,WR

; point to FLASH program memory

; access FLASH program memory

; enable write to memory

; enable Row Erase operation

; disable interrupts

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

; write 55H

Required

Sequence

; write 0AAH

; start erase (CPU stall)

; NOP needed for proper code execution

; re-enable interrupts

NOP

BSF

INTCON,GIE

DS41159B-page 70

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

5. Load Table Pointer with address of first byte

being written.

6.5

Writing to FLASH Program

Memory

6. Write the first 8 bytes into the holding registers

using the TBLWT instruction, auto-increment

may be used.

The minimum programming block is 4 words or 8 bytes.

Word or byte programming is not supported.

Table Writes are used internally to load the holding reg-

isters needed to program the FLASH memory. There

are 8 holding registers used by the Table Writes for

programming.

7. Set the EECON1 register for the write operation:

• set the EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set the WREN to enable byte writes.

8. Disable interrupts.

Since the Table Latch (TABLAT) is only a single byte,

the TBLWT instruction has to be executed 8 times for

each programming operation. All of the Table Write

operations will essentially be short writes, because only

the holding registers are written. At the end of updating

8 registers, the EECON1 register must be written to, to

start the programming operation with a long write.

9. Write 55h to EECON2.

10. Write AAh to EECON2.

11. Set the WR bit. This will begin the write cycle.

12. The CPU will stall for duration of the write (about

2 ms using internal timer).

The long write is necessary for programming the inter-

nal FLASH. Instruction execution is halted while in a

long write cycle. The long write will be terminated by

the internal programming timer.

13. Execute a NOP.

14. Re-enable interrupts.

15. Repeat steps 6-14 seven times, to write 64

bytes.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump rated to operate over the voltage range of

the device for byte or word operations.

16. Verify the memory (Table Read).

This procedure will require about 18 ms to update one

row of 64 bytes of memory. An example of the required

code is given in Example 6-3.

6.5.1

FLASH PROGRAM MEMORY WRITE

SEQUENCE

Note 1: A NOPis needed after the WR command

to ensure proper code execution.

2: Before setting the WR bit, the Table

Pointer address needs to be within the

range of addresses of the 8 bytes in the

holding registers.

The sequence of events for programming an internal

program memory location should be:

1. Read 64 bytes into RAM.

2. Update data values in RAM as necessary.

3. Load Table Pointer with address being erased.

4. Do the row erase procedure.

3: Holding registers are cleared on RESET

and at the completion of each write cycle.

FIGURE 6-5:

TABLE WRITES TO FLASH PROGRAM MEMORY

TABLAT

Write Register

8

TBLPTR = xxxxx0

TBLPTR = xxxxx2

TBLPTR = xxxxx7

TBLPTR = xxxxx1

Holding Register

Program Memory

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 71

PIC18FXX8

EXAMPLE 6-3:

WRITING TO FLASH PROGRAM MEMORY

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

D’64

COUNTER

high (BUFFER_ADDR)

FSR0H

low (BUFFER_ADDR)

FSR0L

upper (CODE_ADDR)

TBLPTRU

high (CODE_ADDR)

TBLPTRH

low (CODE_ADDR)

TBLPTRL

; number of bytes in erase block

; point to buffer

; Load TBLPTR with the base

; address of the memory block

READ_BLOCK

TBLRD*+

MOVF

MOVWF

; read into TABLAT, and inc

; get data

; store data

; done?

TABLAT, W

POSTINC0

DECFSZ COUNTER

BRA

READ_BLOCK

; repeat

MODIFY_WORD

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

DATA_ADDR_HIGH

FSR0H

DATA_ADDR_LOW

FSR0L

NEW_DATA_LOW

POSTINC0

NEW_DATA_HIGH

INDF0

; point to buffer

; update buffer word

ERASE_BLOCK

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

BCF

BSF

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

upper (CODE_ADDR)

TBLPTRU

high (CODE_ADDR)

TBLPTRH

low (CODE_ADDR)

TBLPTRL

EECON1,EEPGD

EECON1,CFGS

EECON1,WREN

EECON1,FREE

INTCON,GIE

55h

; load TBLPTR with the base

; address of the memory block

; point to FLASH program memory

; access FLASH program memory

; enable write to memory

; enable Row Erase operation

; disable interrupts

Required

Sequence

EECON2

AAh

EECON2

EECON1,WR

; write 55H

; write AAH

; start erase (CPU stall)

NOP

BSF

TBLRD*-

INTCON,GIE

; re-enable interrupts

; dummy read decrement

WRITE_BUFFER_BACK

MOVLW

8

; number of write buffer groups of 8 bytes

; point to buffer

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

COUNTER_HI

high (BUFFER_ADDR)

FSR0H

low (BUFFER_ADDR)

FSR0L

PROGRAM_LOOP

MOVLW

MOVWF

8

; number of bytes in holding register

COUNTER

WRITE_WORD_TO_HREGS

MOVFW

MOVWF

TBLWT+*

POSTINC0, W

TABLAT

; get low byte of buffer data

; present data to table latch

; write data, perform a short write

; to internal TBLWT holding register.

; loop until buffers are full

DECFSZ COUNTER

BRA WRITE_WORD_TO_HREGS

DS41159B-page 72

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

EXAMPLE 6-3:

WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

WRITE_WORD_TO_HREGS

MOVFW

MOVWF

POSTINC0, W

TABLAT

; get low byte of buffer data

; present data to table latch

TBLWT+*

; write data, perform a short write

; to internal TBLWT holding register.

; loop until buffers are full

DECFSZ COUNTER

BRA

WRITE_WORD_TO_HREGS

PROGRAM_MEMORY

BSF

BCF

BSF

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

EECON1,EEPGD

EECON1,CFGS

EECON1,WREN

INTCON,GIE

55h

EECON2

0AAh

EECON2

EECON1,WR

; point to FLASH program memory

; access FLASH program memory

; enable write to memory

; disable interrupts

; write 55H

Required

Sequence

; write 0AAH

; start program (CPU stall)

NOP

BSF

INTCON,GIE

; re-enable interrupts

; loop until done

DECFSZ COUNTER_HI

BRA

BCF

PROGRAM_LOOP

EECON1,WREN

; disable write to memory

6.5.2

WRITE VERIFY

6.5.4

PROTECTION AGAINST SPURIOUS

WRITES

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

To reduce the probability against spurious writes to

FLASH program memory, the write initiate sequence

must also be followed. See Section 24.0, Special

Features of the CPU for more detail.

6.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

6.6

FLASH Program Operation During

Code Protection

If a write is terminated by an unplanned event, such as

loss of power or an unexpected RESET, the memory

location just programmed should be verified and repro-

grammed if needed.The WRERR bit is set when a write

operation is interrupted by a MCLR Reset, or a WDT

Time-out Reset during normal operation. In these situ-

ations, users can check the WRERR bit and rewrite the

location.

See Section 24.0, Special Features of the CPU for

details on code protection of FLASH program memory.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 73

PIC18FXX8

TABLE 6-2:

REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Value on

all other

RESETS

Value on:

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TBLPTRU

—

bit21

Program Memory Table Pointer Upper Byte

(TBLPTR<20:16>)

--00 0000 --00 0000

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)

0000 0000 0000 0000

0000 000x 0000 000u

TABLAT

INTCON GIE/GIEH PEIE/GIEL TMR0IE

EECON2 EEPROM Control Register2 (not a physical register)

Program Memory Table Latch

INTE

RBIE

TMR0IF

INTF

WR

RBIF

RD

—

EECON1

IPR2

EEPGD

CFGS

—

FREE

EEIP

EEIF

EEIE

WRERR

BCLIP

BCLIF

BCLIE

WREN

LVDIP

LVDIF

LVDIE

xx-0 x000 uu-0 u000

—

TMR3IP CCP2IP ---1 1111 ---1 1111

TMR3IF CCP2IF ---0 0000 ---0 0000

TMR3IE CCP2IE ---0 0000 ---0 0000

PIR2

—

PIE2

—

Legend: x= unknown, u= unchanged, r = reserved, -= unimplemented read as '0'.

Shaded cells are not used during FLASH/EEPROM access.

DS41159B-page 74

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

7.2

Operation

7.0

7.1

8 X 8 HARDWARE MULTIPLIER

Introduction

Example 7-1 shows the sequence to do an 8 x 8

unsigned multiply. Only one instruction is required

when one argument of the multiply is already loaded in

the WREG register.

An 8 x 8 hardware multiplier is included in the ALU of

the PIC18FXX8 devices. By making the multiply a

hardware operation, it completes in a single instruction

cycle. This is an unsigned multiply that gives a 16-bit

result. The result is stored into the 16-bit product regis-

ter pair (PRODH:PRODL). The multiplier does not

affect any flags in the ALUSTA register.

Example 7-2 shows the sequence to do an 8 x 8 signed

multiply. To account for the sign bits of the arguments,

each argument’s Most Significant bit (MSb) is tested

and the appropriate subtractions are done.

Making the 8 x 8 multiplier execute in a single cycle

gives the following advantages:

EXAMPLE 7-1:

8 x 8 UNSIGNED

MULTIPLY ROUTINE

• Higher computational throughput

MOVF

MULWF

ARG1, W

ARG2

;

• Reduces code size requirements for multiply

; ARG1 * ARG2 ->

algorithms

;

PRODH:PRODL

The performance increase allows the device to be used

in applications previously reserved for Digital Signal

Processors.

Table 7-1 shows a performance comparison between

enhanced devices using the single cycle hardware mul-

tiply, and performing the same function without the

hardware multiply.

EXAMPLE 7-2:

8 x 8 SIGNED MULTIPLY

ROUTINE

MOVF

ARG1,

ARG2

W

MULWF

; ARG1 * ARG2 ->

; PRODH:PRODL

BTFSC

SUBWF

ARG2, SB

PRODH

; Test Sign Bit

; PRODH = PRODH

;

- ARG1

MOVF

ARG2,

W

BTFSC

SUBWF

ARG1, SB

PRODH

; Test Sign Bit

; PRODH = PRODH

;

- ARG2

TABLE 7-1:

Routine

PERFORMANCE COMPARISON

Program

Time

@ 40 MHz @ 10 MHz @ 4 MHz

Cycles

(Max)

Multiply Method

Memory

(Words)

Without hardware multiply

Hardware multiply

13

1

69

1

6.9 µs

100 ns

9.1 µs

600 ns

24.2 µs

2.4 µs

25.4 µs

3.6 µs

27.6 µs

400 ns

36.4 µs

2.4 µs

69 µs

1 µs

91 µs

6 µs

8 x 8 unsigned

8 x 8 signed

Without hardware multiply

Hardware multiply

33

6

91

6

Without hardware multiply

Hardware multiply

21

24

52

36

242

24

254

36

96.8 µs

9.6 µs

242 µs

24 µs

254 µs

36 µs

16 x 16 unsigned

16 x 16 signed

Without hardware multiply

Hardware multiply

102.6 µs

14.4 µs

 2002 Microchip Technology Inc.

DS41159B-page 75

PIC18FXX8

Example 7-3 shows the sequence to do a 16 x 16

unsigned multiply. Equation 7-1 shows the algorithm

that is used. The 32-bit result is stored in four registers,

RES3:RES0.

EQUATION 7-2:

16 x 16 SIGNED

MULTIPLICATION

ALGORITHM

RES3:RES0

=

ARG1H:ARG1L • ARG2H:ARG2L

16

EQUATION 7-1:

16 x 16 UNSIGNED

MULTIPLICATION

ALGORITHM

(ARG1H • ARG2H • 2 )+

8

(ARG1H • ARG2L • 2 )+

8

(ARG1L • ARG2H • 2 )+

(ARG1L • ARG2L)+

(-1 • ARG2H<7> • ARG1H:ARG1L • 2 )+

(-1 • ARG1H<7> • ARG2H:ARG2L • 2

16

RES3:RES0

=

ARG1H:ARG1L • ARG2H:ARG2L

16

(ARG1H • ARG2H • 2 )+

)

8

(ARG1H • ARG2L • 2 )+

8

(ARG1L • ARG2H • 2 )+

(ARG1L • ARG2L)

EXAMPLE 7-4:

16 x 16 SIGNED

MULTIPLY ROUTINE

MOVF

MULWF

ARG1L,

ARG2L

W

; ARG1L * ARG2L ->

; PRODH:PRODL

;

EXAMPLE 7-3:

16 x 16 UNSIGNED

MULTIPLY ROUTINE

MOVFF

PRODH, RES1

PRODL, RES0

MOVF

MULWF

ARG1L, W

ARG2L

;

; ARG1L * ARG2L ->

; PRODH:PRODL

;

MOVF

MULWF

ARG1H,

ARG2H

W

; ARG1H * ARG2H ->

; PRODH:PRODL

;

MOVFF

PRODH, RES1

PRODL, RES0

MOVFF

PRODH, RES3

PRODL, RES2

;

MOVF

MULWF

ARG1H,

ARG2H

W

; ARG1H * ARG2H ->

; PRODH:PRODL

;

MOVF

MULWF

ARG1L,

ARG2H

W

; ARG1L * ARG2H ->

; PRODH:PRODL

;

; Add cross

; products

;

MOVFF

PRODH, RES3

PRODL, RES2

MOVF

ADDWF

MOVF

ADDWFC RES2

CLRF WREG

ADDWFC RES3

PRODL,

RES1

PRODH,

W

MOVF

MULWF

ARG1L,

ARG2H

W

; ARG1L * ARG2H ->

; PRODH:PRODL

MOVF

ADDWF

MOVF

PRODL,

RES1

PRODH,

W

;

; Add cross

; products

;

MOVF

MULWF

ARG1H,

W

;

ADDWFC RES2

CLRF WREG

ADDWFC RES3

;

ARG2L

; ARG1H * ARG2L ->

; PRODH:PRODL

;

; Add cross

; products

;

MOVF

ADDWF

MOVF

ADDWFC RES2

CLRF WREG

ADDWFC RES3

PRODL,

RES1

PRODH,

W

;

MOVF

ARG1H,

W

;

MULWF

ARG2L

; ARG1H * ARG2L ->

; PRODH:PRODL

MOVF

ADDWF

MOVF

PRODL,

RES1

PRODH,

W

;

; Add cross

; products

;

BTFSS

BRA

MOVF

SUBWF

MOVF

ARG2H,

7

; ARG2H:ARG2L neg?

; no, check ARG1

;

ADDWFC RES2

CLRF WREG

ADDWFC RES3

;

SIGN_ARG1

ARG1L,

RES2

ARG1H,

W

SUBWFB RES3

Example 7-4 shows the sequence to do a 16 x 16

signed multiply. Equation 7-2 shows the algorithm

used. The 32-bit result is stored in four registers,

RES3:RES0. To account for the sign bits of the argu-

ments, each argument pairs Most Significant bit (MSb)

is tested and the appropriate subtractions are done.

SIGN_ARG1

BTFSS

BRA

ARG1H,

CONT_CODE

ARG2L,

RES2

ARG2H,

7

; ARG1H:ARG1L neg?

; no, done

;

MOVF

SUBWF

MOVF

W

SUBWFB RES3

;

CONT_CODE

:

DS41159B-page 76

 2002 Microchip Technology Inc.

PIC18FXX8

When the IPEN bit is cleared (default state), the inter-

rupt priority feature is disabled and interrupts are com-

patible with PICmicro^®mid-range devices. In

Compatibility mode, the interrupt priority bits for each

source have no effect. The PEIE bit (INTCON register)

enables/disables all peripheral interrupt sources. The

GIE bit (INTCON register) enables/disables all interrupt

sources. All interrupts branch to address 000008h in

Compatibility mode.

8.0

INTERRUPTS

The PIC18FXX8 devices have multiple interrupt

sources and an interrupt priority feature that allows

each interrupt source to be assigned a high priority

level or a low priority level. The high priority interrupt

vector is at 000008h, and the low priority interrupt vec-

tor is at 000018h. High priority interrupt events will

override any low priority interrupts that may be in

progress.

When an interrupt is responded to, the Global Interrupt

Enable bit is cleared to disable further interrupts. If the

IPEN bit is cleared, this is the GIE bit. If interrupt prior-

ity levels are used, this will be either the GIEH or GIEL

bit. High priority interrupt sources can interrupt a low

priority interrupt.

There are 13 registers that are used to control interrupt

operation. These registers are:

• RCON

• INTCON

• INTCON2

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address

(000008h or 000018h). Once in the Interrupt Service

Routine, the source(s) of the interrupt can be deter-

mined by polling the interrupt flag bits. The interrupt

flag bits must be cleared in software before re-enabling

interrupts, to avoid recursive interrupts.

• INTCON3

• PIR1, PIR2, PIR3

• PIE1, PIE2, PIE3

• IPR1, IPR2, IPR3

It is recommended that the Microchip header files sup-

plied with MPLAB^®IDE, be used for the symbolic bit

names in these registers. This allows the assembler/

compiler to automatically take care of the placement of

these bits within the specified register.

The "return from interrupt" instruction, RETFIE, exits

the interrupt routine and sets the GIE bit (GIEH or GIEL

if priority levels are used), which re-enables interrupts.

Each interrupt source has three bits to control its

operation. The functions of these bits are:

For external interrupt events, such as the INT pins or

the PORTB input change interrupt, the interrupt latency

will be three to four instruction cycles. The exact

latency is the same for one or two-cycle instructions.

Individual interrupt flag bits are set, regardless of the

status of their corresponding enable bit, or the GIE bit.

• Flag bit to indicate that an interrupt event

occurred

• Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

• Priority bit to select high priority or low priority

Note: Do not use the MOVFFinstruction to modify

any of the interrupt control registers while

any interrupt is enabled. Doing so may

cause erratic microcontroller behavior.

The interrupt priority feature is enabled by setting the

IPEN bit (RCON register). When interrupt priority is

enabled, there are two bits that enable interrupts glo-

bally. Setting the GIEH bit (INTCON<7>) enables all

interrupts. Setting the GIEL bit (INTCON register)

enables all interrupts that have the priority bit cleared.

When the interrupt flag, enable bit and appropriate glo-

bal interrupt enable bit are set, the interrupt will vector

immediately to address 000008h or 000018h, depend-

ing on the priority level. Individual interrupts can be

disabled through their corresponding enable bits.

 2002 Microchip Technology Inc

Preliminary

DS41159B-page 77

PIC18FXX8

FIGURE 8-1:

INTERRUPT LOGIC

TMR0IF

TMR0IE

TMR0IP

RBIF

RBIE

RBIP

Wake-up if in SLEEP mode

INT0IF

INT0IE

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

Interrupt to CPU

Vector to Location

0008h

Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit

Peripheral Interrupt Priority bit

GIE/GIEH

TMR1IF

TMR1IE

TMR1IP

IPEN

GIEL/PEIE

XXXXIF

XXXXIE

XXXXIP

IPEN

Additional Peripheral Interrupts

High Priority Interrupt Generation

Low Priority Interrupt Generation

Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit

Peripheral Interrupt Priority bit

TMR0IF

TMR0IE

TMR0IP

Interrupt to CPU

Vector to Location

0018h

TMR1IF

TMR1IE

TMR1IP

RBIF

RBIE

RBIP

PEIE/GIEL

GIE/GIEH

XXXXIF

XXXXIE

XXXXIP

INT0IF

INT0IE

INT1IF

INT1IE

INT1IP

Additional Peripheral Interrupts

INT2IF

INT2IE

INT2IP

DS41159B-page 78

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

8.1

INTCON Registers

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit, or the global

enable bit. User software should ensure

the appropriate interrupt flag bits are clear

prior to enabling an interrupt. This feature

allows software polling.

The INTCON Registers are readable and writable reg-

isters, which contain various enable, priority, and flag

bits. Because of the number of interrupts to be con-

trolled, PIC18FXX8 devices have three INTCON regis-

ters. They are detailed in Register 8-1 through

Register 8-3.

REGISTER 8-1:

INTCON REGISTER

R/W-0 R/W-0

R/W-0

RBIE

R/W-0

INT0IF

R/W-x

RBIF

GIE/GIEH PEIE/GIEL TMR0IE

bit 7

INT0IE

TMR0IF

bit 0

bit 7

GIE/GIEH: Global Interrupt Enable bit

When IPEN (RCON<7>) = 0:

1= Enables all unmasked interrupts

0= Disables all interrupts

When IPEN (RCON<7>) = 1:

1= Enables all high priority interrupts

0= Disables all priority interrupts

bit 6

PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN (RCON<7>) = 0:

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

When IPEN (RCON<7>) = 1:

1= Enables all low priority peripheral interrupts

0= Disables all low priority peripheral interrupts

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TMR0IE: TMR0 Overflow Interrupt Enable bit

1= Enables the TMR0 overflow interrupt

0= Disables the TMR0 overflow interrupt

INT0IE: INT0 External Interrupt Enable bit

1= Enables the INT0 external interrupt

0= Disables the INT0 external interrupt

RBIE: RB Port Change Interrupt Enable bit

1= Enables the RB port change interrupt

0= Disables the RB port change interrupt

TMR0IF: TMR0 Overflow Interrupt Flag bit

1= TMR0 register has overflowed (must be cleared in software)

0= TMR0 register did not overflow

INT0IF: INT0 External Interrupt Flag bit

1= The INT0 external interrupt occurred (must be cleared in software by reading PORTB)

0= The INT0 external interrupt did not occur

RBIF: RB Port Change Interrupt Flag bit

1= At least one of the RB7:RB4 pins changed state (must be cleared in software)

0= None of the RB7:RB4 pins have changed state

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc

Preliminary

DS41159B-page 79

PIC18FXX8

REGISTER 8-2:

INTCON2 REGISTER

R/W-1

RBPU

R/W-1

U-0

R/W-1

U-0

R/W-1

RBIP

INTEDG0 INTEDG1

—

TMR0IP

—

bit 7

bit 0

bit 7

bit 6

bit 5

RBPU: PORTB Pull-up Enable bit

1= All PORTB pull-ups are disabled

0= PORTB pull-ups are enabled by individual port latch values

INTEDG0: External Interrupt 0 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

INTEDG1: External Interrupt 1 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

bit 4-3

Unimplmented: Read as ’0’

bit 2

TMR0IP: TMR0 Overflow Interrupt Priority bit

1= High priority

0= Low priority

bit 1

bit 0

Unimplmented: Read as ’0’

RBIP: RB Port Change Interrupt Priority bit

1= High priority

0= Low priority

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit, or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows software polling.

DS41159B-page 80

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 8-3:

INTCON3 REGISTER

R/W-1

U-0

R/W-0

U-0

R/W-0

INT2IF

R/W-0

INT1IF

INT2IP

INT1IP

—

INT2IE

INT1IE

—

bit 7

bit 0

bit 7

bit 6

INT2IP: INT2 External Interrupt Priority bit

1= High priority

0= Low priority

INT1IP: INT1 External Interrupt Priority bit

1= High priority

0= Low priority

bit 5

bit 4

Unimplmented: Read as ’0’

INT2IE: INT2 External Interrupt Enable bit

1= Enables the INT2 external interrupt

0= Disables the INT2 external interrupt

bit 3

INT1IE: INT1 External Interrupt Enable bit

1= Enables the INT1 external interrupt

0= Disables the INT1 external interrupt

bit 2

bit 1

Unimplmented: Read as ’0’

INT2IF: INT2 External Interrupt Flag bit

1= The INT2 external interrupt occurred (must be cleared in software)

0= The INT2 external interrupt did not occur

bit 0

INT1IF: INT1 External Interrupt Flag bit

1= The INT1 external interrupt occurred (must be cleared in software)

0= The INT1 external interrupt did not occur

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit, or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows software polling.

 2002 Microchip Technology Inc

Preliminary

DS41159B-page 81

PIC18FXX8

8.2

PIR Registers

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit, or the global

enable bit, GIE (INTCON register).

The Peripheral Interrupt Request (PIR) registers con-

tain the individual flag bits for the peripheral interrupts

(Register 8-4 through Register 8-6). Due to the number

of peripheral interrupt sources, there are three Periph-

eral Interrupt Request (Flag) registers (PIR1, PIR2,

PIR3).

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to

enabling an interrupt, and after servicing

that interrupt.

REGISTER 8-4:

PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (PIR1)

R/W-0

PSPIF⁽¹⁾

bit 7

R/W-0

ADIF

R-0

R/W-0

SSPIF

R/W-0

RCIF

TXIF

CCP1IF

TMR2IF

TMR1IF

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit⁽¹⁾

1= A read or a write operation has taken place (must be cleared in software)

0= No read or write has occurred

ADIF: A/D Converter Interrupt Flag bit

1= An A/D conversion completed (must be cleared in software)

0= The A/D conversion is not complete

RCIF: USART Receive Interrupt Flag bit

1=The USART receive buffer, RCREG, is full (cleared when RCREG is read)

0=The USART receive buffer is empty

TXIF: USART Transmit Interrupt Flag bit

1= The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)

0= The USART transmit buffer is full

SSPIF: Master Synchronous Serial Port Interrupt Flag bit

1= The transmission/reception is complete (must be cleared in software)

0= Waiting to transmit/receive

CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1= A TMR1 register capture occurred (must be cleared in software)

0= No TMR1 register capture occurred

Compare mode:

1= A TMR1 register compare match occurred (must be cleared in software)

0= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 1

bit 0

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1= TMR2 to PR2 match occurred (must be cleared in software)

0= No TMR2 to PR2 match occurred

TMR1IF: TMR1 Overflow Interrupt Flag bit

1= TMR1 register overflowed (must be cleared in software)

0= TMR1 register did not overflow

Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit

is unimplemented and reads as ’0’.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

DS41159B-page 82

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 8-5:

PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (PIR2)

U-0

R/W-0

CMIF⁽¹⁾

U-0

R/W-0

EEIF

R/W-0

BCLIF

R/W-0

LVDIF

R/W-0

TMR3IF ECCP1IF⁽¹⁾

R/W-0

—

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ’0’

CMIF: Comparator Interrupt Flag bit ⁽¹⁾

1= Comparator input has changed

0= Comparator input has not changed

bit 5

bit 4

Unimplemented: Read as’0’

EEIF: EEPROM Write Operation Interrupt Flag bit

1= Write operation is complete (must be cleared in software)

0= Write operation is not complete

bit 3

bit 2

bit 1

bit 0

BCLIF: Bus Collision Interrupt Flag bit

1= A bus collision occurred (must be cleared in software)

0= No bus collision occurred

LVDIF: Low Voltage Detect Interrupt Flag bit

1= A low voltage condition occurred (must be cleared in software)

0= The device voltage is above the Low Voltage Detect trip point

TMR3IF: TMR3 Overflow Interrupt Flag bit

1= TMR3 register overflowed (must be cleared in software)

0= TMR3 register did not overflow

ECCP1IF: ECCP1 Interrupt Flag bit ⁽¹⁾

Capture mode:

1= A TMR1 (TMR3) register capture occurred

(must be cleared in software)

0= No TMR1 (TMR3) register capture occurred

Compare mode:

1= A TMR1 register compare match occurred

(must be cleared in software)

0= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit

is unimplemented and reads as ’0’.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc

Preliminary

DS41159B-page 83

PIC18FXX8

REGISTER 8-6:

PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 (PIR3)

R/W-0

IRXIF

R/W-0

ERRIF

R/W-0

WAKIF

TXB2IF

TXB1IF

TXB0IF

RXB1IF

RXB0IF

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IRXIF: Invalid Message Received Interrupt Flag bit

1= An invalid message has occurred on the CAN bus

0= An invalid message has not occurred on the CAN bus

WAKIF: Bus Activity Wake-up Interrupt Flag bit

1= Activity on the CAN bus has occurred

0= Activity on the CAN bus has not occurred

ERRIF: CAN Bus Error Interrupt Flag bit

1= An error has occurred in the CAN module (multiple sources)

0= An error has not occurred in the CAN module

TXB2IF: Transmit Buffer 2 Interrupt Flag bit

1= Transmit Buffer 2 has completed transmission of a message, and may be reloaded

0= Transmit Buffer 2 has not completed transmission of a message

TXB1IF: Transmit Buffer 1 Interrupt Flag bit

1= Transmit Buffer 1 has completed transmission of a message, and may be reloaded

0= Transmit Buffer 1 has not completed transmission of a message

TXB0IF: Transmit Buffer 0 Interrupt Flag bit

1= Transmit Buffer 0 has completed transmission of a message, and may be reloaded

0= Transmit Buffer 0 has not completed transmission of a message

RXB1IF: Receive Buffer 1 Interrupt Flag bit

1= Receive Buffer 1 has received a new message

0= Receive Buffer 1 has not received a new message

RXB0IF: Receive Buffer 0 Interrupt Flag bit

1= Receive Buffer 0 has received a new message

0= Receive Buffer 0 has not received a new message

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

DS41159B-page 84

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

8.3

PIE Registers

The Peripheral Interrupt Enable (PIE) registers contain

the individual enable bits for the peripheral interrupts

(Register 8-7 through Register 8-9). Due to the number

of peripheral interrupt sources, there are three Periph-

eral Interrupt Enable registers (PIE1, PIE2, PIE3).

When IPEN is clear, the PEIE bit must be set to enable

any of these peripheral interrupts.

REGISTER 8-7:

PERIPHERAL INTERRUPT ENABLE REGISTER 1 (PIE1)

R/W-0

PSPIE⁽¹⁾

bit 7

R/W-0

ADIE

R/W-0

RCIE

R/W-0

TXIE

R/W-0

SSPIE

R/W-0

TMR1IE

bit 0

CCP1IE

TMR2IE

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit⁽¹⁾

1= Enables the PSP read/write interrupt

0= Disables the PSP read/write interrupt

ADIE: A/D Converter Interrupt Enable bit

1= Enables the A/D interrupt

0= Disables the A/D interrupt

RCIE: USART Receive Interrupt Enable bit

1= Enables the USART receive interrupt

0= Disables the USART receive interrupt

TXIE: USART Transmit Interrupt Enable bit

1= Enables the USART transmit interrupt

0= Disables the USART transmit interrupt

SSPIE: Master Synchronous Serial Port Interrupt Enable bit

1= Enables the MSSP interrupt

0= Disables the MSSP interrupt

CCP1IE: CCP1 Interrupt Enable bit

1= Enables the CCP1 interrupt

0= Disables the CCP1 interrupt

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1= Enables the TMR2 to PR2 match interrupt

0= Disables the TMR2 to PR2 match interrupt

TMR1IE: TMR1 Overflow Interrupt Enable bit

1= Enables the TMR1 overflow interrupt

0= Disables the TMR1 overflow interrupt

Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit

is unimplemented and reads as ’0’.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc

Preliminary

DS41159B-page 85

PIC18FXX8

REGISTER 8-8:

PERIPHERAL INTERRUPT ENABLE REGISTER 2 (PIE2)

U-0

R/W-0

CMIE⁽¹⁾

U-0

R/W-0

EEIE

R/W-0

BCLIE

R/W-0

LVDIE

R/W-0

TMR3IE ECCP1IE⁽¹⁾

R/W-0

—

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as '0'

CMIE: Comparator Interrupt Enable bit⁽¹⁾

1= Enables the comparator interrupt

0= Disables the comparator interrupt

bit 5

bit 4

Unimplemented: Read as '0'

EEIE: EEPROM Write Interrupt Enable bit

1= Enabled

0= Disabled

bit 3

bit 2

bit 1

bit 0

BCLIE: Bus Collision Interrupt Enable bit

1= Enabled

0= Disabled

LVDIE: Low Voltage Detect Interrupt Enable bit

1= Enabled

0= Disabled

TMR3IE: TMR3 Overflow Interrupt Enable bit

1= Enables the TMR3 overflow interrupt

0= Disables the TMR3 overflow interrupt

ECCP1IE: ECCP1 Interrupt Enable bit ⁽¹⁾

1= Enables the ECCP1 interrupt

0= Disables the ECCP1 interrupt

Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit

is unimplemented and reads as ’0’.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

DS41159B-page 86

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 8-9:

PERIPHERAL INTERRUPT ENABLE REGISTER 3 (PIE3)

R/W-1

IRXIE

R/W-1

ERRIE

R/W-1

WAKIE

TXB2IE

TXB1IE

TXB0IE

RXB1IE

RXB0IE

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IRXIE: Invalid CAN Message Received Interrupt Enable bit

1= Enables the invalid CAN message received interrupt

0= Disables the invalid CAN message received interrupt

WAKIE: Bus Activity Wake-up Interrupt Enable bit

1= Enables the bus activity wake-up interrupt

0= Disables the bus activity wake-up interrupt

ERRIE: CAN bus Error Interrupt Enable bit

1= Enables the CAN bus error interrupt

0= Disables the CAN bus error interrupt

TXB2IE: Transmit Buffer 2 Interrupt Enable bit

1= Enables the Transmit Buffer 2 interrupt

0= Disables the Transmit Buffer 2 interrupt

TXB1IE: Transmit Buffer 1 Interrupt Enable bit

1= Enables the Transmit Buffer 1 interrupt

0= Disables the Transmit Buffer 1 interrupt

TXB0IE: Transmit Buffer 0 Interrupt Enable bit

1= Enables the Transmit Buffer 0 interrupt

0= Disables the Transmit Buffer 0 interrupt

RXB1IE: Receive Buffer 1 Interrupt Enable bit

1= Enables the Receive Buffer 1 interrupt

0= Disables the Receive Buffer 1 interrupt

RXB0IE: Receive Buffer 0 Interrupt Enable bit

1= Enables the Receive Buffer 0 interrupt

0= Disables the Receive Buffer 0 interrupt

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc

Preliminary

DS41159B-page 87

PIC18FXX8

8.4

IPR Registers

The Interrupt Priority (IPR) registers contain the individ-

ual priority bits for the peripheral interrupts. Due to the

number of peripheral interrupt sources, there are three

Peripheral Interrupt Priority registers (IPR1, IPR2 and

IPR3). The operation of the priority bits requires that

the Interrupt Priority Enable bit (IPEN) be set.

REGISTER 8-10: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 (IPR1)

R/W-1

PSPIP⁽¹⁾

bit 7

R/W-1

ADIP

R/W-1

RCIP

R/W-1

TXIP

R/W-1

SSPIP

R/W-1

TMR1IP

bit 0

CCP1IP

TMR2IP

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit⁽¹⁾

1= High priority

0= Low priority

ADIP: A/D Converter Interrupt Priority bit

1= High priority

0= Low priority

RCIP: USART Receive Interrupt Priority bit

1= High priority

0= Low priority

TXIP: USART Transmit Interrupt Priority bit

1= High priority

0= Low priority

SSPIP: Master Synchronous Serial Port Interrupt Priority bit

1= High priority

0= Low priority

CCP1IP: CCP1 Interrupt Priority bit

1=High priority

0=Low priority

TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

1= High priority

0= Low priority

TMR1IP: TMR1 Overflow Interrupt Priority bit

1= High priority

0= Low priority

Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit

is unimplemented and reads as ’0’.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

DS41159B-page 88

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 8-11: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (IPR2)

U-0

R/W-1

CMIP⁽¹⁾

U-0

R/W-0

EEIP

R/W-1

BCLIP

R/W-1

LVDIP

R/W-1

TMR3IP ECCP1IP⁽¹⁾

R/W-1

—

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as '0'

CMIP: Comparator Interrupt Priority bit⁽¹⁾

1= High priority

0= Low priority

bit 5

bit 4

Unimplemented: Read as '0'

EEIP: EEPROM Write Interrupt Priority bit

1= High priority

0= Low priority

bit 3

bit 2

bit 1

bit 0

BCLIP: Bus Collision Interrupt Priority bit

1= High priority

0= Low priority

LVDIP: Low Voltage Detect Interrupt Priority bit

1= High priority

0= Low priority

TMR3IP: TMR3 Overflow Interrupt Priority bit

1= High priority

0= Low priority

ECCP1IP: ECCP1 Interrupt Priority bit⁽¹⁾

1= High priority

0= Low priority

Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit

is unimplemented and reads as ’0’.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc

Preliminary

DS41159B-page 89

PIC18FXX8

REGISTER 8-12: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 (IPR3)

R/W-1

IRXIP

R/W-1

ERRIP

R/W-1

WAKIP

TXB2IP

TXB1IP

TXB0IP

RXB1IP

RXB0IP

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IRXIP: Invalid Message Received Interrupt Priority bit

1= High priority

0= Low priority

WAKIP: Bus Activity Wake-up Interrupt Priority bit

1= High priority

0= Low priority

ERRIP: CAN bus Error Interrupt Priority bit

1= High priority

0= Low priority

TXB2IP: Transmit Buffer 2 Interrupt Priority bit

1= High priority

0= Low priority

TXB1IP: Transmit Buffer 1 Interrupt Priority bit

1= High priority

0= Low priority

TXB0IP: Transmit Buffer 0 Interrupt Priority bit

1= High priority

0= Low priority

RXB1IP: Receive Buffer 1 Interrupt Priority bit

1= High priority

0= Low priority

RXB0IP: Receive Buffer 0 Interrupt Priority bit

1= High priority

0= Low priority

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

DS41159B-page 90

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

8.5

RCON Register

The Reset Control (RCON) register contains the IPEN

bit, which is used to enable prioritized interrupts. The

functions of the other bits in this register are discussed

in more detail in Section 4.14.

REGISTER 8-13: RCON REGISTER

R/W-0

IPEN

U-0

R/W-1

RI

R-1

TO

R-1

PD

R/W-0

POR

R/W-0

BOR

—

bit 7

bit 0

bit 7

IPEN: Interrupt Priority Enable bit

1= Enable priority levels on interrupts

0= Disable priority levels on interrupts (16CXXX Compatibility mode)

bit 6-5

bit 4

Unimplemented: Read as '0'

RI: RESETInstruction Flag bit

For details of bit operation, see Register 4-3

bit 3

bit 2

bit 1

bit 0

TO: Watchdog Time-out Flag bit

For details of bit operation, see Register 4-3

PD: Power-down Detection Flag bit

For details of bit operation, see Register 4-3

POR: Power-on Reset Status bit

For details of bit operation, see Register 4-3

BOR: Brown-out Reset Status bit

For details of bit operation, see Register 4-3

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc

Preliminary

DS41159B-page 91

PIC18FXX8

8.6

INT Interrupts

8.8

PORTB Interrupt-on-Change

External interrupts on the RB0/INT0, RB1/INT1 and

RB2/INT2 pins are edge triggered: either rising, if the

corresponding INTEDGx bit is set in the INTCON2 reg-

ister, or falling, if the INTEDGx bit is clear. When a valid

edge appears on the RBx/INTx pin, the corresponding

flag bit INTxIF is set. This interrupt can be disabled by

clearing the corresponding enable bit INTxIE. Flag bit

INTxIF must be cleared in software in the Interrupt Ser-

vice Routine before re-enabling the interrupt. All exter-

nal interrupts (INT0, INT1 and INT2) can wake-up the

processor from SLEEP, if bit INTxIE was set prior to

going into SLEEP. If the global interrupt enable bit GIE

is set, the processor will branch to the interrupt vector

following wake-up.

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON register). The interrupt can be enabled/

disabled by setting/clearing enable bit RBIE (INTCON

register). Interrupt priority for PORTB interrupt-on-

change is determined by the value contained in the

interrupt priority bit RBIP (INTCON2 register).

8.9

Context Saving During Interrupts

During an interrupt, the return PC value is saved on the

stack. Additionally, the WREG, STATUS and BSR regis-

ters are saved on the fast return stack. If a fast return

from interrupt is not used (see Section 4.3), the user

may need to save the WREG, STATUS and BSR regis-

ters in software. Depending on the user’s application,

other registers may also need to be saved. Example 8-1

saves and restores the WREG, STATUS and BSR

registers during an Interrupt Service Routine.

Interrupt priority for INT1 and INT2 is determined by the

value contained in the interrupt priority bits INT1IP

(INTCON3<6>) and INT2IP (INTCON3<7>). There is

no priority bit associated with INT0; it is always a high

priority interrupt source.

8.7

TMR0 Interrupt

In 8-bit mode (which is the default), an overflow (FFh →

00h) in the TMR0 register will set flag bit TMR0IF. In 16-

bit mode, an overflow (FFFFh → 0000h) in the

TMR0H:TMR0L registers will set flag bit TMR0IF. The

interrupt can be enabled/disabled by setting/clearing

enable bit TMR0IE (INTCON register). Interrupt priority

for Timer0 is determined by the value contained in the

interrupt priority bit TMR0IP (INTCON2 register). See

Section 11.0 for further details on the Timer0 module.

EXAMPLE 8-1:

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF

MOVFF

;

W_TEMP

STATUS, STATUS_TEMP

BSR, BSR_TEMP

; W_TEMP is in Low Access bank

; STATUS_TEMP located anywhere

; BSR located anywhere

; USER ISR CODE

;

MOVFF

MOVF

MOVFF

BSR_TEMP, BSR

W_TEMP, W

STATUS_TEMP, STATUS

; Restore BSR

; Restore WREG

; Restore STATUS

DS41159B-page 92

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 9-1:

RA3:RA0 AND RA5 PINS

BLOCK DIAGRAM

9.0

I/O PORTS

Depending on the device selected, there are up to five

general purpose I/O ports available on PIC18FXX8

devices. Some pins of the I/O ports are multiplexed

with an alternate function from the peripheral features

on the device. In general, when a peripheral is enabled,

that pin may not be used as a general purpose I/O pin.

RD LATA

Data Bus

Q

D

VDD

WR LATA or

WR PORTA

Each port has three registers for its operation:

CK

Data Latch

Q

P

• TRIS register (Data Direction register)

• PORT register (reads the levels on the pins of the

I/O pin⁽¹⁾

device)

Q

D

N

• LAT register (output latch).

WR TRISA

The data latch (LAT register) is useful for

read-modify-write operations on the value that the I/O

pins are driving.

CK

Q

VSS

Analog

Input Mode

TRIS Latch

9.1

PORTA, TRISA and LATA

Registers

RD TRISA

TTL

Input

Buffer

Q

D

PORTA is a 7-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISA. Setting a

TRISA bit (= ‘1’) will make the corresponding PORTA

pin an input (i.e., put the corresponding output driver in

a High-Impedance mode). Clearing a TRISA bit (= ‘0’)

will make the corresponding PORTA pin an output (i.e.,

put the contents of the output latch on the selected pin).

On a Power-on Reset, these pins are configured as

inputs and read as '0'.

EN

RD PORTA

SS Input (RA5 only)

To A/D Converter and LVD Modules

Note 1: I/O pins have diode protection to VDD and VSS.

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the port latch.

FIGURE 9-2:

RA4/T0CKI PIN BLOCK

DIAGRAM

Read-modify-write operations on the LATA register,

reads and writes the latched output value for PORTA.

The RA4 pin is multiplexed with the Timer0 module

clock input to become the RA4/T0CKI pin. The

RA4/T0CKI pin is a Schmitt Trigger input and an open

drain output. All other RA port pins have TTL input

levels and full CMOS output drivers.

RD LATA

Data Bus

Q

D

The other PORTA pins are multiplexed with analog

inputs and the analog VREF+ and VREF- inputs. The

operation of each pin is selected by clearing/setting the

control bits in the ADCON1 register (A/D Control

Register 1). On a Power-on Reset, these pins are

configured as analog inputs and read as '0'.

WR LATA or

WR PORTA

CK

Data Latch

Q

I/O pin⁽¹⁾

N

D

Q

VSS

Schmitt

Trigger

Input

WR TRISA

RD TRISA

The TRISA register controls the direction of the RA

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are

maintained set, when using them as analog inputs.

CK

Q

Buffer

TRIS Latch

TTL

Input

Buffer

EXAMPLE 9-1:

INITIALIZING PORTA

Q

D

CLRF

PORTA ; Initialize PORTA by

; clearing output data latches

CLRF

LATA

; Alternate method to clear

; output data latches

; Configure A/D

EN

RD PORTA

MOVLW 07h

MOVWF ADCON1 ; for digital inputs

TMR0 Clock Input

MOVLW 0xCF

; Value used to initialize

; data direction

Note 1: I/O pin has diode protection to VSS only.

MOVWF TRISA ; Set RA3:RA0 as inputs,

; RA5:RA4 as outputs

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 93

PIC18FXX8

FIGURE 9-3:

RA6/OSC2/CLKOUT PIN BLOCK DIAGRAM

(FOSC = 101, 111)

From OSC1

Oscillator

Circuit

CLKO (FOSC/4)

1

0

Data Latch

Data Bus

Q

D

VDD

P

WR PORTA

CK

Q

RA6/OSC2/

CLKO pin⁽²⁾

TRIS Latch

Q

D

N

WR TRISA

CK

Q

(FOSC = 100,

101, 110, 111)

VSS

Schmitt

Trigger

RD TRISA

Input Buffer

Q

D

Data Latch

EN

RD PORTA

(FOSC = 110, 100)

Note 1: CLKO is 1/4 of FOSC.

2: I/O pin has diode protection to VDD and VSS.

TABLE 9-1:

PORTA FUNCTIONS

Name

Bit#

bit0

Buffer

TTL

Function

RA0/AN0/CVREF

Input/output, analog input, or analog comparator voltage reference

output.

RA1/AN1

bit1

bit2

bit3

bit4

bit5

TTL

Input/output or analog input.

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

Input/output, analog input or VREF-.

Input/output, analog input or VREF+.

ST/OD Input/output, external clock input for Timer0, output is open drain type.

RA5/SS/AN4/LVDIN

TTL

Input/output, slave select input for synchronous serial port, analog input,

or low voltage detect input.

RA6/OSC2/CLKO

bit6

TTL

Input/output or oscillator clock output.

Legend: TTL = TTL input, ST = Schmitt Trigger input, OD = Open Drain

TABLE 9-2:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on

all other

RESETS

Value on

POR, BOR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTA

LATA

—

RA6

RA5

RA4

RA3

RA2

RA1

RA0

-00x 0000 -uuu uuuu

-xxx xxxx -uuu uuuu

-111 1111 -111 1111

Latch A Data Output Register

PORTA Data Direction Register

TRISA

ADCON1 ADFM ADCS2

—

PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 uu-- uuuu

Legend: x= unknown, u= unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.

DS41159B-page 94

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is per-

formed by clearing bit RBPU (INTCON2 register). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

9.2

PORTB, TRISB and LATB Registers

PORTB is an 8-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISB. Setting a

TRISB bit (= ‘1’) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a High-Impedance mode). Clearing a TRISB bit (= ‘0’)

will make the corresponding PORTB pin an output ( i.e.,

put the contents of the output latch on the selected pin).

Four of the PORTB pins (RB7:RB4) have an

interrupt-on-change feature. Only pins configured as

inputs can cause this interrupt to occur (i.e., any

RB7:RB4 pin configured as an output is excluded from

the interrupt-on-change comparison). The input pins (of

RB7:RB4) are compared with the old value latched on

the last read of PORTB. The “mismatch” outputs of

RB7:RB4 are ORed together to generate the RB Port

Change Interrupt with flag bit RBIF (INTCON register).

Read-modify-write operations on the LATB register,

read and write the latched output value for PORTB.

EXAMPLE 9-2:

CLRF

INITIALIZING PORTB

PORTB

; Initialize PORTB by

; clearing output

; data latches

This interrupt can wake the device from SLEEP. The

user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

CLRF

LATB

; Alternate method

; to clear output

; data latches

MOVLW

MOVWF

0CFh

; Value used to

; initialize data

; direction

; Set RB3:RB0 as inputs

; RB5:RB4 as outputs

; RB7:RB6 as inputs

a) Any read or write of PORTB (except with the

MOVFF instruction). This will end the mismatch

condition.

TRISB

b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

FIGURE 9-4:

RB7:RB4 PINS BLOCK

DIAGRAM

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

VDD

RBPU⁽²⁾

Data Bus

Weak

Pull-up

P

Data Latch

D

Q

I/O pin⁽¹⁾

FIGURE 9-5:

RB1:RB0 PINS BLOCK

DIAGRAM

WR LATB

or

CK

TRIS Latch

WR PORTB

VDD

RBPU⁽²⁾

D

Q

Weak

P

Pull-up

WR TRISB

TTL

Input

Buffer

CK

Data Latch

Data Bus

WR Port

ST

Buffer

D

Q

I/O pin⁽¹⁾

RD TRISB

RD LATB

CK

TRIS Latch

D

Q

TTL

Latch

WR TRIS

RD TRIS

Input

Buffer

CK

Q

D

RD PORTB

Set RBIF

EN

Q1

Q3

Q

D

From other

RB7:RB4 pins

EN

RD Port

RBx/INTx

Schmitt Trigger

Buffer

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS

bit(s) and clear the RBPU bit (INTCON2 register).

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS

bit(s) and clear the RBPU bit (INTCON2 register).

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 95

PIC18FXX8

FIGURE 9-6:

RB2/CANTX BLOCK DIAGRAM

OPMODE2:OPMODE0 = 000

ENDRHI

CANTX

0

1

RD LATB

Data Bus

VDD

P

Data Latch

D

Q

WR PORTB or

WR LATB

CK

Q

(1)

TRIS Latch

RB2 pin

Q

D

N

WR TRISB

RD TRISB

CK

Q

VSS

Schmitt

Trigger

Q

D

EN

RD PORTB

Note 1: I/O pin has diode protection to VDD and VSS.

FIGURE 9-7:

BLOCK DIAGRAM OF RB3/CANRX PIN

CANCON<7:5>

VDD

(2)

RBPU

Weak

Pull-up

P

Data Latch

Data Bus

D

Q

I/O

WR LATB or PORTB

WR TRISB

(1)

CK

TRIS Latch

D

Q

CK

TTL

Input

Buffer

RD TRISB

RD LATB

Q

D

EN

RD PORTB

RB3 or CANRX

Schmitt Trigger

Buffer

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).

.

DS41159B-page 96

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 9-3:

PORTB FUNCTIONS

Name

Bit#

Buffer

Function

RB0/INT0

bit0

TTL/ST⁽¹⁾Input/output pin or external interrupt 0 input.

Internal software programmable weak pull-up.

RB1/INT1

bit1

bit2

bit3

bit4

bit5

TTL/ST⁽¹⁾Input/output pin or external interrupt 1 input.

Internal software programmable weak pull-up.

TTL/ST⁽¹⁾

RB2/INT2/

CANTX

Input/output pin, external interrupt 2 input or CAN bus transmit pin.

Internal software programmable weak pull-up.

RB3/CANRX

TTL

Input/output pin or CAN bus receive pin.

Internal software programmable weak pull-up.

RB4

TTL

Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.

RB5/PGM

Input/output pin (with interrupt-on-change). Internal software programmable

weak pull-up. Low voltage serial programming enable.

RB6/PGC

RB7/PGD

bit6

bit7

TTL/ST⁽²⁾Input/output pin (with interrupt-on-change). Internal software programmable

weak pull-up. Serial programming clock.

TTL/ST⁽²⁾Input/output pin (with interrupt-on-change). Internal software programmable

weak pull-up. Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

TABLE 9-4:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

0000 000x 0000 000u

LATB

LATB Data Output Register

TRISB

INTCON

PORTB Data Direction Register

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF INT0IF

RBIF

RBIP

INTCON2

INTCON3

RBPU

INTEDG0 INTEDG1 INTEDG2

INT1IP INT2IE

—

TMR0IP

—

1111 -1-1 1111 -1-1

INT2IP

—

INT1IE

—

INT2IF INT1IF 11-0 0-00 11-0 0-00

Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 97

PIC18FXX8

while other peripherals override the TRIS bit to make a

pin an input. The user should refer to the corresponding

peripheral section for the correct TRIS bit settings.

9.3

PORTC, TRISC and LATC Registers

PORTC is an 8-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISC. Setting a

TRISC bit (= ‘1’) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a High-Impedance mode). Clearing a TRISC bit (= ‘0’)

will make the corresponding PORTC pin an output (i.e.,

put the contents of the output latch on the selected pin).

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register,

without concern due to peripheral overrides.

EXAMPLE 9-3:

INITIALIZING PORTC

CLRF

PORTC

; Initialize PORTC by

; clearing output

; data latches

Read-modify-write operations on the LATC register,

read and write the latched output value for PORTC.

CLRF

LATC

; Alternate method

; to clear output

; data latches

; Value used to

; initialize data

; direction

; Set RC3:RC0 as inputs

; RC5:RC4 as outputs

; RC7:RC6 as inputs

PORTC is multiplexed with several peripheral functions

(Table 9-5). PORTC pins have Schmitt Trigger input

buffers.

MOVLW

MOVWF

0CFh

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an output,

TRISC

FIGURE 9-8:

PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

Peripheral Out Select

Peripheral Data Out

VDD

P

0

1

RD LATC

Data Bus

D

Q

WR LATC

or

WR PORTC

(1)

CK

I/O pin

TRIS OVERRIDE

Data Latch

N

D

Q

Pin Override

Peripheral

VSS

TRIS

Override

WR TRISC

RC0

Yes

Timer1 OSC for

Timer1/Timer3

CK

TRIS Latch

RC1

Yes

Timer1 OSC for

Timer1/Timer3

RD TRISC

RC2

RC3

No

—

Schmitt

Trigger

Peripheral Enable

2

Yes

SPI/I C Master

Clock

Q

D

2

RC4

RC5

RC6

Yes

I C Data Out

EN

SPI Data Out

RD PORTC

USART Async

Peripheral Data In

Xmit, Sync Clock

RC7

Yes

USART Sync

Data Out

Note 1: I/O pins have diode protection to VDD and VSS.

DS41159B-page 98

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 9-5:

Name

PORTC FUNCTIONS

Bit# Buffer Type

Function

RC0/T1OSO/T1CKI

bit0

ST

Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock

input.

RC1/T1OSI

RC2/CCP1

bit1

bit2

bit3

bit4

bit5

bit6

ST

Input/output port pin or Timer1 oscillator input.

Input/output port pin or Capture1 input/Compare1 output/PWM1 output.

Input/output port pin or Synchronous Serial clock for SPI/I²C.

Input/output port pin or SPI Data in (SPI mode) or Data I/O (I²C mode).

Input/output port pin or Synchronous Serial Port data output.

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

Input/output port pin, Addressable USART Asynchronous Transmit or

Addressable USART Synchronous Clock.

RC7/RX/DT

bit7

ST

Input/output port pin, Addressable USART Asynchronous Receive or

Addressable USART Synchronous Data.

Legend: ST = Schmitt Trigger input

TABLE 9-6:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on

all other

RESETS

Value on

POR, BOR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

xxxx xxxx uuuu uuuu

PORTC

LATC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

LATC Data Output Register

PORTC Data Direction Register

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

TRISC

Legend: x= unknown, u= unchanged

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 99

PIC18FXX8

PORTD can be configured as an 8-bit wide micro-

processor port (Parallel Slave Port, or PSP) by setting

the control bit PSPMODE (TRISE<4>). In this mode,

the input buffers are TTL. See Section 10.0 for

additional information on the Parallel Slave Port.

9.4

PORTD, TRISD and LATD

Registers

Note: This port is only available on the

PIC18F448 and PIC18F458.

PORTD is also multiplexed with the analog comparator

module and the ECCP module.

PORTD is an 8-bit wide, bi-directional port. The corre-

sponding Data Direction register for the port is TRISD.

Setting a TRISD bit (= ‘1’) will make the corresponding

PORTD pin an input (i.e., put the corresponding output

driver in a High-Impedance mode). Clearing a TRISD

bit (= ‘0’) will make the corresponding PORTD pin an

output (i.e., put the contents of the output latch on the

selected pin).

EXAMPLE 9-4:

INITIALIZING PORTD

CLRF

PORTD

; Initialize PORTD by

; clearing output

; data latches

CLRF

LATD

; Alternate method

; to clear output

; data latches

Read-modify-write operations on the LATD register

reads and writes the latched output value for PORTD.

MOVLW

MOVWF

MOVLW

07h

CMCON

0CFh

; comparator off

PORTD is uses Schmitt Trigger input buffers. Each pin

is individually configurable as an input or output.

; Value used to

; initialize data

; direction

MOVWF

TRISD

; Set RD3:RD0 as inputs

; RD5:RD4 as outputs

; RD7:RD6 as inputs

FIGURE 9-9:

PORTD BLOCK DIAGRAM IN I/O PORT MODE

PORT/PSP Select

PSP Data Out

RD LATD

VDD

P

Data Bus

D

Q

(1)

WR LATD

or

PORTD

RD0 pin

CK

N

Data Latch

D

Q

Vss

WR TRISD

CK

TRIS Latch

RD TRISD

PSP Read

Schmitt

Trigger

Q

D

EN

RD PORTD

PSP Write

C1IN+

Note 1: I/O pins have diode protection to VDD and VSS.

DS41159B-page 100

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 9-7:

Name

PORTD FUNCTIONS

Bit# Buffer Type

Function

RD0/PSP0/C1IN+

RD1/PSP1/C1IN-

RD2/PSP2/C2IN+

RD3/PSP3/C2IN-

bit0

bit1

bit2

bit3

ST/TTL⁽¹⁾

Input/output port pin, parallel slave port bit0 or C1IN+ Comparator

input.

Input/output port pin, parallel slave port bit1 or C1IN- Comparator

input.

Input/output port pin, parallel slave port bit2 or C2IN+ Comparator

input.

Input/output port pin, parallel slave port bit3 or C2IN- Comparator

input.

RD4/PSP4/ECCP1/P1A bit4

ST/TTL⁽¹⁾

Input/output port pin, parallel slave port bit4 or ECCP1/P1A pin.

Input/output port pin, parallel slave port bit5 or ECCP1/P1B pin.

Input/output port pin, parallel slave port bit6 or ECCP1/P1C pin.

Input/output port pin, parallel slave port bit7 or ECCP1/P1D pin.

RD5/PSP5/P1B

RD6/PSP6/P1C

RD7/PSP7/P1D

bit5

bit6

bit7

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.

TABLE 9-8:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTD

RD7 RD6

RD5

RD4

RD3

RD2

RD1

RD0

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

LATD

LATD Data Output Register

PORTD Data Direction Register

IBF OBF IBOV PSPMODE

TRISD

—

TRISE2 TRISE1 TRISE0 0000 -111 0000 -111

TRISE

Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by PORTD.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 101

PIC18FXX8

When the Parallel Slave Port is active, the PORTE pins

function as its control inputs. For additional details,

refer to Section 10.0.

9.5

PORTE, TRISE and LATE

Registers

Note: This port is only available on the

PORTE pins are also multiplexed with inputs for the

A/D converter and outputs for the analog comparators.

When selected as an analog input, these pins will read

as '0's. Direction bits TRISE<2:0> control the direction

of the RE pins, even when they are being used as ana-

log inputs. The user must make sure to keep the pins

configured as inputs when using them as analog

inputs.

PIC18F448 and PIC18F458.

PORTE is a 3-bit wide, bi-directional port. PORTE has

three pins (RE0/AN5/RD, RE1/AN6/WR/C1OUT and

RE2/AN7/CS/C2OUT), which are individually config-

urable as inputs or outputs. These pins have Schmitt

Trigger input buffers.

Read-modify-write operations on the LATE register,

reads and writes the latched output value for PORTE.

EXAMPLE 9-5:

INITIALIZING PORTE

The corresponding Data Direction register for the port

is TRISE. Setting a TRISE bit (= ‘1’) will make the cor-

responding PORTE pin an input (i.e., put the corre-

sponding output driver in a High-Impedance mode).

Clearing a TRISE bit (= ‘0’) will make the corresponding

PORTE pin an output (i.e., put the contents of the

output latch on the selected pin).

CLRF

PORTE

LATE

03h

; Initialize PORTE by

; clearing output

; data latches

; Alternate method

; to clear output

; data latches

; Value used to

; initialize data

; direction

CLRF

MOVLW

MOVWF

The TRISE register also controls the operation of the

Parallel Slave Port, through the control bits in the upper

half of the register. These are shown in Register 9-1.

TRISE

; Set RE1:RE0 as inputs

; RE2 as an output

; (RE4=0 - PSPMODE Off)

FIGURE 9-10:

PORTE BLOCK DIAGRAM

Peripheral Out Select

Peripheral Data Out

VDD

P

0

1

RD LATE

Data Bus

D

Q

(1)

I/O pin

WR LATE

or

WR PORTE

CK

Data Latch

N

D

Q

VSS

TRIS

WR TRISE

CK

Override

TRIS Latch

RD TRISE

Schmitt

Trigger

TRIS OVERRIDE

Peripheral Enable

Pin Override Peripheral

Q

D

RE0

RE1

RE2

Yes

PSP

EN

RD PORTE

Peripheral Data In

Note 1: I/O pins have diode protection to VDD and VSS.

DS41159B-page 102

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 9-1:

TRISE REGISTER

R-0

IBF

R-0

R/W-0

IBOV

R/W-0

U-0

R/W-1

OBF

PSPMODE

—

TRISE2

TRISE1

TRISE0

bit 7

bit 0

bit 7

bit 6

bit 5

IBF: Input Buffer Full Status bit

1= A word has been received and waiting to be read by the CPU

0= No word has been received

OBF: Output Buffer Full Status bit

1= The output buffer still holds a previously written word

0= The output buffer has been read

IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)

1= A write occurred when a previously input word has not been read

(must be cleared in software)

0= No overflow occurred

bit 4

PSPMODE: Parallel Slave Port Mode Select bit

1= Parallel Slave Port mode

0= General purpose I/O mode

bit 3

bit 2

Unimplemented: Read as '0'

TRISE2: RE2 Direction Control bit

1= Input

0= Output

bit 1

bit 0

TRISE1: RE1 Direction Control bit

1= Input

0= Output

TRISE0: RE0 Direction Control bit

1= Input

0= Output

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

TABLE 9-9:

PORTE FUNCTIONS

Bit# Buffer Type

Name

Function

ST/TTL⁽¹⁾

Input/output port pin, analog input or read control input in Parallel

Slave Port mode.

RE0/AN5/RD

bit0

ST/TTL⁽¹⁾

Input/output port pin, analog input, write control input in Parallel Slave

Port mode or Comparator 1 output.

ST/TTL⁽¹⁾Input/output port pin, analog input, chip select control input in Parallel

Slave Port mode or Comparator 2 output.

RE1/AN6/WR/C1OUT

RE2/AN7/CS/C2OUT

bit1

bit2

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 103

PIC18FXX8

TABLE 9-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Value on

all other

RESETS

Value on:

POR, BOR

Name Bit 7 Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TRISE

IBF OBF IBOV PSPMODE

—

TRISE2

TRISE1

TRISE0 0000 -111 0000 -111

PORTE

—

Read PORTE pin/

Write PORTE Data Latch

---- -xxx ---- -uuu

LATE

—

Read PORTE Data Latch/

Write PORTE Data Latch

---- -xxx ---- -uuu

Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by PORTE.

DS41159B-page 104

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 10-1:

PORTD AND PORTE

BLOCK DIAGRAM

(PARALLEL SLAVE

PORT)

10.0 PARALLEL SLAVE PORT

Note: The Parallel Slave Port is only available on

PIC18F4X8 devices.

In addition to its function as a general I/O port, PORTD

can also operate as an 8-bit wide Parallel Slave Port

(PSP), or microprocessor port. PSP operation is con-

trolled by the 4 upper bits of the TRISE register

(Register 9-1). Setting control bit PSPMODE

(TRISE<4>) enables PSP operation. In Slave mode,

the port is asynchronously readable and writable by the

external world.

One bit of PORTD

Data Bus

D

Q

RDx pin

WR LATD

or

WR PORTD

CK

Data Latch

TTL

Q

D

The PSP can directly interface to an 8-bit microproces-

sor data bus. The external microprocessor can read or

write the PORTD latch as an 8-bit latch. Setting the

control bit PSPMODE enables the PORTE I/O pins to

become control inputs for the microprocessor port.

When set, port pin RE0 is the RD input, RE1 is the WR

input, and RE2 is the CS (chip select) input. For this

functionality, the corresponding data direction bits of

the TRISE register (TRISE<2:0>) must be configured

as inputs (set).

RD PORTD

RD LATD

EN

Set Interrupt Flag

PSPIF (PIR1<7>)

A write to the PSP occurs when both the CS and WR

lines are first detected low. A read from the PSP occurs

when both the CS and RD lines are first detected low.

The timing for the control signals in write and read

modes is shown in Figure 10-2 and Figure 10-3,

respectively.

PORTE pins

Read

RD

CS

WR

TTL

Chip Select

TTL

Write

TTL

Note:

I/O pins have diode protection to VDD and VSS.

FIGURE 10-2:

PARALLEL SLAVE PORT WRITE WAVEFORMS

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

CS

WR

RD

PORTD

IBF

OBF

PSPIF

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 105

PIC18FXX8

FIGURE 10-3:

PARALLEL SLAVE PORT READ WAVEFORMS

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

CS

WR

RD

PORTD

IBF

OBF

PSPIF

TABLE 10-1: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTD Port Data Latch when written; Port pins when read

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

---- -000 ---- -000

---- -xxx ---- -uuu

LATD

LATD Data Output bits

TRISD

PORTE

LATE

PORTD Data Direction bits

—

RE2

RE1

RE0

LATE Data Output bits

IBF OBF

TRISE

IBOV PSPMODE

PORTE Data Direction bits 0000 -111 0000 -111

RBIF 0000 000x 0000 000u

INTCON GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE TMR0IF INT0IF

PIR1

PIE1

IPR1

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

TXIE

TXIP

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.

DS41159B-page 106

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Register 11-1 shows the Timer0 Control register

(T0CON).

11.0 TIMER0 MODULE

The Timer0 module has the following features:

Figure 11-1 shows a simplified block diagram of the

Timer0 module in 8-bit mode and Figure 11-2 shows a

simplified block diagram of the Timer0 module in 16-bit

mode.

• Software selectable as an 8-bit or

16-bit timer/counter

• Readable and writable

• Dedicated 8-bit software programmable prescaler

• Clock source selectable to be external or internal

The T0CON register is a readable and writable register

that controls all the aspects of Timer0, including the

prescale selection.

• Interrupt-on-overflow from FFh to 00h in 8-bit

mode, and FFFFh to 0000h in 16-bit mode

Note: Timer0 is enabled on POR.

• Edge select for external clock

REGISTER 11-1: T0CON REGISTER

R/W-1

TMR0ON

bit 7

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

T0PS2

R/W-1

T0PS1

R/W-1

T0PS0

T08BIT

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

TMR0ON: Timer0 On/Off Control bit

1= Enables Timer0

0= Stops Timer0

T08BIT: Timer0 8-bit/16-bit Control bit

1= Timer0 is configured as an 8-bit timer/counter

0= Timer0 is configured as a 16-bit timer/counter

T0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (CLKO)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Timer0 Prescaler Assignment bit

1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.

0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.

bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits

111=1:256 prescale value

110=1:128 prescale value

101=1:64 prescale value

100=1:32 prescale value

011=1:16 prescale value

010=1:8 prescale value

001=1:4 prescale value

000=1:2 prescale value

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 107

PIC18FXX8

FIGURE 11-1:

TIMER0 BLOCK DIAGRAM IN 8-BIT MODE

Data Bus

8

1

0

RA4/T0CKI

pin⁽²⁾

1

T0SE

Sync with

Internal

Clocks

FOSC/4

TMR0L

Programmable

Prescaler

0

(2 TCY delay)

3

PSA

Set Interrupt

Flag bit TMR0IF

on Overflow

T0PS2, T0PS1, T0PS0

T0CS⁽¹⁾

Note 1: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

2: I/O pins have diode protection to VDD and VSS.

FIGURE 11-2:

TIMER0 BLOCK DIAGRAM IN 16-BIT MODE

T0CKI pin⁽²⁾

1

Sync with

T0SE

Set Interrupt

Flag bit TMR0IF

on Overflow

TMR0

High Byte

Internal

Clocks

0

TMR0L

FOSC/4

Programmable

Prescaler

0

8

(2 TCY delay)

3

Read TMR0L

Write TMR0L

T0PS2, T0PS1, T0PS0

T0CS⁽¹⁾

PSA

8

TMR0H

8

Data Bus<7:0>

Note 1: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

2: I/O pins have diode protection to VDD and VSS.

DS41159B-page 108

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

11.2.1

SWITCHING PRESCALER

ASSIGNMENT

11.1 Timer0 Operation

Timer0 can operate as a timer or as a counter.

The prescaler assignment is fully under software con-

trol (i.e., it can be changed “on-the-fly” during program

execution).

Timer mode is selected by clearing the T0CS bit. In

Timer mode, the Timer0 module will increment every

instruction cycle (without prescaler). If the TMR0L reg-

ister is written, the increment is inhibited for the follow-

ing two instruction cycles. The user can work around

this by writing an adjusted value to the TMR0L register.

11.3 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h in 8-bit mode, or FFFFh

to 0000h in 16-bit mode. This overflow sets the TMR0IF

bit. The interrupt can be masked by clearing the

TMR0IE bit. The TMR0IF bit must be cleared in soft-

ware by the Timer0 module Interrupt Service Routine

before re-enabling this interrupt. The TMR0 interrupt

cannot awaken the processor from SLEEP, since the

timer is shut-off during SLEEP.

Counter mode is selected by setting the T0CS bit. In

Counter mode, Timer0 will increment either on every

rising, or falling edge of pin RA4/T0CKI. The increment-

ing edge is determined by the Timer0 Source Edge

Select bit (T0SE). Clearing the T0SE bit selects the ris-

ing edge. Restrictions on the external clock input are

discussed below.

When an external clock input is used for Timer0, it must

meet certain requirements. The requirements ensure

the external clock can be synchronized with the internal

phase clock (TOSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

11.4 16-bit Mode Timer Reads and

Writes

Timer0 can be set in 16-bit mode by clearing T0CON

T08BIT. Registers TMR0H and TMR0L are used to

access 16-bit timer value.

11.2 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module. The prescaler is not readable or

writable.

TMR0H is not the high byte of the timer/counter in

16-bit mode, but is actually a buffered version of the

high byte of Timer0 (refer to Figure 11-1). The high byte

of the Timer0 counter/timer is not directly readable nor

writable. TMR0H is updated with the contents of the

high byte of Timer0 during a read of TMR0L. This pro-

vides the ability to read all 16 bits of Timer0 without

having to verify that the read of the high and low byte

were valid, due to a rollover between successive reads

of the high and low byte.

The PSA and T0PS2:T0PS0 bits determine the

prescaler assignment and prescale ratio.

Clearing bit PSA will assign the prescaler to the Timer0

module. When the prescaler is assigned to the Timer0

module, prescale values of 1:2, 1:4, ..., 1:256 are

selectable.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g. CLRF TMR0, MOVWF

TMR0, BSF TMR0, x.... etc.) will clear the prescaler

count.

A write to the high byte of Timer0 must also take place

through the TMR0H buffer register. Timer0 high byte is

updated with the contents of buffered value of TMR0H,

when a write occurs to TMR0L. This allows all 16 bits

of Timer0 to be updated at once.

Note: Writing to TMR0 when the prescaler is

assigned to Timer0, will clear the prescaler

count but will not change the prescaler

assignment.

TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

xxxx xxxx uuuu uuuu

TMR0L

TMR0H

Timer0 Module Low Byte Register

Timer0 Module High Byte Register

0000 0000 0000 0000

0000 000x 0000 000u

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

PSA

TMR0IF INT0IF

T0PS2 T0PS1

RBIF

T0CON

TRISA

TMR0ON

T08BIT

T0CS

T0SE

T0PS0 1111 1111 1111 1111

(1)

—

PORTA Data Direction Register

--11 1111 --11 1111

Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.

Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes,

they are disabled and read as ‘0’.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 109

PIC18FXX8

NOTES:

DS41159B-page 110

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Register 12-1 shows the Timer1 control register. This

register controls the Operating mode of the Timer1

module as well as contains the Timer1 oscillator enable

bit (T1OSCEN). Timer1 can be enabled/disabled by

setting/clearing control bit TMR1ON (T1CON register).

12.0 TIMER1 MODULE

The Timer1 module timer/counter has the following

features:

• 16-bit timer/counter

(Two 8-bit registers: TMR1H and TMR1L)

Figure 12-1 is a simplified block diagram of the Timer1

module.

• Readable and writable (both registers)

• Internal or external clock select

Note: Timer1 is disabled on POR.

• Interrupt-on-overflow from FFFFh to 0000h

• RESET from CCP module special event trigger

REGISTER 12-1: T1CON REGISTER

R/W-0

RD16

U-0

R/W-0

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 0

bit 7

RD16: 16-bit Read/Write Mode Enable bit

1= Enables register read/write of Timer1 in one 16-bit operation

0= Enables register read/write of Timer1 in two 8-bit operations

bit 6

Unimplemented: Read as '0'

bit 5-4

T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11=1:8 Prescale value

10=1:4 Prescale value

01=1:2 Prescale value

00=1:1 Prescale value

bit 3

bit 2

T1OSCEN: Timer1 Oscillator Enable bit

1= Timer1 oscillator is enabled

0= Timer1 oscillator is shut-off

The oscillator inverter and feedback resistor are turned off to eliminate power drain.

T1SYNC: Timer1 External Clock Input Synchronization Select bit

When TMR1CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1

TMR1CS: Timer1 Clock Source Select bit

1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)

0= Internal clock (FOSC/4)

bit 0

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 111

PIC18FXX8

When TMR1CS is clear, Timer1 increments every

instruction cycle. When TMR1CS is set, Timer1 incre-

ments on every rising edge of the external clock input

or the Timer1 oscillator, if enabled.

12.1 Timer1 Operation

Timer1 can operate in one of these modes:

• As a timer

• As a synchronous counter

• As an asynchronous counter

When the Timer1 oscillator is enabled (T1OSCEN is

set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins

become inputs. That is, the TRISC<1:0> value is

ignored.

The Operating mode is determined by the clock select

bit, TMR1CS (T1CON register).

Timer1 also has an internal “RESET input”. This

RESET can be generated by the CCP module

(Section 15.1).

FIGURE 12-1:

TIMER1 BLOCK DIAGRAM

CCP Special Event Trigger

TMR1IF

Overflow

Interrupt

Flag bit

Synchronized

TMR1

CLR

0

Clock Input

TMR1L

TMR1H

T1OSC

1

TMR1ON

On/Off

T1SYNC

1

T13CKI/T1OSO

T1OSI

Synchronize

det

T1OSCEN

Enable

Oscillator

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

(1)

0

2

SLEEP Input

T1CKPS1:T1CKPS0

TMR1CS

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.

FIGURE 12-2:

TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE

Data Bus<7:0>

8

TMR1H

8

Write TMR1L

Read TMR1L

Special Event Trigger

0

Synchronized

Clock Input

TMR1IF

Overflow

Interrupt

TMR1

8

Timer 1

high byte

TMR1L

Flag bit

1

TMR1ON

On/Off

T1SYNC

T1OSC

T13CKI/T1OSO

1

Synchronize

det

Prescaler

1, 2, 4, 8

T1OSCEN

Enable

Oscillator

FOSC/4

Internal

Clock

0

(1)

T1OSI

2

SLEEP Input

TMR1CS

T1CKPS1:T1CKPS0

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.

DS41159B-page 112

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

12.2 Timer1 Oscillator

12.4 Resetting Timer1 Using a CCP

Trigger Output

A crystal oscillator circuit is built-in between pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control bit T1OSCEN (T1CON register). The

oscillator is a low power oscillator rated up to 200 kHz.

It will continue to run during SLEEP. It is primarily

intended for a 32 kHz crystal. Table 12-1 shows the

capacitor selection for the Timer1 oscillator.

If the CCP module is configured in Compare mode to

generate a “special event trigger" (CCP1M3:CCP1M0 =

‘1011’), this signal will reset Timer1 and start an A/D

conversion (if the A/D module is enabled).

Note: The special event triggers from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR registers).

The user must provide a software time delay to ensure

proper start-up of the Timer1 oscillator.

Timer1 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this RESET operation may not work.

TABLE 12-1: CAPACITOR SELECTION FOR

THE ALTERNATE

OSCILLATOR

In the event that a write to Timer1 coincides with a special

event trigger from CCP1, the write will take precedence.

Osc Type

Freq

C1

C2

LP

32 kHz

TBD⁽¹⁾

In this mode of operation, the CCPR1H:CCPR1L registers

pair, effectively becomes the period register for Timer1.

Crystal to be Tested:

32.768 kHz Epson C-001R32.768K-A

20 PPM

12.5 Timer1 16-bit Read/Write Mode

Note 1: Microchip suggests 33 pF as a starting

Timer1 can be configured for 16-bit reads and writes

(see Figure 12-2). When the RD16 control bit (T1CON

register) is set, the address for TMR1H is mapped to a

buffer register for the high byte of Timer1. A read from

TMR1L will load the contents of the high byte of Timer1

into the Timer1 high byte buffer. This provides the user

with the ability to accurately read all 16 bits of Timer1,

without having to determine whether a read of the high

byte, followed by a read of the low byte is valid, due to

a rollover between reads.

point in validating the oscillator circuit.

2: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external components.

4: Capacitor values are for design guidance

A write to the high byte of Timer1 must also take place

through the TMR1H buffer register. Timer1 high byte is

updated with the contents of TMR1H when a write

occurs to TMR1L. This allows a user to write all 16 bits

to both the high and low bytes of Timer1 at once.

only.

12.3 Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The TMR1

Interrupt, if enabled, is generated on overflow, which is

latched in interrupt flag bit TMR1IF (PIR registers). This

interrupt can be enabled/disabled by setting/clearing

TMR1 interrupt enable bit TMR1IE (PIE registers).

The high byte of Timer1 is not directly readable or writ-

able in this mode. All reads and writes must take place

through the Timer1 high byte buffer register. Writes to

TMR1H do not clear the Timer1 prescaler. The

prescaler is only cleared on writes to TMR1L.

TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

PIR1

PIE1

IPR1

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

TXIE

TXIP

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

T1CON

RD16

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 113

PIC18FXX8

NOTES:

DS41159B-page 114

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

13.1 Timer2 Operation

13.0 TIMER2 MODULE

Timer2 can be used as the PWM time-base for the

PWM mode of the CCP module. The TMR2 register is

readable and writable, and is cleared on any device

RESET. The input clock (F^OSC/4) has a prescale option

of 1:1, 1:4, or 1:16, selected by control bits

T2CKPS1:T2CKPS0 (T2CON Register). The match

output of TMR2 goes through a 4-bit postscaler (which

gives a 1:1 to 1:16 scaling inclusive) to generate a

TMR2 interrupt (latched in flag bit TMR2IF, PIR

registers).

The Timer2 module timer has the following features:

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match of PR2

• SSP module optional use of TMR2 output to

generate clock shift

The prescaler and postscaler counters are cleared

when any of the following occurs:

Register 13-1 shows the Timer2 Control register.

Timer2 can be shut-off by clearing control bit TMR2ON

(T2CON register) to minimize power consumption.

Figure 13-1 is a simplified block diagram of the Timer2

module. The prescaler and postscaler selection of

Timer2 are controlled by this register.

• A write to the TMR2 register

• A write to the T2CON register

• Any device RESET (Power-on Reset, MCLR

Reset, Watchdog Timer Reset, or Brown-out

Reset)

TMR2 is not cleared when T2CON is written.

Note: Timer2 is disabled on POR.

REGISTER 13-1: T2CON REGISTER

U-0

R/W-0

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 0

bit 7

Unimplemented: Read as '0'

bit 6-3

TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000=1:1 Postscale

0001=1:2 Postscale

•

1111=1:16 Postscale

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0

T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 115

PIC18FXX8

13.2 Timer2 Interrupt

13.3 Output of TMR2

The Timer2 module has an 8-bit period register, PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

initialized to FFh upon RESET.

The output of TMR2 (before the postscaler) is a clock

input to the Synchronous Serial Port module, which

optionally uses it to generate the shift clock.

FIGURE 13-1:

TIMER2 BLOCK DIAGRAM

Sets Flag

TMR2

bit TMR2IF

(1)

Output

Prescaler

RESET

EQ

TMR2

FOSC/4

1:1, 1:4, 1:16

Postscaler

1:1 to 1:16

2

Comparator

T2CKPS1:T2CKPS0

4

PR2

TOUTPS3:TOUTPS0

Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.

TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

CCP1IF

CCP1IE

CCP1IP

INT0IF

TMR2IF

TMR2IE

TMR2IP

RBIF

0000 000x 0000 000u

PIR1

PIE1

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

TMR1IP 0000 0000 0000 0000

0000 0000 0000 0000

TXIE

TXIP

IPR1

TMR2

T2CON

PR2

Timer2 Module Register

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Timer2 Period Register 1111 1111 1111 1111

Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.

DS41159B-page 116

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Figure 14-1 is a simplified block diagram of the Timer3

module.

14.0 TIMER3 MODULE

The Timer3 module timer/counter has the following

features:

Register 14-1 shows the Timer3 Control Register. This

register controls the Operating mode of the Timer3

module and sets the CCP1 and ECCP1 clock source.

• 16-bit timer/counter

(Two 8-bit registers: TMR3H and TMR3L)

Register 12-1 shows the Timer1 Control register. This

register controls the Operating mode of the Timer1

module, as well as contains the Timer1 oscillator

enable bit (T1OSCEN), which can be a clock source for

Timer3.

• Readable and writable (both registers)

• Internal or external clock select

• Interrupt-on-overflow from FFFFh to 0000h

• RESET from CCP1/ECCP1 module trigger

Note: Timer3 is disabled on POR.

REGISTER 14-1: T3CON REGISTER

R/W-0

RD16

R/W-0

T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

bit 0

bit 7

RD16: 16-bit Read/Write Mode Enable bit

1= Enables register read/write of Timer3 in one 16-bit operation

0= Enables register read/write of Timer3 in two 8-bit operations

bit 6,3

T3ECCP1:T3CCP1: Timer3 and Timer1 to CCP1/ECCP1 Enable bits

1x=Timer3 is the clock source for compare/capture CCP1 and ECCP1 modules

01=Timer3 is the clock source for compare/capture of ECCP1,

Timer1 is the clock source for compare/capture of CCP1

00= Timer1 is the clock source for compare/capture CCP1 and ECCP1 modules

bit 5-4

bit 2

T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

T3SYNC: Timer3 External Clock Input Synchronization Control bit

(Not usable if the system clock comes from Timer1/Timer3)

When TMR3CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

When TMR3CS = 0:

This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

TMR3CS: Timer3 Clock Source Select bit

bit 1

1= External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling edge)

0= Internal clock (FOSC/4)

bit 0

TMR3ON: Timer3 On bit

1= Enables Timer3

0= Stops Timer3

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 117

PIC18FXX8

When TMR3CS = 0, Timer3 increments every instruc-

tion cycle. When TMR3CS = 1, Timer3 increments on

every rising edge of the Timer1 external clock input, or

the Timer1 oscillator, if enabled.

14.1 Timer3 Operation

Timer3 can operate in one of these modes:

• As a timer

• As a synchronous counter

• As an asynchronous counter

When the Timer1 oscillator is enabled (T1OSCEN is set),

the RC1/T1OSI and RC0/T1OSO/T1CKI pins become

inputs. That is, the TRISC<1:0> value is ignored.

The Operating mode is determined by the clock select

bit, TMR3CS (T3CON register).

Timer3 also has an internal “RESET input”. This

RESET can be generated by the CCP module

(Section 15.1).

FIGURE 14-1:

TIMER3 BLOCK DIAGRAM

CCP Special Trigger

TMR3IF

Overflow

Interrupt

T3CCPx

Synchronized

0

Clock Input

Flag bit

CLR

TMR3L

TMR3H

T1OSC

1

TMR3ON

On/Off

T3SYNC

T1OSO/

T13CKI

1

Synchronize

det

Prescaler

1, 2, 4, 8

T1OSCEN

Enable

Oscillator

FOSC/4

Internal

Clock

0

(1)

T1OSI

2

SLEEP Input

TMR3CS

T3CKPS1:T3CKPS0

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

FIGURE 14-2:

TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE

Data Bus<7:0>

8

TMR3H

8

Write TMR3L

Read TMR3L

CCP Special Trigger

T3CCPx

0

Synchronized

Clock Input

8

TMR3

TMR3IF Overflow

Interrupt Flag

bit

CLR

TMR3H

TMR3L

1

To Timer1 Clock Input

TMR3ON

On/Off

T3SYNC

T1OSC

T1OSO/

T13CKI

1

Synchronize

det

Prescaler

1, 2, 4, 8

T1OSCEN

Enable

FOSC/4

Internal

Clock

0

(1)

Oscillator

T1OSI

2

SLEEP Input

T3CKPS1:T3CKPS0

TMR3CS

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

DS41159B-page 118

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

14.2 Timer1 Oscillator

14.4 Resetting Timer3 Using a CCP

Trigger Output

The Timer1 oscillator may be used as the clock source

for Timer3. The Timer1 oscillator is enabled by setting

the T1OSCEN bit (T1CON Register). The oscillator is a

low power oscillator rated up to 200 kHz. Refer to

Section 12.0, Timer1 Module for Timer1 oscillator

details.

If the CCP module is configured in Compare mode to

generate a “special event trigger" (CCP1M3:CCP1M0

= 1011), this signal will reset Timer3.

Note: The special event triggers from the CCP

module will not set interrupt flag bit

TMR3IF (PIR registers).

14.3 Timer3 Interrupt

Timer3 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature. If

Timer3 is running in Asynchronous Counter mode, this

RESET operation may not work. In the event that a write

to Timer3 coincides with a special event trigger from

CCP1, the write will take precedence. In this mode of

operation, the CCPR1H:CCPR1L registers pair

becomes the period register for Timer3. Refer to

Section 15.0, “Capture/Compare/PWM (CCP) Modules

for CCP details.

The TMR3 Register pair (TMR3H:TMR3L) increments

from 0000h to FFFFh and rolls over to 0000h. The TMR3

Interrupt, if enabled, is generated on overflow, which is

latched in interrupt flag bit TMR3IF (PIR registers). This

interrupt can be enabled/disabled by setting/clearing

TMR3 interrupt enable bit TMR3IE (PIE registers).

TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Value on

POR,

BOR

Value on

all other

RESETS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR2

GIE/ GIEH PEIE/GIEL TMR0IE

INT0IE

EEIF

RBIE

BCLIF

BCLIE

BCLIP

TMR0IF

LVDIF

LVDIE

LVDIP

INT0IF

RBIF

0000 000x 0000 000u

—

CMIF

CMIE

CMIP

—

TMR3IF ECCP1IF -0-0 0000 -0-0 0000

TMR3IE ECCP1IE -0-0 0000 -0-0 0000

TMR3IP ECCP1IP -0-0 0000 -0-0 0000

xxxx xxxx uuuu uuuu

PIE2

EEIE

EEIP

IPR2

TMR3L

TMR3H

T1CON

T3CON

Holding Register for the Least Significant Byte of the 16-bit TMR3 Register

Holding Register for the Most Significant Byte of the 16-bit TMR3 Register

xxxx xxxx uuuu uuuu

RD16

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 119

PIC18FXX8

NOTES:

DS41159B-page 120

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

received time stamp for the CAN module (refer to

Section 19.0, CAN Module for CAN operation), which

the ECCP module does not. The ECCP module, on the

other hand, has enhanced PWM functionality and auto

shutdown capability. Aside from these, the operation of

the module described in the this section is the same as

the ECCP .

15.0 CAPTURE/COMPARE/PWM

(CCP) MODULES

The CCP (Capture/Compare/PWM) module contains a

16-bit register that can operate as a 16-bit capture reg-

ister, as a 16-bit compare register, or as a PWM Duty

Cycle register.

The control register for the CCP module is shown in

Register 15-1. Table 15-2 (following page) details the

interactions of the CCP and ECCP modules.

The operation of the CCP module is identical to that of

the ECCP module (discussed in detail in Section 16.0),

with two exceptions. The CCP module has a Capture

special event trigger that can be used as a message

REGISTER 15-1: CCP1CON REGISTER

U-0

R/W-0

—

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 0

bit 7

Unimplemented: Read as '0'

bit 7-6

bit 5-4

DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits

(DCx9:DCx2) of the duty cycle are found in CCPRxL.

bit 3-0

CCPxM3:CCPxM0: CCPx Mode Select bits

0000= Capture/Compare/PWM off (resets CCPx module)

0001= Reserved

0010= Compare mode, toggle output on match (CCPxIF bit is set)

0011= Capture mode, CAN message received (CCP1 only)

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode, initialize CCP pin Low, on compare match force CCP pin High

(CCPIF bit is set)

1001= Compare mode, initialize CCP pin High, on compare match force CCP pin Low

(CCPIF bit is set)

1010= Compare mode, CCP pin is unaffected

(CCPIF bit is set)

1011= Compare mode, trigger special event (CCP1IF bit is set; CCP resets TMR1 or TMR3

and starts an A/D conversion, if the A/D module is enabled)

11xx= PWM mode

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 121

PIC18FXX8

An event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the inter-

rupt request flag bit CCP1IF (PIR registers) is set. It

must be cleared in software. If another capture occurs

before the value in register CCPR1 is read, the old

captured value will be lost.

15.1 CCP1 Module

Capture/Compare/PWM Register1 (CCPR1) is com-

prised of two 8-bit registers: CCPR1L (low byte) and

CCPR1H (high byte). The CCP1CON register controls

the operation of CCP1. All are readable and writable.

Table 15-1 shows the timer resources of the CCP

module modes.

15.2.1

CCP PIN CONFIGURATION

In Capture mode, the RC2/CCP1 pin should be

configured as an input by setting the TRISC<2> bit.

TABLE 15-1: CCP1 MODE - TIMER

RESOURCE

Note: If the RC2/CCP1 is configured as an out-

put, a write to the port can cause a capture

condition.

CCP1 Mode

Timer Resource

Capture

Compare

PWM

Timer1 or Timer3

Timer2

15.2.2

TIMER1/TIMER3 MODE SELECTION

The timers used with the capture feature (either Timer1

and/or Timer3) must be running in Timer mode or Syn-

chronized Counter mode. In Asynchronous Counter

mode, the capture operation may not work. The timer

used with each CCP module is selected in the T3CON

register.

15.2 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 or TMR3 register when an

event occurs on pin RC2/CCP1. An event is defined as:

• every falling edge

• every rising edge.

• every 4th rising edge

• every 16th rising edge

TABLE 15-2: INTERACTION OF CCP1 AND ECCP1 MODULES

CCP1

Mode

ECCP1

Mode

Interaction

Capture

TMR1 or TMR3 time-base. Time-base can be different for each CCP.

Compare

The compare could be configured for the special event trigger, which clears either TMR1

or TMR3, depending upon which time-base is used.

Compare

The compare(s) could be configured for the special event trigger, which clears TMR1 or

TMR3, depending upon which time-base is used.

PWM

The PWMs will have the same frequency and update rate (TMR2 interrupt).

Capture

Compare

None.

DS41159B-page 122

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

15.2.3

SOFTWARE INTERRUPT

15.2.5

CAN MESSAGE TIME-STAMP

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE registers) clear to avoid false interrupts

and should clear the flag bit CCP1IF, following any

such change in Operating mode.

The CAN capture event occurs when a message is

received in either of the receive buffers. The CAN mod-

ule provides a rising edge to the CCP1 module to

cause a capture event. This feature is provided to

time-stamp the received CAN messages.

This feature is enabled by setting the CANCAP bit of

the CAN I/O control register (CIOCON<4>). The mes-

sage receive signal from the CAN module then takes

the place of the events on RC2/CCP1.

15.2.4

CCP1 PRESCALER

There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP1 module is

turned off, or the CCP1 module is not in Capture mode,

the prescaler counter is cleared. This means that any

RESET will clear the prescaler counter.

EXAMPLE 15-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF

MOVLW

CCP1CON, F

NEW_CAPT_PS

; Turn CCP module off

; Load WREG with the

; new prescaler mode

; value and CCP ON

; Load CCP1CON with

; this value

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared; therefore, the first capture may be from

a non-zero prescaler. Example 15-1 shows the recom-

mended method for switching between capture pres-

calers. This example also clears the prescaler counter

and will not generate the “false” interrupt.

MOVWF

CCP1CON

FIGURE 15-1:

CAPTURE MODE OPERATION BLOCK DIAGRAM

Set Flag bit CCP1IF

(PIR1<2>)

TMR3H

TMR3L

CCPR1L

TMR1L

T3CCP1

T3ECCP1

TMR3

Enable

Prescaler

÷ 1, 4, 16

CCP1 pin

CCPR1H

TMR1

and

Enable

Edge Detect

T3ECCP1

T3CCP1

TMR1H

CCP1CON<3:0>

Qs

Note: I/O pins have diode protection to VDD and VSS.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 123

PIC18FXX8

15.3.2

TIMER1/TIMER3 MODE SELECTION

15.3 Compare Mode

Timer1 and/or Timer3 must be running in Timer mode,

or Synchronized Counter mode, if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

In Compare mode, the 16-bit CCPR1 and ECCPR1

register value is constantly compared against either the

TMR1 register pair value, or the TMR3 register pair

value. When a match occurs, the CCP1 pin can have

one of the following actions:

15.3.3

SOFTWARE INTERRUPT MODE

• Driven high

When Generate Software Interrupt is chosen, the

CCP1 pin is not affected. Only a CCP interrupt is

generated (if enabled).

• Driven low

• Toggle output (high to low or low to high)

• Remains unchanged

15.3.4

SPECIAL EVENT TRIGGER

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0. At the same time, interrupt flag

bit CCP1IF is set.

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action.

15.3.1

CCP1 PIN CONFIGURATION

The special event trigger output of CCP1 resets either

the TMR1 or TMR3 register pair. Additionally, the

ECCP1 Special Event Trigger will start an A/D

conversion, if the A/D module is enabled.

The user must configure the CCP1 pin as an output by

clearing the appropriate TRISC bit.

Note: Clearing the CCP1CON register will force

the CCP1 compare output latch to the

default low level. This is not the data latch.

Note: The Special Event Trigger from the ECCP1

module will not set the Timer1 or Timer3

interrupt flag bits.

FIGURE 15-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

Special Event Trigger will:

Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit)

Set bit GO/DONE, which starts an A/D conversion (ECCP1 only)

TMR3H TMR3L

TMR1H TMR1L

Special Event Trigger

Set Flag bit CCP1IF

(PIR1<2>)

T3CCP1

T3ECCP1

0

1

Q

S

R

Output

Logic

Comparator

Match

CCP1

Output Enable

CCPR1H

CCPR1L

CCP1CON<3:0>

Mode Select

Note: I/O pins have diode protection to VDD and VSS.

DS41159B-page 124

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

RESETS

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

PIR1

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

SSPIF

SSPIE

SSPIP

CCP1IF

CCP1IE

CCP1IP

TMR2IF

TMR2IE

TMR2IP

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

TMR1IP 0000 0000 0000 0000

1111 1111 1111 1111

PIE1

IPR1

TRISD

TMR1L

TMR1H

T1CON

CCPR1L

CCPR1H

CCP1CON

PIR2

PORTD Data Direction Register

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

RD16

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

Capture/Compare/PWM Register1 (LSB)

Capture/Compare/PWM Register1 (MSB)

xxxx xxxx uuuu uuuu

—

DC1B1

—

DC1B0

EEIF

CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

CMIF

CMIE

CMIP

BCLIF

BCLIE

BCLIP

LVDIF

LVDIE

LVDIP

TMR3IF ECCP1IF -0-0 0000 -0-0 0000

TMR3IE ECCP1IE -0-0 0000 -0-0 0000

TMR3IP ECCP1IP -0-0 0000 -0-0 0000

PIE2

—

EEIE

EEIP

IPR2

—

TMR3L

TMR3H

T3CON

Holding Register for the Least Significant Byte of the 16-bit TMR3 Register

Holding Register for the Most Significant Byte of the 16-bit TMR3 Register

xxxx xxxx uuuu uuuu

RD16

T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1

T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 125

PIC18FXX8

15.4.1

PWM PERIOD

15.4 PWM Mode

The PWM period is specified by writing to the PR2 reg-

ister. The PWM period can be calculated using the

following formula.

In Pulse Width Modulation (PWM) mode, the CCP1 pin

produces up to a 10-bit resolution PWM output. Since

the CCP1 pin is multiplexed with the PORTC data latch,

the TRISC<2> bit must be cleared to make the CCP1

pin an output.

EQUATION 15-1:

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTC I/O data

latch.

PWM period = [(PR2) + 1] • 4 • TOSC •

(TMR2 prescale value)

PWM frequency is defined as 1 / [PWM period].

Figure 15-3 shows a simplified block diagram of the

CCP module in PWM mode.

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 15.4.3.

• TMR2 is cleared

• The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

FIGURE 15-3:

SIMPLIFIED PWM BLOCK

DIAGRAM

• The PWM duty cycle is latched from CCPR1L into

CCPR1H

CCP1CON<5:4>

Note: The Timer2 postscaler (see Section 13.0)

is not used in the determination of the

PWM frequency. The postscaler could be

used to have a servo update rate at a

different frequency than the PWM output.

Duty Cycle Registers

CCPR1L (Master)

CCPR1H (Slave)

Comparator

15.4.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time.

Q

R

S

RC2/CCP1

(Note 1)

TMR2

TRISC<2>

Comparator

PR2

Clear Timer,

Set CCP1 pin and

latch D.C.

EQUATION 15-2:

PWM duty cycle =(CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 prescale value)

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock,

or 2 bits of the prescaler, to create 10-bit time-base.

A PWM output (Figure 15-4) has a time-base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read only register.

FIGURE 15-4:

PWM OUTPUT

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

Period

When the CCPR1H and 2-bit latch match TMR2, con-

catenated with an internal 2-bit Q clock, or 2 bits of the

TMR2 prescaler, the CCP1 pin is cleared.

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

DS41159B-page 126

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

The maximum PWM resolution (bits) for a given PWM

frequency is given by the following equation.

15.4.3

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

EQUATION 15-3:

1. Set the PWM period by writing to the PR2

register.





^FOSC

---------------

log

_FPWM

PWM Resolution (max)

= ----------------------------- b i t s

2. Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

log(2)

3. Make the CCP1 pin an output by clearing the

TRISC<2> bit.

4. Set the TMR2 prescale value and enable Timer2

by writing to T2CON.

Note: If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

5. Configure the CCP1 module for PWM operation.

TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency

2.44 kHz 9.76 kHz 39.06 kHz 156.3 kHz 312.5 kHz 416.6 kHz

Timer Prescaler (1, 4, 16)

PR2 Value

16

FFh

10

4

1

3Fh

8

1

1Fh

7

1

FFh

10

FFh

10

17h

5.5

Maximum Resolution (bits)

TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

PIR1

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

SSPIF

SSPIE

SSPIP

CCP1IF

CCP1IE

CCP1IP

TMR2IF

TMR2IE

TMR2IP

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

TMR1IP 0000 0000 0000 0000

1111 1111 1111 1111

PIE1

IPR1

TRISD

TMR2

PORTD Data Direction Register

Timer2 Module Register

0000 0000 0000 0000

PR2

Timer2 Module Period Register

1111 1111 1111 1111

T2CON

CCPR1L

CCPR1H

CCP1CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Capture/Compare/PWM Register1 (LSB)

Capture/Compare/PWM Register1 (MSB)

xxxx xxxx uuuu uuuu

—

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 127

PIC18FXX8

NOTES:

DS41159B-page 128

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

The operation of the ECCP module differs from the

CCP (discussed in detail in Section 15.0) with the addi-

tion of an enhanced PWM module, which allows for up

to 4 output channels and user selectable polarity.

These features are discussed in detail in Section 16.5.

The module can also be programmed for automatic

shutdown in response to various analog or digital

events.

16.0 ENHANCED CAPTURE/

COMPARE/PWM (ECCP)

MODULE

Note: The ECCP (Enhanced Capture/Compare/

PWM) module is only available on

PIC18F448 and PIC18F458 devices.

This module contains a 16-bit register which can oper-

ate as a 16-bit Capture register, a 16-bit Compare

register, or a PWM Master/Slave Duty Cycle register.

The control register for ECCP1 is shown in

Register 16-1.

REGISTER 16-1: ECCP1CON REGISTER

R/W-0

EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0

bit 7

bit 0

bit 7-6

EPWM1M<1:0>: PWM Output Configuration bits

If ECCP1M<3:2> = 00, 01, 10:

xx= P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins

If ECCP1M<3:2> = 11:

00= Single output; P1A modulated; P1B, P1C, P1D assigned as port pins

01= Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive

10= Half-bridge output; P1A, P1B modulated with deadband control; P1C, P1D assigned as

port pins

11= Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive

bit 5-4

EDC1B<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in ECCPR1L.

bit 3-0

ECCP1M<3:0>: ECCP1 Mode Select bits

0000=Capture/Compare/PWM off (resets ECCP module)

0001=Unused (reserved)

0010=Compare mode, toggle output on match (ECCP1IF bit is set)

0011=Unused (reserved)

0100=Capture mode, every falling edge

0101=Capture mode, every rising edge

0110=Capture mode, every 4th rising edge

0111=Capture mode, every 16th rising edge

1000=Compare mode, set output on match (ECCP1IF bit is set)

1001=Compare mode, clear output on match (ECCP1IF bit is set)

1010=Compare mode, ECCP1 pin is unaffected (ECCP1IF bit is set)

1011=Compare mode, trigger special event (ECCP1IF bit is set; ECCP resets TMR1or TMR3,

and starts an A/D conversion, if the A/D module is enabled)

1100=PWM mode; P1A, P1C active high; P1B, P1D active high

1101=PWM mode; P1A, P1C active high; P1B, P1D active low

1110=PWM mode; P1A, P1C active low; P1B, P1D active high

1111=PWM mode; P1A, P1C active low; P1B, P1D active low

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 129

PIC18FXX8

In PWM mode, the ECCP module can have up to four

available outputs, depending on which Operating mode

is selected. These outputs are multiplexed with PORTD

and the Parallel Slave Port. Both the Operating mode

and the output pin assignments are configured by setting

PWM Output Configuration bits EPWM1M1:EPWM1M0

(ECCP1CON<7:6>). The specific pin assignments for

the various Output modes are shown in Table 16-3.

16.1 ECCP1 Module

Enhanced Capture/Compare/PWM Register1 (ECCPR1)

is comprised of two 8-bit registers: ECCPR1L (low

byte) and ECCPR1H (high byte). The ECCP1CON reg-

ister controls the operation of ECCP1; the additional

registers, ECCPAS and ECCP1DEL, control enhanced

PWM specific features. All registers are readable and

writable.

Table 16-1 shows the timer resources for the ECCP

module modes. Table 16-2 describes the interactions

of the ECCP module with the standard CCP module.

TABLE 16-1: ECCP1 MODE - TIMER

RESOURCE

ECCP1 Mode

Timer Resource

Capture

Compare

PWM

Timer1 or Timer3

Timer2

TABLE 16-2: INTERACTION OF CCP1 AND ECCP1 MODULES

ECCP1 Mode CCP1 Mode

Interaction

TMR1 or TMR3 time-base. Time-base can be different for each CCP.

Capture

Compare

The compare could be configured for the special event trigger, which clears either

TMR1 or TMR3, depending upon which time-base is used.

Compare

The compare(s) could be configured for the special event trigger, which clears TMR1

or TMR3 depending upon which time-base is used.

PWM

The PWMs will have the same frequency and update rate (TMR2 interrupt).

Capture

Compare

None

TABLE 16-3: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES

ECCP1CON

ECCP Mode⁽¹⁾

RD4

RD5

RD6

RD7

Configuration

Conventional CCP Compatible

00xx11xx

ECCP1

RD<5>,

PSP<5>

RD<6>,

PSP<6>

RD<7>,

PSP<7>

Dual Output PWM⁽²⁾

Quad Output PWM⁽²⁾

10xx11xx

x1xx11xx

P1A

P1B

RD<6>,

PSP<6>

RD<7>,

PSP<7>

P1B

P1C

P1D

Legend: x= Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.

Note 1: In all cases, the appropriate TRISD bits must be cleared to make the corresponding pin an output.

2: In these modes, the PSP I/O control for PORTD is overridden by P1B, P1C and P1D.

DS41159B-page 130

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

16.2 Capture Mode

16.3 Compare Mode

The Capture Mode of the ECCP module is virtually

identical in operation to that of the standard CCP mod-

ule, as discussed in Section 15.1. The differences are

in the registers and port pins involved:

The Compare Mode of the ECCP module is virtually

identical in operation to that of the standard CCP mod-

ule, as discussed in Section 15.2. The differences are

in the registers and port pins, as described in

Section 16.2. All other details are exactly the same.

• The 16-bit Capture register is ECCPR1 (ECCPR1H

and ECCPR1L);

16.3.1

SPECIAL EVENT TRIGGER

• The capture event is selected by control bits

Except as noted below, the special event trigger output

of ECCP1 functions identically to that of the standard

CCP module. It may be used to start an A/D conversion

if the A/D module is enabled.

ECCP1M3:ECCP1M0 (ECCP1CON<3:0>);

• The interrupt bits are ECCP1IE (PIE2<0>) and

ECCP1IF (PIR2<0>); and

• The capture input pin is RD4, and its corresponding

direction control bit is TRISD<4>.

Note: The special Event trigger from the ECCP1

module will not set the Timer1 or Timer3

interrupt flag bits.

Other operational details, including timer selection, out-

put pin configuration and software interrupts, are

exactly the same as the standard CCP module.

16.2.1

CAN MESSAGE TIME-STAMP

The special capture event for the reception of CAN

messages (Section 15.2.5) is not available with the

ECCP module.

TABLE 16-4: REGISTERS ASSOCIATED WITH ENHANCED CAPTURE, COMPARE, TIMER1 AND

TIMER3

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR2

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

EEIF

RBIE

BCLIF

BCLIE

BCLIP

TMR0IF

LVDIF

LVDIE

LVDIP

INT0IF

RBIF

0000 000x 0000 000u

—

CMIF

CMIE

CMIP

—

TMR3IF ECCP1IF -0-0 0000 -0-0 0000

TMR3IE ECCP1IE -0-0 0000 -0-0 0000

TMR3IP ECCP1IP -0-0 1111 -1-1 1111

xxxx xxxx uuuu uuuu

PIE2

EEIE

EEIP

IPR2

TMR1L

TMR1H

T1CON

TMR3L

TMR3H

T3CON

TRISD

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

RD16

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

Holding Register for the Least Significant Byte of the 16-bit TMR3 Register

Holding Register for the Most Significant Byte of the 16-bit TMR3 Register

xxxx xxxx uuuu uuuu

RD16

T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

PORTD Data Direction Register

1111 1111 1111 1111

xxxx xxxx uuuu uuuu

ECCPR1L Capture/Compare/PWM Register1 (LSB)

ECCPR1H Capture/Compare/PWM Register1 (MSB)

ECCP1CON EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 0000 0000

Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the ECCP module and Timer1.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 131

PIC18FXX8

Figure 16-1 shows a simplified block diagram of PWM

operation. All control registers are double-buffered and

are loaded at the beginning of a new PWM cycle (the

period boundary when the assigned timer resets), in

order to prevent glitches on any of the outputs. The

exception is the PWM delay register ECCP1DEL,

which is loaded at either the duty cycle boundary or the

boundary period (whichever comes first). Because of

the buffering, the module waits until the assigned timer

resets, instead of starting immediately. This means that

enhanced PWM waveforms do not exactly match the

standard PWM waveforms, but are instead offset by

one full instruction cycle (4 TOSC).

16.4 Standard PWM Mode

When configured in Single Output mode, the ECCP

module functions identically to the standard CCP mod-

ule in PWM mode, as described in Section 15.4. The

differences in registers and ports are as described in

Section 16.2; in addition, the two Least Significant bits

of the 10-bit PWM duty cycle value are represented by

ECCP1CON<5:4>.

Note: When setting up single output PWM opera-

tions, users are free to use either of the pro-

cesses described in Section 15.4.3 or

Section 16.5.8. The latter is more generic,

but will work for either single or multi-output

PWM.

As before, the user must manually configure the appro-

priate TRISD bits for output.

16.5 Enhanced PWM Mode

16.5.1

PWM OUTPUT CONFIGURATIONS

The Enhanced PWM mode provides additional PWM

output options for a broader range of control applica-

tions. The module is an upwardly compatible version of

the standard CCP module and is modified to provide up

to four outputs, designated P1A through P1D. Users

are also able to select the polarity of the signal (either

active high or active low). The module’s Output mode

and polarity are configured by setting the

EPWM1M1:EPWM1M0 and ECCP1M3:ECCP1M0 bits

of the ECCP1CON register (ECCP1CON<7:6> and

ECCP1CON<3:0>, respectively).

The EPWM1M<1:0> bits in the ECCP1CON register

allow one of four configurations:

• Single Output

• Half-Bridge Output

• Full-Bridge Output, Forward mode

• Full-Bridge Output, Reverse mode

The Single Output mode is the Standard PWM mode

discussed in Section 15.4. The Half-Bridge and Full-

Bridge Output modes are covered in detail in the

sections that follow.

The general relationship of the outputs in all

configurations is summarized in Figure 16-2.

FIGURE 16-1:

SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE

ECCP1CON<5:4>

EPWM1M1<1:0>

ECCP1M<3:0>

4

Duty Cycle Registers

2

ECCPR1L

ECCP1/P1A

RD4/PSP4/ECCP1/P1A

TRISD<4>

TRISD<5>

TRISD<6>

TRISD<7>

ECCPR1H (Slave)

Comparator

P1B

RD5/PSP5/P1B

RD6/PSP6/P1C

Output

R

S

Q

Controller

P1C

(Note 1)

TMR2

P1D

RD7/PSP7/P1D

Comparator

PR2

Clear Timer,

set ECCP1 pin and

latch D.C.

ECCP1DEL

Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time-base.

DS41159B-page 132

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 16-2:

PWM OUTPUT RELATIONSHIPS

0

PR2+1

DUTY

CYCLE

SIGNAL

ECCP1CON

<7:6>

PERIOD

P1A Modulated, Active High

P1A Modulated, Active Low

P1A Modulated, Active High

P1A Modulated, Active Low

P1B Modulated, Active High

P1B Modulated, Active Low

P1A Active, Active High

00

Delay

10

Delay

P1A Active, Active Low

P1B Inactive, Active High

P1B Inactive, Active Low

P1C Inactive, Active High

P1C Inactive, Active Low

P1D Modulated, Active High

P1D Modulated, Active Low

P1A Inactive, Active High

P1A Inactive, Active Low

P1B Modulated, Active High

P1B Modulated, Active Low

P1C Active, Active High

P1C Active, Active Low

01

11

P1D Inactive, Active High

P1D Inactive, Active Low

Relationships:

• Period = 4 * TOSC * (PR2 + 1) * (TMR2 prescale value)

• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 prescale value)

• Delay = 4 * TOSC * ECCP1DEL

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 133

PIC18FXX8

16.5.2

HALF-BRIDGE MODE

FIGURE 16-3:

HALF-BRIDGE PWM

OUTPUT

In the Half-Bridge Output mode, two pins are used as

outputs to drive push-pull loads. The RD4/PSP4/

ECCP1/P1A pin has the PWM output signal, while the

RD5/PSP5/P1B pin has the complementary PWM out-

put signal (Figure 16-3). This mode can be used for

half-bridge applications, as shown in Figure 16-4, or for

full-bridge applications, where four power switches are

being modulated with two PWM signals.

Period

Duty Cycle

(2)

P1A

td

P1B

In Half-Bridge Output mode, the programmable dead-

band delay can be used to prevent shoot-through

current in bridge power devices. The value of register

ECCP1DEL dictates the number of clock cycles before

the output is driven active. If the value is greater than

the duty cycle, the corresponding output remains inac-

tive during the entire cycle. See Section 16.5.4 for

more details of the deadband delay operations.

(1)

td = Deadband Delay

Note 1: At this time, the TMR2 register is equal to the

PR2 register.

2: Output signals are shown as asserted high.

Since the P1A and P1B outputs are multiplexed with

the PORTD<4> and PORTD<5> data latches, the

TRISD<4> and TRISD<5> bits must be cleared to

configure P1A and P1B as outputs.

FIGURE 16-4:

EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS

V+

Standard Half-Bridge Circuit (“Push-Pull”)

PIC18F448/458

FET

Driver

+

V

-

P1A

+

-

Load

FET

Driver

+

V

-

P1B

V-

Half-Bridge Output Driving a Full-Bridge Circuit

V+

PIC18F448/458

FET

Driver

P1A

+

-

Load

FET

Driver

FET

Driver

P1B

V-

DS41159B-page 134

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

P1A, P1B, P1C and P1D outputs are multiplexed with

the PORTD<4:7> data latches. The TRISD<4:7> bits

must be cleared to make the P1A, P1B, P1C, and P1D

pins output.

16.5.3

FULL-BRIDGE MODE

In Full-Bridge Output mode, four pins are used as out-

puts; however, only two outputs are active at a time. In

the Forward mode, pin RD4/PSP4/ECCP1/P1A is con-

tinuously active, and pin RD7/PSP7/P1D is modulated.

In the Reverse mode, RD6/PSP6/P1C pin is continu-

ously active, and RD5/PSP5/P1B pin is modulated.

These are illustrated in Figure 16-5.

FIGURE 16-5:

FULL-BRIDGE PWM OUTPUT

FORWARD MODE

Period

(2)

P1A

P1B

P1C

Duty Cycle

(2)

P1D

(1)

REVERSE MODE

Period

Duty Cycle

(2)

P1A

(2)

P1B

(2)

P1C

(2)

P1D

(1)

Note 1: At this time, the TMR2 register is equal to the PR2 register.

Note 2: Output signal is shown as asserted high.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 135

PIC18FXX8

FIGURE 16-6:

EXAMPLE OF FULL-BRIDGE APPLICATION

V+

PIC18F448/458

QB

QD

FET

Driver

FET

Driver

P1D

+

-

Load

P1C

FET

Driver

FET

Driver

P1B

P1A

QA

QC

V-

Figure 16-8 shows an example where the PWM direc-

tion changes from forward to reverse, at a near 100%

duty cycle. At time t1, the output P1A and P1D become

inactive, while output P1C becomes active. In this

example, since the turn off time of the power devices is

longer than the turn on time, a shoot-through current

flows through power devices QB and QD (see

Figure 16-6) for the duration of ‘t’. The same phenom-

enon will occur to power devices QA and QC for PWM

direction change from reverse to forward.

16.5.3.1

Direction Change in Full-Bridge

Mode

In the Full-Bridge Output mode, the EPWM1M1 bit in

the ECCP1CON register allows user to control the

Forward/Reverse direction. When the application firm-

ware changes this direction control bit, the ECCP1

module will assume the new direction on the next PWM

cycle. The current PWM cycle still continues, however,

the non-modulated outputs, P1A and P1C signals, will

transition to the new direction TOSC, 4 TOSC or 16 TOSC

earlier (for T2CKRS<1:0> = 00, 01or 1x, respectively),

before the end of the period. During this transition

cycle, the modulated outputs, P1B and P1D, will go to

the inactive state (Figure 16-7).

If changing PWM direction at high duty cycle is required

for an application, one of the following requirements

must be met:

1. Avoid changing PWM output direction at or near

100% duty cycle.

Note that in the Full-Bridge Output mode, the ECCP

module does not provide any deadband delay. In gen-

eral, since only one output is modulated at all times,

deadband delay is not required. However, there is a sit-

uation where a deadband delay might be required. This

situation occurs when all of the following conditions are

true:

2. Use switch drivers that compensate the slow

turn off of the power devices. The total turn off

time (t_off) of the power device and the driver

must be less than the turn on time (t_on).

1. The direction of the PWM output changes when

the duty cycle of the output is at or near 100%.

2. The turn off time of the power switch, including

the power device and driver circuit, is greater

than turn on time.

DS41159B-page 136

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 16-7:

PWM DIRECTION CHANGE

(1)

PERIOD

SIGNAL

DC

P1A (Active High)

P1B (Active High)

P1C (Active High)

P1D (Active High)

(2)

Note 1: The direction bit in the ECCP1 Control Register (ECCP1CON.EPWM1M1) is written any time during the PWM

cycle.

2: The P1A and P1C signals switch at intervals of TOSC, 4 TOSC or 16 TOSC, depending on the Timer2 prescaler value

earlier when changing direction. The modulated P1B and P1D signals are inactive at this time.

FIGURE 16-8:

PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

FORWARD PERIOD

REVERSE PERIOD

P1A

P1B

(PWM)

P1C

P1D

(PWM)

t

on

External Switch C

External Switch D

t

off

Potential

t = t – t

off

on

Shoot-Through

Current

t1

Note 1: All signals are shown as active high.

2: t is the Turn-on Delay of power switch and driver.

on

3: t is the Turn-off Delay of power switch and driver.

off

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 137

PIC18FXX8

devices in the off state, until the microcontroller drives

the I/O pins with the proper signal levels, or activates

the PWM output(s).

16.5.4

PROGRAMMABLE DEADBAND

DELAY

In half-bridge or full-bridge applications, where all

power switches are modulated at the PWM frequency

at all times, the power switches normally require longer

time to turn off than to turn on. If both the upper and

lower power switches are switched at the same time

(one turned on, and the other turned off), both switches

will be on for a short period of time until one switch

completely turns off. During this time, a very high cur-

rent (shoot-through current) flows through both power

switches, shorting the bridge supply. To avoid this

potentially destructive shoot-through current from flow-

ing during switching, turning on the power switch is nor-

mally delayed to allow the other switch to completely

turn off.

16.5.6

START-UP CONSIDERATIONS

Prior to enabling the PWM outputs, the P1A, P1B, P1C

and P1D latches may not be in the proper states.

Enabling the TRISD bits for output at the same time

with the ECCP1 module may cause damage to the

power switch devices. The ECCP1 module must be

enabled in the proper Output mode with the TRISD bits

enabled as inputs. Once the ECCP1 completes a full

PWM cycle, the P1A, P1B, P1C and 1PD output

latches are properly initialized. At this time, the TRISD

bits can be enabled for outputs to start driving the

power switch devices. The completion of a full PWM

cycle is indicated by the TMR2IF bit going from a ’0’ to

a ’1’.

In the Half-Bridge Output mode, a digitally program-

mable deadband delay is available to avoid shoot-

through current from destroying the bridge power

switches. The delay occurs at the signal transition from

the non-active state to the active state. See Figure 16-3

for illustration. The ECCP1DEL register (Register 16-2)

sets the amount of delay.

16.5.7

OUTPUT POLARITY

CONFIGURATION

The ECCP1M<1:0> bits in the ECCP1CON register

allow user to choose the logic conventions (asserted

high/low) for each of the outputs.

16.5.5

SYSTEM IMPLEMENTATION

The PWM output polarities must be selected before the

PWM outputs are enabled. Charging the polarity con-

figuration while the PWM outputs are active is not rec-

ommended, since it may result in unpredictable

operation.

When the ECCP module is used in the PWM mode, the

application hardware must use the proper external pull-

up and/or pull-down resistors on the PWM output pins.

When the microcontroller powers up, all of the I/O pins

are in the high-impedance state. The external pull-up

and pull-down resistors must keep the power switch

REGISTER 16-2: ECCP1DEL REGISTER

R/W-0

EPDC7

EPDC6

EPDC5

EPDC4

EPDC3

EPDC2

EPDC1

EPDC0

bit 7

bit 0

bit 7-0

EPDC<7:0>: PWM Delay Count for Half-Bridge Output Mode bits

Number of FOSC/4 (TOSC*4) cycles between the P1A transition and the P1B transition

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

DS41159B-page 138

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

2. Configure and start TMR2:

16.5.8

SETUP FOR PWM OPERATION

a) Clear the TMR2 interrupt flag bit by clearing

the TMR2IF bit in the PIR1 register.

The following steps should be taken when configuring

the ECCP1 module for PWM operation:

b) Set the TMR2 prescale value by loading the

T2CKPS bits (T2CON<1:0>).

1. Configure the PWM module:

a) Disable the ECCP1/P1A, P1B, P1C and/or

P1D outputs by setting the respective TRISD

bits.

c) Enable Timer2 by setting the TMR2ON bit

(T2CON<2>) register.

3. Enable PWM outputs after a new cycle has

started:

b) Set the PWM period by loading the PR2

register.

a) Wait until TMR2 overflows (TMR2IF bit

becomes a ’1’). The new PWM cycle begins

here.

c) Set the PWM duty cycle by loading the

ECCPR1L register and ECCP1CON<5:4> bits.

d) Configure the ECCP1 module for the desired

PWM operation, by loading the ECCP1CON

register with the appropriate value. With the

ECCP1M<3:0> bits, select the active high/low

levels for each PWM output. With the

EPWM1M<1:0> bits, select one of the

available Output modes.

b) Enable the ECCP1/P1A, P1B, P1C and/or

P1D pin outputs by clearing the respective

TRISD bits.

e) For Half-Bridge Output mode, set the dead-

band delay by loading the ECCP1DEL

register with the appropriate value.

TABLE 16-5: REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

RCON

IPR2

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RI

RBIE

TO

TMR0IF

PD

INT0IF

POR

RBIF

BOR

0000 000x 0000 000u

0--1 11qq 0--q qquu

IPEN

—

CMIP

CMIF

CMIE

EEIP

EEIF

EEIE

BCLIP

BCLIF

BCLIE

LVDIP

LVDIF

LVDIE

TMR3IP ECCP1IP -0-0 1111 -1-1 1111

TMR3IF ECCP1IF -0-0 0000 -0-0 0000

TMR3IE ECCP1IE -0-0 0000 -0-0 0000

0000 0000 0000 0000

PIR2

—

PIE2

—

TMR2

PR2

Timer2 Module Register

Timer2 Module Period Register

1111 1111 1111 1111

T2CON

TRISD

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

PORTD Data Direction Register

1111 1111 1111 1111

xxxx xxxx uuuu uuuu

ECCPR1H Enhanced Capture/Compare/PWM Register1 High Byte

ECCPR1L Enhanced Capture/Compare/PWM Register1 Low Byte

ECCP1CON EPWM1M1 EPWM1M0 EDC1B1

ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000

ECCP1DEL EPDC7 EPDC6 EPDC5 EPDC4 EPDC3 EPDC2 EPDC1 EPDC0 0000 0000 uuuu uuuu

Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the ECCP module.

EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 0000 0000

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 139

PIC18FXX8

The internal shutdown signal is gated with the outputs

and will immediately and asynchronously disable the

outputs. If the internal shutdown is still in effect at the

16.6 Enhanced CCP Auto-Shutdown

When the ECCP is programmed for any of the PWM

modes, the output pins associated with its function may

be configured for Auto-Shutdown.

time

a new cycle begins, that entire cycle is

suppressed, thus eliminating narrow, glitchy pulses.

Auto-Shutdown allows the internal output of either of

the two comparator modules, or the external interrupt

0, to asynchronously disable the ECCP output pins.

Thus, an external analog or digital event can discon-

tinue an ECCP sequence. The comparator output(s) to

be used is selected by setting the proper mode bits in

the ECCPAS register. To use external interrupt INT0 as

a shutdown event, INT0IE must be set. To use either of

the comparator module outputs as a shutdown event,

corresponding comparators must be enabled. When a

shutdown occurs, the selected output values

(PSSACn, PSSBDn) are written to the ECCP port pins.

The ECCPASE bit is set by hardware upon a compara-

tor event and can only be cleared in software. The

ECCP outputs can be re-enabled only by clearing the

ECCPASE bit.

The Auto-Shutdown mode can be manually entered by

writing a ‘1’ to the ECCPASE bit.

REGISTER 16-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM/AUTO-SHUTDOWN

CONTROL REGISTER

R/W-0

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0

bit 7

bit 0

bit 7

ECCPASE: ECCP Auto-Shutdown Event Status bit

0= ECCP outputs enabled, no shutdown event

1= A shutdown event has occurred, must be reset in software to re-enable ECCP

bit 6-4

ECCPAS<2:0>: ECCP Auto-Shutdown bits

000= No Auto-Shutdown enabled, comparators have no effect on ECCP

001= Comparator 1 output will cause shutdown

010= Comparator 2 output will cause shutdown

011= Either Comparator 1 or 2 can cause shutdown

100= INT0

101= INT0 or Comparator 1 output

110= INT0 or Comparator 2 output

111= INT0 or Comparator 1 or Comparator 2 output

bit 3-2

bit 1-0

PSSACn: Pin A and C Shutdown State Control bits

00= Drive Pins A and C to ‘0’

01= Drive Pins A and C to ‘1’

1x= Pins A and C tri-state

PSSBDn: Pin B and D Shutdown State Control bits

00= Drive Pins B and D to ‘0’

01= Drive Pins B and D to ‘1’

1x= Pins B and D tri-state

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

’1’ = Bit is set

DS41159B-page 140

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

17.3 SPI Mode

17.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

MODULE

The SPI mode allows 8 bits of data to be synchronously

transmitted and received simultaneously. All four modes

of SPI are supported. To accomplish communication,

typically three pins are used:

17.1 Master SSP (MSSP) Module

Overview

• Serial Data Out (SDO) - RC5/SDO

• Serial Data In (SDI) - RC4/SDI/SDA

• Serial Clock (SCK) - RC3/SCK/SCL

The Master Synchronous Serial Port (MSSP) module is

a serial interface useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers, dis-

play drivers, A/D converters, etc. The MSSP module

can operate in one of two modes:

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select (SS) - RF7/SS

Figure 17-1 shows the block diagram of the MSSP

module when operating in SPI mode.

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C)

- Full Master mode

FIGURE 17-1:

MSSP BLOCK DIAGRAM

(SPI MODE)

- Slave mode (with general address call)

The I²C interface supports the following modes in

hardware:

Internal

Data Bus

• Master mode

• Multi-Master mode

• Slave mode

Read

Write

SSPBUF reg

SSPSR reg

17.2 Control Registers

RC4/SDI/SDA

RC5/SDO

The MSSP module has three associated registers.

These include a status register (SSPSTAT) and two

control registers (SSPCON1 and SSPCON2). The use

of these registers and their individual configuration bits

differ significantly, depending on whether the MSSP

module is operated in SPI or I²C mode.

Shift

Clock

bit0

Additional details are provided under the individual

sections.

RF7/SS

Control

Enable

SS

Edge

Select

2

Clock Select

SSPM3:SSPM0

SMP:CKE

2

4

TMR2 Output

RC3/SCK/

SCL

(

)

2

Edge

Select

TOSC

Prescaler

4, 16, 64

Data to TX/RX in SSPSR

TRIS bit

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 141

PIC18FXX8

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

17.3.1

REGISTERS

The MSSP module has four registers for SPI mode

operation. These are:

In receive operations, SSPSR and SSPBUF together

create a double buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

• MSSP Control Register1 (SSPCON1)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• MSSP Shift Register (SSPSR) - Not directly

accessible

During transmission, the SSPBUF is not double buff-

ered. A write to SSPBUF will write to both SSPBUF and

SSPSR.

SSPCON1 and SSPSTAT are the control and status

registers in SPI mode operation. The SSPCON1 regis-

ter is readable and writable. The lower 6 bits of the

SSPSTAT are read only. The upper two bits of the

SSPSTAT are read/write.

REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

bit 7

bit 6

SMP: Sample bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

CKE: SPI Clock Edge Select

When CKP = 0:

1= Data transmitted on rising edge of SCK

0= Data transmitted on falling edge of SCK

When CKP = 1:

1= Data transmitted on falling edge of SCK

0= Data transmitted on rising edge of SCK

bit 5

bit 4

D/A: Data/Address bit

Used in I²C mode only

P: STOP bit

Used in I²C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is

cleared.

bit 3

bit 2

bit 1

bit 0

S: START bit

Used in I²C mode only

R/W: Read/Write bit information

Used in I²C mode only

UA: Update Address

Used in I²C mode only

BF: Buffer Full Status bit (Receive mode only)

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41159B-page 142

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER1 (SPI MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

bit 6

WCOL: Write Collision Detect bit (Transmit mode only)

1= The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

0= No collision

SSPOV: Receive Overflow Indicator bit

SPI Slave mode:

1= A new byte is received while the SSPBUF register is still holding the previous data. In case

of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user

must read the SSPBUF, even if only transmitting data, to avoid setting overflow

(must be cleared in software).

0= No overflow

Note:

In Master mode, the overflow bit is not set since each new reception (and

transmission) is initiated by writing to the SSPBUF register.

bit 5

bit 4

SSPEN: Synchronous Serial Port Enable bit

1= Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins

0= Disables serial port and configures these pins as I/O port pins

Note:

When enabled, these pins must be properly configured as input or output.

CKP: Clock Polarity Select bit

1= IDLE state for clock is a high level

0= IDLE state for clock is a low level

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin

0100= SPI Slave mode, clock = SCK pin, SS pin control enabled

0011= SPI Master mode, clock = TMR2 output/2

0010= SPI Master mode, clock = FOSC/64

0001= SPI Master mode, clock = FOSC/16

0000= SPI Master mode, clock = FOSC/4

Note:

Bit combinations not specifically listed here are either reserved, or implemented in

I²C mode only.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 143

PIC18FXX8

SSPBUF register during transmission/reception of data

will be ignored, and the write collision detect bit, WCOL

(SSPCON1<7>), will be set. User software must clear

the WCOL bit so that it can be determined if the follow-

ing write(s) to the SSPBUF register completed

successfully.

17.3.2

OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON1<5:0>) and SSPSTAT<7:6>.

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (IDLE state of SCK)

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. Buffer

full bit, BF (SSPSTAT<0>), indicates when SSPBUF

has been loaded with the received data (transmission

is complete). When the SSPBUF is read, the BF bit is

cleared. This data may be irrelevant if the SPI is only a

transmitter. Generally, the MSSP Interrupt is used to

determine when the transmission/reception has com-

pleted. The SSPBUF must be read and/or written. If the

interrupt method is not going to be used, then software

polling can be done to ensure that a write collision does

not occur. Example 17-1 shows the loading of the

SSPBUF (SSPSR) for data transmission.

• Data input sample phase (middle or end of data

output time)

• Clock edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

The MSSP consists of a transmit/receive Shift Register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR,

until the received data is ready. Once the 8 bits of data

have been received, that byte is moved to the SSPBUF

register. Then the buffer full detect bit, BF

(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are

set. This double buffering of the received data

(SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the

The SSPSR is not directly readable or writable, and

can only be accessed by addressing the SSPBUF reg-

ister. Additionally, the MSSP status register (SSPSTAT)

indicates the various status conditions.

EXAMPLE 17-1:

LOADING THE SSPBUF (SSPSR) REGISTER

LOOP BTFSS SSPSTAT, BF

;Has data been received(transmit complete)?

BRA

LOOP

;No

MOVF SSPBUF, W

;WREG reg = contents of SSPBUF

MOVWF RXDATA

;Save in user RAM, if data is meaningful

MOVF TXDATA, W

MOVWF SSPBUF

;W reg = contents of TXDATA

;New data to xmit

DS41159B-page 144

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

17.3.3

ENABLING SPI I/O

17.3.4

TYPICAL CONNECTION

To enable the serial port, SSP Enable bit, SSPEN

(SSPCON1<5>), must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, re-initialize the

SSPCON registers, and then set the SSPEN bit. This

configures the SDI, SDO, SCK, and SS pins as serial

port pins. For the pins to behave as the serial port func-

tion, some must have their data direction bits (in the

TRIS register) appropriately programmed as follows:

Figure 17-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge, and latched on the opposite

edge of the clock. Both processors should be pro-

grammed to the same Clock Polarity (CKP), then both

controllers would send and receive data at the same

time. Whether the data is meaningful (or dummy data)

depends on the application software. This leads to

three scenarios for data transmission:

• SDI is automatically controlled by the SPI module

• SDO must have TRISC<5> bit cleared

• SCK (Master mode) must have TRISC<3> bit

cleared

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

• SCK (Slave mode) must have TRISC<3> bit set

• SS must have TRISF<7> bit set

• Master sends dummy data — Slave sends data

Any serial port function that is not desired may be over-

ridden by programming the corresponding data direc-

tion (TRIS) register to the opposite value.

FIGURE 17-2:

SPI MASTER/SLAVE CONNECTION

SPI Master SSPM3:SSPM0 = 00xxb

SPI Slave SSPM3:SSPM0 = 010xb

SDO

SDI

Serial Input Buffer

(SSPBUF)

Serial Input Buffer

(SSPBUF)

SDI

SDO

Shift Register

(SSPSR)

Shift Register

(SSPSR)

LSb

MSb

LSb

Serial Clock

SCK

PROCESSOR 1

PROCESSOR 2

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 145

PIC18FXX8

The clock polarity is selected by appropriately program-

ming the CKP bit (SSPCON1<4>). This then, would

give waveforms for SPI communication as shown in

Figure 17-3, Figure 17-5, and Figure 17-6, where the

MSB is transmitted first. In Master mode, the SPI clock

rate (bit rate) is user programmable to be one of the

following:

17.3.5

MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 17-2) is to broad-

cast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI is

only going to receive, the SDO output could be dis-

abled (programmed as an input). The SSPSR register

will continue to shift in the signal present on the SDI pin

at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and status bits

appropriately set). This could be useful in receiver

applications as a “Line Activity Monitor” mode.

• FOSC/4 (or TCY)

• FOSC/16 (or 4 • TCY)

• FOSC/64 (or 16 • TCY)

• Timer2 output/2

This allows a maximum data rate (at 40 MHz) of

10.00 Mbps.

Figure 17-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

data is shown.

FIGURE 17-3:

SPI MODE WAVEFORM (MASTER MODE)

Write to

SSPBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 Clock

Modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

bit6

bit2

bit5

bit4

bit1

bit0

SDO

(CKE = 0)

bit7

bit3

SDO

(CKE = 1)

SDI

(SMP = 0)

bit0

bit7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit0

bit7

Input

Sample

(SMP = 1)

SSPIF

Next Q4 cycle

after Q2↓

SSPSR to

SSPBUF

DS41159B-page 146

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

the SDO pin is no longer driven, even if in the mid-

dle of a transmitted byte, and becomes a floating

output. External pull-up/pull-down resistors may be

desirable, depending on the application.

17.3.6

SLAVE MODE

In Slave mode, the data is transmitted and received as

the external clock pulses appear on SCK. When the

last bit is latched, the SSPIF interrupt flag bit is set.

Note 1: When the SPI is in Slave mode with SS

pin control enabled (SSPCON<3:0> =

0100), the SPI module will reset if the SS

pin is set to VDD.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

2: If the SPI is used in Slave mode with CKE

set, then the SS pin control must be

enabled.

While in SLEEP mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from SLEEP.

When the SPI module resets, the bit counter is forced

to 0. This can be done by either forcing the SS pin to a

high level or clearing the SSPEN bit.

17.3.7

SLAVE SELECT

SYNCHRONIZATION

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver, the SDO pin can be configured

as an input. This disables transmissions from the SDO.

The SDI can always be left as an input (SDI function),

since it cannot create a bus conflict.

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SS pin control

enabled (SSPCON1<3:0> = 04h). The pin must not

be driven low for the SS pin to function as an input.

The Data Latch must be high. When the SS pin is

low, transmission and reception are enabled and

the SDO pin is driven. When the SS pin goes high,

FIGURE 17-4:

SLAVE SYNCHRONIZATION WAVEFORM

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit6

bit7

bit0

SDO

bit7

SDI

(SMP = 0)

bit0

bit7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 cycle

SSPSR to

SSPBUF

after Q2↓

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 147

PIC18FXX8

FIGURE 17-5:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS

Optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit6

bit2

bit5

bit4

bit1

bit0

SDO

bit7

bit3

SDI

(SMP = 0)

bit0

bit7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 cycle

after Q2↓

SSPSR to

SSPBUF

FIGURE 17-6:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS

Not Optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPBUF

bit6

bit2

bit5

bit4

bit1

bit0

SDO

bit7

bit3

SDI

(SMP = 0)

bit0

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 cycle

after Q2↓

SSPSR to

SSPBUF

DS41159B-page 148

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

17.3.8

SLEEP OPERATION

17.3.10 BUS MODE COMPATIBILITY

In Master mode, all module clocks are halted and the

transmission/reception will remain in that state until the

device wakes from SLEEP. After the device returns to

normal mode, the module will continue to

transmit/receive data.

Table 17-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

TABLE 17-1: SPI BUS MODES

In Slave mode, the SPI transmit/receive shift register

operates asynchronously to the device. This allows the

device to be placed in SLEEP mode and data to be

shifted into the SPI transmit/receive shift register.

When all 8 bits have been received, the MSSP interrupt

flag bit will be set and if enabled, will wake the device

from SLEEP.

Control Bits State

Standard SPI Mode

Terminology

CKP

CKE

0, 0

0, 1

1, 0

1, 1

0

1

0

1

0

17.3.9

EFFECTS OF A RESET

There is also a SMP bit, which controls when the data

is sampled.

A RESET disables the MSSP module and terminates

the current transfer.

TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

INT0IF

RBIF

0000 0000 0000 0000

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111

1111 1111 1111 1111

PIE1

IPR1

TRISC

TRISF

SSPBUF

SSPCON

PORTC Data Direction Register

TRISF7 TRISF6 TRISF5 TRISF4 TRISF3

Synchronous Serial Port Receive Buffer/Transmit Register

TRISF2

TRISF1 TRISF0 1111 1111 uuuu uuuu

xxxx xxxx uuuu uuuu

WCOL

SMP

SSPOV

CKE

SSPEN

D/A

CKP

P

SSPM3

S

SSPM2

R/W

SSPM1 SSPM0 0000 0000 0000 0000

SSPSTAT

UA

BF

0000 0000 0000 0000

Legend: x= unknown, u= unchanged, - = unimplemented, read as ’0’. Shaded cells are not used by the MSSP in SPI mode.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 149

PIC18FXX8

2

17.4.1

REGISTERS

17.4 I C Mode

The MSSP module has six registers for I²C operation.

These are:

The MSSP module in I²C mode fully implements all

master and slave functions (including general call sup-

port) and provides interrupts on START and STOP bits

in hardware to determine a free bus (multi-master func-

tion). The MSSP module implements the standard

mode specifications, as well as 7-bit and 10-bit

addressing.

• MSSP Control Register1 (SSPCON1)

• MSSP Control Register2 (SSPCON2)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• MSSP Shift Register (SSPSR) - Not directly

accessible

Two pins are used for data transfer:

• Serial clock (SCL) - RC3/SCK/SCL

• Serial data (SDA) - RC4/SDI/SDA

• MSSP Address Register (SSPADD)

SSPCON, SSPCON2 and SSPSTAT are the control

and status registers in I²C mode operation. The

SSPCON and SSPCON2 registers are readable and

writable. The lower 6 bits of the SSPSTAT are read

only. The upper two bits of the SSPSTAT are

read/write.

The user must configure these pins as inputs or outputs

through the TRISC<4:3> bits.

FIGURE 17-7:

MSSP BLOCK DIAGRAM

(I²C MODE)

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

Internal

Data Bus

Read

Write

SSPADD register holds the slave device address

when the SSP is configured in I²C Slave mode. When

the SSP is configured in Master mode, the lower

seven bits of SSPADD act as the baud rate generator

reload value.

SSPBUF reg

RC3/SCK/SCL

Shift

Clock

In receive operations, SSPSR and SSPBUF together,

create a double buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

SSPSR reg

RC4/

SDI/

SDA

MSb

LSb

Addr Match

Match Detect

During transmission, the SSPBUF is not double buff-

ered. A write to SSPBUF will write to both SSPBUF and

SSPSR.

SSPADD reg

START and

Set, Reset

S, P bits

(SSPSTAT reg)

STOP bit Detect

DS41159B-page 150

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I²C MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

bit 7

bit 6

bit 5

SMP: Slew Rate Control bit

In Master or Slave mode:

1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for High Speed mode (400 kHz)

CKE: SMBus Select bit

In Master or Slave mode:

1= Enable SMBus specific inputs

0= Disable SMBus specific inputs

D/A: Data/Address bit

In Master mode:

Reserved

In Slave mode:

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

bit 4

bit 3

bit 2

P: STOP bit

1= Indicates that a STOP bit has been detected last

0= STOP bit was not detected last

Note:

This bit is cleared on RESET and when SSPEN is cleared.

S: START bit

1= Indicates that a START bit has been detected last

0= START bit was not detected last

Note:

This bit is cleared on RESET and when SSPEN is cleared.

R/W: Read/Write bit Information (I²C mode only)

In Slave mode:

1= Read

0= Write

Note:

This bit holds the R/W bit information following the last address match. This bit is only

valid from the address match to the next START bit, STOP bit, or not ACK bit.

In Master mode:

1= Transmit is in progress

0= Transmit is not in progress

Note:

ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is

in IDLE mode.

bit 1

bit 0

UA: Update Address (10-bit Slave mode only)

1= Indicates that the user needs to update the address in the SSPADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

In Transmit mode:

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

In Receive mode:

1= Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full

0= Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 151

PIC18FXX8

REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER1 (I²C MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

WCOL: Write Collision Detect bit

In Master Transmit mode:

1= A write to the SSPBUF register was attempted while the I²C conditions were not valid for

a transmission to be started (must be cleared in software)

0= No collision

In Slave Transmit mode:

1= The SSPBUF register is written while it is still transmitting the previous word (must be

cleared in software)

0= No collision

In Receive mode (Master or Slave modes):

This is a “don’t care” bit

bit 6

SSPOV: Receive Overflow Indicator bit

In Receive mode:

1= A byte is received while the SSPBUF register is still holding the previous byte (must

be cleared in software)

0= No overflow

In Transmit mode:

This is a “don’t care” bit in Transmit mode

bit 5

bit 4

SSPEN: Synchronous Serial Port Enable bit

1= Enables the serial port and configures the SDA and SCL pins as the serial port pins

0= Disables serial port and configures these pins as I/O port pins

Note:

When enabled, the SDA and SCL pins must be properly configured as input or output.

CKP: SCK Release Control bit

In Slave mode:

1= Release clock

0= Holds clock low (clock stretch), used to ensure data setup time

In Master mode:

Unused in this mode

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

1111= I²C Slave mode, 10-bit address with START and STOP bit interrupts enabled

1110= I²C Slave mode, 7-bit address with START and STOP bit interrupts enabled

1011= I²C Firmware Controlled Master mode (Slave IDLE)

1000= I²C Master mode, clock = FOSC / (4 * (SSPADD+1))

0111= I²C Slave mode, 10-bit address

0110= I²C Slave mode, 7-bit address

Note:

Bit combinations not specifically listed here are either reserved, or implemented in

SPI mode only.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41159B-page 152

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I²C MODE)

R/W-0

GCEN

R/W-0

RCEN

R/W-0

PEN

R/W-0

RSEN

R/W-0

SEN

ACKSTAT

ACKDT

ACKEN

bit 7

bit 0

bit 7

bit 6

bit 5

GCEN: General Call Enable bit (Slave mode only)

1= Enable interrupt when a general call address (0000h) is received in the SSPSR

0= General call address disabled

ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

1= Acknowledge was not received from slave

0= Acknowledge was received from slave

ACKDT: Acknowledge Data bit (Master Receive mode only)

1= Not Acknowledge

0= Acknowledge

Note:

Value that will be transmitted when the user initiates an Acknowledge sequence at

the end of a receive.

bit 4

ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)

1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0= Acknowledge sequence IDLE

bit 3

bit 2

RCEN: Receive Enable bit (Master Mode only)

1= Enables Receive mode for I²C

0= Receive IDLE

PEN: STOP Condition Enable bit (Master mode only)

1= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.

0= STOP condition IDLE

bit 1

bit 0

RSEN: Repeated START Condition Enabled bit (Master mode only)

1= Initiate Repeated START condition on SDA and SCL pins.

Automatically cleared by hardware.

0= Repeated START condition IDLE

SEN: START Condition Enabled/Stretch Enabled bit

In Master mode:

1= Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.

0= START condition IDLE

In Slave mode:

1= Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled)

0= Clock stretching is enabled for Slave Transmit only (Legacy mode)

Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I²C module is not in the IDLE

mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or

writes to the SSPBUF are disabled).

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR reset

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 153

PIC18FXX8

17.4.2

OPERATION

17.4.3.1

Addressing

Once the MSSP module has been enabled, it waits for

a START condition to occur. Following the START con-

dition, the 8-bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

The MSSP module functions are enabled by setting

MSSP Enable bit, SSPEN (SSPCON<5>).

The SSPCON1 register allows control of the I²C oper-

ation. Four mode selection bits (SSPCON<3:0>) allow

one of the following I²C modes to be selected:

• I²C Master mode, clock = OSC/4 (SSPADD +1)

• I²C Slave mode (7-bit address)

• I²C Slave mode (10-bit address)

• I²C Slave mode (7-bit address), with START and

STOP bit interrupts enabled

1. The SSPSR register value is loaded into the

SSPBUF register.

• I²C Slave mode (10-bit address), with START and

STOP bit interrupts enabled

• I²C Firmware controlled master operation, slave

is IDLE

Selection of any I²C mode, with the SSPEN bit set,

forces the SCL and SDA pins to be open drain, pro-

vided these pins are programmed to inputs by setting

the appropriate TRISC bits. To ensure proper operation

of the module, pull-up resistors must be provided

externally to the SCL and SDA pins.

2. The buffer full bit BF is set.

3. An ACK pulse is generated.

4. MSSP interrupt flag bit, SSPIF (PIR1<3>) is set

(interrupt is generated if enabled) on the falling

edge of the ninth SCL pulse.

In 10-bit Address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit R/W (SSPSTAT<2>) must specify a write

so the slave device will receive the second address

byte. For a 10-bit address, the first byte would equal

‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two

MSbs of the address. The sequence of events for 10-bit

address is as follows, with steps 7 through 9 for the

slave-transmitter:

17.4.3

SLAVE MODE

In Slave mode, the SCL and SDA pins must be config-

ured as inputs (TRISC<4:3> set). The MSSP module

will override the input state with the output data when

required (slave-transmitter).

The I²C Slave mode hardware will always generate an

interrupt on an address match. Through the mode

select bits, the user can also choose to interrupt on

START and STOP bits

1. Receive first (high) byte of Address (bits SSPIF,

BF and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)

byte of Address (clears bit UA and releases the

SCL line).

3. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

When an address is matched or the data transfer after

an address match is received, the hardware automati-

cally will generate the Acknowledge (ACK) pulse and

load the SSPBUF register with the received value cur-

rently in the SSPSR register.

4. Receive second (low) byte of Address (bits

SSPIF, BF, and UA are set).

5. Update the SSPADD register with the first (high)

byte of Address. If match releases SCL line, this

will clear bit UA.

Any combination of the following conditions will cause

the MSSP module not to give this ACK pulse:

6. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

• The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

7. Receive Repeated START condition.

• The overflow bit SSPOV (SSPCON<6>) was set

before the transfer was received.

8. Receive first (high) byte of Address (bits SSPIF

and BF are set).

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The

BF bit is cleared by reading the SSPBUF register, while

bit SSPOV is cleared through software.

9. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

I²C specification, as well as the requirement of the

MSSP module, are shown in timing parameter #100

and parameter #101.

DS41159B-page 154

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

17.4.3.2

Reception

17.4.3.3

Transmission

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

register is cleared. The received address is loaded into

the SSPBUF register and the SDA line is held low

(ACK).

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin RC3/SCK/SCL is held

low, regardless of SEN (see Section 17.4.4, Clock

Stretching for more detail). By stretching the clock, the

master will be unable to assert another clock pulse until

the slave is done preparing the transmit data.The trans-

mit data must be loaded into the SSPBUF register,

which also loads the SSPSR register. Then pin

RC3/SCK/SCL should be enabled by setting bit CKP

(SSPCON1<4>). The eight data bits are shifted out on

the falling edge of the SCL input. This ensures that the

SDA signal is valid during the SCL high time

(Figure 17-9).

When the address byte overflow condition exists, then

the no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF (SSPSTAT<0>) is

set, or bit SSPOV (SSPCON1<6>) is set.

An MSSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-

ware. The SSPSTAT register is used to determine the

status of the byte.

If SEN is enabled (SSPCON1<0>=1), RC3/SCK/SCL

will be held low (clock stretch) following each data

transfer. The clock must be released by setting bit CKP

(SSPCON<4>). See Section 17.4.4, Clock Stretching

for more detail.

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. If the SDA

line is high (not ACK), then the data transfer is com-

plete. In this case, when the ACK is latched by the

slave, the slave logic is reset (resets SSPSTAT regis-

ter) and the slave monitors for another occurrence of

the START bit. If the SDA line was low (ACK), the next

transmit data must be loaded into the SSPBUF register.

Again, pin RC3/SCK/SCL must be enabled by setting

bit CKP.

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 155

PIC18FXX8

2

FIGURE 17-8:

I C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)

DS41159B-page 156

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

2

FIGURE 17-9:

I C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 157

PIC18FXX8

FIGURE 17-10:

I²C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)

DS41159B-page 158

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

2

FIGURE 17-11:

I C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 159

PIC18FXX8

17.4.4

CLOCK STRETCHING

17.4.4.3

Clock Stretching for 7-bit Slave

Transmit Mode

Both 7- and 10-bit Slave modes implement automatic

clock stretching during a transmit sequence.

7-bit Slave Transmit mode implements clock stretching

by clearing the CKP bit after the falling edge of the

ninth clock, if the BF bit is clear. This occurs, regard-

less of the state of the SEN bit.

The SEN bit (SSPCON2<0>) allows clock stretching to

be enabled during receives. Setting SEN will cause

the SCL pin to be held low at the end of each data

receive sequence.

The user’s ISR must set the CKP bit before transmis-

sion is allowed to continue. By holding the SCL line

low, the user has time to service the ISR and load the

contents of the SSPBUF before the master device can

initiate another transmit sequence (see Figure 17-9).

17.4.4.1

Clock Stretching for 7-bit Slave

Receive Mode (SEN = 1)

In 7-bit Slave Receive mode, on the falling edge of the

ninth clock at the end of the ACK sequence, if the BF

bit is set, the CKP bit in the SSPCON1 register is auto-

matically cleared, forcing the SCL output to be held

low. The CKP being cleared to ‘0’ will assert the SCL

line low. The CKP bit must be set in the user’s ISR

before reception is allowed to continue. By holding the

SCL line low, the user has time to service the ISR and

read the contents of the SSPBUF before the master

device can initiate another receive sequence. This will

prevent buffer overruns from occurring.

Note 1: If the user loads the contents of SSPBUF,

setting the BF bit before the falling edge of

the ninth clock, the CKP bit will not be

cleared and clock stretching will not occur.

2: The CKP bit can be set in software,

regardless of the state of the BF bit.

17.4.4.4

Clock Stretching for 10-bit Slave

Transmit Mode

In 10-bit Slave Transmit mode, clock stretching is con-

trolled during the first two address sequences by the

state of the UA bit, just as it is in 10-bit Slave Receive

mode. The first two addresses are followed by a third

address sequence, which contains the high order bits

of the 10-bit address and the R/W bit set to ‘1’. After

the third address sequence is performed, the UA bit is

not set, the module is now configured in Transmit

mode, and clock stretching is controlled by the BF flag,

as in 7-bit Slave Transmit mode (see Figure 17-11).

Note 1: If the user reads the contents of the

SSPBUF before the falling edge of the

ninth clock, thus clearing the BF bit, the

CKP bit will not be cleared and clock

stretching will not occur.

2: The CKP bit can be set in software,

regardless of the state of the BF bit. The

user should be careful to clear the BF bit

in the ISR before the next receive

sequence, in order to prevent an overflow

condition.

17.4.4.2

Clock Stretching for 10-bit Slave

Receive Mode (SEN = 1)

In 10-bit Slave Receive mode, during the address

sequence, clock stretching automatically takes place

but CKP is not cleared. During this time, if the UA bit is

set after the ninth clock, clock stretching is initiated.

The UA bit is set after receiving the upper byte of the

10-bit address, and following the receive of the second

byte of the 10-bit address with the R/W bit cleared to

‘0’. The release of the clock line occurs upon updating

SSPADD. Clock stretching will occur on each data

receive sequence as described in 7-bit mode.

Note: If the user polls the UA bit and clears it by

updating the SSPADD register before the

falling edge of the ninth clock occurs, and if

the user hasn’t cleared the BF bit by read-

ing the SSPBUF register before that time,

then the CKP bit will still NOT be asserted

low. Clock stretching on the basis of the

state of the BF bit only occurs during a data

sequence, not an address sequence.

DS41159B-page 160

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

assert the SCL line until an external I²C master device

has already asserted the SCL line. The SCL output will

remain low until the CKP bit is set, and all other devices

on the I²C bus have de-asserted SCL. This ensures

that a write to the CKP bit will not violate the minimum

high time requirement for SCL (see Figure 17-12).

17.4.4.5

Clock Synchronization and

the CKP bit

If a user clears the CKP bit, the SCL output is forced to

‘0’. Setting the CKP bit will not assert the SCL output

low until the SCL output is already sampled low. If the

user attempts to drive SCL low, the CKP bit will not

FIGURE 17-12:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX-1

Master device

asserts clock

CKP

Master device

de-asserts clock

WR

SSPCON

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 161

PIC18FXX8

2

FIGURE 17-13:

I C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)

DS41159B-page 162

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 17-14:

I²C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 163

PIC18FXX8

If the general call address matches, the SSPSR is

transferred to the SSPBUF, the BF flag bit is set (eighth

bit), and on the falling edge of the ninth bit (ACK bit),

the SSPIF interrupt flag bit is set.

17.4.5

GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I²C bus is such that

the first byte after the START condition usually deter-

mines which device will be the slave addressed by the

master. The exception is the general call address,

which can address all devices. When this address is

used, all devices should, in theory, respond with an

Acknowledge.

When the interrupt is serviced, the source for the inter-

rupt can be checked by reading the contents of the

SSPBUF. The value can be used to determine if the

address was device specific or a general call address.

In 10-bit mode, the SSPADD is required to be updated

for the second half of the address to match, and the UA

bit is set (SSPSTAT<1>). If the general call address is

sampled when the GCEN bit is set, while the slave is

configured in 10-bit Address mode, then the second

half of the address is not necessary, the UA bit will not

be set, and the slave will begin receiving data after the

Acknowledge (Figure 17-15).

The general call address is one of eight addresses

reserved for specific purposes by the I²C protocol. It

consists of all 0’s with R/W = 0.

The general call address is recognized when the Gen-

eral Call Enable bit (GCEN) is enabled (SSPCON2<7>

set). Following a START bit detect, 8-bits are shifted

into the SSPSR and the address is compared against

the SSPADD. It is also compared to the general call

address and fixed in hardware.

FIGURE 17-15:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

(7 OR 10-BIT ADDRESS MODE)

Address is compared to General Call Address

after ACK, set interrupt

Receiving data

D5 D4 D3 D2 D1

ACK

R/W = 0

General Call Address

ACK

SDA

SCL

D7 D6

D0

8

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

9

S

SSPIF

BF (SSPSTAT<0>)

Cleared in software

SSPBUF is read

SSPOV (SSPCON1<6>)

GCEN (SSPCON2<7>)

’0’

’1’

DS41159B-page 164

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Note: The MSSP Module, when configured in I²C

Master mode, does not allow queueing of

events. For instance, the user is not

allowed to initiate a START condition and

immediately write the SSPBUF register to

initiate transmission before the START

condition is complete. In this case, the

SSPBUF will not be written to and the

WCOL bit will be set, indicating that a write

to the SSPBUF did not occur.

17.4.6

MASTER MODE

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON1 and by setting the

SSPEN bit. In Master mode, the SCL and SDA lines

are manipulated by the MSSP hardware.

Master mode of operation is supported by interrupt

generation on the detection of the START and STOP

conditions. The STOP (P) and START (S) bits are

cleared from a RESET or when the MSSP module is

disabled. Control of the I²C bus may be taken when the

P bit is set or the bus is IDLE, with both the S and P bits

clear.

The following events will cause SSP interrupt flag bit,

SSPIF, to be set (SSP interrupt if enabled):

• START condition

In Firmware Controlled Master mode, user code con-

ducts all I²C bus operations based on START and

STOP bit conditions.

• STOP condition

• Data transfer byte transmitted/received

• Acknowledge Transmit

• Repeated START

Once Master mode is enabled, the user has six

options.

1. Assert a START condition on SDA and SCL.

2. Assert a Repeated START condition on SDA

and SCL.

3. Write to the SSPBUF register initiating transmis-

sion of data/address.

4. Configure the I²C port to receive data.

5. Generate an Acknowledge condition at the end

of a received byte of data.

6. Generate a STOP condition on SDA and SCL.

2

FIGURE 17-16:

MSSP BLOCK DIAGRAM (I C MASTER MODE)

Internal

Data Bus

SSPM3:SSPM0

SSPADD<6:0>

Read

Write

SSPBUF

SSPSR

Baud

Rate

Generator

SDA

Shift

Clock

SDA in

MSb

LSb

START bit, STOP bit,

Acknowledge

Generate

SCL

START bit Detect

STOP bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

end of XMIT/RCV

SCL in

Bus Collision

Set/Reset, S, P, WCOL (SSPSTAT)

Set SSPIF, BCLIF

Reset ACKSTAT, PEN (SSPCON2)

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 165

PIC18FXX8

I²C Master Mode Operation

A typical transmit sequence would go as follows:

1. The user generates a START condition by set-

17.4.6.1

The master device generates all of the serial clock

pulses and the START and STOP conditions. A trans-

fer is ended with a STOP condition or with a Repeated

START condition. Since the Repeated START condi-

tion is also the beginning of the next serial transfer, the

I²C bus will not be released.

ting

the

START

enable

bit,

SEN

(SSPCON2<0>).

2. SSPIF is set. The MSSP module will wait the

required start time before any other operation

takes place.

3. The user loads the SSPBUF with the slave

address to transmit.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic ’0’. Serial data is

transmitted 8 bits at a time. After each byte is transmit-

ted, an Acknowledge bit is received. START and STOP

conditions are output to indicate the beginning and the

end of a serial transfer.

4. Address is shifted out the SDA pin until all 8 bits

are transmitted.

5. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

6. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

In Master Receive mode, the first byte transmitted con-

tains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic ’1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ’1’ to indicate receive bit. Serial

data is received via SDA, while SCL outputs the serial

clock. Serial data is received 8 bits at a time. After each

byte is received, an Acknowledge bit is transmitted.

START and STOP conditions indicate the beginning

and end of transmission.

7. The user loads the SSPBUF with eight bits of

data.

8. Data is shifted out the SDA pin until all 8 bits are

transmitted.

9. The MSSP Module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

10. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

The baud rate generator used for the SPI mode opera-

tion is used to set the SCL clock frequency for either

100 kHz, 400 kHz or 1 MHz I²C operation. See

Section 17.4.7, Baud Rate Generator for more details.

11. The user generates a STOP condition by setting

the STOP enable bit PEN (SSPCON2<2>).

12. Interrupt is generated once the STOP condition

is complete.

DS41159B-page 166

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Once the given operation is complete (i.e., transmis-

sion of the last data bit is followed by ACK), the internal

clock will automatically stop counting and the SCL pin

will remain in its last state.

17.4.7

BAUD RATE GENERATOR

In I²C Master mode, the baud rate generator (BRG)

reload value is placed in the lower 7 bits of the

SSPADD register (Figure 17-17). When a write occurs

to SSPBUF, the baud rate generator will automatically

begin counting. The BRG counts down to 0 and stops

until another reload has taken place. The BRG count is

decremented twice per instruction cycle (TCY) on the

Q2 and Q4 clocks. In I²C Master mode, the BRG is

reloaded automatically.

Table 17-3 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

FIGURE 17-17:

BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM3:SSPM0

SSPADD<6:0>

SSPM3:SSPM0

SCL

Reload

Control

Reload

BRG Down Counter

CLKO

FOSC/4

TABLE 17-3: I²C CLOCK RATE W/BRG

(2)

FSCL

(2 Rollovers of BRG)

FCY

FCY*2

BRG Value

10 MHz

4 MHz

1 MHz

20 MHz

8 MHz

2 MHz

19h

20h

3Fh

0Ah

0Dh

28h

03h

0Ah

00h

400 kHz⁽¹⁾

312.5 kHz

100 kHz

400 kHz⁽¹⁾

308 kHz

100 kHz

333 kHz⁽¹⁾

100kHz

1 MHz⁽¹⁾

Note 1: The I²C interface does not conform to the 400 kHz I²C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

2: Actual frequency will depend on bus conditions.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 167

PIC18FXX8

sampled high, the baud rate generator is reloaded with

the contents of SSPADD<6:0> and begins counting.

This ensures that the SCL high time will always be at

least one BRG rollover count, in the event that the clock

is held low by an external device (Figure 17-18).

17.4.7.1

Clock Arbitration

Clock arbitration occurs when the master, during any

receive, transmit or Repeated START/STOP condition,

de-asserts the SCL pin (SCL allowed to float high).

When the SCL pin is allowed to float high, the baud rate

generator (BRG) is suspended from counting until the

SCL pin is actually sampled high. When the SCL pin is

FIGURE 17-18:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

DX

DX-1

SCL allowed to transition high

SCL de-asserted but slave holds

SCL low (clock arbitration)

SCL

BRG decrements on

Q2 and Q4 cycles

BRG

Value

03h

02h

01h

00h (hold off)

03h

02h

SCL is sampled high, reload takes

place and BRG starts its count.

BRG

Reload

DS41159B-page 168

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

17.4.8

I²C MASTER MODE START

CONDITION TIMING

17.4.8.1

WCOL Status Flag

If the user writes the SSPBUF when a START

sequence is in progress, the WCOL is set and the con-

tents of the buffer are unchanged (the write doesn’t

occur).

To initiate a START condition, the user sets the START

condition enable bit, SEN (SSPCON2<0>). If the SDA

and SCL pins are sampled high, the baud rate genera-

tor is reloaded with the contents of SSPADD<6:0> and

starts its count. If SCL and SDA are both sampled high

when the baud rate generator times out (TBRG), the

SDA pin is driven low. The action of the SDA being

driven low, while SCL is high, is the START condition

and causes the S bit (SSPSTAT<3>) to be set. Follow-

ing this, the baud rate generator is reloaded with the

contents of SSPADD<6:0> and resumes its count.

When the baud rate generator times out (TBRG), the

SEN bit (SSPCON2<0>) will be automatically cleared

by hardware, the baud rate generator is suspended,

leaving the SDA line held low and the START condition

is complete.

Note: Because queueing of events is not

allowed, writing to the lower 5 bits of

SSPCON2 is disabled until the START

condition is complete.

Note: If, at the beginning of the START condition,

the SDA and SCL pins are already sam-

pled low, or if during the START condition

the SCL line is sampled low before the

SDA line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCLIF is set, the START condition is

aborted, and the I²C module is reset into its

IDLE state.

FIGURE 17-19:

FIRST START BIT TIMING

Set S bit (SSPSTAT<3>)

Write to SEN bit occurs here

SDA = 1,

At completion of START bit,

Hardware clears SEN bit

and sets SSPIF bit

SCL = 1

TBRG

Write to SSPBUF occurs here

2nd bit

1st bit

SDA

TBRG

SCL

TBRG

S

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 169

PIC18FXX8

I²C MASTER MODE REPEATED

START CONDITION TIMING

Immediately following the SSPIF bit getting set, the

user may write the SSPBUF with the 7-bit address in

7-bit mode, or the default first address in 10-bit mode.

After the first eight bits are transmitted and an ACK is

received, the user may then transmit an additional eight

bits of address (10-bit mode) or eight bits of data (7-bit

mode).

17.4.9

A Repeated START condition occurs when the RSEN

bit (SSPCON2<1>) is programmed high and the I²C

logic module is in the IDLE state. When the RSEN bit is

set, the SCL pin is asserted low. When the SCL pin is

sampled low, the baud rate generator is loaded with the

contents of SSPADD<5:0> and begins counting. The

SDA pin is released (brought high) for one baud rate

generator count (TBRG). When the baud rate generator

times out, if SDA is sampled high, the SCL pin will be

de-asserted (brought high). When SCL is sampled

high, the baud rate generator is reloaded with the con-

tents of SSPADD<6:0> and begins counting. SDA and

SCL must be sampled high for one TBRG. This action is

then followed by assertion of the SDA pin (SDA = 0) for

17.4.9.1

WCOL Status Flag

If the user writes the SSPBUF when a Repeated

START sequence is in progress, the WCOL is set and

the contents of the buffer are unchanged (the write

doesn’t occur).

Note: Because queueing of events is not

allowed, writing of the lower 5 bits of

SSPCON2 is disabled until the Repeated

START condition is complete.

one TBRG while SCL is high. Following this, the RSEN

,

bit (SSPCON2<1>) will be automatically cleared and

the baud rate generator will not be reloaded, leaving

the SDA pin held low. As soon as a START condition is

detected on the SDA and SCL pins, the S bit

(SSPSTAT<3>) will be set. The SSPIF bit will not be set

until the baud rate generator has timed out.

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated

START condition occurs if:

• SDA is sampled low when SCL goes

from low to high.

• SCL goes low before SDA is

asserted low. This may indicate that

another master is attempting to

transmit a data "1".

FIGURE 17-20:

REPEAT START CONDITION WAVEFORM

Set S (SSPSTAT<3>)

Write to SSPCON2

occurs here.

SDA = 1,

SCL = 1

At completion of START bit,

hardware clear RSEN bit

and set SSPIF

SCL (no change)

TBRG

1st bit

SDA

Write to SSPBUF occurs here

TBRG

Falling edge of ninth clock

End of Xmit

SCL

TBRG

Sr = Repeated START

DS41159B-page 170

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

17.4.10 I²C MASTER MODE

TRANSMISSION

17.4.10.3 ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is

cleared when the slave has sent an Acknowledge

(ACK = 0), and is set when the slave does not Acknowl-

edge (ACK = 1). A slave sends an Acknowledge when

it has recognized its address (including a general call),

or when the slave has properly received its data.

Transmission of a data byte, a 7-bit address, or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPBUF register. This action will

set the buffer full flag bit, BF, and allow the baud rate

generator to begin counting and start the next transmis-

sion. Each bit of address/data will be shifted out onto

the SDA pin after the falling edge of SCL is asserted

(see data hold time specification parameter 106). SCL

is held low for one baud rate generator rollover count

(TBRG). Data should be valid before SCL is released

high (see data setup time specification parameter 107).

When the SCL pin is released high, it is held that way

for TBRG. The data on the SDA pin must remain stable

for that duration and some hold time after the next fall-

ing edge of SCL. After the eighth bit is shifted out (the

falling edge of the eighth clock), the BF flag is cleared

and the master releases SDA. This allows the slave

device being addressed to respond with an ACK bit

during the ninth bit time if an address match occurred

or if data was received properly. The status of ACK is

written into the ACKDT bit on the falling edge of the

ninth clock. If the master receives an Acknowledge, the

Acknowledge status bit, ACKSTAT, is cleared. If not,

the bit is set. After the ninth clock, the SSPIF bit is set

and the master clock (baud rate generator) is sus-

pended until the next data byte is loaded into the

SSPBUF, leaving SCL low and SDA unchanged

(Figure 17-21).

17.4.11 I²C MASTER MODE RECEPTION

Master mode reception is enabled by programming the

receive enable bit, RCEN (SSPCON2<3>).

Note: The RCEN bit should be set after ACK

sequence is complete, or the RCEN bit will

be disregarded.

The baud rate generator begins counting, and on each

rollover, the state of the SCL pin changes (high to

low/low to high) and data is shifted into the SSPSR.

After the falling edge of the eighth clock, the receive

enable flag is automatically cleared, the contents of the

SSPSR are loaded into the SSPBUF, the BF flag bit is

set, the SSPIF flag bit is set and the baud rate genera-

tor is suspended from counting, holding SCL low. The

MSSP is now in IDLE state, awaiting the next com-

mand. When the buffer is read by the CPU, the BF flag

bit is automatically cleared. The user can then send an

Acknowledge bit at the end of reception, by setting the

Acknowledge sequence enable bit, ACKEN

(SSPCON2<4>).

17.4.11.1 BF Status Flag

After the write to the SSPBUF, each bit of address will

be shifted out on the falling edge of SCL until all seven

address bits and the R/W bit are completed. On the fall-

ing edge of the eighth clock, the master will de-assert

the SDA pin, allowing the slave to respond with an

Acknowledge. On the falling edge of the ninth clock, the

master will sample the SDA pin to see if the address

was recognized by a slave. The status of the ACK bit is

loaded into the ACKSTAT status bit (SSPCON2<6>).

Following the falling edge of the ninth clock transmis-

sion of the address, the SSPIF is set, the BF flag is

cleared and the baud rate generator is turned off until

another write to the SSPBUF takes place, holding SCL

low and allowing SDA to float.

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

17.4.11.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bits

are received into the SSPSR and the BF flag bit is

already set from a previous reception.

17.4.11.3 WCOL Status Flag

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), the WCOL bit is set and the contents of the buffer

are unchanged (the write doesn’t occur).

17.4.10.1 BF Status Flag

In Transmit mode, the BF bit (SSPSTAT<0>) is set

when the CPU writes to SSPBUF and is cleared when

all 8 bits are shifted out.

17.4.10.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

WCOL must be cleared in software.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 171

PIC18FXX8

2

FIGURE 17-21:

I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

DS41159B-page 172

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

2

FIGURE 17-22:

I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 173

PIC18FXX8

17.4.12 ACKNOWLEDGE SEQUENCE

TIMING

17.4.13 STOP CONDITION TIMING

A STOP bit is asserted on the SDA pin at the end of a

receive/transmit by setting the STOP sequence enable

bit, PEN (SSPCON2<2>). At the end of a receive/trans-

mit the SCL line is held low after the falling edge of the

ninth clock. When the PEN bit is set, the master will

assert the SDA line low. When the SDA line is sampled

low, the baud rate generator is reloaded and counts

down to 0. When the baud rate generator times out, the

SCL pin will be brought high, and one TBRG (baud rate

generator rollover count) later, the SDA pin will be

de-asserted. When the SDA pin is sampled high while

SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG

later, the PEN bit is cleared and the SSPIF bit is set

(Figure 17-24).

An Acknowledge sequence is enabled by setting the

Acknowledge

sequence

enable

bit,

ACKEN

(SSPCON2<4>). When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to gen-

erate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The baud rate gen-

erator then counts for one rollover period (TBRG) and the

SCL pin is de-asserted (pulled high). When the SCL pin

is sampled high (clock arbitration), the baud rate gener-

ator counts for TBRG. The SCL pin is then pulled low. Fol-

lowing this, the ACKEN bit is automatically cleared, the

baud rate generator is turned off and the MSSP module

then goes into IDLE mode (Figure 17-23).

17.4.13.1 WCOL Status Flag

If the user writes the SSPBUF when a STOP sequence

is in progress, then the WCOL bit is set and the con-

tents of the buffer are unchanged (the write doesn’t

occur).

17.4.12.1 WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the con-

tents of the buffer are unchanged (the write doesn’t occur).

FIGURE 17-23:

ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,

Write to SSPCON2

ACKEN automatically cleared

ACKEN = 1, ACKDT = 0

TBRG

ACK

TBRG

SDA

SCL

D0

8

9

SSPIF

Cleared in

Set SSPIF at the end

of receive

Cleared in

software

Set SSPIF at the end

of Acknowledge sequence

Note: TBRG = one baud rate generator period.

DS41159B-page 174

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 17-24:

STOP CONDITION RECEIVE OR TRANSMIT MODE

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

after SDA sampled high. P bit (SSPSTAT<4>) is set.

Write to SSPCON2

Set PEN

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

Falling edge of

9th clock

TBRG

SCL

SDA

ACK

P

TBRG

SCL brought high after TBRG

SDA asserted low before rising edge of clock

to setup STOP condition.

Note: TBRG = one baud rate generator period.

17.4.14 SLEEP OPERATION

17.4.17 MULTI -MASTER

COMMUNICATION, BUS COLLISION

While in SLEEP mode, the I²C module can receive

addresses or data, and when an address match or

complete byte transfer occurs, wake the processor

from SLEEP (if the MSSP interrupt is enabled).

AND BUS ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a '1' on SDA, by letting SDA float high and

another master asserts a '0'. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a '1' and the data sampled on the SDA pin = '0',

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag BCLIF and reset the I²C

port to its IDLE state (Figure 17-25).

17.4.15 EFFECT OF A RESET

A RESET disables the MSSP module and terminates

the current transfer.

17.4.16 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the START and STOP conditions allows

the determination of when the bus is free. The STOP

(P) and START (S) bits are cleared from a RESET or

when the MSSP module is disabled. Control of the I²C

bus may be taken when the P bit (SSPSTAT<4>) is set,

or the bus is idle with both the S and P bits clear. When

the bus is busy, enabling the SSP interrupt will gener-

ate the interrupt when the STOP condition occurs.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are de-asserted, and

the SSPBUF can be written to. When the user services

the bus collision Interrupt Service Routine, and if the

I²C bus is free, the user can resume communication by

asserting a START condition.

If a START, Repeated START, STOP, or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL

lines are de-asserted, and the respective control bits in

the SSPCON2 register are cleared. When the user ser-

vices the bus collision Interrupt Service Routine, and if

the I²C bus is free, the user can resume communication

by asserting a START condition.

In multi-master operation, the SDA line must be moni-

tored for arbitration, to see if the signal level is the

expected output level. This check is performed in

hardware, with the result placed in the BCLIF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

The master will continue to monitor the SDA and SCL

pins. If a STOP condition occurs, the SSPIF bit will be set.

• A START Condition

• A Repeated START Condition

• An Acknowledge Condition

A write to the SSPBUF will start the transmission of

data at the first data bit, regardless of where the trans-

mitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of START and STOP conditions allows the

determination of when the bus is free. Control of the I²C

bus can be taken when the P bit is set in the SSPSTAT

register, or the bus is IDLE and the S and P bits are

cleared.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 175

PIC18FXX8

FIGURE 17-25:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,

data doesn’t match what is driven

by the master.

SDA line pulled low

by another source

Data changes

while SCL = 0

Bus collision has occurred.

SDA released

by master

SDA

SCL

Set bus collision

interrupt (BCLIF)

BCLIF

DS41159B-page 176

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 17-28). If, however, a '1' is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The baud rate generator is then reloaded and

counts down to 0, and during this time, if the SCL pins

are sampled as '0', a bus collision does not occur. At

the end of the BRG count, the SCLpin is asserted low.

17.4.17.1 Bus Collision During a START

Condition

During a START condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning of

the START condition (Figure 17-26).

b) SCL is sampled low before SDA is asserted low

(Figure 17-27).

During a START condition, both the SDA and the SCL

pins are monitored.

Note: The reason that bus collision is not a factor

during a START condition is that no two

bus masters can assert a START condition

at the exact same time. Therefore, one

master will always assert SDA before the

other. This condition does not cause a bus

collision, because the two masters must be

allowed to arbitrate the first address follow-

ing the START condition. If the address is

the same, arbitration must be allowed to

continue into the data portion, Repeated

START or STOP conditions.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the START condition is aborted,

• the BCLIF flag is set, and

•

the MSSP module is reset to its IDLE state

(Figure 17-26).

The START condition begins with the SDA and SCL

pins de-asserted. When the SDA pin is sampled high,

the baud rate generator is loaded from SSPADD<6:0>

and counts down to 0. If the SCL pin is sampled low

while SDA is high, a bus collision occurs, because it is

assumed that another master is attempting to drive a

data '1' during the START condition.

FIGURE 17-26:

BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.

Set BCLIF,

S bit and SSPIF set because

SDA = 0, SCL = 1.

SDA

SCL

SEN

Set SEN, enable START

condition if SDA = 1, SCL=1

SEN cleared automatically because of bus collision.

SSP module reset into IDLE state.

SDA sampled low before

START condition.

Set BCLIF.

S bit and SSPIF set because

SDA = 0, SCL = 1.

BCLIF

SSPIF and BCLIF are

cleared in software.

S

SSPIF

SSPIF and BCLIF are

cleared in software.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 177

PIC18FXX8

FIGURE 17-27:

BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1

TBRG

SDA

Set SEN, enable START

sequence if SDA = 1, SCL = 1

SCL

SEN

SCL = 0 before SDA = 0,

bus collision occurs. Set BCLIF.

SCL = 0 before BRG time-out,

bus collision occurs. Set BCLIF.

BCLIF

Interrupt cleared

in software

S

’0’

SSPIF

FIGURE 17-28:

BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA = 0, SCL = 1

Set S

Set SSPIF

Less than TBRG

TBRG

SDA pulled low by other master.

Reset BRG and assert SDA.

SDA

SCL

S

SCL pulled low after BRG

Time-out

SEN

Set SEN, enable START

sequence if SDA = 1, SCL = 1

’0’

BCLIF

S

SSPIF

Interrupts cleared

in software

SDA = 0, SCL = 1

Set SSPIF

DS41159B-page 178

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

reloaded and begins counting. If SDA goes from high to

low before the BRG times out, no bus collision occurs

because no two masters can assert SDA at exactly the

same time.

17.4.17.2 Bus Collision During a Repeated

START Condition

During a Repeated START condition, a bus collision

occurs if:

If SCL goes from high to low before the BRG times out

and SDA has not already been asserted, a bus collision

occurs. In this case, another master is attempting to

transmit a data ’1’ during the Repeated START

condition, Figure 17-30.

a) A low level is sampled on SDA when SCL goes

from low level to high level.

b) SCL goes low before SDA is asserted low, indi-

cating that another master is attempting to

transmit a data ’1’.

If, at the end of the BRG time-out both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated START condition is

complete.

When the user de-asserts SDA and the pin is allowed

to float high, the BRG is loaded with SSPADD<6:0>

and counts down to 0. The SCL pin is then de-asserted,

and when sampled high, the SDA pin is sampled.

If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit

a

data ’0’,

Figure 17-29). If SDA is sampled high, the BRG is

FIGURE 17-29:

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.

RSEN

BCLIF

Cleared in software

'0'

S

'0'

SSPIF

FIGURE 17-30:

BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG

SDA

SCL

SCL goes low before SDA,

BCLIF

RSEN

Set BCLIF. Release SDA and SCL.

Interrupt cleared

in software

’0’

S

SSPIF

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 179

PIC18FXX8

The STOP condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

float. When the pin is sampled high (clock arbitration),

the baud rate generator is loaded with SSPADD<6:0>

and counts down to 0. After the BRG times out, SDA is

sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ’0’ (Figure 17-31). If the SCL pin is sampled

low before SDA is allowed to float high, a bus collision

occurs. This is another case of another master

attempting to drive a data ’0’ (Figure 17-32).

17.4.17.3 Bus Collision During a STOP

Condition

Bus collision occurs during a STOP condition if:

a) After the SDA pin has been de-asserted and

allowed to float high, SDA is sampled low after

the BRG has timed out.

b) After the SCL pin is de-asserted, SCL is sam-

pled low before SDA goes high.

FIGURE 17-31:

BUS COLLISION DURING A STOP CONDITION (CASE 1)

SDA sampled

TBRG

low after TBRG,

Set BCLIF

SDA

SDA asserted low

SCL

PEN

BCLIF

P

’0’

SSPIF

FIGURE 17-32:

BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG

SDA

SCL goes low before SDA goes high

Set BCLIF

Assert SDA

SCL

PEN

BCLIF

P

’0’

SSPIF

DS41159B-page 180

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

The USART can be configured in the following modes:

18.0 ADDRESSABLE UNIVERSAL

SYNCHRONOUS

• Asynchronous (full duplex)

• Synchronous - Master (half duplex)

• Synchronous - Slave (half duplex).

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

The SPEN (RCSTA register) and the TRISC<7> bits

have to be set and the TRISC<6> bit must be cleared,

in order to configure pins RC6/TX/CK and RC7/RX/DT

as the Universal Synchronous Asynchronous Receiver

Transmitter.

The Universal Synchronous Asynchronous Receiver

Transmitter (USART) module is one of the three serial

I/O modules incorporated into PIC18FXX8 devices.

(USART is also known as a Serial Communications

Interface or SCI.) The USART can be configured as a

full duplex asynchronous system that can communi-

cate with peripheral devices, such as CRT terminals

and personal computers, or it can be configured as a

half duplex synchronous system that can communicate

with peripheral devices, such as A/D or D/A integrated

circuits, Serial EEPROMs, etc.

Register 18-1 shows the Transmit Status and Control

Register (TXSTA) and Register 18-2 shows the

Receive Status and Control Register (RCSTA).

REGISTER 18-1: TXSTA REGISTER

R/W-0

CSRC

R/W-0

TX9

R/W-0

TXEN

R/W-0

SYNC

U-0

—

R/W-0

BRGH

R-1

R/W-0

TX9D

TRMT

bit 7

bit 0

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1= Master mode (Clock generated internally from BRG)

0= Slave mode (Clock from external source)

bit 6

bit 5

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

TXEN: Transmit Enable bit

1= Transmit enabled

0= Transmit disabled

Note: SREN/CREN overrides TXEN in SYNC mode.

bit 4

SYNC: USART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

bit 3

bit 2

Unimplemented: Read as '0'

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: 9th bit of Transmit Data

Can be address/data bit or a parity bit

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’0’ = Bit is cleared

x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 181

PIC18FXX8

REGISTER 18-2: RCSTA REGISTER

R/W-0

SPEN

R/W-0

RX9

R/W-0

SREN

R/W-0

CREN

R/W-0

R-0

R-x

ADDEN

FERR

OERR

RX9D

bit 7

bit 0

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit

1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0= Serial port disabled

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode - Master:

1= Enables single receive

0= Disables single receive (this bit is cleared after reception is complete.)

Synchronous mode - Slave:

Unused in this mode

bit 4

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables continuous receive

0= Disables continuous receive

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enables interrupt and load of the receive buffer when RSR<8>

is set

0= Disables address detection, all bytes are received, and ninth bit can be used as parity bit

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receive next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: 9th bit of Received Data

Can be address/data bit or a parity bit

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41159B-page 182

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Example 18-1 shows the calculation of the baud rate

error for the following conditions:

18.1 USART Baud Rate Generator

(BRG)

FOSC = 16 MHz

Desired Baud Rate = 9600

BRGH = 0

The BRG supports both the Asynchronous and Syn-

chronous modes of the USART. It is a dedicated 8-bit

baud rate generator. The SPBRG register controls the

period of a free running 8-bit timer. In Asynchronous

mode, bit BRGH (TXSTA register) also controls the

baud rate. In Synchronous mode, bit BRGH is ignored.

Table 18-1 shows the formula for computation of the

baud rate for different USART modes, which only apply

in Master mode (internal clock).

SYNC = 0

It may be advantageous to use the high baud rate

(BRGH = 1), even for slower baud clocks. This is

because the FOSC/(16(X + 1)) equation can reduce the

baud rate error in some cases.

Writing a new value to the SPBRG register causes the

BRG timer to be reset (or cleared). This ensures the

BRG does not wait for a timer overflow before

outputting the new baud rate.

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRG register can be calculated

using the formula in Table 18-1. From this, the error in

baud rate can be determined.

18.1.1

SAMPLING

The data on the RC7/RX/DT pin is sampled three times

by a majority detect circuit to determine if a high or a

low level is present at the RX pin.

EXAMPLE 18-1:

CALCULATING BAUD RATE ERROR

Desired Baud Rate

Solving for X:

= FOSC / (64 (X + 1))

X

= ( (FOSC / Desired Baud Rate) / 64 ) - 1

= ((16000000 / 9600) / 64) - 1

= [25.042] = 25

Calculated Baud Rate

Error

= 16000000 / (64 (25 + 1))

= 9615

= (Calculated Baud Rate - Desired Baud Rate)

Desired Baud Rate

= (9615 - 9600) / 9600

= 0.16%

TABLE 18-1: BAUD RATE FORMULA

SYNC

BRGH = 0 (Low Speed)

BRGH = 1 (High Speed)

0

1

(Asynchronous) Baud Rate = FOSC/(64(X+1))

(Synchronous) Baud Rate = FOSC/(4(X+1))

Baud Rate = FOSC/(16(X+1))

NA

Legend: X = value in SPBRG (0 to 255)

TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TXSTA

RCSTA

SPBRG

CSRC

SPEN

TX9

RX9

TXEN SYNC

—

BRGH TRMT TX9D 0000 -010

0000 -010

0000 000x

0000 0000

SREN CREN ADDEN FERR OERR RX9D 0000 000x

0000 0000

Baud Rate Generator Register

Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 183

PIC18FXX8

TABLE 18-3: BAUD RATES FOR SYNCHRONOUS MODE

FOSC = 40 MHz

33 MHz

25 MHz

20 MHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

NA

-

NA

-

NA

-

NA

-

9.6

NA

-

NA

-

NA

-

NA

-

19.2

76.8

96

NA

-

NA

-

NA

-

NA

-

76.92

96.15

303.03

500

+0.16

129

103

32

19

0

77.10

95.93

294.64

485.30

8250

32.23

+0.39

-0.07

-1.79

-2.94

-

106

85

27

16

0

77.16

96.15

297.62

480.77

6250

24.41

+0.47

+0.16

-0.79

-3.85

-

80

64

20

12

0

76.92

96.15

294.12

500

+0.16

64

51

16

9

+0.16

300

500

HIGH

LOW

+1.01

-1.96

0

-

0

-

10000

39.06

5000

19.53

0

-

255

-

255

-

255

-

255

FOSC = 16 MHz

10 MHz

7.15909 MHz

5.0688 MHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

NA

-

NA

-

NA

-

NA

-

9.6

NA

-

+0.16

-0.79

+2.56

0

-

NA

-

+0.16

-1.36

+0.16

+4.17

0

-

9.62

+0.23

+1.32

-1.88

-0.57

-10.51

-

185

92

22

18

5

9.60

0

131

65

16

12

3

19.2

76.8

96

19.23

76.92

95.24

307.70

500

207

51

41

12

7

19.23

75.76

96.15

312.50

500

129

32

25

7

19.24

77.82

94.20

298.35

447.44

1789.80

6.99

19.20

74.54

97.48

316.80

422.40

1267.20

4.95

-2.94

+1.54

+5.60

-15.52

-

300

500

HIGH

LOW

4

3

2

4000

15.63

-

0

2500

9.77

-

0

-

255

-

255

-

255

-

255

FOSC = 4 MHz

3.579545 MHz

1 MHz

32.768 kHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

1.20

2.40

9.62

19.23

83.33

250

-

207

103

25

12

2

0.30

1.17

2.73

8.20

NA

+1.14

26

-

+0.16

+8.51

-13.19

-16.67

-

-2.48

6

2.4

NA

-

NA

-

+13.78

2

9.6

9.62

19.23

76.92

1000

333.33

500

+0.16

+4.17

+11.11

0

103

51

12

9

9.62

+0.23

-0.83

-2.90

+3.57

-0.57

-10.51

-

92

46

11

8

-14.67

0

19.2

76.8

96

19.04

74.57

99.43

298.30

447.44

894.89

3.50

-

NA

-

2

NA

-

300

500

HIGH

LOW

2

0

NA

-

1

NA

-

NA

1000

3.91

-

0

250

-

0

8.20

0.03

0

-

255

-

255

0.98

-

255

DS41159B-page 184

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 18-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)

FOSC = 40 MHz

33 MHz

25 MHz

20 MHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

KBAUD

ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

NA

-

2.40

-0.07

-0.54

-4.09

+7.42

-14.06

-

214

53

26

6

2.40

9.53

19.53

78.13

97.66

NA

-0.15

162

40

19

4

2.40

+0.16

-1.36

+1.73

+8.51

+4.17

-

129

32

15

3

9.6

9.62

18.94

78.13

89.29

312.50

625

+0.16

-1.36

+1.73

-6.99

+4.17

+25.00

-

64

32

7

9.55

-0.76

9.47

19.2

76.8

96

19.10

73.66

103.13

257.81

NA

+1.73

19.53

78.13

104.17

312.50

NA

+1.73

6

4

+1.73

3

2

300

500

HIGH

LOW

1

-

0

-

NA

-

625

0

515.63

2.01

-

0

390.63

1.53

0

312.50

1.22

-

0

2.44

-

255

-

255

-

255

FOSC = 16 MHz

10 MHz

7.15909 MHz

5.0688 MHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

KBAUD

ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

NA

1.20

2.40

9.62

19.23

83.33

250

-

207

103

25

12

2

NA

1.20

-

129

64

15

7

NA

1.20

2.38

9.32

18.64

111.86

NA

-

92

46

11

5

NA

1.20

2.40

9.90

19.80

79.20

NA

-

65

32

7

+0.16

+8.51

-13.19

-16.67

-

+0.16

+1.73

-18.62

-47.92

-

+0.23

0

2.4

2.40

-0.83

0

9.6

9.77

-2.90

+3.13

19.2

76.8

96

19.53

78.13

156.25

NA

-2.90

+3.13

3

1

+45.65

0

+3.13

0

2

1

-

300

500

HIGH

LOW

0

NA

-

NA

-

NA

-

NA

-

NA

-

250

-

0

156.25

0.61

-

0

111.86

0.44

0

79.20

0.31

0

0.98

-

255

-

255

FOSC = 4 MHz

3.579545 MHz

%

1 MHz

32.768 kHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

KBAUD

ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

0.30

1.20

2.40

8.93

20.83

62.50

NA

-0.16

207

51

25

6

0.30

1.19

2.43

9.32

18.64

55.93

NA

+0.23

185

46

22

5

0.30

1.20

2.23

7.81

15.63

NA

+0.16

51

12

6

0.26

NA

-14.67

1

+1.67

-0.83

+0.16

-

2.4

+1.67

+1.32

-6.99

NA

-

9.6

-6.99

-2.90

-18.62

1

NA

-

19.2

76.8

96

+8.51

2

-2.90

2

-18.62

0

NA

-

-18.62

0

-27.17

0

-

NA

-

NA

-

NA

-

300

500

HIGH

LOW

NA

-

NA

-

NA

-

NA

-

NA

-

NA

-

NA

-

NA

62.50

0.24

0

55.93

0.22

0

15.63

0.06

0

0.51

0.002

0

255

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 185

PIC18FXX8

TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)

FOSC = 40 MHz

33 MHz

25 MHz

20 MHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

NA

-

NA

-

NA

-

NA

-

9.6

NA

-

+0.16

-1.36

+0.16

+4.17

0

-

9.60

-0.07

+0.39

-0.54

+2.31

-1.79

+3.13

-

214

106

26

20

6

9.59

-0.15

+0.47

+1.73

+4.17

-

162

80

19

15

4

9.62

+0.16

+1.73

+0.16

+4.17

-16.67

-

129

64

15

12

3

19.2

76.8

96

19.23

75.76

96.15

312.50

500

129

32

25

7

19.28

76.39

98.21

294.64

515.63

2062.50

8,06

19.30

78.13

97.66

312.50

520.83

1562.50

6.10

19.23

78.13

96.15

312.50

416.67

1250

4.88

300

500

HIGH

LOW

4

3

2

2500

9.77

-

0

-

255

-

255

-

255

-

255

FOSC = 16 MHz

10 MHz

7.15909 MHz

5.0688 MHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

NA

-

+0.16

+4.17

+11.11

0

-

NA

-

2.41

+0.23

-0.83

+1.32

-2.90

-6.78

+49.15

-10.51

-

185

46

22

5

2.40

0

131

32

16

3

9.6

9.62

19.23

76.92

100

103

51

12

9

9.62

18.94

78.13

89.29

312.50

625

+0.16

-1.36

+1.73

-6.99

+4.17

+25.00

-

64

32

7

9.52

9.60

0

-2.94

+3.13

+10.00

+5.60

-

19.2

76.8

96

19.45

74.57

89.49

447.44

1.75

18.64

79.20

105.60

316.80

NA

6

4

2

300

500

HIGH

LOW

333.33

500

2

1

0

1

0

-

1000

3.91

-

0

625

0

316.80

1.24

-

0

-

255

2.44

-

255

-

255

-

255

FOSC = 4 MHz

3.579545 MHz

1 MHz

32.768 kHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

0.3

1.2

NA

1.20

2.40

9.62

19.23

NA

-

207

103

25

12

-

NA

1.20

-

+0.23

+1.32

-2.90

+16.52

-25.43

-

185

92

22

11

2

0.30

1.20

2.40

8.93

20.83

62.50

NA

+0.16

207

51

25

6

0.29

1.02

2.05

NA

-2.48

6

+0.16

-14.67

1

2.4

+0.16

2.41

+0.16

-14.67

0

9.6

+0.16

9.73

-6.99

-

19.2

76.8

96

+0.16

18.64

74.57

111.86

223.72

NA

+8.51

2

NA

-

-18.62

0

NA

-

NA

-

1

-

NA

-

300

500

HIGH

LOW

NA

-

0

NA

-

NA

-

NA

-

NA

-

NA

250

0.98

0

55.93

0.22

-

0

62.50

0.24

0

2.05

0.008

0

255

-

255

DS41159B-page 186

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

empty and flag bit TXIF (PIR registers) is set. This inter-

rupt can be enabled/disabled by setting/clearing

enable bit TXIE (PIE registers). Flag bit TXIF will be

set, regardless of the state of enable bit TXIE and can-

not be cleared in software. It will reset only when new

data is loaded into the TXREG register. While flag bit

TXIF indicated the status of the TXREG register,

another bit TRMT (TXSTA register) shows the status of

the TSR register. Status bit TRMT is a read only bit,

which is set when the TSR register is empty. No inter-

rupt logic is tied to this bit, so the user has to poll this

bit in order to determine if the TSR register is empty.

18.2 USART Asynchronous Mode

In this mode, the USART uses standard non-return-to-

zero (NRZ) format (one START bit, eight or nine data

bits and one STOP bit). The most common data format

is 8 bits. An on-chip dedicated 8-bit baud rate generator

can be used to derive standard baud rate frequencies

from the oscillator. The USART transmits and receives

the LSb first. The USART’s transmitter and receiver are

functionally independent, but use the same data format

and baud rate. The baud rate generator produces a

clock, either x16 or x64 of the bit shift rate, depending

on the BRGH bit (TXSTA register). Parity is not sup-

ported by the hardware, but can be implemented in

software (and stored as the ninth data bit).

Asynchronous mode is stopped during SLEEP.

Note 1: The TSR register is not mapped in data

memory, so it is not available to the user.

2: Flag bit TXIF is set when enable bit TXEN

is set.

Asynchronous mode is selected by clearing the SYNC

bit (TXSTA register).

Steps to follow when setting up an Asynchronous

Transmission:

The USART Asynchronous module consists of the

following important elements:

1. Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is desired,

set bit BRGH (Section 18.1).

• Baud Rate Generator

• Sampling Circuit

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

• Asynchronous Transmitter

• Asynchronous Receiver.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set transmit bit

TX9. Can be used as address/data bit.

18.2.1

USART ASYNCHRONOUS

TRANSMITTER

5. Enable the transmission by setting bit TXEN,

which will also set bit TXIF.

The USART transmitter block diagram is shown in

Figure 18-1. The heart of the transmitter is the Transmit

(serial) Shift Register (TSR). The TSR register obtains

its data from the Read/Write Transmit Buffer register

(TXREG). The TXREG register is loaded with data in

software. The TSR register is not loaded until the STOP

bit has been transmitted from the previous load. As

soon as the STOP bit is transmitted, the TSR is loaded

with new data from the TXREG register (if available).

Once the TXREG register transfers the data to the TSR

register (occurs in one TCY), the TXREG register is

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Load data to the TXREG register (starts

transmission).

Note:

TXIF is not cleared immediately upon load-

ing data into the transmit buffer TXREG. The

flag bit becomes valid in the second instruc-

tion cycle following the load instruction.

FIGURE 18-1:

USART TRANSMIT BLOCK DIAGRAM

Data Bus

TXIF

TXREG register

8

TXIE

MSb

(8)

LSb

0

Pin Buffer

and Control

•

• •

TSR register

RC6/TX/CK pin

Interrupt

TXEN

Baud Rate CLK

TRMT

SPEN

SPBRG

Baud Rate Generator

TX9

TX9D

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 187

PIC18FXX8

FIGURE 18-2:

ASYNCHRONOUS TRANSMISSION

Write to TXREG

Word 1

BRG Output

(Shift Clock)

RC6/TX/CK (pin)

START bit

bit 0

bit 1

Word 1

bit 7/8

STOP bit

TXIF bit

(Transmit Buffer

Register Empty Flag)

Word 1

Transmit Shift Reg

TRMT bit

(Transmit Shift

Register Empty Flag)

FIGURE 18-3:

ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

Write to TXREG

Word 1

Word 2

BRG Output

(Shift Clock)

RC6/TX/CK (pin)

START bit

Word 2

bit 0

bit 1

bit 7/8

bit 0

STOP bit

TXIF bit

(Interrupt Reg. Flag)

Word 1

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Transmit Shift Reg.

Word 2

Transmit Shift Reg.

Note: This timing diagram shows two consecutive transmissions.

TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF

RBIF 0000 000x 0000 000u

PIR1

PSPIF

PSPIE

PSPIP

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

PIE1

IPR1

RCSTA

SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

TXREG USART Transmit Register

TXSTA CSRC TX9 TXEN SYNC

SPBRG Baud Rate Generator Register

Legend: x= unknown, - = unimplemented locations read as '0'.

Shaded cells are not used for Asynchronous Transmission.

0000 0000 0000 0000

—

BRGH TRMT TX9D 0000 -010 0000 -010

0000 0000 0000 0000

DS41159B-page 188

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

18.2.2

USART ASYNCHRONOUS

RECEIVER

18.2.3

SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

The receiver block diagram is shown in Figure 18-4.

The data is received on the RC7/RX/DT pin and drives

the data recovery block. The data recovery block is

actually a high speed shifter, operating at x16 times the

baud rate, whereas the main receive serial shifter oper-

ates at the bit rate, or at FOSC. This mode would

typically be used in RS-232 systems.

This mode would typically be used in RS-485 systems.

Steps to follow when setting up an Asynchronous

Reception with Address Detect Enable:

1. Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is required,

set the BRGH bit.

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

Steps to follow when setting up an Asynchronous

Reception:

3. If interrupts are required, set the RCEN bit and

select the desired priority level with the RCIP bit.

1. Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is desired,

set bit BRGH (Section 18.1).

4. Set the RX9 bit to enable 9-bit reception.

5. Set the ADDEN bit to enable address detect.

6. Enable reception by setting the CREN bit.

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

7. The RCIF bit will be set when reception is com-

plete. The interrupt will be Acknowledged if the

RCIE and GIE bits are set.

3. If interrupts are desired, set enable bit RCIE.

4. If 9-bit reception is desired, set bit RX9.

5. Enable the reception by setting bit CREN.

8. Read the RCSTA register to determine if any

error occurred during reception, as well as read

bit 9 of data (if applicable).

6. Flag bit RCIF will be set when reception is com-

plete and an interrupt will be generated if enable

bit RCIE was set.

9. Read RCREG to determine if the device is being

addressed.

7. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. If any error occurred, clear the CREN bit.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and interrupt the CPU.

8. Read the 8-bit received data by reading the

RCREG register.

9. If any error occurred, clear the error by clearing

enable bit CREN.

FIGURE 18-4:

USART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK

FERR

OERR

CREN

SPBRG

÷ 64

or

÷ 16

RSR Register

MSb

LSb

0

Baud Rate Generator

7

1

STOP (8)

START

• • •

RC7/RX/DT

Pin Buffer

and Control

Data

Recovery

RX9

RX9D

SPEN

RCREG Register

FIFO

8

RCIF

RCIE

Interrupt

Data Bus

Note: I/O pins have diode protection to VDD and VSS.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 189

PIC18FXX8

FIGURE 18-5:

ASYNCHRONOUS RECEPTION

START

bit

START

bit

START

bit7/8 STOP bit

bit

RX (pin)

bit0

bit1

STOP

bit

STOP

bit

bit0

bit7/8

Rcv shift

Reg

Rcv Buffer Reg

Word 2

RCREG

Word 1

RCREG

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

TABLE 18-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

TMR0IF INT0IF

RBIF

0000 000x 0000 000u

PSPIF

PSPIE

PSPIP

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TXIF

TXIE

TXIP

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

PIE1

IPR1

RCSTA

RCREG

TXSTA

SPBRG

CREN ADDEN

FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

0000 -010 0000 -010

0000 0000 0000 0000

USART Receive Register

CSRC TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

Baud Rate Generator Register

Legend: x= unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.

DS41159B-page 190

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

(PIE registers). Flag bit TXIF will be set, regardless of

the state of enable bit TXIE and cannot be cleared in

software. It will reset only when new data is loaded into

the TXREG register. While flag bit TXIF indicates the

status of the TXREG register, another bit TRMT

(TXSTA register) shows the status of the TSR register.

TRMT is a read only bit, which is set when the TSR is

empty. No interrupt logic is tied to this bit, so the user

has to poll this bit in order to determine if the TSR reg-

ister is empty. The TSR is not mapped in data memory,

so it is not available to the user.

18.3 USART Synchronous Master

Mode

In Synchronous Master mode, the data is transmitted in

a half-duplex manner (i.e., transmission and reception

do not occur at the same time). When transmitting data,

the reception is inhibited and vice versa. Synchronous

mode is entered by setting bit SYNC (TXSTA register).

In addition, enable bit SPEN (RCSTA register) is set, in

order to configure the RC6/TX/CK and RC7/RX/DT I/O

pins to CK (clock) and DT (data) lines, respectively. The

Master mode indicates that the processor transmits the

master clock on the CK line. The Master mode is

entered by setting bit CSRC (TXSTA register).

Steps to follow when setting up a Synchronous Master

Transmission:

1. Initialize the SPBRG register for the appropriate

baud rate (Section 18.1).

18.3.1

USART SYNCHRONOUS MASTER

TRANSMISSION

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

The USART transmitter block diagram is shown in

Figure 18-1. The heart of the transmitter is the Transmit

(serial) Shift register (TSR). The shift register obtains

its data from the Read/Write Transmit Buffer register

(TXREG). The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCY), the TXREG is empty and interrupt

bit TXIF (PIR registers) is set. The interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting bit TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmission by loading data to the TXREG

register.

Note:

TXIF is not cleared immediately upon load-

ing data into the transmit buffer TXREG. The

flag bit becomes valid in the second instruc-

tion cycle following the load instruction.

TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

CCP1IF

INT0IF

RBIF

0000 000x 0000 000u

PIR1

PSPIF

PSPIE

PSPIP

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TXIF

TXIE

TXIP

TMR2IF TMR1IF 0000 0000 0000 0000

PIE1

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

IPR1

RCSTA

CREN ADDEN

FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

0000 -010 0000 -010

0000 0000 0000 0000

TXREG USART Transmit Register

TXSTA CSRC TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

SPBRG Baud Rate Generator Register

Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 191

PIC18FXX8

FIGURE 18-6:

SYNCHRONOUS TRANSMISSION

Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

bit 7

RC7/RX/DT

bit 0

bit 1

bit 2

bit 7

bit 0

bit 1

Word 2

Word 1

RC6/TX/CK

Write to

TXREG Reg

Write Word 1

Write Word 2

TXIF bit

(Interrupt Flag)

TRMT

TRMT bit

’1’

TXEN bit

Note: Sync Master mode; SPBRG = ’0’; continuous transmission of two 8-bit words.

FIGURE 18-7:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RC7/RX/DT pin

bit0

bit1

bit2

bit6

bit7

RC6/TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

TXEN bit

DS41159B-page 192

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Steps to follow when setting up a Synchronous Master

Reception:

18.3.2

USART SYNCHRONOUS MASTER

RECEPTION

1. Initialize the SPBRG register for the appropriate

baud rate (Section 18.1).

Once Synchronous Master mode is selected, reception

is enabled by setting either enable bit SREN (RCSTA

register), or enable bit CREN (RCSTA register). Data is

sampled on the RC7/RX/DT pin on the falling edge of

the clock. If enable bit SREN is set, only a single word

is received. If enable bit CREN is set, the reception is

continuous until CREN is cleared. If both bits are set,

then CREN takes precedence.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Ensure bits CREN and SREN are clear.

4. If interrupts are desired, set enable bit RCIE.

5. If 9-bit reception is desired, set bit RX9.

6. If a single reception is required, set bit SREN.

For continuous reception, set bit CREN.

7. Interrupt flag bit RCIF will be set when reception

is complete and an interrupt will be generated if

the enable bit RCIE was set.

8. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

9. Read the 8-bit received data by reading the

RCREG register.

10. If any error occurred, clear the error by clearing

bit CREN.

TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

SSPIF

SSPIE

SSPIP

ADDEN

TMR0IF INT0IF

RBIF

0000 000x 0000 000u

PSPIF

PSPIE

PSPIP

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TXIF

TXIE

TXIP

CREN

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

PIE1

IPR1

RCSTA

RCREG

TXSTA

SPBRG

FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

0000 -010 0000 -010

0000 0000 0000 0000

USART Receive Register

CSRC TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

Baud Rate Generator Register

Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.

FIGURE 18-8:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3

Q2

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q4 Q1

RC7/RX/DT pin

RC6/TX/CK pin

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

Write to

bit SREN

SREN bit

CREN bit

’0’

RCIF bit

(Interrupt)

Read

RXREG

Note: Timing diagram demonstrates Sync Master mode with bit SREN = ’1’ and bit BRGH = ’0’.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 193

PIC18FXX8

18.4.2

USART SYNCHRONOUS SLAVE

RECEPTION

18.4 USART Synchronous Slave Mode

Synchronous Slave mode differs from the Master

mode, in that the shift clock is supplied externally at the

RC6/TX/CK pin (instead of being supplied internally in

Master mode). This allows the device to transfer or

receive data while in SLEEP mode. Slave mode is

entered by clearing bit CSRC (TXSTA register).

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the SLEEP

mode and bit SREN, which is a "don’t care" in Slave

mode.

If receive is enabled by setting bit CREN prior to the

SLEEPinstruction, then a word may be received during

SLEEP. On completely receiving the word, the RSR

register will transfer the data to the RCREG register,

and if enable bit RCIE bit is set, the interrupt generated

will wake the chip from SLEEP. If the global interrupt is

enabled, the program will branch to the interrupt vector.

18.4.1

USART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the Synchronous Master and Slave

modes are identical, except in the case of the SLEEP

mode.

Steps to follow when setting up a Synchronous Slave

Reception:

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

1. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in TXREG register.

c) Flag bit TXIF will not be set.

2. If interrupts are desired, set enable bit RCIE.

3. If 9-bit reception is desired, set bit RX9.

4. To enable reception, set enable bit CREN.

d) When the first word has been shifted out of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit TXIF will be set.

5. Flag bit RCIF will be set when reception is com-

plete. An interrupt will be generated if enable bit

RCIE was set.

e) If enable bit TXIE is set, the interrupt will wake

the chip from SLEEP. If the global interrupt is

enabled, the program will branch to the interrupt

vector.

6. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

Steps to follow when setting up a Synchronous Slave

Transmission:

7. Read the 8-bit received data by reading the

RCREG register.

1. Enable the synchronous slave serial port by set-

ting bits SYNC and SPEN and clearing bit

CSRC.

8. If any error occurred, clear the error by clearing

bit CREN.

2. Clear bits CREN and SREN.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting enable bit

TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmission by loading data to the TXREG

register.

DS41159B-page 194

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

TMR0IF INT0IF

RBIF

0000 000x 0000 000u

PSPIF

PSPIE

PSPIP

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TXIF

TXIE

SSPIF

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

IPR1

TXIP

RCSTA

TXREG

TXSTA

SPBRG

CREN

ADDEN

FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

0000 -010 0000 -010

0000 0000 0000 0000

USART Transmit Register

CSRC TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

Baud Rate Generator Register

Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Transmission.

TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Value on

POR,

Value on all

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

other

BOR

RESETS

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

SSPIF

SSPIE

SSPIP

ADDEN

TMR0IF INT0IF

RBIF

0000 000x 0000 000u

PSPIF

PSPIE

PSPIP

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TXIF

TXIE

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

PIE1

IPR1

TXIP

RCSTA

RCREG

TXSTA

SPBRG

CREN

FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

0000 -010 0000 -010

0000 0000 0000 0000

USART Receive Register

CSRC TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

Baud Rate Generator Register

Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Reception.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 195

PIC18FXX8

NOTES:

DS41159B-page 196

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

19.1.1

OVERVIEW OF THE MODULE

19.0 CAN MODULE

19.1 Overview

The CAN bus module consists of a protocol engine and

message buffering and control. The CAN protocol

engine handles all functions for receiving and transmit-

ting messages on the CAN bus. Messages are trans-

mitted by first loading the appropriate data registers.

Status and errors can be checked by reading the

appropriate registers. Any message detected on the

CAN bus is checked for errors and then matched

against filters to see if it should be received and stored

in one of the 2 receive registers.

The Controller Area Network (CAN) module is a serial

interface, useful for communicating with other peripher-

als or microcontroller devices. This interface/protocol

was designed to allow communications within noisy

environments.

The CAN module is a communication controller, imple-

menting the CAN 2.0 A/B protocol as defined in the

BOSCH specification. The module will support CAN

1.2, CAN 2.0A, CAN2.0B Passive, and CAN 2.0B

Active versions of the protocol. The module implemen-

tation is a full CAN system. The CAN specification is

not covered within this data sheet. The reader may

refer to the BOSCH CAN specification for further

details.

The CAN Module supports the following frame types:

• Standard Data Frame

• Extended Data Frame

• Remote Frame

• Error Frame

• Overload Frame Reception

• Interframe Space

The module features are as follows:

• Implementation of the CAN protocol CAN1.2,

CAN2.0A and CAN2.0B

CAN module uses RB3/CANRX and RB2/CANTX/INT2

pins to interface with CAN bus. In order to configure

CANRX and CANTX as CAN interface:

• Standard and extended data frames

• 0 - 8 bytes data length

• bit TRISB<3> must be set;

• Programmable bit rate up to 1 Mbit/sec

• Support for remote frames

• bit TRISB<2> must be cleared.

• Double-buffered receiver with two prioritized

received message storage buffers

19.1.2

TRANSMIT/RECEIVE BUFFERS

The PIC18FXX8 has three transmit and two receive buff-

ers, two acceptance masks (one for each receive

buffer), and a total of six acceptance filters. Figure 19-1

is a block diagram of these buffers and their connection

to the protocol engine.

• 6 full (standard/extended identifier) acceptance

filters, 2 associated with the high priority receive

buffer, and 4 associated with the low priority

receive buffer

• 2 full acceptance filter masks, one each

associated with the high and low priority receive

buffers

• Three transmit buffers with application specified

prioritization and abort capability

• Programmable wake-up functionality with

integrated low pass filter

• Programmable Loopback mode supports self-test

operation

• Signaling via interrupt capabilities for all CAN

receiver and transmitter error states

• Programmable clock source

• Programmable link to timer module for

time-stamping and network synchronization

• Low power SLEEP mode

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 197

PIC18FXX8

FIGURE 19-1:

CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM

BUFFERS

Accept

Acceptance Mask

RXM1

Acceptance Filter

RXM2

TXREQ

TXABT

TXLARB

TXERR

TXBUFF

TXB0

MESSAGE

Accept

Acceptance Mask

RXM0

Acceptance Filter

RXF3

TXREQ

TXABT

TXLARB

TXERR

TXBUFF

TXB1

Acceptance Filter

RXF0

Acceptance Filter

RXF4

MESSAGE

Acceptance Filter

RXF5

Acceptance Filter

RXF1

TXREQ

TXABT

TXLARB

TXERR

TXBUFF

TXB2

Message

Request

MESSAGE

RXB0

RXB1

Data and

Identifier

Data and

Identifier

Message

Queue

Identifier

Control

Transmit Byte Sequencer

Message Assembly Buffer

PROTOCOL

ENGINE

Receive Shift

Transmit Shift

RXERRCNT

Comparator

CRC Register

Bus-Off

Err-Pas

Bit Timing

Generator

Transmit

Logic

Protocol

FSM

Bit Timing

Logic

Transmit

Error

Receive

Error

TXERRCNT

Counter

RX

TX

DS41159B-page 198

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

19.2.1

CAN CONTROL AND STATUS

REGISTERS

19.2 CAN Module Registers

Note: Not all CAN registers are available in the

The registers described in this section control the over-

all operation of the CAN module and show its

operational status.

access bank.

There are many control and data registers associated

with the CAN module. For convenience, their

descriptions have been grouped into the following

sections:

• Control and Status Registers

• Transmit Buffer Registers (Data and Control)

• Receive Buffer Registers (Data and Control)

• Baud Rate Control Registers

• I/O Control Register

• Interrupt Status and Control Registers

REGISTER 19-1: CANCON – CAN CONTROL REGISTER

R/W-1

R/W-0

ABAT

R/W-0

WIN2

R/W-0

WIN1

R/W-0

WIN0

U-0

—

REQOP2 REQOP1 REQOP0

bit 7

bit 0

bit 7-5

REQOP2:REQOP0: Request CAN Operation Mode bits

1xx= Request Configuration mode

011= Request Listen Only mode

010= Request Loopback mode

001= Request Disable mode

000= Request Normal mode

bit 4

ABAT: Abort All Pending Transmissions bit

1= Abort all pending transmissions (in all transmit buffers)

0= Transmissions proceeding as normal

bit 3-1

WIN2:WIN0: Window Address bits

This selects which of the CAN buffers to switch into the access bank area. This allows access

to the buffer registers from any data memory bank. After a frame has caused an interrupt, the

ICODE3:ICODE0 bits can be copied to the WIN3:WIN0 bits to select the correct buffer. See

Example 19-1 for code example.

111= Receive Buffer 0

110= Receive Buffer 0

101= Receive Buffer 1

100= Transmit Buffer 0

011= Transmit Buffer 1

010= Transmit Buffer 2

001= Receive Buffer 0

000= Receive Buffer 0

bit 0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 199

PIC18FXX8

REGISTER 19-2: CANSTAT – CAN STATUS REGISTER

R-1

R-0

U-0

—

R-0

U-0

—

OPMODE2 OPMODE1 OPMODE0

bit 7

ICODE2 ICODE1 ICODE0

bit 0

bit 7-5

OPMODE2:OPMODE0: Operation Mode Status bits

111= Reserved

110= Reserved

101= Reserved

100= Configuration mode

011= Listen Only mode

010= Loopback mode

001= Disable mode

000= Normal mode

Note:

Before the device goes into SLEEP mode, select Disable mode.

bit 4

Unimplemented: Read as ’0’

bit 3-1

ICODE2:ICODE0: Interrupt Code bits

When an interrupt occurs, a prioritized coded interrupt value will be present in the

ICODE3:ICODE0 bits. These codes indicate the source of the interrupt. The ICODE3:ICODE0

bits can be copied to the WIN3:WIN0 bits to select the correct buffer to map into the Access

Bank area. See Example 19-1 for code example.

111= Wake-up on Interrupt

110= RXB0 Interrupt

101= RXB1 Interrupt

100= TXB0 Interrupt

011= TXB1 Interrupt

010= TXB2 Interrupt

001= Error Interrupt

000= No Interrupt

bit 0

Unimplemented: Read as ’0’

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41159B-page 200

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

EXAMPLE 19-1:

WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS

TX/RX BUFFERS

; Save application required context.

; Poll interrupt flags and determine source of interrupt

; This was found to be CAN interrupt

; TempCANCON and TempCANSTAT are variables defined in Access Bank low

MOVFF

CANCON, TempCANCON

; Save CANCON.WIN bits

; This is required to prevent CANCON

; from corrupting CAN buffer access

; in-progress while this interrupt

; occurred

MOVFF

CANSTAT, TempCANSTAT

; Save CANSTAT register

; This is required to make sure that

; we use same CANSTAT value rather

; than one changed by another CAN

; interrupt.

MOVF

ANDLW

ADDWF

TempCANSTAT, W

b’00001110’

PCL, F

; Retrieve ICODE bits

; Perform computed GOTO

; to corresponding interrupt cause

BRA

NoInterrupt

; 000 = No interrupt

ErrorInterrupt

TXB2Interrupt

TXB1Interrupt

TXB0Interrupt

RXB1Interrupt

RXB0Interrupt

; 001 = Error interrupt

; 010 = TXB2 interrupt

; 011 = TXB1 interrupt

; 100 = TXB0 interrupt

; 101 = RXB1 interrupt

; 110 = RXB0 interrupt

; 111 = Wake-up on interrupt

WakeupInterrupt

BCF

PIR3, WAKIF

; Clear the interrupt flag

;

; User code to handle wake-up procedure

;

; Continue checking for other interrupt source or return from here

…

NoInterrupt

…

; PC should never vector here. User may

; place a trap such as infinite loop or pin/port

; indication to catch this error.

ErrorInterrupt

BCF

…

PIR3, ERRIF

; Clear the interrupt flag

; Handle error.

RETFIE

TXB2Interrupt

BCF

GOTO

PIR3, TXB2IF

AccessBuffer

; Clear the interrupt flag

TXB1Interrupt

BCF

GOTO

PIR3, TXB1IF

AccessBuffer

TXB0Interrupt

BCF

GOTO

PIR3, TXB0IF

AccessBuffer

RXB1Interrupt

BCF

GOTO

PIR3, RXB1IF

Accessbuffer

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 201

PIC18FXX8

EXAMPLE 19-1:

WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS

TX/RX BUFFERS (CONTINUED)

RXB0Interrupt

BCF

GOTO

PIR3, RXB0IF

AccessBuffer

; Clear the interrupt flag

AccessBuffer

; This is either TX or RX interrupt

; Copy CANCON.ICODE bits to CANSTAT.WIN bits

MOVF

TempCANCON, W

b’11110001’

TempCANCON

; Clear CANCON.WIN bits before copying

; new ones.

; Use previously saved CANCON value to

; make sure same value.

ANDLW

MOVWF

; Copy masked value back to TempCANCON

MOVF

TempCANSTAT, W

; Retrieve ICODE bits

ANDLW

b’00001110’

; Use previously saved CANSTAT value

; to make sure same value.

IORWF

MOVFF

TempCANCON

TempCANCON, CANCON

; Copy ICODE bits to WIN bits.

; Copy the result to actual CANCON

; Access current buffer…

; User code

; Restore CANCON.WIN bits

MOVF

ANDLW

IORWF

CANCON, W

b’11110001’

TempCANCON

; Preserve current non WIN bits

; Restore original WIN bits

; Do not need to restore CANSTAT - it is read-only register.

; Return from interrupt or check for another module interrupt source

DS41159B-page 202

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 19-3: COMSTAT – COMMUNICATION STATUS REGISTER

R/C-0

R-0

TXWARN RXWARN EWARN

bit 0

R-0

RXB0OVFL RXB1OVFL

bit 7

TXBO

TXBP

RXBP

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RXB0OVFL: Receive Buffer 0 Overflow bit

1= Receive Buffer 0 overflowed

0= Receive Buffer 0 has not overflowed

RXB1OVFL: Receive Buffer 1 Overflow bit

1= Receive Buffer 1 overflowed

0= Receive Buffer 1 has not overflowed

TXBO: Transmitter Bus-Off bit

1= Transmit Error Counter > 255

0= Transmit Error Counter ≤ 255

TXBP: Transmitter Bus Passive bit

1= Transmission Error Counter > 127

0= Transmission Error Counter ≤ 127

RXBP: Receiver Bus Passive bit

1= Receive Error Counter > 127

0= Receive Error Counter ≤ 127

TXWARN: Transmitter Warning bit

1= 127 ≥ Transmit Error Counter > 95

0= Transmit Error Counter ≤ 95

RXWARN: Receiver Warning bit

1= 127 ≥ Receive Error Counter > 95

0= Receive Error Counter ≤ 95

EWARN: Error Warning bit

This bit is a flag of the RXWARN and TXWARN bits

1= The RXWARN or the TXWARN bits are set

0= Neither the RXWARN or the TXWARN bits are set

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 203

PIC18FXX8

19.2.2

CAN TRANSMIT BUFFER

REGISTERS

This section describes the CAN Transmit Buffer

registers and their associated control registers.

REGISTER 19-4: TXBnCON – TRANSMIT BUFFER n CONTROL REGISTERS

U-0

—

R-0

R/W-0

U-0

—

R/W-0

TXABT

TXLARB

TXERR

TXREQ

TXPRI1

TXPRI0

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ’0’

TXABT: Transmission Aborted Status bit

1= Message was aborted

0= Message was not aborted

bit 5

bit 4

bit 3

TXLARB: Transmission Lost Arbitration Status bit

1= Message lost arbitration while being sent

0= Message did not lose arbitration while being sent

TXERR: Transmission Error Detected Status bit

1= A bus error occurred while the message was being sent

0= A bus error did not occur while the message was being sent

TXREQ: Transmit Request Status bit

1= Requests sending a message. Clears the TXABT, TXLARB, and TXERR bits.

0= Automatically cleared when the message is successfully sent

Note:

Clearing this bit in software while the bit is set, will request a message abort.

bit 2

Unimplemented: Read as ’0’

bit 1-0

TXPRI1:TXPRI0: Transmit Priority bits

11= Priority Level 3 (Highest Priority)

10= Priority Level 2

01= Priority Level 1

00= Priority Level 0 (Lowest Priority)

Note:

These bits set the order in which Transmit buffer will be transferred. They do not

alter CAN message identifier.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41159B-page 204

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 19-5: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER, HIGH BYTE

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

bit 7

bit 0

bit 7-0

SID10:SID3: Standard Identifier bits, if EXIDE = 0 (TXBnSID Register)

Extended Identifier bits EID28:EID21, if EXIDE = 1

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 19-6: TXBnSIDL – TRANSMIT BUFFER n STANDARD IDENTIFIER, LOW BYTE

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

R/W-x

—

R/W-x

EXIDE

R/W-x

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

bit 7-5

SID2:SID0: Standard Identifier bits, if EXIDE = 0

Extended Identifier bits EID20:EID18, if EXIDE = 1

Unimplemented: Read as ’0’

bit 4

bit 3

EXIDE: Extended Identifier Enable bit

1= Message will transmit Extended ID, SID10:SID0 becomes EID28:EID18

0= Message will transmit Standard ID, EID17:EID0 are ignored

bit 2

Unimplemented: Read as ’0’

bit 1-0

EID17:EID16: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 19-7: TXBnEIDH – TRANSMIT BUFFER n EXTENDED IDENTIFIER, HIGH BYTE

R/W-x

EID15

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 7

bit 0

bit 7-0

EID15:EID8: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 205

PIC18FXX8

REGISTER 19-8: TXBnEIDL – TRANSMIT BUFFER n EXTENDED IDENTIFIER, LOW BYTE

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

bit 7-0

EID7:EID0: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 19-9: TXBnDm – TRANSMIT BUFFER n DATA FIELD BYTE m REGISTERS

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0

bit 7 bit 0

R/W-x

bit 7-0

TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Byte m bits (where 0≤n<3 and 0<m<8)

Each Transmit Buffer has an array of registers. For example, Transmit buffer 0 has 7 registers:

TXB0D0 to TXB0D7.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41159B-page 206

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PIC18FXX8

REGISTER 19-10: TXBnDLC – TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS

U-0

—

R/W-x

U-0

—

U-0

—

R/W-x

DLC3

R/W-x

DLC2

R/W-x

DLC1

R/W-x

DLC0

TXRTR

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ’0’

TXRTR: Transmission Frame Remote Transmission Request bit

1= Transmitted message will have TXRTR bit set

0= Transmitted message will have TXRTR bit cleared

bit 5-4

bit 3-0

Unimplemented: Read as ’0’

DLC3:DLC0: Data Length Code bits

1111= Reserved

1110= Reserved

1101= Reserved

1100= Reserved

1011= Reserved

1010= Reserved

1001= Reserved

1000= Data Length = 8 bytes

0111= Data Length = 7 bytes

0110= Data Length = 6 bytes

0101= Data Length = 5 bytes

0100= Data Length = 4 bytes

0011= Data Length = 3 bytes

0010= Data Length = 2 bytes

0001= Data Length = 1 bytes

0000= Data Length = 0 bytes

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 19-11: TXERRCNT – TRANSMIT ERROR COUNT REGISTER

R-0

TEC7

TEC6

TEC5

TEC4

TEC3

TEC2

TEC1

TEC0

bit 7

bit 0

bit 7-0

TEC7:TEC0: Transmit Error Counter bits

This register contains a value which is derived from the rate at which errors occur. When the

error count overflows, the bus-off state occurs. When the bus has 128 occurrences of 11

consecutive recessive bits, the counter value is cleared.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 207

PIC18FXX8

19.2.3

CAN RECEIVE BUFFER

REGISTERS

This section shows the Receive Buffer registers with

their associated control registers.

REGISTER 19-12: RXB0CON – RECEIVE BUFFER 0 CONTROL REGISTER

R/C-0

R/W-0

U-0

—

R-0

R/W-0

R-0

R/W-0

RXFUL⁽¹⁾RXM1⁽¹⁾RXM0⁽¹⁾

RXRTRRO RXB0DBEN JTOFF

FILHIT0

bit 7

bit 0

bit 7

RXFUL: Receive Full Status bit⁽¹⁾

1= Receive buffer contains a received message

0= Receive buffer is open to receive a new message

Note:

This bit is set by the CAN module and must be cleared by software after the buffer

is read.

bit 6-5

RXM1:RXM0: Receive Buffer Mode bits⁽¹⁾

11= Receive all messages (including those with errors)

10= Receive only valid messages with extended identifier

01= Receive only valid messages with standard identifier

00= Receive all valid messages

bit 4

bit 3

Unimplemented: Read as ’0’

RXRTRRO: Receive Remote Transfer Request Read Only bit

1= Remote transfer request

0= No remote transfer request

bit 2

bit 1

RXB0DBEN: Receive Buffer 0 Double Buffer Enable bit

1= Receive Buffer 0 overflow will write to Receive Buffer 1

0= No Receive Buffer 0 overflow to Receive Buffer 1

JTOFF: Jump Table Offset bit (read only copy of RXB0DBEN)

1= Allows Jump Table offset between 6 and 7

0= Allows Jump Table offset between 1 and 0

Note:

This bit allows same filter jump table for both RXB0CON and RXB1CON.

bit 0

FILHIT0: Filter Hit bit

This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0

1= Acceptance Filter 1 (RXF1)

0= Acceptance Filter 0 (RXF0)

Note

1: Bits RXFUL, RXM1 and RXM0 of RXB0CON are not mirrored in RXB1CON.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41159B-page 208

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PIC18FXX8

REGISTER 19-13: RXB1CON – RECEIVE BUFFER 1 CONTROL REGISTER

R/C-0

R/W-0

U-0

—

R-0

RXFUL⁽¹⁾RXM1⁽¹⁾RXM0⁽¹⁾

RXRTRRO FILHIT2

FILHIT1

FILHIT0

bit 7

bit 0

bit 7

RXFUL: Receive Full Status bit⁽¹⁾

1= Receive buffer contains a received message

0= Receive buffer is open to receive a new message

Note:

This bit is set by the CAN module and should be cleared by software after the buffer

is read.

bit 6-5

RXM1:RXM0: Receive Buffer Mode bits⁽¹⁾

11= Receive all messages (including those with errors)

10= Receive only valid messages with extended identifier

01= Receive only valid messages with standard identifier

00= Receive all valid messages

bit 4

bit 3

Unimplemented: Read as ’0’

RXRTRRO: Receive Remote Transfer Request bit (read only)

1= Remote transfer request

0= No remote transfer request

bit 2-0

FILHIT2:FILHIT0: Filter Hit bits

These bits indicate which acceptance filter enabled the last message reception into Receive

Buffer 1

111= Reserved

110= Reserved

101= Acceptance Filter 5 (RXF5)

100= Acceptance Filter 4 (RXF4)

011= Acceptance Filter 3 (RXF3)

010= Acceptance Filter 2 (RXF2)

001= Acceptance Filter 1 (RXF1) only possible when RXB0DBEN bit is set

000= Acceptance Filter 0 (RXF0) only possible when RXB0DBEN bit is set

Note

1: Bits RXFUL, RXM1 and RXM0 of RXB1CON are not mirrored in RXB0CON.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 19-14: RXBnSIDH – RECEIVE BUFFER n STANDARD IDENTIFIER, HIGH BYTE

REGISTER

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

bit 7

bit 0

bit 7-0

SID10:SID3: Standard Identifier bits, if EXID = 0 (RXBnSIDL Register)

Extended Identifier bits EID28:EID21, if EXID = 1

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’0’ = Bit is cleared

x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 209

PIC18FXX8

REGISTER 19-15: RXBnSIDL – RECEIVE BUFFER n STANDARD IDENTIFIER, LOW BYTE

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

R/W-x

SRR

R/W-x

EXID

U-0

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

bit 7-5

bit 4

SID2:SID0: Standard Identifier bits, if EXID = 0

Extended Identifier bits EID20:EID18, if EXID = 1

SRR: Substitute Remote Request bit

This bit is always ‘0’ when EXID = ‘1’, or equal to the value of RXRTRRO (RXnBCON<3>)

when EXID = ‘0’.

bit 3

EXID: Extended Identifier bit

1= Received message is an Extended Data Frame, SID10:SID0 are EID28:EID18

0= Received message is a Standard Data Frame

bit 2

Unimplemented: Read as ’0’

bit 1-0

EID17:EID16: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 19-16: RXBnEIDH – RECEIVE BUFFER n EXTENDED IDENTIFIER, HIGH BYTE

R/W-x

EID15

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 0

bit 7

bit 7-0

EID15:EID8: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 19-17: RXBnEIDL – RECEIVE BUFFER n EXTENDED IDENTIFIER, LOW BYTE

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

bit 7-0

EID7:EID0: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

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REGISTER 19-18: RXBnDLC – RECEIVE BUFFER n DATA LENGTH CODE REGISTERS

U-0

—

R/W-x

RB1

R/W-x

RB0

R/W-x

DLC3

R/W-x

DLC2

R/W-x

DLC1

R/W-x

DLC0

RXRTR

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ’0’

RXRTR: Receiver Remote Transmission Request bit

1= Remote transfer request

0= No remote transfer request

bit 5

RB1: Reserved bit 1

Reserved by CAN Spec and read as ’0’

bit 4

RB0: Reserved bit 0

Reserved by CAN Spec and read as ’0’

bit 3-0

DLC3:DLC0: Data Length Code bits

1111= Invalid

1110= Invalid

1101= Invalid

1100= Invalid

1011= Invalid

1010= Invalid

1001= Invalid

1000= Data Length = 8 bytes

0111= Data Length = 7 bytes

0110= Data Length = 6 bytes

0101= Data Length = 5 bytes

0100= Data Length = 4 bytes

0011= Data Length = 3 bytes

0010= Data Length = 2 bytes

0001= Data Length = 1 bytes

0000= Data Length = 0 bytes

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 19-19: RXBnDm – RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0

bit 7 bit 0

R/W-x

bit 7-0

RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0≤n<1 and 0<m<7)

Each Receive Buffer has an array of registers. For example, Receive buffer 0 has 8 registers:

RXB0D0 to RXB0D7.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 211

PIC18FXX8

REGISTER 19-20: RXERRCNT – RECEIVE ERROR COUNT REGISTER

R-0

REC7

REC6

REC5

REC4

REC3

REC2

REC1

REC0

bit 7

bit 0

bit 7-0

REC7:REC0: Receive Error Counter bits

This register contains the Receive Error value as defined by the CAN specifications.

When RXERRCNT > 127, the module will go into an error passive state. RXERRCNT does not

have the ability to put the module in “Bus-Off” state.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

19.2.3.1

Message Acceptance Filters and

Masks

This subsection describes the Message Acceptance

filters and masks for the CAN Receive buffers.

REGISTER 19-21: RXFnSIDH – RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER,

HIGH BYTE

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

bit 7

bit 0

bit 7-0

SID10:SID3: Standard Identifier Filter bits, if EXIDEN = 0

Extended Identifier Filter bits EID28:EID21, if EXIDEN = 1

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 19-22: RXFnSIDL – RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER,

LOW BYTE

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

U-0

—

R/W-x

EXIDEN

U-0

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

bit 7-5

SID2:SID0: Standard Identifier Filter bits, if EXIDEN = 0

Extended Identifier Filter bits EID20:EID18, if EXIDEN = 1

Unimplemented: Read as ’0’

bit 4

bit 3

EXIDEN: Extended Identifier Filter Enable bit

1= Filter will only accept Extended ID messages

0= Filter will only accept Standard ID messages

bit 2

Unimplemented: Read as ’0’

bit 1-0

EID17:EID16: Extended Identifier Filter bits

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41159B-page 212

Preliminary

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PIC18FXX8

REGISTER 19-23: RXFnEIDH – RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER,

HIGH BYTE

R/W-x

EID15

bit 7

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 0

bit 7-0

EID15:EID8: Extended Identifier Filter bits

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 19-24: RXFnEIDL – RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER,

LOW BYTE

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

bit 7-0

EID7:EID0: Extended Identifier Filter bits

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 19-25: RXMnSIDH – RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK,

HIGH BYTE

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

bit 7

bit 0

bit 7-0

SID10:SID3: Standard Identifier Mask bits, or Extended Identifier Mask bits EID28:EID21

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 213

PIC18FXX8

REGISTER 19-26: RXMnSIDL – RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK,

LOW BYTE

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

U-0

—

U-0

—

U-0

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

bit 7-5

bit 4-2

bit 1-0

SID2:SID0: Standard Identifier Mask bits, or Extended Identifier Mask bits EID20:EID18

Unimplemented: Read as ’0’

EID17:EID16: Extended Identifier Mask bits

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 19-27: RXMnEIDH – RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK,

HIGH BYTE

R/W-x

EID15

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 7

bit 0

bit 7-0

EID15:EID8: Extended Identifier Mask bits

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 19-28: RXMnEIDL – RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK,

LOW BYTE

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

bit 7-0

EID7:EID0: Extended Identifier Mask bits

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41159B-page 214

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PIC18FXX8

19.2.4

CAN BAUD RATE REGISTERS

This subsection describes the CAN Baud Rate

registers.

REGISTER 19-29: BRGCON1 – BAUD RATE CONTROL REGISTER 1

R/W-0

SJW1

R/W-0

SJW0

R/W-0

BRP5

R/W-0

BRP4

R/W-0

BRP3

R/W-0

BRP2

R/W-0

BRP1

R/W-0

BRP0

bit 7

bit 0

bit 7-6

bit 5-0

SJW1:SJW0: Synchronized Jump Width bits

11= Synchronization Jump Width Time = 4 x TQ

10= Synchronization Jump Width Time = 3 x TQ

01= Synchronization Jump Width Time = 2 x TQ

00= Synchronization Jump Width Time = 1 x TQ

BRP5:BRP0: Baud Rate Prescaler bits

111111= TQ = (2 x 64)/FOSC

111110= TQ = (2 x 63)/FOSC

:

000001= TQ = (2 x 2)/FOSC

000000= TQ = (2 x 1)/FOSC

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Note: This register is accessible in Configuration mode only.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 215

PIC18FXX8

REGISTER 19-30: BRGCON2 – BAUD RATE CONTROL REGISTER 2

R/W-0

SEG2PHTS

bit 7

R/W-0

SAM

R/W-0

SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0

bit 0

bit 7

SEG2PHTS: Phase Segment 2 Time Select bit

1= Freely programmable

0= Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater

bit 6

SAM: Sample of the CAN bus Line bit

1= Bus line is sampled three times prior to the sample point

0= Bus line is sampled once at the sample point

bit 5-3

SEG1PH2:SEG1PH0: Phase Segment 1 bits

111= Phase Segment 1 Time = 8 x TQ

110= Phase Segment 1 Time = 7 x TQ

101= Phase Segment 1 Time = 6 x TQ

100= Phase Segment 1 Time = 5 x TQ

011= Phase Segment 1 Time = 4 x TQ

010= Phase Segment 1 Time = 3 x TQ

001= Phase Segment 1 Time = 2 x TQ

000= Phase Segment 1 Time = 1 x TQ

bit 2-0

PRSEG2:PRSEG0: Propagation Time Select bits

111= Propagation Time = 8 x TQ

110= Propagation Time = 7 x TQ

101= Propagation Time = 6 x TQ

100= Propagation Time = 5 x TQ

011= Propagation Time = 4 x TQ

010= Propagation Time = 3 x TQ

001= Propagation Time = 2 x TQ

000= Propagation Time = 1 x TQ

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Note: This register is accessible in Configuration mode only.

DS41159B-page 216

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PIC18FXX8

REGISTER 19-31: BRGCON3 – BAUD RATE CONTROL REGISTER 3

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

WAKFIL

SEG2PH2⁽¹⁾SEG2PH1⁽¹⁾SEG2PH0⁽¹⁾

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ’0’

WAKFIL: Selects CAN bus Line Filter for Wake-up bit

1= Use CAN bus line filter for wake-up

0= CAN bus line filter is not used for wake-up

bit 5-3

bit 2-0

Unimplemented: Read as ’0’

SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits⁽¹⁾

111= Phase Segment 2 Time = 8 x TQ

110= Phase Segment 2 Time = 7 x TQ

101= Phase Segment 2 Time = 6 x TQ

100= Phase Segment 2 Time = 5 x TQ

011= Phase Segment 2 Time = 4 x TQ

010= Phase Segment 2 Time = 3 x TQ

001= Phase Segment 2 Time = 2 x TQ

000= Phase Segment 2 Time = 1 x TQ

Note 1: Ignored if SEG2PHTS bit (BRGCON2<7>) is clear.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

19.2.5

CAN MODULE I/O CONTROL

REGISTER

This register controls the operation of the CAN module’s

I/O pins in relation to the rest of the microcontroller.

REGISTER 19-32: CIOCON – CAN I/O CONTROL REGISTER

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

ENDRHI CANCAP

bit 7

bit 0

bit 7-6

bit 5

Unimplemented: Read as ‘0’

ENDRHI: Enable Drive High bit

1= CANTX pin will drive VDD when recessive

0= CANTX pin will tri-state when recessive

bit 4

CANCAP: CAN Message Receive Capture Enable bit

1= Enable CAN capture, CAN message receive signal replaces input on RC2/CCP1

0= Disable CAN capture, RC2/CCP1 input to CCP1 module

bit 3-0

Unimplemented: Read as ’0’

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’0’ = Bit is cleared

x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 217

PIC18FXX8

19.2.6

CAN INTERRUPT REGISTERS

The registers in this section are the same as described

in Section 8.0. They are duplicated here for

convenience.

REGISTER 19-33: PIR3 – PERIPHERAL INTERRUPT FLAG REGISTER

R/W-0

IRXIF

R/W-0

ERRIF

R/W-0

WAKIF

TXB2IF

TXB1IF

TXB0IF

RXB1IF

RXB0IF

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IRXIF: CAN Invalid Received Message Interrupt Flag bit

1= An invalid message has occurred on the CAN bus

0= No invalid message on CAN bus

WAKIF: CAN bus Activity Wake-up Interrupt Flag bit

1= Activity on CAN bus has occurred

0= No activity on CAN bus

ERRIF: CAN bus Error Interrupt Flag bit

1= An error has occurred in the CAN module (multiple sources)

0= No CAN module errors

TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit

1= Transmit Buffer 2 has completed transmission of a message and may be reloaded

0= Transmit Buffer 2 has not completed transmission of a message

TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit

1= Transmit Buffer 1 has completed transmission of a message and may be reloaded

0= Transmit Buffer 1 has not completed transmission of a message

TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit

1= Transmit Buffer 0 has completed transmission of a message and may be reloaded

0= Transmit Buffer 0 has not completed transmission of a message

RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit

1= Receive Buffer 1 has received a new message

0= Receive Buffer 1 has not received a new message

RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit

1= Receive Buffer 0 has received a new message

0= Receive Buffer 0 has not received a new message

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41159B-page 218

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 19-34: PIE3 – PERIPHERAL INTERRUPT ENABLE REGISTER

R/W-0

IRXIE

R/W-0

ERRIE

R/W-0

WAKIE

TXB2IE

TXB1IE

TXB0IE

RXB1IE

RXB0IE

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IRXIE: CAN Invalid Received Message Interrupt Enable bit

1= Enable invalid message received interrupt

0= Disable invalid message received interrupt

WAKIE: CAN bus Activity Wake-up Interrupt Enable bit

1= Enable bus activity wake-up interrupt

0= Disable bus activity wake-up interrupt

ERRIE: CAN bus Error Interrupt Enable bit

1= Enable CAN bus error interrupt

0= Disable CAN bus error interrupt

TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit

1= Enable Transmit Buffer 2 interrupt

0= Disable Transmit Buffer 2 interrupt

TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit

1= Enable Transmit Buffer 1 interrupt

0= Disable Transmit Buffer 1 interrupt

TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit

1= Enable Transmit Buffer 0 interrupt

0= Disable Transmit Buffer 0 interrupt

RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit

1= Enable Receive Buffer 1 interrupt

0= Disable Receive Buffer 1 interrupt

RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit

1= Enable Receive Buffer 0 interrupt

0= Disable Receive Buffer 0 interrupt

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 219

PIC18FXX8

REGISTER 19-35: IPR3 – PERIPHERAL INTERRUPT PRIORITY REGISTER

R/W-1

IRXIP

R/W-1

ERRIP

R/W-1

WAKIP

TXB2IP

TXB1IP

TXB0IP

RXB1IP

RXB0IP

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IRXIP: CAN Invalid Received Message Interrupt Priority bit

1= High priority

0= Low priority

WAKIP: CAN bus Activity Wake-up Interrupt Priority bit

1= High priority

0= Low priority

ERRIP: CAN bus Error Interrupt Priority bit

1= High priority

0= Low priority

TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit

1= High priority

0= Low priority

TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit

1= High priority

0= Low priority

TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit

1= High priority

0= Low priority

RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit

1= High priority

0= Low priority

RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit

1= High priority

0= Low priority

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41159B-page 220

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 19-1: CAN CONTROLLER REGISTER MAP

Address

Name

Address

Name

Address

Name

Address

Name

F7Fh

—

F5Fh

—

F3Fh

—

F1Fh RXM1EIDL

F7Eh

F7Dh

F7Ch

F7Bh

F7Ah

F79h

F78h

F77h

—

F5Eh CANSTATRO1⁽²⁾

F3Eh CANSTATRO3⁽²⁾

F1Eh RXM1EIDH

F1Dh RXM1SIDL

F1Ch RXM1SIDH

F1Bh RXM0EIDL

F1Ah RXM0EIDH

F19h RXM0SIDL

F18h RXM0SIDH

F5Dh

F5Ch

F5Bh

F5Ah

F59h

F58h

F57h

F56h

F55h

F54h

F53h

F52h

F51h

F50h

F4Fh

RXB1D7

RXB1D6

RXB1D5

RXB1D4

RXB1D3

RXB1D2

RXB1D1

RXB1D0

RXB1DLC

RXB1EIDL

RXB1EIDH

RXB1SIDL

RXB1SIDH

RXB1CON

—

F3Dh

F3Ch

F3Bh

F3Ah

F39h

F38h

F37h

F36h

F35h

F34h

F33h

F32h

F31h

F30h

F2Fh

TXB1D7

TXB1D6

TXB1D5

TXB1D4

TXB1D3

TXB1D2

TXB1D1

TXB1D0

TXB1DLC

TXB1EIDL

TXB1EIDH

TXB1SIDL

TXB1SIDH

TXB1CON

—

F17h

F16h

F15h

F14h

F13h

F12h

F11h

F10h

F0Fh

RXF5EIDL

RXF5EIDH

RXF5SIDL

RXF5SIDH

RXF4EIDL

RXF4EIDH

RXF4SIDL

RXF4SIDH

RXF3EIDL

F76h TXERRCNT

F75h RXERRCNT

F74h COMSTAT

F73h

CIOCON

F72h BRGCON3

F71h BRGCON2

F70h BRGCON1

F6Fh CANCON

F6Eh CANSTAT

F4Eh CANSTATRO2⁽²⁾

F2Eh CANSTATRO4⁽²⁾

F0Eh

F0Dh

F0Ch

F0Bh

F0Ah

F09h

F08h

F07h

F06h

F05h

F04h

F03h

F02h

F01h

F00h

RXF3EIDH

RXF3SIDL

RXF3SIDH

RXF2EIDL

RXF2EIDH

RXF2SIDL

RXF2SIDH

RXF1EIDL

RXF1EIDH

RXF1SIDL

RXF1SIDH

RXF0EIDL

RXF0EIDH

RXF0SIDL

RXF0SIDH

F6Dh

F6Ch

F6Bh

F6Ah

F69h

F68h

F67h

F66h

RXB0D7

RXB0D6

RXB0D5

RXB0D4

RXB0D3

RXB0D2

RXB0D1

RXB0D0

F4Dh

F4Ch

F4Bh

F4Ah

F49h

F48h

F47h

F46h

F45h

F44h

F43h

F42h

F41h

F40h

TXB0D7

TXB0D6

F2Dh

F2Ch

F2Bh

F2Ah

F29h

F28h

F27h

F26h

F25h

F24h

F23h

F22h

F21h

F20h

TXB2D7

TXB2D6

TXB0D5

TXB2D5

TXB0D4

TXB2D4

TXB0D3

TXB2D3

TXB0D2

TXB2D2

TXB0D1

TXB2D1

TXB0D0

TXB2D0

F65h RXB0DLC

F64h RXB0EIDL

F63h RXB0EIDH

F62h RXB0SIDL

F61h RXB0SIDH

F60h RXB0CON

TXB0DLC

TXB0EIDL

TXB0EIDH

TXB0SIDL

TXB0SIDH

TXB0CON

TXB2DLC

TXB2EIDL

TXB2EIDH

TXB2SIDL

TXB2SIDH

TXB2CON

Note 1: Shaded registers are available in Access Bank Low area, while the rest are available in Bank 15.

2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given

for each instance of the CANSTAT register, due to the Microchip Header file requirement.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 221

PIC18FXX8

If REQOP<2:0> is set to ‘001’, the module will enter the

Module Disable mode. This mode is similar to disabling

other peripheral modules by turning off the module

enables. This causes the module internal clock to stop

unless the module is active (i.e., receiving or transmit-

ting a message). If the module is active, the module will

wait for 11 recessive bits on the CAN bus, detect that

condition as an idle bus, then accept the module

disable command. OPMODE<2:0> = ‘001’ indicates

whether the module successfully went into Module

Disable mode.

19.3 CAN Modes of Operation

The PIC18FXX8 has six main modes of operation:

• Configuration mode

• Disable mode

• Normal Operation mode

• Listen Only mode

• Loopback mode

• Error Recognition mode

All modes except Error Recognition are requested by

setting the REQOP bits (CANCON<7:5>); Error Recog-

nition is requested through the RXM bits of the Receive

Buffer register(s). Entry into a mode is acknowledged

by monitoring the OPMODE bits.

The WAKIF interrupt is the only module interrupt that is

still active in the Module Disable mode. If the WAKIE is

set, the processor will receive an interrupt whenever

the CAN bus detects a dominant state, as occurs with

a SOF.

When changing modes, the mode will not actually

change until all pending message transmissions are

complete. Because of this, the user must verify that the

device has actually changed into the requested mode

before further operations are executed.

The I/O pins will revert to normal I/O function when the

module is in the Module Disable mode.

19.3.3

NORMAL MODE

This is the standard operating mode of the PIC18FXX8.

In this mode, the device actively monitors all bus mes-

sages and generates Acknowledge bits, error frames,

etc. This is also the only mode in which the PIC18FXX8

will transmit messages over the CAN bus.

19.3.1

CONFIGURATION MODE

The CAN module has to be initialized before the activa-

tion. This is only possible if the module is in the Config-

uration mode. The Configuration mode is requested by

setting REQOP2 bit. Only when the status bit

OPMODE2 has a high level, can the initialization be

performed. Afterwards, the configuration registers, the

acceptance mask registers, and the acceptance filter

registers can be written. The module is activated by

setting the REQOP control bits to zero.

19.3.4

LISTEN ONLY MODE

Listen Only mode provides

a

means for the

PIC18FXX8 to receive all messages, including mes-

sages with errors. This mode can be used for bus mon-

itor applications, or for detecting the baud rate in ‘hot

plugging’ situations. For auto-baud detection, it is nec-

essary that there are at least two other nodes which are

communicating with each other. The baud rate can be

detected empirically by testing different values until

valid messages are received. The Listen Only mode is

a silent mode, meaning no messages will be transmit-

ted while in this state, including error flags or Acknowl-

edge signals. The filters and masks can be used to

allow only particular messages to be loaded into the

receive registers, or the filter masks can be set to all

zeros to allow a message with any identifier to pass.

The error counters are reset and deactivated in this

state. The Listen Only mode is activated by setting the

mode request bits in the CANCON register.

The module will protect the user from accidentally vio-

lating the CAN protocol through programming errors.

All registers which control the configuration of the mod-

ule can not be modified while the module is on-line.

The CAN module will not be allowed to enter the Con-

figuration mode while a transmission is taking place.

The CONFIG bit serves as a lock to protect the

following registers.

• Configuration registers

• Bus Timing registers

• Identifier Acceptance Filter registers

• Identifier Acceptance Mask registers

In the Configuration mode, the module will not transmit

or receive. The error counters are cleared and the inter-

rupt flags remain unchanged. The programmer will

have access to configuration registers that are access

restricted in other modes.

19.3.2

DISABLE MODE

In Disable mode, the module will not transmit or

receive. The module has the ability to set the WAKIF bit

due to bus activity, however, any pending interrupts will

remain and the error counters will retain their value.

DS41159B-page 222

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

19.3.5

LOOPBACK MODE

19.4.2

TRANSMIT PRIORITY

This mode will allow internal transmission of messages

from the transmit buffers to the receive buffers, without

actually transmitting messages on the CAN bus. This

mode can be used in system development and testing.

In this mode, the ACK bit is ignored and the device will

allow incoming messages from itself, just as if they

were coming from another node. The Loopback mode

is a silent mode, meaning no messages will be trans-

mitted while in this state, including error flags or

Acknowledge signals. The TXCAN pin will revert to port

I/O while the device is in this mode. The filters and

masks can be used to allow only particular messages

to be loaded into the receive registers. The masks can

be set to all zeros to provide a mode that accepts all

messages. The Loopback mode is activated by setting

the mode request bits in the CANCON register.

Transmit priority is a prioritization within the PIC18FXX8

of the pending transmittable messages. This is indepen-

dent from, and not related to, any prioritization implicit in

the message arbitration scheme built into the CAN pro-

tocol. Prior to sending the SOF, the priority of all buffers

that are queued for transmission is compared. The trans-

mit buffer with the highest priority will be sent first. If two

buffers have the same priority setting, the buffer with the

highest buffer number will be sent first. There are four

levels of transmit priority. If TXP bits for a particular mes-

sage buffer are set to 11, that buffer has the highest pos-

sible priority. If TXP bits for a particular message buffer

are 00, that buffer has the lowest possible priority.

FIGURE 19-2:

TRANSMIT BUFFER

BLOCK DIAGRAM

19.3.6

ERROR RECOGNITION MODE

TXREQ

TXABT

TXLARB

TXERR

TXBUFF

TXB0

The module can be set to ignore all errors and receive

any message. The Error Recognition mode is activated

by setting the RXM<1:0> bits in the RXBnCON regis-

ters to 11. In this mode, the data which is in the mes-

sage assembly buffer until the error time, is copied in

the receive buffer and can be read via the CPU inter-

face. In addition, the data which was on the internal

sampling of the CAN bus at the error time and the state

vector of the protocol state machine and the bit counter

CntCan, are stored in registers and can be read.

MESSAGE

TXB1

TXREQ

TXABT

TXLARB

TXERR

TXBUFF

MESSAGE

TXB2

TXREQ

TXABT

TXLARB

TXERR

TXBUFF

Message

Request

MESSAGE

19.4 CAN Message Transmission

Message

Queue

19.4.1

TRANSMIT BUFFERS

Control

The PIC18FXX8 implements three Transmit Buffers

(Figure 19-2). Each of these buffers occupies 14 bytes

of SRAM and are mapped into the device memory

map.

Transmit Byte Sequencer

For the MCU to have write access to the message

buffer, the TXREQ bit must be clear, indicating that the

message buffer is clear of any pending message to be

transmitted. At a minimum, the TXBnSIDH, TXBnSIDL,

and TXBnDLC registers must be loaded. If data bytes

are present in the message, the TXBnDm registers

must also be loaded. If the message is to use extended

identifiers, the TXBnEIDm registers must also be

loaded and the EXIDE bit set.

Prior to sending the message, the MCU must initialize

the TXInE bit to enable or disable the generation of an

interrupt when the message is sent. The MCU must

also initialize the TXP priority bits (see Section 19.4.2).

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 223

PIC18FXX8

19.4.3

INITIATING TRANSMISSION

19.4.4

ABORTING TRANSMISSION

To initiate message transmission, the TXREQ bit must

be set for each buffer to be transmitted. When TXREQ

is set, the TXABT, TXLARB and TXERR bits will be

cleared.

The MCU can request to abort a message by clearing

the TXREQ bit associated with the corresponding mes-

sage buffer (TXBnCON<3>). Setting the ABAT bit

(CANCON<4>) will request an abort of all pending mes-

sages. If the message has not yet started transmission,

or if the message started but is interrupted by loss of

arbitration or an error, the abort will be processed. The

abort is indicated when the module sets the ABT bits for

the corresponding buffer (TXBnCON<6>). If the mes-

sage has started to transmit, it will attempt to transmit the

current message fully. If the current message is transmit-

ted fully and is not lost to arbitration or an error, the ABT

bit will not be set, because the message was transmitted

successfully. Likewise, if a message is being transmitted

during an abort request and the message is lost to arbi-

tration or an error, the message will not be retransmitted

and the ABT bit will be set, indicating that the message

was successfully aborted.

Setting the TXREQ bit does not initiate a message

transmission, it merely flags a message buffer as ready

for transmission. Transmission will start when the

device detects that the bus is available. The device will

then begin transmission of the highest priority message

that is ready.

When the transmission has completed successfully, the

TXREQ bit will be cleared, the TXBnIF bit will be set, and

an interrupt will be generated if the TXBnIE bit is set.

If the message transmission fails, the TXREQ will remain

set, indicating that the message is still pending for trans-

mission and one of the following condition flags will be

set. If the message started to transmit but encountered

an error condition, the TXERR and the IRXIF bits will be

set and an interrupt will be generated. If the message lost

arbitration, the TXLARB bit will be set.

DS41159B-page 224

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 19-3:

TRANSMIT MESSAGE FLOW CHART

Start

The message transmission sequence begins when

the device determines that the TXREQ for any of the

transmit registers has been set.

Are any

TXREQ

bits = 1

?

No

Clearing the TXREQ bit while it is set, or setting

the ABAT bit before the message has started

transmission, will abort the message.

Yes

Clear: TXABT, TXLARB

and TXERR

No

Is

Yes

No

CAN bus Available

to Start Transmission

?

TXREQ = 0

ABAT = 1

?

Yes

Examine TXPRI <1:0> to

Determine Highest Priority Message

Begin Transmission (SOF)

Was

No

Set

TXERR = 1

Message Transmitted

Successfully?

Yes

Set TXREQ = 0

Is

Yes

Arbitration Lost During

Transmission

TXLARB = 1?

Yes

Is

Generate

Interrupt

TXIE = 1?

A message can also be

No

aborted, if

a message

error or lost arbitration

condition occurred during

transmission.

No

Is

TXREQ = 0

or TXABT = 1

Yes

?

Set

TXBUFE = 1

No

The TXIE bit determines if an inter-

rupt should be generated when a

message is successfully transmitted.

Abort Transmission:

Set TXABT = 1

END

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 225

PIC18FXX8

The RXM bits set special Receive modes. Normally,

these bits are set to ‘00’ to enable reception of all valid

messages, as determined by the appropriate accep-

tance filters. In this case, the determination of whether

or not to receive standard or extended messages is

determined by the EXIDE bit in the acceptance filter

register. If the RXM bits are set to ‘01’ or ‘10’, the

receiver will accept only messages with standard or

extended identifiers, respectively. If an acceptance fil-

ter has the EXIDE bit set, such that it does not corre-

spond with the RXM mode, that acceptance filter is

rendered useless. These two modes of RXM bits can

be used in systems where it is known that only standard

or extended messages will be on the bus. If the RXM

bits are set to ‘11’, the buffer will receive all messages,

regardless of the values of the acceptance filters. Also,

if a message has an error before the end of frame, that

portion of the message assembled in the MAB before

the error frame, will be loaded into the buffer. This

mode has some value in debugging a CAN system and

would not be used in an actual system environment.

19.5 Message Reception

19.5.1

RECEIVE MESSAGE BUFFERING

The PIC18FXX8 includes two full receive buffers with

multiple acceptance filters for each. There is also a

separate Message Assembly Buffer (MAB), which acts

as a third receive buffer (see Figure 19-4).

19.5.2

RECEIVE BUFFERS

Of the three receive buffers, the MAB is always commit-

ted to receiving the next message from the bus. The

remaining two receive buffers are called RXB0 and

RXB1 and can receive a complete message from the

protocol engine. The MCU can access one buffer while

the other buffer is available for message reception, or

holding a previously received message.

The MAB assembles all messages received. These

messages will be transferred to the RXBn buffers, only

if the acceptance filter criteria are met.

Note: The entire contents of the MAB are moved

into the receive buffer once a message is

accepted. This means that, regardless of

the type of identifier (standard or extended)

and the number of data bytes received, the

entire receive buffer is overwritten with the

MAB contents. Therefore, the contents of

all registers in the buffer must be assumed

to have been modified when any message

is received.

19.5.4

TIME-STAMPING

The CAN module can be programmed to generate a

time-stamp for every message that is received. When

enabled, the module generates a capture signal for

CCP1, which in turns captures the value of either

Timer1 or Timer3. This value can be used as the

message time-stamp.

To use the time-stamp capability, the CANCAP bit

(CIOCAN<4>) must be set. This replaces the capture

input for CCP1 with the signal generated from the CAN

module. In addition, CCP1CON<3:0> must be set to

‘0011’ to enable the CCP special event trigger for CAN

events.

When a message is moved into either of the receive

buffers, the appropriate RXBnIF bit is set. This bit must

be cleared by the MCU when it has completed process-

ing the message in the buffer, in order to allow a new

message to be received into the buffer. This bit pro-

vides a positive lockout to ensure that the MCU has fin-

ished with the message before the PIC18FXX8

attempts to load a new message into the receive buffer.

If the RXBnIE bit is set, an interrupt will be generated to

indicate that a valid message has been received.

FIGURE 19-4:

RECEIVE BUFFER BLOCK

DIAGRAM

Accept

Acceptance Mask

RXM1

19.5.3

RECEIVE PRIORITY

Acceptance Filter

RXM2

RXB0 is the higher priority buffer and has two message

acceptance filters associated with it. RXB1 is the lower

priority buffer and has four acceptance filters associ-

ated with it. The lower number of acceptance filters

makes the match on RXB0 more restrictive and implies

a higher priority for that buffer. Additionally, the

RXB0CON register can be configured such that if

RXB0 contains a valid message and another valid mes-

sage is received, an overflow error will not occur and

the new message will be moved into RXB1, regardless

of the acceptance criteria of RXB1. There are also two

programmable acceptance filter masks available, one

for each receive buffer (see Section 4.5).

Accept

Acceptance Mask

Acceptance Filter

RXF3

RXM0

Acceptance Filter

RXF0

Acceptance Filter

RXF4

Acceptance Filter

RXF5

Acceptance Filter

RXF1

RXB0

RXB1

Data and Data and

Identifier

When a message is received, bits <3:0> of the

RXBnCON register will indicate the acceptance filter

number that enabled reception and whether the

received message is a remote transfer request.

Message Assembly Buffer

DS41159B-page 226

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 19-5:

MESSAGE RECEPTION FLOW CHART

Start

Detect

No

Start of

Message?

Yes

Begin Loading Message into

Message Assembly Buffer (MAB)

Valid

Generate

Error

Frame

No

Message

Received?

Yes

Yes, meets criteria

for RXB1

Yes, meets criteria

for RXBO

Message

Identifier meets

a Filter Criteria?

No

Go to Start

The RXFUL bit determines if the

receive register is empty and able

to accept a new message.

The RXB0DBEN bit determines if

RXB0 can rollover into RXB1 if it is

full.

Is

No

Is

Yes

RXFUL = 0?

RX0DBEN = 1?

Yes

No

Is

No

Generate Overrun Error:

Set RXB1OVFL

Generate Overrun Error:

Set RXB0OVFL

Move Message into RXB0

Set RXRDY = 1

RXFUL = 0?

Yes

Move Message into RXB1

No

Is

Set FILHIT <0>

according to which Filter

Criteria was met

ERRIE = 1?

Set RXRDY = 1

Yes

Go to Start

Set FILHIT <2:0>

according to which Filter

Criteria was met

Is

Yes

Is

Yes

Generate

Interrupt

RXIE = 1?

No

Set CANSTAT <3:0> according

to which Receive Buffer the

Message was loaded into

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 227

PIC18FXX8

For RXB1, the RXB1CON register contains the

FILHIT<2:0> bits. They are coded as follows:

19.6 Message Acceptance Filters and

Masks

• 101= Acceptance Filter 5 (RXF5)

• 100= Acceptance Filter 4 (RXF4)

• 011= Acceptance Filter 3 (RXF3)

• 010= Acceptance Filter 2 (RXF2)

• 001= Acceptance Filter 1 (RXF1)

• 000= Acceptance Filter 0 (RXF0)

The Message Acceptance Filters and Masks are used

to determine if a message in the message assembly

buffer should be loaded into either of the receive buff-

ers. Once a valid message has been received into the

MAB, the identifier fields of the message are compared

to the filter values. If there is a match, that message will

be loaded into the appropriate receive buffer. The filter

masks are used to determine which bits in the identifier

are examined with the filters. A truth table is shown

below in Table 19-2 that indicates how each bit in the

identifier is compared to the masks and filters to deter-

mine if a message should be loaded into a receive

buffer. The mask, essentially determines which bits to

apply the acceptance filters to. If any mask bit is set to

a zero, then that bit will automatically be accepted,

regardless of the filter bit.

Note: 000 and 001 can only occur if the

RXB0DBEN bit is set in the RXB0CON

register, allowing RXB0 messages to

rollover into RXB1.

The coding of the RXB0DBEN bit enables these three

bits to be used similarly to the FILHIT bits and to distin-

guish a hit on filter RXF0 and RXF1, in either RXB0, or

after a rollover into RXB1.

• 111= Acceptance Filter 1 (RXF1)

• 110= Acceptance Filter 0 (RXF0)

• 001= Acceptance Filter 1 (RXF1)

• 000= Acceptance Filter 0

TABLE 19-2: FILTER/MASK TRUTH TABLE

Message

Identifier

bit n001

Accept or

Reject

bit n

Mask

bit n

Filter bit n

If the RXB0DBEN bit is clear, there are six codes cor-

responding to the six filters. If the RXB0DBEN bit is set,

there are six codes corresponding to the six filters, plus

two additional codes corresponding to RXF0 and RXF1

filters that rollover into RXB1.

0

1

X

0

1

X

0

1

0

1

Accept

Reject

Accept

If more than one acceptance filter matches, the FILHIT

bits will encode the binary value of the lowest num-

bered filter that matched. In other words, if filter RXF2

and filter RXF4 match, FILHIT will be loaded with the

value for RXF2. This essentially prioritizes the accep-

tance filters with a lower number filter having higher pri-

ority. Messages are compared to filters in ascending

order of filter number.

Legend: X= don’t care

As shown in the Receive Buffers Block Diagram

(Figure 19-4), acceptance filters RXF0 and RXF1, and

filter mask RXM0 are associated with RXB0. Filters

RXF2, RXF3, RXF4, and RXF5 and mask RXM1 are

associated with RXB1. When a filter matches and a

message is loaded into the receive buffer, the filter num-

ber that enabled the message reception is loaded into

the FILHIT bit(s).

The mask and filter registers can only be modified

when the PIC18FXX8 is in Configuration mode. The

mask and filter registers cannot be read outside of Con-

figuration mode. When outside of Configuration mode,

all mask and filter registers will be read as ‘0’.

FIGURE 19-6:

MESSAGE ACCEPTANCE MASK AND FILTER OPERATION

Acceptance Filter Register

Acceptance Mask Register

RXFn

RXMn

0

RXMn

RxRqst

1

RXFn

1

RXFn

RXMn

n

Message Assembly Buffer

Identifier

DS41159B-page 228

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

The Nominal Bit Time is defined as

19.7 Baud Rate Setting

TBIT = 1 / Nominal Bit rate

All nodes on a given CAN bus must have the same

nominal bit rate. The CAN protocol uses Non-Return-

to-Zero (NRZ) coding, which does not encode a clock

within the data stream. Therefore, the receive clock

must be recovered by the receiving nodes and

synchronized to the transmitters clock.

The Nominal Bit Time can be thought of as being

divided into separate, non-overlapping time segments.

These segments (Figure 19-7) include:

• Synchronization Segment (Sync_Seg)

• Propagation Time Segment (Prop_Seg)

• Phase Buffer Segment 1 (Phase_Seg1)

• Phase Buffer Segment 2 (Phase_Seg2)

As oscillators and transmission time may vary from

node to node; the receiver must have some type of

Phase Lock Loop (PLL) synchronized to data transmis-

sion edges to synchronize and maintain the receiver

clock. Since the data is NRZ coded, it is necessary to

include bit stuffing to ensure that an edge occurs at

least every six bit times, to maintain the Digital Phase

Lock Loop (DPLL) synchronization.

The time segments (and thus the Nominal Bit Time) are

in turn made up of integer units of time called Time

Quanta or TQ (see Figure 19-7). By definition, the nom-

inal bit time is programmable from a minimum of 8 TQ

to a maximum of 25 TQ. Also, by definition, the mini-

mum Nominal Bit Time is 1 µs, corresponding to a max-

imum 1 Mb/s rate. The actual duration is given by the

relationship

The bit timing of the PIC18FXX8 is implemented using

a DPLL that is configured to synchronize to the incom-

ing data, and provides the nominal timing for the trans-

mitted data. The DPLL breaks each bit time into

multiple segments, made up of minimal periods of time

called the Time Quanta (TQ).

Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg +

Phase_Seg1 + Phase_Seg2)

The Time Quantum is a fixed unit derived from the

oscillator period. It is also defined by the programmable

baud rate prescaler with integer values from 1 to 64, in

addition to a fixed divide-by-two for clock generation.

Mathematically, this is

Bus timing functions executed within the bit time frame,

such as synchronization to the local oscillator, network

transmission delay compensation, and sample point

positioning, are defined by the programmable bit timing

logic of the DPLL.

TQ (µs) = (2 * (BRP+1)) / FOSC (MHz)

All devices on the CAN bus must use the same bit rate.

However, all devices are not required to have the same

master oscillator clock frequency. For the different clock

frequencies of the individual devices, the bit rate has to

be adjusted by appropriately setting the baud rate

prescaler and number of time quanta in each segment.

or

TQ (µs) = (2 * (BRP+1)) * TOSC (µs)

where FOSC is the clock frequency, TOSC is the corre-

sponding oscillator period, and BRP is an integer (0

through 63) represented by the binary values of

BRGCON1<5:0>.

The Nominal Bit Rate is the number of bits transmitted

per second, assuming an ideal transmitter with an ideal

oscillator, in the absence of resynchronization. The

nominal bit rate is defined to be a maximum of 1 Mb/s.

FIGURE 19-7:

BIT TIME PARTITIONING

Input

Signal

Propagation

Segment

Phase

Segment 1

Phase

Segment 2

Sync

Segment

Bit

Time

Intervals

TQ

Sample Point

Nominal Bit Time

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 229

PIC18FXX8

19.7.1

TIME QUANTA

19.7.3

PROPAGATION SEGMENT

As already mentioned, the Time Quanta is a fixed unit

derived from the oscillator period and baud rate pres-

caler. Its relationship to TBIT and the Nominal Bit Rate

is shown in Example 19-2.

This part of the bit time is used to compensate for phys-

ical delay times within the network. These delay times

consist of the signal propagation time on the bus line

and the internal delay time of the nodes. The length of

the Propagation Segment can be programmed from

1 TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits.

EXAMPLE 19-2:

CALCULATING TQ,

NOMINAL BIT RATE AND

NOMINAL BIT TIME

19.7.4

PHASE BUFFER SEGMENTS

The Phase Buffer Segments are used to optimally

locate the sampling point of the received bit, within the

nominal bit time. The sampling point occurs between

phase segment 1 and phase segment 2. These seg-

ments can be lengthened or shortened by the resyn-

chronization process. The end of phase segment 1

determines the sampling point within a bit time. Phase

segment 1 is programmable from 1 TQ to 8 TQ in dura-

tion. Phase segment 2 provides delay before the next

transmitted data transition and is also programmable

from 1 TQ to 8 TQ in duration. However, due to IPT

requirements, the actual minimum length of phase seg-

ment 2 is 2 TQ, or it may be defined to be equal to the

greater of phase segment 1 or the Information

Processing Time (IPT).

TQ (µs) = (2 * (BRP+1)) / FOSC (MHz)

TBIT (µs) = TQ (µs) * number of TQ per bit interval

Nominal Bit Rate (bits/s) = 1 / TBIT

CASE 1:

For FOSC = 16 MHz, BRP<5:0> = 00h, and

Nominal Bit Time = 8 TQ:

TQ = (2*1) / 16 = 0.125 µs (125 ns)

TBIT = 8 * 0.125 = 1 µs (10^-6s)

Nominal Bit Rate = 1 / 10^-6= 10⁶bits/s (1 Mb/s)

CASE 2:

19.7.5

SAMPLE POINT

For FOSC = 20 MHz, BRP<5:0> = 01h, and

Nominal Bit Time = 8 TQ:

The Sample Point is the point of time at which the bus

level is read and the value of the received bit is deter-

mined. The sampling point occurs at the end of phase

segment 1. If the bit timing is slow and contains many

TQ, it is possible to specify multiple sampling of the bus

line at the sample point. The value of the received bit is

determined to be the value of the majority decision of

three values. The three samples are taken at the sam-

ple point, and twice before, with a time of TQ/2 between

each sample.

TQ = (2*2) / 20 = 0.2 µs (200 ns)

TBIT = 8 * 0.2 = 1.6 µs (1.6 * 10^-6S)

Nominal Bit Rate = 1 / 1.6 * 10^-6s = 625,000 bits/s

(625 Kb/s)

CASE 3:

For FOSC = 25 MHz, BRP<5:0> = 3Fh, and

Nominal Bit Time = 25 TQ:

19.7.6

INFORMATION PROCESSING TIME

TQ = (2*64) / 25 = 5.12 µs

TBIT = 25 * 5.12 = 128 µs (1.28 * 10^-4s)

Nominal Bit Rate = 1 / 1.28 * 10^-4= 7813 bits/s

The Information Processing Time (IPT) is the time seg-

ment, starting at the sample point that is reserved for

calculation of the subsequent bit level. The CAN spec-

ification defines this time to be less than or equal to

2 TQ. The PIC18FXX8 defines this time to be 2 TQ.

Thus, phase segment 2 must be at least 2 TQ long.

(7.8 Kb/s)

The frequencies of the oscillators in the different nodes

must be coordinated in order to provide a system wide

specified nominal bit time. This means that all oscilla-

tors must have a TOSC that is an integral divisor of TQ.

It should also be noted that although the number of TQ

is programmable from 4 to 25, the usable minimum is

8 TQ. A bit time of less than 8 TQ in length is not

guaranteed to operate correctly.

19.7.2

SYNCHRONIZATION SEGMENT

This part of the bit time is used to synchronize the var-

ious CAN nodes on the bus. The edge of the input sig-

nal is expected to occur during the sync segment. The

duration is 1 TQ.

DS41159B-page 230

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

The phase error of an edge is given by the position of

the edge relative to Sync Seg, measured in TQ. The

phase error is defined in magnitude of TQ as follows:

19.8 Synchronization

To compensate for phase shifts between the oscillator

frequencies of each of the nodes on the bus, each CAN

controller must be able to synchronize to the relevant

signal edge of the incoming signal. When an edge in

the transmitted data is detected, the logic will compare

the location of the edge to the expected time (Sync

Seg). The circuit will then adjust the values of phase

segment 1 and phase segment 2, as necessary. There

are two mechanisms used for synchronization.

• e = 0 if the edge lies within SYNCESEG.

• e > 0 if the edge lies before the SAMPLE POINT.

• e < 0 if the edge lies after the SAMPLE POINT of

the previous bit

If the magnitude of the phase error is less than, or equal

to, the programmed value of the synchronization jump

width, the effect of a resynchronization is the same as

that of a hard synchronization.

19.8.1

HARD SYNCHRONIZATION

If the magnitude of the phase error is larger than the

synchronization jump width, and if the phase error is

positive, then phase segment 1 is lengthened by an

amount equal to the synchronization jump width.

Hard synchronization is only done when there is a

recessive to dominant edge during a BUS IDLE condi-

tion, indicating the start of a message. After hard syn-

chronization, the bit time counters are restarted with

Sync Seg. Hard synchronization forces the edge which

has occurred to lie within the synchronization segment

of the restarted bit time. Due to the rules of synchroni-

zation, if a hard synchronization occurs, there will not

be a resynchronization within that bit time.

If the magnitude of the phase error is larger than the

resynchronization jump width, and if the phase error is

negative, then phase segment 2 is shortened by an

amount equal to the synchronization jump width.

19.8.3

SYNCHRONIZATION RULES

19.8.2

RESYNCHRONIZATION

• Only one synchronization within one bit time is

allowed.

As a result of resynchronization, phase segment 1 may

be lengthened, or phase segment 2 may be shortened.

The amount of lengthening or shortening of the phase

buffer segments has an upper bound given by the Syn-

chronization Jump Width (SJW). The value of the SJW

will be added to phase segment 1 (see Figure 19-8), or

subtracted from phase segment 2 (see Figure 19-9).

The SJW is programmable between 1 TQ and 4 TQ.

• An edge will be used for synchronization only if

the value detected at the previous sample point

(previously read bus value) differs from the bus

value immediately after the edge.

• All other recessive to dominant edges fulfilling

rules 1 and 2, will be used for resynchronization,

with the exception that a node transmitting a dom-

inant bit will not perform a resynchronization as a

result of a recessive to dominant edge with a

positive phase error.

Clocking information will only be derived from reces-

sive to dominant transitions. The property, that only a

fixed maximum number of successive bits have the

same value, ensures resynchronization to the bit

stream during a frame.

FIGURE 19-8:

LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1)

Input

Signal

Bit

Time

Segments

Prop

Segment

Phase

Segment 1

Phase

Segment 2

Sync

≤ SJW

TQ

Sample Point

Nominal Bit Length

Actual Bit Length

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 231

PIC18FXX8

FIGURE 19-9:

SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2)

Prop

Segment

Phase

Segment 1

Phase

Segment 2

Sync

≤ SJW

TQ

Sample Point

Actual Bit Length

Nominal Bit Length

19.11.1 BRGCON1

19.9 Programming Time Segments

The BRP bits control the baud rate prescaler. The

SJW<1:0> bits select the synchronization jump width in

terms of multiples of TQ.

Some requirements for programming of the time

segments:

• Prop Seg + Phase Seg 1 ≥ Phase Seg 2

• Phase Seg 2 ≥ Sync Jump Width.

19.11.2 BRGCON2

For example, assume that a 125 kHz CAN baud rate is

desired, using 20 MHz for FOSC. With a TOSC of 50 ns,

a baud rate prescaler value of 04h gives a TQ of 500 ns.

To obtain a Nominal Bit Rate of 125 kHz, the Nominal

Bit Time must be 8 µs, or 16 TQ.

The PRSEG bits set the length of the propagation seg-

ment in terms of TQ. The SEG1PH bits set the length of

phase segment 1 in TQ. The SAM bit controls how

many times the RXCAN pin is sampled. Setting this bit

to a ‘1’ causes the bus to be sampled three times; twice

at TQ/2 before the sample point, and once at the normal

sample point (which is at the end of phase segment 1).

The value of the bus is determined to be the value read

during at least two of the samples. If the SAM bit is set

to a ‘0’, then the RXCAN pin is sampled only once at

the sample point. The SEG2PHTS bit controls how the

length of phase segment 2 is determined. If this bit is

set to a ‘1’, then the length of phase segment 2 is deter-

mined by the SEG2PH bits of BRGCON3. If the

SEG2PHTS bit is set to a ‘0’, then the length of phase

segment 2 is the greater of phase segment 1 and the

information processing time (which is fixed at 2 TQ for

the PIC18FXX8).

Using 1 TQ for the Sync Segment, 2 TQ for the Propa-

gation Segment and 7 TQ for Phase Segment 1 would

place the sample point at 10 TQ after the transition.

This leaves 6 TQ for Phase Segment 2.

By the rules above, the Sync Jump Width could be the

maximum of 4 TQ. However, normally a large SJW is

only necessary when the clock generation of the differ-

ent nodes is inaccurate or unstable, such as using

ceramic resonators. Typically, an SJW of 1 is enough.

19.10 Oscillator Tolerance

As a rule of thumb, the bit timing requirements allow

ceramic resonators to be used in applications with

transmission rates of up to 125 Kbit/sec. For the full bus

speed range of the CAN protocol, a quartz oscillator is

required. A maximum node-to-node oscillator variation

of 1.7% is allowed.

19.11.3 BRGCON3

The PHSEG2<2:0> bits set the length (in TQ) of phase

segment 2, if the SEG2PHTS bit is set to a ‘1’. If the

SEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0>

bits have no effect.

19.11 Bit Timing Configuration

Registers

The configuration registers (BRGCON1, BRGCON2,

BRGCON3) control the bit timing for the CAN bus inter-

face. These registers can only be modified when the

PIC18FXX8 is in Configuration mode.

DS41159B-page 232

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

19.12.6 ERROR STATES

19.12 Error Detection

Detected errors are made public to all other nodes via

error frames. The transmission of the erroneous mes-

sage is aborted and the frame is repeated as soon as

possible. Furthermore, each CAN node is in one of the

three error states “error-active”, “error-passive” or “bus-

off” according to the value of the internal error counters.

The error-active state is the usual state, where the bus

node can transmit messages and activate error frames

(made of dominant bits), without any restrictions. In the

error-passive state, messages and passive error

frames (made of recessive bits) may be transmitted.

The bus-off state makes it temporarily impossible for

the station to participate in the bus communication.

During this state, messages can neither be received

nor transmitted.

The CAN protocol provides sophisticated error detection

mechanisms. The following errors can be detected.

19.12.1 CRC ERROR

With the Cyclic Redundancy Check (CRC), the trans-

mitter calculates special check bits for the bit

sequence, from the start of a frame until the end of the

data field. This CRC sequence is transmitted in the

CRC field. The receiving node also calculates the CRC

sequence using the same formula and performs a com-

parison to the received sequence. If a mismatch is

detected, a CRC error has occurred and an error frame

is generated. The message is repeated.

19.12.2 ACKNOWLEDGE ERROR

19.12.7 ERROR MODES AND ERROR

COUNTERS

In the Acknowledge field of a message, the transmitter

checks if the Acknowledge slot (which was sent out as

a recessive bit) contains a dominant bit. If not, no other

node has received the frame correctly. An Acknowl-

edge Error has occurred; an error frame is generated

and the message will have to be repeated.

The PIC18FXX8 contains two error counters: the

Receive Error Counter (RXERRCNT), and the Trans-

mit Error Counter (TXERRCNT). The values of both

counters can be read by the MCU. These counters are

incremented or decremented in accordance with the

CAN bus specification.

19.12.3 FORM ERROR

lf a node detects a dominant bit in one of the four seg-

ments, including end of frame, interframe space,

Acknowledge delimiter, or CRC delimiter, then a Form

Error has occurred and an error frame is generated.

The message is repeated.

The PIC18FXX8 is error-active if both error counters

are below the error-passive limit of 128. It is error-

passive if at least one of the error counters equals or

exceeds 128. It goes to bus-off if the transmit error

counter equals or exceeds the bus-off limit of 256. The

device remains in this state until the bus-off recovery

sequence is received. The bus-off recovery sequence

consists of 128 occurrences of 11 consecutive reces-

sive bits (see Figure 19-10). Note that the CAN mod-

ule, after going bus-off, will recover back to error-active

without any intervention by the MCU, if the bus remains

IDLE for 128 X 11 bit times. If this is not desired, the

error Interrupt Service Routine should address this.

The current Error mode of the CAN module can be read

by the MCU via the COMSTAT register.

19.12.4 BIT ERROR

A Bit Error occurs if a transmitter sends a dominant bit

and detects a recessive bit, or if it sends a recessive bit

and detects a dominant bit, when monitoring the actual

bus level and comparing it to the just transmitted bit. In

the case where the transmitter sends a recessive bit

and a dominant bit is detected during the arbitration

field and the Acknowledge slot, no bit error is

generated because normal arbitration is occurring.

Additionally, there is an error state warning flag bit,

EWARN, which is set if at least one of the error

counters equals or exceeds the error warning limit of

96. EWARN is reset if both error counters are less than

the error warning limit.

19.12.5 STUFF BIT ERROR

lf, between the start of frame and the CRC delimiter, six

consecutive bits with the same polarity are detected,

the bit stuffing rule has been violated. A Stuff Bit Error

occurs and an error frame is generated. The message

is repeated.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 233

PIC18FXX8

FIGURE 19-10:

ERROR MODES STATE DIAGRAM

RESET

Error-

Active

RXERRCNT < 127 or

TXERRCNT < 127

128 occurrences of

11 consecutive

"recessive" bits

RXERRCNT > 127 or

TXERRCNT > 127

Error-

Passive

TXERRCNT > 255

Bus-

Off

19.13.1 INTERRUPT CODE BITS

19.13 CAN Interrupts

The source of a pending interrupt is indicated in the

ICODE (interrupt code) bits of the CANSTAT register

(ICOD<2:0>). Interrupts are internally prioritized such

that the higher priority interrupts are assigned lower

ICODE values. Once the highest priority interrupt con-

dition has been cleared, the code for the next highest

priority interrupt that is pending (if any), will be reflected

by the ICODE bits (see Table 19-3, following page).

Note that only those interrupt sources that have their

associated CANINTE enable bit set will be reflected in

the ICODE bits.

The module has several sources of interrupts. Each of

these interrupts can be individually enabled or dis-

abled. The CANINTF register contains interrupt flags.

The CANINTE register contains the enables for the 8

main interrupts. A special set of read only bits in the

CANSTAT register, the ICODE bits, can be used in

combination with a jump table for efficient handling of

interrupts.

All interrupts have one source, with the exception of the

Error Interrupt. Any of the Error Interrupt sources can set

the Error Interrupt Flag. The source of the Error Interrupt

can be determined by reading the Communication

Status register, COMSTAT.

19.13.2 TRANSMIT INTERRUPT

When the Transmit Interrupt is enabled, an interrupt will

be generated when the associated transmit buffer

becomes empty and is ready to be loaded with a new

message. The TXBnIF bit will be set to indicate the

source of the interrupt. The interrupt is cleared by the

MCU resetting the TXBnIF bit to a ‘0’.

The interrupts can be broken up into two categories:

receive and transmit interrupts.

The receive related interrupts are:

• Receive Interrupts

• Wake-up Interrupt

• Receiver Overrun Interrupt

• Receiver Warning Interrupt

• Receiver Error-Passive Interrupt

19.13.3 RECEIVE INTERRUPT

When the Receive Interrupt is enabled, an interrupt will

be generated when a message has been successfully

received and loaded into the associated receive buffer.

This interrupt is activated immediately after receiving

the EOF field. The RXBnIF bit will be set to indicate the

source of the interrupt. The interrupt is cleared by the

MCU resetting the RXBnIF bit to a ‘0’.

The transmit related interrupts are:

• Transmit Interrupts

• Transmitter Warning Interrupt

• Transmitter Error-Passive Interrupt

• Bus-Off Interrupt

DS41159B-page 234

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 19-3: VALUES FOR ICODE<2:0>

ICOD

19.13.6 ERROR INTERRUPT

When the Error Interrupt is enabled, an interrupt is gen-

erated if an overflow condition occurs, or if the error

state of transmitter or receiver has changed. The error

flags in COMSTAT will indicate one of the following

conditions.

Interrupt

Boolean Expression

<2:0>

ERR•WAK•TX0•TX1•TX2•RX0•

RX1

000

None

001

010

011

100

101

110

Error

TXB2

TXB1

TXB0

RXB1

RXB0

ERR

19.13.6.1 Receiver Overflow

An overflow condition occurs when the MAB has

assembled a valid received message (the message

meets the criteria of the acceptance filters) and the

receive buffer associated with the filter is not available

for loading of a new message. The associated

COMSTAT.RXnOVFL bit will be set to indicate the

overflow condition. This bit must be cleared by the

MCU.

ERR•TX0•TX1•TX2

ERR•TX0•TX1

ERR•TX0

ERR•TX0•TX1•TX2•RX0•RX1

ERR•TX0•TX1•TX2•RX0

19.13.6.2 Receiver Warning

Wake on ERR•TX0•TX1•TX2•RX0•RX1•

Interrupt WAK

The receive error counter has reached the MCU

warning limit of 96.

111

Key:

19.13.6.3 Transmitter Warning

ERR = ERRIF * ERRIE RX0 = RXB0IF * RXB0IE

TX0 = TXB0IF * TXB0IE RX1 = RXB1IF * RXB1IE

TX1 = TXB1IF * TXB1IE WAK = WAKIF * WAKIE

TX2 = TXB2IF * TXB2IE

The transmit error counter has reached the MCU

warning limit of 96.

19.13.6.4 Receiver Bus Passive

The receive error counter has exceeded the error-

passive limit of 127 and the device has gone to

error-passive state.

19.13.4 MESSAGE ERROR INTERRUPT

When an error occurs during transmission or reception

of a message, the message error flag IRXIF will be set

and if the IRXIE bit is set, an interrupt will be generated.

This is intended to be used to facilitate baud rate deter-

mination when used in conjunction with Listen Only

mode.

19.13.6.5 Transmitter Bus Passive

The transmit error counter has exceeded the error-

passive limit of 127 and the device has gone to

error- passive state.

19.13.6.6 Bus-Off

19.13.5 BUS ACTIVITY WAKE-UP

INTERRUPT

The transmit error counter has exceeded 255 and the

device has gone to bus-off state.

When the PIC18FXX8 is in SLEEP mode and the Bus

Activity Wake-up Interrupt is enabled, an interrupt will

be generated, and the WAKIF bit will be set when activ-

ity is detected on the CAN bus. This interrupt causes

the PIC18FXX8 to exit SLEEP mode. The interrupt is

reset by the MCU, clearing the WAKIF bit.

19.13.7 INTERRUPT ACKNOWLEDGE

Interrupts are directly associated with one or more sta-

tus flags in the PIR register. Interrupts are pending as

long as one of the flags is set. Once an interrupt flag is

set by the device, the flag can not be reset by the

microcontroller until the interrupt condition is removed.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 235

PIC18FXX8

NOTES:

DS41159B-page 236

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

The A/D module has four registers. These registers are:

20.0 COMPATIBLE 10-BIT

ANALOG-TO-DIGITAL

• A/D Result High Register (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) Converter module has five

inputs for the PIC18F2X8 devices and eight for the

PIC18F4X8 devices. This module has the ADCON0

and ADCON1 register definitions that are compatible

with the PICmicro^®mid-range A/D module.

The ADCON0 register, shown in Register 20-1, con-

trols the operation of the A/D module. The ADCON1

register, shown in Register 20-2, configures the

functions of the port pins.

The A/D allows conversion of an analog input signal to

a corresponding 10-bit digital number.

REGISTER 20-1: ADCON0 REGISTER

R/W-0

ADCS1

bit 7

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0

R/W-0

U-0

—

R/W-0

ADON

ADCS0

GO/DONE

bit 0

bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)

ADCON1

ADCON0

Clock Conversion

0

1

00

01

10

11

00

01

10

11

FOSC/2

FOSC/8

FOSC/32

FRC (clock derived from the internal A/D RC oscillator)

FOSC/4

FOSC/16

FOSC/64

FRC (clock derived from the internal A/D RC oscillator)

bit 5-3 CHS2:CHS0: Analog Channel Select bits

000= channel 0 (AN0)

001= channel 1 (AN1)

010= channel 2 (AN2)

011= channel 3 (AN3)

100= channel 4 (AN4)

101= channel 5 (AN5)⁽¹⁾

110= channel 6 (AN6)⁽¹⁾

111= channel 7 (AN7)⁽¹⁾

Note 1: These channels are unimplemented on PIC18CF2X8 (28-pin) devices. Do not

select any unimplemented channel.

bit 2

GO/DONE: A/D Conversion Status bit

When ADON = 1:

1=A/D conversion in progress (setting this bit starts the A/D conversion which is automatically

cleared by hardware when the A/D conversion is complete)

0=A/D conversion not in progress

bit 1

bit 0

Unimplemented: Read as '0'

ADON: A/D On bit

1= A/D converter module is powered up

0= A/D converter module is shut-off and consumes no operating current

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR reset

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 237

PIC18FXX8

REGISTER 20-2: ADCON1 REGISTER

R/W-0

ADFM

R/W-0

U-0

—

U-0

—

R/W-0

PCFG0

bit 0

ADCS2

PCFG3

PCFG2

PCFG1

bit 7

bit 6

ADFM: A/D Result Format Select bit.

1= Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’.

0= Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.

ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)

ADCON1

ADCON0

Clock Conversion

0

1

00

01

10

11

00

01

10

11

FOSC/2

FOSC/8

FOSC/32

FRC (clock derived from the internal A/D RC oscillator)

FOSC/4

FOSC/16

FOSC/64

FRC (clock derived from the internal A/D RC oscillator)

bit 5-4

bit 3-0

Unimplemented: Read as '0'

PCFG3:PCFG0: A/D Port Configuration Control bits

PCFG

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

VREF+

VREF-

C / R

0000

0001

0010

0011

0100

0101

011x

1000

1001

1010

1011

1100

1101

1110

1111

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

VDD

AN3

VDD

AN3

VDD

AN3

—

VSS

—

8 / 0

7 / 1

5 / 0

4 / 1

3 / 0

2 / 1

0 / 0

6 / 2

6 / 0

5 / 1

4 / 2

3 / 2

2 / 2

1 / 0

1 / 2

VREF+

A

VREF+

A

D

VREF+

D

VREF+

A

VREF-

A

AN3

VDD

AN3

VDD

AN3

AN2

VSS

AN2

VSS

AN2

VREF+

D

A

VREF-

D

VREF+

VREF-

A = Analog input D = Digital I/O

C / R = # of analog input channels / # of A/D voltage references

Note: Shaded cells indicate channels available only on PIC18F4X8 devices.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR reset ’1’ = Bit is set

Note: On any device RESET, the port pins that are multiplexed with analog functions (ANx)

are forced to be analog inputs.

DS41159B-page 238

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

The analog reference voltage is software selectable to

either the device’s positive and negative supply voltage

(VDD and VSS), or the voltage level on the

RA3/AN3/VREF+ pin and RA2/AN2/VREF- pin.

A device RESET forces all registers to their RESET

state. This forces the A/D module to be turned off and

any conversion is aborted.

Each port pin associated with the A/D converter can be

configured as an analog input (RA3 can also be a

voltage reference), or as a digital I/O.

The A/D converter has a unique feature of being able

to operate while the device is in SLEEP mode. To oper-

ate in SLEEP, the A/D conversion clock must be

derived from the A/D’s internal RC oscillator.

The ADRESH and ADRESL registers contain the result

of the A/D conversion. When the A/D conversion is com-

plete, the result is loaded into the ADRESH/ADRESL

registers, the GO/DONE bit (ADCON0<2>) is cleared,

and A/D interrupt flag bit, ADIF, is set. The block

diagram of the A/D module is shown in Figure 20-1.

The output of the sample and hold is the input into the

converter, which generates the result via successive

approximation.

FIGURE 20-1:

A/D BLOCK DIAGRAM

CHS2:CHS0

111

AN7⁽¹⁾

110

AN6⁽¹⁾

101

AN5⁽¹⁾

100

AN4

VAIN

011

(Input Voltage)

AN3

010

AN2

10-bit

Converter

A/D

001

AN1

PCFG0

000

AN0

VDD

VREF+

VREF-

Reference

voltage

VSS

Note 1: Channels AN5 through AN7 are not available on PIC18F2X8 devices.

2: All I/O pins have diode protection to VDD and VSS.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 239

PIC18FXX8

The value that is in the ADRESH/ADRESL registers is

6. Read A/D Result registers (ADRESH/ADRESL);

clear bit ADIF if required.

not modified for

a

Power-on Reset. The

ADRESH/ADRESL registers will contain unknown data

after a Power-on Reset.

7. For next conversion, go to step 1 or step 2, as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before next acquisition starts.

After the A/D module has been configured as desired,

the selected channel must be acquired before the con-

version is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 20.1.

After this acquisition time has elapsed, the A/D conver-

sion can be started. The following steps should be fol-

lowed for doing an A/D conversion:

20.1 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 20-2. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD). The source impedance affects the offset voltage

at the analog input (due to pin leakage current). The

maximum recommended impedance for analog

sources is 2.5 kΩ. After the analog input channel is

selected (changed), this acquisition must be done

before the conversion can be started.

1. Configure the A/D module:

• Configure analog pins, voltage reference and

digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

Note: When the conversion is started, the hold-

ing capacitor is disconnected from the

input pin.

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

OR

• Waiting for the A/D interrupt

FIGURE 20-2:

ANALOG INPUT MODEL

VDD

Sampling

Switch

VT = 0.6V

ANx

SS

RIC ≤ 1k

RSS

Rs

CPIN

5 pF

I LEAKAGE

± 500 nA

VAIN

CHOLD = 120 pF

VT = 0.6V

VSS

Legend: CPIN

VT

= input capacitance

= threshold voltage

6V

5V

VDD 4V

3V

I LEAKAGE = leakage current at the pin due to

various junctions

2V

RIC

= interconnect resistance

= sampling switch

SS

CHOLD

= sample/hold capacitance (from DAC)

5

6 7 8 9 10 11

Sampling Switch (kΩ)

DS41159B-page 240

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

To calculate the minimum acquisition time,

Equation 20-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

Example 20-1 shows the calculation of the minimum

required acquisition time TACQ. This calculation is

based on the following application system assumptions:

• CHOLD

• Rs

=

120 pF

2.5 kΩ

• Conversion Error ≤ 1/2 LSb

• VDD

=

5V → Rss = 7 kΩ

50°C (system max.)

0V @ time = 0

• Temperature

• VHOLD

EQUATION 20-1: ACQUISITION TIME

TACQ

=

Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

TAMP + TC + TCOFF

EQUATION 20-2: A/D MINIMUM CHARGING TIME

VHOLD

or

Tc

=

(VREF – (VREF/2048)) • (1 - e^{(-Tc/CHOLD(RIC + RSS + RS))}

)

-(120 pF)(1 kΩ + RSS + RS) ln(1/2047)

EXAMPLE 20-1:

CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

TACQ

=

TAMP + TC + TCOFF

Temperature coefficient is only required for temperatures > 25°C.

TACQ

TC

=

2 µs + TC + [(Temp - 25°C)(0.05 µs/°C)]

-CHOLD (RIC + RSS + RS) ln(1/2047)

-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885)

-120 pF (10.5 kΩ) ln(0.0004885)

-1.26 µs (-7.6241)

9.61 µs

TACQ

=

2 µs + 9.61 µs + [(50°C - 25°C)(0.05 µs/°C)]

11.61 µs + 1.25 µs

12.86 µs

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 241

PIC18FXX8

20.2 Selecting the A/D Conversion Clock

20.3 Configuring Analog Port Pins

The A/D conversion time per bit is defined as TAD. The

A/D conversion requires 12 TAD per 10-bit conversion.

The source of the A/D conversion clock is software

selectable. The seven possible options for TAD are:

The ADCON1, TRISA and TRISE registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their corresponding

TRIS bits set (input). If the TRIS bit is cleared (output),

the digital output level (VOH or VOL) will be converted.

• 2 TOSC

The A/D operation is independent of the state of the

CHS2:CHS0 bits and the TRIS bits.

• 4 TOSC

• 8 TOSC

• 16 TOSC

Note 1: When reading the port register, all pins con-

figured as analog input channels will read

as cleared (a low level). Pins configured as

digital inputs will convert an analog input.

Analog levels on a digitally configured input

will not affect the conversion accuracy.

• 32 TOSC

• 64 TOSC

• Internal RC oscillator.

For correct A/D conversions, the A/D conversion clock

(TAD) must be selected to ensure a minimum TAD time

of 1.6 µs.

2: Analog levels on any pin that is defined as

a digital input (including the AN4:AN0

pins) may cause the input buffer to con-

sume current that is out of the devices

specification.

Table 20-1 shows the resultant TAD times derived from

the device operating frequencies and the A/D clock

source selected.

TABLE 20-1: TAD vs. DEVICE OPERATING FREQUENCIES

Device Frequency

AD Clock Source (TAD)

Operation ADCS2:ADCS0

000

20 MHz

5 MHz

1.25 MHz

333.33 kHz

2 TOSC

100 ns⁽²⁾

200 ns⁽²⁾

400 ns⁽²⁾

800 ns⁽²⁾

1.6 µs

400 ns⁽²⁾

800 ns⁽²⁾

1.6 µs

3.2 µs

6 µs

12 µs

4 TOSC

8 TOSC

16 TOSC

32 TOSC

64 TOSC

RC

100

001

101

010

110

011

6.4 µs

24 µs⁽³⁾

48 µs⁽³⁾

96 µs⁽³⁾

192 µs⁽³⁾

2 - 6 µs⁽¹⁾

3.2 µs

6.4 µs

12.8 µs

25.6 µs⁽³⁾

51.2 µs⁽³⁾

2 - 6 µs⁽¹⁾

3.2 µs

2 - 6 µs⁽¹⁾

12.8 µs

2 - 6 µs⁽¹⁾

Legend: Shaded cells are outside of recommended range.

Note 1: The RC source has a typical TAD time of 4 µs.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

TABLE 20-2: TAD vs. DEVICE OPERATING FREQUENCIES (FOR EXTENDED, LC DEVICES)

Device Frequency

AD Clock Source (TAD)

Operation ADCS2:ADCS0

000

4 MHz

2 MHz

1.25 MHz

333.33 kHz

2 TOSC

500 ns⁽²⁾

1.0 µs⁽²⁾

2.0 µs⁽²⁾

4.0 µs⁽²⁾

8.0 µs

1.0 µs⁽²⁾

2.0 µs⁽²⁾

4.0 µs

1.6 µs⁽²⁾

3.2 µs⁽²⁾

6.4 µs

6 µs

12 µs

4 TOSC

8 TOSC

16 TOSC

32 TOSC

64 TOSC

RC

100

001

101

010

110

011

24 µs⁽³⁾

48 µs⁽³⁾

96 µs⁽³⁾

192 µs⁽³⁾

3 - 9 µs^(1,4)

8.0 µs

12.8 µs

16.0 µs

32.0 µs

3 - 9 µs^(1,4)

25.6 µs⁽³⁾

51.2 µs⁽³⁾

3 - 9 µs^(1,4)

16.0 µs

3 - 9 µs^(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1: The RC source has a typical TAD time of 6 µs.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

DS41159B-page 242

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

20.4 A/D Conversions

20.5 Use of the ECCP Trigger

Figure 20-3 shows the operation of the A/D converter

after the GO bit has been set. Clearing the GO/DONE

bit during a conversion will abort the current conver-

sion. The A/D result register pair will NOT be updated

with the partially completed A/D conversion sample.

That is, the ADRESH:ADRESL registers will continue

to contain the value of the last completed conversion

(or the last value written to the ADRESH:ADRESL reg-

isters). After the A/D conversion is aborted, a 2 TAD wait

is required before the next acquisition is started. After

this 2 TAD wait, acquisition on the selected channel is

automatically started.

An A/D conversion can be started by the “special event

trigger” of the ECCP module. This requires that the

ECCP1M3:ECCP1M0 bits (ECCP1CON<3:0>) be pro-

grammed as 1011and that the A/D module is enabled

(ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, starting the A/D conversion and

the Timer1 (or Timer3) counter will be reset to zero.

Timer1 (or Timer3) is reset to automatically repeat the

A/D acquisition period with minimal software overhead

(moving ADRESH/ADRESL to the desired location). The

appropriate analog input channel must be selected and

the minimum acquisition done before the “special event

trigger” sets the GO/DONE bit (starts a conversion).

Note: The GO/DONE bit should NOT be set in

If the A/D module is not enabled (ADON is cleared), the

“special event trigger” will be ignored by the A/D module,

but will still reset the Timer1 (or Timer3) counter.

the same instruction that turns on the A/D.

FIGURE 20-3:

A/D CONVERSION TAD CYCLES

TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11

b2 b1 b0

b3 b0

b7

b6

b5

b4

b8

b9

Conversion Starts

Holding capacitor is disconnected from analog input

(typically 100 ns)

Set GO bit

Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

TABLE 20-3: SUMMARY OF A/D REGISTERS

Value on

all other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

TXIE

TXIP

EEIF

EEIE

EEIP

RBIE

SSPIF

SSPIE

SSPIP

BCLIF

BCLIE

BCLIP

TMR0IF

CCP1IF

CCP1IE

CCP1IP

LVDIF

INT0IF

TMR2IF

TMR2IE

TMR2IP

RBIF

0000 000x 0000 000u

0000 0000 0000 0000

-0-0 0000 -0-0 0000

xxxx xxxx uuuu uuuu

(1)

PIR1

PIE1

IPR1

PIR2

PIE2

IPR2

PSPIF

PSPIE

PSPIP

—

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

—

TMR1IF

TMR1IE

TMR1IP

(1)

CMIF

CMIE

CMIP

TMR3IF ECCP1IF

TMR3IE ECCP1IE

TMR3IP ECCP1IP

(1)

—

LVDIE

—

LVDIP

ADRESH A/D Result Register

ADRESL A/D Result Register

ADCON0 ADCS1

ADCS0

ADCS2

RA6

CHS2

—

CHS1

—

CHS0 GO/DONE

—

ADON

PCFG0

RA0

0000 00-0 0000 00-0

00-- 0000 00-- 0000

-00x 0000 -00u 0000

-111 1111 -111 1111

---- -000 ---- -000

---- -xxx ---- -uuu

0000 -111 0000 -111

ADCON1

PORTA

TRISA

PORTE

LATE

ADFM

—

PCFG3

RA3

PCFG2

RA2

PCFG1

RA1

RA5

RA4

—

PORTA Data Direction Register

—

RE2

RE1

RE0

—

LATE2

TRISE2

LATE1

TRISE1

LATE0

TRISE

IBF

OBF

IBOV

PSPMODE

TRISE0

—

Legend: x = unknown, u = unchanged, - = unimplemented, read as ’0’. Shaded cells are not used for A/D conversion.

Note 1: These bits are reserved on PIC18F2X8 devices; always maintain these bits clear.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 243

PIC18FXX8

NOTES:

DS41159B-page 244

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

The CMCON register, shown in Register 21-1, controls

the comparator input and output multiplexers. A block

diagram of the comparator is shown in Figure 21-1.

21.0 COMPARATOR MODULE

Note: The analog comparators are only available

on the PIC18F448 and PIC18F458.

The comparator module contains two analog compara-

tors. The inputs to the comparators are multiplexed

with the RD0 through RD3 pins. The On-Chip Voltage

Reference (Section 22.0) can also be an input to the

comparators.

REGISTER 21-1: CMCON REGISTER

R-0

R/W-0

C2INV

R/W-0

C1INV

R/W-0

CIS

R/W-0

CM2

R/W-0

CM1

R/W-0

CM0

C2OUT

C1OUT

bit 7

bit 0

bit 7

C2OUT: Comparator 2 Output bit

When C2INV = 0:

1= C2 VIN+ > C2 VIN–

0= C2 VIN+ < C2 VIN–

When C2INV = 1:

1= C2 VIN+ < C2 VIN–

0= C2 VIN+ > C2 VIN–

bit 6

C1OUT: Comparator 1 Output bit

When C1INV = 0:

1= C1 VIN+ > C1 VIN–

0= C1 VIN+ < C1 VIN–

When C1INV = 1:

1= C1 VIN+ < C1 VIN–

0= C1 VIN+ > C1 VIN–

bit 5

bit 4

bit 3

C2INV: Comparator 2 Output Inversion bit

1= C2 output inverted

0= C2 output not inverted

C1INV: Comparator 1 Output Inversion bit

1= C1 output inverted

0= C1 output not inverted

CIS: Comparator Input Switch bit

When CM2:CM0 = 110:

1= C1 VIN- connects to RD0/PSP0

C2 VIN- connects to RD2/PSP2

0= C1 VIN- connects to RD1/PSP1

C2 VIN- connects to RD3/PSP3

bit 2-0

CM2:CM0: Comparator Mode bits

Figure 21-1 shows the Comparator modes and CM2:CM0 bit settings

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 245

PIC18FXX8

mode is changed, the comparator output level may not

be valid for the specified mode change delay, shown in

Electrical Specifications (Section 27.0).

21.1 Comparator Configuration

There are eight modes of operation for the compara-

tors. The CMCON register is used to select these

modes. Figure 21-1 shows the eight possible modes.

The TRISD register controls the data direction of the

comparator pins for each mode. If the Comparator

Note: Comparator interrupts should be disabled

during

a

Comparator mode change.

Otherwise, a false interrupt may occur.

FIGURE 21-1:

COMPARATOR I/O OPERATING MODES

Comparators Reset (POR Default Value)

Comparators Off

CM2:CM0 = 000

CM2:CM0 = 111

A

D

VIN-

RD1/PSP1

RD0/PSP0

RD1/PSP1

Off (Read as ’0’)

C1

C2

C1

C2

VIN+

A

D

RD0/PSP0

A

D

VIN-

RD3/PSP3

RD2/PSP2

RD3/PSP3

VIN+

D

RD2/PSP2

Two Independent Comparators with Outputs

CM2:CM0 = 011

Two Independent Comparators

CM2:CM0 = 010

A

VIN-

A

VIN-

RD1/PSP1

RD0/PSP0

RD1/PSP1

RD0/PSP0

C1OUT

C2OUT

C1

C2

VIN+

A

C1OUT

C2OUT

C1

C2

VIN+

A

RE1/WR/AN6

A

VIN-

A

VIN-

RD3/PSP3

RD2/PSP2

RD3/PSP3

RD2/PSP2

VIN+

A

RE2/CS/AN7

Two Common Reference Comparators

Two Common Reference Comparators with Outputs

CM2:CM0 = 100

CM2:CM0 = 101

A

VIN-

RD1/PSP1

RD0/PSP0

RD1/PSP1

RD0/PSP0

C1OUT

C2OUT

C1OUT

C1

C2

C1

C2

VIN+

A

RE1/WR/AN6

A

D

VIN-

RD3/PSP3

RD2/PSP2

A

VIN-

VIN+

RD3/PSP3

RD2/PSP2

C2OUT

VIN+

D

RE2/CS/AN7

Four Inputs Multiplexed to Two Comparators

One Independent Comparator with Output

CM2:CM0 = 110

CM2:CM0 = 001

A

VIN-

RD1/PSP1

RD0/PSP0

CIS = 0

CIS = 1

VIN-

A

C1OUT

C1

C2

VIN+

RD0/PSP0

C1OUT

C2OUT

C1

C2

VIN+

RE1/WR/AN6

A

RD3/PSP3

RD2/PSP2

VIN-

CIS = 0

CIS = 1

VIN+

D

VIN-

RD3/PSP3

RD2/PSP2

Off (Read as ’0’)

VIN+

D

CVREF

From VREF Module

A = Analog Input, port reads zeros always

D = Digital Input

CIS (CMCON<3>) is the Comparator Input Switch

DS41159B-page 246

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

21.3.2

INTERNAL REFERENCE SIGNAL

21.2 Comparator Operation

The comparator module also allows the selection of an

internally generated voltage reference for the compara-

tors. Section 22.0 contains a detailed description of the

Comparator Voltage Reference Module that provides

this signal. The internal reference signal is used when

comparators are in mode CM<2:0> = 110(Figure 21-1).

In this mode, the internal voltage reference is applied to

the VIN+ pin of both comparators.

A single comparator is shown in Figure 21-2 along with

the relationship between the analog input levels and

the digital output. When the analog input at VIN+ is less

than the analog input VIN-, the output of the comparator

is a digital low level. When the analog input at VIN+ is

greater than the analog input VIN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 21-2 represent

the uncertainty due to input offsets and response time.

21.4 Comparator Response Time

21.3 Comparator Reference

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output has a valid level. If the internal ref-

erence is changed, the maximum delay of the internal

voltage reference must be considered when using the

comparator outputs. Otherwise the maximum delay of

the comparators should be used (Section 27.0).

An external or internal reference signal may be used

depending on the Comparator Operating mode. The

analog signal present at VIN- is compared to the signal

at VIN+, and the digital output of the comparator is

adjusted accordingly (Figure 21-2).

FIGURE 21-2:

SINGLE COMPARATOR

21.5 Comparator Outputs

The comparator outputs are read through the CMCON

register. These bits are read only. The comparator

outputs may also be directly output to the RE1 and RE2

I/O pins. When enabled, multiplexors in the output path

of the RE1 and RE2 pins will switch and the output of

each pin will be the unsynchronized output of the com-

parator. The uncertainty of each of the comparators is

related to the input offset voltage and the response time

given in the specifications. Figure 21-3 shows the

comparator output block diagram.

VIN+

VIN-

+

-

Output

VIN-

V

IN–

VIN+

V

IN+

The TRISE bits will still function as an output enable/

disable for the RE1 and RE2 pins while in this mode.

The polarity of the comparator outputs can be changed

using the C2INV and C1INV bits (CMCON<4:5>).

Output

utput

Note 1: When reading the PORT register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert an analog input, according to the

Schmitt Trigger input specification.

21.3.1

EXTERNAL REFERENCE SIGNAL

When external voltage references are used, the

comparator module can be configured to have the com-

parators operate from the same, or different reference

sources. However, threshold detector applications may

require the same reference. The reference signal must

be between VSS and VDD, and can be applied to either

pin of the comparator(s).

2: Analog levels on any pin defined as a dig-

ital input, may cause the input buffer to

consume more current than is specified.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 247

PIC18FXX8

FIGURE 21-3:

COMPARATOR OUTPUT BLOCK DIAGRAM

Port Pins

MULTIPLEX

+

-

CxINV

To RE1 or

RE2 pin

Bus

Data

Q

D

Read CMCON

EN

Q

Set

CMIF

bit

D

From

Other

Comparator

EN

CL

Read CMCON

RESET

21.6 Comparator Interrupts

Note: If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR

registers) interrupt flag may not get set.

The comparator interrupt flag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<7:6>, to

determine the actual change that occurred. The CMIF

bit (PIR registers) is the comparator interrupt flag. The

CMIF bit must be reset by clearing ‘0’. Since it is also

possible to write a '1' to this register, a simulated

interrupt may be initiated.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of CMCON will end the

mismatch condition.

b) Clear flag bit CMIF.

The CMIE bit (PIE registers) and the PEIE bit (INTCON

register) must be set to enable the interrupt. In addition,

the GIE bit must also be set. If any of these bits are

clear, the interrupt is not enabled, though the CMIF bit

will still be set if an interrupt condition occurs.

A mismatch condition will continue to set flag bit CMIF.

Reading CMCON will end the mismatch condition and

allow flag bit CMIF to be cleared.

.

DS41159B-page 248

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

21.7 Comparator Operation During

SLEEP

21.8 Effects of a RESET

A device RESET forces the CMCON register to its

RESET state, causing the comparator module to be in

the comparator RESET mode, CM<2:0> = 000. This

ensures that all potential inputs are analog inputs.

Device current is minimized when analog inputs are

present at RESET time. The comparators will be

powered down during the RESET interval.

When a comparator is active and the device is placed

in SLEEP mode, the comparator remains active and

the interrupt is functional, if enabled. This interrupt will

wake-up the device from SLEEP mode, when enabled.

While the comparator is powered up, higher SLEEP

currents than shown in the power-down current

specification will occur. Each operational comparator

will consume additional current, as shown in the com-

parator specifications. To minimize power consumption

while in SLEEP mode, turn off the comparators,

CM<2:0> = 111, before entering SLEEP. If the device

wakes up from SLEEP, the contents of the CMCON

register are not affected.

21.9 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 21-4. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. The analog input, therefore, must be between

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latchup condition may

occur. A maximum source impedance of 10 kΩ is rec-

ommended for the analog sources. Any external com-

ponent connected to an analog input pin, such as a

capacitor or a Zener diode, should have very little

leakage current.

FIGURE 21-4:

ANALOG INPUT MODEL

VDD

VT = 0.6V

RIC

RS < 10k

AIN

I LEAKAGE

500 nA

CPIN

5 pF

VA

VT = 0.6V

VSS

Legend:

CPIN

VT

=

Input Capacitance

Threshold Voltage

I LEAKAGE = Leakage Current at the pin due to various junctions

RIC

RS

VA

=

Interconnect Resistance

Source Impedance

Analog Voltage

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 249

PIC18FXX8

TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Value on

all other

RESETS

Value on

POR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CMCON C2OUT C1OUT C2INV

CVRCON CVREN CVROE CVRR

C1INV

CVRSS

INT0IE

CIS

CM2

CM1

CM0

CVR0

RBIF

0000 0000 0000 0000

0000 000x 0000 000u

CVR3 CVR2

CVR1

INTCON

GIE/

PEIE/ TMR0IE

GIEL

RBIE TMR0IF INT0IF

GIEH

PIR2

—

CMIF⁽¹⁾

CMIE⁽¹⁾

CMIP⁽¹⁾

RD6

—

EEIF

EEIE

EEIP

RD4

BCLIF LVDIF TMR3IF ECCP1IF⁽¹⁾-0-0 0000 -0-0 0000

BCLIE LVDIE TMR3IE ECCP1IE⁽¹⁾-0-0 0000 -0-0 0000

BCLIP LVDIP TMR3IP ECCP1IP⁽¹⁾-1-1 1111 -1-1 1111

PIE2

IPR2

—

PORTD

LATD

TRISD

PORTE

LATE

RD7

RD5

RD3

RD2

RD1

RD0

x000 0000 u000 0000

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

---- -000 ---- -000

---- -xxx ---- -uuu

LATD7 LATD6 LATD5

LATD4

LATD3 LATD2 LATD1

LATD0

PORTD Data Direction Register

—

RE2

RE1

RE0

LATE2 LATE1

LATE0

TRISE

IBF⁽¹⁾OBF⁽¹⁾IBOV⁽¹⁾PSPMODE⁽¹⁾

TRISE2 TRISE1 TRISE0 0000 -111 0000 -111

Legend: x= unknown, u= unchanged, - = unimplemented, read as "0"

Note 1: These bits are reserved on PIC18F2X8 devices; always maintain these bits clear.

DS41159B-page 250

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

22.1 Configuring the Comparator

22.0 COMPARATOR VOLTAGE

REFERENCE MODULE

Voltage Reference

The Comparator Voltage Reference can output 16 dis-

tinct voltage levels for each range. The equations used

to calculate the output of the Comparator Voltage

Reference are as follows.

Note: The Comparator Voltage Reference is only

available on the PIC18F448 and

PIC18F458.

This module is a 16-tap resistor ladder network that

provides a selectable voltage reference. The resistor

ladder is segmented to provide two ranges of CVREF

values and has a power-down function to conserve

power when the reference is not being used. The

CVRCON register controls the operation of the

reference as shown in Register 22-1. The block

diagram is shown in Figure 22-1.

EQUATION 22-1:

If CVRR = 1:

CVREF = (CVR<3:0>/24) x CVRSRC

where:

CVRSS = 1, CVRSRC = (VREF+) – (VREF-)

CVRSS = 0, CVRSRC = VDD – VSS

The comparator and reference supply voltage can

come from either VDD and VSS, or the external VREF+

and VREF-, that are multiplexed with RA3 and RA2. The

comparator reference supply voltage is controlled by

the CVRSS bit.

EQUATION 22-2:

If CVRR = 0:

CVREF = (CVRSRC x 1/4) + (CVR<3:0>/32) x CVRSRC

where:

CVRSS = 1, CVRSRC = (VREF+) – (VREF-)

CVRSS = 0, CVRSRC = VDD – VSS

The settling time of the Comparator Voltage Reference

must be considered when changing the RA0/AN0/CVREF

output (see Table 27-4 in Section 27.2).

REGISTER 22-1:

CVRCON REGISTER

R/W-0

CVRR

R/W-0

CVR3

R/W-0

CVR2

R/W-0

CVR1

R/W-0

CVR0

CVREN

CVROE

CVRSS

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3-0

CVREN: Comparator Voltage Reference Enable bit

1= CVREF circuit powered on

0= CVREF circuit powered down

CVROE: Comparator VREF Output Enable bit

1= CVREF voltage level is also output on the RA0/AN0/CVREF pin

0= CVREF voltage is disconnected from the RA0/AN0/CVREF pin

CVRR: Comparator VREF Range Selection bit

1= 0.00 CVRSRC to 0.625 CVRSRC, with CVRSRC/24 step size

0= 0.25 CVRSRC to 0.719 CVRSRC, with CVRSRC/32 step size

CVRSS: Comparator VREF Source Selection bit

1= Comparator reference source CVRSRC = VDD – VSS

0= Comparator reference source CVRSRC = (VREF+) – (VREF-)

CVR<3:0>: Comparator VREF Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bits

When CVRR = 1:

CVREF = (CVR3:CVR0/24) • (CVRSRC)

When CVRR = 0:

CVREF = 1/4 • (CVRSRC) + (CVR3:CVR0/32) • (CVRSRC)

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’0’ = Bit is cleared

x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 251

PIC18FXX8

FIGURE 22-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

VDD

VREF+

16 Stages

CVRSS = 0

CVRSS = 1

CVREN

R

8R

R

CVRR

CVRSS = 0

8R

CVRSS = 1

RA2/AN2VREF-

CVR3

RA0/AN0/CVREF

or CVREF of Comparator

(From CVRCON<3:0>)

CVR0

16-to-1 Analog MUX

22.2 Voltage Reference Accuracy/Error

22.4 Effects of a RESET

The full range of voltage reference cannot be realized

due to the construction of the module. The transistors

on the top and bottom of the resistor ladder network

(Figure 22-1) keep VREF from approaching the refer-

ence source rails. The voltage reference is derived

from the reference source; therefore, the VREF output

changes with fluctuations in that source. The absolute

accuracy of the voltage reference can be found in

Section 27.0.

A device RESET disables the voltage reference by

clearing bit CVREN (CVRCON register). This RESET

also disconnects the reference from the RA2 pin by

clearing bit CVROE (CVRCON register) and selects

the high voltage range by clearing bit CVRR (CVRCON

register). The CVRSS value select bits, CVRCON<3:0>,

are also cleared.

22.5 Connection Considerations

The voltage reference module operates independently

of the comparator module. The output of the reference

generator may be connected to the RA0/AN0 pin if the

TRISA<0> bit is set and the CVROE bit (CVRCON<6>)

is set. Enabling the voltage reference output onto the

RA0/AN0 pin, with an input signal present, will increase

current consumption. Connecting RA0/AN0 as a digital

output with CVRSS enabled, will also increase current

consumption.

22.3 Operation During SLEEP

When the device wakes up from SLEEP through an

interrupt or a Watchdog Timer Time-out, the contents of

the CVRCON register are not affected. To minimize

current consumption in SLEEP mode, the voltage

reference should be disabled.

The RA0/AN0 pin can be used as a simple D/A output

with limited drive capability. Due to the limited current

drive capability, a buffer must be used on the voltage

reference output for external connections to VREF.

Figure 22-2 shows an example buffering technique.

DS41159B-page 252

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 22-2:

VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

(1)

R

RA0/AN0

CVREF

Module

+

–

•

CVREF Output

•

Voltage

Reference

Output

Impedance

Note 1: R is dependent upon the voltage reference configuration CVRCON<3:0> and CVRCON<5>.

TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE

Value on

all other

RESETS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR

CVRCON CVREN CVROE CVRR CVRSS CVR3

CVR2

CM2

CVR1

CM1

CVR0 0000 0000 0000 0000

CM0 0000 0000 0000 0000

CMCON

TRISA

C2OUT C1OUT C2INV C1INV

CIS

—

TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 -111 1111

Legend: x= unknown, u= unchanged, - = unimplemented, read as "0".

Shaded cells are not used with the comparator voltage reference.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 253

PIC18FXX8

NOTES:

DS41159B-page 254

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Figure 23-1 shows a possible application voltage curve

(typically for batteries). Over time, the device voltage

decreases. When the device voltage equals voltage VA,

the LVD logic generates an interrupt. This occurs at

time TA. The application software then has the time,

until the device voltage is no longer in valid operating

range, to shutdown the system. Voltage point VB is the

minimum valid operating voltage specification. This

occurs at time TB. The difference TB – TA is the total

time for shutdown.

23.0 LOW VOLTAGE DETECT

In many applications, the ability to determine if the

device voltage (VDD) is below a specified voltage level

is a desirable feature. A window of operation for the

application can be created, where the application soft-

ware can do “housekeeping tasks” before the device

voltage exits the valid operating range. This can be

done using the Low Voltage Detect module.

This module is a software programmable circuitry,

where a device voltage trip point can be specified.

When the voltage of the device becomes lower than the

specified point, an interrupt flag is set. If the interrupt is

enabled, the program execution will branch to the inter-

rupt vector address and the software can then respond

to that interrupt source.

The block diagram for the LVD module is shown in

Figure 23-2. A comparator uses an internally gener-

ated reference voltage as the set point. When the

selected tap output of the device voltage crosses the

set point (is lower than), the LVDIF bit is set.

Each node in the resistor divider represents a “trip

point” voltage. The “trip point” voltage is the minimum

supply voltage level at which the device can operate

before the LVD module asserts an interrupt. When the

supply voltage is equal to the trip point, the voltage

tapped off of the resistor array is equal to the internal

reference voltage generated by the voltage reference

module. The comparator then generates an interrupt

signal setting the LVDIF bit. This voltage is software

programmable to any one of 16 values (see

Figure 23-2). The trip point is selected by programming

the LVDL3:LVDL0 bits (LVDCON<3:0>).

The Low Voltage Detect circuitry is completely under

software control. This allows the circuitry to be “turned

off” by the software, which minimizes the current

consumption for the device.

FIGURE 23-1:

TYPICAL LOW VOLTAGE DETECT APPLICATION

VA

VB

Legend:

VA = LVD trip point

VB = Minimum valid device

operating voltage

TB

TA

Time

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 255

PIC18FXX8

FIGURE 23-2:

LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM

VDD

LVDIN

LVD3:LVD0

LVDCON

Register

LVDIF

Internally Generated

Reference Voltage

LVDEN

The LVD module has an additional feature that allows

the user to supply the trip voltage to the module from

an external source. This mode is enabled when bits

LVDL3:LVDL0 are set to ‘1111’. In this state, the com-

parator input is multiplexed from the external input pin

LVDIN to one input of the comparator (Figure 23-3).

The other input is connected to the internally gener-

ated voltage reference (parameter D423 in

Section 27.2). This gives users flexibility, because it

allows them to configure the Low Voltage Detect inter-

rupt to occur at any voltage in the valid operating

range.

FIGURE 23-3:

LOW VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM

VDD

LVD3:LVD0

LVDCON

Register

LVDIN

LVDEN

Externally Generated

Trip Point

LVD

VxEN

BODEN

EN

BGAP

DS41159B-page 256

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

23.1 Control Register

The Low Voltage Detect Control register controls the

operation of the Low Voltage Detect circuitry.

REGISTER 23-1: LVDCON REGISTER

U-0

—

U-0

—

R-0

R/W-0

LVDL3

R/W-1

LVDL2

R/W-0

LVDL1

R/W-1

LVDL0

IRVST

LVDEN

bit 7

bit 0

bit 7-6

bit 5

Unimplemented: Read as '0'

IRVST: Internal Reference Voltage Stable Flag bit

1= Indicates that the Low Voltage Detect logic will generate the interrupt flag at the

specified voltage range

0= Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the

specified voltage range and the LVD interrupt should not be enabled

bit 4

LVDEN: Low Voltage Detect Power Enable bit

1= Enables LVD, powers up LVD circuit

0= Disables LVD, powers down LVD circuit

bit 3-0

LVDL3:LVDL0: Low Voltage Detection Limit bits

1111= External analog input is used (input comes from the LVDIN pin)

1110= 4.5V min. - 4.77V max.

1101= 4.2V min. - 4.45V max.

1100= 4.0V min. - 4.24V max.

1011= 3.8V min. - 4.03V max.

1010= 3.6V min. - 3.82V max.

1001= 3.5V min. - 3.71V max.

1000= 3.3V min. - 3.50V max.

0111= 3.0V min. - 3.18V max.

0110= 2.8V min. - 2.97V max.

0101= 2.7V min. - 2.86V max.

0100= 2.5V min. - 2.65V max.

0011= 2.4V min. - 2.54V max.

0010= 2.2V min. - 2.33V max.

0001= 2.0V min. - 2.12V max.

0000= Reserved

Note:

LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage

of the device, are not tested.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 257

PIC18FXX8

The following steps are needed to set up the LVD

module:

23.2 Operation

Depending on the power source for the device voltage,

the voltage normally decreases relatively slowly. This

means that the LVD module does not need to be con-

stantly operating. To decrease the current require-

ments, the LVD circuitry only needs to be enabled for

short periods, where the voltage is checked. After

doing the check, the LVD module may be disabled.

1. Write the value to the LVDL3:LVDL0 bits

(LVDCON register), which selects the desired

LVD trip point.

2. Ensure that LVD interrupts are disabled (the

LVDIE bit is cleared or the GIE bit is cleared).

3. Enable the LVD module (set the LVDEN bit in

the LVDCON register).

Each time that the LVD module is enabled, the circuitry

requires some time to stabilize. After the circuitry has

stabilized, all status flags may be cleared. The module

will then indicate the proper state of the system.

4. Wait for the LVD module to stabilize (the IRVST

bit to become set).

5. Clear the LVD interrupt flag, which may have

falsely become set until the LVD module has

stabilized (clear the LVDIF bit).

6. Enable the LVD interrupt (set the LVDIE and the

GIE bits).

Figure 23-4 shows typical waveforms that the LVD

module may be used to detect.

FIGURE 23-4:

LOW VOLTAGE DETECT WAVEFORMS

CASE 1:

LVDIF may not be set

VDD

.

VLVD

LVDIF

Enable LVD

Internally Generated

Reference Stable

TIVRST

LVDIF cleared in software

CASE 2:

VDD

VLVD

LVDIF

Enable LVD

TIVRST

Internally Generated

Reference Stable

LVDIF cleared in software

LVDIF cleared in software,

LVDIF remains set since LVD condition still exists

DS41159B-page 258

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

23.2.1

REFERENCE VOLTAGE SET POINT

23.3 Operation During SLEEP

The Internal Reference Voltage of the LVD module may

be used by other internal circuitry (the Programmable

Brown-out Reset). If these circuits are disabled (lower

current consumption), the reference voltage circuit

requires a time to become stable before a low voltage

condition can be reliably detected. This time is invariant

of system clock speed. This start-up time is specified in

electrical specification parameter 36. The low voltage

interrupt flag will not be enabled until a stable reference

voltage is reached. Refer to the waveform in Figure 23-4.

When enabled, the LVD circuitry continues to operate

during SLEEP. If the device voltage crosses the trip

point, the LVDIF bit will be set and the device will

wake-up from SLEEP. Device execution will continue

from the interrupt vector address if interrupts have

been globally enabled.

23.4 Effects of a RESET

A device RESET forces all registers to their RESET

state. This forces the LVD module to be turned off.

23.2.2

CURRENT CONSUMPTION

When the module is enabled, the LVD comparator and

voltage divider are enabled and will consume static cur-

rent. The voltage divider can be tapped from multiple

places in the resistor array. Total current consumption,

when enabled, is specified in electrical specification

parameter D022B.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 259

PIC18FXX8

NOTES:

DS41159B-page 260

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

SLEEP mode is designed to offer a very low current

power-down mode. The user can wake-up from SLEEP

through external RESET, Watchdog Timer Wake-up or

through an interrupt. Several oscillator options are also

made available to allow the part to fit the application.

The RC oscillator option saves system cost, while the

LP crystal option saves power. A set of configuration

bits is used to select various options.

24.0 SPECIAL FEATURES OF THE

CPU

There are several features intended to maximize sys-

tem reliability, minimize cost through elimination of

external components, provide power saving operating

modes and offer code protection. These are:

• OSC Selection

• RESET

24.1 Configuration Bits

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

The configuration bits can be programmed (read as '0'),

or left unprogrammed (read as '1'), to select various

device configurations. These bits are mapped starting

at program memory location 300000h.

The user will note that address 300000h is beyond the

user program memory space. In fact, it belongs to the

configuration memory space (300000h - 3FFFFFh),

which can only be accessed using Table Reads and

Table Writes.

• Watchdog Timer (WDT)

• SLEEP

• Code Protection

• ID Locations

Programming the configuration registers is done in a

manner similar to programming the FLASH memory.

The EECON1 register WR bit starts a self-timed write

to the configuration register. In normal operation mode,

a TBLWT instruction with the TBLPTR pointed to the

configuration register sets up the address and the data

for the configuration register write. Setting the WR bit

starts a long write to the configuration register. The con-

figuration registers are written a byte at a time. To write

or erase a configuration cell, a TBLWTinstruction can

write a ‘1’ or a ‘0’ into the cell.

• In-Circuit Serial Programming

All PIC18FXX8 devices have a Watchdog Timer, which

is permanently enabled via the configuration bits or

software controlled. It runs off its own RC oscillator for

added reliability. There are two timers that offer neces-

sary delays on power-up. One is the Oscillator Start-up

Timer (OST), intended to keep the chip in RESET until

the crystal oscillator is stable. The other is the Power-

up Timer (PWRT), which provides a fixed delay on

power-up only, designed to keep the part in RESET

while the power supply stabilizes. With these two tim-

ers on-chip, most applications need no external

RESET circuitry.

TABLE 24-1: CONFIGURATION BITS AND DEVICE IDS

Default/

Unprogrammed

Value

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300001h

CONFIG1H

—

OSCSEN

—

FOSC2

BORV0

FOSC1

BOREN

FOSC0

--1- -111

300002h

300003h

300006h

300008h

300009h

30000Ah

30000Bh

30000Ch

30000Dh

CONFIG2L

CONFIG2H

CONFIG4L

CONFIG5L

CONFIG5H

CONFIG6L

CONFIG6H

CONFIG7L

CONFIG7H

—

BORV1

PWRTEN

WDTEN

STVREN

CP0

---- 1111

1--- -1-1

---- 1111

11-- ----

---- 1111

111- ----

---- 1111

-1-- ----

(1)

WDTPS2 WDTPS1 WDTPS0

DEBUG

—

CP3

—

LVP

CP2

—

CP1

—

CPD

—

CPB

—

WRT3

—

WRT2

—

WRT1

—

WRT0

—

WRTD

—

WRTB

—

WRTC

—

EBTR3

—

EBTR2

—

EBTR1

—

EBTR0

—

EBTRB

DEV1

DEV9

—

3FFFFEh DEVID1

3FFFFFh DEVID2

DEV2

DEV10

DEV0

DEV8

REV4

DEV7

REV3

DEV6

REV2

DEV5

REV1

DEV4

REV0

DEV3

0000 1000

Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition.

Shaded cells are unimplemented, read as ‘0’.

Note 1: See Register 24-11 for DEVID1 values.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 261

PIC18FXX8

REGISTER 24-1: CONFIGURATIONREGISTER1HIGH(CONFIG1H:BYTEADDRESS300001h)

U-0

—

U-0

—

R/P-1

U-0

—

U-0

—

R/P-1

OSCSEN

FOSC2 FOSC1 FOSC0

bit 0

bit 7

bit 7-6

bit 5

Unimplemented: Read as ‘0’

OSCSEN: Oscillator System Clock Switch Enable bit

1= Oscillator system clock switch option is disabled (main oscillator is source)

0= Oscillator system clock switch option is enabled (oscillator switching is enabled)

bit 4-3

bit 2-0

Unimplemented: Read as ‘0’

FOSC2:FOSC0: Oscillator Selection bits

111= RC oscillator w/ OSC2 configured as RA6

110= HS oscillator with PLL enabled/clock frequency = (4 x FOSC)

101= EC oscillator w/ OSC2 configured as RA6

100= EC oscillator w/ OSC2 configured as divide-by-4 clock output

011= RC oscillator

010= HS oscillator

001= XT oscillator

000= LP oscillator

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

REGISTER 24-2: CONFIGURATION REGISTER 2 LOW (CONFIG2L:BYTE ADDRESS300002h)

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

BORV1

BORV0 BOREN PWRTEN

bit 0

bit 7

bit 7-4

bit 3-2

Unimplemented: Read as ‘0’

BORV1:BORV0: Brown-out Reset Voltage bits

11= VBOR set to 2.0V

10= VBOR set to 2.7V

01= VBOR set to 4.2V

00= VBOR set to 4.5V

bit 1

bit 0

BOREN: Brown-out Reset Enable bit⁽¹⁾

1= Brown-out Reset enabled

0= Brown-out Reset disabled

PWRTEN: Power-up Timer Enable bit⁽¹⁾

1= PWRT disabled

0= PWRT enabled

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS41159B-page 262

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 24-3: CONFIGURATION REGISTER 2 HIGH (CONFIG2H:BYTE ADDRESS 300003h)

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

WDTPS2 WDTPS1 WDTPS0 WDTEN

bit 0

bit 7

bit 7-4

bit 3-1

Unimplemented: Read as ‘0’

WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits

111= 1:128

110= 1:64

101= 1:32

100= 1:16

011= 1:8

010= 1:4

001= 1:2

000= 1:1

Note: The Watchdog Timer postscale select bits configuration used in the PIC18FXXX

devices has changed from the configuration used in the PIC18CXXX devices.

bit 0

WDTEN: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled (control is placed on the SWDTEN bit)

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

REGISTER 24-4: CONFIGURATION REGISTER 4 LOW (CONFIG4L: BYTE ADDRESS 300006h)

R/P-1

DEBUG

bit 7

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

LVP

U-0

—

R/P-1

STVREN

bit 0

bit 7

DEBUG: Background Debugger Enable bit

1= Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins.

0= Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.

bit 6-3

bit 2

Unimplemented: Read as ‘0’

LVP: Low Voltage ICSP Enable bit

1= Low Voltage ICSP enabled

0= Low Voltage ICSP disabled

bit 1

bit 0

Unimplemented: Read as ‘0’

STVREN: Stack Full/Underflow Reset Enable bit

1= Stack Full/Underflow will cause RESET

0= Stack Full/Underflow will not cause RESET

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 263

PIC18FXX8

REGISTER 24-5: CONFIGURATION REGISTER 5 LOW (CONFIG5L:BYTE ADDRESS300008h)

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1

CP3⁽¹⁾

R/C-1

CP2⁽¹⁾

R/C-1

CP1

R/C-1

CP0

bit 7

bit 0

bit 7-4

bit 3

Unimplemented: Read as ‘0’

CP3: Code Protection bit⁽¹⁾

1= Block 3 (006000-007FFFh) not code protected

0= Block 3 (006000-007FFFh) code protected

bit 2

bit 1

bit 0

CP2: Code Protection bit⁽¹⁾

1= Block 2 (004000-005FFFh) not code protected

0= Block 2 (004000-005FFFh) code protected

CP1: Code Protection bit

1= Block 1 (002000-003FFFh) not code protected

0= Block 1 (002000-003FFFh) code protected

CP0: Code Protection bit

1= Block 0 (000200-001FFFh) not code protected

0= Block 0 (000200-001FFFh) code protected

Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set.

Legend:

R = Readable bit

- n = Value when device is unprogrammed

C = Clearable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

REGISTER 24-6: CONFIGURATION REGISTER 5HIGH (CONFIG5H:BYTEADDRESS300009h)

R/C-1

CPD

R/C-1

CPB

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

bit 7

CPD: Data EEPROM Code Protection bit

1= Data EEPROM not code protected

0= Data EEPROM code protected

bit 6

CPB: Boot Block Code Protection bit

1= Boot Block (000000-0001FFh) not code protected

0= Boot Block (000000-0001FFh) code protected

bit 5-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS41159B-page 264

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 24-7: CONFIGURATIONREGISTER6LOW(CONFIG6L:BYTEADDRESS30000Ah)

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

WRT3⁽¹⁾WRT2⁽¹⁾

R/P-1

WRT1

WRT0

bit 7

bit 0

bit 7-4

bit 3

Unimplemented: Read as ‘0’

WRT3: Write Protection bit⁽¹⁾

1= Block 3 (006000-007FFFh) not write protected

0= Block 3 (006000-007FFFh) write protected

bit 2

bit 1

bit 0

WRT2: Write Protection bit⁽¹⁾

1= Block 2 (004000-005FFFh) not write protected

0= Block 2 (004000-005FFFh) write protected

WRT1: Write Protection bit

1= Block 1 (002000-003FFFh) not write protected

0= Block 1 (002000-003FFFh) write protected

WRT0: Write Protection bit

1= Block 0 (000200-001FFFh) not write protected

0= Block 0 (000200-001FFFh) write protected

Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set.

Legend:

R = Readable bit

- n = Value when device is unprogrammed

P = Programmable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

REGISTER 24-8: CONFIGURATIONREGISTER6HIGH(CONFIG6H:BYTEADDRESS30000Bh)

R/P-1

R-1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

WRTD

WRTB

WRTC

bit 7

bit 0

bit 7

bit 6

bit 5

WRTD: Data EEPROM Write Protection bit

1= Data EEPROM not write protected

0= Data EEPROM write protected

WRTB: Boot Block Write Protection bit

1= Boot Block (000000-0001FFh) not write protected

0= Boot Block (000000-0001FFh) write protected

WRTC: Configuration Register Write Protection bit

1= Configuration registers (300000-3000FFh) not write protected

0= Configuration registers (300000-3000FFh) write protected

Note: This bit is read only, and cannot be changed in User mode.

bit 4-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

P =Programmable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 265

PIC18FXX8

REGISTER 24-9: CONFIGURATIONREGISTER7LOW(CONFIG7L:BYTEADDRESS30000Ch)

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

EBTR3⁽¹⁾EBTR2⁽¹⁾

R/P-1

EBTR1

EBTR0

bit 7

bit 0

bit 7-4

bit 3

Unimplemented: Read as ‘0’

EBTR3: Table Read Protection bit⁽¹⁾

1= Block 3 (006000-007FFFh) not protected from Table Reads executed in other blocks

0= Block 3 (006000-007FFFh) protected from Table Reads executed in other blocks

bit 2

bit 1

bit 0

EBTR2: Table Read Protection bit⁽¹⁾

1= Block 2 (004000-005FFFh) not protected from Table Reads executed in other blocks

0= Block 2 (004000-005FFFh) protected from Table Reads executed in other blocks

EBTR1: Table Read Protection bit

1= Block 1 (002000-003FFFh) not protected from Table Reads executed in other blocks

0= Block 1 (002000-003FFFh) protected from Table Reads executed in other blocks

EBTR0: Table Read Protection bit

1= Block 0 (000200-001FFFh) not protected from Table Reads executed in other blocks

0= Block 0 (000200-001FFFh) protected from Table Reads executed in other blocks

Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set.

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

REGISTER 24-10: CONFIGURATION REGISTER 7 HIGH (CONFIG7H: BYTE ADDRESS 30000Dh)

U-0

—

R/P-1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

EBTRB

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ‘0’

EBTRB: Boot Block Table Read Protection bit

1= Boot Block (000000-0001FFh) not protected from Table Reads executed in other blocks

0= Boot Block (000000-0001FFh) protected from Table Reads executed in other blocks

bit 5-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

P =Programmable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS41159B-page 266

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

REGISTER 24-11: DEVICE ID REGISTER 1 FOR PIC18FXX8 DEVICE

(DEVID1: BYTE ADDRESS 3FFFFEh)

R

DEV2

DEV1

DEV0

REV4

REV3

REV2

REV1

REV0

bit 7

bit 0

bit 7-5

bit 4-0

DEV2:DEV0: Device ID bits

These bits are used with the DEV<10:3> bits in the Device ID Register 2 to identify the

part number

REV4:REV0: Revision ID bits

These bits are used to indicate the device revision

Legend:

R = Readable bit

P =Programmable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

REGISTER 24-12: DEVICE ID REGISTER 2 FOR PIC18FXX8 DEVICE

(DEVID2: BYTE ADDRESS 3FFFFFh)

R

DEV10

DEV9

DEV8

DEV7

DEV6

DEV5

DEV4

DEV3

bit 7

bit 0

bit 7-0

DEV10:DEV3: Device ID bits

These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the

part number

Legend:

R = Readable bit

P =Programmable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 267

PIC18FXX8

The WDT time-out period values may be found in the

Electrical Specifications section under parameter #31.

Values for the WDT postscaler may be assigned using

the configuration bits.

24.2 Watchdog Timer (WDT)

The Watchdog Timer is a free running, on-chip RC

oscillator, which does not require any external compo-

nents. This RC oscillator is separate from the RC oscil-

lator of the OSC1/CLKI pin. That means that the WDT

will run, even if the clock on the OSC1/CLKI and OSC2/

CLKO/RA6 pins of the device has been stopped, for

example, by execution of a SLEEPinstruction.

Note: The CLRWDTand SLEEPinstructions clear

the WDT and the postscaler, if assigned to

the WDT and prevent it from timing out and

generating a device RESET condition.

During normal operation, a WDT time-out generates a

device RESET (Watchdog Timer Reset). If the device is

in SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation (Watch-

dog Timer Wake-up). The TO bit in the RCON register

will be cleared upon a WDT time-out.

Note: When a CLRWDT instruction is executed

and the postscaler is assigned to the WDT,

the postscaler count will be cleared, but the

postscaler assignment is not changed.

The Watchdog Timer is enabled/disabled by a device

configuration bit. If the WDT is enabled, software exe-

cution may not disable this function. When the WDTEN

configuration bit is cleared, the SWDTEN bit enables/

disables the operation of the WDT.

24.2.1

CONTROL REGISTER

Register 24-13 shows the WDTCON register. This is a

readable and writable register, which contains a control

bit that allows software to override the WDT enable

configuration bit, only when the configuration bit has

disabled the WDT.

REGISTER 24-13: WDTCON REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SWDTEN

bit 0

bit 7

bit 7-1

bit 0

Unimplemented: Read as ’0’

SWDTEN: Software Controlled Watchdog Timer Enable bit

1= Watchdog Timer is on

0= Watchdog Timer is turned off if the WDTEN configuration bit in the configuration

register = ‘0’

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR reset

DS41159B-page 268

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

24.2.2

WDT POSTSCALER

The WDT has a postscaler that can extend the WDT

Reset period. The postscaler is selected at the time of

the device programming, by the value written to the

CONFIG2H configuration register.

FIGURE 24-1:

WATCHDOG TIMER BLOCK DIAGRAM

WDT Timer

Postscaler

8

8 - to - 1 MUX

WDTPS2:WDTPS0

WDTEN

Configuration bit

SWDTEN bit

WDT

Time-out

Note:

WDPS2:WDPS0 are bits in register CONFIG2H.

TABLE 24-2: SUMMARY OF WATCHDOG TIMER REGISTERS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CONFIG2H

RCON

—

IPEN

—

RI

—

WDTPS2 WDTPS2 WDTPS0

WDTEN

BOR

TO

—

PD

—

POR

—

WDTCON

SWDTEN

Legend: Shaded cells are not used by the Watchdog Timer.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 269

PIC18FXX8

External MCLR Reset will cause a device RESET. All

other events are considered a continuation of program

execution and will cause a “wake-up”. The TO and PD

bits in the RCON register can be used to determine the

cause of the device RESET. The PD bit, which is set on

power-up, is cleared when SLEEP is invoked. The TO

bit is cleared, if a WDT time-out occurred (and caused

wake-up).

24.3 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared, but

keeps running, the PD bit (RCON<3>) is cleared, the

TO (RCON<4>) bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, low or hi-impedance).

When the SLEEPinstruction is being executed, the next

instruction (PC + 2) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOPafter the SLEEPinstruction.

For lowest current consumption in this mode, place all

I/O pins at either VDD or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down

the A/D and disable external clocks. Pull all I/O pins

that are hi-impedance inputs, high or low externally, to

avoid switching currents caused by floating inputs. The

T0CKI input should also be at VDD or VSS for lowest

current consumption. The contribution from on-chip

pull-ups on PORTB should be considered.

The MCLR pin must be at a logic high level (VIHMC).

24.3.2

WAKE-UP USING INTERRUPTS

24.3.1

WAKE-UP FROM SLEEP

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

The device can wake-up from SLEEP through one of

the following events:

1. External RESET input on MCLR pin.

• If an interrupt condition (interrupt flag bit and inter-

rupt enable bits are set) occurs before the execu-

tion of a SLEEPinstruction, the SLEEPinstruction

will complete as a NOP. Therefore, the WDT and

WDT postscaler will not be cleared, the TO bit will

not be set and PD bits will not be cleared.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. Interrupt from INT pin, RB port change or a

peripheral interrupt.

The following peripheral interrupts can wake the device

from SLEEP:

• If the interrupt condition occurs during or after

the execution of a SLEEPinstruction, the device

will immediately wake-up from SLEEP. The

SLEEPinstruction will be completely executed

before the wake-up. Therefore, the WDT and

WDT postscaler will be cleared, the TO bit will be

set and the PD bit will be cleared.

1. PSP read or write.

2. TMR1 interrupt. Timer1 must be operating as an

asynchronous counter.

3. TMR3 interrupt. Timer3 must be operating as an

asynchronous counter.

4. CCP Capture mode interrupt.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

5. Special event trigger (Timer1 in Asynchronous

mode using an external clock).

6. MSSP (START/STOP) bit detect interrupt.

7. MSSP transmit or receive in Slave mode

(SPI/I²C).

8. USART RX or TX (Synchronous Slave mode).

9. A/D conversion (when A/D clock source is RC).

10. EEPROM write operation complete.

11. LVD interrupt.

To ensure that the WDT is cleared, a CLRWDT

instruction should be executed before a SLEEP

instruction.

Other peripherals cannot generate interrupts, since

during SLEEP, no on-chip clocks are present.

DS41159B-page 270

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 24-2:

WAKE-UP FROM SLEEP THROUGH INTERRUPT^(1,2)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKO⁽⁴⁾

INT pin

(2)

TOST

INTF flag

(INTCON<1>)

Interrupt Latency⁽³⁾

GIEH bit

Processor in

SLEEP

(INTCON<7>)

INSTRUCTION FLOW

PC

PC+2

PC+4

PC + 4

0008h

000Ah

Instruction

Fetched

Inst(0008h)

Inst(PC + 2)

Inst(PC + 4)

Inst(PC + 2)

Inst(000Ah)

Inst(PC) = SLEEP

Instruction

Executed

Dummy Cycle

Inst(0008h)

SLEEP

Inst(PC - 1)

Note 1: XT, HS or LP Oscillator mode assumed.

2: GIE = ’1’ assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.

3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Osc modes.

4: CLKO is not available in these Osc modes, but shown here for timing reference.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 271

PIC18FXX8

Each of the five blocks has three code protection bits

associated with them. They are:

24.4 Program Verification and

Code Protection

• Code Protect bit (CPn)

The overall structure of the code protection on the

PIC18 FLASH devices differs significantly from other

PICmicro devices.

• Write Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 24-3 shows the program memory organization

for 16- and 32-Kbyte devices and the specific code

protection bit associated with each block. The actual

locations of the bits are summarized in Table 24-3.

The user program memory is divided into five blocks.

One of these is a boot block of 512 bytes. The remain-

der of the memory is divided into four blocks on binary

boundaries.

FIGURE 24-3:

CODE PROTECTED PROGRAM MEMORY FOR PIC18F2X8/4X8

MEMORY SIZE/DEVICE

Block Code Protection

16 Kbytes

(PIC18FX48)

32 Kbytes

(PIC18FX58)

Address

Range

Controlled By:

CPB, WRTB, EBTRB

CP0, WRT0, EBTR0

000000h

0001FFh

Boot Block

Block 0

000200h

Block 0

Block 1

001FFFh

002000h

Block 1

Block 2

Block 3

CP1, WRT1, EBTR1

CP2, WRT2, EBTR2

CP3, WRT3, EBTR3

003FFFh

004000h

Unimplemented

Read 0s

005FFFh

006000h

Unimplemented

Read 0s

007FFFh

008000h

Unimplemented

Read 0s

Unimplemented

Read 0s

(Unimplemented Memory Space)

1FFFFFh

TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300008h

CONFIG5L

CONFIG5H

CONFIG6L

—

CPD

—

CPB

—

CP3

—

CP2

—

CP1

—

CP0

—

300009h

30000Ah

30000Bh

30000Ch

30000Dh

—

WRT3

—

WRT2

—

WRT1

—

WRT0

—

CONFIG6H WRTD

WRTB

—

WRTC

—

CONFIG7L

CONFIG7H

—

EBTR3

—

EBTR2

—

EBTR1

—

EBTR0

—

EBTRB

—

Legend: Shaded cells are unimplemented.

DS41159B-page 272

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

24.4.1

PROGRAM MEMORY

CODE PROTECTION

Note: Code protection bits may only be written to

a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ state. Code pro-

tection bits are only set to ‘1’ by a full chip

erase or block erase function. The full chip

erase and block erase functions can only

be initiated via ICSP or an external

programmer.

The user memory may be read to or written from any

location using the Table Read and Table Write instruc-

tions. The device ID may be read with Table Reads.

The configuration registers may be read and written

with the Table Read and Table Write instructions.

In User mode, the CPn bits have no direct effect. CPn

bits inhibit external reads and writes. A block of user

memory may be protected from Table Writes if the

WRTn configuration bit is ‘0’. The EBTRn bits control

Table Reads. For a block of user memory with the

EBTRn bit set to ‘0’, a Table Read instruction that

executes from within that block is allowed to read. A

Table Read instruction that executes from a location

outside of that block is not allowed to read, and will

result in reading ‘0’s. Figures 24-4 through 24-6

illustrate Table Write and Table Read protection.

FIGURE 24-4:

TABLE WRITE (WRTn) DISALLOWED

Register Values

Program Memory

Configuration Bit Settings

000000h

WRTB,EBTRB = 11

0001FFh

000200h

TBLPTR = 000FFF

PC = 001FFE

WRT0,EBTR0 = 01

TBLWT *

001FFFh

002000h

WRT1,EBTR1 = 11

003FFFh

004000h

PC = 004FFE

WRT2,EBTR2 = 11

005FFFh

006000h

WRT3,EBTR3 = 11

007FFFh

Results: All Table Writes disabled to Blockn whenever WRTn = ‘0’.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 273

PIC18FXX8

FIGURE 24-5:

EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED

Register Values

Program Memory

Configuration Bit Settings

000000h

WRTB,EBTRB = 11

0001FFh

000200h

TBLPTR = 000FFF

PC = 002FFE

WRT0,EBTR0 = 10

001FFFh

002000h

TBLRD *

WRT1,EBTR1 = 11

WRT2,EBTR2 = 11

003FFFh

004000h

005FFFh

006000h

WRT3,EBTR3 = 11

007FFFh

Results: All Table Reads from external blocks to Blockn are disabled whenever EBTRn = ‘0’.

TABLAT register returns a value of “0”.

FIGURE 24-6:

EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED

Register Values

Program Memory

Configuration Bit Settings

000000h

WRTB,EBTRB = 11

0001FFh

000200h

TBLPTR = 000FFF

PC = 001FFE

WRT0,EBTR0 = 10

TBLRD *

001FFFh

002000h

WRT1,EBTR1 = 11

WRT2,EBTR2 = 11

WRT3,EBTR3 = 11

003FFFh

004000h

005FFFh

006000h

007FFFh

Results: Table Reads permitted within Blockn, even when EBTRBn = ‘0’.

TABLAT register returns the value of the data at the location TBLPTR.

DS41159B-page 274

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

To use the In-Circuit Debugger function of the micro-

controller, the design must implement In-Circuit Serial

Programming connections to MCLR/VPP, VDD, GND,

RB7 and RB6. This will interface to the In-Circuit

Debugger module available from Microchip, or one of

the third party development tool companies. The

Microchip In-Circuit Debugger (ICD) used with the

PIC18FXXX microcontrollers is the MPLAB^®ICD 2.

24.4.2

DATA EEPROM

CODE PROTECTION

The entire data EEPROM is protected from external

reads and writes by two bits: CPD and WRTD. CPD

inhibits external reads and writes of data EEPROM.

WRTD inhibits external writes to data EEPROM. The

CPU can continue to read and write data EEPROM,

regardless of the protection bit settings.

24.8 Low Voltage ICSP Programming

24.4.3

CONFIGURATION REGISTER

PROTECTION

The LVP bit configuration register CONFIG4L enables

low voltage ICSP programming. This mode allows the

microcontroller to be programmed via ICSP using a

VDD source in the operating voltage range. This only

means that VPP does not have to be brought to VIHH,

but can instead be left at the normal operating voltage.

In this mode, the RB5/PGM pin is dedicated to the pro-

gramming function and ceases to be a general purpose

I/O pin. During programming, VDD is applied to the

MCLR/VPP pin. To enter Programming mode, VDD must

be applied to the RB5/PGM, provided the LVP bit is set.

The LVP bit defaults to a (‘1’) from the factory.

The configuration registers can be write protected. The

WRTC bit controls protection of the configuration regis-

ters. In User mode, the WRTC bit is readable only.

WRTC can only be written via ICSP or an external

programmer.

24.5 ID Locations

Eight memory locations (200000h - 200007h) are des-

ignated as ID locations, where the user can store

checksum or other code identification numbers. These

locations are accessible during normal execution

through the TBLRD and TBLWT instructions, or during

program/verify. The ID locations can be read when the

device is code protected.

Note 1: The High Voltage Programming mode is

always available, regardless of the state

of the LVP bit, by applying VIHH to the

MCLR pin.

2: While in Low Voltage ICSP mode, the

RB5 pin can no longer be used as a

general purpose I/O pin.

24.6

In-Circuit Serial Programming

PIC18FXXX microcontrollers can be serially pro-

grammed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

3: When using Low Voltage ICSP program-

ming (LVP) and the pull-ups on PORTB

are enabled, bit 5 in the TRISB register

must be cleared to disable the pull-up on

RB5 and ensure the proper operation of

the device.

If Low Voltage Programming mode is not used, the LVP

bit can be programmed to a '0' and RB5/PGM becomes

a digital I/O pin. However, the LVP bit may only be pro-

grammed when programming is entered with VIHH on

MCLR/VPP. The LVP bit can only be charged when

using high voltage on MCLR.

24.7 In-Circuit Debugger

When the DEBUG bit in configuration register

CONFIG4L is programmed to a ’0’, the In-Circuit

Debugger functionality is enabled. This function allows

simple debugging functions when used with MPLAB^®

IDE. When the microcontroller has this feature

enabled, some of the resources are not available for

general use. Resources used include 2 I/O pins, stack

locations, program memory and data memory. For

more information on the resources required, see the

User’s Guide for the In-Circuit Debugger you are using.

It should be noted that once the LVP bit is programmed

to 0, only the High Voltage Programming mode is avail-

able and only High Voltage Programming mode can be

used to program the device.

When using Low Voltage ICSP, the part must be sup-

plied 4.5V to 5.5V, if a bulk erase will be executed. This

includes reprogramming of the code protect bits from

an on-state to off-state. For all other cases of Low Volt-

age ICSP, the part may be programmed at the normal

operating voltage. This means unique user IDs, or user

code can be reprogrammed or added.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 275

PIC18FXX8

NOTES:

DS41159B-page 276

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

The control instructions may use some of the following

operands:

25.0 INSTRUCTION SET SUMMARY

The PIC18 instruction set adds many enhancements to

the previous PICmicro instruction sets, while maintaining

an easy migration from these PICmicro instruction sets.

• A program memory address (specified by ‘n’)

• The mode of the Call or Return instructions

(specified by ‘s’)

Most instructions are a single program memory word

(16 bits), but there are three instructions that require

two program memory locations.

• The mode of the Table Read and Table Write

instructions (specified by ‘m’)

• No operand required

(specified by ‘—’)

Each single word instruction is a 16-bit word divided

into an OPCODE, which specifies the instruction type

and one or more operands, which further specify the

operation of the instruction.

All instructions are a single word, except for three

double-word instructions. These three instructions

were made double-word instructions so that all the

required information is available in these 32 bits. In the

second word, the 4 MSbs are 1’s. If this second word is

executed as an instruction (by itself), it will execute as

a NOP.

The instruction set is highly orthogonal and is grouped

into four basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal operations

All single word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles, with the additional instruction cycle(s) executed

as a NOP.

• Control operations

The PIC18 instruction set summary in Table 25-2 lists

byte-oriented, bit-oriented, literal and control

operations. Table 25-1 shows the opcode field

descriptions.

The double-word instructions execute in two instruction

cycles.

Most byte-oriented instructions have three operands:

1. The file register (specified by ‘f’)

One instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1 µs. If a conditional test is

true, or the program counter is changed as a result of

an instruction, the instruction execution time is 2 µs.

Two-word branch instructions (if true) would take 3 µs.

2. The destination of the result

(specified by ‘d’)

3. The accessed memory

(specified by ‘a’)

The file register designator 'f' specifies which file

register is to be used by the instruction.

Figure 25-1 shows the general formats that the

instructions can have.

The destination designator ‘d’ specifies where the

result of the operation is to be placed. If 'd' is zero, the

result is placed in the WREG register. If 'd' is one, the

result is placed in the file register specified in the

instruction.

All examples use the format ‘nnh’ to represent a

hexadecimal number, where ‘h’ signifies

a

hexadecimal digit.

The Instruction Set Summary, shown in Table 25-2,

lists the instructions recognized by the Microchip

Assembler (MPASM^TM).

All bit-oriented instructions have three operands:

1. The file register (specified by ‘f’)

Section 25.2 provides a description of each instruction.

2. The bit in the file register

(specified by ‘b’)

25.1 READ-MODIFY-WRITE

OPERATIONS

3. The accessed memory

(specified by ‘a’)

The bit field designator 'b' selects the number of the bit

affected by the operation, while the file register desig-

nator 'f' represents the number of the file in which the

bit is located.

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

The literal instructions may use some of the following

operands:

• A literal value to be loaded into a file register

(specified by ‘k’)

For example, a “clrf PORTB” instruction will read

PORTB, clear all the data bits, then write the result

back to PORTB. This example would have the unin-

tended result that the condition that sets the RBIF flag

would be cleared.

• The desired FSR register to load the literal value

into (specified by ‘f’)

• No operand required

(specified by ‘—’)

 2002 Microchip Technology Inc.

DS41159B-page 277

PIC18FXX8

TABLE 25-1: OPCODE FIELD DESCRIPTIONS

Field

Description

a

RAM access bit

a = 0: RAM location in Access RAM (BSR register is ignored)

a = 1: RAM bank is specified by BSR register

bbb

BSR

d

Bit address within an 8-bit file register (0 to 7)

Bank Select Register. Used to select the current RAM bank.

Destination select bit;

d = 0: store result in WREG,

d = 1: store result in file register f.

dest

f

Destination either the WREG register or the specified register file location

8-bit Register file address (0x00 to 0xFF)

fs

12-bit Register file address (0x000 to 0xFFF). This is the source address.

12-bit Register file address (0x000 to 0xFFF). This is the destination address.

Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)

Label name

fd

k

label

mm

The mode of the TBLPTR register for the Table Read and Table Write instructions.

Only used with Table Read and Table Write instructions:

*

No change to register (such as TBLPTR with Table Reads and Writes)

Post-Increment register (such as TBLPTR with Table Reads and Writes)

Post-Decrement register (such as TBLPTR with Table Reads and Writes)

Pre-Increment register (such as TBLPTR with Table Reads and Writes)

*+

*-

+*

n

The relative address (2’s complement number) for relative branch instructions, or the direct address for

Call/Branch and Return instructions

PRODH

PRODL

s

Product of Multiply high byte

Product of Multiply low byte

Fast Call/Return mode select bit;

s = 0: do not update into/from shadow registers

s = 1: certain registers loaded into/from shadow registers (Fast mode)

u

Unused or Unchanged

WREG

x

Working register (accumulator)

Don't care (0 or 1).

The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all

Microchip software tools.

TBLPTR

21-bit Table Pointer (points to a Program Memory location)

8-bit Table Latch

TABLAT

TOS

Top-of-Stack

PC

Program Counter

PCL

Program Counter Low Byte

Program Counter High Byte

Program Counter High Byte Latch

Program Counter Upper Byte Latch

Global Interrupt Enable bit

Watchdog Timer

PCH

PCLATH

PCLATU

GIE

WDT

TO

Time-out bit

PD

Power-down bit

C, DC, Z, OV, N

ALU status bits Carry, Digit Carry, Zero, Overflow, Negative

Optional

[

]

)

(

Contents

→

< >

∈

Assigned to

Register bit field

In the set of

italics

User defined term (font is courier)

DS41159B-page 278

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 25-1:

GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

Example Instruction

15

10

OPCODE

9

8

7

0

ADDWF MYREG, W, B

d

a

f (FILE #)

d = 0 for result destination to be WREG register

d = 1 for result destination to be file register (f)

a = 0 to force Access Bank

a = 1 for BSR to select bank

f = 8-bit file register address

Byte to Byte move operations (2-word)

15

12 11

0

OPCODE

f (Source FILE #)

MOVFF MYREG1, MYREG2

15

12 11

1111

f (Destination FILE #)

f = 12-bit file register address

Bit-oriented file register operations

15 12 11 9 8

OPCODE b (BIT #)

7

0

BSF MYREG, bit, B

a

f (FILE #)

b = 3-bit position of bit in file register (f)

a = 0 to force Access Bank

a = 1 for BSR to select bank

f = 8-bit file register address

Literal operations

15

8

7

0

MOVLW 0x7F

OPCODE

k (literal)

k = 8-bit immediate value

Control operations

CALL, GOTO and Branch operations

15

8 7

0

GOTO Label

OPCODE

12 11

n<7:0> (literal)

15

0

1111

n<19:8> (literal)

n = 20-bit immediate value

15

8

7

0

CALL MYFUNC

OPCODE

12 11

n<7:0> (literal)

S

0

n<19:8> (literal)

S = Fast bit

11 10

15

0

BRA MYFUNC

BC MYFUNC

OPCODE

n<10:0> (literal)

15

OPCODE

8 7

n<7:0> (literal)

 2002 Microchip Technology Inc.

DS41159B-page 279

PIC18FXX8

TABLE 25-2: PIC18FXXX INSTRUCTION SET

16-Bit Instruction Word

MSb LSb

Mnemonic,

Status

Affected

Description

Cycles

Notes

Operands

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d, a Add WREG and f

1

0010 01da ffff ffff C, DC, Z, OV, N 1, 2

0010 00da ffff ffff C, DC, Z, OV, N 1, 2

0001 01da ffff ffff Z, N

0110 101a ffff ffff Z

0001 11da ffff ffff Z, N

ADDWFC f, d, a Add WREG and Carry bit to f

ANDWF

CLRF

COMF

f, d, a AND WREG with f

f, a Clear f

f, d, a Complement f

1,2

2

1, 2

4

CPFSEQ f, a

CPFSGT f, a

CPFSLT f, a

Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None

Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None

Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None

4

1, 2

DECF

f, d, a Decrement f

1

0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4

DECFSZ f, d, a Decrement f, Skip if 0

DCFSNZ f, d, a Decrement f, Skip if Not 0

1 (2 or 3) 0010 11da ffff ffff None

1 (2 or 3) 0100 11da ffff ffff None

1, 2, 3, 4

1, 2

INCF

f, d, a Increment f

1

0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4

INCFSZ

INFSNZ

IORWF

MOVF

f, d, a Increment f, Skip if 0

f, d, a Increment f, Skip if Not 0

f, d, a Inclusive OR WREG with f

f, d, a Move f

f_s, f_dMove f_s(source) to 1st word

f_d(destination) 2nd word

1 (2 or 3) 0011 11da ffff ffff None

1 (2 or 3) 0100 10da ffff ffff None

4

1, 2

1

2

0001 00da ffff ffff Z, N

0101 00da ffff ffff Z, N

1100 ffff ffff ffff None

1111 ffff ffff ffff

MOVFF

MOVWF f, a

Move WREG to f

Multiply WREG with f

Negate f

1

0110 111a ffff ffff None

0000 001a ffff ffff None

0110 110a ffff ffff C, DC, Z, OV, N 1, 2

0011 01da ffff ffff C, Z, N

0100 01da ffff ffff Z, N

0011 00da ffff ffff C, Z, N

0100 00da ffff ffff Z, N

0110 100a ffff ffff None

MULWF

NEGF

RLCF

RLNCF

RRCF

RRNCF

SETF

f, a

f, d, a Rotate Left f through Carry

f, d, a Rotate Left f (No Carry)

f, d, a Rotate Right f through Carry

f, d, a Rotate Right f (No Carry)

1, 2

f, a

Set f

SUBFWB f, d, a Subtract f from WREG with

borrow

0101 01da ffff ffff C, DC, Z, OV, N 1, 2

SUBWF

f, d, a Subtract WREG from f

1

0101 11da ffff ffff C, DC, Z, OV, N

0101 10da ffff ffff C, DC, Z, OV, N 1, 2

SUBWFB f, d, a Subtract WREG from f with

borrow

SWAPF

TSTFSZ f, a

XORWF f, d, a Exclusive OR WREG with f

BIT-ORIENTED FILE REGISTER OPERATIONS

f, d, a Swap nibbles in f

1

0011 10da ffff ffff None

4

1, 2

Test f, skip if 0

1 (2 or 3) 0110 011a ffff ffff None

1

0001 10da ffff ffff Z, N

BCF

BSF

BTFSC

BTFSS

BTG

f, b, a Bit Clear f

f, b, a Bit Set f

f, b, a Bit Test f, Skip if Clear

f, b, a Bit Test f, Skip if Set

f, d, a Bit Toggle f

1

1001 bbba ffff ffff None

1000 bbba ffff ffff None

1, 2

3, 4

1, 2

1 (2 or 3) 1011 bbba ffff ffff None

1 (2 or 3) 1010 bbba ffff ffff None

1

0111 bbba ffff ffff None

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be

that value present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and

is driven low by an external device, the data will be written back with a ’0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The

second cycle is executed as a NOP.

4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP,

unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that

all program memory locations have a valid instruction.

5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.

DS41159B-page 280

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED)

Mnemonic,

16-Bit Instruction Word

LSb

Status

Affected

Description

Cycles

Notes

Operands

MSb

CONTROL OPERATIONS

BC

BN

n

Branch if Carry

1 (2)

2

1 (2)

2

1110 0010 nnnn nnnn None

1110 0110 nnnn nnnn None

1110 0011 nnnn nnnn None

1110 0111 nnnn nnnn None

1110 0101 nnnn nnnn None

1110 0001 nnnn nnnn None

1110 0100 nnnn nnnn None

1101 0nnn nnnn nnnn None

1110 0000 nnnn nnnn None

1110 110s kkkk kkkk None

1111 kkkk kkkk kkkk

Branch if Negative

Branch if Not Carry

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

Branch if Overflow

Branch Unconditionally

Branch if Zero

BNC

BNN

BNOV

BNZ

BOV

BRA

BZ

n

n, s

CALL

Call subroutine 1st word

2nd word

CLRWDT

DAW

GOTO

—

n

Clear Watchdog Timer

Decimal Adjust WREG

Go to address 1st word

2nd word

1

2

0000 0000 0000 0100 TO, PD

0000 0000 0000 0111 C

1110 1111 kkkk kkkk None

1111 kkkk kkkk kkkk

NOP

POP

PUSH

RCALL

RESET

RETFIE

—

n

No Operation

No Operation (Note 4)

Pop top of return stack (TOS)

Push top of return stack (TOS) 1

Relative Call

1

0000 0000 0000 0000 None

1111 xxxx xxxx xxxx None

0000 0000 0000 0110 None

0000 0000 0000 0101 None

1101 1nnn nnnn nnnn None

0000 0000 1111 1111 All

0000 0000 0001 000s GIE/GIEH,

PEIE/GIEL

2

1

2

Software device RESET

Return from interrupt enable

s

RETLW

RETURN

SLEEP

k

s

—

Return with literal in WREG

Return from Subroutine

Go into Standby mode

2

1

0000 1100 kkkk kkkk None

0000 0000 0001 001s None

0000 0000 0000 0011 TO, PD

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be

that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and

is driven low by an external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The

second cycle is executed as a NOP.

4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP,

unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that

all program memory locations have a valid instruction.

5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.

 2002 Microchip Technology Inc.

DS41159B-page 281

PIC18FXX8

TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED)

16-Bit Instruction Word

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

LFSR

k

f, k

Add literal and WREG

AND literal with WREG

Inclusive OR literal with WREG 1

Move literal (12-bit) 2nd word

to FSRx 1st word

Move literal to BSR<3:0>

Move literal to WREG

Multiply literal with WREG

Return with literal in WREG

Subtract WREG from literal

1

0000 1111 kkkk

0000 1011 kkkk

0000 1001 kkkk

1110 1110 00ff

1111 0000 kkkk

0000 0001 0000

0000 1110 kkkk

0000 1101 kkkk

0000 1100 kkkk

0000 1000 kkkk

0000 1010 kkkk

kkkk C, DC, Z, OV, N

kkkk Z, N

kkkk None

kkkk

kkkk None

kkkk C, DC, Z, OV, N

kkkk Z, N

2

MOVLB

MOVLW

MULLW

RETLW

SUBLW

XORLW

k

1

2

1

Exclusive OR literal with WREG 1

DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS

TBLRD*

Table Read

2

0000 0000 0000

1000 None

1001 None

1010 None

1011 None

1100 None

1101 None

1110 None

1111 None

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

Table Read with post-increment

Table Read with post-decrement

Table Read with pre-increment

Table Write

Table Write with post-increment

Table Write with post-decrement

Table Write with pre-increment

2 (5)

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be

that value present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and

is driven low by an external device, the data will be written back with a ’0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The

second cycle is executed as a NOP.

4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP,

unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that

all program memory locations have a valid instruction.

5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.

DS41159B-page 282

 2002 Microchip Technology Inc.

PIC18FXX8

25.2 Instruction Set

ADDLW

ADD literal to W

ADDWF

ADD W to f

Syntax:

[ label ] ADDLW

0 ≤ k ≤ 255

k

Syntax:

[ label ] ADDWF

f [,d [,a]]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(W) + k → W

N, OV, C, DC, Z

Operation:

(W) + (f) → dest

0000

1111

kkkk

Status Affected:

Encoding:

N, OV, C, DC, Z

Description:

The contents of W are added to the

8-bit literal ’k’ and the result is

placed in W.

0010

01da

ffff

Description:

Add W to register ’f’. If ’d’ is 0, the

result is stored in W. If ’d’ is 1, the

result is stored back in register ’f’

(default). If ‘a’ is 0, the Access

Bank will be selected. If ‘a’ is 1, the

BSR is used.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Words:

Cycles:

1

Decode

Read

literal ’k’

Process

Data

Write to W

Q Cycle Activity:

Q1

ADDLW

0x15

Example:

Q2

Q3

Q4

Before Instruction

Decode

Read

register ’f’

Process

Data

Write to

destination

W

=

0x10

After Instruction

W

=

0x25

ADDWF

REG, W

Example:

Before Instruction

W

REG

=

0x17

0xC2

After Instruction

W

REG

=

0xD9

0xC2

 2002 Microchip Technology Inc.

DS41159B-page 283

PIC18FXX8

ADDWFC

ADD W and Carry bit to f

ANDLW

AND literal with W

Syntax:

[ label ] ADDWFC

f [,d [,a]]

Syntax:

[ label ] ANDLW

0 ≤ k ≤ 255

k

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

Operation:

Status Affected:

Encoding:

(W) .AND. k → W

N, Z

Operation:

(W) + (f) + (C) → dest

0000

1011

kkkk

Status Affected:

Encoding:

N, OV, C, DC, Z

Description:

The contents of W are ANDed with

the 8-bit literal 'k'. The result is

placed in W.

0010

00da

ffff

Description:

Add W, the Carry Flag and data

memory location ’f’. If ’d’ is 0, the

result is placed in W. If ’d’ is 1, the

result is placed in data memory loca-

tion 'f'. If ‘a’ is 0, the Access Bank

will be selected. If ‘a’ is 1, the BSR

will not be overridden.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal

’k’

Process

Data

Write to W

Words:

Cycles:

1

ANDLW

0x5F

Example:

Q Cycle Activity:

Q1

Before Instruction

Q2

Q3

Q4

W

=

0xA3

0x03

Decode

Read

register ’f’

Process

Data

Write to

destination

After Instruction

W

=

ADDWFC

REG, W

Example:

Before Instruction

Carry bit =

1

REG

W

=

0x02

0x4D

After Instruction

Carry bit =

0

REG

W

=

0x02

0x50

DS41159B-page 284

 2002 Microchip Technology Inc.

PIC18FXX8

ANDWF

AND W with f

BC

Branch if Carry

[ label ] BC

Syntax:

[ label ] ANDWF

f [,d [,a]]

Syntax:

n

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

Operation:

-128 ≤ n ≤ 127

if carry bit is ’1’

(PC) + 2 + 2n → PC

Operation:

(W) .AND. (f) → dest

Status Affected:

Encoding:

None

Status Affected:

Encoding:

N, Z

1110

0010

nnnn

0001

01da

ffff

Description:

If the Carry bit is ’1’, then the

program will branch.

Description:

The contents of W are AND’ed with

register 'f'. If 'd' is 0, the result is

stored in W. If 'd' is 1, the result is

stored back in register 'f' (default). If

‘a’ is 0, the Access Bank will be

selected. If ‘a’ is 1, the BSR will not

be overridden (default).

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

Q1

Q Cycle Activity:

If Jump:

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Decode

Read

register ’f’

Process

Data

Write to

destination

Decode

Read literal

’n’

Process

Data

Write to PC

No

operation

No

operation

No

operation

No

operation

ANDWF

REG, W

Example:

Before Instruction

If No Jump:

Q1

W

REG

=

0x17

0xC2

Q2

Q3

Q4

Decode

Read literal

’n’

Process

Data

No

operation

After Instruction

W

REG

=

0x02

0xC2

HERE

BC JUMP

Example:

Before Instruction

PC

=

address (HERE)

After Instruction

If Carry

=

1;

PC

address (JUMP)

If Carry

PC

0;

address (HERE+2)

 2002 Microchip Technology Inc.

DS41159B-page 285

PIC18FXX8

BCF

Bit Clear f

BN

Branch if Negative

[ label ] BN

Syntax:

[ label ] BCF f,b[,a]

Syntax:

n

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operands:

Operation:

-128 ≤ n ≤ 127

if negative bit is ’1’

(PC) + 2 + 2n → PC

Operation:

0 → f

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0110

nnnn

1001

bbba

ffff

Description:

If the Negative bit is ’1’, then the

program will branch.

Description:

Bit 'b' in register 'f' is cleared. If ‘a’

is 0, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

Q1

Q Cycle Activity:

If Jump:

Q2

Q3

Q4

Decode

Read

register ’f’

Process

Data

Write

Q1

Q2

Q3

Q4

register ’f’

Decode

Read literal

’n’

Process

Data

Write to PC

BCF

FLAG_REG,

7

Example:

No

operation

No

operation

No

operation

No

operation

Before Instruction

FLAG_REG = 0xC7

If No Jump:

Q1

After Instruction

Q2

Q3

Q4

FLAG_REG = 0x47

Decode

Read literal

’n’

Process

Data

No

operation

HERE

BN Jump

Example:

Before Instruction

PC

=

address (HERE)

After Instruction

If Negative

=

1;

PC

address (Jump)

If Negative

PC

0;

address (HERE+2)

DS41159B-page 286

 2002 Microchip Technology Inc.

PIC18FXX8

BNC

Branch if Not Carry

BNN

Branch if Not Negative

Syntax:

[ label ] BNC

-128 ≤ n ≤ 127

if carry bit is ’0’

n

Syntax:

[ label ] BNN

-128 ≤ n ≤ 127

n

Operands:

Operation:

Operands:

Operation:

if negative bit is ’0’

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0011

nnnn

1110

0111

nnnn

Description:

If the Carry bit is ’0’, then the

program will branch.

Description:

If the Negative bit is ’0’, then the

program will branch.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Decode

Read literal

’n’

Process

Data

Write to PC

Decode

Read literal

’n’

Process

Data

Write to PC

No

operation

If No Jump:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

’n’

Process

Data

No

operation

Decode

Read literal

’n’

Process

Data

No

operation

HERE

BNC Jump

HERE

BNN Jump

Example:

Before Instruction

PC

=

address (HERE)

PC

=

address (HERE)

After Instruction

If Carry

=

0;

If Negative

=

0;

PC

address (Jump)

PC

address (Jump)

If Carry

PC

1;

If Negative

PC

1;

address (HERE+2)

 2002 Microchip Technology Inc.

DS41159B-page 287

PIC18FXX8

BNOV

Branch if Not Overflow

BNZ

Branch if Not Zero

Syntax:

[ label ] BNOV

-128 ≤ n ≤ 127

n

Syntax:

[ label ] BNZ

-128 ≤ n ≤ 127

if zero bit is ’0’

n

Operands:

Operation:

Operands:

Operation:

if overflow bit is ’0’

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0101

nnnn

1110

0001

nnnn

Description:

If the Overflow bit is ’0’, then the

program will branch.

Description:

If the Zero bit is ’0’, then the pro-

gram will branch.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Decode

Read literal

’n’

Process

Data

Write to PC

Decode

Read literal

’n’

Process

Data

Write to PC

No

operation

If No Jump:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

’n’

Process

Data

No

operation

Decode

Read literal

’n’

Process

Data

No

operation

HERE

BNOV Jump

HERE

BNZ Jump

Example:

Before Instruction

PC

=

address (HERE)

PC

=

address (HERE)

After Instruction

If Overflow

=

0;

If Zero

=

0;

PC

address (Jump)

PC

address (Jump)

If Overflow

PC

1;

If Zero

PC

1;

address (HERE+2)

DS41159B-page 288

 2002 Microchip Technology Inc.

PIC18FXX8

BRA

Unconditional Branch

[ label ] BRA

BSF

Bit Set f

Syntax:

n

Syntax:

[ label ] BSF f,b[,a]

Operands:

Operation:

Status Affected:

Encoding:

-1024 ≤ n ≤ 1023

(PC) + 2 + 2n → PC

None

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation:

1 → f

1101

0nnn

nnnn

Status Affected:

Encoding:

None

Description:

Add the 2’s complement number

’2n’ to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is a

two-cycle instruction.

1000

bbba

ffff

Description:

Bit 'b' in register 'f' is set. If ‘a’ is 0,

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value.

Words:

Cycles:

1

2

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

’n’

Process

Data

Write to PC

Decode

Read

register ’f’

Process

Data

Write

register ’f’

No

operation

BSF

FLAG_REG, 7

Example:

Before Instruction

HERE

BRA Jump

Example:

FLAG_REG

=

0x0A

0x8A

Before Instruction

After Instruction

FLAG_REG

PC

=

address (HERE)

address (Jump)

After Instruction

PC

 2002 Microchip Technology Inc.

DS41159B-page 289

PIC18FXX8

BTFSC

Bit Test File, Skip if Clear

BTFSS

Bit Test File, Skip if Set

Syntax:

[ label ] BTFSC f,b[,a]

Syntax:

[ label ] BTFSS f,b[,a]

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation:

skip if (f) = 0

None

Operation:

skip if (f) = 1

None

Status Affected:

Encoding:

Status Affected:

Encoding:

1011

bbba

ffff

1010

bbba

ffff

Description:

If bit 'b' in register ’f' is 0, then the

next instruction is skipped.

Description:

If bit 'b' in register 'f' is 1, then the

next instruction is skipped.

If bit 'b' is 0, then the next instruction

fetched during the current instruction

execution is discarded, and a NOPis

executed instead, making this a

two-cycle instruction. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

If bit 'b' is 1, then the next instruction

fetched during the current instruc-

tion execution, is discarded and a

NOPis executed instead, making this

a two-cycle instruction. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

Process Data

No

Decode

Read

Process Data

No

register ’f’

operation

register ’f’

operation

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

HERE

FALSE

TRUE

BTFSC

:

FLAG, 1

HERE

FALSE

TRUE

BTFSS

:

FLAG, 1

Example:

Before Instruction

PC

Before Instruction

PC

=

address (HERE)

=

address (HERE)

After Instruction

If FLAG<1>

=

0;

If FLAG<1>

=

0;

PC

address (TRUE)

1;

PC

address (FALSE)

1;

If FLAG<1>

PC

If FLAG<1>

PC

address (FALSE)

address (TRUE)

DS41159B-page 290

 2002 Microchip Technology Inc.

PIC18FXX8

BTG

Bit Toggle f

BOV

Branch if Overflow

Syntax:

[ label ] BTG f,b[,a]

Syntax:

[ label ] BOV

-128 ≤ n ≤ 127

n

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operands:

Operation:

if overflow bit is ’1’

(PC) + 2 + 2n → PC

Operation:

(f) → f

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0100

nnnn

0111

bbba

ffff

Description:

If the Overflow bit is ’1’, then the

program will branch.

Description:

Bit ’b’ in data memory location ’f’ is

inverted. If ‘a’ is 0, the Access Bank

will be selected, overriding the BSR

value. If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

Q1

Q Cycle Activity:

If Jump:

Q2

Q3

Q4

Decode

Read

register ’f’

Process

Data

Write

Q1

Q2

Q3

Q4

register ’f’

Decode

Read literal

’n’

Process

Data

Write to PC

BTG

PORTC,

4

Example:

No

operation

No

operation

No

operation

No

operation

Before Instruction:

PORTC

=

0111 0101 [0x75]

If No Jump:

Q1

After Instruction:

Q2

Q3

Q4

PORTC

=

0110 0101 [0x65]

Decode

Read literal

’n’

Process

Data

No

operation

HERE

BOV JUMP

Example:

Before Instruction

PC

=

address (HERE)

After Instruction

If Overflow

=

1;

PC

address (JUMP)

If Overflow

PC

0;

address (HERE+2)

 2002 Microchip Technology Inc.

DS41159B-page 291

PIC18FXX8

BZ

Branch if Zero

[ label ] BZ

CALL

Subroutine Call

Syntax:

n

Syntax:

[ label ] CALL k [,s]

Operands:

Operation:

-128 ≤ n ≤ 127

Operands:

0 ≤ k ≤ 1048575

s ∈ [0,1]

if Zero bit is ’1’

(PC) + 2 + 2n → PC

Operation:

(PC) + 4 → TOS,

k → PC<20:1>,

if s = 1

Status Affected:

Encoding:

None

1110

0000

nnnn

(W) → WS,

(STATUS) → STATUSS,

(BSR) → BSRS

Description:

If the Zero bit is ’1’, then the

program will branch.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Status Affected:

None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

1110

1111

110s

k kkk

kkkk

7

0

8

k

kkk kkkk

19

Description:

Subroutine call of entire 2 Mbyte

memory range. First, return

address (PC+ 4) is pushed onto the

return stack. If ’s’ = 1, the W,

Words:

Cycles:

1

1(2)

STATUS and BSR registers are

also pushed into their respective

shadow registers, WS, STATUSS

and BSRS. If 's' = 0, no update

occurs (default). Then, the 20-bit

value ’k’ is loaded into PC<20:1>.

CALLis a two-cycle instruction.

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Decode

Read literal

’n’

Process

Data

Write to PC

No

operation

No

operation

No

operation

No

operation

Words:

Cycles:

2

If No Jump:

Q1

Q2

Q3

Q4

Decode

Read literal

’n’

Process

Data

No

operation

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal Push PC to Read literal

HERE

BZ Jump

Example:

’k’<7:0>,

stack

’k’<19:8>,

Write to PC

Before Instruction

PC

=

address (HERE)

No

operation

After Instruction

If Zero

=

1;

PC

address (Jump)

HERE

CALL THERE,FAST

Example:

If Zero

PC

0;

address (HERE+2)

Before Instruction

PC

=

address (HERE)

After Instruction

PC

=

address (THERE)

TOS

WS

address (HERE + 4)

W

BSR

STATUS

BSRS

STATUSS=

DS41159B-page 292

 2002 Microchip Technology Inc.

PIC18FXX8

CLRF

Clear f

CLRWDT

Clear Watchdog Timer

Syntax:

[label] CLRF f [,a]

Syntax:

[ label ] CLRWDT

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

Operation:

None

000h → WDT,

000h → WDT postscaler,

1 → TO,

Operation:

000h → f

1 → Z

1 → PD

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

TO, PD

0110

101a

ffff

0000

0100

Description:

Clears the contents of the specified

register. If ‘a’ is 0, the Access Bank

will be selected, overriding the BSR

value. If ‘a’ = 1, then the bank will

be selected as per the BSR value

(default).

Description:

CLRWDTinstruction resets the

Watchdog Timer. It also resets the

postscaler of the WDT. Status bits

TO and PD are set.

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

No

operation

Process

Data

No

operation

Decode

Read

register ’f’

Process

Data

Write

register ’f’

CLRWDT

Example:

CLRF

FLAG_REG

Example:

Before Instruction

WDT Counter

=

?

Before Instruction

FLAG_REG

=

0x5A

0x00

After Instruction

FLAG_REG

WDT Counter

WDT Postscaler

TO

PD

=

0x00

0

1

 2002 Microchip Technology Inc.

DS41159B-page 293

PIC18FXX8

COMF

Complement f

CPFSEQ

Compare f with W, skip if f = W

Syntax:

[ label ] COMF f [,d [,a]]

Syntax:

[ label ] CPFSEQ f [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

(f) – (W),

Operation:

(f) → dest

skip if (f) = (W)

(unsigned comparison)

Status Affected:

Encoding:

N, Z

Status Affected:

Encoding:

None

0001

11da

ffff

0110

001a

ffff

Description:

The contents of register ’f’ are com-

plemented. If ’d’ is 0, the result is

stored in W. If ’d’ is 1, the result is

stored back in register ’f’ (default). If

‘a’ is 0, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

Description:

Compares the contents of data

memory location 'f' to the contents

of W by performing an unsigned

subtraction.

If 'f' = W, then the fetched instruc-

tion is discarded and a NOPis exe-

cuted instead, making this a

two-cycle instruction. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Words:

Cycles:

1

Decode

Read

register ’f’

Process

Data

Write to

1(2)

destination

Note: 3 cycles if skip and followed

by a 2-word instruction.

COMF

REG, W

Example:

Before Instruction

Q Cycle Activity:

Q1

REG

=

0x13

Q2

Q3

Q4

After Instruction

Decode

Read

register ’f’

Process

Data

No

operation

REG

=

0x13

W

=

0xEC

If skip:

Q1

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No

operation

No

operation

HERE

CPFSEQ REG

Example:

NEQUAL

EQUAL

:

Before Instruction

PC Address

=

HERE

W

REG

=

?

After Instruction

If REG

PC

=

W;

Address (EQUAL)

If REG

PC

≠

=

W;

Address (NEQUAL)

DS41159B-page 294

 2002 Microchip Technology Inc.

PIC18FXX8

CPFSGT

Compare f with W, skip if f > W

CPFSLT

Compare f with W, skip if f < W

Syntax:

[ label ] CPFSGT f [,a]

Syntax:

[ label ] CPFSLT f [,a]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

(f) − (W),

Operation:

(f) – (W),

skip if (f) > (W)

(unsigned comparison)

skip if (f) < (W)

(unsigned comparison)

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0110

010a

ffff

0110

000a

ffff

Description:

Compares the contents of data

memory location ’f’ to the contents

of the W by performing an

Description:

Compares the contents of data

memory location 'f' to the contents

of W by performing an unsigned

subtraction.

unsigned subtraction.

If the contents of ’f’ are greater than

the contents of WREG, then the

fetched instruction is discarded and

a NOPis executed instead, making

this a two-cycle instruction. If ‘a’ is

0, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

If the contents of 'f' are less than

the contents of W, then the fetched

instruction is discarded and a NOP

is executed instead, making this a

two-cycle instruction. If ‘a’ is 0, the

Access Bank will be selected. If ’a’

is 1, the BSR will not be overridden

(default).

Words:

Cycles:

1

1(2)

Words:

Cycles:

1

Note: 3 cycles if skip and followed

by a 2-word instruction.

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

Read

register ’f’

Process

Data

No

operation

Q2

Q3

Q4

Decode

Read

register ’f’

Process

Data

No

operation

If skip:

Q1

Q2

Q3

Q4

If skip:

Q1

No

operation

No

operation

No

operation

No

operation

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

If skip and followed by 2-word instruction:

No

Q1

Q2

Q3

Q4

operation

No

operation

No

operation

HERE

NLESS

LESS

CPFSLT REG

:

Example:

HERE

CPFSGT REG

Example:

NGREATER

GREATER

:

Before Instruction

PC

W

=

Address (HERE)

?

Before Instruction

After Instruction

PC

W

=

Address (HERE)

?

If REG

PC

If REG

PC

<

=

≥

=

W;

Address (LESS)

W;

Address (NLESS)

After Instruction

If REG

PC

>

=

W;

Address (GREATER)

If REG

PC

≤

=

W;

Address (NGREATER)

 2002 Microchip Technology Inc.

DS41159B-page 295

PIC18FXX8

DAW

Decimal Adjust W Register

DECF

Decrement f

Syntax:

[label] DAW

Syntax:

[ label ] DECF f [,d [,a]]

Operands:

Operation:

None

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

If [W<3:0> >9] or [DC = 1] then

(W<3:0>) + 6 → W<3:0>;

else

(W<3:0>) → W<3:0>;

Operation:

(f) – 1 → dest

Status Affected:

Encoding:

C, DC, N, OV, Z

0000

01da

ffff

If [W<7:4> >9] or [C = 1] then

(W<7:4>) + 6 → W<7:4>;

else

Description:

Decrement register 'f'. If 'd' is 0, the

result is stored in W. If 'd' is 1, the

result is stored back in register 'f'

(default). If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ = 1, then the

bank will be selected as per the

BSR value (default).

(W<7:4>) → W<7:4>;

Status Affected:

Encoding:

C

0000

0111

Description:

DAW adjusts the eight-bit value in

W, resulting from the earlier addi-

tion of two variables (each in

packed BCD format) and produces

a correct packed BCD result.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Q3

Q4

Decode

Read

register ’f’

Process

Data

Write to

destination

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register W

Process

Data

Write

W

DECF

CNT,

Example:

Before Instruction

DAW

Example1:

CNT

Z

=

0x01

0

Before Instruction

After Instruction

W

C

DC

=

0xA5

0

CNT

=

0x00

1

Z

After Instruction

W

=

0x05

C

DC

=

1

0

Example 2:

Before Instruction

W

=

0xCE

C

DC

=

0

After Instruction

W

=

0x34

C

DC

=

1

0

DS41159B-page 296

 2002 Microchip Technology Inc.

PIC18FXX8

DECFSZ

Decrement f, skip if 0

DCFSNZ

Decrement f, skip if not 0

Syntax:

[ label ] DECFSZ f [,d [,a]]

Syntax:

[ label ] DCFSNZ f [,d [,a]]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) – 1 → dest,

skip if result = 0

Operation:

(f) – 1 → dest,

skip if result ≠ 0

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0010

11da

ffff

0100

11da

ffff

Description:

The contents of register 'f' are dec-

remented. If 'd' is 0, the result is

placed in W. If 'd' is 1, the result is

placed back in register 'f' (default).

If the result is 0, the next instruc-

tion, which is already fetched, is

discarded, and a NOPis executed

instead, making it a two-cycle

instruction. If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ = 1, then the

bank will be selected as per the

BSR value (default).

Description:

The contents of register 'f' are dec-

remented. If 'd' is 0, the result is

placed in W. If 'd' is 1, the result is

placed back in register 'f' (default).

If the result is not 0, the next

instruction, which is already

fetched, is discarded, and a NOPis

executed instead, making it a

two-cycle instruction. If ’a’ is 0, the

Access Bank will be selected,

overriding the BSR value. If ’a’ = 1,

then the bank will be selected as

per the BSR value (default).

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ’f’

Process

Data

Write to

destination

Decode

Read

register ’f’

Process

Data

Write to

destination

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

HERE

DECFSZ

GOTO

CNT

LOOP

HERE

ZERO

NZERO

DCFSNZ TEMP

:

Example:

CONTINUE

Before Instruction

TEMP

PC

=

Address (HERE)

=

?

After Instruction

CNT

=

≠

=

CNT - 1

0;

Address (CONTINUE)

0;

Address (HERE+2)

TEMP

If TEMP

PC

If TEMP

PC

=

≠

=

TEMP - 1,

0;

Address (ZERO)

0;

Address (NZERO)

If CNT

PC

If CNT

PC

 2002 Microchip Technology Inc.

DS41159B-page 297

PIC18FXX8

GOTO

Unconditional Branch

INCF

Increment f

Syntax:

[ label ] GOTO k

0 ≤ k ≤ 1048575

k → PC<20:1>

None

Syntax:

[ label ] INCF f [,d [,a]]

Operands:

Operation:

Status Affected:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) + 1 → dest

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

Status Affected:

Encoding:

C, DC, N, OV, Z

1110

1111

k kkk

kkkk

7

0

8

k

kkk kkkk

0010

10da

ffff

19

Description:

GOTOallows an unconditional

branch anywhere within entire

2 Mbyte memory range. The 20-bit

value ’k’ is loaded into PC<20:1>.

GOTOis always a two-cycle

instruction.

Description:

The contents of register ’f’ are

incremented. If ’d’ is 0, the result is

placed in W. If ’d’ is 1, the result is

placed back in register ’f’ (default).

If ’a’ is 0, the Access Bank will be

selected, overriding the BSR value.

If ’a’ = 1, then the bank will be

selected as per the BSR value

(default).

Words:

Cycles:

2

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Q3

Q4

Decode

Read literal

’k’<7:0>,

No

operation

Read literal

’k’<19:8>,

Write to PC

Q Cycle Activity:

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

Decode

Read

register ’f’

Process

Data

Write to

destination

GOTO THERE

Example:

INCF

CNT,

Example:

After Instruction

Before Instruction

PC

=

Address (THERE)

CNT

=

0xFF

Z

=

0

?

C

DC

After Instruction

CNT

=

0x00

Z

1

C

DC

DS41159B-page 298

 2002 Microchip Technology Inc.

PIC18FXX8

INCFSZ

Increment f, skip if 0

INFSNZ

Increment f, skip if not 0

Syntax:

[ label ] INCFSZ f [,d [,a]]

Syntax:

[ label ] INFSNZ f [,d [,a]]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) + 1 → dest,

skip if result = 0

Operation:

(f) + 1 → dest,

skip if result ≠ 0

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0011

11da

ffff

0100

10da

ffff

Description:

The contents of register ’f’ are

incremented. If ’d’ is 0, the result is

placed in W. If ’d’ is 1, the result is

placed back in register ’f’ (default).

If the result is 0, the next instruc-

tion, which is already fetched, is

discarded, and a NOPis executed

instead, making it a two-cycle

instruction. If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ = 1, then the

bank will be selected as per the

BSR value (default).

Description:

The contents of register 'f' are

incremented. If 'd' is 0, the result is

placed in W. If 'd' is 1, the result is

placed back in register 'f' (default).

If the result is not 0, the next

instruction, which is already

fetched, is discarded, and a NOPis

executed instead, making it a

two-cycle instruction. If ’a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ’a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ’f’

Process

Data

Write to

destination

Decode

Read

register ’f’

Process

Data

Write to

destination

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

HERE

NZERO

ZERO

INCFSZ

:

CNT

HERE

ZERO

NZERO

INFSNZ REG

Example:

Before Instruction

PC

=

Address (HERE)

PC

=

Address (HERE)

After Instruction

CNT

If CNT

PC

If CNT

PC

=

≠

=

CNT + 1

REG

If REG

PC

If REG

PC

=

≠

=

REG + 1

0;

Address (ZERO)

0;

Address (NZERO)

0;

Address (ZERO)

 2002 Microchip Technology Inc.

DS41159B-page 299

PIC18FXX8

IORLW

Inclusive OR literal with W

IORWF

Inclusive OR W with f

Syntax:

[ label ] IORLW k

0 ≤ k ≤ 255

Syntax:

[ label ] IORWF f [,d [,a]]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(W) .OR. k → W

N, Z

Operation:

(W) .OR. (f) → dest

0000

1001

kkkk

Status Affected:

Encoding:

N, Z

Description:

The contents of W are OR’ed with

the eight-bit literal 'k'. The result is

placed in W.

0001

00da

ffff

Description:

Inclusive OR W with register 'f'. If 'd'

is 0, the result is placed in W. If 'd'

is 1, the result is placed back in

register 'f' (default). If ’a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ’a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ’k’

Process

Data

Write to W

Words:

Cycles:

1

IORLW

0x35

Example:

Before Instruction

Q Cycle Activity:

Q1

W

=

0x9A

Q2

Q3

Q4

Decode

Read

register ’f’

Process

Data

Write to

destination

After Instruction

W

=

0xBF

IORWF RESULT, W

Example:

Before Instruction

RESULT =

0x13

0x91

W

=

After Instruction

RESULT =

0x13

0x93

W

=

DS41159B-page 300

 2002 Microchip Technology Inc.

PIC18FXX8

LFSR

Load FSR

MOVF

Move f

Syntax:

[ label ] LFSR f,k

Syntax:

[ label ] MOVF f [,d [,a]]

Operands:

0 ≤ f ≤ 2

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

0 ≤ k ≤ 4095

Operation:

k → FSRf

Operation:

f → dest

Status Affected:

Encoding:

None

Status Affected:

Encoding:

N, Z

1110

1111

1110

0000

00ff

k kkk

11

kkkk

k kkk

0101

00da

ffff

7

Description:

The 12-bit literal ’k’ is loaded into

the file select register pointed to

by ’f’.

Description:

The contents of register ’f’ are

moved to a destination dependent

upon the status of ’d’. If 'd' is 0, the

result is placed in W. If 'd' is 1, the

result is placed back in register 'f'

(default). Location 'f' can be any-

where in the 256 byte bank. If ’a’ is

0, the Access Bank will be

Words:

Cycles:

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

Decode

Read literal

’k’ MSB

Process

Data

Write

literal ’k’

MSB to

FSRfH

Decode

Read literal

’k’ LSB

Process

Data

Write literal

’k’ to FSRfL

Words:

Cycles:

1

Q Cycle Activity:

Q1

LFSR 2, 0x3AB

Example:

Q2

Q3

Q4

After Instruction

Decode

Read

register ’f’

Process

Data

Write W

FSR2H

FSR2L

=

0x03

0xAB

MOVF

REG, W

Example:

Before Instruction

REG

W

=

0x22

0xFF

After Instruction

REG

W

=

0x22

 2002 Microchip Technology Inc.

DS41159B-page 301

PIC18FXX8

MOVFF

Move f to f

MOVLB

Move literal to low nibble in BSR

Syntax:

[ label ] MOVFF f_s,f_d

Syntax:

[ label ] MOVLB k

0 ≤ k ≤ 255

k → BSR

Operands:

0 ≤ f_s≤ 4095

0 ≤ f_d≤ 4095

Operands:

Operation:

Status Affected:

Encoding:

Operation:

(f_s) → f_d

None

Status Affected:

None

0000

0001

kkkk

Encoding:

1st word (source)

2nd word (destin.)

Description:

The 8-bit literal ’k’ is loaded into

the Bank Select Register (BSR).

1100

1111

ffff

ffff_s

ffff_d

Words:

Cycles:

1

Description:

The contents of source register ’f_s’

are moved to destination register

’f_d’. Location of source ’f_s’ can be

anywhere in the 4096 byte data

space (000h to FFFh), and location

of destination ’f_d’ can also be any-

where from 000h to FFFh.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal

’k’

Process

Data

Write

literal ’k’ to

BSR

Either source or destination can be

W (a useful special situation).

MOVFFis particularly useful for

transferring a data memory location

to a peripheral register (such as the

transmit buffer or an I/O port).

MOVLB

5

Example:

Before Instruction

BSR register

=

0x02

0x05

After Instruction

BSR register

The MOVFFinstruction cannot use

the PCL, TOSU, TOSH or TOSL as

the destination register.

The MOVFFinstruction should not

be used to modify interrupt settings

while any interrupt is enabled (see

page 77).

Words:

Cycles:

2

2 (3)

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ’f’

(src)

Process

Data

No

operation

Decode

No

operation

No

operation

Write

register ’f’

(dest)

No dummy

read

MOVFF

REG1, REG2

Example:

Before Instruction

REG1

REG2

=

0x33

0x11

After Instruction

REG1

REG2

=

0x33,

0x33

DS41159B-page 302

 2002 Microchip Technology Inc.

PIC18FXX8

MOVLW

Move literal to W

MOVWF

Move W to f

Syntax:

[ label ] MOVLW k

0 ≤ k ≤ 255

k → W

Syntax:

[ label ] MOVWF f [,a]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

(W) → f

None

Status Affected:

Encoding:

None

0000

1110

kkkk

0110

111a

ffff

Description:

The eight-bit literal ’k’ is loaded into

W.

Description:

Move data from W to register ’f’.

Location ’f’ can be anywhere in the

256 byte bank. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ’k’

Process

Data

Write to W

Words:

Cycles:

1

MOVLW

0x5A

Example:

Q Cycle Activity:

Q1

After Instruction

Q2

Q3

Q4

W

=

0x5A

Decode

Read

register ’f’

Process

Data

Write

register ’f’

MOVWF

REG

Example:

Before Instruction

W

REG

=

0x4F

0xFF

After Instruction

W

REG

=

0x4F

 2002 Microchip Technology Inc.

DS41159B-page 303

PIC18FXX8

MULLW

Multiply Literal with W

MULWF

Multiply W with f

Syntax:

[ label ] MULLW

0 ≤ k ≤ 255

k

Syntax:

[ label ] MULWF f [,a]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

(W) x k → PRODH:PRODL

Operation:

(W) x (f) → PRODH:PRODL

None

Status Affected:

Encoding:

None

0000

1101

kkkk

0000

001a

ffff

Description:

An unsigned multiplication is car-

ried out between the contents of

W and the 8-bit literal ’k’. The

16-bit result is placed in

PRODH:PRODL register pair.

PRODH contains the high byte.

W is unchanged.

None of the status flags are

affected.

Note that neither overflow nor

carry is possible in this opera-

tion. A zero result is possible, but

not detected.

Description:

An unsigned multiplication is car-

ried out between the contents of

W and the register file location ’f’.

The 16-bit result is stored in the

PRODH:PRODL register pair.

PRODH contains the high byte.

Both W and ’f’ are unchanged.

None of the status flags are

affected.

Note that neither overflow nor

carry is possible in this opera-

tion. A zero result is possible, but

not detected. If ‘a’ is 0, the

Access Bank will be selected,

overriding the BSR value. If

‘a’= 1, then the bank will be

selected as per the BSR value

(default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ’k’

Process

Data

Write

registers

PRODH:

PRODL

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

MULLW

0xC4

Example:

Decode

Read

register ’f’

Process

Data

Write

Before Instruction

registers

PRODH:

PRODL

W

PRODH

PRODL

=

0xE2

?

After Instruction

W

MULWF

REG

Example:

=

0xE2

PRODH

PRODL

=

0xAD

0x08

Before Instruction

W

=

0xC4

REG

PRODH

PRODL

=

0xB5

?

After Instruction

W

=

0xC4

REG

PRODH

PRODL

=

0xB5

0x8A

0x94

DS41159B-page 304

 2002 Microchip Technology Inc.

PIC18FXX8

NEGF

Negate f

NOP

No Operation

Syntax:

[ label ] NEGF f [,a]

Syntax:

[ label ] NOP

None

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

Operation:

Status Affected:

Encoding:

No operation

None

Operation:

( f ) + 1 → f

Status Affected:

Encoding:

N, OV, C, DC, Z

0000

1111

0000

xxxx

0000

xxxx

0000

xxxx

0110

110a

ffff

Description:

Words:

No operation.

Description:

Location ‘f’ is negated using two’s

complement. The result is placed in

the data memory location 'f'. If ’a’ is

0, the Access Bank will be

1

Cycles:

Q Cycle Activity:

Q1

selected, overriding the BSR value.

If ’a’ = 1, then the bank will be

selected as per the BSR value.

Q2

No

Q3

No

Q4

Decode

No

operation

Words:

Cycles:

1

Example:

None.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ’f’

Process

Data

Write

register ’f’

NEGF

REG, 1

Example:

Before Instruction

REG

=

0011 1010 [0x3A]

1100 0110 [0xC6]

After Instruction

REG

=

 2002 Microchip Technology Inc.

DS41159B-page 305

PIC18FXX8

POP

Pop Top of Return Stack

PUSH

Push Top of Return Stack

Syntax:

[ label ] POP

None

Syntax:

[ label ] PUSH

None

Operands:

Operation:

Status Affected:

Encoding:

Operands:

Operation:

Status Affected:

Encoding:

(TOS) → bit bucket

None

(PC+2) → TOS

None

0000

0110

0000

0101

Description:

The TOS value is pulled off the

return stack and is discarded. The

TOS value then becomes the previ-

ous value that was pushed onto the

return stack.

This instruction is provided to

enable the user to properly manage

the return stack to incorporate a

software stack.

Description:

The PC+2 is pushed onto the top of

the return stack. The previous TOS

value is pushed down on the stack.

This instruction allows the user to

implement a software stack by

modifying TOS, and then push it

onto the return stack.

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

PUSH PC+2

onto return

stack

No

operation

No

operation

Q2

Q3

Q4

Decode

No

operation

POP TOS

value

No

operation

PUSH

Example:

POP

GOTO

Example:

Before Instruction

NEW

TOS

PC

=

0x00345A

0x000124

Before Instruction

TOS

=

0x0031A2

0x014332

After Instruction

Stack (1 level down)

PC

=

0x000126

0x00345A

TOS

After Instruction

Stack (1 level down)

TOS

PC

=

0x014332

NEW

DS41159B-page 306

 2002 Microchip Technology Inc.

PIC18FXX8

RCALL

Relative Call

RESET

Reset

Syntax:

[ label ] RCALL

-1024 ≤ n ≤ 1023

(PC) + 2 → TOS,

n

Syntax:

[ label ] RESET

Operands:

Operation:

Operands:

Operation:

None

Reset all registers and flags that

are affected by a MCLR Reset.

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

All

1101

1nnn

nnnn

0000

1111

Description:

Subroutine call with a jump up to

1K from the current location. First,

return address (PC+2) is pushed

onto the stack. Then, add the 2’s

complement number ’2n’ to the PC.

Since the PC will have incremented

to fetch the next instruction, the

new address will be PC+2+2n.

This instruction is a two-cycle

instruction.

Description:

This instruction provides a way to

execute a MCLR Reset in software.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Start

reset

No

operation

No

operation

Words:

Cycles:

1

2

RESET

Example:

After Instruction

Registers =

Reset Value

Q Cycle Activity:

Q1

Flags*

=

Q2

Q3

Q4

Decode

Read literal

’n’

Process

Data

Write to PC

Push PC to

stack

No

operation

HERE

RCALL

Jump

Example:

Before Instruction

PC

=

Address (HERE)

After Instruction

PC

=

Address (Jump)

Address (HERE+2)

TOS =

 2002 Microchip Technology Inc.

DS41159B-page 307

PIC18FXX8

RETFIE

Return from Interrupt

RETLW

Return Literal to W

Syntax:

[ label ] RETFIE [s]

s ∈ [0,1]

Syntax:

[ label ] RETLW k

0 ≤ k ≤ 255

Operands:

Operation:

Operands:

Operation:

(TOS) → PC,

1 → GIE/GIEH or PEIE/GIEL,

if s = 1

k → W,

(TOS) → PC,

PCLATU, PCLATH are unchanged

(WS) → W,

(STATUSS) → STATUS,

(BSRS) → BSR,

Status Affected:

Encoding:

None

0000

1100

kkkk

PCLATU, PCLATH are unchanged.

Description:

W is loaded with the eight-bit literal

'k'. The program counter is loaded

from the top of the stack (the return

address). The high address latch

(PCLATH) remains unchanged.

Status Affected:

Encoding:

GIE/GIEH, PEIE/GIEL.

0000

0001

000s

Description:

Return from interrupt. Stack is

popped and Top-of-Stack (TOS) is

loaded into the PC. Interrupts are

enabled by setting either the high

or low priority global interrupt

enable bit. If ‘s’ = 1, the contents of

the shadow registers WS,

STATUSS and BSRS are loaded

into their corresponding registers,

W, STATUS and BSR. If ‘s’ = 0, no

update of these registers occurs

(default).

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ’k’

Process

Data

pop PC from

stack, Write

to W

No

operation

Words:

Cycles:

1

2

Example:

CALL TABLE ; W contains table

; offset value

Q Cycle Activity:

Q1

Q2

Q3

Q4

; W now has

; table value

Decode

No

operation

No

operation

pop PC from

stack

:

TABLE

ADDWF PCL ; W = offset

Set GIEH or

GIEL

RETLW k0

RETLW k1

:

; Begin table

;

No

operation

No

operation

No

operation

No

operation

:

RETLW kn

; End of table

RETFIE

1

Example:

After Interrupt

Before Instruction

PC

W

=

TOS

WS

W

=

0x07

BSR

STATUS

GIE/GIEH, PEIE/GIEL

BSRS

STATUSS

1

After Instruction

W

=

value of kn

DS41159B-page 308

 2002 Microchip Technology Inc.

PIC18FXX8

RETURN

Return from Subroutine

RLCF

Rotate Left f through Carry

Syntax:

[ label ] RETURN [s]

s ∈ [0,1]

Syntax:

[ label ] RLCF f [,d [,a]]

Operands:

Operation:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(TOS) → PC,

if s = 1

(WS) → W,

Operation:

(f<n>) → dest<n+1>,

(f<7>) → C,

(STATUSS) → STATUS,

(BSRS) → BSR,

PCLATU, PCLATH are unchanged

(C) → dest<0>

Status Affected:

Encoding:

C, N, Z

Status Affected:

Encoding:

None

0011

01da

ffff

0000

0001

001s

Description:

The contents of register 'f' are

rotated one bit to the left through

the Carry Flag. If 'd' is 0, the result

is placed in W. If 'd' is 1, the result

is stored back in register 'f'

(default). If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ = 1, then the

bank will be selected as per the

BSR value (default).

Description:

Return from subroutine. The stack

is popped and the top of the stack

(TOS) is loaded into the program

counter. If ‘s’= 1, the contents of the

shadow registers WS, STATUSS

and BSRS are loaded into their cor-

responding registers, W, STATUS

and BSR. If ‘s’ = 0, no update of

these registers occurs (default).

Words:

Cycles:

1

2

register f

C

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

No

operation

Process

Data

pop PC from

stack

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

Decode

Read

register ’f’

Process

Data

Write to

destination

RLCF

REG, W

Example:

RETURN

Example:

Before Instruction

REG

C

=

1110 0110

0

After Interrupt

PC = TOS

After Instruction

REG

=

1110 0110

W

C

=

1100 1100

1

 2002 Microchip Technology Inc.

DS41159B-page 309

PIC18FXX8

RLNCF

Rotate Left f (no carry)

RRCF

Rotate Right f through Carry

Syntax:

[ label ] RLNCF f [,d [,a]]

Syntax:

[ label ] RRCF f [,d [,a]]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f<n>) → dest<n+1>,

(f<7>) → dest<0>

Operation:

(f<n>) → dest<n-1>,

(f<0>) → C,

(C) → dest<7>

Status Affected:

Encoding:

N, Z

Status Affected:

Encoding:

C, N, Z

0100

01da

ffff

0011

00da

ffff

Description:

The contents of register ’f’ are

rotated one bit to the left. If ’d’ is 0,

the result is placed in W. If ’d’ is 1,

the result is stored back in register

'f' (default). If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, then the

bank will be selected as per the

BSR value (default).

Description:

The contents of register 'f' are

rotated one bit to the right through

the Carry Flag. If 'd' is 0, the result

is placed in W. If 'd' is 1, the result

is placed back in register 'f'

(default). If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, then the

bank will be selected as per the

BSR value (default).

register f

Words:

Cycles:

1

register f

C

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

Read

register ’f’

Process

Data

Write to

destination

Q2

Q3

Q4

Decode

Read

register ’f’

Process

Data

Write to

destination

RLNCF

REG

Example:

Before Instruction

RRCF

REG, W

Example:

REG

=

1010 1011

0101 0111

After Instruction

Before Instruction

REG

=

REG

C

=

1110 0110

0

After Instruction

REG

=

1110 0110

W

C

=

0111 0011

0

DS41159B-page 310

 2002 Microchip Technology Inc.

PIC18FXX8

RRNCF

Rotate Right f (no carry)

SETF

Set f

Syntax:

[ label ] RRNCF f [,d [,a]]

Syntax:

[ label ] SETF f [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

FFh → f

Operation:

(f<n>) → dest<n-1>,

(f<0>) → dest<7>

Status Affected:

Encoding:

None

0110

100a

ffff

Status Affected:

Encoding:

N, Z

Description:

The contents of the specified regis-

ter are set to FFh. If ’a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ’a’ is 1, then

the bank will be selected as per the

BSR value (default).

0100

00da

ffff

Description:

The contents of register ’f’ are

rotated one bit to the right. If ’d’ is 0,

the result is placed in W. If ’d’ is 1,

the result is placed back in register

'f' (default). If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

register f

Decode

Read

register ’f’

Process

Data

Write

register ’f’

Words:

Cycles:

1

SETF

REG

Example:

Before Instruction

Q Cycle Activity:

Q1

REG

=

0x5A

0xFF

Q2

Q3

Q4

After Instruction

REG

Decode

Read

register ’f’

Process

Data

Write to

destination

=

RRNCF

REG, 1, 0

Example 1:

Before Instruction

REG

=

1101 0111

1110 1011

RRNCF REG, W

After Instruction

REG

=

Example 2:

Before Instruction

W

REG

=

?

1101 0111

After Instruction

W

REG

=

1110 1011

1101 0111

 2002 Microchip Technology Inc.

DS41159B-page 311

PIC18FXX8

SLEEP

Enter SLEEP mode

SUBFWB

Subtract f from W with borrow

Syntax:

[ label ] SLEEP

Syntax:

[ label ] SUBFWB f [,d [,a]]

Operands:

Operation:

None

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

00h → WDT,

0 → WDT postscaler,

1 → TO,

Operation:

(W) – (f) – (C) → dest

0 → PD

Status Affected:

Encoding:

N, OV, C, DC, Z

Status Affected:

Encoding:

TO, PD

0101

01da

ffff

0000

0011

Description:

Subtract register 'f' and carry flag

(borrow) from W (2’s complement

method). If 'd' is 0, the result is

stored in W. If 'd' is 1, the result is

stored in register 'f' (default). If ’a’ is

0, the Access Bank will be selected,

overriding the BSR value. If ’a’ is 1,

then the bank will be selected as

per the BSR value (default).

Description:

The power-down status bit (PD) is

cleared. The time-out status bit

(TO) is set. Watchdog Timer and

its postscaler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

No

operation

Process

Data

Go to

sleep

Q2

Q3

Q4

Decode

Read

register ’f’

Process

Data

Write to

destination

SLEEP

Example:

SUBFWB REG

Example 1:

Before Instruction

TO

PD

=

?

Before Instruction

REG

=

0x03

0x02

0x01

After Instruction

W

C

=

TO

=

1 †

PD

=

0

After Instruction

REG

W

=

0xFF

0x02

† If WDT causes wake-up, this bit is cleared.

C

Z

N

=

0x00

0x01 ; result is negative

SUBFWB

REG, 0, 0

Example 2:

Before Instruction

REG

=

2

W

C

=

5

1

After Instruction

REG

W

=

2

3

C

Z

N

=

1

0

; result is positive

SUBFWB

REG, 1, 0

Example 3:

Before Instruction

REG

=

1

W

C

=

2

0

After Instruction

REG

W

=

0

2

C

Z

N

=

1

0

; result is zero

DS41159B-page 312

 2002 Microchip Technology Inc.

PIC18FXX8

SUBLW

Subtract W from literal

SUBWF

Syntax:

Subtract W from f

Syntax:

[ label ] SUBLW k

0 ≤ k ≤ 255

[ label ] SUBWF f [,d [,a]]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

k – (W) → W

N, OV, C, DC, Z

Operation:

(f) – (W) → dest

0000

1000

kkkk

Status Affected:

Encoding:

N, OV, C, DC, Z

Description:

W is subtracted from the eight-bit

literal 'k'. The result is placed in

W.

0101

11da

ffff

Description:

Subtract W from register 'f' (2’s

complement method). If 'd' is 0,

the result is stored in W. If 'd' is 1,

the result is stored back in regis-

ter 'f' (default). If ’a’ is 0, the

Access Bank will be selected,

overriding the BSR value. If ’a’ is

1, then the bank will be selected

as per the BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ’k’

Process

Data

Write to W

SUBLW 0x02

Example 1:

Words:

Cycles:

1

Before Instruction

W

C

=

1

?

Q Cycle Activity:

Q1

Q2

Q3

Q4

After Instruction

Decode

Read

register ’f’

Process

Data

Write to

destination

W

=

1

C

=

1

0

; result is positive

Z

SUBWF REG

Example 1:

N

SUBLW 0x02

Example 2:

Before Instruction

REG

W

C

=

3

2

?

Before Instruction

W

C

=

2

?

After Instruction

REG

W

=

1

2

W

=

0

C

Z

N

=

1

0

; result is positive

C

Z

N

=

1

0

; result is zero

SUBWF REG, W

Example 2:

SUBLW 0x02

Example 3:

Before Instruction

REG

=

2

?

W

C

=

3

?

W

C

=

After Instruction

W

=

FF ; (2’s complement)

REG

=

2

0

C

Z

N

=

0

1

; result is negative

W

=

C

Z

N

=

1

0

; result is zero

SUBWF REG

Example 3:

Before Instruction

REG

=

0x01

W

C

=

0x02

?

After Instruction

REG

W

=

0xFFh ;(2’s complement)

0x02

C

Z

N

=

0x00 ; result is negative

0x00

0x01

 2002 Microchip Technology Inc.

DS41159B-page 313

PIC18FXX8

SUBWFB

Syntax:

Subtract W from f with Borrow

SWAPF

Swap f

Syntax:

[ label ] SWAPF f [,d [,a]]

[ label ] SUBWFB f [,d [,a]]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f<3:0>) → dest<7:4>,

(f<7:4>) → dest<3:0>

Operation:

(f) – (W) – (C) → dest

Status Affected: N, OV, C, DC, Z

Status Affected:

Encoding:

None

0101

10da

ffff

Encoding:

0011

10da

ffff

Description:

Subtract W and the carry flag (bor-

row) from register 'f' (2’s complement

method). If 'd' is 0, the result is stored

in W. If 'd' is 1, the result is stored

back in register 'f' (default). If ’a’ is 0,

the Access Bank will be selected,

overriding the BSR value. If ’a’ is 1,

then the bank will be selected as per

the BSR value (default).

Description:

The upper and lower nibbles of reg-

ister ’f’ are exchanged. If ’d’ is 0, the

result is placed in W. If ’d’ is 1, the

result is placed in register ’f’

(default). If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ’f’

Process

Data

Write to

destination

Decode

Read

register ’f’

Process

Data

Write to

destination

SUBWFB REG, 1, 0

Example 1:

Before Instruction

SWAPF

REG

Example:

REG

=

0x19

0x0D

0x01

(0001 1001)

(0000 1101)

Before Instruction

W

C

=

REG

=

0x53

0x35

After Instruction

REG

=

REG

=

0x0C

0x0D

(0000 1011)

(0000 1101)

W

=

C

Z

N

=

0x01

0x00

; result is positive

SUBWFB REG, 0, 0

Example 2:

Before Instruction

REG

W

C

=

0x1B

0x1A

0x00

(0001 1011)

(0001 1010)

After Instruction

REG

W

=

0x1B

0x00

(0001 1011)

C

Z

N

=

0x01

0x00

; result is zero

SUBWFB REG, 1, 0

Example 3:

Before Instruction

REG

W

C

=

0x03

0x0E

0x01

(0000 0011)

(0000 1101)

After Instruction

REG

=

0xF5

0x0E

(1111 0100)

; [2’s comp]

(0000 1101)

W

=

C

Z

N

=

0x00

0x01

; result is negative

DS41159B-page 314

 2002 Microchip Technology Inc.

PIC18FXX8

TBLRD

Table Read

TBLRD

Table Read (cont’d)

TBLRD *+ ;

Syntax:

[ label ] TBLRD ( *; *+; *-; +*)

Example1:

Operands:

Operation:

None

Before Instruction

TABLAT

TBLPTR

MEMORY(0x00A356)

=

0x55

0x00A356

0x34

if TBLRD *,

(Prog Mem (TBLPTR)) → TABLAT;

TBLPTR - No Change;

if TBLRD *+,

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) +1 → TBLPTR;

if TBLRD *-,

After Instruction

TABLAT

TBLPTR

=

0x34

0x00A357

TBLRD +* ;

Example2:

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) -1 → TBLPTR;

if TBLRD +*,

(TBLPTR) +1 → TBLPTR;

(Prog Mem (TBLPTR)) → TABLAT;

Before Instruction

TABLAT

TBLPTR

=

0xAA

0x01A357

0x12

MEMORY(0x01A357)

MEMORY(0x01A358)

0x34

After Instruction

Status Affected:None

TABLAT

TBLPTR

=

0x34

0x01A358

0000

10nn

nn=0 *

=1 *+

=2 *-

=3 +*

Encoding:

Description:

This instruction is used to read the con-

tents of Program Memory (P.M.). To

address the program memory, a pointer

called Table Pointer (TBLPTR) is used.

The TBLPTR (a 21-bit pointer) points

to each byte in the program memory.

TBLPTR has a 2 Mbyte address range.

TBLPTR[0] = 0: Least Significant

Byte of Program

Memory Word

TBLPTR[0] = 1: Most Significant

Byte of Program

Memory Word

The TBLRDinstruction can modify the

value of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

No

operation

No

No operation

No

No operation

operation (Read Program operation (Write TABLAT)

Memory)

 2002 Microchip Technology Inc.

DS41159B-page 315

PIC18FXX8

TBLWT

Table Write

TBLWT Table Write (Continued)

Syntax:

[ label ]

TBLWT ( *; *+; *-; +*)

Words: 1

Operands:

Operation:

None

Cycles: 2

if TBLWT*,

Q Cycle Activity:

(TABLAT) → Holding Register;

TBLPTR - No Change;

if TBLWT*+,

Q1

Q2

Q3

Q4

Decode

No

operation

(TABLAT) → Holding Register;

(TBLPTR) +1 → TBLPTR;

if TBLWT*-,

(TABLAT) → Holding Register;

(TBLPTR) -1 → TBLPTR;

if TBLWT+*,

No

operation

No

operation

(Read

No

operation

No

operation

(Write to

Holding

Register )

TABLAT)

(TBLPTR) +1 → TBLPTR;

(TABLAT) → Holding Register;

Example1:

TBLWT *+;

Before Instruction

Status Affected: None

TABLAT

TBLPTR

=

0x55

0000

11nn

nn=0 *

=1 *+

=2 *-

=3 +*

Encoding:

0x00A356

HOLDING REGISTER

(0x00A356)

=

0xFF

After Instructions (table write completion)

TABLAT

TBLPTR

HOLDING REGISTER

(0x00A356)

=

0x55

0x00A357

Description:

This instruction uses the 3 LSBs of

TBLPTR to determine which of the 8

holding registers the TABLAT is written

to. The holding registers are used to

program the contents of Program

Memory (P.M.). (Refer to Section 6.0

for additional details on programming

FLASH memory.)

=

0x55

Example 2:

TBLWT +*;

Before Instruction

TABLAT

TBLPTR

HOLDING REGISTER

(0x01389A)

HOLDING REGISTER

(0x01389B)

=

0x34

0x01389A

=

0xFF

The TBLPTR (a 21-bit pointer) points

to each byte in the program memory.

TBLPTR has a 2 MBtye address

range. The LSb of the TBLPTR selects

which byte of the program memory

location to access.

After Instruction (table write completion)

TABLAT

TBLPTR

HOLDING REGISTER

(0x01389A)

HOLDING REGISTER

(0x01389B)

=

0x34

0x01389B

=

0xFF

0x34

TBLPTR[0] = 0:Least Significant

Byte of Program

Memory Word

TBLPTR[0] = 1:Most Significant

Byte of Program

Memory Word

The TBLWT instruction can modify the

value of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

DS41159B-page 316

 2002 Microchip Technology Inc.

PIC18FXX8

TSTFSZ

Test f, skip if 0

XORLW

Exclusive OR literal with W

Syntax:

[ label ] TSTFSZ f [,a]

Syntax:

[ label ] XORLW k

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

Operation:

Status Affected:

Encoding:

(W) .XOR. k → W

N, Z

Operation:

skip if f = 0

None

Status Affected:

Encoding:

0000

1010

kkkk

0110

011a

ffff

Description:

The contents of W are XORed

with the 8-bit literal 'k'. The result

is placed in W.

Description:

If ’f’ = 0, the next instruction,

fetched during the current instruc-

tion execution is discarded and a

NOPis executed, making this a

two-cycle instruction. If ’a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ’a’ is 1,

then the bank will be selected as

per the BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ’k’

Process

Data

Write to W

Words:

Cycles:

1

1(2)

XORLW 0xAF

Example:

Note: 3 cycles if skip and followed

by a 2-word instruction.

Before Instruction

W

=

0xB5

0x1A

Q Cycle Activity:

Q1

After Instruction

Q2

Q3

Q4

W

=

Decode

Read

register ’f’

Process

Data

No

operation

If skip:

Q1

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No

operation

No

operation

HERE

NZERO

ZERO

TSTFSZ CNT

:

Example:

:

Before Instruction

PC

=

Address (HERE)

After Instruction

If CNT

=

≠

=

0x00,

PC

Address (ZERO)

0x00,

If CNT

PC

Address (NZERO)

 2002 Microchip Technology Inc.

DS41159B-page 317

PIC18FXX8

XORWF

Exclusive OR W with f

Syntax:

[ label ] XORWF f [,d [,a]]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(W) .XOR. (f) → dest

Status Affected:

Encoding:

N, Z

0001

10da

ffff

Description:

Exclusive OR the contents of W

with register ’f’. If ’d’ is 0, the result

is stored in W. If ’d’ is 1, the result is

stored back in the register ’f’

(default). If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ’f’

Process

Data

Write to

destination

XORWF

REG

Example:

Before Instruction

REG

W

=

0xAF

0xB5

After Instruction

REG

W

=

0x1A

0xB5

DS41159B-page 318

 2002 Microchip Technology Inc.

PIC18FXX8

The MPLAB IDE allows you to:

26.0 DEVELOPMENT SUPPORT

• Edit your source files (either assembly or ‘C’)

The PICmicro^®microcontrollers are supported with a

full range of hardware and software development tools:

• One touch assemble (or compile) and download

to PICmicro emulator and simulator tools (auto-

matically updates all project information)

• Integrated Development Environment

- MPLAB^®IDE Software

• Debug using:

- source files

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

- absolute listing file

- machine code

- MPLAB C17 and MPLAB C18 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

The ability to use MPLAB IDE with multiple debugging

tools allows users to easily switch from the cost-

effective simulator to a full-featured emulator with

minimal retraining.

• Simulators

- MPLAB SIM Software Simulator

• Emulators

26.2 MPASM Assembler

- MPLAB ICE 2000 In-Circuit Emulator

- ICEPIC™ In-Circuit Emulator

• In-Circuit Debugger

The MPASM assembler is a full-featured universal

macro assembler for all PICmicro MCU’s.

- MPLAB ICD

The MPASM assembler has a command line interface

and a Windows shell. It can be used as a stand-alone

application on a Windows 3.x or greater system, or it

can be used through MPLAB IDE. The MPASM assem-

bler generates relocatable object files for the MPLINK

object linker, Intel^®standard HEX files, MAP files to

detail memory usage and symbol reference, an abso-

lute LST file that contains source lines and generated

machine code, and a COD file for debugging.

• Device Programmers

- PRO MATE^®II Universal Device Programmer

- PICSTART^®Plus Entry-Level Development

Programmer

• Low Cost Demonstration Boards

- PICDEM^TM1 Demonstration Board

- PICDEM 2 Demonstration Board

- PICDEM 3 Demonstration Board

- PICDEM 17 Demonstration Board

- KEELOQ^®Demonstration Board

The MPASM assembler features include:

• Integration into MPLAB IDE projects.

• User-defined macros to streamline assembly

code.

26.1 MPLAB Integrated Development

Environment Software

• Conditional assembly for multi-purpose source

files.

The MPLAB IDE software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. The MPLAB IDE is a Windows^®-based

application that contains:

• Directives that allow complete control over the

assembly process.

26.3 MPLAB C17 and MPLAB C18

C Compilers

• An interface to debugging tools

- simulator

The MPLAB C17 and MPLAB C18 Code Development

Systems are complete ANSI ‘C’ compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microcontrollers, respectively. These compilers provide

powerful integration capabilities and ease of use not

found with other compilers.

- programmer (sold separately)

- emulator (sold separately)

- in-circuit debugger (sold separately)

• A full-featured editor

• A project manager

For easier source level debugging, the compilers pro-

vide symbol information that is compatible with the

MPLAB IDE memory display.

• Customizable toolbar and key mapping

• A status bar

• On-line help

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 319

PIC18FXX8

26.4 MPLINK Object Linker/

MPLIB Object Librarian

26.6 MPLAB ICE High Performance

Universal In-Circuit Emulator with

MPLAB IDE

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C compilers. It can also

link relocatable objects from pre-compiled libraries,

using directives from a linker script.

The MPLAB ICE universal in-circuit emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PICmicro

microcontrollers (MCUs). Software control of the

MPLAB ICE in-circuit emulator is provided by the

MPLAB Integrated Development Environment (IDE),

which allows editing, building, downloading and source

debugging from a single environment.

The MPLIB object librarian is a librarian for pre-

compiled code to be used with the MPLINK object

linker. When a routine from a library is called from

another source file, only the modules that contain that

routine will be linked in with the application. This allows

large libraries to be used efficiently in many different

applications. The MPLIB object librarian manages the

creation and modification of library files.

The MPLAB ICE 2000 is a full-featured emulator sys-

tem with enhanced trace, trigger and data monitoring

features. Interchangeable processor modules allow the

system to be easily reconfigured for emulation of differ-

ent processors. The universal architecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PICmicro microcontrollers.

The MPLINK object linker features include:

• Integration with MPASM assembler and MPLAB

C17 and MPLAB C18 C compilers.

The MPLAB ICE in-circuit emulator system has been

designed as a real-time emulation system, with

advanced features that are generally found on more

expensive development tools. The PC platform and

Microsoft^®Windows environment were chosen to best

make these features available to you, the end user.

• Allows all memory areas to be defined as sections

to provide link-time flexibility.

The MPLIB object librarian features include:

• Easier linking because single libraries can be

included instead of many smaller files.

• Helps keep code maintainable by grouping

related modules together.

26.7 ICEPIC In-Circuit Emulator

• Allows libraries to be created and modules to be

added, listed, replaced, deleted or extracted.

The ICEPIC low cost, in-circuit emulator is a solution

for the Microchip Technology PIC16C5X, PIC16C6X,

PIC16C7X and PIC16CXXX families of 8-bit One-

Time-Programmable (OTP) microcontrollers. The mod-

ular system can support different subsets of PIC16C5X

or PIC16CXXX products through the use of inter-

changeable personality modules, or daughter boards.

The emulator is capable of emulating without target

application circuitry being present.

26.5 MPLAB SIM Software Simulator

The MPLAB SIM software simulator allows code devel-

opment in a PC-hosted environment by simulating the

PICmicro series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user-defined key press, to any of the pins. The

execution can be performed in single step, execute

until break, or trace mode.

The MPLAB SIM simulator fully supports symbolic debug-

ging using the MPLAB C17 and the MPLAB C18 C com-

pilers and the MPASM assembler. The software simulator

offers the flexibility to develop and debug code outside of

the laboratory environment, making it an excellent multi-

project software development tool.

DS41159B-page 320

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

26.8 MPLAB ICD In-Circuit Debugger

26.11 PICDEM 1 Low Cost PICmicro

Demonstration Board

Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-

erful, low cost, run-time development tool. This tool is

based on the FLASH PICmicro MCUs and can be used

to develop for this and other PICmicro microcontrollers.

The MPLAB ICD utilizes the in-circuit debugging capa-

bility built into the FLASH devices. This feature, along

with Microchip’s In-Circuit Serial Programming^TMproto-

col, offers cost-effective in-circuit FLASH debugging

from the graphical user interface of the MPLAB

Integrated Development Environment. This enables a

designer to develop and debug source code by watch-

ing variables, single-stepping and setting break points.

Running at full speed enables testing hardware in real-

time.

The PICDEM 1 demonstration board is a simple board

which demonstrates the capabilities of several of

Microchip’s microcontrollers. The microcontrollers sup-

ported are: PIC16C5X (PIC16C54 to PIC16C58A),

PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,

PIC17C42, PIC17C43 and PIC17C44. All necessary

hardware and software is included to run basic demo

programs. The user can program the sample microcon-

trollers provided with the PICDEM 1 demonstration

board on a PRO MATE II device programmer, or a

PICSTART Plus development programmer, and easily

test firmware. The user can also connect the

PICDEM 1 demonstration board to the MPLAB ICE in-

circuit emulator and download the firmware to the emu-

lator for testing. A prototype area is available for the

user to build some additional hardware and connect it

to the microcontroller socket(s). Some of the features

include an RS-232 interface, a potentiometer for simu-

lated analog input, push button switches and eight

LEDs connected to PORTB.

26.9 PRO MATE II Universal Device

Programmer

The PRO MATE II universal device programmer is a

full-featured programmer, capable of operating in

stand-alone mode, as well as PC-hosted mode. The

PRO MATE II device programmer is CE compliant.

The PRO MATE II device programmer has program-

mable VDD and VPP supplies, which allow it to verify

programmed memory at VDD min and VDD max for max-

imum reliability. It has an LCD display for instructions

and error messages, keys to enter commands and a

modular detachable socket assembly to support various

package types. In stand-alone mode, the PRO MATE II

device programmer can read, verify, or program

PICmicro devices. It can also set code protection in this

mode.

26.12 PICDEM 2 Low Cost PIC16CXX

Demonstration Board

The PICDEM 2 demonstration board is a simple dem-

onstration board that supports the PIC16C62,

PIC16C64, PIC16C65, PIC16C73 and PIC16C74

microcontrollers. All the necessary hardware and soft-

ware is included to run the basic demonstration pro-

grams. The user can program the sample

microcontrollers provided with the PICDEM 2 demon-

stration board on a PRO MATE II device programmer,

or a PICSTART Plus development programmer, and

easily test firmware. The MPLAB ICE in-circuit emula-

tor may also be used with the PICDEM 2 demonstration

board to test firmware. A prototype area has been pro-

vided to the user for adding additional hardware and

connecting it to the microcontroller socket(s). Some of

the features include a RS-232 interface, push button

switches, a potentiometer for simulated analog input, a

serial EEPROM to demonstrate usage of the I²C^TMbus

and separate headers for connection to an LCD

module and a keypad.

26.10 PICSTART Plus Entry Level

Development Programmer

The PICSTART Plus development programmer is an

easy-to-use, low cost, prototype programmer. It con-

nects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient.

The PICSTART Plus development programmer sup-

ports all PICmicro devices with up to 40 pins. Larger pin

count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus development programmer is CE

compliant.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 321

PIC18FXX8

26.13 PICDEM 3 Low Cost PIC16CXXX

Demonstration Board

26.14 PICDEM 17 Demonstration Board

The PICDEM 17 demonstration board is an evaluation

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. All neces-

sary hardware is included to run basic demo programs,

which are supplied on a 3.5-inch disk. A programmed

sample is included and the user may erase it and

program it with the other sample programs using the

PRO MATE II device programmer, or the PICSTART

Plus development programmer, and easily debug and

test the sample code. In addition, the PICDEM 17 dem-

onstration board supports downloading of programs to

and executing out of external FLASH memory on board.

The PICDEM 17 demonstration board is also usable

with the MPLAB ICE in-circuit emulator, or the

PICMASTER emulator and all of the sample programs

can be run and modified using either emulator. Addition-

ally, a generous prototype area is available for user

hardware.

The PICDEM 3 demonstration board is a simple dem-

onstration board that supports the PIC16C923 and

PIC16C924 in the PLCC package. It will also support

future 44-pin PLCC microcontrollers with an LCD Mod-

ule. All the necessary hardware and software is

included to run the basic demonstration programs. The

user can program the sample microcontrollers pro-

vided with the PICDEM 3 demonstration board on a

PRO MATE II device programmer, or a PICSTART Plus

development programmer with an adapter socket, and

easily test firmware. The MPLAB ICE in-circuit emula-

tor may also be used with the PICDEM 3 demonstration

board to test firmware. A prototype area has been pro-

vided to the user for adding hardware and connecting it

to the microcontroller socket(s). Some of the features

include a RS-232 interface, push button switches, a

potentiometer for simulated analog input, a thermistor

and separate headers for connection to an external

LCD module and a keypad. Also provided on the

PICDEM 3 demonstration board is a LCD panel, with 4

commons and 12 segments, that is capable of display-

ing time, temperature and day of the week. The

PICDEM 3 demonstration board provides an additional

RS-232 interface and Windows software for showing

the demultiplexed LCD signals on a PC. A simple serial

interface allows the user to construct a hardware

demultiplexer for the LCD signals.

26.15 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support

Microchip’s HCS Secure Data Products. The HCS eval-

uation kit includes a LCD display to show changing

codes, a decoder to decode transmissions and a pro-

gramming interface to program test transmitters.

DS41159B-page 322

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 26-1: DEVELOPMENT TOOLS FROM MICROCHIP

0 1 5 2 P M C

X X X C R M F

H C S X X X

X X C 9 3

/ X X C 2 5

/ X X C 2 4

X X X F 8 C 1 P I

X X C 8 2 C 1 P I

X 7 X 7 C 1 C I P

X 4 1 7 C I C P

X 9 X 6 C 1 C I P

X 8 X 6 F 1 C I P

8 X 6 1 F C I P

/ X 8 1 6 C I C P

X 7 X 6 C 1 C I P

X 7 1 6 C I C P

X 6 2 1 6 C I F P

X

X X C 6 C 1 P I

X 6 1 6 C I C P

X 5 1 6 C I C P

0 0 1 4 C I 0 P

X

X X C 2 C 1 P I

s o l T e o r a w f t S o s r o t a u l E m e r u b g e g D s m e a r m o g P r r

s t K l a i E d v n a s d r a B o o m D e

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 323

PIC18FXX8

NOTES:

DS41159B-page 324

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

27.0 ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-55°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V

Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V

Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V

Total power dissipation (Note 1) ...............................................................................................................................1.0W

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin ..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) ...................................................................................................±20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports (combined) ....................................................................................................200 mA

Maximum current sourced by all ports (combined) ...............................................................................................200 mA

Note 1: Power dissipation is calculated as follows:

Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latchup.

Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather

than pulling this pin directly to VSS.

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions

above those indicated in the operation listings of this specification is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 325

PIC18FXX8

FIGURE 27-1:

PIC18FXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

6.0V

5.5V

5.0V

4.5V

4.0V

PIC18FXX8

4.2V

3.5V

3.0V

2.5V

2.0V

40 MHz

Frequency

FIGURE 27-2:

PIC18LFXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

6.0V

5.5V

5.0V

4.5V

4.0V

PIC18LFXX8

4.2V

3.5V

3.0V

2.5V

2.0V

40 MHz

4 MHz

Frequency

FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V

= 40 MHz, if VDDAPPMIN > 4.2V

Note: VDDAPPMIN is the minimum voltage of the PICmicro^®device in the application.

DS41159B-page 326

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

27.1 DC Characteristics

PIC18LFXX8

Standard Operating Conditions (unless otherwise stated)

(Industrial)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

PIC18FXX8

(Industrial, Extended)

Param

No.

Characteristic/

Symbol

Min Typ⁽⁵⁾Max Units

Conditions

Device

VDD

Supply Voltage

D001

D002

PIC18LFXX8 2.0

PIC18FXX8 4.2

—

5.5

—

V

HS, XT, RC and LP osc mode

VDR

RAM Data Retention

1.5

Voltage⁽¹⁾

D003

D004

VPOR

VDD Start Voltage

to ensure internal

Power-on Reset signal

—

0.7

—

V

See section on Power-on Reset for details

SVDD

VBOR

VDD Rise Rate

to ensure internal

Power-on Reset signal

0.05

V/ms See section on Power-on Reset for details

Brown-out Reset Voltage

PIC18LFXX8

D005

BORV1:BORV0 = 11 2.0

BORV1:BORV0 = 10 2.7

BORV1:BORV0 = 01 4.2

BORV1:BORV0 = 00 4.5

PIC18FXX8

—

2.16

2.86

4.46

4.78

V

BORV1:BORV0 = 1x N.A.

BORV1:BORV0 = 01 4.2

BORV1:BORV0 = 00 4.5

—

N.A.

4.46

4.78

V

Not in operating voltage range of device

Legend: Shading of rows is to assist in readability of the table.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET, without losing

RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption.

The test conditions for all IDD measurements in Active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and

all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.

5: Typical is taken at 25°C.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 327

PIC18FXX8

27.1 DC Characteristics (Continued)

PIC18LFXX8

Standard Operating Conditions (unless otherwise stated)

(Industrial)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

PIC18FXX8

(Industrial, Extended)

Param

Symbol

No.

Characteristic/

Device

Min Typ⁽⁵⁾Max Units

Conditions

Supply Current^(2,3,4)

PIC18LFXX8

IDD

D010

XT, RC, RCIO osc configurations

—

1

2

TBD mA FOSC = 4 MHz, VDD = 2.0V

D010

PIC18FXX8

PIC18LFXX8

PIC18FXX8

PIC18LFXX8

PIC18FXX8

PIC18LFXX8

XT, RC, RCIO osc configurations

TBD mA FOSC = 4 MHz, VDD = 4.2V

D010A

D010C

D013

LP osc configuration

30 TBD µA FOSC = 32 kHz, VDD = 2.0V

LP osc configuration

185 TBD µA FOSC = 32 kHz, VDD = 4.2V

EC, ECIO osc configurations,

22 TBD mA FOSC = 40 MHz, VDD = 5.5V

EC, ECIO osc configurations,

22 TBD mA FOSC = 40 MHz, VDD = 5.5V

HS osc configurations

1.4 TBD mA FOSC = 6 MHz, VDD = 2.5V

14 TBD mA FOSC = 25 MHz, VDD = 5.5V

HS + PLL osc configuration

—

22 TBD mA FOSC = 10 MHz, VDD = 5.5V

D013

PIC18FXX8

HS osc configurations

14 TBD mA FOSC = 25 MHz, VDD = 5.5V

HS + PLL osc configuration

—

22 TBD mA FOSC = 10 MHz, VDD = 5.5V

D014

PIC18LFXX8

PIC18FXX8

Timer1 osc configuration

32 TBD µA FOSC = 32 kHz, VDD = 2.5V

OSCB osc configuration

62 TBD µA FOSC = 32 kHz, VDD = 4.2V

—

Legend: Rows are shaded for improved readability.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET, without losing

RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in Active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS,

and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.

5: Typical is taken at 25°C.

DS41159B-page 328

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

27.1 DC Characteristics (Continued)

PIC18LFXX8

(Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

PIC18FXX8

(Industrial, Extended)

Param

Symbol

No.

Characteristic/

Device

Min Typ⁽⁵⁾Max Units

Conditions

IPD

Power-down Current⁽³⁾

D020

D021B

PIC18LFXX8

—

0.09 TBD µA VDD = 2.5V, -40°C to +85°C

0.11 TBD µA VDD = 5.5V, -40°C to +85°C

PIC18FXX8

—

0.1 TBD µA VDD = 4.2V, -40°C to +85°C

0.11 TBD µA VDD = 5.5V, -40°C to +85°C

—

0.1 TBD µA VDD = 4.2V, -40°C to +125°C

0.11 TBD µA VDD = 5.5V, -40°C to +125°C

∆IWDT

Module Differential Current

D022

Watchdog Timer

—

1

TBD µA VDD = 2.5V

PIC18LFXX8

15 TBD µA VDD = 5.5V

15 TBD µA VDD = 5.5V, -40°C to +85°C

15 TBD µA VDD = 5.5V, -40°C to +125°C

Watchdog Timer

—

PIC18FXX8

D022A ∆IBOR

D022A

Brown-out Reset

—

40 TBD µA VDD = 5.5V

PIC18LFXX8

Brown-out Reset

—

40 TBD µA VDD = 5.5V, -40°C to +85°C

40 TBD µA VDD = 5.5V, -40°C to +125°

PIC18FXX8

D022B ∆ILVD

D022B

Low Voltage Detect

—

30 TBD µA VDD = 2.5V

PIC18LFXX8

Low Voltage Detect

—

40 TBD µA VDD = 4.2V, -40°C to +85°C

40 TBD µA VDD = 4.2V, -40°C to +125°C

PIC18FXX8

D025

∆IOSCB

Timer1 Oscillator

—

8

TBD µA VDD = 2.5V

PIC18LFXX8

Timer1 Oscillator

—

9

TBD µA VDD = 4.2V, -40°C to +85°C

TBD µA VDD = 4.2V, -40°C to +125°C

PIC18FXX8

Legend: Rows are shaded for improved readability.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET, without losing

RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in Active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS,

and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.

5: Typical is taken at 25°C.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 329

PIC18FXX8

27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended)

PIC18LFXX8 (Industrial)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

Symbol

No.

Characteristic/

Device

Min

Max

Units

Conditions

VIL

Input Low Voltage

I/O ports:

D030

D030A

D031

with TTL buffer

VSS

—

0.15 VDD

0.8

V

VDD < 4.5V

4.5V ≤ VDD ≤ 5.5V

with Schmitt Trigger buffer

RC3 and RC4

VSS

0.2 VDD

0.3 VDD

V

D032

MCLR

VSS

0.2 VDD

0.3 VDD

V

D032A

OSC1 (in XT, HS and LP modes)

and T1OSI

D033

OSC1 (in RC mode)⁽¹⁾

Input High Voltage

I/O ports:

VSS

0.2 VDD

V

VIH

D040

D040A

D041

with TTL buffer

0.25 VDD + 0.8V

2.0

VDD

V

VDD < 4.5V

4.5V ≤ VDD ≤ 5.5V

with Schmitt Trigger buffer

RC3 and RC4

0.8 VDD

0.7 VDD

VDD

V

D042

MCLR

0.8 VDD

0.7 VDD

VDD

V

D042A

OSC1 (in XT, HS and LP modes)

and T1OSI

D043

OSC1 (RC mode)⁽¹⁾

0.9 VDD

TBD

VDD

TBD

V

D050 VHYS

Hysteresis of Schmitt Trigger

Inputs

IIL

Input Leakage Current^(2,3)

D060

I/O ports

—

1

µA VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

D061

MCLR

—

5

µA Vss ≤ VPIN ≤ VDD

D063

OSC1

IPU

Weak Pull-up Current

PORTB weak pull-up current

D070 IPURB

50

400

µA VDD = 5V, VPIN = VSS

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the

PICmicro device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

DS41159B-page 330

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended)

PIC18LFXX8 (Industrial) (Continued)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

DC CHARACTERISTICS

Param

Symbol

No.

Characteristic/

Device

Min

Max

Units

Conditions

VOL

Output Low Voltage

D080

I/O ports

—

0.6

V

IOL = 8.5 mA, VDD = 4.2V,

-40°C to +85°C

D080A

D083

IOL = 7.0 mA, VDD = 4.2V,

-40°C to +125°C

IOL = 1.6 mA, VDD = 4.2V,

-40°C to +85°C

OSC2/CLKO

(RC mode)

D083A

IOL = 1.2 mA, VDD = 4.2V,

-40°C to +125°C

VOH

Output High Voltage⁽³⁾

D090

I/O ports

VDD - 0.7

—

V

IOH = -3.0 mA, VDD = 4.2V,

-40°C to +85°C

D090A

D092

IOH = -2.5 mA, VDD = 4.2V,

-40°C to +125°C

OSC2/CLKO

(RC mode)

—

IOH = -1.3 mA, VDD = 4.2V,

-40°C to +85°C

IOH = -1.0 mA, VDD = 4.2V,

-40°C to +125°C

D092A

D150

—

VOD

Open Drain High Voltage

7.5

RA4 pin

Capacitive Loading Specs

on Output Pins

D101

D102

CIO

CB

All I/O pins and OSC2

(in RC mode)

—

50

pF To meet the AC Timing Specifications

pF In I²C mode

SCL, SDA

400

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the

PICmicro device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 331

PIC18FXX8

FIGURE 27-3:

LOW VOLTAGE DETECT CHARACTERISTICS

VDD

(LVDIF can be

cleared in software)

VLVD

(LVDIF set by hardware)

37

LVDIF

TABLE 27-1: LOW VOLTAGE DETECT CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No.

Symbol

Characteristic

Min

Max

Units

Conditions

(Note 1)

D420 VLVD

LVD Voltage

LVDL<3:0> = 0000

—

2.0

2.2

2.4

2.5

2.7

2.8

3.0

3.3

3.5

3.6

3.8

4.0

4.2

4.5

1.17

—

V

LVDL<3:0> = 0001

LVDL<3:0> = 0010

LVDL<3:0> = 0011

LVDL<3:0> = 0100

LVDL<3:0> = 0101

LVDL<3:0> = 0110

LVDL<3:0> = 0111

LVDL<3:0> = 1000

LVDL<3:0> = 1001

LVDL<3:0> = 1010

LVDL<3:0> = 1011

LVDL<3:0> = 1100

LVDL<3:0> = 1101

LVDL<3:0> = 1110

2.12

2.33

2.54

2.66

2.86

2.98

3.2

3.52

3.72

3.84

4.04

4.26

4.46

4.78

1.23

D423

VBGAP

Bandgap Reference Voltage Value

Note 1: This is not a valid setting since the minimum supply voltage is 2.0V.

DS41159B-page 332

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

TABLE 27-2: DC CHARACTERISTICS: EEPROM AND ENHANCED FLASH

DC Characteristics

Standard Operating Conditions

Param

Sym

No.

Characteristic

Min

Typ†

Max Units

Conditions

Data EEPROM Memory

D120

ED

Byte Endurance

100K

10K

1M

100K

—

E/W -40°C to +85°C

E/W +85°C to +125°C

D120A ED

D121

VDRW VDD for Read/Write

VMIN

5.5

V

Using EECON to read/write

VMIN = Minimum operating voltage

D122

D123

TDEW Erase/Write Cycle Time

TRETD Retention

—

2

—

ms

40

—

Years Provided no specifications are

violated

D124

TREF

Number of Total Erase/Write

Cycles to Data EEPROM before

Refresh*

1M

10M

1M

—

Cycles -40°C to +85°C

D124A TREF Number of Total Erase/Write

Cycles to Data EEPROM before

Refresh*

100K

Cycles +85°C to +125°C

Program Flash Memory

D130

EP

Cell Endurance

VDD for Read

10K

1000

VMIN

4.5

100K

10K

—

E/W -40°C to +85°C

E/W +85°C to +125°C

D130A EP

D131

D132

VPR

VIE

5.5

V

VMIN = Minimum operating voltage

Using ICSP port

VDD for ISCP Erase

VDD for ISCP Write

—

D132A VIW

4.5

—

Using ICSP port

D132B VPEW VDD for EECON Erase/Write

VMIN

—

Using EECON to erase/write

VMIN = Minimum operating voltage

D133

TIE

ICSP Erase Cycle Time

—

1

4

—

ms VDD > 4.5V

D133A TIW

ICSP Erase or Write Cycle Time

(externally timed)

—

D133B TPIW

Self-timed Write Cycle Time

—

2

—

ms

D134

†

TRETD Retention

40

—

Years Provided no specifications are

violated

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

*

See Section 5.8 for more information.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 333

PIC18FXX8

TABLE 27-3: COMPARATOR SPECIFICATIONS

Operating Conditions: VDD range as described in Section 27.1, -40°C < TA < +125°C.

Param

No.

Sym

Characteristics

Min

Typ

Max

Units

Comments

D300

VIOFF

Input Offset Voltage

Input Common Mode Voltage

CMRR CMRR

5.0

10

mV

V

D301

D302

VICM

0

VDD – 1.5

+55*

db

D300

TRESP

Response Time⁽¹⁾

TBD*

ns

PIC18FXX8

PIC18LFXX8

D301

TMC2OV Comparator Mode Change to

Output Valid

10*

µs

*

These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from

VSS to VDD.

TABLE 27-4: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: VDD range as described in Section 27.1, -40°C < TA < +125°C.

Param No.

Sym

Characteristics

Resolution

Min

Typ

Max

Units

Comments

D310

D311

D312

D310

VRES

VDD/24

VDD/32

TBD

LSB

Ω

VRAA

VRUR

TSET

Absolute Accuracy

Unit Resistor Value (R)

Settling Time⁽¹⁾

2K*

10*

µs

*

These parameters are characterized but not tested.

Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000to 1111.

DS41159B-page 334

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

27.3 AC (Timing) Characteristics

27.3.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created

following one of the following formats:

1. TppS2ppS

2. TppS

3. TCC:ST

4. Ts

(I²C specifications only)

T

F

Frequency

T

Time

Lowercase letters (pp) and their meanings:

pp

cc

ck

cs

di

CCP1

CLKO

CS

osc

rd

OSC1

RD

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O port

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (Hi-impedance)

Low

Valid

L

Hi-impedance

I²C only

AA

output access

Bus free

High

Low

High

Low

BUF

TCC:ST (I²C specifications only)

CC

HD

ST

Hold

SU

Setup

DAT

STA

DATA input hold

START condition

STO

STOP condition

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 335

PIC18FXX8

27.3.2

TIMING CONDITIONS

The temperature and voltages specified in Table 27-5

apply to all timing specifications, unless otherwise

noted. Figure 27-4 specifies the load conditions for the

timing specifications.

TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for extended

Operating voltage VDD range as described in DC spec Section 27.1.

LC parts operate for industrial temperatures only.

FIGURE 27-4:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 Load Condition 2

VDD/2

CL

RL

VSS

CL

RL = 464Ω

CL = 50 pF for all pins except OSC2/CLKO

and including D and E outputs as ports

VSS

DS41159B-page 336

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

27.3.3

TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 27-5:

EXTERNAL CLOCK TIMING

Q4

Q1

1

Q2

Q3

Q4

4

Q1

OSC1

CLKO

3

4

3

2

TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS

Param No. Symbol

Characteristic

Min

Max

Units

Conditions

1A

FOSC

External CLKI Frequency⁽¹⁾

DC

4

MHz XT osc

25

10

MHz HS osc

MHz HS + PLL osc

DC

200

40

kHz LP osc

MHz EC

Oscillator Frequency⁽¹⁾

DC

0.1

4

MHz RC osc

MHz XT osc

25

10

200

—

MHz HS osc

4

MHz HS + PLL osc

kHz LP osc

5

1

TOSC

External CLKI Period⁽¹⁾

250

40

100

ns XT and RC osc

ns HS osc

ns HS + PLL osc

5

—

µs LP osc

ns EC

Oscillator Period⁽¹⁾

250

—

ns RC osc

ns XT osc

10,000

100

40

10,000

100

ns HS osc

ns HS + PLL osc

5

100

30

2.5

10

—

µs LP osc

ns TCY = 4/FOSC

ns XT osc

ns LP osc

µs HS osc

ns XT osc

ns LP osc

ns HS osc

2

3

TCY

Instruction Cycle Time⁽¹⁾

TosL,

TosH

External Clock in (OSC1)

High or Low Time

—

4

TosR,

TosF

External Clock in (OSC1)

Rise or Fall Time

20

50

7.5

—

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with

the device executing code. Exceeding these specified limits may result in an unstable oscillator operation

and/or higher than expected current consumption. All devices are tested to operate at "Min." values with an

external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "Max." cycle time

limit is "DC" (no clock) for all devices.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 337

PIC18FXX8

TABLE 27-7: PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V)

Param No. Symbol

Characteristic

Min

Max

Units

Conditions

7

TPLL

PLL Start-up Time (Lock Time)

CLKO Stability (Jitter) using PLL

—

2

ms

%

∆^CLK

TBD

FIGURE 27-6:

CLKO AND I/O TIMING

Q1

Q2

Q3

Q4

OSC1

CLKO

11

10

13

14

12

19

18

16

I/O Pin

(Input)

15

17

I/O Pin

(Output)

New Value

Old Value

20, 21

Note: Refer to Figure 27-4 for load conditions.

TABLE 27-8: CLKO AND I/O TIMING REQUIREMENTS

Param

Symbol

Characteristic

Min

Typ

Max

Units Conditions

No.

10

TosH2ckL OSC1↑ to CLKO↓

TosH2ckH OSC1↑ to CLKO↑

—

75

35

—

50

—

10

—

10

—

200

100

ns

(1)

11

12

TckR

TckF

CLKO rise time

CLKO fall time

13

14

TckL2ioV CLKO ↓ to Port out valid

TioV2ckH Port in valid before CLKO↑

TckH2ioI Port in hold after CLKO↑

TosH2ioV OSC1↑ (Q1 cycle) to Port out valid

0.5 TCY + 20 ns

15

0.25 TCY + 25

—

ns

16

0

—

17

150

—

18

TosH2ioI OSC1↑ (Q2 cycle) to Port

PIC18FXX8

100

200

0

input invalid (I/O in hold time)

18A

19

PIC18LFXX8

—

TioV2osH Port input valid to OSC1↑ (I/O in setup time)

—

20

TIOR

Port output rise time

Port output fall time

INT pin high or low time

PIC18FXX8

PIC18LFXX8

PIC18FXX8

PIC18LFXX8

—

25

60

25

60

—

20A

21

—

TIOF

—

21A

22††

23††

24††

—

TINP

TCY

20

TRBP

TRCP

RB7:RB4 change INT high or low time

RC7:RC4 change INT high or low time

—

†† These parameters are asynchronous events, not related to any internal clock edges.

Note 1: Measurements are taken in RC mode where CLKO pin output is 4 x TOSC.

DS41159B-page 338

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 27-7:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

31

34

I/O Pins

Note: Refer to Figure 27-4 for load conditions.

FIGURE 27-8:

BROWN-OUT RESET AND LOW VOLTAGE DETECT TIMING

BVDD (for 35)

VLVD (for 37)

35, 37

VDD

VBGAP = 1.2V

VIRVST

Enable Internal Reference Voltage

Internal Reference Voltage stable

36

TABLE 27-9: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

BROWN-OUT RESET AND LOW VOLTAGE DETECT REQUIREMENTS

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

30

TmcL

TWDT

MCLR Pulse Width (low)

2

7

—

µs

31

Watchdog Timer Time-out Period

(No Prescaler)

18

33

ms

32

33

34

TOST

TPWRT

TIOZ

Oscillation Start-up Timer Period

Power-up Timer Period

1024 TOSC

—

72

2

1024 TOSC

—

ms

µs

TOSC = OSC1 period

28

—

132

—

I/O Hi-impedance from MCLR Low or

Watchdog Timer Reset

35

36

TBOR

Brown-out Reset Pulse Width

200

—

µs

For VDD ≤ BVDD (see D005)

For VDD ≤ VLVD (see D420)

TIVRST

Time for Internal Reference

Voltage to become stable

20

50

37

TLVD

Low Voltage Detect Pulse Width

200

—

µs

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 339

PIC18FXX8

FIGURE 27-9:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

41

40

42

T1OSO/T1CKI

46

45

47

48

TMR0 or

TMR1

Note: Refer to Figure 27-4 for load conditions.

TABLE 27-10: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

Symbol

Characteristic

Min

Max Units Conditions

No.

40

Tt0H

T0CKI High Pulse Width

No prescaler

With prescaler

No prescaler

With prescaler

No prescaler

With prescaler

0.5 TCY + 20

10

—

ns

41

42

Tt0L

Tt0P

T0CKI Low Pulse Width

T0CKI Period

0.5 TCY + 20

10

TCY + 10

Greater of:

20 ns or TCY + 40

N

ns N = prescale

value

(1, 2, 4,..., 256)

45

46

Tt1H

Tt1L

T1CKI

High Time

Synchronous, no prescaler

0.5 TCY + 20

—

ns

Synchronous, PIC18FXX8

10

with prescaler

PIC18LFXX8

25

—

Asynchronous PIC18FXX8

PIC18LFXX8

30

—

50

0.5 TCY + 5

10

—

T1CKI

Low Time

Synchronous, no prescaler

Synchronous, PIC18FXX8

—

with prescaler

PIC18LFXX8

25

—

Asynchronous PIC18FXX8

PIC18LFXX8

30

—

TBD

—

47

48

Tt1P

Ft1

T1CKI

Input Period

Synchronous

Greater of:

20 ns or TCY + 40

N

ns N = prescale

value

(1, 2, 4, 8)

Asynchronous

60

DC

—

50

ns

kHz

—

T1CKI Oscillator Input Frequency Range

Tcke2tmrI Delay from External T1CKI Clock Edge to

Timer Increment

2 TOSC

7 TOSC

DS41159B-page 340

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 27-10:

CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND ECCP1)

CCPx

(Capture Mode)

50

51

52

54

CCPx

(Compare or PWM Mode)

53

Note: Refer to Figure 27-4 for load conditions.

TABLE 27-11: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND ECCP1)

Param

Symbol

Characteristic

Min

Max

Units

Conditions

No.

50

TccL

CCPx input low No Prescaler

time

0.5 TCY + 20

—

ns

With

PIC18FXX8

PIC18LFXX8

10

Prescaler

20

51

TccH

CCPx input

high time

No Prescaler

0.5 TCY + 20

With

PIC18FXX8

10

20

Prescaler

PIC18LFXX8

52

53

TccP

TccR

CCPx input period

3 TCY + 40

N

N = prescale

value (1,4 or 16)

CCPx output fall time

PIC18FXX8

PIC18LFXX8

PIC18FXX8

PIC18LFXX8

—

25

45

25

45

ns

54

TccF

CCPx output fall time

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 341

PIC18FXX8

FIGURE 27-11:

PARALLEL SLAVE PORT TIMING (PIC18F248 AND PIC18F458)

RE2/CS

RE0/RD

RE1/WR

65

RD7:RD0

62

64

63

Note: Refer to Figure 27-4 for load conditions.

TABLE 27-12: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F248 AND PIC18F458)

Param

Symbol

Characteristic

Min

Max Units

Conditions

No.

62

TdtV2wrH Data-in valid before WR↑ or CS↑

20

25

—

ns

(setup time)

ns Extended Temp. range

63

64

TwrH2dtI

WR↑ or CS↑ to data-in invalid PIC18FXX8

(hold time)

20

35

—

ns

PIC18LFXX8

TrdL2dtV RD↓ and CS↓ to data-out valid

—

80

90

ns

ns Extended Temp. range

65

66

TrdH2dtI

TibfINH

RD↑ or CS↓ to data-out invalid

Inhibit the IBF flag bit being cleared from

10

—

30

ns

3 TCY

WR↑ or CS↑

DS41159B-page 342

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 27-12:

EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

SS

70

SCK

(CKP = 0)

71

72

78

79

SCK

(CKP = 1)

78

80

MSb

Bit6 - - - - - -1

Bit6 - - - -1

LSb

SDO

SDI

75, 76

MSb In

74

LSb In

73

Note: Refer to Figure 27-4 for load conditions.

TABLE 27-13: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param

Symbol

Characteristic

Min

Max Units Conditions

No.

70

TssL2scH, SS↓ to SCK↓ or SCK↑ input

TssL2scL

TCY

—

ns

71

TscH

SCK input high time

(Slave mode)

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

71A

72

40

1.25 TCY + 30

40

ns (Note 1)

TscL

SCK input low time

(Slave mode)

ns

72A

73

ns (Note 1)

TdiV2scH, Setup time of SDI data input to SCK edge

TdiV2scL

100

ns

73A

74

TB2B

Last clock edge of Byte1 to the 1st clock edge of 1.5 TCY + 40

Byte2

—

ns (Note 2)

TscH2diL, Hold time of SDI data input to SCK edge

TscL2diL

100

ns

75

TdoR

SDO data output rise time

PIC18FXX8

—

25

45

25

45

25

50

100

ns

PIC18LFXX8

76

78

TdoF

TscR

SDO data output fall time

SCK output rise time

(Master mode)

PIC18FXX8

PIC18LFXX8

79

80

TscF

SCK output fall time (Master mode)

TscH2doV, SDO data output valid after

TscL2doV SCK edge

PIC18FXX8

PIC18LFXX8

Note 1: Requires the use of parameter # 73A.

2: Only if parameter #’s 71A and 72A are used.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 343

PIC18FXX8

FIGURE 27-13:

EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

SS

81

SCK

(CKP = 0)

71

72

79

78

73

SCK

(CKP = 1)

80

LSb

MSb

Bit6 - - - - - -1

Bit6 - - - -1

SDO

SDI

75, 76

MSb In

74

LSb In

Note: Refer to Figure 27-4 for load conditions.

TABLE 27-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Param

Symbol

Characteristic

Min

Max Units Conditions

No.

71

TscH

SCK input high time

(Slave mode)

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

71A

72

40

1.25 TCY + 30

40

ns (Note 1)

TscL

SCK input low time

(Slave mode)

ns

72A

73

ns (Note 1)

TdiV2scH, Setup time of SDI data input to SCK edge

TdiV2scL

100

ns

73A

74

TB2B

Last clock edge of Byte1 to the 1st clock edge of 1.5 TCY + 40

Byte2

—

ns (Note 2)

TscH2diL, Hold time of SDI data input to SCK edge

TscL2diL

100

ns

75

TdoR

SDO data output rise time

PIC18FXX8

—

25

45

25

45

25

50

100

—

ns

PIC18LFXX8

76

78

TdoF

TscR

SDO data output fall time

—

SCK output rise time

(Master mode)

PIC18FXX8

—

PIC18LFXX8

—

79

80

TscF

SCK output fall time (Master mode)

—

TscH2doV, SDO data output valid after

TscL2doV SCK edge

PIC18FXX8

—

PIC18LFXX8

—

81

TdoV2scH, SDO data output setup to SCK edge

TdoV2scL

TCY

Note 1: Requires the use of parameter # 73A.

2: Only if parameter #’s 71A and 72A are used.

DS41159B-page 344

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 27-14:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

SS

70

SCK

(CKP = 0)

83

71

72

78

79

SCK

(CKP = 1)

79

78

80

SDO

SDI

MSb

LSb

Bit6 - - - - - -1

Bit6 - - - -1

77

75, 76

MSb In

74

LSb In

73

Note: Refer to Figure 27-4 for load conditions.

TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS, SLAVE MODE TIMING (CKE = 0)

Param

Symbol

Characteristic

Min

Max Units Conditions

No.

70

TssL2scH, SS↓ to SCK↓ or SCK↑ input

TssL2scL

TCY

—

ns

71

TscH

SCK input high time (Slave mode) Continuous

1.25 TCY + 30

—

ns

71A

72

Single Byte

Continuous

Single Byte

40

1.25 TCY + 30

40

ns (Note 1)

TscL

SCK input low time (Slave mode)

ns

72A

73

ns (Note 1)

TdiV2scH, Setup time of SDI data input to SCK edge

TdiV2scL

100

ns

73A

74

TB2B

Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40

—

ns (Note 2)

TscH2diL, Hold time of SDI data input to SCK edge

TscL2diL

100

ns

75

TdoR

SDO data output rise time

PIC18FXX8

—

25

45

25

50

25

45

25

50

100

—

ns

PIC18LFXX8

76

77

78

TdoF

SDO data output fall time

—

10

—

TssH2doZ SS↑ to SDO output hi-impedance

TscR

SCK output rise time (Master mode) PIC18FXX8

PIC18LFXX8

79

80

TscF

SCK output fall time (Master mode)

—

TscH2doV, SDO data output valid after SCK

TscL2doV edge

PIC18FXX8

PIC18LFXX8

83

TscH2ssH, SS ↑ after SCK edge

TscL2ssH

1.5 TCY + 40

Note 1: Requires the use of parameter # 73A.

2: Only if parameter #’s 71A and 72A are used.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 345

PIC18FXX8

FIGURE 27-15:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

82

SS

70

SCK

83

(CKP = 0)

71

72

SCK

(CKP = 1)

80

MSb

Bit6 - - - - - -1

Bit6 - - - -1

LSb

SDO

SDI

75, 76

77

MSb In

74

LSb In

Note: Refer to Figure 27-4 for load conditions.

TABLE 27-16: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param

Symbol

Characteristic

Min

Max Units Conditions

No.

70

TssL2scH, SS↓ to SCK↓ or SCK↑ input

TssL2scL

TCY

—

ns

71

TscH

TscL

TB2B

SCK input high time

(Slave mode)

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

71A

72

40

1.25 TCY + 30

40

ns (Note 1)

ns

SCK input low time

(Slave mode)

72A

73A

74

ns (Note 1)

ns (Note 2)

ns

Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40

TscH2diL, Hold time of SDI data input to SCK edge

TscL2diL

100

75

TdoR

SDO data output rise time

PIC18FXX8

—

25

45

25

ns

PIC18LFXX8

76

TdoF

SDO data output fall time

77

78

TssH2doZ SS↑ to SDO output hi-impedance

10

—

50

25

ns

TscR

SCK output rise time

(Master mode)

PIC18FXX8

PIC18LFXX8

45

79

80

TscF

SCK output fall time (Master mode)

25

TscH2doV, SDO data output valid after SCK

TscL2doV edge

PIC18FXX8

50

PIC18LFXX8

100

82

83

TssL2doV SDO data output valid after SS↓

PIC18FXX8

—

50

100

—

ns

edge

PIC18LFXX8

TscH2ssH, SS ↑ after SCK edge

TscL2ssH

1.5 TCY + 40

Note 1: Requires the use of parameter # 73A.

2: Only if parameter #’s 71A and 72A are used.

DS41159B-page 346

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 27-16:

I²C BUS START/STOP BITS TIMING

SCL

SDA

91

93

90

92

STOP

Condition

START

Condition

Note: Refer to Figure 27-4 for load conditions.

TABLE 27-17: I²C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

Param

Symbol

Characteristic

Min

Max

Units

Conditions

No.

90

TSU:STA START condition

Setup time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4700

600

—

ns

Only relevant for Repeated

START condition

91

92

93

THD:STA START condition

Hold time

4000

600

ns

After this period, the first

clock pulse is generated

TSU:STO STOP condition

Setup time

4700

600

THD:STO STOP condition

Hold time

4000

600

FIGURE 27-17:

I²C BUS DATA TIMING

103

102

100

101

SCL

90

106

107

91

92

SDA

In

110

109

SDA

Out

Note: Refer to Figure 27-4 for load conditions.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 347

PIC18FXX8

TABLE 27-18: I²C BUS DATA REQUIREMENTS (SLAVE MODE)

Param

Symbol

Characteristic

100 kHz mode

Min

Max Units

Conditions

No.

100

THIGH

Clock high time

4.0

—

µs

PIC18FXX8 must operate

at a minimum of 1.5 MHz

400 kHz mode

0.6

PIC18FXX8 must operate

at a minimum of 10 MHz

SSP Module

1.5 TCY

4.7

—

101

TLOW

Clock low time

100 kHz mode

µs

PIC18FXX8 must operate

at a minimum of 1.5 MHz

400 kHz mode

1.3

—

PIC18FXX8 must operate

at a minimum of 10 MHz

SSP module

1.5 TCY

—

ns

102

103

TR

TF

SDA and SCL rise 100 kHz mode

1000

time

400 kHz mode

20 + 0.1 CB 300

CB is specified to be from

10 to 400 pF

SDA and SCL fall 100 kHz mode

—

300

ns

time

400 kHz mode

20 + 0.1 CB 300

CB is specified to be from

10 to 400 pF

90

TSU:STA

THD:STA

START condition

setup time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4.7

0.6

4.0

0.6

0

—

µs

ns

µs

ns

µs

ns

µs

Only relevant for Repeated

START condition

91

START condition

hold time

—

After this period the first

clock pulse is generated

—

106

107

92

THD:DAT Data input hold

time

—

0

0.9

—

TSU:DAT

TSU:STO

TAA

Data input setup

time

250

100

4.7

0.6

—

(Note 2)

—

STOP condition

setup time

—

109

110

Output valid from

clock

3500

—

(Note 1)

—

TBUF

Bus free time

4.7

1.3

—

Time the bus must be free

before a new transmission

can start

—

D102

CB

Bus capacitive loading

—

400

pF

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but the requirement

TSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line.

Before the SCL line is released, TR max. + TSU;DAT = 1000 + 250 = 1250 ns (according to the Standard

mode I²C bus specification).

DS41159B-page 348

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 27-18:

MASTER SSP I²C BUS START/STOP BITS TIMING WAVEFORMS

SCL

SDA

93

91

90

92

STOP

Condition

START

Condition

Note: Refer to Figure 27-4 for load conditions.

TABLE 27-19: MASTER SSP I²C BUS START/STOP BITS REQUIREMENTS

Param

Symbol

Characteristic

Min

Max Units

Conditions

No.

90

TSU:STA START condition

Setup time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

2(TOSC)(BRG + 1)

—

ns Only relevant for

Repeated START

condition

91

92

93

THD:STA START condition

Hold time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

2(TOSC)(BRG + 1)

ns After this period, the

first clock pulse is

generated

TSU:STO STOP condition

Setup time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

2(TOSC)(BRG + 1)

ns

THD:STO STOP condition

Hold time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

2(TOSC)(BRG + 1)

ns

Note 1: Maximum pin capacitance = 10 pF for all I²C pins.

FIGURE 27-19:

MASTER SSP I²C BUS DATA TIMING

103

102

100

101

SCL

90

106

91

92

107

SDA

In

110

109

SDA

Out

Note: Refer to Figure 27-4 for load conditions.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 349

PIC18FXX8

TABLE 27-20: MASTER SSP I²C BUS DATA REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max Units

Conditions

No.

100

THIGH

Clock high time 100 kHz mode

400 kHz mode

2(TOSC)(BRG + 1)

—

ms

ns

2(TOSC)(BRG + 1)

1 MHz mode⁽¹⁾

2(TOSC)(BRG + 1)

—

101

102

103

90

TLOW

TR

Clock low time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

2(TOSC)(BRG + 1)

—

2(TOSC)(BRG + 1)

—

2(TOSC)(BRG + 1)

—

SDA and SCL

rise time

—

1000

300

100

—

CB is specified to be from

10 to 400 pF

20 + 0.1 CB

ns

—

ns

TF

SDA and SCL

fall time

—

ns

CB is specified to be from

10 to 400 pF

20 + 0.1 CB

ns

—

ns

TSU:STA

THD:STA

START condition 100 kHz mode

2(TOSC)(BRG + 1)

ms

Only relevant for

Repeated START

condition

setup time

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode⁽¹⁾

2(TOSC)(BRG + 1)

—

91

START condition 100 kHz mode

2(TOSC)(BRG + 1)

—

ms After this period, the first

hold time

clock pulse is generated

400 kHz mode

2(TOSC)(BRG + 1)

—

ms

1 MHz mode⁽¹⁾

2(TOSC)(BRG + 1)

—

ms

ns

106

107

92

THD:DAT Data input

hold time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

0

—

0

0.9

—

ms

ns

TBD

TSU:DAT

TSU:STO

TAA

Data input

setup time

250

—

ns

ms

ns

(Note 2)

100

—

TBD

—

STOP condition 100 kHz mode

2(TOSC)(BRG + 1)

—

setup time

400 kHz mode

1 MHz mode⁽¹⁾

2(TOSC)(BRG + 1)

—

2(TOSC)(BRG + 1)

—

109

110

Output valid from 100 kHz mode

—

3500

1000

—

clock

400 kHz mode

1 MHz mode⁽¹⁾

—

TBUF

Bus free time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

4.7

1.3

TBD

—

ms Time the bus must be free

before a new transmission

can start

ms

—

ms

—

D102 CB

Bus capacitive loading

400

pF

Note 1: Maximum pin capacitance = 10 pF for all I²C pins.

2: A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but parameter #107 ≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL

signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the

SDA line. Before the SCL line is released, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for

100 kHz mode).

DS41159B-page 350

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 27-20:

USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

RC6/TX/CK

121

RC7/RX/DT

120

Note: Refer to Figure 27-4 for load conditions.

122

TABLE 27-21: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param

Symbol

Characteristic

Min

Max

Units Conditions

No.

120

TckH2dtV SYNC XMIT (Master & Slave)

Clock high to data-out valid

PIC18FXX8

PIC18LFXX8

PIC18FXX8

PIC18LFXX8

PIC18FXX8

PIC18LFXX8

—

40

100

20

ns

121

122

Tckrf

Tdtrf

Clock out rise time and fall time

(Master mode)

50

Data-out rise time and fall time

20

50

FIGURE 27-21:

USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

RC6/TX/CK

125

RC7/RX/DT

126

Note: Refer to Figure 27-4 for load conditions.

TABLE 27-22: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Param

Symbol

Characteristic

Min

Max

Units

Conditions

No.

125

TdtV2ckl SYNC RCV (Master & Slave)

Data-hold before CK ↓ (DT hold time)

10

15

—

ns

126

TckL2dtl

Data-hold after CK ↓ (DT hold time)

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 351

PIC18FXX8

TABLE 27-23: A/D CONVERTER CHARACTERISTICS: PIC18FXX8 (INDUSTRIAL, EXTENDED)

PIC18LFXX8 (INDUSTRIAL)

Param

No.

Symbol

Characteristic

Resolution

Min

Typ

Max

Units

Conditions

A01

NR

—

10

TBD

bit VREF = VDD ≥ 3.0V

bit VREF = VDD < 3.0V

A03

A04

A05

A06

EIL

Integral linearity error

Differential linearity error

Full scale error

—

<±1

TBD

LSb VREF = VDD ≥ 3.0V

LSb VREF = VDD < 3.0V

EDL

EFS

EOFF

—

<±1

TBD

LSb VREF = VDD ≥ 3.0V

LSb VREF = VDD < 3.0V

—

<±1

TBD

LSb VREF = VDD ≥ 3.0V

LSb VREF = VDD < 3.0V

Offset error

—

<±1.5

TBD

LSb VREF = VDD ≥ 3.0V

LSb VREF = VDD < 3.0V

A10

A20

A20A

A21

A22

A25

A30

—

Monotonicity

guaranteed⁽³⁾

—

V

VSS ≤ VAIN ≤ VREF

VREF

Reference voltage

(VREFH – VREFL)

0V

3V

—

V

For 10-bit resolution

VREFH

VREFL

VAIN

Reference voltage High

Reference voltage Low

Analog input voltage

VSS

—

VDD + 0.3V

VDD

V

VSS - 0.3V

—

V

VREF + 0.3V

10.0

V

ZAIN

Recommended impedance of

analog voltage source

kΩ

A40

A50

IAD

A/D conversion PIC18FXX8

—

180

90

—

µA Average current

current (VDD)

consumption when

PIC18LFXX8

µA

A/D is on (Note 1).

IREF

VREF input current (Note 2)

10

—

1000

µA During VAIN acquisition.

Based on differential of

VHOLD to VAIN. To charge

CHOLD.

—

10

µA During A/D conversion

cycle.

Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current

spec includes any such leakage from the A/D module.

VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or VDD and VSS pins, whichever is selected

as reference input.

2: VSS ≤ VAIN ≤ VREF

3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes.

DS41159B-page 352

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

FIGURE 27-22:

A/D CONVERSION TIMING

BSF ADCON0, GO

(Note 2)

131

130

Q4

132

A/D CLK

. . .

9

8

7

2

1

0

A/D DATA

ADRES

NEW_DATA

TCY

OLD_DATA

ADIF

GO

DONE

SAMPLING STOPPED

SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEPinstruction to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

TABLE 27-24: A/D CONVERSION REQUIREMENTS

Param

Symbol

Characteristic

Min

Max

Units

Conditions

No.

130

TAD

A/D clock period

PIC18FXX8

1.6

20⁽⁵⁾

µs TOSC based, VREF ≥ 3.0V

PIC18LFXX8

PIC18FXX8

PIC18LFXX8

3.0

2.0

3.0

11

20⁽⁵⁾

6.0

9.0

12

µs TOSC based, VREF full range

µs A/D RC mode

TAD

131

132

TCNV

TACQ

Conversion time

(not including acquisition time) (Note 1)

Acquisition time (Note 3)

15

10

—

µs -40°C ≤ Temp ≤ +125°C

µs 0°C ≤ Temp ≤ +125°C

135

136

TSWC

TAMP

Switching time from convert → sample

Amplifier settling time (Note 2)

—

1

(Note 4)

—

µs This may be used if the

“new” input voltage has not

changed by more than 1 LSb

(i.e., 5 mV @ 5.12V) from the

last sampled voltage (as

stated on CHOLD).

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 20.0 for minimum conditions when input voltage has changed more than 1 LSb.

3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale

after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels

is 50Ω.

4: On the next Q4 cycle of the device clock.

5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 353

PIC18FXX8

NOTES:

DS41159B-page 354

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

28.0 DC AND AC

CHARACTERISTICS GRAPHS

AND TABLES

Graphs and Tables are not available at this time.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 355

PIC18FXX8

NOTES:

DS41159B-page 356

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

29.0 PACKAGING INFORMATION

29.1 Package Marking Information

28-Lead PDIP (Skinny DIP)

Example

XXXXXXXXXXXXXXXXX

PIC18F258-I/SP

YYWWNNN

0220017

40-Lead PDIP

Example

XXXXXXXXXXXXXXXXXX

YYWWNNN

PIC18F448-I/P

0220017

Example

28-Lead SOIC

XXXXXXXXXXXXXXXXX

PIC18F248-E/SO

0220017

YYWWNNN

Legend: XX...X Customer specific information*

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line thus limiting the number of available characters

for customer specific information.

*

Standard PICmicro device marking consists of Microchip part number, year code, week code, and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 357

PIC18FXX8

29.1 Package Marking Information (Continued)

44-Lead PLCC

Example

XXXXXXXXXX

PIC18F458

-I/L

XXXXXXXXXX

YYWWNNN

0220017

44-Lead TQFP

Example

XXXXXXXXXX

YYWWNNN

PIC18F448

-I/PT

0220017

DS41159B-page 358

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

29.2 Package Details

The following sections give the technical details of the

packages.

28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)

E1

D

2

n

1

α

E

A2

A

L

c

B1

β

A1

eB

B

p

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

28

.100

.150

.130

2.54

3.81

3.30

Top to Seating Plane

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A

A2

A1

E

.140

.160

3.56

4.06

.125

.015

.300

.275

1.345

.125

.008

.040

.016

.320

.135

3.18

0.38

7.62

6.99

34.16

3.18

0.20

1.02

0.41

8.13

5

3.43

.310

.285

1.365

.130

.012

.053

.019

.350

10

.325

.295

1.385

.135

.015

.065

.022

.430

15

7.87

7.24

34.67

3.30

0.29

1.33

0.48

8.89

10

8.26

7.49

35.18

3.43

0.38

1.65

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

5

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-095

Drawing No. C04-070

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 359

PIC18FXX8

40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)

E1

D

2

α

n

1

E

A2

A

L

c

B1

B

β

A1

p

eB

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

40

MAX

n

p

Number of Pins

Pitch

40

.100

.175

.150

2.54

Top to Seating Plane

A

.160

.190

.160

4.06

3.56

4.45

3.81

4.83

4.06

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.140

.015

.595

.530

2.045

.120

.008

.030

.014

.620

5

0.38

15.11

13.46

51.94

3.05

0.20

0.76

0.36

15.75

5

.600

.545

2.058

.130

.012

.050

.018

.650

10

.625

.560

2.065

.135

.015

.070

.022

.680

15

15.24

13.84

52.26

3.30

0.29

1.27

0.46

16.51

10

15.88

14.22

52.45

3.43

0.38

1.78

0.56

17.27

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

§

eB

α

β

Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

5

10

15

5

10

15

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-011

Drawing No. C04-016

DS41159B-page 360

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)

E

E1

p

D

B

2

n

1

h

α

45°

c

A2

A

φ

β

L

A1

Units

INCHES*

NOM

MILLIMETERS

NOM

Dimension Limits

MIN

MAX

MIN

MAX

n

p

Number of Pins

Pitch

28

1.27

2.50

2.31

0.20

10.34

7.49

17.87

0.50

0.84

4

.050

.099

.091

.008

.407

.295

.704

.020

.033

4

Overall Height

A

.093

.104

2.36

2.64

Molded Package Thickness

Standoff

A2

A1

E

.088

.004

.394

.288

.695

.010

.016

0

.094

.012

.420

.299

.712

.029

.050

8

2.24

0.10

10.01

7.32

17.65

0.25

0.41

0

2.39

0.30

10.67

7.59

18.08

0.74

1.27

8

§

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle Top

c

Lead Thickness

Lead Width

.009

.014

0

.011

.017

12

.013

.020

15

0.23

0.36

0

0.28

0.42

12

0.33

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-052

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 361

PIC18FXX8

44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)

E

E1

#leads=n1

D

D1

n 1 2

CH2 x 45°

CH1 x 45°

α

A3

A2

A

35°

B1

B

c

A1

β

p

E2

D2

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

44

MAX

n

p

Number of Pins

Pitch

44

.050

11

1.27

11

Pins per Side

Overall Height

n1

A

.165

.145

.020

.024

.040

.000

.685

.650

.590

.008

.026

.013

0

.173

.153

.028

.029

.045

.005

.690

.653

.620

.011

.029

.020

5

.180

4.19

3.68

0.51

0.61

1.02

0.00

17.40

16.51

14.99

0.20

0.66

0.33

0

4.39

3.87

0.71

0.74

1.14

0.13

17.53

16.59

15.75

0.27

0.74

0.51

5

4.57

Molded Package Thickness

Standoff

A2

A1

A3

CH1

CH2

E

.160

.035

.034

.050

.010

.695

.656

.630

.013

.032

.021

10

4.06

0.89

0.86

1.27

0.25

17.65

16.66

16.00

0.33

0.81

0.53

10

§

Side 1 Chamfer Height

Corner Chamfer 1

Corner Chamfer (others)

Overall Width

Overall Length

D

Molded Package Width

Molded Package Length

Footprint Width

E1

D1

E2

D2

c

Footprint Length

Lead Thickness

Upper Lead Width

Lower Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

B1

B

α

β

0

5

10

0

5

10

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-047

Drawing No. C04-048

DS41159B-page 362

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D1

D

2

1

B

n

°

CH x 45

α

A

c

φ

β

A1

A2

L

(F)

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

44

MAX

n

p

Number of Pins

Pitch

44

.031

11

0.80

11

Pins per Side

Overall Height

n1

A

.039

.037

.002

.018

.043

.039

.004

.024

.039

3.5

.047

1.00

0.95

1.10

1.00

0.10

0.60

1.20

Molded Package Thickness

Standoff

A2

A1

L

(F)

φ

.041

.006

.030

1.05

0.15

0.75

§

0.05

0.45

1.00

0

Foot Length

Footprint (Reference)

Foot Angle

0

.463

.390

.004

.012

.025

5

7

.482

.398

.008

.017

.045

15

3.5

12.00

10.00

0.15

0.38

0.89

10

7

12.25

10.10

0.20

0.44

1.14

15

Overall Width

E

D

.472

.394

.006

.015

.035

10

11.75

9.90

0.09

0.30

0.64

5

Overall Length

Molded Package Width

Molded Package Length

Lead Thickness

E1

D1

c

Lead Width

B

CH

α

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-076

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 363

PIC18FXX8

NOTES:

DS41159B-page 364

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

APPENDIX A: DATA SHEET

REVISION HISTORY

APPENDIX B: DEVICE

DIFFERENCES

The differences between the devices listed in this data

sheet are shown in Table B-1.

Revision A (June 2001)

Original data sheet for the PIC18FXX8 family.

Revision B (May 2002)

Updated information on CAN module, device memory

and register maps, I/O ports and Enhanced CCP.

TABLE B-1:

DEVICE DIFFERENCES

Features

PIC18F248

PIC18F258

PIC18F448

PIC18F458

Internal

Program

Memory

Bytes

16K

32K

16K

32K

# of Single word

Instructions

8192

16384

8192

16384

Data Memory (Bytes)

I/O Ports

768

Ports A, B, C

—

1536

Ports A, B, C

—

768

1536

Ports A, B, C, D, E Ports A, B, C, D, E

Enhanced Capture/Compare/PWM

Modules

1

Parallel Slave Port

No

Yes

10-bit Analog-to-Digital Converter

Analog Comparators

5 input channels 5 input channels 8 input channels 8 input channels

No

2

Analog Comparators VREF Output

Packages

N/A

Yes

28-pin SPDIP

28-pin SOIC

28-pin SPDIP

28-pin SOIC

40-pin PDIP

44-pin PLCC

44-pin TQFP

40-pin PDIP

44-pin PLCC

44-pin TQFP

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 365

PIC18FXX8

APPENDIX C: DEVICE MIGRATIONS

APPENDIX D: MIGRATING FROM

OTHER PICmicro

This section is intended to describe the functional and

electrical specification differences when migrating

between functionally similar devices (such as from a

PIC16C74A to a PIC16C74B).

DEVICES

This discusses some of the issues in migrating from

other PICmicro devices to the PIC18FXX8 family of

devices.

Not Applicable

D.1

PIC16CXXX to PIC18FXX8

See Application Note AN716.

D.2

PIC17CXXX to PIC18FXX8

See Application Note AN726.

DS41159B-page 366

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

APPENDIX E: DEVELOPMENT

TOOL VERSION

REQUIREMENTS

This lists the minimum requirements (software/

firmware) of the specified development tool to support

the devices listed in this data sheet.

MPLAB^®SIMULATOR:

MPLAB^®ICE 2000:

MPLAB IDE

V7.40 (MPLAB IDE V5.40)

TBD

PIC18FXX8 Processor Module:

Part Number

PCM 18XD0

PIC18FXX8 Device Adapter:

Socket

Part Number

28-pin PDIP

28-pin SOIC

DVA16XP282

DVA16XP282 with

XLT 28SO Transition

Socket

40-pin PDIP

44-pin TQFP

DVA16XP401

DVA16PQ441 with

XLT 44PT Transition

Socket

44-pin PLCC

DVA16XL441

MPLAB^®ICD 2:

PRO MATE^®II:

TBD

Device Programmer

PICSTART^®Plus:

version TBD

Development Programmer

MPASM^TMAssembler:

V2.80

(MPLAB IDE V5.40)

MPLAB^®C18 C Compiler: version TBD

CAN-TOOL:

Not available at time of

printing.

Third Party Tools:

OSEK/VDX

operating

system available from

Vector Infromatik GmbH,

Germany and Realogy

Ltd, UK.

Note: Please read all associated README.TXT

files that are supplied with the develop-

ment tools. These "read me" files will dis-

cuss product support and any known

limitations.

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 367

PIC18FXX8

NOTES:

DS41159B-page 368

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

INDEX

Block Diagrams

A

A/D ........................................................................... 239

Analog Input Model ...........................................240, 249

Baud Rate Generator .............................................. 167

CAN Buffers and Protocol Engine ........................... 198

Capture Mode (CCP Module) .................................. 123

Comparator I/O Operating Modes ........................... 246

Comparator Output .................................................. 248

Compare (CCP Module) Mode Operation ............... 124

Enhanced PWM ....................................................... 132

Interrupt Logic ............................................................ 78

Low Voltage Detect ................................................. 256

Low Voltage Detect with External Input ................... 256

A/D ................................................................................... 237

A/D Converter Flag (ADIF bit) .................................. 239

A/D Converter Interrupt, Configuring ....................... 240

Acquisition Requirements ........................................ 240

Acquisition Time ....................................................... 241

ADCON0 Register .................................................... 237

ADCON1 Register .................................................... 237

ADRESH Register .................................................... 237

ADRESH/ADRESL Registers .................................. 239

ADRESL Register .................................................... 237

Analog Port Pins, Configuring .................................. 242

Associated Registers Summary ............................... 243

Calculating the Minimum Required

2

MSSP (I C Master Mode) ........................................ 165

2

MSSP (I C Mode) .................................................... 150

Acquisition Time ............................................... 241

Configuring the Module ............................................ 240

Conversion Clock (TAD) ........................................... 242

Conversion Status (GO/DONE bit) .......................... 239

Conversion TAD Cycles ............................................ 243

Conversions ............................................................. 243

Converter Characteristics ........................................ 352

Minimum Charging Time .......................................... 241

Selecting the Conversion Clock ............................... 242

Special Event Trigger (CCP) .................................... 124

Special Event Trigger (ECCP) ......................... 131, 243

TAD vs. Device Operating Frequencies

MSSP (SPI Mode) ................................................... 141

On-Chip Reset Circuit ................................................ 25

PIC18F248/258 Architecture ....................................... 8

PIC18F448/458 Architecture ....................................... 9

PLL ............................................................................ 19

PORTC (Peripheral Output Override) ........................ 98

PORTD and PORTE (Parallel Slave Port) ............... 105

PORTD in I/O Port Mode ......................................... 100

PORTE .................................................................... 102

PWM (CCP Module) ................................................ 126

RA3:RA0 and RA5 Port Pins ..................................... 93

RA4/T0CKI Pin .......................................................... 93

RA6/OSC2/CLKO Pin ................................................ 94

RB1:RB0 Port Pins .................................................... 95

RB2:CANTX Port Pins ............................................... 96

RB3:CANRX Port Pins ............................................... 96

RB7:RB4 Port Pins .................................................... 95

Reads from FLASH Program Memory ....................... 69

Receive Buffer ......................................................... 226

Table Read Operation ............................................... 65

Table Write Operation ................................................ 66

Table Writes to FLASH Program Memory ................. 71

Timer0 Module

(For Extended, LC Devices) (table) ................. 242

TAD vs. Device Operating Frequencies (table) ........ 242

Use of the ECCP Trigger ......................................... 243

Absolute Maximum Ratings ............................................. 325

AC (Timing) Characteristics ............................................. 335

Parameter Symbology ............................................. 335

Access Bank ...................................................................... 54

ACKSTAT ......................................................................... 171

ADCON0 Register ............................................................ 237

GO/DONE bit ........................................................... 239

ADCON1 Register ............................................................ 237

ADDLW ............................................................................ 283

Addressable Universal Synchronous Asynchronous

Receiver Transmitter. See USART

ADDWF ............................................................................ 283

ADDWFC ......................................................................... 284

ADRESH Register ............................................................ 237

ADRESH/ADRESL Registers ........................................... 239

ADRESL Register ............................................................ 237

Analog-to-Digital Converter. See A/D

16-bit Mode ...................................................... 108

8-bit Mode ........................................................ 108

Timer1 Module ......................................................... 112

Timer1 Module (16-bit Read/Write Mode) ............... 112

Timer2 ..................................................................... 116

Timer3 ..................................................................... 118

Timer3 (16-bit Read/Write Mode) ............................ 118

Transmit Buffer ........................................................ 223

USART Receive ....................................................... 189

USART Transmit ...................................................... 187

Voltage Reference ................................................... 252

Watchdog Timer ...................................................... 269

BN .................................................................................... 286

BNC ................................................................................. 287

BNN ................................................................................. 287

BNOV ............................................................................... 288

BNZ .................................................................................. 288

BOR. See Brown-out Reset

ANDLW ............................................................................ 284

ANDWF ............................................................................ 285

Assembler

MPASM Assembler .................................................. 319

Associated Registers ............................................... 190, 195

B

Bank Select Register (BSR) ............................................... 54

Baud Rate Generator ....................................................... 167

BC .................................................................................... 285

BCF .................................................................................. 286

BF ..................................................................................... 171

Bit Timing Configuration Registers

BOV ................................................................................. 291

BRA ................................................................................. 289

BRGCON1 ............................................................... 232

BRGCON2 ............................................................... 232

BRGCON3 ............................................................... 232

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 369

PIC18FXX8

BRG. See Baud Rate Generator

Programming Time Segments ................................. 232

Propagation Segment .............................................. 230

Receive Buffer Registers ......................................... 208

Receive Buffers ....................................................... 226

Receive Message Buffering ..................................... 226

Receive Priority ........................................................ 226

Registers .................................................................. 199

Resynchronization ................................................... 231

Sample Point ........................................................... 230

Shortening a bit Period ............................................ 232

Stuff Bit Error ........................................................... 233

Synchronization ....................................................... 231

Synchronization Rules ............................................. 231

Synchronization Segment ........................................ 230

Time Quanta ............................................................ 230

Transmit Buffer Registers ........................................ 204

Transmit Buffers ...................................................... 223

Transmit Message Flow Chart ................................. 225

Transmit Priority ....................................................... 223

Transmit/Receive Buffers ........................................ 197

Values for ICODE (table) ......................................... 235

Capture (CCP Module) .................................................... 122

CAN Message Time-Stamp ..................................... 123

CCP Pin Configuration ............................................. 122

CCPR1H:CCPR1L Registers ................................... 122

Software Interrupt .................................................... 123

Timer1/Timer3 Mode Selection ................................ 122

Capture (ECCP Module) .................................................. 131

CAN Message Time-Stamp ..................................... 131

Capture/Compare/PWM (CCP) ........................................ 121

Capture Mode. See Capture (CCP Module)

Brown-out Reset (BOR) ............................................. 26, 261

BSF ..................................................................................289

BTFSC .............................................................................290

BTFSS ..............................................................................290

BTG ..................................................................................291

BZ .....................................................................................292

C

CALL ................................................................................292

CAN Module .....................................................................197

Aborting Transmission .............................................224

Acknowledge Error ...................................................233

Baud Rate Registers ................................................215

Baud Rate Setting ....................................................229

Bit Error ....................................................................233

Bit Time Partitioning .................................................229

Bit Timing Configuration Registers ...........................232

Calculating TQ, Nominal bit Rate and

Nominal bit Time ..............................................230

Configuration Mode ..................................................222

Control and Status Registers ...................................199

Controller Register Map ...........................................221

CRC Error ................................................................233

Disable Mode ...........................................................222

Error Detection .........................................................233

Error Modes and Error Counters ..............................233

Error Modes State Diagram .....................................234

Error States ..............................................................233

Filter Mask Truth (table) ...........................................228

Form Error ................................................................233

Hard Synchronization ...............................................231

I/O Control Register .................................................217

Information Processing Time ...................................230

Initiating Transmission .............................................224

Interrupt Acknowledge .............................................235

Interrupt Registers ....................................................218

Interrupts ..................................................................234

Bus Activity Wake-up .......................................235

Bus-Off .............................................................235

Code bits ..........................................................234

Error .................................................................235

Message Error .................................................235

Receive ............................................................234

Receiver Bus Passive ......................................235

Receiver Overflow ............................................235

Receiver Warning ............................................235

Transmit ...........................................................234

Transmitter Bus Passive ..................................235

Transmitter Warning ........................................235

Lengthening a bit Period ..........................................231

Listen Only Mode .....................................................222

Loopback Mode ........................................................223

Message Acceptance Filters and

CCP1 Module .......................................................... 122

CCPR1H Register .................................................... 122

CCPR1L Register .................................................... 122

Compare Mode. See Compare (CCP Module)

Interaction of CCP1 and ECCP1 Modules ............... 122

PWM Mode. See PWM (CCP Module)

Timer Resources ..................................................... 122

Ceramic Resonators

Ranges Tested .......................................................... 17

Clocking Scheme ............................................................... 41

CLRF ............................................................................... 293

CLRWDT .......................................................................... 293

Code Examples

16 x 16 Signed Multiply Routine ................................ 76

16 x 16 Unsigned Multiply Routine ............................ 76

8 x 8 Signed Multiply Routine .................................... 75

8 x 8 Unsigned Multiply Routine ................................ 75

Changing Between Capture Prescalers ................... 123

Data EEPROM Read ................................................. 61

Data EEPROM Refresh Routine ................................ 62

Data EEPROM Write ................................................. 61

Erasing a FLASH Program Memory Row .................. 70

Fast Register Stack ................................................... 40

How to Clear RAM (Bank 1) Using

Indirect Addressing ............................................ 55

Initializing PORTA ...................................................... 93

Initializing PORTB ...................................................... 95

Initializing PORTC ..................................................... 98

Initializing PORTD ................................................... 100

Initializing PORTE .................................................... 102

Loading the SSPBUF Register ................................ 144

Reading a FLASH Program Memory Word ............... 69

Saving STATUS, WREG and

Masks ....................................................... 212, 228

Message Acceptance Mask and

Filter Operation ................................................228

Message Reception .................................................226

Message Reception Flow Chart ...............................227

Message Time-Stamping .........................................226

Message Transmission ............................................223

Modes of Operation ..................................................222

Normal Mode ............................................................222

Oscillator Tolerance .................................................232

Overview ..................................................................197

Phase Buffer Segments ...........................................230

BSR Registers in RAM ...................................... 92

DS41159B-page 370

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

WIN and ICODE bits Usage in Interrupt

DC Characteristics ............................ 327, 328, 329, 330, 331

EEPROM and Enhanced FLASH ............................ 333

DCFSNZ .......................................................................... 297

DECF ............................................................................... 296

DECFSZ .......................................................................... 297

Development Support ...................................................... 319

Development Tool Version Requirements ....................... 367

Device Differences ........................................................... 365

Device Migrations ............................................................ 366

Device Overview .................................................................. 7

Features ...................................................................... 7

Direct Addressing .............................................................. 56

Disable Mode (CAN Module) ........................................... 222

Service Routine to Access TX/RX Buffers ....... 201

Writing to FLASH Program Memory .................... 72–73

Code Protection ............................................................... 261

COMF ............................................................................... 294

Comparator Module ......................................................... 245

Analog Input Connection Considerations ................. 249

Associated Registers ............................................... 250

Configuration ............................................................ 246

Effects of a RESET .................................................. 249

External Reference Signal ....................................... 247

Internal Reference Signal ........................................ 247

Interrupts .................................................................. 248

Operation ................................................................. 247

Operation During SLEEP ......................................... 249

Outputs .................................................................... 247

Reference ................................................................ 247

Response Time ........................................................ 247

Comparator Specifications ............................................... 334

Comparator Voltage Reference Module ........................... 251

Accuracy/Error ......................................................... 252

Associated Registers ............................................... 253

Configuring ............................................................... 251

Connection Considerations ...................................... 252

Effects of a RESET .................................................. 252

Operation During SLEEP ......................................... 252

Output Buffer Example ............................................. 253

Compare (CCP Module) ................................................... 124

Associated Registers ............................................... 125

CCP1 Pin Configuration ........................................... 124

CCPR1H:CCPR1L Registers ................................... 124

Software Interrupt .................................................... 124

Special Event Trigger ........................113, 119, 124, 243

Timer1/Timer3 Mode Selection ................................ 124

Compare (ECCP Module) ................................................ 131

Associated Registers ............................................... 131

Special Event Trigger ............................................... 131

Compatible 10-bit Analog-to-Digital Converter

E

Electrical Characteristics ................................................. 325

Enhanced Capture/Compare/PWM (ECCP) .................... 129

Auto-Shutdown ........................................................ 140

Capture Mode. See Capture (ECCP Module)

Compare Mode. See Compare (ECCP Module)

ECCPR1H Register ................................................. 130

ECCPR1L Register .................................................. 130

Interaction of CCP1 and ECCP1 Modules ............... 130

Pin Assignments for Various Modes ........................ 130

PWM Mode. See PWM (ECCP Module)

Timer Resources ..................................................... 130

Enhanced CCP Auto-Shutdown ...................................... 140

Enhanced PWM Mode. See PWM

(ECCP Module) ........................................................ 132

Errata ................................................................................... 5

Error Recognition Mode (CAN Module) ........................... 222

External Clock Input ........................................................... 19

F

Firmware Instructions ...................................................... 277

FLASH Program Memory .................................................. 65

Associated Registers ................................................. 74

Control Registers ....................................................... 66

Erase Sequence ........................................................ 70

Erasing ...................................................................... 70

Operation During Code Protect ................................. 73

Reading ..................................................................... 69

TABLAT (Table Latch) Register ................................. 68

Table Pointer

(A/D) Module. See A/D.

Configuration Mode (CAN Module) .................................. 222

CPFSEQ .......................................................................... 294

CPFSGT ........................................................................... 295

CPFSLT ........................................................................... 295

Crystal Oscillator

Boundaries Based on Operation ....................... 68

Table Pointer Boundaries .......................................... 68

Table Reads and Table Writes .................................. 65

TBLPTR (Table Pointer) Register .............................. 68

Write Sequence ......................................................... 71

Writing to ................................................................... 71

Protection Against Spurious Writes ................... 73

Unexpected Termination ................................... 73

Write Verify ........................................................ 73

Capacitor Selection .................................................... 18

D

Data EEPROM Memory ..................................................... 59

Associated Registers ................................................. 63

EEADR Register ........................................................ 59

EECON1 Register ...................................................... 59

EECON2 Register ...................................................... 59

Operation During Code Protect .................................. 62

Protection Against Spurious Writes ........................... 62

Reading ...................................................................... 61

Usage ......................................................................... 62

Write Verify ................................................................ 62

Writing to .................................................................... 61

Data Memory ...................................................................... 44

General Purpose Registers ........................................ 44

Special Function Registers ........................................ 44

Data Memory Map

G

GOTO .............................................................................. 298

H

Hardware Multiplier ............................................................ 75

Operation ................................................................... 75

Performance Comparison (table) ............................... 75

HS4 (PLL) .......................................................................... 19

PIC18F248/448 .......................................................... 45

PIC18F258/458 .......................................................... 46

DAW ................................................................................. 296

DC and AC Characteristics Graphs and Tables ............... 355

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 371

PIC18FXX8

BZ ............................................................................ 292

CALL ........................................................................ 292

CLRF ....................................................................... 293

CLRWDT ................................................................. 293

COMF ...................................................................... 294

CPFSEQ .................................................................. 294

CPFSGT .................................................................. 295

CPFSLT ................................................................... 295

DAW ........................................................................ 296

DCFSNZ .................................................................. 297

DECF ....................................................................... 296

DECFSZ .................................................................. 297

GOTO ...................................................................... 298

INCF ........................................................................ 298

INCFSZ .................................................................... 299

INFSNZ .................................................................... 299

IORLW ..................................................................... 300

IORWF ..................................................................... 300

LFSR ........................................................................ 301

MOVF ...................................................................... 301

MOVFF .................................................................... 302

MOVLB .................................................................... 302

MOVLW ................................................................... 303

MOVWF ................................................................... 303

MULLW .................................................................... 304

MULWF .................................................................... 304

NEGF ....................................................................... 305

NOP ......................................................................... 305

POP ......................................................................... 306

PUSH ....................................................................... 306

RCALL ..................................................................... 307

RESET ..................................................................... 307

RETFIE .................................................................... 308

RETLW .................................................................... 308

RETURN .................................................................. 309

RLCF ....................................................................... 309

RLNCF ..................................................................... 310

RRCF ....................................................................... 310

RRNCF .................................................................... 311

SETF ........................................................................ 311

SLEEP ..................................................................... 312

SUBFWB ................................................................. 312

SUBLW .................................................................... 313

SUBWF .................................................................... 313

SUBWFB ................................................................. 314

SWAPF .................................................................... 314

TBLRD ..................................................................... 315

TBLWT ..................................................................... 316

TSTFSZ ................................................................... 317

XORLW .................................................................... 317

XORWF ................................................................... 318

Summary Table ....................................................... 280

I

I/O Ports .............................................................................93

2

I C Mode ..........................................................................150

ACK Pulse ........................................................ 154, 155

Acknowledge Sequence Timing ...............................174

Baud Rate Generator ...............................................167

Bus Collision and Arbitration ....................................175

Bus Collision During a Repeated

START Condition .............................................179

Bus Collision During a START Condition .................177

Bus Collision During a STOP Condition ...................180

Clock Arbitration .......................................................168

Clock Stretching .......................................................160

Effect of a RESET ....................................................175

General Call Address Support .................................164

Master Mode ............................................................165

Operation .........................................................166

Reception .........................................................171

Repeated START Condition Timing .................170

Master Mode START Condition Timing ...................169

Master Mode Transmission ......................................171

Multi-Master Mode ...................................................175

Read/Write bit Information (R/W bit) ................ 154, 155

Registers ..................................................................150

Serial Clock (RC3/SCK/SCL) ...................................155

Slave Mode ..............................................................154

Addressing .......................................................154

Reception .........................................................155

Transmission ....................................................155

SLEEP Operation .....................................................175

STOP Condition Timing ...........................................174

ICEPIC In-Circuit Emulator ..............................................320

ID Locations ............................................................. 261, 275

INCF .................................................................................298

INCFSZ ............................................................................299

In-Circuit Debugger ..........................................................275

In-Circuit Serial Programming (ICSP) ...................... 261, 275

Indirect Addressing ............................................................56

FSR Register ..............................................................55

INDF Register ............................................................55

Operation ...................................................................55

INFSNZ ............................................................................299

Initialization Conditions for All Registers ............................30

Instruction Cycle .................................................................41

Instruction Flow/Pipelining .................................................41

Instruction Format ............................................................279

Instruction Set ..................................................................277

ADDLW ....................................................................283

ADDWF ....................................................................283

ADDWFC .................................................................284

ANDLW ....................................................................284

ANDWF ....................................................................285

BC ............................................................................285

BCF ..........................................................................286

BN ............................................................................286

BNC ..........................................................................287

BNN ..........................................................................287

BNOV .......................................................................288

BNZ ..........................................................................288

BOV ..........................................................................291

BRA ..........................................................................289

BSF ..........................................................................289

BTFSC .....................................................................290

BTFSS ......................................................................290

BTG ..........................................................................291

INTCON Register

RBIF bit ...................................................................... 95

2

Inter-Integrated Circuit. See I C

Interrupt Sources

A/D Conversion Complete ....................................... 240

CAN Module ............................................................ 234

Capture Complete (CCP) ......................................... 123

Compare Complete (CCP) ....................................... 124

Interrupt-on-Change (RB7:RB4) ................................ 95

TMR0 Overflow ........................................................ 109

TMR1 Overflow .................................................111, 113

TMR2 to PR2 Match ................................................ 116

TMR2 to PR2 Match (PWM) .............................115, 126

TMR3 Overflow .................................................117, 119

DS41159B-page 372

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Interrupt-on-Change (RB7:RB4) Flag

SPI Master/Slave Connection .................................. 145

SPI Mode ................................................................. 141

SPI Slave Mode ....................................................... 147

TMR2 Output for Clock Shift .............................115, 116

Typical Connection .................................................. 145

(RBIF bit) .................................................................... 95

Interrupts ............................................................................ 77

Context Saving During ............................................... 92

Enable Registers ........................................................ 85

Flag Registers ............................................................ 82

INT ............................................................................. 92

PORTB Interrupt-on-Change ..................................... 92

Priority Registers ........................................................ 88

TMR0 ......................................................................... 92

Interrupts, Flag bits

2

MSSP. See also I C Mode, SPI Mode.

MULLW ............................................................................ 304

MULWF ............................................................................ 304

N

NEGF ............................................................................... 305

NOP ................................................................................. 305

Normal Operation Mode (CAN Module) ........................... 222

CCP1 Flag (CCP1IF bit) ...........................122, 123, 124

Interrupts, Flag bits

A/D Converter Flag (ADIF bit) .................................. 239

IORLW ............................................................................. 300

IORWF ............................................................................. 300

O

OPCODE Field Descriptions ............................................ 278

OPTION_REG Register

K

PSA bit ..................................................................... 109

T0CS bit ................................................................... 109

T0PS2:T0PS0 bits ................................................... 109

T0SE bit ................................................................... 109

Oscillator

KEELOQ Evaluation and Programming Tools ................... 322

L

LFSR ................................................................................ 301

Listen Only Mode (CAN Module) ..................................... 222

Lookup Tables .................................................................... 43

Computed GOTO ....................................................... 43

Table Reads/Table Writes ......................................... 43

Loopback Mode (CAN Module) ........................................ 222

Low Voltage Detect .......................................................... 255

Characteristics ......................................................... 332

Characteristics (diagram) ......................................... 332

Current Consumption ............................................... 259

Effects of a RESET .................................................. 259

Operation ................................................................. 258

Operation During SLEEP ......................................... 259

Reference Voltage Set Point .................................... 259

Typical Application ................................................... 255

Low Voltage ICSP Programming ..................................... 275

LVD. See Low Voltage Detect.

Effects of SLEEP Mode ............................................. 23

Power-up Delays ....................................................... 23

Switching Feature ...................................................... 20

System Clock Switch bit ............................................ 20

Transitions ................................................................. 21

Oscillator Configurations .................................................... 17

Crystal Oscillator, Ceramic Resonators ..................... 17

EC .............................................................................. 17

ECIO .......................................................................... 17

HS .............................................................................. 17

HS4 ............................................................................ 17

LP .............................................................................. 17

RC ........................................................................17, 18

RCIO .......................................................................... 17

XT .............................................................................. 17

Oscillator Selection .......................................................... 261

Oscillator, Timer1 ..............................................111, 113, 119

Oscillator, WDT ................................................................ 268

M

Master Synchronous Serial Port (MSSP). See MSSP.

Master Synchronous Serial Port. See MSSP.

P

Memory Organization ......................................................... 37

Data Memory ............................................................. 44

Internal Program Memory Operation ......................... 37

Program Memory ....................................................... 37

Migrating from other PICmicro Devices ........................... 366

MOVF ............................................................................... 301

MOVFF ............................................................................. 302

MOVLB ............................................................................. 302

MOVLW ............................................................................ 303

MOVWF ........................................................................... 303

MPLAB C17 and MPLAB C18 C Compilers ..................... 319

MPLAB ICD In-Circuit Debugger ...................................... 321

MPLAB ICE High Performance Universal

Packaging Information ..................................................... 357

Details ...................................................................... 359

Marking .................................................................... 357

Parallel Slave Port (PSP) ..........................................100, 105

Associated Registers ............................................... 106

PORTD .................................................................... 105

PSP Mode Select (PSPMODE) bit .......................... 100

RE2/CS .................................................................... 105

PIC18FXX8 Voltage-Frequency Graph

(Industrial) ................................................................ 326

PIC18LFXX8 Voltage-Frequency Graph

(Industrial) ................................................................ 326

PICDEM 1 Low Cost PICmicro

In-Circuit Emulator with MPLAB IDE ........................ 320

MPLAB Integrated Development

Demonstration Board ............................................... 321

PICDEM 17 Demonstration Board ................................... 322

PICDEM 2 Low Cost PIC16CXX

Demonstration Board ............................................... 321

PICDEM 3 Low Cost PIC16CXXX

Environment Software .............................................. 319

MPLINK Object Linker/MPLIB Object Librarian ............... 320

MSSP ............................................................................... 141

Control Registers ..................................................... 141

Enabling SPI I/O ...................................................... 145

Demonstration Board ............................................... 322

PICSTART Plus Entry Level Development

2

I C Mode Operation ................................................. 154

Programmer ............................................................. 321

Operation ................................................................. 144

Overview .................................................................. 141

SPI Master Mode ..................................................... 146

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 373

PIC18FXX8

Pin Functions

PORTD

Associated Register Summary ................................ 101

MCLR/VPP ..................................................................10

OSC1/CLKI ................................................................10

OSC2/CLKO/RA6 .......................................................10

RA0/AN0/CVREF ........................................................11

RA1/AN1 ....................................................................11

RA2/AN2/VREF- ..........................................................11

RA3/AN3/VREF+ .........................................................11

RA4/T0CKI .................................................................11

RA5/AN4/SS/LVDIN ...................................................11

RA6 ............................................................................11

RB0/INT0 ...................................................................12

RB1/INT1 ...................................................................12

RB2/CANTX ...............................................................12

RB3/CANRX ...............................................................12

RB4 ............................................................................12

RB5/PGM ...................................................................12

RB6/PGC ...................................................................12

RB7/PGD ...................................................................12

RC0/T1OSO/T1CKI ....................................................13

RC1/T1OSI .................................................................13

RC2/CCP1 .................................................................13

RC3/SCK/SCL ............................................................13

RC4/SDI/SDA .............................................................13

RC5/SDO ...................................................................13

RC6/TX/CK ................................................................13

RC7/RX/DT ................................................................13

RD0/PSP0/C1IN+ ......................................................14

RD1/PSP1/C1IN- .......................................................14

RD2/PSP2/C2IN+ ......................................................14

RD3/PSP3/C2IN- .......................................................14

RD4/PSP4/ECCP/PA .................................................14

RD5/PSP5/PB ............................................................14

RD6/PSP6/PC ............................................................14

RD7/PSP7/PD ............................................................14

RE0/AN5/RD ..............................................................15

RE1/AN6/WR/C1OUT ................................................15

RE2/AN7/CS/C2OUT .................................................15

Pinout I/O Descriptions ......................................................10

Pointer, FSRn .....................................................................55

POP ..................................................................................306

POR. See Power-on Reset.

Functions ................................................................. 101

LATD Register ......................................................... 100

Parallel Slave Port (PSP) Function .......................... 100

PORTD Register ...................................................... 100

TRISD Register ........................................................ 100

PORTE

Associated Register Summary ................................ 104

Functions ................................................................. 103

LATE Register ......................................................... 102

PORTE Register ...................................................... 102

PSP Mode Select (PSPMODE) bit .......................... 100

RE2/CS .................................................................... 105

TRISE Register ........................................................ 102

Postscaler, WDT

Assignment (PSA bit) ............................................... 109

Rate Select (T0PS2:T0PS0 bits) ............................. 109

Power-down Mode. See SLEEP

Power-on Reset (POR) ...............................................26, 261

MCLR ......................................................................... 26

Oscillator Start-up Timer (OST) ..........................26, 261

PLL Lock Time-out ..................................................... 26

Power-up Timer (PWRT) ....................................26, 261

Time-out Sequence ................................................... 27

Power-up Delays

OSC1 and OSC2 Pin States in SLEEP Mode ........... 23

Prescaler, Capture ........................................................... 123

Prescaler, Timer0 ............................................................. 109

Assignment (PSA bit) ............................................... 109

Rate Select (T0PS2:T0PS0 bits) ............................. 109

Prescaler, Timer2 ............................................................. 126

PRO MATE II Universal Device Programmer .................. 321

Product Identification System .......................................... 381

Program Counter

PCL Register ............................................................. 40

PCLATH Register ...................................................... 40

PCLATU Register ...................................................... 40

Program Memory ............................................................... 37

Fast Register Stack ................................................... 40

Instructions ................................................................ 41

Two-Word .......................................................... 43

Map and Stack for PIC18F248/448 ........................... 37

Map and Stack for PIC18F258/458 ........................... 37

PUSH and POP Instructions ...................................... 40

Return Address Stack ................................................ 38

Return Stack Pointer (STKPTR) ................................ 38

Stack Full/Underflow Resets ...................................... 40

Top-of-Stack Access .................................................. 38

Program Verification and Code Protection ....................... 272

Associated Registers Summary ............................... 272

Configuration Register Protection ............................ 275

Data EEPROM Code Protection .............................. 275

Program Memory Code Protection .......................... 273

Programming, Device Instructions ................................... 277

PUSH ............................................................................... 306

PWM (CCP Module) ........................................................ 126

CCPR1H:CCPR1L Registers ................................... 126

Duty Cycle ............................................................... 126

Example Frequencies/Resolutions .......................... 127

Output Diagram ....................................................... 126

Period ...................................................................... 126

Registers Associated with PWM and Timer2 ........... 127

Setup for PWM Operation ........................................ 127

TMR2 to PR2 Match .........................................115, 126

PORTA

Associated Register Summary ...................................94

Functions ....................................................................94

LATA Register ............................................................93

PORTA Register ........................................................93

TRISA Register ..........................................................93

PORTB

Associated Registers .................................................97

Functions ....................................................................97

LATB Register ............................................................95

PORTB Register ........................................................95

RB7:RB4 Interrupt-on-Change Flag

(RBIF bit) ............................................................95

TRISB Register ..........................................................95

PORTC

Associated Registers .................................................99

Functions ....................................................................99

LATC Register ............................................................98

PORTC Register ........................................................98

RC3/SCK/SCL Pin ...................................................155

RC7/RX/DT Pin ........................................................183

TRISC Register .................................................. 98, 181

DS41159B-page 374

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

PWM (ECCP Module) ...................................................... 132

Associated Registers ............................................... 139

Direction Change in Full-Bridge Output Mode ......... 136

Enhanced CCP Auto-Shutdown ............................... 140

Full-Bridge Application Example .............................. 136

Full-Bridge Mode ...................................................... 135

Full-Bridge PWM Output Diagram ........................... 135

Half-Bridge Mode ..................................................... 134

Half-Bridge Output Diagram ..................................... 134

Half-Bridge Output Mode Applications Example ...... 134

Output Configurations .............................................. 132

Output Polarity Configuration ................................... 138

Output Relationships Diagram ................................. 133

Programmable Deadband Delay .............................. 138

PWM Direction Change at Near 100%

EECON1 (EEPROM Control 1) ............................60, 67

INTCON (Interrupt Control) ........................................ 79

INTCON2 (Interrupt Control 2) ................................... 80

INTCON3 (Interrupt Control 3) ................................... 81

IPR1 (Peripheral Interrupt Priority 1) ......................... 88

IPR2 (Peripheral Interrupt Priority 2) ......................... 89

IPR3 (Peripheral Interrupt Priority 3) ......................... 90

IPR3 (Peripheral Interrupt Priority) .......................... 220

LVDCON (LVD Control) ........................................... 257

OSCCON (Oscillator Control) .................................... 20

PIE1 (Peripheral Interrupt Enable 1) .......................... 85

PIE2 (Peripheral Interrupt Enable 2) .......................... 86

PIE3 (Peripheral Interrupt Enable 3) .......................... 87

PIE3 (Peripheral Interrupt Enable) ........................... 219

PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 82

PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 83

PIR3 (Peripheral Interrupt Flag) ............................... 218

PIR3 (Peripheral Interrupt Request (Flag) 3) ............. 84

RCON (Reset Control) ..........................................58, 91

RCSTA (USART Receive Status) ............................ 182

RXB0CON (Receive Buffer 0 Control) ..................... 208

RXB1CON (Receive Buffer 1 Control) ..................... 209

RXBnDLC (Receive Buffer n

Duty Cycle Diagram ......................................... 137

PWM Direction Change Diagram ............................. 137

Setup for PWM Operation ........................................ 139

Standard Mode ........................................................ 132

Start-up Considerations ........................................... 138

System Implementation ........................................... 138

Q

Q Clock ............................................................................ 126

Data Length Code) .......................................... 211

RXBnDm (Receive Buffer n Data

Field Byte m) ................................................... 211

RXBnEIDH (Receive Buffer n Extended

R

RAM. See Data Memory.

RCALL .............................................................................. 307

RCON Register

Identifier,

High Byte) ........................................................ 210

RXBnEIDL (Receive Buffer n Extended

Significance of Status bits vs.

Initialization Condition ........................................ 27

RCSTA Register ............................................................... 181

SPEN bit .................................................................. 181

Receiver Warning ............................................................. 235

Register File ....................................................................... 44

Register File Summary ....................................................... 49

Registers

Identifier, Low Byte) ......................................... 210

RXBnSIDH (Receive Buffer n Standard

Identifier, High Byte) ........................................ 209

RXBnSIDL (Receive Buffer n Standard

Identifier, Low Byte) ......................................... 210

RXERRCNT (Receive Error Count) ......................... 212

RXFnEIDH (Receive Acceptance Filter n

ADCON0 (A/D Control 0) ......................................... 237

ADCON1 (A/D Control 1) ......................................... 238

BRGCON1 (Baud Rate Control 1) ........................... 215

BRGCON2 (Baud Rate Control 2) ........................... 216

BRGCON3 (Baud Rate Control 3) ........................... 217

CANCON (CAN Control) .......................................... 199

CANSTAT (CAN Status) .......................................... 200

CCP1CON (CCP1 Control) ...................................... 121

CIOCON (CAN I/O Control) ..................................... 217

CMCON (Comparator Control) ................................ 245

COMSTAT (CAN Communication Status) ............... 203

CONFIG1H (Configuration 1 High) .......................... 262

CONFIG2H (Configuration 2 High) .......................... 263

CONFIG2L (Configuration 2 Low) ............................ 262

CONFIG4L (Configuration 4 Low) ............................ 263

CONFIG5H (Configuration 5 High) .......................... 264

CONFIG5L (Configuration 5 Low) ............................ 264

CONFIG6H (Configuration 6 High) .......................... 265

CONFIG6L (Configuration 6 Low) ............................ 265

CONFIG7H (Configuration 7 High) .......................... 266

CONFIG7L (Configuration 7 Low) ............................ 266

CVRCON (Comparator Voltage

Extended Identifier, High Byte) ........................ 213

RXFnEIDL (Receive Acceptance Filter n

Extended Identifier, Low Byte) ......................... 213

RXFnSIDH (Receive Acceptance Filter n

Standard Identifier Filter, High Byte) ............... 212

RXFnSIDL (Receive Acceptance Filter n

Standard Identifier Filter, Low Byte) ................ 212

RXMnEIDH (Receive Acceptance Mask n

Extended Identifier Mask, High Byte) .............. 214

RXMnEIDL (Receive Acceptance Mask n

Extended Identifier Mask, Low Byte) ............... 214

RXMnSIDH (Receive Acceptance Mask n

Standard Identifier Mask, High Byte) ............... 213

RXMnSIDL (Receive Acceptance Mask n

Standard Identifier Mask, Low Byte) ................ 214

SSPCON1 (MSSP Control 1) .................................. 143

2

SSPCON1 (MSSP Control 1) (I C Mode ................. 152

2

SSPCON2 (MSSP Control 2) (I C Mode) ................ 153

SSPSTAT (MSSP Status) ........................................ 142

2

SSPSTAT (MSSP Status) (I C Mode) ..................... 151

STATUS .................................................................... 57

STKPTR (Stack Pointer) ............................................ 39

T0CON (Timer0 Control) ......................................... 107

T1CON (Timer1 Control) ......................................... 111

T2CON (Timer2 Control) ......................................... 115

T3CON (Timer3 Control) ......................................... 117

TRISE (PORTE Direction/PSP Control) .................. 103

TXBnCON (Transmit Buffer n Control) .................... 204

Reference Control) ........................................... 251

Device ID Register 1 ................................................ 267

Device ID Register 2 ................................................ 267

ECCP1CON (ECCP1 Control) ................................. 129

ECCP1DEL (PWM Delay) ........................................ 138

ECCPAS (Enhanced Capture/Compare/PWM

Auto-Shutdown Control) ................................... 140

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 375

PIC18FXX8

TXBnDLC (Transmit Buffer n Data

Length Code) ...................................................207

TXBnDm (Transmit Buffer n

Data Field Byte m) ...........................................206

TXBnEIDH (Transmit Buffer n

Extended Identifier, High Byte) ........................205

TXBnEIDL (Transmit Buffer n

Slave Select Synchronization .................................. 147

SLEEP Operation .................................................... 149

SPI Clock ................................................................. 146

SSPBUF Register .................................................... 146

SSPSR Register ...................................................... 146

SSPOV bit ........................................................................ 171

SSPSTAT Register

Extended Identifier, Low Byte) .........................206

TXBnSIDH (Transmit Buffer n

Standard Identifier, High Byte) .........................205

TXBnSIDL (Transmit Buffer n

R/W bit ..............................................................154, 155

SUBFWB ......................................................................... 312

SUBLW ............................................................................ 313

SUBWF ............................................................................ 313

SUBWFB ......................................................................... 314

SWAPF ............................................................................ 314

Standard Identifier, Low Byte) ..........................205

TXERRCNT (Transmit Error Count) .........................207

TXSTA (USART Transmit Status) ............................181

WDTCON (Watchdog Timer Control) .......................268

RESET ............................................................... 25, 261, 307

MCLR Reset During Normal Operation ......................25

MCLR Reset During SLEEP ......................................25

Power-on Reset (POR) ..............................................25

Programmable Brown-out Reset (PBOR) ..................25

RESET Instruction ......................................................25

Stack Full Reset .........................................................25

Stack Underflow Reset ...............................................25

Watchdog Timer (WDT) Reset ...................................25

RETFIE ............................................................................308

RETLW .............................................................................308

RETURN ..........................................................................309

Revision History ...............................................................365

RLCF ................................................................................309

RLNCF .............................................................................310

RRCF ...............................................................................310

RRNCF .............................................................................311

T

Table Pointer Operations (table) ........................................ 68

TBLRD ............................................................................. 315

TBLWT ............................................................................. 316

Timer0 .............................................................................. 107

16-bit Mode Timer Reads and Writes ...................... 109

Clock Source Edge Select (T0SE bit) ...................... 109

Clock Source Select (T0CS bit) ............................... 109

Operation ................................................................. 109

Overflow Interrupt .................................................... 109

Prescaler .................................................................. 109

Prescaler. See Prescaler, Timer0

Switching Prescaler Assignment ............................. 109

Timer1 .............................................................................. 111

Associated Registers ............................................... 113

Operation ................................................................. 112

Oscillator ...........................................................111, 113

Overflow Interrupt .............................................111, 113

Special Event Trigger (CCP) ............................113, 124

Special Event Trigger (ECCP) ................................. 131

TMR1H Register ...................................................... 111

TMR1L Register ....................................................... 111

TMR3L Register ....................................................... 117

Timer2 .............................................................................. 115

Associated Registers ............................................... 116

Operation ................................................................. 115

Postscaler. See Postscaler, Timer2

S

Sales and Support ............................................................381

SCI. See USART

SCK pin ............................................................................141

SDI pin .............................................................................141

SDO pin ............................................................................141

Serial Clock (SCK) pin .....................................................141

Serial Communication Interface. See USART

Serial Peripheral Interface. See SPI

PR2 Register ....................................................115, 126

Prescaler. See Prescaler, Timer2

SETF ................................................................................311

Slave Select (SS) Pin .......................................................141

Slave Select Synchronization ...........................................147

Slave Select, SS pin .........................................................141

SLEEP .............................................................. 261, 270, 312

Software Simulator (MPLAB SIM) ....................................320

Special Event Trigger. See Compare

Special Features of the CPU ............................................261

Configuration bits .....................................................261

Configuration bits and Device IDs ............................261

Configuration Registers .................................... 262–267

Special Function Register Map ..........................................47

Special Function Registers ................................................44

SPI Mode

SSP Clock Shift ................................................115, 116

TMR2 Register ......................................................... 115

TMR2 to PR2 Match Interrupt ...................115, 116, 126

Timer3 .............................................................................. 117

Associated Registers ............................................... 119

Operation ................................................................. 118

Oscillator .................................................................. 119

Overflow Interrupt .............................................117, 119

Special Event Trigger (CCP) ................................... 119

TMR3H Register ...................................................... 117

Timing Conditions ............................................................ 336

Load Conditions for Device Specifications .............. 336

Temperature and Voltage

Associated Registers ...............................................149

Bus Mode Compatibility ...........................................149

Effects of a RESET ..................................................149

Master Mode ............................................................146

Master/Slave Connection .........................................145

Serial Clock ..............................................................141

Serial Data In (SDI) pin ............................................141

Serial Data Out (SDO) pin ........................................141

Slave Mode ..............................................................147

Slave Select .............................................................141

Specifications - AC .......................................... 336

Timing Diagrams

A/D Conversion ........................................................ 353

Acknowledge Sequence .......................................... 174

Baud Rate Generator with Clock Arbitration ............ 168

BRG Reset Due to SDA Arbitration During

START Condition ............................................. 178

Brown-out Reset (BOR) and Low

Voltage Detect ................................................. 339

DS41159B-page 376

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Bus Collision During a Repeated

Time-out Sequence on Power-up

START Condition (Case 1) .............................. 179

Bus Collision During a Repeated

(MCLR Not Tied to VDD): Case 2 ...................... 28

Time-out Sequence on Power-up

START Condition (Case2) ............................... 179

Bus Collision During a STOP

Condition (Case 1) ........................................... 180

Bus Collision During a STOP

Condition (Case 2) ........................................... 180

Bus Collision During START

Condition (SCL = 0) ......................................... 178

Bus Collision During START

Condition (SDA Only) ....................................... 177

Bus Collision for Transmit and

Acknowledge .................................................... 176

Capture/Compare/PWM

(MCLR Tied to VDD Via RC Network) ................ 28

Timer0 and Timer1 External Clock .......................... 340

Transition Between Timer1 and OSC1

(HS with PLL) .................................................... 22

Transition Between Timer1 and OSC1

(HS, XT, LP) ...................................................... 21

Transition Between Timer1 and OSC1

(RC, EC) ............................................................ 22

Transition from OSC1 to Timer1 Oscillator ................ 21

USART Asynchronous Reception ............................ 190

USART Asynchronous Transmission ...................... 188

USART Asynchronous Transmission

(CCP1 and ECCP1) ......................................... 341

CLKO and I/O .......................................................... 338

Clock Synchronization ............................................. 161

External Clock .......................................................... 337

First START bit Timing ............................................. 169

(Back to Back) ................................................. 188

USART Synchronous Receive (Master/Slave) ........ 351

USART Synchronous Reception

(Master Mode, SREN) ..................................... 193

USART Synchronous Transmission ........................ 192

USART Synchronous Transmission

2

I C Bus Data ............................................................ 347

2

I C Bus START/STOP bits ...................................... 347

(Master/Slave) ................................................. 351

USART Synchronous Transmission

2

I C Master Mode (Reception, 7-bit Address) ........... 173

2

I C Master Mode (Transmission, 7 or

(Through TXEN) .............................................. 192

Wake-up from SLEEP via Interrupt .......................... 271

Timing Diagrams and Specifications ............................... 337

A/D Conversion Requirements ................................ 353

Capture/Compare/PWM Requirements

10-bit Address) ................................................. 172

I C Slave Mode (Transmission,

2

10-bit Address) ................................................. 159

I C Slave Mode (Transmission,

2

7-bit Address) ................................................... 157

I C Slave Mode SEN = 1 (Reception,

10-bit Address) ................................................. 163

I C Slave Mode with SEN = 0 (Reception,

10-bit Address) ................................................. 158

I C Slave Mode with SEN = 0 (Reception,

7-bit Address) ................................................... 156

I C Slave Mode with SEN = 1 (Reception,

(CCP1 and ECCP1) ......................................... 341

CLKO and I/O Timing Requirements ....................... 338

Example SPI Mode Requirements

(Master Mode, CKE = 0) .................................. 343

Example SPI Mode Requirements

2

(Master Mode, CKE = 1) .................................. 344

Example SPI Mode Requirements

2

(Slave Mode, CKE = 0) .................................... 345

Example SPI Slave Mode Requirements (CKE = 1) 346

External Clock Timing Requirements ...................... 337

7-bit Address) ................................................... 162

Low Voltage Detect .................................................. 258

2

Master SSP I C Bus Data ........................................ 349

I C Bus Data Requirements (Slave Mode) .............. 348

2

Master SSP I C Bus START/STOP bits .................. 349

I C Bus START/STOP bits Requirements

Parallel Slave Port (PIC18F248

(Slave Mode) ................................................... 347

2

and PIC18F458) ............................................... 342

Parallel Slave Port Read Waveforms ....................... 106

Parallel Slave Port Write Waveforms ....................... 105

Repeat START Condition ........................................ 170

RESET, Watchdog Timer (WDT), Oscillator

Start-up Timer (OST), Power-up Timer

(PWRT) ............................................................ 339

Slave Mode General Call Address Sequence

Master SSP I C Bus Data Requirements ................ 350

2

Master SSP I C Bus START/STOP bits

Requirements .................................................. 349

Parallel Slave Port Requirements

(PIC18F248 and PIC18F458) .......................... 342

PLL Clock ................................................................ 338

RESET, Watchdog Timer, Oscillator Start-up

Timer, Power-up Timer, Brown-out Reset

(7 or 10-bit Address Mode) .............................. 164

Slave Synchronization ............................................. 147

Slow Rise Time (MCLR Tied to VDD

and Low Voltage Detect Requirements ........... 339

Timer0 and Timer1 External

Clock Requirements ........................................ 340

USART Synchronous Transmission

Via RC Network) ................................................ 29

SPI Master Mode (CKE = 0) .................................... 343

SPI Master Mode (CKE = 1) .................................... 344

SPI Mode (Master Mode) ......................................... 146

SPI Mode (Slave Mode with CKE = 0) ..................... 148

SPI Mode (Slave Mode with CKE = 1) ..................... 148

SPI Slave Mode (CKE = 0) ...................................... 345

SPI Slave Mode (CKE = 1) ...................................... 346

STOP Condition Receive or Transmit Mode ............ 175

Time-out Sequence on POR w/ PLL Enabled

Requirements .................................................. 351

TSTFSZ ........................................................................... 317

TXSTA Register

BRGH bit ................................................................. 183

(MCLR Tied to VDD Via RC Network) ................ 29

Time-out Sequence on Power-up

(MCLR Not Tied to VDD): Case 1 ....................... 28

 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 377

PIC18FXX8

U

V

USART .............................................................................181

Asynchronous Mode ................................................187

Asynchronous Reception ................................. 189, 190

Asynchronous Transmission ....................................187

Associated Registers .......................................188

Baud Rate Generator (BRG) ....................................183

Associated Registers .......................................183

Baud Rate Error, Calculating ...........................183

Baud Rate Formula ..........................................183

Baud Rates for Asynchronous Mode

Voltage Reference Specifications .................................... 334

W

Wake-up from SLEEP ...............................................261, 270

Using Interrupts ....................................................... 270

Watchdog Timer (WDT) ............................................261, 268

Associated Registers ............................................... 269

Control Register ....................................................... 268

Postscaler ................................................................ 269

Programming Considerations .............................66, 268

RC Oscillator ............................................................ 268

Time-out Period ....................................................... 268

WCOL ...............................................................169, 171, 174

WCOL Status Flag ........................................................... 169

WDT. See Watchdog Timer. ............................................ 268

WWW, On-Line Support ...................................................... 5

(BRGH = 0) ..............................................185

Baud Rates for Asynchronous Mode

(BRGH = 1) ..............................................186

Baud Rates for Synchronous Mode .................184

High Baud Rate Select (BRGH bit) ..................183

Sampling ..........................................................183

Serial Port Enable (SPEN) bit ..................................181

Setting Up 9-bit Mode with Address Detect .............189

Synchronous Master Mode ......................................191

Synchronous Master Reception ...............................193

Associated Registers .......................................193

Synchronous Master Transmission ..........................191

Associated Registers .......................................191

Synchronous Slave Mode ........................................194

Synchronous Slave Reception ......................... 194, 195

Synchronous Slave Transmission

X

XORLW ............................................................................ 317

XORWF ........................................................................... 318

Associated Registers .......................................195

Synchronous Slave Transmit ...................................194

DS41159B-page 378

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

Systems Information and Upgrade Hot Line

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 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 379

PIC18FXX8

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

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Literature Number:

DS41159B

Device:

PIC18FXX8

Questions:

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4. What additions to the data sheet do you think would enhance the structure and subject?

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DS41159B-page 380

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX8

PIC18FXX8 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature Package

Range

Pattern

a)

PIC18LF258 - I/L 301 = Industrial temp., PLCC

package, Extended VDD limits, QTP pattern

#301.

b)

c)

PIC18LF458 - I/PT = Industrial temp., TQFP

package, Extended VDD limits.

Device

PIC18F248/258⁽¹⁾, PIC18F448/458⁽¹⁾, PIC18F248/258T⁽²⁾

PIC18F448/458T⁽²⁾

,

PIC18F258 - E/L = Extended temp., PLCC

package, normal VDD limits.

;

VDD range 4.2V to 5.5V

PIC18LF248/258⁽¹⁾, PIC18LF448/458⁽¹⁾, PIC18LF248/258T⁽²⁾

PIC18LF448/458T^(2);

,

VDD range 2.0V to 5.5V

Temperature Range

Package

I

E

=

-40°C to +85°C (Industrial)

-40°C to +125°C (Extended)

Note 1:

2:

F

LF

T

=

Standard Voltage Range

Wide Voltage Range

in tape and reel PLCC, and TQFP

packages only.

PT

L

SO

SP

P

=

TQFP (Thin Quad Flatpack)

PLCC

SOIC

Skinny Plastic DIP

PDIP

Pattern

QTP, SQTP, Code or Special Requirements

(blank otherwise)

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

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Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

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 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 381

M

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Microchip Technology Consulting (Shanghai)

Co., Ltd., Chengdu Liaison Office

Rm. 2401, 24th Floor,

Ming Xing Financial Tower

No. 88 TIDU Street

Chengdu 610016, China

Tel: 86-28-86766200 Fax: 86-28-86766599

China - Fuzhou

Microchip Technology Consulting (Shanghai)

Co., Ltd., Fuzhou Liaison Office

Unit 28F, World Trade Plaza

No. 71 Wusi Road

Fuzhou 350001, China

2 Lan Drive, Suite 120

Westford, MA 01886

Tel: 978-692-3848 Fax: 978-692-3821

Chicago

333 Pierce Road, Suite 180

Itasca, IL 60143

Tel: 630-285-0071 Fax: 630-285-0075

Dallas

4570 Westgrove Drive, Suite 160

Addison, TX 75001

Tel: 972-818-7423 Fax: 972-818-2924

Tung Hua North Road

Taipei, 105, Taiwan

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

Denmark

Detroit

Tri-Atria Office Building

Tel: 86-591-7503506 Fax: 86-591-7503521

32255 Northwestern Highway, Suite 190

Farmington Hills, MI 48334

Tel: 248-538-2250 Fax: 248-538-2260

Microchip Technology Nordic ApS

Regus Business Centre

Lautrup hoj 1-3

Ballerup DK-2750 Denmark

Tel: 45 4420 9895 Fax: 45 4420 9910

China - Shanghai

Microchip Technology Consulting (Shanghai)

Co., Ltd.

Room 701, Bldg. B

Far East International Plaza

No. 317 Xian Xia Road

Shanghai, 200051

Tel: 86-21-6275-5700 Fax: 86-21-6275-5060

China - Shenzhen

Microchip Technology Consulting (Shanghai)

Co., Ltd., Shenzhen Liaison Office

Rm. 1315, 13/F, Shenzhen Kerry Centre,

Renminnan Lu

Shenzhen 518001, China

Tel: 86-755-2350361 Fax: 86-755-2366086

Kokomo

2767 S. Albright Road

Kokomo, Indiana 46902

Tel: 765-864-8360 Fax: 765-864-8387

Los Angeles

France

Microchip Technology SARL

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

18201 Von Karman, Suite 1090

Irvine, CA 92612

Tel: 949-263-1888 Fax: 949-263-1338

Batiment A - ler Etage

91300 Massy, France

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Microchip Technology GmbH

Gustav-Heinemann Ring 125

D-81739 Munich, Germany

Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

New York

150 Motor Parkway, Suite 202

Hauppauge, NY 11788

Tel: 631-273-5305 Fax: 631-273-5335

San Jose

China - Hong Kong SAR

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Microchip Technology Hongkong Ltd.

Unit 901-6, Tower 2, Metroplaza

223 Hing Fong Road

Kwai Fong, N.T., Hong Kong

Tel: 852-2401-1200 Fax: 852-2401-3431

Italy

Microchip Technology SRL

Centro Direzionale Colleoni

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Tel: 408-436-7950 Fax: 408-436-7955

Toronto

6285 Northam Drive, Suite 108

Mississauga, Ontario L4V 1X5, Canada

Tel: 905-673-0699 Fax: 905-673-6509

India

Milan, Italy

Tel: 39-039-65791-1 Fax: 39-039-6899883

Microchip Technology Inc.

India Liaison Office

United Kingdom

Microchip Ltd.

505 Eskdale Road

Winnersh Triangle

Wokingham

Berkshire, England RG41 5TU

Tel: 44 118 921 5869 Fax: 44-118 921-5820

Austria

Divyasree Chambers

1 Floor, Wing A (A3/A4)

No. 11, O’Shaugnessey Road

Bangalore, 560 025, India

Tel: 91-80-2290061 Fax: 91-80-2290062

Microchip Technology Austria GmbH

Durisolstrasse 2

A-4600 Wels

Austria

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

05/16/02

DS41159B-page 382

Preliminary

 2002 Microchip Technology Inc.


型号：	PIC18LF248EPSQTP
厂家：	MICROCHIP
描述：	High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN 高性能，四十分之二十八引脚增强型闪存微控制器与CAN 闪存微控制器
文件：	总384页 (文件大小：5831K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC18LF248EPSQTP [MICROCHIP]

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