PIC18FXX2T-E/SP_技术文档

PIC18FXX2

Data Sheet

High-Performance, Enhanced Flash

Microcontrollers with 10-Bit A/D

DS39564C

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

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OTHERWISE, RELATED TO THE INFORMATION,

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS39564C-page ii

PIC18FXX2

28/40-pin High Performance, Enhanced FLASH

Microcontrollers with 10-Bit A/D

High Performance RISC CPU:

Peripheral Features (Continued):

• C compiler optimized architecture/instruction set

- Source code compatible with the PIC16 and

PIC17 instruction sets

• Addressable USART module:

- Supports RS-485 and RS-232

• Parallel Slave Port (PSP) module

• Linear program memory addressing to 32 Kbytes

• Linear data memory addressing to 1.5 Kbytes

Analog Features:

• Compatible 10-bit Analog-to-Digital Converter

module (A/D) with:

- Fast sampling rate

- Conversion available during SLEEP

- Linearity ≤ 1 LSb

• Programmable Low Voltage Detection (PLVD)

- Supports interrupt on-Low Voltage Detection

• Programmable Brown-out Reset (BOR)

On-Chip Program

On-Chip

RAM EEPROM

(bytes)

Data

Memory

Device

FLASH # Single Word

(bytes)

Instructions

PIC18F242

PIC18F252

PIC18F442

16K

32K

16K

8192

16384

8192

768

1536

768

256

PIC18F452

32K

16384

1536

256

Special Microcontroller Features:

• Up to 10 MIPs operation:

- DC - 40 MHz osc./clock input

• 100,000 erase/write cycle Enhanced FLASH

program memory typical

• 1,000,000 erase/write cycle Data EEPROM

memory

- 4 MHz - 10 MHz osc./clock input with PLL active

• 16-bit wide instructions, 8-bit wide data path

• Priority levels for interrupts

• 8 x 8 Single Cycle Hardware Multiplier

• FLASH/Data EEPROM Retention: > 40 years

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own On-Chip RC

Oscillator for reliable operation

Peripheral Features:

• High current sink/source 25 mA/25 mA

• Three external interrupt pins

• Timer0 module: 8-bit/16-bit timer/counter with

8-bit programmable prescaler

• Programmable code protection

• Power saving SLEEP mode

• Timer1 module: 16-bit timer/counter

• Timer2 module: 8-bit timer/counter with 8-bit

period register (time-base for PWM)

• Timer3 module: 16-bit timer/counter

• Secondary oscillator clock option - Timer1/Timer3

• Two Capture/Compare/PWM (CCP) modules.

CCP pins that can be configured as:

- Capture input: capture is 16-bit,

• Selectable oscillator options including:

- 4X Phase Lock Loop (of primary oscillator)

- Secondary Oscillator (32 kHz) clock input

• Single supply 5V In-Circuit Serial Programming™

(ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

CMOS Technology:

max. resolution 6.25 ns (TCY/16)

- Compare is 16-bit, max. resolution 100 ns (TCY)

- PWM output: PWM resolution is 1- to 10-bit,

max. PWM freq. @: 8-bit resolution = 156 kHz

10-bit resolution = 39 kHz

• Master Synchronous Serial Port (MSSP) module,

Two modes of operation:

• Low power, high speed FLASH/EEPROM

technology

• Fully static design

• Wide operating voltage range (2.0V to 5.5V)

• Industrial and Extended temperature ranges

• Low power consumption:

- < 1.6 mA typical @ 5V, 4 MHz

- 25 μA typical @ 3V, 32 kHz

- < 0.2 μA typical standby current

- 3-wire SPI™ (supports all 4 SPI modes)

- I²C™ Master and Slave mode

DS39564C-page 1

PIC18FXX2

Pin Diagrams

PLCC

RA4/T0CKI

39

38

37

36

35

34

33

32

31

30

29

RB3/CCP2*

RB2/INT2

RB1/INT1

RB0/INT0

VDD

7

RA5/AN4/SS/LVDIN

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

VDD

8

9

10

11

12

13

14

15

16

17

PIC18F442

PIC18F452

VSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

VSS

OSC1/CLKI

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

NC

TQFP

NC

33

RC7/RX/DT

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

VSS

1

2

3

4

5

6

7

8

9

RC0/T1OSO/T1CKI

OSC2/CLKO/RA6

OSC1/CLKI

VSS

32

31

30

29

28

27

26

PIC18F442

VDD

RE2/AN7/CS

RE1/AN6/WR

RE0/AN5/RD

RA5/AN4/SS/LVDIN

RA4/T0CKI

PIC18F452

VDD

RB0/INT0

RB1/INT1

RB2/INT2

RB3/CCP2*

25

24

23

10

11

* RB3 is the alternate pin for the CCP2 pin multiplexing.

DS39564C-page 2

PIC18FXX2

Pin Diagrams (Cont.’d)

DIP

MCLR/VPP

RA0/AN0

1

2

3

4

5

6

7

8

RB7/PGD

RB6/PGC

RB5/PGM

RB4

RB3/CCP2*

RB2/INT2

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4/SS/LVDIN

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

VDD

RB1/INT1

RB0/INT0

VDD

9

10

11

12

13

14

15

16

17

18

19

20

VSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

RC6/TX/CK

RC5/SDO

VSS

OSC1/CLKI

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2*

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

Note: Pin compatible with 40-pin PIC16C7X devices.

DIP, SOIC

28

27

26

1

2

3

4

5

6

7

8

9

RB7/PGD

RB6/PGC

RB5/PGM

RB4

RB3/CCP2*

RB2/INT2

RB1/INT1

RB0/INT0

VDD

MCLR/VPP

RA0/AN0

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

25

24

23

22

21

20

19

18

17

16

15

RA5/AN4/SS/LVDIN

VSS

OSC1/CLKI

VSS

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2*

RC2/CCP1

10

11

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

12

13

14

RC3/SCK/SCL

* RB3 is the alternate pin for the CCP2 pin multiplexing.

DS39564C-page 3

PIC18FXX2

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Oscillator Configurations ............................................................................................................................................................ 17

3.0 Reset.......................................................................................................................................................................................... 25

4.0 Memory Organization................................................................................................................................................................. 35

5.0 FLASH Program Memory........................................................................................................................................................... 55

6.0 Data EEPROM Memory ............................................................................................................................................................. 65

7.0 8 X 8 Hardware Multiplier........................................................................................................................................................... 71

8.0 Interrupts .................................................................................................................................................................................... 73

9.0 I/O Ports ..................................................................................................................................................................................... 87

10.0 Timer0 Module ......................................................................................................................................................................... 103

11.0 Timer1 Module ......................................................................................................................................................................... 107

12.0 Timer2 Module ......................................................................................................................................................................... 111

13.0 Timer3 Module ......................................................................................................................................................................... 113

14.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 117

15.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 125

16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 165

17.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module................................................................................................... 181

18.0 Low Voltage Detect .................................................................................................................................................................. 189

19.0 Special Features of the CPU.................................................................................................................................................... 195

20.0 Instruction Set Summary.......................................................................................................................................................... 211

21.0 Development Support............................................................................................................................................................... 253

22.0 Electrical Characteristics.......................................................................................................................................................... 259

23.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 289

24.0 Packaging Information.............................................................................................................................................................. 305

Appendix A: Revision History............................................................................................................................................................ 313

Appendix B: Device Differences........................................................................................................................................................ 313

Appendix C: Conversion Considerations........................................................................................................................................... 314

Appendix D: Migration from Baseline to Enhanced Devices ............................................................................................................. 314

Appendix E: Migration from Mid-range to Enhanced Devices........................................................................................................... 315

Appendix F: Migration from High-end to Enhanced Devices ............................................................................................................ 315

Index .................................................................................................................................................................................................. 317

On-Line Support................................................................................................................................................................................. 327

Reader Response .............................................................................................................................................................................. 328

PIC18FXX2 Product Identification System......................................................................................................................................... 329

DS39564C-page 4

PIC18FXX2

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

welcome your feedback.

Most Current Data Sheet

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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DS39564C-page 5

PIC18FXX2

NOTES:

DS39564C-page 6

PIC18FXX2

The following two figures are device block diagrams

sorted by pin count: 28-pin for Figure 1-1 and 40/44-pin

for Figure 1-2. The 28-pin and 40/44-pin pinouts are

listed in Table 1-2 and Table 1-3, respectively.

1.0

DEVICE OVERVIEW

This document contains device specific information for

the following devices:

• PIC18F242

• PIC18F252

• PIC18F442

• PIC18F452

These devices come in 28-pin and 40/44-pin packages.

The 28-pin devices do not have a Parallel Slave Port

(PSP) implemented and the number of Analog-to-

Digital (A/D) converter input channels is reduced to 5.

An overview of features is shown in Table 1-1.

TABLE 1-1:

DEVICE FEATURES

Features

PIC18F242

PIC18F252

PIC18F442

PIC18F452

Operating Frequency

Program Memory (Bytes)

Program Memory (Instructions)

Data Memory (Bytes)

Data EEPROM Memory (Bytes)

Interrupt Sources

DC - 40 MHz

32K

16K

32K

16K

8192

768

256

18

8192

16384

1536

768

1536

256

17

18

I/O Ports

Ports A, B, C

Ports A, B, C, D, E Ports A, B, C, D, E

Timers

4

2

4

2

4

2

4

2

Capture/Compare/PWM Modules

MSSP,

Addressable

USART

MSSP,

Addressable

USART

MSSP,

Addressable

USART

MSSP,

Addressable

USART

Serial Communications

Parallel Communications

—

PSP

10-bit Analog-to-Digital Module

5 input channels

8 input channels

POR, BOR,

RESETInstruction, RESETInstruction, RESETInstruction, RESETInstruction,

RESETS (and Delays)

Stack Full,

Stack Underflow

(PWRT, OST)

Stack Full,

Stack Underflow

(PWRT, OST)

Stack Full,

Stack Underflow

(PWRT, OST)

Stack Full,

Stack Underflow

(PWRT, OST)

Programmable Low Voltage

Detect

Yes

Programmable Brown-out Reset

Instruction Set

Yes

75 Instructions

40-pin DIP

44-pin PLCC

44-pin TQFP

40-pin DIP

44-pin PLCC

44-pin TQFP

28-pin DIP

28-pin SOIC

28-pin DIP

28-pin SOIC

Packages

DS39564C-page 7

PIC18FXX2

FIGURE 1-1:

PIC18F2X2 BLOCK DIAGRAM

Data Bus<8>

PORTA

Table Pointer

inc/dec logic

21

Data Latch

21

RA0/AN0

8

Data RAM

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4/SS/LVDIN

RA6

21

Address Latch

12⁽²⁾

PCLATU PCLATH

Address Latch

Address<12>

Program Memory

(up to 2 Mbytes)

PCU PCH PCL

Program Counter

4

BSR

12

4

Data Latch

Bank0, F

FSR0

FSR1

FSR2

31 Level Stack

12

16

inc/dec

logic

Decode

Table Latch

PORTB

8

ROM Latch

RB0/INT0

RB1/INT1

RB2/INT2

RB3/CCP2⁽¹⁾

RB4

Instruction

Register

RB5/PGM

RB6/PCG

RB7/PGD

8

Instruction

Decode &

Control

PRODH PRODL

8 x 8 Multiply

OSC2/CLKO

OSC1/CLKI

3

Power-up

Timer

8

Timing

Generation

Oscillator

Start-up Timer

T1OSCI

T1OSCO

WREG

8

BIT OP

8

Power-on

Reset

8

Watchdog

Timer

4X PLL

ALU<8>

PORTC

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2⁽¹⁾

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

Brown-out

Reset

8

Precision

Voltage

Reference

Low Voltage

Programming

MCLR

In-Circuit

Debugger

RC6/TX/CK

RC7/RX/DT

VDD, VSS

A/D Converter

Timer0

CCP1

Timer1

Timer2

Timer3

Master

Synchronous

Serial Port

Addressable

USART

CCP2

Data EEPROM

Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.

2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFFinstruction).

3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations

are device dependent.

DS39564C-page 8

PIC18FXX2

FIGURE 1-2:

PIC18F4X2 BLOCK DIAGRAM

Data Bus<8>

PORTA

RA0/AN0

RA1/AN1

Table Pointer

Data Latch

21

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4/SS/LVDIN

RA6

Data RAM

(up to 4K

address reach)

8

inc/dec logic

21

Address Latch

12⁽²⁾

PCLATU

PCLATH

Address Latch

Program Memory

(up to 2 Mbytes)

Address<12>

PCH PCL

Program Counter

PCU

PORTB

4

BSR

12

4

Data Latch

RB0/INT0

RB1/INT1

RB2/INT2

RB3/CCP2⁽¹⁾

RB4

Bank0, F

FSR0

FSR1

FSR2

31 Level Stack

12

RB5/PGM

RB6/PCG

RB7/PGD

16

inc/dec

logic

Decode

Table Latch

8

ROM Latch

PORTC

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2⁽¹⁾

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

Instruction

Register

8

Instruction

Decode &

Control

RC6/TX/CK

RC7/RX/DT

PRODH PRODL

8 x 8 Multiply

OSC2/CLKO

OSC1/CLKI

3

Power-up

Timer

PORTD

8

RD0/PSP0

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

Timing

Generation

Oscillator

Start-up Timer

WREG

8

T1OSCI

T1OSCO

BIT OP

8

Power-on

Reset

8

Watchdog

Timer

4X PLL

ALU<8>

Brown-out

Reset

8

Precision

PORTE

Voltage

Reference

Low Voltage

Programming

MCLR

RE0/AN5/RD

In-Circuit

Debugger

RE1/AN6/WR

RE2/AN7/CS

VDD, VSS

A/D Converter

Timer0

CCP1

Timer1

CCP2

Timer2

Timer3

Master

Synchronous

Serial Port

Addressable

USART

Parallel Slave Port

Data EEPROM

Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.

2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFFinstruction).

3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations

are device dependent.

DS39564C-page 9

PIC18FXX2

TABLE 1-2:

PIC18F2X2 PINOUT I/O DESCRIPTIONS

Pin Number

DIP SOIC

Type

Buffer

Type

Pin Name

Description

MCLR/VPP

MCLR

1

Master Clear (input) or high voltage ICSP programming

enable pin.

I

ST

Master Clear (Reset) input. This pin is an active low

RESET to the device.

VPP

NC

I

ST

—

High voltage ICSP programming enable pin.

—

9

—

9

—

These pins should be left unconnected.

OSC1/CLKI

OSC1

Oscillator crystal or external clock input.

I

ST

Oscillator crystal input or external clock source input.

ST buffer when configured in RC mode, CMOS otherwise.

External clock source input. Always associated with

pin function OSC1. (See related OSC1/CLKI,

OSC2/CLKO pins.)

CLKI

CMOS

OSC2/CLKO/RA6

OSC2

10

Oscillator crystal or clock output.

O

—

Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO which has 1/4

the frequency of OSC1, and denotes the instruction

cycle rate.

CLKO

RA6

I/O

TTL

General Purpose I/O pin.

PORTA is a bi-directional I/O port.

RA0/AN0

RA0

2

3

4

2

3

4

I/O

I

TTL

Analog

Digital I/O.

Analog input 0.

AN0

RA1/AN1

RA1

I/O

I

TTL

Analog

Digital I/O.

Analog input 1.

AN1

RA2/AN2/VREF-

RA2

I/O

TTL

Digital I/O.

AN2

VREF-

I

Analog

Analog input 2.

A/D Reference Voltage (Low) input.

RA3/AN3/VREF+

RA3

5

I/O

TTL

Digital I/O.

AN3

VREF+

I

Analog

Analog input 3.

A/D Reference Voltage (High) input.

RA4/T0CKI

RA4

6

7

6

7

I/O

I

ST/OD

ST

Digital I/O. Open drain when configured as output.

Timer0 external clock input.

T0CKI

RA5/AN4/SS/LVDIN

RA5

AN4

SS

I/O

TTL

Analog

ST

Digital I/O.

Analog input 4.

SPI Slave Select input.

Low Voltage Detect Input.

I

LVDIN

Analog

RA6

See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = Output

I = Input

P = Power

OD = Open Drain (no P diode to VDD)

DS39564C-page 10

PIC18FXX2

TABLE 1-2:

Pin Name

PIC18F2X2 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Buffer

Type

Description

Type

DIP SOIC

PORTB is a bi-directional I/O port. PORTB can be software

programmed for internal weak pull-ups on all inputs.

RB0/INT0

RB0

21

22

23

24

21

22

23

24

I/O

I

TTL

ST

Digital I/O.

External Interrupt 0.

INT0

RB1/INT1

RB1

I/O

I

TTL

ST

INT1

External Interrupt 1.

RB2/INT2

RB2

I/O

I

TTL

ST

Digital I/O.

External Interrupt 2.

INT2

RB3/CCP2

RB3

I/O

TTL

ST

Digital I/O.

CCP2

Capture2 input, Compare2 output, PWM2 output.

RB4

25

26

25

26

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

RB5/PGM

RB5

I/O

TTL

ST

Digital I/O. Interrupt-on-change pin.

Low Voltage ICSP programming enable pin.

PGM

RB6/PGC

RB6

27

28

27

28

I/O

TTL

ST

Digital I/O. Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming clock pin.

PGC

RB7/PGD

RB7

I/O

TTL

ST

Digital I/O. Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming data pin.

PGD

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = Output

I = Input

P = Power

OD = Open Drain (no P diode to VDD)

DS39564C-page 11

PIC18FXX2

TABLE 1-2:

PIC18F2X2 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

DIP SOIC

Type

Buffer

Type

Pin Name

Description

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI

RC0

11

12

11

12

I/O

O

I

ST

—

ST

Digital I/O.

Timer1 oscillator output.

Timer1/Timer3 external clock input.

T1OSO

T1CKI

RC1/T1OSI/CCP2

RC1

I/O

I

I/O

ST

CMOS

ST

Digital I/O.

Timer1 oscillator input.

Capture2 input, Compare2 output, PWM2 output.

T1OSI

CCP2

RC2/CCP1

RC2

13

14

13

14

I/O

ST

Digital I/O.

CCP1

Capture1 input/Compare1 output/PWM1 output.

RC3/SCK/SCL

RC3

I/O

ST

Digital I/O.

SCK

SCL

Synchronous serial clock input/output for SPI mode.

Synchronous serial clock input/output for I²C mode

RC4/SDI/SDA

RC4

15

I/O

I

I/O

ST

Digital I/O.

SDI

SDA

SPI Data In.

I²C Data I/O.

RC5/SDO

RC5

16

17

16

17

I/O

O

ST

—

Digital I/O.

SPI Data Out.

SDO

RC6/TX/CK

RC6

TX

CK

I/O

O

I/O

ST

—

ST

Digital I/O.

USART Asynchronous Transmit.

USART Synchronous Clock (see related RX/DT).

RC7/RX/DT

18

RC7

RX

DT

I/O

I

I/O

ST

Digital I/O.

USART Asynchronous Receive.

USART Synchronous Data (see related TX/CK).

VSS

VDD

8, 19 8, 19

20 20

P

—

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = Output

I = Input

P = Power

OD = Open Drain (no P diode to VDD)

DS39564C-page 12

PIC18FXX2

TABLE 1-3:

Pin Name

PIC18F4X2 PINOUT I/O DESCRIPTIONS

Pin Number

Buffer

Type

Description

Type

DIP PLCC TQFP

MCLR/VPP

MCLR

1

2

18

Master Clear (input) or high voltage ICSP

programming enable pin.

I

ST

Master Clear (Reset) input. This pin is an active

low RESET to the device.

VPP

NC

I

ST

—

High voltage ICSP programming enable pin.

—

These pins should be left unconnected.

OSC1/CLKI

OSC1

13

14

30

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source

input. ST buffer when configured in RC mode,

CMOS otherwise.

I

ST

CLKI

CMOS

External clock source input. Always associated

with pin function OSC1. (See related OSC1/CLKI,

OSC2/CLKO pins.)

OSC2/CLKO/RA6

OSC2

14

15

31

Oscillator crystal or clock output.

O

—

Oscillator crystal output. Connects to crystal

or resonator in Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO,

which has 1/4 the frequency of OSC1 and

denotes the instruction cycle rate.

General Purpose I/O pin.

CLKO

RA6

I/O

TTL

PORTA is a bi-directional I/O port.

RA0/AN0

RA0

2

3

4

3

4

5

19

20

21

I/O

I

TTL

Analog

Digital I/O.

Analog input 0.

AN0

RA1/AN1

RA1

I/O

I

TTL

Analog

Digital I/O.

Analog input 1.

AN1

RA2/AN2/VREF-

RA2

I/O

TTL

Digital I/O.

AN2

VREF-

I

Analog

Analog input 2.

A/D Reference Voltage (Low) input.

RA3/AN3/VREF+

RA3

5

6

22

I/O

TTL

Digital I/O.

AN3

VREF+

I

Analog

Analog input 3.

A/D Reference Voltage (High) input.

RA4/T0CKI

RA4

6

7

8

23

24

I/O

I

ST/OD

ST

Digital I/O. Open drain when configured as output.

Timer0 external clock input.

T0CKI

RA5/AN4/SS/LVDIN

RA5

AN4

SS

I/O

TTL

Analog

ST

Digital I/O.

Analog input 4.

SPI Slave Select input.

Low Voltage Detect Input.

I

LVDIN

Analog

RA6

(See the OSC2/CLKO/RA6 pin.)

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = Output

I = Input

P = Power

OD = Open Drain (no P diode to VDD)

DS39564C-page 13

PIC18FXX2

TABLE 1-3:

PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

Description

DIP PLCC TQFP

PORTB is a bi-directional I/O port. PORTB can be

software programmed for internal weak pull-ups on all

inputs.

RB0/INT0

RB0

33

34

35

36

37

38

39

8

9

I/O

I

TTL

ST

Digital I/O.

External Interrupt 0.

INT0

RB1/INT1

RB1

I/O

I

TTL

ST

INT1

External Interrupt 1.

RB2/INT2

RB2

10

11

I/O

I

TTL

ST

Digital I/O.

External Interrupt 2.

INT2

RB3/CCP2

RB3

I/O

TTL

ST

Digital I/O.

CCP2

Capture2 input, Compare2 output, PWM2 output.

RB4

37

38

41

42

14

15

I/O

TTL

Digital I/O. Interrupt-on-change pin.

RB5/PGM

RB5

I/O

TTL

ST

Digital I/O. Interrupt-on-change pin.

Low Voltage ICSP programming enable pin.

PGM

RB6/PGC

RB6

39

40

43

44

16

17

I/O

TTL

ST

Digital I/O. Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming clock

pin.

PGC

RB7/PGD

RB7

I/O

TTL

ST

Digital I/O. Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming data

pin.

PGD

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = Output

I = Input

P = Power

OD = Open Drain (no P diode to VDD)

DS39564C-page 14

PIC18FXX2

TABLE 1-3:

Pin Name

PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Buffer

Type

Description

Type

DIP PLCC TQFP

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI

RC0

15

16

18

32

35

I/O

O

I

ST

—

ST

Digital I/O.

Timer1 oscillator output.

Timer1/Timer3 external clock input.

T1OSO

T1CKI

RC1/T1OSI/CCP2

RC1

I/O

I

I/O

ST

CMOS

ST

Digital I/O.

Timer1 oscillator input.

Capture2 input, Compare2 output, PWM2 output.

T1OSI

CCP2

RC2/CCP1

RC2

17

18

19

20

36

37

I/O

ST

Digital I/O.

CCP1

Capture1 input/Compare1 output/PWM1 output.

RC3/SCK/SCL

RC3

I/O

ST

Digital I/O.

Synchronous serial clock input/output for

SPI mode.

SCK

SCL

I/O

ST

Synchronous serial clock input/output for

I²C mode.

RC4/SDI/SDA

RC4

23

25

42

I/O

I

I/O

ST

Digital I/O.

SDI

SDA

SPI Data In.

I²C Data I/O.

RC5/SDO

RC5

24

25

26

27

43

44

I/O

O

ST

—

Digital I/O.

SPI Data Out.

SDO

RC6/TX/CK

RC6

TX

CK

I/O

O

I/O

ST

—

ST

Digital I/O.

USART Asynchronous Transmit.

USART Synchronous Clock (see related RX/DT).

RC7/RX/DT

26

29

1

RC7

RX

DT

I/O

I

I/O

ST

Digital I/O.

USART Asynchronous Receive.

USART Synchronous Data (see related TX/CK).

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = Output

I = Input

P = Power

OD = Open Drain (no P diode to VDD)

DS39564C-page 15

PIC18FXX2

TABLE 1-3:

PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

Description

DIP PLCC TQFP

PORTD is a bi-directional I/O port, or a Parallel Slave

Port (PSP) for interfacing to a microprocessor port.

These pins have TTL input buffers when PSP module

is enabled.

RD0/PSP0

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

19

20

21

22

27

28

29

30

21

22

23

24

30

31

32

33

38

39

40

41

2

I/O

ST

TTL

Digital I/O.

Parallel Slave Port Data.

ST

TTL

Digital I/O.

Parallel Slave Port Data.

ST

TTL

Digital I/O.

Parallel Slave Port Data.

ST

TTL

Digital I/O.

Parallel Slave Port Data.

ST

TTL

Digital I/O.

Parallel Slave Port Data.

3

ST

TTL

Digital I/O.

Parallel Slave Port Data.

4

ST

TTL

Digital I/O.

Parallel Slave Port Data.

5

ST

Digital I/O.

TTL

Parallel Slave Port Data.

PORTE is a bi-directional I/O port.

RE0/RD/AN5

RE0

8

9

25

26

27

I/O

ST

TTL

Digital I/O.

RD

Read control for parallel slave port

(see also WR and CS pins).

Analog input 5.

AN5

Analog

RE1/WR/AN6

RE1

10

11

ST

TTL

Digital I/O.

WR

Write control for parallel slave port

(see CS and RD pins).

Analog input 6.

AN6

Analog

RE2/CS/AN7

RE2

10

ST

Digital I/O.

CS

TTL

Chip Select control for parallel slave port

(see related RD and WR).

Analog input 7.

AN7

VSS

Analog

—

12, 31 13, 34 6, 29

11, 32 12, 35 7, 28

P

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

VDD

—

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

O = Output

I = Input

P = Power

OD = Open Drain (no P diode to VDD)

DS39564C-page 16

PIC18FXX2

TABLE 2-1:

CAPACITOR SELECTION FOR

CERAMIC RESONATORS

2.0

2.1

OSCILLATOR

CONFIGURATIONS

Ranges Tested:

Oscillator Types

Mode

Freq

C1

C2

The PIC18FXX2 can be operated in eight different

Oscillator modes. The user can program three configu-

ration bits (FOSC2, FOSC1, and FOSC0) to select one

of these eight modes:

XT

455 kHz

2.0 MHz

4.0 MHz

68 - 100 pF 68 - 100 pF

15 - 68 pF

HS

8.0 MHz

16.0 MHz

10 - 68 pF

10 - 22 pF

10 - 68 pF

10 - 22 pF

1. LP

Low Power Crystal

2. XT

Crystal/Resonator

These values are for design guidance only.

See notes following this table.

3. HS

High Speed Crystal/Resonator

4. HS + PLL

High Speed Crystal/Resonator

with PLL enabled

Resonators Used:

455 kHz Panasonic EFO-A455K04B

2.0 MHz Murata Erie CSA2.00MG

4.0 MHz Murata Erie CSA4.00MG

8.0 MHz Murata Erie CSA8.00MT

16.0 MHz Murata Erie CSA16.00MX

0.3%

0.5%

5. RC

External Resistor/Capacitor

6. RCIO

External Resistor/Capacitor with

I/O pin enabled

7. EC

External Clock

8. ECIO

External Clock with I/O pin

enabled

All resonators used did not have built-in capacitors.

2.2

Crystal Oscillator/Ceramic

Resonators

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

In XT, LP, HS or HS+PLL Oscillator modes, a crystal or

ceramic resonator is connected to the OSC1 and

OSC2 pins to establish oscillation. Figure 2-1 shows

the pin connections.

2: When operating below 3V VDD, or when

using certain ceramic resonators at any

voltage, it may be necessary to use

high-gain HS mode, try a lower frequency

resonator, or switch to a crystal oscillator.

The PIC18FXX2 oscillator design requires the use of a

parallel cut crystal.

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturers

specifications.

3: Since each resonator/crystal has its own

characteristics, the user should consult the

resonator/crystal manufacturer for appro-

priate values of external components, or

verify oscillator performance.

FIGURE 2-1:

CRYSTAL/CERAMIC

RESONATOROPERATION

(HS, XT OR LP

CONFIGURATION)

(1)

C1

OSC1

To

Internal

Logic

(3)

RF

XTAL

SLEEP

(2)

RS

(1)

PIC18FXXX

C2

OSC2

Note 1: See Table 2-1 and Table 2-2 for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF varies with the Oscillator mode chosen.

DS39564C-page 17

PIC18FXX2

TABLE 2-2:

CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

2.3

RC Oscillator

For timing-insensitive applications, the “RC” and

“RCIO” device options offer additional cost savings.

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) val-

ues and the operating temperature. In addition to this,

the oscillator frequency will vary from unit to unit due to

normal process parameter variation. Furthermore, the

difference in lead frame capacitance between package

types will also affect the oscillation frequency, espe-

cially for low CEXT values. The user also needs to take

into account variation due to tolerance of external R

and C components used. Figure 2-3 shows how the

R/C combination is connected.

Ranges Tested:

Mode

Freq

C1

C2

LP

32.0 kHz

200 kHz

1.0 MHz

4.0 MHz

8.0 MHz

20.0 MHz

25.0 MHz

33 pF

15 pF

33 pF

15 pF

XT

HS

22-68 pF

15 pF

22-68 pF

15 pF

15-33 pF

In the RC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic.

These values are for design guidance only.

See notes following this table.

Note: If the oscillator frequency divided by 4 sig-

nal is not required in the application, it is

recommended to use RCIO mode to save

current.

Crystals Used

32.0 kHz

200 kHz

1.0 MHz

4.0 MHz

8.0 MHz

Epson C-001R32.768K-A

STD XTL 200.000KHz

ECS ECS-10-13-1

20 PPM

50 PPM

30 PPM

FIGURE 2-3:

RC OSCILLATOR MODE

ECS ECS-40-20-1

Epson CA-301 8.000M-C

VDD

20.0 MHz Epson CA-301 20.000M-C

REXT

Internal

OSC1

Clock

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

CEXT

VSS

PIC18FXXX

2: Rs may be required in HS mode, as well

as XT mode, to avoid overdriving crystals

with low drive level specification.

OSC2/CLKO

FOSC/4

3: Since each resonator/crystal has its own

characteristics, the user should consult the

resonator/crystal manufacturer for appro-

priate values of external components., or

verify oscillator performance.

Recommended values:3 kΩ ≤ REXT ≤ 100 kΩ

CEXT > 20pF

The RCIO Oscillator mode functions like the RC mode,

except that the OSC2 pin becomes an additional gen-

eral purpose I/O pin. The I/O pin becomes bit 6 of

PORTA (RA6).

An external clock source may also be connected to the

OSC1 pin in the HS, XT and LP modes, as shown in

Figure 2-2.

FIGURE 2-2:

EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP

OSC CONFIGURATION)

OSC1

Clock from

Ext. System

PIC18FXXX

OSC2

Open

DS39564C-page 18

PIC18FXX2

FIGURE 2-5:

EXTERNAL CLOCK INPUT

OPERATION

(ECIOCONFIGURATION)

2.4

External Clock Input

The EC and ECIO Oscillator modes require an external

clock source to be connected to the OSC1 pin. The

feedback device between OSC1 and OSC2 is turned

off in these modes to save current. There is no oscilla-

tor start-up time required after a Power-on Reset or

after a recovery from SLEEP mode.

OSC1

Clock from

Ext. System

PIC18FXXX

I/O (OSC2)

RA6

In the EC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic. Figure 2-4 shows the pin connections for the EC

Oscillator mode.

2.5

HS/PLL

A Phase Locked Loop circuit is provided as a program-

mable option for users that want to multiply the fre-

quency of the incoming crystal oscillator signal by 4.

For an input clock frequency of 10 MHz, the internal

clock frequency will be multiplied to 40 MHz. This is

useful for customers who are concerned with EMI due

to high frequency crystals.

FIGURE 2-4:

EXTERNAL CLOCK INPUT

OPERATION

(EC CONFIGURATION)

OSC1

Clock from

The PLL can only be enabled when the oscillator con-

figuration bits are programmed for HS mode. If they are

programmed for any other mode, the PLL is not

enabled and the system clock will come directly from

OSC1.

Ext. System

PIC18FXXX

OSC2

FOSC/4

The ECIO Oscillator mode functions like the EC mode,

except that the OSC2 pin becomes an additional gen-

eral purpose I/O pin. The I/O pin becomes bit 6 of

PORTA (RA6). Figure 2-5 shows the pin connections

for the ECIO Oscillator mode.

The PLL is one of the modes of the FOSC<2:0> config-

uration bits. The Oscillator mode is specified during

device programming.

A PLL lock timer is used to ensure that the PLL has

locked before device execution starts. The PLL lock

timer has a time-out that is called TPLL.

FIGURE 2-6:

PLL BLOCK DIAGRAM

(from Configuration

bit Register)

HS Osc

PLL Enable

Phase

Comparator

OSC2

OSC1

FIN

Loop

Filter

VCO

Crystal

Osc

SYSCLK

FOUT

Divide by 4

DS39564C-page 19

PIC18FXX2

tion mode. Figure 2-7 shows a block diagram of the

system clock sources. The clock switching feature is

enabled by programming the Oscillator Switching

Enable (OSCSEN) bit in Configuration Register1H to a

’0’. Clock switching is disabled in an erased device.

See Section 11.0 for further details of the Timer1 oscil-

lator. See Section 19.0 for Configuration Register

details.

2.6

Oscillator Switching Feature

The PIC18FXX2 devices include a feature that allows

the system clock source to be switched from the main

oscillator to an alternate low frequency clock source.

For the PIC18FXX2 devices, this alternate clock source

is the Timer1 oscillator. If a low frequency crystal (32

kHz, for example) has been attached to the Timer1

oscillator pins and the Timer1 oscillator has been

enabled, the device can switch to a Low Power Execu-

FIGURE 2-7:

DEVICE CLOCK SOURCES

PIC18FXXX

Main Oscillator

OSC2

TOSC/4

4 x PLL

SLEEP

TOSC

TT1P

TSCLK

OSC1

Timer1 Oscillator

T1OSO

T1OSCEN

Clock

Source

Enable

Oscillator

T1OSI

Clock Source option

for other modules

DS39564C-page 20

PIC18FXX2

2.6.1

SYSTEM CLOCK SWITCH BIT

Note: The Timer1 oscillator must be enabled and

operating to switch the system clock

source. The Timer1 oscillator is enabled by

setting the T1OSCEN bit in the Timer1

control register (T1CON). If the Timer1

oscillator is not enabled, then any write to

the SCS bit will be ignored (SCS bit forced

cleared) and the main oscillator will

continue to be the system clock source.

The system clock source switching is performed under

software control. The system clock switch bit, SCS

(OSCCON<0>) controls the clock switching. When the

SCS bit is ’0’, the system clock source comes from the

main oscillator that is selected by the FOSC configura-

tion bits in Configuration Register1H. When the SCS bit

is set, the system clock source will come from the

Timer1 oscillator. The SCS bit is cleared on all forms of

RESET.

REGISTER 2-1:

OSCCON REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

SCS

bit 7

bit 0

bit 7-1 Unimplemented: Read as '0'

bit 0 SCS: System Clock Switch bit

When OSCSEN configuration bit = ’0’ and T1OSCEN bit is set:

1= Switch to Timer1 oscillator/clock pin

0= Use primary oscillator/clock input pin

When OSCSEN and T1OSCEN are in other states:

bit is forced clear

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 21

PIC18FXX2

A timing diagram indicating the transition from the main

oscillator to the Timer1 oscillator is shown in

Figure 2-8. The Timer1 oscillator is assumed to be run-

ning all the time. After the SCS bit is set, the processor

is frozen at the next occurring Q1 cycle. After eight syn-

chronization cycles are counted from the Timer1 oscil-

lator, operation resumes. No additional delays are

required after the synchronization cycles.

2.6.2

OSCILLATOR TRANSITIONS

The PIC18FXX2 devices contain circuitry to prevent

“glitches” when switching between oscillator sources.

Essentially, the circuitry waits for eight rising edges of

the clock source that the processor is switching to. This

ensures that the new clock source is stable and that its

pulse width will not be less than the shortest pulse

width of the two clock sources.

FIGURE 2-8:

TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR

Q1 Q2 Q3 Q4 Q1

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

TT1P

1

2

3

4

5

6

7

8

T1OSI

OSC1

Tscs

TOSC

Internal

System

Clock

TDLY

SCS

(OSCCON<0>)

Program

Counter

PC

PC + 2

PC + 4

Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.

The sequence of events that takes place when switch-

ing from the Timer1 oscillator to the main oscillator will

depend on the mode of the main oscillator. In addition

to eight clock cycles of the main oscillator, additional

delays may take place.

If the main oscillator is configured for an external crys-

tal (HS, XT, LP), then the transition will take place after

an oscillator start-up time (TOST) has occurred. A timing

diagram, indicating the transition from the Timer1 oscil-

lator to the main oscillator for HS, XT and LP modes, is

shown in Figure 2-9.

FIGURE 2-9:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)

Q1 Q2 Q3 Q4 Q1 Q2 Q3

Q3

Q4

Q1

TT1P

T1OSI

OSC1

1

2

3

4

5

6

7

8

TOST

TSCS

OSC2

TOSC

Internal System

Clock

SCS

(OSCCON<0>)

Program Counter

PC

PC + 2

PC + 6

Note 1: TOST = 1024 TOSC (drawing not to scale).

DS39564C-page 22

PIC18FXX2

If the main oscillator is configured for HS-PLL mode, an

oscillator start-up time (TOST) plus an additional PLL

time-out (TPLL) will occur. The PLL time-out is typically

2 ms and allows the PLL to lock to the main oscillator

frequency. A timing diagram indicating the transition

from the Timer1 oscillator to the main oscillator for

HS-PLL mode is shown in Figure 2-10.

FIGURE 2-10:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)

TT1P

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q4

Q1

T1OSI

OSC1

TOST

TPLL

OSC2

TSCS

TOSC

PLL Clock

Input

1

2

3

4

5

6

7

8

Internal System

Clock

SCS

(OSCCON<0>)

Program Counter

PC

PC + 2

PC + 4

Note 1: TOST = 1024 TOSC (drawing not to scale).

If the main oscillator is configured in the RC, RCIO, EC

or ECIO modes, there is no oscillator start-up time-out.

Operation will resume after eight cycles of the main

oscillator have been counted. A timing diagram, indi-

cating the transition from the Timer1 oscillator to the

main oscillator for RC, RCIO, EC and ECIO modes, is

shown in Figure 2-11.

FIGURE 2-11:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)

Q3

Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1

TT1P

T1OSI

OSC1

TOSC

6

1

4

5

7

8

2

3

OSC2

Internal System

Clock

SCS

(OSCCON<0>)

TSCS

Program Counter

PC

PC + 2

PC + 4

Note 1: RC Oscillator mode assumed.

DS39564C-page 23

PIC18FXX2

switching currents have been removed, SLEEP mode

achieves the lowest current consumption of the device

(only leakage currents). Enabling any on-chip feature

that will operate during SLEEP will increase the current

consumed during SLEEP. The user can wake from

SLEEP through external RESET, Watchdog Timer

Reset, or through an interrupt.

2.7

Effects of SLEEP Mode on the

On-Chip Oscillator

When the device executes a SLEEP instruction, the

on-chip clocks and oscillator are turned off and the

device is held at the beginning of an instruction cycle

(Q1 state). With the oscillator off, the OSC1 and OSC2

signals will stop oscillating. Since all the transistor

TABLE 2-3:

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

OSC Mode

OSC1 Pin

OSC2 Pin

RC

Floating, external resistor

should pull high

At logic low

RCIO

Floating, external resistor

should pull high

Configured as PORTA, bit 6

ECIO

EC

Floating

Configured as PORTA, bit 6

At logic low

LP, XT, and HS

Feedback inverter disabled, at

quiescent voltage level

Feedback inverter disabled, at

quiescent voltage level

Note: See Table 3-1, in the “Reset” section, for time-outs due to SLEEP and MCLR Reset.

With the PLL enabled (HS/PLL Oscillator mode), the

2.8

Power-up Delays

time-out sequence following a Power-on Reset is differ-

ent from other Oscillator modes. The time-out

sequence is as follows: First, the PWRT time-out is

invoked after a POR time delay has expired. Then, the

Oscillator Start-up Timer (OST) is invoked. However,

this is still not a sufficient amount of time to allow the

PLL to lock at high frequencies. The PWRT timer is

used to provide an additional fixed 2 ms (nominal)

time-out to allow the PLL ample time to lock to the

incoming clock frequency.

Power up delays are controlled by two timers, so that

no external RESET circuitry is required for most appli-

cations. The delays ensure that the device is kept in

RESET, until the device power supply and clock are

stable. For additional information on RESET operation,

see Section 3.0.

The first timer is the Power-up Timer (PWRT), which

optionally provides a fixed delay of 72 ms (nominal) on

power-up only (POR and BOR). The second timer is

the Oscillator Start-up Timer (OST), intended to keep

the chip in RESET until the crystal oscillator is stable.

DS39564C-page 24

PIC18FXX2

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal oper-

ation. Status bits from the RCON register, RI, TO, PD,

POR and BOR, are set or cleared differently in different

RESET situations, as indicated in Table 3-2. These bits

are used in software to determine the nature of the

RESET. See Table 3-3 for a full description of the

RESET states of all registers.

3.0

RESET

The PIC18FXXX differentiates between various kinds

of RESET:

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during SLEEP

d) Watchdog Timer (WDT) Reset (during normal

operation)

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 3-1.

e) Programmable Brown-out Reset (BOR)

f) RESETInstruction

The Enhanced MCU devices have a MCLR noise filter

in the MCLR Reset path. The filter will detect and

ignore small pulses.

g) Stack Full Reset

h) Stack Underflow Reset

The MCLR pin is not driven low by any internal

RESETS, including the WDT.

Most registers are unaffected by a RESET. Their status

is unknown on POR and unchanged by all other

RESETS. The other registers are forced to a “RESET

state” on Power-on Reset, MCLR, WDT Reset, Brown-

out Reset, MCLR Reset during SLEEP and by the

RESETinstruction.

FIGURE 3-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

External Reset

MCLR

SLEEP

WDT

Module

Time-out

Reset

VDD Rise

Detect

Power-on Reset

VDD

Brown-out

Reset

S

BOREN

OST/PWRT

OST

10-bit Ripple Counter

Chip_Reset

Q

R

OSC1

PWRT

10-bit Ripple Counter

On-chip

RC OSC⁽¹⁾

Enable PWRT

(2)

Enable OST

Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.

2: See Table 3-1 for time-out situations.

DS39564C-page 25

PIC18FXX2

3.1

Power-On Reset (POR)

3.3

Oscillator Start-up Timer (OST)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected. To take advantage of the POR cir-

cuitry, just tie the MCLR pin directly (or through a resis-

tor) to VDD. This will eliminate external RC components

usually needed to create a Power-on Reset delay. A

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over (parameter 32). This ensures that

the crystal oscillator or resonator has started and

stabilized.

minimum rise rate for

(parameter D004). For a slow rise time, see Figure 3-2.

VDD

is specified

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

When the device starts normal operation (i.e., exits the

RESET condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in RESET until the operating

conditions are met.

3.4

PLL Lock Time-out

With the PLL enabled, the time-out sequence following

a Power-on Reset is different from other Oscillator

modes. A portion of the Power-up Timer is used to pro-

vide a fixed time-out that is sufficient for the PLL to lock

to the main oscillator frequency. This PLL lock time-out

(TPLL) is typically 2 ms and follows the oscillator

start-up time-out (OST).

FIGURE 3-2:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

3.5

Brown-out Reset (BOR)

VDD

A configuration bit, BOREN, can disable (if clear/

programmed), or enable (if set) the Brown-out Reset

circuitry. If VDD falls below parameter D005 for greater

than parameter 35, the brown-out situation will reset

the chip. A RESET may not occur if VDD falls below

parameter D005 for less than parameter 35. The chip

will remain in Brown-out Reset until VDD rises above

BVDD. If the Power-up Timer is enabled, it will be

invoked after VDD rises above BVDD; it then will keep

the chip in RESET for an additional time delay

(parameter 33). If VDD drops below BVDD while the

Power-up Timer is running, the chip will go back into a

Brown-out Reset and the Power-up Timer will be initial-

ized. Once VDD rises above BVDD, the Power-up Timer

will execute the additional time delay.

D

R

R1

MCLR

PIC18FXXX

C

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

3.6

Time-out Sequence

3: R1 = 100Ω to 1 kΩ will limit any current flow-

ing into MCLR from external capacitor C, in

the event of MCLR/VPP pin breakdown due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS).

On power-up, the time-out sequence is as follows:

First, PWRT time-out is invoked after the POR time

delay has expired. Then, OST is activated. The total

time-out will vary based on oscillator configuration and

the status of the PWRT. For example, in RC mode with

the PWRT disabled, there will be no time-out at all.

Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and

Figure 3-7 depict time-out sequences on power-up.

3.2

Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out

(parameter 33) only on power-up from the POR. The

Power-up Timer operates on an internal RC oscillator.

The chip is kept in RESET as long as the PWRT is

active. The PWRT’s time delay allows VDD to rise to an

acceptable level. A configuration bit is provided to

enable/disable the PWRT.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire.

Bringing MCLR high will begin execution immediately

(Figure 3-5). This is useful for testing purposes or to

synchronize more than one PIC18FXXX device operat-

ing in parallel.

The power-up time delay will vary from chip-to-chip due

to VDD, temperature and process variation. See DC

parameter D033 for details.

Table 3-2 shows the RESET conditions for some

Special Function Registers, while Table 3-3 shows the

RESET conditions for all the registers.

DS39564C-page 26

PIC18FXX2

TABLE 3-1:

Oscillator

TIME-OUT IN VARIOUS SITUATIONS

Power-up⁽²⁾

Wake-up from

SLEEP or

Oscillator Switch

Brown-out

Configuration

PWRTE = 0

PWRTE = 1

72 ms + 1024 TOSC

+ 2ms

1024 TOSC

+ 2 ms

72 ms⁽²⁾+ 1024 TOSC

+ 2 ms

HS with PLL enabled⁽¹⁾

1024 TOSC + 2 ms

HS, XT, LP

EC

72 ms + 1024 TOSC

72 ms

1024 TOSC

72 ms⁽²⁾+ 1024 TOSC

72 ms⁽²⁾

1024 TOSC

—

External RC

72 ms

72 ms⁽²⁾

Note 1: 2 ms is the nominal time required for the 4x PLL to lock.

2: 72 ms is the nominal power-up timer delay, if implemented.

REGISTER 3-1:

RCON REGISTER BITS AND POSITIONS

R/W-0

IPEN

U-0

—

U-0

—

R/W-1

RI

R-1

TO

R-1

PD

R/W-0

POR

R/W-0

BOR

bit 7

bit 0

Note 1: Refer to Section 4.14 (page 53) for bit definitions.

TABLE 3-2:

STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR

RCON REGISTER

Program

Counter

RCON

Register

Condition

RI TO PD POR BOR STKFUL STKUNF

Power-on Reset

0000h

0--1 1100

0--u uuuu

1

u

1

u

1

u

0

u

0

u

MCLR Reset during normal

operation

Software Reset during normal

operation

0000h

0--0 uuuu

0--u uu11

0

u

1

u

1

u

Stack Full Reset during normal

operation

Stack Underflow Reset during

normal operation

MCLR Reset during SLEEP

WDT Reset

0000h

0--u 10uu

0--u 01uu

u--u 00uu

0--1 11u0

u--u 00uu

u

1

u

1

u

1

0

1

0

1

0

1

0

u

1

u

0

u

WDT Wake-up

PC + 2

Brown-out Reset

0000h

PC + 2⁽¹⁾

Interrupt wake-up from SLEEP

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as '0'

Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (0x000008h or 0x000018h).

DS39564C-page 27

PIC18FXX2

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Register

Applicable Devices

TOSU

242 442 252 452

---0 0000

0000 0000

00-0 0000

---0 0000

0000 0000

--00 0000

0000 0000

xxxx xxxx

0000 000x

1111 -1-1

11-0 0-00

N/A

---0 0000

0000 0000

uu-0 0000

---0 0000

0000 0000

--00 0000

0000 0000

uuuu uuuu

0000 000u

1111 -1-1

11-0 0-00

N/A

---0 uuuu⁽³⁾

uuuu uuuu⁽³⁾

uu-u uuuu⁽³⁾

---u uuuu

uuuu uuuu

PC + 2⁽²⁾

--uu uuuu

uuuu uuuu

uuuu uuuu⁽¹⁾

uuuu -u-u⁽¹⁾

uu-u u-uu⁽¹⁾

N/A

TOSH

TOSL

STKPTR

PCLATU

PCLATH

PCL

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

PRODH

PRODL

INTCON

INTCON2

INTCON3

INDF0

POSTINC0

N/A

POSTDEC0 242 442 252 452

N/A

PREINC0

PLUSW0

FSR0H

242 442 252 452

N/A

---- xxxx

xxxx xxxx

N/A

---- uuuu

uuuu uuuu

N/A

---- uuuu

uuuu uuuu

N/A

FSR0L

WREG

INDF1

POSTINC1

N/A

POSTDEC1 242 442 252 452

N/A

PREINC1

PLUSW1

242 442 252 452

N/A

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ’0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.

DS39564C-page 28

PIC18FXX2

TABLE 3-3:

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESET Instruction

Stack Resets

FSR1H

FSR1L

BSR

242 442 252 452

---- xxxx

xxxx xxxx

---- 0000

N/A

---- uuuu

uuuu uuuu

---- 0000

N/A

---- uuuu

uuuu uuuu

---- uuuu

N/A

INDF2

POSTINC2

N/A

POSTDEC2 242 442 252 452

N/A

PREINC2

PLUSW2

FSR2H

242 442 252 452

N/A

---- xxxx

xxxx xxxx

---x xxxx

0000 0000

xxxx xxxx

1111 1111

---- ---0

--00 0101

---- ---0

0--q 11qq

xxxx xxxx

0-00 0000

0000 0000

1111 1111

-000 0000

xxxx xxxx

0000 0000

---- uuuu

uuuu uuuu

---u uuuu

uuuu uuuu

1111 1111

---- ---0

--00 0101

---- ---0

0--q qquu

uuuu uuuu

u-uu uuuu

0000 0000

1111 1111

-000 0000

uuuu uuuu

0000 0000

---- uuuu

uuuu uuuu

---u uuuu

uuuu uuuu

---- ---u

--uu uuuu

---- ---u

u--u qquu

uuuu uuuu

u-uu uuuu

uuuu uuuu

1111 1111

-uuu uuuu

uuuu uuuu

FSR2L

STATUS

TMR0H

TMR0L

T0CON

OSCCON

LVDCON

WDTCON

RCON⁽⁴⁾

TMR1H

TMR1L

T1CON

TMR2

PR2

T2CON

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ’0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.

DS39564C-page 29

PIC18FXX2

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Register

Applicable Devices

ADRESH

ADRESL

ADCON0

ADCON1

CCPR1H

CCPR1L

CCP1CON

CCPR2H

CCPR2L

CCP2CON

TMR3H

242 442 252 452

xxxx xxxx

0000 00-0

00-- 0000

xxxx xxxx

--00 0000

xxxx xxxx

--00 0000

xxxx xxxx

0000 0000

0000 -010

0000 000x

0000 0000

xx-0 x000

---- ----

uuuu uuuu

0000 00-0

00-- 0000

uuuu uuuu

--00 0000

uuuu uuuu

--00 0000

uuuu uuuu

0000 0000

0000 -010

0000 000x

0000 0000

uu-0 u000

---- ----

uuuu uuuu

uuuu uu-u

uu-- uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

uuuu -uuu

uuuu uuuu

uu-0 u000

---- ----

TMR3L

T3CON

SPBRG

RCREG

TXREG

TXSTA

RCSTA

EEADR

EEDATA

EECON1

EECON2

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ’0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.

DS39564C-page 30

PIC18FXX2

TABLE 3-3:

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESET Instruction

Stack Resets

IPR2

PIR2

PIE2

242 442 252 452

---1 1111

---0 0000

1111 1111

-111 1111

0000 0000

-000 0000

0000 0000

-000 0000

0000 -111

1111 1111

-111 1111⁽⁵⁾

---- -xxx

xxxx xxxx

-xxx xxxx⁽⁵⁾

---- -000

xxxx xxxx

-x0x 0000⁽⁵⁾

---1 1111

---0 0000

1111 1111

-111 1111

0000 0000

-000 0000

0000 0000

-000 0000

0000 -111

1111 1111

-111 1111⁽⁵⁾

---- -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

---- -000

uuuu uuuu

-u0u 0000⁽⁵⁾

---u uuuu

---u uuuu⁽¹⁾

---u uuuu

uuuu uuuu

-uuu uuuu

uuuu uuuu⁽¹⁾

-uuu uuuu⁽¹⁾

uuuu uuuu

-uuu uuuu

uuuu -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

---- -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

---- -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

IPR1

PIR1

PIE1

TRISE

TRISD

TRISC

TRISB

TRISA^(5,6)

LATE

LATD

LATC

LATB

LATA^(5,6)

PORTE

PORTD

PORTC

PORTB

PORTA^(5,6)

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ’0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.

DS39564C-page 31

PIC18FXX2

FIGURE 3-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 3-4:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 3-5:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

DS39564C-page 32

PIC18FXX2

FIGURE 3-6:

SLOW RISE TIME (MCLR TIED TO VDD)

5V

1V

0V

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

FIGURE 3-7:

TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)

VDD

MCLR

IINTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

TPLL

PLL TIME-OUT

INTERNAL RESET

Note: TOST = 1024 clock cycles.

TPLL ≈ 2 ms max. First three stages of the PWRT timer.

DS39564C-page 33

PIC18FXX2

NOTES:

DS39564C-page 34

PIC18FXX2

4.0

MEMORY ORGANIZATION

There are three memory blocks in Enhanced MCU

devices. These memory blocks are:

• Program Memory

• Data RAM

• Data EEPROM

Data and program memory use separate busses,

which allows for concurrent access of these blocks.

Additional detailed information for FLASH program

memory and Data EEPROM is provided in Section 5.0

and Section 6.0, respectively.

4.1

Program Memory Organization

A 21-bit program counter is capable of addressing the

2-Mbyte program memory space. Accessing a location

between the physically implemented memory and the

2-Mbyte address will cause a read of all ’0’s (a NOP

instruction).

The PIC18F252 and PIC18F452 each have 32 Kbytes

of FLASH memory, while the PIC18F242 and

PIC18F442 have 16 Kbytes of FLASH. This means that

PIC18FX52 devices can store up to 16K of single word

instructions, and PIC18FX42 devices can store up to

8K of single word instructions.

The RESET vector address is at 0000h and the

interrupt vector addresses are at 0008h and 0018h.

Figure 4-1 shows the Program Memory Map for

PIC18F242/442 devices and Figure 4-2 shows the

Program Memory Map for PIC18F252/452 devices.

DS39564C-page 35

PIC18FXX2

FIGURE 4-1:

PROGRAM MEMORY MAP

AND STACK FOR

PIC18F442/242

FIGURE 4-2:

PROGRAM MEMORY MAP

AND STACK FOR

PIC18F452/252

PC<20:0>

21

CALL,RCALL,RETURN

RETFIE,RETLW

CALL,RCALL,RETURN

RETFIE,RETLW

Stack Level 1

•

Stack Level 31

RESET Vector

Stack Level 31

RESET Vector

0000h

High Priority Interrupt Vector

Low Priority Interrupt Vector

High Priority Interrupt Vector

Low Priority Interrupt Vector

0008h

0018h

0008h

0018h

On-Chip

Program Memory

3FFFh

4000h

On-Chip

Program Memory

7FFFh

8000h

Read '0'

1FFFFFh

200000h

1FFFFFh

200000h

DS39564C-page 36

PIC18FXX2

4.2.2

RETURN STACK POINTER

(STKPTR)

4.2

Return Address Stack

The return address stack allows any combination of up

to 31 program calls and interrupts to occur. The PC

(Program Counter) is pushed onto the stack when a

CALLor RCALLinstruction is executed, or an interrupt

is acknowledged. The PC value is pulled off the stack

on a RETURN, RETLW or a RETFIE instruction.

PCLATU and PCLATH are not affected by any of the

RETURNor CALLinstructions.

The STKPTR register contains the stack pointer value,

the STKFUL (stack full) status bit, and the STKUNF

(stack underflow) status bits. Register 4-1 shows the

STKPTR register. The value of the stack pointer can be

0 through 31. The stack pointer increments when val-

ues are pushed onto the stack and decrements when

values are popped off the stack. At RESET, the stack

pointer value will be 0. The user may read and write the

stack pointer value. This feature can be used by a Real

Time Operating System for return stack maintenance.

The stack operates as a 31-word by 21-bit RAM and a

5-bit stack pointer, with the stack pointer initialized to

00000b after all RESETS. There is no RAM associated

with stack pointer 00000b. This is only a RESET value.

During a CALLtype instruction, causing a push onto the

stack, the stack pointer is first incremented and the

RAM location pointed to by the stack pointer is written

with the contents of the PC. During a RETURN type

instruction, causing a pop from the stack, the contents

of the RAM location pointed to by the STKPTR are

transferred to the PC and then the stack pointer is

decremented.

After the PC is pushed onto the stack 31 times (without

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit can only be cleared in software or

by a POR.

The action that takes place when the stack becomes

full depends on the state of the STVREN (Stack Over-

flow Reset Enable) configuration bit. Refer to

Section 20.0 for a description of the device configura-

tion bits. If STVREN is set (default), the 31st push will

push the (PC + 2) value onto the stack, set the STKFUL

bit, and reset the device. The STKFUL bit will remain

set and the stack pointer will be set to ‘0’.

The stack space is not part of either program or data

space. The stack pointer is readable and writable, and

the address on the top of the stack is readable and writ-

able through SFR registers. Data can also be pushed

to, or popped from, the stack using the top-of-stack

SFRs. Status bits indicate if the stack pointer is at, or

beyond the 31 levels provided.

If STVREN is cleared, the STKFUL bit will be set on the

31st push and the stack pointer will increment to 31.

Any additional pushes will not overwrite the 31st push,

and STKPTR will remain at 31.

When the stack has been popped enough times to

unload the stack, the next pop will return a value of zero

to the PC and sets the STKUNF bit, while the stack

pointer remains at 0. The STKUNF bit will remain set

until cleared in software or a POR occurs.

4.2.1

TOP-OF-STACK ACCESS

The top of the stack is readable and writable. Three

register locations, TOSU, TOSH and TOSL hold the

contents of the stack location pointed to by the

STKPTR register. This allows users to implement a

software stack if necessary. After a CALL, RCALLor

interrupt, the software can read the pushed value by

reading the TOSU, TOSH and TOSL registers. These

values can be placed on a user defined software stack.

At return time, the software can replace the TOSU,

TOSH and TOSL and do a return.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the

program to the RESET vector, where the

stack conditions can be verified and

appropriate actions can be taken.

The user must disable the global interrupt enable bits

during this time to prevent inadvertent stack

operations.

DS39564C-page 37

PIC18FXX2

REGISTER 4-1:

STKPTR REGISTER

R/C-0 R/C-0

U-0

—

R/W-0

SP4

R/W-0

SP3

R/W-0

SP2

R/W-0

SP1

R/W-0

SP0

STKOVF STKUNF

bit 7

bit 0

bit 7⁽¹⁾

bit 6⁽¹⁾

STKOVF: Stack Full Flag bit

1= Stack became full or overflowed

0= Stack has not become full or overflowed

STKUNF: Stack Underflow Flag bit

1= Stack underflow occurred

0= Stack underflow did not occur

bit 5

Unimplemented: Read as '0'

bit 4-0

SP4:SP0: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

FIGURE 4-3:

RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

Return Address Stack

11111

11110

11101

STKPTR<4:0>

00010

TOSU

0x00

TOSH

0x1A

TOSL

0x34

00011

0x001A34 00010

0x000D58 00001

00000

Top of Stack

4.2.3

PUSH AND POP INSTRUCTIONS

4.2.4

STACK FULL/UNDERFLOW RESETS

Since the Top-of-Stack (TOS) is readable and writable,

the ability to push values onto the stack and pull values

off the stack without disturbing normal program execu-

tion is a desirable option. To push the current PC value

onto the stack, a PUSH instruction can be executed.

This will increment the stack pointer and load the cur-

rent PC value onto the stack. TOSU, TOSH and TOSL

can then be modified to place a return address on the

stack.

These resets are enabled by programming the

STVREN configuration bit. When the STVREN bit is

disabled, a full or underflow condition will set the appro-

priate STKFUL or STKUNF bit, but not cause a device

RESET. When the STVREN bit is enabled, a full or

underflow will set the appropriate STKFUL or STKUNF

bit and then cause a device RESET. The STKFUL or

STKUNF bits are only cleared by the user software or

a POR Reset.

The ability to pull the TOS value off of the stack and

replace it with the value that was previously pushed

onto the stack, without disturbing normal execution, is

achieved by using the POPinstruction. The POPinstruc-

tion discards the current TOS by decrementing the

stack pointer. The previous value pushed onto the

stack then becomes the TOS value.

DS39564C-page 38

PIC18FXX2

4.3

Fast Register Stack

4.4

PCL, PCLATH and PCLATU

A “fast interrupt return” option is available for interrupts.

A Fast Register Stack is provided for the STATUS,

WREG and BSR registers and are only one in depth.

The stack is not readable or writable and is loaded with

the current value of the corresponding register when

the processor vectors for an interrupt. The values in the

registers are then loaded back into the working regis-

ters, if the FAST RETURNinstruction is used to return

from the interrupt.

The program counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21-bits

wide. The low byte is called the PCL register. This reg-

ister is readable and writable. The high byte is called

the PCH register. This register contains the PC<15:8>

bits and is not directly readable or writable. Updates to

the PCH register may be performed through the

PCLATH register. The upper byte is called PCU. This

register contains the PC<20:16> bits and is not directly

readable or writable. Updates to the PCU register may

be performed through the PCLATU register.

A low or high priority interrupt source will push values

into the stack registers. If both low and high priority

interrupts are enabled, the stack registers cannot be

used reliably for low priority interrupts. If a high priority

interrupt occurs while servicing a low priority interrupt,

the stack register values stored by the low priority inter-

rupt will be overwritten.

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the LSB of PCL is fixed to a value of ’0’.

The PC increments by 2 to address sequential

instructions in the program memory.

If high priority interrupts are not disabled during low pri-

ority interrupts, users must save the key registers in

software during a low priority interrupt.

The CALL, RCALL, GOTO and program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

If no interrupts are used, the fast register stack can be

used to restore the STATUS, WREG and BSR registers

at the end of a subroutine call. To use the fast register

stack for a subroutine call, a FAST CALL instruction

must be executed.

The contents of PCLATH and PCLATU will be trans-

ferred to the program counter by an operation that

writes PCL. Similarly, the upper two bytes of the pro-

gram counter will be transferred to PCLATH and

PCLATU by an operation that reads PCL. This is useful

for computed offsets to the PC (see Section 4.8.1).

Example 4-1 shows a source code example that uses

the fast register stack.

4.5

Clocking Scheme/Instruction

Cycle

EXAMPLE 4-1:

FAST REGISTER STACK

CODE EXAMPLE

CALL SUB1, FAST

;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-

gram counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clocks and instruction execution flow

are shown in Figure 4-4.

•

SUB1

•

RETURN FAST

;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

FIGURE 4-4:

CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Internal

Phase

Clock

Q4

PC

PC+2

PC+4

PC

OSC2/CLKO

(RC mode)

Execute INST (PC-2)

Fetch INST (PC)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+2)

Fetch INST (PC+4)

DS39564C-page 39

PIC18FXX2

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

4.6

Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO)

then two cycles are required to complete the instruction

(Example 4-2).

In the execution cycle, the fetched instruction is latched

into the “Instruction Register” (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

EXAMPLE 4-2:

INSTRUCTION PIPELINE FLOW

TCY0

TCY1

TCY2

TCY3

TCY4

TCY5

1. MOVLW 55h

2. MOVWF PORTB

3. BRA SUB_1

Fetch 1

Execute 1

Fetch 2

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

PORTA, BIT3 (Forced NOP)

Flush (NOP)

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction

is “flushed” from the pipeline while the new instruction is being fetched and then executed.

The CALLand GOTOinstructions have an absolute pro-

4.7

Instructions in Program Memory

gram memory address embedded into the instruction.

Since instructions are always stored on word bound-

aries, the data contained in the instruction is a word

address. The word address is written to PC<20:1>,

which accesses the desired byte address in program

memory. Instruction #2 in Figure 4-5 shows how the

instruction “GOTO 000006h’ is encoded in the program

memory. Program branch instructions which encode a

relative address offset operate in the same manner.

The offset value stored in a branch instruction repre-

sents the number of single word instructions that the

PC will be offset by. Section 20.0 provides further

details of the instruction set.

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte of an instruction

word is always stored in a program memory location

with an even address (LSB =’0’). Figure 4-5 shows an

example of how instruction words are stored in the pro-

gram memory. To maintain alignment with instruction

boundaries, the PC increments in steps of 2 and the

LSB will always read ’0’ (see Section 4.4).

FIGURE 4-5:

INSTRUCTIONS IN PROGRAM MEMORY

Word Address

LSB = 1

LSB = 0

↓

Program Memory

^{Byte Locations}→

000000h

000002h

000004h

000006h

000008h

00000Ah

00000Ch

00000Eh

000010h

000012h

000014h

Instruction 1:

Instruction 2:

0Fh

EFh

F0h

C1h

F4h

55h

03h

00h

23h

56h

MOVLW

GOTO

055h

000006h

Instruction 3:

MOVFF

123h, 456h

DS39564C-page 40

PIC18FXX2

second word of the instruction is executed by itself (first

word was skipped), it will execute as a NOP. This action

is necessary when the two-word instruction is preceded

by a conditional instruction that changes the PC. A pro-

gram example that demonstrates this concept is shown

in Example 4-3. Refer to Section 20.0 for further details

of the instruction set.

4.7.1

TWO-WORD INSTRUCTIONS

The PIC18FXX2 devices have four two-word instruc-

tions: MOVFF, CALL, GOTOand LFSR. The second

word of these instructions has the 4 MSBs set to 1’s

and is a special kind of NOPinstruction. The lower 12

bits of the second word contain data to be used by the

instruction. If the first word of the instruction is exe-

cuted, the data in the second word is accessed. If the

EXAMPLE 4-3:

TWO-WORD INSTRUCTIONS

Source Code

CASE 1:

Object Code

0110 0110 0000 0000 TSTFSZ

REG1

; is RAM location 0?

1100 0001 0010 0011

1111 0100 0101 0110

0010 0100 0000 0000

MOVFF

ADDWF

REG1, REG2 ; No, execute 2-word instruction

; 2nd operand holds address of REG2

REG3

; continue code

CASE 2:

Object Code

Source Code

TSTFSZ

0110 0110 0000 0000

1100 0001 0010 0011

1111 0100 0101 0110

0010 0100 0000 0000

REG1

; is RAM location 0?

MOVFF

REG1, REG2 ; Yes

; 2nd operand becomes NOP

REG3 ; continue code

ADDWF

4.8.2

TABLE READS/TABLE WRITES

4.8

Lookup Tables

A better method of storing data in program memory

allows 2 bytes of data to be stored in each instruction

location.

Lookup tables are implemented two ways. These are:

• Computed GOTO

• Table Reads

Lookup table data may be stored 2 bytes per program

word by using table reads and writes. The table pointer

(TBLPTR) specifies the byte address and the table

latch (TABLAT) contains the data that is read from, or

written to program memory. Data is transferred to/from

program memory, one byte at a time.

4.8.1

COMPUTED GOTO

A computed GOTOis accomplished by adding an offset

to the program counter (ADDWF PCL).

A lookup table can be formed with an ADDWF PCL

instruction and a group of RETLW 0xnn instructions.

WREG is loaded with an offset into the table before

executing a call to that table. The first instruction of the

called routine is the ADDWF PCLinstruction. The next

instruction executed will be one of the RETLW 0xnn

instructions, that returns the value 0xnnto the calling

function.

A description of the Table Read/Table Write operation

is shown in Section 3.0.

The offset value (value in WREG) specifies the number

of bytes that the program counter should advance.

In this method, only one data byte may be stored in

each instruction location and room on the return

address stack is required.

Note: The ADDWF PCL instruction does not

update PCLATH and PCLATU. A read

operation on PCL must be performed to

update PCLATH and PCLATU.

DS39564C-page 41

PIC18FXX2

4.9.1

GENERAL PURPOSE REGISTER

FILE

4.9

Data Memory Organization

The data memory is implemented as static RAM. Each

register in the data memory has a 12-bit address,

allowing up to 4096 bytes of data memory. Figure 4-6

and Figure 4-7 show the data memory organization for

the PIC18FXX2 devices.

The register file can be accessed either directly or indi-

rectly. Indirect addressing operates using a File Select

Register and corresponding Indirect File Operand. The

operation of indirect addressing is shown in

Section 4.12.

The data memory map is divided into as many as 16

banks that contain 256 bytes each. The lower 4 bits of

the Bank Select Register (BSR<3:0>) select which

bank will be accessed. The upper 4 bits for the BSR are

not implemented.

Enhanced MCU devices may have banked memory in

the GPR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other RESETS.

Data RAM is available for use as GPR registers by all

instructions. The top half of Bank 15 (0xF80 to 0xFFF)

contains SFRs. All other banks of data memory contain

GPR registers, starting with Bank 0.

The data memory contains Special Function Registers

(SFR) and General Purpose Registers (GPR). The

SFRs are used for control and status of the controller

and peripheral functions, while GPRs are used for data

storage and scratch pad operations in the user’s appli-

cation. The SFRs start at the last location of Bank 15

(0xFFF) and extend downwards. Any remaining space

beyond the SFRs in the Bank may be implemented as

GPRs. GPRs start at the first location of Bank 0 and

grow upwards. Any read of an unimplemented location

will read as ’0’s.

4.9.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and Peripheral Modules for control-

ling the desired operation of the device. These regis-

ters are implemented as static RAM. A list of these

registers is given in Table 4-1 and Table 4-2.

The SFRs can be classified into two sets; those asso-

ciated with the “core” function and those related to the

peripheral functions. Those registers related to the

“core” are described in this section, while those related

to the operation of the peripheral features are

described in the section of that peripheral feature.

The entire data memory may be accessed directly or

indirectly. Direct addressing may require the use of the

BSR register. Indirect addressing requires the use of a

File Select Register (FSRn) and a corresponding Indi-

rect File Operand (INDFn). Each FSR holds a 12-bit

address value that can be used to access any location

in the Data Memory map without banking.

The SFRs are typically distributed among the

peripherals whose functions they control.

The instruction set and architecture allow operations

across all banks. This may be accomplished by indirect

addressing or by the use of the MOVFFinstruction. The

MOVFF instruction is a two-word/two-cycle instruction

that moves a value from one register to another.

The unused SFR locations will be unimplemented and

read as '0's. See Table 4-1 for addresses for the SFRs.

To ensure that commonly used registers (SFRs and

select GPRs) can be accessed in a single cycle,

regardless of the current BSR values, an Access Bank

is implemented. A segment of Bank 0 and a segment of

Bank 15 comprise the Access RAM. Section 4.10

provides a detailed description of the Access RAM.

DS39564C-page 42

PIC18FXX2

FIGURE 4-6:

BSR<3:0>

DATA MEMORY MAP FOR PIC18F242/442

Data Memory Map

000h

00h

Access RAM

GPR

= 0000

07Fh

080h

0FFh

100h

Bank 0

FFh

00h

= 0001

= 0010

GPR

Bank 1

Bank 2

1FFh

200h

FFh

00h

FFh

2FFh

300h

Access Bank

00h

Access RAM low

7Fh

= 0011

= 1110

80h

Access RAM high

(SFRs)

Bank 3

to

Bank 14

Unused

Read ’00h’

FFh

When a = 0,

the BSR is ignored and the

Access Bank is used.

The first 128 bytes are General

Purpose RAM (from Bank 0).

The second 128 bytes are

Special Function Registers

(from Bank 15).

EFFh

F00h

F7Fh

F80h

FFFh

00h

FFh

Unused

SFR

= 1111

Bank 15

When a = 1,

the BSR is used to specify the

RAM location that the

instruction uses.

DS39564C-page 43

PIC18FXX2

FIGURE 4-7:

DATA MEMORY MAP FOR PIC18F252/452

BSR<3:0>

Data Memory Map

000h

00h

Access RAM

GPR

= 0000

07Fh

Bank 0

080h

FFh

00h

0FFh

100h

= 0001

= 0010

GPR

Bank 1

Bank 2

Bank 3

FFh

00h

1FFh

200h

FFh

00h

2FFh

300h

= 0011

= 0100

= 0101

GPR

FFh

3FFh

400h

Bank 4

Bank 5

GPR

Access Bank

4FFh

500h

00h

Access RAM low

00h

FFh

7Fh

80h

Access RAM high

(SFR’s)

5FFh

600h

FFh

When a = 0,

the BSR is ignored and the

Access Bank is used.

The first 128 bytes are General

Purpose RAM (from Bank 0).

The second 128 bytes are

Special Function Registers

(from Bank 15).

= 0110

= 1110

Bank 6

to

Unused

Read ’00h’

Bank 14

EFFh

F00h

00h

FFh

Unused

SFR

= 1111

F7Fh

Bank 15

F80h

FFFh

When a = 1,

the BSR is used to specify the

RAM location that the

instruction uses.

DS39564C-page 44

PIC18FXX2

TABLE 4-1:

SPECIAL FUNCTION REGISTER MAP

Address

FFFh

FFEh

FFDh

FFCh

FFBh

FFAh

FF9h

FF8h

FF7h

FF6h

FF5h

FF4h

FF3h

FF2h

FF1h

FF0h

FEFh

Name

TOSU

Address

FDFh

Name

INDF2⁽³⁾

POSTINC2⁽³⁾

Address

FBFh

FBEh

FBDh

FBCh

FBBh

FBAh

FB9h

FB8h

FB7h

FB6h

FB5h

FB4h

FB3h

FB2h

FB1h

FB0h

FAFh

FAEh

FADh

FACh

FABh

FAAh

FA9h

FA8h

FA7h

FA6h

FA5h

FA4h

FA3h

FA2h

FA1h

FA0h

Name

CCPR1H

CCPR1L

CCP1CON

CCPR2H

CCPR2L

CCP2CON

—

Address

F9Fh

F9Eh

F9Dh

F9Ch

F9Bh

F9Ah

F99h

F98h

F97h

F96h

F95h

F94h

F93h

F92h

F91h

F90h

F8Fh

F8Eh

F8Dh

F8Ch

F8Bh

F8Ah

F89h

F88h

F87h

F86h

F85h

F84h

F83h

F82h

F81h

F80h

Name

IPR1

PIR1

PIE1

—

TOSH

FDEh

TOSL

FDDh POSTDEC2⁽³⁾

STKPTR

PCLATU

PCLATH

PCL

FDCh

FDBh

FDAh

FD9h

FD8h

FD7h

FD6h

FD5h

FD4h

FD3h

FD2h

FD1h

FD0h

FCFh

FCEh

FCDh

FCCh

FCBh

FCAh

FC9h

FC8h

FC7h

FC6h

FC5h

FC4h

FC3h

FC2h

FC1h

FC0h

PREINC2⁽³⁾

PLUSW2⁽³⁾

FSR2H

—

FSR2L

—

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

PRODH

PRODL

INTCON

INTCON2

INTCON3

INDF0⁽³⁾

STATUS

TMR0H

TMR0L

—

TRISE⁽²⁾

TRISD⁽²⁾

TRISC

TRISB

TRISA

—

T0CON

—

OSCCON

LVDCON

WDTCON

RCON

TMR3H

TMR3L

T3CON

—

TMR1H

TMR1L

SPBRG

RCREG

TXREG

TXSTA

RCSTA

—

FEEh POSTINC0⁽³⁾

FEDh POSTDEC0⁽³⁾

—

T1CON

TMR2

LATE⁽²⁾

LATD⁽²⁾

LATC

LATB

LATA

—

FECh

FEBh

FEAh

FE9h

FE8h

FE7h

PREINC0⁽³⁾

PLUSW0⁽³⁾

FSR0H

PR2

T2CON

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

ADRESH

ADRESL

ADCON0

ADCON1

—

FSR0L

EEADR

EEDATA

EECON2

EECON1

—

WREG

INDF1⁽³⁾

—

FE6h POSTINC1⁽³⁾

FE5h POSTDEC1⁽³⁾

—

FE4h

FE3h

FE2h

FE1h

FE0h

PREINC1⁽³⁾

PLUSW1⁽³⁾

FSR1H

—

PORTE⁽²⁾

PORTD⁽²⁾

PORTC

PORTB

PORTA

—

IPR2

FSR1L

PIR2

BSR

PIE2

Note 1: Unimplemented registers are read as ’0’.

2: This register is not available on PIC18F2X2 devices.

3: This is not a physical register.

DS39564C-page 45

PIC18FXX2

TABLE 4-2:

REGISTER FILE SUMMARY

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TOSU

—

Top-of-Stack upper Byte (TOS<20:16>)

---0 0000

0000 0000

00-0 0000

---0 0000

0000 0000

37

38

39

58

71

75

76

77

50

TOSH

Top-of-Stack High Byte (TOS<15:8>)

Top-of-Stack Low Byte (TOS<7:0>)

TOSL

STKPTR

PCLATU

PCLATH

PCL

STKFUL

—

STKUNF

—

Return Stack Pointer

Holding Register for PC<20:16>

Holding Register for PC<15:8>

PC Low Byte (PC<7:0>)

(2)

TBLPTRU

—

bit21

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000

TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

0000 0000

xxxx xxxx

0000 000x

1111 -1-1

11-0 0-00

n/a

TBLPTRL

TABLAT

PRODH

PRODL

Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

Program Memory Table Latch

Product Register High Byte

Product Register Low Byte

INTCON

INTCON2

INTCON3

INDF0

GIE/GIEH PEIE/GIEL

TMR0IE

INTEDG0 INTEDG1 INTEDG2

INT1IP INT2IE

INT0IE

RBIE

—

TMR0IF

TMR0IP

—

INT0IF

—

RBIF

RBIP

RBPU

INT2IP

—

INT1IE

INT2IF

INT1IF

Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)

POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)

POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register)

n/a

PREINC0

PLUSW0

Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)

n/a

Uses contents of FSR0 to address data memory - value of FSR0 (not a physical register).

Offset by value in WREG.

n/a

FSR0H

FSR0L

WREG

INDF1

—

Indirect Data Memory Address Pointer 0 High Byte ---- 0000

50

n/a

50

Indirect Data Memory Address Pointer 0 Low Byte

Working Register

xxxx xxxx

Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)

n/a

POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register)

POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register)

PREINC1

PLUSW1

Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)

Uses contents of FSR1 to address data memory - value of FSR1 (not a physical register).

Offset by value in WREG.

FSR1H

FSR1L

BSR

—

Indirect Data Memory Address Pointer 1 High Byte ---- 0000

50

49

50

Indirect Data Memory Address Pointer 1 Low Byte

xxxx xxxx

—

Bank Select Register

---- 0000

INDF2

Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)

n/a

POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)

POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register)

PREINC2

PLUSW2

Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)

Uses contents of FSR2 to address data memory - value of FSR2 (not a physical register).

Offset by value in WREG.

FSR2H

FSR2L

STATUS

TMR0H

TMR0L

T0CON

—

Indirect Data Memory Address Pointer 2 High Byte ---- 0000

50

Indirect Data Memory Address Pointer 2 Low Byte

xxxx xxxx

—

N

OV

Z

DC

C

---x xxxx

0000 0000

xxxx xxxx

1111 1111

52

Timer0 Register High Byte

Timer0 Register Low Byte

105

103

TMR0ON

T08BIT

T0CS

T0SE

PSA

T0PS2

T0PS1

T0PS0

Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.

3: These registers and bits are reserved on the PIC18F2X2 devices; always maintain these clear.

DS39564C-page 46

PIC18FXX2

TABLE 4-2:

REGISTER FILE SUMMARY (CONTINUED)

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCCON

LVDCON

WDTCON

RCON

—

IRVST

—

LVDEN

—

LVDL3

—

LVDL2

—

LVDL1

—

SCS

---- ---0

--00 0101

21

LVDL0

191

203

—

SWDTE ---- ---0

BOR

IPEN

—

RI

TO

PD

POR

0--1 11qq 53, 28, 84

TMR1H

Timer1 Register High Byte

Timer1 Register Low Byte

xxxx xxxx

107

111

112

111

125

134

126

127

137

TMR1L

T1CON

RD16

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS TMR1ON 0-00 0000

0000 0000

TMR2

Timer2 Register

PR2

Timer2 Period Register

1111 1111

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

ADRESH

ADRESL

ADCON0

ADCON1

CCPR1H

CCPR1L

CCP1CON

CCPR2H

CCPR2L

CCP2CON

TMR3H

SSP Receive Buffer/Transmit Register

2

xxxx xxxx

0000 0000

2

SSP Address Register in I C Slave mode. SSP Baud Rate Reload Register in I C Master mode.

SMP

WCOL

GCEN

CKE

D/A

P

S

R/W

SSPM2

PEN

UA

BF

SSPOV

ACKSTAT

SSPEN

ACKDT

CKP

SSPM3

RCEN

SSPM1

RSEN

SSPM0 0000 0000

ACKEN

SEN

0000 0000

A/D Result Register High Byte

A/D Result Register Low Byte

xxxx xxxx 187,188

ADCS1

ADFM

ADCS0

ADCS2

CHS2

—

CHS1

—

CHS0

GO/DONE

PCFG2

—

ADON

0000 00-0

181

182

PCFG3

PCFG1

PCFG0 00-- 0000

Capture/Compare/PWM Register1 High Byte

Capture/Compare/PWM Register1 Low Byte

xxxx xxxx 121, 123

—

DC1B1

DC1B0

CCP1M3

CCP2M3

T3CCP1

CCP1M2

CCP2M2

T3SYNC

CCP1M1

CCP2M1

CCP1M0 --00 0000

117

xxxx xxxx 121, 123

Capture/Compare/PWM Register2 High Byte

Capture/Compare/PWM Register2 Low Byte

—

DC2B1

DC2B0

CCP2M0 --00 0000

117

113

168

Timer3 Register High Byte

Timer3 Register Low Byte

xxxx xxxx

TMR3L

T3CON

RD16

T3CCP2

T3CKPS1 T3CKPS0

TMR3CS TMR3ON 0000 0000

SPBRG

RCREG

USART1 Baud Rate Generator

USART1 Receive Register

0000 0000

0000 0000 175, 178,

180

TXREG

USART1 Transmit Register

0000 0000 173, 176,

179

TXSTA

CSRC

SPEN

TX9

RX9

TXEN

SREN

SYNC

CREN

—

BRGH

FERR

TRMT

OERR

TX9D

RX9D

0000 -010

0000 000x

166

167

RCSTA

ADDEN

EEADR

EEDATA

EECON2

EECON1

Data EEPROM Address Register

Data EEPROM Data Register

0000 0000 65, 69

0000 0000 69

---- ---- 65, 69

xx-0 x000 66

Data EEPROM Control Register 2 (not a physical register)

EEPGD CFGS FREE WRERR

—

WREN

WR

RD

Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.

3: These registers and bits are reserved on the PIC18F2X2 devices; always maintain these clear.

DS39564C-page 47

PIC18FXX2

TABLE 4-2:

REGISTER FILE SUMMARY (CONTINUED)

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IPR2

PIR2

PIE2

—

EEIP

EEIF

BCLIP

BCLIF

BCLIE

SSPIP

SSPIF

SSPIE

—

LVDIP

LVDIF

TMR3IP

TMR3IF

TMR3IE

TMR2IP

TMR2IF

TMR2IE

CCP2IP ---1 1111

CCP2IF ---0 0000

CCP2IE ---0 0000

TMR1IP 1111 1111

TMR1IF 0000 0000

TMR1IE 0000 0000

83

79

81

82

78

80

98

96

93

90

87

99

—

EEIE

LVDIE

(3)

IPR1

PIR1

PIE1

PSPIP

PSPIF

PSPIE

IBF

ADIP

ADIF

ADIE

OBF

RCIP

RCIF

RCIE

IBOV

TXIP

CCP1IP

CCP1IF

CCP1IE

(3)

TXIF

TXIE

(3)

TRISE

PSPMODE

Data Direction bits for PORTE

0000 -111

1111 1111

-111 1111

---- -xxx

TRISD

TRISC

TRISB

TRISA

Data Direction Control Register for PORTD

Data Direction Control Register for PORTC

Data Direction Control Register for PORTB

(1)

—

TRISA6

—

Data Direction Control Register for PORTA

(3)

LATE

—

Read PORTE Data Latch,

Write PORTE Data Latch

(3)

LATD

LATC

LATB

LATA

Read PORTD Data Latch, Write PORTD Data Latch

Read PORTC Data Latch, Write PORTC Data Latch

xxxx xxxx

-xxx xxxx

---- -000

xxxx xxxx

-x0x 0000

95

93

90

87

99

95

93

90

87

Read PORTB Data Latch, Write PORTB Data Latch

(1)

—

LATA6

Read PORTA Data Latch, Write PORTA Data Latch

(3)

PORTE

Read PORTE pins, Write PORTE Data Latch

Read PORTD pins, Write PORTD Data Latch

Read PORTC pins, Write PORTC Data Latch

PORTD

PORTC

PORTB

PORTA

Read PORTB pins, Write PORTB Data Latch

(1)

—

RA6

Read PORTA pins, Write PORTA Data Latch

Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.

3: These registers and bits are reserved on the PIC18F2X2 devices; always maintain these clear.

DS39564C-page 48

PIC18FXX2

4.10

Access Bank

4.11 Bank Select Register (BSR)

The Access Bank is an architectural enhancement

which is very useful for C compiler code optimization.

The techniques used by the C compiler may also be

useful for programs written in assembly.

The need for a large general purpose memory space

dictates a RAM banking scheme. The data memory is

partitioned into sixteen banks. When using direct

addressing, the BSR should be configured for the

desired bank.

This data memory region can be used for:

BSR<3:0> holds the upper 4 bits of the 12-bit RAM

address. The BSR<7:4> bits will always read ’0’s, and

writes will have no effect.

• Intermediate computational values

• Local variables of subroutines

• Faster context saving/switching of variables

• Common variables

A

MOVLB instruction has been provided in the

instruction set to assist in selecting banks.

• Faster evaluation/control of SFRs (no banking)

If the currently selected bank is not implemented, any

read will return all '0's and all writes are ignored. The

STATUS register bits will be set/cleared as appropriate

for the instruction performed.

The Access Bank is comprised of the upper 128 bytes

in Bank 15 (SFRs) and the lower 128 bytes in Bank 0.

These two sections will be referred to as Access RAM

High and Access RAM Low, respectively. Figure 4-6

and Figure 4-7 indicate the Access RAM areas.

Each Bank extends up to FFh (256 bytes). All data

memory is implemented as static RAM.

A bit in the instruction word specifies if the operation is

to occur in the bank specified by the BSR register or in

the Access Bank. This bit is denoted by the ’a’ bit (for

access bit).

A MOVFFinstruction ignores the BSR, since the 12-bit

addresses are embedded into the instruction word.

Section 4.12 provides a description of indirect address-

ing, which allows linear addressing of the entire RAM

space.

When forced in the Access Bank (a = 0), the last

address in Access RAM Low is followed by the first

address in Access RAM High. Access RAM High maps

the Special Function registers, so that these registers

can be accessed without any software overhead. This is

useful for testing status flags and modifying control bits.

FIGURE 4-8:

DIRECT ADDRESSING

Direct Addressing

(3)

From Opcode

BSR<3:0>

7

0

(2)

(3)

Bank Select

Location Select

00h

01h

100h

0Eh

E00h

0Fh

F00h

000h

Data

Memory⁽¹⁾

0FFh

1FFh

EFFh

FFFh

Bank 0

Bank 1

Bank 14 Bank 15

Note 1: For register file map detail, see Table 4-1.

2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the

registers of the Access Bank.

3: The MOVFFinstruction embeds the entire 12-bit address in the instruction.

DS39564C-page 49

PIC18FXX2

the data from the address pointed to by

FSR1H:FSR1L. INDFn can be used in code anywhere

an operand can be used.

4.12 Indirect Addressing, INDF and

FSR Registers

Indirect addressing is a mode of addressing data mem-

ory, where the data memory address in the instruction

is not fixed. An FSR register is used as a pointer to the

data memory location that is to be read or written. Since

this pointer is in RAM, the contents can be modified by

the program. This can be useful for data tables in the

data memory and for software stacks. Figure 4-9

shows the operation of indirect addressing. This shows

the moving of the value to the data memory address

specified by the value of the FSR register.

If INDF0, INDF1 or INDF2 are read indirectly via an

FSR, all '0's are read (zero bit is set). Similarly, if

INDF0, INDF1 or INDF2 are written to indirectly, the

operation will be equivalent to a NOPinstruction and the

STATUS bits are not affected.

4.12.1

INDIRECT ADDRESSING

OPERATION

Each FSR register has an INDF register associated

with it, plus four additional register addresses. Perform-

ing an operation on one of these five registers deter-

mines how the FSR will be modified during indirect

addressing.

Indirect addressing is possible by using one of the

INDF registers. Any instruction using the INDF register

actually accesses the register pointed to by the File

Select Register, FSR. Reading the INDF register itself,

indirectly (FSR = 0), will read 00h. Writing to the INDF

register indirectly, results in a no operation. The FSR

register contains a 12-bit address, which is shown in

Figure 4-10.

When data access is done to one of the five INDFn

locations, the address selected will configure the FSRn

register to:

• Do nothing to FSRn after an indirect access (no

change) - INDFn

The INDFn register is not a physical register. Address-

ing INDFn actually addresses the register whose

address is contained in the FSRn register (FSRn is a

pointer). This is indirect addressing.

• Auto-decrement FSRn after an indirect access

(post-decrement) - POSTDECn

• Auto-increment FSRn after an indirect access

(post-increment) - POSTINCn

Example 4-4 shows a simple use of indirect addressing

to clear the RAM in Bank1 (locations 100h-1FFh) in a

minimum number of instructions.

• Auto-increment FSRn before an indirect access

(pre-increment) - PREINCn

• Use the value in the WREG register as an offset

to FSRn. Do not modify the value of the WREG or

the FSRn register after an indirect access (no

change) - PLUSWn

EXAMPLE 4-4:

HOW TO CLEAR RAM

(BANK1) USING INDIRECT

ADDRESSING

LFSR FSR0 ,0x100

CLRF POSTINC0

;

When using the auto-increment or auto-decrement fea-

tures, the effect on the FSR is not reflected in the

STATUS register. For example, if the indirect address

causes the FSR to equal '0', the Z bit will not be set.

; register and

; inc pointer

; All done with

; Bank1?

BTFSS FSR0H, 1

GOTO NEXT

Incrementing or decrementing an FSR affects all 12

bits. That is, when FSRnL overflows from an increment,

FSRnH will be incremented automatically.

; NO, clear next

; YES, continue

CONTINUE

Adding these features allows the FSRn to be used as a

stack pointer, in addition to its uses for table operations

in data memory.

There are three indirect addressing registers. To

address the entire data memory space (4096 bytes),

these registers are 12-bit wide. To store the 12-bits of

addressing information, two 8-bit registers are

required. These indirect addressing registers are:

Each FSR has an address associated with it that per-

forms an indexed indirect access. When a data access

to this INDFn location (PLUSWn) occurs, the FSRn is

configured to add the signed value in the WREG regis-

ter and the value in FSR to form the address before an

indirect access. The FSR value is not changed.

1. FSR0: composed of FSR0H:FSR0L

2. FSR1: composed of FSR1H:FSR1L

3. FSR2: composed of FSR2H:FSR2L

If an FSR register contains a value that points to one of

the INDFn, an indirect read will read 00h (zero bit is

set), while an indirect write will be equivalent to a NOP

(STATUS bits are not affected).

In addition, there are registers INDF0, INDF1 and

INDF2, which are not physically implemented. Reading

or writing to these registers activates indirect address-

ing, with the value in the corresponding FSR register

being the address of the data. If an instruction writes a

value to INDF0, the value will be written to the address

pointed to by FSR0H:FSR0L. A read from INDF1 reads

If an indirect addressing operation is done where the

target address is an FSRnH or FSRnL register, the

write operation will dominate over the pre- or

post-increment/decrement functions.

DS39564C-page 50

PIC18FXX2

FIGURE 4-9:

INDIRECT ADDRESSING OPERATION

0h

RAM

Instruction

Executed

Opcode

Address

12

FFFh

File Address = access of an indirect addressing register

BSR<3:0>

12

Instruction

Fetched

4

8

Opcode

File

FSR

FIGURE 4-10:

INDIRECT ADDRESSING

Indirect Addressing

11

FSR Register

0

Location Select

0000h

Data

Memory⁽¹⁾

0FFFh

Note 1: For register file map detail, see Table 4-1.

DS39564C-page 51

PIC18FXX2

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

4.13 STATUS Register

The STATUS register, shown in Register 4-2, contains

the arithmetic status of the ALU. The STATUS register

can be the destination for any instruction, as with any

other register. If the STATUS register is the destination

for an instruction that affects the Z, DC, C, OV, or N bits,

then the write to these five bits is disabled. These bits

are set or cleared according to the device logic. There-

fore, the result of an instruction with the STATUS

register as destination may be different than intended.

It is recommended, therefore, that only BCF, BSF,

SWAPF, MOVFF and MOVWF instructions are used to

alter the STATUS register, because these instructions

do not affect the Z, C, DC, OV, or Nbits from the

STATUS register. For other instructions not affecting

any status bits, see Table 20-2.

Note: The C and DC bits operate as a borrow and

digit borrow bit respectively, in subtraction.

REGISTER 4-2:

STATUS REGISTER

U-0

—

U-0

—

U-0

—

R/W-x

N

R/W-x

OV

R/W-x

Z

R/W-x

DC

R/W-x

C

bit 7

bit 0

bit 7-5

bit 4

Unimplemented: Read as '0'

N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was

negative (ALU MSB = 1).

1= Result was negative

0= Result was positive

bit 3

OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the

7-bit magnitude, which causes the sign bit (bit7) to change state.

1= Overflow occurred for signed arithmetic (in this arithmetic operation)

0= No overflow occurred

bit 2

bit 1

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit

For ADDWF, ADDLW, SUBLW, and SUBWFinstructions

1= A carry-out from the 4th low order bit of the result occurred

0= No carry-out from the 4th low order bit of the result

Note:

For borrow, the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the bit 4 or bit 3 of the source register.

bit 0

C: Carry/borrow bit

For ADDWF, ADDLW, SUBLW, and SUBWFinstructions

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the high or low order bit of the source register.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 52

PIC18FXX2

4.14 RCON Register

Note 1: If the BOREN configuration bit is set

(Brown-out Reset enabled), the BOR bit is

’1’ on a Power-on Reset. After a Brown-

out Reset has occurred, the BOR bit will

be cleared, and must be set by firmware to

indicate the occurrence of the next

Brown-out Reset.

The Reset Control (RCON) register contains flag bits

that allow differentiation between the sources of a

device RESET. These flags include the TO, PD, POR,

BOR and RI bits. This register is readable and writable.

2: It is recommended that the POR bit be set

after

a Power-on Reset has been

detected, so that subsequent Power-on

Resets may be detected.

REGISTER 4-3:

RCON REGISTER

R/W-0

IPEN

U-0

—

U-0

—

R/W-1

RI

R-1

TO

R-1

PD

R/W-0

POR

R/W-0

BOR

bit 7

bit 0

bit 7

IPEN: Interrupt Priority Enable bit

1= Enable priority levels on interrupts

0= Disable priority levels on interrupts (16CXXX Compatibility mode)

bit 6-5

Unimplemented: Read as '0'

bit 4

RI: RESETInstruction Flag bit

1= The RESETinstruction was not executed

0= The RESETinstruction was executed causing a device RESET

(must be set in software after a Brown-out Reset occurs)

bit 3

bit 2

bit 1

TO: Watchdog Time-out Flag bit

1= After power-up, CLRWDTinstruction, or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down Detection Flag bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

POR: Power-on Reset Status bit

1= A Power-on Reset has not occurred

0= A Power-on Reset occurred

(must be set in software after a Power-on Reset occurs)

bit 0

BOR: Brown-out Reset Status bit

1= A Brown-out Reset has not occurred

0= A Brown-out Reset occurred

(must be set in software after a Brown-out Reset occurs)

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 53

PIC18FXX2

NOTES:

DS39564C-page 54

PIC18FXX2

5.1

Table Reads and Table Writes

5.0

FLASH PROGRAM MEMORY

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data

RAM:

The FLASH Program Memory is readable, writable,

and erasable during normal operation over the entire

VDD range.

A read from program memory is executed on one byte

at a time. A write to program memory is executed on

blocks of 8 bytes at a time. Program memory is erased

in blocks of 64 bytes at a time. A bulk erase operation

may not be issued from user code.

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16-bits wide, while the

data RAM space is 8-bits wide. Table Reads and Table

Writes move data between these two memory spaces

through an 8-bit register (TABLAT).

Writing or erasing program memory will cease instruc-

tion fetches until the operation is complete. The pro-

gram memory cannot be accessed during the write or

erase, therefore, code cannot execute. An internal pro-

gramming timer terminates program memory writes

and erases.

Table Read operations retrieve data from program

memory and places it into the data RAM space.

Figure 5-1 shows the operation of a Table Read with

program memory and data RAM.

A value written to program memory does not need to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP.

Table Write operations store data from the data mem-

ory space into holding registers in program memory.

The procedure to write the contents of the holding reg-

isters into program memory is detailed in Section 5.5,

'”Writing to FLASH Program Memory”. Figure 5-2

shows the operation of a Table Write with program

memory and data RAM.

Table operations work with byte entities. A table block

containing data, rather than program instructions, is not

required to be word aligned. Therefore, a table block

can start and end at any byte address. If a Table Write

is being used to write executable code into program

memory, program instructions will need to be word

aligned.

FIGURE 5-1:

TABLE READ OPERATION

Instruction: TBLRD*

Program Memory

(1)

Table Pointer

Table Latch (8-bit)

TABLAT

TBLPTRU TBLPTRH TBLPTRL

Program Memory

(TBLPTR)

Note 1: Table Pointer points to a byte in program memory.

DS39564C-page 55

PIC18FXX2

FIGURE 5-2:

TABLE WRITE OPERATION

Instruction: TBLWT*

Program Memory

Holding Registers

(1)

Table Pointer

Table Latch (8-bit)

TABLAT

TBLPTRU TBLPTRH TBLPTRL

Program Memory

(TBLPTR)

Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by

TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in

Section 5.5.

The FREE bit, when set, will allow a program memory

erase operation. When the FREE bit is set, the erase

operation is initiated on the next WR command. When

FREE is clear, only writes are enabled.

5.2

Control Registers

Several control registers are used in conjunction with

the TBLRDand TBLWTinstructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset or a WDT Time-out Reset during normal opera-

tion. In these situations, the user can check the

WRERR bit and rewrite the location. It is necessary to

reload the data and address registers (EEDATA and

EEADR), due to RESETvalues of zero.

5.2.1

EECON1 AND EECON2 REGISTERS

EECON1 is the control register for memory accesses.

EECON2 is not a physical register. Reading EECON2

will read all '0's. The EECON2 register is used

exclusively in the memory write and erase sequences.

Control bit WR initiates write operations. This bit cannot

be cleared, only set, in software. It is cleared in hard-

ware at the completion of the write operation. The

inability to clear the WR bit in software prevents the

Control bit EEPGD determines if the access will be a

program or data EEPROM memory access. When

clear, any subsequent operations will operate on the

data EEPROM memory. When set, any subsequent

operations will operate on the program memory.

accidental or premature termination of

operation.

a write

Note: Interrupt flag bit EEIF, in the PIR2 register,

is set when the write is complete. It must

be cleared in software.

Control bit CFGS determines if the access will be to the

configuration registers or to program memory/data

EEPROM memory. When set, subsequent operations

will operate on configuration registers, regardless of

EEPGD (see “Special Features of the CPU”,

Section 19.0). When clear, memory selection access is

determined by EEPGD.

DS39564C-page 56

PIC18FXX2

REGISTER 5-1:

EECON1 REGISTER (ADDRESS FA6h)

R/W-x

CFGS

U-0

—

R/W-0

FREE

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

EEPGD

WRERR

bit 7

bit 0

bit 7

bit 6

EEPGD: FLASH Program or Data EEPROM Memory Select bit

1= Access FLASH Program memory

0= Access Data EEPROM memory

CFGS: FLASH Program/Data EE or Configuration Select bit

1= Access Configuration registers

0= Access FLASH Program or Data EEPROM memory

bit 5

bit 4

Unimplemented: Read as '0'

FREE: FLASH Row Erase Enable bit

1= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0= Perform write only

bit 3

WRERR: FLASH Program/Data EE Error Flag bit

1= A write operation is prematurely terminated

(any RESET during self-timed programming in normal operation)

0= The write operation completed

Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows

tracing of the error condition.

bit 2

bit 1

WREN: FLASH Program/Data EE Write Enable bit

1= Allows write cycles

0= Inhibits write to the EEPROM

WR: Write Control bit

1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self timed and the bit is cleared by hardware once write is complete. The

WR bit can only be set (not cleared) in software.)

0= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)

in software. RD bit cannot be set when EEPGD = 1.)

0= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 57

PIC18FXX2

5.2.2

TABLAT - TABLE LATCH REGISTER

5.2.4

TABLE POINTER BOUNDARIES

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR space. The Table Latch is used to hold

8-bit data during data transfers between program

memory and data RAM.

TBLPTR is used in reads, writes, and erases of the

FLASH program memory.

When a TBLRD is executed, all 22 bits of the Table

Pointer determine which byte is read from program

memory into TABLAT.

5.2.3

TBLPTR - TABLE POINTER

REGISTER

When a TBLWTis executed, the three LSbs of the Table

Pointer (TBLPTR<2:0>) determine which of the eight

program memory holding registers is written to. When

the timed write to program memory (long write) begins,

the 19 MSbs of the Table Pointer, TBLPTR

(TBLPTR<21:3>), will determine which program mem-

ory block of 8 bytes is written to. For more detail, see

Section 5.5 (“Writing to FLASH Program Memory”).

The Table Pointer (TBLPTR) addresses a byte within

the program memory. The TBLPTR is comprised of

three SFR registers: Table Pointer Upper Byte, Table

Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-

ters join to form a 22-bit wide pointer. The low order 21

bits allow the device to address up to 2 Mbytes of pro-

gram memory space. The 22nd bit allows access to the

Device ID, the User ID and the Configuration bits.

When an erase of program memory is executed, the 16

MSbs of the Table Pointer (TBLPTR<21:6>) point to the

64-byte block that will be erased. The Least Significant

bits (TBLPTR<5:0>) are ignored.

The table pointer, TBLPTR, is used by the TBLRDand

TBLWTinstructions. These instructions can update the

TBLPTR in one of four ways based on the table opera-

tion. These operations are shown in Table 5-1. These

operations on the TBLPTR only affect the low order

21 bits.

Figure 5-3 describes the relevant boundaries of

TBLPTR based on FLASH program memory

operations.

TABLE 5-1:

Example

TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

Operation on Table Pointer

TBLRD*

TBLWT*

TBLPTR is not modified

TBLRD*+

TBLWT*+

TBLPTR is incremented after the read/write

TBLPTR is decremented after the read/write

TBLPTR is incremented before the read/write

TBLRD*-

TBLWT*-

TBLRD+*

TBLWT+*

FIGURE 5-3:

TABLE POINTER BOUNDARIES BASED ON OPERATION

21

16 15

TBLPTRH

8

7

TBLPTRL

0

TBLPTRU

ERASE - TBLPTR<21:6>

WRITE - TBLPTR<21:3>

READ - TBLPTR<21:0>

DS39564C-page 58

PIC18FXX2

TBLPTR points to a byte address in program space.

Executing TBLRD places the byte pointed to into

TABLAT. In addition, TBLPTR can be modified

automatically for the next Table Read operation.

5.3

Reading the FLASH Program

Memory

The TBLRDinstruction is used to retrieve data from pro-

gram memory and place into data RAM. Table Reads

from program memory are performed one byte at a

time.

The internal program memory is typically organized by

words. The Least Significant bit of the address selects

between the high and low bytes of the word. Figure 5-4

shows the interface between the internal program

memory and the TABLAT.

FIGURE 5-4:

READS FROM FLASH PROGRAM MEMORY

Program Memory

(Even Byte Address)

(Odd Byte Address)

TBLPTR = xxxxx1

TBLPTR = xxxxx0

Instruction Register

(IR)

TABLAT

Read Register

FETCH

TBLRD

EXAMPLE 5-1:

READING A FLASH PROGRAM MEMORY WORD

MOVLW CODE_ADDR_UPPER

MOVWF TBLPTRU

; Load TBLPTR with the base

; address of the word

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

READ_WORD

TBLRD*+

; read into TABLAT and increment

; get data

MOVF TABLAT, W

MOVWF WORD_EVEN

TBLRD*+

MOVF TABLAT, W

MOVWF WORD_ODD

; read into TABLAT and increment

; get data

DS39564C-page 59

PIC18FXX2

5.4.1

FLASH PROGRAM MEMORY

ERASE SEQUENCE

5.4

Erasing FLASH Program memory

The minimum erase block is 32 words or 64 bytes. Only

through the use of an external programmer, or through

ICSP control can larger blocks of program memory be

bulk erased. Word erase in the FLASH array is not

supported.

The sequence of events for erasing a block of internal

program memory location is:

1. Load table pointer with address of row being

erased.

When initiating an erase sequence from the micro-

controller itself, a block of 64 bytes of program memory

is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased.

TBLPTR<5:0> are ignored.

2. Set EEPGD bit to point to program memory,

clear CFGS bit to access program memory, set

WREN bit to enable writes, and set FREE bit to

enable the erase.

3. Disable interrupts.

The EECON1 register commands the erase operation.

The EEPGD bit must be set to point to the FLASH pro-

gram memory. The WREN bit must be set to enable

write operations. The FREE bit is set to select an erase

operation.

4. Write 55h to EECON2.

5. Write AAh to EECON2.

6. Set the WR bit. This will begin the row erase

cycle.

7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).

For protection, the write initiate sequence for EECON2

must be used.

8. Re-enable interrupts.

A long write is necessary for erasing the internal

FLASH. Instruction execution is halted while in a long

write cycle. The long write will be terminated by the

internal programming timer.

EXAMPLE 5-2:

ERASING A FLASH PROGRAM MEMORY ROW

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

CODE_ADDR_UPPER

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

; load TBLPTR with the base

; address of the memory block

ERASE_ROW

BSF

BCF

BSF

EECON1,EEPGD

EECON1,CFGS

EECON1,WREN

EECON1,FREE

INTCON,GIE

55h

EECON2

AAh

EECON2

EECON1,WR

INTCON,GIE

; point to FLASH program memory

; access FLASH program memory

; enable write to memory

; enable Row Erase operation

; disable interrupts

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

Required

Sequence

; write 55h

; write AAh

; start erase (CPU stall)

; re-enable interrupts

BSF

DS39564C-page 60

PIC18FXX2

operations will essentially be short writes, because only

the holding registers are written. At the end of updating

8 registers, the EECON1 register must be written to, to

start the programming operation with a long write.

5.5

Writing to FLASH Program

Memory

The minimum programming block is 4 words or 8 bytes.

Word or byte programming is not supported.

The long write is necessary for programming the inter-

nal FLASH. Instruction execution is halted while in a

long write cycle. The long write will be terminated by

the internal programming timer.

Table Writes are used internally to load the holding reg-

isters needed to program the FLASH memory. There

are 8 holding registers used by the Table Writes for

programming.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump rated to operate over the voltage range of

the device for byte or word operations.

Since the Table Latch (TABLAT) is only a single byte,

the TBLWT instruction has to be executed 8 times for

each programming operation. All of the Table Write

FIGURE 5-5:

TABLE WRITES TO FLASH PROGRAM MEMORY

TABLAT

Write Register

8

TBLPTR = xxxxx0

TBLPTR = xxxxx2

TBLPTR = xxxxx7

Holding Register

TBLPTR = xxxxx1

Holding Register

Program Memory

10. Write AAh to EECON2.

5.5.1

FLASH PROGRAM MEMORY WRITE

SEQUENCE

11. Set the WR bit. This will begin the write cycle.

12. The CPU will stall for duration of the write (about

2 ms using internal timer).

The sequence of events for programming an internal

program memory location should be:

13. Re-enable interrupts.

1. Read 64 bytes into RAM.

14. Repeat steps 6-14 seven times, to write

64 bytes.

2. Update data values in RAM as necessary.

3. Load Table Pointer with address being erased.

4. Do the row erase procedure.

15. Verify the memory (Table Read).

This procedure will require about 18 ms to update one

row of 64 bytes of memory. An example of the required

code is given in Example 5-3.

5. Load Table Pointer with address of first byte

being written.

6. Write the first 8 bytes into the holding registers

Note: Before setting the WR bit, the table pointer

address needs to be within the intended

address range of the 8 bytes in the holding

registers.

with auto-increment (TBLWT*+or TBLWT+*).

7. Set EEPGD bit to point to program memory,

clear the CFGS bit to access program memory,

and set WREN to enable byte writes.

8. Disable interrupts.

9. Write 55h to EECON2.

DS39564C-page 61

PIC18FXX2

EXAMPLE 5-3:

WRITING TO FLASH PROGRAM MEMORY

MOVLW

D'64

; number of bytes in erase block

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

COUNTER

BUFFER_ADDR_HIGH

FSR0H

BUFFER_ADDR_LOW

FSR0L

CODE_ADDR_UPPER

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

; point to buffer

; Load TBLPTR with the base

; address of the memory block

READ_BLOCK

TBLRD*+

MOVF

MOVWF

; read into TABLAT, and inc

; get data

; store data

; done?

TABLAT, W

POSTINC0

DECFSZ COUNTER

BRA

READ_BLOCK

; repeat

MODIFY_WORD

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

DATA_ADDR_HIGH

FSR0H

DATA_ADDR_LOW

FSR0L

NEW_DATA_LOW

POSTINC0

NEW_DATA_HIGH

INDF0

; point to buffer

; update buffer word

ERASE_BLOCK

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

BCF

BSF

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

CODE_ADDR_UPPER

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

EECON1,EEPGD

EECON1,CFGS

EECON1,WREN

EECON1,FREE

INTCON,GIE

55h

EECON2

AAh

EECON2

EECON1,WR

INTCON,GIE

; load TBLPTR with the base

; address of the memory block

; point to FLASH program memory

; access FLASH program memory

; enable write to memory

; enable Row Erase operation

; disable interrupts

; write 55h

; write AAh

; start erase (CPU stall)

; re-enable interrupts

; dummy read decrement

BSF

TBLRD*-

WRITE_BUFFER_BACK

MOVLW

8

; number of write buffer groups of 8 bytes

; point to buffer

MOVWF

MOVLW

MOVWF

COUNTER_HI

BUFFER_ADDR_HIGH

FSR0H

MOVLW

MOVWF

BUFFER_ADDR_LOW

FSR0L

PROGRAM_LOOP

MOVLW

8

; number of bytes in holding register

MOVWF

COUNTER

WRITE_WORD_TO_HREGS

MOVF

POSTINC0, W

TABLAT

; get low byte of buffer data

; present data to table latch

; write data, perform a short write

; to internal TBLWT holding register.

; loop until buffers are full

MOVWF

TBLWT+*

DECFSZ COUNTER

BRA

WRITE_WORD_TO_HREGS

DS39564C-page 62

PIC18FXX2

EXAMPLE 5-3:

WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

PROGRAM_MEMORY

BSF

BCF

BSF

BCF

EECON1,EEPGD

EECON1,CFGS

EECON1,WREN

INTCON,GIE

55h

; point to FLASH program memory

; access FLASH program memory

; enable write to memory

; disable interrupts

MOVLW

Required

Sequence

MOVWF

MOVLW

MOVWF

BSF

EECON2

AAh

EECON2

EECON1,WR

INTCON,GIE

; write 55h

; write AAh

; start program (CPU stall)

; re-enable interrupts

; loop until done

BSF

DECFSZ COUNTER_HI

BRA

BCF

PROGRAM_LOOP

EECON1,WREN

; disable write to memory

5.5.2

WRITE VERIFY

5.5.4

PROTECTION AGAINST SPURIOUS

WRITES

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

To protect against spurious writes to FLASH program

memory, the write initiate sequence must also be fol-

lowed. See “Special Features of the CPU”

(Section 19.0) for more detail.

5.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

5.6

FLASH Program Operation During

Code Protection

If a write is terminated by an unplanned event, such as

loss of power or an unexpected RESET, the memory

location just programmed should be verified and repro-

grammed if needed.The WRERR bit is set when a write

operation is interrupted by a MCLR Reset, or a WDT

Time-out Reset during normal operation. In these situ-

ations, users can check the WRERR bit and rewrite the

location.

See “Special Features of the CPU” (Section 19.0) for

details on code protection of FLASH program memory.

TABLE 5-2:

REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Value on

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Other

RESETS

FF8h

TBLPTRU

—

bit21 Program Memory Table Pointer Upper Byte

(TBLPTR<20:16>)

--00 0000 --00 0000

FF7h

FF6h

FF5h

FF2h

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)

0000 0000 0000 0000

0000 000x 0000 000u

TABLAT

INTCON

Program Memory Table Latch

GIE/

PEIE/ TMR0IE INTE

GIEL

RBIE

TMR0IF

INTF

WR

RBIF

RD

GIEH

FA7h

FA6h

FA2h

EECON2 EEPROM Control Register2 (not a physical register)

—

EECON1 EEPGD CFGS

—

FREE WRERR WREN

xx-0 x000 uu-0 u000

---1 1111 ---1 1111

IPR2

—

EEIP

BCLIP

LVDIP TMR3IP CCP2IP

FA1h

FA0h

PIR2

PIE2

—

EEIF

EEIE

BCLIF

BCLIE

LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000

LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000

Legend: x= unknown, u= unchanged, r = reserved, -= unimplemented read as '0'.

Shaded cells are not used during FLASH/EEPROM access.

DS39564C-page 63

PIC18FXX2

NOTES:

DS39564C-page 64

PIC18FXX2

6.1

EEADR

6.0

DATA EEPROM MEMORY

The address register can address up to a maximum of

256 bytes of data EEPROM.

The Data EEPROM is readable and writable during

normal operation over the entire VDD range. The data

memory is not directly mapped in the register file

space. Instead, it is indirectly addressed through the

Special Function Registers (SFR).

6.2

EECON1 and EECON2 Registers

EECON1 is the control register for EEPROM memory

accesses.

There are four SFRs used to read and write the

program and data EEPROM memory. These registers

are:

EECON2 is not a physical register. Reading EECON2

will read all '0's. The EECON2 register is used

exclusively in the EEPROM write sequence.

• EECON1

• EECON2

• EEDATA

• EEADR

Control bits RD and WR initiate read and write opera-

tions, respectively. These bits cannot be cleared, only

set, in software. They are cleared in hardware at the

completion of the read or write operation. The inability

to clear the WR bit in software prevents the accidental

or premature termination of a write operation.

The EEPROM data memory allows byte read and write.

When interfacing to the data memory block, EEDATA

holds the 8-bit data for read/write and EEADR holds the

address of the EEPROM location being accessed.

These devices have 256 bytes of data EEPROM with

an address range from 0h to FFh.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset during normal opera-

tion. In these situations, the user can check the

WRERR bit and rewrite the location. It is necessary to

reload the data and address registers (EEDATA and

EEADR), due to the RESET condition forcing the

contents of the registers to zero.

The EEPROM data memory is rated for high erase/

write cycles. A byte write automatically erases the loca-

tion and writes the new data (erase-before-write). The

write time is controlled by an on-chip timer. The write

time will vary with voltage and temperature, as well as

from chip to chip. Please refer to parameter D122

(Electrical Characteristics, Section 22.0) for exact

limits.

Note: Interrupt flag bit, EEIF in the PIR2 register,

is set when write is complete. It must be

cleared in software.

DS39564C-page 65

PIC18FXX2

REGISTER 6-1:

EECON1 REGISTER (ADDRESS FA6h)

R/W-x

CFGS

U-0

—

R/W-0

FREE

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

EEPGD

WRERR

bit 7

bit 0

bit 7

bit 6

EEPGD: FLASH Program or Data EEPROM Memory Select bit

1= Access FLASH Program memory

0= Access Data EEPROM memory

CFGS: FLASH Program/Data EE or Configuration Select bit

1= Access Configuration or Calibration registers

0= Access FLASH Program or Data EEPROM memory

bit 5

bit 4

Unimplemented: Read as '0'

FREE: FLASH Row Erase Enable bit

1= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0= Perform write only

bit 3

WRERR: FLASH Program/Data EE Error Flag bit

1= A write operation is prematurely terminated

(any MCLR or any WDT Reset during self-timed programming in normal operation)

0= The write operation completed

Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing

of the error condition.

bit 2

bit 1

WREN: FLASH Program/Data EE Write Enable bit

1= Allows write cycles

0= Inhibits write to the EEPROM

WR: Write Control bit

1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete. The

WR bit can only be set (not cleared) in software.)

0= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)

in software. RD bit cannot be set when EEPGD = 1.)

0= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 66

PIC18FXX2

(EECON1<6>), and then set control bit RD

(EECON1<0>). The data is available for the very next

instruction cycle; therefore, the EEDATA register can

be read by the next instruction. EEDATA will hold this

value until another read operation, or until it is written to

by the user (during a write operation).

6.3

Reading the Data EEPROM

Memory

To read a data memory location, the user must write the

address to the EEADR register, clear the EEPGD con-

trol bit (EECON1<7>), clear the CFGS control bit

EXAMPLE 6-1:

DATA EEPROM READ

MOVLW

MOVWF

BCF

DATA_EE_ADDR

EEADR

EECON1, EEPGD ; Point to DATA memory

;

; Data Memory Address to read

BCF

BSF

MOVF

EECON1, CFGS

EECON1, RD

EEDATA, W

; Access program FLASH or Data EEPROM memory

; EEPROM Read

; W = EEDATA

cution (i.e., runaway programs). The WREN bit should

be kept clear at all times, except when updating the

EEPROM. The WREN bit is not cleared by hardware.

6.4

Writing to the Data EEPROM

Memory

To write an EEPROM data location, the address must

first be written to the EEADR register and the data writ-

ten to the EEDATA register. Then the sequence in

Example 6-2 must be followed to initiate the write cycle.

After a write sequence has been initiated, EECON1,

EEADR and EDATA cannot be modified. The WR bit

will be inhibited from being set unless the WREN bit is

set. The WREN bit must be set on a previous instruc-

tion. Both WR and WREN cannot be set with the same

instruction.

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. It is strongly

recommended that interrupts be disabled during this

code segment.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EEPROM Write Complete

Interrupt Flag bit (EEIF) is set. The user may either

enable this interrupt, or poll this bit. EEIF must be

cleared by software.

Additionally, the WREN bit in EECON1 must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code exe-

EXAMPLE 6-2:

DATA EEPROM WRITE

MOVLW

MOVWF

MOVLW

MOVWF

BCF

DATA_EE_ADDR

EEADR

DATA_EE_DATA

EEDATA

;

; Data Memory Address to read

;

; Data Memory Value to write

EECON1, EEPGD ; Point to DATA memory

BCF

BSF

EECON1, CFGS

EECON1, WREN

; Access program FLASH or Data EEPROM memory

; Enable writes

BCF

INTCON, GIE

55h

EECON2

AAh

EECON2

; Disable interrupts

;

; Write 55h

;

; Write AAh

; Set WR bit to begin write

; Enable interrupts

Required

Sequence

MOVLW

MOVWF

MOVLW

MOVWF

BSF

EECON1, WR

INTCON, GIE

BSF

.

; user code execution

.

BCF

EECON1, WREN

; Disable writes on write complete (EEIF set)

DS39564C-page 67

PIC18FXX2

6.5

Write Verify

6.7

Operation During Code Protect

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

Data EEPROM memory has its own code protect

mechanism. External Read and Write operations are

disabled if either of these mechanisms are enabled.

The microcontroller itself can both read and write to the

internal Data EEPROM, regardless of the state of the

code protect configuration bit. Refer to “Special Features

of the CPU” (Section 19.0) for additional information.

6.6

Protection Against Spurious Write

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared.

Also, the Power-up Timer (72 ms duration) prevents

EEPROM write.

6.8

Using the Data EEPROM

The data EEPROM is a high endurance, byte address-

able array that has been optimized for the storage of

frequently changing information (e.g., program vari-

ables or other data that are updated often). Frequently

changing values will typically be updated more often

than specification D124. If this is not the case, an array

refresh must be performed. For this reason, variables

that change infrequently (such as constants, IDs, cali-

bration, etc.) should be stored in FLASH program

memory.

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch, or software malfunction.

A simple data EEPROM refresh routine is shown in

Example 6-3.

Note: If data EEPROM is only used to store con-

stants and/or data that changes rarely, an

array refresh is likely not required. See

specification D124.

EXAMPLE 6-3:

DATA EEPROM REFRESH ROUTINE

clrf

EEADR

; Start at address 0

bcf

bsf

EECON1,CFGS

EECON1,EEPGD

INTCON,GIE

EECON1,WREN

; Set for memory

; Set for Data EEPROM

; Disable interrupts

; Enable writes

; Loop to refresh array

; Read current address

;

; Write 55h

;

; Write AAh

; Set WR bit to begin write

; Wait for write to complete

Loop

bsf

EECON1,RD

55h

EECON2

AAh

EECON2

EECON1,WR

$-2

movlw

movwf

movlw

movwf

bsf

btfsc

bra

incfsz EEADR,F

; Increment address

bra

Loop

; Not zero, do it again

bcf

bsf

EECON1,WREN

INTCON,GIE

; Disable writes

; Enable interrupts

DS39564C-page 68

PIC18FXX2

TABLE 6-1:

REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Value on

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Other

RESETS

FF2h

INTCON

EEADR

GIE/

GIEH

PEIE/

GIEL

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000u

FA9h

FA8h

FA7h

FA6h

FA2h

FA1h

FA0h

EEPROM Address Register

0000 0000 0000 0000

EEDATA EEPROM Data Register

EECON2 EEPROM Control Register2 (not a physical register)

—

EECON1 EEPGD CFGS

—

FREE WRERR WREN

WR

RD

xx-0 x000 uu-0 u000

IPR2

PIR2

PIE2

—

EEIP

EEIF

EEIE

BCLIP

BCLIF

BCLIE

LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111

LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000

LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000

Legend: x= unknown, u= unchanged, r = reserved, -= unimplemented, read as '0'.

Shaded cells are not used during FLASH/EEPROM access.

DS39564C-page 69

PIC18FXX2

NOTES:

DS39564C-page 70

PIC18FXX2

Making the 8 x 8 multiplier execute in a single cycle

gives the following advantages:

7.0

7.1

8 X 8 HARDWARE MULTIPLIER

Introduction

• Higher computational throughput

• Reduces code size requirements for multiply

algorithms

An 8 x 8 hardware multiplier is included in the ALU of

the PIC18FXX2 devices. By making the multiply a

hardware operation, it completes in a single instruction

cycle. This is an unsigned multiply that gives a 16-bit

result. The result is stored into the 16-bit product regis-

ter pair (PRODH:PRODL). The multiplier does not

affect any flags in the ALUSTA register.

The performance increase allows the device to be used

in applications previously reserved for Digital Signal

Processors.

Table 7-1 shows a performance comparison between

enhanced devices using the single cycle hardware mul-

tiply, and performing the same function without the

hardware multiply.

TABLE 7-1:

Routine

PERFORMANCE COMPARISON

Multiply Method

Program

Memory

(Words)

Time

Cycles

(Max)

@ 40 MHz @ 10 MHz @ 4 MHz

Without hardware multiply

Hardware multiply

13

1

69

1

6.9 μs

100 ns

9.1 μs

600 ns

24.2 μs

2.4 μs

25.4 μs

3.6 μs

27.6 μs

400 ns

36.4 μs

2.4 μs

96.8 μs

9.6 μs

69 μs

1 μs

8 x 8 unsigned

8 x 8 signed

Without hardware multiply

Hardware multiply

33

6

91

6

91 μs

6 μs

242 μs

24 μs

254 μs

36 μs

Without hardware multiply

Hardware multiply

21

24

52

36

242

24

254

36

16 x 16 unsigned

16 x 16 signed

Without hardware multiply

Hardware multiply

102.6 μs

14.4 μs

EXAMPLE 7-2:

8 x 8 SIGNED MULTIPLY

ROUTINE

7.2

Operation

Example 7-1 shows the sequence to do an 8 x 8

unsigned multiply. Only one instruction is required

when one argument of the multiply is already loaded in

the WREG register.

MOVF

MULWF

ARG1,

ARG2

W

; ARG1 * ARG2 ->

; PRODH:PRODL

; Test Sign Bit

; PRODH = PRODH

BTFSC

SUBWF

ARG2, SB

PRODH, F

Example 7-2 shows the sequence to do an 8 x 8 signed

multiply. To account for the sign bits of the arguments,

each argument’s Most Significant bit (MSb) is tested

and the appropriate subtractions are done.

;

- ARG1

MOVF

ARG2,

W

BTFSC

SUBWF

ARG1, SB

PRODH, F

; Test Sign Bit

; PRODH = PRODH

;

- ARG2

EXAMPLE 7-1:

8 x 8 UNSIGNED

MULTIPLY ROUTINE

Example 7-3 shows the sequence to do a 16 x 16

unsigned multiply. Equation 7-1 shows the algorithm

that is used. The 32-bit result is stored in four registers,

RES3:RES0.

MOVF

MULWF

ARG1, W

ARG2

;

; ARG1 * ARG2 ->

;

PRODH:PRODL

EQUATION 7-1:

16 x 16 UNSIGNED

MULTIPLICATION

ALGORITHM

RES3:RES0

=

ARG1H:ARG1L • ARG2H:ARG2L

(ARG1H • ARG2H • 2¹⁶) +

(ARG1H • ARG2L • 2⁸) +

(ARG1L • ARG2H • 2⁸) +

(ARG1L • ARG2L)

DS39564C-page 71

PIC18FXX2

EXAMPLE 7-3:

16 x 16 UNSIGNED

EXAMPLE 7-4:

16 x 16 SIGNED

MULTIPLY ROUTINE

MOVF

MULWF

ARG1L, W

ARG2L

MOVF

MULWF

ARG1L,

ARG2L

W

; ARG1L * ARG2L ->

; PRODH:PRODL

; ARG1L * ARG2L ->

; PRODH:PRODL

MOVFF

PRODH, RES1

PRODL, RES0

;

MOVFF

PRODH, RES1

PRODL, RES0

;

MOVF

MULWF

ARG1H,

ARG2H

W

MOVF

MULWF

ARG1H,

ARG2H

W

; ARG1H * ARG2H ->

; PRODH:PRODL

;

; ARG1H * ARG2H ->

; PRODH:PRODL

;

MOVFF

PRODH, RES3

PRODL, RES2

MOVFF

PRODH, RES3

PRODL, RES2

MOVF

MULWF

ARG1L,

ARG2H

W

MOVF

MULWF

ARG1L,

ARG2H

W

; ARG1L * ARG2H ->

; PRODH:PRODL

MOVF

ADDWF

MOVF

ADDWFC RES2,

CLRF WREG

ADDWFC RES3,

PRODL,

RES1,

PRODH,

W

F

W

F

;

MOVF

ADDWF

MOVF

ADDWFC RES2,

CLRF WREG

ADDWFC RES3,

PRODL,

RES1,

PRODH,

W

F

W

F

;

; Add cross

; products

;

; Add cross

; products

;

F

W

F

W

;

MOVF

MULWF

ARG1H,

ARG2L

;

MOVF

MULWF

ARG1H,

ARG2L

;

; ARG1H * ARG2L ->

; PRODH:PRODL

MOVF

ADDWF

MOVF

ADDWFC RES2,

CLRF WREG

ADDWFC RES3,

PRODL,

RES1,

PRODH,

W

F

W

F

;

MOVF

ADDWF

MOVF

ADDWFC RES2,

CLRF WREG

ADDWFC RES3,

PRODL,

RES1,

PRODH,

W

F

W

F

;

; Add cross

; products

;

; Add cross

; products

;

F

7

;

BTFSS

BRA

MOVF

SUBWF

MOVF

ARG2H,

SIGN_ARG1

ARG1L,

RES2

ARG1H,

; ARG2H:ARG2L neg?

; no, check ARG1

;

Example 7-4 shows the sequence to do a 16 x 16

signed multiply. Equation 7-2 shows the algorithm

used. The 32-bit result is stored in four registers,

RES3:RES0. To account for the sign bits of the argu-

ments, each argument pairs Most Significant bit (MSb)

is tested and the appropriate subtractions are done.

W

SUBWFB RES3

SIGN_ARG1

BTFSS

BRA

ARG1H,

CONT_CODE

ARG2L,

RES2

ARG2H,

7

; ARG1H:ARG1L neg?

; no, done

;

EQUATION 7-2:

16 x 16 SIGNED

MULTIPLICATION

ALGORITHM

MOVF

SUBWF

MOVF

W

RES3:RES0

SUBWFB RES3

=

ARG1H:ARG1L • ARG2H:ARG2L

;

(ARG1H • ARG2H • 2¹⁶) +

CONT_CODE

:

(ARG1H • ARG2L • 2⁸) +

(ARG1L • ARG2H • 2⁸) +

(ARG1L • ARG2L) +

(-1 • ARG2H<7> • ARG1H:ARG1L • 2¹⁶) +

(-1 • ARG1H<7> • ARG2H:ARG2L • 2¹⁶)

DS39564C-page 72

PIC18FXX2

When the IPEN bit is cleared (default state), the inter-

rupt priority feature is disabled and interrupts are com-

patible with PICmicro^®mid-range devices. In

Compatibility mode, the interrupt priority bits for each

source have no effect. INTCON<6> is the PEIE bit,

which enables/disables all peripheral interrupt sources.

INTCON<7> is the GIE bit, which enables/disables all

interrupt sources. All interrupts branch to address

000008h in Compatibility mode.

8.0

INTERRUPTS

The PIC18FXX2 devices have multiple interrupt

sources and an interrupt priority feature that allows

each interrupt source to be assigned a high priority

level or a low priority level. The high priority interrupt

vector is at 000008h and the low priority interrupt vector

is at 000018h. High priority interrupt events will over-

ride any low priority interrupts that may be in progress.

There are ten registers which are used to control

interrupt operation. These registers are:

When an interrupt is responded to, the Global Interrupt

Enable bit is cleared to disable further interrupts. If the

IPEN bit is cleared, this is the GIE bit. If interrupt priority

levels are used, this will be either the GIEH or GIEL bit.

High priority interrupt sources can interrupt a low

priority interrupt.

• RCON

• INTCON

• INTCON2

• INTCON3

• PIR1, PIR2

• PIE1, PIE2

• IPR1, IPR2

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address

(000008h or 000018h). Once in the Interrupt Service

Routine, the source(s) of the interrupt can be deter-

mined by polling the interrupt flag bits. The interrupt

flag bits must be cleared in software before re-enabling

interrupts to avoid recursive interrupts.

It is recommended that the Microchip header files sup-

plied with MPLAB^®IDE be used for the symbolic bit

names in these registers. This allows the assembler/

compiler to automatically take care of the placement of

these bits within the specified register.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine and sets the GIE bit (GIEH or GIEL

if priority levels are used), which re-enables interrupts.

Each interrupt source, except INT0, has three bits to

control its operation. The functions of these bits are:

For external interrupt events, such as the INT pins or

the PORTB input change interrupt, the interrupt latency

will be three to four instruction cycles. The exact

latency is the same for one or two-cycle instructions.

Individual interrupt flag bits are set, regardless of the

status of their corresponding enable bit or the GIE bit.

• Flag bit to indicate that an interrupt event

occurred

• Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

Note: Do not use the MOVFFinstruction to modify

any of the Interrupt control registers while

any interrupt is enabled. Doing so may

cause erratic microcontroller behavior.

• Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the

IPEN bit (RCON<7>). When interrupt priority is

enabled, there are two bits which enable interrupts glo-

bally. Setting the GIEH bit (INTCON<7>) enables all

interrupts that have the priority bit set. Setting the GIEL

bit (INTCON<6>) enables all interrupts that have the

priority bit cleared. When the interrupt flag, enable bit

and appropriate global interrupt enable bit are set, the

interrupt will vector immediately to address 000008h or

000018h, depending on the priority level. Individual

interrupts can be disabled through their corresponding

enable bits.

DS39564C-page 73

PIC18FXX2

FIGURE 8-1:

INTERRUPT LOGIC

Wake-up if in SLEEP mode

TMR0IF

TMR0IE

TMR0IP

RBIF

RBIE

RBIP

INT0IF

INT0IE

Interrupt to CPU

Vector to location

0008h

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit

Peripheral Interrupt Priority bit

GIEH/GIE

TMR1IF

TMR1IE

TMR1IP

IPE

IPEN

XXXXIF

XXXXIE

XXXXIP

GIEL/PEIE

IPEN

Additional Peripheral Interrupts

High Priority Interrupt Generation

Low Priority Interrupt Generation

Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit

Peripheral Interrupt Priority bit

Interrupt to CPU

Vector to Location

0018h

TMR0IF

TMR0IE

TMR0IP

TMR1IF

TMR1IE

TMR1IP

RBIF

RBIE

RBIP

GIEL/PEIE

GIE/GIEH

XXXXIF

XXXXIE

XXXXIP

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

Additional Peripheral Interrupts

INT2IP

DS39564C-page 74

PIC18FXX2

8.1

INTCON Registers

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit. User software should ensure

the appropriate interrupt flag bits are clear

prior to enabling an interrupt. This feature

allows for software polling.

The INTCON Registers are readable and writable reg-

isters, which contain various enable, priority and flag

bits.

REGISTER 8-1:

INTCON REGISTER

R/W-0 R/W-0

R/W-0

RBIE

R/W-0

INT0IF

R/W-x

RBIF

bit 0

GIE/GIEH PEIE/GIEL

bit 7

TMR0IE

INT0IE

TMR0IF

bit 7

GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:

1= Enables all unmasked interrupts

0= Disables all interrupts

When IPEN = 1:

1= Enables all high priority interrupts

0= Disables all interrupts

bit 6

PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN = 0:

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

When IPEN = 1:

1= Enables all low priority peripheral interrupts

0= Disables all low priority peripheral interrupts

bit 5

bit 4

bit 3

TMR0IE: TMR0 Overflow Interrupt Enable bit

1= Enables the TMR0 overflow interrupt

0= Disables the TMR0 overflow interrupt

INT0IE: INT0 External Interrupt Enable bit

1= Enables the INT0 external interrupt

0= Disables the INT0 external interrupt

RBIE: RB Port Change Interrupt Enable bit

1= Enables the RB port change interrupt

0= Disables the RB port change interrupt

bit 2

bit 1

bit 0

TMR0IF: TMR0 Overflow Interrupt Flag bit

1= TMR0 register has overflowed (must be cleared in software)

0= TMR0 register did not overflow

INT0IF: INT0 External Interrupt Flag bit

1= The INT0 external interrupt occurred (must be cleared in software)

0= The INT0 external interrupt did not occur

RBIF: RB Port Change Interrupt Flag bit

1= At least one of the RB7:RB4 pins changed state (must be cleared in software)

0= None of the RB7:RB4 pins have changed state

Note: A mismatch condition will continue to set this bit. Reading PORTB will end the

mismatch condition and allow the bit to be cleared.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 75

PIC18FXX2

REGISTER 8-2:

INTCON2 REGISTER

R/W-1

RBPU

R/W-1

U-0

—

R/W-1

U-0

—

R/W-1

RBIP

bit 0

INTEDG0 INTEDG1 INTEDG2

TMR0IP

bit 7

bit 6

bit 5

bit 4

RBPU: PORTB Pull-up Enable bit

1= All PORTB pull-ups are disabled

0= PORTB pull-ups are enabled by individual port latch values

INTEDG0:External Interrupt0 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

INTEDG1: External Interrupt1 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

INTEDG2: External Interrupt2 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

bit 3

bit 2

Unimplemented: Read as '0'

TMR0IP: TMR0 Overflow Interrupt Priority bit

1= High priority

0= Low priority

bit 1

bit 0

Unimplemented: Read as '0'

RBIP: RB Port Change Interrupt Priority bit

1= High priority

0= Low priority

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows for software polling.

DS39564C-page 76

PIC18FXX2

REGISTER 8-3:

INTCON3 REGISTER

R/W-1

U-0

—

R/W-0

U-0

—

R/W-0

INT2IF

R/W-0

INT1IF

INT2IP

INT1IP

INT2IE

INT1IE

bit 7

bit 0

bit 7

bit 6

INT2IP: INT2 External Interrupt Priority bit

1= High priority

0= Low priority

INT1IP: INT1 External Interrupt Priority bit

1= High priority

0= Low priority

bit 5

bit 4

Unimplemented: Read as '0'

INT2IE: INT2 External Interrupt Enable bit

1= Enables the INT2 external interrupt

0= Disables the INT2 external interrupt

bit 3

INT1IE: INT1 External Interrupt Enable bit

1= Enables the INT1 external interrupt

0= Disables the INT1 external interrupt

bit 2

bit 1

Unimplemented: Read as '0'

INT2IF: INT2 External Interrupt Flag bit

1= The INT2 external interrupt occurred (must be cleared in software)

0= The INT2 external interrupt did not occur

bit 0

INT1IF: INT1 External Interrupt Flag bit

1= The INT1 external interrupt occurred (must be cleared in software)

0= The INT1 external interrupt did not occur

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows for software polling.

DS39564C-page 77

PIC18FXX2

8.2

PIR Registers

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

The PIR registers contain the individual flag bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are two Peripheral Interrupt

Flag Registers (PIR1, PIR2).

2: User software should ensure the appropriate

interrupt flag bits are cleared prior to enabling

an interrupt, and after servicing that interrupt.

REGISTER 8-4:

PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

R/W-0

PSPIF⁽¹⁾

bit 7

R/W-0

ADIF

R-0

R/W-0

SSPIF

R/W-0

RCIF

TXIF

CCP1IF TMR2IF TMR1IF

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

PSPIF⁽¹⁾: Parallel Slave Port Read/Write Interrupt Flag bit

1= A read or a write operation has taken place (must be cleared in software)

0= No read or write has occurred

ADIF: A/D Converter Interrupt Flag bit

1= An A/D conversion completed (must be cleared in software)

0= The A/D conversion is not complete

RCIF: USART Receive Interrupt Flag bit

1= The USART receive buffer, RCREG, is full (cleared when RCREG is read)

0= The USART receive buffer is empty

TXIF: USART Transmit Interrupt Flag bit (see Section 16.0 for details on TXIF functionality)

1= The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)

0= The USART transmit buffer is full

SSPIF: Master Synchronous Serial Port Interrupt Flag bit

1= The transmission/reception is complete (must be cleared in software)

0= Waiting to transmit/receive

CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1= A TMR1 register capture occurred (must be cleared in software)

0= No TMR1 register capture occurred

Compare mode:

1= A TMR1 register compare match occurred (must be cleared in software)

0= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 1

bit 0

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1= TMR2 to PR2 match occurred (must be cleared in software)

0= No TMR2 to PR2 match occurred

TMR1IF: TMR1 Overflow Interrupt Flag bit

1= TMR1 register overflowed (must be cleared in software)

0= MR1 register did not overflow

Note 1: This bit is reserved on PIC18F2X2 devices; always maintain this bit clear.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 78

PIC18FXX2

REGISTER 8-5:

PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2

U-0

—

U-0

—

U-0

—

R/W-0

EEIF

R/W-0

BCLIF

R/W-0

LVDIF

R/W-0

CCP2IF

bit 0

TMR3IF

bit 7

bit 7-5

bit 4

Unimplemented: Read as '0'

EEIF: Data EEPROM/FLASH Write Operation Interrupt Flag bit

1= The Write operation is complete (must be cleared in software)

0= The Write operation is not complete, or has not been started

bit 3

bit 2

bit 1

bit 0

BCLIF: Bus Collision Interrupt Flag bit

1= A bus collision occurred (must be cleared in software)

0= No bus collision occurred

LVDIF: Low Voltage Detect Interrupt Flag bit

1= A low voltage condition occurred (must be cleared in software)

0= The device voltage is above the Low Voltage Detect trip point

TMR3IF: TMR3 Overflow Interrupt Flag bit

1= TMR3 register overflowed (must be cleared in software)

0= TMR3 register did not overflow

CCP2IF: CCPx Interrupt Flag bit

Capture mode:

1= A TMR1 register capture occurred (must be cleared in software)

0= No TMR1 register capture occurred

Compare mode:

1= A TMR1 register compare match occurred (must be cleared in software)

0= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 79

PIC18FXX2

8.3

PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of periph-

eral interrupt sources, there are two Peripheral Inter-

rupt Enable Registers (PIE1, PIE2). When IPEN = 0,

the PEIE bit must be set to enable any of these

peripheral interrupts.

REGISTER 8-6:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

PSPIE⁽¹⁾

bit 7

R/W-0

ADIE

R/W-0

RCIE

R/W-0

TXIE

R/W-0

SSPIE

R/W-0

CCP1IE TMR2IE TMR1IE

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PSPIE⁽¹⁾: Parallel Slave Port Read/Write Interrupt Enable bit

1= Enables the PSP read/write interrupt

0= Disables the PSP read/write interrupt

ADIE: A/D Converter Interrupt Enable bit

1= Enables the A/D interrupt

0= Disables the A/D interrupt

RCIE: USART Receive Interrupt Enable bit

1= Enables the USART receive interrupt

0= Disables the USART receive interrupt

TXIE: USART Transmit Interrupt Enable bit

1= Enables the USART transmit interrupt

0= Disables the USART transmit interrupt

SSPIE: Master Synchronous Serial Port Interrupt Enable bit

1= Enables the MSSP interrupt

0= Disables the MSSP interrupt

CCP1IE: CCP1 Interrupt Enable bit

1= Enables the CCP1 interrupt

0= Disables the CCP1 interrupt

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1= Enables the TMR2 to PR2 match interrupt

0= Disables the TMR2 to PR2 match interrupt

TMR1IE: TMR1 Overflow Interrupt Enable bit

1= Enables the TMR1 overflow interrupt

0= Disables the TMR1 overflow interrupt

Note 1: This bit is reserved on PIC18F2X2 devices; always maintain this bit clear.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 80

PIC18FXX2

REGISTER 8-7:

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

U-0

—

U-0

—

U-0

—

R/W-0

EEIE

R/W-0

BCLIE

R/W-0

LVDIE

R/W-0

TMR3IE

CCP2IE

bit 7

bit 0

bit 7-5

bit 4

Unimplemented: Read as '0'

EEIE: Data EEPROM/FLASH Write Operation Interrupt Enable bit

1= Enabled

0= Disabled

bit 3

bit 2

bit 1

bit 0

BCLIE: Bus Collision Interrupt Enable bit

1= Enabled

0= Disabled

LVDIE: Low Voltage Detect Interrupt Enable bit

1= Enabled

0= Disabled

TMR3IE: TMR3 Overflow Interrupt Enable bit

1= Enables the TMR3 overflow interrupt

0= Disables the TMR3 overflow interrupt

CCP2IE: CCP2 Interrupt Enable bit

1= Enables the CCP2 interrupt

0= Disables the CCP2 interrupt

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 81

PIC18FXX2

8.4

IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of periph-

eral interrupt sources, there are two Peripheral Inter-

rupt Priority Registers (IPR1, IPR2). The operation of

the priority bits requires that the Interrupt Priority

Enable (IPEN) bit be set.

REGISTER 8-8:

IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

R/W-1

PSPIP⁽¹⁾

bit 7

R/W-1

ADIP

R/W-1

RCIP

R/W-1

TXIP

R/W-1

SSPIP

R/W-1

TMR1IP

bit 0

CCP1IP

TMR2IP

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PSPIP⁽¹⁾: Parallel Slave Port Read/Write Interrupt Priority bit

1= High priority

0= Low priority

ADIP: A/D Converter Interrupt Priority bit

1= High priority

0= Low priority

RCIP: USART Receive Interrupt Priority bit

1= High priority

0= Low priority

TXIP: USART Transmit Interrupt Priority bit

1= High priority

0= Low priority

SSPIP: Master Synchronous Serial Port Interrupt Priority bit

1= High priority

0= Low priority

CCP1IP: CCP1 Interrupt Priority bit

1= High priority

0= Low priority

TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

1= High priority

0= Low priority

TMR1IP: TMR1 Overflow Interrupt Priority bit

1= High priority

0= Low priority

Note 1: This bit is reserved on PIC18F2X2 devices; always maintain this bit set.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 82

PIC18FXX2

REGISTER 8-9:

IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2

U-0

—

U-0

—

U-0

—

R/W-1

EEIP

R/W-1

BCLIP

R/W-1

LVDIP

R/W-1

TMR3IP

CCP2IP

bit 7

bit 0

bit 7-5

bit 4

Unimplemented: Read as '0'

EEIP: Data EEPROM/FLASH Write Operation Interrupt Priority bit

1= High priority

0= Low priority

bit 3

bit 2

bit 1

bit 0

BCLIP: Bus Collision Interrupt Priority bit

1= High priority

0= Low priority

LVDIP: Low Voltage Detect Interrupt Priority bit

1= High priority

0= Low priority

TMR3IP: TMR3 Overflow Interrupt Priority bit

1= High priority

0= Low priority

CCP2IP: CCP2 Interrupt Priority bit

1= High priority

0= Low priority

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 83

PIC18FXX2

8.5

RCON Register

The RCON register contains the bit which is used to

enable prioritized interrupts (IPEN).

REGISTER 8-10: RCON REGISTER

R/W-0

IPEN

U-0

—

U-0

—

R/W-1

RI

R-1

TO

R-1

PD

R/W-0

POR

R/W-0

BOR

bit 7

bit 0

bit 7

IPEN: Interrupt Priority Enable bit

1= Enable priority levels on interrupts

0= Disable priority levels on interrupts (16CXXX Compatibility mode)

bit 6-5

bit 4

Unimplemented: Read as '0'

RI: RESETInstruction Flag bit

For details of bit operation, see Register 4-3

TO: Watchdog Time-out Flag bit

For details of bit operation, see Register 4-3

PD: Power-down Detection Flag bit

bit 3

bit 2

bit 1

bit 0

For details of bit operation, see Register 4-3

POR: Power-on Reset Status bit

For details of bit operation, see Register 4-3

BOR: Brown-out Reset Status bit

For details of bit operation, see Register 4-3

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 84

PIC18FXX2

8.6

INT0 Interrupt

8.7

TMR0 Interrupt

External interrupts on the RB0/INT0, RB1/INT1 and

RB2/INT2 pins are edge triggered: either rising, if the

corresponding INTEDGx bit is set in the INTCON2 reg-

ister, or falling, if the INTEDGx bit is clear. When a valid

edge appears on the RBx/INTx pin, the corresponding

flag bit INTxF is set. This interrupt can be disabled by

clearing the corresponding enable bit INTxE. Flag bit

INTxF must be cleared in software in the Interrupt Ser-

vice Routine before re-enabling the interrupt. All exter-

nal interrupts (INT0, INT1 and INT2) can wake-up the

processor from SLEEP, if bit INTxE was set prior to

going into SLEEP. If the global interrupt enable bit GIE

is set, the processor will branch to the interrupt vector

following wake-up.

In 8-bit mode (which is the default), an overflow

(FFh → 00h) in the TMR0 register will set flag bit

TMR0IF. In 16-bit mode, an overflow (FFFFh → 0000h)

in the TMR0H:TMR0L registers will set flag bit TMR0IF.

The interrupt can be enabled/disabled by setting/

clearing enable bit T0IE (INTCON<5>). Interrupt prior-

ity for Timer0 is determined by the value contained in

the interrupt priority bit TMR0IP (INTCON2<2>). See

Section 10.0 for further details on the Timer0 module.

8.8

PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit, RBIE (INTCON<3>).

Interrupt priority for PORTB interrupt-on-change is

determined by the value contained in the interrupt

priority bit, RBIP (INTCON2<0>).

Interrupt priority for INT1 and INT2 is determined by the

value contained in the interrupt priority bits, INT1IP

(INTCON3<6>) and INT2IP (INTCON3<7>). There is

no priority bit associated with INT0. It is always a high

priority interrupt source.

8.9

Context Saving During Interrupts

During an interrupt, the return PC value is saved on the

stack. Additionally, the WREG, STATUS and BSR regis-

ters are saved on the fast return stack. If a fast return

from interrupt is not used (See Section 4.3), the user

may need to save the WREG, STATUS and BSR regis-

ters in software. Depending on the user’s application,

other registers may also need to be saved. Equation 8-1

saves and restores the WREG, STATUS and BSR

registers during an Interrupt Service Routine.

EXAMPLE 8-1:

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF

MOVFF

;

W_TEMP

STATUS,STATUS_TEMP

BSR,

; W_TEMP is in virtual bank

; STATUS_TEMP located anywhere

; BSR located anywhere

BSR_TEMP

; USER ISR CODE

;

MOVFF

MOVF

MOVFF

BSR_TEMP, BSR

W_TEMP,

STATUS_TEMP,STATUS

; Restore BSR

; Restore WREG

; Restore STATUS

W

DS39564C-page 85

PIC18FXX2

NOTES:

DS39564C-page 86

PIC18FXX2

EXAMPLE 9-1:

CLRF PORTA

INITIALIZING PORTA

; Initialize PORTA by

; clearing output

; data latches

; Alternate method

; to clear output

; data latches

; Configure A/D

; for digital inputs

; Value used to

; initialize data

; direction

; Set RA<3:0> as inputs

; RA<5:4> as outputs

9.0

I/O PORTS

Depending on the device selected, there are either five

ports or three ports available. Some pins of the I/O

ports are multiplexed with an alternate function from

the peripheral features on the device. In general, when

a peripheral is enabled, that pin may not be used as a

general purpose I/O pin.

CLRF LATA

MOVLW 0x07

MOVWF ADCON1

MOVLW 0xCF

Each port has three registers for its operation. These

registers are:

• TRIS register (data direction register)

MOVWF TRISA

• PORT register (reads the levels on the pins of the

device)

• LAT register (output latch)

The data latch (LAT register) is useful for read-modify-

write operations on the value that the I/O pins are

driving.

FIGURE 9-1:

BLOCK DIAGRAM OF

RA3:RA0AND RA5 PINS

9.1

PORTA, TRISA and LATA

Registers

RD LATA

PORTA is a 7-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISA. Setting a

TRISA bit (= 1) will make the corresponding PORTA pin

an input (i.e., put the corresponding output driver in a

Hi-Impedance mode). Clearing a TRISA bit (= 0) will

make the corresponding PORTA pin an output (i.e., put

the contents of the output latch on the selected pin).

Data

Bus

D

Q

VDD

WR LATA

Q

Data Latch

CK

or

P

PORTA

I/O pin⁽¹⁾

N

D

Q

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the port latch.

WR TRISA

VSS

Q

CK

The Data Latch register (LATA) is also memory

mapped. Read-modify-write operations on the LATA

register reads and writes the latched output value for

PORTA.

Analog

Input

TRIS Latch

Mode

TTL

Input

Buffer

RD TRISA

Q

The RA4 pin is multiplexed with the Timer0 module

clock input to become the RA4/T0CKI pin. The RA4/

T0CKI pin is a Schmitt Trigger input and an open drain

output. All other RA port pins have TTL input levels and

full CMOS output drivers.

D

EN

The other PORTA pins are multiplexed with analog

inputs and the analog VREF+ and VREF- inputs. The

operation of each pin is selected by clearing/setting the

control bits in the ADCON1 register (A/D Control

Register1).

RD PORTA

SS Input (RA5 only)

To A/D Converter and LVD Modules

Note: On a Power-on Reset, RA5 and RA3:RA0

are configured as analog inputs and read

as ‘0’. RA6 and RA4 are configured as

digital inputs.

Note 1: I/O pins have protection diodes to VDD and VSS.

The TRISA register controls the direction of the RA

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

DS39564C-page 87

PIC18FXX2

FIGURE 9-2:

BLOCK DIAGRAM OF

RA4/T0CKI PIN

FIGURE 9-3:

BLOCK DIAGRAM OF

RA6 PIN

ECRA6 or

RCRA6 Enable

Data

Bus

RD LATA

Data

Bus

RD LATA

D

Q

D

Q

WR LATA

or

PORTA

VDD

P

I/O pin⁽¹⁾

Q

CK

N

Data Latch

CK

WR LATA

or

PORTA

D

Q

VSS

Data Latch

I/O pin⁽¹⁾

N

WR TRISA

Schmitt

Trigger

Input

D

Q

CK

TRIS Latch

VSS

Buffer

CK

Q

WR

TRISA

TRIS Latch

RD TRISA

TTL

Input

Buffer

Q

D

RD TRISA

EN

ECRA6 or

RCRA6

Enable

RD PORTA

Q

D

EN

TMR0 Clock Input

RD PORTA

Note 1: I/O pin has protection diode to VSS only.

Note 1: I/O pins have protection diodes to VDD and VSS.

DS39564C-page 88

PIC18FXX2

TABLE 9-1:

Name

PORTA FUNCTIONS

Bit#

Buffer

Function

RA0/AN0

bit0

bit1

bit2

bit3

bit4

TTL

ST

Input/output or analog input.

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

Input/output or analog input or VREF-.

Input/output or analog input or VREF+.

Input/output or external clock input for Timer0.

Output is open drain type.

RA5/SS/AN4/LVDIN

OSC2/CLKO/RA6

bit5

bit6

TTL

Input/output or slave select input for synchronous serial port or analog

input, or low voltage detect input.

OSC2 or clock output or I/O pin.

Legend: TTL = TTL input, ST = Schmitt Trigger input

TABLE 9-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on

POR,

BOR

Value on

All Other

RESETS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTA

LATA

—

RA6

RA5

RA4

RA3

RA2

RA1

RA0

-x0x 0000 -u0u 0000

-xxx xxxx -uuu uuuu

-111 1111 -111 1111

00-- 0000 00-- 0000

LATA Data Output Register

TRISA

ADCON1

PORTA Data Direction Register

ADFM ADCS2

—

PCFG3

PCFG2

PCFG1

PCFG0

Legend: x= unknown, u= unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.

DS39564C-page 89

PIC18FXX2

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

9.2

PORTB, TRISB and LATB

Registers

PORTB is an 8-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB pin

an input (i.e., put the corresponding output driver in a

Hi-Impedance mode). Clearing a TRISB bit (= 0) will

make the corresponding PORTB pin an output (i.e., put

the contents of the output latch on the selected pin).

RB3 can be configured by the configuration bit

CCP2MX as the alternate peripheral pin for the CCP2

module (CCP2MX=’0’).

FIGURE 9-4:

BLOCK DIAGRAM OF

The Data Latch register (LATB) is also memory

mapped. Read-modify-write operations on the LATB

register reads and writes the latched output value for

PORTB.

RB7:RB4 PINS

VDD

RBPU⁽²⁾

Data Bus

Weak

P

Pull-up

Data Latch

D

Q

EXAMPLE 9-2:

CLRF

INITIALIZING PORTB

I/O pin⁽¹⁾

PORTB

; Initialize PORTB by

; clearing output

; data latches

WR LATB

or

PORTB

CK

TRIS Latch

D

Q

CLRF

LATB

; Alternate method

; to clear output

; data latches

WR TRISB

TTL

CK

Input

Buffer

ST

Buffer

MOVLW 0xCF

; Value used to

; initialize data

; direction

RD TRISB

RD LATB

MOVWF TRISB

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

Latch

Q

D

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is per-

formed by clearing bit RBPU (INTCON2<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

EN

Q1

RD PORTB

Set RBIF

D

RD PORTB

Q3

From other

EN

RB7:RB4 pins

Note: On a Power-on Reset, these pins are

RB7:RB5 in Serial Programming mode

configured as digital inputs.

Note 1: I/O pins have diode protection to VDD and VSS.

Four of the PORTB pins, RB7:RB4, have an interrupt-

on-change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

configured as an output is excluded from the interrupt-

on-change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed together to generate the RB Port Change

Interrupt with flag bit, RBIF (INTCON<0>).

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU bit (INTCON2<7>).

Note 1: While in Low Voltage ICSP mode, the

RB5 pin can no longer be used as a gen-

eral purpose I/O pin, and should be held

low during normal operation to protect

against inadvertent ICSP mode entry.

This interrupt can wake the device from SLEEP. The

user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

2: When using Low Voltage ICSP program-

ming (LVP), the pull-up on RB5 becomes

disabled. If TRISB bit 5 is cleared,

thereby setting RB5 as an output, LATB

bit 5 must also be cleared for proper

operation.

a) Any read or write of PORTB (except with the

MOVFF instruction). This will end the mismatch

condition.

b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

DS39564C-page 90

PIC18FXX2

FIGURE 9-5:

BLOCK DIAGRAM OF RB2:RB0 PINS

VDD

RBPU⁽²⁾

Weak

P

Pull-up

Data Latch

Data Bus

D

Q

I/O pin⁽¹⁾

WR Port

CK

TRIS Latch

D

Q

TTL

Input

Buffer

WR TRIS

CK

RD TRIS

RD Port

Q

D

EN

RB0/INT

Schmitt Trigger

Buffer

RD Port

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

FIGURE 9-6:

BLOCK DIAGRAM OF RB3 PIN

VDD

Weak

RBPU⁽²⁾

CCP2MX

P

Pull-up

CCP Output⁽³⁾

1

0

VDD

P

Enable⁽³⁾

CCP Output

Data Latch

I/O pin⁽¹⁾

Data Bus

D

Q

WR LATB or

WR PORTB

N

CK

VSS

TRIS Latch

D

TTL

WR TRISB

Input

CK

Q

Buffer

RD TRISB

RD LATB

D

Q

EN

RD PORTB

CCP2 Input⁽³⁾

Schmitt Trigger

Buffer

CCP2MX = 0

Note 1: I/O pin has diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).

3: The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (=’0’) in the configuration register.

DS39564C-page 91

PIC18FXX2

TABLE 9-3:

PORTB FUNCTIONS

Name

Bit#

Buffer

Function

RB0/INT0

bit0

TTL/ST⁽¹⁾Input/output pin or external interrupt input0.

Internal software programmable weak pull-up.

RB1/INT1

bit1

bit2

bit3

TTL/ST⁽¹⁾Input/output pin or external interrupt input1.

Internal software programmable weak pull-up.

TTL/ST⁽¹⁾Input/output pin or external interrupt input2.

Internal software programmable weak pull-up.

TTL/ST⁽⁴⁾Input/output pin or Capture2 input/Compare2 output/PWM output when

CCP2MX configuration bit is enabled.

RB2/INT2

RB3/CCP2⁽³⁾

Internal software programmable weak pull-up.

RB4

bit4

bit5

TTL

Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.

RB5/PGM⁽⁵⁾

TTL/ST⁽²⁾Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.

Low voltage ICSP enable pin.

RB6/PGC

RB7/PGD

bit6

bit7

TTL/ST⁽²⁾Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.

Serial programming clock.

TTL/ST⁽²⁾Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.

Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on.

4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.

5: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB5 I/O function. LVP

must be disabled to enable RB5 as an I/O pin and allow maximum compatibility to the other 28-pin and

40-pin mid-range devices.

TABLE 9-4:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTB

LATB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx

1111 1111

0000 000x

uuuu uuuu

1111 1111

0000 000u

LATB Data Output Register

TRISB

INTCON

PORTB Data Direction Register

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF INT0IF

RBIF

INTCON2

RBPU INTEDG0 INTEDG1 INTEDG2

INT2IP INT1IP INT2IE

—

TMR0IP

—

RBIP

1111 -1-1

11-0 0-00

1111 -1-1

11-0 0-00

INTCON3

—

INT1IE

INT2IF

INT1IF

Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.

DS39564C-page 92

PIC18FXX2

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register,

without concern due to peripheral overrides.

9.3

PORTC, TRISC and LATC

Registers

PORTC is an 8-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISC. Setting a

TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a Hi-Impedance mode). Clearing a TRISC bit (= 0) will

make the corresponding PORTC pin an output (i.e., put

the contents of the output latch on the selected pin).

RC1 is normally configured by configuration bit,

CCP2MX, as the default peripheral pin of the CCP2

module (default/erased state, CCP2MX = ’1’).

EXAMPLE 9-3:

INITIALIZING PORTC

CLRF

PORTC

; Initialize PORTC by

; clearing output

; data latches

The Data Latch register (LATC) is also memory

mapped. Read-modify-write operations on the LATC

register reads and writes the latched output value for

PORTC.

CLRF

LATC

; Alternate method

; to clear output

; data latches

MOVLW 0xCF

; Value used to

PORTC is multiplexed with several peripheral functions

(Table 9-5). PORTC pins have Schmitt Trigger input

buffers.

; initialize data

; direction

MOVWF TRISC

; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an out-

put, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the corre-

sponding peripheral section for the correct TRIS bit

settings.

Note: On a Power-on Reset, these pins are

configured as digital inputs.

FIGURE 9-7:

PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

Port/Peripheral Select⁽²⁾

VDD

Peripheral Data Out

RD LATC

0

Data Latch

Data Bus

D

Q

P

WR LATC or

WR PORTC

1

I/O pin⁽¹⁾

CK

TRIS Latch

D

Q

WR TRISC

RD TRISC

CK

Q

N

Schmitt

Trigger

VSS

Peripheral Output

Enable⁽³⁾

D

Q

EN

RD PORTC

Peripheral Data In

Note 1: I/O pins have diode protection to VDD and VSS.

2: Port/Peripheral Select signal selects between port data (input) and peripheral output.

3: Peripheral Output Enable is only active if peripheral select is active.

DS39564C-page 93

PIC18FXX2

TABLE 9-5:

Name

PORTC FUNCTIONS

Bit# Buffer Type

Function

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

bit0

bit1

ST

Input/output port pin or Timer1 oscillator output/Timer1 clock input.

Input/output port pin, Timer1 oscillator input, or Capture2 input/

Compare2 output/PWM output when CCP2MX configuration bit is

set.

RC2/CCP1

bit2

bit3

ST

Input/output port pin or Capture1 input/Compare1 output/PWM1

output.

RC3 can also be the synchronous serial clock for both SPI and I²C

RC3/SCK/SCL

modes.

RC4/SDI/SDA

RC5/SDO

bit4

bit5

bit6

ST

RC4 can also be the SPI Data In (SPI mode) or Data I/O (I²C mode).

Input/output port pin or Synchronous Serial Port data output.

RC6/TX/CK

Input/output port pin, Addressable USART Asynchronous Transmit, or

Addressable USART Synchronous Clock.

RC7/RX/DT

bit7

ST

Input/output port pin, Addressable USART Asynchronous Receive, or

Addressable USART Synchronous Data.

Legend: ST = Schmitt Trigger input

TABLE 9-6:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTC

LATC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

xxxx xxxx

1111 1111

uuuu uuuu

1111 1111

LATC Data Output Register

TRISC

PORTC Data Direction Register

Legend: x= unknown, u= unchanged

DS39564C-page 94

PIC18FXX2

FIGURE 9-8:

PORTD BLOCK DIAGRAM

IN I/O PORT MODE

9.4

PORTD, TRISD and LATD

Registers

This section is applicable only to the PIC18F4X2

devices.

RD LATD

PORTD is an 8-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISD. Setting a

TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., put the corresponding output driver in

a Hi-Impedance mode). Clearing a TRISD bit (= 0) will

make the corresponding PORTD pin an output (i.e., put

the contents of the output latch on the selected pin).

Data

Bus

D

Q

I/O pin⁽¹⁾

WR LATD

or

PORTD

CK

Data Latch

D

Q

The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD

register reads and writes the latched output value for

PORTD.

WR TRISD

Schmitt

Trigger

Input

CK

TRIS Latch

Buffer

PORTD is an 8-bit port with Schmitt Trigger input buff-

ers. Each pin is individually configurable as an input or

output.

RD TRISD

Q

D

Note: On a Power-on Reset, these pins are

configured as digital inputs.

EN

PORTD can be configured as an 8-bit wide micropro-

cessor port (parallel slave port) by setting control bit

PSPMODE (TRISE<4>). In this mode, the input buffers

are TTL. See Section 9.6 for additional information on

the Parallel Slave Port (PSP).

RD PORTD

Note 1: I/O pins have diode protection to VDD and VSS.

EXAMPLE 9-4:

INITIALIZING PORTD

CLRF

PORTD ; Initialize PORTD by

; clearing output

; data latches

CLRF

LATD

; Alternate method

; to clear output

; data latches

MOVLW 0xCF

; Value used to

; initialize data

; direction

MOVWF TRISD

; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

DS39564C-page 95

PIC18FXX2

TABLE 9-7:

Name

PORTD FUNCTIONS

Bit#

Buffer Type

Function

RD0/PSP0

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

ST/TTL⁽¹⁾

Input/output port pin or parallel slave port bit0.

Input/output port pin or parallel slave port bit1.

Input/output port pin or parallel slave port bit2.

Input/output port pin or parallel slave port bit3.

Input/output port pin or parallel slave port bit4.

Input/output port pin or parallel slave port bit5.

Input/output port pin or parallel slave port bit6.

Input/output port pin or parallel slave port bit7.

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode.

TABLE 9-8:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTD

LATD

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

xxxx xxxx

1111 1111

0000 -111

uuuu uuuu

1111 1111

0000 -111

LATD Data Output Register

TRISD

TRISE

PORTD Data Direction Register

IBF

OBF

IBOV

PSPMODE

—

PORTE Data Direction bits

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.

DS39564C-page 96

PIC18FXX2

FIGURE 9-9:

PORTEBLOCKDIAGRAM

IN I/O PORT MODE

9.5

PORTE, TRISE and LATE

Registers

This section is only applicable to the PIC18F4X2

devices.

RD LATE

PORTE is a 3-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISE. Setting a

TRISE bit (= 1) will make the corresponding PORTE pin

an input (i.e., put the corresponding output driver in a

Hi-Impedance mode). Clearing a TRISE bit (= 0) will

make the corresponding PORTE pin an output (i.e., put

the contents of the output latch on the selected pin).

Data

Bus

D

Q

I/O pin⁽¹⁾

WR LATE

or

PORTE

CK

Data Latch

D

Q

The Data Latch register (LATE) is also memory

mapped. Read-modify-write operations on the LATE

register reads and writes the latched output value for

PORTE.

WR TRISE

Schmitt

Trigger

Input

CK

TRIS Latch

Buffer

PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6

and RE2/CS/AN7) which are individually configurable

as inputs or outputs. These pins have Schmitt Trigger

input buffers.

RD TRISE

Q

D

Register 9-1 shows the TRISE register, which also

controls the parallel slave port operation.

EN

PORTE pins are multiplexed with analog inputs. When

selected as an analog input, these pins will read as '0's.

RD PORTE

To Analog Converter

TRISE controls the direction of the RE pins, even when

they are being used as analog inputs. The user must

make sure to keep the pins configured as inputs when

using them as analog inputs.

Note 1: I/O pins have diode protection to VDD and VSS.

Note: On a Power-on Reset, these pins are

configured as analog inputs.

EXAMPLE 9-5:

INITIALIZING PORTE

CLRF

PORTE

; Initialize PORTE by

; clearing output

; data latches

CLRF

LATE

; Alternate method

; to clear output

; data latches

MOVLW 0x07

; Configure A/D

MOVWF ADCON1 ; for digital inputs

MOVLW 0x05

; Value used to

; initialize data

; direction

MOVWF TRISE

; Set RE<0> as inputs

; RE<1> as outputs

; RE<2> as inputs

DS39564C-page 97

PIC18FXX2

REGISTER 9-1:

TRISE REGISTER

R-0

IBF

R-0

R/W-0

IBOV

R/W-0

U-0

—

R/W-1

OBF

PSPMODE

TRISE2

TRISE1

TRISE0

bit 7

bit 0

bit 7

bit 6

bit 5

IBF: Input Buffer Full Status bit

1= A word has been received and waiting to be read by the CPU

0= No word has been received

OBF: Output Buffer Full Status bit

1= The output buffer still holds a previously written word

0= The output buffer has been read

IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)

1= A write occurred when a previously input word has not been read

(must be cleared in software)

0= No overflow occurred

bit 4

PSPMODE: Parallel Slave Port Mode Select bit

1= Parallel Slave Port mode

0= General purpose I/O mode

bit 3

bit 2

Unimplemented: Read as '0'

TRISE2: RE2 Direction Control bit

1= Input

0= Output

bit 1

bit 0

TRISE1: RE1 Direction Control bit

1= Input

0= Output

TRISE0: RE0 Direction Control bit

1= Input

0= Output

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 98

PIC18FXX2

TABLE 9-9:

Name

PORTE FUNCTIONS

Bit#

Buffer Type

Function

Input/output port pin or read control input in Parallel Slave Port mode

or analog input:

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

bit0

ST/TTL⁽¹⁾

RD

1= Not a read operation

0= Read operation. Reads PORTD register (if chip selected).

Input/output port pin or write control input in Parallel Slave Port mode

or analog input:

bit1

bit2

ST/TTL⁽¹⁾

WR

1= Not a write operation

0= Write operation. Writes PORTD register (if chip selected).

Input/output port pin or chip select control input in Parallel Slave Port

mode or analog input:

CS

1= Device is not selected

0= Device is selected

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.

TABLE 9-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Other

RESETS

PORTE

LATE

—

RE2

RE1

RE0

---- -000

---- -xxx

0000 -111

00-- 0000

---- -000

---- -uuu

0000 -111

00-- 0000

—

PSPMODE

—

LATE Data Output Register

PORTE Data Direction bits

TRISE

IBF

OBF

IBOV

—

ADCON1 ADFM ADCS2

PCFG3

PCFG2

PCFG1

PCFG0

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE.

DS39564C-page 99

PIC18FXX2

FIGURE 9-10:

PORTD AND PORTE

BLOCK DIAGRAM

(PARALLEL SLAVE

PORT)

9.6

Parallel Slave Port

The Parallel Slave Port is implemented on the 40-pin

devices only (PIC18F4X2).

PORTD operates as an 8-bit wide Parallel Slave Port,

or microprocessor port when control bit, PSPMODE

(TRISE<4>) is set. It is asynchronously readable and

writable by the external world through RD control input

pin, RE0/RD and WR control input pin, RE1/WR.

Data Bus

D

Q

RDx

WR LATD

or

CK

PORTD

It can directly interface to an 8-bit microprocessor data

bus. The external microprocessor can read or write the

PORTD latch as an 8-bit latch. Setting bit PSPMODE

enables port pin RE0/RD to be the RD input, RE1/WR

to be the WR input and RE2/CS to be the CS (chip

select) input. For this functionality, the corresponding

data direction bits of the TRISE register (TRISE<2:0>)

must be configured as inputs (set). The A/D port config-

uration bits PCFG2:PCFG0 (ADCON1<2:0>) must be

set, which will configure pins RE2:RE0 as digital I/O.

TTL

Data Latch

Q

D

RD PORTD

EN

TRIS Latch

RD LATD

A write to the PSP occurs when both the CS and WR

lines are first detected low. A read from the PSP occurs

when both the CS and RD lines are first detected low.

One bit of PORTD

Set Interrupt Flag

PSPIF (PIR1<7>)

The PORTE I/O pins become control inputs for the

microprocessor port when bit PSPMODE (TRISE<4>)

is set. In this mode, the user must make sure that the

TRISE<2:0> bits are set (pins are configured as digital

inputs), and the ADCON1 is configured for digital I/O.

In this mode, the input buffers are TTL.

Read

RD

CS

TTL

Chip Select

TTL

Write

WR

TTL

Note: I/O pin has protection diodes to VDD and VSS.

FIGURE 9-11:

PARALLEL SLAVE PORT WRITE WAVEFORMS

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

CS

WR

RD

PORTD<7:0>

IBF

OBF

PSPIF

DS39564C-page 100

PIC18FXX2

FIGURE 9-12:

PARALLEL SLAVE PORT READ WAVEFORMS

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

CS

WR

RD

PORTD<7:0>

IBF

OBF

PSPIF

TABLE 9-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTD

LATD

Port Data Latch when written; Port pins when read

LATD Data Output bits

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

---- -000 ---- -000

---- -xxx ---- -uuu

0000 -111 0000 -111

0000 000x 0000 000u

TRISD

PORTE

LATE

PORTD Data Direction bits

—

RE2

RE1

RE0

LATE Data Output bits

PORTE Data Direction bits

TMR0IF INT0IF RBIF

TRISE

INTCON

IBF

OBF

IBOV

TMR0IF

PSPMODE

INT0IE

—

GIE/

GIEH

PEIE/

GIEL

RBIE

PIR1

PSPIF

PSPIE

PSPIP

ADFM

ADIF

ADIE

RCIF

RCIE

RCIP

—

TXIF

TXIE

TXIP

—

SSPIF

SSPIE

SSPIP

CCP1IF TMR2IF

TMR1IF 0000 0000 0000 0000

PIE1

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

IPR1

ADIP

ADCON1

ADCS2

PCFG3 PCFG2

PCFG1

PCFG0

00-- 0000 00-- 0000

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.

DS39564C-page 101

PIC18FXX2

NOTES:

DS39564C-page 102

PIC18FXX2

Figure 10-1 shows a simplified block diagram of the

Timer0 module in 8-bit mode and Figure 10-2 shows a

simplified block diagram of the Timer0 module in 16-bit

mode.

10.0 TIMER0 MODULE

The Timer0 module has the following features:

• Software selectable as an 8-bit or 16-bit timer/

counter

The T0CON register (Register 10-1) is a readable and

writable register that controls all the aspects of Timer0,

including the prescale selection.

• Readable and writable

• Dedicated 8-bit software programmable prescaler

• Clock source selectable to be external or internal

• Interrupt-on-overflow from FFh to 00h in 8-bit

mode and FFFFh to 0000h in 16-bit mode

• Edge select for external clock

REGISTER 10-1: T0CON: TIMER0 CONTROL REGISTER

R/W-1

TMR0ON

bit 7

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

T0PS2

R/W-1

T0PS1

R/W-1

T0PS0

bit 0

T08BIT

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

TMR0ON: Timer0 On/Off Control bit

1= Enables Timer0

0= Stops Timer0

T08BIT: Timer0 8-bit/16-bit Control bit

1= Timer0 is configured as an 8-bit timer/counter

0= Timer0 is configured as a 16-bit timer/counter

T0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (CLKO)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Timer0 Prescaler Assignment bit

1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.

0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.

T0PS2:T0PS0: Timer0 Prescaler Select bits

111= 1:256 prescale value

110= 1:128 prescale value

101= 1:64 prescale value

100= 1:32 prescale value

011= 1:16 prescale value

010= 1:8 prescale value

001= 1:4 prescale value

000= 1:2 prescale value

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 103

PIC18FXX2

FIGURE 10-1:

TIMER0 BLOCK DIAGRAM IN 8-BIT MODE

Data Bus

FOSC/4

0

1

8

1

Sync with

Internal

Clocks

TMR0L

RA4/T0CKI pin

Programmable

Prescaler

0

(2 TCY delay)

T0SE

3

PSA

Set Interrupt

Flag bit TMR0IF

on Overflow

T0PS2, T0PS1, T0PS0

T0CS

Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

FIGURE 10-2:

TIMER0 BLOCK DIAGRAM IN 16-BIT MODE

FOSC/4

0

1

Sync with

Set Interrupt

Flag bit TMR0IF

on Overflow

TMR0

High Byte

Internal

Clocks

1

TMR0L

Programmable

Prescaler

T0CKI pin

0

8

(2 TCY delay)

T0SE

3

Read TMR0L

Write TMR0L

T0PS2, T0PS1, T0PS0

T0CS

PSA

8

TMR0H

8

Data Bus<7:0>

Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

DS39564C-page 104

PIC18FXX2

10.2.1 SWITCHING PRESCALER ASSIGNMENT

10.1 Timer0 Operation

Timer0 can operate as a timer or as a counter.

The prescaler assignment is fully under software con-

trol, (i.e., it can be changed “on-the-fly” during program

execution).

Timer mode is selected by clearing the T0CS bit. In

Timer mode, the Timer0 module will increment every

instruction cycle (without prescaler). If the TMR0L reg-

ister is written, the increment is inhibited for the follow-

ing two instruction cycles. The user can work around

this by writing an adjusted value to the TMR0L register.

10.3 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h in 8-bit mode, or FFFFh

to 0000h in 16-bit mode. This overflow sets the TMR0IF

bit. The interrupt can be masked by clearing the

TMR0IE bit. The TMR0IE bit must be cleared in soft-

ware by the Timer0 module Interrupt Service Routine

before re-enabling this interrupt. The TMR0 interrupt

cannot awaken the processor from SLEEP, since the

timer is shut-off during SLEEP.

Counter mode is selected by setting the T0CS bit. In

Counter mode, Timer0 will increment, either on every

rising or falling edge of pin RA4/T0CKI. The increment-

ing edge is determined by the Timer0 Source Edge

Select bit (T0SE). Clearing the T0SE bit selects the ris-

ing edge. Restrictions on the external clock input are

discussed below.

When an external clock input is used for Timer0, it must

meet certain requirements. The requirements ensure

the external clock can be synchronized with the internal

phase clock (TOSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

10.4 16-Bit Mode Timer Reads and

Writes

TMR0H is not the high byte of the timer/counter in

16-bit mode, but is actually a buffered version of the

high byte of Timer0 (refer to Figure 10-2). The high byte

of the Timer0 counter/timer is not directly readable nor

writable. TMR0H is updated with the contents of the

high byte of Timer0 during a read of TMR0L. This pro-

vides the ability to read all 16-bits of Timer0 without

having to verify that the read of the high and low byte

were valid due to a rollover between successive reads

of the high and low byte.

10.2 Prescaler

An 8-bit counter is available as a prescaler for the Timer0

module. The prescaler is not readable or writable.

The PSA and T0PS2:T0PS0 bits determine the

prescaler assignment and prescale ratio.

Clearing bit PSA will assign the prescaler to the Timer0

module. When the prescaler is assigned to the Timer0

module, prescale values of 1:2, 1:4,..., 1:256 are

selectable.

A write to the high byte of Timer0 must also take place

through the TMR0H buffer register. Timer0 high byte is

updated with the contents of TMR0H when a write

occurs to TMR0L. This allows all 16-bits of Timer0 to be

updated at once.

When assigned to the Timer0 module, all instructions

writing to the TMR0L register (e.g., CLRF TMR0,

MOVWF TMR0, BSF TMR0, x....etc.) will clear the

prescaler count.

Note: Writing to TMR0L when the prescaler is

assigned to Timer0 will clear the prescaler

count, but will not change the prescaler

assignment.

TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TMR0L

TMR0H

INTCON

T0CON

TRISA

Timer0 Module Low Byte Register

Timer0 Module High Byte Register

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0000 000x 0000 000u

1111 1111 1111 1111

-111 1111 -111 1111

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

PSA

TMR0IF INT0IF

T0PS2 T0PS1

RBIF

TMR0ON

—

T08BIT

T0CS

T0SE

T0PS0

PORTA Data Direction Register

Legend: x= unknown, u= unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

DS39564C-page 105

PIC18FXX2

NOTES:

DS39564C-page 106

PIC18FXX2

Figure 11-1 is a simplified block diagram of the Timer1

module.

11.0 TIMER1 MODULE

The Timer1 module timer/counter has the following

features:

Register 11-1 details the Timer1 control register. This

register controls the Operating mode of the Timer1

module, and contains the Timer1 oscillator enable bit

(T1OSCEN). Timer1 can be enabled or disabled by

setting or clearing control bit TMR1ON (T1CON<0>).

• 16-bit timer/counter

(two 8-bit registers; TMR1H and TMR1L)

• Readable and writable (both registers)

• Internal or external clock select

• Interrupt-on-overflow from FFFFh to 0000h

• RESET from CCP module special event trigger

REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0

RD16

U-0

—

R/W-0

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 0

bit 7

RD16: 16-bit Read/Write Mode Enable bit

1= Enables register Read/Write of Timer1 in one 16-bit operation

0= Enables register Read/Write of Timer1 in two 8-bit operations

bit 6

Unimplemented: Read as '0'

bit 5-4

T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3

bit 2

T1OSCEN: Timer1 Oscillator Enable bit

1= Timer1 Oscillator is enabled

0= Timer1 Oscillator is shut-off

The oscillator inverter and feedback resistor are turned off to eliminate power drain.

T1SYNC: Timer1 External Clock Input Synchronization Select bit

When TMR1CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

TMR1CS: Timer1 Clock Source Select bit

bit 1

bit 0

1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)

0= Internal clock (FOSC/4)

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 107

PIC18FXX2

When TMR1CS = 0, Timer1 increments every instruc-

tion cycle. When TMR1CS = 1, Timer1 increments on

every rising edge of the external clock input or the

Timer1 oscillator, if enabled.

11.1 Timer1 Operation

Timer1 can operate in one of these modes:

• As a timer

• As a synchronous counter

• As an asynchronous counter

When the Timer1 oscillator is enabled (T1OSCEN is

set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins

become inputs. That is, the TRISC<1:0> value is

ignored, and the pins are read as ‘0’.

The Operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>).

Timer1 also has an internal “RESET input”. This

RESET can be generated by the CCP module

(Section 14.0).

FIGURE 11-1:

TIMER1 BLOCK DIAGRAM

CCP Special Event Trigger

TMR1IF

Overflow

Interrupt

Flag Bit

Synchronized

Clock Input

TMR1

CLR

0

TMR1L

TMR1H

1

TMR1ON

On/Off

T1SYNC

T1OSC

1

T1CKI/T1OSO

T1OSI

Synchronize

det

T1OSCEN

Enable

Oscillator

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

(1)

0

2

SLEEP Input

T1CKPS1:T1CKPS0

TMR1CS

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

FIGURE 11-2:

TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE

Data Bus<7:0>

8

TMR1H

8

Write TMR1L

Read TMR1L

CCP Special Event Trigger

TMR1IF

Overflow

Interrupt

Synchronized

Clock Input

TMR1

8

0

CLR

Timer 1

High Byte

TMR1L

Flag bit

1

TMR1ON

on/off

T1SYNC

T1OSC

T13CKI/T1OSO

1

Synchronize

det

Prescaler

1, 2, 4, 8

T1OSCEN

Enable

FOSC/4

Internal

Clock

0

(1)

T1OSI

Oscillator

2

SLEEP Input

TMR1CS

T1CKPS1:T1CKPS0

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

DS39564C-page 108

PIC18FXX2

11.2 Timer1 Oscillator

11.4 Resetting Timer1 using a CCP

Trigger Output

A crystal oscillator circuit is built-in between pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control bit T1OSCEN (T1CON<3>). The oscilla-

tor is a low power oscillator rated up to 200 kHz. It will

continue to run during SLEEP. It is primarily intended

for a 32 kHz crystal. Table 11-1 shows the capacitor

selection for the Timer1 oscillator.

If the CCP module is configured in Compare mode to

generate a “special event trigger” (CCP1M3:CCP1M0

= 1011), this signal will reset Timer1 and start an A/D

conversion (if the A/D module is enabled).

Note: The special event triggers from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

The user must provide a software time delay to ensure

proper start-up of the Timer1 oscillator.

Timer1 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this RESET operation may not work.

TABLE 11-1: CAPACITOR SELECTION FOR

THE ALTERNATE

OSCILLATOR

In the event that a write to Timer1 coincides with a

special event trigger from CCP1, the write will take

precedence.

Osc Type

Freq

C1

C2

LP

32 kHz

TBD⁽¹⁾

In this mode of operation, the CCPR1H:CCPR1L regis-

ters pair effectively becomes the period register for

Timer1.

Crystal to be Tested:

32.768 kHz Epson C-001R32.768K-A

20 PPM

11.5 Timer1 16-Bit Read/Write Mode

Note 1: Microchip suggests 33 pF as a starting

Timer1 can be configured for 16-bit reads and writes

(see Figure 11-2). When the RD16 control bit

(T1CON<7>) is set, the address for TMR1H is mapped

to a buffer register for the high byte of Timer1. A read

from TMR1L will load the contents of the high byte of

Timer1 into the Timer1 high byte buffer. This provides

the user with the ability to accurately read all 16-bits of

Timer1 without having to determine whether a read of

the high byte followed by a read of the low byte is valid,

due to a rollover between reads.

point in validating the oscillator circuit.

2: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the

resonator/crystal

manufacturer

for appropriate values of external

components.

4: Capacitor values are for design guidance

A write to the high byte of Timer1 must also take place

through the TMR1H buffer register. Timer1 high byte is

updated with the contents of TMR1H when a write

occurs to TMR1L. This allows a user to write all 16 bits

to both the high and low bytes of Timer1 at once.

only.

11.3 Timer1 Interrupt

The TMR1 Register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

TMR1 Interrupt, if enabled, is generated on overflow,

which is latched in interrupt flag bit TMR1IF (PIR1<0>).

This interrupt can be enabled/disabled by setting/

clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>).

The high byte of Timer1 is not directly readable or writ-

able in this mode. All reads and writes must take place

through the Timer1 high byte buffer register. Writes to

TMR1H do not clear the Timer1 prescaler. The

prescaler is only cleared on writes to TMR1L.

DS39564C-page 109

PIC18FXX2

TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

(1)

PIR1

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

(1)

PIE1

TXIE

TXIP

IPR1

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

T1CON RD16

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.

DS39564C-page 110

PIC18FXX2

12.1 Timer2 Operation

12.0 TIMER2 MODULE

Timer2 can be used as the PWM time-base for the

PWM mode of the CCP module. The TMR2 register is

readable and writable, and is cleared on any device

RESET. The input clock (F^OSC/4) has a prescale option

of 1:1, 1:4 or 1:16, selected by control bits

T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-

put of TMR2 goes through a 4-bit postscaler (which

gives a 1:1 to 1:16 scaling inclusive) to generate a

TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)).

The Timer2 module timer has the following features:

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match of PR2

• SSP module optional use of TMR2 output to

generate clock shift

The prescaler and postscaler counters are cleared

when any of the following occurs:

Timer2 has a control register shown in Register 12-1.

Timer2 can be shut-off by clearing control bit TMR2ON

(T2CON<2>) to minimize power consumption.

Figure 12-1 is a simplified block diagram of the Timer2

module. Register 12-1 shows the Timer2 control regis-

ter. The prescaler and postscaler selection of Timer2

are controlled by this register.

• a write to the TMR2 register

• a write to the T2CON register

• any device RESET (Power-on Reset, MCLR

Reset, Watchdog Timer Reset, or Brown-out

Reset)

TMR2 is not cleared when T2CON is written.

REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER

U-0

—

R/W-0

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 0

bit 7

Unimplemented: Read as '0'

bit 6-3

TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000= 1:1 Postscale

0001= 1:2 Postscale

•

1111= 1:16 Postscale

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0

T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 111

PIC18FXX2

12.2 Timer2 Interrupt

12.3 Output of TMR2

The Timer2 module has an 8-bit period register, PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

initialized to FFh upon RESET.

The output of TMR2 (before the postscaler) is fed to the

Synchronous Serial Port module, which optionally uses

it to generate the shift clock.

FIGURE 12-1:

TIMER2 BLOCK DIAGRAM

Sets Flag

TMR2

bit TMR2IF

(1)

Output

Prescaler

RESET

EQ

TMR2

FOSC/4

1:1, 1:4, 1:16

Postscaler

1:1 to 1:16

2

Comparator

PR2

T2CKPS1:T2CKPS0

4

TOUTPS3:TOUTPS0

Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.

TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

CCP1IF

INT0IF

RBIF

0000 000x 0000 000u

(1)

PIR1

PIE1

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TMR2IF

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

TMR1IP 0000 0000 0000 0000

0000 0000 0000 0000

(1)

TXIE

TXIP

CCP1IE TMR2IE

CCP1IP TMR2IP

IPR1

TMR2

T2CON

PR2

Timer2 Module Register

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Timer2 Period Register 1111 1111 1111 1111

Legend: x= unknown, u= unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.

DS39564C-page 112

PIC18FXX2

Figure 13-1 is a simplified block diagram of the Timer3

module.

13.0 TIMER3 MODULE

The Timer3 module timer/counter has the following

features:

Register 13-1 shows the Timer3 control register. This

register controls the Operating mode of the Timer3

module and sets the CCP clock source.

• 16-bit timer/counter

(two 8-bit registers; TMR3H and TMR3L)

Register 11-1 shows the Timer1 control register. This

register controls the Operating mode of the Timer1

module, as well as contains the Timer1 oscillator

enable bit (T1OSCEN), which can be a clock source for

Timer3.

• Readable and writable (both registers)

• Internal or external clock select

• Interrupt-on-overflow from FFFFh to 0000h

• RESET from CCP module trigger

REGISTER 13-1: T3CON: TIMER3 CONTROL REGISTER

R/W-0

RD16

R/W-0

T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

bit 0

bit 7

RD16: 16-bit Read/Write Mode Enable bit

1= Enables register Read/Write of Timer3 in one 16-bit operation

0= Enables register Read/Write of Timer3 in two 8-bit operations

bit 6-3

T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits

1x=Timer3 is the clock source for compare/capture CCP modules

01=Timer3 is the clock source for compare/capture of CCP2,

Timer1 is the clock source for compare/capture of CCP1

00=Timer1 is the clock source for compare/capture CCP modules

bit 5-4

bit 2

T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

T3SYNC: Timer3 External Clock Input Synchronization Control bit

(Not usable if the system clock comes from Timer1/Timer3)

When TMR3CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

When TMR3CS = 0:

This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

TMR3CS: Timer3 Clock Source Select bit

bit 1

bit 0

1= External clock input from Timer1 oscillator or T1CKI

(on the rising edge after the first falling edge)

0= Internal clock (FOSC/4)

TMR3ON: Timer3 On bit

1= Enables Timer3

0= Stops Timer3

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 113

PIC18FXX2

When TMR3CS = 0, Timer3 increments every instruc-

tion cycle. When TMR3CS = 1, Timer3 increments on

every rising edge of the Timer1 external clock input or

the Timer1 oscillator, if enabled.

13.1 Timer3 Operation

Timer3 can operate in one of these modes:

• As a timer

• As a synchronous counter

• As an asynchronous counter

When the Timer1 oscillator is enabled (T1OSCEN is

set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins

become inputs. That is, the TRISC<1:0> value is

ignored, and the pins are read as ‘0’.

The Operating mode is determined by the clock select

bit, TMR3CS (T3CON<1>).

Timer3 also has an internal “RESET input”. This RESET

can be generated by the CCP module (Section 14.0).

FIGURE 13-1:

TIMER3 BLOCK DIAGRAM

CCP Special Trigger

T3CCPx

TMR3IF

Overflow

Interrupt

Flag bit

Synchronized

Clock Input

0

CLR

TMR3L

TMR3H

T1OSC

1

TMR3ON

On/Off

T3SYNC

(3)

T1OSO/

T13CKI

1

Synchronize

det

Prescaler

1, 2, 4, 8

T1OSCEN

Enable

FOSC/4

Internal

Clock

0

(1)

T1OSI

Oscillator

2

SLEEP Input

TMR3CS

T3CKPS1:T3CKPS0

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

FIGURE 13-2:

TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE

Data Bus<7:0>

8

TMR3H

8

Write TMR3L

Read TMR3L

CCP Special Trigger

T3CCPx

0

Synchronized

Clock Input

8

TMR3

Set TMR3IF Flag bit

on Overflow

CLR

Timer3

High Byte

TMR3L

1

To Timer1 Clock Input

TMR3ON

On/Off

T3SYNC

T1OSC

T1OSO/

T13CKI

1

Synchronize

det

Prescaler

1, 2, 4, 8

T1OSCEN

Enable

FOSC/4

Internal

Clock

0

(1)

Oscillator

T1OSI

2

SLEEP Input

T3CKPS1:T3CKPS0

TMR3CS

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

DS39564C-page 114

PIC18FXX2

13.2 Timer1 Oscillator

13.4 Resetting Timer3 Using a CCP

Trigger Output

The Timer1 oscillator may be used as the clock source

for Timer3. The Timer1 oscillator is enabled by setting

the T1OSCEN (T1CON<3>) bit. The oscillator is a low

power oscillator rated up to 200 KHz. See Section 11.0

for further details.

If the CCP module is configured in Compare mode to

generate a “special event trigger” (CCP1M3:CCP1M0

= 1011), this signal will reset Timer3.

Note: The special event triggers from the CCP

module will not set interrupt flag bit,

TMR3IF (PIR1<0>).

13.3 Timer3 Interrupt

The TMR3 Register pair (TMR3H:TMR3L) increments

from 0000h to FFFFh and rolls over to 0000h. The

TMR3 Interrupt, if enabled, is generated on overflow,

which is latched in interrupt flag bit, TMR3IF

(PIR2<1>). This interrupt can be enabled/disabled by

setting/clearing TMR3 interrupt enable bit, TMR3IE

(PIE2<1>).

Timer3 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer3 is running in Asynchronous Counter mode,

this RESET operation may not work. In the event that a

write to Timer3 coincides with a special event trigger

from CCP1, the write will take precedence. In this mode

of operation, the CCPR1H:CCPR1L registers pair

effectively becomes the period register for Timer3.

TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

PIR2

—

EEIF

EEIE

EEIP

BCLIF

BCLIE

BCLIP

LVDIF

LVDIE

LVDIP

TMR3IF

TMR3IE

TMR3IP

CCP2IF ---0 0000 ---0 0000

CCP2IE ---0 0000 ---0 0000

CCP2IP ---1 1111 ---1 1111

xxxx xxxx uuuu uuuu

PIE2

IPR2

TMR3L

TMR3H

T1CON

T3CON

Holding Register for the Least Significant Byte of the 16-bit TMR3 Register

Holding Register for the Most Significant Byte of the 16-bit TMR3 Register

xxxx xxxx uuuu uuuu

RD16

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.

DS39564C-page 115

PIC18FXX2

NOTES:

DS39564C-page 116

PIC18FXX2

The operation of CCP1 is identical to that of CCP2, with

the exception of the special event trigger. Therefore,

operation of a CCP module in the following sections is

described with respect to CCP1.

14.0 CAPTURE/COMPARE/PWM

(CCP) MODULES

Each CCP (Capture/Compare/PWM) module contains

a 16-bit register which can operate as a 16-bit Capture

register, as a 16-bit Compare register or as a PWM

Master/Slave Duty Cycle register. Table 14-1 shows

the timer resources of the CCP Module modes.

Table 14-2 shows the interaction of the CCP modules.

REGISTER 14-1: CCP1CON REGISTER/CCP2CON REGISTER

U-0

—

U-0

—

R/W-0

DCxB1

DCxB0

CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit 0

bit 7

bit 7-6

bit 5-4

Unimplemented: Read as '0'

DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits

(DCx9:DCx2) of the duty cycle are found in CCPRxL.

bit 3-0

CCPxM3:CCPxM0: CCPx Mode Select bits

0000= Capture/Compare/PWM disabled (resets CCPx module)

0001= Reserved

0010= Compare mode, toggle output on match (CCPxIF bit is set)

0011= Reserved

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode,

Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set)

1001= Compare mode,

Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set)

1010= Compare mode,

Generate software interrupt on compare match (CCPIF bit is set, CCP pin is unaffected)

1011= Compare mode,

Trigger special event (CCPIF bit is set)

11xx= PWM mode

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 117

PIC18FXX2

14.1 CCP1 Module

14.2 CCP2 Module

Capture/Compare/PWM Register 1 (CCPR1) is com-

prised of two 8-bit registers: CCPR1L (low byte) and

CCPR1H (high byte). The CCP1CON register controls

the operation of CCP1. All are readable and writable.

Capture/Compare/PWM Register2 (CCPR2) is com-

prised of two 8-bit registers: CCPR2L (low byte) and

CCPR2H (high byte). The CCP2CON register controls

the operation of CCP2. All are readable and writable.

TABLE 14-1: CCP MODE - TIMER

RESOURCE

CCP Mode

Timer Resource

Capture

Compare

PWM

Timer1 or Timer3

Timer2

TABLE 14-2: INTERACTION OF TWO CCP MODULES

CCPx Mode CCPy Mode

Interaction

Capture

TMR1 or TMR3 time-base. Time-base can be different for each CCP.

Compare The compare could be configured for the special event trigger,

which clears either TMR1 or TMR3 depending upon which time-base is used.

Compare

PWM

Compare The compare(s) could be configured for the special event trigger,

which clears TMR1 or TMR3 depending upon which time-base is used.

PWM

The PWMs will have the same frequency and update rate

(TMR2 interrupt).

PWM

Capture

None

Compare None

DS39564C-page 118

PIC18FXX2

14.3.3

SOFTWARE INTERRUPT

14.3 Capture Mode

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<2>) clear to avoid false interrupts and

should clear the flag bit, CCP1IF, following any such

change in Operating mode.

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 or TMR3 registers when an

event occurs on pin RC2/CCP1. An event is defined as

one of the following:

• every falling edge

• every rising edge

14.3.4

CCP PRESCALER

• every 4th rising edge

• every 16th rising edge

There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off or the CCP module is not in Capture mode,

the prescaler counter is cleared. This means that any

RESET will clear the prescaler counter.

The event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the inter-

rupt request flag bit CCP1IF (PIR1<2>) is set; it must be

cleared in software. If another capture occurs before the

value in register CCPR1 is read, the old captured value

is overwritten by the new captured value.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore, the first capture may be from

a non-zero prescaler. Example 14-1 shows the recom-

mended method for switching between capture pres-

calers. This example also clears the prescaler counter

and will not generate the “false” interrupt.

14.3.1

CCP PIN CONFIGURATION

In Capture mode, the RC2/CCP1 pin should be

configured as an input by setting the TRISC<2> bit.

Note: If the RC2/CCP1 is configured as an out-

put, a write to the port can cause a capture

condition.

EXAMPLE 14-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF

CCP1CON, F ; Turn CCP module off

MOVLW NEW_CAPT_PS ; Load WREG with the

; new prescaler mode

14.3.2

TIMER1/TIMER3 MODE SELECTION

The timers that are to be used with the capture feature

(either Timer1 and/or Timer3) must be running in Timer

mode or Synchronized Counter mode. In Asynchro-

nous Counter mode, the capture operation may not

work. The timer to be used with each CCP module is

selected in the T3CON register.

; value and CCP ON

; Load CCP1CON with

; this value

MOVWF CCP1CON

FIGURE 14-1:

CAPTURE MODE OPERATION BLOCK DIAGRAM

TMR3H

TMR3L

CCPR1L

TMR1L

Set Flag bit CCP1IF

T3CCP2

TMR3

Enable

Prescaler

÷ 1, 4, 16

CCP1 pin

CCPR1H

TMR1

and

Edge Detect

T3CCP2

Enable

TMR1H

CCP1CON<3:0>

Q’s

Set Flag bit CCP2IF

T3CCP1

TMR3H

TMR3L

CCPR2L

TMR1L

T3CCP2

TMR3

Enable

Prescaler

÷ 1, 4, 16

CCP2 pin

CCPR2H

TMR1

and

Edge Detect

Enable

T3CCP2

T3CCP1

TMR1H

CCP2CON<3:0>

Q’s

DS39564C-page 119

PIC18FXX2

14.4.2

TIMER1/TIMER3 MODE SELECTION

14.4 Compare Mode

Timer1 and/or Timer3 must be running in Timer mode

or Synchronized Counter mode if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

In Compare mode, the 16-bit CCPR1 (CCPR2) register

value is constantly compared against either the TMR1

register pair value, or the TMR3 register pair value.

When a match occurs, the RC2/CCP1 (RC1/CCP2) pin

is:

14.4.3

SOFTWARE INTERRUPT MODE

• driven High

When generate software interrupt is chosen, the CCP1

pin is not affected. Only a CCP interrupt is generated (if

enabled).

• driven Low

• toggle output (High to Low or Low to High)

• remains unchanged

14.4.4

SPECIAL EVENT TRIGGER

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the

same time, interrupt flag bit CCP1IF (CCP2IF) is set.

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action.

14.4.1

CCP PIN CONFIGURATION

The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

The user must configure the CCPx pin as an output by

clearing the appropriate TRISC bit.

Note: Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the

default low level. This is not the PORTC

I/O data latch.

The special trigger output of CCPx resets either the

TMR1 or TMR3 register pair. Additionally, the CCP2

Special Event Trigger will start an A/D conversion if the

A/D module is enabled.

Note: The special event trigger from the CCP2

module will not set the Timer1 or Timer3

interrupt flag bits.

FIGURE 14-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

Special Event Trigger will:

Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit,

and set bit GO/DONE (ADCON0<2>)

which starts an A/D conversion (CCP2 only)

Special Event Trigger

Set Flag bit CCP1IF

CCPR1H CCPR1L

Comparator

Q

S

R

Output

Logic

Match

RC2/CCP1 pin

TRISC<2>

Output Enable

1

0

CCP1CON<3:0>

Mode Select

T3CCP2

TMR1H TMR1L

TMR3H TMR3L

Special Event Trigger

Set Flag bit CCP2IF

T3CCP1

T3CCP2

0

1

Q

S

R

Output

Logic

Comparator

Match

RC1/CCP2 pin

TRISC<1>

Output Enable

CCPR2H CCPR2L

CCP2CON<3:0>

Mode Select

DS39564C-page 120

PIC18FXX2

TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Other

RESETS

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

(1)

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

1111 1111 1111 1111

(1)

PIE1

TXIE

TXIP

IPR1

TRISC

TMR1L

TMR1H

T1CON

CCPR1L

PORTC Data Direction Register

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

RD16

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

Capture/Compare/PWM Register1 (LSB)

xxxx xxxx uuuu uuuu

CCPR1H Capture/Compare/PWM Register1 (MSB)

CCP1CON

CCPR2L

—

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

xxxx xxxx uuuu uuuu

Capture/Compare/PWM Register2 (LSB)

CCPR2H Capture/Compare/PWM Register2 (MSB)

xxxx xxxx uuuu uuuu

CCP2CON

PIR2

—

DC2B1

—

DC2B0

EEIE

EEIF

CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

BCLIF

BCLIE

BCLIP

LVDIF

LVDIE

LVDIP

TMR3IF CCP2IF ---0 0000 ---0 0000

TMR3IE CCP2IE ---0 0000 ---0 0000

TMR3IP CCP2IP ---1 1111 ---1 1111

PIE2

—

IPR2

—

EEIP

TMR3L

TMR3H

T3CON

Holding Register for the Least Significant Byte of the 16-bit TMR3 Register

Holding Register for the Most Significant Byte of the 16-bit TMR3 Register

xxxx xxxx uuuu uuuu

RD16

T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2x2 devices; always maintain these bits clear.

DS39564C-page 121

PIC18FXX2

14.5.1

PWM PERIOD

14.5 PWM Mode

The PWM period is specified by writing to the PR2

register. The PWM period can be calculated using the

following formula:

In Pulse Width Modulation (PWM) mode, the CCP1 pin

produces up to a 10-bit resolution PWM output. Since

the CCP1 pin is multiplexed with the PORTC data latch,

the TRISC<2> bit must be cleared to make the CCP1

pin an output.

PWM period = (PR2) + 1] • 4 • TOSC •

(TMR2 prescale value)

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTC I/O data

latch.

PWM frequency is defined as 1 / [PWM period].

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

• TMR2 is cleared

Figure 14-3 shows a simplified block diagram of the

CCP module in PWM mode.

• The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 14.5.3.

• The PWM duty cycle is latched from CCPR1L into

CCPR1H

Note: The Timer2 postscaler (see Section 12.0)

is not used in the determination of the

PWM frequency. The postscaler could be

used to have a servo update rate at a

different frequency than the PWM output.

FIGURE 14-3:

SIMPLIFIED PWM BLOCK

DIAGRAM

CCP1CON<5:4>

Duty Cycle Registers

CCPR1L

14.5.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

CCPR1H (Slave)

Comparator

Q

R

S

RC2/CCP1

(Note 1)

TMR2

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 prescale value)

TRISC<2>

Comparator

PR2

Clear Timer,

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read only register.

CCP1 pin and

latch D.C.

Note: 8-bit timer is concatenated with 2-bit internal Q clock or 2

bits of the prescaler to create 10-bit time-base.

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

A PWM output (Figure 14-4) has a time-base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

When the CCPR1H and 2-bit latch match TMR2 con-

catenated with an internal 2-bit Q clock or 2 bits of the

TMR2 prescaler, the CCP1 pin is cleared.

FIGURE 14-4:

PWM OUTPUT

The maximum PWM resolution (bits) for a given PWM

frequency is given by the equation:

Period

FOSC

⎛

⎝

⎞

⎠

---------------

log

FPWM

PWM Resolution (max)

= ----------------------------- b i t s

log(2)

Duty Cycle

TMR2 = PR2

Note: If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

TMR2 = Duty Cycle

TMR2 = PR2

DS39564C-page 122

PIC18FXX2

3. Make the CCP1 pin an output by clearing the

TRISC<2> bit.

14.5.3

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

4. Set the TMR2 prescale value and enable Timer2

by writing to T2CON.

1. Set the PWM period by writing to the PR2 register.

5. Configure the CCP1 module for PWM operation.

2. Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

TABLE 14-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency

2.44 kHz

9.77 kHz

39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16)

PR2 Value

16

0xFF

14

4

1

0x3F

8

1

0x1F

7

1

0xFF

12

0xFF

10

0x17

6.58

Maximum Resolution (bits)

TABLE 14-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

CCP1IF

INT0IF

RBIF

0000 000x 0000 000u

(1)

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TMR2IF

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

TMR1IP 0000 0000 0000 0000

1111 1111 1111 1111

(1)

PIE1

TXIE

TXIP

CCP1IE TMR2IE

CCP1IP TMR2IP

IPR1

TRISC

TMR2

PR2

PORTC Data Direction Register

Timer2 Module Register

0000 0000 0000 0000

Timer2 Module Period Register

1111 1111 1111 1111

T2CON

CCPR1L

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Capture/Compare/PWM Register1 (LSB)

xxxx xxxx uuuu uuuu

CCPR1H Capture/Compare/PWM Register1 (MSB)

CCP1CON

CCPR2L

—

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

xxxx xxxx uuuu uuuu

Capture/Compare/PWM Register2 (LSB)

CCPR2H Capture/Compare/PWM Register2 (MSB)

CCP2CON DC2B1 DC2B0

xxxx xxxx uuuu uuuu

—

CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.

DS39564C-page 123

PIC18FXX2

NOTES:

DS39564C-page 124

PIC18FXX2

15.3 SPI Mode

15.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

MODULE

The SPI mode allows 8-bits of data to be synchronously

transmitted and received, simultaneously. All four modes

of SPI are supported. To accomplish communication,

typically three pins are used:

15.1 Master SSP (MSSP) Module

Overview

• Serial Data Out (SDO) - RC5/SDO

• Serial Data In (SDI) - RC4/SDI/SDA

• Serial Clock (SCK) - RC3/SCK/SCL/LVDIN

The Master Synchronous Serial Port (MSSP) module is

a serial interface useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers, dis-

play drivers, A/D converters, etc. The MSSP module

can operate in one of two modes:

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select (SS) - RA5/SS/AN4

Figure 15-1 shows the block diagram of the MSSP

module when operating in SPI mode.

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C)

- Full Master mode

FIGURE 15-1:

MSSP BLOCK DIAGRAM

(SPI MODE)

- Slave mode (with general address call)

The I²C interface supports the following modes in

hardware:

Internal

Data Bus

• Master mode

• Multi-Master mode

• Slave mode

Read

Write

SSPBUF reg

SSPSR reg

15.2 Control Registers

RC4/SDI/SDA

RC5/SDO

The MSSP module has three associated registers.

These include a status register (SSPSTAT) and two

control registers (SSPCON1 and SSPCON2). The use

of these registers and their individual configuration bits

differ significantly, depending on whether the MSSP

module is operated in SPI or I²C mode.

shift

clock

bit0

Additional details are provided under the individual

sections.

RA5/SS/AN4

Control

Enable

SS

Edge

Select

2

Clock Select

SSPM3:SSPM0

SMP:CKE

2

4

TMR2 output

RC3/SCK/

SCL/LVDIN

(

)

2

Edge

Select

TOSC

Prescaler

4, 16, 64

Data to TX/RX in SSPSR

TRIS bit

DS39564C-page 125

PIC18FXX2

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

15.3.1

REGISTERS

The MSSP module has four registers for SPI mode

operation. These are:

In receive operations, SSPSR and SSPBUF together

create a double buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

• MSSP Control Register1 (SSPCON1)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• MSSP Shift Register (SSPSR) - Not directly

accessible

During transmission, the SSPBUF is not double buff-

ered. A write to SSPBUF will write to both SSPBUF and

SSPSR.

SSPCON1 and SSPSTAT are the control and status

registers in SPI mode operation. The SSPCON1 regis-

ter is readable and writable. The lower 6 bits of the

SSPSTAT are read only. The upper two bits of the

SSPSTAT are read/write.

REGISTER 15-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

bit 7

bit 6

SMP: Sample bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

CKE: SPI Clock Edge Select

When CKP = 0:

1= Data transmitted on rising edge of SCK

0= Data transmitted on falling edge of SCK

When CKP = 1:

1= Data transmitted on falling edge of SCK

0= Data transmitted on rising edge of SCK

bit 5

bit 4

D/A: Data/Address bit

Used in I²C mode only

P: STOP bit

Used in I²C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is

cleared.

bit 3

bit 2

bit 1

bit 0

S: START bit

Used in I²C mode only

R/W: Read/Write bit information

Used in I²C mode only

UA: Update Address

Used in I²C mode only

BF: Buffer Full Status bit (Receive mode only)

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 126

PIC18FXX2

REGISTER 15-2: SSPCON1: MSSP CONTROL REGISTER1 (SPI MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

bit 6

WCOL: Write Collision Detect bit (Transmit mode only)

1= The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

0= No collision

SSPOV: Receive Overflow Indicator bit

SPI Slave mode:

1= A new byte is received while the SSPBUF register is still holding the previous data. In case

of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user

must read the SSPBUF, even if only transmitting data, to avoid setting overflow

(must be cleared in software).

0= No overflow

Note: In Master mode, the overflow bit is not set since each new reception (and

transmission) is initiated by writing to the SSPBUF register.

bit 5

bit 4

SSPEN: Synchronous Serial Port Enable bit

1= Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins

0= Disables serial port and configures these pins as I/O port pins

Note:

When enabled, these pins must be properly configured as input or output.

CKP: Clock Polarity Select bit

1= IDLE state for clock is a high level

0= IDLE state for clock is a low level

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin

0100= SPI Slave mode, clock = SCK pin, SS pin control enabled

0011= SPI Master mode, clock = TMR2 output/2

0010= SPI Master mode, clock = FOSC/64

0001= SPI Master mode, clock = FOSC/16

0000= SPI Master mode, clock = FOSC/4

Note: Bit combinations not specifically listed here are either reserved, or implemented in

I²C mode only.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 127

PIC18FXX2

SSPBUF register during transmission/reception of data

will be ignored, and the write collision detect bit, WCOL

(SSPCON1<7>), will be set. User software must clear

the WCOL bit so that it can be determined if the follow-

ing write(s) to the SSPBUF register completed

successfully.

15.3.2

OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON1<5:0>) and SSPSTAT<7:6>.

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (IDLE state of SCK)

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. Buffer

full bit, BF (SSPSTAT<0>), indicates when SSPBUF

has been loaded with the received data (transmission

is complete). When the SSPBUF is read, the BF bit is

cleared. This data may be irrelevant if the SPI is only a

transmitter. Generally, the MSSP Interrupt is used to

determine when the transmission/reception has com-

pleted. The SSPBUF must be read and/or written. If the

interrupt method is not going to be used, then software

polling can be done to ensure that a write collision does

not occur. Example 15-1 shows the loading of the

SSPBUF (SSPSR) for data transmission.

• Data input sample phase (middle or end of data

output time)

• Clock edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

The MSSP consists of a transmit/receive Shift Register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR,

until the received data is ready. Once the 8 bits of data

have been received, that byte is moved to the SSPBUF

register. Then the buffer full detect bit, BF

(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are

set. This double buffering of the received data

(SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the

The SSPSR is not directly readable or writable, and

can only be accessed by addressing the SSPBUF reg-

ister. Additionally, the MSSP status register (SSPSTAT)

indicates the various status conditions.

EXAMPLE 15-1:

LOADING THE SSPBUF (SSPSR) REGISTER

LOOP BTFSS SSPSTAT, BF

;Has data been received(transmit complete)?

BRA

LOOP

;No

MOVF SSPBUF, W

;WREG reg = contents of SSPBUF

MOVWF RXDATA

;Save in user RAM, if data is meaningful

MOVF TXDATA, W

MOVWF SSPBUF

;W reg = contents of TXDATA

;New data to xmit

DS39564C-page 128

PIC18FXX2

15.3.3

ENABLING SPI I/O

15.3.4

TYPICAL CONNECTION

To enable the serial port, SSP Enable bit, SSPEN

(SSPCON1<5>), must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, re-initialize the

SSPCON registers, and then set the SSPEN bit. This

configures the SDI, SDO, SCK, and SS pins as serial

port pins. For the pins to behave as the serial port func-

tion, some must have their data direction bits (in the

TRIS register) appropriately programmed. That is:

Figure 15-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge, and latched on the opposite

edge of the clock. Both processors should be pro-

grammed to the same Clock Polarity (CKP), then both

controllers would send and receive data at the same

time. Whether the data is meaningful (or dummy data)

depends on the application software. This leads to

three scenarios for data transmission:

• SDI is automatically controlled by the SPI module

• SDO must have TRISC<5> bit cleared

• SCK (Master mode) must have TRISC<3> bit

cleared

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

• SCK (Slave mode) must have TRISC<3> bit set

• SS must have TRISC<4> bit set

• Master sends dummy data — Slave sends data

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

FIGURE 15-2:

SPI MASTER/SLAVE CONNECTION

SPI Master SSPM3:SSPM0 = 00xxb

SPI Slave SSPM3:SSPM0 = 010xb

SDO

SDI

Serial Input Buffer

(SSPBUF)

Serial Input Buffer

(SSPBUF)

SDI

SDO

Shift Register

(SSPSR)

Shift Register

(SSPSR)

LSb

MSb

LSb

Serial Clock

SCK

PROCESSOR 1

PROCESSOR 2

DS39564C-page 129

PIC18FXX2

Figure 15-3, Figure 15-5, and Figure 15-6, where the

MSB is transmitted first. In Master mode, the SPI clock

rate (bit rate) is user programmable to be one of the

following:

15.3.5

MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 15-2) is to

broadcast data by the software protocol.

• FOSC/4 (or TCY)

• FOSC/16 (or 4 • TCY)

• FOSC/64 (or 16 • TCY)

• Timer2 output/2

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI is

only going to receive, the SDO output could be dis-

abled (programmed as an input). The SSPSR register

will continue to shift in the signal present on the SDI pin

at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and status bits

appropriately set). This could be useful in receiver

applications as a “Line Activity Monitor” mode.

This allows a maximum data rate (at 40 MHz) of

10.00 Mbps.

Figure 15-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

data is shown.

The clock polarity is selected by appropriately program-

ming the CKP bit (SSPCON1<4>). This then, would

give waveforms for SPI communication as shown in

FIGURE 15-3:

SPI MODE WAVEFORM (MASTER MODE)

Write to

SSPBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 Clock

Modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

bit6

bit2

bit5

bit4

bit1

bit0

SDO

(CKE = 0)

bit7

bit3

SDO

(CKE = 1)

SDI

(SMP = 0)

bit0

bit7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit0

bit7

Input

Sample

(SMP = 1)

SSPIF

Next Q4 cycle

after Q2↓

SSPSR to

SSPBUF

DS39564C-page 130

PIC18FXX2

longer driven, even if in the middle of a transmitted

byte, and becomes a floating output. External pull-up/

pull-down resistors may be desirable, depending on the

application.

15.3.6

SLAVE MODE

In Slave mode, the data is transmitted and received as

the external clock pulses appear on SCK. When the

last bit is latched, the SSPIF interrupt flag bit is set.

Note 1: When the SPI is in Slave mode with SS

pin control enabled (SSPCON<3:0> =

0100), the SPI module will reset if the SS

pin is set to VDD.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

2: If the SPI is used in Slave mode with CKE

set, then the SS pin control must be

enabled.

While in SLEEP mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from sleep.

When the SPI module resets, the bit counter is forced

to 0. This can be done by either forcing the SS pin to a

high level or clearing the SSPEN bit.

15.3.7

SLAVE SELECT

SYNCHRONIZATION

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver the SDO pin can be configured as

an input. This disables transmissions from the SDO.

The SDI can always be left as an input (SDI function),

since it cannot create a bus conflict.

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SS pin control enabled

(SSPCON1<3:0> = 04h). The pin must not be driven

low for the SS pin to function as an input. The Data

Latch must be high. When the SS pin is low, transmis-

sion and reception are enabled and the SDO pin is

driven. When the SS pin goes high, the SDO pin is no

FIGURE 15-4:

SLAVE SYNCHRONIZATION WAVEFORM

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit6

bit7

bit0

SDO

bit7

SDI

(SMP = 0)

bit0

bit7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 cycle

SSPSR to

SSPBUF

after Q2↓

DS39564C-page 131

PIC18FXX2

FIGURE 15-5:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS

Optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit6

bit2

bit5

bit4

bit1

bit0

SDO

bit7

bit3

SDI

(SMP = 0)

bit0

bit7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 cycle

after Q2↓

SSPSR to

SSPBUF

FIGURE 15-6:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS

Not Optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPBUF

bit6

bit2

bit5

bit4

bit1

bit0

SDO

bit7

bit3

SDI

(SMP = 0)

bit0

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 cycle

after Q2↓

SSPSR to

SSPBUF

DS39564C-page 132

PIC18FXX2

15.3.8

SLEEP OPERATION

15.3.10 BUS MODE COMPATIBILITY

In Master mode, all module clocks are halted and the

transmission/reception will remain in that state until the

device wakes from SLEEP. After the device returns to

Normal mode, the module will continue to transmit/

receive data.

Table 15-1 shows the compatibility between the

standard SPI modes and the states the CKP and CKE

control bits.

TABLE 15-1: SPI BUS MODES

In Slave mode, the SPI transmit/receive shift register

operates asynchronously to the device. This allows the

device to be placed in SLEEP mode and data to be

shifted into the SPI transmit/receive shift register.

When all 8 bits have been received, the MSSP interrupt

flag bit will be set and if enabled, will wake the device

from SLEEP.

Control Bits State

Standard SPI Mode

Terminology

CKP

CKE

0, 0

0, 1

1, 0

1, 1

0

1

0

1

0

15.3.9

EFFECTS OF A RESET

There is also a SMP bit which controls when the data is

sampled.

A RESET disables the MSSP module and terminates

the current transfer.

TABLE 15-2: REGISTERS ASSOCIATED WITH SPI OPERATION

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE/GIEH

PEIE/

GIEL

TMR0IE INT0IE

RBIE

TMR0IF

CCP1IF

INT0IF

RBIF

0000 000x 0000 000u

(1)

PIR1

PSPIF

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

SSPIF

SSPIE

SSPIP

TMR2IF TMR1IF 0000 0000 0000 0000

(1)

PIE1

PSPIE

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

1111 1111 1111 1111

(1)

IPR1

PSPIP

TRISC

SSPBUF

SSPCON

TRISA

SSPSTAT

PORTC Data Direction Register

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

WCOL

—

SSPOV SSPEN

PORTA Data Direction Register

CKE D/A

CKP

SSPM3

SSPM2

R/W

SSPM1

UA

SSPM0 0000 0000 0000 0000

-111 1111 -111 1111

SMP

P

S

BF

0000 0000 0000 0000

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices; always maintain these bits clear.

DS39564C-page 133

PIC18FXX2

2

15.4.1

REGISTERS

15.4 I C Mode

The MSSP module has six registers for I²C operation.

These are:

The MSSP module in I²C mode fully implements all

master and slave functions (including general call sup-

port) and provides interrupts on START and STOP bits

in hardware to determine a free bus (multi-master func-

tion). The MSSP module implements the Standard

mode specifications, as well as 7-bit and 10-bit

addressing.

• MSSP Control Register1 (SSPCON1)

• MSSP Control Register2 (SSPCON2)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• MSSP Shift Register (SSPSR) - Not directly

accessible

Two pins are used for data transfer:

• Serial clock (SCL) - RC3/SCK/SCL

• Serial data (SDA) - RC4/SDI/SDA

• MSSP Address Register (SSPADD)

SSPCON, SSPCON2 and SSPSTAT are the control

and status registers in I²C mode operation. The

SSPCON and SSPCON2 registers are readable and

writable. The lower 6 bits of the SSPSTAT are read

only. The upper two bits of the SSPSTAT are read/

write.

The user must configure these pins as inputs or outputs

through the TRISC<4:3> bits.

FIGURE 15-7:

MSSP BLOCK DIAGRAM

(I²C MODE)

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

Internal

Data Bus

Read

Write

SSPADD register holds the slave device address

when the SSP is configured in I²C Slave mode. When

the SSP is configured in Master mode, the lower

seven bits of SSPADD act as the baud rate generator

reload value.

SSPBUF reg

RC3/SCK/SCL

Shift

Clock

In receive operations, SSPSR and SSPBUF together,

create a double buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

SSPSR reg

RC4/

SDI/

SDA

MSb

LSb

Addr Match

Match Detect

During transmission, the SSPBUF is not double buff-

ered. A write to SSPBUF will write to both SSPBUF and

SSPSR.

SSPADD reg

START and

Set, Reset

S, P bits

(SSPSTAT reg)

STOP bit Detect

DS39564C-page 134

PIC18FXX2

REGISTER 15-3: SSPSTAT: MSSP STATUS REGISTER (I²C MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

bit 7

bit 6

bit 5

SMP: Slew Rate Control bit

In Master or Slave mode:

1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for High Speed mode (400 kHz)

CKE: SMBus Select bit

In Master or Slave mode:

1= Enable SMBus specific inputs

0= Disable SMBus specific inputs

D/A: Data/Address bit

In Master mode:

Reserved

In Slave mode:

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

bit 4

bit 3

bit 2

P: STOP bit

1= Indicates that a STOP bit has been detected last

0= STOP bit was not detected last

Note:

This bit is cleared on RESET and when SSPEN is cleared.

S: START bit

1= Indicates that a start bit has been detected last

0= START bit was not detected last

Note:

This bit is cleared on RESET and when SSPEN is cleared.

R/W: Read/Write bit Information (I²C mode only)

In Slave mode:

1= Read

0= Write

Note: This bit holds the R/W bit information following the last address match. This bit is only

valid from the address match to the next START bit, STOP bit, or not ACK bit.

In Master mode:

1= Transmit is in progress

0= Transmit is not in progress

Note:

ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is

in IDLE mode.

bit 1

bit 0

UA: Update Address (10-bit Slave mode only)

1= Indicates that the user needs to update the address in the SSPADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

In Transmit mode:

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

In Receive mode:

1= Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full

0= Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 135

PIC18FXX2

REGISTER 15-4: SSPCON1: MSSP CONTROL REGISTER1 (I²C MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

WCOL: Write Collision Detect bit

In Master Transmit mode:

1= A write to the SSPBUF register was attempted while the I²C conditions were not valid for

a transmission to be started (must be cleared in software)

0= No collision

In Slave Transmit mode:

1= The SSPBUF register is written while it is still transmitting the previous word (must be

cleared in software)

0= No collision

In Receive mode (Master or Slave modes):

This is a “don’t care” bit

bit 6

SSPOV: Receive Overflow Indicator bit

In Receive mode:

1= A byte is received while the SSPBUF register is still holding the previous byte (must

be cleared in software)

0= No overflow

In Transmit mode:

This is a “don’t care” bit in Transmit mode

bit 5

bit 4

SSPEN: Synchronous Serial Port Enable bit

1= Enables the serial port and configures the SDA and SCL pins as the serial port pins

0= Disables serial port and configures these pins as I/O port pins

Note: When enabled, the SDA and SCL pins must be properly configured as input or output.

CKP: SCK Release Control bit

In Slave mode:

1= Release clock

0= Holds clock low (clock stretch), used to ensure data setup time

In Master mode:

Unused in this mode

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

1111= I²C Slave mode, 10-bit address with START and STOP bit interrupts enabled

1110= I²C Slave mode, 7-bit address with START and STOP bit interrupts enabled

1011= I²C Firmware Controlled Master mode (Slave IDLE)

1000= I²C Master mode, clock = FOSC / (4 * (SSPADD+1))

0111= I²C Slave mode, 10-bit address

0110= I²C Slave mode, 7-bit address

Note: Bit combinations not specifically listed here are either reserved, or implemented in

SPI mode only.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 136

PIC18FXX2

REGISTER 15-5: SSPCON2: MSSP CONTROL REGISTER 2 (I²C MODE)

R/W-0

GCEN

R/W-0

RCEN

R/W-0

PEN

R/W-0

RSEN

R/W-0

SEN

ACKSTAT

ACKDT

ACKEN

bit 7

bit 0

bit 7

bit 6

bit 5

GCEN: General Call Enable bit (Slave mode only)

1= Enable interrupt when a general call address (0000h) is received in the SSPSR

0= General call address disabled

ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

1= Acknowledge was not received from slave

0= Acknowledge was received from slave

ACKDT: Acknowledge Data bit (Master Receive mode only)

1= Not Acknowledge

0= Acknowledge

Note: Value that will be transmitted when the user initiates an Acknowledge sequence at

the end of a receive.

bit 4

ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)

1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0= Acknowledge sequence IDLE

bit 3

bit 2

RCEN: Receive Enable bit (Master mode only)

1= Enables Receive mode for I²C

0= Receive IDLE

PEN: STOP Condition Enable bit (Master mode only)

1= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.

0= STOP condition IDLE

bit 1

bit 0

RSEN: Repeated START Condition Enabled bit (Master mode only)

1= Initiate Repeated START condition on SDA and SCL pins.

Automatically cleared by hardware.

0= Repeated START condition IDLE

SEN: START Condition Enabled/Stretch Enabled bit

In Master mode:

1= Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.

0= START condition IDLE

In Slave mode:

1= Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled)

0= Clock stretching is enabled for slave transmit only (Legacy mode)

Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I²C module is not in the IDLE

mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or

writes to the SSPBUF are disabled).

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 137

PIC18FXX2

15.4.2

OPERATION

15.4.3.1

Addressing

Once the MSSP module has been enabled, it waits for

a START condition to occur. Following the START con-

dition, the 8-bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

The MSSP module functions are enabled by setting

MSSP Enable bit, SSPEN (SSPCON<5>).

The SSPCON1 register allows control of the I²C oper-

ation. Four mode selection bits (SSPCON<3:0>) allow

one of the following I²C modes to be selected:

• I²C Master mode, clock = OSC/4 (SSPADD +1)

• I²C Slave mode (7-bit address)

• I²C Slave mode (10-bit address)

• I²C Slave mode (7-bit address), with START and

STOP bit interrupts enabled

1. The SSPSR register value is loaded into the

SSPBUF register.

• I²C Slave mode (10-bit address), with START and

STOP bit interrupts enabled

• I²C Firmware controlled master operation, slave

is IDLE

Selection of any I²C mode, with the SSPEN bit set,

forces the SCL and SDA pins to be open drain, pro-

vided these pins are programmed to inputs by setting

the appropriate TRISC bits. To guarantee proper oper-

ation of the module, pull-up resistors must be provided

externally to the SCL and SDA pins.

2. The buffer full bit BF is set.

3. An ACK pulse is generated.

4. MSSP interrupt flag bit, SSPIF (PIR1<3>) is set

(interrupt is generated if enabled) on the falling

edge of the ninth SCL pulse.

In 10-bit Address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit R/W (SSPSTAT<2>) must specify a write

so the slave device will receive the second address

byte. For a 10-bit address, the first byte would equal

‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two

MSbs of the address. The sequence of events for 10-bit

address is as follows, with steps 7 through 9 for the

slave-transmitter:

15.4.3

SLAVE MODE

In Slave mode, the SCL and SDA pins must be config-

ured as inputs (TRISC<4:3> set). The MSSP module

will override the input state with the output data when

required (slave-transmitter).

The I²C Slave mode hardware will always generate an

interrupt on an address match. Through the mode

select bits, the user can also choose to interrupt on

START and STOP bits

1. Receive first (high) byte of Address (bits SSPIF,

BF and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)

byte of Address (clears bit UA and releases the

SCL line).

3. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

When an address is matched or the data transfer after

an address match is received, the hardware automati-

cally will generate the Acknowledge (ACK) pulse and

load the SSPBUF register with the received value

currently in the SSPSR register.

4. Receive second (low) byte of Address (bits

SSPIF, BF, and UA are set).

5. Update the SSPADD register with the first (high)

byte of Address. If match releases SCL line, this

will clear bit UA.

Any combination of the following conditions will cause

the MSSP module not to give this ACK pulse:

6. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

• The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

7. Receive Repeated START condition.

• The overflow bit SSPOV (SSPCON<6>) was set

before the transfer was received.

8. Receive first (high) byte of Address (bits SSPIF

and BF are set).

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The

BF bit is cleared by reading the SSPBUF register, while

bit SSPOV is cleared through software.

9. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

I²C specification, as well as the requirement of the

MSSP module, are shown in timing parameter 100 and

parameter 101.

DS39564C-page 138

PIC18FXX2

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. If the SDA

line is high (not ACK), then the data transfer is com-

plete. In this case, when the ACK is latched by the

slave, the slave logic is reset (resets SSPSTAT regis-

ter) and the slave monitors for another occurrence of

the START bit. If the SDA line was low (ACK), the next

transmit data must be loaded into the SSPBUF register.

Again, pin RC3/SCK/SCL must be enabled by setting

bit CKP.

15.4.3.2

Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

register is cleared. The received address is loaded into

the SSPBUF register and the SDA line is held low

(ACK).

When the address byte overflow condition exists, then

the no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF (SSPSTAT<0>) is

set, or bit SSPOV (SSPCON1<6>) is set.

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

An MSSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-

ware. The SSPSTAT register is used to determine the

status of the byte.

If SEN is enabled (SSPCON1<0>=1), RC3/SCK/SCL

will be held low (clock stretch) following each data trans-

fer. The clock must be released by setting bit CKP

(SSPCON<4>). See Section 15.4.4 (“Clock Stretching”),

for more detail.

15.4.3.3

Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin RC3/SCK/SCL is held

low, regardless of SEN (see “Clock Stretching”,

Section 15.4.4, for more detail). By stretching the clock,

the master will be unable to assert another clock pulse

until the slave is done preparing the transmit data.The

transmit data must be loaded into the SSPBUF register,

which also loads the SSPSR register. Then pin RC3/

SCK/SCL should be enabled by setting bit CKP

(SSPCON1<4>). The eight data bits are shifted out on

the falling edge of the SCL input. This ensures that the

SDA signal is valid during the SCL high time

(Figure 15-9).

DS39564C-page 139

PIC18FXX2

2

FIGURE 15-8:

I C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)

DS39564C-page 140

PIC18FXX2

2

FIGURE 15-9:

I C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)

DS39564C-page 141

PIC18FXX2

FIGURE 15-10:

I²C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)

DS39564C-page 142

PIC18FXX2

2

FIGURE 15-11:

I C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

DS39564C-page 143

PIC18FXX2

15.4.4

CLOCK STRETCHING

15.4.4.3

Clock Stretching for 7-bit Slave

Transmit Mode

Both 7- and 10-bit Slave modes implement automatic

clock stretching during a transmit sequence.

7-bit Slave Transmit mode implements clock stretching

by clearing the CKP bit after the falling edge of the

ninth clock, if the BF bit is clear. This occurs,

regardless of the state of the SEN bit.

The SEN bit (SSPCON2<0>) allows clock stretching to

be enabled during receives. Setting SEN will cause

the SCL pin to be held low at the end of each data

receive sequence.

The user’s ISR must set the CKP bit before transmis-

sion is allowed to continue. By holding the SCL line

low, the user has time to service the ISR and load the

contents of the SSPBUF before the master device can

initiate another transmit sequence (see Figure 15-9).

15.4.4.1

Clock Stretching for 7-bit Slave

Receive Mode (SEN = 1)

In 7-bit Slave Receive mode, on the falling edge of the

ninth clock at the end of the ACK sequence, if the BF

bit is set, the CKP bit in the SSPCON1 register is auto-

matically cleared, forcing the SCL output to be held

low. The CKP being cleared to ‘0’ will assert the SCL

line low. The CKP bit must be set in the user’s ISR

before reception is allowed to continue. By holding the

SCL line low, the user has time to service the ISR and

read the contents of the SSPBUF before the master

device can initiate another receive sequence. This will

prevent buffer overruns from occurring (see

Figure 15-13).

Note 1: If the user loads the contents of SSPBUF,

setting the BF bit before the falling edge of

the ninth clock, the CKP bit will not be

cleared and clock stretching will not occur.

2: The CKP bit can be set in software,

regardless of the state of the BF bit.

15.4.4.4

Clock Stretching for 10-bit Slave

Transmit Mode

In 10-bit Slave Transmit mode, clock stretching is con-

trolled during the first two address sequences by the

state of the UA bit, just as it is in 10-bit Slave Receive

mode. The first two addresses are followed by a third

address sequence, which contains the high order bits

of the 10-bit address and the R/W bit set to ‘1’. After

the third address sequence is performed, the UA bit is

not set, the module is now configured in Transmit

mode, and clock stretching is controlled by the BF flag,

as in 7-bit Slave Transmit mode (see Figure 15-11).

Note 1: If the user reads the contents of the

SSPBUF before the falling edge of the

ninth clock, thus clearing the BF bit, the

CKP bit will not be cleared and clock

stretching will not occur.

2: The CKP bit can be set in software,

regardless of the state of the BF bit. The

user should be careful to clear the BF bit

in the ISR before the next receive

sequence, in order to prevent an overflow

condition.

15.4.4.2

Clock Stretching for 10-bit Slave

Receive Mode (SEN = 1)

In 10-bit Slave Receive mode, during the address

sequence, clock stretching automatically takes place

but CKP is not cleared. During this time, if the UA bit is

set after the ninth clock, clock stretching is initiated.

The UA bit is set after receiving the upper byte of the

10-bit address, and following the receive of the second

byte of the 10-bit address with the R/W bit cleared to

‘0’. The release of the clock line occurs upon updating

SSPADD. Clock stretching will occur on each data

receive sequence as described in 7-bit mode.

Note: If the user polls the UA bit and clears it by

updating the SSPADD register before the

falling edge of the ninth clock occurs, and if

the user hasn’t cleared the BF bit by read-

ing the SSPBUF register before that time,

then the CKP bit will still NOT be asserted

low. Clock stretching on the basis of the

state of the BF bit only occurs during a data

sequence, not an address sequence.

DS39564C-page 144

PIC18FXX2

15.4.4.5

Clock Synchronization and

the CKP bit

If a user clears the CKP bit, the SCL output is forced to

‘0’. Setting the CKP bit will not assert the SCL output

low until the SCL output is already sampled low. If the

user attempts to drive SCL low, the CKP bit will not

assert the SCL line until an external I²C master device

has already asserted the SCL line. The SCL output will

remain low until the CKP bit is set, and all other

devices on the I²C bus have de-asserted SCL. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCL (see

Figure 15-12).

FIGURE 15-12:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX-1

Master device

asserts clock

CKP

Master device

de-asserts clock

WR

SSPCON

DS39564C-page 145

PIC18FXX2

2

FIGURE 15-13:

I C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)

DS39564C-page 146

PIC18FXX2

FIGURE 15-14:

I²C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)

DS39564C-page 147

PIC18FXX2

If the general call address matches, the SSPSR is

transferred to the SSPBUF, the BF flag bit is set (eighth

bit), and on the falling edge of the ninth bit (ACK bit),

the SSPIF interrupt flag bit is set.

15.4.5

GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I²C bus is such that

the first byte after the START condition usually deter-

mines which device will be the slave addressed by the

master. The exception is the general call address,

which can address all devices. When this address is

used, all devices should, in theory, respond with an

Acknowledge.

When the interrupt is serviced, the source for the inter-

rupt can be checked by reading the contents of the

SSPBUF. The value can be used to determine if the

address was device specific or a general call address.

In 10-bit mode, the SSPADD is required to be updated

for the second half of the address to match, and the UA

bit is set (SSPSTAT<1>). If the general call address is

sampled when the GCEN bit is set, while the slave is

configured in 10-bit Address mode, then the second

half of the address is not necessary, the UA bit will not

be set, and the slave will begin receiving data after the

Acknowledge (Figure 15-15).

The general call address is one of eight addresses

reserved for specific purposes by the I²C protocol. It

consists of all 0’s with R/W = 0.

The general call address is recognized when the Gen-

eral Call Enable bit (GCEN) is enabled (SSPCON2<7>

set). Following a START bit detect, 8-bits are shifted

into the SSPSR and the address is compared against

the SSPADD. It is also compared to the general call

address and fixed in hardware.

FIGURE 15-15:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

(7 OR 10-BIT ADDRESS MODE)

Address is compared to General Call Address

after ACK, set interrupt

Receiving data

D5 D4 D3 D2 D1

ACK

9

R/W = 0

General Call Address

ACK

SDA

SCL

D7 D6

D0

8

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

S

SSPIF

BF (SSPSTAT<0>)

Cleared in software

SSPBUF is read

SSPOV (SSPCON1<6>)

GCEN (SSPCON2<7>)

'0'

'1'

DS39564C-page 148

PIC18FXX2

Note: The MSSP Module, when configured in I²C

Master mode, does not allow queueing of

events. For instance, the user is not

allowed to initiate a START condition and

immediately write the SSPBUF register to

initiate transmission before the START

condition is complete. In this case, the

SSPBUF will not be written to and the

WCOL bit will be set, indicating that a write

to the SSPBUF did not occur.

15.4.6

MASTER MODE

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON1 and by setting the

SSPEN bit. In Master mode, the SCL and SDA lines

are manipulated by the MSSP hardware.

Master mode of operation is supported by interrupt

generation on the detection of the START and STOP

conditions. The STOP (P) and START (S) bits are

cleared from a RESET or when the MSSP module is

disabled. Control of the I²C bus may be taken when the

P bit is set or the bus is IDLE, with both the S and P bits

clear.

The following events will cause SSP interrupt flag bit,

SSPIF, to be set (SSP interrupt if enabled):

In Firmware Controlled Master mode, user code con-

ducts all I²C bus operations based on START and

STOP bit conditions.

• START condition

• STOP condition

• Data transfer byte transmitted/received

• Acknowledge Transmit

• Repeated START

Once Master mode is enabled, the user has six

options.

1. Assert a START condition on SDA and SCL.

2. Assert a Repeated START condition on SDA

and SCL.

3. Write to the SSPBUF register initiating

transmission of data/address.

4. Configure the I²C port to receive data.

5. Generate an Acknowledge condition at the end

of a received byte of data.

6. Generate a STOP condition on SDA and SCL.

2

FIGURE 15-16:

MSSP BLOCK DIAGRAM (I C MASTER MODE)

Internal

Data Bus

SSPM3:SSPM0

SSPADD<6:0>

Read

Write

SSPBUF

SSPSR

Baud

Rate

Generator

SDA

Shift

Clock

SDA in

MSb

LSb

START bit, STOP bit,

Acknowledge

Generate

SCL

START bit Detect

STOP bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

end of XMIT/RCV

SCL in

Bus Collision

Set/Reset, S, P, WCOL (SSPSTAT)

Set SSPIF, BCLIF

Reset ACKSTAT, PEN (SSPCON2)

DS39564C-page 149

PIC18FXX2

I²C Master Mode Operation

A typical transmit sequence would go as follows:

1. The user generates a START condition by set-

15.4.6.1

The master device generates all of the serial clock

pulses and the START and STOP conditions. A trans-

fer is ended with a STOP condition or with a Repeated

START condition. Since the Repeated START condi-

tion is also the beginning of the next serial transfer, the

I²C bus will not be released.

ting

the

START

enable

bit,

SEN

(SSPCON2<0>).

2. SSPIF is set. The MSSP module will wait the

required start time before any other operation

takes place.

3. The user loads the SSPBUF with the slave

address to transmit.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic '0'. Serial data is

transmitted 8 bits at a time. After each byte is transmit-

ted, an Acknowledge bit is received. START and STOP

conditions are output to indicate the beginning and the

end of a serial transfer.

4. Address is shifted out the SDA pin until all 8 bits

are transmitted.

5. The MSSP Module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

6. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

In Master Receive mode, the first byte transmitted con-

tains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic '1'. Thus, the first byte transmitted is a 7-bit slave

address followed by a '1' to indicate receive bit. Serial

data is received via SDA, while SCL outputs the serial

clock. Serial data is received 8 bits at a time. After each

byte is received, an Acknowledge bit is transmitted.

START and STOP conditions indicate the beginning

and end of transmission.

7. The user loads the SSPBUF with eight bits of

data.

8. Data is shifted out the SDA pin until all 8 bits are

transmitted.

9. The MSSP Module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

10. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

The baud rate generator used for the SPI mode opera-

tion is used to set the SCL clock frequency for either

100 kHz, 400 kHz or 1 MHz I²C operation. See

Section 15.4.7 (“Baud Rate Generator”), for more

detail.

11. The user generates a STOP condition by setting

the STOP enable bit PEN (SSPCON2<2>).

12. Interrupt is generated once the STOP condition

is complete.

DS39564C-page 150

PIC18FXX2

Once the given operation is complete (i.e., transmis-

sion of the last data bit is followed by ACK), the internal

clock will automatically stop counting and the SCL pin

will remain in its last state.

15.4.7

BAUD RATE GENERATOR

In I²C Master mode, the baud rate generator (BRG)

reload value is placed in the lower 7 bits of the

SSPADD register (Figure 15-17). When a write occurs

to SSPBUF, the baud rate generator will automatically

begin counting. The BRG counts down to 0 and stops

until another reload has taken place. The BRG count is

decremented twice per instruction cycle (TCY) on the

Q2 and Q4 clocks. In I²C Master mode, the BRG is

reloaded automatically.

Table 15-3 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

FIGURE 15-17:

BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM3:SSPM0

SSPADD<6:0>

SSPM3:SSPM0

SCL

Reload

Control

Reload

BRG Down Counter

CLKO

Fosc/4

TABLE 15-3: I²C CLOCK RATE W/BRG

(2)

FSCL

(2 Rollovers of BRG)

FCY

FCY*2

BRG Value

10 MHz

4 MHz

1 MHz

20 MHz

8 MHz

2 MHz

19h

20h

3Fh

0Ah

0Dh

28h

03h

0Ah

00h

400 kHz⁽¹⁾

312.5 kHz

100 kHz

400 kHz⁽¹⁾

308 kHz

100 kHz

333 kHz⁽¹⁾

100kHz

1 MHz⁽¹⁾

Note 1: The I²C interface does not conform to the 400 kHz I²C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

2: Actual frequency will depend on bus conditions. Theoretically, bus conditions will add rise time and extend

low time of clock period, producing the effective frequency.

DS39564C-page 151

PIC18FXX2

sampled high, the baud rate generator is reloaded with

the contents of SSPADD<6:0> and begins counting.

This ensures that the SCL high time will always be at

least one BRG rollover count, in the event that the clock

is held low by an external device (Figure 15-18).

15.4.7.1

Clock Arbitration

Clock arbitration occurs when the master, during any

receive, transmit or Repeated START/STOP condition,

de-asserts the SCL pin (SCL allowed to float high).

When the SCL pin is allowed to float high, the baud rate

generator (BRG) is suspended from counting until the

SCL pin is actually sampled high. When the SCL pin is

FIGURE 15-18:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

DX

DX-1

SCL allowed to transition high

SCL de-asserted but slave holds

SCL low (clock arbitration)

SCL

BRG decrements on

Q2 and Q4 cycles

BRG

Value

03h

02h

01h

00h (hold off)

03h

02h

SCL is sampled high, reload takes

place and BRG starts its count.

BRG

Reload

DS39564C-page 152

PIC18FXX2

15.4.8

I²C MASTER MODE START

CONDITION TIMING

15.4.8.1

WCOL Status Flag

If the user writes the SSPBUF when a START

sequence is in progress, the WCOL is set and the con-

tents of the buffer are unchanged (the write doesn’t

occur).

To initiate a START condition, the user sets the START

condition enable bit, SEN (SSPCON2<0>). If the SDA

and SCL pins are sampled high, the baud rate genera-

tor is reloaded with the contents of SSPADD<6:0> and

starts its count. If SCL and SDA are both sampled high

when the baud rate generator times out (TBRG), the

SDA pin is driven low. The action of the SDA being

driven low, while SCL is high, is the START condition

and causes the S bit (SSPSTAT<3>) to be set. Follow-

ing this, the baud rate generator is reloaded with the

contents of SSPADD<6:0> and resumes its count.

When the baud rate generator times out (TBRG), the

SEN bit (SSPCON2<0>) will be automatically cleared

by hardware, the baud rate generator is suspended,

leaving the SDA line held low and the START condition

is complete.

Note: Because queueing of events is not

allowed, writing to the lower 5 bits of

SSPCON2 is disabled until the START

condition is complete.

Note: If at the beginning of the START condition,

the SDA and SCL pins are already sam-

pled low, or if during the START condition

the SCL line is sampled low before the

SDA line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCLIF is set, the START condition is

aborted, and the I²C module is reset into its

IDLE state.

FIGURE 15-19:

FIRST START BIT TIMING

Set S bit (SSPSTAT<3>)

Write to SEN bit occurs here

SDA = 1,

At completion of START bit,

Hardware clears SEN bit

and sets SSPIF bit

SCL = 1

TBRG

Write to SSPBUF occurs here

2nd bit

1st bit

SDA

TBRG

SCL

TBRG

S

DS39564C-page 153

PIC18FXX2

I²C MASTER MODE REPEATED

START CONDITION TIMING

Immediately following the SSPIF bit getting set, the

user may write the SSPBUF with the 7-bit address in

7-bit mode, or the default first address in 10-bit mode.

After the first eight bits are transmitted and an ACK is

received, the user may then transmit an additional eight

bits of address (10-bit mode) or eight bits of data (7-bit

mode).

15.4.9

A Repeated START condition occurs when the RSEN

bit (SSPCON2<1>) is programmed high and the I²C

logic module is in the IDLE state. When the RSEN bit is

set, the SCL pin is asserted low. When the SCL pin is

sampled low, the baud rate generator is loaded with the

contents of SSPADD<5:0> and begins counting. The

SDA pin is released (brought high) for one baud rate

generator count (TBRG). When the baud rate generator

times out, if SDA is sampled high, the SCL pin will be

de-asserted (brought high). When SCL is sampled

high, the baud rate generator is reloaded with the con-

tents of SSPADD<6:0> and begins counting. SDA and

SCL must be sampled high for one TBRG. This action is

then followed by assertion of the SDA pin (SDA = 0) for

15.4.9.1

WCOL Status Flag

If the user writes the SSPBUF when a Repeated

START sequence is in progress, the WCOL is set and

the contents of the buffer are unchanged (the write

doesn’t occur).

Note: Because queueing of events is not

allowed, writing of the lower 5 bits of

SSPCON2 is disabled until the Repeated

START condition is complete.

one TBRG while SCL is high. Following this, the RSEN

,

bit (SSPCON2<1>) will be automatically cleared and

the baud rate generator will not be reloaded, leaving

the SDA pin held low. As soon as a START condition is

detected on the SDA and SCL pins, the S bit

(SSPSTAT<3>) will be set. The SSPIF bit will not be set

until the baud rate generator has timed out.

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated

START condition occurs if:

• SDA is sampled low when SCL goes

from low to high.

• SCL goes low before SDA is

asserted low. This may indicate that

another master is attempting to

transmit a data "1".

FIGURE 15-20:

REPEAT START CONDITION WAVEFORM

Set S (SSPSTAT<3>)

Write to SSPCON2

occurs here.

SDA = 1,

SCL = 1

At completion of START bit,

hardware clear RSEN bit

and set SSPIF

SCL (no change)

TBRG

1st bit

SDA

Write to SSPBUF occurs here

TBRG

Falling edge of ninth clock

End of Xmit

SCL

TBRG

Sr = Repeated START

DS39564C-page 154

PIC18FXX2

15.4.10 I²C MASTER MODE

TRANSMISSION

15.4.10.3 ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is

cleared when the slave has sent an Acknowledge (ACK

= 0), and is set when the slave does not Acknowledge

(ACK = 1). A slave sends an Acknowledge when it has

recognized its address (including a general call) or

when the slave has properly received its data.

Transmission of a data byte, a 7-bit address, or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPBUF register. This action will

set the buffer full flag bit, BF, and allow the baud rate

generator to begin counting and start the next transmis-

sion. Each bit of address/data will be shifted out onto

the SDA pin after the falling edge of SCL is asserted

(see data hold time specification parameter 106). SCL

is held low for one baud rate generator rollover count

(TBRG). Data should be valid before SCL is released

high (see data setup time specification parameter 107).

When the SCL pin is released high, it is held that way

for TBRG. The data on the SDA pin must remain stable

for that duration and some hold time after the next fall-

ing edge of SCL. After the eighth bit is shifted out (the

falling edge of the eighth clock), the BF flag is cleared

and the master releases SDA. This allows the slave

device being addressed to respond with an ACK bit

during the ninth bit time if an address match occurred

or if data was received properly. The status of ACK is

written into the ACKDT bit on the falling edge of the

ninth clock. If the master receives an Acknowledge, the

Acknowledge status bit, ACKSTAT, is cleared. If not,

the bit is set. After the ninth clock, the SSPIF bit is set

and the master clock (baud rate generator) is sus-

pended until the next data byte is loaded into the

SSPBUF, leaving SCL low and SDA unchanged

(Figure 15-21).

15.4.11 I²C MASTER MODE RECEPTION

Master mode reception is enabled by programming the

receive enable bit, RCEN (SSPCON2<3>).

Note: In the MSSP module, the RCEN bit must

be set after the ACK sequence or the

RCEN bit will be disregarded.

The baud rate generator begins counting, and on each

rollover, the state of the SCL pin changes (high to low/

low to high) and data is shifted into the SSPSR. After

the falling edge of the eighth clock, the receive enable

flag is automatically cleared, the contents of the

SSPSR are loaded into the SSPBUF, the BF flag bit is

set, the SSPIF flag bit is set and the baud rate genera-

tor is suspended from counting, holding SCL low. The

MSSP is now in IDLE state, awaiting the next com-

mand. When the buffer is read by the CPU, the BF flag

bit is automatically cleared. The user can then send an

Acknowledge bit at the end of reception, by setting the

Acknowledge sequence enable bit, ACKEN

(SSPCON2<4>).

15.4.11.1 BF Status Flag

After the write to the SSPBUF, each bit of address will

be shifted out on the falling edge of SCL until all seven

address bits and the R/W bit are completed. On the fall-

ing edge of the eighth clock, the master will de-assert

the SDA pin, allowing the slave to respond with an

Acknowledge. On the falling edge of the ninth clock, the

master will sample the SDA pin to see if the address

was recognized by a slave. The status of the ACK bit is

loaded into the ACKSTAT status bit (SSPCON2<6>).

Following the falling edge of the ninth clock transmis-

sion of the address, the SSPIF is set, the BF flag is

cleared and the baud rate generator is turned off until

another write to the SSPBUF takes place, holding SCL

low and allowing SDA to float.

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

15.4.11.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bits

are received into the SSPSR and the BF flag bit is

already set from a previous reception.

15.4.11.3 WCOL Status Flag

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), the WCOL bit is set and the contents of the buffer

are unchanged (the write doesn’t occur).

15.4.10.1 BF Status Flag

In Transmit mode, the BF bit (SSPSTAT<0>) is set

when the CPU writes to SSPBUF and is cleared when

all 8 bits are shifted out.

15.4.10.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

WCOL must be cleared in software.

DS39564C-page 155

PIC18FXX2

2

FIGURE 15-21:

I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

DS39564C-page 156

PIC18FXX2

2

FIGURE 15-22:

I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

DS39564C-page 157

PIC18FXX2

15.4.12 ACKNOWLEDGE SEQUENCE

TIMING

15.4.13 STOP CONDITION TIMING

A STOP bit is asserted on the SDA pin at the end of a

receive/transmit by setting the STOP sequence enable

bit, PEN (SSPCON2<2>). At the end of a receive/trans-

mit the SCL line is held low after the falling edge of the

ninth clock. When the PEN bit is set, the master will

assert the SDA line low. When the SDA line is sampled

low, the baud rate generator is reloaded and counts

down to 0. When the baud rate generator times out, the

SCL pin will be brought high, and one TBRG (baud rate

generator rollover count) later, the SDA pin will be

de-asserted. When the SDA pin is sampled high while

SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG

later, the PEN bit is cleared and the SSPIF bit is set

(Figure 15-24).

An Acknowledge sequence is enabled by setting the

Acknowledge

sequence

enable

bit,

ACKEN

(SSPCON2<4>). When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to gen-

erate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The baud rate gen-

erator then counts for one rollover period (TBRG) and the

SCL pin is de-asserted (pulled high). When the SCL pin

is sampled high (clock arbitration), the baud rate gener-

ator counts for TBRG. The SCL pin is then pulled low. Fol-

lowing this, the ACKEN bit is automatically cleared, the

baud rate generator is turned off and the MSSP module

then goes into IDLE mode (Figure 15-23).

15.4.13.1 WCOL Status Flag

If the user writes the SSPBUF when a STOP sequence

is in progress, then the WCOL bit is set and the con-

tents of the buffer are unchanged (the write doesn’t

occur).

15.4.12.1 WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the con-

tents of the buffer are unchanged (the write doesn’t occur).

FIGURE 15-23:

ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,

Write to SSPCON2

ACKEN automatically cleared

ACKEN = 1, ACKDT = 0

TBRG

ACK

TBRG

SDA

SCL

D0

8

9

SSPIF

Cleared in

Set SSPIF at the end

of receive

Cleared in

software

Set SSPIF at the end

of Acknowledge sequence

Note: TBRG = one baud rate generator period.

FIGURE 15-24:

STOP CONDITION RECEIVE OR TRANSMIT MODE

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

Write to SSPCON2

Set PEN

after SDA sampled high. P bit (SSPSTAT<4>) is set.

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

Falling edge of

9th clock

TBRG

SCL

SDA

ACK

P

TBRG

SCL brought high after TBRG

SDA asserted low before rising edge of clock

to setup STOP condition.

Note: TBRG = one baud rate generator period.

DS39564C-page 158

PIC18FXX2

15.4.14 SLEEP OPERATION

15.4.17 MULTI -MASTER COMMUNICATION,

BUS COLLISION, AND BUS

ARBITRATION

While in SLEEP mode, the I²C module can receive

addresses or data, and when an address match or

complete byte transfer occurs, wake the processor

from SLEEP (if the MSSP interrupt is enabled).

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a '1' on SDA, by letting SDA float high and

another master asserts a '0'. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a '1' and the data sampled on the SDA pin = '0',

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag BCLIF and reset the I²C

port to its IDLE state (Figure 15-25).

15.4.15 EFFECT OF A RESET

A RESET disables the MSSP module and terminates

the current transfer.

15.4.16 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the START and STOP conditions allows the

determination of when the bus is free. The STOP (P)

and START (S) bits are cleared from a RESET or when

the MSSP module is disabled. Control of the I²C bus

may be taken when the P bit (SSPSTAT<4>) is set, or

the bus is idle with both the S and P bits clear. When the

bus is busy, enabling the SSP interrupt will generate the

interrupt when the STOP condition occurs.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are de-asserted, and

the SSPBUF can be written to. When the user services

the bus collision Interrupt Service Routine, and if the

I²C bus is free, the user can resume communication by

asserting a START condition.

If a START, Repeated START, STOP, or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL

lines are de-asserted, and the respective control bits in

the SSPCON2 register are cleared. When the user ser-

vices the bus collision Interrupt Service Routine, and if

the I²C bus is free, the user can resume communication

by asserting a START condition.

In multi-master operation, the SDA line must be moni-

tored for arbitration, to see if the signal level is the

expected output level. This check is performed in

hardware, with the result placed in the BCLIF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

The master will continue to monitor the SDA and SCL

pins. If a STOP condition occurs, the SSPIF bit will be set.

• A START Condition

• A Repeated START Condition

• An Acknowledge Condition

A write to the SSPBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of START and STOP conditions allows the

determination of when the bus is free. Control of the I²C

bus can be taken when the P bit is set in the SSPSTAT

register, or the bus is IDLE and the S and P bits are

cleared.

FIGURE 15-25:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,

data doesn’t match what is driven

by the master.

SDA line pulled low

by another source

Data changes

while SCL = 0

Bus collision has occurred.

SDA released

by master

SDA

SCL

Set bus collision

interrupt (BCLIF)

BCLIF

DS39564C-page 159

PIC18FXX2

If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 15-28). If, however, a '1' is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The baud rate generator is then reloaded and

counts down to 0, and during this time, if the SCL pins

are sampled as '0', a bus collision does not occur. At

the end of the BRG count, the SCLpin is asserted low.

15.4.17.1 Bus Collision During a START

Condition

During a START condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning of

the START condition (Figure 15-26).

b) SCL is sampled low before SDA is asserted low

(Figure 15-27).

During a START condition, both the SDA and the SCL

pins are monitored.

Note: The reason that bus collision is not a factor

during a START condition is that no two

bus masters can assert a START condition

at the exact same time. Therefore, one

master will always assert SDA before the

other. This condition does not cause a bus

collision, because the two masters must be

allowed to arbitrate the first address follow-

ing the START condition. If the address is

the same, arbitration must be allowed to

continue into the data portion, Repeated

START or STOP conditions.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the START condition is aborted,

• the BCLIF flag is set, and

• the MSSP module is reset to its IDLE state

(Figure 15-26).

The START condition begins with the SDA and SCL

pins de-asserted. When the SDA pin is sampled high,

the baud rate generator is loaded from SSPADD<6:0>

and counts down to 0. If the SCL pin is sampled low

while SDA is high, a bus collision occurs, because it is

assumed that another master is attempting to drive a

data '1' during the START condition.

FIGURE 15-26:

BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.

Set BCLIF,

S bit and SSPIF set because

SDA = 0, SCL = 1.

SDA

SCL

SEN

Set SEN, enable START

condition if SDA = 1, SCL=1

SEN cleared automatically because of bus collision.

SSP module reset into IDLE state.

SDA sampled low before

START condition.

Set BCLIF.

S bit and SSPIF set because

SDA = 0, SCL = 1.

BCLIF

SSPIF and BCLIF are

cleared in software.

S

SSPIF

SSPIF and BCLIF are

cleared in software.

DS39564C-page 160

PIC18FXX2

FIGURE 15-27:

BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1

TBRG

SDA

Set SEN, enable START

sequence if SDA = 1, SCL = 1

SCL

SEN

SCL = 0 before SDA = 0,

bus collision occurs. set BCLIF

SCL = 0 before BRG time-out,

bus collision occurs. Set BCLIF.

BCLIF

Interrupt cleared

in software

S

'0'

SSPIF

FIGURE 15-28:

BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA = 0, SCL = 1

Set S

Set SSPIF

Less than TBRG

TBRG

SDA pulled low by other master.

Reset BRG and assert SDA.

SDA

SCL

S

SCL pulled low after BRG

Time-out

SEN

Set SEN, enable START

sequence if SDA = 1, SCL = 1

'0'

BCLIF

S

SSPIF

Interrupts cleared

in software

SDA = 0, SCL = 1

Set SSPIF

DS39564C-page 161

PIC18FXX2

reloaded and begins counting. If SDA goes from high to

low before the BRG times out, no bus collision occurs

because no two masters can assert SDA at exactly the

same time.

15.4.17.2 Bus Collision During a Repeated

START Condition

During a Repeated START condition, a bus collision

occurs if:

If SCL goes from high to low before the BRG times out

and SDA has not already been asserted, a bus collision

occurs. In this case, another master is attempting to

transmit a data ’1’ during the Repeated START

condition, Figure 15-30.

a) A low level is sampled on SDA when SCL goes

from low level to high level.

b) SCL goes low before SDA is asserted low, indi-

cating that another master is attempting to

transmit a data ’1’.

If, at the end of the BRG time-out both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated START condition is

complete.

When the user de-asserts SDA and the pin is allowed

to float high, the BRG is loaded with SSPADD<6:0>

and counts down to 0. The SCL pin is then de-asserted,

and when sampled high, the SDA pin is sampled.

If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit

a

data ’0’,

Figure 15-29). If SDA is sampled high, the BRG is

FIGURE 15-29:

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.

RSEN

BCLIF

Cleared in software

'0'

S

'0'

SSPIF

FIGURE 15-30:

BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG

SDA

SCL

SCL goes low before SDA,

BCLIF

RSEN

Set BCLIF. Release SDA and SCL.

Interrupt cleared

in software

'0'

S

SSPIF

DS39564C-page 162

PIC18FXX2

The STOP condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

float. When the pin is sampled high (clock arbitration),

the baud rate generator is loaded with SSPADD<6:0>

and counts down to 0. After the BRG times out, SDA is

sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data '0' (Figure 15-31). If the SCL pin is sampled

low before SDA is allowed to float high, a bus collision

occurs. This is another case of another master

attempting to drive a data '0' (Figure 15-32).

15.4.17.3 Bus Collision During a STOP

Condition

Bus collision occurs during a STOP condition if:

a) After the SDA pin has been de-asserted and

allowed to float high, SDA is sampled low after

the BRG has timed out.

b) After the SCL pin is de-asserted, SCL is

sampled low before SDA goes high.

FIGURE 15-31:

BUS COLLISION DURING A STOP CONDITION (CASE 1)

SDA sampled

low after TBRG,

Set BCLIF

TBRG

SDA

SDA asserted low

SCL

PEN

BCLIF

P

'0'

SSPIF

FIGURE 15-32:

BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG

SDA

SCL goes low before SDA goes high

Set BCLIF

Assert SDA

SCL

PEN

BCLIF

P

'0'

SSPIF

DS39564C-page 163

PIC18FXX2

NOTES:

DS39564C-page 164

PIC18FXX2

16.0 ADDRESSABLE UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

The Universal Synchronous Asynchronous Receiver

Transmitter (USART) module is one of the two serial

I/O modules. (USART is also known as a Serial Com-

munications Interface or SCI.) The USART can be con-

figured as a full duplex asynchronous system that can

communicate with peripheral devices, such as CRT ter-

minals and personal computers, or it can be configured

as a half-duplex synchronous system that can commu-

nicate with peripheral devices, such as A/D or D/A

integrated circuits, serial EEPROMs, etc.

The USART can be configured in the following modes:

• Asynchronous (full-duplex)

• Synchronous - Master (half-duplex)

• Synchronous - Slave (half-duplex)

In order to configure pins RC6/TX/CK and RC7/RX/DT

as the Universal Synchronous Asynchronous Receiver

Transmitter:

• bit SPEN (RCSTA<7>) must be set (= 1),

• bit TRISC<6> must be cleared (= 0), and

• bit TRISC<7> must be set (=1).

Register 16-1 shows the Transmit Status and Control

Register (TXSTA) and Register 16-2 shows the

Receive Status and Control Register (RCSTA).

DS39564C-page 165

PIC18FXX2

REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0

CSRC

R/W-0

TX9

R/W-0

TXEN

R/W-0

SYNC

U-0

—

R/W-0

BRGH

R-1

R/W-0

TX9D

TRMT

bit 7

bit 0

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

TXEN: Transmit Enable bit

1= Transmit enabled

0= Transmit disabled

Note:

SREN/CREN overrides TXEN in SYNC mode.

bit 4

SYNC: USART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

bit 3

bit 2

Unimplemented: Read as '0'

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: 9th bit of Transmit Data

Can be Address/Data bit or a parity bit.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 166

PIC18FXX2

REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0

SPEN

R/W-0

RX9

R/W-0

SREN

R/W-0

CREN

R/W-0

R-0

R-x

ADDEN

FERR

OERR

RX9D

bit 7

bit 0

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit

1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0= Serial port disabled

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode - Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode - Slave:

Don’t care

bit 4

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables receiver

0= Disables receiver

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enable interrupt and load of the receive buffer

when RSR<8> is set

0= Disables address detection, all bytes are received, and ninth bit can be used as parity bit

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receive next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: 9th bit of Received Data

This can be Address/Data bit or a parity bit, and must be calculated by user firmware.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 167

PIC18FXX2

Example 16-1 shows the calculation of the baud rate

error for the following conditions:

16.1 USART Baud Rate Generator

(BRG)

• FOSC = 16 MHz

• Desired Baud Rate = 9600

• BRGH = 0

The BRG supports both the Asynchronous and Syn-

chronous modes of the USART. It is a dedicated 8-bit

baud rate generator. The SPBRG register controls the

period of a free running 8-bit timer. In Asynchronous

mode, bit BRGH (TXSTA<2>) also controls the baud

rate. In Synchronous mode, bit BRGH is ignored.

Table 16-1 shows the formula for computation of the

baud rate for different USART modes, which only apply

in Master mode (internal clock).

• SYNC = 0

It may be advantageous to use the high baud rate

(BRGH = 1) even for slower baud clocks. This is

because the FOSC/(16(X + 1)) equation can reduce the

baud rate error in some cases.

Writing a new value to the SPBRG register causes the

BRG timer to be reset (or cleared). This ensures the

BRG does not wait for a timer overflow before

outputting the new baud rate.

Given the desired baud rate and Fosc, the nearest inte-

ger value for the SPBRG register can be calculated

using the formula in Table 16-1. From this, the error in

baud rate can be determined.

16.1.1

SAMPLING

The data on the RC7/RX/DT pin is sampled three times

by a majority detect circuit to determine if a high or a

low level is present at the RX pin.

EXAMPLE 16-1:

Desired Baud Rate

Solving for X:

CALCULATING BAUD RATE ERROR

=

FOSC / (64 (X + 1))

X

=

( (FOSC / Desired Baud Rate) / 64 ) – 1

((16000000 / 9600) / 64) – 1

[25.042] = 25

Calculated Baud Rate

=

16000000 / (64 (25 + 1))

9615

Error

=

(Calculated Baud Rate – Desired Baud Rate)

Desired Baud Rate

=

(9615 – 9600) / 9600

0.16%

TABLE 16-1: BAUD RATE FORMULA

SYNC

BRGH = 0 (Low Speed)

BRGH = 1 (High Speed)

0

1

(Asynchronous) Baud Rate = FOSC/(64(X+1))

(Synchronous) Baud Rate = FOSC/(4(X+1))

Baud Rate = FOSC/(16(X+1))

N/A

Legend: X = value in SPBRG (0 to 255)

TABLE 16-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TXSTA

RCSTA

SPBRG

CSRC

SPEN

TX9

RX9

TXEN SYNC

—

BRGH TRMT TX9D 0000 -010

0000 -010

0000 -00x

0000 0000

SREN CREN ADDEN FERR OERR RX9D 0000 -00x

0000 0000

Baud Rate Generator Register

Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.

DS39564C-page 168

PIC18FXX2

TABLE 16-3: BAUD RATES FOR SYNCHRONOUS MODE

FOSC = 40 MHz

33 MHz

25 MHz

20 MHz

SPBRG

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

value

(decimal)

%

KBAUD ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

NA

-

NA

-

NA

-

NA

-

9.6

NA

-

NA

-

NA

-

NA

-

19.2

76.8

96

NA

-

NA

-

NA

-

NA

-

76.92

96.15

303.03

500

+0.16

129

103

32

19

0

77.10

95.93

294.64

485.30

8250

32.23

+0.39

-0.07

-1.79

-2.94

-

106

85

27

16

0

77.16

96.15

297.62

480.77

6250

24.41

+0.47

+0.16

-0.79

-3.85

-

80

64

20

12

0

76.92

96.15

294.12

500

+0.16

64

51

16

9

+0.16

300

500

HIGH

LOW

+1.01

-1.96

0

-

0

-

10000

39.06

5000

19.53

0

-

255

-

255

-

255

-

255

FOSC = 16 MHz

10 MHz

7.15909 MHz

5.0688 MHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

NA

-

NA

-

NA

-

NA

-

9.6

NA

-

+0.16

-0.79

+2.56

0

-

NA

-

+0.16

-1.36

+0.16

+4.17

0

-

9.62

+0.23

+1.32

-1.88

-0.57

-10.51

-

185

92

22

18

5

9.60

0

131

65

16

12

3

19.2

76.8

96

19.23

76.92

95.24

307.70

500

207

51

41

12

7

19.23

75.76

96.15

312.50

500

129

32

25

7

19.24

77.82

94.20

298.35

447.44

1789.80

6.99

19.20

74.54

97.48

316.80

422.40

1267.20

4.95

-2.94

+1.54

+5.60

-15.52

-

300

500

HIGH

LOW

4

3

2

4000

15.63

-

0

2500

9.77

-

0

-

255

-

255

-

255

-

255

FOSC = 4 MHz

3.579545 MHz

1 MHz

32.768 kHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

1.20

2.40

9.62

19.23

83.33

250

-

207

103

25

12

2

0.30

1.17

2.73

8.20

NA

+1.14

26

-

+0.16

+8.51

-13.19

-16.67

-

-2.48

6

2.4

NA

-

NA

-

+13.78

2

9.6

9.62

19.23

76.92

1000

333.33

500

+0.16

+4.17

+11.11

0

103

51

12

9

9.62

+0.23

-0.83

-2.90

+3.57

-0.57

-10.51

-

92

46

11

8

-14.67

0

19.2

76.8

96

19.04

74.57

99.43

298.30

447.44

894.89

3.50

-

NA

-

2

NA

-

300

500

HIGH

LOW

2

0

NA

-

1

NA

-

NA

1000

3.91

-

0

250

-

0

8.20

0.03

0

-

255

-

255

0.98

-

255

DS39564C-page 169

PIC18FXX2

TABLE 16-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)

FOSC = 40 MHz

33 MHz

25 MHz

20 MHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

KBAUD

ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

NA

-

2.40

-0.07

-0.54

-4.09

+7.42

-14.06

-

214

53

26

6

2.40

9.53

19.53

78.13

97.66

NA

-0.15

162

40

19

4

2.40

+0.16

-1.36

+1.73

+8.51

+4.17

-

129

32

15

3

9.6

9.62

18.94

78.13

89.29

312.50

625

+0.16

-1.36

+1.73

-6.99

+4.17

+25.00

-

64

32

7

9.55

-0.76

9.47

19.2

76.8

96

19.10

73.66

103.13

257.81

NA

+1.73

19.53

78.13

104.17

312.50

NA

+1.73

6

4

+1.73

3

2

300

500

HIGH

LOW

1

-

0

-

NA

-

625

0

515.63

2.01

-

0

390.63

1.53

0

312.50

1.22

-

0

2.44

-

255

-

255

-

255

FOSC = 16 MHz

10 MHz

7.15909 MHz

5.0688 MHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

KBAUD

ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

NA

1.20

2.40

9.62

19.23

83.33

250

-

207

103

25

12

2

NA

1.20

-

129

64

15

7

NA

1.20

2.38

9.32

18.64

111.86

NA

-

92

46

11

5

NA

1.20

2.40

9.90

19.80

79.20

NA

-

65

32

7

+0.16

+8.51

-13.19

-16.67

-

+0.16

+1.73

-18.62

-47.92

-

+0.23

0

2.4

2.40

-0.83

0

9.6

9.77

-2.90

+3.13

19.2

76.8

96

19.53

78.13

156.25

NA

-2.90

+3.13

3

1

+45.65

0

+3.13

0

2

1

-

300

500

HIGH

LOW

0

NA

-

NA

-

NA

-

NA

-

NA

-

250

-

0

156.25

0.61

-

0

111.86

0.44

0

79.20

0.31

0

0.98

-

255

-

255

FOSC = 4 MHz

3.579545 MHz

%

1 MHz

32.768 kHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

KBAUD

ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

0.30

1.20

2.40

8.93

20.83

62.50

NA

-0.16

207

51

25

6

0.30

1.19

2.43

9.32

18.64

55.93

NA

+0.23

185

46

22

5

0.30

1.20

2.23

7.81

15.63

NA

+0.16

51

12

6

0.26

NA

-14.67

1

+1.67

-0.83

+0.16

-

2.4

+1.67

+1.32

-6.99

NA

-

9.6

-6.99

-2.90

-18.62

1

NA

-

19.2

76.8

96

+8.51

2

-2.90

2

-18.62

0

NA

-

-18.62

0

-27.17

0

-

NA

-

NA

-

NA

-

300

500

HIGH

LOW

NA

-

NA

-

NA

-

NA

-

NA

-

NA

-

NA

-

NA

62.50

0.24

0

55.93

0.22

0

15.63

0.06

0

0.51

0.002

0

255

DS39564C-page 170

PIC18FXX2

TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)

FOSC = 40 MHz

33 MHz

25 MHz

20 MHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

NA

-

NA

-

NA

-

NA

-

9.6

NA

-

+0.16

-1.36

+0.16

+4.17

0

-

9.60

-0.07

+0.39

-0.54

+2.31

-1.79

+3.13

-

214

106

26

20

6

9.59

-0.15

+0.47

+1.73

+4.17

-

162

80

19

15

4

9.62

+0.16

+1.73

+0.16

+4.17

-16.67

-

129

64

15

12

3

19.2

76.8

96

19.23

75.76

96.15

312.50

500

129

32

25

7

19.28

76.39

98.21

294.64

515.63

2062.50

8,06

19.30

78.13

97.66

312.50

520.83

1562.50

6.10

19.23

78.13

96.15

312.50

416.67

1250

4.88

300

500

HIGH

LOW

4

3

2

2500

9.77

-

0

-

255

-

255

-

255

-

255

FOSC = 16 MHz

10 MHz

7.15909 MHz

5.0688 MHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

NA

-

+0.16

+4.17

+11.11

0

-

NA

-

2.41

+0.23

-0.83

+1.32

-2.90

-6.78

+49.15

-10.51

-

185

46

22

5

2.40

0

131

32

16

3

9.6

9.62

19.23

76.92

100

103

51

12

9

9.62

18.94

78.13

89.29

312.50

625

+0.16

-1.36

+1.73

-6.99

+4.17

+25.00

-

64

32

7

9.52

9.60

0

-2.94

+3.13

+10.00

+5.60

-

19.2

76.8

96

19.45

74.57

89.49

447.44

1.75

18.64

79.20

105.60

316.80

NA

6

4

2

300

500

HIGH

LOW

333.33

500

2

1

0

1

0

-

1000

3.91

-

0

625

0

316.80

1.24

-

0

-

255

2.44

-

255

-

255

-

255

FOSC = 4 MHz

3.579545 MHz

1 MHz

32.768 kHz

BAUD

RATE

(Kbps)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

SPBRG

value

(decimal)

%

KBAUD ERROR

0.3

1.2

NA

1.20

2.40

9.62

19.23

NA

-

207

103

25

12

-

NA

1.20

-

+0.23

+1.32

-2.90

+16.52

-25.43

-

185

92

22

11

2

0.30

1.20

2.40

8.93

20.83

62.50

NA

+0.16

207

51

25

6

0.29

1.02

2.05

NA

-2.48

6

+0.16

-14.67

1

2.4

+0.16

2.41

+0.16

-14.67

0

9.6

+0.16

9.73

-6.99

-

19.2

76.8

96

+0.16

18.64

74.57

111.86

223.72

NA

+8.51

2

NA

-

-18.62

0

NA

-

NA

-

1

-

NA

-

300

500

HIGH

LOW

NA

-

0

NA

-

NA

-

NA

-

NA

-

250

0.98

0

55.93

0.22

-

0

62.50

0.24

0

2.05

0.008

0

255

-

255

DS39564C-page 171

PIC18FXX2

flag bit TXIF (PIR1<4>) is set. This interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

( PIE1<4>). Flag bit TXIF will be set, regardless of the

state of enable bit TXIE and cannot be cleared in soft-

ware. It will reset only when new data is loaded into the

TXREG register. While flag bit TXIF indicated the sta-

tus of the TXREG register, another bit, TRMT

(TXSTA<1>), shows the status of the TSR register. Sta-

tus bit TRMT is a read-only bit, which is set when the

TSR register is empty. No interrupt logic is tied to this

bit, so the user has to poll this bit in order to determine

if the TSR register is empty.

16.2 USART Asynchronous Mode

In this mode, the USART uses standard non-return-to-

zero (NRZ) format (one START bit, eight or nine data

bits and one STOP bit). The most common data format

is 8-bits. An on-chip dedicated 8-bit baud rate genera-

tor can be used to derive standard baud rate frequen-

cies from the oscillator. The USART transmits and

receives the LSb first. The USART’s transmitter and

receiver are functionally independent, but use the

same data format and baud rate. The baud rate gener-

ator produces a clock, either x16 or x64 of the bit shift

rate, depending on bit BRGH (TXSTA<2>). Parity is not

supported by the hardware, but can be implemented in

software (and stored as the ninth data bit).

Asynchronous mode is stopped during SLEEP.

Note 1: The TSR register is not mapped in data

memory, so it is not available to the user.

2: Flag bit TXIF is set when enable bit TXEN

is set.

Asynchronous mode is selected by clearing bit SYNC

(TXSTA<4>).

To set up an asynchronous transmission:

The USART Asynchronous module consists of the

following important elements:

1. Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is desired,

set bit BRGH (Section 16.1).

• Baud Rate Generator

• Sampling Circuit

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

• Asynchronous Transmitter

• Asynchronous Receiver

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set transmit bit

TX9. Can be used as address/data bit.

16.2.1

USART ASYNCHRONOUS

TRANSMITTER

5. Enable the transmission by setting bit TXEN,

which will also set bit TXIF.

The USART transmitter block diagram is shown in

Figure 16-1. The heart of the transmitter is the Transmit

(serial) Shift Register (TSR). The shift register obtains

its data from the read/write transmit buffer, TXREG. The

TXREG register is loaded with data in software. The

TSR register is not loaded until the STOP bit has been

transmitted from the previous load. As soon as the

STOP bit is transmitted, the TSR is loaded with new

data from the TXREG register (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCY), the TXREG register is empty and

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Load data to the TXREG register (starts

transmission).

Note: TXIF is not cleared immediately upon load-

ing data into the transmit buffer TXREG.

The flag bit becomes valid in the second

instruction cycle following the load

instruction.

FIGURE 16-1:

USART TRANSMIT BLOCK DIAGRAM

Data Bus

TXIF

TXREG Register

8

TXIE

MSb

(8)

LSb

0

Pin Buffer

and Control

•

• •

TSR Register

RC6/TX/CK pin

Interrupt

TXEN

Baud Rate CLK

TRMT

SPEN

SPBRG

Baud Rate Generator

TX9

TX9D

DS39564C-page 172

PIC18FXX2

FIGURE 16-2:

ASYNCHRONOUS TRANSMISSION

Write to TXREG

Word 1

BRG Output

(Shift Clock)

RC6/TX/CK (pin)

START bit

bit 0

bit 1

Word 1

bit 7/8

STOP bit

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

Word 1

Transmit Shift Reg

TRMT bit

(Transmit Shift

Reg. Empty Flag)

FIGURE 16-3:

ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

Write to TXREG

Word 2

Word 1

BRG Output

(Shift Clock)

RC6/TX/CK (pin)

START bit

bit 0

bit 1

bit 7/8

bit 0

STOP bit

TXIF bit

(Interrupt Reg. Flag)

Word 2

Word 1

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Transmit Shift Reg.

Word 2

Transmit Shift Reg.

Note: This timing diagram shows two consecutive transmissions.

TABLE 16-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF

RBIF

0000 000x 0000 000u

PIR1

PSPIF⁽¹⁾

PSPIE⁽¹⁾

PSPIP⁽¹⁾

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

PIE1

IPR1

RCSTA

SREN CREN ADDEN FERR

OERR

RX9D 0000 -00x 0000 -00x

0000 0000 0000 0000

TXREG USART Transmit Register

TXSTA CSRC TX9 TXEN SYNC

SPBRG Baud Rate Generator Register

—

BRGH TRMT

TX9D 0000 -010 0000 -010

0000 0000 0000 0000

Legend: x= unknown, - = unimplemented locations read as '0'.

Shaded cells are not used for Asynchronous Transmission.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.

DS39564C-page 173

PIC18FXX2

16.2.2

USART ASYNCHRONOUS

RECEIVER

16.2.3

SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

The receiver block diagram is shown in Figure 16-4.

The data is received on the RC7/RX/DT pin and drives

the data recovery block. The data recovery block is

actually a high speed shifter operating at x16 times the

baud rate, whereas the main receive serial shifter oper-

ates at the bit rate or at FOSC. This mode would

typically be used in RS-232 systems.

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is required,

set the BRGH bit.

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

To set up an Asynchronous Reception:

1. Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is desired,

set bit BRGH (Section 16.1).

3. If interrupts are required, set the RCEN bit and

select the desired priority level with the RCIP bit.

4. Set the RX9 bit to enable 9-bit reception.

5. Set the ADDEN bit to enable address detect.

6. Enable reception by setting the CREN bit.

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

3. If interrupts are desired, set enable bit RCIE.

4. If 9-bit reception is desired, set bit RX9.

5. Enable the reception by setting bit CREN.

7. The RCIF bit will be set when reception is com-

plete. The interrupt will be acknowledged if the

RCIE and GIE bits are set.

6. Flag bit RCIF will be set when reception is com-

plete and an interrupt will be generated if enable

bit RCIE was set.

8. Read the RCSTA register to determine if any

error occurred during reception, as well as read

bit 9 of data (if applicable).

7. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

9. Read RCREG to determine if the device is being

addressed.

10. If any error occurred, clear the CREN bit.

8. Read the 8-bit received data by reading the

RCREG register.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and interrupt the CPU.

9. If any error occurred, clear the error by clearing

enable bit CREN.

10. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 16-4:

USART RECEIVE BLOCK DIAGRAM

FERR

OERR

CREN

x64 Baud Rate CLK

÷ 64

or

÷ 16

RSR Register

MSb

LSb

SPBRG

0

7

1

STOP (8)

START

• • •

Baud Rate Generator

RX9

RC7/RX/DT

Pin Buffer

and Control

Data

Recovery

RX9D

RCREG Register

FIFO

SPEN

8

Interrupt

RCIF

RCIE

Data Bus

DS39564C-page 174

PIC18FXX2

FIGURE 16-5:

ASYNCHRONOUS RECEPTION

START

bit

START

bit

START

bit7/8 STOP bit

bit

RX (pin)

bit0

bit1

STOP

bit

STOP

bit

bit0

bit7/8

Rcv Shift

Reg

Rcv Buffer Reg

Word 2

RCREG

Word 1

RCREG

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing

the OERR (overrun) bit to be set.

TABLE 16-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF

GIEL

RBIF

0000 000x 0000 000u

PIR1

PSPIF⁽¹⁾

PSPIE⁽¹⁾ADIE

PSPIP⁽¹⁾ADIP

ADIF

RCIF

RCIE

RCIP

TXIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1

TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

IPR1

RCSTA

SPEN

RX9

SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x

RCREG USART Receive Register

0000 0000 0000 0000

TX9D 0000 -010 0000 -010

0000 0000 0000 0000

TXSTA

CSRC

TX9

TXEN SYNC

—

BRGH TRMT

SPBRG

Baud Rate Generator Register

Legend: x= unknown, - = unimplemented locations read as '0'.

Shaded cells are not used for Asynchronous Reception.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits

clear.

DS39564C-page 175

PIC18FXX2

(PIE1<4>). Flag bit TXIF will be set, regardless of the

state of enable bit TXIE, and cannot be cleared in soft-

ware. It will reset only when new data is loaded into the

TXREG register. While flag bit TXIF indicates the status

of the TXREG register, another bit TRMT (TXSTA<1>)

shows the status of the TSR register. TRMT is a read

only bit, which is set when the TSR is empty. No inter-

rupt logic is tied to this bit, so the user has to poll this

bit in order to determine if the TSR register is empty.

The TSR is not mapped in data memory, so it is not

available to the user.

16.3 USART Synchronous Master

Mode

In Synchronous Master mode, the data is transmitted in

a half-duplex manner (i.e., transmission and reception

do not occur at the same time). When transmitting data,

the reception is inhibited and vice versa. Synchronous

mode is entered by setting bit SYNC (TXSTA<4>). In

addition, enable bit SPEN (RCSTA<7>) is set in order

to configure the RC6/TX/CK and RC7/RX/DT I/O pins

to CK (clock) and DT (data) lines, respectively. The

Master mode indicates that the processor transmits the

master clock on the CK line. The Master mode is

entered by setting bit CSRC (TXSTA<7>).

To set up a Synchronous Master Transmission:

1. Initialize the SPBRG register for the appropriate

baud rate (Section 16.1).

16.3.1

USART SYNCHRONOUS MASTER

TRANSMISSION

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting bit TXEN.

The USART transmitter block diagram is shown in

Figure 16-1. The heart of the transmitter is the Transmit

(serial) Shift Register (TSR). The shift register obtains

its data from the read/write transmit buffer register

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCYCLE), the TXREG is empty and inter-

rupt bit TXIF (PIR1<4>) is set. The interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmission by loading data to the TXREG

register.

Note: TXIF is not cleared immediately upon load-

ing data into the transmit buffer TXREG.

The flag bit becomes valid in the second

instruction cycle following the load

instruction.

TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE/

GIEH

PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF

GIEL

RBIF

0000 000x 0000 000u

PIR1

PSPIF⁽¹⁾ADIF

PSPIE⁽¹⁾ADIE

PSPIP⁽¹⁾ADIP

RCIF

RCIE

RCIP

TXIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1

TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

IPR1

RCSTA

SPEN

RX9

SREN CREN ADDEN FERR

OERR

RX9D

0000 -00x 0000 -00x

0000 0000 0000 0000

0000 -010 0000 -010

0000 0000 0000 0000

TXREG USART Transmit Register

TXSTA CSRC TX9 TXEN SYNC

SPBRG Baud Rate Generator Register

Legend: x= unknown, - = unimplemented, read as '0'.

Shaded cells are not used for Synchronous Master Transmission.

—

BRGH

TRMT

TX9D

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits

clear.

DS39564C-page 176

PIC18FXX2

FIGURE 16-6:

SYNCHRONOUS TRANSMISSION

Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4

Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4

RC7/RX/DT

bit 0

bit 1

bit 2

bit 7

bit 0

bit 1

Word 2

bit 7

Word 1

RC6/TX/CK

Write to

TXREG Reg

Write Word1

Write Word2

TXIF bit

(Interrupt Flag)

TRMT

TRMT bit

'1'

TXEN bit

Note: Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.

FIGURE 16-7:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RC7/RX/DT pin

bit0

bit2

bit1

bit6

bit7

RC6/TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

TXEN bit

DS39564C-page 177

PIC18FXX2

4. If interrupts are desired, set enable bit RCIE.

5. If 9-bit reception is desired, set bit RX9.

16.3.2

USART SYNCHRONOUS MASTER

RECEPTION

6. If a single reception is required, set bit SREN.

For continuous reception, set bit CREN.

Once Synchronous mode is selected, reception is

enabled by setting either enable bit SREN

(RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is

sampled on the RC7/RX/DT pin on the falling edge of

the clock. If enable bit SREN is set, only a single word

is received. If enable bit CREN is set, the reception is

continuous until CREN is cleared. If both bits are set,

then CREN takes precedence.

7. Interrupt flag bit RCIF will be set when reception

is complete and an interrupt will be generated if

the enable bit RCIE was set.

8. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

9. Read the 8-bit received data by reading the

RCREG register.

To set up a Synchronous Master Reception:

1. Initialize the SPBRG register for the appropriate

baud rate (Section 16.1).

10. If any error occurred, clear the error by clearing

bit CREN.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

11. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

3. Ensure bits CREN and SREN are clear.

TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE/

GIEH

PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF

GIEL

RBIF

0000 000x 0000 000u

PIR1

PSPIF⁽¹⁾ADIF

PSPIE⁽¹⁾ADIE

PSPIP⁽¹⁾ADIP

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

PIE1

IPR1

RCSTA

SPEN

RX9

SREN CREN ADDEN FERR

OERR

RX9D 0000 -00x 0000 -00x

0000 0000 0000 0000

RCREG USART Receive Register

TXSTA CSRC TX9 TXEN SYNC

SPBRG Baud Rate Generator Register

—

BRGH

TRMT

TX9D 0000 -010 0000 -010

0000 0000 0000 0000

Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.

FIGURE 16-8:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

RC7/RX/DT pin

RC6/TX/CK pin

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

Write to

bit SREN

SREN bit

CREN bit

'0'

RCIF bit

(Interrupt)

Read

RXREG

Note: Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRGH = '0'.

DS39564C-page 178

PIC18FXX2

To set up a Synchronous Slave Transmission:

16.4 USART Synchronous Slave Mode

1. Enable the synchronous slave serial port by set-

ting bits SYNC and SPEN and clearing bit

CSRC.

Synchronous Slave mode differs from the Master mode

in the fact that the shift clock is supplied externally at

the RC6/TX/CK pin (instead of being supplied internally

in Master mode). This allows the device to transfer or

receive data while in SLEEP mode. Slave mode is

entered by clearing bit CSRC (TXSTA<7>).

2. Clear bits CREN and SREN.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting enable bit

TXEN.

16.4.1

USART SYNCHRONOUS SLAVE

TRANSMIT

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

The operation of the Synchronous Master and Slave

modes are identical, except in the case of the SLEEP

mode.

7. Start transmission by loading data to the TXREG

register.

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in TXREG register.

c) Flag bit TXIF will not be set.

d) When the first word has been shifted out of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit TXIF will now be

set.

e) If enable bit TXIE is set, the interrupt will wake

the chip from SLEEP. If the global interrupt is

enabled, the program will branch to the interrupt

vector.

TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE/

GIEH

PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF

GIEL

RBIF 0000 000x 0000 000u

PIR1

PSPIF⁽¹⁾ADIF

PSPIE⁽¹⁾ADIE

PSPIP⁽¹⁾ADIP

RCIF

RCIE

RCIP

TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

PIE1

IPR1

RCSTA

SPEN

RX9

SREN CREN ADDEN FERR

OERR

RX9D 0000 -00x 0000 -00x

0000 0000 0000 0000

TXREG USART Transmit Register

TXSTA CSRC TX9 TXEN SYNC

SPBRG Baud Rate Generator Register

Legend: x= unknown, - = unimplemented, read as '0'.

Shaded cells are not used for Synchronous Slave Transmission.

—

BRGH

TRMT

TX9D 0000 -010 0000 -010

0000 0000 0000 0000

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits

clear.

DS39564C-page 179

PIC18FXX2

To set up a Synchronous Slave Reception:

16.4.2

USART SYNCHRONOUS SLAVE

RECEPTION

1. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the SLEEP

mode and bit SREN, which is a “don't care” in Slave

mode.

2. If interrupts are desired, set enable bit RCIE.

3. If 9-bit reception is desired, set bit RX9.

4. To enable reception, set enable bit CREN.

If receive is enabled by setting bit CREN prior to the

SLEEPinstruction, then a word may be received during

SLEEP. On completely receiving the word, the RSR

register will transfer the data to the RCREG register,

and if enable bit RCIE bit is set, the interrupt generated

will wake the chip from SLEEP. If the global interrupt is

enabled, the program will branch to the interrupt vector.

5. Flag bit RCIF will be set when reception is com-

plete. An interrupt will be generated if enable bit

RCIE was set.

6. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

7. Read the 8-bit received data by reading the

RCREG register.

8. If any error occurred, clear the error by clearing

bit CREN.

9. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 16-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Value on

All Other

RESETS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR

INTCON

GIE/

GIEH

PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF

GIEL

RBIF 0000 000x 0000 000u

PIR1

PSPIF⁽¹⁾ADIF

PSPIE⁽¹⁾ADIE

PSPIP⁽¹⁾ADIP

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

PIE1

IPR1

RCSTA

SPEN

RX9

SREN CREN ADDEN FERR

OERR

RX9D 0000 -00x 0000 -00x

0000 0000 0000 0000

RCREG USART Receive Register

TXSTA CSRC TX9 TXEN

SPBRG Baud Rate Generator Register

Legend: x= unknown, - = unimplemented, read as '0'.

Shaded cells are not used for Synchronous Slave Reception.

SYNC

—

BRGH TRMT

TX9D 0000 -010 0000 -010

0000 0000 0000 0000

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits

clear.

DS39564C-page 180

PIC18FXX2

The A/D module has four registers. These registers

are:

17.0 COMPATIBLE 10-BIT

ANALOG-TO-DIGITAL

• A/D Result High Register (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) converter module has five

inputs for the PIC18F2X2 devices and eight for the

PIC18F4X2 devices. This module has the ADCON0

and ADCON1 register definitions that are compatible

with the mid-range A/D module.

The ADCON0 register, shown in Register 17-1, con-

trols the operation of the A/D module. The ADCON1

register, shown in Register 17-2, configures the

functions of the port pins.

The A/D allows conversion of an analog input signal to

a corresponding 10-bit digital number.

REGISTER 17-1: ADCON0 REGISTER

R/W-0

ADCS1

bit 7

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0

R/W-0

U-0

—

R/W-0

ADON

bit 0

ADCS0

GO/DONE

bit 7-6

ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)

ADCON1

ADCON0

Clock Conversion

0

1

00

01

10

11

00

01

10

11

FOSC/2

FOSC/8

FOSC/32

FRC (clock derived from the internal A/D RC oscillator)

FOSC/4

FOSC/16

FOSC/64

FRC (clock derived from the internal A/D RC oscillator)

bit 5-3

CHS2:CHS0: Analog Channel Select bits

000= channel 0, (AN0)

001= channel 1, (AN1)

010= channel 2, (AN2)

011= channel 3, (AN3)

100= channel 4, (AN4)

101= channel 5, (AN5)

110= channel 6, (AN6)

111= channel 7, (AN7)

Note: The PIC18F2X2 devices do not implement the full 8 A/D channels; the unimplemented

selections are reserved. Do not select any unimplemented channel.

bit 2

GO/DONE: A/D Conversion Status bit

When ADON = 1:

1= A/D conversion in progress (setting this bit starts the A/D conversion which is automatically

cleared by hardware when the A/D conversion is complete)

0= A/D conversion not in progress

bit 1

bit 0

Unimplemented: Read as '0'

ADON: A/D On bit

1= A/D converter module is powered up

0= A/D converter module is shut-off and consumes no operating current

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 181

PIC18FXX2

REGISTER 17-2: ADCON1 REGISTER

R/W-0

ADFM

R/W-0

U-0

—

U-0

—

R/W-0

ADCS2

PCFG3

PCFG2

PCFG1

PCFG0

bit 7

bit 0

bit 7

bit 6

ADFM: A/D Result Format Select bit

1= Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’.

0= Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.

ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)

ADCON1

ADCON0

Clock Conversion

0

1

00

01

10

11

00

01

10

11

FOSC/2

FOSC/8

FOSC/32

FRC (clock derived from the internal A/D RC oscillator)

FOSC/4

FOSC/16

FOSC/64

FRC (clock derived from the internal A/D RC oscillator)

bit 5-4

bit 3-0

Unimplemented: Read as '0'

PCFG3:PCFG0: A/D Port Configuration Control bits

PCFG

<3:0>

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

VREF+

VREF-

C / R

0000

0001

0010

0011

0100

0101

011x

1000

1001

1010

1011

1100

1101

1110

1111

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

VDD

AN3

VDD

AN3

VDD

AN3

—

VSS

—

8 / 0

7 / 1

5 / 0

4 / 1

3 / 0

2 / 1

0 / 0

6 / 2

6 / 0

5 / 1

4 / 2

3 / 2

2 / 2

1 / 0

1 / 2

VREF+

A

VREF+

A

D

VREF+

D

VREF+

A

VREF-

A

AN3

VDD

AN3

VDD

AN3

AN2

VSS

AN2

VSS

AN2

VREF+

D

A

VREF-

D

VREF+

VREF-

A = Analog input D = Digital I/O

C/R = # of analog input channels / # of A/D voltage references

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Note: On any device RESET, the port pins that are multiplexed with analog functions (ANx) are

forced to be an analog input.

DS39564C-page 182

PIC18FXX2

The analog reference voltage is software selectable to

either the device’s positive and negative supply voltage

(VDD and VSS), or the voltage level on the RA3/AN3/

VREF+ pin and RA2/AN2/VREF- pin.

Each port pin associated with the A/D converter can be

configured as an analog input (RA3 can also be a

voltage reference) or as a digital I/O.

The ADRESH and ADRESL registers contain the result

of the A/D conversion. When the A/D conversion is

complete, the result is loaded into the ADRESH/

ADRESL registers, the GO/DONE bit (ADCON0<2>) is

cleared, and A/D interrupt flag bit, ADIF is set. The block

diagram of the A/D module is shown in Figure 17-1.

The A/D converter has a unique feature of being able

to operate while the device is in SLEEP mode. To oper-

ate in SLEEP, the A/D conversion clock must be

derived from the A/D’s internal RC oscillator.

The output of the sample and hold is the input into the

converter, which generates the result via successive

approximation.

A device RESET forces all registers to their RESET

state. This forces the A/D module to be turned off and

any conversion is aborted.

FIGURE 17-1:

A/D BLOCK DIAGRAM

CHS<2:0>

111

AN7*

110

AN6*

101

AN5*

100

AN4

VAIN

011

(Input Voltage)

AN3

010

AN2

10-bit

Converter

A/D

001

AN1

PCFG<3:0>

000

AN0

VDD

VREF+

VREF-

Reference

Voltage

VSS

* These channels are implemented only on the PIC18F4X2 devices.

DS39564C-page 183

PIC18FXX2

The value that is in the ADRESH/ADRESL registers is

not modified for a Power-on Reset. The ADRESH/

ADRESL registers will contain unknown data after a

Power-on Reset.

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

(interrupts disabled)

OR

After the A/D module has been configured as desired,

the selected channel must be acquired before the con-

version is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 17.1.

After this acquisition time has elapsed, the A/D conver-

sion can be started. The following steps should be

followed for doing an A/D conversion:

• Waiting for the A/D interrupt

6. Read A/D Result registers (ADRESH/ADRESL);

clear bit ADIF if required.

7. For next conversion, go to step 1 or step 2 as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before the next acquisition starts.

1. Configure the A/D module:

17.1 A/D Acquisition Requirements

• Configure analog pins, voltage reference and

digital I/O (ADCON1)

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 17-2. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD). The source impedance affects the offset voltage

at the analog input (due to pin leakage current). The

maximum recommended impedance for analog

sources is 2.5 kΩ. After the analog input channel is

selected (changed), this acquisition must be done

before the conversion can be started.

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

• Set PEIE bit

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE bit (ADCON0)

Note: When the conversion is started, the hold-

ing capacitor is disconnected from the

input pin.

FIGURE 17-2:

ANALOG INPUT MODEL

VDD

Sampling

Switch

VT = 0.6V

ANx

SS

RIC ≤ 1k

RSS

Rs

CPIN

5 pF

I LEAKAGE

500 nA

VAIN

CHOLD = 120 pF

VT = 0.6V

VSS

Legend: CPIN

VT

= input capacitance

= threshold voltage

6V

5V

VDD 4V

I LEAKAGE = leakage current at the pin due to

various junctions

3V

RIC

SS

= interconnect resistance

= sampling switch

2V

CHOLD

= sample/hold capacitance (from DAC)

5

6 7 8 9 10 11

Sampling Switch (kΩ)

DS39564C-page 184

PIC18FXX2

To calculate the minimum acquisition time,

Equation 17-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

EQUATION 17-1: ACQUISITION TIME

TACQ

=

Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

TAMP + TC + TCOFF

EQUATION 17-2: A/D MINIMUM CHARGING TIME

VHOLD =

or

(VREF – (VREF/2048)) • (1 – e^{(-Tc/CHOLD(RIC + RSS + RS))}

)

TC

=

-(120 pF)(1 kΩ + RSS + RS) ln(1/2048)

Example 17-1 shows the calculation of the minimum

required acquisition time, TACQ. This calculation is

based on the following application system assump-

tions:

• CHOLD

=

≤

=

120 pF

• Rs

2.5 kΩ

1/2 LSb

• Conversion Error

• VDD

5V → Rss = 7 kΩ

50°C (system max.)

0V @ time = 0

• Temperature

• VHOLD

EXAMPLE 17-1:

CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

TACQ

=

TAMP + TC + TCOFF

Temperature coefficient is only required for temperatures > 25°C.

TACQ

TC

=

2 μs + TC + [(Temp – 25°C)(0.05 μs/°C)]

-CHOLD (RIC + RSS + RS) ln(1/2048)

-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004883)

-120 pF (10.5 kΩ) ln(0.0004883)

-1.26 μs (-7.6246)

9.61 μs

TACQ

=

2 μs + 9.61 μs + [(50°C – 25°C)(0.05 μs/°C)]

11.61 μs + 1.25 μs

12.86 μs

DS39564C-page 185

PIC18FXX2

17.2 Selecting the A/D Conversion Clock

17.3 Configuring Analog Port Pins

The A/D conversion time per bit is defined as TAD. The

A/D conversion requires 12 TAD per 10-bit conversion.

The source of the A/D conversion clock is software

selectable. The seven possible options for TAD are:

The ADCON1, TRISA and TRISE registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs, must have their corresponding

TRIS bits set (input). If the TRIS bit is cleared (output),

the digital output level (VOH or VOL) will be converted.

• 2 TOSC

The A/D operation is independent of the state of the

CHS2:CHS0 bits and the TRIS bits.

• 4 TOSC

• 8 TOSC

• 16 TOSC

Note 1: When reading the port register, all pins con-

figured as analog input channels will read

as cleared (a low level). Pins configured as

digital inputs will convert an analog input.

Analog levels on a digitally configured input

will not affect the conversion accuracy.

• 32 TOSC

• 64 TOSC

• Internal A/D module RC oscillator (2-6 μs)

For correct A/D conversions, the A/D conversion clock

(TAD) must be selected to ensure a minimum TAD time

of 1.6 μs.

2: Analog levels on any pin that is defined as

a digital input (including the AN4:AN0

pins) may cause the input buffer to con-

sume current that is out of the device’s

specification.

Table 17-1 shows the resultant TAD times derived from

the device operating frequencies and the A/D clock

source selected.

TABLE 17-1: TAD vs. DEVICE OPERATING FREQUENCIES

AD Clock Source (TAD)

Maximum Device Frequency

Operation

ADCS2:ADCS0

PIC18FXX2

PIC18LFXX2

2 TOSC

4 TOSC

8 TOSC

16 TOSC

32 TOSC

64 TOSC

RC

000

100

001

101

010

110

011

1.25 MHz

2.50 MHz

5.00 MHz

10.00 MHz

20.00 MHz

40.00 MHz

—

666 kHz

1.33 MHz

2.67 MHz

5.33 MHz

10.67 MHz

21.33 MHz

—

DS39564C-page 186

PIC18FXX2

(or the last value written to the ADRESH:ADRESL reg-

isters). After the A/D conversion is aborted, a 2 TAD wait

is required before the next acquisition is started. After

this 2 TAD wait, acquisition on the selected channel is

automatically started. The GO/DONE bit can then be

set to start the conversion.

17.4 A/D Conversions

Figure 17-3 shows the operation of the A/D converter

after the GO bit has been set. Clearing the GO/DONE

bit during a conversion will abort the current conver-

sion. The A/D result register pair will NOT be updated

with the partially completed A/D conversion sample.

That is, the ADRESH:ADRESL registers will continue

to contain the value of the last completed conversion

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

FIGURE 17-3:

A/D CONVERSION TAD CYCLES

TCY - TAD

TAD1

TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8

TAD9

b1

TAD10 TAD11

b0

b5

b4

b3 b2

b7

b6

b8

b9

Conversion Starts

Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO bit

Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

Format Select bit (ADFM) controls this justification.

Figure 17-4 shows the operation of the A/D result justi-

fication. The extra bits are loaded with ’0’s. When an

A/D result will not overwrite these locations (A/D

disable), these registers may be used as two general

purpose 8-bit registers.

17.4.1

A/D RESULT REGISTERS

The ADRESH:ADRESL register pair is the location

where the 10-bit A/D result is loaded at the completion

of the A/D conversion. This register pair is 16-bits wide.

The A/D module gives the flexibility to left or right justify

the 10-bit result in the 16-bit result register. The A/D

FIGURE 17-4:

A/D RESULT JUSTIFICATION

10-bit Result

ADFM = 0

ADFM = 1

0

7

2 1 0 7

0 7 6 5

0

0000 00

ADRESH

ADRESL

ADRESH

ADRESL

10-bit Result

Left Justified

Right Justified

DS39564C-page 187

PIC18FXX2

(moving ADRESH/ADRESL to the desired location).

The appropriate analog input channel must be selected

and the minimum acquisition done before the “special

17.5 Use of the CCP2 Trigger

An A/D conversion can be started by the “special event

trigger” of the CCP2 module. This requires that the

CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-

grammed as 1011and that the A/D module is enabled

(ADON bit is set). When the trigger occurs, the GO/

DONE bit will be set, starting the A/D conversion, and

the Timer1 (or Timer3) counter will be reset to zero.

Timer1 (or Timer3) is reset to automatically repeat the

A/D acquisition period with minimal software overhead

event trigger” sets the GO/DONE bit (starts

conversion).

a

If the A/D module is not enabled (ADON is cleared), the

“special event trigger” will be ignored by the A/D

module, but will still reset the Timer1 (or Timer3)

counter.

TABLE 17-2: SUMMARY OF A/D REGISTERS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Other

RESETS

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

(1)

PIR1

PIE1

IPR1

PIR2

PIE2

IPR2

PSPIF

PSPIE

PSPIP

—

ADIF

ADIE

ADIP

—

RCIF

RCIE

RCIP

—

TXIF

TXIE

TXIP

EEIF

EEIE

EEIP

SSPIF

SSPIE

SSPIP

BCLIF

BCLIE

BCLIP

CCP1IF

CCP1IE

CCP1IP

LVDIF

TMR2IF TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

TMR2IP TMR1IP 0000 0000 0000 0000

TMR3IF CCP2IF ---0 0000 ---0 0000

TMR3IE CCP2IE ---0 0000 ---0 0000

TMR3IP CCP2IP ---1 1111 ---1 0000

xxxx xxxx uuuu uuuu

(1)

—

LVDIE

—

LVDIP

ADRESH A/D Result Register

ADRESL A/D Result Register

xxxx xxxx uuuu uuuu

ADCON0

ADCON1

PORTA

TRISA

ADCS1

ADFM

—

ADCS0

ADCS2

RA6

CHS2

—

CHS1

—

CHS0 GO/DONE

—

ADON 0000 00-0 0000 00-0

PCFG0 ---- -000 ---- -000

PCFG3

RA3

PCFG2

RA2

PCFG1

RA1

RA5

RA4

RA0

--0x 0000 --0u 0000

--11 1111 --11 1111

---- -000 ---- -000

—

PORTA Data Direction Register

PORTE

LATE

—

RE2

RE1

RE0

—

LATE2

LATE1

LATE0 ---- -xxx ---- -uuu

TRISE

IBF

OBF

IBOV

PSPMODE

PORTE Data Direction bits

0000 -111 0000 -111

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.

DS39564C-page 188

PIC18FXX2

The Low Voltage Detect circuitry is completely under

software control. This allows the circuitry to be “turned

off” by the software, which minimizes the current

consumption for the device.

18.0 LOW VOLTAGE DETECT

In many applications, the ability to determine if the

device voltage (VDD) is below a specified voltage level

is a desirable feature. A window of operation for the

application can be created, where the application soft-

ware can do “housekeeping tasks” before the device

voltage exits the valid operating range. This can be

done using the Low Voltage Detect module.

Figure 18-1 shows a possible application voltage curve

(typically for batteries). Over time, the device voltage

decreases. When the device voltage equals voltage VA,

the LVD logic generates an interrupt. This occurs at

time TA. The application software then has the time,

until the device voltage is no longer in valid operating

range, to shutdown the system. Voltage point VB is the

minimum valid operating voltage specification. This

occurs at time TB. The difference TB - TA is the total

time for shutdown.

This module is a software programmable circuitry,

where a device voltage trip point can be specified.

When the voltage of the device becomes lower then the

specified point, an interrupt flag is set. If the interrupt is

enabled, the program execution will branch to the inter-

rupt vector address and the software can then respond

to that interrupt source.

FIGURE 18-1:

TYPICAL LOW VOLTAGE DETECT APPLICATION

VA

VB

Legend:

VA = LVD trip point

VB = Minimum valid device

operating voltage

TB

TA

Time

The block diagram for the LVD module is shown in

Figure 18-2. A comparator uses an internally gener-

ated reference voltage as the set point. When the

selected tap output of the device voltage crosses the

set point (is lower than), the LVDIF bit is set.

supply voltage is equal to the trip point, the voltage

tapped off of the resistor array is equal to the 1.2V

internal reference voltage generated by the voltage

reference module. The comparator then generates an

interrupt signal setting the LVDIF bit. This voltage is

software programmable to any one of 16 values (see

Figure 18-2). The trip point is selected by

programming the LVDL3:LVDL0 bits (LVDCON<3:0>).

Each node in the resistor divider represents a “trip

point” voltage. The “trip point” voltage is the minimum

supply voltage level at which the device can operate

before the LVD module asserts an interrupt. When the

DS39564C-page 189

PIC18FXX2

FIGURE 18-2:

LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM

VDD

LVDIN

LVD Control

Register

–

+

LVDIF

Internally Generated

LVDEN

Reference Voltage

1.2V Typical

The LVD module has an additional feature that allows

the user to supply the trip voltage to the module from

an external source. This mode is enabled when bits

LVDL3:LVDL0 are set to 1111. In this state, the com-

parator input is multiplexed from the external input pin,

LVDIN (Figure 18-3). This gives users flexibility,

because it allows them to configure the Low Voltage

Detect interrupt to occur at any voltage in the valid

operating range.

FIGURE 18-3:

LOW VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM

VDD

LVD Control

Register

LVDIN

LVDEN

Externally Generated

Trip Point

–

+

LVD

VxEN

BODEN

EN

BGAP

DS39564C-page 190

PIC18FXX2

18.1 Control Register

The Low Voltage Detect Control register controls the

operation of the Low Voltage Detect circuitry.

REGISTER 18-1: LVDCON REGISTER

U-0

—

U-0

—

R-0

R/W-0

LVDL3

R/W-1

LVDL2

R/W-0

LVDL1

R/W-1

LVDL0

IRVST

LVDEN

bit 7

bit 0

bit 7-6

bit 5

Unimplemented: Read as '0'

IRVST: Internal Reference Voltage Stable Flag bit

1= Indicates that the Low Voltage Detect logic will generate the interrupt flag at the

specified voltage range

0= Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the

specified voltage range and the LVD interrupt should not be enabled

bit 4

LVDEN: Low Voltage Detect Power Enable bit

1= Enables LVD, powers up LVD circuit

0= Disables LVD, powers down LVD circuit

bit 3-0

LVDL3:LVDL0: Low Voltage Detection Limit bits

1111= External analog input is used (input comes from the LVDIN pin)

1110= 4.5V - 4.77V

1101= 4.2V - 4.45V

1100= 4.0V - 4.24V

1011= 3.8V - 4.03V

1010= 3.6V - 3.82V

1001= 3.5V - 3.71V

1000= 3.3V - 3.50V

0111= 3.0V - 3.18V

0110= 2.8V - 2.97V

0101= 2.7V - 2.86V

0100= 2.5V - 2.65V

0011= 2.4V - 2.54V

0010= 2.2V - 2.33V

0001= 2.0V - 2.12V

0000= Reserved

Note:

LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage

of the device are not tested.

Legend:

R = Readable bit

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39564C-page 191

PIC18FXX2

The following steps are needed to set up the LVD

module:

18.2 Operation

Depending on the power source for the device voltage,

the voltage normally decreases relatively slowly. This

means that the LVD module does not need to be con-

stantly operating. To decrease the current require-

ments, the LVD circuitry only needs to be enabled for

short periods, where the voltage is checked. After

doing the check, the LVD module may be disabled.

1. Write the value to the LVDL3:LVDL0 bits

(LVDCON register), which selects the desired

LVD Trip Point.

2. Ensure that LVD interrupts are disabled (the

LVDIE bit is cleared or the GIE bit is cleared).

3. Enable the LVD module (set the LVDEN bit in

the LVDCON register).

Each time that the LVD module is enabled, the circuitry

requires some time to stabilize. After the circuitry has

stabilized, all status flags may be cleared. The module

will then indicate the proper state of the system.

4. Wait for the LVD module to stabilize (the IRVST

bit to become set).

5. Clear the LVD interrupt flag, which may have

falsely become set until the LVD module has

stabilized (clear the LVDIF bit).

6. Enable the LVD interrupt (set the LVDIE and the

GIE bits).

Figure 18-4 shows typical waveforms that the LVD

module may be used to detect.

FIGURE 18-4:

LOW VOLTAGE DETECT WAVEFORMS

CASE 1:

LVDIF may not be set

VDD

VLVD

LVDIF

Enable LVD

Internally Generated

Reference Stable

TIVRST

LVDIF cleared in software

CASE 2:

VDD

VLVD

LVDIF

Enable LVD

TIVRST

Internally Generated

Reference Stable

LVDIF cleared in software

LVDIF cleared in software,

LVDIF remains set since LVD condition still exists

DS39564C-page 192

PIC18FXX2

18.2.1

REFERENCE VOLTAGE SET POINT

18.3 Operation During SLEEP

The Internal Reference Voltage of the LVD module may

be used by other internal circuitry (the Programmable

Brown-out Reset). If these circuits are disabled (lower

current consumption), the reference voltage circuit

requires a time to become stable before a low voltage

condition can be reliably detected. This time is invariant

of system clock speed. This start-up time is specified in

electrical specification parameter 36. The low voltage

interrupt flag will not be enabled until a stable reference

voltage is reached. Refer to the waveform in Figure 18-4.

When enabled, the LVD circuitry continues to operate

during SLEEP. If the device voltage crosses the trip

point, the LVDIF bit will be set and the device will wake-

up from SLEEP. Device execution will continue from

the interrupt vector address if interrupts have been

globally enabled.

18.4 Effects of a RESET

A device RESET forces all registers to their RESET

state. This forces the LVD module to be turned off.

18.2.2

CURRENT CONSUMPTION

When the module is enabled, the LVD comparator and

voltage divider are enabled and will consume static cur-

rent. The voltage divider can be tapped from multiple

places in the resistor array. Total current consumption,

when enabled, is specified in electrical specification

parameter #D022B.

DS39564C-page 193

PIC18FXX2

NOTES:

DS39564C-page 194

PIC18FXX2

19.1 Configuration Bits

19.0 SPECIAL FEATURES OF THE

CPU

The configuration bits can be programmed (read as '0'),

or left unprogrammed (read as '1'), to select various

device configurations. These bits are mapped starting

at program memory location 300000h.

There are several features intended to maximize sys-

tem reliability, minimize cost through elimination of

external components, provide power saving Operating

modes and offer code protection. These are:

The user will note that address 300000h is beyond the

user program memory space. In fact, it belongs to the

configuration memory space (300000h - 3FFFFFh),

which can only be accessed using Table Reads and

Table Writes.

• OSC Selection

• RESET

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

Programming the configuration registers is done in a

manner similar to programming the FLASH memory

(see Section 5.5.1). The only difference is the configu-

ration registers are written a byte at a time. The

sequence of events for programming configuration

registers is:

• Watchdog Timer (WDT)

• SLEEP

1. Load table pointer with address of configuration

register being written.

• Code Protection

• ID Locations

2. Write a single byte using the TBLWTinstruction.

• In-Circuit Serial Programming

3. Set EEPGD to point to program memory, set the

CFGS bit to access configuration registers, and

set WREN to enable byte writes.

All PIC18FXX2 devices have a Watchdog Timer, which

is permanently enabled via the configuration bits or

software controlled. It runs off its own RC oscillator for

added reliability. There are two timers that offer neces-

sary delays on power-up. One is the Oscillator Start-up

Timer (OST), intended to keep the chip in RESET until

the crystal oscillator is stable. The other is the Power-

up Timer (PWRT), which provides a fixed delay on

power-up only, designed to keep the part in RESET

while the power supply stabilizes. With these two tim-

ers on-chip, most applications need no external

RESET circuitry.

4. Disable interrupts.

5. Write 55h to EECON2.

6. Write AAh to EECON2.

7. Set the WR bit. This will begin the write cycle.

8. CPU will stall for duration of write (approximately

2 ms using internal timer).

9. Execute a NOP.

10. Re-enable interrupts.

SLEEP mode is designed to offer a very low current

Power-down mode. The user can wake-up from

SLEEP through external RESET, Watchdog Timer

Wake-up or through an interrupt. Several oscillator

options are also made available to allow the part to fit

the application. The RC oscillator option saves system

cost, while the LP crystal option saves power. A set of

configuration bits are used to select various options.

DS39564C-page 195

PIC18FXX2

TABLE 19-1: CONFIGURATION BITS AND DEVICE IDS

Default/

Unprogrammed

Value

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300001h

CONFIG1H

CONFIG2L

CONFIG2H

CONFIG3H

CONFIG4L

CONFIG5L

CONFIG5H

CONFIG6L

CONFIG6H

CONFIG7L

CONFIG7H

—

OSCSEN

—

FOSC2

BORV0

FOSC1

BOREN

FOSC0

--1- -111

300002h

300003h

300005h

300006h

300008h

300009h

30000Ah

30000Bh

30000Ch

30000Dh

—

BORV1

PWRTEN

WDTEN

CCP2MX

STVREN

CP0

---- 1111

---- ---1

1--- -1-1

---- 1111

11-- ----

---- 1111

111- ----

---- 1111

-1-- ----

(1)

WDTPS2 WDTPS1 WDTPS0

—

LVP

—

DEBUG

—

CP3

—

CP2

—

CP1

—

CPD

—

CPB

—

WRT3

—

WRT2

—

WRT1

—

WRT0

—

WRTD

—

WRTB

—

WRTC

—

EBTR3

—

EBTR2

—

EBTR1

—

EBTR0

—

EBTRB

DEV1

DEV9

—

3FFFFEh DEVID1

3FFFFFh DEVID2

DEV2

DEV10

DEV0

DEV8

REV4

DEV7

REV3

DEV6

REV2

DEV5

REV1

DEV4

REV0

DEV3

0000 0100

Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition.

Shaded cells are unimplemented, read as ‘0’.

Note 1: See Register 19-12 for DEVID1 values.

REGISTER 19-1: CONFIGURATIONREGISTER1HIGH(CONFIG1H:BYTEADDRESS300001h)

U-0

—

U-0

—

R/P-1

U-0

—

U-0

—

R/P-1

OSCSEN

FOSC2 FOSC1 FOSC0

bit 0

bit 7

bit 7-6

bit 5

Unimplemented: Read as ‘0’

OSCSEN: Oscillator System Clock Switch Enable bit

1= Oscillator system clock switch option is disabled (main oscillator is source)

0= Oscillator system clock switch option is enabled (oscillator switching is enabled)

bit 4-3

bit 2-0

Unimplemented: Read as ‘0’

FOSC2:FOSC0: Oscillator Selection bits

111= RC oscillator w/ OSC2 configured as RA6

110= HS oscillator with PLL enabled/Clock frequency = (4 x FOSC)

101= EC oscillator w/ OSC2 configured as RA6

100= EC oscillator w/ OSC2 configured as divide-by-4 clock output

011= RC oscillator

010= HS oscillator

001= XT oscillator

000= LP oscillator

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS39564C-page 196

PIC18FXX2

REGISTER 19-2: CONFIGURATION REGISTER 2 LOW (CONFIG2L: BYTE ADDRESS 300002h)

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

BORV1

BORV0 BOREN PWRTEN

bit 0

bit 7

bit 7-4

bit 3-2

Unimplemented: Read as ‘0’

BORV1:BORV0: Brown-out Reset Voltage bits

11= VBOR set to 2.5V

10= VBOR set to 2.7V

01= VBOR set to 4.2V

00= VBOR set to 4.5V

bit 1

bit 0

BOREN: Brown-out Reset Enable bit

1= Brown-out Reset enabled

0= Brown-out Reset disabled

PWRTEN: Power-up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

REGISTER 19-3: CONFIGURATION REGISTER 2 HIGH (CONFIG2H:BYTE ADDRESS 300003h)

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

WDTPS2 WDTPS1 WDTPS0 WDTEN

bit 0

bit 7

bit 7-4

bit 3-1

Unimplemented: Read as ‘0’

WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits

111= 1:128

110= 1:64

101= 1:32

100= 1:16

011= 1:8

010= 1:4

001= 1:2

000= 1:1

bit 0

WDTEN: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled (control is placed on the SWDTEN bit)

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS39564C-page 197

PIC18FXX2

REGISTER 19-4: CONFIGURATION REGISTER 3 HIGH (CONFIG3H:BYTE ADDRESS 300005h)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

CCP2MX

bit 0

bit 7

bit 7-1

bit 0

Unimplemented: Read as ‘0’

CCP2MX: CCP2 Mux bit

1= CCP2 input/output is multiplexed with RC1

0= CCP2 input/output is multiplexed with RB3

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

REGISTER 19-5: CONFIGURATION REGISTER 4 LOW (CONFIG4L:BYTE ADDRESS300006h)

R/P-1

BKBUG

bit 7

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

LVP

U-0

—

R/P-1

STVREN

bit 0

bit 7

DEBUG: Background Debugger Enable bit

1= Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins.

0= Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.

bit 6-3

bit 2

Unimplemented: Read as ‘0’

LVP: Low Voltage ICSP Enable bit

1= Low Voltage ICSP enabled

0= Low Voltage ICSP disabled

bit 1

bit 0

Unimplemented: Read as ‘0’

STVREN: Stack Full/Underflow Reset Enable bit

1= Stack Full/Underflow will cause RESET

0= Stack Full/Underflow will not cause RESET

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS39564C-page 198

PIC18FXX2

REGISTER 19-6: CONFIGURATION REGISTER 5 LOW (CONFIG5L: BYTE ADDRESS 300008h)

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1

CP3⁽¹⁾

R/C-1

CP2⁽¹⁾

R/C-1

CP1

R/C-1

CP0

bit 7

bit 0

bit 7-4

bit 3

Unimplemented: Read as ‘0’

CP3: Code Protection bit⁽¹⁾

1= Block 3 (006000-007FFFh) not code protected

0= Block 3 (006000-007FFFh) code protected

bit 2

bit 1

bit 0

CP2: Code Protection bit⁽¹⁾

1= Block 2 (004000-005FFFh) not code protected

0= Block 2 (004000-005FFFh) code protected

CP1: Code Protection bit

1= Block 1 (002000-003FFFh) not code protected

0= Block 1 (002000-003FFFh) code protected

CP0: Code Protection bit

1= Block 0 (000200-001FFFh) not code protected

0= Block 0 (000200-001FFFh) code protected

Note 1: Unimplemented in PIC18FX42 devices; maintain this bit set.

Legend:

R = Readable bit

- n = Value when device is unprogrammed

C = Clearable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

REGISTER 19-7: CONFIGURATIONREGISTER5HIGH(CONFIG5H:BYTEADDRESS300009h)

R/C-1

CPD

R/C-1

CPB

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

bit 7

CPD: Data EEPROM Code Protection bit

1= Data EEPROM not code protected

0= Data EEPROM code protected

bit 6

CPB: Boot Block Code Protection bit

1= Boot Block (000000-0001FFh) not code protected

0= Boot Block (000000-0001FFh) code protected

bit 5-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

DS39564C-page 199

PIC18FXX2

REGISTER 19-8: CONFIGURATIONREGISTER6LOW(CONFIG6L:BYTEADDRESS30000Ah)

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1

WRT3⁽¹⁾WRT2⁽¹⁾

R/C-1

WRT1

R/C-1

WRT0

bit 7

bit 0

bit 7-4

bit 3

Unimplemented: Read as ‘0’

WRT3: Write Protection bit⁽¹⁾

1= Block 3 (006000-007FFFh) not write protected

0= Block 3 (006000-007FFFh) write protected

bit 2

bit 1

bit 0

WRT2: Write Protection bit⁽¹⁾

1= Block 2 (004000-005FFFh) not write protected

0= Block 2 (004000-005FFFh) write protected

WRT1: Write Protection bit

1= Block 1 (002000-003FFFh) not write protected

0= Block 1 (002000-003FFFh) write protected

WRT0: Write Protection bit

1= Block 0 (000200h-001FFFh) not write protected

0= Block 0 (000200h-001FFFh) write protected

Note 1: Unimplemented in PIC18FX42 devices; maintain this bit set.

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

REGISTER 19-9: CONFIGURATIONREGISTER6HIGH(CONFIG6H:BYTEADDRESS30000Bh)

R/C-1

C-1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

WRTD

WRTB

WRTC

bit 7

bit 0

bit 7

bit 6

bit 5

WRTD: Data EEPROM Write Protection bit

1= Data EEPROM not write protected

0= Data EEPROM write protected

WRTB: Boot Block Write Protection bit

1= Boot Block (000000-0001FFh) not write protected

0= Boot Block (000000-0001FFh) write protected

WRTC: Configuration Register Write Protection bit

1= Configuration registers (300000-3000FFh) not write protected

0= Configuration registers (300000-3000FFh) write protected

Note: This bit is read only, and cannot be changed in User mode.

Unimplemented: Read as ‘0’

bit 4-0

Legend:

R = Readable bit

C =Clearable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS39564C-page 200

PIC18FXX2

REGISTER 19-10: CONFIGURATIONREGISTER7LOW(CONFIG7L:BYTEADDRESS30000Ch)

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1

EBTR3⁽¹⁾EBTR2⁽¹⁾EBTR1

EBTR0

bit 7

bit 0

bit 7-4

bit 3

Unimplemented: Read as ‘0’

EBTR3: Table Read Protection bit⁽¹⁾

1= Block 3 (006000-007FFFh) not protected from Table Reads executed in other blocks

0= Block 3 (006000-007FFFh) protected from Table Reads executed in other blocks

bit 2

bit 1

bit 0

EBTR2: Table Read Protection bit⁽¹⁾

1= Block 2 (004000-005FFFh) not protected from Table Reads executed in other blocks

0= Block 2 (004000-005FFFh) protected from Table Reads executed in other blocks

EBTR1: Table Read Protection bit

1= Block 1 (002000-003FFFh) not protected from Table Reads executed in other blocks

0= Block 1 (002000-003FFFh) protected from Table Reads executed in other blocks

EBTR0: Table Read Protection bit

1= Block 0 (000200h-001FFFh) not protected from Table Reads executed in other blocks

0= Block 0 (000200h-001FFFh) protected from Table Reads executed in other blocks

Note 1: Unimplemented in PIC18FX42 devices; maintain this bit set.

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

REGISTER 19-11: CONFIGURATIONREGISTER 7HIGH (CONFIG7H:BYTEADDRESS30000Dh)

U-0

—

R/C-1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

EBTRB

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ‘0’

EBTRB: Boot Block Table Read Protection bit

1= Boot Block (000000-0001FFh) not protected from Table Reads executed in other blocks

0= Boot Block (000000-0001FFh) protected from Table Reads executed in other blocks

bit 5-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

C =Clearable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS39564C-page 201

PIC18FXX2

REGISTER 19-12: DEVICE ID REGISTER 1 FOR PIC18FXX2 (DEVID1: BYTE ADDRESS 3FFFFEh)

R

DEV2

DEV1

DEV0

REV4

REV3

REV2

REV1

REV0

bit 7

bit 0

bit 7-5

bit 4-0

DEV2:DEV0: Device ID bits

000= PIC18F252

001= PIC18F452

100= PIC18F242

101= PIC18F442

REV4:REV0: Revision ID bits

These bits are used to indicate the device revision.

Legend:

R = Readable bit

P =Programmable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

REGISTER 19-13: DEVICEIDREGISTER2FORPIC18FXX2(DEVID2:BYTEADDRESS3FFFFFh)

R

DEV10

DEV9

DEV8

DEV7

DEV6

DEV5

DEV4

DEV3

bit 7

bit 0

bit 7-0

DEV10:DEV3: Device ID bits

These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the

part number.

Legend:

R = Readable bit

P =Programmable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS39564C-page 202

PIC18FXX2

The WDT time-out period values may be found in the

Electrical Specifications (Section 22.0) under parame-

ter D031. Values for the WDT postscaler may be

assigned using the configuration bits.

19.2 Watchdog Timer (WDT)

The Watchdog Timer is a free running on-chip RC oscil-

lator, which does not require any external components.

This RC oscillator is separate from the RC oscillator of

the OSC1/CLKI pin. That means that the WDT will run,

even if the clock on the OSC1/CLKI and OSC2/CLKO/

RA6 pins of the device has been stopped, for example,

by execution of a SLEEPinstruction.

Note: The CLRWDTand SLEEPinstructions clear

the WDT and the postscaler, if assigned to

the WDT and prevent it from timing out and

generating a device RESET condition.

During normal operation, a WDT time-out generates a

device RESET (Watchdog Timer Reset). If the device is

in SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation (Watch-

dog Timer Wake-up). The TO bit in the RCON register

will be cleared upon a WDT time-out.

Note: When a CLRWDT instruction is executed

and the postscaler is assigned to the WDT,

the postscaler count will be cleared, but the

postscaler assignment is not changed.

The Watchdog Timer is enabled/disabled by a device

configuration bit. If the WDT is enabled, software exe-

cution may not disable this function. When the WDTEN

configuration bit is cleared, the SWDTEN bit enables/

disables the operation of the WDT.

19.2.1

CONTROL REGISTER

Register 19-14 shows the WDTCON register. This is a

readable and writable register, which contains a control

bit that allows software to override the WDT enable

configuration bit, only when the configuration bit has

disabled the WDT.

REGISTER 19-14: WDTCON REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SWDTEN

bit 0

bit 7

bit 7-1

bit 0

Unimplemented: Read as ’0’

SWDTEN: Software Controlled Watchdog Timer Enable bit

1= Watchdog Timer is on

0= Watchdog Timer is turned off if the WDTEN configuration bit in the configuration

register = ‘0’

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

DS39564C-page 203

PIC18FXX2

19.2.2

WDT POSTSCALER

The WDT has a postscaler that can extend the WDT

Reset period. The postscaler is selected at the time of

the device programming, by the value written to the

CONFIG2H configuration register.

FIGURE 19-1:

WATCHDOG TIMER BLOCK DIAGRAM

WDT Timer

Postscaler

8

8 - to - 1 MUX

WDTPS2:WDTPS0

WDTEN

Configuration bit

SWDTEN bit

WDT

Time-out

Note:

WDPS2:WDPS0 are bits in register CONFIG2H.

TABLE 19-2: SUMMARY OF WATCHDOG TIMER REGISTERS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CONFIG2H

RCON

—

IPEN

—

RI

—

WDTPS2 WDTPS2 WDTPS0

WDTEN

BOR

TO

—

PD

—

POR

—

WDTCON

SWDTEN

Legend: Shaded cells are not used by the Watchdog Timer.

DS39564C-page 204

PIC18FXX2

External MCLR Reset will cause a device RESET. All

other events are considered a continuation of program

execution and will cause a “wake-up”. The TO and PD

bits in the RCON register can be used to determine the

cause of the device RESET. The PD bit, which is set on

power-up, is cleared when SLEEP is invoked. The TO

bit is cleared, if a WDT time-out occurred (and caused

wake-up).

19.3 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared, but

keeps running, the PD bit (RCON<3>) is cleared, the

TO (RCON<4>) bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, low or hi-impedance).

When the SLEEPinstruction is being executed, the next

instruction (PC + 2) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOPafter the SLEEPinstruction.

For lowest current consumption in this mode, place all

I/O pins at either VDD or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down

the A/D and disable external clocks. Pull all I/O pins

that are hi-impedance inputs, high or low externally, to

avoid switching currents caused by floating inputs. The

T0CKI input should also be at VDD or VSS for lowest

current consumption. The contribution from on-chip

pull-ups on PORTB should be considered.

The MCLR pin must be at a logic high level (VIHMC).

19.3.2

WAKE-UP USING INTERRUPTS

19.3.1

WAKE-UP FROM SLEEP

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

The device can wake-up from SLEEP through one of

the following events:

1. External RESET input on MCLR pin.

• If an interrupt condition (interrupt flag bit and inter-

rupt enable bits are set) occurs before the execu-

tion of a SLEEPinstruction, the SLEEPinstruction

will complete as a NOP. Therefore, the WDT and

WDT postscaler will not be cleared, the TO bit will

not be set and PD bits will not be cleared.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. Interrupt from INT pin, RB port change or a

Peripheral Interrupt.

The following peripheral interrupts can wake the device

from SLEEP:

• If the interrupt condition occurs during or after

the execution of a SLEEPinstruction, the device

will immediately wake-up from SLEEP. The

SLEEPinstruction will be completely executed

before the wake-up. Therefore, the WDT and

WDT postscaler will be cleared, the TO bit will be

set and the PD bit will be cleared.

1. PSP read or write.

2. TMR1 interrupt. Timer1 must be operating as

an asynchronous counter.

3. TMR3 interrupt. Timer3 must be operating as

an asynchronous counter.

4. CCP Capture mode interrupt.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

5. Special event trigger (Timer1 in Asynchronous

mode using an external clock).

6. MSSP (START/STOP) bit detect interrupt.

7. MSSP transmit or receive in Slave mode

(SPI/I²C).

8. USART RX or TX (Synchronous Slave mode).

9. A/D conversion (when A/D clock source is RC).

10. EEPROM write operation complete.

11. LVD interrupt.

To ensure that the WDT is cleared, a CLRWDTinstruction

should be executed before a SLEEPinstruction.

Other peripherals cannot generate interrupts, since

during SLEEP, no on-chip clocks are present.

DS39564C-page 205

PIC18FXX2

FIGURE 19-2:

WAKE-UP FROM SLEEP THROUGH INTERRUPT^(1,2)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKO⁽⁴⁾

INT pin

(2)

TOST

INTF flag

(INTCON<1>)

Interrupt Latency⁽³⁾

GIEH bit

Processor in

SLEEP

(INTCON<7>)

INSTRUCTION FLOW

PC

PC+2

PC+4

PC + 4

0008h

000Ah

Instruction

Fetched

Inst(0008h)

Inst(PC + 2)

Inst(PC + 4)

Inst(000Ah)

Inst(PC) = SLEEP

Instruction

Executed

Inst(PC + 2)

Dummy Cycle

Inst(0008h)

SLEEP

Inst(PC - 1)

Note 1: XT, HS or LP Oscillator mode assumed.

2: GIE = '1' assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Osc modes.

4: CLKO is not available in these Osc modes, but shown here for timing reference.

DS39564C-page 206

PIC18FXX2

Each of the five blocks has three code protection bits

associated with them. They are:

19.4 Program Verification and

Code Protection

• Code Protect bit (CPn)

The overall structure of the code protection on the

PIC18 FLASH devices differs significantly from other

PICmicro devices.

• Write Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 19-3 shows the program memory organization

for 16- and 32-Kbyte devices, and the specific code

protection bit associated with each block. The actual

locations of the bits are summarized in Table 19-3.

The user program memory is divided into five blocks.

One of these is a boot block of 512 bytes. The remain-

der of the memory is divided into four blocks on binary

boundaries.

FIGURE 19-3:

CODE PROTECTED PROGRAM MEMORY FOR PIC18F2XX/4XX

MEMORY SIZE/DEVICE

Block Code Protection

16 Kbytes

32 Kbytes

Address

Range

Controlled By:

CPB, WRTB, EBTRB

CP0, WRT0, EBTR0

(PIC18FX42)

(PIC18FX52)

000000h

0001FFh

Boot Block

Block 0

000200h

Block 0

Block 1

001FFFh

002000h

Block 1

Block 2

Block 3

CP1, WRT1, EBTR1

CP2, WRT2, EBTR2

CP3, WRT3, EBTR3

003FFFh

004000h

Unimplemented

Read 0’s

005FFFh

006000h

Unimplemented

Read 0’s

007FFFh

008000h

Unimplemented

Read 0’s

Unimplemented

Read 0’s

(Unimplemented Memory Space)

1FFFFFh

TABLE 19-3: SUMMARY OF CODE PROTECTION REGISTERS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300008h

CONFIG5L

CONFIG5H

CONFIG6L

—

CPD

—

CPB

—

CP3

—

CP2

—

CP1

—

CP0

—

300009h

30000Ah

30000Bh

30000Ch

30000Dh

—

WRT3

—

WRT2

—

WRT1

—

WRT0

—

CONFIG6H WRTD

WRTB

—

WRTC

—

CONFIG7L

CONFIG7H

—

EBTR3

—

EBTR2

—

EBTR1

—

EBTR0

—

EBTRB

—

Legend: Shaded cells are unimplemented.

DS39564C-page 207

PIC18FXX2

outside of that block is not allowed to read, and will

result in reading ‘0’s. Figures 19-4 through 19-6

illustrate Table Write and Table Read protection.

19.4.1

PROGRAM MEMORY

CODE PROTECTION

The user memory may be read to or written from any

location using the Table Read and Table Write instruc-

tions. The device ID may be read with Table Reads.

The configuration registers may be read and written

with the Table Read and Table Write instructions.

Note: Code protection bits may only be written to

a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ state. Code pro-

tection bits are only set to ‘1’ by a full chip

erase or block erase function. The full chip

erase and block erase functions can only

be initiated via ICSP or an external

programmer.

In User mode, the CPn bits have no direct effect. CPn

bits inhibit external reads and writes. A block of user

memory may be protected from Table Writes if the

WRTn configuration bit is ‘0’. The EBTRn bits control

Table Reads. For a block of user memory with the

EBTRn bit set to ‘0’, a Table Read instruction that

executes from within that block is allowed to read. A

Table Read instruction that executes from a location

FIGURE 19-4:

TABLE WRITE (WRTn) DISALLOWED

Program Memory

Register Values

Configuration Bit Settings

000000h

WRTB,EBTRB = 11

0001FFh

000200h

TBLPTR = 000FFF

PC = 001FFE

WRT0,EBTR0 = 01

TBLWT *

001FFFh

002000h

WRT1,EBTR1 = 11

WRT2,EBTR2 = 11

WRT3,EBTR3 = 11

003FFFh

004000h

PC = 004FFE

005FFFh

006000h

007FFFh

Results: All Table Writes disabled to Blockn whenever WRTn = ‘0’.

DS39564C-page 208

PIC18FXX2

FIGURE 19-5:

EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED

Register Values

Program Memory

Configuration Bit Settings

000000h

WRTB,EBTRB = 11

0001FFh

000200h

TBLPTR = 000FFF

PC = 002FFE

WRT0,EBTR0 = 10

001FFFh

002000h

TBLRD *

WRT1,EBTR1 = 11

WRT2,EBTR2 = 11

003FFFh

004000h

005FFFh

006000h

WRT3,EBTR3 = 11

007FFFh

Results: All Table Reads from external blocks to Blockn are disabled whenever EBTRn = ‘0’.

TABLAT register returns a value of “0”.

FIGURE 19-6:

EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED

Register Values

Program Memory

Configuration Bit Settings

000000h

WRTB,EBTRB = 11

0001FFh

000200h

TBLPTR = 000FFF

PC = 001FFE

WRT0,EBTR0 = 10

TBLRD *

001FFFh

002000h

WRT1,EBTR1 = 11

WRT2,EBTR2 = 11

WRT3,EBTR3 = 11

003FFFh

004000h

005FFFh

006000h

007FFFh

Results: Table Reads permitted within Blockn, even when EBTRBn = ‘0’.

TABLAT register returns the value of the data at the location TBLPTR.

DS39564C-page 209

PIC18FXX2

To use the In-Circuit Debugger function of the micro-

controller, the design must implement In-Circuit Serial

Programming connections to MCLR/VPP, VDD, GND,

RB7 and RB6. This will interface to the In-Circuit

Debugger module available from Microchip or one of

the third party development tool companies.

19.4.2

DATA EEPROM

CODE PROTECTION

The entire Data EEPROM is protected from external

reads and writes by two bits: CPD and WRTD. CPD

inhibits external reads and writes of Data EEPROM.

WRTD inhibits external writes to Data EEPROM. The

CPU can continue to read and write Data EEPROM

regardless of the protection bit settings.

19.8 Low Voltage ICSP Programming

The LVP bit configuration register CONFIG4L enables

low voltage ICSP programming. This mode allows the

microcontroller to be programmed via ICSP using a

VDD source in the operating voltage range. This only

means that VPP does not have to be brought to VIHH,

but can instead be left at the normal operating voltage.

In this mode, the RB5/PGM pin is dedicated to the pro-

gramming function and ceases to be a general purpose

I/O pin. During programming, VDD is applied to the

MCLR/VPP pin. To enter Programming mode, VDD must

be applied to the RB5/PGM, provided the LVP bit is set.

The LVP bit defaults to a (‘1’) from the factory.

19.4.3

CONFIGURATION REGISTER

PROTECTION

The configuration registers can be write protected. The

WRTC bit controls protection of the configuration regis-

ters. In User mode, the WRTC bit is readable only. WRTC

can only be written via ICSP or an external programmer.

19.5 ID Locations

Eight memory locations (200000h - 200007h) are des-

ignated as ID locations, where the user can store

checksum or other code identification numbers. These

locations are accessible during normal execution

through the TBLRD and TBLWTinstructions, or during

program/verify. The ID locations can be read when the

device is code protected.

Note 1: The High Voltage Programming mode is

always available, regardless of the state

of the LVP bit, by applying VIHH to the

MCLR pin.

2: While in low voltage ICSP mode, the RB5

pin can no longer be used as a general

purpose I/O pin, and should be held low

during normal operation to protect

against inadvertent ICSP mode entry.

The sequence for programming the ID locations is sim-

ilar to programming the FLASH memory (see

Section 5.5.1).

19.6

In-Circuit Serial Programming

3: When using low voltage ICSP program-

ming (LVP), the pull-up on RB5 becomes

disabled. If TRISB bit 5 is cleared,

thereby setting RB5 as an output, LATB

bit 5 must also be cleared for proper

operation.

PIC18FXXX microcontrollers can be serially pro-

grammed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

If Low Voltage Programming mode is not used, the LVP

bit can be programmed to a '0' and RB5/PGM becomes

a digital I/O pin. However, the LVP bit may only be pro-

grammed when programming is entered with VIHH on

MCLR/VPP.

19.7 In-Circuit Debugger

It should be noted that once the LVP bit is programmed

to 0, only the High Voltage Programming mode is avail-

able and only High Voltage Programming mode can be

used to program the device.

When the DEBUG bit in configuration register

CONFIG4L is programmed to a '0', the In-Circuit

Debugger functionality is enabled. This function allows

simple debugging functions when used with MPLAB^®

IDE. When the microcontroller has this feature

enabled, some of the resources are not available for

general use. Table 19-4 shows which features are

consumed by the background debugger.

When using low voltage ICSP, the part must be sup-

plied 4.5V to 5.5V, if a bulk erase will be executed. This

includes reprogramming of the code protect bits from

an on-state to off-state. For all other cases of low volt-

age ICSP, the part may be programmed at the normal

operating voltage. This means unique user IDs, or user

code can be reprogrammed or added.

TABLE 19-4: DEBUGGER RESOURCES

I/O pins

RB6, RB7

Stack

2 levels

512 bytes

10 bytes

Program Memory

Data Memory

DS39564C-page 210

PIC18FXX2

The literal instructions may use some of the following

operands:

20.0 INSTRUCTION SET SUMMARY

The PIC18FXXX instruction set adds many enhance-

ments to the previous PICmicro instruction sets, while

maintaining an easy migration from these PICmicro

instruction sets.

• A literal value to be loaded into a file register

(specified by ‘k’)

• The desired FSR register to load the literal value

into (specified by ‘f’)

Most instructions are a single program memory word

(16-bits), but there are three instructions that require

two program memory locations.

• No operand required

(specified by ‘—’)

The control instructions may use some of the following

operands:

Each single word instruction is a 16-bit word divided

into an OPCODE, which specifies the instruction type

and one or more operands, which further specify the

operation of the instruction.

• A program memory address (specified by ‘n’)

• The mode of the Call or Return instructions

(specified by ‘s’)

The instruction set is highly orthogonal and is grouped

into four basic categories:

• The mode of the Table Read and Table Write

instructions (specified by ‘m’)

• Byte-oriented operations

• Bit-oriented operations

• Literal operations

• No operand required

(specified by ‘—’)

All instructions are a single word, except for three dou-

ble-word instructions. These three instructions were

made double-word instructions so that all the required

information is available in these 32 bits. In the second

word, the 4-MSbs are 1’s. If this second word is exe-

cuted as an instruction (by itself), it will execute as a

NOP.

• Control operations

The PIC18FXXX instruction set summary in Table 20-2

lists byte-oriented, bit-oriented, literal and control

operations. Table 20-1 shows the opcode field

descriptions.

Most byte-oriented instructions have three operands:

All single word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles with the additional instruction cycle(s) executed

as a NOP.

1. The file register (specified by ‘f’)

2. The destination of the result

(specified by ‘d’)

3. The accessed memory

(specified by ‘a’)

The file register designator 'f' specifies which file

register is to be used by the instruction.

The double-word instructions execute in two instruction

cycles.

The destination designator ‘d’ specifies where the

result of the operation is to be placed. If 'd' is zero, the

result is placed in the WREG register. If 'd' is one, the

result is placed in the file register specified in the

instruction.

One instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1 μs. If a conditional test is

true or the program counter is changed as a result of an

instruction, the instruction execution time is 2 μs.

Two-word branch instructions (if true) would take 3 μs.

All bit-oriented instructions have three operands:

1. The file register (specified by ‘f’)

Figure 20-1 shows the general formats that the

instructions can have.

2. The bit in the file register

(specified by ‘b’)

All examples use the format ‘nnh’ to represent a

3. The accessed memory

(specified by ‘a’)

hexadecimal number, where ‘h’ signifies

hexadecimal digit.

a

The bit field designator 'b' selects the number of the bit

affected by the operation, while the file register desig-

nator 'f' represents the number of the file in which the

bit is located.

The Instruction Set Summary, shown in Table 20-2,

lists the instructions recognized by the Microchip

Assembler (MPASM^TM).

Section 20.1 provides a description of each instruction.

DS39564C-page 211

PIC18FXX2

TABLE 20-1: OPCODE FIELD DESCRIPTIONS

Field

Description

a

RAM access bit

a = 0: RAM location in Access RAM (BSR register is ignored)

a = 1: RAM bank is specified by BSR register

bbb

BSR

d

Bit address within an 8-bit file register (0 to 7)

Bank Select Register. Used to select the current RAM bank.

Destination select bit;

d = 0: store result in WREG,

d = 1: store result in file register f.

dest

f

Destination either the WREG register or the specified register file location

8-bit Register file address (0x00 to 0xFF)

fs

12-bit Register file address (0x000 to 0xFFF). This is the source address.

12-bit Register file address (0x000 to 0xFFF). This is the destination address.

Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)

Label name

fd

k

label

mm

The mode of the TBLPTR register for the Table Read and Table Write instructions.

Only used with Table Read and Table Write instructions:

*

No Change to register (such as TBLPTR with Table reads and writes)

Post-Increment register (such as TBLPTR with Table reads and writes)

Post-Decrement register (such as TBLPTR with Table reads and writes)

Pre-Increment register (such as TBLPTR with Table reads and writes)

*+

*-

+*

n

The relative address (2’s complement number) for relative branch instructions, or the direct address for

Call/Branch and Return instructions

PRODH

PRODL

s

Product of Multiply high byte

Product of Multiply low byte

Fast Call/Return mode select bit.

s = 0: do not update into/from shadow registers

s = 1: certain registers loaded into/from shadow registers (Fast mode)

u

Unused or Unchanged

WREG

x

Working register (accumulator)

Don't care (0 or 1)

The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all

Microchip software tools.

TBLPTR

TABLAT

TOS

21-bit Table Pointer (points to a Program Memory location)

8-bit Table Latch

Top-of-Stack

PC

Program Counter

PCL

Program Counter Low Byte

Program Counter High Byte

Program Counter High Byte Latch

Program Counter Upper Byte Latch

Global Interrupt Enable bit

Watchdog Timer

PCH

PCLATH

PCLATU

GIE

WDT

TO

Time-out bit

PD

Power-down bit

C, DC, Z, OV, N ALU status bits Carry, Digit Carry, Zero, Overflow, Negative

[

]

)

Optional

(

Contents

→

< >

∈

Assigned to

Register bit field

In the set of

italics

User defined term (font is courier)

DS39564C-page 212

PIC18FXX2

FIGURE 20-1:

GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

Example Instruction

15

10

OPCODE

9

8

7

0

d

a

f (FILE #)

ADDWF MYREG, W, B

d = 0 for result destination to be WREG register

d = 1 for result destination to be file register (f)

a = 0 to force Access Bank

a = 1 for BSR to select bank

f = 8-bit file register address

Byte to Byte move operations (2-word)

15

12 11

0

OPCODE

f (Source FILE #)

MOVFF MYREG1, MYREG2

15

12 11

1111

f (Destination FILE #)

f = 12-bit file register address

Bit-oriented file register operations

15 12 11 9 8

OPCODE b (BIT #)

7

0

BSF MYREG, bit, B

a

f (FILE #)

b = 3-bit position of bit in file register (f)

a = 0 to force Access Bank

a = 1 for BSR to select bank

f = 8-bit file register address

Literal operations

15

8

7

0

MOVLW 0x7F

OPCODE

k (literal)

k = 8-bit immediate value

Control operations

CALL, GOTO and Branch operations

15

8 7

0

GOTO Label

OPCODE

12 11

n<7:0> (literal)

15

0

1111

n<19:8> (literal)

n = 20-bit immediate value

15

8

7

0

CALL MYFUNC

OPCODE

12 11

n<7:0> (literal)

S

0

n<19:8> (literal)

S = Fast bit

11 10

15

0

BRA MYFUNC

BC MYFUNC

OPCODE

n<10:0> (literal)

15

OPCODE

8 7

n<7:0> (literal)

DS39564C-page 213

PIC18FXX2

TABLE 20-2: PIC18FXXX INSTRUCTION SET

16-Bit Instruction Word

MSb LSb

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ADDWFC

ANDWF

CLRF

f, d, a Add WREG and f

f, d, a Add WREG and Carry bit to f

f, d, a AND WREG with f

1

0010 01da0 ffff

0010 0da

ffff C, DC, Z, OV, N 1, 2

ffff

0001 01da

0110 101a

0001 11da

ffff Z, N

ffff

1,2

2

f, a

Clear f

Z

COMF

f, d, a Complement f

ffff Z, N

ffff None

1, 2

4

CPFSEQ

CPFSGT

CPFSLT

DECF

DECFSZ

DCFSNZ

INCF

INCFSZ

INFSNZ

IORWF

MOVF

f, a

Compare f with WREG, skip =

Compare f with WREG, skip >

Compare f with WREG, skip <

1 (2 or 3) 0110 001a

1 (2 or 3) 0110 010a

1 (2 or 3) 0110 000a

1, 2

f, d, a Decrement f

1

0000 01da

ffff C, DC, Z, OV, N 1, 2, 3, 4

f, d, a Decrement f, Skip if 0

f, d, a Decrement f, Skip if Not 0

f, d, a Increment f

f, d, a Increment f, Skip if 0

f, d, a Increment f, Skip if Not 0

f, d, a Inclusive OR WREG with f

f, d, a Move f

1 (2 or 3) 0010 11da

1 (2 or 3) 0100 11da

1

1 (2 or 3) 0011 11da

1 (2 or 3) 0100 10da

1

2

ffff None

1, 2, 3, 4

1, 2

0010 10da

ffff C, DC, Z, OV, N 1, 2, 3, 4

ffff None

ffff Z, N

ffff None

ffff

4

1, 2

1

0001 00da

0101 00da

1100 ffff

1111 ffff

0110 111a

0000 001a

0110 110a

0011 01da

0100 01da

0011 00da

0100 00da

0110 100a

0101 01da

MOVFF

f , f

Move f (source) to 1st word

s

d

s

f (destination) 2nd word

d

MOVWF

MULWF

NEGF

RLCF

RLNCF

RRCF

RRNCF

SETF

SUBFWB

f, a

Move WREG to f

Multiply WREG with f

Negate f

1

ffff None

ffff C, DC, Z, OV, N 1, 2

ffff C, Z, N

f, d, a Rotate Left f through Carry

f, d, a Rotate Left f (No Carry)

f, d, a Rotate Right f through Carry

f, d, a Rotate Right f (No Carry)

ffff Z, N

ffff C, Z, N

ffff Z, N

ffff None

1, 2

f, a

Set f

f, d, a Subtract f from WREG with

borrow

ffff C, DC, Z, OV, N 1, 2

SUBWF

SUBWFB

f, d, a Subtract WREG from f

f, d, a Subtract WREG from f with

borrow

1

0101 11da

0101 10da

ffff

ffff C, DC, Z, OV, N

ffff C, DC, Z, OV, N 1, 2

SWAPF

TSTFSZ

XORWF

f, d, a Swap nibbles in f

1

0011 10da

ffff

ffff None

ffff Z, N

4

1, 2

f, a

Test f, skip if 0

1 (2 or 3) 0110 011a

1

f, d, a Exclusive OR WREG with f

0001 10da

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

BTG

f, b, a Bit Clear f

f, b, a Bit Set f

f, b, a Bit Test f, Skip if Clear

f, b, a Bit Test f, Skip if Set

f, d, a Bit Toggle f

1

1001 bbba

1000 bbba

ffff

ffff None

1, 2

3, 4

1, 2

1 (2 or 3) 1011 bbba

1 (2 or 3) 1010 bbba

1

0111 bbba

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an

external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the

first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory

locations have a valid instruction.

5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.

DS39564C-page 214

PIC18FXX2

TABLE 20-2: PIC18FXXX INSTRUCTION SET (CONTINUED)

16-Bit Instruction Word

Mnemonic,

Operands

Status

Notes

Description

Cycles

Affected

MSb

LSb

CONTROL OPERATIONS

BC

BN

n

Branch if Carry

1 (2)

1110 0010

1110 0110

1110 0011

1110 0111

1110 0101

1110 0001

1110 0100

1101 0nnn

1110 0000

1110 110s

1111 kkkk

0000 0000

1110 1111

1111 kkkk

0000 0000

1111 xxxx

0000 0000

1101 1nnn

0000 0000

nnnn

kkkk

0000

kkkk

0000

xxxx

0000

nnnn

1111

0001

nnnn None

kkkk None

kkkk

Branch if Negative

Branch if Not Carry

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

Branch if Overflow

Branch Unconditionally

Branch if Zero

Call subroutine1st word

2nd word

Clear Watchdog Timer

Decimal Adjust WREG

Go to address1st word

2nd word

1 (2)

2

1 (2)

2

BNC

BNN

BNOV

BNZ

BOV

BRA

BZ

n

n, s

CALL

CLRWDT

DAW

GOTO

—

n

1

2

0100 TO, PD

0111

C

kkkk None

kkkk

NOP

POP

PUSH

RCALL

RESET

RETFIE

—

n

No Operation

1

2

1

2

0000 None

xxxx None

0110 None

0101 None

nnnn None

1111 All

4

Pop top of return stack (TOS)

Push top of return stack (TOS)

Relative Call

Software device RESET

Return from interrupt enable

s

000s GIE/GIEH,

PEIE/GIEL

RETLW

RETURN

SLEEP

k

s

—

Return with literal in WREG

Return from Subroutine

Go into Standby mode

2

1

0000 1100

0000 0000

kkkk

0001

0000

kkkk None

001s None

0011 TO, PD

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an

external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the

first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory

locations have a valid instruction.

5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.

DS39564C-page 215

PIC18FXX2

TABLE 20-2: PIC18FXXX INSTRUCTION SET (CONTINUED)

16-Bit Instruction Word

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

LFSR

k

f, k

Add literal and WREG

AND literal with WREG

1

2

0000 1111 kkkk

0000 1011 kkkk

0000 1001 kkkk

1110 1110 00ff

1111 0000 kkkk

0000 0001 0000

0000 1110 kkkk

0000 1101 kkkk

0000 1100 kkkk

0000 1000 kkkk

0000 1010 kkkk

kkkk C, DC, Z, OV, N

kkkk Z, N

kkkk None

kkkk

kkkk None

kkkk C, DC, Z, OV, N

kkkk Z, N

Inclusive OR literal with WREG

Move literal (12-bit) 2nd word

to FSRx 1st word

Move literal to BSR<3:0>

Move literal to WREG

Multiply literal with WREG

Return with literal in WREG

Subtract WREG from literal

Exclusive OR literal with WREG

MOVLB

MOVLW

MULLW

RETLW

SUBLW

XORLW

k

1

2

1

DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS

TBLRD*

Table Read

2

0000 0000 0000

1000 None

1001 None

1010 None

1011 None

1100 None

1101 None

1110 None

1111 None

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

Table Read with post-increment

Table Read with post-decrement

Table Read with pre-increment

Table Write

Table Write with post-increment

Table Write with post-decrement

Table Write with pre-increment

2 (5)

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an

external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the

first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory

locations have a valid instruction.

5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.

DS39564C-page 216

PIC18FXX2

20.1 Instruction Set

ADDLW

ADD literal to W

ADDWF

ADD W to f

Syntax:

[ label ] ADDLW

0 ≤ k ≤ 255

k

Syntax:

[ label ] ADDWF

f [,d [,a]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(W) + k → W

N, OV, C, DC, Z

Operation:

(W) + (f) → dest

0000

1111

kkkk

Status Affected:

Encoding:

N, OV, C, DC, Z

Description:

The contents of W are added to the

8-bit literal 'k' and the result is

placed in W.

0010

01da

ffff

Description:

Add W to register 'f'. If 'd' is 0, the

result is stored in W. If 'd' is 1, the

result is stored back in register 'f'

(default). If ‘a’ is 0, the Access

Bank will be selected. If ‘a’ is 1, the

BSR is used.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal 'k'

Process

Data

Write to W

Words:

Cycles:

1

Q Cycle Activity:

Q1

ADDLW

0x15

Example:

Q2

Read

register 'f'

Q3

Process

Data

Q4

Write to

destination

Before Instruction

Decode

W

=

0x10

After Instruction

W

=

0x25

ADDWF

REG, 0, 0

Example:

Before Instruction

W

REG

=

0x17

0xC2

After Instruction

W

REG

=

0xD9

0xC2

DS39564C-page 217

PIC18FXX2

ADDWFC

ADD W and Carry bit to f

ANDLW

AND literal with W

Syntax:

[ label ] ADDWFC

f [,d [,a]

Syntax:

[ label ] ANDLW

0 ≤ k ≤ 255

(W) .AND. k → W

N,Z

k

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

Operation:

Status Affected:

Encoding:

Operation:

(W) + (f) + (C) → dest

0000

1011

kkkk

Status Affected:

Encoding:

N,OV, C, DC, Z

Description:

The contents of W are ANDed with

the 8-bit literal 'k'. The result is

placed in W.

0010

00da

ffff

Description:

Add W, the Carry Flag and data

memory location 'f'. If 'd' is 0, the

result is placed in W. If 'd' is 1, the

result is placed in data memory loca-

tion 'f'. If ‘a’ is 0, the Access Bank

will be selected. If ‘a’ is 1, the BSR

will not be overridden.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write to W

Decode

Read literal

'k'

Process

Data

Words:

Cycles:

1

ANDLW

0x5F

Example:

Q Cycle Activity:

Q1

Before Instruction

Q2

Q3

Q4

W

=

0xA3

0x03

Decode

Read

register 'f'

Process

Data

Write to

destination

After Instruction

W

=

ADDWFC

REG, 0, 1

Example:

Before Instruction

Carry bit =

1

REG

W

=

0x02

0x4D

After Instruction

Carry bit =

0

REG

W

=

0x02

0x50

DS39564C-page 218

PIC18FXX2

ANDWF

AND W with f

BC

Branch if Carry

[ label ] BC

Syntax:

[ label ] ANDWF

f [,d [,a]

Syntax:

n

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

Operation:

-128 ≤ n ≤ 127

if carry bit is ’1’

(PC) + 2 + 2n → PC

Operation:

(W) .AND. (f) → dest

Status Affected:

Encoding:

None

Status Affected:

Encoding:

N,Z

1110

0010

nnnn

0001

01da

ffff

Description:

If the Carry bit is ’1’, then the

program will branch.

Description:

The contents of W are AND’ed with

register 'f'. If 'd' is 0, the result is

stored in W. If 'd' is 1, the result is

stored back in register 'f' (default). If

‘a’ is 0, the Access Bank will be

selected. If ‘a’ is 1, the BSR will not

be overridden (default).

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

Q1

Q Cycle Activity:

If Jump:

Q2

Q3

Q4

Q1

Decode

Q2

Read literal

'n'

Q3

Process

Data

Q4

Write to PC

Decode

Read

register 'f'

Process

Data

Write to

destination

No

operation

No

operation

No

operation

No

operation

ANDWF

REG, 0, 0

Example:

Before Instruction

If No Jump:

Q1

W

REG

=

0x17

0xC2

Q2

Q3

Q4

Decode

Read literal

'n'

Process

Data

No

operation

After Instruction

W

=

0x02

0xC2

REG

HERE

BC

5

Example:

Before Instruction

PC

=

address (HERE)

After Instruction

If Carry

=

1;

PC

address (HERE+12)

0;

If Carry

PC

address (HERE+2)

DS39564C-page 219

PIC18FXX2

BCF

Bit Clear f

BN

Branch if Negative

[ label ] BN

Syntax:

[ label ] BCF f,b[,a]

Syntax:

n

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operands:

Operation:

-128 ≤ n ≤ 127

if negative bit is ’1’

(PC) + 2 + 2n → PC

Operation:

0 → f

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0110

nnnn

1001

bbba

ffff

Description:

If the Negative bit is ’1’, then the

program will branch.

Description:

Bit 'b' in register 'f' is cleared. If ‘a’

is 0, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

Q1

Q Cycle Activity:

If Jump:

Q2

Read

register 'f'

Q3

Process

Data

Q4

Write

Decode

Q1

Q2

Q3

Q4

register 'f'

Decode

Read literal

'n'

Process

Data

Write to PC

BCF

FLAG_REG, 7, 0

Example:

No

operation

No

operation

No

operation

No

operation

Before Instruction

FLAG_REG = 0xC7

If No Jump:

Q1

After Instruction

Q2

Q3

Q4

FLAG_REG = 0x47

Decode

Read literal

'n'

Process

Data

No

operation

HERE

BN Jump

Example:

Before Instruction

PC

=

address (HERE)

After Instruction

If Negative

=

1;

PC

address (Jump)

If Negative

PC

0;

address (HERE+2)

DS39564C-page 220

PIC18FXX2

BNC

Branch if Not Carry

BNN

Branch if Not Negative

Syntax:

[ label ] BNC

-128 ≤ n ≤ 127

if carry bit is ’0’

n

Syntax:

[ label ] BNN

n

Operands:

Operation:

Operands:

Operation:

-128 ≤ n ≤ 127

if negative bit is ’0’

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0011

nnnn

1110

0111

nnnn

Description:

If the Carry bit is ’0’, then the

program will branch.

Description:

If the Negative bit is ’0’, then the

program will branch.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Decode

Read literal

'n'

Process

Data

Write to PC

Decode

Read literal

'n'

Process

Data

Write to PC

No

operation

If No Jump:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

'n'

Process

Data

No

operation

Decode

Read literal

'n'

Process

Data

No

operation

HERE

BNC Jump

HERE

BNN Jump

Example:

Before Instruction

PC

=

address (HERE)

PC

=

address (HERE)

After Instruction

If Carry

=

0;

If Negative

=

0;

PC

address (Jump)

PC

address (Jump)

If Carry

PC

1;

If Negative

PC

1;

address (HERE+2)

DS39564C-page 221

PIC18FXX2

BNOV

Branch if Not Overflow

BNZ

Branch if Not Zero

Syntax:

[ label ] BNOV

n

Syntax:

[ label ] BNZ

-128 ≤ n ≤ 127

if zero bit is ’0’

n

Operands:

Operation:

-128 ≤ n ≤ 127

Operands:

Operation:

if overflow bit is ’0’

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0101

nnnn

1110

0001

nnnn

Description:

If the Overflow bit is ’0’, then the

program will branch.

Description:

If the Zero bit is ’0’, then the pro-

gram will branch.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Decode

Read literal

'n'

Process

Data

Write to PC

Decode

Read literal

'n'

Process

Data

Write to PC

No

operation

If No Jump:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

'n'

Process

Data

No

operation

Decode

Read literal

'n'

Process

Data

No

operation

HERE

BNOV Jump

HERE

BNZ Jump

Example:

Before Instruction

PC

=

address (HERE)

PC

=

address (HERE)

After Instruction

If Overflow

=

0;

If Zero

=

0;

PC

address (Jump)

PC

address (Jump)

If Overflow

PC

1;

If Zero

PC

1;

address (HERE+2)

DS39564C-page 222

PIC18FXX2

BRA

Unconditional Branch

[ label ] BRA

BSF

Bit Set f

Syntax:

n

Syntax:

[ label ] BSF f,b[,a]

Operands:

Operation:

Status Affected:

Encoding:

-1024 ≤ n ≤ 1023

(PC) + 2 + 2n → PC

None

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation:

1 → f

1101

0nnn

nnnn

Status Affected:

Encoding:

None

Description:

Add the 2’s complement number

’2n’ to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is a

two-cycle instruction.

1000

bbba

ffff

Description:

Bit 'b' in register 'f' is set. If ‘a’ is 0

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value.

Words:

Cycles:

1

2

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write to PC

Q2

Read

register 'f'

Q3

Process

Data

Q4

Write

Decode

Read literal

'n'

Process

Data

Decode

register 'f'

No

operation

BSF

FLAG_REG, 7, 1

Example:

Before Instruction

HERE

BRA Jump

Example:

FLAG_REG

=

0x0A

0x8A

Before Instruction

After Instruction

FLAG_REG

PC

=

address (HERE)

address (Jump)

After Instruction

PC

DS39564C-page 223

PIC18FXX2

BTFSC

Bit Test File, Skip if Clear

BTFSS

Bit Test File, Skip if Set

Syntax:

[ label ] BTFSC f,b[,a]

Syntax:

[ label ] BTFSS f,b[,a]

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation:

skip if (f) = 0

None

Operation:

skip if (f) = 1

None

Status Affected:

Encoding:

Status Affected:

Encoding:

1011

bbba

ffff

1010

bbba

ffff

Description:

If bit 'b' in register ’f' is 0, then the

next instruction is skipped.

Description:

If bit 'b' in register 'f' is 1, then the

next instruction is skipped.

If bit 'b' is 0, then the next instruction

fetched during the current instruction

execution is discarded, and a NOPis

executed instead, making this a two-

cycle instruction. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

If bit 'b' is 1, then the next instruction

fetched during the current instruc-

tion execution, is discarded and a

NOPis executed instead, making this

a two-cycle instruction. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

Process Data

No

Decode

Read

Process Data

No

register 'f'

operation

register 'f'

operation

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

HERE

FALSE

TRUE

BTFSC

:

FLAG, 1, 0

Example:

HERE

FALSE

TRUE

BTFSS

:

FLAG, 1, 0

Example:

Before Instruction

PC

Before Instruction

PC

=

address (HERE)

=

address (HERE)

After Instruction

If FLAG<1>

=

0;

If FLAG<1>

=

0;

PC

address (TRUE)

1;

PC

address (FALSE)

1;

If FLAG<1>

PC

If FLAG<1>

PC

address (FALSE)

address (TRUE)

DS39564C-page 224

PIC18FXX2

BTG

Bit Toggle f

BOV

Branch if Overflow

Syntax:

[ label ] BTG f,b[,a]

Syntax:

[ label ] BOV

n

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operands:

Operation:

-128 ≤ n ≤ 127

if overflow bit is ’1’

(PC) + 2 + 2n → PC

Operation:

(f) → f

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0100

nnnn

0111

bbba

ffff

Description:

If the Overflow bit is ’1’, then the

program will branch.

Description:

Bit 'b' in data memory location 'f' is

inverted. If ‘a’ is 0, the Access Bank

will be selected, overriding the BSR

value. If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

Q1

Q Cycle Activity:

If Jump:

Q2

Read

register 'f'

Q3

Process

Data

Q4

Write

Decode

Q1

Q2

Q3

Q4

register 'f'

Decode

Read literal

'n'

Process

Data

Write to PC

BTG

PORTC, 4, 0

Example:

No

operation

No

operation

No

operation

No

operation

Before Instruction:

PORTC

=

0111 0101 [0x75]

If No Jump:

Q1

After Instruction:

Q2

Q3

Q4

PORTC

=

0110 0101 [0x65]

Decode

Read literal

'n'

Process

Data

No

operation

HERE

BOV Jump

Example:

Before Instruction

PC

=

address (HERE)

After Instruction

If Overflow

=

1;

PC

address (Jump)

If Overflow

PC

0;

address (HERE+2)

DS39564C-page 225

PIC18FXX2

BZ

Branch if Zero

[ label ] BZ

CALL

Subroutine Call

Syntax:

n

Syntax:

[ label ] CALL k [,s]

Operands:

Operation:

-128 ≤ n ≤ 127

Operands:

0 ≤ k ≤ 1048575

s ∈ [0,1]

if Zero bit is ’1’

(PC) + 2 + 2n → PC

Operation:

(PC) + 4 → TOS,

k → PC<20:1>,

if s = 1

Status Affected:

Encoding:

None

1110

0000

nnnn

(W) → WS,

(STATUS) → STATUSS,

(BSR) → BSRS

Description:

If the Zero bit is ’1’, then the pro-

gram will branch.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Status Affected:

None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

1110

1111

110s

k kkk

kkkk

7

0

8

k

kkk kkkk

19

Description:

Subroutine call of entire 2 Mbyte

memory range. First, return

address (PC+ 4) is pushed onto the

return stack. If ’s’ = 1, the W,

Words:

Cycles:

1

1(2)

STATUS and BSR registers are

also pushed into their respective

shadow registers, WS, STATUSS

and BSRS. If 's' = 0, no update

occurs (default). Then, the 20-bit

value ’k’ is loaded into PC<20:1>.

CALLis a two-cycle instruction.

Q Cycle Activity:

If Jump:

Q1

Decode

Q2

Read literal

'n'

Q3

Process

Data

Q4

Write to PC

No

operation

No

operation

No

operation

No

operation

Words:

Cycles:

2

If No Jump:

Q1

Q2

Q3

Q4

Decode

Read literal

'n'

Process

Data

No

operation

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal Push PC to Read literal

HERE

BZ Jump

Example:

'k'<7:0>,

stack

’k’<19:8>,

Write to PC

Before Instruction

No

operation

No

operation

No

operation

No

operation

PC

=

address (HERE)

After Instruction

If Zero

=

1;

PC

address (Jump)

HERE

CALL THERE,1

Example:

If Zero

PC

0;

address (HERE+2)

Before Instruction

PC

=

address (HERE)

After Instruction

PC

=

address (THERE)

TOS

WS

address (HERE + 4)

W

BSRS

BSR

STATUSS=

STATUS

DS39564C-page 226

PIC18FXX2

CLRF

Clear f

CLRWDT

Clear Watchdog Timer

Syntax:

[ label ] CLRF f [,a]

Syntax:

[ label ] CLRWDT

None

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

Operation:

000h → WDT,

000h → WDT postscaler,

1 → TO,

Operation:

000h → f

1 → Z

1 → PD

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

TO, PD

0110

101a

ffff

0000

0100

Description:

Clears the contents of the specified

register. If ‘a’ is 0, the Access Bank

will be selected, overriding the BSR

value. If ‘a’ = 1, then the bank will

be selected as per the BSR value

(default).

Description:

CLRWDTinstruction resets the

Watchdog Timer. It also resets the

postscaler of the WDT. Status bits

TO and PD are set.

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

No

operation

Q2

Q3

Q4

Write

register 'f'

Decode

No

operation

Process

Data

Decode

Read

register 'f'

Process

Data

CLRWDT

Example:

CLRF

FLAG_REG,1

Example:

Before Instruction

WDT Counter

=

?

Before Instruction

FLAG_REG

=

0x5A

0x00

After Instruction

WDT Counter

WDT Postscaler

TO

=

0x00

After Instruction

FLAG_REG

0

1

PD

DS39564C-page 227

PIC18FXX2

COMF

Complement f

CPFSEQ

Compare f with W, skip if f = W

Syntax:

[ label ] COMF f [,d [,a]

Syntax:

[ label ] CPFSEQ f [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

(f) – (W),

Operation:

(f) → dest

skip if (f) = (W)

(unsigned comparison)

Status Affected:

Encoding:

N, Z

Status Affected:

Encoding:

None

0001

11da

ffff

0110

001a

ffff

Description:

The contents of register 'f' are com-

plemented. If 'd' is 0, the result is

stored in W. If 'd' is 1, the result is

stored back in register 'f' (default). If

‘a’ is 0, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

Description:

Compares the contents of data

memory location 'f' to the contents

of W by performing an unsigned

subtraction.

If 'f' = W, then the fetched instruc-

tion is discarded and a NOPis exe-

cuted instead, making this a two-

cycle instruction. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Read

register 'f'

Q3

Q4

Write to

Words:

Cycles:

1

Decode

Process

Data

1(2)

destination

Note: 3 cycles if skip and followed

by a 2-word instruction.

COMF

REG, 0, 0

Example:

Before Instruction

Q Cycle Activity:

Q1

REG

=

0x13

Q2

Q3

Q4

After Instruction

Decode

Read

register 'f'

Process

Data

No

operation

REG

=

0x13

W

=

0xEC

If skip:

Q1

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No

operation

No

operation

HERE

NEQUAL

EQUAL

CPFSEQ REG, 0

:

Example:

Before Instruction

PC Address

=

HERE

W

REG

=

?

After Instruction

If REG

PC

=

W;

Address (EQUAL)

If REG

PC

≠

=

W;

Address (NEQUAL)

DS39564C-page 228

PIC18FXX2

CPFSGT

Compare f with W, skip if f > W

CPFSLT

Compare f with W, skip if f < W

Syntax:

[ label ] CPFSGT f [,a]

Syntax:

[ label ] CPFSLT f [,a]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

(f) − (W),

Operation:

(f) – (W),

skip if (f) > (W)

(unsigned comparison)

skip if (f) < (W)

(unsigned comparison)

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0110

010a

ffff

0110

000a

ffff

Description:

Compares the contents of data

memory location 'f' to the contents

of the W by performing an

Description:

Compares the contents of data

memory location 'f' to the contents

of W by performing an unsigned

subtraction.

unsigned subtraction.

If the contents of 'f' are greater than

the contents of WREG, then the

fetched instruction is discarded and

a NOPis executed instead, making

this a two-cycle instruction. If ‘a’ is

0, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

If the contents of 'f' are less than

the contents of W, then the fetched

instruction is discarded and a NOP

is executed instead, making this a

two-cycle instruction. If ‘a’ is 0, the

Access Bank will be selected. If ’a’

is 1, the BSR will not be overridden

(default).

Words:

Cycles:

1

1(2)

Words:

Cycles:

1

Note: 3 cycles if skip and followed

by a 2-word instruction.

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

Read

register 'f'

Process

Data

No

operation

Q2

Q3

Q4

Decode

Read

register 'f'

Process

Data

No

operation

If skip:

Q1

Q2

No

operation

Q3

No

operation

Q4

No

operation

If skip:

Q1

No

operation

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No

If skip and followed by 2-word instruction:

No

Q1

Q2

Q3

Q4

operation

No

operation

No

operation

HERE

NLESS

LESS

CPFSLT REG, 1

:

Example:

HERE

NGREATER

GREATER

CPFSGT REG, 0

:

Example:

Before Instruction

PC

W

=

Address (HERE)

?

Before Instruction

After Instruction

PC

W

=

Address (HERE)

?

If REG

PC

If REG

PC

<

=

≥

=

W;

Address (LESS)

W;

Address (NLESS)

After Instruction

If REG

PC

>

=

W;

Address (GREATER)

If REG

PC

≤

=

W;

Address (NGREATER)

DS39564C-page 229

PIC18FXX2

DAW

Decimal Adjust W Register

DECF

Decrement f

Syntax:

[ label ] DAW

None

Syntax:

[ label ] DECF f [,d [,a]

Operands:

Operation:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

If [W<3:0> >9] or [DC = 1] then

(W<3:0>) + 6 → W<3:0>;

else

(W<3:0>) → W<3:0>;

Operation:

(f) – 1 → dest

Status Affected:

Encoding:

C, DC, N, OV, Z

0000

01da

ffff

If [W<7:4> >9] or [C = 1] then

(W<7:4>) + 6 → W<7:4>;

else

Description:

Decrement register 'f'. If 'd' is 0, the

result is stored in W. If 'd' is 1, the

result is stored back in register 'f'

(default). If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ = 1, then the

bank will be selected as per the

BSR value (default).

(W<7:4>) → W<7:4>;

Status Affected:

Encoding:

C

0000

0111

Description:

DAW adjusts the eight-bit value in

W, resulting from the earlier addi-

tion of two variables (each in

packed BCD format) and produces

a correct packed BCD result.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Read

register 'f'

Q3

Process

Data

Q4

Write to

destination

Decode

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register W

Process

Data

Write

W

DECF

CNT,

1, 0

Example:

Before Instruction

DAW

Example1:

CNT

Z

=

0x01

0

=

Before Instruction

After Instruction

W

C

DC

=

0xA5

0

CNT

Z

=

0x00

1

After Instruction

W

=

0x05

C

DC

=

1

0

Example 2:

Before Instruction

W

=

0xCE

C

DC

=

0

After Instruction

W

=

0x34

C

DC

=

1

0

DS39564C-page 230

PIC18FXX2

DECFSZ

Decrement f, skip if 0

DCFSNZ

Decrement f, skip if not 0

Syntax:

[ label ] DECFSZ f [,d [,a]]

Syntax:

[ label ] DCFSNZ f [,d [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) – 1 → dest,

skip if result = 0

Operation:

(f) – 1 → dest,

skip if result ≠ 0

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0010

11da

ffff

0100

11da

ffff

Description:

The contents of register 'f' are dec-

remented. If 'd' is 0, the result is

placed in W. If 'd' is 1, the result is

placed back in register 'f' (default).

If the result is 0, the next instruc-

tion, which is already fetched, is

discarded, and a NOPis executed

instead, making it a two-cycle

instruction. If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ = 1, then the

bank will be selected as per the

BSR value (default).

Description:

The contents of register 'f' are dec-

remented. If 'd' is 0, the result is

placed in W. If 'd' is 1, the result is

placed back in register 'f' (default).

If the result is not 0, the next

instruction, which is already

fetched, is discarded, and a NOPis

executed instead, making it a two-

cycle instruction. If ’a’ is 0, the

Access Bank will be selected,

overriding the BSR value. If ’a’ = 1,

then the bank will be selected as

per the BSR value (default).

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register 'f'

Process

Data

Write to

destination

Decode

Read

register 'f'

Process

Data

Write to

destination

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

HERE

DECFSZ

GOTO

CNT, 1, 1

LOOP

HERE

ZERO

NZERO

DCFSNZ TEMP, 1, 0

:

Example:

CONTINUE

Before Instruction

TEMP

PC

=

Address (HERE)

=

?

After Instruction

CNT

=

≠

=

CNT - 1

0;

TEMP

If TEMP

PC

If TEMP

PC

=

≠

=

TEMP - 1,

If CNT

0;

PC

Address (CONTINUE)

0;

Address (ZERO)

0;

Address (NZERO)

If CNT

PC

Address (HERE+2)

DS39564C-page 231

PIC18FXX2

GOTO

Unconditional Branch

INCF

Increment f

Syntax:

[ label ] GOTO k

0 ≤ k ≤ 1048575

k → PC<20:1>

None

Syntax:

[ label ] INCF f [,d [,a]

Operands:

Operation:

Status Affected:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) + 1 → dest

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

Status Affected:

Encoding:

C, DC, N, OV, Z

1110

1111

k kkk

kkkk

7

0

8

k

kkk kkkk

0010

10da

ffff

19

Description:

GOTOallows an unconditional

branch anywhere within entire

2 Mbyte memory range. The 20-bit

value ’k’ is loaded into PC<20:1>.

GOTOis always a two-cycle

instruction.

Description:

The contents of register 'f' are

incremented. If 'd' is 0, the result is

placed in W. If 'd' is 1, the result is

placed back in register 'f' (default).

If ’a’ is 0, the Access Bank will be

selected, overriding the BSR value.

If ’a’ = 1, then the bank will be

selected as per the BSR value

(default).

Words:

Cycles:

2

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Read literal

'k'<7:0>,

Q3

No

operation

Q4

Read literal

’k’<19:8>,

Decode

Q Cycle Activity:

Q1

Write to PC

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

Decode

Read

register 'f'

Process

Data

Write to

destination

GOTO THERE

Example:

INCF

CNT, 1, 0

Example:

After Instruction

Before Instruction

PC

=

Address (THERE)

CNT

=

0xFF

Z

=

0

?

C

DC

After Instruction

CNT

=

0x00

Z

1

C

DC

DS39564C-page 232

PIC18FXX2

INCFSZ

Increment f, skip if 0

INFSNZ

Increment f, skip if not 0

Syntax:

[ label ] INCFSZ f [,d [,a]

Syntax:

[ label ] INFSNZ f [,d [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) + 1 → dest,

skip if result = 0

Operation:

(f) + 1 → dest,

skip if result ≠ 0

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0011

11da

ffff

0100

10da

ffff

Description:

The contents of register 'f' are

incremented. If 'd' is 0, the result is

placed in W. If 'd' is 1, the result is

placed back in register 'f'. (default)

If the result is 0, the next instruc-

tion, which is already fetched, is

discarded, and a NOPis executed

instead, making it a two-cycle

instruction. If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ = 1, then the

bank will be selected as per the

BSR value (default).

Description:

The contents of register 'f' are

incremented. If 'd' is 0, the result is

placed in W. If 'd' is 1, the result is

placed back in register 'f' (default).

If the result is not 0, the next

instruction, which is already

fetched, is discarded, and a NOPis

executed instead, making it a two-

cycle instruction. If ’a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ’a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register 'f'

Process

Data

Write to

destination

Decode

Read

register 'f'

Process

Data

Write to

destination

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

HERE

NZERO

ZERO

INCFSZ

:

CNT, 1, 0

HERE

ZERO

NZERO

INFSNZ REG, 1, 0

Example:

Before Instruction

PC

=

Address (HERE)

PC

=

Address (HERE)

After Instruction

CNT

If CNT

PC

=

≠

=

CNT + 1

REG

If REG

PC

=

≠

=

REG + 1

0;

Address (ZERO)

0;

Address (NZERO)

0;

Address (ZERO)

If CNT

PC

If REG

PC

DS39564C-page 233

PIC18FXX2

IORLW

Inclusive OR literal with W

IORWF

Inclusive OR W with f

Syntax:

[ label ] IORLW k

0 ≤ k ≤ 255

Syntax:

[ label ] IORWF f [,d [,a]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(W) .OR. k → W

N, Z

Operation:

(W) .OR. (f) → dest

0000

1001

kkkk

Status Affected:

Encoding:

N, Z

Description:

The contents of W are OR’ed with

the eight-bit literal 'k'. The result is

placed in W.

0001

00da

ffff

Description:

Inclusive OR W with register 'f'. If 'd'

is 0, the result is placed in W. If 'd'

is 1, the result is placed back in

register 'f' (default). If ’a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ’a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write to W

Decode

Read

literal 'k'

Process

Data

Words:

Cycles:

1

IORLW

0x35

Example:

Before Instruction

Q Cycle Activity:

Q1

W

=

0x9A

Q2

Q3

Q4

Decode

Read

register 'f'

Process

Data

Write to

destination

After Instruction

W

=

0xBF

IORWF RESULT, 0, 1

Example:

Before Instruction

RESULT =

0x13

0x91

W

=

After Instruction

RESULT =

0x13

0x93

W

=

DS39564C-page 234

PIC18FXX2

LFSR

Load FSR

MOVF

Move f

Syntax:

[ label ] LFSR f,k

Syntax:

[ label ] MOVF f [,d [,a]

Operands:

0 ≤ f ≤ 2

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

0 ≤ k ≤ 4095

Operation:

k → FSRf

Operation:

f → dest

Status Affected:

Encoding:

None

Status Affected:

Encoding:

N, Z

1110

1111

1110

0000

00ff

k kkk

11

kkkk

k kkk

0101

00da

ffff

7

Description:

The 12-bit literal 'k' is loaded into

the file select register pointed to

by 'f'.

Description:

The contents of register 'f' are

moved to a destination dependent

upon the status of ’d’. If 'd' is 0, the

result is placed in W. If 'd' is 1, the

result is placed back in register 'f'

(default). Location 'f' can be any-

where in the 256 byte bank. If ’a’ is

0, the Access Bank will be

Words:

Cycles:

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

Decode

Read literal

'k' MSB

Process

Data

Write

literal 'k'

MSB to

FSRfH

Decode

Read literal

'k' LSB

Process

Data

Write literal

'k' to FSRfL

Words:

Cycles:

1

Q Cycle Activity:

Q1

LFSR 2, 0x3AB

Example:

Q2

Read

register 'f'

Q3

Process

Data

Q4

Write W

After Instruction

Decode

FSR2H

FSR2L

=

0x03

0xAB

MOVF

REG, 0, 0

Example:

Before Instruction

REG

W

=

0x22

0xFF

After Instruction

REG

W

=

0x22

DS39564C-page 235

PIC18FXX2

MOVFF

Move f to f

MOVLB

Move literal to low nibble in BSR

Syntax:

[ label ] MOVFF f_s,f_d

Syntax:

[ label ] MOVLB

0 ≤ k ≤ 255

k → BSR

k

Operands:

0 ≤ f_s≤ 4095

0 ≤ f_d≤ 4095

Operands:

Operation:

Status Affected:

Encoding:

Operation:

(f_s) → f_d

None

Status Affected:

None

0000

0001

kkkk

Encoding:

1st word (source)

2nd word (destin.)

Description:

The 8-bit literal 'k' is loaded into

the Bank Select Register (BSR).

1100

1111

ffff

ffff_s

ffff_d

Words:

Cycles:

1

Description:

The contents of source register 'f_s'

are moved to destination register

'f_d'. Location of source 'f_s' can be

anywhere in the 4096 byte data

space (000h to FFFh), and location

of destination 'f_d' can also be any-

where from 000h to FFFh.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal

'k'

Process

Data

Write

literal 'k' to

BSR

Either source or destination can be

W (a useful special situation).

MOVFFis particularly useful for

transferring a data memory location

to a peripheral register (such as the

transmit buffer or an I/O port).

MOVLB

5

Example:

Before Instruction

BSR register

=

0x02

0x05

After Instruction

BSR register

The MOVFFinstruction cannot use

the PCL, TOSU, TOSH or TOSL as

the destination register.

Note: The MOVFFinstruction

should not be used to mod-

ify interrupt settings while

any interrupt is enabled.

See Section 8.0 for more

information.

Words:

Cycles:

2

2 (3)

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register 'f'

(src)

Process

Data

No

operation

Decode

No

operation

No

operation

Write

register 'f'

(dest)

No dummy

read

MOVFF

REG1, REG2

Example:

Before Instruction

REG1

REG2

=

0x33

0x11

After Instruction

REG1

REG2

=

0x33,

0x33

DS39564C-page 236

PIC18FXX2

MOVLW

Move literal to W

MOVWF

Move W to f

Syntax:

[ label ] MOVLW k

0 ≤ k ≤ 255

k → W

Syntax:

[ label ] MOVWF f [,a]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

(W) → f

None

Status Affected:

Encoding:

None

0000

1110

kkkk

0110

111a

ffff

Description:

The eight-bit literal 'k' is loaded

into W.

Description:

Move data from W to register 'f'.

Location 'f' can be anywhere in the

256 byte bank. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write to W

Decode

Read

literal 'k'

Process

Data

Words:

Cycles:

1

MOVLW

0x5A

Example:

Q Cycle Activity:

Q1

After Instruction

Q2

Q3

Q4

W

=

0x5A

Decode

Read

register 'f'

Process

Data

Write

register 'f'

MOVWF

REG, 0

Example:

Before Instruction

W

REG

=

0x4F

0xFF

After Instruction

W

REG

=

0x4F

DS39564C-page 237

PIC18FXX2

MULLW

Multiply Literal with W

MULWF

Multiply W with f

Syntax:

[ label ] MULLW

k

Syntax:

[ label ] MULWF f [,a]

Operands:

Operation:

Status Affected:

Encoding:

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

(W) x k → PRODH:PRODL

Operation:

(W) x (f) → PRODH:PRODL

None

Status Affected:

Encoding:

None

0000

1101

kkkk

0000

001a

ffff

Description:

An unsigned multiplication is car-

ried out between the contents of

W and the 8-bit literal 'k'. The

16-bit result is placed in

PRODH:PRODL register pair.

PRODH contains the high byte.

W is unchanged.

None of the status flags are

affected.

Note that neither overflow nor

carry is possible in this opera-

tion. A zero result is possible but

not detected.

Description:

An unsigned multiplication is car-

ried out between the contents of

W and the register file location 'f'.

The 16-bit result is stored in the

PRODH:PRODL register pair.

PRODH contains the high byte.

Both W and 'f' are unchanged.

None of the status flags are

affected.

Note that neither overflow nor

carry is possible in this opera-

tion. A zero result is possible but

not detected. If ‘a’ is 0, the

Access Bank will be selected,

overriding the BSR value. If

‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Read

literal 'k'

Q3

Process

Data

Q4

Write

registers

PRODH:

PRODL

Decode

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

MULLW

0xC4

Example:

Decode

Read

register 'f'

Process

Data

Write

Before Instruction

registers

PRODH:

PRODL

W

PRODH

PRODL

=

0xE2

?

After Instruction

W

MULWF

REG, 1

Example:

=

0xE2

PRODH

PRODL

=

0xAD

0x08

Before Instruction

W

=

0xC4

REG

PRODH

PRODL

=

0xB5

?

After Instruction

W

=

0xC4

REG

PRODH

PRODL

=

0xB5

0x8A

0x94

DS39564C-page 238

PIC18FXX2

NEGF

Negate f

NOP

No Operation

Syntax:

[ label ] NEGF f [,a]

Syntax:

[ label ] NOP

None

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

Operation:

Status Affected:

Encoding:

No operation

None

Operation:

( f ) + 1 → f

Status Affected:

Encoding:

N, OV, C, DC, Z

0000

1111

0000

xxxx

0000

xxxx

0000

xxxx

0110

110a

ffff

Description:

Words:

No operation.

Description:

Location ‘f’ is negated using two’s

complement. The result is placed in

the data memory location 'f'. If ’a’ is

0, the Access Bank will be

1

Cycles:

Q Cycle Activity:

Q1

selected, overriding the BSR value.

If ’a’ = 1, then the bank will be

selected as per the BSR value.

Q2

No

Q3

No

Q4

No

Decode

operation

Words:

Cycles:

1

Example:

None.

Q Cycle Activity:

Q1

Q2

Q3

Process

Data

Q4

Write

register 'f'

Decode

Read

register 'f'

NEGF

REG, 1

Example:

Before Instruction

REG

=

0011 1010 [0x3A]

1100 0110 [0xC6]

After Instruction

REG

=

DS39564C-page 239

PIC18FXX2

POP

Pop Top of Return Stack

PUSH

Push Top of Return Stack

Syntax:

[ label ] POP

None

Syntax:

[ label ] PUSH

None

Operands:

Operation:

Status Affected:

Encoding:

Operands:

Operation:

Status Affected:

Encoding:

(TOS) → bit bucket

None

(PC+2) → TOS

None

0000

0110

0000

0101

Description:

The TOS value is pulled off the

return stack and is discarded. The

TOS value then becomes the previ-

ous value that was pushed onto the

return stack.

This instruction is provided to

enable the user to properly manage

the return stack to incorporate a

software stack.

Description:

The PC+2 is pushed onto the top of

the return stack. The previous TOS

value is pushed down on the stack.

This instruction allows to implement

a software stack by modifying TOS,

and then push it onto the return

stack.

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

PUSH PC+2

onto return

stack

No

operation

No

operation

Q2

Q3

Q4

Decode

No

operation

POP TOS

value

No

operation

PUSH

Example:

POP

GOTO

Example:

Before Instruction

NEW

TOS

PC

=

00345Ah

000124h

Before Instruction

TOS

=

0031A2h

014332h

After Instruction

Stack (1 level down)

PC

=

000126h

00345Ah

TOS

After Instruction

Stack (1 level down)

TOS

PC

=

014332h

NEW

DS39564C-page 240

PIC18FXX2

RCALL

Relative Call

RESET

Reset

Syntax:

[ label ] RCALL

-1024 ≤ n ≤ 1023

(PC) + 2 → TOS,

n

Syntax:

[ label ] RESET

None

Operands:

Operation:

Operands:

Operation:

Reset all registers and flags that

are affected by a MCLR Reset.

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

All

1101

1nnn

nnnn

0000

1111

Description:

Subroutine call with a jump up to

1K from the current location. First,

return address (PC+2) is pushed

onto the stack. Then, add the 2’s

complement number ’2n’ to the PC.

Since the PC will have incremented

to fetch the next instruction, the

new address will be PC+2+2n.

This instruction is a two-cycle

instruction.

Description:

This instruction provides a way to

execute a MCLR Reset in software.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Start

reset

No

operation

No

operation

Words:

Cycles:

1

2

RESET

Example:

After Instruction

Registers =

Reset Value

Q Cycle Activity:

Q1

Flags*

=

Q2

Q3

Q4

Decode

Read literal

'n'

Process

Data

Write to PC

Push PC to

stack

No

operation

HERE

RCALL

Jump

Example:

Before Instruction

PC

=

Address (HERE)

After Instruction

PC

=

Address (Jump)

Address (HERE+2)

TOS =

DS39564C-page 241

PIC18FXX2

RETFIE

Return from Interrupt

RETLW

Return Literal to W

Syntax:

[ label ] RETFIE [s]

Syntax:

[ label ] RETLW k

Operands:

Operation:

s ∈ [0,1]

Operands:

Operation:

0 ≤ k ≤ 255

(TOS) → PC,

k → W,

1 → GIE/GIEH or PEIE/GIEL,

if s = 1

(TOS) → PC,

PCLATU, PCLATH are unchanged

(WS) → W,

(STATUSS) → STATUS,

(BSRS) → BSR,

Status Affected:

Encoding:

None

0000

1100

kkkk

PCLATU, PCLATH are unchanged.

Description:

W is loaded with the eight-bit literal

'k'. The program counter is loaded

from the top of the stack (the return

address). The high address latch

(PCLATH) remains unchanged.

Status Affected:

Encoding:

GIE/GIEH, PEIE/GIEL.

0000

0001

000s

Description:

Return from Interrupt. Stack is

popped and Top-of-Stack (TOS) is

loaded into the PC. Interrupts are

enabled by setting either the high

or low priority global interrupt

enable bit. If ‘s’ = 1, the contents of

the shadow registers WS,

STATUSS and BSRS are loaded

into their corresponding registers,

W, STATUS and BSR. If ‘s’ = 0, no

update of these registers occurs

(default).

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal 'k'

Process

Data

pop PC from

stack, Write

to W

No

operation

Words:

Cycles:

1

2

Example:

CALL TABLE ; W contains table

; offset value

Q Cycle Activity:

Q1

Q2

Q3

Q4

; W now has

; table value

Decode

No

operation

No

operation

pop PC from

stack

:

TABLE

ADDWF PCL ; W = offset

Set GIEH or

GIEL

RETLW k0

RETLW k1

:

; Begin table

;

No

operation

No

operation

No

operation

No

operation

:

RETLW kn

; End of table

RETFIE

1

Example:

After Interrupt

Before Instruction

PC

W

BSR

STATUS

=

TOS

WS

W

=

0x07

BSRS

STATUSS

1

After Instruction

GIE/GIEH, PEIE/GIEL

W

=

value of kn

DS39564C-page 242

PIC18FXX2

RETURN

Return from Subroutine

RLCF

Rotate Left f through Carry

Syntax:

[ label ] RETURN [s]

Syntax:

[ label ] RLCF f [,d [,a]

Operands:

Operation:

s ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(TOS) → PC,

if s = 1

(WS) → W,

Operation:

(f<n>) → dest<n+1>,

(f<7>) → C,

(STATUSS) → STATUS,

(BSRS) → BSR,

PCLATU, PCLATH are unchanged

(C) → dest<0>

Status Affected:

Encoding:

C, N, Z

Status Affected:

Encoding:

None

0011

01da

ffff

0000

0001

001s

Description:

The contents of register 'f' are

rotated one bit to the left through

the Carry Flag. If 'd' is 0, the result

is placed in W. If 'd' is 1, the result

is stored back in register 'f'

(default). If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ = 1, then the

bank will be selected as per the

BSR value (default).

Description:

Return from subroutine. The stack

is popped and the top of the stack

(TOS) is loaded into the program

counter. If ‘s’= 1, the contents of the

shadow registers WS, STATUSS

and BSRS are loaded into their cor-

responding registers, W, STATUS

and BSR. If ‘s’ = 0, no update of

these registers occurs (default).

Words:

Cycles:

1

2

register f

C

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

No

operation

Process

Data

pop PC from

stack

Q2

Q3

Q4

No

Decode

Read

Process

Write to

operation

register 'f'

Data

destination

RLCF

REG, 0, 0

Example:

RETURN

Example:

Before Instruction

REG

C

=

1110 0110

0

After Interrupt

PC = TOS

After Instruction

REG

=

1110 0110

W

C

=

1100 1100

1

DS39564C-page 243

PIC18FXX2

RLNCF

Rotate Left f (no carry)

RRCF

Rotate Right f through Carry

Syntax:

[ label ] RLNCF f [,d [,a]

Syntax:

[ label ] RRCF f [,d [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f<n>) → dest<n+1>,

(f<7>) → dest<0>

Operation:

(f<n>) → dest<n-1>,

(f<0>) → C,

(C) → dest<7>

Status Affected:

Encoding:

N, Z

Status Affected:

Encoding:

C, N, Z

0100

01da

ffff

0011

00da

ffff

Description:

The contents of register 'f' are

rotated one bit to the left. If 'd' is 0,

the result is placed in W. If 'd' is 1,

the result is stored back in register

'f' (default). If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, then the

bank will be selected as per the

BSR value (default).

Description:

The contents of register 'f' are

rotated one bit to the right through

the Carry Flag. If 'd' is 0, the result

is placed in W. If 'd' is 1, the result

is placed back in register 'f'

(default). If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, then the

bank will be selected as per the

BSR value (default).

register f

Words:

Cycles:

1

register f

C

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

Read

register 'f'

Process

Data

Write to

destination

Q2

Q3

Q4

Decode

Read

Process

Write to

register 'f'

Data

destination

RLNCF

REG, 1, 0

Example:

Before Instruction

RRCF

REG, 0, 0

Example:

REG

=

1010 1011

0101 0111

After Instruction

Before Instruction

REG

=

REG

C

=

1110 0110

0

After Instruction

REG

=

1110 0110

W

C

=

0111 0011

0

DS39564C-page 244

PIC18FXX2

RRNCF

Rotate Right f (no carry)

SETF

Set f

Syntax:

[ label ] RRNCF f [,d [,a]

Syntax:

[ label ] SETF f [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

FFh → f

Operation:

(f<n>) → dest<n-1>,

(f<0>) → dest<7>

Status Affected:

Encoding:

None

0110

100a

ffff

Status Affected:

Encoding:

N, Z

Description:

The contents of the specified regis-

ter are set to FFh. If ’a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ’a’ is 1, then

the bank will be selected as per the

BSR value (default).

0100

00da

ffff

Description:

The contents of register 'f' are

rotated one bit to the right. If 'd' is 0,

the result is placed in W. If 'd' is 1,

the result is placed back in register

'f' (default). If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

register f

Decode

Read

register 'f'

Process

Data

Write

register 'f'

Words:

Cycles:

1

SETF

REG,1

Example:

Before Instruction

Q Cycle Activity:

Q1

REG

=

0x5A

0xFF

Q2

Read

register 'f'

Q3

Process

Data

Q4

Write to

destination

After Instruction

REG

Decode

=

RRNCF

REG, 1, 0

Example 1:

Before Instruction

REG

=

1101 0111

1110 1011

RRNCF REG, 0, 0

After Instruction

REG

=

Example 2:

Before Instruction

W

REG

=

?

1101 0111

After Instruction

W

REG

=

1110 1011

1101 0111

DS39564C-page 245

PIC18FXX2

SLEEP

Enter SLEEP mode

SUBFWB

Subtract f from W with borrow

Syntax:

[ label ] SLEEP

None

Syntax:

[ label ] SUBFWB f [,d [,a]

Operands:

Operation:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

00h → WDT,

0 → WDT postscaler,

1 → TO,

Operation:

(W) – (f) – (C) → dest

0 → PD

Status Affected:

Encoding:

N, OV, C, DC, Z

Status Affected:

Encoding:

TO, PD

0101

01da

ffff

0000

0011

Description:

Subtract register 'f' and carry flag

(borrow) from W (2’s complement

method). If 'd' is 0, the result is

stored in W. If 'd' is 1, the result is

stored in register 'f' (default). If ’a’ is

0, the Access Bank will be selected,

overriding the BSR value. If ’a’ is 1,

then the bank will be selected as

per the BSR value (default).

Description:

The power-down status bit (PD) is

cleared. The time-out status bit

(TO) is set. Watchdog Timer and

its postscaler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Go to

sleep

Q Cycle Activity:

Q1

Decode

No

operation

Process

Data

Q2

Q3

Q4

Decode

Read

register 'f'

Process

Data

Write to

destination

SLEEP

Example:

SUBFWB

REG, 1, 0

Example 1:

Before Instruction

TO

=

?

Before Instruction

PD

=

?

REG

=

3

2

1

After Instruction

W

C

=

TO

PD

=

1 †

0

After Instruction

REG

W

=

FF

2

† If WDT causes wake-up, this bit is cleared.

C

Z

N

=

0

1

; result is negative

SUBFWB

REG, 0, 0

Example 2:

Before Instruction

REG

=

2

W

C

=

5

1

After Instruction

REG

=

2

3

W

=

C

Z

N

=

1

0

; result is positive

SUBFWB

REG, 1, 0

Example 3:

Before Instruction

REG

=

1

W

C

=

2

0

After Instruction

REG

=

0

2

W

=

C

Z

N

=

1

0

; result is zero

DS39564C-page 246

PIC18FXX2

SUBLW

Subtract W from literal

SUBWF

Syntax:

Subtract W from f

Syntax:

[ label ] SUBLW k

0 ≤ k ≤ 255

[ label ] SUBWF f [,d [,a]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

k – (W) → W

N, OV, C, DC, Z

Operation:

(f) – (W) → dest

0000

1000

kkkk

Status Affected:

Encoding:

N, OV, C, DC, Z

Description:

W is subtracted from the eight-bit

literal 'k'. The result is placed

in W.

0101

11da

ffff

Description:

Subtract W from register 'f' (2’s

complement method). If 'd' is 0,

the result is stored in W. If 'd' is 1,

the result is stored back in regis-

ter 'f' (default). If ’a’ is 0, the

Access Bank will be selected,

overriding the BSR value. If ’a’ is

1, then the bank will be selected

as per the BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal 'k'

Process

Data

Write to W

SUBLW 0x02

Example 1:

Words:

Cycles:

1

Before Instruction

W

C

=

1

?

Q Cycle Activity:

Q1

Q2

Q3

Q4

After Instruction

Decode

Read

register 'f'

Process

Data

Write to

destination

W

=

1

C

=

1

0

; result is positive

Z

SUBWF

REG, 1, 0

Example 1:

N

SUBLW 0x02

Example 2:

Before Instruction

REG

W

C

=

3

2

?

Before Instruction

W

C

=

2

?

After Instruction

REG

W

C

Z

N

=

1

2

1

0

W

=

0

; result is positive

C

=

1

0

; result is zero

Z

N

SUBWF

REG, 0, 0

Example 2:

SUBLW 0x02

Example 3:

Before Instruction

REG

=

2

?

W

C

=

3

?

W

C

=

After Instruction

W

=

FF ; (2’s complement)

REG

=

2

0

1

0

C

=

0

1

; result is negative

W

=

Z

C

Z

N

=

; result is zero

N

SUBWF

REG, 1, 0

Example 3:

Before Instruction

REG

=

1

W

C

=

2

?

After Instruction

REG

=

FFh ;(2’s complement)

2

W

=

C

Z

N

=

0

1

; result is negative

DS39564C-page 247

PIC18FXX2

SUBWFB

Syntax:

Subtract W from f with Borrow

SWAPF

Swap f

Syntax:

[ label ] SWAPF f [,d [,a]

[ label ] SUBWFB f [,d [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f<3:0>) → dest<7:4>,

(f<7:4>) → dest<3:0>

Operation:

(f) – (W) – (C) → dest

Status Affected: N, OV, C, DC, Z

Status Affected:

Encoding:

None

Encoding:

0101

10da

ffff

0011

10da

ffff

Description:

Subtract W and the carry flag (bor-

row) from register 'f' (2’s complement

method). If 'd' is 0, the result is stored

in W. If 'd' is 1, the result is stored

back in register 'f' (default). If ’a’ is 0,

the Access Bank will be selected,

overriding the BSR value. If ’a’ is 1,

then the bank will be selected as per

the BSR value (default).

Description:

The upper and lower nibbles of reg-

ister 'f' are exchanged. If 'd' is 0, the

result is placed in W. If 'd' is 1, the

result is placed in register 'f'

(default). If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write to

destination

Q2

Q3

Q4

Write to

destination

Decode

Read

register 'f'

Process

Data

Decode

Read

register 'f'

Process

Data

SUBWFB REG, 1, 0

Example 1:

Before Instruction

SWAPF

REG, 1, 0

Example:

REG

=

0x19

0x0D

1

(0001 1001)

(0000 1101)

Before Instruction

W

C

=

REG

=

0x53

0x35

After Instruction

REG

=

REG

=

0x0C

0x0D

(0000 1011)

(0000 1101)

W

=

C

Z

N

=

1

0

; result is positive

SUBWFB REG, 0, 0

Example 2:

Before Instruction

REG

W

C

=

0x1B

0x1A

0

(0001 1011)

(0001 1010)

After Instruction

REG

=

0x1B

0x00

(0001 1011)

W

=

C

Z

N

=

1

0

; result is zero

SUBWFB REG, 1, 0

Example 3:

Before Instruction

REG

W

C

=

0x03

0x0E

1

(0000 0011)

(0000 1101)

After Instruction

REG

=

0xF5

0x0E

(1111 0100)

; [2’s comp]

(0000 1101)

W

=

C

Z

N

=

0

1

; result is negative

DS39564C-page 248

PIC18FXX2

TBLRD

Table Read

TBLRD

Table Read (cont’d)

TBLRD *+ ;

Syntax:

[ label ] TBLRD ( *; *+; *-; +*)

None

Example1:

Operands:

Operation:

Before Instruction

TABLAT

TBLPTR

=

0x55

0x00A356

0x34

if TBLRD *,

(Prog Mem (TBLPTR)) → TABLAT;

TBLPTR - No Change;

if TBLRD *+,

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) +1 → TBLPTR;

if TBLRD *-,

MEMORY(0x00A356)

After Instruction

TABLAT

TBLPTR

=

0x34

0x00A357

TBLRD +* ;

Example2:

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) -1 → TBLPTR;

if TBLRD +*,

(TBLPTR) +1 → TBLPTR;

(Prog Mem (TBLPTR)) → TABLAT;

Before Instruction

TABLAT

=

0xAA

TBLPTR

0x01A357

0x12

MEMORY(0x01A357)

MEMORY(0x01A358)

0x34

After Instruction

Status Affected:None

TABLAT

TBLPTR

=

0x34

0x01A358

0000

10nn

nn=0 *

=1 *+

=2 *-

=3 +*

Encoding:

Description:

This instruction is used to read the con-

tents of Program Memory (P.M.). To

address the program memory, a pointer

called Table Pointer (TBLPTR) is used.

The TBLPTR (a 21-bit pointer) points

to each byte in the program memory.

TBLPTR has a 2 Mbyte address range.

TBLPTR[0] = 0: Least Significant

Byte of Program

Memory Word

TBLPTR[0] = 1: Most Significant

Byte of Program

Memory Word

The TBLRDinstruction can modify the

value of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

No

operation

No

operation

No

operation

No

No operation

No

No operation

operation (Read Program operation (Write TABLAT)

Memory)

DS39564C-page 249

PIC18FXX2

TBLWT

Table Write

TBLWT

Table Write (Continued)

TBLWT *+;

Syntax:

[ label ]

None

TBLWT ( *; *+; *-; +*)

Example1:

Operands:

Operation:

Before Instruction

TABLAT

TBLPTR

=

0x55

if TBLWT*,

0x00A356

(TABLAT) → Holding Register;

TBLPTR - No Change;

if TBLWT*+,

(TABLAT) → Holding Register;

(TBLPTR) +1 → TBLPTR;

if TBLWT*-,

(TABLAT) → Holding Register;

(TBLPTR) -1 → TBLPTR;

if TBLWT+*,

HOLDING REGISTER

(0x00A356)

=

0xFF

After Instructions (table write completion)

TABLAT

TBLPTR

=

0x55

0x00A357

=

HOLDING REGISTER

(0x00A356)

=

0x55

TBLWT +*;

Example 2:

Before Instruction

(TBLPTR) +1 → TBLPTR;

(TABLAT) → Holding Register;

TABLAT

TBLPTR

=

0x34

0x01389A

HOLDING REGISTER

(0x01389A)

HOLDING REGISTER

(0x01389B)

Status Affected: None

=

0xFF

0000

11nn

nn=0 *

=1 *+

=2 *-

=3 +*

Encoding:

=

0xFF

After Instruction (table write completion)

TABLAT

TBLPTR

=

0x34

0x01389B

=

HOLDING REGISTER

(0x01389A)

HOLDING REGISTER

(0x01389B)

=

0xFF

0x34

Description:

This instruction uses the 3 LSbs of the

TBLPTR to determine which of the 8

holding registers the TABLAT data is

written to. The 8 holding registers are

used to program the contents of Pro-

gram Memory (P.M.). See Section 5.0

for information on writing to FLASH

memory.

The TBLPTR (a 21-bit pointer) points

to each byte in the program memory.

TBLPTR has a 2 MBtye address

range. The LSb of the TBLPTR selects

which byte of the program memory

location to access.

TBLPTR[0] = 0:Least Significant

Byte of Program

Memory Word

TBLPTR[0] = 1:Most Significant

Byte of Program

Memory Word

The TBLWT instruction can modify the

value of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

No

Q3

No

Q4

No

Decode

operation

No

operation

(Read

TABLAT)

operation

(Write to Holding

Register or Memory)

DS39564C-page 250

PIC18FXX2

TSTFSZ

Test f, skip if 0

XORLW

Exclusive OR literal with W

Syntax:

[ label ] TSTFSZ f [,a]

Syntax:

[ label ] XORLW k

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

Operation:

Status Affected:

Encoding:

(W) .XOR. k → W

N, Z

Operation:

skip if f = 0

None

Status Affected:

Encoding:

0000

1010

kkkk

0110

011a

ffff

Description:

The contents of W are XORed

with the 8-bit literal 'k'. The result

is placed in W.

Description:

If 'f' = 0, the next instruction,

fetched during the current instruc-

tion execution, is discarded and a

NOPis executed, making this a two-

cycle instruction. If ’a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ’a’ is 1,

then the bank will be selected as

per the BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write to W

Decode

Read

literal 'k'

Process

Data

Words:

Cycles:

1

1(2)

Example:

XORLW 0xAF

= 0xB5

Note: 3 cycles if skip and followed

by a 2-word instruction.

Before Instruction

W

Q Cycle Activity:

Q1

After Instruction

Q2

Q3

Process

Data

Q4

No

operation

W

=

0x1A

Decode

Read

register 'f'

If skip:

Q1

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No

operation

No

operation

HERE

NZERO

ZERO

TSTFSZ CNT, 1

:

Example:

:

Before Instruction

PC = Address (HERE)

After Instruction

If CNT

=

≠

=

0x00,

PC

Address (ZERO)

0x00,

If CNT

PC

Address (NZERO)

DS39564C-page 251

PIC18FXX2

XORWF

Exclusive OR W with f

Syntax:

[ label ] XORWF f [,d [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(W) .XOR. (f) → dest

Status Affected:

Encoding:

N, Z

0001

10da

ffff

Description:

Exclusive OR the contents of W

with register 'f'. If 'd' is 0, the result

is stored in W. If 'd' is 1, the result is

stored back in the register 'f'

(default). If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register 'f'

Process

Data

Write to

destination

XORWF

REG, 1, 0

Example:

Before Instruction

REG

=

0xAF

0xB5

W

=

After Instruction

REG

=

0x1A

0xB5

W

=

DS39564C-page 252

PIC18FXX2

The MPLAB IDE allows you to:

21.0 DEVELOPMENT SUPPORT

The PICmicro^®microcontrollers are supported with a

full range of hardware and software development tools:

• Edit your source files (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro emulator and simulator tools (auto-

matically updates all project information)

• Integrated Development Environment

- MPLAB^®IDE Software

• Debug using:

- source files

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

- absolute listing file

- machine code

- MPLAB C17 and MPLAB C18 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

The ability to use MPLAB IDE with multiple debugging

tools allows users to easily switch from the cost-

effective simulator to a full-featured emulator with

minimal retraining.

• Simulators

- MPLAB SIM Software Simulator

• Emulators

21.2 MPASM Assembler

- MPLAB ICE 2000 In-Circuit Emulator

- ICEPIC™ In-Circuit Emulator

• In-Circuit Debugger

The MPASM assembler is a full-featured universal

macro assembler for all PICmicro MCU’s.

- MPLAB ICD

The MPASM assembler has a command line interface

and a Windows shell. It can be used as a stand-alone

application on a Windows 3.x or greater system, or it

can be used through MPLAB IDE. The MPASM assem-

bler generates relocatable object files for the MPLINK

object linker, Intel^®standard HEX files, MAP files to

detail memory usage and symbol reference, an abso-

lute LST file that contains source lines and generated

machine code, and a COD file for debugging.

• Device Programmers

- PRO MATE^®II Universal Device Programmer

- PICSTART^®Plus Entry-Level Development

Programmer

• Low Cost Demonstration Boards

- PICDEM^TM1 Demonstration Board

- PICDEM 2 Demonstration Board

- PICDEM 3 Demonstration Board

- PICDEM 17 Demonstration Board

- KEELOQ^®Demonstration Board

The MPASM assembler features include:

• Integration into MPLAB IDE projects.

• User-defined macros to streamline assembly

code.

21.1 MPLAB Integrated Development

Environment Software

• Conditional assembly for multi-purpose source

files.

The MPLAB IDE software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. The MPLAB IDE is a Windows^®based

application that contains:

• Directives that allow complete control over the

assembly process.

21.3 MPLAB C17 and MPLAB C18

C Compilers

• An interface to debugging tools

- simulator

The MPLAB C17 and MPLAB C18 Code Development

Systems are complete ANSI ‘C’ compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microcontrollers, respectively. These compilers provide

powerful integration capabilities and ease of use not

found with other compilers.

- programmer (sold separately)

- emulator (sold separately)

- in-circuit debugger (sold separately)

• A full-featured editor

• A project manager

For easier source level debugging, the compilers pro-

vide symbol information that is compatible with the

MPLAB IDE memory display.

• Customizable toolbar and key mapping

• A status bar

• On-line help

DS39564C-page 253

PIC18FXX2

21.4 MPLINK Object Linker/

MPLIB Object Librarian

21.6 MPLAB ICE High Performance

Universal In-Circuit Emulator with

MPLAB IDE

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C compilers. It can also

link relocatable objects from pre-compiled libraries,

using directives from a linker script.

The MPLAB ICE universal in-circuit emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PICmicro

microcontrollers (MCUs). Software control of the

MPLAB ICE in-circuit emulator is provided by the

MPLAB Integrated Development Environment (IDE),

which allows editing, building, downloading and source

debugging from a single environment.

The MPLIB object librarian is a librarian for pre-

compiled code to be used with the MPLINK object

linker. When a routine from a library is called from

another source file, only the modules that contain that

routine will be linked in with the application. This allows

large libraries to be used efficiently in many different

applications. The MPLIB object librarian manages the

creation and modification of library files.

The MPLAB ICE 2000 is a full-featured emulator sys-

tem with enhanced trace, trigger and data monitoring

features. Interchangeable processor modules allow the

system to be easily reconfigured for emulation of differ-

ent processors. The universal architecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PICmicro microcontrollers.

The MPLINK object linker features include:

• Integration with MPASM assembler and MPLAB

C17 and MPLAB C18 C compilers.

The MPLAB ICE in-circuit emulator system has been

designed as a real-time emulation system, with

advanced features that are generally found on more

expensive development tools. The PC platform and

Microsoft^®Windows environment were chosen to best

make these features available to you, the end user.

• Allows all memory areas to be defined as sections

to provide link-time flexibility.

The MPLIB object librarian features include:

• Easier linking because single libraries can be

included instead of many smaller files.

• Helps keep code maintainable by grouping

related modules together.

21.7 ICEPIC In-Circuit Emulator

• Allows libraries to be created and modules to be

added, listed, replaced, deleted or extracted.

The ICEPIC low cost, in-circuit emulator is a solution

for the Microchip Technology PIC16C5X, PIC16C6X,

PIC16C7X and PIC16CXXX families of 8-bit One-

Time-Programmable (OTP) microcontrollers. The mod-

ular system can support different subsets of PIC16C5X

or PIC16CXXX products through the use of inter-

changeable personality modules, or daughter boards.

The emulator is capable of emulating without target

application circuitry being present.

21.5 MPLAB SIM Software Simulator

The MPLAB SIM software simulator allows code devel-

opment in a PC-hosted environment by simulating the

PICmicro series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user-defined key press, to any of the pins. The

execution can be performed in single step, execute

until break, or trace mode.

The MPLAB SIM simulator fully supports symbolic debug-

ging using the MPLAB C17 and the MPLAB C18 C com-

pilers and the MPASM assembler. The software simulator

offers the flexibility to develop and debug code outside of

the laboratory environment, making it an excellent multi-

project software development tool.

DS39564C-page 254

PIC18FXX2

21.8 MPLAB ICD In-Circuit Debugger

21.11 PICDEM 1 Low Cost PICmicro

Demonstration Board

Microchip's In-Circuit Debugger, MPLAB ICD, is a pow-

erful, low cost, run-time development tool. This tool is

based on the FLASH PICmicro MCUs and can be used

to develop for this and other PICmicro microcontrollers.

The MPLAB ICD utilizes the in-circuit debugging capa-

bility built into the FLASH devices. This feature, along

with Microchip's In-Circuit Serial Programming^TMproto-

col, offers cost-effective in-circuit FLASH debugging

from the graphical user interface of the MPLAB

Integrated Development Environment. This enables a

designer to develop and debug source code by watch-

ing variables, single-stepping and setting break points.

Running at full speed enables testing hardware in real-

time.

The PICDEM 1 demonstration board is a simple board

which demonstrates the capabilities of several of

Microchip’s microcontrollers. The microcontrollers sup-

ported are: PIC16C5X (PIC16C54 to PIC16C58A),

PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,

PIC17C42, PIC17C43 and PIC17C44. All necessary

hardware and software is included to run basic demo

programs. The user can program the sample microcon-

trollers provided with the PICDEM 1 demonstration

board on a PRO MATE II device programmer, or a

PICSTART Plus development programmer, and easily

test firmware. The user can also connect the

PICDEM 1 demonstration board to the MPLAB ICE in-

circuit emulator and download the firmware to the emu-

lator for testing. A prototype area is available for the

user to build some additional hardware and connect it

to the microcontroller socket(s). Some of the features

include an RS-232 interface, a potentiometer for simu-

lated analog input, push button switches and eight

LEDs connected to PORTB.

21.9 PRO MATE II Universal Device

Programmer

The PRO MATE II universal device programmer is a

full-featured programmer, capable of operating in

stand-alone mode, as well as PC-hosted mode. The

PRO MATE II device programmer is CE compliant.

The PRO MATE II device programmer has program-

mable VDD and VPP supplies, which allow it to verify

programmed memory at VDD min and VDD max for max-

imum reliability. It has an LCD display for instructions

and error messages, keys to enter commands and a

modular detachable socket assembly to support various

package types. In stand-alone mode, the PRO MATE II

device programmer can read, verify, or program

PICmicro devices. It can also set code protection in this

mode.

21.12 PICDEM 2 Low Cost PIC16CXX

Demonstration Board

The PICDEM 2 demonstration board is a simple dem-

onstration board that supports the PIC16C62,

PIC16C64, PIC16C65, PIC16C73 and PIC16C74

microcontrollers. All the necessary hardware and soft-

ware is included to run the basic demonstration pro-

grams. The user can program the sample

microcontrollers provided with the PICDEM 2 demon-

stration board on a PRO MATE II device programmer,

or a PICSTART Plus development programmer, and

easily test firmware. The MPLAB ICE in-circuit emula-

tor may also be used with the PICDEM 2 demonstration

board to test firmware. A prototype area has been pro-

vided to the user for adding additional hardware and

connecting it to the microcontroller socket(s). Some of

the features include a RS-232 interface, push button

switches, a potentiometer for simulated analog input, a

serial EEPROM to demonstrate usage of the I²C^TMbus

and separate headers for connection to an LCD

module and a keypad.

21.10 PICSTART Plus Entry Level

Development Programmer

The PICSTART Plus development programmer is an

easy-to-use, low cost, prototype programmer. It con-

nects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient.

The PICSTART Plus development programmer sup-

ports all PICmicro devices with up to 40 pins. Larger pin

count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus development programmer is CE

compliant.

DS39564C-page 255

PIC18FXX2

21.13 PICDEM 3 Low Cost PIC16CXXX

Demonstration Board

21.14 PICDEM 17 Demonstration Board

The PICDEM 17 demonstration board is an evaluation

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. All neces-

sary hardware is included to run basic demo programs,

which are supplied on a 3.5-inch disk. A programmed

sample is included and the user may erase it and

program it with the other sample programs using the

PRO MATE II device programmer, or the PICSTART

Plus development programmer, and easily debug and

test the sample code. In addition, the PICDEM 17 dem-

onstration board supports downloading of programs to

and executing out of external FLASH memory on board.

The PICDEM 17 demonstration board is also usable

with the MPLAB ICE in-circuit emulator, or the

PICMASTER emulator and all of the sample programs

can be run and modified using either emulator. Addition-

ally, a generous prototype area is available for user

hardware.

The PICDEM 3 demonstration board is a simple dem-

onstration board that supports the PIC16C923 and

PIC16C924 in the PLCC package. It will also support

future 44-pin PLCC microcontrollers with an LCD Mod-

ule. All the necessary hardware and software is

included to run the basic demonstration programs. The

user can program the sample microcontrollers pro-

vided with the PICDEM 3 demonstration board on a

PRO MATE II device programmer, or a PICSTART Plus

development programmer with an adapter socket, and

easily test firmware. The MPLAB ICE in-circuit emula-

tor may also be used with the PICDEM 3 demonstration

board to test firmware. A prototype area has been pro-

vided to the user for adding hardware and connecting it

to the microcontroller socket(s). Some of the features

include a RS-232 interface, push button switches, a

potentiometer for simulated analog input, a thermistor

and separate headers for connection to an external

LCD module and a keypad. Also provided on the

PICDEM 3 demonstration board is a LCD panel, with 4

commons and 12 segments, that is capable of display-

ing time, temperature and day of the week. The

PICDEM 3 demonstration board provides an additional

RS-232 interface and Windows software for showing

the demultiplexed LCD signals on a PC. A simple serial

interface allows the user to construct a hardware

demultiplexer for the LCD signals.

21.15 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support

Microchip’s HCS Secure Data Products. The HCS eval-

uation kit includes a LCD display to show changing

codes, a decoder to decode transmissions and a

programming interface to program test transmitters.

DS39564C-page 256

PIC18FXX2

TABLE 21-1: DEVELOPMENT TOOLS FROM MICROCHIP

0 1 5 2 P M C

X X X C R M F

H C S X X X

X X C 9 3

/ X X C 2 5

/ X X C 2 4

X X X F 8 C 1 P I

X X C 8 2 C 1 P I

X 7 X 7 C 1 C I P

X 4 1 7 C I C P

X 9 X 6 C 1 C I P

X 8 X 6 F 1 C I P

8 X 6 1 F C I P

/ X 8 1 6 C I C P

X 7 X 6 C 1 C I P

X 7 1 6 C I C P

X 6 2 1 6 C I F P

X X X C 6 C 1 P I

X 6 1 6 C I C P

X 5 1 6 C I C P

0 0 1 4 C I 0 P

X X X C 2 C 1 P I

s o l T e o r a w f t S o s r o t a u l E m e r u b g e g D s m e a r m o g P r r

s t K l a i E d v n a s d r a B o o m D e

DS39564C-page 257

PIC18FXX2

NOTES:

DS39564C-page 258

PIC18FXX2

22.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings ^(†)

Ambient temperature under bias.............................................................................................................-55°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V

Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V

Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V

Total power dissipation (Note 1) ...............................................................................................................................1.0W

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin ..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined)...................................................200 mA

Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............................................200 mA

Maximum current sunk by PORTC and PORTD (Note 3) (combined)..................................................................200 mA

Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200 mA

Note 1: Power dissipation is calculated as follows:

Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latchup.

Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather

than pulling this pin directly to VSS.

3: PORTD and PORTE not available on the PIC18F2X2 devices.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

DS39564C-page 259

PIC18FXX2

FIGURE 22-1:

PIC18FXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

6.0V

5.5V

5.0V

4.5V

4.0V

PIC18FXXX

4.2V

3.5V

3.0V

2.5V

2.0V

40 MHz

Frequency

FIGURE 22-2:

PIC18LFXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

6.0V

5.5V

5.0V

4.5V

4.0V

PIC18LFXXX

4.2V

3.5V

3.0V

2.5V

2.0V

40 MHz

4 MHz

Frequency

FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz

Note: VDDAPPMIN is the minimum voltage of the PICmicro^®device in the application.

DS39564C-page 260

PIC18FXX2

22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended)

PIC18LFXX2 (Industrial)

PIC18LFXX2

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

(Industrial)

Standard Operating Conditions (unless otherwise stated)

PIC18FXX2

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

(Industrial, Extended)

-40°C ≤ TA ≤ +125°C for extended

Param

No.

Symbol

Characteristic

Supply Voltage

Min

Typ Max Units

Conditions

VDD

D001

D002

PIC18LFXX2 2.0

PIC18FXX2 4.2

—

5.5

—

V

HS, XT, RC and LP Osc mode

VDR

RAM Data Retention

1.5

Voltage⁽¹⁾

D003

D004

VPOR

VDD Start Voltage

to ensure internal

Power-on Reset signal

—

0.7

—

V

See Section 3.1 (Power-on Reset) for details

SVDD

VBOR

VDD Rise Rate

to ensure internal

Power-on Reset signal

0.05

V/ms See Section 3.1 (Power-on Reset) for details

Brown-out Reset Voltage

PIC18LFXX2

D005

BORV1:BORV0 = 11 1.98

BORV1:BORV0 = 10 2.67

BORV1:BORV0 = 01 4.16

BORV1:BORV0 = 00 4.45

PIC18FXX2

—

2.14

2.89

4.5

V

85°C ≥ T ≥ 25°C

4.83

BORV1:BORV0 = 1x N.A.

BORV1:BORV0 = 01 4.16

BORV1:BORV0 = 00 4.45

—

N.A.

4.5

V

Not in operating voltage range of device

4.83

Legend: Shading of rows is to assist in readability of the table.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an

impact on the current consumption.

The test conditions for all IDD measurements in active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all

features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...).

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.

5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not additive.

Once one of these modules is enabled, the other may also be enabled without further penalty.

DS39564C-page 261

PIC18FXX2

22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended)

PIC18LFXX2 (Industrial) (Continued)

PIC18LFXX2

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

(Industrial)

Standard Operating Conditions (unless otherwise stated)

PIC18FXX2

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

(Industrial, Extended)

-40°C ≤ TA ≤ +125°C for extended

Param

No.

Symbol

Characteristic

Min

Typ Max Units

Conditions

IDD

Supply Current^(2,4)

D010

PIC18LFXX2

XT osc configuration

—

.5

1.2

1

mA VDD = 2.0V, +25°C, FOSC = 4 MHz

1.25 mA VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz

2

mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz

RC osc configuration

—

.3

1.5

1

3

mA VDD = 2.0V, +25°C, FOSC = 4 MHz

mA VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz

mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz

RCIO osc configuration

—

.3

.75

1

3

mA VDD = 2.0V, +25°C, FOSC = 4 MHz

mA VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz

mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz

D010

PIC18FXX2

XT osc configuration

—

1.2

1.5

2

3

mA VDD = 4.2V, +25°C, FOSC = 4 MHz

mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz

mA VDD = 4.2V, -40°C to +125°C, FOSC = 4 MHz

RC osc configuration

—

1.5

1.6

3

4

mA VDD = 4.2V, +25°C, FOSC = 4 MHz

mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz

mA VDD = 4.2V, -40°C to +125°C, FOSC = 4 MHz

RCIO osc configuration

—

.75

.8

2

3

mA VDD = 4.2V, +25°C, FOSC = 4 MHz

mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz

mA VDD = 4.2V, -40°C to +125°C, FOSC = 4 MHz

D010A

PIC18LFXX2

PIC18FXX2

LP osc, FOSC = 32 kHz, WDT disabled

μA VDD = 2.0V, -40°C to +85°C

—

14

30

LP osc, FOSC = 32 kHz, WDT disabled

μA VDD = 4.2V, -40°C to +85°C

μA VDD = 4.2V, -40°C to +125°C

—

40

50

70

100

Legend: Shading of rows is to assist in readability of the table.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an

impact on the current consumption.

The test conditions for all IDD measurements in active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all

features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...).

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.

5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not additive.

Once one of these modules is enabled, the other may also be enabled without further penalty.

DS39564C-page 262

PIC18FXX2

22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended)

PIC18LFXX2 (Industrial) (Continued)

PIC18LFXX2

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

(Industrial)

Standard Operating Conditions (unless otherwise stated)

PIC18FXX2

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

(Industrial, Extended)

-40°C ≤ TA ≤ +125°C for extended

Param

No.

Symbol

Characteristic

Min

Typ Max Units

Conditions

IDD

Supply Current^(2,4)(Continued)

D010C

D013

PIC18LFXX2

—

EC, ECIO osc configurations

mA VDD = 4.2V, -40°C to +85°C

10

25

PIC18FXX2

—

EC, ECIO osc configurations

mA VDD = 4.2V, -40°C to +125°C

PIC18LFXX2

HS osc configuration

—

.6

10

2

15

mA FOSC = 4 MHz, VDD = 2.0V

mA FOSC = 25 MHz, VDD = 5.5V

HS + PLL osc configurations

mA FOSC = 10 MHz, VDD = 5.5V

—

15

25

D013

PIC18FXX2

—

HS osc configuration

10

15

25

mA FOSC = 25 MHz, VDD = 5.5V

HS + PLL osc configurations

mA FOSC = 10 MHz, VDD = 5.5V

—

D014

PIC18LFXX2

—

Timer1 osc configuration

μA FOSC = 32 kHz, VDD = 2.0V

15

55

PIC18FXX2

Timer1 osc configuration

—

200

250

μA FOSC = 32 kHz, VDD = 4.2V, -40°C to +85°C

μA FOSC = 32 kHz, VDD = 4.2V, -40°C to +125°C

IPD

Power-down Current⁽³⁾

D020

—

.08

.1

3

.9

4

10

μA VDD = 2.0V, +25°C

μA VDD = 2.0V, -40°C to +85°C

μA VDD = 4.2V, -40°C to +85°C

PIC18LFXX2

D020

PIC18FXX2

—

.1

3

15

.9

10

25

μA VDD = 4.2V, +25°C

μA VDD = 4.2V, -40°C to +85°C

μA VDD = 4.2V, -40°C to +125°C

D021B

Legend: Shading of rows is to assist in readability of the table.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an

impact on the current consumption.

The test conditions for all IDD measurements in active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all

features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...).

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.

5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not additive.

Once one of these modules is enabled, the other may also be enabled without further penalty.

DS39564C-page 263

PIC18FXX2

22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended)

PIC18LFXX2 (Industrial) (Continued)

PIC18LFXX2

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

(Industrial)

Standard Operating Conditions (unless otherwise stated)

PIC18FXX2

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

(Industrial, Extended)

-40°C ≤ TA ≤ +125°C for extended

Param

No.

Symbol

Characteristic

Min

Typ Max Units

Conditions

Module Differential Current

D022

ΔIWDT

Watchdog Timer

—

.75

2

10

1.5

8

25

μA VDD = 2.0V, +25°C

μA VDD = 2.0V, -40°C to +85°C

μA VDD = 4.2V, -40°C to +85°C

PIC18LFXX2

Watchdog Timer

—

7

10

25

15

25

40

μA VDD = 4.2V, +25°C

μA VDD = 4.2V, -40°C to +85°C

μA VDD = 4.2V, -40°C to +125°C

PIC18FXX2

D022A ΔIBOR

D022A

Brown-out Reset⁽⁵⁾

—

29

33

35

45

50

μA VDD = 2.0V, +25°C

μA VDD = 2.0V, -40°C to +85°C

μA VDD = 4.2V, -40°C to +85°C

PIC18LFXX2

Brown-out Reset⁽⁵⁾

—

36

40

50

65

μA VDD = 4.2V, +25°C

μA VDD = 4.2V, -40°C to +85°C

μA VDD = 4.2V, -40°C to +125°C

PIC18FXX2

D022B ΔILVD

D022B

Low Voltage Detect⁽⁵⁾

—

29

33

35

45

50

μA VDD = 2.0V, +25°C

μA VDD = 2.0V, -40°C to +85°C

μA VDD = 4.2V, -40°C to +85°C

PIC18LFXX2

Low Voltage Detect⁽⁵⁾

—

33

40

50

65

μA VDD = 4.2V, +25°C

μA VDD = 4.2V, -40°C to +85°C

μA VDD = 4.2V, -40°C to +125°C

PIC18FXX2

D025

ΔITMR1

Timer1 Oscillator

—

5.2

6.5

30

40

50

μA VDD = 2.0V, +25°C

μA VDD = 2.0V, -40°C to +85°C

μA VDD = 4.2V, -40°C to +85°C

PIC18LFXX2

Timer1 Oscillator

—

6.5

40

50

65

μA VDD = 4.2V, +25°C

μA VDD = 4.2V, -40°C to +85°C

μA VDD = 4.2V, -40°C to +125°C

PIC18FXX2

Legend: Shading of rows is to assist in readability of the table.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an

impact on the current consumption.

The test conditions for all IDD measurements in active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all

features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...).

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.

5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not additive.

Once one of these modules is enabled, the other may also be enabled without further penalty.

DS39564C-page 264

PIC18FXX2

22.2 DC Characteristics: PIC18FXX2 (Industrial, Extended)

PIC18LFXX2 (Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

DC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Max

Units

Conditions

VIL

Input Low Voltage

I/O ports:

with TTL buffer

D030

D030A

D031

Vss

—

0.15 VDD

0.8

V

VDD < 4.5V

4.5V ≤ VDD ≤ 5.5V

with Schmitt Trigger buffer

RC3 and RC4

Vss

0.2 VDD

0.3 VDD

V

D032

MCLR

VSS

0.2 VDD

0.3 VDD

V

D032A

OSC1 (in XT, HS and LP modes)

and T1OSI

D033

OSC1 (in RC and EC mode)⁽¹⁾

Input High Voltage

I/O ports:

VSS

0.2 VDD

V

VIH

D040

with TTL buffer

0.25 VDD +

0.8V

VDD

V

VDD < 4.5V

D040A

D041

2.0

4.5V ≤ VDD ≤ 5.5V

with Schmitt Trigger buffer

RC3 and RC4

0.8 VDD

0.7 VDD

VDD

V

D042

MCLR, OSC1 (EC mode)

0.8 VDD

0.7 VDD

VDD

V

D042A

OSC1 (in XT, HS and LP modes)

and T1OSI

D043

D060

OSC1 (RC mode)⁽¹⁾

Input Leakage Current^(2,3)

I/O ports

0.9 VDD

.02

VDD

1

V

IIL

μA VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

D061

D063

MCLR

—

1

μA Vss ≤ VPIN ≤ VDD

OSC1

IPU

Weak Pull-up Current

PORTB weak pull-up current

D070

IPURB

50

450

μA VDD = 5V, VPIN = VSS

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the

PICmicro device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Parameter is characterized but not tested.

DS39564C-page 265

PIC18FXX2

22.2 DC Characteristics: PIC18FXX2 (Industrial, Extended)

PIC18LFXX2 (Industrial) (Continued)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

Symbol

No.

Characteristic

Min

Max

Units

Conditions

VOL

VOH

VOD

Output Low Voltage

I/O ports

D080

—

0.6

V

IOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

IOL = 7.0 mA, VDD = 4.5V,

-40°C to +125°C

D080A

D083

OSC2/CLKO

(RC mode)

IOL = 1.6 mA, VDD = 4.5V,

-40°C to +85°C

D083A

IOL = 1.2 mA, VDD = 4.5V,

-40°C to +125°C

Output High Voltage⁽³⁾

D090

I/O ports

VDD – 0.7

—

V

IOH = -3.0 mA, VDD = 4.5V,

-40°C to +85°C

IOH = -2.5 mA, VDD = 4.5V,

-40°C to +125°C

D090A

D092

OSC2/CLKO

(RC mode)

—

IOH = -1.3 mA, VDD = 4.5V,

-40°C to +85°C

IOH = -1.0 mA, VDD = 4.5V,

-40°C to +125°C

D092A

D150

—

Open Drain High Voltage

8.5

RA4 pin

Capacitive Loading Specs

on Output Pins

D100⁽⁴⁾COSC2 OSC2 pin

15

pF In XT, HS and LP modes

when external clock is used

to drive OSC1

—

D101

D102

CIO

CB

All I/O pins and OSC2

(in RC mode)

—

50

pF To meet the AC Timing

Specifications

pF In I²C mode

SCL, SDA

400

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the

PICmicro device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Parameter is characterized but not tested.

DS39564C-page 266

PIC18FXX2

FIGURE 22-3:

LOW VOLTAGE DETECT CHARACTERISTICS

VDD

(LVDIF can be

cleared in software)

VLVD

(LVDIF set by hardware)

37

LVDIF

TABLE 22-1: LOW VOLTAGE DETECT CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

T ≥ 25°C

D420

VLVD

LVDVoltageonVDD LVV = 0001

1.98

2.18

2.37

2.48

2.67

2.77

2.98

3.27

3.47

3.57

3.76

3.96

4.16

4.45

2.06

2.27

2.47

2.58

2.78

2.89

3.1

2.14

2.36

2.57

2.68

2.89

3.01

3.22

3.55

3.75

3.87

4.08

4.3

V

transition high to

LVV = 0010

T ≥ 25°C

low

LVV = 0011

LVV = 0100

LVV = 0101

LVV = 0110

LVV = 0111

LVV = 1000

LVV = 1001

LVV = 1010

LVV = 1011

LVV = 1100

LVV = 1101

LVV = 1110

3.41

3.61

3.72

3.92

4.13

4.33

4.64

4.5

4.83

DS39564C-page 267

PIC18FXX2

TABLE 22-2: MEMORY PROGRAMMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

DC Characteristics

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

Sym

No.

Characteristic

Min

Typ†

Max Units

Conditions

Internal Program Memory

Programming Specifications

D110

D113

VPP

9.00

—

13.25

10

V

Voltage on MCLR/VPP pin

IDDP

mA

Supply Current during

Programming

Data EEPROM Memory

1M

—

D120

ED

Cell Endurance

100K

VMIN

E/W -40°C to +85°C

D121 VDRW VDD for Read/Write

5.5

V

Using EECON to read/write

VMIN = Minimum operating

voltage

—

D122 TDEW Erase/Write Cycle Time

D123 TRETD Characteristic Retention

4

ms

40

—

Year Provided no other

specifications are violated

D124

TREF

Number of Total Erase/Write

Cycles before Refresh⁽¹⁾

1M

10M

—

E/W -40°C to +85°C

Program FLASH Memory

Cell Endurance

—

D130

D131

EP

10K

100K

—

E/W -40°C to +85°C

VPR

VDD for Read

VMIN

5.5

V

VMIN = Minimum operating

voltage

—

D132

VIE

VDD for Block Erase

4.5

5.5

V

Using ICSP port

D132A VIW

VDD for Externally Timed Erase

or Write

—

D132B VPEW VDD for Self-timed Write

VMIN

5.5

V

VMIN = Minimum operating

voltage

—

1

—

D133

TIE

ICSP Block Erase Cycle Time

4

ms VDD ≥ 4.5V

—

D133A TIW

ICSP Erase or Write Cycle Time

(externally timed)

—

D133A TIW

Self-timed Write Cycle Time

2

ms

D134 TRETD Characteristic Retention

40

—

Year Provided no other

specifications are violated

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Refer to Section 6.8 for a more detailed discussion on data EEPROM endurance.

DS39564C-page 268

PIC18FXX2

22.3 AC (Timing) Characteristics

22.3.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created

following one of the following formats:

1. TppS2ppS

2. TppS

T

3. TCC:ST

4. Ts

(I²C specifications only)

F

Frequency

T

Time

Lowercase letters (pp) and their meanings:

pp

cc

ck

cs

di

CCP1

CLKO

CS

osc

rd

OSC1

RD

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O port

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

Fall

P

R

V

Z

Period

H

High

Rise

I

Invalid (Hi-impedance)

Low

Valid

L

Hi-impedance

I²C only

AA

output access

Bus free

High

Low

High

Low

BUF

TCC:ST (I²C specifications only)

CC

HD

Hold

SU

Setup

ST

DAT

STA

DATA input hold

START condition

STO

STOP condition

DS39564C-page 269

PIC18FXX2

22.3.2

TIMING CONDITIONS

The temperature and voltages specified in Table 22-3

apply to all timing specifications unless otherwise

noted. Figure 22-4 specifies the load conditions for the

timing specifications.

TABLE 22-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

AC CHARACTERISTICS

Operating voltage VDD range as described in DC spec Section 22.1 and

Section 22.2.

LC parts operate for industrial temperatures only.

FIGURE 22-4:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load condition 1 Load condition 2

VDD/2

CL

RL

VSS

CL

RL = 464Ω

CL = 50 pF for all pins except OSC2/CLKO

and including D and E outputs as ports

VSS

DS39564C-page 270

PIC18FXX2

22.3.3

TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 22-5:

EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

Q4

Q1

1

Q2

Q3

Q4

Q1

OSC1

CLKO

3

4

3

2

TABLE 22-4: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max

Units

Conditions

No.

1A

FOSC

External CLKI Frequency⁽¹⁾

Oscillator Frequency⁽¹⁾

DC

0.1

4

40

25

4

MHz EC, ECIO, -40°C to +85°C

MHz EC, ECIO, +85°C to +125°C

MHz RC osc

4

MHz XT osc

25

10

6.25

200

MHz HS osc

4

MHz HS + PLL osc, -40°C to +85°C

MHz HS + PLL osc, +85°C to +125°C

kHz LP Osc mode

4

5

External CLKI Period⁽¹⁾

Oscillator Period⁽¹⁾

25

40

—

ns

EC, ECIO, -40°C to +85°C

EC, ECIO, +85°C to +125°C

1

TOSC

250

40

—

10,000

250

ns

μs

RC osc

XT osc

HS osc

100

160

25

250

HS + PLL osc, -40°C to +85°C

HS + PLL osc, +85°C to +125°C

LP osc

250

—

2

3

TCY

Instruction Cycle Time⁽¹⁾

100

160

30

—

ns

μs

ns

TCY = 4/FOSC, -40°C to +85°C

TCY = 4/FOSC, +85°C to +125°C

TosL,

TosH

External Clock in (OSC1)

High or Low Time

—

XT osc

LP osc

HS osc

XT osc

LP osc

HS osc

2.5

10

—

4

TosR,

TosF

External Clock in (OSC1)

Rise or Fall Time

—

20

50

7.5

—

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations

except PLL. All specified values are based on characterization data for that particular oscillator type under

standard operating conditions with the device executing code. Exceeding these specified limits may result in

an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to

operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input

is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

DS39564C-page 271

PIC18FXX2

TABLE 22-5: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V)

Param

Sym

Characteristic

Min

Typ†

Max

Units Conditions

No.

—

FOSC Oscillator Frequency Range

4

—

10

40

2

MHz HS mode only

FSYS On-chip VCO System Frequency

16

—

-2

MHz HS mode only

t_rc

PLL Start-up Time (Lock Time)

ms

%

Δ^CLKCLKO Stability (Jitter)

+2

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

FIGURE 22-6:

CLKO AND I/O TIMING

Q1

Q2

Q3

Q4

OSC1

11

10

CLKO

13

14

12

19

18

16

I/O Pin

(input)

15

17

I/O Pin

(output)

New Value

Old Value

20, 21

Refer to Figure 22-4 for load conditions.

Note:

DS39564C-page 272

PIC18FXX2

TABLE 22-6: CLKO AND I/O TIMING REQUIREMENTS

Param.

Symbol

Characteristic

Min

Typ

Max

Units Conditions

No.

10

TosH2ckL OSC1↑ to CLKO↓

TosH2ckH OSC1↑ to CLKO↑

—

75

35

—

50

—

10

—

10

—

200

100

ns (Note 1)

11

—

12

TckR

TckF

CLKO rise time

CLKO fall time

—

13

—

14

TckL2ioV CLKO↓ to Port out valid

—

0.5 TCY + 20 ns (Note 1)

15

TioV2ckH Port in valid before CLKO ↑

TckH2ioI Port in hold after CLKO ↑

TosH2ioV OSC1↑ (Q1 cycle) to Port out valid

0.25 TCY + 25

—

ns (Note 1)

16

0

—

ns (Note 1)

17

150

—

ns

18

TosH2ioI OSC1↑ (Q2 cycle) to Port

PIC18FXXX

100

200

0

ns

input invalid (I/O in hold time)

18A

19

PIC18LFXXX

—

ns

TioV2osH Port input valid to OSC1↑ (I/O in setup time)

—

ns

20

TioR

Port output rise time

Port output fall time

INT pin high or low time

PIC18FXXX

PIC18LFXXX

PIC18FXXX

PIC18LFXXX

—

25

60

25

60

—

ns

20A

21

—

ns VDD = 2V

TioF

—

ns

21A

22††

23††

24††

—

ns VDD = 2V

TINP

TCY

20

ns

TRBP

TRCP

RB7:RB4 change INT high or low time

RC7:RC4 change INT high or low time

—

†† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.

FIGURE 22-7:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

31

34

I/O Pins

Note:

Refer to Figure 22-4 for load conditions.

DS39564C-page 273

PIC18FXX2

FIGURE 22-8:

BROWN-OUT RESET TIMING

BVDD

VDD

35

VBGAP = 1.2V

Typical

VIRVST

Enable Internal Reference Voltage

Internal Reference Voltage stable

36

TABLE 22-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

30

TmcL

TWDT

MCLR Pulse Width (low)

2

7

—

μs

31

Watchdog Timer Time-out Period

(No Postscaler)

18

33

ms

32

33

34

TOST

TPWRT

T^IOZ

Oscillation Start-up Timer Period

Power up Timer Period

1024 TOSC

—

72

2

1024 TOSC

—

ms

μs

TOSC = OSC1 period

28

—

132

—

I/O Hi-impedance from MCLR Low

or Watchdog Timer Reset

35

36

37

TBOR

TIVRST

TLVD

Brown-out Reset Pulse Width

200

—

20

—

500

—

μs VDD ≤ BVDD (see

D005)

Time for Internal Reference

Voltage to become stable

μs

Low Voltage Detect Pulse Width

200

μs VDD ≤ VLVD (see

D420)

DS39564C-page 274

PIC18FXX2

FIGURE 22-9:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

41

40

42

T1OSO/T1CKI

46

45

47

48

TMR0 or

TMR1

Note:

Refer to Figure 22-4 for load conditions.

TABLE 22-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No.

Symbol

Characteristic

T0CKI High Pulse Width

Min

Max Units

Conditions

40

Tt0H

No Prescaler

With Prescaler

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5TCY + 20

10

—

ns

41

42

Tt0L

Tt0P

T0CKI Low Pulse Width

T0CKI Period

0.5TCY + 20

10

TCY + 10

Greater of:

20 nS or TCY + 40

N

ns N = prescale

value

(1, 2, 4,..., 256)

45

46

Tt1H

Tt1L

T1CKI High

Time

Synchronous, no prescaler

0.5TCY + 20

—

ns

Synchronous,

with prescaler

PIC18FXXX

PIC18LFXXX

PIC18FXXX

PIC18LFXXX

10

25

Asynchronous

30

50

T1CKI Low

Time

Synchronous, no prescaler

0.5TCY + 5

Synchronous,

with prescaler

PIC18FXXX

10

25

30

50

PIC18LFXXX

PIC18FXXX

PIC18LFXXX

Asynchronous

47

48

Tt1P

Ft1

T1CKI input

period

Synchronous

Greater of:

20 nS or TCY + 40

N

ns N = prescale

value

(1, 2, 4, 8)

Asynchronous

60

DC

—

50

ns

kHz

—

T1CKI oscillator input frequency range

Tcke2tmrI Delay from external T1CKI clock edge to timer

increment

2 TOSC

7 TOSC

DS39564C-page 275

PIC18FXX2

FIGURE 22-10:

CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)

CCPx

(Capture Mode)

50

51

52

54

CCPx

(Compare or PWM Mode)

53

Refer to Figure 22-4 for load conditions.

Note:

TABLE 22-9: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)

Param.

Symbol

Characteristic

Min

Max

Units

Conditions

No.

50

TccL

CCPx input low No Prescaler

time

0.5 TCY + 20

—

ns

With

PIC18FXXX

PIC18LFXXX

10

Prescaler

20

51

TccH

CCPx input

high time

No Prescaler

0.5 TCY + 20

With

PIC18FXXX

10

20

Prescaler

PIC18LFXXX

52

53

TccP

TccR

CCPx input period

3 TCY + 40

N

N = prescale

value (1,4 or 16)

CCPx output fall time

PIC18FXXX

PIC18LFXXX

PIC18FXXX

PIC18LFXXX

—

25

60

25

60

ns

VDD = 2V

54

TccF

CCPx output fall time

DS39564C-page 276

PIC18FXX2

FIGURE 22-11:

PARALLEL SLAVE PORT TIMING (PIC18F4X2)

RE2/CS

RE0/RD

RE1/WR

65

RD7:RD0

62

64

63

Note:

Refer to Figure 22-4 for load conditions.

TABLE 22-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X2)

Param.

Symbol

Characteristic

Min

Max Units

Conditions

No.

62

TdtV2wrH Data in valid before WR↑ or CS↑

20

25

—

ns

(setup time)

ns Extended Temp. Range

63

64

TwrH2dtI

WR↑ or CS↑ to data–in invalid PIC18FXXX

(hold time)

20

35

—

ns

PIC18LFXXX

ns VDD = 2V

TrdL2dtV RD↓ and CS↓ to data–out valid

—

80

90

ns

ns Extended Temp. Range

65

66

TrdH2dtI

TibfINH

RD↑ or CS↓ to data–out invalid

10

—

30

ns

Inhibit of the IBF flag bit being cleared from

3 TCY

WR↑ or CS↑

DS39564C-page 277

PIC18FXX2

FIGURE 22-12:

EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

SS

70

SCK

(CKP = 0)

71

72

78

79

SCK

(CKP = 1)

78

80

bit6 - - - - - -1

bit6 - - - -1

MSb

LSb

SDO

SDI

75, 76

MSb In

74

LSb In

73

Note: Refer to Figure 22-4 for load conditions.

TABLE 22-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param.

Symbol

Characteristic

Min

Max Units Conditions

No.

70

TssL2scH, SS↓ to SCK↓ or SCK↑ input

TssL2scL

TCY

—

ns

71

TscH

SCK input high time

(Slave mode)

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

71A

72

40

1.25 TCY + 30

40

ns (Note 1)

TscL

SCK input low time

(Slave mode)

ns

72A

73

ns (Note 1)

TdiV2scH, Setup time of SDI data input to SCK edge

TdiV2scL

100

ns

73A

74

TB2B

Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40

—

ns (Note 2)

TscH2diL, Hold time of SDI data input to SCK edge

TscL2diL

100

ns

75

76

78

79

80

TdoR

TdoF

TscR

TscF

SDO data output rise time

PIC18FXXX

PIC18LFXXX

PIC18FXXX

PIC18LFXXX

PIC18FXXX

PIC18LFXXX

—

25

60

25

60

25

60

25

60

50

150

ns

ns VDD = 2V

SDO data output fall time

ns

ns VDD = 2V

ns

SCK output rise time

(Master mode)

ns VDD = 2V

ns

SCK output fall time (Master mode) PIC18FXXX

PIC18LFXXX

ns VDD = 2V

ns

TscH2doV, SDO data output valid after SCK PIC18FXXX

TscL2doV edge

PIC18LFXXX

ns VDD = 2V

Note 1: Requires the use of Parameter # 73A.

2: Only if Parameter # 71A and # 72A are used.

DS39564C-page 278

PIC18FXX2

FIGURE 22-13:

EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

SS

81

SCK

(CKP = 0)

71

72

79

78

73

SCK

(CKP = 1)

80

LSb

MSb

bit6 - - - - - -1

bit6 - - - -1

SDO

SDI

75, 76

MSb In

74

LSb In

Note: Refer to Figure 22-4 for load conditions.

TABLE 22-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Param.

Symbol

TscH

TscL

Characteristic

Min

Max Units Conditions

No.

71

SCK input high time

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

(Slave mode)

71A

72

40

1.25 TCY + 30

40

ns (Note 1)

SCK input low time

(Slave mode)

ns

72A

73

ns (Note 1)

TdiV2scH, Setup time of SDI data input to SCK edge

TdiV2scL

100

ns

73A

74

TB2B

Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40

—

ns (Note 2)

TscH2diL, Hold time of SDI data input to SCK edge

TscL2diL

100

ns

75

76

78

79

80

81

TdoR

TdoF

TscR

TscF

SDO data output rise time

PIC18FXXX

PIC18LFXXX

PIC18FXXX

PIC18LFXXX

—

TCY

25

60

25

60

25

60

25

60

50

150

—

ns

ns VDD = 2V

SDO data output fall time

ns

ns VDD = 2V

SCK output rise time (Master mode) PIC18FXXX

PIC18LFXXX

ns

ns VDD = 2V

SCK output fall time (Master mode) PIC18FXXX

PIC18LFXXX

ns

ns VDD = 2V

TscH2doV, SDO data output valid after SCK

TscL2doV edge

PIC18FXXX

ns

PIC18LFXXX

ns VDD = 2V

ns

TdoV2scH, SDO data output setup to SCK edge

TdoV2scL

Note 1: Requires the use of Parameter # 73A.

2: Only if Parameter # 71A and # 72A are used.

DS39564C-page 279

PIC18FXX2

FIGURE 22-14:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

SS

70

SCK

(CKP = 0)

83

71

72

78

79

SCK

(CKP = 1)

78

80

MSb

bit6 - - - - - -1

bit6 - - - -1

LSb

SDO

SDI

77

75, 76

MSb In

74

LSb In

73

Note:

Refer to Figure 22-4 for load conditions.

TABLE 22-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))

Param. No. Symbol

Characteristic

Min

Max Units Conditions

70

TssL2scH, SS↓ to SCK↓ or SCK↑ input

TCY

—

ns

TssL2scL

TscH

71

SCK input high time (Slave mode)

SCK input low time (Slave mode)

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

71A

72

40

1.25 TCY + 30

40

ns (Note 1)

TscL

ns

72A

73

ns (Note 1)

TdiV2scH, Setup time of SDI data input to SCK edge

TdiV2scL

100

ns

73A

74

TB2B

Last clock edge of Byte1 to the first clock edge of Byte2 1.5 TCY + 40

—

ns (Note 2)

TscH2diL, Hold time of SDI data input to SCK edge

TscL2diL

100

ns

75

76

TdoR

SDO data output rise time

PIC18FXXX

PIC18LFXXX

PIC18FXXX

PIC18LFXXX

—

25

60

25

60

ns

VDD = 2V

TdoF

SDO data output fall time

77

78

TssH2doZ SS↑ to SDO output hi-impedance

10

—

50

25

ns

TscR

SCK output rise time (Master mode)

PIC18FXXX

PIC18LFXXX

PIC18FXXX

PIC18LFXXX

60

VDD = 2V

79

80

83

TscF

SCK output fall time (Master mode)

25

60

TscH2doV, SDO data output valid after SCK edge PIC18FXXX

TscL2doV

50

PIC18LFXXX

150

TscH2ssH, SS ↑ after SCK edge

1.5 TCY + 40

—

ns

TscL2ssH

Note 1: Requires the use of Parameter # 73A.

2: Only if Parameter # 71A and # 72A are used.

DS39564C-page 280

PIC18FXX2

FIGURE 22-15:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

82

SS

70

SCK

83

(CKP = 0)

71

72

SCK

(CKP = 1)

80

MSb

bit6 - - - - - -1

bit6 - - - -1

LSb

SDO

SDI

75, 76

77

MSb In

74

LSb In

Note: Refer to Figure 22-4 for load conditions.

TABLE 22-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param. No.

70

Symbol

Characteristic

Min

Max Units Conditions

TssL2scH, SS↓ to SCK↓ or SCK↑ input

TCY

—

ns

TssL2scL

71

TscH

TscL

TB2B

SCK input high time

(Slave mode)

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

71A

72

40

1.25 TCY + 30

40

ns (Note 1)

ns

SCK input low time

(Slave mode)

72A

73A

74

ns (Note 1)

ns (Note 2)

ns

Last clock edge of Byte1 to the first clock edge of Byte2 1.5 TCY + 40

TscH2diL, Hold time of SDI data input to SCK edge

TscL2diL

100

75

76

TdoR

SDO data output rise time

PIC18FXXX

PIC18LFXXX

PIC18FXXX

PIC18LFXXX

—

25

60

25

60

ns

VDD = 2V

TdoF

SDO data output fall time

77

78

TssH2doZ SS↑ to SDO output hi-impedance

10

—

50

25

ns

TscR

SCK output rise time (Master mode) PIC18FXXX

PIC18LFXXX

60

VDD = 2V

79

80

82

83

TscF

SCK output fall time (Master mode)

PIC18FXXX

PIC18LFXXX

PIC18FXXX

PIC18LFXXX

25

60

TscH2doV, SDO data output valid after SCK

TscL2doV edge

50

150

TssL2doV SDO data output valid after SS↓ edge PIC18FXXX

PIC18LFXXX

—

50

ns

150

TscH2ssH, SS ↑ after SCK edge

1.5 TCY + 40

—

ns

TscL2ssH

Note 1: Requires the use of Parameter # 73A.

2: Only if Parameter # 71A and # 72A are used.

DS39564C-page 281

PIC18FXX2

FIGURE 22-16:

I²C BUS START/STOP BITS TIMING

SCL

SDA

91

93

90

92

STOP

Condition

START

Condition

Note: Refer to Figure 22-4 for load conditions.

TABLE 22-15: I²C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

Param.

Symbol

Characteristic

Min

Max

Units

Conditions

No.

90

TSU:STA START condition

Setup time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4700

600

—

ns

Only relevant for Repeated

START condition

91

92

93

THD:STA START condition

Hold time

4000

600

ns

After this period, the first

clock pulse is generated

TSU:STO STOP condition

Setup time

4700

600

THD:STO STOP condition

Hold time

4000

600

FIGURE 22-17:

I²C BUS DATA TIMING

103

102

100

101

SCL

90

106

107

91

92

SDA

In

110

109

SDA

Out

Note: Refer to Figure 22-4 for load conditions.

DS39564C-page 282

PIC18FXX2

TABLE 22-16: I²C BUS DATA REQUIREMENTS (SLAVE MODE)

Param.

No.

Symbol

Characteristic

100 kHz mode

Min

Max

Units

Conditions

Clock high time

4.0

—

μs

PIC18FXXX must operate at a

minimum of 1.5 MHz

100

THIGH

400 kHz mode

0.6

—

μs

PIC18FXXX must operate at a

minimum of 10 MHz

SSP Module

1.5 TCY

4.7

—

Clock low time

100 kHz mode

μs

PIC18FXXX must operate at a

minimum of 1.5 MHz

101

102

TLOW

400 kHz mode

1.3

—

PIC18FXXX must operate at a

minimum of 10 MHz

SSP Module

1.5 TCY

—

SDA and SCL rise

time

100 kHz mode

400 kHz mode

1000

300

ns

TR

20 + 0.1 CB

CB is specified to be from

10 to 400 pF

SDA and SCL fall

time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

—

1000

300

—

ns

μs

ns

μs

ns

μs

ns

μs

VDD ≥ 4.2V

103

90

TF

20 + 0.1 CB

START condition

setup time

4.7

0.6

4.0

0.6

0

Only relevant for Repeated

START condition

TSU:STA

THD:STA

THD:DAT

TSU:DAT

TSU:STO

TAA

—

START condition hold 100 kHz mode

time

—

After this period, the first clock

pulse is generated

91

400 kHz mode

—

Data input hold time

100 kHz mode

400 kHz mode

—

106

107

92

0

0.9

—

Data input setup time 100 kHz mode

400 kHz mode

250

100

4.7

0.6

—

(Note 2)

—

STOP condition

setup time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

—

Output valid from

clock

3500

—

(Note 1)

109

110

—

Bus free time

4.7

1.3

—

Time the bus must be free

before a new transmission can

start

TBUF

—

CB

Bus capacitive loading

—

400

pF

D102

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of

the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2

2: A Fast mode I C bus device can be used in a Standard mode I C bus system, but the requirement TSU:DAT ≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If

such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.

2

TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification) before the SCL line is

released.

DS39564C-page 283

PIC18FXX2

FIGURE 22-18:

MASTER SSP I²C BUS START/STOP BITS TIMING WAVEFORMS

SCL

SDA

93

91

90

92

STOP

Condition

START

Condition

Note: Refer to Figure 22-4 for load conditions.

TABLE 22-17: MASTER SSP I²C BUS START/STOP BITS REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max Units

Conditions

No.

90

TSU:STA START condition

Setup time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

2(TOSC)(BRG + 1)

—

ns Only relevant for

Repeated START

condition

91

92

93

THD:STA START condition

Hold time

100 kHz mode

2(TOSC)(BRG + 1)

ns After this period, the

first clock pulse is

generated

400 kHz mode

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

2(TOSC)(BRG + 1)

TSU:STO STOP condition

Setup time

100 kHz mode

2(TOSC)(BRG + 1)

ns

400 kHz mode

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

2(TOSC)(BRG + 1)

THD:STO STOP condition

Hold time

100 kHz mode

2(TOSC)(BRG + 1)

ns

400 kHz mode

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

2(TOSC)(BRG + 1)

Note 1: Maximum pin capacitance = 10 pF for all I²C pins.

FIGURE 22-19:

MASTER SSP I²C BUS DATA TIMING

103

102

100

101

SCL

90

106

91

92

107

SDA

In

110

109

SDA

Out

Note: Refer to Figure 22-4 for load conditions.

DS39564C-page 284

PIC18FXX2

TABLE 22-18: MASTER SSP I²C BUS DATA REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max Units

Conditions

No.

100

THIGH

Clock high time 100 kHz mode

400 kHz mode

2(TOSC)(BRG + 1)

—

ms

ns

2(TOSC)(BRG + 1)

1 MHz mode⁽¹⁾

2(TOSC)(BRG + 1)

—

101

102

TLOW

TR

Clock low time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

2(TOSC)(BRG + 1)

—

2(TOSC)(BRG + 1)

—

2(TOSC)(BRG + 1)

—

SDA and SCL

rise time

—

1000

300

1000

300

—

CB is specified to be from

10 to 400 pF

20 + 0.1 CB

ns

—

ns

103

90

TF

SDA and SCL

fall time

—

ns

VDD ≥ 4.2V

20 + 0.1 CB

ns

TSU:STA START condition 100 kHz mode

2(TOSC)(BRG + 1)

ms Only relevant for

setup time

Repeated START

condition

ms

400 kHz mode

1 MHz mode⁽¹⁾

2(TOSC)(BRG + 1)

—

ms

2(TOSC)(BRG + 1)

—

91

THD:STA START condition 100 kHz mode

2(TOSC)(BRG + 1)

—

ms After this period, the first

hold time

clock pulse is generated

400 kHz mode

2(TOSC)(BRG + 1)

—

ms

1 MHz mode⁽¹⁾

2(TOSC)(BRG + 1)

—

ms

ns

106

107

92

THD:DAT Data input

hold time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

0

—

0

0.9

—

ms

TSU:DAT Data input

setup time

250

ns

(Note 2)

100

—

TSU:STO STOP condition 100 kHz mode

2(TOSC)(BRG + 1)

—

ms

ns

setup time

400 kHz mode

1 MHz mode⁽¹⁾

2(TOSC)(BRG + 1)

—

2(TOSC)(BRG + 1)

—

109

TAA

Output validfrom 100 kHz mode

—

3500

1000

—

clock

400 kHz mode

1 MHz mode⁽¹⁾

ns

—

ns

110

TBUF

CB

Bus free time

100 kHz mode

400 kHz mode

4.7

1.3

—

ms Time the bus must be free

before a new transmission

—

ms

can start

pF

D102

Bus capacitive loading

—

400

Note 1: Maximum pin capacitance = 10 pF for all I²C pins.

2: A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but parameter #107 ≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL

signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the

SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line

is released.

DS39564C-page 285

PIC18FXX2

FIGURE 22-20:

USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

RC6/TX/CK

121

RC7/RX/DT

120

Note: Refer to Figure 22-4 for load conditions.

122

TABLE 22-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max

Units Conditions

No.

120

TckH2dtV SYNC XMIT (MASTER & SLAVE)

Clock high to data out valid

PIC18FXXX

PIC18LFXXX

PIC18FXXX

PIC18LFXXX

PIC18FXXX

PIC18LFXXX

—

50

150

25

ns

ns VDD = 2V

ns

121

122

Tckr

Tdtr

Clock out rise time and fall time

(Master mode)

60

ns VDD = 2V

ns

Data out rise time and fall time

25

60

ns VDD = 2V

FIGURE 22-21:

USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

RC6/TX/CK

125

RC7/RX/DT

126

Note: Refer to Figure 22-4 for load conditions.

TABLE 22-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max Units Conditions

No.

125

TdtV2ckl SYNC RCV (MASTER & SLAVE)

Data hold before CK ↓ (DT hold time)

10

15

20

—

ns

126

TckL2dtl Data hold after CK ↓ (DT hold time)

PIC18FXXX

PIC18LFXXX

VDD = 2V

DS39564C-page 286

PIC18FXX2

TABLE 22-21: A/D CONVERTER CHARACTERISTICS: PIC18FXX2 (INDUSTRIAL, EXTENDED)

PIC18LFXX2 (INDUSTRIAL)

Param

No.

Symbol

Characteristic

Resolution

Min

Typ

Max

Units

Conditions

A01

NR

—

10

< 1

bit

A03

A04

A05

A06

A10

EIL

Integral linearity error

Differential linearity error

Gain error

LSb VREF = VDD = 5.0V

EDL

EG

< 1

EOFF

Offset error

< 1.5

(2)

—

Monotonicity

guaranteed

—

VSS ≤ VAIN ≤ VREF

A20

A20A

VREF

Reference Voltage

(VREFH – VREFL)

1.8V

3V

—

V

VDD < 3.0V

VDD ≥ 3.0V

A21

A22

A25

A30

VREFH

VREFL

VAIN

Reference voltage High

Reference voltage Low

Analog input voltage

AVSS

—

AVDD + 0.3V

VREFH

V

AVSS – 0.3V

—

AVDD + 0.3V

2.5

VDD ≥ 2.5V (Note 3)

ZAIN

Recommended impedance of

analog voltage source

kΩ (Note 4)

A50

IREF

VREF input current (Note 1)

—

5

150

μA During VAIN acquisition

μA During A/D conversion cycle

Note 1: Vss ≤ VAIN ≤ VREF

2: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.

3: For VDD < 2.5V, VAIN should be limited to < .5 VDD.

4: Maximum allowed impedance for analog voltage source is 10 kΩ. This requires higher acquisition times.

FIGURE 22-22:

A/D CONVERSION TIMING

BSF ADCON0, GO

(Note 2)

131

130

Q4

132

A/D CLK

. . .

9

8

7

2

1

0

A/D DATA

ADRES

NEW_DATA

TCY

OLD_DATA

ADIF

GO

DONE

SAMPLING STOPPED

SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEPinstruction to be executed.

2: This is a minimal RC delay (typically 100 nS), which also disconnects the holding capacitor from the analog input.

DS39564C-page 287

PIC18FXX2

TABLE 22-22: A/D CONVERSION REQUIREMENTS

Param

Symbol

Characteristic

Min

Max

Units

Conditions

No.

130

TAD

A/D clock period

PIC18FXXX

1.6

2.0

11

20⁽⁴⁾

6.0

μs TOSC based

μs A/D RC mode

131

132

135

TCNV

TACQ

TSWC

Conversion time

(not including acquisition time) (Note 1)

Acquisition time (Note 2)

12

TAD

5

10

—

μs VREF = VDD = 5.0V

μs VREF = VDD = 2.5V

Switching Time from convert → sample

—

(Note 3)

Note 1: ADRES register may be read on the following TCY cycle.

2: The time for the holding capacitor to acquire the “New” input voltage, when the new input value has not

changed by more than 1 LSB from the last sampled voltage. The source impedance (RS) on the input channels

is 50Ω. See Section 17.0 for more information on acquisition time consideration.

3: On the next Q4 cycle of the device clock.

4: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

DS39564C-page 288

PIC18FXX2

23.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are

not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean - 3σ)

respectively, where σ is a standard deviation, over the whole temperature range.

FIGURE 23-1:

TYPICAL IDD vs. FOSC OVER VDD (HS MODE)

12

Typical:

statistical mean @ 25°C

5.5V

5.0V

4.5V

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

10

8

4.0V

3.5V

6

4

3.0V

2

2.5V

2.0V

0

4

6

8

10

12

14

16

18

20

22

24

26

FOSC (MHz)

FIGURE 23-2:

MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)

12

5.5V

Typical:

statistical mean @ 25°C

5.0V

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

10

8

4.5V

4.0V

3.5V

6

3.0V

4

2.5V

2

2.0V

0

4

6

8

10

12

14

16

18

20

22

24

26

FOSC (MHz)

DS39564C-page 289

PIC18FXX2

FIGURE 23-3:

TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE)

20

18

16

14

12

10

8

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

5.5V

5.0V

4.5V

4.2V

6

4

2

0

4

5

6

7

8

9

10

FOSC (MHz)

FIGURE 23-4:

MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE)

20

18

16

14

12

10

8

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

5.5V

5.0V

4.5V

4.2V

6

4

2

0

4

5

6

7

8

9

10

FOSC (MHz)

DS39564C-page 290

PIC18FXX2

FIGURE 23-5:

TYPICAL IDD vs. FOSC OVER VDD (XT MODE)

2,000

1,800

1,600

1,400

1,200

1,000

800

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

600

400

200

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

FOSC (MHz)

FIGURE 23-6:

MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)

2,000

1,800

1,600

1,400

1,200

1,000

800

5.5V

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

600

400

200

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

FOSC (MHz)

DS39564C-page 291

PIC18FXX2

FIGURE 23-7:

TYPICAL IDD vs. FOSC OVER VDD (LP MODE)

100

90

80

70

60

50

40

30

20

10

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

0

20

30

40

50

60

70

80

90

100

FOSC (kHz)

FIGURE 23-8:

MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)

140

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

5.5V

120

100

80

5.0V

4.5V

4.0V

3.5V

60

3.0V

2.5V

2.0V

40

20

0

20

30

40

50

60

70

80

90

100

FOSC (kHz)

DS39564C-page 292

PIC18FXX2

FIGURE 23-9:

TYPICAL IDD vs. FOSC OVER VDD (EC MODE)

16

Typical:

statistical mean @ 25°C

5.5V

5.0V

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

14

12

10

8

4.5V

4.2V

4.0V

6

3.5V

4

3.0V

2

2.5V

2.0V

0

4

8

12

16

20

24

28

32

36

40

FOSC (MHz)

FIGURE 23-10:

MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)

16

Typical:

statistical mean @ 25°C

5.5V

5.0V

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

14

12

10

8

4.5V

4.2V

4.0V

3.5V

6

4

3.0V

2

2.5V

2.0V

0

4

8

12

16

20

24

28

32

36

40

FOSC (MHz)

DS39564C-page 293

PIC18FXX2

FIGURE 23-11:

TYPICAL AND MAXIMUM IDD vs. VDD

(TIMER1 AS MAIN OSCILLATOR, 32.768 kHz, C1 AND C2 = 47 pF)

180

160

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-10°C to 70°C)

Minimum: mean – 3σ (-10°C to 70°C)

140

120

100

80

Max (+70°C)

Max (70C)

60

Typ (+25°C)

Typ (25C)

40

20

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 23-12:

AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R

(RC MODE, C = 20 pF, +25°C)

4,500

4,000

3,500

3,000

2,500

2,000

1,500

1,000

500

Operation above 4 MHz is not recommended.

Ω

3.3k

Ω

5.1k

Ω

10k

Ω

100k

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS39564C-page 294

PIC18FXX2

FIGURE 23-13:

AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R

(RC MODE, C = 100 pF, +25°C)

2,000

1,800

1,600

1,400

1,200

1,000

800

Ω

3.3k

Ω

5.1k

600

Ω

10k

400

200

Ω

100k

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 23-14:

AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R

(RC MODE, C = 300 pF, +25°C)

800

700

600

500

400

300

200

100

Ω

3.3k

5.1k

Ω

10k

Ω

100k

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS39564C-page 295

PIC18FXX2

FIGURE 23-15:

IPD vs. VDD, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED)

100

Max

(-40°C to +125°C)

10

Max

(+85°C)

1

Typ (+25°C)

0.1

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

0.01

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 23-16:

ΔIBOR vs. VDD OVER TEMPERATURE (BOR ENABLED, VBOR = 2.00 - 2.16V)

90

80

70

60

50

40

30

20

10

Max (+125°C)

Max (125C)

Device

Held in

RESET

Reset

Max (+85°C)

Max (85C)

TTypyp(+(2255C°C) )

Device

in

SLEEP

Sleep

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS39564C-page 296

PIC18FXX2

FIGURE 23-17:

TYPICAL AND MAXIMUM ΔITMR1 vs. VDD OVER TEMPERATURE (-10°C TO +70°C,

TIMER1 WITH OSCILLATOR, XTAL = 32 kHz, C1 AND C2 = 47 pF)

14

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-10°C to 70°C)

Minimum: mean – 3σ (-10°C to 70°C)

12

10

8

MMaaxx(+(7700C°C) )

Typ (+25°C)

Typ (25C)

6

4

2

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 23-18:

TYPICAL AND MAXIMUM ΔIWDT vs. VDD OVER TEMPERATURE (WDT ENABLED)

70

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

60

50

40

30

20

10

0

Max (+125°C)

Max (125C)

Max (+85°C)

Max (85C)

Typ (+25°C)

Typ (25C)

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS39564C-page 297

PIC18FXX2

FIGURE 23-19:

TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40°C TO +125°C)

50

Typical:

statistical mean @ 25°C

45

40

35

30

25

20

15

10

5

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

Max

(+125°C)

(125C)

Max

MAX

(+85°C)

(85C)

Typ

(+25°C)

(25C)

Min

(-40°C)

(-40C)

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 23-20:

ΔILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 4.5 - 4.78V)

90

80

70

60

50

40

30

20

10

Max (+125°C)

Max (125C)

Max (+125°C)

Max (125C)

Typ (+25°C)

Typ (25C)

TTyypp((+2255C°)C)

LVDIF can be

cleared by

firmware

LVDIF state

is unknown

LVDIF is set

by hardware

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS39564C-page 298

PIC18FXX2

FIGURE 23-21:

TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C)

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

Max

Typ (+25°C)

Typ (25C)

Min

0.0

0

5

10

15

20

25

IOH (-mA)

FIGURE 23-22:

TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C)

3.0

2.5

2.0

1.5

1.0

0.5

Max

Typ (+25°C)

Typ (25C)

Min

0.0

0

5

10

15

20

25

IOH (-mA)

DS39564C-page 299

PIC18FXX2

FIGURE 23-23:

TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C)

1.8

1.6

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Max

TyTpy(p+(2255°CC))

0

5

10

15

20

25

IOL (-mA)

FIGURE 23-24:

TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C)

2.5

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

2.0

1.5

1.0

0.5

0.0

Max

Typ (+25°C)

Typ (25C)

0

5

10

15

20

25

IOL (-mA)

DS39564C-page 300

PIC18FXX2

FIGURE 23-25:

MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C)

4.0

Typical:

statistical mean @ 25°C

VIH Max

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

VIH Min

VIL Max

VIL Min

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 23-26:

MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40°C TO +125°C)

1.6

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

VTH (Max)

VTH (Min)

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS39564C-page 301

PIC18FXX2

FIGURE 23-27:

MINIMUM AND MAXIMUM VIN vs. VDD (I²C INPUT, -40°C TO +125°C)

3.5

VIH Max

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Minimum: mean – 3σ (-40°C to 125°C)

VILMax

VIH Min

VIL Min

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 23-28:

A/D NON-LINEARITY vs. VREFH (VDD = VREFH, -40°C TO +125°C)

4

3.5

3

-40°C

-40C

+25°C

25C

2.5

2

+85°C

85C

1.5

1

0.5

0

+125°C

125C

2

2.5

3

3.5

4

4.5

5

5.5

VDD and VREFH (V)

DS39564C-page 302

PIC18FXX2

FIGURE 23-29:

A/D NON-LINEARITY vs. VREFH (VDD = 5V, -40°C TO +125°C)

3

2.5

2

1.5

1

Max (-40°C to +125°C)

Max (-40C to 125C)

TTyypp((+2255C°)C)

0.5

0

2

2.5

3

3.5

4

4.5

5

5.5

VREFH (V)

DS39564C-page 303

PIC18FXX2

NOTES:

DS39564C-page 304

PIC18FXX2

24.0 PACKAGING INFORMATION

24.1 Package Marking Information

28-Lead SPDIP

Example

e

3

PIC18F242-I/SP

0610017

XXXXXXXXXXXXXXXXX

YYWWNNN

28-Lead SOIC

Example

e

3

XXXXXXXXXXXXXXXXXXXX

PIC18F242-E/SO

0610017

YYWWNNN

40-Lead PDIP

Example

XXXXXXXXXXXXXXXXXX

YYWWNNN

e3

PIC18F442-I/P

0610017

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

e

3

*

)

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS39564C-page 305

PIC18FXX2

Package Marking Information (Cont’d)

44-Lead TQFP

Example

-E/PT

XXXXXXXXXX

YYWWNNN

PIC18F452

e

3

0610017

44-Lead PLCC

Example

XXXXXXXXXX

YYWWNNN

PIC18F442

3

e

-I/L

0610017

DS39564C-page 306

PIC18FXX2

24.2 Package Details

The following sections give the technical details of the packages.

28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E1

D

2

n

1

α

E

A2

L

A

c

B1

β

A1

eB

B

p

Units

INCHES

*

MILLIMETERS

Dimension Limits

MIN

NOM

28

MAX

MIN

NOM

28

MAX

n

p

Number of Pins

Pitch

.100

2.54

Top to Seating Plane

A

.140

.150

.130

.160

3.56

3.18

3.81

3.30

4.06

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.125

.015

.300

.275

1.345

.125

.008

.040

.016

.320

.135

3.43

0.38

7.62

6.99

34.16

3.18

0.20

1.02

0.41

8.13

5

.310

.285

1.365

.130

.012

.053

.019

.350

10

.325

.295

1.385

.135

.015

.065

.022

.430

15

7.87

7.24

34.67

3.30

0.29

1.33

0.48

8.89

10

8.26

7.49

35.18

3.43

0.38

1.65

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

5

β

5

10

15

5

10

15

*

Controlling Parameter

§

Significant Characteristic

Notes:

Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MO-095

Drawing No. C04-070

DS39564C-page 307

PIC18FXX2

28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

E1

p

D

B

2

n

1

h

α

45°

c

A2

A

φ

β

L

A1

Units

INCHES*

MILLIMETERS

Dimension Limits

MIN

NOM

28

MAX

MIN

NOM

28

MAX

n

p

Number of Pins

Pitch

.050

1.27

Overall Height

A

.093

.099

.091

.008

.407

.295

.704

.020

.033

4

.104

2.36

2.50

2.31

0.20

10.34

7.49

17.87

0.50

0.84

4

2.64

Molded Package Thickness

Standoff

A2

A1

E

.088

.004

.394

.288

.695

.010

.016

0

.094

.012

.420

.299

.712

.029

.050

8

2.24

0.10

10.01

7.32

17.65

0.25

0.41

0

2.39

0.30

10.67

7.59

18.08

0.74

1.27

8

§

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

c

Foot Angle Top

Lead Thickness

Lead Width

.009

.014

0

.011

.017

12

.013

.020

15

0.23

0.36

0

0.28

0.42

12

0.33

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-052

DS39564C-page 308

PIC18FXX2

40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E1

D

2

1

α

n

E

A2

A

L

c

B1

B

β

A1

p

eB

Units

INCHES*

NOM

40

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

40

MAX

n

p

Number of Pins

Pitch

.100

2.54

Top to Seating Plane

A

.160

.175

.190

.160

4.06

3.56

4.45

3.81

4.83

4.06

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.140

.015

.595

.530

2.045

.120

.008

.030

.014

.620

5

.150

0.38

15.11

13.46

51.94

3.05

0.20

0.76

0.36

15.75

5

.600

.545

2.058

.130

.012

.050

.018

.650

10

.625

.560

2.065

.135

.015

.070

.022

.680

15

15.24

13.84

52.26

3.30

0.29

1.27

0.46

16.51

10

15.88

14.22

52.45

3.43

0.38

1.78

0.56

17.27

15

E1

D

Tip to Seating Plane

Lead Thickness

Upper Lead Width

L

c

B1

B

eB

α

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

§

β

Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

Notes:

5

10

15

5

10

15

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MO-011

Drawing No. C04-016

DS39564C-page 309

PIC18FXX2

44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

E1

#leads=n1

p

D1

D

2

1

B

n

CH x 45°

α

A

c

φ

β

A1

A2

L

F

Units

Dimension Limits

INCHES

NOM

44

MILLIMETERS

*

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

44

.031

11

0.80

11

Pins per Side

n1

A

Overall Height

.039

.043

.039

.004

.024

.039 REF.

3.5

.047

1.00

1.10

1.20

Molded Package Thickness

Standoff

A2

A1

L

.037

.002

.018

.041

.006

.030

0.95

0.05

0.45

1.00

0.10

0.60

1.05

0.15

0.75

Foot Length

Footprint (Reference)

Foot Angle

F

φ

1.00 REF.

3.5

12.00

0

7

0

7

Overall Width

E

D

.463

.390

.004

.012

.025

.472

.394

.006

.015

.035

10

.482

.398

.008

.017

.045

11.75

9.90

0.09

0.30

0.64

12.25

10.10

0.20

Overall Length

12.00

10.00

0.15

0.38

0.89

10

Molded Package Width

Molded Package Length

Lead Thickness

Lead Width

E1

D1

c

B

CH

α

0.44

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

1.14

5

15

5

15

β

5

10

5

10

*

Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

REF: Reference Dimension, usually without tolerance, for information purposes only.

See ASME Y14.5M

JEDEC Equivalent: MS-026

Revised 07-22-05

Drawing No. C04-076

DS39564C-page 310

PIC18FXX2

44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

E1

#leads=n1

D

D1

n 1 2

CH2 x 45°

CH1 x 45°

α

A3

A2

A

35°

B1

B

c

A1

β

p

E2

D2

Units

INCHES*

NOM

44

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

44

MAX

n

p

Number of Pins

Pitch

.050

1.27

11

Pins per Side

Overall Height

n1

A

11

.173

.153

.028

.029

.045

.005

.690

.653

.620

.011

.029

.020

5

.165

.145

.020

.024

.040

.000

.685

.650

.590

.008

.026

.013

0

.180

4.19

3.68

0.51

0.61

1.02

0.00

17.40

16.51

14.99

0.20

0.66

0.33

0

4.39

3.87

0.71

0.74

1.14

0.13

17.53

16.59

15.75

0.27

0.74

0.51

5

4.57

Molded Package Thickness

A2

A1

A3

CH1

CH2

E

.160

.035

.034

.050

.010

.695

.656

.630

.013

.032

.021

10

4.06

0.89

0.86

1.27

0.25

17.65

16.66

16.00

0.33

0.81

0.53

10

Standoff

§

Side 1 Chamfer Height

Corner Chamfer 1

Corner Chamfer (others)

Overall Width

Overall Length

D

Molded Package Width

Molded Package Length

Footprint Width

E1

D1

E2

D2

c

Footprint Length

Lead Thickness

Upper Lead Width

Lower Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

B1

B

α

β

0

5

10

0

5

10

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MO-047

Drawing No. C04-048

DS39564C-page 311

PIC18FXX2

NOTES:

DS39564C-page 312

PIC18FXX2

APPENDIX A: REVISION HISTORY

APPENDIX B: DEVICE

DIFFERENCES

Revision A (June 2001)

The differences between the devices listed in this data

sheet are shown in Table B-1.

Original data sheet for the PIC18FXX2 family.

Revision B (August 2002)

This revision includes the DC and AC Characteristics

Graphs and Tables. The Electrical Specifications in

Section 22.0 have been updated and there have been

minor corrections to the data sheet text.

Revision C (October 2006)

Packaging diagrams updated.

TABLE B-1:

DEVICE DIFFERENCES

Feature

PIC18F242

PIC18F252

PIC18F442

PIC18F452

Program Memory (Kbytes)

Data Memory (Bytes)

A/D Channels

16

768

5

32

1536

5

16

768

8

32

1536

8

Parallel Slave Port (PSP)

No

Yes

40-pin DIP

44-pin PLCC

44-pin TQFP

40-pin DIP

44-pin PLCC

44-pin TQFP

28-pin DIP

28-pin SOIC

28-pin DIP

28-pin SOIC

Package Types

DS39564C-page 313

PIC18FXX2

APPENDIX C: CONVERSION

APPENDIX D: MIGRATION FROM

BASELINE TO

CONSIDERATIONS

ENHANCED DEVICES

This appendix discusses the considerations for con-

verting from previous versions of a device to the ones

listed in this data sheet. Typically, these changes are

due to the differences in the process technology used.

An example of this type of conversion is from a

PIC16C74A to a PIC16C74B.

This section discusses how to migrate from a Baseline

device (i.e., PIC16C5X) to an Enhanced MCU device

(i.e., PIC18FXXX).

The following are the list of modifications over the

PIC16C5X microcontroller family:

Not Applicable

Not Currently Available

DS39564C-page 314

PIC18FXX2

APPENDIX E: MIGRATION FROM

MID-RANGE TO

APPENDIX F: MIGRATION FROM

HIGH-END TO

ENHANCED DEVICES

A detailed discussion of the differences between the

mid-range MCU devices (i.e., PIC16CXXX) and the

enhanced devices (i.e., PIC18FXXX) is provided in

AN716, “Migrating Designs from PIC16C74A/74B to

PIC18F442”. The changes discussed, while device

specific, are generally applicable to all mid-range to

enhanced device migrations.

A detailed discussion of the migration pathway and dif-

ferences between the high-end MCU devices (i.e.,

PIC17CXXX) and the enhanced devices (i.e.,

PIC18FXXX) is provided in AN726, “PIC17CXXX to

PIC18FXXX Migration”. This Application Note is

available as Literature Number DS00726.

This Application Note is available as Literature Number

DS00716.

DS39564C-page 315

PIC18FXX2

NOTES:

DS39564C-page 316

PIC18FXX2

INDEX

Block Diagrams

A

A/D Converter .......................................................... 183

Analog Input Model .................................................. 184

Baud Rate Generator .............................................. 151

Capture Mode Operation ......................................... 119

Compare Mode Operation ....................................... 120

Low Voltage Detect

A/D ................................................................................... 181

A/D Converter Flag (ADIF Bit) ................................. 183

A/D Converter Interrupt, Configuring ....................... 184

Acquisition Requirements ........................................ 184

ADCON0 Register .................................................... 181

ADCON1 Register .................................................... 181

ADRESH Register .................................................... 181

ADRESH/ADRESL Registers .................................. 183

ADRESL Register .................................................... 181

Analog Port Pins ................................................ 99, 100

Analog Port Pins, Configuring .................................. 186

Associated Registers ............................................... 188

Configuring the Module ............................................ 184

Conversion Clock (TAD) ........................................... 186

Conversion Status (GO/DONE Bit) .......................... 183

Conversions ............................................................. 187

Converter Characteristics ........................................ 287

Equations

External Reference Source ............................. 190

Internal Reference Source ............................... 190

MSSP

2

I C Mode ......................................................... 134

MSSP (SPI Mode) ................................................... 125

On-Chip Reset Circuit ................................................ 25

Parallel Slave Port (PORTD and PORTE) ............... 100

PIC18F2X2 .................................................................. 8

PIC18F4X2 .................................................................. 9

PLL ............................................................................ 19

PORTC (Peripheral Output Override) ........................ 93

PORTD (I/O Mode) .................................................... 95

PORTE (I/O Mode) .................................................... 97

PWM Operation (Simplified) .................................... 122

RA3:RA0 and RA5 Port Pins ..................................... 87

RA4/T0CKI Pin .......................................................... 88

RA6 Pin ..................................................................... 88

RB2:RB0 Port Pins .................................................... 91

RB3 Pin ..................................................................... 91

RB7:RB4 Port Pins .................................................... 90

Table Read Operation ............................................... 55

Table Write Operation ................................................ 56

Table Writes to FLASH Program Memory ................. 61

Timer0 in 16-bit Mode .............................................. 104

Timer0 in 8-bit Mode ................................................ 104

Timer1 ..................................................................... 108

Timer1 (16-bit R/W Mode) ....................................... 108

Timer2 ..................................................................... 112

Timer3 ..................................................................... 114

Timer3 (16-bit R/W Mode) ....................................... 114

USART

Acquisition Time ............................................... 185

Minimum Charging Time .................................. 185

Examples

Calculating the Minimum Required

Acquisition Time ...................................... 185

Result Registers ....................................................... 187

Special Event Trigger (CCP) ............................ 120, 188

TAD vs. Device Operating Frequencies .................... 186

Use of the CCP2 Trigger .......................................... 188

Absolute Maximum Ratings ............................................. 259

AC (Timing) Characteristics ............................................. 269

Load Conditions for Device Timing

Specifications ................................................... 270

Parameter Symbology ............................................. 269

Temperature and Voltage Specifications - AC ......... 270

Timing Conditions .................................................... 270

ACKSTAT Status Flag ..................................................... 155

ADCON0 Register ............................................................ 181

GO/DONE Bit ........................................................... 183

ADCON1 Register ............................................................ 181

ADDLW ............................................................................ 217

ADDWF ............................................................................ 217

ADDWFC ......................................................................... 218

ADRESH Register ............................................................ 181

ADRESH/ADRESL Registers ........................................... 183

ADRESL Register ............................................................ 181

Analog-to-Digital Converter. See A/D

Asynchronous Receive .................................... 174

Asynchronous Transmit ................................... 172

Watchdog Timer ...................................................... 204

BN .................................................................................... 220

BNC ................................................................................. 221

BNN ................................................................................. 221

BNOV ............................................................................... 222

BNZ .................................................................................. 222

BOR. See Brown-out Reset

ANDLW ............................................................................ 218

ANDWF ............................................................................ 219

Assembler

BOV ................................................................................. 225

BRA ................................................................................. 223

BRG. See Baud Rate Generator

MPASM Assembler .................................................. 253

Brown-out Reset (BOR) ..................................................... 26

BSF .................................................................................. 223

BTFSC ............................................................................. 224

BTFSS ............................................................................. 224

BTG ................................................................................. 225

Bus Collision During a STOP Condition .......................... 163

BZ .................................................................................... 226

B

Baud Rate Generator ....................................................... 151

BC .................................................................................... 219

BCF .................................................................................. 220

BF Status Flag ................................................................. 155

DS39564C-page 317

PIC18FXX2

C

D

CALL ................................................................................226

Capture (CCP Module) .....................................................119

Associated Registers ...............................................121

CCP Pin Configuration .............................................119

CCPR1H:CCPR1L Registers ...................................119

Software Interrupt .....................................................119

Timer1/Timer3 Mode Selection ................................119

Capture/Compare/PWM (CCP) ........................................117

Capture Mode. See Capture

Data EEPROM Memory

Associated Registers ................................................. 69

EEADR Register ........................................................ 65

EECON1 Register ...................................................... 65

EECON2 Register ...................................................... 65

Operation During Code Protect ................................. 68

Protection Against Spurious Write ............................. 68

Reading ..................................................................... 67

Using .......................................................................... 68

Write Verify ................................................................ 68

Writing ........................................................................ 67

Data Memory ..................................................................... 42

General Purpose Registers ....................................... 42

Map for PIC18F242/442 ............................................ 43

Map for PIC18F252/452 ............................................ 44

Special Function Registers ........................................ 42

DAW ................................................................................ 230

DC and AC Characteristics

CCP1 ........................................................................118

CCPR1H Register ............................................118

CCPR1L Register ............................................118

CCP2 ........................................................................118

CCPR2H Register ............................................118

CCPR2L Register ............................................118

Compare Mode. See Compare

Interaction of Two CCP Modules .............................118

PWM Mode. See PWM

Timer Resources ......................................................118

Clocking Scheme/Instruction Cycle ....................................39

CLRF ................................................................................227

CLRWDT ..........................................................................227

Code Examples

Graphs and Tables .................................................. 289

DC Characteristics ....................................................261, 265

DCFSNZ .......................................................................... 231

DECF ............................................................................... 230

DECFSZ .......................................................................... 231

Development Support ...................................................... 253

Device Differences ........................................................... 313

Device Overview .................................................................. 7

Features ....................................................................... 7

Direct Addressing ............................................................... 51

Example ..................................................................... 49

16 x 16 Signed Multiply Routine .................................72

16 x 16 Unsigned Multiply Routine .............................72

8 x 8 Signed Multiply Routine .....................................71

8 x 8 Unsigned Multiply Routine .................................71

Changing Between Capture Prescalers ...................119

Data EEPROM Read .................................................67

Data EEPROM Refresh Routine ................................68

Data EEPROM Write ..................................................67

Erasing a FLASH Program Memory Row ..................60

Fast Register Stack ....................................................39

How to Clear RAM (Bank1) Using

Indirect Addressing ............................................50

Initializing PORTA ......................................................87

Initializing PORTB ......................................................90

Initializing PORTC ......................................................93

Initializing PORTD ......................................................95

Initializing PORTE ......................................................97

Loading the SSPBUF (SSPSR) Register .................128

Reading a FLASH Program Memory Word ................59

Saving STATUS, WREG and BSR

E

Electrical Characteristics .................................................. 259

Errata ................................................................................... 5

F

Firmware Instructions ....................................................... 211

FLASH Program Memory ................................................... 55

Associated Registers ................................................. 63

Control Registers ....................................................... 56

Erase Sequence ........................................................ 60

Erasing ....................................................................... 60

Operation During Code Protect ................................. 63

Reading ..................................................................... 59

TABLAT Register ....................................................... 58

Table Pointer ............................................................. 58

Boundaries Based on Operation ........................ 58

Table Pointer Boundaries .......................................... 58

Table Reads and Table Writes .................................. 55

Block Diagrams

Registers in RAM ...............................................85

Writing to FLASH Program Memory ..................... 62–63

Code Protection ...............................................................195

COMF ...............................................................................228

Compare (CCP Module) ...................................................120

Associated Registers ...............................................121

CCP Pin Configuration .............................................120

CCPR1 Register .......................................................120

Software Interrupt .....................................................120

Special Event Trigger ........................109, 115, 120, 188

Timer1/Timer3 Mode Selection ................................120

Configuration Bits .............................................................195

Context Saving During Interrupts .......................................85

Conversion Considerations ..............................................314

CPFSEQ ..........................................................................228

CPFSGT ...........................................................................229

CPFSLT ...........................................................................229

Reads from FLASH Program Memory ....... 59

Writing to .................................................................... 61

Protection Against Spurious Writes ................... 63

Unexpected Termination .................................... 63

Write Verify ........................................................ 63

G

General Call Address Support ......................................... 148

GOTO .............................................................................. 232

DS39564C-page 318

PIC18FXX2

Instruction Set .................................................................. 211

ADDLW .................................................................... 217

ADDWF .................................................................... 217

ADDWFC ................................................................. 218

ANDLW .................................................................... 218

ANDWF .................................................................... 219

BC ............................................................................ 219

BCF ......................................................................... 220

BN ............................................................................ 220

BNC ......................................................................... 221

BNN ......................................................................... 221

BNOV ...................................................................... 222

BNZ ......................................................................... 222

BOV ......................................................................... 225

BRA ......................................................................... 223

BSF .......................................................................... 223

BTFSC ..................................................................... 224

BTFSS ..................................................................... 224

BTG ......................................................................... 225

BZ ............................................................................ 226

CALL ........................................................................ 226

CLRF ....................................................................... 227

CLRWDT ................................................................. 227

COMF ...................................................................... 228

CPFSEQ .................................................................. 228

CPFSGT .................................................................. 229

CPFSLT ................................................................... 229

DAW ........................................................................ 230

DCFSNZ .................................................................. 231

DECF ....................................................................... 230

DECFSZ .................................................................. 231

GOTO ...................................................................... 232

INCF ........................................................................ 232

INCFSZ .................................................................... 233

INFSNZ .................................................................... 233

IORLW ..................................................................... 234

IORWF ..................................................................... 234

LFSR ....................................................................... 235

MOVF ...................................................................... 235

MOVFF .................................................................... 236

MOVLB .................................................................... 236

MOVLW ................................................................... 237

MOVWF ................................................................... 237

MULLW .................................................................... 238

MULWF .................................................................... 238

NEGF ....................................................................... 239

NOP ......................................................................... 239

POP ......................................................................... 240

PUSH ....................................................................... 240

RCALL ..................................................................... 241

RESET ..................................................................... 241

RETFIE .................................................................... 242

RETLW .................................................................... 242

RETURN .................................................................. 243

RLCF ....................................................................... 243

RLNCF ..................................................................... 244

RRCF ....................................................................... 244

RRNCF .................................................................... 245

SETF ....................................................................... 245

SLEEP ..................................................................... 246

SUBFWB ................................................................. 246

SUBLW .................................................................... 247

SUBWF .................................................................... 247

SUBWFB ................................................................. 248

SWAPF .................................................................... 248

I

I/O Ports ............................................................................. 87

2

I C (MSSP Module)

ACK Pulse ................................................................ 139

Read/Write Bit Information (R/W Bit) ....................... 139

2

I C (SSP Module)

ACK Pulse ................................................................ 138

2

I C Master Mode Reception ............................................. 155

2

I C Mode

Clock Stretching ....................................................... 144

2

I C Mode (MSSP Module) ................................................ 134

Registers .................................................................. 134

2

I C Module

ACK Pulse ........................................................ 138, 139

Acknowledge Sequence Timing ............................... 158

Baud Rate Generator ............................................... 151

Bus Collision

Repeated START Condition ............................ 162

START Condition ............................................. 160

Clock Arbitration ....................................................... 152

Effect of a RESET .................................................... 159

General Call Address Support ................................. 148

Master Mode ............................................................ 149

Operation ......................................................... 150

Repeated START Condition Timing ................. 154

Master Mode START Condition ............................... 153

Master Mode Transmission ...................................... 155

Multi-Master Communication, Bus Collision

and Arbitration .................................................. 159

Multi-Master Mode ................................................... 159

Operation ................................................................. 138

Read/Write Bit Information (R/W Bit) ............... 138, 139

Serial Clock (RC3/SCK/SCL) ................................... 139

Slave Mode .............................................................. 138

Addressing ....................................................... 138

Reception ......................................................... 139

Transmission .................................................... 139

Slave Mode Timing (10-bit Reception,

SEN = 0) .......................................................... 142

Slave Mode Timing (10-bit Reception,

SEN = 1) .......................................................... 147

Slave Mode Timing (10-bit Transmission) ................ 143

Slave Mode Timing (7-bit Reception,

SEN = 0) .......................................................... 140

Slave Mode Timing (7-bit Reception,

SEN = 1) .......................................................... 146

Slave Mode Timing (7-bit Transmission) .................. 141

SLEEP Operation ..................................................... 159

STOP Condition Timing ........................................... 158

ICEPIC In-Circuit Emulator .............................................. 254

ID Locations ............................................................. 195, 210

INCF ................................................................................. 232

INCFSZ ............................................................................ 233

In-Circuit Debugger .......................................................... 210

In-Circuit Serial Programming (ICSP) ...................... 195, 210

Indirect Addressing ............................................................ 51

INDF and FSR Registers ........................................... 50

Indirect Addressing Operation ............................................ 51

Indirect File Operand .......................................................... 42

INFSNZ ............................................................................ 233

Instruction Cycle ................................................................. 39

Instruction Flow/Pipelining ................................................. 40

Instruction Format ............................................................ 213

DS39564C-page 319

PIC18FXX2

TBLRD .....................................................................249

TBLWT .....................................................................250

TSTFSZ ....................................................................251

XORLW ....................................................................251

XORWF ....................................................................252

Summary Table ........................................................214

Instructions in Program Memory ........................................40

Two-Word Instructions ...............................................41

INT Interrupt (RB0/INT). See Interrupt Sources

M

Master SSP (MSSP) Module Overview ........................... 125

Master Synchronous Serial Port (MSSP). See MSSP.

Master Synchronous Serial Port. See MSSP

Memory Organization

Data Memory ............................................................. 42

Program Memory ....................................................... 35

Memory Programming Requirements .............................. 268

Migration from Baseline to Enhanced Devices ................ 314

Migration from High-End to Enhanced Devices ............... 315

Migration from Mid-Range to Enhanced Devices ............ 315

MOVF .............................................................................. 235

MOVFF ............................................................................ 236

MOVLB ............................................................................ 236

MOVLW ........................................................................... 237

MOVWF ........................................................................... 237

MPLAB C17 and MPLAB C18 C Compilers ..................... 253

MPLAB ICD In-Circuit Debugger ..................................... 255

MPLAB ICE High Performance Universal In-Circuit

Emulator with MPLAB IDE ....................................... 254

MPLAB Integrated Development

Environment Software ............................................. 253

MPLINK Object Linker/MPLIB Object Librarian ............... 254

MSSP ............................................................................... 125

Control Registers (general) ...................................... 125

Enabling SPI I/O ...................................................... 129

Operation ................................................................. 128

Typical Connection .................................................. 129

MSSP Module

INTCON Register

RBIF Bit ......................................................................90

INTCON Registers ....................................................... 75–77

2

Inter-Integrated Circuit. See I C

Interrupt Sources ..............................................................195

A/D Conversion Complete ........................................184

Capture Complete (CCP) .........................................119

Compare Complete (CCP) .......................................120

INT0 ...........................................................................85

Interrupt-on-Change (RB7:RB4 ) ...............................90

PORTB, Interrupt-on-Change ....................................85

RB0/INT Pin, External ................................................85

TMR0 .........................................................................85

TMR0 Overflow ........................................................105

TMR1 Overflow ................................................ 107, 109

TMR2 to PR2 Match .................................................112

TMR2 to PR2 Match (PWM) ............................ 111, 122

TMR3 Overflow ................................................ 113, 115

USART Receive/Transmit Complete ........................165

Interrupts ............................................................................73

Logic ...........................................................................74

Interrupts, Enable Bits

SPI Master Mode ..................................................... 130

SPI Master./Slave Connection ................................. 129

SPI Slave Mode ....................................................... 131

MULLW ............................................................................ 238

MULWF ............................................................................ 238

CCP1 Enable (CCP1IE Bit) ......................................119

Interrupts, Flag Bits

A/D Converter Flag (ADIF Bit) ..................................183

CCP1 Flag (CCP1IF Bit) ..........................................119

CCP1IF Flag (CCP1IF Bit) .......................................120

Interrupt-on-Change (RB7:RB4) Flag

N

NEGF ............................................................................... 239

NOP ................................................................................. 239

(RBIF Bit) ...........................................................90

IORLW .............................................................................234

IORWF .............................................................................234

IPR Registers ............................................................... 82–83

O

Opcode Field Descriptions ............................................... 212

OPTION_REG Register

K

PSA Bit .................................................................... 105

T0CS Bit .................................................................. 105

T0PS2:T0PS0 Bits ................................................... 105

T0SE Bit ................................................................... 105

Oscillator Configuration ...................................................... 17

EC .............................................................................. 17

ECIO .......................................................................... 17

HS .............................................................................. 17

HS + PLL ................................................................... 17

LP .............................................................................. 17

RC .............................................................................. 17

RCIO .......................................................................... 17

XT .............................................................................. 17

Oscillator Selection .......................................................... 195

Oscillator, Timer1 ..............................................107, 109, 115

Oscillator, Timer3 ............................................................. 113

Oscillator, WDT ................................................................ 203

KEELOQ Evaluation and Programming Tools ...................256

L

LFSR ................................................................................235

Lookup Tables

Computed GOTO .......................................................41

Table Reads, Table Writes .........................................41

Low Voltage Detect ..........................................................189

Converter Characteristics .........................................267

Effects of a RESET ..................................................193

Operation .................................................................192

Current Consumption .......................................193

During SLEEP ..................................................193

Reference Voltage Set Point ............................193

Typical Application ...................................................189

LVD. See Low Voltage Detect. .........................................189

DS39564C-page 320

PIC18FXX2

RC7/RX/DT ................................................................ 15

RD0/PSP0 ................................................................. 16

RD1/PSP1 ................................................................. 16

RD2/PSP2 ................................................................. 16

RD3/PSP3 ................................................................. 16

RD4/PSP4 ................................................................. 16

RD5/PSP5 ................................................................. 16

RD6/PSP6 ................................................................. 16

RD7/PSP7 ................................................................. 16

RE0/RD/AN5 .............................................................. 16

RE1/WR/AN6 ............................................................. 16

RE2/CS/AN7 .............................................................. 16

VDD ............................................................................ 16

VSS ............................................................................ 16

PIC18FXX2 Voltage-Frequency Graph

(Industrial) ................................................................ 260

PIC18LFXX2 Voltage-Frequency Graph

(Industrial) ................................................................ 260

PICDEM 1 Low Cost PICmicro

Demonstration Board ............................................... 255

PICDEM 17 Demonstration Board ................................... 256

PICDEM 2 Low Cost PIC16CXX

Demonstration Board ............................................... 255

PICDEM 3 Low Cost PIC16CXXX

Demonstration Board ............................................... 256

PICSTART Plus Entry Level Development

Programmer ............................................................. 255

PIE Registers ................................................................80–81

Pinout I/O Descriptions

PIC18F2X2 ................................................................ 10

PIR Registers ................................................................78–79

PLL Lock Time-out ............................................................. 26

Pointer, FSR ...................................................................... 50

POP ................................................................................. 240

POR. See Power-on Reset

P

Packaging ........................................................................ 305

Details ...................................................................... 307

Marking Information ................................................. 305

Parallel Slave Port

PORTD .................................................................... 100

Parallel Slave Port (PSP) ........................................... 95, 100

Associated Registers ............................................... 101

RE0/RD/AN5 Pin ................................................ 99, 100

RE1/WR/AN6 Pin ............................................... 99, 100

RE2/CS/AN7 Pin ................................................ 99, 100

Select (PSPMODE Bit) ...................................... 95, 100

PIC18F2X2 Pin Functions

MCLR/VPP .................................................................. 10

OSC1/CLKI ................................................................ 10

OSC2/CLKO/RA6 ...................................................... 10

RA0/AN0 .................................................................... 10

RA1/AN1 .................................................................... 10

RA2/AN2/VREF- .......................................................... 10

RA3/AN3/VREF+ ......................................................... 10

RA4/T0CKI ................................................................. 10

RA5/AN4/SS/LVDIN ................................................... 10

RB0/INT0 ................................................................... 11

RB1/INT1 ................................................................... 11

RB2/INT2 ................................................................... 11

RB3/CCP2 ................................................................. 11

RB4 ............................................................................ 11

RB5/PGM ................................................................... 11

RB6/PGC ................................................................... 11

RB7/PGD ................................................................... 11

RC0/T1OSO/T1CKI ................................................... 12

RC1/T1OSI/CCP2 ...................................................... 12

RC2/CCP1 ................................................................. 12

RC3/SCK/SCL ........................................................... 12

RC4/SDI/SDA ............................................................ 12

RC5/SDO ................................................................... 12

RC6/TX/CK ................................................................ 12

RC7/RX/DT ................................................................ 12

VDD ............................................................................. 12

VSS ............................................................................. 12

PIC18F4X2 Pin Functions

PORTA

Associated Registers ................................................. 89

LATA Register ........................................................... 87

PORTA Register ........................................................ 87

TRISA Register .......................................................... 87

PORTB

Associated Registers ................................................. 92

LATB Register ........................................................... 90

PORTB Register ........................................................ 90

RB0/INT Pin, External ................................................ 85

RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) .......... 90

TRISB Register .......................................................... 90

PORTC

Associated Registers ................................................. 94

LATC Register ........................................................... 93

PORTC Register ........................................................ 93

RC3/SCK/SCL Pin ................................................... 139

RC7/RX/DT Pin ........................................................ 168

TRISC Register ...................................................93, 165

PORTD

MCLR/VPP .................................................................. 13

OSC1/CLKI ................................................................ 13

OSC2/CLKO .............................................................. 13

RA0/AN0 .................................................................... 13

RA1/AN1 .................................................................... 13

RA2/AN2/VREF- .......................................................... 13

RA3/AN3/VREF+ ......................................................... 13

RA4/T0CKI ................................................................. 13

RA5/AN4/SS/LVDIN ................................................... 13

RB0/INT ..................................................................... 14

RB1 ............................................................................ 14

RB2 ............................................................................ 14

RB3 ............................................................................ 14

RB4 ............................................................................ 14

RB5/PGM ................................................................... 14

RB6/PGC ................................................................... 14

RB7/PGD ................................................................... 14

RC0/T1OSO/T1CKI ................................................... 15

RC1/T1OSI/CCP2 ...................................................... 15

RC2/CCP1 ................................................................. 15

RC3/SCK/SCL ........................................................... 15

RC4/SDI/SDA ............................................................ 15

RC5/SDO ................................................................... 15

RC6/TX/CK ................................................................ 15

Associated Registers ................................................. 96

LATD Register ........................................................... 95

Parallel Slave Port (PSP) Function ............................ 95

PORTD Register ........................................................ 95

TRISD Register .......................................................... 95

DS39564C-page 321

PIC18FXX2

PORTE

Registers

ADCON0 (A/D Control 0) ......................................... 181

Analog Port Pins ................................................ 99, 100

Associated Registers .................................................99

LATE Register ............................................................97

PORTE Register ........................................................97

PSP Mode Select (PSPMODE Bit) .................... 95, 100

RE0/RD/AN5 Pin ................................................ 99, 100

RE1/WR/AN6 Pin ............................................... 99, 100

RE2/CS/AN7 Pin ................................................ 99, 100

TRISE Register ..........................................................97

Postscaler, WDT

ADCON1 (A/D Control 1) ......................................... 182

CCP1CON and CCP2CON

(Capture/Compare/PWM Control) ................... 117

CONFIG1H (Configuration 1 High) .......................... 196

CONFIG2H (Configuration 2 High) .......................... 197

CONFIG2L (Configuration 2 Low) ........................... 197

CONFIG3H (Configuration 3 High) .......................... 198

CONFIG4L (Configuration 4 Low) ........................... 198

CONFIG5H (Configuration 5 High) .......................... 199

CONFIG5L (Configuration 5 Low) ........................... 199

CONFIG6H (Configuration 6 High) .......................... 200

CONFIG6L (Configuration 6 Low) ........................... 200

CONFIG7H (Configuration 7 High) .......................... 201

CONFIG7L (Configuration 7 Low) ........................... 201

DEVID1 (Device ID Register 1) ............................... 202

DEVID2 (Device ID Register 2) ............................... 202

EECON1 (Data EEPROM Control 1) ....................57, 66

File Summary ........................................................46–48

INTCON (Interrupt Control) ........................................ 75

INTCON2 (Interrupt Control 2) ................................... 76

INTCON3 (Interrupt Control 3) ................................... 77

IPR1 (Peripheral Interrupt Priority 1) ......................... 82

IPR2 (Peripheral Interrupt Priority 2) ......................... 83

LVDCON (LVD Control) ........................................... 191

OSCCON (Oscillator Control) .................................... 21

PIE1 (Peripheral Interrupt Enable 1) .......................... 80

PIE2 (Peripheral Interrupt Enable 2) .......................... 81

PIR1 (Peripheral Interrupt Request 1) ....................... 78

PIR2 (Peripheral Interrupt Request 2) ....................... 79

RCON (Register Control) ........................................... 84

RCON (RESET Control) ............................................ 53

RCSTA (Receive Status and Control) ..................... 167

SSPCON1 (MSSP Control 1)

Assignment (PSA Bit) ...............................................105

Rate Select (T0PS2:T0PS0 Bits) .............................105

Switching Between Timer0 and WDT ......................105

Power-down Mode. See SLEEP

Power-on Reset (POR) ......................................................26

Oscillator Start-up Timer (OST) .................................26

Power-up Timer (PWRT) ............................................26

Prescaler, Capture ...........................................................119

Prescaler, Timer0 .............................................................105

Assignment (PSA Bit) ...............................................105

Rate Select (T0PS2:T0PS0 Bits) .............................105

Switching Between Timer0 and WDT ......................105

Prescaler, Timer2 .............................................................122

PRO MATE II Universal Device Programmer ...................255

Product Identification System ...........................................327

Program Counter

PCL Register ..............................................................39

PCLATH Register .......................................................39

PCLATU Register .......................................................39

Program Memory

Interrupt Vector ..........................................................35

Map and Stack for PIC18F442/242 ............................36

Map and Stack for PIC18F452/252 ............................36

RESET Vector ............................................................35

Program Verification and Code Protection .......................207

Associated Registers ...............................................207

Programming, Device Instructions ...................................211

PSP.See Parallel Slave Port.

2

I C Mode ......................................................... 136

SPI Mode ......................................................... 127

SSPCON2 (MSSP Control 2)

2

I C Mode ......................................................... 137

Pulse Width Modulation. See PWM (CCP Module).

PUSH ...............................................................................240

PWM (CCP Module) .........................................................122

Associated Registers ...............................................123

CCPR1H:CCPR1L Registers ...................................122

Duty Cycle ................................................................122

Example Frequencies/Resolutions ...........................123

Period .......................................................................122

Setup for PWM Operation ........................................123

TMR2 to PR2 Match ......................................... 111, 122

SSPSTAT (MSSP Status)

2

I C Mode ......................................................... 135

SPI Mode ......................................................... 126

STATUS ..................................................................... 52

STKPTR (Stack Pointer) ............................................ 38

T0CON (Timer0 Control) ......................................... 103

T1CON (Timer 1 Control) ........................................ 107

T2CON (Timer 2 Control) ........................................ 111

T3CON (Timer3 Control) ......................................... 113

TRISE ........................................................................ 98

TXSTA (Transmit Status and Control) ..................... 166

WDTCON (Watchdog Timer Control) ...................... 203

RESET ................................................................25, 195, 241

Brown-out Reset (BOR) ........................................... 195

MCLR Reset (During SLEEP) .................................... 25

MCLR Reset (Normal Operation) .............................. 25

Oscillator Start-up Timer (OST) ............................... 195

Power-on Reset (POR) .......................................25, 195

Power-up Timer (PWRT) ......................................... 195

Programmable Brown-out Reset (BOR) .................... 25

RESET Instruction ..................................................... 25

Stack Full Reset ......................................................... 25

Stack Underflow Reset .............................................. 25

Watchdog Timer (WDT) Reset .................................. 25

Q

Q Clock ............................................................................122

R

RAM. See Data Memory

RC Oscillator ......................................................................18

RCALL ..............................................................................241

RCSTA Register

SPEN Bit ..................................................................165

Register File .......................................................................42

DS39564C-page 322

PIC18FXX2

RETFIE ............................................................................ 242

RETLW ............................................................................. 242

RETURN .......................................................................... 243

Revision History ............................................................... 313

RLCF ................................................................................ 243

RLNCF ............................................................................. 244

RRCF ............................................................................... 244

RRNCF ............................................................................. 245

T

TABLAT Register ............................................................... 58

Table Pointer Operations (table) ........................................ 58

TBLPTR Register ............................................................... 58

TBLRD ............................................................................. 249

TBLWT ............................................................................. 250

Time-out Sequence ........................................................... 26

Time-out in Various Situations ................................... 27

Timer0 .............................................................................. 103

16-bit Mode Timer Reads and Writes ...................... 105

Associated Registers ............................................... 105

Clock Source Edge Select (T0SE Bit) ..................... 105

Clock Source Select (T0CS Bit) ............................... 105

Operation ................................................................. 105

Overflow Interrupt .................................................... 105

Prescaler. See Prescaler, Timer0

Timer1 .............................................................................. 107

16-bit Read/Write Mode ........................................... 109

Associated Registers ............................................... 110

Operation ................................................................. 108

Oscillator ...........................................................107, 109

Overflow Interrupt .............................................107, 109

Special Event Trigger (CCP) ............................109, 120

TMR1H Register ...................................................... 107

TMR1L Register ....................................................... 107

Timer2 .............................................................................. 111

Associated Registers ............................................... 112

Operation ................................................................. 111

Postscaler. See Postscaler, Timer2

S

SCI. See USART

SCK .................................................................................. 125

SDI ................................................................................... 125

SDO ................................................................................. 125

Serial Clock, SCK ............................................................. 125

Serial Communication Interface. See USART

Serial Data In, SDI ........................................................... 125

Serial Data Out, SDO ....................................................... 125

Serial Peripheral Interface. See SPI

SETF ................................................................................ 245

Slave Select Synchronization ........................................... 131

Slave Select, SS .............................................................. 125

SLEEP ...............................................................195, 205, 246

Software Simulator (MPLAB SIM) .................................... 254

Special Event Trigger. See Compare

Special Features of the CPU ............................................ 195

Configuration Registers ................................... 196–201

Special Function Registers ................................................ 42

Map ............................................................................ 45

SPI

Master Mode ............................................................ 130

Serial Clock .............................................................. 125

Serial Data In ........................................................... 125

Serial Data Out ........................................................ 125

Slave Select ............................................................. 125

SPI Clock ................................................................. 130

SPI Mode ................................................................. 125

SPI Master/Slave Connection .......................................... 129

SPI Module

PR2 Register ....................................................111, 122

Prescaler. See Prescaler, Timer2

SSP Clock Shift ................................................111, 112

TMR2 Register ......................................................... 111

TMR2 to PR2 Match Interrupt ...................111, 112, 122

Timer3 .............................................................................. 113

Associated Registers ............................................... 115

Operation ................................................................. 114

Oscillator ...........................................................113, 115

Overflow Interrupt .............................................113, 115

Special Event Trigger (CCP) ................................... 115

TMR3H Register ...................................................... 113

TMR3L Register ....................................................... 113

Timing Diagrams

Associated Registers ............................................... 133

Bus Mode Compatibility ........................................... 133

Effects of a RESET .................................................. 133

Master/Slave Connection ......................................... 129

Slave Mode .............................................................. 131

Slave Select Synchronization .................................. 131

Slave Synch Timing ................................................. 131

SLEEP Operation ..................................................... 133

SS .................................................................................... 125

SSP

Bus Collision

Transmit and Acknowledge ..................... 159

A/D Conversion ........................................................ 287

Acknowledge Sequence .......................................... 158

Baud Rate Generator with Clock Arbitration ............ 152

BRG Reset Due to SDA Arbitration During

START Condition ............................................. 161

Brown-out Reset (BOR) ........................................... 274

Bus Collision

Start Condition (SDA Only) .............................. 160

Bus Collision During a Repeated

START Condition (Case 1) .............................. 162

Bus Collision During a Repeated

START Condition (Case 2) .............................. 162

Bus Collision During a START Condition

(SCL = 0) ......................................................... 161

Bus Collision During a STOP Condition

(Case 1) ........................................................... 163

Bus Collision During a STOP Condition

(Case 2) ........................................................... 163

Capture/Compare/PWM (CCP1 and CCP2) ............ 276

CLKO and I/O .......................................................... 272

Clock Synchronization ............................................. 145

2

I C Mode. See I C

SPI Mode ................................................................. 125

SPI Mode. See SPI

SSPBUF Register .................................................... 130

SSPSR Register ...................................................... 130

TMR2 Output for Clock Shift ............................ 111, 112

SSPOV Status Flag .......................................................... 155

SSPSTAT Register

R/W Bit ............................................................. 138, 139

Status Bits

Significance and the Initialization Condition

for RCON Register ............................................. 27

SUBFWB .......................................................................... 246

SUBLW ............................................................................ 247

SUBWF ............................................................................ 247

SUBWFB .......................................................................... 248

SWAPF ............................................................................ 248

DS39564C-page 323

PIC18FXX2

Example SPI Master Mode (CKE = 0) .....................278

Example SPI Master Mode (CKE = 1) .....................279

Example SPI Slave Mode (CKE = 0) .......................280

Example SPI Slave Mode (CKE = 1) .......................281

External Clock (All Modes except PLL) ....................271

First START Bit Timing ............................................153

USART Synchronous Transmission

(Through TXEN) .............................................. 177

Wake-up from SLEEP via Interrupt .......................... 206

Timing Diagrams Requirements

2

Master SSP I C Bus START/STOP Bits .................. 284

Timing Requirements

2

I C Bus Data ............................................................282

A/D Conversion ........................................................ 288

Capture/Compare/PWM (CCP1 and CCP2) ............ 276

CLKO and I/O .......................................................... 273

Example SPI Mode (Master Mode, CKE = 0) .......... 278

Example SPI Mode (Master Mode, CKE = 1) .......... 279

Example SPI Mode (Slave Mode, CKE = 0) ............ 280

Example SPI Slave Mode (CKE = 1) ....................... 281

External Clock .......................................................... 271

2

I C Bus START/STOP Bits ......................................282

2

I C Master Mode (Reception, 7-bit Address) ...........157

2

I C Master Mode (Transmission,

7 or 10-bit Address) .........................................156

I C Slave Mode Timing (10-bit Reception,

2

SEN = 0) ..........................................................142

I C Slave Mode Timing (10-bit Transmission) .........143

I C Slave Mode Timing (7-bit Reception,

2

I C Bus Data (Slave Mode) ..................................... 283

2

SEN = 0) ..........................................................140

I C Slave Mode Timing (7-bit Reception,

Master SSP I C Bus Data ........................................ 285

2

Parallel Slave Port (PIC18F4X2) ............................. 277

RESET, Watchdog Timer, Oscillator Start-up

Timer, Power-up Timer and

SEN = 1) .................................................. 146, 147

I C Slave Mode Timing (7-bit Transmission) ...........141

2

Low Voltage Detect ..................................................192

Brown-out Reset Requirements ....................... 274

Timer0 and Timer1 External Clock .......................... 275

USART Synchronous Receive ................................. 286

USART Synchronous Transmission ........................ 286

Timing Specifications

PLL Clock ................................................................ 272

TRISE Register

PSPMODE Bit .....................................................95, 100

TSTFSZ ........................................................................... 251

Two-Word Instructions

2

Master SSP I C Bus Data ........................................284

2

Master SSP I C Bus START/STOP Bits ..................284

Parallel Slave Port (PIC18F4X2) ..............................277

Parallel Slave Port (Read) ........................................101

Parallel Slave Port (Write) ........................................100

PWM Output .............................................................122

Repeat START Condition .........................................154

RESET, Watchdog Timer (WDT),

Oscillator Start-up Timer (OST) and

Power-up Timer (PWRT) .................................273

Slave Synchronization ..............................................131

Slaver Mode General Call Address Sequence

(7 or 10-bit Address Mode) ..............................148

Slow Rise Time (MCLR Tied to VDD) .........................33

SPI Mode (Master Mode) .........................................130

SPI Mode (Slave Mode with CKE = 0) .....................132

SPI Mode (Slave Mode with CKE = 1) .....................132

Stop Condition Receive or Transmit Mode ..............158

Time-out Sequence on POR w/PLL Enabled

Example Cases .......................................................... 41

TXSTA Register

BRGH Bit ................................................................. 168

U

Universal Synchronous Asynchronous

Receiver Transmitter. See USART

USART ............................................................................. 165

Asynchronous Mode ................................................ 172

Associated Registers, Receive ........................ 175

Associated Registers, Transmit ....................... 173

Receiver .......................................................... 174

Transmitter ....................................................... 172

Baud Rate Generator (BRG) ................................... 168

Associated Registers ....................................... 168

Baud Rate Error, Calculating ........................... 168

Baud Rate Formula .......................................... 168

Baud Rates for Asynchronous Mode

(MCLR Tied to VDD) ...........................................33

Time-out Sequence on Power-up

(MCLR Not Tied to VDD)

Case 1 ................................................................32

Case 2 ................................................................32

Time-out Sequence on Power-up

(MCLR Tied to VDD) ...........................................32

Timer0 and Timer1 External Clock ...........................275

Timing for Transition Between Timer1 and

OSC1 (HS with PLL) ..........................................23

Transition Between Timer1 and OSC1

(HS, XT, LP) .......................................................22

Transition Between Timer1 and OSC1

(RC, EC) ............................................................23

Transition from OSC1 to Timer1 Oscillator ................22

USART Asynchronous Master Transmission ...........173

USART Asynchronous Master Transmission

(Back to Back) ..................................................173

USART Asynchronous Reception ............................175

USART Synchronous Receive (Master/Slave) .........286

USART Synchronous Reception

(BRGH = 0) .............................................. 170

Baud Rates for Asynchronous Mode

(BRGH = 1) .............................................. 171

Baud Rates for Synchronous Mode ................. 169

High Baud Rate Select (BRGH Bit) ................. 168

Sampling .......................................................... 168

Serial Port Enable (SPEN Bit) ................................. 165

Synchronous Master Mode ...................................... 176

Associated Registers, Reception ..................... 178

Associated Registers, Transmit ....................... 176

Reception ........................................................ 178

Transmission ................................................... 176

Synchronous Slave Mode ........................................ 179

Associated Registers, Receive ........................ 180

Associated Registers, Transmit ....................... 179

Reception ........................................................ 180

Transmission ................................................... 179

(Master Mode, SREN) ......................................178

USART Synchronous Transmission .........................177

USART Synchronous Transmission

(Master/Slave) ..................................................286

DS39564C-page 324

PIC18FXX2

W

X

Wake-up from SLEEP .............................................. 195, 205

Using Interrupts ........................................................ 205

Watchdog Timer (WDT) ........................................... 195, 203

Associated Registers ............................................... 204

Control Register ....................................................... 203

Postscaler ........................................................ 203, 204

Programming Considerations .................................. 203

RC Oscillator ............................................................ 203

Time-out Period ....................................................... 203

WCOL .............................................................................. 153

WCOL Status Flag ............................................153, 155, 158

WWW, On-Line Support ....................................................... 5

XORLW ............................................................................ 251

XORWF ........................................................................... 252

DS39564C-page 325

PIC18FXX2

NOTES:

DS39564C-page 326

PIC18FXX2

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

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Users of Microchip products can receive assistance

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software

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Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

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Technical support is available through the web site

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specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

DS39564C-page 327

PIC18FXX2

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

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Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

PIC18FXX2

DS39564C

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS39564C-page 328

Advance Information

PIC18FXX2

PIC18FXX2 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

X

/XX

XXX

PART NO.

Device

−

Examples:

Temperature Package

Range

Pattern

a) PIC18LF452 - I/P 301 = Industrial temp.,

PDIP package, Extended VDD limits,

QTP pattern #301.

b) PIC18LF242 - I/SO = Industrial temp.,

SOIC package, Extended VDD limits.

c) PIC18F442 - E/P = Extended temp.,

PDIP package, normal VDD limits.

(1)

(2)

Device

PIC18FXX2 , PIC18FXX2T ;

VDD range 4.2V to 5.5V

(1)

(2)

PIC18LFXX2 , PIC18LFXX2T

VDD range 2.5V to 5.5V

;

Temperature

Range

I

E

=

-40°C to +85°C (Industrial)

-40°C to +125°C (Extended)

Note 1: F

LF

2: T

=

Standard Voltage range

Wide Voltage Range

Package

PT

SO

SP

P

=

TQFP (Thin Quad Flatpack)

SOIC

Skinny Plastic DIP

PDIP

PLCC

=

in tape and reel - SOIC,

PLCC, and TQFP

packages only.

L

Pattern

QTP, SQTP, Code or Special Requirements

(blank otherwise)

DS39564C-page 329

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

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Tel: 852-2401-1200

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Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

08/29/06

DS39564C-page 330


型号：	PIC18FXX2T-E/SP
厂家：	MICROCHIP
描述：	High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D 高性能，增强型闪存微控制器与10位A / D 闪存微控制器
文件：	总332页 (文件大小：5931K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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