PIC18F8585-E/PT_技术文档

PIC18F6585/8585/6680/8680

Data Sheet

64/68/80-Pin High-Performance,

64-Kbyte Enhanced Flash

Microcontrollers with ECAN Module

 2004 Microchip Technology Inc.

DS30491C

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is intended through suggestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microchip Technology Incorporated with respect

to the accuracy or use of such information, or infringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical

components in life support systems is not authorized except

with express written approval by Microchip. No licenses are

conveyed, implicitly or otherwise, under any intellectual

property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart and rfPIC are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,

SEEVAL, SmartShunt and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net,

dsPICworks, ECAN, ECONOMONITOR, FanSense,

FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,

ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK,

MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode,

SmartSensor, SmartTel and Total Endurance are trademarks

of Microchip Technology Incorporated in the U.S.A. and other

countries.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in October

2003. The Company’s quality system processes and procedures are for

its PICmicro^®8-bit MCUs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS30491C-page ii

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash

Microcontrollers with ECAN Module

High-Performance RISC CPU:

Analog Features:

• Source code compatible with the PIC16 and

PIC17 instruction sets

• Up to 16-channel, 10-bit Analog-to-Digital

Converter module (A/D) with:

• Linear program memory addressing to 2 Mbytes

• Linear data memory addressing to 4096 bytes

• 1 Kbyte of data EEPROM

• Up to 10 MIPs operation:

- DC – 40 MHz osc./clock input

- Fast sampling rate

- Programmable acquisition time

- Conversion available during Sleep

• Programmable 16-level Low-Voltage Detection

(LVD) module:

- 4 MHz-10 MHz osc./clock input with PLL active

• 16-bit wide instructions, 8-bit wide data path

• Priority levels for interrupts

- Supports interrupt on Low-Voltage Detection

• Programmable Brown-out Reset (BOR)

• Dual analog comparators:

• 31-level, software accessible hardware stack

• 8 x 8 Single-Cycle Hardware Multiplier

- Programmable input/output configuration

ECAN Module Features:

• Message bit rates up to 1 Mbps

• Conforms to CAN 2.0B ACTIVE Specification

• Fully backward compatible with PIC18XXX8 CAN

modules

External Memory Interface

(PIC18F8X8X Devices Only):

• Address capability of up to 2 Mbytes

• 16-bit interface

• Three modes of operation:

Peripheral Features:

• High current sink/source 25 mA/25 mA

• Four external interrupt pins

- Legacy, Enhanced Legacy, FIFO

• Three dedicated transmit buffers with prioritization

• Two dedicated receive buffers

• Six programmable receive/transmit buffers

• Three full 29-bit acceptance masks

• 16 full 29-bit acceptance filters with dynamic association

• DeviceNet™ data byte filter support

• Automatic remote frame handling

• Advanced Error Management features

• Timer0 module: 8-bit/16-bit timer/counter

• Timer1 module: 16-bit timer/counter

• Timer2 module: 8-bit timer/counter

• Timer3 module: 16-bit timer/counter

• Secondary oscillator clock option – Timer1/Timer3

• One Capture/Compare/PWM (CCP) module:

- Capture is 16-bit, max. resolution 6.25 ns

(TCY/16)

Special Microcontroller Features:

• 100,000 erase/write cycle Enhanced Flash

program memory typical

• 1,000,000 erase/write cycle Data EEPROM

memory typical

- Compare is 16-bit, max. resolution 100 ns (TCY)

- PWM output: PWM resolution is 1 to 10-bit

• Enhanced Capture/Compare/PWM (ECCP) module:

- Same Capture/Compare features as CCP

- One, two or four PWM outputs

• 1-second programming time

• Flash/Data EEPROM Retention: > 40 years

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own On-Chip

RC Oscillator

- Selectable polarity

- Programmable dead time

- Auto-shutdown on external event

- Auto-restart

• Master Synchronous Serial Port (MSSP) module

with two modes of operation:

• Programmable code protection

• Power saving Sleep mode

- 3-wire SPI™ (supports all 4 SPI modes)

- I²C™ Master and Slave mode

• Selectable oscillator options including:

- Software enabled 4x Phase Lock Loop (of

primary oscillator)

- Secondary Oscillator (32 kHz) clock input

• In-Circuit Serial Programming™ (ICSP™) via two pins

• MPLAB^®In-Circuit Debug (ICD) via two pins

• Enhanced Addressable USART module:

- Supports RS-232, RS-485 and LIN 1.2

- Programmable wake-up on Start bit

- Auto-baud detect

• Parallel Slave Port (PSP) module

 2004 Microchip Technology Inc.

DS30491C-page 1

PIC18F6585/8585/6680/8680

CMOS Technology:

• Low-power, high-speed Flash technology

• Fully static design

• Wide operating voltage range (2.0V to 5.5V)

• Industrial and Extended temperature ranges

Program Memory

Data Memory

MSSP

CCP/

ECCP

(PWM)

10-bit

A/D (ch)

ECAN/

AUSART 8-bit/16-bit

Timers

Device

I/O

EMA

# Single-Word SRAM EEPROM

Instructions (bytes) (bytes)

Master

Bytes

SPI

2

I C

PIC18F6585 48K

PIC18F6680 64K

PIC18F8585 48K

PIC18F8680 64K

24576

32768

24576

32768

3328

1024

53

69

12

16

1/1

Y

Y/Y

2/3

N

Y

DS30491C-page 2

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

Pin Diagrams

64-Pin TQFP

64 63 62 61 60 59 58 57 56 55 54 53 52 51

50 49

RB0/INT0

RE1/WR

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

RB1/INT1

RE0/RD

RG0/CANTX1

RG1/CANTX2

RG2/CANRX

RG3

2

RB2/INT2

3

RB3/INT3

4

RB4/KBI0

5

RB5/KBI1/PGM

RB6/KBI2/PGC

VSS

6

RG5/MCLR/VPP

RG4/P1D

7

PIC18F6X8X

8

VSS

OSC2/CLKO/RA6

OSC1/CLKI

VDD

9

VDD

10

11

12

13

14

15

16

RF7/SS

RB7/KBI3/PGD

RC5/SDO

RF6/AN11/C1IN-

RF5/AN10/C1IN+/CVREF

RF4/AN9/C2IN-

RF3/AN8/C2IN+

RF2/AN7/C1OUT

RC4/SDI/SDA

RC3/SCK/SCL

RC2/CCP1/P1A

17 18 19 20 21 22 23 24 25 26 27 28

29 30 31 32

Note 1: CCP2 pin placement depends on CCP2MX setting.

 2004 Microchip Technology Inc.

DS30491C-page 3

PIC18F6585/8585/6680/8680

Pin Diagrams (Continued)

68-Pin PLCC

9

8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

10

11

12

13

14

15

16

60

59

RB0/INT0

RB1/INT1

RB2/INT2

RB3/INT3

RB4/KBI0

RB5/KBI1/PGM

RB6/KBI2/PGC

VSS

RE1/WR

RE0/RD

RG0/CANTX1

RG1/CANTX2

RG2/CANRX

RG3

Top View

58

57

56

55

54

53

52

51

50

49

RG5/MCLR/VPP

RG4/P1D

17

18

19

20

21

N/C

PIC18F6X8X

OSC2/CLKO/RA6

VSS

VDD

OSC1/CLKI

VDD

RF7/SS

22

23

24

25

26

RF6/AN11/C1IN-

RF5/AN10/C1IN+/CVREF

RF4/AN9/C2IN-

RF3/AN8/C2IN+

RF2/AN7/C1OUT

48

47

46

45

44

RB7/KBI3/PGD

RC5/SDO

RC4/SDI/SDA

RC3/SCK/SCL

RC2/CCP1/P1A

2728 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Note 1: CCP2 pin placement depends on CCP2MX setting.

DS30491C-page 4

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

Pin Diagrams (Continued)

80-Pin TQFP

80 79 78

77 76 75 74 73 72 71 70 69 68 67 66 65

64 63 62 61

RH2/A18

1

RJ2/WRL

RJ3/WRH

RB0/INT0

RB1/INT1

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

RH3/A19

2

RE1/WR/AD9

3

RE0/RD/AD8

4

RG0/CANTX1

5

RB2/INT2

RB3/INT3/CCP2⁽²⁾

RG1/CANTX2

6

RB4/KBI0

RG2/CANRX

7

RB5/KBI1/PGM

RB6/KBI2/PGC

VSS

RG3

8

RG5/MCLR/VPP

9

RG4/P1D

PIC18F8X8X

10

VSS

11

OSC2/CLKO/RA6

OSC1/CLKI

VDD

12

RF7/SS

13

RB7/KBI3/PGD

RC5/SDO

RF6/AN11/C1IN-

14

RF5/AN10/C1IN+/CVREF

15

RC4/SDI/SDA

RC3/SCK/SCL

RC2/CCP1/P1A

RJ7/UB

RF4/AN9/C2IN-

16

RF3/AN8/C2IN+

17

RF2/AN7/C1OUT

18

RH7/AN15/P1B⁽³⁾

19

RH6/AN14/P1C⁽³⁾

RJ6/LB

20

40

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Note 1: PSP is available only in Microcontroller mode.

2: CCP2 pin placement depends on CCP2MX and Processor mode settings.

3: P1B and P1C pin placement depends on ECCPMX setting.

 2004 Microchip Technology Inc.

DS30491C-page 5

PIC18F6585/8585/6680/8680

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Oscillator Configurations ............................................................................................................................................................ 23

3.0 Reset.......................................................................................................................................................................................... 33

4.0 Memory Organization................................................................................................................................................................. 51

5.0 Flash Program Memory.............................................................................................................................................................. 83

6.0 External Memory Interface ......................................................................................................................................................... 93

7.0 Data EEPROM Memory ........................................................................................................................................................... 101

8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 107

9.0 Interrupts .................................................................................................................................................................................. 109

10.0 I/O Ports ................................................................................................................................................................................... 125

11.0 Timer0 Module ......................................................................................................................................................................... 155

12.0 Timer1 Module ......................................................................................................................................................................... 159

13.0 Timer2 Module ......................................................................................................................................................................... 162

14.0 Timer3 Module ......................................................................................................................................................................... 164

15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 167

16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 175

17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 189

18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (USART).................................................................. 229

19.0 10-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 249

20.0 Comparator Module.................................................................................................................................................................. 259

21.0 Comparator Voltage Reference Module................................................................................................................................... 265

22.0 Low-Voltage Detect.................................................................................................................................................................. 269

23.0 ECAN Module........................................................................................................................................................................... 275

24.0 Special Features of the CPU.................................................................................................................................................... 345

25.0 Instruction Set Summary.......................................................................................................................................................... 365

26.0 Development Support............................................................................................................................................................... 407

27.0 Electrical Characteristics.......................................................................................................................................................... 413

28.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 449

29.0 Packaging Information.............................................................................................................................................................. 465

Appendix A: Revision History............................................................................................................................................................. 469

Appendix B: Device Differences......................................................................................................................................................... 469

Appendix C: Conversion Considerations ........................................................................................................................................... 470

Appendix D: Migration from Mid-Range to Enhanced Devices.......................................................................................................... 470

Appendix E: Migration from High-End to Enhanced Devices............................................................................................................. 471

Index .................................................................................................................................................................................................. 473

On-Line Support................................................................................................................................................................................. 487

Systems Information and Upgrade Hot Line ...................................................................................................................................... 487

Reader Response .............................................................................................................................................................................. 488

PIC18F6585/8585/6680/8680 Product Identification System ............................................................................................................ 489

DS30491C-page 6

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.

We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page)

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When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-

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 2004 Microchip Technology Inc.

DS30491C-page 7

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 8

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

All

other

features

for

devices

in

the

1.0

DEVICE OVERVIEW

PIC18F6585/8585/6680/8680 family are identical.

These are summarized in Table 1-1.

This document contains device specific information for

the following devices:

Block diagrams of the PIC18F6X8X and PIC18F8X8X

devices are provided in Figure 1-1 and Figure 1-2,

respectively. The pinouts for these device families are

listed in Table 1-2.

• PIC18F6585

• PIC18F6680

• PIC18F8585

• PIC18F8680

PIC18F6X8X devices are available in 64-pin TQFP and

68-pin PLCC packages. PIC18F8X8X devices are

available in the 80-pin TQFP package. They are

differentiated from each other in four ways:

1. Flash program memory (48 Kbytes for

PIC18FX585 devices, 64 Kbytes for

PIC18FX680)

2. A/D channels (12 for PIC18F6X8X devices,

16 for PIC18F8X8X)

3. I/O ports (7 on PIC18F6X8X devices, 9 on

PIC18F8X8X)

4. External program memory interface (present

only on PIC18F8X8X devices)

TABLE 1-1:

PIC18F6585/8585/6680/8680 DEVICE FEATURES

Features

PIC18F6585

PIC18F6680

PIC18F8585

PIC18F8680

Operating Frequency

DC – 40 MHz

DC – 25 MHz w/EMA DC – 25 MHz w/EMA

Program Memory (Bytes)

Program Memory (Instructions)

Data Memory (Bytes)

Data EEPROM Memory (Bytes)

External Memory Interface

Interrupt Sources

48K

64K

48K (2 MB EMA)

64K (2 MB EMA)

24576

32768

24576

32768

3328

1024

No

Yes

29

I/O Ports

Ports A-G

Ports A-H, J

Timers

4

1

4

1

4

1

4

1

Capture/Compare/PWM Module

EnhancedCapture/Compare/PWM

Module

Serial Communications

MSSP,

Enhanced AUSART, Enhanced AUSART, Enhanced AUSART, Enhanced AUSART,

ECAN

(1)

Parallel Communications

10-bit Analog-to-Digital Module

Resets (and Delays)

PSP

12 input channels

16 input channels

POR, BOR,

RESETInstruction,

Stack Full,

POR, BOR,

RESETInstruction,

Stack Full,

POR, BOR,

RESETInstruction,

Stack Full,

POR, BOR,

RESETInstruction,

Stack Full,

Stack Underflow

(PWRT, OST)

Stack Underflow

(PWRT, OST)

Stack Underflow

(PWRT, OST)

Stack Underflow

(PWRT, OST)

Programmable Low-Voltage Detect

Programmable Brown-out Reset

Instruction Set

Yes

75 Instructions

80-pin TQFP

75 Instructions

80-pin TQFP

Package

64-pin TQFP,

68-pin PLCC

64-pin TQFP,

68-pin PLCC

Note 1: PSP is only available in Microcontroller mode.

 2004 Microchip Technology Inc.

DS30491C-page 9

PIC18F6585/8585/6680/8680

FIGURE 1-1:

PIC18F6X8X BLOCK DIAGRAM

Data Bus<8>

PORTA

RA0/AN0

RA1/AN1

Table Pointer<21>

Data Latch

21

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

8

Data RAM

(3328 bytes)

inc/dec logic

21

RA5/AN4/LVDIN

OSC2/CLKO/RA6

Address Latch

12

21

PCLATH

PCLATU

PORTB

RB2/INT2:RB0/INT0

RB3/INT3

RB4/KBI0

RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

Address<12>

PCU PCH PCL

Program Counter

4

BSR

12

FSR0

4

Bank0, F

Address Latch

FSR1

FSR2

Program Memory

(48 Kbytes)

31 Level Stack

12

Data Latch

PORTC

inc/dec

logic

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2⁽¹⁾

RC2/CCP1/P1A

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

Decode

Table Latch

8

16

ROM Latch

IR

PORTD

PORTE

8

RD7/PSP7:RD0/PSP0

PRODH PRODL

8 x 8 Multiply

Instruction

Decode &

Control

RE0/RD

RE1/WR

RE2/CS

RE3

8

3

W

8

BITOP

8

Power-up

Timer

RE4

OSC2/CLKO/RA6

OSC1/CLKI

RE5/P1C

RE6/P1B

RE7/CCP2⁽¹⁾

Timing

Generation

Oscillator

Start-up Timer

8

ALU<8>

Power-on

Reset

PORTF

RF0/AN5

8

RF1/AN6/C2OUT

RF2/AN7/C1OUT

RF3/AN8/C2IN+

RF4/AN9/C2IN-

RF5/AN10/C1IN+/CVREF

RF6/AN11/C1IN-

RF7/SS

Watchdog

Timer

Precision

Band Gap

Reference

Brown-out

Reset

Test Mode

Select

RG5/

VDD, VSS

MCLR

PORTG

RG0/CANTX1

RG1/CANTX2

RG2/CANRX

RG3

RG4/P1D

RG5/MCLR/VPP

BOR

LVD

Timer3

Timer0

Timer1

Timer2

Synchronous

Serial Port

10-bit

ADC

CCP2

ECCP1

Comparator

AUSART

ECAN Module

Data EEPROM

Note 1: The CCP2 pin placement depends on the CCP2MX and Processor mode settings.

DS30491C-page 10

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 1-2:

PIC18F8X8X BLOCK DIAGRAM

Data Bus<8>

AD7:AD0

PORTA

RA0/AN0

RA1/AN1

Table Pointer<21>

inc/dec logic

Data Latch

21

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

8

Data RAM

(3328 bytes)

RA5/AN4/LVDIN

OSC2/CLKO/RA6

21

Address Latch

12

21

PCLATH

PCLATU

PORTB

RB2/INT2:RB0/INT0

RB3/INT3/CCP2⁽¹⁾

RB4/KBI0

RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

Address<12>

PCU PCH PCL

Program Counter

4

BSR

12

FSR0

4

Bank0, F

Address Latch

FSR1

FSR2

Program Memory

(64 Kbytes)

31 Level Stack

12

Data Latch

PORTC

inc/dec

logic

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2⁽¹⁾

RC2/CCP1/P1A

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

Decode

Table Latch

8

16

ROM Latch

IR

RC6/TX/CK

RC7/RX/DT

PORTD

PORTE

A16, AD15:AD8

8

RD7/PSP7/AD7:

RD0/PSP0/AD0

PRODH PRODL

8 x 8 Multiply

Instruction

Decode &

Control

RE0/RD/AD8

RE1/WR/AD9

RE2/CS/AD10

RE3/AD11

8

3

W

8

BITOP

8

Power-up

Timer

RE4/AD12

OSC2/CLKO/RA6

OSC1/CLKI

RE5/AD13/P1C⁽²⁾

RE6/AD14/P1B⁽²⁾

RE7/CCP2⁽¹⁾/AD15

Timing

Generation

Oscillator

Start-up Timer

8

ALU<8>

Power-on

Reset

PORTF

RF0/AN5

8

RF1/AN6/C2OUT

RF2/AN7/C1OUT

RF3/AN8/C2IN+

RF4/AN9/C2IN-

RF5/AN10/C1IN+/CVREF

RF6/AN11/C1IN-

RF7/SS

Watchdog

Timer

Precision

Band Gap

Reference

Brown-out

Reset

Test Mode

Select

PORTJ

RJ0/ALE

RJ1/OE

RJ2/WRL

RJ3/WRH

RJ4/BA0

RJ5/CE

PORTG

PORTH

RG0/CANTX1

RG1/CANTX2

RG2/CANRX

RG3

RG4/P1D

RG5/

VDD, VSS

MCLR

RJ6/LB

RJ7/UB

RG5/MCLR/VPP

RH7/AN15/P1B⁽²⁾

RH6/AN14/P1C⁽²⁾

RH5/AN13

BOR

LVD

Timer3

Timer0

Timer2

Timer1

RH4/AN12

RH3/A19:RH0/A16

Synchronous

Serial Port

10-bit

ADC

ECCP1

CCP2

Comparator

AUSART

ECAN Module

Note 1: The CCP2 pin placement depends on the CCP2MX and Processor mode settings.

2: P1B and P1C pin placement depends on the ECCPMX setting.

 2004 Microchip Technology Inc.

DS30491C-page 11

PIC18F6585/8585/6680/8680

TABLE 1-2:

PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS

Pin Number

Type

Buffer

Type

Pin Name

PIC18F6X8X PIC18F8X8X

Description

TQFP PLCC

TQFP

RG5/MCLR/VPP

7

16

50

9

Master Clear (input) or programming

voltage (input).

RG5

MCLR

I

ST

General purpose input pin.

Master Clear (Reset) input. This pin is

an active-low Reset to the device.

Programming voltage input.

VPP

P

I

OSC1/CLKI

OSC1

39

49

50

Oscillator crystal or external clock input.

Oscillator crystal input or external clock

source input. ST buffer when configured

in RC mode; otherwise CMOS.

CMOS/ST

CMOS

CLKI

I

External clock source input. Always

associated with pin function OSC1

(see OSC1/CLKI, OSC2/CLKO pins).

OSC2/CLKO/RA6

OSC2

40

51

Oscillator crystal or clock output.

Oscillator crystal output.

O

—

Connects to crystal or resonator in

Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO

which has 1/4 the frequency of OSC1

and denotes the instruction cycle rate.

General purpose I/O pin.

CLKO

RA6

I/O

TTL

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

Analog = Analog input

ST

I

= Schmitt Trigger input with CMOS levels

= Input

O

= Output

P

= Power

OD

= Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X8X devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.

6: PSP is available in Microcontroller mode only.

7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

DS30491C-page 12

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 1-2:

PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

PIC18F6X8X PIC18F8X8X

Description

TQFP PLCC

TQFP

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

24

23

22

34

33

32

30

I/O

I

TTL

Analog

Digital I/O.

Analog input 0.

AN0

RA1/AN1

RA1

29

28

I/O

I

TTL

Analog

Digital I/O.

Analog input 1.

AN1

RA2/AN2/VREF-

RA2

I/O

TTL

Digital I/O.

AN2

VREF-

I

Analog

Analog input 2.

A/D reference voltage (Low) input.

RA3/AN3/VREF+

RA3

21

28

27

31

39

38

27

34

33

I/O

I

TTL

Analog

Digital I/O.

Analog input 3.

A/D reference voltage (High) input.

AN3

VREF+

RA4/T0CKI

RA4

I/O

I

ST/OD

ST

Digital I/O – Open-drain when

configured as output.

Timer0 external clock input.

T0CKI

RA5/AN4/LVDIN

RA5

I/O

TTL

Digital I/O.

AN4

LVDIN

I

Analog

Analog input 4.

Low-voltage detect input.

RA6

See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

Analog = Analog input

ST

I

= Schmitt Trigger input with CMOS levels

= Input

O

= Output

P

= Power

OD

= Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X8X devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.

6: PSP is available in Microcontroller mode only.

7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

 2004 Microchip Technology Inc.

DS30491C-page 13

PIC18F6585/8585/6680/8680

TABLE 1-2:

PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

PIC18F6X8X PIC18F8X8X

Description

TQFP PLCC

TQFP

PORTB is a bidirectional I/O port. PORTB

can be software programmed for internal

weak pull-ups on all inputs.

RB0/INT0

RB0

48

47

46

45

60

59

58

57

58

57

56

55

I/O

I

TTL

ST

Digital I/O.

External interrupt 0.

INT0

RB1/INT1

RB1

I/O

I

TTL

ST

Digital I/O.

External interrupt 1.

INT1

RB2/INT2

RB2

I/O

I

TTL

ST

Digital I/O.

External interrupt 2.

INT2

RB3/INT3/CCP2

RB3

I/O

TTL

ST

Digital I/O.

INT3

External interrupt 3.

Capture 2 input/Compare 2 output/

PWM 2 output.

CCP2⁽¹⁾

RB4/KBI0

RB4

44

43

56

55

54

53

I/O

I

TTL

ST

Digital I/O.

Interrupt-on-change pin.

KBI0

RB5/KBI1/PGM

RB5

I/O

I

I/O

TTL

ST

Digital I/O.

KBI1

PGM

Interrupt-on-change pin.

Low-Voltage ICSP Programming

enable pin.

RB6/KBI2/PGC

RB6

42

37

54

48

52

47

I/O

I

I/O

TTL

ST

Digital I/O.

KBI2

PGC

Interrupt-on-change pin.

In-circuit debugger and ICSP

programming clock.

RB7/KBI3/PGD

RB7

I/O

TTL

ST

Digital I/O.

KBI3

PGD

Interrupt-on-change pin.

In-circuit debugger and ICSP

programming data.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

Analog = Analog input

ST

I

= Schmitt Trigger input with CMOS levels

= Input

O

= Output

P

= Power

OD

= Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X8X devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.

6: PSP is available in Microcontroller mode only.

7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

DS30491C-page 14

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 1-2:

PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

PIC18F6X8X PIC18F8X8X

Description

TQFP PLCC

TQFP

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

30

29

41

40

36

I/O

O

I

ST

—

ST

Digital I/O.

Timer1 oscillator output.

Timer1/Timer3 external clock input.

T1OSO

T13CKI

RC1/T1OSI/CCP2

RC1

35

I/O

I

I/O

ST

CMOS

ST

Digital I/O.

T1OSI

Timer1 oscillator input.

CCP2 Capture input/Compare output/

PWM 2 output.

CCP2^{(1, 4)}

RC2/CCP1/P1A

RC2

33

34

44

45

43

44

I/O

ST

Digital I/O.

CCP1 Capture input/Compare output.

CCP1 PWM output A.

CCP1

P1A

RC3/SCK/SCL

RC3

I/O

ST

Digital I/O.

Synchronous serial clock input/output

for SPI mode.

SCK

SCL

I/O

ST

Synchronous serial clock input/output

for I²C mode.

RC4/SDI/SDA

RC4

35

46

45

I/O

I

I/O

ST

Digital I/O.

SPI data in.

I²C data I/O.

SDI

SDA

RC5/SDO

RC5

36

31

47

42

46

37

I/O

O

ST

—

Digital I/O.

SPI data out.

SDO

RC6/TX/CK

RC6

I/O

O

I/O

ST

—

ST

Digital I/O.

TX

CK

USART asynchronous transmit.

USART synchronous clock

(see RX/DT).

RC7/RX/DT

RC7

32

43

38

I/O

I

I/O

ST

Digital I/O.

RX

DT

USART 1 asynchronous receive.

USART 1 synchronous data

(see TX/CK).

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

Analog = Analog input

ST

I

= Schmitt Trigger input with CMOS levels

= Input

O

= Output

P

= Power

OD

= Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X8X devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.

6: PSP is available in Microcontroller mode only.

7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

 2004 Microchip Technology Inc.

DS30491C-page 15

PIC18F6585/8585/6680/8680

TABLE 1-2:

PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

PIC18F6X8X PIC18F8X8X

Description

TQFP PLCC

TQFP

PORTD is a bidirectional I/O port. These

pins have TTL input buffers when external

memory is enabled.

RD0/PSP0/AD0

RD0

58

55

54

53

52

51

50

49

3

72

69

68

67

66

65

64

63

I/O

ST

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 0.

PSP0⁽⁶⁾

AD0⁽³⁾

RD1/PSP1/AD1

RD1

67

66

65

64

63

62

61

I/O

ST

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 1.

PSP1⁽⁶⁾

AD1⁽³⁾

RD2/PSP2/AD2

RD2

I/O

ST

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 2.

PSP2⁽⁶⁾

AD2⁽³⁾

RD3/PSP3/AD3

RD3

I/O

ST

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 3.

PSP3⁽⁶⁾

AD3⁽³⁾

RD4/PSP4/AD4

RD4

I/O

ST

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 4.

PSP4⁽⁶⁾

AD4⁽³⁾

RD5/PSP5/AD5

RD5

I/O

ST

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 5.

PSP5⁽⁶⁾

AD5⁽³⁾

RD6/PSP6/AD6

RD6

I/O

ST

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 6.

PSP6⁽⁶⁾

AD6⁽³⁾

RD7/PSP7/AD7

RD7

I/O

ST

TTL

Digital I/O.

Parallel Slave Port data.

External memory address/data 7.

PSP7⁽⁶⁾

AD7⁽³⁾

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

Analog = Analog input

ST

I

= Schmitt Trigger input with CMOS levels

= Input

O

= Output

P

= Power

OD

= Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X8X devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.

6: PSP is available in Microcontroller mode only.

7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

DS30491C-page 16

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 1-2:

PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

PIC18F6X8X PIC18F8X8X

Description

TQFP PLCC

TQFP

PORTE is a bidirectional I/O port.

RE0/RD/AD8

RE0

2

1

11

10

9

4

I/O

I

ST

TTL

Digital I/O.

Read control for Parallel Slave Port

(see WR and CS pins).

RD⁽⁶⁾

AD8⁽³⁾

I/O

TTL

External memory address/data 8.

RE1/WR/AD9

RE1

3

I/O

I

ST

TTL

Digital I/O.

Write control for Parallel Slave Port

(see CS and RD pins).

WR⁽⁶⁾

AD9⁽³⁾

I/O

TTL

External memory address/data 9.

RE2/CS/AD10

RE2

64

78

I/O

I

ST

TTL

Digital I/O.

Chip select control for Parallel Slave

Port (see RD and WR).

CS⁽⁶⁾

AD10⁽³⁾

I/O

TTL

External memory address/data 10.

RE3/AD11

RE3

63

62

61

8

7

6

77

76

75

I/O

ST

TTL

Digital I/O.

External memory address/data 11.

AD11⁽³⁾

RE4/AD12

RE4

I/O

ST

TTL

Digital I/O.

External memory address/data 12.

AD12⁽³⁾

RE5/AD13/P1C

RE5

I/O

ST

TTL

ST

Digital I/O.

External memory address/data 13.

ECCP1 PWM output C.

AD13⁽³⁾

P1C⁽⁷⁾

RE6/AD14/P1B

RE6

60

59

5

4

74

73

I/O

ST

TTL

ST

Digital I/O.

External memory address/data 14.

ECCP1 PWM output B.

AD14⁽³⁾

P1B⁽⁷⁾

RE7/CCP2/AD15

RE7

I/O

ST

Digital I/O.

Capture 2 input/Compare 2 output/

PWM 2 output.

CCP2^(1,4)

AD15⁽³⁾

I/O

TTL

External memory address/data 15.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

Analog = Analog input

ST

I

= Schmitt Trigger input with CMOS levels

= Input

O

= Output

P

= Power

OD

= Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X8X devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.

6: PSP is available in Microcontroller mode only.

7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

 2004 Microchip Technology Inc.

DS30491C-page 17

PIC18F6585/8585/6680/8680

TABLE 1-2:

PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

PIC18F6X8X PIC18F8X8X

Description

TQFP PLCC

TQFP

PORTF is a bidirectional I/O port.

RF0/AN5

RF0

18

17

28

27

24

I/O

I

ST

Analog

Digital I/O.

Analog input 5.

AN5

RF1/AN6/C2OUT

RF1

23

18

17

16

15

I/O

I

O

ST

Analog

ST

Digital I/O.

Analog input 6.

Comparator 2 output.

AN6

C2OUT

RF2/AN7/C1OUT

RF2

16

15

14

13

26

25

24

23

I/O

I

O

ST

Analog

ST

Digital I/O.

Analog input 7.

Comparator 1 output.

AN7

C1OUT

RF3/AN8/C2IN+

RF1

I/O

I

ST

Analog

Digital I/O.

Analog input 8.

Comparator 2 input (+).

AN8

C2IN+

RF4/AN9/C2IN-

RF1

I/O

I

ST

Analog

Digital I/O.

Analog input 9.

Comparator 2 input (-).

AN9

C2IN-

RF5/AN10/C1IN+/CVREF

RF1

AN10

C1IN+

CVREF

I/O

I

ST

Digital I/O.

Analog input 10.

Comparator 1 input (+).

Comparator VREF output.

Analog

O

RF6/AN11/C1IN-

RF6

12

11

22

21

14

13

I/O

I

ST

Analog

Digital I/O.

Analog input 11.

Comparator 1 input (-)

AN11

C1IN-

RF7/SS

RF7

I/O

I

ST

TTL

Digital I/O.

SPI slave select input.

SS

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

Analog = Analog input

ST

I

= Schmitt Trigger input with CMOS levels

= Input

O

= Output

P

= Power

OD

= Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X8X devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.

6: PSP is available in Microcontroller mode only.

7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

DS30491C-page 18

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 1-2:

PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

PIC18F6X8X PIC18F8X8X

Description

TQFP PLCC

TQFP

PORTG is a bidirectional I/O port.

RG0/CANTX1

RG0

3

4

5

12

13

14

5

I/O

O

ST

TTL

Digital I/O.

CAN bus transmit 1.

CANTX1

RG1/CANTX2

RG1

6

7

I/O

O

ST

TTL

Digital I/O.

CAN bus transmit 2.

CANTX2

RG2/CANRX

RG2

I/O

I

ST

TTL

Digital I/O.

CAN bus receive.

CANRX

RG3

6

8

15

17

8

I/O

ST

Digital I/O.

RG4/P1D

RG4

10

I/O

O

ST

TTL

Digital I/O.

ECCP1 PWM output D.

P1D

RG5

7

16

9

I

ST

General purpose input pin.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

Analog = Analog input

ST

I

= Schmitt Trigger input with CMOS levels

= Input

O

= Output

P

= Power

OD

= Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X8X devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.

6: PSP is available in Microcontroller mode only.

7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

 2004 Microchip Technology Inc.

DS30491C-page 19

PIC18F6585/8585/6680/8680

TABLE 1-2:

PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

PIC18F6X8X PIC18F8X8X

Description

TQFP PLCC

TQFP

PORTH is a bidirectional I/O port⁽⁵⁾

.

RH0/A16

RH0

—

79

I/O

O

ST

TTL

Digital I/O.

External memory address 16.

A16

RH1/A17

RH1

80

1

I/O

O

ST

TTL

Digital I/O.

External memory address 17.

A17

RH2/A18

RH2

I/O

O

ST

TTL

Digital I/O.

External memory address 18.

A18

RH3/A19

RH3

2

I/O

O

ST

TTL

Digital I/O.

External memory address 19.

A19

RH4/AN12

RH4

22

21

20

I/O

I

ST

Analog

Digital I/O.

Analog input 12.

AN12

RH5/AN13

RH5

I/O

I

ST

Analog

Digital I/O.

Analog input 13.

AN13

RH6/AN14/P1C

RH6

I/O

I

I/O

ST

Analog

ST

Digital I/O.

Analog input 14.

Alternate CCP1 PWM output C.

AN14

P1C⁽⁷⁾

RH7/AN15/P1B

RH7

—

19

I/O

I

ST

Analog

Digital I/O.

Analog input 15.

Alternate CCP1 PWM output B.

AN15

P1B⁽⁷⁾

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

Analog = Analog input

ST

I

= Schmitt Trigger input with CMOS levels

= Input

O

= Output

P

= Power

OD

= Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X8X devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.

6: PSP is available in Microcontroller mode only.

7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

DS30491C-page 20

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 1-2:

PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Type

Buffer

Type

Pin Name

PIC18F6X8X PIC18F8X8X

Description

TQFP PLCC

TQFP

PORTJ is a bidirectional I/O port⁽⁵⁾

Digital I/O.

.

RJ0/ALE

RJ0

—

62

I/O

O

ST

TTL

ALE

External memory address latch

enable.

RJ1/OE

RJ1

—

61

60

59

39

I/O

O

ST

TTL

Digital I/O.

External memory output enable.

OE

RJ2/WRL

RJ2

I/O

O

ST

TTL

Digital I/O.

External memory write low control.

WRL

RJ3/WRH

RJ3

I/O

O

ST

TTL

Digital I/O.

External memory write high control.

WRH

RJ4/BA0

RJ4

I/O

O

ST

TTL

Digital I/O.

System bus byte address 0 control.

BA0

RJ5/CE

CE

—

40

42

I/O

O

ST

TTL

Digital I/O

External memory chip enable.

RJ6/LB

RJ6

I/O

O

ST

TTL

Digital I/O.

External memory low byte select.

LB

RJ7/UB

RJ7

—

41

I/O

O

ST

TTL

Digital I/O.

External memory high byte select.

UB

VSS

VDD

9, 25, 19, 36,

41, 56 53, 68

11, 31,

51, 70

P

—

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

10,26, 2, 20,

38, 57 37, 49

12, 32,

48, 71

P

AVSS

AVDD

NC

20

19

—

30

29

26

25

—

P

—

Ground reference for analog modules.

Positive supply for analog modules.

No connect.

1, 18,

—

35, 52

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

Analog = Analog input

ST

I

= Schmitt Trigger input with CMOS levels

= Input

O

= Output

P

= Power

OD

= Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X8X devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.

6: PSP is available in Microcontroller mode only.

7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.

 2004 Microchip Technology Inc.

DS30491C-page 21

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 22

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 2-1:

CRYSTAL/CERAMIC

RESONATOROPERATION

(HS, XT OR LP

2.0

2.1

OSCILLATOR

CONFIGURATIONS

CONFIGURATION)

Oscillator Types

(1)

C1

OSC1

The PIC18F6585/8585/6680/8680 devices can be

operated in eleven different oscillator modes. The user

can program four configuration bits (FOSC3, FOSC2,

FOSC1 and FOSC0) to select one of these eleven

modes:

To

Internal

Logic

(3)

RF

XTAL

Sleep

(2)

RS

1. LP

2. XT

3. HS

4. RC

5. EC

6. ECIO

Low-Power Crystal

(1)

C2

PIC18FXX80/XX85

Crystal/Resonator

OSC2

High-Speed Crystal/Resonator

External Resistor/Capacitor

External Clock

Note 1: See Table 2-1 and Table 2-2 for recommended

values of C1 and C2.

2: A series resistor (RS) may be required for AT

External Clock with I/O

pin enabled

strip cut crystals.

3: RF varies with the oscillator mode chosen.

7. HS+PLL

8. RCIO

High-Speed Crystal/Resonator

with PLL enabled

External Resistor/Capacitor with

I/O pin enabled

TABLE 2-1:

CAPACITOR SELECTION FOR

CERAMIC RESONATORS

9. ECIO+SPLL External Clock with software

controlled PLL

Ranges Tested:

10. ECIO+PLL External Clock with PLL and I/O

pin enabled

Mode

Freq

C1

C2

XT

455 kHz

2.0 MHz

4.0 MHz

68-100 pF

15-68 pF

68-100 pF

15-68 pF

11. HS+SPLL

High-Speed Crystal/Resonator

with software control

HS

8.0 MHz

16.0 MHz

10-68 pF

10-22 pF

10-68 pF

10-22 pF

2.2

Crystal Oscillator/Ceramic

Resonators

These values are for design guidance only.

See notes following this table.

In XT, LP, HS, HS+PLL or HS+SPLL Oscillator modes,

a crystal or ceramic resonator is connected to the OSC1

and OSC2 pins to establish oscillation. Figure 2-1

shows the pin connections.

Resonators Used:

2.0 MHz Murata Erie CSA2.00MG

4.0 MHz Murata Erie CSA4.00MG

8.0 MHz Murata Erie CSA8.00MT

16.0 MHz Murata Erie CSA16.00MX

0.5%

The PIC18F6585/8585/6680/8680 oscillator design

requires the use of a parallel cut crystal.

Note:

Use of a series cut crystal may give a fre-

quency out of the crystal manufacturers

specifications.

All resonators used did not have built-in capacitors.

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

2: When operating below 3V VDD, or when

using certain ceramic resonators at any

voltage, it may be necessary to use high

gain HS mode, try a lower frequency

resonator, or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult the

resonator/crystal manufacturer for appro-

priate values of external components, or

verify oscillator performance.

 2004 Microchip Technology Inc.

DS30491C-page 23

PIC18F6585/8585/6680/8680

An external clock source may also be connected to the

OSC1 pin in the HS, XT and LP modes, as shown in

Figure 2-2.

TABLE 2-2:

CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Ranges Tested:

FIGURE 2-2:

EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR

LP OSC CONFIGURATION)

Mode

Freq

C1

C2

LP

32.0 kHz

200 kHz

1.0 MHz

4.0 MHz

8.0 MHz

20.0 MHz

25.0 MHz

33 pF

15 pF

33 pF

15 pF

XT

HS

47-68 pF

15 pF

47-68 pF

15 pF

OSC1

Clock from

Ext. System

PIC18FXX80/XX85

OSC2

15 pF

Open

15 pF

15-33 pF

TBD

15-33 pF

TBD

2.3

RC Oscillator

For timing insensitive applications, the “RC” and

“RCIO” device options offer additional cost savings.

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) val-

ues and the operating temperature. In addition to this,

the oscillator frequency will vary from unit to unit, due

to normal process parameter variation. Furthermore,

the difference in lead frame capacitance between pack-

age types will also affect the oscillation frequency,

especially for low CEXT values. The user also needs to

take into account variation due to tolerance of external

R and C components used. Figure 2-3 shows how the

R/C combination is connected.

These values are for design guidance only.

See notes following this table.

Crystals Used

32.0 kHz

200 kHz

1.0 MHz

4.0 MHz

8.0 MHz

Epson C-001R32.768K-A ± 20 PPM

STD XTL 200.000KHz

ECS ECS-10-13-1

ECS ECS-40-20-1

± 20 PPM

± 50 PPM

Epson CA-301 8.000M-C ± 30 PPM

20.0 MHz Epson CA-301 20.000M-C ± 30 PPM

In the RC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic.

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

2: Rs (see Figure 2-1) may be required in

HS mode, as well as XT mode, to avoid

overdriving crystals with low drive level

specifications.

FIGURE 2-3:

RC OSCILLATOR MODE

VDD

3: Since each resonator/crystal has its own

characteristics, the user should consult the

resonator/crystal manufacturer for appro-

priate values of external components, or

verify oscillator performance.

REXT

Internal

OSC1

Clock

CEXT

VSS

PIC18FXX80/XX85

OSC2/CLKO

FOSC/4

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

CEXT > 20pF

The RCIO Oscillator mode functions like the RC mode

except that the OSC2 pin becomes an additional gen-

eral purpose I/O pin. The I/O pin becomes bit 6 of

PORTA (RA6).

DS30491C-page 24

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

2.4

External Clock Input

2.5

Phase Locked Loop (PLL)

The EC, ECIO, EC+PLL and EC+SPLL Oscillator

modes require an external clock source to be con-

nected to the OSC1 pin. The feedback device between

OSC1 and OSC2 is turned off in these modes to save

current. There is a maximum 1.5 µs start-up required

after a Power-on Reset, or wake-up from Sleep mode.

A Phase Locked Loop circuit is provided as a

programmable option for users that want to multiply the

frequency of the incoming oscillator signal by 4. For an

input clock frequency of 10 MHz, the internal clock

frequency will be multiplied to 40 MHz. This is useful for

customers who are concerned with EMI due to

high-frequency crystals.

In the EC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic. Figure 2-4 shows the pin connections for the EC

Oscillator mode.

The PLL can only be enabled when the oscillator config-

uration bits are programmed for High-Speed Oscillator

or External Clock mode. If they are programmed for any

other mode, the PLL is not enabled and the system clock

will come directly from OSC1. There are two types of

PLL modes: Software Controlled PLL and Configuration

bits Controlled PLL. In Software Controlled PLL mode,

PIC18F6585/8585/6680/8680 executes at regular clock

frequency after all Reset conditions. During execution,

application can enable PLL and switch to 4x clock

frequency operation by setting the PLLEN bit in the

OSCCON register. In Configuration bits Controlled PLL

mode, PIC18F6585/8585/6680/8680 always executes

with 4x clock frequency.

FIGURE 2-4:

EXTERNAL CLOCK INPUT

OPERATION

(EC CONFIGURATION)

OSC1

Clock from

Ext. System

PIC18FXX80/XX85

OSC2

FOSC/4

The type of PLL is selected by programming the

FOSC<3:0> configuration bits in the CONFIG1H

Configuration register. The oscillator mode is specified

during device programming.

The ECIO Oscillator mode functions like the EC mode,

except that the OSC2 pin becomes an additional gen-

eral purpose I/O pin. The I/O pin becomes bit 6 of

PORTA (RA6). Figure 2-5 shows the pin connections

for the ECIO Oscillator mode.

A PLL lock timer is used to ensure that the PLL has

locked before device execution starts. The PLL lock

timer has a time-out that is called TPLL.

FIGURE 2-5:

EXTERNAL CLOCK INPUT

OPERATION

(ECIOCONFIGURATION)

OSC1

Clock from

Ext. System

PIC18FXX80/XX85

I/O (OSC2)

RA6

FIGURE 2-6:

PLL BLOCK DIAGRAM

PLL Enable

Phase

Comparator

FIN

Loop

Filter

VCO

SYSCLK

FOUT

Divide by 4

 2004 Microchip Technology Inc.

DS30491C-page 25

PIC18F6585/8585/6680/8680

execution mode. Figure 2-7 shows a block diagram of

the system clock sources. The clock switching feature

is enabled by programming the Oscillator Switching

Enable (OSCSEN) bit in configuration register,

CONFIG1H, to a ‘0’. Clock switching is disabled in an

erased device. See Section 12.0 “Timer1 Module” for

further details of the Timer1 oscillator. See Section 24.0

“Special Features of the CPU” for configuration

register details.

2.6

Oscillator Switching Feature

The PIC18F6585/8585/6680/8680 devices include a

feature that allows the system clock source to be

switched from the main oscillator to an alternate

low-frequency

clock

source.

For

the

PIC18F6585/8585/6680/8680 devices, this alternate

clock source is the Timer1 oscillator. If a low-frequency

crystal (32 kHz, for example) has been attached to the

Timer1 oscillator pins and the Timer1 oscillator has

been enabled, the device can switch to a low-power

FIGURE 2-7:

DEVICE CLOCK SOURCES

PIC18FXX80/XX85

Main Oscillator

OSC2

Tosc/4

4 x PLL

Sleep

TOSC

TT1P

TSCLK

OSC1

Timer1 Oscillator

T1OSO

T1OSCEN

Enable

Oscillator

Clock

Source

T1OSI

Clock Source Option

for other Modules

DS30491C-page 26

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

enabled (PLLEN = 1) and locked (LOCK = 1), else it will

be forced clear. When programmed with Configuration

Controlled PLL mode, the SCS1 bit will be forced clear.

2.6.1

SYSTEM CLOCK SWITCH BIT

The system clock source switching is performed under

software control. The System Clock Switch bits,

SCS1:SCS0 (OSCCON<1:0>), control the clock switch-

ing. When the SCS0 bit is ‘0’, the system clock source

comes from the main oscillator that is selected by the

FOSC configuration bits in configuration register,

CONFIG1H. When the SCS0 bit is set, the system clock

source will come from the Timer1 oscillator. The SCS0

bit is cleared on all forms of Reset.

Note:

The Timer1 oscillator must be enabled

and operating to switch the system clock

source. The Timer1 oscillator is enabled

by setting the T1OSCEN bit in the Timer1

Control register (T1CON). If the Timer1

oscillator is not enabled, then any write to

the SCS0 bit will be ignored (SCS0 bit

forced cleared) and the main oscillator will

continue to be the system clock source.

When FOSC bits are programmed for software PLL

mode, the SCS1 bit can be used to select between pri-

mary oscillator/clock and PLL output. The SCS1 bit will

only have an effect on the system clock if the PLL is

REGISTER 2-1:

OSCCON REGISTER

U-0

—

U-0

—

U-0

—

U-0

R/W-0

LOCK

R/W-0

SCS1

R/W-0

SCS0

—

PLLEN

bit 7

bit 0

bit 7-4 Unimplemented: Read as ‘0’

bit 3

bit 2

bit 1

LOCK: Phase Lock Loop Lock Status bit

1= Phase Lock Loop output is stable as system clock

0= Phase Lock Loop output is not stable and output cannot be used as system clock

PLLEN⁽¹⁾: Phase Lock Loop Enable bit

1= Enable Phase Lock Loop output as system clock

0= Disable Phase Lock Loop

SCS1: System Clock Switch bit 1

When PLLEN and LOCK bits are set:

1= Use PLL output

0= Use primary oscillator/clock input pin

When PLLEN or LOCK bit is cleared:

Bit is forced clear.

bit 0

SCS0⁽²⁾: System Clock Switch bit 0

When OSCSEN configuration bit = 0and T1OSCEN bit = 1:

1= Switch to Timer1 oscillator/clock pin

0= Use primary oscillator/clock input pin

When OSCSEN and T1OSCEN are in other states:

Bit is forced clear.

Note 1: PLLEN bit is ignored when configured for ECIO+PLL and HS+PLL. This bit is used

in ECIO+SPLL and HS+SPLL modes only.

2: The setting of SCS0 = 1supersedes SCS1 = 1.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc.

DS30491C-page 27

PIC18F6585/8585/6680/8680

The sequence of events that takes place when switch-

ing from the Timer1 oscillator to the main oscillator will

depend on the mode of the main oscillator. In addition

to eight clock cycles of the main oscillator, additional

delays may take place.

2.6.2

OSCILLATOR TRANSITIONS

PIC18F6585/8585/6680/8680 devices contain circuitry

to prevent “glitches” when switching between oscillator

sources. Essentially, the circuitry waits for eight rising

edges of the clock source that the processor is switch-

ing to. This ensures that the new clock source is stable

and that its pulse width will not be less than the shortest

pulse width of the two clock sources.

If the main oscillator is configured for an external

crystal (HS, XT, LP), then the transition will take place

after an oscillator start-up time (TOST) has occurred. A

timing diagram, indicating the transition from the

Timer1 oscillator to the main oscillator for HS, XT and

LP modes, is shown in Figure 2-9.

A timing diagram, indicating the transition from the

main oscillator to the Timer1 oscillator, is shown in

Figure 2-8. The Timer1 oscillator is assumed to be run-

ning all the time. After the SCS0 bit is set, the processor

is frozen at the next occurring Q1 cycle. After eight

synchronization cycles are counted from the Timer1

oscillator, operation resumes. No additional delays are

required after the synchronization cycles.

FIGURE 2-8:

TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR

Q1 Q2 Q3 Q4 Q1

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

TT1P

1

2

3

4

5

6

7

8

T1OSI

OSC1

TSCS

TOSC

Internal

System

Clock

TDLY

SCS

(OSCCON<0>)

Program

Counter

PC

PC + 2

PC + 4

Note:

TDLY is the delay from SCS high to first count of transition circuit.

FIGURE 2-9:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)

Q1 Q2 Q3 Q4 Q1 Q2 Q3

Q3

Q4

Q1

TT1P

T1OSI

OSC1

1

2

3

4

5

6

7

8

TOST

TSCS

TOSC

Internal

System Clock

SCS

(OSCCON<0>)

Program

Counter

PC + 6

PC

PC + 2

Note:

TOST = 1024 TOSC (drawing not to scale).

DS30491C-page 28

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

If the main oscillator is configured for HS mode with

If the main oscillator is configured for EC mode with PLL

active, only the PLL time-out (TPLL) will occur. The PLL

time-out is typically 2 ms and allows the PLL to lock to

the main oscillator frequency. A timing diagram, indicat-

ing the transition from the Timer1 oscillator to the main

oscillator for EC with PLL active, is shown in Figure 2-11.

PLL active, an oscillator start-up time (TOST) plus an

additional PLL time-out (TPLL) will occur. The PLL time-

out is typically 2 ms and allows the PLL to lock to the

main oscillator frequency. A timing diagram, indicating

the transition from the Timer1 oscillator to the main

oscillator for HS-PLL mode, is shown in Figure 2-10.

FIGURE 2-10:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1

(HS WITH PLL ACTIVE, SCS1 = 1)

TT1P

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q4

Q1

T1OSI

OSC1

TOST

TPLL

TSCS

TOSC

1

PLL Clock

Input

2

3

4

5

6

7

8

Internal System

Clock

SCS

(OSCCON<0>)

Program Counter

PC + 4

PC

PC + 2

Note:

TOST = 1024 TOSC (drawing not to scale).

FIGURE 2-11:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1

(EC WITH PLL ACTIVE, SCS1 = 1)

TT1P

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q4

Q1

T1OSI

OSC1

TPLL

TSCS

TOSC

PLL Clock

Input

1

2

3

4

5

6

7

8

Internal System

Clock

SCS

(OSCCON<0>)

Program Counter

PC

PC + 2

PC + 4

 2004 Microchip Technology Inc.

DS30491C-page 29

PIC18F6585/8585/6680/8680

If the main oscillator is configured in the RC, RCIO, EC

or ECIO modes, there is no oscillator start-up time-out.

Operation will resume after eight cycles of the main

oscillator have been counted. A timing diagram, indi-

cating the transition from the Timer1 oscillator to the

main oscillator for RC, RCIO, EC and ECIO modes, is

shown in Figure 2-12.

FIGURE 2-12:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)

Q3

Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1

TT1P

OSC

T

T1OSI

OSC1

6

1

4

5

7

8

2

3

Internal System

Clock

SCS

(OSCCON<0>)

TSCS

Program

Counter

PC + 2

PC

PC + 4

Note:

RC Oscillator mode assumed.

DS30491C-page 30

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

switching currents have been removed, Sleep mode

achieves the lowest current consumption of the device

(only leakage currents). Enabling any on-chip feature

2.7

Effects of Sleep Mode on the

On-Chip Oscillator

When the device executes a SLEEPinstruction, the on-

chip clocks and oscillator are turned off and the device

is held at the beginning of an instruction cycle (Q1

state). With the oscillator off, the OSC1 and OSC2

signals will stop oscillating. Since all the transistor

that will operate during Sleep will increase the current

consumed during Sleep. The user can wake from

Sleep through external Reset, Watchdog Timer Reset,

or through an interrupt.

TABLE 2-3:

OSC Mode

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

OSC1 Pin

OSC2 Pin

RC

Floating, external resistor should pull high

At logic low

RCIO

Floating, external resistor should pull high

Configured as PORTA, bit 6

At logic low

ECIO

Floating

EC

LP, XT, and HS

Feedback inverter disabled at

quiescent voltage level

Feedback inverter disabled at

quiescent voltage level

Note:

See Table 3-1 in Section 3.0 “Reset”, for time-outs due to Sleep and MCLR Reset.

With the PLL enabled (HS+PLL and EC+PLL Oscillator

2.8

Power-up Delays

mode), the time-out sequence following a Power-on

Reset is different from other oscillator modes. The

time-out sequence is as follows: First, the PWRT time-

out is invoked after a POR time delay has expired.

Then, the Oscillator Start-up Timer (OST) is invoked.

However, this is still not a sufficient amount of time to

allow the PLL to lock at high frequencies. The PWRT

timer is used to provide an additional fixed 2 ms

(nominal) time-out to allow the PLL ample time to lock

to the incoming clock frequency.

Power-up delays are controlled by two timers so that no

external Reset circuitry is required for most applica-

tions. The delays ensure that the device is kept in

Reset until the device power supply and clock are sta-

ble. For additional information on Reset operation, see

Section 3.0 “Reset”.

The first timer is the Power-up Timer (PWRT) which

optionally provides a fixed delay of 72 ms (nominal) on

power-up only (POR and BOR). The second timer is

the Oscillator Start-up Timer (OST), intended to keep

the chip in Reset until the crystal oscillator is stable.

 2004 Microchip Technology Inc.

DS30491C-page 31

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 32

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

Most registers are not affected by a WDT wake-up

since this is viewed as the resumption of normal oper-

3.0

RESET

The PIC18F6585/8585/6680/8680 devices differentiate

between various kinds of Reset:

ation. Status bits from the RCON register, RI, TO, PD,

POR and BOR, are set or cleared differently in different

Reset situations, as indicated in Table 3-2. These bits

are used in software to determine the nature of the

Reset. See Table 3-3 for a full description of the Reset

states of all registers.

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during Sleep

d) Watchdog Timer (WDT) Reset (during normal

operation)

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 3-1.

e) Programmable Brown-out Reset (BOR)

f) RESETInstruction

The Enhanced MCU devices have a MCLR noise filter

in the MCLR Reset path. The filter will detect and

ignore small pulses. The MCLR pin is not driven low by

any internal Resets, including the WDT.

g) Stack Full Reset

h) Stack Underflow Reset

Most registers are unaffected by a Reset. Their status

is unknown on POR and unchanged by all other

Resets. The other registers are forced to a “Reset

state” on Power-on Reset, MCLR, WDT Reset, Brown-

out Reset, MCLR Reset during Sleep and by the

RESETinstruction.

FIGURE 3-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

External Reset

MCLR

SLEEP

WDT

Module

Time-out

Reset

VDD Rise

Detect

Power-on Reset

VDD

Brown-out

Reset

S

BOREN

OST/PWRT

OST

10-bit Ripple Counter

Chip_Reset

R

Q

OSC1

PWRT

10-bit Ripple Counter

On-chip

RC OSC⁽¹⁾

Enable PWRT

(2)

Enable OST

Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.

2: See Table 3-1 for time-out situations.

 2004 Microchip Technology Inc.

DS30491C-page 33

PIC18F6585/8585/6680/8680

3.1

Power-on Reset (POR)

3.3

Oscillator Start-up Timer (OST)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected. To take advantage of the POR cir-

cuitry, tie the MCLR pin through a 1 kΩ to 10 kΩ resis-

tor to VDD. This will eliminate external RC components

usually needed to create a Power-on Reset delay. A

minimum rise rate for VDD is specified (parameter

D004). For a slow rise time, see Figure 3-2.

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycles (from OSC1 input) delay after the

PWRT delay is over (parameter #32). This ensures that

the crystal oscillator or resonator has started and

stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset, or wake-up from

Sleep.

When the device starts normal operation (i.e., exits the

Reset condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

3.4

PLL Lock Time-out

With the PLL enabled, the time-out sequence following

a Power-on Reset is different from other oscillator

modes. A portion of the Power-up Timer is used to pro-

vide a fixed time-out that is sufficient for the PLL to lock

to the main oscillator frequency. This PLL lock time-out

(TPLL) is typically 2 ms and follows the oscillator

start-up time-out (OST).

FIGURE 3-2:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

VDD

3.5

Brown-out Reset (BOR)

A configuration bit, BOREN, can disable (if clear/

programmed), or enable (if set) the Brown-out Reset

circuitry. If VDD falls below parameter D005 for greater

than parameter #35, the brown-out situation will reset

the chip. A Reset may not occur if VDD falls below

parameter D005 for less than parameter #35. The chip

will remain in Brown-out Reset until VDD rises above

BVDD. If the Power-up Timer is enabled, it will be

invoked after VDD rises above BVDD; it then will keep

the chip in Reset for an additional time delay (parame-

ter #33). If VDD drops below BVDD while the Power-up

Timer is running, the chip will go back into a Brown-out

Reset and the Power-up Timer will be initialized. Once

VDD rises above BVDD, the Power-up Timer will

execute the additional time delay.

D

R

R1

MCLR

PIC18FXX8X

C

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

3: R1 = 1 kΩ to 10 kΩ will limit any current flow-

ing into MCLR from external capacitor C, in

the event of MCLR/VPP pin breakdown due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS).

3.6

Time-out Sequence

On power-up, the time-out sequence is as follows:

First, PWRT time-out is invoked after the POR time

delay has expired. Then, OST is activated. The total

time-out will vary based on oscillator configuration and

the status of the PWRT. For example, in RC mode with

the PWRT disabled, there will be no time-out at all.

Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and

Figure 3-7 depict time-out sequences on power-up.

3.2

Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out

(parameter #33) only on power-up from the POR. The

Power-up Timer operates on an internal RC oscillator.

The chip is kept in Reset as long as the PWRT is active.

The PWRT’s time delay allows VDD to rise to an

acceptable level. A configuration bit is provided to

enable/disable the PWRT.

Since the time-outs occur from the POR pulse, the

time-outs will expire if MCLR is kept low long enough.

Bringing MCLR high will begin execution immediately

(Figure 3-5). This is useful for testing purposes or to

synchronize more than one PIC18FXX8X device

operating in parallel.

The power-up time delay will vary from chip-to-chip due

to VDD, temperature and process variation. See DC

parameter #33 for details.

Table 3-2 shows the Reset conditions for some Special

Function Registers while Table 3-3 shows the Reset

conditions for all of the registers.

DS30491C-page 34

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 3-1:

TIME-OUT IN VARIOUS SITUATIONS

Power-up⁽²⁾

Wake-up from

Sleep or

Oscillator Switch

Oscillator

Configuration

Brown-out

PWRTE = 0

HS with PLL enabled⁽¹⁾72 ms + 1024 TOSC + 2ms

PWRTE = 1

1024 TOSC + 2 ms 1024 TOSC + 2 ms 1024 TOSC + 2 ms

EC with PLL enabled⁽¹⁾

72 ms + 2ms

72 ms + 1024 TOSC

72 ms

1.5 µs + 2 ms

1024 TOSC

1.5 µs

2 ms

1024 TOSC

1.5 µs

1.5 µs + 2 ms

1024 TOSC

1.5 µs⁽³⁾

HS, XT, LP

EC

External RC

72 ms

1.5 µs

Note 1: 2 ms is the nominal time required for the 4x PLL to lock.

2: 72 ms is the nominal power-up timer delay if implemented.

3: 1.5 µs is the recovery time from Sleep. There is no recovery time from oscillator switch.

REGISTER 3-1:

RCON REGISTER BITS AND POSITIONS

R/W-0

IPEN

U-0

—

U-0

—

R/W-1

RI

R/W-1

TO

R/W-1

PD

R/W-1

POR

R/W-0

BOR

bit 7

Note:

bit 0

Refer to Section 4.14 “RCON Register” for bit definitions.

TABLE 3-2:

STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR

RCON REGISTER

Program

Counter

RCON

Register

Condition

RI TO PD POR BOR STKFUL STKUNF

Power-on Reset

0000h

0--1 1100

0--u uuuu

1

u

1

u

1

u

0

u

0

u

MCLR Reset during normal

operation

Software Reset during normal

operation

0000h

0--0 uuuu

0--u uu11

0

u

1

u

1

u

Stack Full Reset during normal

operation

Stack Underflow Reset during

normal operation

MCLR Reset during Sleep

WDT Reset

0000h

0--u 10uu

0--u 01uu

u--u 00uu

0--1 11u0

u--u 00uu

u

1

u

1

u

1

0

1

0

1

0

1

0

u

1

u

0

u

WDT Wake-up

PC + 2

0000h

PC + 2⁽¹⁾

Brown-out Reset

Interrupt wake-up from Sleep

Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’

Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (000008h or 000018h).

 2004 Microchip Technology Inc.

DS30491C-page 35

PIC18F6585/8585/6680/8680

TABLE 3-3:

Register

TOSU

INITIALIZATION CONDITIONS FOR ALL REGISTERS

MCLR Resets

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Applicable Devices

PIC18F6X8X PIC18F8X8X

---0 0000

0000 0000

uu-0 0000

---0 0000

0000 0000

--00 0000

0000 0000

uuuu uuuu

0000 000x

1111 1111

1100 0000

N/A

---0 uuuu⁽³⁾

uuuu uuuu⁽³⁾

uu-u uuuu⁽³⁾

---u uuuu

uuuu uuuu

PC + 2⁽²⁾

--uu uuuu

uuuu uuuu

uuuu uuuu⁽¹⁾

N/A

---0 0000

TOSH

0000 0000

00-0 0000

---0 0000

0000 0000

--00 0000

0000 0000

xxxx xxxx

0000 000x

1111 1111

1100 0000

N/A

TOSL

STKPTR

PCLATU

PCLATH

PCL

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

PRODH

PRODL

INTCON

INTCON2

INTCON3

INDF0

POSTINC0

POSTDEC0

PREINC0

PLUSW0

FSR0H

N/A

---- xxxx

xxxx xxxx

N/A

---- uuuu

uuuu uuuu

N/A

---- uuuu

uuuu uuuu

N/A

FSR0L

WREG

INDF1

POSTINC1

POSTDEC1

PREINC1

PLUSW1

N/A

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

DS30491C-page 36

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 3-3:

Register

FSR1H

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

---- xxxx

---- uuuu

PIC18F6X8X PIC18F8X8X

FSR1L

xxxx xxxx

---- 0000

N/A

uuuu uuuu

---- 0000

N/A

uuuu uuuu

---- uuuu

N/A

BSR

INDF2

POSTINC2

POSTDEC2

PREINC2

PLUSW2

FSR2H

N/A

---- xxxx

xxxx xxxx

---x xxxx

0000 0000

xxxx xxxx

1111 1111

---- 0000

--00 0101

---- ---0

0--q 11qq

xxxx xxxx

0-00 0000

0000 0000

1111 1111

-000 0000

xxxx xxxx

0000 0000

---- uuuu

uuuu uuuu

---u uuuu

uuuu uuuu

1111 1111

---- 0000

--00 0101

---- ---0

0--q qquu

uuuu uuuu

u-uu uuuu

0000 0000

1111 1111

-000 0000

uuuu uuuu

0000 0000

---- uuuu

uuuu uuuu

---u uuuu

uuuu uuuu

---- uuuu

--uu uuuu

---- ---u

u--u qquu

uuuu uuuu

u-uu uuuu

uuuu uuuu

1111 1111

-uuu uuuu

uuuu uuuu

FSR2L

STATUS

TMR0H

TMR0L

T0CON

OSCCON

LVDCON

WDTCON

RCON⁽⁴⁾

TMR1H

TMR1L

T1CON

TMR2

PR2

T2CON

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

 2004 Microchip Technology Inc.

DS30491C-page 37

PIC18F6585/8585/6680/8680

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Register

Applicable Devices

ADRESH

xxxx xxxx

uuuu uuuu

PIC18F6X8X PIC18F8X8X

ADRESL

ADCON0

ADCON1

ADCON2

CCPR1H

CCPR1L

CCP1CON

CCPR2H

CCPR2L

CCP2CON

CCPAS1

CVRCON

CMCON

TMR3H

xxxx xxxx

--00 0000

0-00 0000

xxxx xxxx

0000 0000

xxxx xxxx

--00 0000

0000 0000

xxxx xxxx

0000 0000

0000 ----

0000 0000

0000 0010

0000 000x

---- --00

0000 0000

xx-0 x000

00-0 x000

uuuu uuuu

--00 0000

0-00 0000

uuuu uuuu

0000 0000

uuuu uuuu

--00 0000

0000 0000

uuuu uuuu

0000 ----

0000 0000

0000 0010

0000 000x

---- --00

0000 0000

uu-0 u000

00-0 u000

uuuu uuuu

--uu uuuu

u-uu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

uuuu ----

uuuu uuuu

---- --uu

uuuu uuuu

uu-0 u000

uu-u uuuu

TMR3L

T3CON

PSPCON

SPBRG

RCREG

TXREG

TXSTA

RCSTA

EEADRH

EEADR

EEDATA

EECON2

EECON1

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

DS30491C-page 38

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 3-3:

Register

IPR3

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

1111 1111

uuuu uuuu

PIC18F6X8X PIC18F8X8X

PIR3

0000 0000

-1-1 1111

-0-0 0000

1111 1111

0000 0000

0-00 --00

1111 1111

---1 1111

1111 1111

0000 -111

1111 1111

-111 1111⁽⁵⁾

xxxx xxxx

---x xxxx

xxxx xxxx

-xxx xxxx⁽⁵⁾

0000 0000

-1-1 1111

-0-0 0000

1111 1111

0000 0000

0-00 --00

1111 1111

---1 1111

1111 1111

0000 -111

1111 1111

-111 1111⁽⁵⁾

uuuu uuuu

---u uuuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

uuuu uuuu

-u-u uuuu

-u-u uuuu⁽¹⁾

-u-u uuuu

uuuu uuuu

uuuu uuuu⁽¹⁾

uuuu uuuu

u-uu --uu

uuuu uuuu

---u uuuu

uuuu uuuu

uuuu -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

uuuu uuuu

---u uuuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

PIE3

IPR2

PIR2

PIE2

IPR1

PIR1

PIE1

MEMCON

TRISJ

TRISH

TRISG

TRISF

TRISE

TRISD

TRISC

TRISB

TRISA^(5,6)

LATJ

LATH

LATG

LATF

LATE

LATD

LATC

LATB

LATA^(5,6)

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

 2004 Microchip Technology Inc.

DS30491C-page 39

PIC18F6585/8585/6680/8680

TABLE 3-3:

Register

PORTJ

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Applicable Devices

xxxx xxxx

uuuu uuuu

PIC18F6X8X PIC18F8X8X

PORTH

0000 xxxx

--xx xxxx

x000 0000

---- -000

xxxx xxxx

-x0x 0000⁽⁵⁾

0000 0000

-1-0 0-00

0000 0000

0001 0000

0000 0000

0000 ----

00-- -000

0000 0000

1000 000-

100- 000-

xxxx xxxx

-xxx xxxx

0000 uuuu

--uu uuuu

u000 0000

---- -000

uuuu uuuu

-u0u 0000⁽⁵⁾

0000 0000

-1-0 0-00

0000 0000

0001 0000

0000 0000

0000 ----

00-- -000

0000 0000

1000 000-

100- 000-

uuuu uuuu

-uuu uuuu

uuuu uuuu

--uu uuuu

u000 0000

---- -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

uuuu uuuu

-u-u u-uu

uuuu uuuu

uuuu ----

uu-- -uuu

uuuu uuuu

uuuu uuu-

uuu- uuu-

uuuu uuuu

-uuu uuuu

PORTG

PORTF

PORTE

PORTD

PORTC

PORTB

PORTA^(5,6)

SPBRGH

BAUDCON

ECCP1DEL

ECANCON

TXERRCNT

RXERRCNT

COMSTAT

CIOCON

BRGCON3

BRGCON2

BRGCON1

CANCON

CANSTAT

RXB0D7

RXB0D6

RXB0D5

RXB0D4

RXB0D3

RXB0D2

RXB0D1

RXB0D0

RXB0DLC

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

DS30491C-page 40

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 3-3:

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESET Instruction

Stack Resets

RXB0EIDL

RXB0EIDH

RXB0SIDL

RXB0SIDH

RXB0CON

RXB1D7

PIC18F6X8X PIC18F8X8X

xxxx xxxx

xxxx x-xx

xxxx xxxx

000- 0000

xxxx xxxx

-xxx xxxx

xxxx xxxx

xxxx x-xx

xxxx xxxx

000- 0000

xxxx xxxx

-x-- xxxx

xxxx xxxx

xxx- x-xx

uuuu uuuu

uuuu u-uu

uuuu uuuu

000- 0000

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

000- 0000

uuuu uuuu

-u-- uuuu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuuu u-uu

uuuu uuuu

uuu- uuuu

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

uuu- uuuu

uuuu uuuu

-u-- uuuu

uuuu uuuu

-uuu uuuu

uuu- u-uu

RXB1D6

RXB1D5

RXB1D4

RXB1D3

RXB1D2

RXB1D1

RXB1D0

RXB1DLC

RXB1EIDL

RXB1EIDH

RXB1SIDL

RXB1SIDH

RXB1CON

TXB0D7

TXB0D6

TXB0D5

TXB0D4

TXB0D3

TXB0D2

TXB0D1

TXB0D0

TXB0DLC

TXB0EIDL

TXB0EIDH

TXB0SIDL

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

 2004 Microchip Technology Inc.

DS30491C-page 41

PIC18F6585/8585/6680/8680

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Register

Applicable Devices

TXB0SIDH

TXB0CON

TXB1D7

PIC18F6X8X PIC18F8X8X

xxxx xxxx

0000 0-00

xxxx xxxx

-x-- xxxx

xxxx xxxx

xxx- x-xx

xxxx xxxx

0000 0-00

xxxx xxxx

-x-- xxxx

xxxx xxxx

xxx- x-xx

0000 0-00

xxxx xxxx

uuuu uuuu

0000 0-00

uuuu uuuu

-u-- uuuu

uuuu uuuu

uuu- u-uu

uuuu uuuu

0000 0-00

uuuu uuuu

-u-- uuuu

uuuu uuuu

uuu- u-uu

0000 0-00

uuuu uuuu

uuuu u-uu

uuuu uuuu

-u-- uuuu

uuuu uuuu

uuu- uu-u

-uuu uuuu

uuuu u-uu

0uuu uuuu

-u-- uuuu

uuuu uuuu

uuu- u-uu

uuuu u-uu

uuuu uuuu

TXB1D6

TXB1D5

TXB1D4

TXB1D3

TXB1D2

TXB1D1

TXB1D0

TXB1DLC

TXB1EIDL

TXB1EIDH

TXB1SIDL

TXB1SIDH

TXB1CON

TXB2D7

TXB2D6

TXB2D5

TXB2D4

TXB2D3

TXB2D2

TXB2D1

TXB2D0

TXB2DLC

TXB2EIDL

TXB2EIDH

TXB2SIDL

TXB2SIDH

TXB2CON

RXM1EIDL

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

DS30491C-page 42

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 3-3:

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESET Instruction

Stack Resets

RXM1EIDH

RXM1SIDL

RXM1SIDH

RXM0EIDL

RXM0EIDH

RXM0SIDL

RXM0SIDH

RXF5EIDL

RXF5EIDH

RXF5SIDL

RXF5SIDH

RXF4EIDL

RXF4EIDH

RXF4SIDL

RXF4SIDH

RXF3EIDL

RXF3EIDH

RXF3SIDL

RXF3SIDH

RXF2EIDL

RXF2EIDH

RXF2SIDL

RXF2SIDH

RXF1EIDL

RXF1EIDH

RXF1SIDL

RXF1SIDH

RXF0EIDL

RXF0EIDH

RXF0SIDL

RXF0SIDH

PIC18F6X8X PIC18F8X8X

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

 2004 Microchip Technology Inc.

DS30491C-page 43

PIC18F6585/8585/6680/8680

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Register

Applicable Devices

B5D7⁽⁷⁾

B5D6⁽⁷⁾

B5D5⁽⁷⁾

B5D4⁽⁷⁾

B5D3⁽⁷⁾

B5D2⁽⁷⁾

B5D1⁽⁷⁾

B5D0⁽⁷⁾

B5DLC⁽⁷⁾

B5EIDL⁽⁷⁾

B5EIDH⁽⁷⁾

B5SIDL⁽⁷⁾

B5SIDH⁽⁷⁾

B5CON⁽⁷⁾

B4D7⁽⁷⁾

B4D6⁽⁷⁾

B4D5⁽⁷⁾

B4D4⁽⁷⁾

B4D3⁽⁷⁾

B4D2⁽⁷⁾

B4D1⁽⁷⁾

B4D0⁽⁷⁾

B4DLC⁽⁷⁾

B4EIDL⁽⁷⁾

B4EIDH⁽⁷⁾

B4SIDL⁽⁷⁾

B4SIDH⁽⁷⁾

B4CON⁽⁷⁾

B3D7⁽⁷⁾

PIC18F6X8X PIC18F8X8X

xxxx xxxx

-xxx xxxx

xxxx xxxx

xxxx x-xx

0000 0000

xxxx xxxx

-xxx xxxx

xxxx xxxx

xxxx x-xx

xxxx xxxx

0000 0000

xxxx xxxx

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

0000 0000

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

0000 0000

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

B3D6⁽⁷⁾

B3D5⁽⁷⁾

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

DS30491C-page 44

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 3-3:

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESET Instruction

Stack Resets

B3D4⁽⁷⁾

B3D3⁽⁷⁾

B3D2⁽⁷⁾

B3D1⁽⁷⁾

PIC18F6X8X PIC18F8X8X

xxxx xxxx

-xxx xxxx

xxxx xxxx

xxxx x-xx

xxxx xxxx

0000 0000

xxxx xxxx

-xxx xxxx

xxxx xxxx

xxxx x-xx

xxxx xxxx

0000 0000

xxxx xxxx

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

0000 0000

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

0000 0000

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

B3D0⁽⁷⁾

B3DLC⁽⁷⁾

B3EIDL⁽⁷⁾

B3EIDH⁽⁷⁾

B3SIDL⁽⁷⁾

B3SIDH⁽⁷⁾

B3CON⁽⁷⁾

B2D7⁽⁷⁾

B2D6⁽⁷⁾

B2D5⁽⁷⁾

B2D4⁽⁷⁾

B2D3⁽⁷⁾

B2D2⁽⁷⁾

B2D1⁽⁷⁾

B2D0⁽⁷⁾

B2DLC⁽⁷⁾

B2EIDL⁽⁷⁾

B2EIDH⁽⁷⁾

B2SIDL⁽⁷⁾

B2SIDH⁽⁷⁾

B2CON⁽⁷⁾

B1D7⁽⁷⁾

B1D6⁽⁷⁾

B1D5⁽⁷⁾

B1D4⁽⁷⁾

B1D3⁽⁷⁾

B1D2⁽⁷⁾

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

 2004 Microchip Technology Inc.

DS30491C-page 45

PIC18F6585/8585/6680/8680

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Register

Applicable Devices

B1D1⁽⁷⁾

B1D0⁽⁷⁾

PIC18F6X8X PIC18F8X8X

xxxx xxxx

-xxx xxxx

xxxx xxxx

xxxx x-xx

xxxx xxxx

0000 0000

xxxx xxxx

-xxx xxxx

xxxx xxxx

xxxx x-xx

xxxx xxxx

0000 0000

---0 00--

0000 0000

0000 00--

0000 0000

0000 0101

0101 0000

---0 0000

0000 0000

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

0000 0000

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

0000 0000

---u uu--

0000 0000

0000 00--

0000 0000

0000 0101

0101 0000

---0 0000

0000 0000

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

-uuu uuuu

uuuu uuuu

uuuu u-uu

uuuu uuuu

---u uu--

uuuu uuuu

uuuu uu--

uuuu uuuu

-u-- uuuu

uuuu uuuu

B1DLC⁽⁷⁾

B1EIDL⁽⁷⁾

B1EIDH⁽⁷⁾

B1SIDL⁽⁷⁾

B1SIDH⁽⁷⁾

B1CON⁽⁷⁾

B0D7⁽⁷⁾

B0D6⁽⁷⁾

B0D5⁽⁷⁾

B0D4⁽⁷⁾

B0D3⁽⁷⁾

B0D2⁽⁷⁾

B0D1⁽⁷⁾

B0D0⁽⁷⁾

B0DLC⁽⁷⁾

B0EIDL⁽⁷⁾

B0EIDH⁽⁷⁾

B0SIDL⁽⁷⁾

B0SIDH⁽⁷⁾

B0CON⁽⁷⁾

TXBIE⁽⁷⁾

BIE0⁽⁷⁾

BSEL0⁽⁷⁾

MSEL3⁽⁷⁾

MSEL2⁽⁷⁾

MSEL1⁽⁷⁾

MSEL0⁽⁷⁾

SDFLC⁽⁷⁾

RXFCON1⁽⁷⁾

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

DS30491C-page 46

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 3-3:

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESET Instruction

Stack Resets

RXFCON0⁽⁷⁾

PIC18F6X8X PIC18F8X8X

0000 0000

0001 0001

0000 0000

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

0000 0000

0001 0001

0000 0000

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

-uuu uuuu

RXFBCON7⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXFBCON6⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXFBCON5⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXFBCON4⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXFBCON3⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXFBCON2⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXFBCON1⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXFBCON0⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF15EIDL⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF15EIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF15SIDL⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF15SIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF14EIDL⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF14EIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF14SIDL⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF14SIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF13EIDL⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF13EIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF13SIDL⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF13SIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF12EIDL⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF12EIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF12SIDL⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF12SIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF11EIDL⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF11EIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF11SIDL⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF11SIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF10EIDL⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF10EIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

 2004 Microchip Technology Inc.

DS30491C-page 47

PIC18F6585/8585/6680/8680

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

Power-on Reset,

Brown-out Reset

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Register

Applicable Devices

RXF10SIDL⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF10SIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

-uuu uuuu

RXF9EIDL⁽⁷⁾

RXF9EIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF9SIDL⁽⁷⁾

PIC18F6X8X PIC18F8X8X

RXF9SIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF8EIDL⁽⁷⁾

PIC18F6X8X PIC18F8X8X

RXF8EIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF8SIDL⁽⁷⁾

PIC18F6X8X PIC18F8X8X

RXF8SIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF7EIDL⁽⁷⁾

PIC18F6X8X PIC18F8X8X

RXF7EIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF7SIDL⁽⁷⁾

PIC18F6X8X PIC18F8X8X

RXF7SIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF6EIDL⁽⁷⁾

PIC18F6X8X PIC18F8X8X

RXF6EIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

RXF6SIDL⁽⁷⁾

PIC18F6X8X PIC18F8X8X

RXF6SIDH⁽⁷⁾PIC18F6X8X PIC18F8X8X

PIC18F6X8X PIC18F8X8X

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

DS30491C-page 48

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 3-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA 1 kΩ RESISTOR)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 3-4:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 3-5:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

 2004 Microchip Technology Inc.

DS30491C-page 49

PIC18F6585/8585/6680/8680

FIGURE 3-6:

SLOW RISE TIME (MCLR TIED TO VDD VIA 1 kΩ RESISTOR)

5V

1V

0V

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

FIGURE 3-7:

TIME-OUT SEQUENCE ON POR W/ PLL ENABLED

(MCLR TIED TO VDD VIA 1 kΩ RESISTOR)

VDD

MCLR

IINTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

TPLL

PLL TIME-OUT

INTERNAL RESET

Note:

TOST = 1024 clock cycles.

TPLL ≈ 2 ms max. First three stages of the PWRT timer.

DS30491C-page 50

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

4.1.1

PIC18F8X8X PROGRAM MEMORY

MODES

4.0

MEMORY ORGANIZATION

There

are

three

memory

blocks

in

PIC18F8X8X devices differ significantly from their

PIC18 predecessors in their utilization of program

memory. In addition to available on-chip Flash program

memory, these controllers can also address up to

2 Mbytes of external program memory through the

external memory interface. There are four distinct

operating modes available to the controllers:

PIC18F6585/8585/6680/8680 devices. They are:

• Program Memory

• Data RAM

• Data EEPROM

Data and program memory use separate busses which

allows for concurrent access of these blocks. Additional

detailed information for Flash program memory and data

EEPROM is provided in Section 5.0 “Flash Program

Memory” and Section 7.0 “Data EEPROM Memory”,

respectively.

• Microprocessor (MP)

• Microprocessor with Boot Block (MPBB)

• Extended Microcontroller (EMC)

• Microcontroller (MC)

In addition to on-chip Flash, the PIC18F8X8X devices

are also capable of accessing external program mem-

ory through an external memory bus. Depending on the

selected operating mode (discussed in Section 4.1.1

“PIC18F8X8X Program Memory Modes”), the

controllers may access either internal or external pro-

gram memory exclusively, or both internal and external

memory in selected blocks. Additional information on

the external memory interface is provided in

Section 6.0 “External Memory Interface”.

The Program Memory mode is determined by setting

the two Least Significant bits of the CONFIG3L config-

uration byte, as shown in Register 4-1. (See also

Section 24.1 “Configuration Bits” for additional

details on the device configuration bits.)

The Program Memory modes operate as follows:

• The Microprocessor Mode permits access only

to external program memory; the contents of the

on-chip Flash memory are ignored. The 21-bit

program counter permits access to a 2-MByte

linear program memory space.

4.1

Program Memory Organization

• The Microprocessor with Boot Block Mode

accesses on-chip Flash memory from addresses

000000h to 0007FFh. Above this, external

program memory is accessed all the way up to

the 2-MByte limit. Program execution auto-

matically switches between the two memories as

required.

A 21-bit program counter is capable of addressing the

2-Mbyte program memory space. Accessing a location

between the physically implemented memory and the

2-Mbyte address will cause a read of all ‘0’s (a NOP

instruction).

The PIC18F6585 and PIC18F8585 each have

48 Kbytes of on-chip Flash memory, while the

PIC18F6680 and PIC18F8680 have 64 Kbytes of Flash.

This means that PIC18FX585 devices can store inter-

nally up to 24,576 single-word instructions and

PIC18FX680 devices can store up to 32,768 single-word

instructions.

• The Microcontroller Mode accesses only

on-chip Flash memory. Attempts to read above

the physical limit of the on-chip Flash (0BFFFh for

the PIC18F8585, 0FFFFh for the PIC18F8680)

causes a read of all ‘0’s (a NOPinstruction).

The Microcontroller mode is the only operating

mode available to PIC18F6X8X devices.

The Reset vector address is at 0000h and the interrupt

vector addresses are at 0008h and 0018h.

• The Extended Microcontroller Mode allows

access to both internal and external program

memories as a single block. The device can

access its entire on-chip Flash memory; above

this, the device accesses external program mem-

ory up to the 2-MByte program space limit. As

with Boot Block mode, execution automatically

switches between the two memories as required.

Figure 4-1 shows the program memory map for

PIC18F6585/8585 devices while Figure 4-2 shows the

program memory map for PIC18F6680/8680 devices.

In all modes, the microcontroller has complete access

to data RAM and EEPROM.

Figure 4-3 compares the memory maps of the different

Program Memory modes. The differences between on-

chip and external memory access limitations are more

fully explained in Table 4-1.

 2004 Microchip Technology Inc.

DS30491C-page 51

PIC18F6585/8585/6680/8680

FIGURE 4-1:

INTERNAL PROGRAM

MEMORY MAP AND

STACK FOR

FIGURE 4-2:

INTERNAL PROGRAM

MEMORY MAP AND

STACK FOR

PIC18F6585/8585

PIC18F6680/8680

PC<20:0>

21

CALL,RCALL,RETURN

RETFIE,RETLW

CALL,RCALL,RETURN

RETFIE,RETLW

Stack Level 1

•

Stack Level 31

Reset Vector

Stack Level 31

Reset Vector

000000h

High Priority Interrupt Vector

Low Priority Interrupt Vector

High Priority Interrupt Vector

Low Priority Interrupt Vector

000008h

000018h

000008h

000018h

On-Chip Flash

Program Memory

00BFFFh

00C000h

On-Chip Flash

Program Memory

00FFFFh

010000h

Read ‘0’

1FFFFFh

200000h

1FFFFFh

200000h

TABLE 4-1:

MEMORY ACCESS FOR PIC18F8X8X PROGRAM MEMORY MODES

Internal Program Memory External Program Memory

Operating Mode

Execution

Table Read

From

Execution

Table Read

From

Table Write To

From

Microprocessor

No Access

Yes

No Access

Yes

No Access

Yes

Microprocessor w/

Boot Block

Microcontroller

Yes

No Access

Yes

No Access

Yes

No Access

Yes

Extended

Microcontroller

DS30491C-page 52

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 4-1:

CONFIG3L CONFIGURATION BYTE

R/P-1

WAIT

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

PM1

R/P-1

PM0

bit 7

bit 0

bit 7

WAIT: External Bus Data Wait Enable bit

1= Wait selections unavailable, device will not wait

0= Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>)

bit 6-2

bit 1-0

Unimplemented: Read as ‘0’

PM1:PM0: Processor Data Memory Mode Select bits

11= Microcontroller mode

10= Microprocessor mode

01= Microcontroller with Boot Block mode

00= Extended Microcontroller mode

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

- n = Value after erase

FIGURE 4-3:

MEMORY MAPS FOR PIC18F8X8X PROGRAM MEMORY MODES

Microprocessor

with Boot Block

Mode

Extended

Microcontroller

Mode

Microprocessor

Microcontroller

Mode

000000h

On-Chip

Program

Memory

(No

On-Chip

Program

Memory

On-Chip

Program

Memory

Program

Memory

00BFFFh⁽¹⁾

00FFFFh⁽²⁾

00BFFFh⁽¹⁾

00FFFFh⁽²⁾

access)

0007FFh

000800h

00C000h⁽¹⁾

010000h⁽²⁾

00C000h⁽¹⁾

010000h⁽²⁾

External

Program

Memory

Reads

‘0’s

External

Program

Memory

External

Program

Memory

1FFFFFh

External On-Chip

Memory

Flash

External

Memory

External

Memory

On-Chip

Flash

On-Chip

Flash

On-Chip

Flash

Note 1: PIC18F6585 and PIC18F8585.

2: PIC18F6680 and PIC18F8680.

 2004 Microchip Technology Inc.

DS30491C-page 53

PIC18F6585/8585/6680/8680

4.2.2

RETURN STACK POINTER

(STKPTR)

4.2

Return Address Stack

The return address stack allows any combination of up

to 31 program calls and interrupts to occur. The PC

(Program Counter) is pushed onto the stack when a

CALLor RCALLinstruction is executed or an interrupt is

Acknowledged. The PC value is pulled off the stack on

a RETURN, RETLW, or a RETFIE instruction. PCLATU

and PCLATH are not affected by any of the RETURNor

CALLinstructions.

The STKPTR register contains the stack pointer value,

the STKFUL (Stack Full) status bit, and the STKUNF

(Stack Underflow) status bits. Register 4-2 shows the

STKPTR register. The value of the stack pointer can be

0 through 31. The stack pointer increments when values

are pushed onto the stack and decrements when values

are popped off the stack. At Reset, the stack pointer

value will be ‘0’. The user may read and write the stack

pointer value. This feature can be used by a Real-Time

Operating System for return stack maintenance.

The stack operates as a 31-word by 21-bit RAM and a

5-bit stack pointer, with the stack pointer initialized to

00000b after all Resets. There is no RAM associated

with stack pointer 00000b. This is only a Reset value.

During a CALLtype instruction causing a push onto the

stack, the stack pointer is first incremented and the

RAM location pointed to by the stack pointer is written

with the contents of the PC. During a RETURN type

instruction causing a pop from the stack, the contents

of the RAM location pointed to by the STKPTR are

transferred to the PC and then the stack pointer is

decremented.

After the PC is pushed onto the stack 31 times (without

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit can only be cleared in software or

by a POR.

The action that takes place when the stack becomes

full depends on the state of the STVREN (Stack

Overflow Reset Enable) configuration bit. Refer to

Section 25.0 “Instruction Set Summary” for a

description of the device configuration bits. If STVREN

is set (default), the 31st push will push the (PC + 2)

value onto the stack, set the STKFUL bit and reset the

device. The STKFUL bit will remain set and the stack

pointer will be set to ‘0’.

The stack space is not part of either program or data

space. The stack pointer is readable and writable and

the address on the top of the stack is readable and writ-

able through SFR registers. Data can also be pushed

to or popped from the stack, using the top-of-stack

SFRs. Status bits indicate if the stack pointer is at or

beyond the 31 levels provided.

If STVREN is cleared, the STKFUL bit will be set on the

31st push and the stack pointer will increment to 31.

Any additional pushes will not overwrite the 31st push

and STKPTR will remain at 31.

4.2.1

TOP-OF-STACK ACCESS

When the stack has been popped enough times to

unload the stack, the next pop will return a value of zero

to the PC and sets the STKUNF bit while the stack

pointer remains at ‘0’. The STKUNF bit will remain set

until cleared in software or a POR occurs.

The top of the stack is readable and writable. Three

register locations, TOSU, TOSH and TOSL, hold the

contents of the stack location pointed to by the

STKPTR register. This allows users to implement a

software stack if necessary. After a CALL, RCALLor

interrupt, the software can read the pushed value by

reading the TOSU, TOSH and TOSL registers. These

values can be placed on a user defined software stack.

At return time, the software can replace the TOSU,

TOSH and TOSL and do a return.

Note:

Returning a value of zero to the PC on an

underflow has the effect of vectoring the

program to the Reset vector, where the

stack conditions can be verified and

appropriate actions can be taken.

The user must disable the global interrupt enable bits

during this time to prevent inadvertent stack

operations.

DS30491C-page 54

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 4-2:

STKPTR REGISTER

R/C-0 R/C-0

U-0

—

R/W-0

SP4

R/W-0

SP3

R/W-0

SP2

R/W-0

SP1

R/W-0

SP0

STKFUL⁽¹⁾STKUNF⁽¹⁾

bit 7

bit 0

bit 7

bit 6

STKFUL: Stack Full Flag bit

1= Stack became full or overflowed

0= Stack has not become full or overflowed

STKUNF: Stack Underflow Flag bit

1= Stack underflow occurred

0= Stack underflow did not occur

bit 5

Unimplemented: Read as ‘0’

bit 4-0

SP4:SP0: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.

Legend:

C = Clearable bit

- n = Value at POR ‘1’ = Bit is set

R = Readable bit U = Unimplemented bit, read as ‘0’ W = Writable bit

‘0’ = Bit is cleared x = Bit is unknown

FIGURE 4-4:

RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

Return Address Stack

11111

11110

11101

STKPTR<4:0>

TOSU

00h

TOSH

1Ah

TOSL

34h

00010

00011

001A34h 00010

000D58h 00001

00000

Top-of-Stack

4.2.3

PUSHAND POPINSTRUCTIONS

4.2.4

STACK FULL/UNDERFLOW RESETS

Since the Top-of-Stack (TOS) is readable and writable,

the ability to push values onto the stack and pull values

off the stack, without disturbing normal program execu-

tion, is a desirable option. To push the current PC value

onto the stack, a PUSH instruction can be executed.

This will increment the stack pointer and load the cur-

rent PC value onto the stack. TOSU, TOSH and TOSL

can then be modified to place a return address on the

stack.

These Resets are enabled by programming the

STVREN configuration bit. When the STVREN bit is

disabled, a full or underflow condition will set the

appropriate STKFUL or STKUNF bit, but not cause a

device Reset. When the STVREN bit is enabled, a full

or underflow condition will set the appropriate STKFUL

or STKUNF bit and then cause a device Reset. The

STKFUL or STKUNF bits are only cleared by the user

software or a POR Reset.

The ability to pull the TOS value off of the stack and

replace it with the value that was previously pushed

onto the stack, without disturbing normal execution, is

achieved by using the POPinstruction. The POPinstruc-

tion discards the current TOS by decrementing the

stack pointer. The previous value pushed onto the

stack then becomes the TOS value.

 2004 Microchip Technology Inc.

DS30491C-page 55

PIC18F6585/8585/6680/8680

4.3

Fast Register Stack

4.4

PCL, PCLATH and PCLATU

A “fast interrupt return” option is available for interrupts.

A fast register stack is provided for the Status, WREG

and BSR registers and is only one in depth. The stack

is not readable or writable and is loaded with the

current value of the corresponding register when the

processor vectors for an interrupt. The values in the

registers are then loaded back into the working regis-

ters if the FAST RETURNinstruction is used to return

from the interrupt.

The program counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21 bits

wide. The low byte is called the PCL register; this reg-

ister is readable and writable. The high byte is called

the PCH register. This register contains the PC<15:8>

bits and is not directly readable or writable; updates to

the PCH register may be performed through the

PCLATH register. The upper byte is called PCU. This

register contains the PC<20:16> bits and is not directly

readable or writable; updates to the PCU register may

be performed through the PCLATU register.

A low or high priority interrupt source will push values

into the stack registers. If both low and high priority

interrupts are enabled, the stack registers cannot be

used reliably for low priority interrupts. If a high priority

interrupt occurs while servicing a low priority interrupt,

the stack register values stored by the low priority

interrupt will be overwritten.

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the LSB of the PCL is fixed to a value of

‘0’. The PC increments by 2 to address sequential

instructions in the program memory.

If high priority interrupts are not disabled during low

priority interrupts, users must save the key registers in

software during a low priority interrupt.

The CALL, RCALL, GOTO and program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

If no interrupts are used, the fast register stack can be

used to restore the Status, WREG and BSR registers at

the end of a subroutine call. To use the fast register

stack for a subroutine call, a FAST CALL instruction

must be executed.

The contents of PCLATH and PCLATU will be trans-

ferred to the program counter by an operation that

writes PCL. Similarly, the upper two bytes of the pro-

gram counter will be transferred to PCLATH and

PCLATU by an operation that reads PCL. This is useful

for computed offsets to the PC (see Section 4.8.1

“Computed GOTO”).

Example 4-1 shows a source code example that uses

the fast register stack.

EXAMPLE 4-1:

FAST REGISTER STACK

CODE EXAMPLE

;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK

4.5

Clocking Scheme/Instruction

Cycle

CALL SUB1, FAST

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the

program counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clocks and instruction execution flow

are shown in Figure 4-5.

•

SUB1

•

RETURN FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

FIGURE 4-5:

CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Internal

Phase

Clock

Q4

PC

PC+2

PC+4

PC

OSC2/CLKO

(RC Mode)

Execute INST (PC-2)

Fetch INST (PC)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+2)

Fetch INST (PC+4)

DS30491C-page 56

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

4.6

Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute takes another instruction

cycle. However, due to the pipelining each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO),

then two cycles are required to complete the instruction

(Example 4-2).

In the execution cycle, the fetched instruction is latched

into the “Instruction Register” (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

EXAMPLE 4-2:

INSTRUCTION PIPELINE FLOW

TCY0

TCY1

TCY2

TCY3

TCY4

TCY5

1. MOVLW 55h

2. MOVWF PORTB

3. BRA SUB_1

Fetch 1

Execute 1

Fetch 2

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

PORTA, 3 (Forced NOP)

Flush (NOP)

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

All instructions are single cycle except for any program branches. These take two cycles since the fetch instruction

is “flushed” from the pipeline while the new instruction is being fetched and then executed.

The CALLand GOTOinstructions have an absolute pro-

4.7

Instructions in Program Memory

gram memory address embedded into the instruction.

Since instructions are always stored on word bound-

aries, the data contained in the instruction is a word

address. The word address is written to PC<20:1>

which accesses the desired byte address in program

memory. Instruction #2 in Figure 4-6 shows how the

instruction “GOTO 000006h” is encoded in the program

memory. Program branch instructions which encode a

relative address offset operate in the same manner.

The offset value stored in a branch instruction repre-

sents the number of single-word instructions that the

PC will be offset by. Section 25.0 “Instruction Set

Summary” provides further details of the instruction

set.

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte (LSB) of an

instruction word is always stored in a program memory

location with an even address (LSB = 0). Figure 4-6

shows an example of how instruction words are stored

in the program memory. To maintain alignment with

instruction boundaries, the PC increments in steps of 2

and the LSB will always read ‘0’ (see Section 4.4

“PCL, PCLATH and PCLATU”).

FIGURE 4-6:

INSTRUCTIONS IN PROGRAM MEMORY

Word Address

LSB = 1

LSB = 0

↓

Program Memory

^{Byte Locations}→

000000h

000002h

000004h

000006h

000008h

00000Ah

00000Ch

00000Eh

000010h

000012h

000014h

Instruction 1:

Instruction 2:

0Fh

55h

03h

00h

23h

56h

MOVLW

GOTO

055h

000006h

0EFh

0F0h

0C1h

0F4h

Instruction 3:

MOVFF

123h, 456h

 2004 Microchip Technology Inc.

DS30491C-page 57

PIC18F6585/8585/6680/8680

accessed. If the second word of the instruction is exe-

cuted by itself (first word was skipped), it will execute as

a NOP. This action is necessary when the two-word

instruction is preceded by a conditional instruction that

changes the PC. A program example that demon-

strates this concept is shown in Example 4-3. Refer to

Section 25.0 “Instruction Set Summary” for further

details of the instruction set.

4.7.1

TWO-WORD INSTRUCTIONS

The PIC18F6585/8585/6680/8680 devices have four

two-word instructions: MOVFF, CALL, GOTO and

LFSR. The second word of these instructions has the 4

MSBs set to ‘1’s and is a special kind of NOPinstruction.

The lower 12 bits of the second word contain data to be

used by the instruction. If the first word of the instruc-

tion is executed, the data in the second word is

EXAMPLE 4-3:

CASE 1:

TWO-WORD INSTRUCTIONS

Object Code

Source Code

0110 0110 0000 0000 TSTFSZ

1100 0001 0010 0011 MOVFF

1111 0100 0101 0110

REG1

; is RAM location 0?

REG1, REG2 ; No, execute 2-word instruction

; 2nd operand holds address of REG2

0010 0100 0000 0000 ADDWF

REG3

; continue code

CASE 2:

Object Code

Source Code

0110 0110 0000 0000 TSTFSZ

1100 0001 0010 0011 MOVFF

1111 0100 0101 0110

REG1

; is RAM location 0?

REG1, REG2 ; Yes

; 2nd operand becomes NOP

REG3 ; continue code

0010 0100 0000 0000 ADDWF

4.8.2

TABLE READS/TABLE WRITES

4.8

Look-up Tables

A better method of storing data in program memory

allows 2 bytes of data to be stored in each instruction

location.

Look-up tables are implemented two ways. These are:

• Computed GOTO

• Table Reads

Look-up table data may be stored 2 bytes per program

word by using table reads and writes. The Table Pointer

(TBLPTR) specifies the byte address and the Table

Latch (TABLAT) contains the data that is read from, or

written to program memory. Data is transferred to/from

program memory, one byte at a time.

4.8.1

COMPUTED GOTO

A computed GOTOis accomplished by adding an offset

to the program counter (ADDWF PCL).

A look-up table can be formed with an ADDWF PCL

instruction and a group of RETLW 0xnn instructions.

WREG is loaded with an offset into the table before

executing a call to that table. The first instruction of the

called routine is the ADDWF PCL instruction. The next

instruction executed will be one of the RETLW 0xnn

instructions that returns the value 0xnn to the calling

function.

A description of the table read/table write operation is

shown in Section 5.0 “Flash Program Memory”.

The offset value (value in WREG) specifies the number

of bytes that the program counter should advance.

In this method, only one data byte may be stored in

each instruction location and room on the return

address stack is required.

DS30491C-page 58

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

4.9.1

GENERAL PURPOSE

REGISTER FILE

4.9

Data Memory Organization

The data memory is implemented as static RAM. Each

register in the data memory has a 12-bit address,

allowing up to 4096 bytes of data memory. Figure 4-7

shows the data memory organization for the

PIC18F6585/8585/6680/8680 devices.

The register file can be accessed either directly or indi-

rectly. Indirect addressing operates using a File Select

Register and corresponding Indirect File Operand. The

operation of indirect addressing is shown in

Section 4.12 “Indirect Addressing, INDF and FSR

Registers”.

The data memory map is divided into 16 banks that

contain 256 bytes each. The lower 4 bits of the Bank

Select Register (BSR<3:0>) select which bank will be

accessed. The upper 4 bits for the BSR are not

implemented.

Enhanced MCU devices may have banked memory in

the GPR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other Resets.

Data RAM is available for use as general purpose regis-

ters by all instructions. The top section of Bank 15

(0F60h to 0FFFh) contains SFRs. All other banks of data

memory contain GPR registers, starting with Bank 0.

The data memory contains Special Function Registers

(SFR) and General Purpose Registers (GPR). The

SFRs are used for control and status of the controller

and peripheral functions, while GPRs are used for data

storage and scratch pad operations in the user’s appli-

cation. The SFRs start at the last location of Bank 15

(0FFFh) and extend downwards. Any remaining space

beyond the SFRs in the Bank may be implemented as

GPRs. GPRs start at the first location of Bank 0 and

grow upwards. Any read of an unimplemented location

will read as ‘0’s.

4.9.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral modules for controlling

the desired operation of the device. These registers are

implemented as static RAM. A list of these registers is

given in Table 4-2 and Table 4-3.

The entire data memory may be accessed directly or

indirectly. Direct addressing may require the use of the

BSR register. Indirect addressing requires the use of a

File Select Register (FSRn) and a corresponding Indi-

rect File Operand (INDFn). Each FSR holds a 12-bit

address value that can be used to access any location

in the data memory map without banking.

The SFRs can be classified into two sets: those asso-

ciated with the “core” function and those related to the

peripheral functions. Those registers related to the

“core” are described in this section, while those related

to the operation of the peripheral features are

described in the section of that peripheral feature. The

SFRs are typically distributed among the peripherals

whose functions they control.

The instruction set and architecture allow operations

across all banks. This may be accomplished by indirect

addressing or by the use of the MOVFFinstruction. The

MOVFF instruction is a two-word/two-cycle instruction

that moves a value from one register to another.

The unused SFR locations are unimplemented and

read as ‘0’s. The addresses for the SFRs are listed in

Table 4-2.

To ensure that commonly used registers (SFRs and

select GPRs) can be accessed in a single cycle regard-

less of the current BSR values, an Access Bank is

implemented. A segment of Bank 0 and a segment of

Bank 15 comprise the Access RAM. Section 4.10

“Access Bank” provides a detailed description of the

Access RAM.

 2004 Microchip Technology Inc.

DS30491C-page 59

PIC18F6585/8585/6680/8680

FIGURE 4-7:

DATA MEMORY MAP FOR PIC18FXX80/XX85 DEVICES

BSR<3:0>

Data Memory Map

000h

00h

Access RAM

GPRs

= 0000

05Fh

Bank 0

060h

FFh

00h

0FFh

100h

= 0001

= 0010

GPRs

Bank 1

Bank 2

Bank 3

FFh

00h

1FFh

200h

FFh

00h

2FFh

300h

= 0011

= 0100

GPRs

FFh

3FFh

400h

Bank 4

Access Bank

4FFh

500h

00h

Access RAM low

5Fh

60h

Access RAM high

(SFRs)

FFh

Bank 5

to

Bank 12

GPRs

When a = 0,

the BSR is ignored and the

Access Bank is used.

CFFh

D00h

= 1101

= 1110

Bank 13

Bank 14

Bank 15

CAN SFRs

The first 96 bytes are General

Purpose RAM (from Bank 0).

The second 160 bytes are

Special Function Registers

(from Bank 15).

DFFh

E00h

00h

FFh

00h

EFFh

F00h

CAN SFRs

SFRs

= 1111

F5Fh

F60h

FFh

FFFh

When a = 1,

the BSR is used to specify the

RAM location that the instruction

uses.

DS30491C-page 60

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 4-2:

SPECIAL FUNCTION REGISTER MAP

Address

FFFh

FFEh

FFDh

FFCh

FFBh

FFAh

FF9h

FF8h

FF7h

FF6h

FF5h

FF4h

FF3h

FF2h

FF1h

FF0h

FEFh

Name

TOSU

Address

FDFh

Name

INDF2⁽³⁾

POSTINC2⁽³⁾

Address

FBFh

FBEh

FBDh

FBCh

FBBh

FBAh

FB9h

FB8h

FB7h

FB6h

FB5h

FB4h

FB3h

FB2h

FB1h

FB0h

FAFh

FAEh

FADh

FACh

FABh

FAAh

FA9h

FA8h

FA7h

FA6h

FA5h

FA4h

FA3h

FA2h

FA1h

FA0h

Name

Address

F9Fh

Name

IPR1

PIR1

PIE1

CCPR1H

CCPR1L

CCP1CON

CCPR2H

CCPR2L

CCP2CON

TOSH

FDEh

F9Eh

TOSL

FDDh POSTDEC2⁽³⁾

F9Dh

F9Ch MEMCON⁽²⁾

STKPTR

PCLATU

PCLATH

PCL

FDCh

FDBh

FDAh

FD9h

FD8h

FD7h

FD6h

FD5h

FD4h

FD3h

FD2h

FD1h

FD0h

FCFh

FCEh

FCDh

FCCh

FCBh

FCAh

FC9h

FC8h

FC7h

FC6h

FC5h

FC4h

FC3h

FC2h

FC1h

FC0h

PREINC2⁽³⁾

PLUSW2⁽³⁾

FSR2H

(1)

F9Bh

F9Ah

F99h

F98h

F97h

F96h

F95h

F94h

F93h

F92h

F91h

F90h

F8Fh

F8Eh

F8Dh

F8Ch

F8Bh

F8Ah

F89h

F88h

F87h

F86h

F85h

F84h

F83h

F82h

F81h

F80h

—

TRISJ⁽²⁾

TRISH⁽²⁾

TRISG

TRISF

TRISE

TRISD

TRISC

TRISB

TRISA

LATJ⁽²⁾

LATH⁽²⁾

LATG

(1)

FSR2L

—

(1)

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

PRODH

PRODL

INTCON

INTCON2

INTCON3

INDF0⁽³⁾

STATUS

TMR0H

—

(1)

—

TMR0L

ECCP1AS

CVRCON

CMCON

TMR3H

TMR3L

T3CON

PSPCON

SPBRG

RCREG

TXREG

TXSTA

RCSTA

EEADRH

EEADR

EEDATA

EECON2

EECON1

IPR3

T0CON

(1)

—

OSCCON

LVDCON

WDTCON

RCON

TMR1H

FEEh POSTINC0⁽³⁾

FEDh POSTDEC0⁽³⁾

TMR1L

LATF

T1CON

LATE

FECh

FEBh

FEAh

FE9h

FE8h

FE7h

PREINC0⁽³⁾

PLUSW0⁽³⁾

FSR0H

TMR2

LATD

PR2

LATC

T2CON

LATB

FSR0L

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

ADRESH

ADRESL

ADCON0

ADCON1

ADCON2

LATA

WREG

INDF1⁽³⁾

PORTJ⁽²⁾

PORTH⁽²⁾

PORTG

PORTF

PORTE

PORTD

PORTC

PORTB

PORTA

FE6h POSTINC1⁽³⁾

FE5h POSTDEC1⁽³⁾

FE4h

FE3h

FE2h

FE1h

FE0h

PREINC1⁽³⁾

PLUSW1⁽³⁾

FSR1H

PIR3

PIE3

IPR2

FSR1L

PIR2

BSR

PIE2

Note 1: Unimplemented registers are read as ‘0’.

2: This register is not available on PIC18F6X8X devices.

3: This is not a physical register.

 2004 Microchip Technology Inc.

DS30491C-page 61

PIC18F6585/8585/6680/8680

TABLE 4-2:

SPECIAL FUNCTION REGISTER MAP (CONTINUED)

Address

F7Fh

F7Eh

F7Dh

F7Ch

F7Bh

F7Ah

F79h

F78h

F77h

F76h

Name

Address

Name

Address

Name

Address

Name

SPBRGH

F5Fh CANCON_RO0

F5Eh CANSTAT_RO0

F3Fh CANCON_RO2

F3Eh CANSTAT_RO2

F1Fh RXM1EIDL

F1Eh RXM1EIDH

F1Dh RXM1SIDL

F1Ch RXM1SIDH

F1Bh RXM0EIDL

F1Ah RXM0EIDH

F19h RXM0SIDL

F18h RXM0SIDH

F17h RXF5EIDL

F16h RXF5EIDH

F15h RXF5SIDL

F14h RXF5SIDH

F13h RXF4EIDL

F12h RXF4EIDH

F11h RXF4SIDL

F10h RXF4SIDH

F0Fh RXF3EIDL

F0Eh RXF3EIDH

F0Dh RXF3SIDL

F0Ch RXF3SIDH

F0Bh RXF2EIDL

F0Ah RXF2EIDH

F09h RXF2SIDL

F08h RXF2SIDH

F07h RXF1EIDL

F06h RXF1EIDH

F05h RXF1SIDL

F04h RXF1SIDH

F03h RXF0EIDL

F02h RXF0EIDH

F01h RXF0SIDL

F00h RXF0SIDH

BAUDCON

(1)

—

F5Dh

F5Ch

F5Bh

F5Ah

F59h

F58h

F57h

F56h

F55h

F54h

F53h

F52h

F51h

F50h

RXB1D7

RXB1D6

F3Dh

F3Ch

F3Bh

F3Ah

F39h

F38h

F37h

F36h

F35h

F34h

F33h

F32h

F31h

F30h

TXB1D7

TXB1D6

(1)

—

(1)

—

RXB1D5

TXB1D5

(1)

—

RXB1D4

TXB1D4

ECCP1DEL

RXB1D3

TXB1D3

(1)

—

RXB1D2

TXB1D2

ECANCON

TXERRCNT

RXB1D1

TXB1D1

RXB1D0

TXB1D0

F75h RXERRCNT

RXB1DLC

RXB1EIDL

RXB1EIDH

RXB1SIDL

RXB1SIDH

RXB1CON

TXB1DLC

TXB1EIDL

TXB1EIDH

TXB1SIDL

TXB1SIDH

TXB1CON

F74h

F73h

F72h

F71h

F70h

F6Fh

F6Eh

F6Dh

F6Ch

F6Bh

F6Ah

F69h

F68h

F67h

F66h

F65h

F64h

F63h

F62h

F61h

F60h

COMSTAT

CIOCON

BRGCON3

BRGCON2

BRGCON1

CANCON

CANSTAT

RXB0D7

F4Fh CANCON_RO1

F4Eh CANSTAT_RO1

F2Fh CANCON_RO3

F2Eh CANSTAT_RO3

F4Dh

F4Ch

F4Bh

F4Ah

F49h

F48h

F47h

F46h

F45h

F44h

F43h

F42h

F41h

F40h

TXB0D7

TXB0D6

F2Dh

F2Ch

F2Bh

F2Ah

F29h

F28h

F27h

F26h

F25h

F24h

F23h

F22h

F21h

F20h

TXB2D7

TXB2D6

RXB0D6

RXB0D5

TXB0D5

TXB2D5

RXB0D4

TXB0D4

TXB2D4

RXB0D3

TXB0D3

TXB2D3

RXB0D2

TXB0D2

TXB2D2

RXB0D1

TXB0D1

TXB2D1

RXB0D0

TXB0D0

TXB2D0

RXB0DLC

RXB0EIDL

RXB0EIDH

RXB0SIDL

RXB0SIDH

RXB0CON

TXB0DLC

TXB0EIDL

TXB0EIDH

TXB0SIDL

TXB0SIDH

TXB0CON

TXB2DLC

TXB2EIDL

TXB2EIDH

TXB2SIDL

TXB2SIDH

TXB2CON

Note 1: Unimplemented registers are read as ‘0’.

2: This register is not available on PIC18F6X8X devices.

3: This is not a physical register.

DS30491C-page 62

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 4-2:

SPECIAL FUNCTION REGISTER MAP (CONTINUED)

Address

EFFh

EFEh

EFDh

EFCh

EFBh

EFAh

EF9h

EF8h

EF7h

EF6h

EF5h

EF4h

EF3h

EF2h

EF1h

EF0h

EEFh

EEEh

EEDh

EECh

EEBh

EEAh

EE9h

EE8h

EE7h

EE6h

EE5h

EE4h

EE3h

EE2h

EE1h

EE0h

Name

Address

EDFh

EDEh

EDDh

EDCh

EDBh

EDAh

ED9h

ED8h

ED7h

ED6h

ED5h

ED4h

ED3h

ED2h

ED1h

ED0h

ECFh

ECEh

ECDh

ECCh

ECBh

ECAh

EC9h

EC8h

EC7h

EC6h

EC5h

EC4h

EC3h

EC2h

EC1h

EC0h

Name

Address

EBFh

EBEh

EBDh

EBCh

EBBh

EBAh

EB9h

EB8h

EB7h

EB6h

EB5h

EB4h

EB3h

EB2h

EB1h

EB0h

EAFh

EAEh

EADh

EACh

EABh

EAAh

EA9h

EA8h

EA7h

EA6h

EA5h

EA4h

EA3h

EA2h

EA1h

EA0h

Name

Address

E9Fh

E9Eh

E9Dh

E9Ch

E9Bh

E9Ah

E99h

E98h

E97h

E96h

E95h

E94h

E93h

E92h

E91h

E90h

E8Fh

E8Eh

E8Dh

E8Ch

E8Bh

E8Ah

E89h

E88h

E87h

E86h

E85h

E84h

E83h

E82h

E81h

E80h

Name

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

Note 1: Unimplemented registers are read as ‘0’.

2: This register is not available on PIC18F6X8X devices.

3: This is not a physical register.

 2004 Microchip Technology Inc.

DS30491C-page 63

PIC18F6585/8585/6680/8680

TABLE 4-2:

SPECIAL FUNCTION REGISTER MAP (CONTINUED)

Address

Name Address Name Address Name

Address

E1Fh

E1Eh

E1Dh

E1Ch

E1Bh

E1Ah

E19h

E18h

E17h

E16h

E15h

E14h

E13h

E12h

E11h

E10h

E0Fh

E0Eh

E0Dh

E0Ch

E0Bh

E0Ah

E09h

E08h

E07h

E06h

E05h

E04h

E03h

E02h

E01h

E00h

Name

(1)

E7Fh CANCON_RO4

E7Eh CANSTAT_RO4

E5Fh CANCON_RO6

E5Eh CANSTAT_RO6

E3Fh CANCON_RO8

E3Eh CANSTAT_RO8

—

(1)

—

(1)

E7Dh

E7Ch

E7Bh

E7Ah

E79h

E78h

E77h

E76h

E75h

E74h

E73h

E72h

E71h

E70h

B5D7

B5D6

E5Dh

E5Ch

E5Bh

E5Ah

E59h

E58h

E57h

E56h

E55h

E54h

E53h

E52h

E51h

E50h

B3D7

B3D6

E3Dh

E3Ch

E3Bh

E3Ah

E39h

E38h

E37h

E36h

E35h

E34h

E33h

E32h

E31h

E30h

B1D7

B1D6

—

(1)

—

(1)

B5D5

B3D5

B1D5

—

(1)

B5D4

B3D4

B1D4

—

(1)

B5D3

B3D3

B1D3

—

(1)

B5D2

B3D2

B1D2

—

(1)

B5D1

B3D1

B1D1

—

(1)

B5D0

B3D0

B1D0

—

(1)

B5DLC

B5EIDL

B5EIDH

B5SIDL

B5SIDH

B5CON

B3DLC

B3EIDL

B3EIDH

B3SIDL

B3SIDH

B3CON

B1DLC

B1EIDL

B1EIDH

B1SIDL

B1SIDH

B1CON

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

E6Fh CANCON_RO5

E6Eh CANSTAT_RO5

E4Fh CANCON_RO7

E4Eh CANSTAT_RO7

E2Fh CANCON_RO9

E2Eh CANSTAT_RO9

—

(1)

—

(1)

E6Dh

E6Ch

E6Bh

E6Ah

E69h

E68h

E67h

E66h

E65h

E64h

E63h

E62h

E61h

E60h

B4D7

B4D6

E4Dh

E4Ch

E4Bh

E4Ah

E49h

E48h

E47h

E46h

E45h

E44h

E43h

E42h

E41h

E40h

B2D7

B2D6

E2Dh

E2Ch

E2Bh

E2Ah

E29h

E28h

E27h

E26h

E25h

E24h

E23h

E22h

E21h

E20h

B0D7

B0D6

—

(1)

—

(1)

B4D5

B2D5

B0D5

—

(1)

B4D4

B2D4

B0D4

—

(1)

B4D3

B2D3

B0D3

—

(1)

B4D2

B2D2

B0D2

—

(1)

B4D1

B2D1

B0D1

—

(1)

B4D0

B2D0

B0D0

—

(1)

B4DLC

B4EIDL

B4EIDH

B4SIDL

B4SIDH

B4CON

B2DLC

B2EIDL

B2EIDH

B2SIDL

B2SIDH

B2CON

B0DLC

B0EIDL

B0EIDH

B0SIDL

B0SIDH

B0CON

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

Note 1: Unimplemented registers are read as ‘0’.

2: This register is not available on PIC18F6X8X devices.

3: This is not a physical register.

DS30491C-page 64

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 4-2:

SPECIAL FUNCTION REGISTER MAP (CONTINUED)

Address

DFFh

DFEh

DFDh

DFCh

DFBh

DFAh

DF9h

DF8h

DF7h

DF6h

DF5h

DF4h

DF3h

DF2h

DF1h

DF0h

DEFh

DEEh

DEDh

DECh

DEBh

DEAh

DE9h

DE8h

DE7h

DE6h

DE5h

DE4h

DE3h

DE2h

DE1h

DE0h

Name

Address

DDFh

DDEh

DDDh

DDCh

DDBh

DDAh

DD9h

DD8h

DD7h

DD6h

DD5h

DD4h

DD3h

DD2h

DD1h

DD0h

DCFh

DCEh

DCDh

DCCh

DCBh

DCAh

DC9h

DC8h

DC7h

DC6h

DC5h

DC4h

DC3h

DC2h

DC1h

DC0h

Name

Address

DBFh

DBEh

DBDh

DBCh

DBBh

DBAh

DB9h

DB8h

DB7h

DB6h

DB5h

DB4h

DB3h

DB2h

DB1h

DB0h

DAFh

DAEh

DADh

DACh

DABh

DAAh

DA9h

DA8h

DA7h

DA6h

DA5h

DA4h

DA3h

DA2h

DA1h

DA0h

Name

Address

D9Fh

D9Eh

D9Dh

D9Ch

D9Bh

D9Ah

D99h

D98h

D97h

D96h

D95h

D94h

Name

(1)

—

(1)

—

(1)

—

(1)

TXBIE

—

(1)

—

(1)

BIE0

—

(1)

—

(1)

BSEL0

SDFLC

—

(1)

—

(1)

—

(1)

—

RXFCON1

RXFCON0

—

(1)

—

(1)

MSEL3

MSEL2

MSEL1

MSEL0

—

D93h RXF15EIDL

D92h RXF15EIDH

D91h RXF15SIDL

(1)

—

(1)

—

(1)

—

D90h RXF15SIDH

(1)

—

D8Fh

D8Eh

D8Dh

D8Ch

—

(1)

—

(1)

—

(1)

—

(1)

—

D8Bh RXF14EIDL

D8Ah RXF14EIDH

D89h RXF14SIDL

D88h RXF14SIDH

D87h RXF13EIDL

D86h RXF13EIDH

D85h RXF13SIDL

D84h RXF13SIDH

D83h RXF12EIDL

D82h RXF12EIDH

D81h RXF12SIDL

D80h RXF12SIDH

(1)

—

(1)

—

(1)

—

(1)

RXFBCON7

RXFBCON6

RXFBCON5

RXFBCON4

RXFBCON3

RXFBCON2

RXFBCON1

RXFBCON0

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

(1)

—

Note 1: Unimplemented registers are read as ‘0’.

2: This register is not available on PIC18F6X8X devices.

3: This is not a physical register.

 2004 Microchip Technology Inc.

DS30491C-page 65

PIC18F6585/8585/6680/8680

TABLE 4-2:

SPECIAL FUNCTION REGISTER MAP (CONTINUED)

Address

D7Fh

D7Eh

D7Dh

D7Ch

D7Bh

D7Ah

D79h

D78h

D77h

D76h

D75h

D74h

D73h

D72h

D71h

D70h

D6Fh

D6Eh

D6Dh

D6Ch

D6Bh

D6Ah

D69h

D68h

D67h

D66h

D65h

D64h

D63h

D62h

D61h

D60h

Name

Address

Name

Address

Name

Address

Name

(1)

—

(1)

—

(1)

—

(1)

—

RXF11EIDL

RXF11EIDH

RXF11SIDL

RXF11SIDH

RXF10EIDL

RXF10EIDH

RXF10SIDL

RXF10SIDH

RXF9EIDL

RXF9EIDH

RXF9SIDL

RXF9SIDH

(1)

—

(1)

—

(1)

—

(1)

—

RXF8EIDL

RXF8EIDH

RXF8SIDL

RXF8SIDH

RXF7EIDL

RXF7EIDH

RXF7SIDL

RXF7SIDH

RXF6EIDL

RXF6EIDH

RXF6SIDL

RXF6SIDH

Note 1: Unimplemented registers are read as ‘0’.

2: This register is not available on PIC18F6X8X devices.

3: This is not a physical register.

DS30491C-page 66

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 4-3:

REGISTER FILE SUMMARY

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TOSU

—

Top-of-Stack Upper Byte (TOS<20:16>)

---0 0000 36, 54

0000 0000 36, 54

00-0 0000 36, 55

--00 0000 36, 56

0000 0000 36, 56

--00 0000 36, 86

0000 0000 36, 86

xxxx xxxx 36, 107

0000 000x 36, 111

1111 1111 36, 112

1100 0000 36, 113

TOSH

Top-of-Stack High Byte (TOS<15:8>)

Top-of-Stack Low Byte (TOS<7:0>)

TOSL

STKPTR

PCLATU

PCLATH

PCL

STKFUL

—

STKUNF

—

Return Stack Pointer

bit 21

Holding Register for PC<20:16>

Holding Register for PC<15:8>

PC Low Byte (PC<7:0>)

(2)

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

PRODH

PRODL

—

bit 21

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

Program Memory Table Pointer High Byte (TBLPTR<15:8>)

Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

Program Memory Table Latch

Product Register High Byte

Product Register Low Byte

INTCON

INTCON2

INTCON3

INDF0

GIE/GIEH

RBPU

PEIE/GIEL

INTEDG0

INT1IP

TMR0IE

INTEDG1

INT3IE

INT0IE

INTEDG2

INT2IE

RBIE

INTEDG3

INT1IE

TMR0IF

TMR0IP

INT3IF

INT0IF

INT3IP

INT2IF

RBIF

RBIP

INT2IP

INT1IF

Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)

n/a

79

POSTINC0

POSTDEC0

PREINC0

PLUSW0

Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)

Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)

Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)

Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented

(not a physical register) – value of FSR0 offset by value in WREG

FSR0H

—

Indirect Data Memory Address Pointer 0 High Byte

---- 0000 36, 79

xxxx xxxx 36, 79

FSR0L

Indirect Data Memory Address Pointer 0 Low Byte

Working Register

WREG

xxxx xxxx

36

79

INDF1

Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)

Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)

Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)

Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)

n/a

POSTINC1

POSTDEC1

PREINC1

PLUSW1

Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented

(not a physical register) – value of FSR1 offset by value in WREG

FSR1H

—

Indirect Data Memory Address Pointer 1 High Byte

---- 0000 37, 79

xxxx xxxx 37, 79

---- 0000 37, 78

FSR1L

Indirect Data Memory Address Pointer 1 Low Byte

BSR

—

Bank Select Register

INDF2

Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)

Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)

Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)

n/a

79

POSTINC2

POSTDEC2

PREINC2

PLUSW2

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented

(not a physical register) – value of FSR2 offset by value in WREG

FSR2H

FSR2L

—

Indirect Data Memory Address Pointer 2 High Byte

---- 0000 37, 79

xxxx xxxx 37, 79

Indirect Data Memory Address Pointer 2 Low Byte

x= unknown, u= unchanged, – = unimplemented, q= value depends on condition

Legend:

Note 1:

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator

modes.

2:

3:

4:

5:

6:

7:

Bit 21 of the TBLPTRU allows access to the device configuration bits.

These registers are unused on PIC18F6X80 devices; always maintain these clear.

These bits have multiple functions depending on the CAN module mode selection.

Meaning of this register depends on whether this buffer is configured as transmit or receive.

RG5 is available as an input when MCLR is disabled.

This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.

 2004 Microchip Technology Inc.

DS30491C-page 67

PIC18F6585/8585/6680/8680

TABLE 4-3:

REGISTER FILE SUMMARY (CONTINUED)

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

STATUS

TMR0H

TMR0L

—

N

OV

Z

DC

C

---x xxxx 37, 81

0000 0000 37, 157

xxxx xxxx 37, 157

1111 1111 37, 155

---- 0000 27, 37

--00 0101 37, 271

Timer0 Register High Byte

Timer0 Register Low Byte

T0CON

OSCCON

LVDCON

WDTCON

RCON

TMR0ON

T08BIT

—

T0CS

—

T0SE

—

PSA

LOCK

LVDL3

—

T0PS2

PLLEN

LVDL2

—

T0PS1

SCS1

LVDL1

—

T0PS0

SCS

—

IRVST

—

LVDEN

—

LVDL0

—

SWDTE ---- ---0 37, 355

IPEN

—

RI

TO

PD

POR

BOR

0--1 11qq 37, 82,

123

TMR1H

Timer1 Register High Byte

Timer1 Register Low Byte

xxxx xxxx 37, 159

TMR1L

T1CON

RD16

—

T1CKPS1

T1CKPS0 T1OSCEN

T1SYNC

TMR1CS TMR1ON 0-00 0000 37, 159

0000 0000 37, 162

TMR2

Timer2 Register

PR2

Timer2 Period Register

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0

1111 1111 37, 163

T2CON

—

TMR2ON

2

T2CKPS1 T2CKPS0 -000 0000 37, 162

xxxx xxxx 37, 189

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

ADRESH

ADRESL

ADCON0

ADCON1

ADCON2

CCPR1H

CCPR1L

CCP1CON

CCPR2H

CCPR2L

CCP2CON

ECCP1AS

CVRCON

CMCON

TMR3H

SSP Receive Buffer/Transmit Register

2

SSP Address Register in I C Slave mode. SSP Baud Rate Reload Register in I C Master mode.

0000 0000 37, 198

0000 0000 37, 199

SMP

WCOL

GCEN

CKE

D/A

P

S

R/W

SSPM2

PEN

UA

BF

SSPOV

ACKSTAT

SSPEN

ACKDT

CKP

SSPM3

RCEN

SSPM1

RSEN

SSPM0 0000 0000 37, 191

ACKEN

SEN

0000 0000 37, 201

xxxx xxxx 38, 257

--00 0000 38, 249

A/D Result Register High Byte

A/D Result Register Low Byte

—

CHS3

VCFG1

ACQT2

CHS2

VCFG0

ACQT1

CHS1

PCFG3

ACQT0

CHS0

PCFG2

ADCS2

GO/DONE

PCFG1

ADON

PCFG0 --00 0000 38, 257

ADCS0 0-00 0000 38, 251

xxxx xxxx 38, 173

ADFM

ADCS1

Enhanced Capture/Compare/PWM Register 1 High Byte

Enhanced Capture/Compare/PWM Register 1 Low Byte

xxxx xxxx 38, 172

P1M1

P1M0

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1 CCP1M0 0000 0000 38, 172

xxxx xxxx 38, 172

Capture/Compare/PWM Register 2 High Byte

Capture/Compare/PWM Register 2 Low Byte

xxxx xxxx 38, 172

—

DC2B1

DC2B0

CCP2M3

PSSAC1

CVR3

CCP2M2

PSSAC0

CVR2

CCP2M1 CCP2M0 --00 0000 38, 172

ECCPASE

CVREN

C2OUT

ECCPAS2

CVROE

C1OUT

ECCPAS1 ECCPAS0

PSSBD1

CVR1

CM1

PSSBD0 0000 0000 38, 172

CVRR

C2INV

CVRSS

C1INV

CVR0

CM0

0000 0000 38, 265

0000 0000 38, 259

xxxx xxxx 38, 164

CIS

CM2

Timer3 Register High Byte

Timer3 Register Low Byte

TMR3L

T3CON

RD16

IBF

T3CCP2

OBF

T3CKPS1

IBOV

T3CKPS0

T3CCP1

—

T3SYNC

—

TMR3CS TMR3ON 0000 0000 38, 164

0000 ---- 38, 153

PSPCON

PSPMODE

—

Legend:

Note 1:

x= unknown, u= unchanged, – = unimplemented, q= value depends on condition

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator

modes.

2:

3:

4:

5:

6:

7:

Bit 21 of the TBLPTRU allows access to the device configuration bits.

These registers are unused on PIC18F6X80 devices; always maintain these clear.

These bits have multiple functions depending on the CAN module mode selection.

Meaning of this register depends on whether this buffer is configured as transmit or receive.

RG5 is available as an input when MCLR is disabled.

This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.

DS30491C-page 68

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 4-3:

REGISTER FILE SUMMARY (CONTINUED)

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPBRG

RCREG

TXREG

TXSTA

USART Baud Rate Generator

USART Receive Register

USART Transmit Register

0000 0000 38, 239

0000 0000 38, 241

0000 0000 38, 239

0000 0010 38, 230

0000 000x 38, 231

CSRC

SPEN

—

TX9

RX9

—

TXEN

SREN

—

SYNC

CREN

—

SENDB

ADDEN

—

BRGH

FERR

—

TRMT

OERR

TX9D

RX9D

RCSTA

EEADRH

EEADR

EEDATA

EECON2

EECON1

IPR3

EE Adr Register High ---- --00 38, 105

0000 0000 38, 105

Data EEPROM Address Register

Data EEPROM Data Register

0000 0000 38, 105

Data EEPROM Control Register 2 (not a physical register)

---- ---- 38, 105

EEPGD

IRXIP

CFGS

—

FREE

WRERR

TXB1IP

WREN

WR

RD

00-0 x000 38, 102

WAKIP

ERRIP

TXB2IP/

TXBnIP

TXB0IP

RXB1IP/

RXBnIP FIFOWMIP

RXB0IP/ 1111 1111 39, 122

PIR3

PIE3

IRXIF

IRXIE

WAKIF

WAKIE

ERRIF

ERRIE

TXB2IF/

TXBnIF

TXB1IF

TXB1IE

TXB0IF

TXB0IE

RXB1IF/

RXBnIF FIFOWMIF

RXB0IF/ 0000 0000 39, 116

TXB2IE/

TXBnIE

RXB1IE/

RXBnIE FIFOWMIE

RXB0IE/ 0000 0000 39, 119

IPR2

PIR2

PIE2

IPR1

PIR1

PIE1

—

CMIP

CMIF

CMIE

ADIP

ADIF

ADIE

—

EEIP

EEIF

EEIE

TXIP

TXIF

BCLIP

BCLIF

BCLIE

SSPIP

SSPIF

SSPIE

—

LVDIP

LVDIF

LVDIE

CCP1IP

CCP1IF

CCP1IE

—

TMR3IP

TMR3IF

TMR3IE

TMR2IP

TMR2IF

TMR2IE

WM1

CCP2IP -1-1 1111 39, 121

—

CCP2IF -0-0 0000 39, 115

CCP2IE -0-0 0000 39, 118

TMR1IP 0111 1111 39, 120

TMR1IF 0000 0000 39, 114

TMR1IE 0000 0000 39, 117

—

PSPIP

PSPIF

PSPIE

EBDIS

RCIP

RCIF

RCIE

WAIT1

TXIE

WAIT0

(3)

MEMCON

WM0

0-00 --00 39, 94

1111 1111 39, 151

1111 1111 39, 148

---1 1111 39, 145

1111 1111 39, 141

1111 1111 39, 138

1111 1111 39, 135

1111 1111 39, 131

1111 1111 39, 128

-111 1111 39, 125

xxxx xxxx 39, 151

xxxx xxxx 39, 148

---x xxxx 39, 145

xxxx xxxx 39, 141

xxxx xxxx 39, 138

xxxx xxxx 39, 133

xxxx xxxx 39, 131

xxxx xxxx 39, 128

-xxx xxxx 39, 125

(3)

TRISJ

Data Direction Control Register for PORTJ

Data Direction Control Register for PORTH

(3)

TRISH

TRISG

TRISF

TRISE

TRISD

TRISC

TRISB

TRISA

—

Data Direction Control Register for PORTG

Data Direction Control Register for PORTF

Data Direction Control Register for PORTE

Data Direction Control Register for PORTD

Data Direction Control Register for PORTC

Data Direction Control Register for PORTB

(1)

—

TRISA6

Data Direction Control Register for PORTA

(3)

LATJ

Read PORTJ Data Latch, Write PORTJ Data Latch

Read PORTH Data Latch, Write PORTH Data Latch

(3)

LATH

LATG

LATF

LATE

LATD

LATC

LATB

LATA

—

Read PORTG Data Latch, Write PORTG Data Latch

Read PORTF Data Latch, Write PORTF Data Latch

Read PORTE Data Latch, Write PORTE Data Latch

Read PORTD Data Latch, Write PORTD Data Latch

Read PORTC Data Latch, Write PORTC Data Latch

Read PORTB Data Latch, Write PORTB Data Latch

(1)

—

LATA6

Read PORTA Data Latch, Write PORTA Data Latch

Legend:

Note 1:

x= unknown, u= unchanged, – = unimplemented, q= value depends on condition

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator

modes.

2:

3:

4:

5:

6:

7:

Bit 21 of the TBLPTRU allows access to the device configuration bits.

These registers are unused on PIC18F6X80 devices; always maintain these clear.

These bits have multiple functions depending on the CAN module mode selection.

Meaning of this register depends on whether this buffer is configured as transmit or receive.

RG5 is available as an input when MCLR is disabled.

This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.

 2004 Microchip Technology Inc.

DS30491C-page 69

PIC18F6585/8585/6680/8680

TABLE 4-3:

REGISTER FILE SUMMARY (CONTINUED)

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(3)

PORTJ

Read PORTJ pins, Write PORTJ Data Latch

xxxx xxxx 40, 151

xxxx xxxx 40, 148

--0x xxxx 40, 145

xxxx xxxx 40, 141

xxxx xxxx 40, 136

xxxx xxxx 40, 133

xxxx xxxx 40, 131

xxxx xxxx 40, 128

-x0x 0000 40, 125

0000 0000 40, 233

(3)

PORTH

Read PORTH pins, Write PORTH Data Latch

(6)

PORTG

—

RG5

Read PORTG pins, Write PORTG Data Latch

PORTF

Read PORTF pins, Write PORTF Data Latch

Read PORTE pins, Write PORTE Data Latch

Read PORTD pins, Write PORTD Data Latch

Read PORTC pins, Write PORTC Data Latch

PORTE

PORTD

PORTC

PORTB

Read PORTB pins, Write PORTB Data Latch

(1)

PORTA

—

RA6

Read PORTA pins, Write PORTA Data Latch

SPBRGH

BAUDCON

ECCP1DEL

TXERRCNT

RXERRCNT

Enhanced USART Baud Rate Generator High Byte

—

RCIDL

PDC6

TEC6

REC6

—

SCKP

PDC4

TEC4

REC4

TXBP

BRG16

PDC3

TEC3

REC3

RXBP

—

WUE

PDC1

TEC1

REC1

ABDEN -1-0 0-00 40, 233

PRSEN

TEC7

REC7

PDC5

TEC5

REC5

TXBO

PDC2

PDC0

TEC0

REC0

0000 0000 40, 187

0000 0000 40, 288

0000 0000 40, 296

TEC2

REC2

COMSTAT

Mode 0

RXB0OVFL RXB1OVFL

RXBnOVFL

FIFOEMPTY RXBnOVFL

TXWARN

RXWARN EWARN 0000 0000 40, 284

RXWARN EWARN -000 0000 40, 284

RXWARN EWARN 0000 0000 40, 284

COMSTAT

Mode 1

—

TXBO

TXBP

RXBP

TXWARN

—

COMSTAT

Mode 2

CIOCON

TX2SRC

WAKDIS

SEG2PHT

SJW1

TX2EN

WAKFIL

SAM

ENDRHI

—

CANCAP

—

0000 ---- 40, 318

BRGCON3

BRGCON2

BRGCON1

SEG2PH2 SEG2PH1 SEG2PH0 00-- -000 40, 317

SEG1PH2 SEG1PH1 SEG1PH0

PRSEG2

BRP2

PRSEG1 PRSEG0 0000 0000 40, 317

SJW0

BRP5

BRP4

ABAT

BRP3

WIN2

BRP1

WIN0

BRP0

—

0000 0000 40, 317

1000 000- 40, 239

CANCON

Mode 0

REQOP2

REQOP1

REQOP0

WIN1

CANCON

Mode 1

REQOP2

REQOP1

REQOP0

ABAT

—

FP0

—

1000 ---- 40, 239

1000 0000 40, 239

000- 0000 40, 239

CANCON

Mode 2

FP3

FP2

FP1

CANSTAT

Mode 0

OPMODE2 OPMODE1 OPMODE0

ICODE2

EICODE3

ICODE1

EICODE2

ICODE0

CANSTAT

Modes 0, 1

OPMODE2 OPMODE1 OPMODE0 EICODE4

EICODE1 EICODE0 0000 0000 40, 239

EWIN1 EWIN0 0001 0000 40, 323

ECANCON

RXB0D7

RXB0D6

RXB0D5

RXB0D4

RXB0D3

RXB0D2

RXB0D1

RXB0D0

MDSEL1

RXB0D77

RXB0D67

RXB0D57

RXB0D47

RXB0D37

RXB0D27

RXB0D17

RXB0D07

MDSEL0

RXB0D76

RXB0D66

RXB0D56

RXB0D46

RXB0D36

RXB0D26

RXB0D16

RXB0D06

FIFOWM

RXB0D75

RXB0D65

RXB0D55

RXB0D45

RXB0D35

RXB0D25

RXB0D15

RXB0D05

EWIN4

EWIN3

EWIN2

RXB0D74

RXB0D64

RXB0D54

RXB0D44

RXB0D34

RXB0D24

RXB0D14

RXB0D04

RXB0D73

RXB0D63

RXB0D53

RXB0D43

RXB0D33

RXB0D23

RXB0D13

RXB0D03

RXB0D72

RXB0D62

RXB0D52

RXB0D42

RXB0D32

RXB0D22

RXB0D12

RXB0D02

RXB0D71 RXB0D70 xxxx xxxx 40, 230

RXB0D61 RXB0D60 xxxx xxxx 40, 230

RXB0D51 RXB0D50 xxxx xxxx 40, 230

RXB0D41 RXB0D40 xxxx xxxx 40, 230

RXB0D31 RXB0D30 xxxx xxxx 40, 230

RXB0D21 RXB0D20 xxxx xxxx 40, 230

RXB0D11 RXB0D10 xxxx xxxx 40, 230

RXB0D01 RXB0D00 xxxx xxxx 40, 230

Legend:

Note 1:

x= unknown, u= unchanged, – = unimplemented, q= value depends on condition

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator

modes.

2:

3:

4:

5:

6:

7:

Bit 21 of the TBLPTRU allows access to the device configuration bits.

These registers are unused on PIC18F6X80 devices; always maintain these clear.

These bits have multiple functions depending on the CAN module mode selection.

Meaning of this register depends on whether this buffer is configured as transmit or receive.

RG5 is available as an input when MCLR is disabled.

This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.

DS30491C-page 70

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 4-3:

REGISTER FILE SUMMARY (CONTINUED)

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RXB0DLC

RXB0EIDL

RXB0EIDH

RXB0SIDL

RXB0SIDH

—

RXRTR

EID6

RB1

EID5

EID13

SID0

SID8

RB0

EID4

EID12

SRR

DLC3

EID3

EID11

EXID

SID6

DLC2

EID2

DLC1

EID1

EID9

EID17

SID4

DLC0

EID0

EID8

EID16

SID3

-xxx xxxx 40, 230

xxxx xxxx 41, 230

xxxx x-xx 41, 230

xxxx xxxx 41, 230

000- 0000 41, 230

EID7

EID15

SID2

EID14

SID1

EID10

—

SID10

RXFUL

SID9

SID7

SID5

(4)

RXB0CON

Mode 0

RXM1

RXM0

—

RXRTRR0

RXB0DBEN

JTOFF

FILHIT0

(4)

RXB0CON

Mode 1, 2

RXFUL

RXM1

RTRR0

FILHIT4

FILHIT3

FILHIT2

FILHIT1

FILHIT0

0000 0000 41, 230

RXB1D7

RXB1D6

RXB1D5

RXB1D4

RXB1D3

RXB1D2

RXB1D1

RXB1D0

RXB1DLC

RXB1EIDL

RXB1EIDH

RXB1SIDL

RXB1SIDH

RXB1D77

RXB1D67

RXB1D57

RXB1D47

RXB1D37

RXB1D27

RXB1D17

RXB1D07

—

RXB1D76

RXB1D66

RXB1D56

RXB1D46

RXB1D36

RXB1D26

RXB1D16

RXB1D06

RXRTR

EID6

RXB1D75

RXB1D65

RXB1D55

RXB1D45

RXB1D35

RXB1D25

RXB1D15

RXB1D05

RB1

RXB1D74

RXB1D64

RXB1D54

RXB1D44

RXB1D34

RXB1D24

RXB1D14

RXB1D04

RB0

RXB1D73

RXB1D63

RXB1D53

RXB1D43

RXB1D33

RXB1D23

RXB1D13

RXB1D03

DLC3

RXB1D72

RXB1D62

RXB1D52

RXB1D42

RXB1D32

RXB1D22

RXB1D12

RXB1D02

DLC2

RXB1D71 RXB1D70 xxxx xxxx 41, 230

RXB1D61 RXB1D60 xxxx xxxx 41, 230

RXB1D51 RXB1D50 xxxx xxxx 41, 230

RXB1D41 RXB1D40 xxxx xxxx 41, 230

RXB1D31 RXB1D30 xxxx xxxx 41, 230

RXB1D21 RXB1D20 xxxx xxxx 41, 230

RXB1D11 RXB1D10 xxxx xxxx 41, 230

RXB1D01 RXB1D00 xxxx xxxx 41, 230

DLC1

EID1

EID9

EID17

SID4

DLC0

EID0

EID8

EID16

SID3

-xxx xxxx 41, 230

xxxx xxxx 41, 230

xxxx x-xx 41, 230

xxxx xxxx 41, 230

000- 0000 41, 230

EID7

EID5

EID4

EID3

EID2

EID15

EID14

EID13

EID12

EID11

EID10

SID2

SID1

SID0

SRR

EXID

—

SID10

SID9

SID8

SID7

SID6

SID5

(4)

RXB1CON

Mode 0

RXFUL

RXM1

RXM0

—

RXRTRR0

FILHIT2

FILHIT1

FILHIT0

(4)

RXB1CON

Mode 1, 2

RXFUL

RXM1

RTRRO

FILHIT4

FILHIT3

FILHIT2

FILHIT1

FILHIT0

0000 0000 41, 230

TXB0D7

TXB0D6

TXB0D5

TXB0D4

TXB0D3

TXB0D2

TXB0D1

TXB0D0

TXB0DLC

TXB0EIDL

TXB0EIDH

TXB0SIDL

TXB0SIDH

TXB0D77

TXB0D67

TXB0D57

TXB0D47

TXB0D37

TXB0D27

TXB0D17

TXB0D07

—

TXB0D76

TXB0D66

TXB0D56

TXB0D46

TXB0D36

TXB0D26

TXB0D16

TXB0D06

TXRTR

EID6

TXB0D75

TXB0D65

TXB0D55

TXB0D45

TXB0D35

TXB0D25

TXB0D15

TXB0D05

—

TXB0D74

TXB0D64

TXB0D54

TXB0D44

TXB0D34

TXB0D24

TXB0D14

TXB0D04

—

TXB0D73

TXB0D63

TXB0D53

TXB0D43

TXB0D33

TXB0D23

TXB0D13

TXB0D03

DLC3

TXB0D72

TXB0D62

TXB0D52

TXB0D42

TXB0D32

TXB0D22

TXB0D12

TXB0D02

DLC2

TXB0D71 TXB0D70 xxxx xxxx 41, 230

TXB0D61 TXB0D60 xxxx xxxx 41, 230

TXB0D51 TXB0D50 xxxx xxxx 41, 230

TXB0D41 TXB0D40 xxxx xxxx 41, 230

TXB0D31 TXB0D30 xxxx xxxx 41, 230

TXB0D21 TXB0D20 xxxx xxxx 41, 230

TXB0D11 TXB0D10 xxxx xxxx 41, 230

TXB0D01 TXB0D00 xxxx xxxx 41, 230

DLC1

EID1

DLC0

EID0

EID8

EID16

SID3

-x-- xxxx 41, 230

xxxx xxxx 41, 230

xx-x x-xx 41, 230

xxxx xxxx 42, 230

EID7

EID5

EID4

EID3

EID2

EID15

EID14

EID13

EID12

EID11

EID10

EID9

SID2

SID1

SID0

—

EXIDE

—

EID17

SID4

SID10

SID9

SID8

SID7

SID6

SID5

TXB0CON

Mode 0

—

TXABT

TXLARB

TXERR

TXREQ

—

TXPRI1

TXPRI0 -000 0-00 42, 230

TXB0CON

Mode 1, 2

TXBIF

TXABT

TXLARB

TXERR

TXREQ

—

TXPRI1

TXPRI0 0000 0-00 42, 230

Legend:

Note 1:

x= unknown, u= unchanged, – = unimplemented, q= value depends on condition

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator

modes.

2:

3:

4:

5:

6:

7:

Bit 21 of the TBLPTRU allows access to the device configuration bits.

These registers are unused on PIC18F6X80 devices; always maintain these clear.

These bits have multiple functions depending on the CAN module mode selection.

Meaning of this register depends on whether this buffer is configured as transmit or receive.

RG5 is available as an input when MCLR is disabled.

This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.

 2004 Microchip Technology Inc.

DS30491C-page 71

PIC18F6585/8585/6680/8680

TABLE 4-3:

REGISTER FILE SUMMARY (CONTINUED)

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TXB1D7

TXB1D6

TXB1D5

TXB1D4

TXB1D3

TXB1D2

TXB1D1

TXB1D0

TXB1DLC

TXB1EIDL

TXB1EIDH

TXB1SIDL

TXB1SIDH

TXB1D77

TXB1D67

TXB1D57

TXB1D47

TXB1D37

TXB1D27

TXB1D17

TXB1D07

—

TXB1D76

TXB1D66

TXB1D56

TXB1D46

TXB1D36

TXB1D26

TXB1D16

TXB1D06

TXRTR

EID6

TXB1D75

TXB1D65

TXB1D55

TXB1D45

TXB1D35

TXB1D25

TXB1D15

TXB1D05

—

TXB1D74

TXB1D64

TXB1D54

TXB1D44

TXB1D34

TXB1D24

TXB1D14

TXB1D04

—

TXB1D73

TXB1D63

TXB1D53

TXB1D43

TXB1D33

TXB1D23

TXB1D13

TXB1D03

DLC3

TXB1D72

TXB1D62

TXB1D52

TXB1D42

TXB1D32

TXB1D22

TXB1D12

TXB1D02

DLC2

TXB1D71 TXB1D70 xxxx xxxx 42, 230

TXB1D61 TXB1D60 xxxx xxxx 42, 230

TXB1D51 TXB1D50 xxxx xxxx 42, 230

TXB1D41 TXB1D40 xxxx xxxx 42, 230

TXB1D31 TXB1D30 xxxx xxxx 42, 230

TXB1D21 TXB1D20 xxxx xxxx 42, 230

TXB1D11 TXB1D10 xxxx xxxx 42, 230

TXB1D01 TXB1D00 xxxx xxxx 42, 230

DLC1

EID1

DLC0

EID0

EID8

EID16

SID3

-x-- xxxx 42, 230

xxxx xxxx 42, 230

xx-x x-xx 42, 230

xxxx xxxx 42, 230

EID7

EID5

EID4

EID3

EID2

EID15

EID14

EID13

EID12

EID11

EID10

EID9

SID2

SID1

SID0

—

EXIDE

—

EID17

SID4

SID10

SID9

SID8

SID7

SID6

SID5

TXB1CON

Mode 0

—

TXABT

TXLARB

TXERR

TXREQ

—

TXPRI1

TXPRI0 -000 0-00 42, 230

TXB1CON

Mode 1, 2

TXBIF

TXABT

TXLARB

TXERR

TXREQ

—

TXPRI1

TXPRI0 0000 0-00 42, 230

TXB2D7

TXB2D6

TXB2D5

TXB2D4

TXB2D3

TXB2D2

TXB2D1

TXB2D0

TXB2DLC

TXB2EIDL

TXB2EIDH

TXB2SIDL

TXB2SIDH

TXB2D77

TXB2D67

TXB2D57

TXB2D47

TXB2D37

TXB2D27

TXB2D17

TXB2D07

—

TXB2D76

TXB2D66

TXB2D56

TXB2D46

TXB2D36

TXB2D26

TXB2D16

TXB2D06

TXRTR

EID6

TXB2D75

TXB2D65

TXB2D55

TXB2D45

TXB2D35

TXB2D25

TXB2D15

TXB2D05

—

TXB2D74

TXB2D64

TXB2D54

TXB2D44

TXB2D34

TXB2D24

TXB2D14

TXB2D04

—

TXB2D73

TXB2D63

TXB2D53

TXB2D43

TXB2D33

TXB2D23

TXB2D13

TXB2D03

DLC3

TXB2D72

TXB2D62

TXB2D52

TXB2D42

TXB2D32

TXB2D22

TXB2D12

TXB2D02

DLC2

TXB2D71 TXB2D70 xxxx xxxx 42, 230

TXB2D61 TXB2D60 xxxx xxxx 42, 230

TXB2D51 TXB2D50 xxxx xxxx 42, 230

TXB2D41 TXB2D40 xxxx xxxx 42, 230

TXB2D31 TXB2D30 xxxx xxxx 42, 230

TXB2D21 TXB2D20 xxxx xxxx 42, 230

TXB2D11 TXB2D10 xxxx xxxx 42, 230

TXB2D01 TXB2D00 xxxx xxxx 42, 230

DLC1

EID1

DLC0

EID0

EID8

EID16

SID3

-x-- xxxx 42, 230

xxxx xxxx 42, 230

xxx- x-xx 42, 230

xxxx xxxx 42, 230

EID7

EID5

EID4

EID3

EID2

EID15

EID14

EID13

EID12

EID11

EID10

EID9

SID2

SID1

SID0

—

EXIDE

—

EID17

SID4

SID10

SID9

SID8

SID7

SID6

SID5

TXB2CON

Mode 0

—

TXABT

TXLARB

TXERR

TXREQ

—

TXPRI1

TXPRI0 -000 0-00 42, 230

TXB2CON

Mode 1, 2

TXBIF

TXABT

TXLARB

TXERR

TXREQ

—

TXPRI1

TXPRI0 0000 0-00 42, 230

RXM1EIDL

RXM1EIDH

RXM1SIDL

RXM1SIDH

RXM0EIDL

RXM0EIDH

RXM0SIDL

RXM0SIDH

EID7

EID15

SID2

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID4

EID12

—

EID3

EID11

EXIDEN

SID6

EID2

EID10

—

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

xxxx xxxx 42, 230

xxxx xxxx 43, 230

xx-x 0-xx 43, 230

xxxx xxxx 43, 230

xx-x 0-xx 43, 230

xxxx xxxx 43, 230

xxxx xxxx 47, 230

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

EID3

EID15

SID2

EID11

EXIDM

SID6

SID10

EID7

SID7

EID4

SID5

EID2

(7)

RXF15EIDL

EID3

Legend:

Note 1:

x= unknown, u= unchanged, – = unimplemented, q= value depends on condition

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator

modes.

2:

3:

4:

5:

6:

7:

Bit 21 of the TBLPTRU allows access to the device configuration bits.

These registers are unused on PIC18F6X80 devices; always maintain these clear.

These bits have multiple functions depending on the CAN module mode selection.

Meaning of this register depends on whether this buffer is configured as transmit or receive.

RG5 is available as an input when MCLR is disabled.

This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.

DS30491C-page 72

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 4-3:

REGISTER FILE SUMMARY (CONTINUED)

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(7)

RXF15EIDH

EID15

SID2

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID14

SID1

SID9

EID6

EID14

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID13

SID0

SID8

EID5

EID13

EID12

—

EID11

EXIDEN

SID6

EID10

—

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID9

EID17

SID4

EID1

EID9

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

EID8

EID16

SID3

EID0

EID8

xxxx xxxx 47, 230

xx-x x-xx 47, 230

xxxx xxxx 47, 230

xx-x x-xx 47, 230

xxxx xxxx 47, 230

xx-x x-xx 47, 230

xxxx xxxx 47, 230

xx-x x-xx 47, 230

xxxx xxxx 47, 230

xx-x x-xx 47, 230

xxxx xxxx 47, 230

xx-x x-xx 48, 230

xxxx xxxx 48, 230

xxxx xxxx 47, 230

xxxx xxxx 48, 230

xx-x x-xx 48, 230

xxxx xxxx 48, 230

xx-x x-xx 48, 230

xxxx xxxx 48, 230

xx-x x-xx 48, 230

xxxx xxxx 48, 230

xx-x x-xx 48, 230

xxxx xxxx 48, 230

xxxx xxxx 43, 230

(7)

RXF15SIDL

(7)

RXF15SIDH

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

(7)

RXF14EIDL

EID3

(7)

RXF14EIDH

EID15

SID2

EID11

EXIDEN

SID6

(7)

RXF14SIDL

(7)

RXF14SIDH

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

(7)

RXF13EIDL

EID3

(7)

RXF13EIDH

EID15

SID2

EID11

EXIDEN

SID6

(7)

RXF13SIDL

(7)

RXF13SIDH

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

(7)

RXF12EIDL

EID3

(7)

RXF12EIDH

EID15

SID2

EID11

EXIDEN

SID6

(7)

RXF12SIDL

(7)

RXF12SIDH

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

(7)

RXF11EIDL

EID3

(7)

RXF11EIDH

EID15

SID2

EID11

EXIDEN

SID6

(7)

RXF11SIDL

(7)

RXF11SIDH

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

(7)

RXF10EIDL

EID3

(7)

RXF10EIDH

EID15

SID2

EID11

EXIDEN

SID6

(7)

RXF10SIDL

(7)

RXF10SIDH

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

(7)

RXF9EIDL

EID3

(7)

RXF9EIDH

EID15

SID2

EID11

EXIDEN

SID6

(7)

RXF9SIDL

(7)

RXF9SIDH

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

(7)

RXF8EIDL

EID3

(7)

RXF8EIDH

EID15

SID2

EID11

EXIDEN

SID6

(7)

RXF8SIDL

(7)

RXF8SIDH

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

(7)

RXF7EIDL

EID3

(7)

RXF7EIDH

EID15

SID2

EID11

EXIDEN

SID6

(7)

RXF7SIDL

(7)

RXF7SIDH

SID10

EID7

SID7

EID4

EID12

—

SID5

EID2

EID10

—

(7)

RXF6EIDL

EID3

(7)

RXF6EIDH

EID15

SID2

EID11

EXIDEN

SID6

(7)

RXF6SIDL

(7)

RXF6SIDH

SID10

EID7

SID7

EID4

EID12

SID5

EID2

EID10

RXF5EIDL

RXF5EIDH

EID3

EID15

EID11

Legend:

Note 1:

x= unknown, u= unchanged, – = unimplemented, q= value depends on condition

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator

modes.

2:

3:

4:

5:

6:

7:

Bit 21 of the TBLPTRU allows access to the device configuration bits.

These registers are unused on PIC18F6X80 devices; always maintain these clear.

These bits have multiple functions depending on the CAN module mode selection.

Meaning of this register depends on whether this buffer is configured as transmit or receive.

RG5 is available as an input when MCLR is disabled.

This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.

 2004 Microchip Technology Inc.

DS30491C-page 73

PIC18F6585/8585/6680/8680

TABLE 4-3:

REGISTER FILE SUMMARY (CONTINUED)

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RXF5SIDL

RXF5SIDH

RXF4EIDL

RXF4EIDH

RXF4SIDL

RXF4SIDH

RXF3EIDL

RXF3EIDH

RXF3SIDL

RXF3SIDH

RXF2EIDL

RXF2EIDH

RXF2SIDL

RXF2SIDH

RXF1EIDL

RXF1EIDH

RXF1SIDL

RXF1SIDH

RXF0EIDL

RXF0EIDH

RXF0SIDL

RXF0SIDH

SID2

SID10

EID7

SID1

SID9

SID0

SID8

—

EXIDEN

SID6

—

EID17

SID4

EID16

SID3

xx-x x-xx 43, 230

xxxx xxxx 43, 230

xx-x x-xx 43, 230

xxxx xxxx 43, 230

xx-x x-xx 43, 230

xxxx xxxx 43, 230

xx-x x-xx 43, 230

xxxx xxxx 43, 230

xx-x x-xx 43, 230

xxxx xxxx 43, 230

xx-x x-xx 43, 230

xxxx xxxx 43, 230

xxxx xxxx 44, 230

-xxx xxxx 44, 230

xxxx xxxx 44, 230

xxxx x-xx 44, 230

SID7

EID4

EID12

—

SID5

EID2

EID10

—

EID6

EID5

EID3

EID1

EID0

EID15

SID2

EID14

SID1

EID13

SID0

EID11

EXIDEN

SID6

EID9

EID8

EID17

SID4

EID16

SID3

SID10

EID7

SID9

SID8

SID7

EID4

EID12

—

SID5

EID2

EID10

—

EID6

EID5

EID3

EID1

EID0

EID15

SID2

EID14

SID1

EID13

SID0

EID11

EXIDEN

SID6

EID9

EID8

EID17

SID4

EID16

SID3

SID10

EID7

SID9

SID8

SID7

EID4

EID12

—

SID5

EID2

EID10

—

EID6

EID5

EID3

EID1

EID0

EID15

SID2

EID14

SID1

EID13

SID0

EID11

EXIDEN

SID6

EID9

EID8

EID17

SID4

EID16

SID3

SID10

EID7

SID9

SID8

SID7

EID4

EID12

—

SID5

EID2

EID10

—

EID6

EID5

EID3

EID1

EID0

EID15

SID2

EID14

SID1

EID13

SID0

EID11

EXIDEN

SID6

EID9

EID8

EID17

SID4

EID16

SID3

SID10

EID7

SID9

SID8

SID7

EID4

EID12

—

SID5

EID2

EID10

—

EID6

EID5

EID3

EID1

EID0

EID15

SID2

EID14

SID1

EID13

SID0

EID11

EXIDEN

SID6

EID9

EID8

EID17

SID4

EID16

SID3

SID10

B5D77

B5D67

B5D57

B5D47

B5D37

B5D27

B5D17

B5D07

—

SID9

SID8

SID7

B5D74

B5D64

B5D54

B5D44

B5D34

B5D24

B5D14

B5D04

RB0

SID5

B5D72

B5D62

B5D52

B5D42

B5D32

B5D22

B5D12

B5D02

DLC2

EID2

EID10

—

(7)

B5D7

B5D76

B5D66

B5D56

B5D46

B5D36

B5D26

B5D16

B5D06

RXRTR

EID6

B5D75

B5D65

B5D55

B5D45

B5D35

B5D25

B5D15

B5D05

RB1

B5D73

B5D63

B5D53

B5D43

B5D33

B5D23

B5D13

B5D03

DLC3

EID3

B5D71

B5D61

B5D51

B5D41

B5D31

B5D21

B5D11

B5D01

DLC1

EID1

B5D70

B5D60

B5D50

B5D40

B5D30

B5D20

B5D10

B5D00

DLC0

EID0

(7)

B5D6

(7)

B5D5

(7)

B5D4

(7)

B5D3

(7)

B5D2

(7)

B5D1

(7)

B5D0

(7)

B5DLC

(7)

B5EIDL

EID7

EID5

EID4

EID12

SRR

(7)

B5EIDH

EID15

SID2

EID14

SID1

EID13

SID0

EID11

EID9

EID8

(7)

B5SIDL

EXID/

EID17

EID16

(5)

EXIDE

(7)

B5SIDH

SID10

SID9

SID8

SID7

SID6

SID5

SID4

SID3

xxxx xxxx 44, 230

(5, 7)

B5CON

RXFUL/

TXBIF

RXM1/

TXABT

RTRRO/

TXLARB

FILHIT4/

TXERR

FILHIT3/

TXREQ

FILHIT2/

RTREN

FILHIT1/

TXPRI1

FILHIT0/ 0000 0000 44, 230

TXPRI0

(7)

B4D7

B4D77

B4D67

B4D57

B4D47

B4D76

B4D66

B4D56

B4D46

B4D75

B4D65

B4D55

B4D45

B4D74

B4D64

B4D54

B4D44

B4D73

B4D63

B4D53

B4D43

B4D72

B4D62

B4D52

B4D42

B4D71

B4D61

B4D51

B4D41

B4D70

B4D60

B4D50

B4D40

xxxx xxxx 44, 230

(7)

B4D6

(7)

B4D5

(7)

B4D4

Legend:

Note 1:

x= unknown, u= unchanged, – = unimplemented, q= value depends on condition

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator

modes.

2:

3:

4:

5:

6:

7:

Bit 21 of the TBLPTRU allows access to the device configuration bits.

These registers are unused on PIC18F6X80 devices; always maintain these clear.

These bits have multiple functions depending on the CAN module mode selection.

Meaning of this register depends on whether this buffer is configured as transmit or receive.

RG5 is available as an input when MCLR is disabled.

This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.

DS30491C-page 74

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 4-3:

REGISTER FILE SUMMARY (CONTINUED)

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(7)

B4D3

B4D37

B4D27

B4D17

B4D07

—

B4D36

B4D26

B4D16

B4D06

RXRTR

EID6

B4D35

B4D25

B4D15

B4D05

RB1

B4D34

B4D24

B4D14

B4D04

RB0

B4D33

B4D23

B4D13

B4D03

DLC3

EID3

B4D32

B4D22

B4D12

B4D02

DLC2

EID2

B4D31

B4D21

B4D11

B4D01

DLC1

EID1

B4D30

B4D20

B4D10

B4D00

DLC0

EID0

xxxx xxxx 44, 230

-xxx xxxx 44, 230

xxxx xxxx 44, 230

xxxx x-xx 44, 230

(7)

B4D2

(7)

B4D1

(7)

B4D0

(7)

B4DLC

(7)

B4EIDL

EID7

EID5

EID4

(7)

B4EIDH

EID15

SID2

EID14

SID1

EID13

SID0

EID12

SRR

EID11

EID10

—

EID9

EID8

(7)

B4SIDL

EXID/

EID17

EID16

(5)

EXIDE

SID6

(7)

B4SIDH

SID10

SID9

SID8

SID7

SID5

SID4

SID3

xxxx xxxx 44, 230

(5, 7)

B4CON

RXFUL/

TXB3IF

RXM1/

TXABT

RTRRO/

TXLARB

FILHIT4/

TXERR

FILHIT3/

TXREQ

FILHIT2/

RTREN

FILHIT1/

TXPRI1

FILHIT0/ 0000 0000 44, 230

TXPRI0

(7)

B3D7

B3D77

B3D67

B3D57

B3D47

B3D37

B3D27

B3D17

B3D07

—

B3D76

B3D66

B3D56

B3D46

B3D36

B3D26

B3D16

B3D06

RXRTR

EID6

B3D75

B3D65

B3D55

B3D45

B3D35

B3D25

B3D15

B3D05

RB1

B3D74

B3D64

B3D54

B3D44

B3D34

B3D24

B3D14

B3D04

RB0

B3D73

B3D63

B3D53

B3D43

B3D33

B3D23

B3D13

B3D03

DLC3

B3D72

B3D62

B3D52

B3D42

B3D32

B3D22

B3D12

B3D02

DLC2

EID2

B3D71

B3D61

B3D51

B3D41

B3D31

B3D21

B3D11

B3D01

DLC1

B3D70

B3D60

B3D50

B3D40

B3D30

B3D20

B3D10

B3D00

DLC0

xxxx xxxx 44, 230

xxxx xxxx 45, 230

-xxx xxxx 45, 230

xxxx xxxx 45, 230

xxxx x-xx 45, 230

(7)

B3D6

(7)

B3D5

(7)

B3D4

(7)

B3D3

(7)

B3D2

(7)

B3D1

(7)

B3D0

(7)

B3DLC

(7)

B3EIDL

EID7

EID5

EID4

EID3

EID1

EID0

(7)

B3EIDH

EID15

SID2

EID14

SID1

EID13

SID0

EID12

SRR

EID11

EID10

—

EID9

EID8

(7)

B3SIDL

EXID/

EID17

EID16

(5)

EXIDE

(7)

B3SIDH

SID10

SID9

SID8

SID7

SID6

SID5

SID4

SID3

xxxx xxxx 45, 230

(5, 7)

B3CON

RXFUL/

TXBIF

RXM1/

TXABT

RTRRO/

TXLARB

FILHIT4/

TXERR

FILHIT3/

TXREQ

FILHIT2/

RTREN

FILHIT1/

TXPRI1

FILHIT0/ 0000 0000 45, 230

TXPRI0

(7)

B2D7

B2D77

B2D67

B2D57

B2D47

B2D37

B2D27

B2D17

B2D07

—

B2D76

B2D66

B2D56

B2D46

B2D36

B2D26

B2D16

B2D06

RXRTR

EID6

B2D75

B2D65

B2D55

B2D45

B2D35

B2D25

B2D15

B2D05

RB1

B2D74

B2D64

B2D54

B2D44

B2D34

B2D24

B2D14

B2D04

RB0

B2D73

B2D63

B2D53

B2D43

B2D33

B2D23

B2D13

B2D03

DLC3

B2D72

B2D62

B2D52

B2D42

B2D32

B2D22

B2D12

B2D02

DLC2

EID2

B2D71

B2D61

B2D51

B2D41

B2D31

B2D21

B2D11

B2D01

DLC1

B2D70

B2D60

B2D50

B2D40

B2D30

B2D20

B2D10

B2D00

DLC0

xxxx xxxx 45, 230

-xxx xxxx 45, 230

xxxx xxxx 45, 230

xxxx x-xx 45, 230

(7)

B2D6

(7)

B2D5

(7)

B2D4

(7)

B2D3

(7)

B2D2

(7)

B2D1

(7)

B2D0

(7)

B2DLC

(7)

B2EIDL

EID7

EID5

EID4

EID3

EID1

EID0

(7)

B2EIDH

EID15

SID2

EID14

SID1

EID13

SID0

EID12

SRR

EID11

EID10

—

EID9

EID8

(7)

B2SIDL

EXID/

EID17

EID16

(5)

EXIDE

(7)

B2SIDH

SID10

SID9

SID8

SID7

SID6

SID5

SID4

SID3

xxxx xxxx 45, 230

Legend:

Note 1:

x= unknown, u= unchanged, – = unimplemented, q= value depends on condition

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator

modes.

2:

3:

4:

5:

6:

7:

Bit 21 of the TBLPTRU allows access to the device configuration bits.

These registers are unused on PIC18F6X80 devices; always maintain these clear.

These bits have multiple functions depending on the CAN module mode selection.

Meaning of this register depends on whether this buffer is configured as transmit or receive.

RG5 is available as an input when MCLR is disabled.

This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.

 2004 Microchip Technology Inc.

DS30491C-page 75

PIC18F6585/8585/6680/8680

TABLE 4-3:

REGISTER FILE SUMMARY (CONTINUED)

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(5, 7)

B2CON

RXFUL/

TXBIF

RXM1/

TXABT

RTRRO/

TXLARB

FILHIT4/

TXERR

FILHIT3/

TXREQ

FILHIT2/

RTREN

FILHIT1/

TXPRI1

FILHIT0/ 0000 0000 45, 230

TXPRI0

(7)

B1D7

B1D77

B1D67

B1D57

B1D47

B1D37

B1D27

B1D17

B1D07

—

B1D76

B1D66

B1D56

B1D46

B1D36

B1D26

B1D16

B1D06

RXRTR

EID6

B1D75

B1D65

B1D55

B1D45

B1D35

B1D25

B1D15

B1D05

RB1

B1D74

B1D64

B1D54

B1D44

B1D34

B1D24

B1D14

B1D04

RB0

B1D73

B1D63

B1D53

B1D43

B1D33

B1D23

B1D13

B1D03

DLC3

EID3

B1D72

B1D62

B1D52

B1D42

B1D32

B1D22

B1D12

B1D02

DLC2

EID2

B1D71

B1D61

B1D51

B1D41

B1D31

B1D21

B1D11

B1D01

DLC1

EID1

B1D70

B1D60

B1D50

B1D40

B1D30

B1D20

B1D10

B1D00

DLC0

EID0

xxxx xxxx 45, 230

xxxx xxxx 46, 230

-xxx xxxx 46, 230

xxxx xxxx 46, 230

xxxx x-xx 46, 230

xxxx xxxx 46, 230

(7)

B1D6

(7)

B1D5

(7)

B1D4

(7)

B1D3

(7)

B1D2

(7)

B1D1

(7)

B1D0

(7)

B1DLC

(7)

B1EIDL

EID7

EID5

EID4

(7)

B1EIDH

EID15

SID2

EID14

SID1

EID13

SID0

EID12

SRR

EID11

EXID

EID10

—

EID9

EID8

(7)

B1SIDL

EID17

SID4

EID16

SID3

(7)

B1SIDH

SID10

SID9

SID8

SID7

SID6

SID5

(5, 7)

B1CON

RXFUL/

TXBIF

RXM1/

TXABT

RTRRO/

TXLARB

FILHIT4/

TXERR

FILHIT3/

TXREQ

FILHIT2/

RTREN

FILHIT1/

TXPRI1

FILHIT0/ 0000 0000 46, 230

TXPRI0

(7)

B0D7

B0D77

B0D67

B0D57

B0D47

B0D37

B0D27

B0D17

B0D07

—

B0D76

B0D66

B0D56

B0D46

B0D36

B0D26

B0D16

B0D06

RTR

B0D75

B0D65

B0D55

B0D45

B0D35

B0D25

B0D15

B0D05

RB1

B0D74

B0D64

B0D54

B0D44

B0D34

B0D24

B0D14

B0D04

RB0

B0D73

B0D63

B0D53

B0D43

B0D33

B0D23

B0D13

B0D03

DLC3

EID3

B0D72

B0D62

B0D52

B0D42

B0D32

B0D22

B0D12

B0D02

DLC2

EID2

B0D71

B0D61

B0D51

B0D41

B0D31

B0D21

B0D11

B0D01

DLC1

EID1

B0D70

B0D60

B0D50

B0D40

B0D30

B0D20

B0D10

B0D00

DLC0

EID0

xxxx xxxx 46, 230

-xxx xxxx 46, 230

xxxx xxxx 46, 230

xxxx x-xx 46, 230

xxxx xxxx 46, 230

(7)

B0D6

(7)

B0D5

(7)

B0D4

(7)

B0D3

(7)

B0D2

(7)

B0D1

(7)

B0D0

(7)

B0DLC

(7)

B0EIDL

EID7

EID6

EID5

EID4

(7)

B0EIDH

EID15

SID2

EID14

SID1

EID13

SID0

EID12

SRR

EID11

EXID

EID10

—

EID9

EID8

(7)

B0SIDL

EID17

SID4

EID16

SID3

(7)

B0SIDH

SID10

SID9

SID8

SID7

SID6

SID5

(5, 7)

B0CON

RXFUL/

TXBIF

RXM1/

TXABT

RTRRO/

TXLARB

FILHIT4/

TXERR

FILHIT3/

TXREQ

FILHIT2/

RTREN

FILHIT1/

TXPRI1

FILHIT0/ 0000 0000 46, 230

TXPRI0

(7)

TXBIE

—

TXB2IE

B2IE

TXB1IE

B1IE

TXB0IE

B0IE

—

---0 00-- 46, 230

RXB0IE 0000 0000 46, 230

0000 00-- 46, 230

FIL12_0 0000 0000 46, 230

(7)

BIE0

B5IE

B4IE

B3IE

RXB1IE

—

(7)

BSEL0

B5TXEN

FIL15_1

FIL11_1

FIL7_1

FIL3_1

—

B4TXEN

FIL15_0

FIL11_0

FIL7_0

FIL3_0

—

B3TXEN

FIL14_1

FIL10_1

FIL6_1

FIL2_1

—

B2TXEN

FIL14_0

FIL10_0

FIL6_0

B1TXEN

FIL13_1

FIL9_1

B0TXEN

FIL13_0

FIL9_0

—

(7)

MSEL3

FIL12_1

FIL8_1

FIL4_1

FIL0_1

DFLC1

RXF9EN

RXF1EN

(7)

MSEL2

FIL8_0

FIL4_0

FIL0_0

DFLC0

0000 0000 46, 230

0000 0101 46, 230

0101 0000 46, 230

---0 0000 46, 230

(7)

MSEL1

FIL5_1

FIL5_0

(7)

MSEL0

FIL2_0

FIL1_1

FIL1_0

(7)

SDFLC

DFLC4

DFLC3

RXF11EN

RXF3EN

DFLC2

RXF10EN

RXF2EN

(7)

RXFCON1

RXF15EN

RXF7EN

RXF14EN

RXF6EN

RXF13EN

RXF5EN

RXF12EN

RXF4EN

RXF8EN 0000 0000 46, 230

RXF0EN 0011 1111 47, 230

(7)

RXFCON0

Legend:

Note 1:

x= unknown, u= unchanged, – = unimplemented, q= value depends on condition

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator

modes.

2:

3:

4:

5:

6:

7:

Bit 21 of the TBLPTRU allows access to the device configuration bits.

These registers are unused on PIC18F6X80 devices; always maintain these clear.

These bits have multiple functions depending on the CAN module mode selection.

Meaning of this register depends on whether this buffer is configured as transmit or receive.

RG5 is available as an input when MCLR is disabled.

This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.

DS30491C-page 76

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 4-3:

REGISTER FILE SUMMARY (CONTINUED)

Value on

POR, BOR on page:

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(7)

RXFBCON7

F15BP_3

F13BP_3

F11BP_3

F9BP_3

F7BP_3

F5BP_3

F3BP_3

F1BP_3

F15BP_2

F13BP_2

F11BP_2

F9BP_2

F7BP_2

F5BP_2

F3BP_2

F1BP_2

F15BP_1

F13BP_1

F11BP_1

F9BP_1

F7BP_1

F5BP_1

F3BP_1

F1BP_1

F15BP_0

F13BP_0

F11BP_0

F9BP_0

F7BP_0

F5BP_0

F3BP_0

F1BP_0

F14BP_3

F12BP_3

F10BP_3

F8BP_3

F6BP_3

F4BP_3

F2BP_3

F0BP_3

F14BP_2

F12BP_2

F10BP_2

F8BP_2

F6BP_2

F4BP_2

F2BP_2

F0BP_2

F14BP_1 F14BP_01 0000 0000 47, 230

F12BP_1 F12BP_01 0000 0000 47, 230

F10BP_1 F10BP_01 0000 0000 47, 230

(7)

RXFBCON6

(7)

RXFBCON5

(7)

RXFBCON4

F8BP_1

F6BP_1

F4BP_1

F2BP_1

F0BP_1

F8BP_01 0000 0000 47, 230

F6BP_01 0000 0000 47, 230

F4BP_01 0000 0000 47, 230

F2BP_01 0000 0000 47, 230

F0BP_01 0000 0000 47, 230

(7)

RXFBCON3

(7)

RXFBCON2

(7)

RXFBCON1

(7)

RXFBCON0

Legend:

Note 1:

x= unknown, u= unchanged, – = unimplemented, q= value depends on condition

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator

modes.

2:

3:

4:

5:

6:

7:

Bit 21 of the TBLPTRU allows access to the device configuration bits.

These registers are unused on PIC18F6X80 devices; always maintain these clear.

These bits have multiple functions depending on the CAN module mode selection.

Meaning of this register depends on whether this buffer is configured as transmit or receive.

RG5 is available as an input when MCLR is disabled.

This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.

 2004 Microchip Technology Inc.

DS30491C-page 77

PIC18F6585/8585/6680/8680

4.10

Access Bank

4.11 Bank Select Register (BSR)

The Access Bank is an architectural enhancement

which is very useful for C compiler code optimization.

The techniques used by the C compiler may also be

useful for programs written in assembly.

The need for a large general purpose memory space

dictates a RAM banking scheme. The data memory is

partitioned into sixteen banks. When using direct

addressing, the BSR should be configured for the

desired bank.

This data memory region can be used for:

BSR<3:0> holds the upper 4 bits of the 12-bit RAM

address. The BSR<7:4> bits will always read ‘0’s and

writes will have no effect.

• Intermediate computational values

• Local variables of subroutines

• Faster context saving/switching of variables

• Common variables

A

MOVLB instruction has been provided in the

instruction set to assist in selecting banks.

• Faster evaluation/control of SFRs (no banking)

If the currently selected bank is not implemented, any

read will return all ‘0’s and all writes are ignored. The

Status register bits will be set/cleared as appropriate for

the instruction performed.

The Access Bank is comprised of the upper 160 bytes

in Bank 15 (SFRs) and the lower 96 bytes in Bank 0.

These two sections will be referred to as Access RAM

High and Access RAM Low, respectively. Figure 4-7

indicates the Access RAM areas.

Each Bank extends up to 0FFh (256 bytes). All data

memory is implemented as static RAM.

A bit in the instruction word specifies if the operation is

to occur in the bank specified by the BSR register or in

the Access Bank. This bit is denoted by the ‘a’ bit (for

access bit).

A MOVFFinstruction ignores the BSR since the 12-bit

addresses are embedded into the instruction word.

Section 4.12 “Indirect Addressing, INDF and FSR

Registers” provides a description of indirect address-

ing which allows linear addressing of the entire RAM

space.

When forced in the Access Bank (a = 0), the last

address in Access RAM Low is followed by the first

address in Access RAM High. Access RAM High maps

the Special Function Registers so that these registers

can be accessed without any software overhead. This is

useful for testing status flags and modifying control bits.

FIGURE 4-8:

DIRECT ADDRESSING

Direct Addressing

(3)

From Opcode

BSR<3:0>

7

0

(2)

(3)

Bank Select

Location Select

00h

01h

100h

0Eh

E00h

0Fh

F00h

000h

Data

Memory⁽¹⁾

0FFh

Bank 0

1FFh

Bank 1

EFFh

FFFh

Bank 14

Bank 15

Note 1: For register file map detail, see Table 4-2.

2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the

registers of the Access Bank.

3: The MOVFFinstruction embeds the entire 12-bit address in the instruction.

DS30491C-page 78

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

the data from the address pointed to by

FSR1H:FSR1L. INDFn can be used in code anywhere

an operand can be used.

4.12 Indirect Addressing, INDF and

FSR Registers

Indirect addressing is a mode of addressing data mem-

ory where the data memory address in the instruction

is not fixed. An FSR register is used as a pointer to the

data memory location that is to be read or written. Since

this pointer is in RAM, the contents can be modified by

the program. This can be useful for data tables in the

data memory and for software stacks. Figure 4-9

shows the operation of indirect addressing. This shows

the moving of the value to the data memory address

specified by the value of the FSR register.

If INDF0, INDF1, or INDF2 are read indirectly via an

FSR, all ‘0’s are read (zero bit is set). Similarly, if

INDF0, INDF1, or INDF2 are written to indirectly, the

operation will be equivalent to a NOPinstruction and the

Status bits are not affected.

4.12.1

INDIRECT ADDRESSING

OPERATION

Each FSR register has an INDF register associated

with it plus four additional register addresses.

Performing an operation on one of these five registers

determines how the FSR will be modified during

indirect addressing.

Indirect addressing is possible by using one of the

INDF registers. Any instruction using the INDF register

actually accesses the register pointed to by the File

Select Register, FSR. Reading the INDF register itself,

indirectly (FSR = 0), will read 00h. Writing to the INDF

register indirectly, results in a no operation. The FSR

register contains a 12-bit address which is shown in

Figure 4-10.

When data access is done to one of the five INDFn

locations, the address selected will configure the FSRn

register to:

• Do nothing to FSRn after an indirect access (no

change) – INDFn.

The INDFn register is not a physical register. Address-

ing INDFn actually addresses the register whose

address is contained in the FSRn register (FSRn is a

pointer). This is indirect addressing.

• Auto-decrement FSRn after an indirect access

(post-decrement) – POSTDECn.

• Auto-increment FSRn after an indirect access

(post-increment) – POSTINCn.

Example 4-4 shows a simple use of indirect addressing

to clear the RAM in Bank 1 (locations 100h-1FFh) in a

minimum number of instructions.

• Auto-increment FSRn before an indirect access

(pre-increment) – PREINCn.

• Use the value in the WREG register as an offset

to FSRn. Do not modify the value of the WREG or

the FSRn register after an indirect access (no

change) – PLUSWn.

EXAMPLE 4-4:

HOW TO CLEAR RAM

(BANK 1) USING

INDIRECT ADDRESSING

LFSR

CLRF

FSR0, 100h

POSTINC0

;

When using the auto-increment or auto-decrement fea-

tures, the effect on the FSR is not reflected in the Status

register. For example, if the indirect address causes the

FSR to equal ‘0’, the Z bit will not be set.

; register and

; inc pointer

; All done with

; Bank1?

BTFSS FSR0H, 1

Incrementing or decrementing an FSR affects all

12 bits. That is, when FSRnL overflows from an

increment, FSRnH will be incremented automatically.

BRA

CONTINUE

; YES, continue

Adding these features allows the FSRn to be used as a

stack pointer in addition to its uses for table operations

in data memory.

There are three Indirect Addressing registers. To

address the entire data memory space (4096 bytes),

these registers are 12-bits wide. To store the 12 bits of

addressing information, two 8-bit registers are

required. These Indirect Addressing registers are:

Each FSR has an address associated with it that

performs an indexed indirect access. When a data

access to this INDFn location (PLUSWn) occurs, the

FSRn is configured to add the signed value in the

WREG register and the value in FSR to form the

address before an indirect access. The FSR value is

not changed.

1. FSR0: composed of FSR0H:FSR0L

2. FSR1: composed of FSR1H:FSR1L

3. FSR2: composed of FSR2H:FSR2L

In addition, there are registers INDF0, INDF1 and

INDF2 which are not physically implemented. Reading

or writing to these registers activates indirect address-

ing with the value in the corresponding FSR register

being the address of the data. If an instruction writes a

value to INDF0, the value will be written to the address

pointed to by FSR0H:FSR0L. A read from INDF1 reads

If an FSR register contains a value that points to one of

the INDFn, an indirect read will read 00h (zero bit is

set), while an indirect write will be equivalent to a NOP

(Status bits are not affected).

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If an indirect addressing operation is done where the

target address is an FSRnH or FSRnL register, the

write operation will dominate over the pre- or

post-increment/decrement functions.

FIGURE 4-9:

INDIRECT ADDRESSING OPERATION

0h

RAM

Instruction

Executed

Opcode

Address

12

0FFFh

File Address = Access of an Indirect Addressing Register

BSR<3:0>

12

Instruction

Fetched

4

8

Opcode

FSR

File

FIGURE 4-10:

INDIRECT ADDRESSING

Indirect Addressing

11

FSR Register

0

Location Select

0000h

Data

Memory⁽¹⁾

0FFFh

Note 1: For register file map detail, see Table 4-2.

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For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the Status register

4.13 Status Register

The Status register, shown in Register 4-3, contains the

arithmetic status of the ALU. The Status register can be

the destination for any instruction as with any other reg-

ister. If the Status register is the destination for an

instruction that affects the Z, DC, C, OV or N bits, then

the write to these five bits is disabled. These bits are set

or cleared according to the device logic. Therefore, the

result of an instruction with the Status register as

destination may be different than intended.

as 000u u1uu(where u= unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF, MOVFF and MOVWF instructions are used to

alter the Status register because these instructions do

not affect the Z, C, DC, OV or N bits from the Status

register. For other instructions not affecting any status

bits, see Table 25-2.

Note:

The C and DC bits operate as a borrow and

digit borrow bit respectively, in subtraction.

REGISTER 4-3:

STATUS REGISTER

U-0

—

U-0

—

U-0

—

R/W-x

OV

R/W-x

Z

R/W-x

DC

R/W-x

C

N

bit 7

bit 0

bit 7-5

bit 4

Unimplemented: Read as ‘0’

N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was

negative (ALU MSB = 1).

1= Result was negative

0= Result was positive

bit 3

OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the

7-bit magnitude which causes the sign bit (bit 7) to change state.

1= Overflow occurred for signed arithmetic (in this arithmetic operation)

0= No overflow occurred

bit 2

bit 1

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit

For ADDWF, ADDLW, SUBLW, and SUBWFinstructions:

1= A carry-out from the 4th low order bit of the result occurred

0= No carry-out from the 4th low order bit of the result

Note:

For borrow, the polarity is reversed. A subtraction is executed by adding the

2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit

is loaded with either the bit 4 or bit 3 of the source register.

bit 0

C: Carry/borrow bit

For ADDWF, ADDLW, SUBLW, and SUBWFinstructions:

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note:

For borrow, the polarity is reversed. A subtraction is executed by adding the

2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit

is loaded with either the high or low-order bit of the source register.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

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4.14 RCON Register

Note 1: It is recommended that the POR bit be set

after Power-on Reset has been

a

The Reset Control (RCON) register contains flag bits

that allow differentiation between the sources of a

device Reset. These flags include the TO, PD, POR,

BOR and RI bits. This register is readable and writable.

detected so that subsequent Power-on

Resets may be detected.

2: Brown-out Reset is said to have occurred

when BOR is ‘0’ and POR is ‘1’ (assum-

ing that POR was set to ‘1’ by software

immediately after POR).

REGISTER 4-4:

RCON REGISTER

R/W-0

IPEN

U-0

—

U-0

—

R/W-1

RI

R/W-1

TO

R/W-1

PD

R/W-0

POR

R/W-0

BOR

bit 7

bit 0

bit 7

IPEN: Interrupt Priority Enable bit

1= Enable priority levels on interrupts

0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6-5 Unimplemented: Read as ‘0’

bit 4

RI: RESETInstruction Flag bit

1= The RESETinstruction was not executed

0= The RESETinstruction was executed causing a device Reset

(must be set in software after a Brown-out Reset occurs)

bit 3

bit 2

bit 1

bit 0

TO: Watchdog Time-out Flag bit

1= After power-up, CLRWDTinstruction, or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down Detection Flag bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

POR: Power-on Reset Status bit

1= A Power-on Reset has not occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

BOR: Brown-out Reset Status bit

1= A Brown-out Reset has not occurred

0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

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5.1

Table Reads and Table Writes

5.0

FLASH PROGRAM MEMORY

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data RAM:

The Flash program memory is readable, writable and

erasable during normal operation over the entire VDD

range.

• Table Read (TBLRD)

• Table Write (TBLWT)

A read from program memory is executed on one byte

at a time. A write to program memory is executed on

blocks of 8 bytes at a time. Program memory is erased

in blocks of 64 bytes at a time. A bulk erase operation

cannot be issued from user code.

The program memory space is 16 bits wide, while the

data RAM space is 8-bits wide. Table reads and table

writes move data between these two memory spaces

through an 8-bit register (TABLAT).

Writing or erasing program memory will cease

instruction fetches until the operation is complete. The

program memory cannot be accessed during the write

or erase, therefore, code cannot execute. An internal

programming timer terminates program memory writes

and erases.

Table read operations retrieve data from program

memory and places it into the data RAM space.

Figure 5-1 shows the operation of a table read with

program memory and data RAM.

Table write operations store data from the data memory

space into holding registers in program memory. The

procedure to write the contents of the holding

registers into program memory is detailed in

Section 5.5 “Writing to Flash Program Memory”.

Figure 5-2 shows the operation of a table write with

program memory and data RAM.

A value written to program memory does not need to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP.

Table operations work with byte entities. A table block

containing data, rather than program instructions, is not

required to be word aligned. Therefore, a table block can

start and end at any byte address. If a table write is being

used to write executable code into program memory,

program instructions will need to be word aligned.

FIGURE 5-1:

TABLE READ OPERATION

Instruction: TBLRD*

Program Memory

(1)

Table Pointer

Table Latch (8-bit)

TABLAT

TBLPTRU TBLPTRH TBLPTRL

Program Memory

(TBLPTR)

Note 1: Table Pointer points to a byte in program memory.

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FIGURE 5-2:

TABLE WRITE OPERATION

Instruction: TBLWT*

Program Memory

Holding Registers

(1)

Table Pointer

Table Latch (8-bit)

TABLAT

TBLPTRU TBLPTRH TBLPTRL

Program Memory

(TBLPTR)

Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by

TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in

Section 5.5 “Writing to Flash Program Memory”.

The FREE bit, when set, will allow a program memory

erase operation. When the FREE bit is set, the erase

operation is initiated on the next WR command. When

FREE is clear, only writes are enabled.

5.2

Control Registers

Several control registers are used in conjunction with

the TBLRDand TBLWTinstructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset or a WDT Time-out Reset during normal opera-

tion. In these situations, the user can check the

WRERR bit and rewrite the location. It is necessary to

reload the data and address registers (EEDATA and

EEADR) due to Reset values of zero.

5.2.1

EECON1 AND EECON2 REGISTERS

EECON1 is the control register for memory accesses.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the memory write and erase sequences.

The WR control bit initiates write operations. The bit

cannot be cleared, only set in software; it is cleared in

hardware at the completion of the write operation. The

inability to clear the WR bit in software prevents the

Control bit EEPGD determines if the access will be a

program or data EEPROM memory access. When

clear, any subsequent operations will operate on the

data EEPROM memory. When set, any subsequent

operations will operate on the program memory.

accidental or premature termination of

operation.

a write

Note:

Interrupt flag bit, EEIF in the PIR2 register,

is set when the write is complete. It must

be cleared in software.

Control bit CFGS determines if the access will be to the

configuration/calibration registers or to program

memory/data EEPROM memory. When set, subse-

quent operations will operate on configuration registers

regardless of EEPGD (see Section 24.0 “Special

Features of the CPU”). When clear, memory selection

access is determined by EEPGD.

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REGISTER 5-1:

EECON1 REGISTER (ADDRESS FA6h)

R/W-x

CFGS

U-0

—

R/W-0

FREE

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

EEPGD

WRERR

bit 7

bit 0

bit 7

bit 6

EEPGD: Flash Program or Data EEPROM Memory Select bit

1= Access Flash program memory

0= Access data EEPROM memory

CFGS: Flash Program/Data EEPROM or Configuration Select bit

1= Access configuration registers

0= Access Flash program or data EEPROM memory

bit 5

bit 4

Unimplemented: Read as ‘0’

FREE: Flash Row Erase Enable bit

1= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0= Perform write only

bit 3

WRERR: Flash Program/Data EEPROM Error Flag bit

1= A write operation is prematurely terminated

(any Reset during self-timed programming in normal operation)

0= The write operation completed

Note:

When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows

tracing of the error condition.

bit 2

bit 1

WREN: Flash Program/Data EEPROM Write Enable bit

1= Allows write cycles

0= Inhibits write to the EEPROM

WR: Write Control bit

1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write

cycle. (The operation is self-timed and the bit is cleared by hardware once write is

complete. The WR bit can only be set (not cleared) in software.)

0= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bit

can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

0= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

S = Settable bit

- n = Value after erase

x = Bit is unknown

‘0’ = Bit is cleared

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5.2.2

TABLAT – TABLE LATCH REGISTER

5.2.4

TABLE POINTER BOUNDARIES

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR space. The Table Latch is used to hold 8-

bit data during data transfers between program

memory and data RAM.

TBLPTR is used in reads, writes and erases of the

Flash program memory.

When a TBLRD is executed, all 22 bits of the table

pointer determine which byte is read from program

memory into TABLAT.

5.2.3

TBLPTR – TABLE POINTER

REGISTER

When a TBLWTis executed, the three LSbs of the Table

Pointer (TBLPTR<2:0>) determine which of the eight

program memory holding registers is written to. When

the timed write to program memory (long write) begins,

the 19 MSbs of the Table Pointer (TBLPTR<21:3>) will

determine which program memory block of 8 bytes is

written to. For more detail, see Section 5.5 “Writing to

Flash Program Memory”.

The Table Pointer (TBLPTR) addresses a byte within

the program memory. The TBLPTR is comprised of

three SFR registers: Table Pointer Upper Byte, Table

Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-

ters join to form a 22-bit wide pointer. The low-order

21 bits allow the device to address up to 2 Mbytes of

program memory space. The 22nd bit allows access to

the device ID, the user ID and the configuration bits.

When an erase of program memory is executed, the

16 MSbs of the Table Pointer (TBLPTR<21:6>) point to

the 64-byte block that will be erased. The Least

Significant bits (TBLPTR<5:0>) are ignored.

The Table Pointer, TBLPTR, is used by the TBLRDand

TBLWTinstructions. These instructions can update the

TBLPTR in one of four ways based on the table opera-

tion. These operations are shown in Table 5-1. These

operations on the TBLPTR only affect the low-order

21 bits.

Figure 5-3 describes the relevant boundaries of

TBLPTR based on Flash program memory operations.

TABLE 5-1:

Example

TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

Operation on Table Pointer

TBLRD*

TBLWT*

TBLPTR is not modified

TBLRD*+

TBLWT*+

TBLPTR is incremented after the read/write

TBLPTR is decremented after the read/write

TBLPTR is incremented before the read/write

TBLRD*-

TBLWT*-

TBLRD+*

TBLWT+*

FIGURE 5-3:

TABLE POINTER BOUNDARIES BASED ON OPERATION

21

16 15

TBLPTRH

8

7

TBLPTRL

0

TBLPTRU

ERASE – TBLPTR<20:6>

WRITE – TBLPTR<21:3>

READ – TBLPTR<21:0>

DS30491C-page 86

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TBLPTR points to a byte address in program space.

Executing TBLRD places the byte pointed to into

TABLAT. In addition, TBLPTR can be modified

5.3

Reading the Flash Program

Memory

The TBLRD instruction is used to retrieve data from

program memory and places it into data RAM. Table

reads from program memory are performed one byte at

a time.

automatically for the next table read operation.

The internal program memory is typically organized by

words. The Least Significant bit of the address selects

between the high and low bytes of the word. Figure 5-4

shows the interface between the internal program

memory and the TABLAT.

FIGURE 5-4:

READS FROM FLASH PROGRAM MEMORY

Program Memory

(Even Byte Address)

(Odd Byte Address)

TBLPTR = xxxxx1

TBLPTR = xxxxx0

Instruction Register

(IR)

TABLAT

Read Register

FETCH

TBLRD

EXAMPLE 5-1:

READING A FLASH PROGRAM MEMORY WORD

MOVLW

upper(CODE_ADDR)

TBLPTRU

high(CODE_ADDR)

TBLPTRH

low(CODE_ADDR_LOW)

TBLPTRL

; Load TBLPTR with the base

; address of the word

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

READ_WORD

TBLRD*+

MOVF

MOVWF

TBLRD*+

MOVF

; read into TABLAT and increment

; get data

TABLAT, W

LSB

; read into TABLAT and increment

; get data

TABLAT, W

MSB

MOVWF

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5.4.1

FLASH PROGRAM MEMORY

ERASE SEQUENCE

5.4

Erasing Flash Program Memory

The minimum erase block is 32 words or 64 bytes. Only

through the use of an external programmer or through

ICSP control can larger blocks of program memory be

bulk erased. Word erase in the Flash array is not

supported.

The sequence of events for erasing a block of internal

program memory location is:

1. Load table pointer with address of row being

erased.

When initiating an erase sequence from the micro-

controller itself, a block of 64 bytes of program memory

is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased.

TBLPTR<5:0> are ignored.

2. Set the EECON1 register for the erase

operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN bit to enable writes;

• set FREE bit to enable the erase.

3. Disable interrupts.

The EECON1 register commands the erase operation.

The EEPGD bit must be set to point to the Flash

program memory. The WREN bit must be set to enable

write operations. The FREE bit is set to select an erase

operation.

4. Write 55h to EECON2.

5. Write 0AAh to EECON2.

6. Set the WR bit. This will begin the row erase

cycle.

For protection, the write initiate sequence for EECON2

must be used.

7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).

A long write is necessary for erasing the internal Flash.

Instruction execution is halted while in a long write

cycle. The long write will be terminated by the internal

programming timer.

8. Execute a NOP.

9. Re-enable interrupts.

EXAMPLE 5-2:

ERASING A FLASH PROGRAM MEMORY ROW

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

upper(CODE_ADDR)

TBLPTRU

high(CODE_ADDR)

TBLPTRH

low(CODE_ADDR)

TBLPTRL

; load TBLPTR with the base

; address of the memory block

ERASE_ROW

BSF

BCF

BSF

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

EECON1, FREE

INTCON, GIE

55h

EECON2

0AAh

EECON2

EECON1, WR

; point to Flash program memory

; access Flash program memory

; enable write to memory

; enable Row Erase operation

; disable interrupts

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

; write 55h

Required

Sequence

; write 0AAh

; start erase (CPU stall)

NOP

BSF

INTCON, GIE

; re-enable interrupts

DS30491C-page 88

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the holding registers are written. At the end of updating

eight registers, the EECON1 register must be written

to, to start the programming operation with a long write.

5.5

Writing to Flash Program Memory

The minimum programming block is 4 words or 8 bytes.

Word or byte programming is not supported.

The long write is necessary for programming the inter-

nal Flash. Instruction execution is halted while in a long

write cycle. The long write will be terminated by the

internal programming timer.

Table writes are used internally to load the holding

registers needed to program the Flash memory. There

are eight holding registers used by the table writes for

programming.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump, rated to operate over the voltage range

of the device for byte or word operations.

Since the Table Latch (TABLAT) is only a single byte,

the TBLWT instruction has to be executed 8 times for

each programming operation. All of the table write

operations will essentially be short writes because only

FIGURE 5-5:

TABLE WRITES TO FLASH PROGRAM MEMORY

TABLAT

Write Register

8

TBLPTR = xxxxx0

TBLPTR = xxxxx2

TBLPTR = xxxxx7

TBLPTR = xxxxx1

Holding Register

Program Memory

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8. Disable interrupts.

5.5.1

FLASH PROGRAM MEMORY WRITE

SEQUENCE

9. Write 55h to EECON2.

10. Write 0AAh to EECON2.

The sequence of events for programming an internal

program memory location should be:

11. Set the WR bit. This will begin the write cycle.

12. The CPU will stall for duration of the write (about

5 ms using internal timer).

1. Read 64 bytes into RAM.

2. Update data values in RAM as necessary.

3. Load table pointer with address being erased.

4. Do the row erase procedure.

13. Execute a NOP.

14. Re-enable interrupts.

15. Repeat steps 6-14 seven times to write 64 bytes.

16. Verify the memory (table read).

5. Load table pointer with address of first byte

being written.

6. Write the first 8 bytes into the holding registers

with auto-increment.

This procedure will require about 40 ms to update one

row of 64 bytes of memory. An example of the required

code is given in Example 5-3.

7. Set the EECON1 register for the write operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN to enable byte writes.

Note:

Before setting the WR bit, the Table

Pointer address needs to be within the

intended address range of the eight bytes

in the holding register.

EXAMPLE 5-3:

WRITING TO FLASH PROGRAM MEMORY

MOVLW

D’64

; number of bytes in erase block

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

COUNTER

high(BUFFER_ADDR)

FSR0H

low(BUFFER_ADDR)

FSR0L

upper(CODE_ADDR)

TBLPTRU

high(CODE_ADDR)

TBLPTRH

low(CODE_ADDR)

TBLPTRL

; point to buffer

; Load TBLPTR with the base

; address of the memory block

READ_BLOCK

TBLRD*+

MOVF

MOVWF

DECFSZ

BRA

; read into TABLAT, and inc

; get data

; store data

; done?

TABLAT, W

POSTINC0

COUNTER

READ_BLOCK

; repeat

MODIFY_WORD

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

high(DATA_ADDR)

FSR0H

low(DATA_ADDR)

FSR0L

low(NEW_DATA)

POSTINC0

high(NEW_DATA)

INDF0

; point to buffer

; update buffer word

DS30491C-page 90

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

EXAMPLE 5-3:

WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

ERASE_BLOCK

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

BCF

BSF

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

upper(CODE_ADDR)

TBLPTRU

high(CODE_ADDR)

TBLPTRH

low(CODE_ADDR)

TBLPTRL

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

EECON1, FREE

INTCON, GIE

55h

; load TBLPTR with the base

; address of the memory block

; point to Flash program memory

; access Flash program memory

; enable write to memory

; enable Row Erase operation

; disable interrupts

EECON2

0AAh

EECON2

EECON1, WR

; write 55H

Required

Sequence

; write AAH

; start erase (CPU stall)

NOP

BSF

TBLRD*-

INTCON, GIE

; re-enable interrupts

; dummy read decrement

WRITE_BUFFER_BACK

MOVLW

8

; number of write buffer groups of 8 bytes

; point to buffer

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

COUNTER_HI

high(BUFFER_ADDR)

FSR0H

low(BUFFER_ADDR)

FSR0L

PROGRAM_LOOP

MOVLW

MOVWF

8

; number of bytes in holding register

COUNTER

WRITE_WORD_TO_HREGS

MOVFW

MOVWF

TBLWT+*

POSTINC0, W

TABLAT

; get low byte of buffer data

; present data to table latch

; write data, perform a short write

; to internal TBLWT holding register.

; loop until buffers are full

DECFSZ

BRA

COUNTER

WRITE_WORD_TO_HREGS

PROGRAM_MEMORY

BSF

BCF

BSF

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

INTCON, GIE

55h

EECON2

0AAh

EECON2

EECON1, WR

; point to Flash program memory

; access Flash program memory

; enable write to memory

; disable interrupts

; write 55h

Required

Sequence

; write 0AAh

; start program (CPU stall)

NOP

BSF

DECFSZ

BRA

INTCON, GIE

COUNTER_HI

PROGRAM_LOOP

EECON1, WREN

; re-enable interrupts

; loop until done

BCF

; disable write to memory

 2004 Microchip Technology Inc.

DS30491C-page 91

PIC18F6585/8585/6680/8680

5.5.2

WRITE VERIFY

5.5.4

PROTECTION AGAINST SPURIOUS

WRITES

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

To protect against spurious writes to Flash program

memory, the write initiate sequence must also be

followed. See Section 24.0 “Special Features of the

CPU” for more detail.

5.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

5.6

Flash Program Operation During

Code Protection

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and repro-

grammed if needed. The WRERR bit is set when a

write operation is interrupted by a MCLR Reset or a

WDT Time-out Reset during normal operation. In these

situations, users can check the WRERR bit and rewrite

the location.

See Section 24.0 “Special Features of the CPU” for

details on code protection of Flash program memory.

TABLE 5-2:

Name

REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Value on

Value on:

POR, BOR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

TBLPTRU

—

bit 21 Program Memory Table Pointer Upper Byte

(TBLPTR<20:16>)

--00 0000 --00 0000

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)

0000 0000 0000 0000

TABLAT

INTCON

EECON2

EECON1

IPR2

Program Memory Table Latch

GIE/GIEH PEIE/GIEL TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

RD

EEPROM Control Register 2 (not a physical register)

—

EEPGD

CFGS

CMIP

CMIF

CMIE

—

FREE

EEIP

EEIF

EEIE

WRERR WREN

WR

xx-0 x000 uu-0 u000

—

BCLIP

BCLIF

BCLIE

LVDIP

LVDIF

LVDIE

TMR3IP

TMR3IF

TMR3IE

CCP2IP -1-1 1111 -1-1 1111

CCP2IF -0-0 0000 -0-0 0000

CCP2IE -0-0 0000 -0-0 0000

PIR2

PIE2

Legend:

x= unknown, u= unchanged, r= reserved, – = unimplemented, read as ‘0’.

Shaded cells are not used during Flash/EEPROM access.

DS30491C-page 92

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

6.1

Program Memory Modes and the

External Memory Interface

6.0

EXTERNAL MEMORY

INTERFACE

As previously noted, PIC18F8X8X controllers are

capable of operating in any one of four program mem-

ory modes using combinations of on-chip and external

program memory. The functions of the multiplexed port

pins depend on the program memory mode selected as

well as the setting of the EBDIS bit.

Note:

The external memory interface is not

implemented on PIC18F6X8X (64/68-pin)

devices.

The external memory interface is a feature of the

PIC18F8X8X devices that allows the controller to

access external memory devices (such as Flash,

EPROM, SRAM, etc.) as program memory.

In Microprocessor Mode, the external bus is always

active and the port pins have only the external bus

function.

The physical implementation of the interface uses

27 pins. These pins are reserved for external address/

data bus functions; they are multiplexed with I/O port

pins on four ports. Three I/O ports are multiplexed with

the address/data bus, while the fourth port is multi-

plexed with the bus control signals. The I/O port func-

tions are enabled when the EBDIS bit in the MEMCON

register is set (see Register 6-1). A list of the

multiplexed pins and their functions is provided in

Table 6-1.

In Microcontroller Mode, the bus is not active and the

pins have their port functions only. Writes to the

MEMCOM register are not permitted.

In Microprocessor with Boot Block or Extended

Microcontroller Mode, the external program memory

bus shares I/O port functions on the pins. When the

device is fetching or doing table read/table write

operations on the external program memory space, the

pins will have the external bus function. If the device is

fetching and accessing internal program memory

locations only, the EBDIS control bit will change the

pins from external memory to I/O port functions. When

EBDIS = 0, the pins function as the external bus. When

EBDIS = 1, the pins function as I/O ports.

As implemented in the PIC18F8X8X devices, the

interface operates in a similar manner to the external

memory interface introduced on PIC18C601/801

microcontrollers. The most notable difference is that

the interface on PIC18F8X8X devices only operates in

16-bit modes. The 8-bit mode is not supported.

For a more complete discussion of the operating modes

that use the external memory interface, refer to

Section 4.1.1 “PIC18F8X8X Program Memory

Modes”.

 2004 Microchip Technology Inc.

DS30491C-page 93

PIC18F6585/8585/6680/8680

REGISTER 6-1:

MEMCON REGISTER

R/W-0

EBDIS⁽¹⁾

bit 7

U-0

—

R/W-0

WAIT1

R/W-0

WAIT0

U-0

—

U-0

—

R/W-0

WM1

R/W-0

WM0

bit 0

bit 7

EBDIS: External Bus Disable bit⁽¹⁾

1= External system bus disabled, all external bus drivers are mapped as I/O ports

0= External system bus enabled and I/O ports are disabled

Note 1: This bit is ignored when device is accessing external memory either to fetch an

instruction or perform TBLRD/TBLWT.

bit 6

Unimplemented: Read as ‘0’

bit 5-4

WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits

11= Table reads and writes will wait 0 TCY

10= Table reads and writes will wait 1 TCY

01= Table reads and writes will wait 2 TCY

00= Table reads and writes will wait 3 TCY

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

WM<1:0>: TBLWTOperation with 16-bit Bus bits

1x= Word Write mode: LSB and MSB word output, WRH active when MSB written

01= Byte Select mode: TABLAT data copied on both MS and LS Byte, WRH and (UB or LB)

will activate

00= Byte Write mode: TABLAT data copied on both MS and LS Byte, WRH or WRL will activate

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Note:

The MEMCON register is held in Reset in Microcontroller mode.

DS30491C-page 94

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

If the device fetches or accesses external memory

When the device is executing out of internal memory

(with EBDIS = 0) in Microprocessor with Boot Block

mode or Extended Microcontroller mode, the control sig-

nals will be in inactive. They will go to a state where the

AD<15:0>, A<19:16> are tri-state; the OE, WRH, WRL,

UB and LB signals are ‘1’; and ALE and BA0 are ‘0’.

while EBDIS = 1, the pins will switch to external bus. If

the EBDIS bit is set by a program executing from exter-

nal memory, the action of setting the bit will be delayed

until the program branches into the internal memory. At

that time, the pins will change from external bus to I/O

ports.

TABLE 6-1:

Name

PIC18F8X8X EXTERNAL BUS – I/O PORT FUNCTIONS

Port

Bit

Function

RD0/AD0

RD1/AD1

RD2/AD2

RD3/AD3

RD4/AD4

RD5/AD5

RD6/AD6

RD7/AD7

RE0/AD8

RE1/AD9

RE2/AD10

RE3/AD11

RE4/AD12

RE5/AD13

RE6/AD14

RE7/AD15

RH0/A16

RH1/A17

RH2/A18

RH3/A19

RJ0/ALE

RJ1/OE

PORTD

PORTE

PORTH

PORTJ

bit 0 Input/Output or System Bus Address bit 0 or Data bit 0

bit 1 Input/Output or System Bus Address bit 1 or Data bit 1

bit 2 Input/Output or System Bus Address bit 2 or Data bit 2

bit 3 Input/Output or System Bus Address bit 3 or Data bit 3

bit 4 Input/Output or System Bus Address bit 4 or Data bit 4

bit 5 Input/Output or System Bus Address bit 5 or Data bit 5

bit 6 Input/Output or System Bus Address bit 6 or Data bit 6

bit 7 Input/Output or System Bus Address bit 7 or Data bit 7

bit 0 Input/Output or System Bus Address bit 8 or Data bit 8

bit 1 Input/Output or System Bus Address bit 9 or Data bit 9

bit 2 Input/Output or System Bus Address bit 10 or Data bit 10

bit 3 Input/Output or System Bus Address bit 11 or Data bit 11

bit 4 Input/Output or System Bus Address bit 12 or Data bit 12

bit 5 Input/Output or System Bus Address bit 13 or Data bit 13

bit 6 Input/Output or System Bus Address bit 14 or Data bit 14

bit 7 Input/Output or System Bus Address bit 15 or Data bit 15

bit 0 Input/Output or System Bus Address bit 16

bit 1 Input/Output or System Bus Address bit 17

bit 2 Input/Output or System Bus Address bit 18

bit 3 Input/Output or System Bus Address bit 19

bit 0 Input/Output or System Bus Address Latch Enable (ALE) Control pin

bit 1 Input/Output or System Bus Output Enable (OE) Control pin

bit 2 Input/Output or System Bus Write Low (WRL) Control pin

bit 3 Input/Output or System Bus Write High (WRH) Control pin

bit 4 Input/Output or System Bus Byte Address bit 0

RJ2/WRL

RJ3/WRH

RJ4/BA0

RJ5/CE

bit 5 Input/Output or Chip Enable

RJ6/LB

bit 6 Input/Output or System Bus Lower Byte Enable (LB) Control pin

bit 7 Input/Output or System Bus Upper Byte Enable (UB) Control pin

RJ7/UB

 2004 Microchip Technology Inc.

DS30491C-page 95

PIC18F6585/8585/6680/8680

For all 16-bit modes, the Address Latch Enable (ALE)

pin indicates that the Address bits (A<15:0>) are avail-

able on the external memory interface bus. Following

the address latch, the Output Enable signal (OE ) will

enable both bytes of program memory at once to form

a 16-bit instruction word.

6.2

16-bit Mode

The external memory interface implemented in

PIC18F8X8X devices operates only in 16-bit mode.

The mode selection is not software configurable but is

programmed via the configuration bits.

The WM<1:0> bits in the MEMCON register determine

three types of connections in 16-bit mode. They are

referred to as:

In Byte Select mode, JEDEC standard Flash memories

will require BA0 for the byte address line, and one I/O

line to select between Byte and Word mode. The other

16-bit modes do not need BA0. JEDEC standard static

RAM memories will use the UB or LB signals for byte

selection.

• 16-bit Byte Write

• 16-bit Word Write

• 16-bit Byte Select

These three different configurations allow the designer

maximum flexibility in using 8-bit and 16-bit memory

devices.

6.2.1

16-BIT BYTE WRITE MODE

Figure 6-1 shows an example of 16-bit Byte Write

mode for PIC18F8X8X devices.

FIGURE 6-1:

16-BIT BYTE WRITE MODE EXAMPLE

D<7:0>

(MSB)

A<x:0>

(LSB)

A<x:0>

PIC18F8X8X

AD<7:0>

A<19:0>

D<15:8>

373

D<7:0>

CE

D<7:0>

CE

AD<15:8>

ALE

(1)

OE WR

A<19:16>

CE

OE

WRH

WRL

Address Bus

Data Bus

Control Lines

Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.

DS30491C-page 96

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

6.2.2

16-BIT WORD WRITE MODE

Figure 6-2 shows an example of 16-bit Word Write

mode for PIC18F8X8X devices.

FIGURE 6-2:

16-BIT WORD WRITE MODE EXAMPLE

PIC18F8X8X

AD<7:0>

A<20:1>

D<15:0>

JEDEC Word

373

A<x:0>

EPROM Memory

D<15:0>

CE

(1)

OE

WR

AD<15:8>

ALE

A<19:16>

CE

OE

WRH

Address Bus

Data Bus

Control Lines

Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.

 2004 Microchip Technology Inc.

DS30491C-page 97

PIC18F6585/8585/6680/8680

6.2.3

16-BIT BYTE SELECT MODE

Figure 6-3 shows an example of 16-bit Byte Select

mode for PIC18F8X8X devices.

FIGURE 6-3:

16-BIT BYTE SELECT MODE EXAMPLE

PIC18F8X8X

AD<7:0>

A<20:1>

373

AD<15:8>

373

ALE

A<19:16>

OE

A<20:1>

A<x:1>

OE

(1)

WRH

WR

WRL

BA0

JEDEC Word

A0

SRAM Memory

CE

LB

UB

D<15:0>

LB

D<15:0>

UB

Address Bus

Data Bus

Control Lines

Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.

DS30491C-page 98

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

6.2.4

16-BIT MODE TIMING

Figure 6-4 shows the 16-bit mode external bus timing

for PIC18F8X8X devices.

FIGURE 6-4:

EXTERNAL PROGRAM MEMORY BUS TIMING (16-BIT MODE)

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q4

Q2

Q4

Q3

Q4

Apparent Q

Actual Q

A<19:16>

0h

Ch

3AABh

CF33h

0E55h

9256h

AD<15:0>

BA0

ALE

OE

WRH

WRL

‘1’

1 TCY Wait

Opcode Fetch

Table Read

of 92h

MOVLW55h

from 007556h

from 199E67h

 2004 Microchip Technology Inc.

DS30491C-page 99

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 100

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

7.1

EEADRH:EEADR

7.0

DATA EEPROM MEMORY

The address register pair, EEADRH:EEADR, can

address up to a maximum of 1024 bytes of data

EEPROM.

The data EEPROM is readable and writable during nor-

mal operation over the entire VDD range. The data

memory is not directly mapped in the register file

space. Instead, it is indirectly addressed through the

Special Function Registers (SFR).

7.2

EECON1 and EECON2 Registers

There are five SFRs used to read and write the

program and data EEPROM memory. These registers

are:

EECON1 is the control register for EEPROM memory

accesses.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the EEPROM write sequence.

• EECON1

• EECON2

• EEDATA

• EEADR

Control bits RD and WR initiate read and write opera-

tions, respectively. These bits cannot be cleared, only

set in software. They are cleared in hardware at the

completion of the read or write operation. The inability

to clear the WR bit in software prevents the accidental

or premature termination of a write operation.

• EEADRH

The EEPROM data memory allows byte read and write.

When interfacing to the data memory block, EEDATA

holds the 8-bit data for read/write and EEADR holds the

address of the EEPROM location being accessed.

These devices have 1024 bytes of data EEPROM with

an address range from 0h to 3FFh.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset or a WDT Time-out Reset during normal opera-

tion. In these situations, the user can check the

WRERR bit and rewrite the location. It is necessary to

reload the data and address registers (EEDATA and

EEADR) due to the Reset condition forcing the

contents of the registers to zero.

The EEPROM data memory is rated for high erase/

write cycles. A byte write automatically erases the loca-

tion and writes the new data (erase-before-write). The

write time is controlled by an on-chip timer. The write

time will vary with voltage and temperature as well as

from chip to chip. Please refer to parameter D122

(Electrical Characteristics, Section 27.0 “Electrical

Characteristics”) for exact limits.

Note:

Interrupt flag bit, EEIF in the PIR2 register,

is set when write is complete. It must be

cleared in software.

 2004 Microchip Technology Inc.

DS30491C-page 101

PIC18F6585/8585/6680/8680

REGISTER 7-1:

EECON1 REGISTER (ADDRESS FA6h)

R/W-x

CFGS

U-0

—

R/W-0

FREE

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

EEPGD

WRERR

bit 7

bit 0

bit 7

bit 6

EEPGD: Flash Program or Data EEPROM Memory Select bit

1= Access Flash program memory

0= Access data EEPROM memory

CFGS: Flash Program/Data EE or Configuration Select bit

1= Access configuration or calibration registers

0= Access Flash program or data EEPROM memory

bit 5

bit 4

Unimplemented: Read as ‘0’

FREE: Flash Row Erase Enable bit

1= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0= Perform write only

bit 3

WRERR: Flash Program/Data EE Error Flag bit

1= A write operation is prematurely terminated (any MCLR or any WDT Reset during self-timed

programming in normal operation)

0= The write operation completed

Note:

When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows

tracing of the error condition.

bit 2

bit 1

WREN: Flash Program/Data EE Write Enable bit

1= Allows write cycles

0= Inhibits write to the EEPROM

WR: Write Control bit

1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete. The

WR bit can only be set (not cleared) in software.)

0= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bit

can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

0= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

S = Settable bit

- n = Value after erase

x = Bit is unknown

‘0’ = Bit is cleared

DS30491C-page 102

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

(EECON1<6>) and then set control bit, RD

(EECON1<0>). The data is available for the very next

instruction cycle; therefore, the EEDATA register can

7.3

Reading the Data EEPROM

Memory

To read a data memory location, the user must write the

address to the EEADR register, clear the EEPGD con-

trol bit (EECON1<7>), clear the CFGS control bit

be read by the next instruction. EEDATA will hold this

value until another read operation or until it is written to

by the user (during a write operation).

EXAMPLE 7-1:

DATA EEPROM READ

MOVLW

MOVWF

MOVLW

MOVWF

BCF

BSF

MOVF

DATA_EE_ADR_HI

EEADRH

DATA_EE_ADDR_LOW

EEADR

EECON1, EEPGD

EECON1, CFGS

EECON1, RD

EEDATA, W

;

; Data Memory Address to read

; Point to DATA memory

; Access program Flash or Data EEPROM memory

; EEPROM Read

; W = EEDATA

cution (i.e., runaway programs). The WREN bit should

be kept clear at all times except when updating the

EEPROM. The WREN bit is not cleared by hardware.

7.4

Writing to the Data EEPROM

Memory

To write an EEPROM data location, the address must

first be written to the EEADRH:EEADR register pair

and the data written to the EEDATA register. Then the

sequence in Example 7-2 must be followed to initiate

the write cycle.

After a write sequence has been initiated, EECON1,

EEADRH:EEADR and EDATA cannot be modified. The

WR bit will be inhibited from being set unless the

WREN bit is set. The WREN bit must be set on a pre-

vious instruction. Both WR and WREN cannot be set

with the same instruction.

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write 0AAh to

EECON2, then set WR bit) for each byte. It is strongly

recommended that interrupts be disabled during this

code segment.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EEPROM Write Complete

Interrupt Flag bit (EEIF) is set. The user may either

enable this interrupt or poll this bit. EEIF must be

cleared by software.

Additionally, the WREN bit in EECON1 must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code exe-

EXAMPLE 7-2:

DATA EEPROM WRITE

MOVLW

DATA_EE_ADDR_HI

EEADRH

DATA_EE_ADDR_LOW

EEADR

DATA_EE_DATA

EEDATA

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

;

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BCF

; Data Memory Address to read

;

; Data Memory Value to write

; Point to DATA memory

; Access program Flash or Data EEPROM memory

; Enable writes

BCF

BSF

BCF

INTCON, GIE

55h

EECON2

0AAh

EECON2

; Disable interrupts

;

; Write 55h

;

; Write 0AAh

; Set WR bit to begin write

; Enable interrupts

Required

Sequence

MOVLW

MOVWF

MOVLW

MOVWF

BSF

EECON1, WR

INTCON, GIE

BSF

.

; user code execution

.

BCF

EECON1, WREN

; Disable writes on write complete (EEIF set)

 2004 Microchip Technology Inc.

DS30491C-page 103

PIC18F6585/8585/6680/8680

7.5

Write Verify

7.7

Operation During Code-Protect

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

Data EEPROM memory has its own code-protect

mechanism. External read and write operations are

disabled if either of these mechanisms are enabled.

The microcontroller itself can both read and write to the

internal data EEPROM regardless of the state of the

code-protect configuration bit. Refer to Section 24.0

“Special Features of the CPU” for additional

information.

7.6

Protection Against Spurious Write

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared.

Also, the Power-up Timer (72 ms duration) prevents

EEPROM write.

7.8

Using the Data EEPROM

The data EEPROM is a high endurance, byte address-

able array that has been optimized for the storage of

frequently changing information (e.g., program vari-

ables or other data that are updated often). Frequently

changing values will typically be updated more often

than specification D124. If this is not the case, an array

refresh must be performed. For this reason, variables

that change infrequently (such as constants, IDs,

calibration, etc.) should be stored in Flash program

memory.

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch, or software malfunction.

A simple data EEPROM refresh routine is shown in

Example 7-3.

Note:

If data EEPROM is only used to store con-

stants and/or data that changes rarely, an

array refresh is likely not required. See

specification D124.

EXAMPLE 7-3:

DATA EEPROM REFRESH ROUTINE

CLRF

BCF

EEADRH

EEADR

EECON1, CFGS

EECON1, EEPGD

INTCON, GIE

EECON1, WREN

;

; Start at address 0

; Set for memory

; Set for Data EEPROM

; Disable interrupts

; Enable writes

; Loop to refresh array

; Read current address

;

; Write 55h

;

; Write 0AAh

; Set WR bit to begin write

; Wait for write to complete

BSF

Loop

BSF

EECON1, RD

55h

EECON2

0AAh

EECON2

EECON1, WR

$-2

MOVLW

MOVWF

MOVLW

MOVWF

BSF

BTFSC

BRA

INCFSZ

BRA

EEADR, F

Loop

; Increment address

; Not zero, do it again

INCFS2

BRA

EEADRH, F

Loop

;

BCF

BSF

EECON1, WREN

INTCON, GIE

; Disable writes

; Enable interrupts

DS30491C-page 104

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 7-1:

Name

REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Value on

all other

Resets

Value on:

POR, BOR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

EEADRH

GIE/

GIEH

PEIE/

GIEL

T0IE

—

INTE

—

RBIE

—

T0IF

—

INTF

RBIF 0000 000x 0000 000u

—

EE Addr High

---- --00 ---- --00

0000 0000 0000 0000

EEADR EEPROM Address Register

EEDATA EEPROM Data Register

EECON2 EEPROM Control Register 2 (not a physical register)

—

EECON1 EEPGD CFGS

—

FREE WRERR WREN

WR

RD

xx-0 x000 uu-0 u000

IPR2

PIR2

PIE2

—

CMIP

CMIF

CMIE

EEIP

EEIF

EEIE

BCLIP

BCLIF

BCLIE

LVDIP TMR3IP CCP2IP -1-1 1111 ---1 1111

LVDIF TMR3IF CCP2IF -0-0 0000 ---0 0000

LVDIE TMR3IE CCP2IE -0-0 0000 ---0 0000

Legend: x= unknown, u= unchanged, r= reserved, –= unimplemented, read as ‘0’.

Shaded cells are not used during Flash/EEPROM access.

 2004 Microchip Technology Inc.

DS30491C-page 105

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 106

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

8.2

Operation

8.0

8.1

8 x 8 HARDWARE MULTIPLIER

Introduction

Example 8-1 shows the sequence to do an 8 x 8

unsigned multiply. Only one instruction is required

when one argument of the multiply is already loaded in

the WREG register.

An 8 x 8 hardware multiplier is included in the ALU of

the PIC18F6585/8585/6680/8680 devices. By making

the multiply a hardware operation, it completes in a sin-

gle instruction cycle. This is an unsigned multiply that

gives a 16-bit result. The result is stored in the 16-bit

product register pair (PRODH:PRODL). The multiplier

does not affect any flags in the ALUSTA register.

Example 8-2 shows the sequence to do an 8 x 8 signed

multiply. To account for the sign bits of the arguments,

each argument’s Most Significant bit (MSb) is tested

and the appropriate subtractions are done.

EXAMPLE 8-1:

8 x 8 UNSIGNED

MULTIPLY ROUTINE

Making the 8 x 8 multiplier execute in a single cycle

gives the following advantages:

MOVF

MULWF

ARG1, W

ARG2

;

• Higher computational throughput

; ARG1 * ARG2 ->

; PRODH:PRODL

• Reduces code size requirements for multiply

algorithms

The performance increase allows the device to be used

in applications previously reserved for Digital Signal

Processors.

EXAMPLE 8-2:

8 x 8 SIGNED MULTIPLY

ROUTINE

Table 8-1 shows a performance comparison between

enhanced devices using the single-cycle hardware

multiply and performing the same function without the

hardware multiply.

MOVF

MULWF

ARG1, W

ARG2

;

; ARG1 * ARG2 ->

; PRODH:PRODL

; Test Sign Bit

; PRODH = PRODH

BTFSC

SUBWF

ARG2, SB

PRODH

;

- ARG1

MOVF

BTFSC

SUBWF

ARG2, W

ARG1, SB

PRODH

; Test Sign Bit

; PRODH = PRODH

;

- ARG2

TABLE 8-1:

Routine

PERFORMANCE COMPARISON

Program

Time

@ 40 MHz @ 10 MHz @ 4 MHz

Cycles

(Max)

Multiply Method

Memory

(Words)

Without hardware multiply

Hardware multiply

13

1

69

1

6.9 µs

100 ns

9.1 µs

600 ns

24.2 µs

2.4 µs

25.4 µs

3.6 µs

27.6 µs

400 ns

36.4 µs

2.4 µs

96.8 µs

9.6 µs

69 µs

1 µs

8 x 8 unsigned

8 x 8 signed

Without hardware multiply

Hardware multiply

33

6

91

6

91 µs

6 µs

242 µs

24 µs

254 µs

36 µs

Without hardware multiply

Hardware multiply

21

24

52

36

242

24

254

36

16 x 16 unsigned

16 x 16 signed

Without hardware multiply

Hardware multiply

102.6 µs

14.4 µs

 2004 Microchip Technology Inc.

DS30491C-page 107

PIC18F6585/8585/6680/8680

Example 8-3 shows the sequence to do a 16 x 16

unsigned multiply. Equation 8-1 shows the algorithm

that is used. The 32-bit result is stored in four registers,

RES3:RES0.

EQUATION 8-2:

16 x 16 SIGNED

MULTIPLICATION

ALGORITHM

RES3:RES0

=

ARG1H:ARG1L • ARG2H:ARG2L

(ARG1H • ARG2H • 216) +

EQUATION 8-1:

16 x 16 UNSIGNED

MULTIPLICATION

ALGORITHM

(ARG1H • ARG2L • 28) +

(ARG1L • ARG2H • 28) +

(ARG1L • ARG2L) +

(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +

(-1 • ARG1H<7> • ARG2H:ARG2L • 216)

RES3:RES0

=

ARG1H:ARG1L • ARG2H:ARG2L

(ARG1H • ARG2H • 216) +

(ARG1H • ARG2L • 28) +

(ARG1L • ARG2H • 28) +

(ARG1L • ARG2L)

EXAMPLE 8-4:

16 x 16 SIGNED

MULTIPLY ROUTINE

MOVF

MULWF

ARG1L, W

ARG2L

EXAMPLE 8-3:

16 x 16 UNSIGNED

MULTIPLY ROUTINE

; ARG1L * ARG2L ->

; PRODH:PRODL

MOVF

MULWF

ARG1L, W

ARG2L

MOVFF

PRODH, RES1

PRODL, RES0

;

; ARG1L * ARG2L ->

; PRODH:PRODL

;

MOVFF

PRODH, RES1

PRODL, RES0

MOVF

MULWF

ARG1H, W

ARG2H

; ARG1H * ARG2H ->

;

; PRODH:PRODL

;

MOVF

MULWF

ARG1H, W

ARG2H

MOVFF

PRODH, RES3

PRODL, RES2

; ARG1H * ARG2H ->

; PRODH:PRODL

MOVFF

PRODH, RES3

PRODL, RES2

;

MOVF

MULWF

ARG1L, W

ARG2H

; ARG1L * ARG2H ->

; PRODH:PRODL

MOVF

MULWF

ARG1L, W

ARG2H

MOVF

ADDWF

MOVF

PRODL, W

RES1

PRODH, W

;

; ARG1L * ARG2H ->

; PRODH:PRODL

; Add cross

; products

MOVF

ADDWF

MOVF

PRODL, W

RES1

PRODH, W

;

ADDWFC RES2

CLRF WREG

ADDWFC RES3

;

; Add cross

; products

ADDWFC RES2

CLRF WREG

ADDWFC RES3

;

MOVF

MULWF

ARG1H, W

ARG2L

;

; ARG1H * ARG2L ->

;

; PRODH:PRODL

MOVF

MULWF

ARG1H, W

ARG2L

;

MOVF

ADDWF

MOVF

PRODL, W

RES1

PRODH, W

;

; ARG1H * ARG2L ->

; PRODH:PRODL

; Add cross

; products

MOVF

ADDWF

MOVF

PRODL, W

RES1

PRODH, W

;

ADDWFC RES2

CLRF WREG

ADDWFC RES3

;

; Add cross

; products

ADDWFC RES2

CLRF WREG

ADDWFC RES3

;

BTFSS

BRA

MOVF

SUBWF

MOVF

ARG2H, 7

; ARG2H:ARG2L neg?

; no, check ARG1

;

SIGN_ARG1

ARG1L, W

RES2

Example 8-4 shows the sequence to do a 16 x 16

signed multiply. Equation 8-2 shows the algorithm

used. The 32-bit result is stored in four registers,

RES3:RES0. To account for the sign bits of the argu-

ments, each argument pairs’ Most Significant bit (MSb)

is tested and the appropriate subtractions are done.

ARG1H, W

SUBWFB RES3

SIGN_ARG1

BTFSS

BRA

ARG1H, 7

CONT_CODE

ARG2L, W

RES2

; ARG1H:ARG1L neg?

; no, done

;

MOVF

SUBWF

MOVF

ARG2H, W

SUBWFB RES3

;

CONT_CODE

:

DS30491C-page 108

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

When the IPEN bit is cleared (default state), the

interrupt priority feature is disabled and interrupts are

9.0

INTERRUPTS

compatible with PICmicro^®mid-range devices. In Com-

patibility mode, the interrupt priority bits for each source

have no effect. INTCON<6> is the PEIE bit which

enables/disables all peripheral interrupt sources.

INTCON<7> is the GIE bit which enables/disables all

interrupt sources. All interrupts branch to address

000008h in Compatibility mode.

The PIC18F6585/8585/6680/8680 devices have multi-

ple interrupt sources and an interrupt priority feature

that allows each interrupt source to be assigned a high

or a low priority level. The high priority interrupt vector

is at 000008h while the low priority interrupt vector is at

000018h. High priority interrupt events will override any

low priority interrupts that may be in progress.

There are thirteen registers which are used to control

interrupt operation. They are:

When an interrupt is responded to, the global interrupt

enable bit is cleared to disable further interrupts. If the

IPEN bit is cleared, this is the GIE bit. If interrupt priority

levels are used, this will be either the GIEH or GIEL bit.

High priority interrupt sources can interrupt a low

priority interrupt.

• RCON

• INTCON

• INTCON2

• INTCON3

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address

(000008h or 000018h). Once in the Interrupt Service

Routine, the source(s) of the interrupt can be deter-

mined by polling the interrupt flag bits. The interrupt

flag bits must be cleared in software before re-enabling

interrupts to avoid recursive interrupts.

• PIR1, PIR2, PIR3

• PIE1, PIE2, PIE3

• IPR1, IPR2, IPR3

It is recommended that the Microchip header files

supplied with MPLAB^®IDE be used for the symbolic bit

names in these registers. This allows the assembler/

compiler to automatically take care of the placement of

these bits within the specified register.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine and sets the GIE bit (GIEH or GIEL

if priority levels are used) which re-enables interrupts.

Each interrupt source (except INT0) has three bits to

control its operation. The functions of these bits are:

For external interrupt events, such as the INT pins or

the PORTB input change interrupt, the interrupt latency

will be three to four instruction cycles. The exact

latency is the same for one- or two-cycle instructions.

Individual interrupt flag bits are set regardless of the

status of their corresponding enable bit or the GIE bit.

• Flag bit to indicate that an interrupt event

occurred

• Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

• Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the

IPEN bit (RCON<7>). When interrupt priority is

enabled, there are two bits which enable interrupts

globally. Setting the GIEH bit (INTCON<7>) enables all

interrupts that have the priority bit set. Setting the GIEL

bit (INTCON<6>) enables all interrupts that have the

priority bit cleared. When the interrupt flag, enable bit

and appropriate global interrupt enable bit are set, the

interrupt will vector immediately to address 000008h or

000018h depending on the priority level. Individual

interrupts can be disabled through their corresponding

enable bits.

 2004 Microchip Technology Inc.

DS30491C-page 109

PIC18F6585/8585/6680/8680

FIGURE 9-1:

INTERRUPT LOGIC

Wake-up if in Sleep Mode

TMR0IF

TMR0IE

TMR0IP

RBIF

RBIE

RBIP

INT0IF

INT0IE

Interrupt to CPU

Vector to Location

0008h

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit

Peripheral Interrupt Priority bit

GIEH/GIE

TMR1IF

TMR1IE

TMR1IP

IPE

IPEN

XXXXIF

XXXXIE

XXXXIP

GIEL/PEIE

IPEN

Additional Peripheral Interrupts

High Priority Interrupt Generation

Low Priority Interrupt Generation

Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit

Peripheral Interrupt Priority bit

Interrupt to CPU

Vector to Location

0018h

TMR0IF

TMR0IE

TMR0IP

TMR1IF

TMR1IE

TMR1IP

RBIF

RBIE

XXXXIF

XXXXIE

XXXXIP

GIEL/PEIE

RBIP

GIE/GEIH

INT1IF

INT1IE

INT1IP

Additional Peripheral Interrupts

INT2IF

INT2IE

INT2IP

DS30491C-page 110

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

9.1

INTCON Registers

Note:

Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit. User software should ensure

the appropriate interrupt flag bits are clear

prior to enabling an interrupt. This feature

allows for software polling.

The INTCON registers are readable and writable

registers which contain various enable, priority and flag

bits.

REGISTER 9-1:

INTCON REGISTER

R/W-0 R/W-0

R/W-0

RBIE

R/W-0

INT0IF

R/W-x

RBIF

GIE/GIEH PEIE/GIEL

bit 7

TMR0IE

INT0IE

TMR0IF

bit 0

bit 7

GIE/GIEH: Global Interrupt Enable bit

When IPEN (RCON<7>) = 0:

1= Enables all unmasked interrupts

0= Disables all interrupts

When IPEN (RCON<7>) = 1:

1= Enables all high priority interrupts

0= Disables all interrupts

bit 6

PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN (RCON<7>) = 0:

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

When IPEN (RCON<7>) = 1:

1= Enables all low priority peripheral interrupts

0= Disables all low priority peripheral interrupts

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TMR0IE: TMR0 Overflow Interrupt Enable bit

1= Enables the TMR0 overflow interrupt

0= Disables the TMR0 overflow interrupt

INT0IE: INT0 External Interrupt Enable bit

1= Enables the INT0 external interrupt

0= Disables the INT0 external interrupt

RBIE: RB Port Change Interrupt Enable bit

1= Enables the RB port change interrupt

0= Disables the RB port change interrupt

TMR0IF: TMR0 Overflow Interrupt Flag bit

1= TMR0 register has overflowed (must be cleared in software)

0= TMR0 register did not overflow

INT0IF: INT0 External Interrupt Flag bit

1= The INT0 external interrupt occurred (must be cleared in software)

0= The INT0 external interrupt did not occur

RBIF: RB Port Change Interrupt Flag bit

1= At least one of the RB7:RB4 pins changed state (must be cleared in software)

0= None of the RB7:RB4 pins have changed state

Note:

A mismatch condition will continue to set this bit. Reading PORTB will end the

mismatch condition and allow the bit to be cleared.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 111

PIC18F6585/8585/6680/8680

REGISTER 9-2:

INTCON2 REGISTER

R/W-1

RBPU

R/W-1

RBIP

INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP

INT3IP

bit 7

bit 0

bit 7

bit 6

RBPU: PORTB Pull-up Enable bit

1= All PORTB pull-ups are disabled

0= PORTB pull-ups are enabled by individual port latch values

INTEDG0: External Interrupt 0 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

bit 5

bit 4

INTEDG1: External Interrupt 1 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

INTEDG2: External Interrupt 2 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

bit 3

bit 2

bit 1

bit 0

INTEDG3: External Interrupt 3 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

TMR0IP: TMR0 Overflow Interrupt Priority bit

1= High priority

0= Low priority

INT3IP: INT3 External Interrupt Priority bit

1= High priority

0= Low priority

RBIP: RB Port Change Interrupt Priority bit

1= High priority

0= Low priority

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Note:

Interrupt flag bits are set when an interrupt condition occurs regardless of the state

of its corresponding enable bit or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows for software polling.

DS30491C-page 112

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 9-3:

INTCON3 REGISTER

R/W-1

R/W-0

INT3IF

R/W-0

INT2IF

R/W-0

INT1IF

INT2IP

INT1IP

INT3IE

INT2IE

INT1IE

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

INT2IP: INT2 External Interrupt Priority bit

1= High priority

0= Low priority

INT1IP: INT1 External Interrupt Priority bit

1= High priority

0= Low priority

INT3IE: INT3 External Interrupt Enable bit

1= Enables the INT3 external interrupt

0= Disables the INT3 external interrupt

INT2IE: INT2 External Interrupt Enable bit

1= Enables the INT2 external interrupt

0= Disables the INT2 external interrupt

INT1IE: INT1 External Interrupt Enable bit

1= Enables the INT1 external interrupt

0= Disables the INT1 external interrupt

INT3IF: INT3 External Interrupt Flag bit

1= The INT3 external interrupt occurred (must be cleared in software)

0= The INT3 external interrupt did not occur

INT2IF: INT2 External Interrupt Flag bit

1= The INT2 external interrupt occurred (must be cleared in software)

0= The INT2 external interrupt did not occur

INT1IF: INT1 External Interrupt Flag bit

1= The INT1 external interrupt occurred (must be cleared in software)

0= The INT1 external interrupt did not occur

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Note:

Interrupt flag bits are set when an interrupt condition occurs regardless of the state

of its corresponding enable bit or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows for software polling.

 2004 Microchip Technology Inc.

DS30491C-page 113

PIC18F6585/8585/6680/8680

9.2

PIR Registers

Note 1: Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

The PIR registers contain the individual flag bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are three Peripheral Interrupt

Flag registers (PIR1, PIR2 and PIR3).

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to

enabling an interrupt, and after servicing

that interrupt.

REGISTER 9-4:

PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

R/W-0

PSPIF⁽¹⁾

bit 7

R/W-0

ADIF

R-0

R/W-0

SSPIF

R/W-0

RCIF

TXIF

CCP1IF

TMR2IF

TMR1IF

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit⁽¹⁾

1= A read or a write operation has taken place (must be cleared in software)

0= No read or write has occurred

ADIF: A/D Converter Interrupt Flag bit

1= An A/D conversion completed (must be cleared in software)

0= The A/D conversion is not complete

RCIF: USART Receive Interrupt Flag bit

1= The USART receive buffer, RCREG, is full (cleared when RCREG is read)

0= The USART receive buffer is empty

TXIF: USART Transmit Interrupt Flag bit

1= The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)

0= The USART transmit buffer is full

SSPIF: Master Synchronous Serial Port Interrupt Flag bit

1= The transmission/reception is complete (must be cleared in software)

0= Waiting to transmit/receive

CCP1IF: Enhanced CCP1 Interrupt Flag bit

Capture mode:

1= A TMR1 register capture occurred (must be cleared in software)

0= No TMR1 register capture occurred

Compare mode:

1= A TMR1 register compare match occurred (must be cleared in software)

0= No TMR1 register compare match occurred

PWM mode:

Unused in this mode.

bit 1

bit 0

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1= TMR2 to PR2 match occurred (must be cleared in software)

0= No TMR2 to PR2 match occurred

TMR1IF: TMR1 Overflow Interrupt Flag bit

1= TMR1 register overflowed (must be cleared in software)

0= TMR1 register did not overflow

Note 1: Available in Microcontroller mode only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 114

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 9-5:

PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2

U-0

—

R/W-0

CMIF

U-0

—

R/W-0

EEIF

R/W-0

BCLIF

R/W-0

LVDIF

R/W-0

TMR3IF

CCP2IF

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ‘0’

CMIF: Comparator Interrupt Flag bit

1= The comparator input has changed (must be cleared in software)

0= The comparator input has not changed

bit 5

bit 4

Unimplemented: Read as ‘0’

EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit

1= The write operation is complete (must be cleared in software)

0= The write operation is not complete, or has not been started

bit 3

BCLIF: Bus Collision Interrupt Flag bit

1= A bus collision occurred while the SSP module (configured in I²C Master mode)

was transmitting (must be cleared in software)

0= No bus collision occurred

bit 2

bit 1

bit 0

LVDIF: Low-Voltage Detect Interrupt Flag bit

1= A low-voltage condition occurred (must be cleared in software)

0= The device voltage is above the Low-Voltage Detect trip point

TMR3IF: TMR3 Overflow Interrupt Flag bit

1= TMR3 register overflowed (must be cleared in software)

0= TMR3 register did not overflow

CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1= A TMR1 or TMR3 register capture occurred (must be cleared in software)

0= No TMR1 or TMR3 register capture occurred

Compare mode:

1= A TMR1 or TMR3 register compare match occurred (must be cleared in software)

0= No TMR1 or TMR3 register compare match occurred

PWM mode:

Unused in this mode.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 115

PIC18F6585/8585/6680/8680

REGISTER 9-6:

PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3

R/W-0

IRXIF

R/W-0

ERRIF

R/W-0

WAKIF

TXB2IF/ TXB1IF⁽¹⁾TXB0IF⁽¹⁾RXB1IF/

RXB0IF/

TXBnIF

RXBnIF FIFOWMIF

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

IRXIF: CAN Invalid Received Message Interrupt Flag bit

1= An invalid message has occurred on the CAN bus

0= No invalid message on CAN bus

WAKIF: CAN bus Activity Wake-up Interrupt Flag bit

1= Activity on CAN bus has occurred

0= No activity on CAN bus

ERRIF: CAN bus Error Interrupt Flag bit

1= An error has occurred in the CAN module (multiple sources)

0= No CAN module errors

When CAN is in Mode 0:

TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit

1= Transmit Buffer 2 has completed transmission of a message and may be reloaded

0= Transmit Buffer 2 has not completed transmission of a message

When CAN is in Mode 1 or 2:

TXBnIF: Any Transmit Buffer Interrupt Flag bit

1= One or more transmit buffers has completed transmission of a message and may be

reloaded (TXBIE or BIE0<7:2> must be non-zero)

0= No message was transmitted

bit 3

bit 2

bit 1

TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit⁽¹⁾

1= Transmit Buffer 1 has completed transmission of a message and may be reloaded

0= Transmit Buffer 1 has not completed transmission of a message

TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit⁽¹⁾

1= Transmit Buffer 0 has completed transmission of a message and may be reloaded

0= Transmit Buffer 0 has not completed transmission of a message

When CAN is in Mode 0:

RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit

1= Receive Buffer 1 has received a new message

0= Receive Buffer 1 has not received a new message

When CAN is in Mode 1 or 2:

RXBnIF: CAN Receive Buffer Interrupt Flag bit

1= One or more receive buffers has received a new message

0= No receive buffer has received a new message

bit 0

When CAN is in Mode 0:

RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit⁽¹⁾

1= Receive Buffer 0 has received a new message

0= Receive Buffer 0 has not received a new message

When CAN is in Mode 1:

Unimplemented: Read as ‘0’

When CAN is in Mode 2:

FIFOWMIF: FIFO Watermark Interrupt Flag bit

1= FIFO high watermark is reached

0= FIFO high watermark is not reached

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 116

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

9.3

PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three Peripheral

Interrupt Enable registers (PIE1, PIE2 and PIE3).

When the IPEN bit (RCON<7>) is ‘0’, the PEIE bit must

be set to enable any of these peripheral interrupts.

REGISTER 9-7:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

PSPIE⁽¹⁾

bit 7

R/W-0

ADIE

R/W-0

RCIE

R/W-0

TXIE

R/W-0

SSPIE

R/W-0

TMR1IE

bit 0

CCP1IE

TMR2IE

bit 7

PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit⁽¹⁾

1= Enables the PSP read/write interrupt

0= Disables the PSP read/write interrupt

Note 1: Available in Microcontroller mode only.

ADIE: A/D Converter Interrupt Enable bit

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

1= Enables the A/D interrupt

0= Disables the A/D interrupt

RCIE: USART Receive Interrupt Enable bit

1= Enables the USART receive interrupt

0= Disables the USART receive interrupt

TXIE: USART Transmit Interrupt Enable bit

1= Enables the USART transmit interrupt

0= Disables the USART transmit interrupt

SSPIE: Master Synchronous Serial Port Interrupt Enable bit

1= Enables the MSSP interrupt

0= Disables the MSSP interrupt

CCP1IE: Enhanced CCP1 Interrupt Enable bit

1= Enables the CCP1 interrupt

0= Disables the CCP1 interrupt

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1= Enables the TMR2 to PR2 match interrupt

0= Disables the TMR2 to PR2 match interrupt

TMR1IE: TMR1 Overflow Interrupt Enable bit

1= Enables the TMR1 overflow interrupt

0= Disables the TMR1 overflow interrupt

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 117

PIC18F6585/8585/6680/8680

REGISTER 9-8:

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

U-0

—

R/W-0

CMIE

U-0

—

R/W-0

EEIE

R/W-0

BCLIE

R/W-0

LVDIE

R/W-0

TMR3IE

CCP2IE

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ‘0’

CMIE: Comparator Interrupt Enable bit

1= Enables the comparator interrupt

0= Disables the comparator interrupt

bit 5

bit 4

Unimplemented: Read as ‘0’

EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit

1= Enables the write operation interrupt

0= Disables the write operation interrupt

bit 3

bit 2

bit 1

bit 0

BCLIE: Bus Collision Interrupt Enable bit

1= Enables the bus collision interrupt

0= Disables the bus collision interrupt

LVDIE: Low-Voltage Detect Interrupt Enable bit

1= Enables the Low-Voltage Detect interrupt

0= Disables the Low-Voltage Detect interrupt

TMR3IE: TMR3 Overflow Interrupt Enable bit

1= Enables the TMR3 overflow interrupt

0= Disables the TMR3 overflow interrupt

CCP2IE: CCP2 Interrupt Enable bit

1= Enables the CCP2 interrupt

0= Disables the CCP2 interrupt

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 118

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 9-9:

PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

R/W-0

IRXIE

R/W-0

ERRIE

R/W-0

TXB2IE/ TXB1IE⁽¹⁾TXB0IE⁽¹⁾RXB1IE/

TXBnIE RXBnIE

R/W-0

WAKIE

RXB0IE/

FIFOWMIE

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

IRXIE: CAN Invalid Received Message Interrupt Enable bit

1= Enable invalid message received interrupt

0= Disable invalid message received interrupt

WAKIE: CAN bus Activity Wake-up Interrupt Enable bit

1= Enable bus activity wake-up interrupt

0= Disable bus activity wake-up interrupt

ERRIE: CAN bus Error Interrupt Enable bit

1= Enable CAN bus error interrupt

0= Disable CAN bus error interrupt

When CAN is in Mode 0:

TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit

1= Enable Transmit Buffer 2 interrupt

0= Disable Transmit Buffer 2 interrupt

When CAN is in Mode 1 or 2:

TXBnIE: CAN Transmit Buffer Interrupts Enable bit

1= Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0

0= Disable all transmit buffer interrupts

bit 3

bit 2

bit 1

TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit⁽¹⁾

1= Enable Transmit Buffer 1 interrupt

0= Disable Transmit Buffer 1 interrupt

TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit⁽¹⁾

1= Enable Transmit Buffer 0 interrupt

0= Disable Transmit Buffer 0 interrupt

When CAN is in Mode 0:

RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit

1= Enable Receive Buffer 1 interrupt

0= Disable Receive Buffer 1 interrupt

When CAN is in Mode 1 or 2:

RXBnIE: CAN Receive Buffer Interrupts Enable bit

1= Enable receive buffer interrupt; individual interrupt is enabled by BIE0

0= Disable all receive buffer interrupts

bit 0

When CAN is in Mode 0:

RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit

1= Enable Receive Buffer 0 interrupt

0= Disable Receive Buffer 0 interrupt

When CAN is in Mode 1:

Unimplemented: Read as ‘0’

When CAN is in Mode 2:

FIFOWMIE: FIFO Watermark Interrupt Enable bit

1= Enable FIFO watermark interrupt

0= Disable FIFO watermark interrupt

Note 1: In CAN Mode 1 and 2, this bit is forced to ‘0’.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 119

PIC18F6585/8585/6680/8680

9.4

IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three Peripheral

Interrupt Priority registers (IPR1, IPR2 and IPR3). The

operation of the priority bits requires that the Interrupt

Priority Enable (IPEN) bit be set.

REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

R/W-1

PSPIP⁽¹⁾

bit 7

R/W-1

ADIP

R/W-1

RCIP

R/W-1

TXIP

R/W-1

SSPIP

R/W-1

TMR1IP

bit 0

CCP1IP

TMR2IP

bit 7

PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit⁽¹⁾

1= High priority

0= Low priority

Note 1: Available in Microcontroller mode only.

ADIP: A/D Converter Interrupt Priority bit

bit 6

bit 5

bit 4

1= High priority

0= Low priority

RCIP: USART Receive Interrupt Priority bit

1= High priority

0= Low priority

TXIP: USART Transmit Interrupt Priority bit

1= High priority

0= Low priority

bit 3

bit 2

bit 1

bit 0

SSPIP: Master Synchronous Serial Port Interrupt Priority bit

1= High priority

0= Low priority

CCP1IP: CCP1 Interrupt Priority bit

1= High priority

0= Low priority

TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

1= High priority

0= Low priority

TMR1IP: TMR1 Overflow Interrupt Priority bit

1= High priority

0= Low priority

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 120

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2

U-0

—

R/W-1

CMIP

U-0

—

R/W-1

EEIP

R/W-1

BCLIP

R/W-1

LVDIP

R/W-1

TMR3IP

CCP2IP

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ‘0’

CMIP: Comparator Interrupt Priority bit

1= High priority

0= Low priority

bit 5

bit 4

Unimplemented: Read as ‘0’

EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit

1= High priority

0= Low priority

bit 3

bit 2

bit 1

bit 0

BCLIP: Bus Collision Interrupt Priority bit

1= High priority

0= Low priority

LVDIP: Low-Voltage Detect Interrupt Priority bit

1= High priority

0= Low priority

TMR3IP: TMR3 Overflow Interrupt Priority bit

1= High priority

0= Low priority

CCP2IP: CCP2 Interrupt Priority bit

1= High priority

0= Low priority

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 121

PIC18F6585/8585/6680/8680

REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3

R/W-1

IRXIP

R/W-1

ERRIP

R/W-1

TXB2IP/ TXB1IP⁽¹⁾TXB0IP⁽¹⁾RXB1IP/

TXBnIP RXBnIP

R/W-1

WAKIP

RXB0IP/

FIFOWMIP

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

IRXIP: CAN Invalid Received Message Interrupt Priority bit

1= High priority

0= Low priority

WAKIP: CAN bus Activity Wake-up Interrupt Priority bit

1= High priority

0= Low priority

ERRIP: CAN bus Error Interrupt Priority bit

1= High priority

0= Low priority

When CAN is in Mode 0:

TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit

1= High priority

0= Low priority

When CAN is in Mode 1 or 2:

TXBnIP: CAN Transmit Buffer Interrupt Priority bit

1= High priority

0= Low priority

bit 3

bit 2

bit 1

TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit⁽¹⁾

1= High priority

0= Low priority

TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit⁽¹⁾

1= High priority

0= Low priority

When CAN is in Mode 0:

RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit

1= High priority

0= Low priority

When CAN is in Mode 1 or 2:

RXBnIP: CAN Receive Buffer Interrupts Priority bit

1= High priority

0= Low priority

bit 0

When CAN is in Mode 0:

RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit

1= High priority

0= Low priority

When CAN is in Mode 1:

Unimplemented: Read as ‘0’

When CAN is in Mode 2:

FIFOWMIP: FIFO Watermark Interrupt Priority bit

1= High priority

0= Low priority

Note 1: In CAN Mode 1 and 2, this bit is forced to ‘0’.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 122

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

9.5

RCON Register

The RCON register contains the IPEN bit which is used

to enable prioritized interrupts. The functions of the

other bits in this register are discussed in more detail in

Section 4.14 “RCON Register”.

REGISTER 9-13: RCON REGISTER

R/W-0

IPEN

U-0

—

U-0

—

R/W-1

RI

R-1

TO

R-1

PD

R/W-0

POR

R/W-0

BOR

bit 7

bit 0

bit 7

IPEN: Interrupt Priority Enable bit

1= Enable priority levels on interrupts

0= Disable priority levels on interrupts (PIC16 Compatibility mode)

bit 6-5 Unimplemented: Read as ‘0’

bit 4

bit 3

bit 2

bit 1

bit 0

RI: RESETInstruction Flag bit

For details of bit operation, see Register 4-4.

TO: Watchdog Time-out Flag bit

For details of bit operation, see Register 4-4.

PD: Power-down Detection Flag bit

For details of bit operation, see Register 4-4.

POR: Power-on Reset Status bit

For details of bit operation, see Register 4-4.

BOR: Brown-out Reset Status bit

For details of bit operation, see Register 4-4.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

 2004 Microchip Technology Inc.

DS30491C-page 123

PIC18F6585/8585/6680/8680

9.6

INT0 Interrupt

9.7

TMR0 Interrupt

External interrupts on the RB0/INT0, RB1/INT1, RB2/

INT2 and RB3/INT3 pins are edge-triggered: either ris-

ing if the corresponding INTEDGx bit is set in the

INTCON2 register, or falling if the INTEDGx bit is clear.

When a valid edge appears on the RBx/INTx pin, the

corresponding flag bit, INTxF, is set. This interrupt can

be disabled by clearing the corresponding enable bit,

INTxE. Flag bit, INTxF, must be cleared in software in

the Interrupt Service Routine before re-enabling the

interrupt. All external interrupts (INT0, INT1, INT2 and

INT3) can wake-up the processor from Sleep if bit

INTxIE was set prior to going into Sleep. If the global

interrupt enable bit GIE is set, the processor will branch

to the interrupt vector following wake-up.

In 8-bit mode (which is the default), an overflow in the

TMR0 register (0FFh → 00h) will set flag bit TMR0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L regis-

ters (0FFFFh → 0000h) will set flag bit, TMR0IF. The

interrupt can be enabled/disabled by setting/clearing

enable bit, TMR0IE (INTCON<5>). Interrupt priority for

Timer0 is determined by the value contained in the

interrupt priority bit, TMR0IP (INTCON2<2>). See

Section 11.0 “Timer0 Module” for further details on

the Timer0 module.

9.8

PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit, RBIE (INTCON<3>).

Interrupt priority for PORTB interrupt-on-change is

determined by the value contained in the interrupt

priority bit, RBIP (INTCON2<0>).

The interrupt priority for INT, INT2 and INT3 is deter-

mined by the value contained in the interrupt priority

bits: INT1IP (INTCON3<6>), INT2IP (INTCON3<7>)

and INT3IP (INTCON2<1>). There is no priority bit

associated with INT0; it is always a high priority

interrupt source.

9.9

Context Saving During Interrupts

During an interrupt, the return PC value is saved on the

stack. Additionally, the WREG, Status and BSR registers

are saved on the fast return stack. If a fast return from

interrupt is not used (See Section 4.3 “Fast Register

Stack”), the user may need to save the WREG, Status

and BSR registers in software. Depending on the user’s

application, other registers may also need to be saved.

Example 9-1 saves and restores the WREG, Status and

BSR registers during an Interrupt Service Routine.

EXAMPLE 9-1:

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF

MOVFF

;

W_TEMP

STATUS, STATUS_TEMP

BSR, BSR_TEMP

; W_TEMP is in virtual bank

; STATUS_TEMP located anywhere

; BSR located anywhere

; USER ISR CODE

;

MOVFF

MOVF

MOVFF

BSR_TEMP, BSR

W_TEMP, W

STATUS_TEMP, STATUS

; Restore BSR

; Restore WREG

; Restore STATUS

DS30491C-page 124

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

10.1 PORTA, TRISA and LATA

Registers

10.0 I/O PORTS

Depending on the device selected, there are either seven

or nine I/O ports available on PIC18F6X8X/8X8X

devices. Some of their pins are multiplexed with one or

more alternate functions from the other peripheral fea-

tures on the device. In general, when a peripheral is

enabled, that pin may not be used as a general purpose

I/O pin.

PORTA is a 7-bit wide, bidirectional port. The corre-

sponding data direction register is TRISA. Setting a

TRISA bit (= 1) will make the corresponding PORTA pin

an input (i.e., put the corresponding output driver in a

high-impedance mode). Clearing a TRISA bit (= 0) will

make the corresponding PORTA pin an output (i.e., put

the contents of the output latch on the selected pin).

Each port has three registers for its operation. These

registers are:

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the port latch.

• TRIS register (data direction register)

The Data Latch register (LATA) is also memory

mapped. Read-modify-write operations on the LATA

register read and write the latched output value for

PORTA.

• PORT register (reads the levels on the pins of the

device)

• LAT register (output latch)

The Data Latch register (LAT) is useful for read-modify-

write operations on the value that the I/O pins are

driving.

The RA4 pin is multiplexed with the Timer0 module

clock input to become the RA4/T0CKI pin. The

RA4/T0CKI pin is a Schmitt Trigger input and an open-

drain output. All other RA port pins have TTL input

levels and full CMOS output drivers.

A simplified version of a generic I/O port and its

operation is shown in Figure 10-1.

The RA6 pin is only enabled as a general I/O pin in

ECIO and RCIO Oscillator modes.

FIGURE 10-1:

SIMPLIFIED BLOCK

DIAGRAM OF

The other PORTA pins are multiplexed with analog

inputs and the analog VREF+ and VREF- inputs. The

operation of each pin is selected by clearing/setting the

control bits in the ADCON1 register (A/D Control

Register 1).

PORT/LAT/TRIS

OPERATION

RD LAT

Note:

On a Power-on Reset, RA5 and RA3:RA0

are configured as analog inputs and read

as ‘0’. RA6 and RA4 are configured as

digital inputs.

TRIS

D

Q

WR LAT +

WR Port

CK

Data Latch

The TRISA register controls the direction of the RA pins

even when they are being used as analog inputs. The

user must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

Data Bus

RD Port

I/O pin

EXAMPLE 10-1:

INITIALIZING PORTA

CLRF

PORTA

; Initialize PORTA by

; clearing output

; data latches

CLRF

LATA

; Alternate method

; to clear output

; data latches

MOVLW 0Fh

; Configure A/D

MOVWF ADCON1 ; for digital inputs

MOVLW 0CFh

; Value used to

; initialize data

; direction

MOVWF TRISA

; Set RA<3:0> as inputs

; RA<5:4> as outputs

 2004 Microchip Technology Inc.

DS30491C-page 125

PIC18F6585/8585/6680/8680

FIGURE 10-2:

BLOCK DIAGRAM OF

RA3:RA0AND RA5PINS

FIGURE 10-3:

BLOCK DIAGRAM OF

RA4/T0CKI PIN

RD LATA

Data

Bus

Data

Bus

D

Q

D

Q

WR LATA

or

PORTA

WR LATA

or

PORTA

VDD

I/O pin⁽¹⁾

Q

Data Latch

CK

P

N

Data Latch

I/O pin⁽¹⁾

D

Q

N

D

Q

VSS

WR TRISA

RD TRISA

Schmitt

Trigger

Input

WR TRISA

RD TRISA

CK

Q

VSS

Analog

Q

CK

TRIS Latch

Input

Buffer

Mode

TTL

Input

Buffer

Q

D

Q

D

EN

RD PORTA

TMR0 Clock Input

To A/D Converter and LVD Modules

Note 1: I/O pins have protection diodes to VDD and VSS.

FIGURE 10-4:

BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O)

ECRA6 or RCRA6 Enable

Data Bus

RD LATA

D

Q

VDD

P

WR LATA or PORTA

CK

Data Latch

I/O pin⁽¹⁾

N

D

Q

WR TRISA

VSS

CK

Q

TRIS Latch

TTL

Input

Buffer

TRISA

RD

ECRA6 or RCRA6 Enable

Q

D

EN

RD PORTA

Note 1: I/O pins have protection diodes to VDD and VSS.

DS30491C-page 126

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 10-1: PORTA FUNCTIONS

Name

RA0/AN0

Bit#

Buffer

Function

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

TTL

Input/output or analog input.

RA1/AN1

Input/output or analog input.

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

Input/output or analog input or VREF-.

Input/output or analog input or VREF+.

ST/OD Input/output or external clock input for Timer0. Output is open-drain type.

RA5/AN4/LVDIN

TTL

Input/output or slave select input for synchronous serial port or analog

input, or Low-Voltage Detect input.

OSC2/CLKO/RA6

bit 6

TTL

OSC2 or clock output, or I/O pin.

Legend: TTL = TTL input, ST = Schmitt Trigger input

TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTA

LATA

—

RA6

RA5

RA4

RA3

RA2

RA1

RA0

-x0x 0000 -u0u 0000

-xxx xxxx -uuu uuuu

-111 1111 -111 1111

LATA Data Output Register

PORTA Data Direction Register

TRISA

ADCON1

—

VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000

Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’.

Shaded cells are not used by PORTA.

 2004 Microchip Technology Inc.

DS30491C-page 127

PIC18F6585/8585/6680/8680

A mismatch condition will continue to set flag bit, RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

10.2 PORTB, TRISB and LATB

Registers

PORTB is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISB bit (= 0)

will make the corresponding PORTB pin an output (i.e.,

put the contents of the output latch on the selected pin).

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

For PIC18FXX85 devices, RB3 can be configured by the

configuration bit, CCP2MX, as the alternate peripheral

pin for the CCP2 module. This is only available when the

device is configured in Microprocessor, Microprocessor

with Boot Block, or Extended Microcontroller Operating

modes.

The Data Latch register (LATB) is also memory mapped.

Read-modify-write operations on the LATB register read

and write the latched output value for PORTB.

EXAMPLE 10-2:

INITIALIZING PORTB

The RB5 pin is used as the LVP programming pin.

When the LVP configuration bit is programmed, this pin

loses the I/O function and becomes a programming test

function.

CLRF

PORTB

; Initialize PORTB by

; clearing output

; data latches

CLRF

LATB

; Alternate method

; to clear output

; data latches

Note:

When LVP is enabled, the weak pull-up on

RB5 is disabled.

MOVLW

MOVWF

0CFh

; Value used to

; initialize data

; direction

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

FIGURE 10-5:

BLOCK DIAGRAM OF

RB7:RB4 PINS

TRISB

VDD

RBPU⁽²⁾

Data Bus

Weak

P

Pull-up

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

performed by clearing bit RBPU (INTCON2<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

Data Latch

D

Q

WR LATB

or PORTB

I/O pin⁽¹⁾

CK

TRIS Latch

D

Q

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

WR TRISB

TTL

Input

Buffer

CK

ST

Buffer

Four of the PORTB pins (RB3:RB0) are the external

interrupt pins, INT3 through INT0. In order to use these

pins as external interrupts, the corresponding TRISB

bit must be set to ‘1’.

RD TRISB

RD LATB

Latch

The other four PORTB pins (RB7:RB4) have an

interrupt-on-change feature. Only pins configured as

inputs can cause this interrupt to occur (i.e., any

RB7:RB4 pin configured as an output is excluded from

the interrupt-on-change comparison). The input pins (of

RB7:RB4) are compared with the old value latched on

the last read of PORTB. The “mismatch” outputs of

RB7:RB4 are OR’ed together to generate the RB port

change interrupt with flag bit, RBIF (INTCON<0>).

Q

D

RD PORTB

Set RBIF

Q1

EN

Q

D

RD PORTB

Q3

From other

RB7:RB4 pins

EN

RB7:RB5 in Serial Programming Mode

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU bit (INTCON2<7>).

a) Any read or write of PORTB (except with the

MOVFF instruction). This will end the mismatch

condition.

b) Clear flag bit RBIF.

DS30491C-page 128

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 10-6:

BLOCK DIAGRAM OF RB2:RB0 PINS

VDD

RBPU⁽²⁾

Weak

P

Pull-up

Data Latch

Data Bus

WR Port

D

Q

I/O pin⁽¹⁾

CK

TRIS Latch

D

Q

TTL

Input

Buffer

WR TRIS

CK

RD TRIS

RD Port

Q

D

EN

INTx

RD Port

Schmitt Trigger

Buffer

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

FIGURE 10-7:

BLOCK DIAGRAM OF RB3 PIN

VDD

Weak

RBPU⁽²⁾

CCP2MX

P

Pull-up

CCP Output⁽³⁾

1

VDD

P

Enable⁽³⁾

CCP Output

0

Data Latch

Data Bus

I/O pin⁽¹⁾

D

Q

WR LATB or

WR PORTB

N

CK

VSS

TRIS Latch

D

TTL

WR TRISB

Input

CK

Q

Buffer

RD TRISB

RD LATB

D

Q

RD PORTB

EN

RD PORTB

CCP2 or INT3

Schmitt Trigger

Buffer

CCP2MX = 0

Note 1: I/O pin has diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).

3: For PIC18FXX85 parts, the CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration

register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.

 2004 Microchip Technology Inc.

DS30491C-page 129

PIC18F6585/8585/6680/8680

TABLE 10-3: PORTB FUNCTIONS

Name

RB0/INT0

Bit#

Buffer

Function

bit 0

TTL/ST⁽¹⁾Input/output pin or external interrupt input 0. Internal software

programmable weak pull-up.

RB1/INT1

bit 1

bit 2

bit 3

TTL/ST⁽¹⁾Input/output pin or external interrupt input 1. Internal software

programmable weak pull-up.

TTL/ST⁽¹⁾Input/output pin or external interrupt input 2. Internal software

programmable weak pull-up.

TTL/ST⁽⁴⁾Input/output pin or external interrupt input 3. Capture 2 input/

Compare 2 output/PWM output (when CCP2MX configuration bit is

enabled, all PIC18FXX85 operating modes except Microcontroller

mode). Internal software programmable weak pull-up.

RB2/INT2

RB3/INT3/CCP2⁽³⁾

RB4/KBI0

bit 4

bit 5

bit 6

bit 7

TTL

Input/output pin (with interrupt-on-change). Internal software

programmable weak pull-up.

RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

TTL/ST⁽²⁾Input/output pin (with interrupt-on-change). Internal software

programmable weak pull-up. Low-voltage ICSP enable pin.

TTL/ST⁽²⁾Input/output pin (with interrupt-on-change). Internal software

programmable weak pull-up. Serial programming clock.

TTL/ST⁽²⁾Input/output pin (with interrupt-on-change). Internal software

programmable weak pull-up. Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: RC1 is the alternate assignment for CCP2 when CCP2MX is not set (all operating modes except

Microcontroller mode).

4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.

TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTB

LATB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

0000 0000 0000 0000

LATB Data Output Register

TRISB

INTCON

PORTB Data Direction Register

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF INT0IF

RBIF

INTCON2

INTCON3

Legend:

RBPU

INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP

INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF

RBIP

1111 1111 1111 1111

1100 0000 1100 0000

INT2IP

INT1IF

x= unknown, u= unchanged. Shaded cells are not used by PORTB.

DS30491C-page 130

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register

without concern due to peripheral overrides.

10.3 PORTC, TRISC and LATC

Registers

PORTC is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISC. Setting a

TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISC bit (= 0)

will make the corresponding PORTC pin an output (i.e.,

put the contents of the output latch on the selected pin).

RC1 is normally configured by configuration bit,

CCP2MX, as the default peripheral pin of the CCP2

module (default/erased state, CCP2MX = 1).

EXAMPLE 10-3:

INITIALIZING PORTC

CLRF

PORTC

; Initialize PORTC by

; clearing output

; data latches

The Data Latch register (LATC) is also memory mapped.

Read-modify-write operations on the LATC register read

and write the latched output value for PORTC.

CLRF

LATC

; Alternate method

; to clear output

; data latches

PORTC is multiplexed with several peripheral functions

(Table 10-5). PORTC pins have Schmitt Trigger input

buffers.

MOVLW

MOVWF

0CFh

; Value used to

; initialize data

; direction

; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

TRISC

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an

output, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the corre-

sponding peripheral section for the correct TRIS bit

settings.

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

FIGURE 10-8:

PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

PORTC/Peripheral Out Select

Peripheral Data Out

VDD

P

0

1

RD LATC

Data Bus

D

Q

(1)

I/O pin

WR LATC or

WR PORTC

CK

Data Latch

TRIS OVERRIDE

N

D

Q

Override

Peripheral

TRIS

Override

Logic

VSS

WR TRISC

CK

RC0

Yes

Timer1 Osc for

Timer1/Timer3

TRIS Latch

RC1

Yes

Timer1 Osc for

Timer1/Timer3,

CCP2 I/O

RD TRISC

Schmitt

Trigger

Peripheral Output

RC2

RC3

Yes

CCP1 I/O

(2)

Enable

2

Q

D

SPI/I C

Master Clock

EN

2

RC4

RC5

RC6

Yes

I C Data Out

RD PORTC

SPI Data Out

Peripheral Data In

USART Async

Xmit, Sync Clock

Note 1: I/O pins have diode protection to VDD and VSS.

2: Peripheral output enable is only active if peripheral select is active.

RC7

Yes

USART Sync

Data Out

 2004 Microchip Technology Inc.

DS30491C-page 131

PIC18F6585/8585/6680/8680

TABLE 10-5: PORTC FUNCTIONS

Name

Bit# Buffer Type

Function

RC0/T1OSO/T13CKI bit 0

ST

Input/output port pin, Timer1 oscillator output or Timer1/Timer3

clock input.

RC1/T1OSI/CCP2⁽¹⁾

bit 1

ST

Input/output port pin, Timer1 oscillator input or Capture 2 input/

Compare 2 output/PWM output (when CCP2MX configuration bit is

disabled).

RC2/CCP1/P1A

RC3/SCK/SCL

bit 2

bit 3

ST

Input/output port pin or Capture 1 input/Compare 1 output/

PWM1 output.

RC3 can also be the synchronous serial clock for both SPI and I²C

modes.

RC4/SDI/SDA

RC5/SDO

bit 4

bit 5

bit 6

ST

RC4 can also be the SPI data in (SPI mode) or data I/O (I²C mode).

Input/output port pin or synchronous serial port data output.

RC6/TX/CK

Input/output port pin, addressable USART asynchronous transmit or

addressable USART synchronous clock.

RC7/RX/DT

bit 7

ST

Input/output port pin, addressable USART asynchronous receive or

addressable USART synchronous data.

Legend: ST = Schmitt Trigger input

Note 1: RB3 is the alternate assignment for CCP2 when CCP2MX is set.

TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTC

LATC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

LATC Data Output Register

PORTC Data Direction Register

TRISC

Legend: x= unknown, u= unchanged

DS30491C-page 132

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 10-9:

PORTD BLOCK DIAGRAM

IN I/O PORT MODE

10.4 PORTD, TRISD and LATD

Registers

PORTD is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISD. Setting a

TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISD bit (= 0)

will make the corresponding PORTD pin an output (i.e.,

put the contents of the output latch on the selected pin).

RD LATD

Data

Bus

D

Q

WR LATD

or

PORTD

I/O pin⁽¹⁾

CK

Data Latch

The Data Latch register (LATD) is also memory mapped.

Read-modify-write operations on the LATD register read

and write the latched output value for PORTD.

D

Q

Schmitt

Trigger

Input

WR TRISD

RD TRISD

CK

TRIS Latch

PORTD is an 8-bit port with Schmitt Trigger input

buffers. Each pin is individually configurable as an input

or output.

Buffer

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

On PIC18F8X8X devices, PORTD is multiplexed with

the system bus as the external memory interface; I/O

port functions are only available when the system bus

is disabled by setting the EBDIS bit in the MEMCOM

register (MEMCON<7>). When operating as the exter-

nal memory interface, PORTD is the low-order byte of

the multiplexed address/data bus (AD7:AD0).

Q

D

EN

RD PORTD

Note 1: I/O pins have diode protection to VDD and VSS.

PORTD can also be configured as an 8-bit wide micro-

processor port (Parallel Slave Port) by setting control

bit, PSPMODE (TRISE<4>). In this mode, the input

buffers are TTL. See Section 10.10 “Parallel Slave

Port (PSP)” for additional information.

EXAMPLE 10-4:

INITIALIZING PORTD

CLRF

PORTD

; Initialize PORTD by

; clearing output

; data latches

CLRF

LATD

; Alternate method

; to clear output

; data latches

MOVLW 0CFh

MOVWF TRISD

; Value used to

; initialize data

; direction

; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

 2004 Microchip Technology Inc.

DS30491C-page 133

PIC18F6585/8585/6680/8680

FIGURE 10-10:

PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE (PIC18F8X8X ONLY)

Q

D

EN

RD PORTD

RD LATD

Data Bus

Port

D

Q

0

1

Data

WR LATD

or PORTD

(1)

I/O pin

CK

Data Latch

D

Q

TTL

WR TRISD

RD TRISD

CK

Input

Buffer

TRIS Latch

Bus Enable

System Bus

Control

Data/TRIS Out

Drive Bus

Instruction Register

Instruction Read

Note 1: I/O pins have protection diodes to VDD and VSS.

DS30491C-page 134

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 10-7: PORTD FUNCTIONS

Name

Bit#

Buffer Type

Function

RD0/PSP0/AD0⁽²⁾

RD1/PSP1/AD1⁽²⁾

RD2/PSP2/AD2⁽²⁾

RD3/PSP3/AD3⁽²⁾

RD4/PSP4/AD4⁽²⁾

RD5/PSP5/AD5⁽²⁾

RD6/PSP6/AD6⁽²⁾

RD7/PSP7/AD7⁽²⁾

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

ST/TTL⁽¹⁾

Input/output port pin, Parallel Slave Port bit 0 or address/data bus bit 0.

Input/output port pin, Parallel Slave Port bit 1 or address/data bus bit 1.

Input/output port pin, Parallel Slave Port bit 2 or address/data bus bit 2.

Input/output port pin, Parallel Slave Port bit 3 or address/data bus bit 3.

Input/output port pin, Parallel Slave Port bit 4 or address/data bus bit 4.

Input/output port pin, Parallel Slave Port bit 5 or address/data bus bit 5.

Input/output port pin, Parallel Slave Port bit 6 or address/data bus bit 6.

Input/output port pin, Parallel Slave Port bit 7 or address/data bus bit 7.

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave

Port mode.

2: Available in PIC18F8X8X devices only.

TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

PORTD

LATD

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

0000 ---- 0000 ----

LATD Data Output Register

PORTD Data Direction Register

TRISD

PSPCON

IBF

OBF

—

IBOV PSPMODE

WAIT1 WAIT0

—

MEMCON EBDIS

WM1

WM0 0-00 --00 0-00 --00

Legend: x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.

 2004 Microchip Technology Inc.

DS30491C-page 135

PIC18F6585/8585/6680/8680

Pin RE7 can be configured as the alternate peripheral

10.5 PORTE, TRISE and LATE

Registers

pin for the CCP2 module when the device is operating

in Microcontroller mode. This is done by clearing the

configuration bit, CCP2MX, in configuration register,

CONFIG3H (CONFIG3H<0>).

PORTE is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISE. Setting a

TRISE bit (= 1) will make the corresponding PORTE

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISE bit (= 0)

will make the corresponding PORTE pin an output (i.e.,

put the contents of the output latch on the selected pin).

Note:

For PIC18F8X8X (80-pin) devices operat-

ing in other than Microcontroller mode,

PORTE defaults to the system bus on

Power-on Reset.

Read-modify-write operations on the LATE register

read and write the latched output value for PORTE.

EXAMPLE 10-5:

INITIALIZING PORTE

PORTE is an 8-bit port with Schmitt Trigger input

buffers. Each pin is individually configurable as an input

or output. PORTE is multiplexed with the Enhanced

CCP module (Table 10-9).

CLRF

PORTE

LATE

03h

; Initialize PORTE by

; clearing output

; data latches

; Alternate method

; to clear output

; data latches

; Value used to

;initializedata

; direction

CLRF

On PIC18F8X8X devices, PORTE is also multiplexed

with the system bus as the external memory interface;

the I/O bus is available only when the system bus is

disabled by setting the EBDIS bit in the MEMCON

register (MEMCON<7>). If the device is configured in

Microprocessor or Extended Microcontroller mode, then

the PORTE<7:0> becomes the high byte of the address/

data bus for the external program memory interface. In

Microcontroller mode, the PORTE<2:0> pins become the

control inputs for the Parallel Slave Port when bit

PSPMODE (PSPCON<4>) is set. (Refer to

Section 4.1.1 “PIC18F8X8X Program Memory

Modes” for more information on program memory

modes.)

MOVLW

MOVWF

TRISE

; Set RE1:RE0 as inputs

; RE7:RE2 as outputs

When the Parallel Slave Port is active, three PORTE

pins (RE0/RD/AD8, RE1/WR/AD9 and RE2/CS/AD10)

function as its control inputs. This automatically occurs

when the PSPMODE bit (PSPCON<4>) is set. Users

must also make certain that bits TRISE<2:0> are set to

configure the pins as digital inputs and the ADCON1

register is configured for digital I/O. The PORTE PSP

control functions are summarized in Table 10-9.

DS30491C-page 136

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 10-11:

PORTE BLOCK DIAGRAM IN I/O MODE

Peripheral Out Select

Peripheral Data Out

VDD

P

0

1

RD LATE

Data Bus

WR LATE

or WR PORTE

D

Q

(1)

I/O pin

CK

Data Latch

N

D

Q

TRIS OVERRIDE

VSS

WR TRISE

TRIS

Override

CK

Pin Override

Peripheral

TRIS Latch

RE0

RE1

RE2

RE3

RE4

RE5

RE6

RE7

Yes

External Bus

RD TRISE

Schmitt

Trigger

Peripheral Enable

Q

D

EN

RD PORTE

Peripheral Data In

Note 1: I/O pins have diode protection to VDD and VSS.

FIGURE 10-12:

PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE (PIC18F8X8X ONLY)

Q

D

EN

RD PORTE

RD LATE

Data Bus

Port

D

Q

0

1

Data

WR LATE

or PORTE

(1)

I/O pin

CK

Data Latch

D

Q

TTL

WR TRISE

CK

Input

Buffer

TRIS Latch

RD TRISE

Bus Enable

Data/TRIS Out

Drive Bus

System Bus

Control

Instruction Register

Instruction Read

Note 1: I/O pins have protection diodes to VDD and VSS.

 2004 Microchip Technology Inc.

DS30491C-page 137

PIC18F6585/8585/6680/8680

TABLE 10-9:

Name

PORTE FUNCTIONS

Bit#

Buffer Type

Function

RE0/RD/AD8⁽²⁾

RE1/WR/AD9⁽²⁾

RE2/CS/AD10⁽²⁾

bit 0

ST/TTL⁽¹⁾

Input/output port pin, read control for Parallel Slave Port or

address/data bit 8.

For RD (PSP Control mode):

1= Not a read operation

0= Read operation, reads PORTD register (if chip selected)

bit 1

bit 2

ST/TTL⁽¹⁾

Input/output port pin, write control for Parallel Slave Port or

address/data bit 9.

For WR (PSP Control mode):

1= Not a write operation

0= Write operation, writes PORTD register (if chip selected)

Input/output port pin, chip select control for Parallel Slave Port or

address/data bit 10.

For CS (PSP Control mode):

1= Device is not selected

0= Device is selected

RE3/AD11⁽²⁾

RE4/AD12⁽²⁾

RE5/AD13/⁽²⁾P1C⁽³⁾bit 5

RE6/AD14/⁽²⁾P1B⁽³⁾

RE7/CCP2/AD15⁽²⁾

bit 3

bit 4

ST/TTL⁽¹⁾

Input/output port pin or address/data bit 11.

Input/output port pin or address/data bit 12.

Input/output port pin, address/data bit 13 or ECCP1 PWM output C.

Input/output port pin, address/data bit 13 or ECCP1 PWM output B.

bit 6

bit 7

Input/output port pin, Capture 2 input/Compare 2 output/PWM output

(PIC18F8X20 devices in Microcontroller mode only) or

address/data bit 15.

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O or CCP mode, and TTL buffers when in System Bus or PSP

Control mode.

2: Available in PIC18F8X8X devices only.

3: On PIC18F8X8X devices, these pins may be moved to RHY or RH6 by changing the ECCPMX

configuration bit.

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Value on

Value on:

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

1111 1111

xxxx xxxx

0-00 --00

0000 ----

1111 1111

uuuu uuuu

0000 --00

0000 ----

TRISE

PORTE Data Direction Control Register

PORTE

LATE

Read PORTE pin/Write PORTE Data Latch

Read PORTE Data Latch/Write PORTE Data Latch

MEMCON EBDIS

PSPCON IBF

—

WAIT1

WAIT0

—

WM1

—

WM0

—

OBF

IBOV PSPMODE

Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTE.

DS30491C-page 138

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

EXAMPLE 10-6:

INITIALIZING PORTF

10.6 PORTF, LATF and TRISF Registers

CLRF

PORTF

; Initialize PORTF by

; clearing output

; data latches

; Alternate method

; to clear output

; data latches

PORTF is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISF. Setting a

TRISF bit (= 1) will make the corresponding PORTF pin

an input (i.e., put the corresponding output driver in a

high-impedance mode). Clearing a TRISF bit (= 0) will

make the corresponding PORTF pin an output (i.e., put

the contents of the output latch on the selected pin).

CLRF

LATF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

07h

CMCON

0Fh

ADCON1

0CFh

;

; Turn off comparators

;

; Set PORTF as digital I/O

; Value used to

; initialize data

; direction

; Set RF3:RF0 as inputs

; RF5:RF4 as outputs

; RF7:RF6 as inputs

Read-modify-write operations on the LATF register

read and write the latched output value for PORTF.

PORTF is multiplexed with several analog peripheral

functions, including the A/D converter inputs and

comparator inputs, outputs, and voltage reference.

MOVWF

TRISF

Note 1: On a Power-on Reset, the RF6:RF0 pins

are configured as inputs and read as ‘0’.

2: To configure PORTF as digital I/O, turn off

comparators and set ADCON1 value.

FIGURE 10-13:

PORTF RF1/AN6/C2OUT AND RF2/AN7/C1OUT PINS BLOCK DIAGRAM

Port/Comparator Select

Comparator Data Out

VDD

P

0

1

RD LATF

Q

Data Bus

D

WR LATF or

I/O pin

WR PORTF

Q

CK

Data Latch

N

D

Q

VSS

WR TRISF

CK

Analog

Input

Mode

TRIS Latch

Schmitt

Trigger

RD TRISF

Q

D

EN

RD PORTF

To A/D Converter

Note 1: I/O pins have diode protection to VDD and VSS.

 2004 Microchip Technology Inc.

DS30491C-page 139

PIC18F6585/8585/6680/8680

FIGURE 10-14:

RF6:RF3 AND RF0 PINS

BLOCK DIAGRAM

FIGURE 10-15:

RF7 PIN BLOCK

DIAGRAM

RD LATF

Data

Bus

Data

Bus

D

Q

D

Q

WR LATF or

WR PORTF

I/O pin

WR LATF

or

WR PORTF

VDD

CK

Data Latch

CK

Q

P

Data Latch

D

Q

N

I/O pin

Schmitt

Trigger

Input

D

Q

WR TRISF

CK

TRIS Latch

Buffer

WR TRISF

RD TRISF

VSS

Analog

CK

TRIS Latch

Q

TTL

Input

Buffer

Input

Mode

RD TRISF

ST

Input

Q

D

Buffer

Q

D

EN

RD PORTF

SS Input

EN

RD PORTF

To A/D Converter or Comparator Input

Note:

I/O pins have diode protection to VDD and VSS.

Note 1: I/O pins have diode protection to VDD and VSS.

DS30491C-page 140

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 10-11: PORTF FUNCTIONS

Name

RF0/AN5

Bit#

Buffer Type

Function

bit 0

ST

Input/output port pin or analog input.

RF1/AN6/C2OUT bit 1

RF2/AN7/C1OUT bit 2

Input/output port pin, analog input or comparator 2 output.

Input/output port pin, analog input or comparator 1 output.

Input/output port pin, analog input or comparator 2 input (+).

Input/output port pin, analog input or comparator 2 input (-).

RF3/AN8/C2IN+

RF4/AN9/C2IN-

bit 3

bit 4

bit 5

RF5/AN10/

C1IN+/CVREF

Input/output port pin, analog input, comparator 1 input (+) or

comparator reference output.

RF6/AN11/C1IN-

RF7/SS

bit 6

bit 7

ST

Input/output port pin, analog input or comparator 1 input (-).

ST/TTL

Input/output port pin or slave select pin for synchronous serial port.

Legend: ST = Schmitt Trigger input, TTL = TTL input

TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF

Value on

all other

Resets

Value on:

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TRISF

PORTF Data Direction Control Register

Read PORTF pin/Write PORTF Data Latch

Read PORTF Data Latch/Write PORTF Data Latch

1111 1111

xxxx xxxx

0000 0000

1111 1111

uuuu uuuu

--00 0000

0000 0000

PORTF

LATF

ADCON1

CMCON

—

VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000

Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTF.

 2004 Microchip Technology Inc.

DS30491C-page 141

PIC18F6585/8585/6680/8680

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register

without concern due to peripheral overrides.

10.7 PORTG, TRISG and LATG

Registers

PORTG is a 6-bit wide port with 5 bidirectional pins and

1 unidirectional pin. The corresponding data direction

register is TRISG. Setting a TRISG bit (= 1) will make

the corresponding PORTG pin an input (i.e., put the

corresponding output driver in a high-impedance

mode). Clearing a TRISG bit (= 0) will make the corre-

sponding PORTG pin an output (i.e., put the contents

of the output latch on the selected pin).

EXAMPLE 10-7:

INITIALIZING PORT

CLRF

PORTG

; Initialize PORTG by

; clearing output

; data latches

; Alternate method

; to clear output

; data latches

; Value used to

; initialize data

; direction

CLRF

LATG

MOVLW 04h

The Data Latch register (LATG) is also memory mapped.

Read-modify-write operations on the LATG register read

and write the latched output value for PORTG.

MOVWF TRISG

; Set RG1:RG0 as outputs

; RG2 as input

; RG4:RG3 as inputs

Pins RG0-RG2 on PORTG are multiplexed with the CAN

peripheral. Refer to Section 23.0 “ECAN Module” for

proper settings of TRISG when CAN is enabled. RG5 is

multiplexed with MCLR/VPP. Refer to Register 24-5 for

more information.

Note 1: On a Power-on Reset, RG5 is enabled as

a digital input only if Master Clear

functionality is disabled (MCLRE = 0).

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTG pin. Some

peripherals override the TRIS bit to make a pin an output,

while other peripherals override the TRIS bit to make a

pin an input. The user should refer to the corresponding

peripheral section for the correct TRIS bit settings.

2: If the device Master Clear is disabled,

verify that either of the following is done to

ensure proper entry into ICSP mode:

a) disable Low-Voltage Programming

(CONFIG4L<2> = 0); or

b) make certain that RB5/KBI1/PGM is

held low during entry into ICSP.

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

FIGURE 10-16:

RG0/CANTX1 PIN BLOCK DIAGRAM

OPMODE2:OPMODE0 = 000

TXD

ENDRHI

VDD

0

RD LATG

1

Data Bus

D

Q

P

WR PORTG or

WR LATG

CK

Q

Data Latch

I/O pin

D

Q

N

WR TRISG

RD TRISG

CK

Q

TRIS Latch

VSS

OPMODE2:OPMODE0 = 000

Schmitt

Trigger

Q

D

EN

RD PORTG

Note: I/O pins have diode protection to VDD and VSS.

DS30491C-page 142

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 10-17:

RG1/CANTX2 PIN BLOCK DIAGRAM

TX1SRC

OPMODE2:OPMODE0 = 000

TX2EN

TXD

0

1

CANCLK

ENDRHI

0

1

VDD

P

RD LATG

Data Bus

D

Q

WR PORTG or

WR LATG

CK

Q

Data Latch

I/O pin

D

Q

N

WR TRISG

RD TRISG

CK

Q

TRIS Latch

VSS

OPMODE2:OPMODE0 = 000

Schmitt

Trigger

Q

D

EN

RD PORTG

Note: I/O pins have diode protection to VDD and VSS.

FIGURE 10-18:

RG2/CANRX PIN BLOCK

DIAGRAM

FIGURE 10-19:

RG3 PIN BLOCK

DIAGRAM

RD LATG

Data Bus

D

Q

D

Q

I/O pin

WR LATG

or

WR PORTG

WR LATG

or

WR PORTG

CK

Data Latch

D

Q

D

Q

Schmitt

Trigger

Input

Schmitt

Trigger

Input

WR TRISG

CK

Buffer

TRIS Latch

RD TRISG

Q

D

Q

D

EN

RD PORTG

CANRX

RD PORTG

Note: I/O pins have diode protection to VDD and VSS.

 2004 Microchip Technology Inc.

DS30491C-page 143

PIC18F6585/8585/6680/8680

FIGURE 10-20:

RG4/P1D PIN BLOCK DIAGRAM

CCP1 P1D Enable

P1D Out

RD LATG

1

0

Data Bus

D

Q

I/O pin

WR LATG

or

WR PORTG

CK

Data Latch

Auto-Shutdown

D

Q

Schmitt

Trigger

Input

WR TRISG

CK

TRIS Latch

Buffer

RD TRISG

Q

D

EN

RD PORTG

Note: I/O pins have diode protection to VDD and VSS.

FIGURE 10-21:

RG5/MCLR/VPP PIN BLOCK DIAGRAM

MCLRE

Data Bus

RD TRISA

RG5/MCLR/VPP

Schmitt

Trigger

RD LATA

Latch

Q

D

EN

RD PORTA

High-Voltage Detect

HV

Internal MCLR

Filter

Low-Level

MCLR Detect

DS30491C-page 144

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 10-13: PORTG FUNCTIONS

Name

Bit#

Buffer Type

Function

RG0/CANTX1

RG1/CANTX2

bit 0

bit 1

ST

Input/output port pin or CAN bus transmit output.

Input/output port pin, CAN bus complimentary transmit output or CAN

bus bit time clock.

RG2/CANRX

RG3

bit 2

bit 3

bit 4

bit 5

ST

Input/output port pin or CAN bus receive.

Input/output port pin.

RG4/P1D

Input/output port pin or ECCP1 PWM output D.

RG5/MCLR/VPP

Master Clear input or programming voltage input (if MCLR is enabled).

Input only port pin or programming voltage input (if MCLR is

disabled).

Legend: ST = Schmitt Trigger input

TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTG

LATG

—

RG5⁽¹⁾Read PORTF pin/Write PORTF Data Latch

--0x xxxx --0u uuuu

---x xxxx ---u uuuu

---1 1111 ---1 1111

—

LATG Data Output Register

TRISG

Data Direction Control Register for PORTG

Legend: x= unknown, u= unchanged

Note 1: RG5 is available as an input only when MCLR is disabled.

 2004 Microchip Technology Inc.

DS30491C-page 145

PIC18F6585/8585/6680/8680

FIGURE 10-22:

RH3:RH0 PINS BLOCK

DIAGRAM IN I/O MODE

10.8 PORTH, LATH and TRISH

Registers

Note:

PORTH is available only on PIC18F8X8X

devices.

RD LATH

Data

Bus

PORTH is an 8-bit wide, bidirectional I/O port. The cor-

responding data direction register is TRISH. Setting a

TRISH bit (= 1) will make the corresponding PORTH

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISH bit (= 0)

will make the corresponding PORTH pin an output (i.e.,

put the contents of the output latch on the selected pin).

D

Q

I/O pin⁽¹⁾

WR LATH

or

PORTH

CK

Data Latch

D

Q

Read-modify-write operations on the LATH register

read and write the latched output value for PORTH.

Schmitt

Trigger

Input

WR TRISH

RD TRISH

CK

TRIS Latch

Buffer

Pins RH7:RH4 are multiplexed with analog inputs

AN15:AN12. Pins RH3:RH0 are multiplexed with the

system bus as the external memory interface; they are

the high-order address bits, A19:A16. By default, pins

RH7:RH4 are enabled as A/D inputs and pins

RH3:RH0 are enabled as the system address bus.

Register ADCON1 configures RH7:RH4 as I/O or A/D

inputs. Register MEMCON configures RH3:RH0 as I/O

or system bus pins.

Q

D

EN

RD PORTH

Pins RH7 and RH6 can be configured as the alternate

peripheral pins for CCP1 PWM output P1B and P1C,

respectively. This is done by clearing the configuration

bit ECCPMX, in configuration register CONFIG3H

(CONFIG3H<1>).

Note 1: I/O pins have diode protection to VDD and VSS.

FIGURE 10-23:

RH7:RH4 PINS BLOCK

DIAGRAM IN I/O MODE

Note 1: On Power-on Reset, PORTH pins

RH7:RH4 default to A/D inputs and read

as ‘0’.

RD LATH

Data

Bus

2: On Power-on Reset, PORTH pins

D

Q

RH3:RH0 default to system bus signals.

I/O pin⁽¹⁾

WR LATH

or

PORTH

CK

Data Latch

EXAMPLE 10-8:

INITIALIZING PORTH

CLRF

PORTH

; Initialize PORTH by

; clearing output

; data latches

; Alternate method

; to clear output

; data latches

;

D

Q

Schmitt

Trigger

Input

WR TRISH

CLRF

LATH

CK

TRIS Latch

Buffer

MOVLW

MOVWF

MOVLW

0Fh

ADCON1

0CFh

RD TRISH

;

; Value used to

; initialize data

; direction

Q

D

MOVWF

TRISH

; Set RH3:RH0 as inputs

; RH5:RH4 as outputs

; RH7:RH6 as inputs

EN

RD PORTH

To A/D Converter

Note 1: I/O pins have diode protection to VDD and VSS.

DS30491C-page 146

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 10-24:

RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE

Q

D

EN

RD PORTH

RD LATD

Data Bus

Port

D

Q

0

1

Data

I/O pin⁽¹⁾

WR LATH

or

PORTH

CK

Data Latch

D

Q

WR TRISH

RD TRISH

TTL

Input

Buffer

CK

TRIS Latch

External Enable

Address Out

System Bus

Control

Drive System

To Instruction Register

Instruction Read

Note 1: I/O pins have diode protection to VDD and VSS.

 2004 Microchip Technology Inc.

DS30491C-page 147

PIC18F6585/8585/6680/8680

TABLE 10-15: PORTH FUNCTIONS

Name

RH0/A16

Bit#

Buffer Type

Function

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

ST/TTL⁽¹⁾

ST

Input/output port pin or address bit 16 for external memory interface.

Input/output port pin or address bit 17 for external memory interface.

Input/output port pin or address bit 18 for external memory interface.

Input/output port pin or address bit 19 for external memory interface.

Input/output port pin or analog input channel 12.

RH1/A17

RH2/A18

RH3/A19

RH4/AN12

RH5/AN13

ST

Input/output port pin or analog input channel 13.

RH6/AN14/P1C⁽²⁾

RH7/AN15/P1B⁽²⁾

ST

Input/output port pin or analog input channel 14.

ST

Input/output port pin or analog input channel 15.

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave

Port mode.

2: Alternate pin assignment when ECCPMX configuration bit is cleared.

TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH

Value on

Value on:

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

1111 1111

xxxx xxxx

--00 0000

0-00 --00

1111 1111

uuuu uuuu

--00 0000

0-00 --00

TRISH

PORTH Data Direction Control Register

Read PORTH pin/Write PORTH Data Latch

Read PORTH Data Latch/Write PORTH Data Latch

PORTH

LATH

ADCON1

MEMCON⁽¹⁾EBDIS

—

VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

WAIT1 WAIT0 WM1 WM0

—

Legend: x= unknown, u= unchanged, – = unimplemented. Shaded cells are not used by PORTH.

Note 1: This register is held in Reset in Microcontroller mode.

DS30491C-page 148

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 10-25:

PORTJ BLOCK DIAGRAM

IN I/O MODE

10.9 PORTJ, TRISJ and LATJ

Registers

Note:

PORTJ is available only on PIC18F8X8X

devices.

RD LATJ

Data

Bus

PORTJ is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISJ. Setting a

TRISJ bit (= 1) will make the corresponding PORTJ pin

an input (i.e., put the corresponding output driver in a

high-impedance mode). Clearing a TRISJ bit (= 0) will

make the corresponding PORTJ pin an output (i.e., put

the contents of the output latch on the selected pin).

D

Q

I/O pin⁽¹⁾

WR LATJ

or

PORTJ

CK

Data Latch

D

Q

Schmitt

Trigger

Input

The Data Latch register (LATJ) is also memory

mapped. Read-modify-write operations on the LATJ

register read and write the latched output value for

PORTJ.

WR TRISJ

CK

TRIS Latch

Buffer

RD TRISJ

PORTJ is multiplexed with the system bus as the

external memory interface; I/O port functions are only

available when the system bus is disabled. When

operating as the external memory interface, PORTJ

provides the control signal to external memory devices.

The RJ5 pin is not multiplexed with any system bus

functions.

Q

D

EN

RD PORTJ

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTJ pin. Some

peripherals override the TRIS bit to make a pin an

output, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the

corresponding peripheral section for the correct TRIS

bit settings.

Note 1: I/O pins have diode protection to VDD and VSS.

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register

without concern due to peripheral overrides.

EXAMPLE 10-9:

INITIALIZING PORTJ

CLRF

PORTJ

; Initialize PORTG by

; clearing output

; data latches

CLRF

LATJ

; Alternate method

; to clear output

; data latches

MOVLW 0CFh

MOVWF TRISJ

; Value used to

; initializedata

; direction

; Set RJ3:RJ0 as inputs

; RJ5:RJ4 as output

; RJ7:RJ6 as inputs

 2004 Microchip Technology Inc.

DS30491C-page 149

PIC18F6585/8585/6680/8680

FIGURE 10-26:

RJ5:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE

Q

D

EN

RD PORTJ

RD LATJ

Data Bus

Port

D

Q

0

1

Data

I/O pin⁽¹⁾

WR LATJ

or

PORTJ

CK

Data Latch

D

Q

WR TRISJ

RD TRISJ

CK

TRIS Latch

Control Out

System Bus

Control

External Enable

Drive System

Note 1: I/O pins have diode protection to VDD and VSS.

FIGURE 10-27:

RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE

Q

D

EN

RD PORTJ

RD LATJ

Data Bus

Port

D

Q

0

1

Data

I/O pin⁽¹⁾

WR LATJ

or

PORTJ

CK

Data Latch

D

Q

WR TRISJ

CK

TRIS Latch

RD TRISJ

UB/LB Out

WM = 01

System Bus

Control

Drive System

Note 1: I/O pins have diode protection to VDD and VSS.

DS30491C-page 150

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 10-17: PORTJ FUNCTIONS

Name

RJ0/ALE

Bit#

Buffer Type

Function

bit 0

ST

Input/output port pin or address latch enable control for external

memory interface.

RJ1/OE

bit 1

bit 2

bit 3

bit 4

ST

Input/output port pin or output enable control for external memory

interface.

RJ2/WRL

RJ3/WRH

RJ4/BA0

Input/output port pin or write low byte control for external memory

interface.

Input/output port pin or write high byte control for external memory

interface.

Input/output port pin or byte address 0 control for external memory

interface.

RJ5/CE

RJ6/LB

bit 5

bit 6

ST

Input/output port pin or external memory chip enable.

Input/output port pin or lower byte select control for external

memory interface.

RJ7/UB

bit 7

ST

Input/output port pin or upper byte select control for external

memory interface.

Legend: ST = Schmitt Trigger input

TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTJ

LATJ

Read PORTJ pin/Write PORTJ Data Latch

LATJ Data Output Register

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

TRISJ

Data Direction Control Register for PORTJ

Legend: x= unknown, u= unchanged

 2004 Microchip Technology Inc.

DS30491C-page 151

PIC18F6585/8585/6680/8680

FIGURE 10-28:

PORTD AND PORTE

BLOCK DIAGRAM

(PARALLEL SLAVE PORT)

10.10 Parallel Slave Port (PSP)

PORTD also operates as an 8-bit wide Parallel Slave

Port, or microprocessor port, when control bit

PSPMODE (TRISE<4>) is set. It is asynchronously

readable and writable by the external world through RD

control input pin, RE0/RD/AD8 and WR control input

pin, RE1/WR/AD9.

Data Bus

D

Q

RDx

WR LATD

or

PORTD

CK

Data Latch

Note:

For PIC18F8X8X devices, the Parallel

Slave Port is available only in

Microcontroller mode.

TTL

Q

D

The PSP can directly interface to an 8-bit micro-

processor data bus. The external microprocessor can

read or write the PORTD latch as an 8-bit latch. Setting

bit PSPMODE enables port pin RE0/RD/AD8 to be the

RD input, RE1/WR/AD9 to be the WR input and

RE2/CS/AD10 to be the CS (chip select) input. For this

functionality, the corresponding data direction bits of

the TRISE register (TRISE<2:0>) must be configured

as inputs (set). The A/D port configuration bits

PCFG2:PCFG0 (ADCON1<2:0>) must be set, which

will configure pins RE2:RE0 as digital I/O.

RD PORTD

EN

TRIS Latch

RD LATD

One bit of PORTD

Set Interrupt Flag

PSPIF (PIR1<7>)

A write to the PSP occurs when both the CS and WR

lines are first detected low. A read from the PSP occurs

when both the CS and RD lines are first detected low.

The PORTE I/O pins become control inputs for

the microprocessor port when bit PSPMODE

(PSPCON<4>) is set. In this mode, the user must make

sure that the TRISE<2:0> bits are set (pins are config-

ured as digital inputs) and the ADCON1 is configured

for digital I/O. In this mode, the input buffers are TTL.

Read

RD

CS

TTL

Chip Select

TTL

Write

WR

TTL

Note: I/O pin has protection diodes to VDD and VSS.

DS30491C-page 152

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 10-1: PSPCON REGISTER

R-0

IBF

R-0

R/W-0

IBOV

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

OBF

PSPMODE

bit 7

bit 0

bit 7

bit 6

bit 5

IBF: Input Buffer Full Status bit

1= A data byte has been received and is waiting to be read by the CPU

0= No data byte has been received

OBF: Output Buffer Full Status bit

1= The output buffer still holds a previously written data byte

0= The output buffer has been read

IBOV: Input Buffer Overflow Detect bit

1= A write occurred when a previously input data byte has not been read

(must be cleared in software)

0= No overflow occurred

bit 4

PSPMODE: Parallel Slave Port Mode Select bit

1= Parallel Slave Port mode

0= General Purpose I/O mode

bit 3-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

FIGURE 10-29:

PARALLEL SLAVE PORT WRITE WAVEFORMS

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

CS

WR

RD

PORTD<7:0>

IBF

OBF

PSPIF

 2004 Microchip Technology Inc.

DS30491C-page 153

PIC18F6585/8585/6680/8680

FIGURE 10-30:

PARALLEL SLAVE PORT READ WAVEFORMS

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

CS

WR

RD

PORTD<7:0>

IBF

OBF

PSPIF

TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTD Port Data Latch when Written; Port pins when Read

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

LATD

LATD Data Output bits

TRISD

PORTD Data Direction bits

(1)

PORTE RE7/CCP2/ RE6/AD14/ RE5/AD13/

RE4/

RE3/ RE2/CS / RE1/WR / RE0/RD / xxxx xxxx uuuu uuuu

AD15

P1B

P1C

AD12

AD11

AD10

AD9

AD8

LATE

LATE Data Output bits

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

0000 ---- 0000 ----

0000 0000 0000 0000

TRISE

PORTE Data Direction bits

PSPCON

INTCON

IBF

OBF

IBOV

PSPMODE

INT0IE

—

GIE/

GIEH

PEIE/

GIEL

TMR0IF

RBIE

TMR0IF

INT0IF

RBIF

(1)

PIR1

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

SSPIF

SSPIE

SSPIP

CCP1IF

CCP1IE

CCP1IP

TMR2IF

TMR2IE

TMR2IP

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

TMR1IP 1111 1111 1111 1111

(1)

PIE1

IPR1

Legend:

x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.

Note 1: Enabled only in Microcontroller mode.

DS30491C-page 154

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

Figure 11-1 shows a simplified block diagram of the

Timer0 module in 8-bit mode and Figure 11-2 shows a

simplified block diagram of the Timer0 module in 16-bit

11.0 TIMER0 MODULE

The Timer0 module has the following features:

mode.

• Software selectable as an 8-bit or 16-bit timer/

counter

The T0CON register (Register 11-1) is a readable and

writable register that controls all the aspects of Timer0,

including the prescale selection.

• Readable and writable

• Dedicated 8-bit software programmable prescaler

• Clock source selectable to be external or internal

Note:

Timer0 is enabled on POR.

• Interrupt-on-overflow from 0FFh to 00h in 8-bit

mode and 0FFFFh to 0000h in 16-bit mode

• Edge select for external clock

REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER

R/W-1

TMR0ON

bit 7

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

T0PS2

R/W-1

T0PS1

R/W-1

T0PS0

T08BIT

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

TMR0ON: Timer0 On/Off Control bit

1= Enables Timer0

0= Stops Timer0

T08BIT: Timer0 8-bit/16-bit Control bit

1= Timer0 is configured as an 8-bit timer/counter

0= Timer0 is configured as a 16-bit timer/counter

T0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (CLKO)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Timer0 Prescaler Assignment bit

1= TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.

0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.

bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits

111= 1:256 prescale value

110= 1:128 prescale value

101= 1:64 prescale value

100= 1:32 prescale value

011= 1:16 prescale value

010= 1:8 prescale value

001= 1:4 prescale value

000= 1:2 prescale value

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 155

PIC18F6585/8585/6680/8680

FIGURE 11-1:

TIMER0 BLOCK DIAGRAM IN 8-BIT MODE

Data Bus

FOSC/4

0

1

8

0

Sync with

Internal

Clocks

TMR0

RA4/T0CKI pin

Programmable

Prescaler

1

(2 TCY delay)

T0SE

3

PSA

Set Interrupt

Flag bit TMR0IF

on Overflow

T0PS2, T0PS1, T0PS0

T0CS

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

FIGURE 11-2:

TIMER0 BLOCK DIAGRAM IN 16-BIT MODE

FOSC/4

0

Sync with

Internal

Clocks

Set Interrupt

Flag bit TMR0IF

on Overflow

TMR0

High Byte

1

TMR0L

Programmable

Prescaler

T0CKI pin

1

8

(2 TCY delay)

T0SE

3

Read TMR0L

Write TMR0L

T0PS2, T0PS1, T0PS0

T0CS

PSA

8

TMR0H

8

Data Bus<7:0>

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

DS30491C-page 156

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

11.2.1

SWITCHING PRESCALER

ASSIGNMENT

11.1 Timer0 Operation

Timer0 can operate as a timer or as a counter.

The prescaler assignment is fully under software

control (i.e., it can be changed “on-the-fly” during

program execution).

Timer mode is selected by clearing the T0CS bit. In

Timer mode, the Timer0 module will increment every

instruction cycle (without prescaler). If the TMR0 regis-

ter is written, the increment is inhibited for the following

two instruction cycles. The user can work around this

by writing an adjusted value to the TMR0 register.

11.3 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from 0FFh to 00h in 8-bit mode, or

0FFFFh to 0000h in 16-bit mode. This overflow sets the

TMR0IF bit. The interrupt can be masked by clearing

the TMR0IE bit. The TMR0IE bit must be cleared in

software by the Timer0 module Interrupt Service

Routine before re-enabling this interrupt. The TMR0

interrupt cannot awaken the processor from Sleep

since the timer is shut-off during Sleep.

Counter mode is selected by setting the T0CS bit. In

Counter mode, Timer0 will increment either on every

rising or falling edge of pin RA4/T0CKI. The increment-

ing edge is determined by the Timer0 Source Edge

Select bit (T0SE). Clearing the T0SE bit selects the

rising edge. Restrictions on the external clock input are

discussed below.

When an external clock input is used for Timer0, it must

meet certain requirements. The requirements ensure

the external clock can be synchronized with the internal

phase clock (TOSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

11.4 16-Bit Mode Timer Reads

and Writes

TMR0H is not the high byte of the timer/counter in

16-bit mode, but is actually a buffered version of the

high byte of Timer0 (refer to Figure 11-2). The high byte

of the Timer0 counter/timer is not directly readable nor

writable. TMR0H is updated with the contents of the

high byte of Timer0 during a read of TMR0L. This pro-

vides the ability to read all 16 bits of Timer0 without

having to verify that the read of the high and low byte

were valid due to a rollover between successive reads

of the high and low byte.

11.2 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module. The prescaler is not readable or

writable.

The PSA and T0PS2:T0PS0 bits determine the

prescaler assignment and prescale ratio.

Clearing bit PSA will assign the prescaler to the Timer0

module. When the prescaler is assigned to the Timer0

module, prescale values of 1:2, 1:4, ..., 1:256 are

selectable.

A write to the high byte of Timer0 must also take place

through the TMR0H buffer register. Timer0 high byte is

updated with the contents of TMR0H when a write

occurs to TMR0L. This allows all 16 bits of Timer0 to be

updated at once.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF TMR0, MOVWF

TMR0, BSF TMR0, x, ..., etc.) will clear the prescaler

count.

Note:

Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler

count but will not change the prescaler

assignment.

TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

Value on

all other

Resets

Value on

POR, BOR

Bit 1

Bit 0

TMR0L Timer0 Module Low Byte Register

TMR0H Timer0 Module High Byte Register

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u

T0CON

TRISA

TMR0ON

—

T08BIT

T0CS

T0SE

PSA

T0PS2 T0PS1 T0PS0 1111 1111 1111 1111

PORTA Data Direction Register

-111 1111 -111 1111

Legend: x= unknown, u= unchanged, – = unimplemented locations, read as ‘0’. Shaded cells are not used by

Timer0.

 2004 Microchip Technology Inc.

DS30491C-page 157

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 158

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

Figure 12-1 is a simplified block diagram of the Timer1

module.

12.0 TIMER1 MODULE

The Timer1 module timer/counter has the following

features:

Register 12-1 details the Timer1 Control register. This

register controls the operating mode of the Timer1

module and contains the Timer1 Oscillator Enable bit

(T1OSCEN). Timer1 can be enabled or disabled by

setting or clearing control bit, TMR1ON (T1CON<0>).

• 16-bit timer/counter

(two 8-bit registers; TMR1H and TMR1L)

• Readable and writable (both registers)

• Internal or external clock select

• Interrupt on overflow from 0FFFFh to 0000h

• Reset from CCP module special event trigger

REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0

RD16

U-0

—

R/W-0

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 0

bit 7

bit 6

RD16: 16-bit Read/Write Mode Enable bit

1= Enables register read/write of Timer1 in one 16-bit operation

0= Enables register read/write of Timer1 in two 8-bit operations

Unimplemented: Read as ‘0’

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11= 1:8 prescale value

10= 1:4 prescale value

01= 1:2 prescale value

00= 1:1 prescale value

bit 3

bit 2

T1OSCEN: Timer1 Oscillator Enable bit

1= Timer1 oscillator is enabled

0= Timer1 oscillator is shut-off

The oscillator inverter and feedback resistor are turned off to eliminate power drain.

T1SYNC: Timer1 External Clock Input Synchronization Select bit

When TMR1CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1

bit 0

TMR1CS: Timer1 Clock Source Select bit

1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)

0= Internal clock (FOSC/4)

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 159

PIC18F6585/8585/6680/8680

When TMR1CS = 0, Timer1 increments every instruc-

12.1 Timer1 Operation

tion cycle. When TMR1CS = 1, Timer1 increments on

every rising edge of the external clock input or the

Timer1 oscillator if enabled.

Timer1 can operate in one of these modes:

• As a timer

• As a synchronous counter

• As an asynchronous counter

When the Timer1 oscillator is enabled (T1OSCEN is

set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins

become inputs. That is, the TRISC<1:0> value is

ignored and the pins are read as ‘0’.

The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>).

Timer1 also has an internal “Reset input”. This Reset

can be generated by the CCP module (Section 15.0

“Capture/Compare/PWM (CCP) Modules”).

FIGURE 12-1:

TIMER1 BLOCK DIAGRAM

CCP Special Event Trigger

TMR1IF

Overflow

Interrupt

Flag Bit

Synchronized

TMR1

0

Clock Input

CLR

TMR1L

TMR1H

1

TMR1ON

On/Off

T1SYNC

T1OSC

1

T13CKI/T1OSO

T1OSI

Synchronize

det

T1OSCEN

Enable

Oscillator

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

(1)

0

2

Sleep Input

T1CKPS1:T1CKPS0

TMR1CS

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

FIGURE 12-2:

TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE

Data Bus<7:0>

8

TMR1H

8

Write TMR1L

Read TMR1L

CCP Special Event Trigger

0

TMR1IF

Overflow

Interrupt

Synchronized

Clock Input

TMR1

8

CLR

Timer 1

High Byte

TMR1L

Flag bit

1

TMR1ON

T1SYNC

On/Off

T1OSC

T13CKI/T1OSO

1

Synchronize

det

Prescaler

1, 2, 4, 8

T1OSCEN

Enable

Oscillator

FOSC/4

Internal

Clock

0

(1)

T1OSI

2

Sleep Input

TMR1CS

T1CKPS1:T1CKPS0

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

DS30491C-page 160

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

12.2 Timer1 Oscillator

12.4 Resetting Timer1 Using a CCP

Trigger Output

A crystal oscillator circuit is built-in between pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control bit, T1OSCEN (T1CON<3>). The oscil-

lator is a low-power oscillator rated up to 200 kHz. It will

continue to run during Sleep. It is primarily intended for

a 32 kHz crystal. Table 12-1 shows the capacitor

selection for the Timer1 oscillator.

If the CCP module is configured in Compare mode

to generate “special event trigger”

a

(CCP1M3:CCP1M0 = 1011), this signal will reset

Timer1 and start an A/D conversion (if the A/D module

is enabled).

Note:

The special event triggers from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

The user must provide a software time delay to ensure

proper start-up of the Timer1 oscillator.

Timer1 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

TABLE 12-1: CAPACITOR SELECTION

FOR THE ALTERNATE

OSCILLATOR

Osc Type

Freq

C1

C2

In the event that a write to Timer1 coincides with a

special event trigger from CCP1, the write will take

precedence.

LP

32 kHz

TBD⁽¹⁾

Crystal to be Tested:

32.768 kHz Epson C-001R32.768K-A

In this mode of operation, the CCPR1H:CCPR1L register

pair effectively becomes the period register for Timer1.

20 PPM

Note 1: Microchip suggests 33 pF as a starting

point in validating the oscillator circuit.

12.5 Timer1 16-Bit Read/Write Mode

2: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time.

Timer1 can be configured for 16-bit reads and writes

(see Figure 12-2). When the RD16 control bit

(T1CON<7>) is set, the address for TMR1H is mapped

to a buffer register for the high byte of Timer1. A read

from TMR1L will load the contents of the high byte of

Timer1 into the Timer1 high byte buffer. This provides

the user with the ability to accurately read all 16 bits of

Timer1 without having to determine whether a read of

the high byte, followed by a read of the low byte, is valid

due to a rollover between reads.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate

values

of

external

components.

4: Capacitor values are for design guidance

only.

A write to the high byte of Timer1 must also take place

through the TMR1H Buffer register. Timer1 high byte is

updated with the contents of TMR1H when a write

occurs to TMR1L. This allows a user to write all 16 bits

to both the high and low bytes of Timer1 at once.

12.3 Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to 0FFFFh and rolls over to 0000h. The

TMR1 interrupt, if enabled, is generated on overflow

which is latched in interrupt flag bit, TMR1IF

(PIR1<0>). This interrupt can be enabled/disabled by

setting/clearing TMR1 interrupt enable bit, TMR1IE

(PIE1<0>).

The high byte of Timer1 is not directly readable or writ-

able in this mode. All reads and writes must take place

through the Timer1 High Byte Buffer register. Writes to

TMR1H do not clear the Timer1 prescaler. The

prescaler is only cleared on writes to TMR1L.

TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

INT0IF

RBIF

0000 0000 0000 0000

PIR1

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111

PIE1

TXIE

TXIP

IPR1

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

T1CON

RD16

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

Legend:

x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

 2004 Microchip Technology Inc.

DS30491C-page 161

PIC18F6585/8585/6680/8680

13.1 Timer2 Operation

13.0 TIMER2 MODULE

Timer2 can be used as the PWM time base for the

PWM mode of the CCP module. The TMR2 register is

readable and writable and is cleared on any device

Reset. The input clock (FOSC/4) has a prescale option

of 1:1, 1:4 or 1:16, selected by control bits,

T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-

put of TMR2 goes through a 4-bit postscaler (which

gives a 1:1 to 1:16 scaling inclusive) to generate a

TMR2 interrupt latched in flag bit, TMR2IF (PIR1<1>).

The Timer2 module timer has the following features:

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match of PR2

• SSP module optional use of TMR2 output to

generate clock shift

The prescaler and postscaler counters are cleared

when any of the following occurs:

Timer2 has a control register shown in Register 13-1.

Timer2 can be shut-off by clearing control bit, TMR2ON

(T2CON<2>), to minimize power consumption.

Figure 13-1 is a simplified block diagram of the Timer2

module. Register 13-1 shows the Timer2 Control regis-

ter. The prescaler and postscaler selection of Timer2

are controlled by this register.

• a write to the TMR2 register

• a write to the T2CON register

• any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset, or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER

U-0

—

R/W-0

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 0

bit 7

Unimplemented: Read as ‘0’

bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits

0000= 1:1 postscale

0001= 1:2 postscale

•

1111= 1:16 postscale

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 162

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

13.2 Timer2 Interrupt

13.3 Output of TMR2

The Timer2 module has an 8-bit period register, PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

initialized to 0FFh upon Reset.

The output of TMR2 (before the postscaler) is fed to the

synchronous serial port module which optionally uses it

to generate the shift clock.

FIGURE 13-1:

TIMER2 BLOCK DIAGRAM

Sets Flag

TMR2

bit TMR2IF

(1)

Output

Prescaler

Reset

EQ

FOSC/4

TMR2

1:1, 1:4, 1:16

Postscaler

1:1 to 1:16

2

Comparator

PR2

T2CKPS1:T2CKPS0

4

T2OUTPS3:T2OUTPS0

Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.

TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

INT0IF

RBIF

0000 0000 0000 0000

PIR1

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111

0000 0000 0000 0000

PIE1

TXIE

TXIP

IPR1

TMR2

T2CON

PR2

Timer2 Module Register

—

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Timer2 Period Register 1111 1111 1111 1111

x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

Legend:

 2004 Microchip Technology Inc.

DS30491C-page 163

PIC18F6585/8585/6680/8680

Figure 14-1 is a simplified block diagram of the Timer3

module.

14.0 TIMER3 MODULE

The Timer3 module timer/counter has the following

features:

Register 14-1 shows the Timer3 Control register. This

register controls the operating mode of the Timer3

module and sets the Enhanced CCP1 and CCP2 clock

source.

• 16-bit timer/counter

(two 8-bit registers; TMR3H and TMR3L)

• Readable and writable (both registers)

• Internal or external clock select

Register 12-1 shows the Timer1 Control register. This

register controls the operating mode of the Timer1

module, as well as containing the Timer1 oscillator

enable bit (T1OSCEN) which can be a clock source for

Timer3.

• Interrupt on overflow from FFFFh to 0000h

• Reset from CCP module trigger

REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER

R/W-0

RD16

R/W-0

T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

bit 0

bit 7

RD16: 16-bit Read/Write Mode Enable bit

1= Enables register read/write of Timer3 in one 16-bit operation

0= Enables register read/write of Timer3 in two 8-bit operations

bit 6, 3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits

1x= Timer3 is the clock source for compare/capture of CCP1 and CCP2 modules

01= Timer3 is the clock source for compare/capture of CCP2 module,

Timer1 is the clock source for compare/capture of CCP1 module

00= Timer1 is the clock source for compare/capture of CCP1 and CCP2 modules

bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits

11= 1:8 prescale value

10= 1:4 prescale value

01= 1:2 prescale value

00= 1:1 prescale value

bit 2

T3SYNC: Timer3 External Clock Input Synchronization Control bit

(Not usable if the system clock comes from Timer1/Timer3.)

When TMR3CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

When TMR3CS = 0:

This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

bit 1

bit 0

TMR3CS: Timer3 Clock Source Select bit

1= External clock input from Timer1 oscillator or T13CKI

(on the rising edge after the first falling edge)

0= Internal clock (FOSC/4)

TMR3ON: Timer3 On bit

1= Enables Timer3

0= Stops Timer3

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 164

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

When TMR3CS = 0, Timer3 increments every instruc-

tion cycle. When TMR3CS = 1, Timer3 increments on

every rising edge of the Timer1 external clock input or

the Timer1 oscillator if enabled.

14.1 Timer3 Operation

Timer3 can operate in one of these modes:

• As a timer

• As a synchronous counter

• As an asynchronous counter

When the Timer1 oscillator is enabled (T1OSCEN is

set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins

become inputs. That is, the TRISC<1:0> value is

The operating mode is determined by the clock select

bit, TMR3CS (T3CON<1>).

ignored and the pins are read as ‘0’.

Timer3 also has an internal “Reset input”. This Reset

can be generated by the CCP module (Section 14.0

“Timer3 Module”).

FIGURE 14-1:

TIMER3 BLOCK DIAGRAM

CCP Special Trigger

T3CCPx

TMR3IF

Overflow

Interrupt

Synchronized

Clock Input

0

Flag bit

CLR

TMR3H

T1OSC

TMR3L

1

TMR3ON

On/Off

T3SYNC

(3)

T1OSO/

T13CKI

1

Synchronize

det

Prescaler

1, 2, 4, 8

T1OSCEN

Enable

Oscillator

FOSC/4

Internal

Clock

0

(1)

T1OSI

2

TMR3CS

Sleep Input

T3CKPS1:T3CKPS0

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

FIGURE 14-2:

TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE

Data Bus<7:0>

8

TMR3H

8

Write TMR3L

Read TMR3L

CCP Special Trigger

T3CCPx

0

Synchronized

Clock Input

8

TMR3

Set TMR3IF Flag bit

on Overflow

CLR

Timer3

High Byte

TMR3L

1

To Timer1 Clock Input

TMR3ON

On/Off

T3SYNC

T1OSC

T1OSO/

T13CKI

1

Synchronize

det

Prescaler

1, 2, 4, 8

T1OSCEN

Enable

Oscillator

FOSC/4

Internal

Clock

0

(1)

T1OSI

2

Sleep Input

T3CKPS1:T3CKPS0

TMR3CS

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

 2004 Microchip Technology Inc.

DS30491C-page 165

PIC18F6585/8585/6680/8680

14.2 Timer1 Oscillator

14.4 Resetting Timer3 Using a CCP

Trigger Output

The Timer1 oscillator may be used as the clock source

for Timer3. The Timer1 oscillator is enabled by setting

the T1OSCEN (T1CON<3>) bit. The oscillator is a low-

power oscillator rated up to 200 kHz. See Section 12.0

“Timer1 Module” for further details.

If the CCP module is configured in Compare mode

to

generate

a

“special

event

trigger”

(CCP1M3:CCP1M0 = 1011), this signal will reset

Timer3.

Note:

The special event triggers from the CCP

module will not set interrupt flag bit,

TMR3IF (PIR1<0>).

14.3 Timer3 Interrupt

The TMR3 register pair (TMR3H:TMR3L) increments

from 0000h to 0FFFFh and rolls over to 0000h. The

TMR3 interrupt, if enabled, is generated on overflow

which is latched in interrupt flag bit, TMR3IF

(PIR2<1>). This interrupt can be enabled/disabled by

setting/clearing TMR3 interrupt enable bit, TMR3IE

(PIE2<1>).

Timer3 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer3 is running in Asynchronous Counter mode,

this Reset operation may not work. In the event that a

write to Timer3 coincides with a special event trigger

from CCP1, the write will take precedence. In this mode

of operation, the CCPR1H:CCPR1L register pair

effectively becomes the period register for Timer3.

TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000 0000 0000

PIR2

—

CMIF

CMIE

CMIP

—

EEIF

EEIE

EEIP

BCLIF

BCLIE

BCLIP

LVDIF

LVDIE

LVDIP

TMR3IF

TMR3IE

TMR3IP

CCP2IF -0-0 0000 -0-0 0000

CCP2IE -0-0 0000 -0-0 0000

CCP2IP -1-1 1111 -1-1 1111

xxxx xxxx uuuu uuuu

PIE2

IPR2

TMR3L

TMR3H

T1CON

T3CON

Legend:

Holding Register for the Least Significant Byte of the 16-bit TMR3 Register

Holding Register for the Most Significant Byte of the 16-bit TMR3 Register

xxxx xxxx uuuu uuuu

RD16

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.

DS30491C-page 166

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

Additionally, the CCP2 special event trigger may be

used to start an A/D conversion if the A/D module is

enabled.

15.0 CAPTURE/COMPARE/PWM

(CCP) MODULES

PIC18FXX80/XX85 devices contain a total of two CCP

modules: CCP1 and CCP2. CCP1 is an enhanced

version of the CCP2 module. CCP1 is fully backward

compatible with the CCP2 module.

To avoid duplicate information, this section describes

basic CCP module operation that applies to both CCP1

and CCP2. Enhanced CCP functionality of the

CCP1 module is described in Section 16.0 “Enhanced

Capture/Compare/PWM (ECCP) Module”.

The CCP1 module differs from CCP2 in the following

respect:

The control registers for the CCP1 and CCP2 modules

are shown in Register 15-1 and Register 15-2,

respectively. Table 15-2 details the interactions of the

CCP and ECCP modules.

• CCP1 contains a special trigger event that may

reset Timer1 or the Timer3 register pair

• CCP1 contains “CAN Message Time-Stamp Trigger”

• CCP1 contains enhanced PWM output with

programmable dead band and auto-shutdown

functionality

REGISTER 15-1: CCP1CON REGISTER

R/W-0

CCP1M0

bit 0

R/W-0

P1M1

R/W-0

P1M0

R/W-0

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1

bit 7

bit 7-6

P1M1:P1M0: Enhanced PWM Output Configuration bits

If CCP1M<3:2> = 00, 01, 10:

xx=P1A assigned as capture/compare input; P1B, P1C, P1D assigned as port pins

If CCP1M<3:2> = 11:

00= Single output; P1A modulated; P1B, P1C, P1D assigned as port pins

01= Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive

10= Half-bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as

port pins

11= Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive

bit 5-4

DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are

found in CCPR1L.

bit 3-0

CCP1M3:CCP1M0: Enhanced CCP Mode Select bits

0000= Capture/Compare/PWM off (resets CCP1 module)

0001= Reserved

0010= Compare mode, toggle output on match

0011= Reserved

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode, initialize CCP pin low, on compare match force CCP pin high

1001= Compare mode, initialize CCP pin high, on compare match force CCP pin low

1010= Compare mode, generate software interrupt only, CCP pin is unaffected

1011= Compare mode, trigger special event, resets TMR1 or TMR3

1100= PWM mode; P1A, P1C active-high; P1B, P1D active-high

1101= PWM mode; P1A, P1C active-high; P1B, P1D active-low

1110= PWM mode; P1A, P1C active-low; P1B, P1D active-high

1111= PWM mode; P1A, P1C active-low; P1B, P1D active-low

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 167

PIC18F6585/8585/6680/8680

REGISTER 15-2: CCP2CON REGISTER

U-0

—

U-0

—

R/W-0

DC2B1

DC2B0

CCP2M3 CCP2M2 CCP2M1 CCP2M0

bit 0

bit 7

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

DC2B1:DC2B0: PWM Duty Cycle bit 1 and bit 0

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are

found in CCPR2L.

bit 3-0

CCP2M3:CCP2M0: CCP2 Mode Select bits

0000= Capture/Compare/PWM off (resets CCP2 module)

0001= Reserved

0010= Compare mode, toggle output on match

0011= Reserved

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode, initialize CCP pin low, on compare match force CCP pin high

1001= Compare mode, initialize CCP pin high, on compare match force CCP pin low

1010= Compare mode, generate software interrupt only, CCP pin is unaffected

1011= Compare mode, trigger special event, resets TMR1 or TMR3 and starts A/D conversion

if A/D module is enabled

11xx= PWM mode

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 168

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

An event is selected by control bits CCPxM3:CCPxM0

(CCPxCON<3:0>). When a capture is made, the inter-

rupt request flag bit, CCPxIF (PIR registers), is set. It

must be cleared in software. If another capture occurs

before the value in register CCPRx is read, the old

captured value will be lost.

15.1 CCP Module

Both CCP1 and CCP2 are comprised of two 8-bit

registers: CCPRxL (low byte) and CCPRxH (high byte),

1 ≤ x ≤ 2. The CCPxCON register controls the

operation of CCPx. All are readable and writable.

Table 15-1 shows the timer resources of the CCP

module modes.

15.2.1

CCP PIN CONFIGURATION

In Capture mode, the CCPx pin should be configured

as an input by setting the appropriate TRIS bit.

TABLE 15-1: CCP MODE – TIMER

RESOURCE

Note:

If the CCPx is configured as an output, a

write to the port can cause a capture

condition.

CCP Mode

Timer Resource

Capture

Compare

PWM

Timer1 or Timer3

Timer2

15.2.2

TIMER1/TIMER3 MODE SELECTION

The timer used with each CCP module is selected in

the T3CCP2:T3CCP1 bits of the T3CON register. The

timers used with the capture feature (either Timer1 or

Timer3) must be running in Timer mode or Synchro-

nized Counter mode. In Asynchronous Counter mode,

the capture operation may not work.

15.2 Capture Mode

In Capture mode, CCPRxH:CCPRxL captures the

16-bit value of the TMR1 or TMR3 register when an

event occurs on pin CCPn. An event is defined as:

• every falling edge

• every rising edge

• every 4th rising edge

• every 16th rising edge

TABLE 15-2: INTERACTION OF CCP MODULES

CCP1

Mode

CCP2

Mode

Interaction

Capture

TMR1 or TMR3 time base. Time base can be different for each CCP.

Compare

The compare could be configured for the special event trigger which clears either TMR1

or TMR3 depending upon which time base is used.

Compare

The compare(s) could be configured for the special event trigger which clears TMR1 or

TMR3 depending upon which time base is used.

PWM

The PWMs will have the same frequency and update rate (TMR2 interrupt).

Capture

Compare

None.

 2004 Microchip Technology Inc.

DS30491C-page 169

PIC18F6585/8585/6680/8680

15.2.3

SOFTWARE INTERRUPT

15.2.5

CAN MESSAGE TIME-STAMP

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCPxIE (PIE registers) clear to avoid false interrupts

and should clear the flag bit, CCPxIF, following any

such change in operating mode.

The CAN capture event occurs when a message is

received in any of the receive buffers. When config-

ured, the CAN module provides the trigger to the CCP1

module to cause a capture event. This feature is

provided to time-stamp the received CAN messages.

This feature is enabled by setting the CANCAP bit of

the CAN I/O Control register (CIOCON<4>). The

message receive signal from the CAN module then

takes the place of the events on RC2/CCP1.

15.2.4

CCP PRESCALER

There are four prescaler settings specified by bits

CCPxM3:CCPxM0. Whenever the CCPx module is

turned off, or the CCPx module is not in Capture mode,

the prescaler counter is cleared. This means that any

Reset will clear the prescaler counter.

EXAMPLE 15-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

Switching from one capture prescaler to another may

generate an interrupt. The prescaler counter will not be

cleared; therefore, the first capture may be from a

non-zero prescaler. Example 15-1 shows the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

CLRF

MOVLW

CCP1CON

NEW_CAPT_PS

; Turn CCP module off

; Load WREG with the

; new prescaler mode

; value and CCP ON

; Load CCP1CON with

; this value

MOVWF

CCP1CON

FIGURE 15-1:

CAPTURE MODE OPERATION BLOCK DIAGRAM

TMR3H

TMR3L

CCPR1L

TMR1L

Set Flag bit CCP1IF

T3CCP2

TMR3

Enable

Prescaler

÷ 1, 4, 16

CCP1 pin

CCPR1H

TMR1

and

Edge Detect

Enable

TMR1H

CCP1CON<3:0>

Q’s

Set Flag bit CCP2IF

T3CCP1

TMR3H

TMR3L

CCPR2L

TMR1L

T3CCP2

TMR3

Enable

Prescaler

÷ 1, 4, 16

CCP2 pin

CCPR2H

TMR1

and

Edge Detect

Enable

T3CCP2

T3CCP1

TMR1H

CCP2CON<3:0>

Q’s

DS30491C-page 170

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

15.3.2

TIMER1/TIMER3 MODE SELECTION

15.3 Compare Mode

The timer used with each CCP module is selected in

the T3CCP2:T3CCP1 bits of the T3CON register.

Timer1 and/or Timer3 must be running in Timer mode,

or Synchronized Counter mode, if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

In Compare mode, the 16-bit CCPRx register value is

constantly compared against either the TMR1 register

pair value or the TMR3 register pair value. When a

match occurs, the CCPx pin can have one of the

following actions:

• Driven high

• Driven low

15.3.3

SOFTWARE INTERRUPT MODE

• Toggle output (high-to-low or low-to-high)

• Remains unchanged

When generate software interrupt is chosen, the CCPx

pin is not affected. Only a CCP interrupt is generated (if

enabled).

The action on the pin is based on the value of control

bits, CCPxM3:CCPxM0. At the same time, interrupt

flag bit, CCPxIF, is set.

15.3.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated

which may be used to initiate an action.

When configured to drive the CCP pin, the CCP1 pin

cannot be changed; CCP1 module controls the pin.

The special event trigger output of CCP1 resets either

the TMR1 or TMR3 register pair. This allows the CCPR1

register to effectively be a 16-bit programmable period

register for TMR1 or TMR3.

15.3.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the appropriate TRIS bit.

Additionally, the CCP2 special event trigger will start an

A/D conversion if the A/D module is enabled.

By default, the CCP2 pin is multiplexed with RC1.

Alternately, it can also be multiplexed with either RB3

or RE7. This is done by changing the CCP2MX

configuration bit.

Note:

The special event trigger from the CCPx

module will not set the Timer1 or Timer3

interrupt flag bits.

Note:

Clearing the CCPxCON register will force

the CCPx compare output latch to the

default low level. This is not the data latch.

FIGURE 15-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

Special Event Trigger will:

Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit

and set bit GO/DONE (ADCON0<2>)

which starts an A/D conversion (CCP2 only)

Set Flag bit CCP1IF

CCPR1H CCPR1L

Comparator

Q

S

R

Output

Logic

Match

RC2/CCP1 pin

TRISC<2>

Output Enable

1

0

CCP1CON<3:0>

Mode Select

T3CCP2

TMR1H TMR1L

TMR3H TMR3L

Special Event Trigger

Set Flag bit CCP2IF

T3CCP1

T3CCP2

0

1

Q

S

R

Output

Logic

Comparator

Match

RC1/CCP2 pin

TRISC<1>

Output Enable

CCPR2H CCPR2L

CCP2CON<3:0>

Mode Select

 2004 Microchip Technology Inc.

DS30491C-page 171

PIC18F6585/8585/6680/8680

TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

CCP1IF

INT0IF

RBIF

0000 000x 0000 000u

PIR1

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

SSPIF

SSPIE

SSPIP

TMR2IF

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

TMR1IP 1111 1111 1111 1111

1111 1111 1111 1111

PIE1

CCP1IE TMR2IE

CCP1IP TMR2IP

IPR1

TRISD

TMR1L

TMR1H

T1CON

CCPR1L

CCPR1H

CCP1CON

PIR2

PORTD Data Direction Register

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

RD16

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

Capture/Compare/PWM Register 1 (LSB)

Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx uuuu uuuu

P1M1

—

P1M0

CMIF

CMIE

CMIP

DC1B1

—

DC1B0

EEIF

CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

BCLIF

BCLIE

BCLIP

LVDIF

LVDIE

LVDIP

TMR3IF

TMR3IE

TMR3IP

CCP2IF -0-0 0000 -0-0 0000

CCP2IE -0-0 0000 -0-0 0000

CCP2IP -1-1 1111 -1-1 1111

xxxx xxxx uuuu uuuu

PIE2

—

EEIE

EEIP

IPR2

—

TMR3L

TMR3H

T3CON

Legend:

Holding Register for the Least Significant Byte of the 16-bit TMR3 Register

Holding Register for the Most Significant Byte of the 16-bit TMR3 Register

xxxx xxxx uuuu uuuu

RD16

T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by capture and Timer1.

DS30491C-page 172

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

15.4.1

PWM PERIOD

15.4 PWM Mode

The PWM period is specified by writing to the PR2

register. The PWM period can be calculated using the

following formula.

In Pulse Width Modulation (PWM) mode, the CCPx pin

produces up to a 10-bit resolution PWM output. For

PWM mode to function properly, the TRIS bit for the

CCPx pin must be cleared to make it an output.

EQUATION 15-1:

Note:

Clearing the CCPxCON register will force

the CCPx PWM output latch to the default

low level. This is not the port data latch.

PWM Period = [(PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

Figure 15-3 shows a simplified block diagram of the

CCP module in PWM mode.

PWM frequency is defined as 1/[PWM period].

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 15.4.3

“Setup for PWM Operation”.

• TMR2 is cleared

• The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

FIGURE 15-3:

SIMPLIFIED PWM BLOCK

DIAGRAM

• The PWM duty cycle is latched from CCPR1L into

CCPR1H

CCPxCON<5:4>

Duty Cycle Registers

Note:

The Timer2 postscaler (see Section 13.0

“Timer2 Module”) is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

CCPRxL (Master)

CCPRxH (Slave)

Comparator

Q

R

15.4.2

PWM DUTY CYCLE

CCPx

The PWM duty cycle is specified by writing to the

CCPRxL register and to the CCPxCON<5:4> bits. Up

to 10-bit resolution is available. The CCPRxL contains

the eight MSbs and the CCPxCON<5:4> contain the

two LSbs. This 10-bit value is represented by

CCPRxL:CCPxCON<5:4>. The following equation is

used to calculate the PWM duty cycle in time.

(Note 1)

TMR2

S

TRIS bit

Comparator

PR2

Clear Timer,

set CCPx pin and

latch D.C.

EQUATION 15-2:

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or

2 bits of the prescaler to create 10-bit time base.

PWM Duty Cycle = (CCPRxL:CCPxCON<5:4>) •

TOSC • (TMR2 Prescale Value)

A PWM output (Figure 15-4) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

CCPRxL and CCPxCON<5:4> can be written to at any

time but the duty cycle value is not latched into

CCPRxH until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPRxH is a read-only register.

FIGURE 15-4:

PWM OUTPUT

The CCPRxH register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation.

Period

Duty Cycle

When the CCPRxH and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the CCPx pin is cleared.

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

 2004 Microchip Technology Inc.

DS30491C-page 173

PIC18F6585/8585/6680/8680

The maximum PWM resolution (bits) for a given PWM

frequency is given by the following equation.

15.4.3

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

EQUATION 15-3:

1. Set the PWM period by writing to the PR2

register.



^FOSC

---------------

log



_FPWM

2. Set the PWM duty cycle by writing to the

CCPRxL register and CCPxCON<5:4> bits.

PWM Resolution (max)

= ----------------------------- b i t s

log(2)

3. Make the CCPx pin an output by clearing

corresponding TRIS bit.

4. Set the TMR2 prescale value and enable Timer2

by writing to T2CON.

Note:

If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

5. Configure the CCPx module for PWM operation.

TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency

2.44 kHz 9.76 kHz 39.06 kHz 156.3 kHz 312.5 kHz 416.6 kHz

Timer Prescaler (1, 4, 16)

PR2 Value

16

0FFh

10

4

1

3Fh

8

1

1Fh

7

1

0FFh

10

0FFh

10

17h

5.5

Maximum Resolution (bits)

TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

CCP1IF

CCP1IE

CCP1IP

INT0IF

TMR2IF

TMR2IE

TMR2IP

RBIF

0000 000x 0000 000u

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

TMR1IP 1111 1111 1111 1111

1111 1111 1111 1111

PIE1

TXIE

TXIP

IPR1

TRISC

TMR2

PR2

PORTC Data Direction Register

Timer2 Module Register

0000 0000 0000 0000

Timer2 Module Period Register

1111 1111 1111 1111

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

CCPR1L Capture/Compare/PWM Register 1 (LSB)

CCPR1H Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx uuuu uuuu

CCP1CON

P1M1

P1M0

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

xxxx xxxx uuuu uuuu

CCPR2L Capture/Compare/PWM Register 2 (LSB)

CCPR2H Capture/Compare/PWM Register 2 (MSB)

xxxx xxxx uuuu uuuu

CCP2CON

—

DC2B1

DC2B0

CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

Legend:

x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.

DS30491C-page 174

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

The control register for CCP1 is shown in Register 16-1.

16.0 ENHANCED CAPTURE/

COMPARE/PWM (ECCP)

MODULE

In addition to the expanded functions of the

CCP1CON register, the CCP1 module has two

additional registers associated with enhanced PWM

The CCP1 module is implemented as a standard CCP

module with enhanced PWM capabilities. These capa-

bilities allow for 2 or 4 output channels, user selectable

polarity, dead-band control, and automatic shutdown

and restart and are discussed in detail in Section 16.2

“Enhanced PWM Mode”.

operation and auto-shutdown features:

• ECCP1DEL

• ECCP1AS

REGISTER 16-1: CCP1CON REGISTER

R/W-0

P1M1

R/W-0

P1M0

R/W-0

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 0

bit 7

bit 7-6

P1M1:P1M0: Enhanced PWM Output Configuration bits

If CCP1M<3:2> = 00, 01, 10:

xx= P1A assigned as capture/compare input; P1B, P1C, P1D assigned as port pins

If CCP1M<3:2> = 11:

00= Single output; P1A modulated, P1B, P1C, P1D assigned as port pins

01= Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive

10= Half-bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as

port pins

11= Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive

bit 5-4

DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are

found in CCPR1L.

bit 3-0

CCP1M3:CCP1M0: Enhanced CCP Mode Select bits

0000=Capture/Compare/PWM off (resets CCP1 module)

0001=Reserved

0010=Compare mode, toggle output on match

0011=Capture mode, CAN message time-stamp

0100=Capture mode, every falling edge

0101=Capture mode, every rising edge

0110=Capture mode, every 4th rising edge

0111=Capture mode, every 16th rising edge

1000=Compare mode, initialize CCP pin low, on compare match, force CCP pin high

1001=Compare mode, initialize CCP pin high, on compare match, force CCP pin low

1010=Compare mode, generate software interrupt only, CCP pin is unaffected

1011=Compare mode, trigger special event, resets TMR1 or TMR3

1100=PWM mode; P1A, P1C active-high; P1B, P1D active-high

1101=PWM mode; P1A, P1C active-high; P1B, P1D active-low

1110=PWM mode; P1A, P1C active-low; P1B, P1D active-high

1111=PWM mode; P1A, P1C active-low; P1B, P1D active-low

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 175

PIC18F6585/8585/6680/8680

To configure I/O pins as PWM outputs, the proper PWM

16.1 ECCP Outputs

mode must be selected by setting the P1Mx and

CCP1Mx bits (CCP1CON<7:6> and <3:0>, respec-

tively). The appropriate TRIS direction bits for the port

pins must also be set as outputs.

The enhanced CCP module may have up to four

outputs depending on the selected operating mode.

These outputs, designated P1A through P1D, are

multiplexed with I/O pins RC2, RE6, RE5 and RG4.

The pin assignments are summarized in Table 16-1.

TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES

CCP1CON

ECCP Mode

RC2

RE6

RE5

RG4

Configuration

Compatible CCP

Dual PWM

00xx11xx

10xx11xx

x1xx11xx

CCP1

P1A

RE6

RE5

RG4

P1D

P1B⁽²⁾

Quad PWM

P1A

P1C⁽²⁾

Legend: x= Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.

Note 1: TRIS register values must be configured appropriately.

2: On PIC18F8X8X devices, these pins can be alternately multiplexed with RH7 or RH6 by changing the

ECCPMX configuration bit.

FIGURE 16-1:

COMPARE MODE OPERATION BLOCK DIAGRAM

Special Event Trigger will:

Reset Timer1 or Timer3, but will not set Timer1 or Timer3 interrupt flag bit

and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion.

Set Flag bit CCP1IF

Match

CCPR1H CCPR1L

Comparator

Q

S

R

Output

Logic

RB3/CCP1/P1A pin

TRISB<3>

Output Enable

1

0

T3CCP2

CCP1CON<3:0>

Mode Select

TMR1H TMR1L

TMR3H TMR3L

DS30491C-page 176

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

16.2.2

PWM DUTY CYCLE

16.2 Enhanced PWM Mode

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The PWM duty cycle is

calculated by the following equation.

The Enhanced PWM mode provides additional PWM

output options for a broader range of control applica-

tions. The module is a backward compatible version of

the standard CCP module and offers up to four outputs,

designated P1A through P1D. Users are also able to

select the polarity of the signal (either active-high or

active-low). The module’s output mode and polarity are

configured by setting the P1M1:P1M0 and

CCP1M3:CCP1M0 bits of the CCP1CON register

(CCP1CON<7:6> and CCP1CON<3:0>, respectively).

EQUATION 16-2:

PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 Prescale Value)

Figure 16-2 shows a simplified block diagram of PWM

operation. All control registers are double-buffered and

are loaded at the beginning of a new PWM cycle (the

period boundary when Timer2 resets) in order to pre-

vent glitches on any of the outputs. The exception is the

PWM Delay register, ECCP1DEL, which is loaded at

either the duty cycle boundary or the boundary period

(whichever comes first). Because of the buffering, the

module waits until the assigned timer resets instead of

starting immediately. This means that enhanced PWM

waveforms do not exactly match the standard PWM

waveforms, but are instead offset by one full instruction

cycle (4 TOSC).

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not copied into

CCPR1H until a match between PR2 and TMR2 occurs

(i.e., the period is complete). In PWM mode, CCPR1H

is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM opera-

tion. When the CCPR1H and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or two bits

of the TMR2 prescaler, the CCP1 pin is cleared. The

maximum PWM resolution (bits) for a given PWM

frequency is given by the following equation:

As before, the user must manually configure the

appropriate TRIS bits for output.

16.2.1

PWM PERIOD

EQUATION 16-3:

The PWM period is specified by writing to the PR2

register. The PWM period can be calculated using the

following equation.

FOSC

log

FPWM

bits

PWM Resolution (max) =

log(2)

EQUATION 16-1:

PWM Period = [(PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

Note:

If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

PWM frequency is defined as 1/[PWM period]. When

TMR2 is equal to PR2, the following three events occur

on the next increment cycle:

16.2.3

PWM OUTPUT CONFIGURATIONS

The P1M1:P1M0 bits in the CCP1CON register allow

one of four configurations:

• TMR2 is cleared

• The CCP1 pin is set (if PWM duty cycle = 0%, the

CCP1 pin will not be set)

• Single Output

• Half-Bridge Output

• The PWM duty cycle is copied from CCPR1L into

CCPR1H

• Full-Bridge Output, Forward mode

• Full-Bridge Output, Reverse mode

Note:

The Timer2 postscaler (see Section 13.0

“Timer2 Module”) is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

The Single Output mode is the standard PWM mode

discussed in Section 16.2 “Enhanced PWM Mode”.

The Half-Bridge and Full-Bridge Output modes are

covered in detail in the sections that follow.

The general relationship of the outputs in all

configurations is summarized in Figure 16-3.

 2004 Microchip Technology Inc.

DS30491C-page 177

PIC18F6585/8585/6680/8680

TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency

2.44 kHz

9.77 kHz

39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16)

PR2 Value

16

FFh

10

4

1

3Fh

8

1

1Fh

7

1

FFh

10

FFh

10

17h

6.58

Maximum Resolution (bits)

FIGURE 16-2:

SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE

CCP1CON<5:4>

P1M1<1:0>

CCP1M<3:0>

4

Duty Cycle Registers

2

CCPR1L

CCP1/P1A

RC2/CCP1/P1A

TRISC<2>

TRISE<6>

TRISE<5>

TRISG<4>

CCPR1H (Slave)

Comparator

RE6/AD14/P1B or RH7⁽²⁾

RE5/AD13/P1C or RH6⁽²⁾

RG4/P1D

P1B

Output

Controller

R

S

Q

P1C

(Note 1)

TMR2

P1D

Comparator

PR2

Clear Timer,

set CCP1 pin and

latch D.C.

CCP1DEL

Note 1:

2:

The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock or 2 bits of the prescaler to create the 10-bit time base.

Alternate setting controlled by the ECCPMX bit (PIC18F8X8X devices only).

FIGURE 16-3:

PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)

0

PR2 + 1

Duty

Cycle

SIGNAL

CCP1CON

<7:6>

Period

P1A Modulated

P1B Modulated

P1A Active

(Single Output)

00

10

(1)

Delay

(Half-Bridge)

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

(Full-Bridge,

Forward)

01

(Full-Bridge,

Reverse)

11

P1D Inactive

Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.2.6 “Programmable Dead-Band Delay”).

DS30491C-page 178

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 16-4:

PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

0

PR2 + 1

Duty

Cycle

SIGNAL

CCP1CON

<7:6>

Period

P1A Modulated

P1B Modulated

P1A Active

(Single Output)

00

10

(1)

Delay

(Half-Bridge)

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

(Full-Bridge,

Forward)

01

(Full-Bridge,

Reverse)

11

P1D Inactive

Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.2.6 “Programmable Dead-Band Delay”).

Relationships:

•

Period = 4 * TOSC * (PR2 + 1) * (TMR2 prescale value)

Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 prescale value)

Delay = 4 * TOSC * (PWM1CON<6:0>)

 2004 Microchip Technology Inc.

DS30491C-page 179

PIC18F6585/8585/6680/8680

Since the P1A and P1B outputs are multiplexed with

the PORTC<2> and PORTE<6> data latches, the

TRISC<2> and TRISE<6> bits must be cleared to

configure P1A and P1B as outputs.

16.2.4

HALF-BRIDGE MODE

In the Half-Bridge Output mode, two pins are used as

outputs to drive push-pull loads. The PWM output signal

is output on the P1A pin while the complementary PWM

output signal is output on the P1B pin (Figure 16-5).

This mode can be used for half-bridge applications, as

shown in Figure 16-6, or for full-bridge applications

where four power switches are being modulated with

two PWM signals.

FIGURE 16-5:

HALF-BRIDGE PWM

OUTPUT

Period

Duty Cycle

In Half-Bridge Output mode, the programmable dead-

band delay can be used to prevent shoot-through

current in half-bridge power devices. The value of bits

PDC6:PDC0 sets the number of instruction cycles

before the output is driven active. If the value is greater

than the duty cycle, the corresponding output remains

inactive during the entire cycle. See Section 16.2.6

“Programmable Dead-Band Delay” for more details

of the dead-band delay operations.

(2)

P1A

td

P1B

(1)

td = Dead-band Delay

Note 1: At this time, the TMR2 register is equal to the

PR2 register.

2: Output signals are shown as active-high.

FIGURE 16-6:

EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS

V+

Standard Half-Bridge Circuit (“Push-Pull”)

PIC18FXX80/XX85

FET

Driver

+

V

-

P1A

Load

FET

Driver

+

V

-

P1B

V-

Half-Bridge Output Driving a Full-Bridge Circuit

V+

PIC18FXX80/XX85

FET

Driver

FET

Driver

P1A

Load

FET

Driver

P1B

V-

DS30491C-page 180

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

P1A, P1B, P1C and P1D outputs are multiplexed with

the PORTC<2>, PORTE<6:5> and PORTG<4> data

latches. The TRISC<2>, TRISC<6:5> and TRISG<4>

bits must be cleared to make the P1A, P1B, P1C and

P1D pins outputs.

16.2.5

FULL-BRIDGE MODE

In Full-Bridge Output mode, four pins are used as

outputs; however, only two outputs are active at a time.

In the Forward mode, pin P1A is continuously active

and pin P1D is modulated. In the Reverse mode, pin

PGC is continuously active and pin P1B is modulated.

These are illustrated in Figure 16-7.

FIGURE 16-7:

FULL-BRIDGE PWM OUTPUT

Forward Mode

Period

(2)

P1A

Duty Cycle

(2)

P1B

P1C

(2)

P1D

(1)

Reverse Mode

Period

Duty Cycle

(2)

P1A

(2)

P1B

(2)

P1C

(2)

P1D

(1)

Note 1: At this time, the TMR2 register is equal to the PR2 register.

Note 2: Output signal is shown as active-high.

 2004 Microchip Technology Inc.

DS30491C-page 181

PIC18F6585/8585/6680/8680

FIGURE 16-8:

EXAMPLE OF FULL-BRIDGE APPLICATION

V+

PIC18FXX80/XX85

QC

QA

FET

Driver

FET

Driver

P1A

Load

P1B

FET

Driver

FET

Driver

P1C

P1D

QD

QB

V-

Figure 16-10 shows an example where the PWM direc-

tion changes from forward to reverse at a near 100%

duty cycle. At time t1, the output P1A and P1D become

inactive while output P1C becomes active. In this

example, since the turn off time of the power devices is

longer than the turn on time, a shoot-through current

may flow through power devices QC and QD (see

Figure 16-8) for the duration of ‘t’. The same phenom-

enon will occur to power devices QA and QB for PWM

direction change from reverse to forward.

16.2.5.1

Direction Change in Full-Bridge Mode

In the Full-Bridge Output mode, the P1M1 bit in the

CCP1CON register allows the user to control the

forward/reverse direction. When the application

firmware changes this direction control bit, the module

will assume the new direction on the next PWM cycle.

Just before the end of the current PWM period, the mod-

ulated outputs (P1B and P1D) are placed in their inactive

state while the unmodulated outputs (P1A and P1C) are

switched to drive in the opposite direction. This occurs in

a time interval of (4 TOSC * (Timer2 Prescale value))

before the next PWM period begins. The Timer2

prescaler will be either 1, 4 or 16, depending on the

value of the T2CKPS bit (T2CON<1:0>). During the

interval from the switch of the unmodulated outputs to

the beginning of the next period, the modulated outputs

(P1B and P1D) remain inactive. This relationship is

shown in Figure 16-9.

If changing PWM direction at high duty cycle is required

for an application, one of the following requirements

must be met:

1. Reduce PWM for

changing directions.

a PWM period before

2. Use switch drivers that can drive the switches off

faster than they can drive them on.

Other options to prevent shoot-through current may

exist.

Note that in the Full-Bridge Output mode, the CCP1

module does not provide any dead-band delay. In

general, since only one output is modulated at all times,

dead-band delay is not required. However, there is a

situation where a dead-band delay might be required.

This situation occurs when both of the following

conditions are true:

1. The direction of the PWM output changes when

the duty cycle of the output is at or near 100%.

2. The turn off time of the power switch, including

the power device and driver circuit, is greater

than the turn on time.

DS30491C-page 182

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 16-9:

PWM DIRECTION CHANGE

(1)

Period

SIGNAL

P1A (Active-High)

P1B (Active-High)

DC

P1C (Active-High)

P1D (Active-High)

(Note 2)

DC

Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.

2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at inter-

vals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D

signals are inactive at this time.

FIGURE 16-10:

PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

Forward Period

Reverse Period

t1

P1A

P1B

DC

P1C

P1D

DC

t

ON

External Switch C

External Switch D

t

OFF

Potential

Shoot-Through

Current

t = t

– t

ON

OFF

Note 1: All signals are shown as active-high.

2: t is the turn on delay of power switch QC and its driver.

ON

3: t

is the turn off delay of power switch QD and its driver.

OFF

 2004 Microchip Technology Inc.

DS30491C-page 183

PIC18F6585/8585/6680/8680

A shutdown event can be caused by either of the two

comparator modules or a low level on the RB0 pin (or

any combination of these three sources). The compar-

ators may be used to monitor a voltage input propor-

tional to a current being monitored in the bridge circuit.

If the voltage exceeds a threshold, the comparator

switches state and triggers a shutdown. Alternatively, a

low digital signal on the RB0 pin can also trigger a

shutdown. The auto-shutdown feature can be disabled

by not selecting any auto-shutdown sources. The

auto-shutdown sources to be used are selected using

the ECCPAS2:ECCPAS0 bits (bits <6:4> of the

ECCP1AS register).

16.2.6

PROGRAMMABLE

DEAD-BAND DELAY

In half-bridge applications where all power switches are

modulated at the PWM frequency at all times, the

power switches normally require more time to turn off

than to turn on. If both the upper and lower power

switches are switched at the same time (one turned on

and the other turned off), both switches may be on for

a short period of time until one switch completely turns

off. During this brief interval, a very high current (shoot-

through current) may flow through both power

switches, shorting the bridge supply. To avoid this

potentially destructive shoot-through current from flow-

ing during switching, turning on either of the power

switches is normally delayed to allow the other switch

to completely turn off.

When a shutdown occurs, the output pins are asyn-

chronously placed in their shutdown states, specified

by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits

(ECCP1AS<3:0>). Each pin pair (P1A/P1C and P1B/

P1D) may be set to drive high, drive low, or be tri-stated

(not driving). The ECCPASE bit (ECCP1AS<7>) is also

set to hold the enhanced PWM outputs in their

shutdown states.

In the Half-Bridge Output mode, a digitally pro-

grammable dead-band delay is available to avoid

shoot-through current from destroying the bridge

power switches. The delay occurs at the signal

transition from the non-active state to the active state.

See Figure 16-5 for an illustration. The lower seven bits

of the ECCP1DEL register (Register 16-2) set the

delay period in terms of microcontroller instruction

cycles (TCY or 4 TOSC).

The ECCPASE bit is set by hardware when a shutdown

event occurs. If automatic restarts are not enabled, the

ECCPASE bit is cleared by firmware when the cause of

the shutdown clears. If automatic restarts are enabled,

the ECCPASE bit is automatically cleared when the

cause of the auto-shutdown has cleared.

16.2.7

ENHANCED PWM

AUTO-SHUTDOWN

If the ECCPASE bit is set when a PWM period begins,

the PWM outputs remain in their shutdown state for that

entire PWM period. When the ECCPASE bit is cleared,

the PWM outputs will return to normal operation at the

beginning of the next PWM period.

When the CCP1 is programmed for any of the

enhanced PWM modes, the active output pins may be

configured for auto-shutdown. Auto-shutdown immedi-

ately places the enhanced PWM output pins into a

defined shutdown state when a shutdown event

occurs.

Note:

Writing to the ECCPASE bit is disabled

while a shutdown condition is active.

REGISTER 16-2: ECCP1DEL: ECCP1 DELAY REGISTER

R/W-0

PDC6

R/W-0

PDC5

R/W-0

PDC4

R/W-0

PDC3

R/W-0

PDC2

R/W-0

PDC1

R/W-0

PDC0

PRSEN

bit 7

bit 0

bit 7

PRSEN: PWM Restart Enable bit

1= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event

goes away; the PWM restarts automatically

0= Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM

bit 6-0

PDC<6:0>: PWM Delay Count bits

Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should

transition active and the actual time it transitions active.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 184

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 16-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN

CONTROL REGISTER

R/W-0

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0

bit 7

bit 0

bit 7

ECCPASE: ECCP Auto-Shutdown Event Status bit

0= ECCP outputs are operating

1= A shutdown event has occurred; ECCP outputs are in shutdown state

bit 6-4

ECCPAS<2:0>: ECCP Auto-Shutdown Source Select bits

000=Auto-shutdown is disabled

001=Comparator 1 output

010=Comparator 2 output

011=Either Comparator 1 or 2

100=RB0

101=RB0 or Comparator 1

110=RB0 or Comparator 2

111=RB0 or Comparator 1 or Comparator 2

bit 3-2

bit 1-0

PSSACn: Pins A and C Shutdown State Control bits

00= Drive pins A and C to ‘0’

01= Drive pins A and C to ‘1’

1x= Pins A and C tri-state

PSSBDn: Pins B and D Shutdown State Control bits

00= Drive pins B and D to ‘0’

01= Drive pins B and D to ‘1’

1x= Pins B and D tri-state

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 185

PIC18F6585/8585/6680/8680

16.2.7.1

Auto-Shutdown and Automatic

Restart

16.2.8

START-UP CONSIDERATIONS

When the ECCP module is used in the PWM mode, the

application hardware must use the proper external pull-

up and/or pull-down resistors on the PWM output pins.

When the microcontroller is released from Reset, all of

the I/O pins are in the high-impedance state. The exter-

nal circuits must keep the power switch devices in the

off state until the microcontroller drives the I/O pins with

the proper signal levels or activates the PWM output(s).

The auto-shutdown feature can be configured to allow

automatic restarts of the module following a shutdown

event. This is enabled by setting the PRSEN bit of the

ECCP1DEL register (ECCP1DEL<7>).

In Shutdown mode with PRSEN = 1(Figure 16-11), the

ECCPASE bit will remain set for as long as the cause

of the shutdown continues. When the shutdown condi-

tion clears, the ECCPASE bit is cleared. If PRSEN = 0

(Figure 16-12), once a shutdown condition occurs, the

ECCPASE bit will remain set until it is cleared by firm-

ware. Once ECCPASE is cleared, the enhanced PWM

will resume at the beginning of the next PWM period.

The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow

the user to choose whether the PWM output signals are

active-high or active-low for each pair of PWM output

pins (P1A/P1C and P1B/P1D). The PWM output

polarities must be selected before the PWM pins are

configured as outputs. Changing the polarity configura-

tion while the PWM pins are configured as outputs is

not recommended since it may result in damage to the

application circuits.

Note:

Writing to the ECCPASE bit is disabled

while a shutdown condition is active.

Independent of the PRSEN bit setting, if the auto-

shutdown source is one of the comparators, the shut-

down condition is a level. The ECCPASE bit cannot be

cleared as long as the cause of the shutdown persists.

The P1A, P1B, P1C and P1D output latches may not be

in the proper states when the PWM module is initialized.

Enabling the PWM pins for output at the same time as

the ECCP module may cause damage to the applica-

tion circuit. The ECCP module must be enabled in the

proper Output mode and complete a full PWM cycle

before configuring the PWM pins as outputs. The com-

pletion of a full PWM cycle is indicated by the TMR2IF

bit being set as the second PWM period begins.

The Auto-Shutdown mode can be forced by writing a ‘1’

to the ECCPASE bit.

FIGURE 16-11:

PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)

PWM Period

Shutdown Event

ECCPASE bit

PWM Activity

Normal PWM

Start of

PWM Period

Shutdown

Event Occurs Event Clears

Shutdown

PWM

Resumes

FIGURE 16-12:

PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)

PWM Period

Shutdown Event

ECCPASE bit

PWM Activity

Normal PWM

ECCPASE

Cleared by

Firmware

Start of

PWM Period

Shutdown

Event Occurs Event Clears

Shutdown

PWM

Resumes

DS30491C-page 186

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

7. If auto-restart operation is required, set the

PRSEN bit (ECCP1DEL<7>).

16.2.9

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the ECCP1 module for PWM operation:

8. Configure and start TMR2:

• Clear the TMR2 interrupt flag bit by clearing

the TMR2IF bit (PIR1<1>).

1. Configure the PWM pins, P1A and P1B (and

P1C and P1D, if used), as inputs by setting the

corresponding TRISB bits.

• Set the TMR2 prescale value by loading the

T2CKPS bits (T2CON<1:0>).

2. Set the PWM period by loading the PR2 register.

• Enable Timer2 by setting the TMR2ON bit

(T2CON<2>).

3. Configure the ECCP1 module for the desired

PWM mode and configuration by loading the

CCP1CON register with the appropriate values:

9. Enable PWM outputs after a new PWM cycle

has started:

• Select one of the available output

configurations and direction with the

P1M1:P1M0 bits.

• Wait until TMR2 overflows (TMR2IF bit is set).

• Enable the CCP1/P1A, P1B, P1C and/or P1D

pin outputs by clearing the respective TRISB

bits.

• Select the polarities of the PWM output

signals with the CCP1M3:CCP1M0 bits.

• Clear the ECCPASE bit (ECCP1AS<7>).

4. Set the PWM duty cycle by loading the CCPR1L

register and CCP1CON<5:4> bits.

16.2.10 EFFECTS OF A RESET

5. For Half-Bridge Output mode, set the dead-

band delay by loading ECCP1DEL<6:0> with

the appropriate value.

Both Power-on and subsequent Resets will force all

ports to Input mode and the CCP registers to their

Reset states.

6. If auto-shutdown operation is required, load the

ECCPAS register:

This forces the Enhanced CCP module to reset to a

state compatible with the standard CCP module.

• Select the auto-shutdown sources using the

ECCPAS<2:0> bits.

• Select the shutdown states of the PWM

output pins using PSSAC1:PSSAC0 and

PSSBD1:PSSBD0 bits.

• Set the ECCPASE bit (ECCPAS<7>).

• Configure the comparators using the CMCON

register.

• Configure the comparator inputs as analog

inputs.

TABLE 16-3: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

CCP1IF

CCP1IE

CCP1IP

INT0IF

TMR2IF

TMR2IE

TMR2IP

RBIF

0000 000x 0000 000u

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

TMR1IP 1111 1111 1111 1111

1111 1111 1111 1111

PIE1

TXIE

TXIP

IPR1

TRISC

TRISE

TRISG

TMR2

PORTC Data Direction Register

PORTE Data Direction Register

1111 1111 1111 1111

—

---1 1111 ---1 1111

PORTG Data Direction Register

Timer2 Module Register

Timer2 Module Period Register

0000 0000 0000 0000

PR2

1111 1111 1111 1111

T2CON

CCPR1L

CCPR1H

CCP1CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Capture/Compare/PWM Register 1 (LSB)

Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx uuuu uuuu

P1M1

P1M0

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000

ECCP1DEL PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 uuuu uuuu

Legend: x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.

 2004 Microchip Technology Inc.

DS30491C-page 187

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 188

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

17.3 SPI Mode

17.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

MODULE

The SPI mode allows 8 bits of data to be synchronously

transmitted and received simultaneously. All four

modes of SPI are supported. To accomplish

communication, typically three pins are used:

17.1 Master SSP (MSSP) Module

Overview

• Serial Data Out (SDO) – RC5/SDO

• Serial Data In (SDI) – RC4/SDI/SDA

The Master Synchronous Serial Port (MSSP) module is

a serial interface, useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers, dis-

play drivers, A/D converters, etc. The MSSP module

can operate in one of two modes:

• Serial Clock (SCK) – RC3/SCK/SCL

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select (SS) – RF7/SS

Figure 17-1 shows the block diagram of the MSSP

module when operating in SPI mode.

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C)

- Full Master mode

FIGURE 17-1:

MSSP BLOCK DIAGRAM

(SPI MODE)

- Slave mode (with general address call)

The I²C interface supports the following modes in

hardware:

Internal

Data Bus

Read

Write

• Master mode

• Multi-Master mode

• Slave mode

SSPBUF Reg

SSPSR Reg

17.2 Control Registers

RC4/SDI/SDA

RC5/SDO

The MSSP module has three associated registers.

These include a status register (SSPSTAT) and two

control registers (SSPCON1 and SSPCON2). The use

of these registers and their individual configuration bits

differ significantly depending on whether the MSSP

module is operated in SPI or I²C mode.

Shift

Clock

bit0

RF7/SS

Control

Enable

SS

Additional details are provided under the individual

sections.

Edge

Select

2

Clock Select

SSPM3:SSPM0

SMP:CKE

2

4

TMR2 Output

RC3/SCK/

SCL

(

)

2

Edge

Select

TOSC

Prescaler

4, 16, 64

Data to TX/RX in SSPSR

TRIS bit

 2004 Microchip Technology Inc.

DS30491C-page 189

PIC18F6585/8585/6680/8680

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

17.3.1

REGISTERS

The MSSP module has four registers for SPI mode

operation. These are:

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

• MSSP Control Register 1 (SSPCON1)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer Register

(SSPBUF)

During transmission, the SSPBUF is not double-

buffered. A write to SSPBUF will write to both SSPBUF

and SSPSR.

• MSSP Shift Register (SSPSR) – Not directly

accessible

SSPCON1 and SSPSTAT are the control and status

registers in SPI mode operation. The SSPCON1 regis-

ter is readable and writable. The lower 6 bits of the

SSPSTAT are read-only. The upper two bits of the

SSPSTAT are read/write.

REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

bit 7

bit 6

SMP: Sample bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode.

CKE: SPI Clock Edge Select bit

When CKP = 0:

1= Data transmitted on rising edge of SCK

0= Data transmitted on falling edge of SCK

When CKP = 1:

1= Data transmitted on falling edge of SCK

0= Data transmitted on rising edge of SCK

bit 5

bit 4

D/A: Data/Address bit

Used in I²C mode only.

P: Stop bit

Used in I²C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is

cleared.

bit 3

bit 2

bit 1

bit 0

S: Start bit

Used in I²C mode only.

R/W: Read/Write bit Information

Used in I²C mode only.

UA: Update Address bit

Used in I²C mode only.

BF: Buffer Full Status bit (Receive mode only)

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 190

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

bit 6

WCOL: Write Collision Detect bit (Transmit mode only)

1= The SSPBUF register is written while it is still transmitting the previous word (must be

cleared in software)

0= No collision

SSPOV: Receive Overflow Indicator bit

SPI Slave mode:

1= A new byte is received while the SSPBUF register is still holding the previous data. In case

of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user

must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be

cleared in software).

0= No overflow

Note:

In Master mode, the overflow bit is not set since each new reception (and

transmission) is initiated by writing to the SSPBUF register.

bit 5

bit 4

SSPEN: Synchronous Serial Port Enable bit

1= Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins

0= Disables serial port and configures these pins as I/O port pins

Note:

When enabled, these pins must be properly configured as input or output.

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level

0= Idle state for clock is a low level

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin

0100= SPI Slave mode, clock = SCK pin, SS pin control enabled

0011= SPI Master mode, clock = TMR2 output/2

0010= SPI Master mode, clock = FOSC/64

0001= SPI Master mode, clock = FOSC/16

0000= SPI Master mode, clock = FOSC/4

Note:

Bit combinations not specifically listed here are either reserved or implemented in

I²C mode only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 191

PIC18F6585/8585/6680/8680

reading the data that was just received. Any write to the

SSPBUF register during transmission/reception of data

will be ignored and the Write Collision detect bit, WCOL

(SSPCON1<7>), will be set. User software must clear

the WCOL bit so that it can be determined if the follow-

ing write(s) to the SSPBUF register completed

successfully.

17.3.2

OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON1<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. Buffer

Full bit, BF (SSPSTAT<0>), indicates when SSPBUF

has been loaded with the received data (transmission

is complete). When the SSPBUF is read, the BF bit is

cleared. This data may be irrelevant if the SPI is only a

transmitter. Generally, the MSSP interrupt is used to

determine when the transmission/reception has com-

pleted. The SSPBUF must be read and/or written. If the

interrupt method is not going to be used, then software

polling can be done to ensure that a write collision does

not occur. Example 17-1 shows the loading of the

SSPBUF (SSPSR) for data transmission.

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

The MSSP consists of a Transmit/Receive Shift regis-

ter (SSPSR) and a Buffer register (SSPBUF). The

SSPSR shifts the data in and out of the device, MSb

first. The SSPBUF holds the data that was written to the

SSPSR, until the received data is ready. Once the 8 bits

of data have been received, that byte is moved to the

SSPBUF register. Then the Buffer Full detect bit, BF

(SSPSTAT<0>) and the interrupt flag bit, SSPIF, are

set. This double-buffering of the received data

(SSPBUF) allows the next byte to start reception before

The SSPSR is not directly readable or writable and can

only be accessed by addressing the SSPBUF register.

Additionally, the MSSP Status register (SSPSTAT)

indicates the various status conditions.

EXAMPLE 17-1:

LOADING THE SSPBUF (SSPSR) REGISTER

LOOP

BTFSS

BRA

SSPSTAT, BF

LOOP

;Has data been received(transmit complete)?

;No

MOVF

SSPBUF, W

;WREG reg = contents of SSPBUF

MOVWF

RXDATA

;Save in user RAM, if data is meaningful

MOVF

MOVWF

TXDATA, W

SSPBUF

;W reg = contents of TXDATA

;New data to xmit

DS30491C-page 192

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

17.3.3

ENABLING SPI I/O

17.3.4

TYPICAL CONNECTION

To enable the serial port, SSP Enable bit, SSPEN

(SSPCON1<5>), must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, reinitialize the

SSPCON registers and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial

port pins. For the pins to behave as the serial port func-

tion, some must have their data direction bits (in the

TRIS register) appropriately programmed as follows:

Figure 17-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge and latched on the opposite edge

of the clock. Both processors should be programmed to

the same Clock Polarity (CKP), then both controllers

would send and receive data at the same time.

Whether the data is meaningful (or dummy data)

depends on the application software. This leads to

three scenarios for data transmission:

• SDI is automatically controlled by the SPI module

• SDO must have TRISC<5> bit cleared

• SCK (Master mode) must have TRISC<3> bit

cleared

• Master sends data - Slave sends dummy data

• Master sends data - Slave sends data

• SCK (Slave mode) must have TRISC<3> bit set

• SS must have TRISF<7> bit set

• Master sends dummy data - Slave sends data

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

FIGURE 17-2:

SPI MASTER/SLAVE CONNECTION

SPI Master SSPM3:SSPM0 = 00xxb

SPI Slave SSPM3:SSPM0 = 010xb

SDO

SDI

Serial Input Buffer

(SSPBUF)

Serial Input Buffer

(SSPBUF)

SDI

SDO

Shift Register

(SSPSR)

Shift Register

(SSPSR)

LSb

MSb

LSb

Serial Clock

SCK

PROCESSOR 1

PROCESSOR 2

 2004 Microchip Technology Inc.

DS30491C-page 193

PIC18F6585/8585/6680/8680

Figure 17-3, Figure 17-5 and Figure 17-6, where the

MSB is transmitted first. In Master mode, the SPI clock

rate (bit rate) is user programmable to be one of the

following:

17.3.5

MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 17-2) is to

broadcast data by the software protocol.

• FOSC/4 (or TCY)

• FOSC/16 (or 4 • TCY)

• FOSC/64 (or 16 • TCY)

• Timer2 output/2

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI is

only going to receive, the SDO output could be dis-

abled (programmed as an input). The SSPSR register

will continue to shift in the signal present on the SDI pin

at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and status bits

appropriately set). This could be useful in receiver

applications as a “Line Activity Monitor” mode.

This allows a maximum data rate (at 40 MHz) of

10.00 Mbps.

Figure 17-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

data is shown.

The clock polarity is selected by appropriately program-

ming the CKP bit (SSPCON1<4>). This then, would

give waveforms for SPI communication, as shown in

FIGURE 17-3:

SPI MODE WAVEFORM (MASTER MODE)

Write to

SSPBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 Clock

Modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

(CKE = 0)

bit 7

bit 3

SDO

(CKE = 1)

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit 0

bit 7

Input

Sample

(SMP = 1)

SSPIF

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

DS30491C-page 194

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

the SS pin goes high, the SDO pin is no longer driven

even if in the middle of a transmitted byte and becomes

a floating output. External pull-up/pull-down resistors

may be desirable depending on the application.

17.3.6

SLAVE MODE

In Slave mode, the data is transmitted and received as

the external clock pulses appear on SCK. When the

last bit is latched, the SSPIF interrupt flag bit is set.

Note 1: When the SPI is in Slave mode with SS pin

control enabled (SSPCON<3:0> = 0100),

the SPI module will reset if the SS pin is set

to VDD.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

2: If the SPI is used in Slave mode with CKE

set, then the SS pin control must be

enabled.

While in Sleep mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from Sleep.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

17.3.7

SLAVE SELECT

SYNCHRONIZATION

The SS pin allows a Synchronous Slave mode. The SPI

must be in Slave mode with SS pin control enabled

(SSPCON1<3:0> = 04h). The pin must not be driven

low for the SS pin to function as an input. The data latch

must be high. When the SS pin is low, transmission and

reception are enabled and the SDO pin is driven. When

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver, the SDO pin can be configured

as an input. This disables transmissions from the SDO.

The SDI can always be left as an input (SDI function)

since it cannot create a bus conflict.

FIGURE 17-4:

SLAVE SYNCHRONIZATION WAVEFORM

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit 6

bit 7

bit 0

SDO

bit 7

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

 2004 Microchip Technology Inc.

DS30491C-page 195

PIC18F6585/8585/6680/8680

FIGURE 17-5:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS

Optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

bit 3

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 Cycle

SSPSR to

SSPBUF

after Q2↓

FIGURE 17-6:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS

Not Optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPBUF

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

bit 3

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

DS30491C-page 196

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

17.3.8

SLEEP OPERATION

17.3.10 BUS MODE COMPATIBILITY

In Master mode, all module clocks are halted and the

transmission/reception will remain in that state until the

device wakes from Sleep. After the device returns to

normal mode, the module will continue to

transmit/receive data.

Table 17-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

TABLE 17-1: SPI BUS MODES

In Slave mode, the SPI Transmit/Receive Shift register

operates asynchronously to the device. This allows the

device to be placed in Sleep mode and data to be

shifted into the SPI Transmit/Receive Shift register.

When all 8 bits have been received, the MSSP interrupt

flag bit will be set and if enabled, will wake the device

from Sleep.

Control Bits State

Standard SPI Mode

Terminology

CKP

CKE

0, 0

0, 1

1, 0

1, 1

0

1

0

1

0

17.3.9

EFFECTS OF A RESET

There is also a SMP bit which controls when the data is

sampled.

A Reset disables the MSSP module and terminates the

current transfer.

TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

INT0IF

RBIF

0000 0000 0000 0000

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111

1111 1111 1111 1111

PIE1

IPR1

TRISC

TRISF

PORTC Data Direction Register

TRISF7 TRISF6 TRISF5 TRISF4 TRISF3

Synchronous Serial Port Receive Buffer/Transmit Register

TRISF2

TRISF1 TRISF0 1111 1111 uuuu uuuu

xxxx xxxx uuuu uuuu

SSPBUF

SSPCON

SSPSTAT

Legend:

WCOL

SMP

SSPOV

CKE

SSPEN

D/A

CKP

P

SSPM3

S

SSPM2

R/W

SSPM1 SSPM0 0000 0000 0000 0000

UA

BF

0000 0000 0000 0000

x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.

 2004 Microchip Technology Inc.

DS30491C-page 197

PIC18F6585/8585/6680/8680

2

17.4.1

REGISTERS

17.4 I C Mode

The MSSP module has six registers for I²C operation.

These are:

The MSSP module in I²C mode fully implements all

master and slave functions (including general call sup-

port) and provides interrupts on Start and Stop bits in

hardware to determine a free bus (multi-master func-

tion). The MSSP module implements the standard

mode specifications, as well as 7-bit and 10-bit

addressing.

• MSSP Control Register 1 (SSPCON1)

• MSSP Control Register 2 (SSPCON2)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• MSSP Shift Register (SSPSR) – Not directly

accessible

Two pins are used for data transfer:

• Serial clock (SCL) – RC3/SCK/SCL

• Serial data (SDA) – RC4/SDI/SDA

• MSSP Address Register (SSPADD)

SSPCON, SSPCON2 and SSPSTAT are the control

and status registers in I²C mode operation. The

SSPCON and SSPCON2 registers are readable and

writable. The lower six bits of the SSPSTAT are read-

only. The upper two bits of the SSPSTAT are

read/write.

The user must configure these pins as inputs or outputs

through the TRISC<4:3> bits.

FIGURE 17-7:

MSSP BLOCK DIAGRAM

(I²C MODE)

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

Internal

Data Bus

Read

Write

SSPADD register holds the slave device address when

the SSP is configured in I²C Slave mode. When the

SSP is configured in Master mode, the lower seven bits

of SSPADD act as the Baud Rate Generator reload

value.

RC3/SCK/

SCL

SSPBUF Reg

Shift

Clock

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

SSPSR Reg

RC4/

SDI/

SDA

MSb

LSb

Addr Match

Match Detect

SSPADD Reg

During transmission, the SSPBUF is not double-

buffered. A write to SSPBUF will write to both SSPBUF

and SSPSR.

Set, Reset

S, P bits

(SSPSTAT Reg)

Start and

Stop bit Detect

DS30491C-page 198

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I²C MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

bit 7

bit 6

bit 5

SMP: Slew Rate Control bit

In Master or Slave mode:

1= Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)

0= Slew rate control enabled for High-Speed mode (400 kHz)

CKE: SMBus Select bit

In Master or Slave mode:

1= Enable SMBus specific inputs

0= Disable SMBus specific inputs

D/A: Data/Address bit

In Master mode:

Reserved.

In Slave mode:

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

bit 4

bit 3

bit 2

P: Stop bit

1= Indicates that a Stop bit has been detected last

0= Stop bit was not detected last

Note:

This bit is cleared on Reset and when SSPEN is cleared.

S: Start bit

1= Indicates that a Start bit has been detected last

0= Start bit was not detected last

Note:

This bit is cleared on Reset and when SSPEN is cleared.

R/W: Read/Write bit Information (I²C mode only)

In Slave mode:

1= Read

0= Write

Note:

This bit holds the R/W bit information following the last address match. This bit is

only valid from the address match to the next Start bit, Stop bit or not ACK bit.

In Master mode:

1= Transmit is in progress

0= Transmit is not in progress

Note:

ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is

in Idle mode.

bit 1

bit 0

UA: Update Address bit (10-bit Slave mode only)

1= Indicates that the user needs to update the address in the SSPADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

In Transmit mode:

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

In Receive mode:

1= Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full

0= Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

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REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I²C MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

WCOL: Write Collision Detect bit

In Master Transmit mode:

1= A write to the SSPBUF register was attempted while the I²C conditions were not valid for

a transmission to be started (must be cleared in software)

0= No collision

In Slave Transmit mode:

1= The SSPBUF register is written while it is still transmitting the previous word (must be

cleared in software)

0= No collision

In Receive mode (Master or Slave modes):

This is a “don’t care” bit.

bit 6

SSPOV: Receive Overflow Indicator bit

In Receive mode:

1= A byte is received while the SSPBUF register is still holding the previous byte (must be

cleared in software)

0= No overflow

In Transmit mode:

This is a “don’t care” bit in Transmit mode.

bit 5

bit 4

SSPEN: Synchronous Serial Port Enable bit

1= Enables the serial port and configures the SDA and SCL pins as the serial port pins

0= Disables serial port and configures these pins as I/O port pins

Note:

When enabled, the SDA and SCL pins must be properly configured as input or

output.

CKP: SCK Release Control bit

In Slave mode:

1= Release clock

0= Holds clock low (clock stretch), used to ensure data setup time

In Master mode:

Unused in this mode.

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

1111= I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

1110= I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1011= I²C Firmware Controlled Master mode (slave Idle)

1000= I²C Master mode, clock = FOSC/(4 * (SSPADD + 1))

0111= I²C Slave mode, 10-bit address

0110= I²C Slave mode, 7-bit address

Note:

Bit combinations not specifically listed here are either reserved or implemented in

SPI mode only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 200

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I²C MODE)

R/W-0

GCEN

R/W-0

RCEN

R/W-0

PEN

R/W-0

RSEN

R/W-0

SEN

ACKSTAT

ACKDT

ACKEN

bit 7

bit 0

bit 7

bit 6

bit 5

GCEN: General Call Enable bit (Slave mode only)

1= Enable interrupt when a general call address (0000h) is received in the SSPSR

0= General call address disabled

ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

1= Acknowledge was not received from slave

0= Acknowledge was received from slave

ACKDT: Acknowledge Data bit (Master Receive mode only)

1= Not Acknowledge

0= Acknowledge

Note:

Value that will be transmitted when the user initiates an Acknowledge sequence at

the end of a receive.

bit 4

ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)

1= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.

Automatically cleared by hardware.

0= Acknowledge sequence Idle

bit 3

bit 2

bit 1

bit 0

RCEN: Receive Enable bit (Master Mode only)

1= Enables Receive mode for I²C

0= Receive Idle

PEN: Stop Condition Enable bit (Master mode only)

1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0= Stop condition Idle

RSEN: Repeated Start Condition Enabled bit (Master mode only)

1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0= Repeated Start condition Idle

SEN: Start Condition Enabled/Stretch Enabled bit

In Master mode:

1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0= Start condition Idle

In Slave mode:

1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0= Clock stretching is disabled

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Note:

For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I²C module is not in the Idle mode,

this bit may not be set (no spooling) and the SSPBUF may not be written (or writes

to the SSPBUF are disabled).

 2004 Microchip Technology Inc.

DS30491C-page 201

PIC18F6585/8585/6680/8680

17.4.2

OPERATION

17.4.3.1

Addressing

The MSSP module functions are enabled by setting

MSSP Enable bit, SSPEN (SSPCON<5>).

The SSPCON1 register allows control of the I²C oper-

ation. Four mode selection bits (SSPCON<3:0>) allow

one of the following I²C modes to be selected:

• I²C Master mode, clock = OSC/4 (SSPADD + 1)

• I²C Slave mode (7-bit address)

• I²C Slave mode (10-bit address)

Once the MSSP module has been enabled, it waits for

a Start condition to occur. Following the Start condition,

the 8 bits are shifted into the SSPSR register. All incom-

ing bits are sampled with the rising edge of the clock

(SCL) line. The value of register SSPSR<7:1> is com-

pared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match and the BF

and SSPOV bits are clear, the following events occur:

• I²C Slave mode (7-bit address) with Start and

Stop bit interrupts enabled

• I²C Slave mode (10-bit address) with Start and

Stop bit interrupts enabled

• I²C Firmware Controlled Master mode, slave is

Idle

Selection of any I²C mode with the SSPEN bit set,

forces the SCL and SDA pins to be open-drain, pro-

vided these pins are programmed to inputs by setting

the appropriate TRISC bits. To ensure proper operation

of the module, pull-up resistors must be provided

externally to the SCL and SDA pins.

1. The SSPSR register value is loaded into the

SSPBUF register.

2. The buffer full bit BF is set.

3. An ACK pulse is generated.

4. MSSP interrupt flag bit, SSPIF (PIR1<3>), is set

(interrupt is generated, if enabled) on the falling

edge of the ninth SCL pulse.

In 10-bit Address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit R/W (SSPSTAT<2>) must specify a write

so the slave device will receive the second address

byte. For a 10-bit address, the first byte would equal

‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two

MSbs of the address. The sequence of events for

10-bit address is as follows, with steps 7 through 9 for

the slave-transmitter:

17.4.3

SLAVE MODE

In Slave mode, the SCL and SDA pins must be config-

ured as inputs (TRISC<4:3> set). The MSSP module

will override the input state with the output data when

required (slave-transmitter).

The I²C Slave mode hardware will always generate an

interrupt on an address match. Through the mode

select bits, the user can also choose to interrupt on

Start and Stop bits

1. Receive first (high) byte of address (bits SSPIF,

BF and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

When an address is matched or the data transfer after

an address match is received, the hardware automati-

cally will generate the Acknowledge (ACK) pulse and

load the SSPBUF register with the received value

currently in the SSPSR register.

3. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

4. Receive second (low) byte of address (bits

SSPIF, BF, and UA are set).

5. Update the SSPADD register with the first (high)

byte of address. If match releases SCL line, this

will clear bit UA.

Any combination of the following conditions will cause

the MSSP module not to give this ACK pulse:

6. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

• The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

7. Receive Repeated Start condition.

• The overflow bit SSPOV (SSPCON<6>) was set

before the transfer was received.

8. Receive first (high) byte of address (bits SSPIF

and BF are set).

In this case, the SSPSR register value is not loaded

into the SSPBUF but bit SSPIF (PIR1<3>) is set. The

BF bit is cleared by reading the SSPBUF register while

bit SSPOV is cleared through software.

9. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

I²C specification, as well as the requirement of the

MSSP module, are shown in timing parameter #100

and parameter #101.

DS30491C-page 202

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

17.4.3.2

Reception

17.4.3.3

Transmission

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

register is cleared. The received address is loaded into

the SSPBUF register and the SDA line is held low

(ACK).

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin RC3/SCK/SCL is held

low, regardless of SEN (see Section 17.4.4 “Clock

Stretching” for more detail). By stretching the clock,

the master will be unable to assert another clock pulse

until the slave is done preparing the transmit data. The

transmit data must be loaded into the SSPBUF register

which also loads the SSPSR register. Then pin RC3/

SCK/SCL should be enabled by setting bit CKP

(SSPCON1<4>). The eight data bits are shifted out on

the falling edge of the SCL input. This ensures that the

SDA signal is valid during the SCL high time

(Figure 17-9).

When the address byte overflow condition exists, then

the no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF (SSPSTAT<0>) is

set or bit SSPOV (SSPCON1<6>) is set.

An MSSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-

ware. The SSPSTAT register is used to determine the

status of the byte.

If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL

will be held low (clock stretch) following each data

transfer. The clock must be released by setting bit

CKP (SSPCON<4>). See Section 17.4.4 “Clock

Stretching” for more detail.

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. If the SDA

line is high (not ACK), then the data transfer is com-

plete. In this case, when the ACK is latched by the

slave, the slave logic is reset (resets SSPSTAT regis-

ter) and the slave monitors for another occurrence of

the Start bit. If the SDA line was low (ACK), the next

transmit data must be loaded into the SSPBUF register.

Again, pin RC3/SCK/SCL must be enabled by setting

bit CKP.

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

 2004 Microchip Technology Inc.

DS30491C-page 203

PIC18F6585/8585/6680/8680

2

FIGURE 17-8:

I C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)

DS30491C-page 204

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

2

FIGURE 17-9:

I C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)

 2004 Microchip Technology Inc.

DS30491C-page 205

PIC18F6585/8585/6680/8680

FIGURE 17-10:

I²C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)

DS30491C-page 206

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

2

FIGURE 17-11:

I C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

 2004 Microchip Technology Inc.

DS30491C-page 207

PIC18F6585/8585/6680/8680

17.4.4

CLOCK STRETCHING

17.4.4.3

Clock Stretching for 7-bit Slave

Transmit Mode

Both 7- and 10-bit Slave modes implement automatic

clock stretching during a transmit sequence.

7-bit Slave Transmit mode implements clock stretching

by clearing the CKP bit after the falling edge of the ninth

clock, if the BF bit is clear. This occurs regardless of the

state of the SEN bit.

The SEN bit (SSPCON2<0>) allows clock stretching to

be enabled during receives. Setting SEN will cause the

SCL pin to be held low at the end of each data receive

sequence.

The user’s ISR must set the CKP bit before transmis-

sion is allowed to continue. By holding the SCL line low,

the user has time to service the ISR and load the con-

tents of the SSPBUF before the master device can

initiate another transmit sequence (see Figure 17-9).

17.4.4.1

Clock Stretching for 7-bit Slave

Receive Mode (SEN = 1)

In 7-bit Slave Receive mode, on the falling edge of the

ninth clock at the end of the ACK sequence if the BF bit

is set, the CKP bit in the SSPCON1 register is automat-

ically cleared, forcing the SCL output to be held low.

The CKP being cleared to ‘0’ will assert the SCL line

low. The CKP bit must be set in the user’s ISR before

reception is allowed to continue. By holding the SCL

line low, the user has time to service the ISR and read

the contents of the SSPBUF before the master device

can initiate another receive sequence. This will prevent

buffer overruns from occurring (see Figure 17-13).

Note 1: If the user loads the contents of SSPBUF,

setting the BF bit before the falling edge of

the ninth clock, the CKP bit will not be

cleared and clock stretching will not occur.

2: The CKP bit can be set in software

regardless of the state of the BF bit.

17.4.4.4

Clock Stretching for 10-bit Slave

Transmit Mode

In 10-bit Slave Transmit mode, clock stretching is

controlled during the first two address sequences by

the state of the UA bit, just as it is in 10-bit Slave

Receive mode. The first two addresses are followed by

a third address sequence which contains the high order

bits of the 10-bit address and the R/W bit set to ‘1’. After

the third address sequence is performed, the UA bit is

not set, the module is now configured in Transmit

mode, and clock stretching is controlled by the BF flag

as in 7-bit Slave Transmit mode (see Figure 17-11).

Note 1: If the user reads the contents of the

SSPBUF before the falling edge of the

ninth clock, thus clearing the BF bit, the

CKP bit will not be cleared and clock

stretching will not occur.

2: The CKP bit can be set in software

regardless of the state of the BF bit. The

user should be careful to clear the BF bit

in the ISR before the next receive

sequence in order to prevent an overflow

condition.

17.4.4.2

Clock Stretching for 10-bit Slave

Receive Mode (SEN = 1)

In 10-bit Slave Receive mode, during the address

sequence, clock stretching automatically takes place

but CKP is not cleared. During this time, if the UA bit is

set after the ninth clock, clock stretching is initiated.

The UA bit is set after receiving the upper byte of the

10-bit address and following the receive of the second

byte of the 10-bit address with the R/W bit cleared to

‘0’. The release of the clock line occurs upon updating

SSPADD. Clock stretching will occur on each data

receive sequence as described in 7-bit mode.

Note:

If the user polls the UA bit and clears it by

updating the SSPADD register before the

falling edge of the ninth clock occurs and if

the user hasn’t cleared the BF bit by read-

ing the SSPBUF register before that time,

then the CKP bit will still NOT be asserted

low. Clock stretching on the basis of the

state of the BF bit only occurs during a

data sequence, not an address sequence.

DS30491C-page 208

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

until an external I²C master device has already

asserted the SCL line. The SCL output will remain low

until the CKP bit is set and all other devices on the I²C

bus have deasserted SCL. This ensures that a write to

the CKP bit will not violate the minimum high time

requirement for SCL (see Figure 17-12).

17.4.4.5

Clock Synchronization and

the CKP bit

When the CKP bit is cleared, the SCL output is forced

to ‘0’. However, setting the CKP bit will not assert the

SCL output low until the SCL output is already sampled

low. Therefore, the CKP bit will not assert the SCL line

FIGURE 17-12:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX-1

Master device

asserts clock

CKP

Master device

deasserts clock

WR

SSPCON

 2004 Microchip Technology Inc.

DS30491C-page 209

PIC18F6585/8585/6680/8680

2

FIGURE 17-13:

I C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)

DS30491C-page 210

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 17-14:

I²C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)

 2004 Microchip Technology Inc.

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If the general call address matches, the SSPSR is

transferred to the SSPBUF, the BF flag bit is set (eighth

bit) and on the falling edge of the ninth bit (ACK bit), the

SSPIF interrupt flag bit is set.

17.4.5

GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I²C bus is such that

the first byte after the Start condition usually

determines which device will be the slave addressed by

the master. The exception is the general call address

which can address all devices. When this address is

used, all devices should, in theory, respond with an

Acknowledge.

When the interrupt is serviced, the source for the inter-

rupt can be checked by reading the contents of the

SSPBUF. The value can be used to determine if the

address was device specific or a general call address.

In 10-bit mode, the SSPADD is required to be updated

for the second half of the address to match and the UA

bit is set (SSPSTAT<1>). If the general call address is

sampled when the GCEN bit is set while the slave is

configured in 10-bit Address mode, then the second

half of the address is not necessary, the UA bit will not

be set and the slave will begin receiving data after the

Acknowledge (Figure 17-15).

The general call address is one of eight addresses

reserved for specific purposes by the I²C protocol. It

consists of all ‘0’s with R/W = 0.

The general call address is recognized when the Gen-

eral Call Enable bit (GCEN) is enabled (SSPCON2<7>

is set). Following a Start bit detect, 8 bits are shifted into

the SSPSR and the address is compared against the

SSPADD. It is also compared to the general call

address and fixed in hardware.

FIGURE 17-15:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

(7 OR 10-BIT ADDRESS MODE)

Address is compared to General Call Address

after ACK, set interrupt

Receiving Data

D5 D4 D3 D2 D1

ACK

R/W = 0

General Call Address

ACK

9

SDA

SCL

D7 D6

D0

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

9

S

SSPIF

BF (SSPSTAT<0>)

Cleared in software

SSPBUF is read

SSPOV (SSPCON1<6>)

GCEN (SSPCON2<7>)

‘0’

‘1’

DS30491C-page 212

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17.4.6

MASTER MODE

Note:

The MSSP module, when configured in

I²C Master mode, does not allow queueing

of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPBUF register to

initiate transmission before the Start condi-

tion is complete. In this case, the SSPBUF

will not be written to and the WCOL bit will

be set, indicating that a write to the

SSPBUF did not occur.

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON1 and by setting the

SSPEN bit. In Master mode, the SCL and SDA lines

are manipulated by the MSSP hardware.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop

conditions. The Stop (P) and Start (S) bits are cleared

from a Reset or when the MSSP module is disabled.

Control of the I²C bus may be taken when the P bit is

set or the bus is Idle, with both the S and P bits clear.

The following events will cause SSP interrupt flag bit,

SSPIF, to be set (SSP interrupt if enabled):

In Firmware Controlled Master mode, user code

conducts all I²C bus operations based on Start and

Stop bit conditions.

• Start Condition

• Stop Condition

Once Master mode is enabled, the user has six

options.

• Data Transfer Byte Transmitted/Received

• Acknowledge Transmit

• Repeated Start

1. Assert a Start condition on SDA and SCL.

2. Assert a Repeated Start condition on SDA and

SCL.

3. Write to the SSPBUF register initiating

transmission of data/address.

4. Configure the I²C port to receive data.

5. Generate an Acknowledge condition at the end

of a received byte of data.

6. Generate a Stop condition on SDA and SCL.

2

FIGURE 17-16:

MSSP BLOCK DIAGRAM (I C MASTER MODE)

Internal

Data Bus

SSPM3:SSPM0

SSPADD<6:0>

Read

Write

SSPBUF

SSPSR

Baud

Rate

Generator

SDA

Shift

Clock

SDA In

MSb

LSb

Start bit, Stop bit,

Acknowledge

Generate

SCL

Start bit Detect

Stop bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

end of XMIT/RCV

SCL In

Bus Collision

Set/Reset S, P, WCOL (SSPSTAT)

Set SSPIF, BCLIF

Reset ACKSTAT, PEN (SSPCON2)

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I²C Master Mode Operation

A typical transmit sequence would go as follows:

17.4.6.1

1. The user generates a Start condition by setting

the Start enable bit, SEN (SSPCON2<0>).

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I²C bus will

not be released.

2. SSPIF is set. The MSSP module will wait the

required start time before any other operation

takes place.

3. The user loads the SSPBUF with the slave

address to transmit.

In Master Transmitter mode, serial data is output

through SDA while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic ‘0’. Serial data is

transmitted 8 bits at a time. After each byte is transmit-

ted, an Acknowledge bit is received. Start and Stop

conditions are output to indicate the beginning and the

end of a serial transfer.

4. Address is shifted out the SDA pin until all 8 bits

are transmitted.

5. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

6. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

In Master Receive mode, the first byte transmitted con-

tains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic ‘1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate a receive bit. Serial

data is received via SDA while SCL outputs the serial

clock. Serial data is received 8 bits at a time. After each

byte is received, an Acknowledge bit is transmitted.

Start and Stop conditions indicate the beginning and

end of transmission.

7. The user loads the SSPBUF with eight bits of

data.

8. Data is shifted out the SDA pin until all 8 bits are

transmitted.

9. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

10. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

The Baud Rate Generator used for the SPI mode

operation is used to set the SCL clock frequency for

either 100 kHz, 400 kHz or 1 MHz I²C operation. See

Section 17.4.7 “Baud Rate Generator” for more

detail.

11. The user generates a Stop condition by setting

the Stop enable bit PEN (SSPCON2<2>).

12. Interrupt is generated once the Stop condition is

complete.

DS30491C-page 214

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Once the given operation is complete (i.e., transmis-

sion of the last data bit is followed by ACK), the internal

clock will automatically stop counting and the SCL pin

will remain in its last state.

17.4.7

BAUD RATE GENERATOR

In I²C Master mode, the Baud Rate Generator (BRG)

reload value is placed in the lower 7 bits of the

SSPADD register (Figure 17-17). When a write occurs

to SSPBUF, the Baud Rate Generator will automatically

begin counting. The BRG counts down to ‘0’ and stops

until another reload has taken place. The BRG count is

decremented twice per instruction cycle (TCY) on the

Q2 and Q4 clocks. In I²C Master mode, the BRG is

reloaded automatically.

Table 17-3 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

FIGURE 17-17:

BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM3:SSPM0

SSPADD<6:0>

SSPM3:SSPM0

SCL

Reload

Control

Reload

BRG Down Counter

CLKO

FOSC/4

TABLE 17-3: I²C CLOCK RATE w/BRG

FSCL

FCY

FCY*2

BRG Value

(2 Rollovers of BRG)

10 MHz

4 MHz

1 MHz

20 MHz

8 MHz

2 MHz

19h

20h

64h

0Ah

0Dh

28h

03h

0Ah

00h

400 kHz⁽¹⁾

312.5 kHz

100 kHz

400 kHz⁽¹⁾

308 kHz

100 kHz

333 kHz⁽¹⁾

100 kHz

1 MHz⁽¹⁾

Note 1: The I²C interface does not conform to the 400 kHz I²C specification (which applies to rates greater than

100 kHz) in all details but may be used with care where higher rates are required by the application.

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SCL pin is sampled high, the Baud Rate Generator is

reloaded with the contents of SSPADD<6:0> and

begins counting. This ensures that the SCL high time

will always be at least one BRG rollover count in the

event that the clock is held low by an external device

(Figure 17-18).

17.4.7.1

Clock Arbitration

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

deasserts the SCL pin (SCL allowed to float high).

When the SCL pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting

until the SCL pin is actually sampled high. When the

FIGURE 17-18:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

DX

DX-1

SCL allowed to transition high

SCL deasserted but slave holds

SCL low (clock arbitration)

SCL

BRG decrements on

Q2 and Q4 cycles

BRG

Value

03h

02h

01h

00h (hold off)

03h

02h

SCL is sampled high, reload takes

place and BRG starts its count

BRG

Reload

DS30491C-page 216

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17.4.8

I²C MASTER MODE START

CONDITION TIMING

17.4.8.1

WCOL Status Flag

If the user writes the SSPBUF when a Start sequence

is in progress, the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

To initiate a Start condition, the user sets the Start Con-

dition Enable bit, SEN (SSPCON2<0>). If the SDA and

SCL pins are sampled high, the Baud Rate Generator

is reloaded with the contents of SSPADD<6:0> and

starts its count. If SCL and SDA are both sampled high

when the Baud Rate Generator times out (TBRG), the

SDA pin is driven low. The action of the SDA being

driven low while SCL is high is the Start condition and

causes the S bit (SSPSTAT<3>) to be set. Following

this, the Baud Rate Generator is reloaded with the

contents of SSPADD<6:0> and resumes its count.

When the Baud Rate Generator times out (TBRG), the

SEN bit (SSPCON2<0>) will be automatically cleared

by hardware, the Baud Rate Generator is suspended,

leaving the SDA line held low and the Start condition is

complete.

Note:

Because queueing of events is not

allowed, writing to the lower 5 bits of

SSPCON2 is disabled until the Start

condition is complete.

Note:

If at the beginning of the Start condition,

the SDA and SCL pins are already sam-

pled low or if during the Start condition, the

SCL line is sampled low before the SDA

line is driven low, a bus collision occurs,

the Bus Collision Interrupt Flag, BCLIF, is

set, the Start condition is aborted and the

I²C module is reset into its Idle state.

FIGURE 17-19:

FIRST START BIT TIMING

Set S bit (SSPSTAT<3>)

At completion of Start bit,

Write to SEN bit occurs here

SDA = 1,

SCL = 1

hardware clears SEN bit

and sets SSPIF bit

TBRG

Write to SSPBUF occurs here

1st bit

2nd bit

SDA

TBRG

SCL

TBRG

S

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I²C MASTER MODE REPEATED

START CONDITION TIMING

Immediately following the SSPIF bit getting set, the

user may write the SSPBUF with the 7-bit address in

7-bit mode, or the default first address in 10-bit mode.

After the first eight bits are transmitted and an ACK is

received, the user may then transmit an additional eight

bits of address (10-bit mode) or eight bits of data (7-bit

mode).

17.4.9

A Repeated Start condition occurs when the RSEN bit

(SSPCON2<1>) is programmed high and the I²C logic

module is in the Idle state. When the RSEN bit is set,

the SCL pin is asserted low. When the SCL pin is

sampled low, the Baud Rate Generator is loaded with

the contents of SSPADD<5:0> and begins counting.

The SDA pin is released (brought high) for one Baud

Rate Generator count (TBRG). When the Baud Rate

Generator times out, if SDA is sampled high, the SCL

pin will be deasserted (brought high). When SCL is

sampled high, the Baud Rate Generator is reloaded

with the contents of SSPADD<6:0> and begins count-

ing. SDA and SCL must be sampled high for one TBRG.

This action is then followed by assertion of the SDA pin

(SDA = 0) for one TBRG while SCL is high. Following

this, the RSEN bit (SSPCON2<1>) will be automatically

cleared and the Baud Rate Generator will not be

reloaded, leaving the SDA pin held low. As soon as a

Start condition is detected on the SDA and SCL pins,

the S bit (SSPSTAT<3>) will be set. The SSPIF bit will

notbesetuntiltheBaudRateGeneratorhastimedout.

17.4.9.1

WCOL Status Flag

If the user writes the SSPBUF when a Repeated Start

sequence is in progress, the WCOL is set and the con-

tents of the buffer are unchanged (the write doesn’t

occur).

Note:

Because queueing of events is not

allowed, writing of the lower 5 bits of

SSPCON2 is disabled until the Repeated

Start condition is complete.

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated Start

condition occurs if:

• SDA is sampled low when SCL goes

from low-to-high.

• SCL goes low before SDA is

asserted low. This may indicate that

another master is attempting to

transmit a data ‘1’.

FIGURE 17-20:

REPEAT START CONDITION WAVEFORM

Set S (SSPSTAT<3>)

Write to SSPCON2

occurs here.

SDA = 1,

SCL (no change).

SDA = 1,

SCL = 1

At completion of Start bit,

hardware clears RSEN bit

and sets SSPIF

TBRG

1st bit

SDA

Write to SSPBUF occurs here

TBRG

Falling edge of ninth clock,

end of Xmit

SCL

TBRG

Sr = Repeated Start

DS30491C-page 218

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17.4.10 I²C MASTER MODE

TRANSMISSION

17.4.10.3 ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is

cleared when the slave has sent an Acknowledge

(ACK = 0) and is set when the slave does not Acknowl-

edge (ACK = 1). A slave sends an Acknowledge when

it has recognized its address (including a general call)

or when the slave has properly received its data.

Transmission of a data byte, a 7-bit address, or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPBUF register. This action will

set the Buffer Full flag bit, BF and allow the Baud Rate

Generator to begin counting and start the next trans-

mission. Each bit of address/data will be shifted out

onto the SDA pin after the falling edge of SCL is

asserted (see data hold time specification parameter

#106). SCL is held low for one Baud Rate Generator

rollover count (TBRG). Data should be valid before SCL

is released high (see data setup time specification

parameter #107). When the SCL pin is released high, it

is held that way for TBRG. The data on the SDA pin

must remain stable for that duration and some hold

time after the next falling edge of SCL. After the eighth

bit is shifted out (the falling edge of the eighth clock),

the BF flag is cleared and the master releases SDA.

This allows the slave device being addressed to

respond with an ACK bit during the ninth bit time if an

address match occurred, or if data was received

properly. The status of ACK is written into the ACKDT

bit on the falling edge of the ninth clock. If the master

receives an Acknowledge, the Acknowledge Status bit,

ACKSTAT, is cleared. If not, the bit is set. After the ninth

clock, the SSPIF bit is set and the master clock (Baud

Rate Generator) is suspended until the next data byte

is loaded into the SSPBUF, leaving SCL low and SDA

unchanged (Figure 17-21).

17.4.11 I²C MASTER MODE RECEPTION

Master mode reception is enabled by programming the

receive enable bit, RCEN (SSPCON2<3>).

Note:

The MSSP module must be in an Idle state

before the RCEN bit is set or the RCEN bit

will be disregarded.

The Baud Rate Generator begins counting and on each

rollover, the state of the SCL pin changes (high-to-low/

low-to-high) and data is shifted into the SSPSR. After the

falling edge of the eighth clock, the receive enable flag is

automatically cleared, the contents of the SSPSR are

loaded into the SSPBUF, the BF flag bit is set, the SSPIF

flag bit is set and the Baud Rate Generator is suspended

from counting, holding SCL low. The MSSP is now in Idle

state awaiting the next command. When the buffer is

read by the CPU, the BF flag bit is automatically cleared.

The user can then send an Acknowledge bit at the end

of reception by setting the Acknowledge sequence

enable bit, ACKEN (SSPCON2<4>).

17.4.11.1 BF Status Flag

After the write to the SSPBUF, each bit of the address

will be shifted out on the falling edge of SCL until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

deassert the SDA pin, allowing the slave to respond

with an Acknowledge. On the falling edge of the ninth

clock, the master will sample the SDA pin to see if the

address was recognized by a slave. The status of the

ACK bit is loaded into the ACKSTAT status bit

(SSPCON2<6>). Following the falling edge of the ninth

clock transmission of the address, the SSPIF is set, the

BF flag is cleared and the Baud Rate Generator is

turned off until another write to the SSPBUF takes

place, holding SCL low and allowing SDA to float.

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

17.4.11.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bits

are received into the SSPSR and the BF flag bit is

already set from a previous reception.

17.4.11.3 WCOL Status Flag

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), the WCOL bit is set and the contents of the buffer

are unchanged (the write doesn’t occur).

17.4.10.1 BF Status Flag

In Transmit mode, the BF bit (SSPSTAT<0>) is set

when the CPU writes to SSPBUF and is cleared when

all 8 bits are shifted out.

17.4.10.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

WCOL must be cleared in software.

 2004 Microchip Technology Inc.

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2

FIGURE 17-21:

I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

DS30491C-page 220

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2

FIGURE 17-22:

I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

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17.4.12 ACKNOWLEDGE SEQUENCE

TIMING

17.4.13 STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN (SSPCON2<2>). At the end of a receive/

transmit, the SCL line is held low after the falling edge

of the ninth clock. When the PEN bit is set, the master

will assert the SDA line low. When the SDA line is

sampled low, the Baud Rate Generator is reloaded and

counts down to ‘0’. When the Baud Rate Generator

times out, the SCL pin will be brought high and one

TBRG (Baud Rate Generator rollover count) later, the

SDA pin will be deasserted. When the SDA pin is sam-

pled high while SCL is high, the P bit (SSPSTAT<4>) is

set. A TBRG later, the PEN bit is cleared and the SSPIF

bit is set (Figure 17-24).

An Acknowledge sequence is enabled by setting

the Acknowledge Sequence Enable bit, ACKEN

(SSPCON2<4>). When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to gen-

erate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The Baud Rate

Generator then counts for one rollover period (TBRG)

and the SCL pin is deasserted (pulled high). When the

SCL pin is sampled high (clock arbitration), the Baud

Rate Generator counts for TBRG. The SCL pin is then

pulled low. Following this, the ACKEN bit is automatically

cleared, the Baud Rate Generator is turned off and the

MSSP module then goes into Idle mode (Figure 17-23).

17.4.13.1 WCOL Status Flag

If the user writes the SSPBUF when a Stop sequence

is in progress, then the WCOL bit is set and the con-

tents of the buffer are unchanged (the write doesn’t

occur).

17.4.12.1 WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 17-23:

ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,

write to SSPCON2

ACKEN automatically cleared

ACKEN = 1, ACKDT = 0

TBRG

ACK

TBRG

SDA

SCL

D0

8

9

SSPIF

Cleared in

Set SSPIF at the end

of receive

software

Cleared in

software

Set SSPIF at the end

of Acknowledge sequence

Note: TBRG = one Baud Rate Generator period.

FIGURE 17-24:

STOP CONDITION RECEIVE OR TRANSMIT MODE

SCL = 1for TBRG, followed by SDA = 1for TBRG

after SDA sampled high. P bit (SSPSTAT<4>) is set.

Write to SSPCON2,

set PEN

Falling edge of

9th clock

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

TBRG

SCL

SDA

ACK

P

TBRG

SCL brought high after TBRG

SDA asserted low before rising edge of clock

to setup Stop condition

Note: TBRG = one Baud Rate Generator period.

DS30491C-page 222

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17.4.14 SLEEP OPERATION

17.4.17 MULTI -MASTER COMMUNICATION,

While in Sleep mode, the I²C module can receive

addresses or data and when an address match or com-

plete byte transfer occurs, wake the processor from

Sleep (if the MSSP interrupt is enabled).

BUS COLLISION AND

BUS ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a ‘1’ on SDA by letting SDA float high and

another master asserts a ‘0’. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a ‘1’ and the data sampled on the SDA pin = 0,

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag, BCLIF and reset the

I²C port to its Idle state (Figure 17-25).

17.4.15 EFFECT OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

17.4.16 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSP module is disabled. Control of the I²C bus may

be taken when the P bit (SSPSTAT<4>) is set or the

bus is Idle, with both the S and P bits clear. When the

bus is busy, enabling the SSP interrupt will generate

the interrupt when the Stop condition occurs.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are deasserted and the

SSPBUF can be written to. When the user services the

bus collision Interrupt Service Routine and if the I²C

bus is free, the user can resume communication by

asserting a Start condition.

In multi-master operation, the SDA line must be moni-

tored for arbitration to see if the signal level is the

expected output level. This check is performed in

hardware with the result placed in the BCLIF bit.

If a Start, Repeated Start, Stop, or Acknowledge condi-

tion was in progress when the bus collision occurred,

the condition is aborted, the SDA and SCL lines are

deasserted, and the respective control bits in the

SSPCON2 register are cleared. When the user ser-

vices the bus collision Interrupt Service Routine and if

the I²C bus is free, the user can resume communication

by asserting a Start condition.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSPIF bit will be set.

• A Repeated Start Condition

• An Acknowledge Condition

A write to the SSPBUF will start the transmission of

data at the first data bit regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the determi-

nation of when the bus is free. Control of the I²C bus can

be taken when the P bit is set in the SSPSTAT register or

the bus is Idle and the S and P bits are cleared.

FIGURE 17-25:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,

data doesn’t match what is driven

by the master.

SDA line pulled low

by another source

Data changes

while SCL = 0

Bus collision has occurred.

SDA released

by master

SDA

SCL

Set bus collision

interrupt (BCLIF)

BCLIF

 2004 Microchip Technology Inc.

DS30491C-page 223

PIC18F6585/8585/6680/8680

If the SDA pin is sampled low during this count, the

17.4.17.1 Bus Collision During a Start

Condition

BRG is reset and the SDA line is asserted early

(Figure 17-28). If, however, a ‘1’ is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The Baud Rate Generator is then reloaded and

counts down to ‘0’ and during this time, if the SCL pins

are sampled as ‘0’, a bus collision does not occur. At

the end of the BRG count, the SCLpin is asserted low.

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning of

the Start condition (Figure 17-26).

b) SCL is sampled low before SDA is asserted low

(Figure 17-27).

During a Start condition, both the SDA and the SCL

pins are monitored.

Note:

The reason that bus collision is not a factor

during a Start condition is that no two bus

masters can assert a Start condition at the

exact same time. Therefore, one master

will always assert SDA before the other.

This condition does not cause a bus

collision because the two masters must be

allowed to arbitrate the first address follow-

ing the Start condition. If the address is the

same, arbitration must be allowed to

continue into the data portion, Repeated

Start or Stop conditions.

If the SDA pin is already low or the SCL pin is already

low, then all of the following occur:

• the Start condition is aborted,

• the BCLIF flag is set, and

• the MSSP module is reset to its Idle state

(Figure 17-26).

The Start condition begins with the SDA and SCL pins

deasserted. When the SDA pin is sampled high, the

Baud Rate Generator is loaded from SSPADD<6:0>

and counts down to ‘0’. If the SCL pin is sampled low

while SDA is high, a bus collision occurs because it is

assumed that another master is attempting to drive a

data ‘1’ during the Start condition.

FIGURE 17-26:

BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.

Set BCLIF;

S bit and SSPIF set because

SDA = 0, SCL = 1.

SDA

SCL

SEN

Set SEN, enable Start

condition if SDA = 1, SCL = 1

SEN cleared automatically because of bus collision.

SSP module reset into Idle state.

SDA sampled low before

Start condition. Set BCLIF;

S bit and SSPIF set because

SDA = 0, SCL = 1.

BCLIF

SSPIF and BCLIF are

cleared in software

S

SSPIF

SSPIF and BCLIF are

cleared in software

DS30491C-page 224

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 17-27:

BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1

TBRG

SDA

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

SCL

SEN

SCL = 0before SDA = 0,

bus collision occurs. Set BCLIF.

SCL = 0before BRG time-out,

bus collision occurs. Set BCLIF.

BCLIF

Interrupt cleared

in software

S

‘0’

SSPIF

FIGURE 17-28:

BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA = 0, SCL = 1

Set S

Set SSPIF

Less than TBRG

TBRG

SDA pulled low by other master.

Reset BRG and assert SDA.

SDA

SCL

S

SCL pulled low after BRG

Time-out

SEN

Set SEN, enable START

sequence if SDA = 1, SCL = 1

‘0’

BCLIF

S

SSPIF

Interrupts cleared

in software

SDA = 0, SCL = 1,

set SSPIF

 2004 Microchip Technology Inc.

DS30491C-page 225

PIC18F6585/8585/6680/8680

reloaded and begins counting. If SDA goes from high to

17.4.17.2 Bus Collision During a Repeated

Start Condition

low before the BRG times out, no bus collision occurs

because no two masters can assert SDA at exactly the

same time.

During a Repeated Start condition, a bus collision

occurs if:

If SCL goes from high to low before the BRG times out

and SDA has not already been asserted, a bus collision

occurs. In this case, another master is attempting to

transmit a data ‘1’ during the Repeated Start condition

(see Figure 17-30).

a) A low level is sampled on SDA when SCL goes

from low level to high level.

b) SCL goes low before SDA is asserted low,

indicating that another master is attempting to

transmit a data ‘1’.

If, at the end of the BRG time-out, both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated Start condition is

complete.

When the user deasserts SDA and the pin is allowed to

float high, the BRG is loaded with SSPADD<6:0> and

counts down to ‘0’. The SCL pin is then deasserted and

when sampled high, the SDA pin is sampled.

If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, see

Figure 17-29). If SDA is sampled high, the BRG is

FIGURE 17-29:

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.

RSEN

BCLIF

Cleared in software

‘0’

S

‘0’

SSPIF

FIGURE 17-30:

BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG

SDA

SCL

SCL goes low before SDA,

set BCLIF. Release SDA and SCL.

BCLIF

RSEN

Interrupt cleared

in software

‘0’

S

SSPIF

DS30491C-page 226

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

The Stop condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

float. When the pin is sampled high (clock arbitration),

the Baud Rate Generator is loaded with SSPADD<6:0>

and counts down to ‘0’. After the BRG times out, SDA

is sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 17-31). If the SCL pin is

sampled low before SDA is allowed to float high, a bus

collision occurs. This is another case of another master

attempting to drive a data ‘0’ (Figure 17-32).

17.4.17.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDA pin has been deasserted and

allowed to float high, SDA is sampled low after

the BRG has timed out.

b) After the SCL pin is deasserted, SCL is sampled

low before SDA goes high.

FIGURE 17-31:

BUS COLLISION DURING A STOP CONDITION (CASE 1)

SDA sampled

low after TBRG,

set BCLIF

TBRG

SDA

SDA asserted low

SCL

PEN

BCLIF

P

‘0’

SSPIF

FIGURE 17-32:

BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG

SDA

SCL goes low before SDA goes high,

set BCLIF

Assert SDA

SCL

PEN

BCLIF

P

‘0’

SSPIF

 2004 Microchip Technology Inc.

DS30491C-page 227

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 228

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

In order to configure pins RC6/TX/CK and RC7/RX/DT

as the Universal Synchronous Asynchronous Receiver

Transmitter:

18.0 ENHANCED UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

• SPEN (RCSTA<7>) bit must be set (= 1),

• TRISC<6> bit must be set (= 1), and

• TRISC<7> bit must be set (= 1).

The Universal Synchronous Asynchronous Receiver

Transmitter (USART) module is one of the two serial

I/O modules. (USART is also known as a Serial

Communications Interface or SCI.) The USART can be

configured as a full-duplex asynchronous system that

can communicate with peripheral devices, such as

CRT terminals and personal computers. It can also be

configured as a half-duplex synchronous system that

can communicate with peripheral devices, such as A/D

or D/A integrated circuits, serial EEPROMs, etc.

Note:

The USART control will automatically

reconfigure the pin from input to output as

needed.

The operation of the Enhanced USART module is

controlled through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCON)

The Enhanced USART module implements additional

features, including automatic baud rate detection and

calibration, automatic wake-up on sync break reception

and 12-bit break character transmit. These make it

ideally suited for use in Local Interconnect Network bus

(LIN bus) systems.

These are detailed on the following pages in

Register 18-1, Register 18-2 and Register 18-3,

respectively.

The USART can be configured in the following modes:

• Asynchronous (full-duplex) with:

- Auto-wake-up on character reception

- Auto-baud calibration

- 12-bit break character transmission

• Synchronous – Master (half-duplex) with

selectable clock polarity

• Synchronous – Slave (half-duplex) with selectable

clock polarity

 2004 Microchip Technology Inc.

DS30491C-page 229

PIC18F6585/8585/6680/8680

REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0

CSRC

bit 7

R/W-0

TX9

R/W-0

TXEN

R/W-0

SYNC

R/W-0

BRGH

R-1

R/W-0

TX9D

bit 0

SENDB

TRMT

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care.

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

TXEN: Transmit Enable bit

1= Transmit enabled

0= Transmit disabled

Note:

SREN/CREN overrides TXEN in Sync mode.

bit 4

bit 3

SYNC: USART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

SENDB: Send Break Character bit

Asynchronous mode:

1= Send sync break on next transmission (cleared by hardware upon completion)

0= Sync break transmission completed

Synchronous mode:

Don’t care.

bit 2

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode.

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: 9th bit of Transmit Data

Can be address/data bit or a parity bit.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 230

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0

SPEN

R/W-0

RX9

R/W-0

SREN

R/W-0

CREN

R/W-0

R-0

R-x

ADDEN

FERR

OERR

RX9D

bit 7

bit 0

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit

1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0= Serial port disabled (held in Reset)

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care.

Synchronous mode – Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave:

Don’t care.

bit 4

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables receiver

0= Disables receiver

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enables interrupt and loads the receive buffer when RSR<8>

is set

0= Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 9-bit (RX9 = 0):

Don’t care.

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receiving next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: 9th bit of Received Data

This can be an address/data bit or a parity bit and must be calculated by user firmware.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 231

PIC18F6585/8585/6680/8680

REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER

U-0

—

R-1

U-0

—

R/W-0

SCKP

R/W-0

U-0

—

R/W-0

WUE

R/W-0

RCIDL

BRG16

ABDEN

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ‘0’

RCIDL: Receive Operation Idle Status bit

1= Receive operation is Idle

0= Receive operation is active

bit 5

bit 4

Unimplemented: Read as ‘0’

SCKP: Synchronous Clock Polarity Select bit

Asynchronous mode:

Unused in this mode.

Synchronous mode:

1= Idle state for clock (CK) is a high level

0= Idle state for clock (CK) is a low level

bit 3

BRG16: 16-bit Baud Rate Register Enable bit

1= 16-bit Baud Rate Generator – SPBRGH and SPBRG

0= 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored

bit 2

bit 1

Unimplemented: Read as ‘0’

WUE: Wake-up Enable bit

Asynchronous mode:

1= USART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared

in hardware on following rising edge

0= RX pin not monitored or rising edge detected

Synchronous mode:

Unused in this mode.

bit 0

ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:

1= Enable baud rate measurement on the next character – requires reception of a sync field

(55h); cleared in hardware upon completion

0= Baud rate measurement disabled or completed

Synchronous mode:

Unused in this mode.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 232

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

the error in baud rate can be determined. An example

18.1 USART Baud Rate Generator (BRG)

calculation is shown in Example 18-1. Typical baud

rates and error values for the various Asynchronous

modes are shown in Table 18-2. It may be advantageous

to use the high baud rate (BRGH = 1) or the 16-bit BRG

to reduce the baud rate error, or achieve a slow baud

rate for a fast oscillator frequency.

The BRG is a dedicated 8-bit or 16-bit generator that

supports both the Asynchronous and Synchronous

modes of the USART. By default, the BRG operates in

8-bit mode; setting the BRG16 bit (BAUDCON<3>)

selects 16-bit mode.

The SPBRGH:SPBRG register pair controls the period

of a free-running timer. In Asynchronous mode, bits

BRGH (TXSTA<2>) and BRG16 also control the baud

rate. In Synchronous mode, bit BRGH is ignored.

Table 18-1 shows the formula for computation of the

baud rate for different USART modes which only apply

in Master mode (internally generated clock).

Writing a new value to the SPBRGH:SPBRG registers

causes the BRG timer to be reset (or cleared). This

ensures the BRG does not wait for a timer overflow

before outputting the new baud rate.

18.1.1

SAMPLING

The data on the RC7/RX/DT pin is sampled three times

by a majority detect circuit to determine if a high or a

low level is present at the RX pin.

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRGH:SPBRG registers can be

calculated using the formulas in Table 18-1. From this,

TABLE 18-1: BAUD RATE FORMULAS

Configuration Bits

BRG/USART Mode

Baud Rate Formula

FOSC/[64 (n + 1)]

FOSC/[16 (n + 1)]

SYNC

BRG16

BRGH

0

1

0

1

0

1

0

1

0

1

x

8-bit/Asynchronous

16-bit/Asynchronous

8-bit/Synchronous

16-bit/Synchronous

FOSC/[4 (n + 1)]

Legend: x= Don’t care, n = Value of SPBRGH:SPBRG register pair

EXAMPLE 18-1: CALCULATING BAUD RATE ERROR

For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:

Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1))

Solving for SPBRGH:SPBRG:

X

= ((FOSC/Desired Baud Rate)/64) – 1

= ((16000000/9600)/64) – 1

= [25.042] = 25

Calculated Baud Rate= 16000000/(64 (25 + 1))

= 9615

Error

= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate

= (9615 – 9600)/9600 = 0.16%

TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Value on

POR, BOR

Value on all

other Resets

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TXSTA

CSRC

SPEN

—

TX9

RX9

TXEN

SREN

—

SYNC

CREN

SCKP

SENDB

ADDEN

BRG16

BRGH

FERR

—

TRMT

OERR

WUE

TX9D

RX9D

0000 0010

0000 000x

0000 0010

0000 000x

-1-0 0-00

0000 0000

RCSTA

BAUDCON

RCIDL

ABDEN -1-0 0-00

0000 0000

SPBRGH Baud Rate Generator Register, High Byte

SPBRG

Baud Rate Generator Register, Low Byte

x= unknown, -= unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

0000 0000

Legend:

 2004 Microchip Technology Inc.

DS30491C-page 233

PIC18F6585/8585/6680/8680

TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0

BAUD

RATE

(K)

FOSC = 40.000 MHz

FOSC = 20.000 MHz

FOSC = 10.000 MHz

FOSC = 8.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

SPBRG Actual

value

(decimal)

SPBRG Actual

value

(decimal)

SPBRG

value

(decimal)

%

Error

%

Error

%

Error

Rate

(K)

Rate

(K)

Rate

(K)

Error

(decimal)

0.3

1.2

—

255

129

31

15

4

—

129

64

15

7

—

1201

2403

9615

—

-0.16

—

103

51

12

—

1.221

1.73

0.16

1.73

8.51

-9.58

1.202

2.404

9.766

19.531

52.083

78.125

0.16

1.73

-9.58

-32.18

2.4

2.441

9.615

19.531

56.818

125.000

1.73

0.16

1.73

-1.36

8.51

255

64

31

10

4

2.404

9.6

9.766

19.2

57.6

115.2

19.531

62.500

104.167

2

—

2

1

—

SYNC = 0, BRGH = 0, BRG16 = 0

BAUD

RATE

(K)

FOSC = 4.000 MHz

FOSC = 2.000 MHz

FOSC = 1.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

SPBRG Actual

value

(decimal)

SPBRG

value

(decimal)

%

Error

%

Error

Rate

(K)

Rate

(K)

Error

(decimal)

0.3

1.2

0.300

1.202

0.16

207

51

25

6

300

1201

2403

—

-0.16

—

103

25

12

—

300

1201

—

-0.16

—

51

12

—

2.4

2.404

0.16

9.6

8.929

-6.99

8.51

—

19.2

57.6

115.2

20.833

62.500

2

—

8.51

0

—

-45.75

0

—

SYNC = 0, BRGH = 1, BRG16 = 0

BAUD

RATE

(K)

FOSC = 40.000 MHz

FOSC = 20.000 MHz

FOSC = 10.000 MHz

FOSC = 8.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

(decimal)

SPBRG Actual

value

(decimal)

SPBRG Actual

value

(decimal)

SPBRG

value

%

Error

%

Error

%

Error

%

Error

Rate

(K)

Rate

(K)

Rate

(K)

(decimal)

0.3

1.2

—

2.4

—

2.441

9.615

19.531

56.818

125.000

1.73

0.16

1.73

-1.36

8.51

255

64

31

10

4

2403

9615

19230

55555

—

-0.16

3.55

—

207

51

25

8

9.6

9.766

19.231

58.140

113.636

1.73

0.16

0.94

-1.36

255

129

42

9.615

19.231

56.818

113.636

0.16

-1.36

129

64

21

10

19.2

57.6

115.2

21

—

SYNC = 0, BRGH = 1, BRG16 = 0

BAUD

RATE

(K)

FOSC = 4.000 MHz

FOSC = 2.000 MHz

FOSC = 1.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

SPBRG Actual

value

(decimal)

SPBRG

value

(decimal)

%

Error

%

Error

Rate

(K)

Rate

(K)

Error

(decimal)

0.3

1.2

—

207

103

25

12

3

—

1201

2403

9615

—

-0.16

—

103

51

12

—

300

1201

2403

—

-0.16

—

207

51

25

—

1.202

0.16

8.51

2.4

2.404

9.6

9.615

19.2

57.6

115.2

19.231

62.500

125.000

—

1

—

DS30491C-page 234

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 20.000 MHz FOSC = 10.000 MHz

BAUD

RATE

(K)

FOSC = 40.000 MHz

FOSC = 8.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

SPBRG

value

(decimal)

%

Error

%

Error

value

(decimal)

Rate

(K)

value

Rate

(K)

Rate

(K)

Error

(decimal)

0.3

1.2

0.300

1.200

0.00

0.02

0.06

0.16

0.94

-1.36

8332

2082

1040

259

129

42

0.300

1.200

0.02

-0.03

0.16

4165

1041

520

129

64

0.300

1.200

0.02

-0.03

0.16

1.73

-1.36

8.51

2082

520

259

64

300

1201

2403

9615

19230

55555

—

-0.04

-0.16

3.55

—

1665

415

207

51

2.4

2.402

2.399

2.404

9.6

9.615

19.2

57.6

115.2

19.231

58.140

113.636

19.231

56.818

113.636

0.16

19.531

56.818

125.000

31

25

-1.36

21

10

8

21

10

4

—

SYNC = 0, BRGH = 0, BRG16 = 1

BAUD

RATE

(K)

FOSC = 4.000 MHz

FOSC = 2.000 MHz

FOSC = 1.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

SPBRG Actual

value

(decimal)

SPBRG

value

(decimal)

%

Error

%

Error

Rate

(K)

Rate

(K)

Error

(decimal)

0.3

1.2

0.300

1.202

0.04

0.16

8.51

832

207

103

25

12

3

300

1201

2403

9615

—

-0.16

—

415

103

51

12

—

300

1201

2403

—

-0.16

—

207

51

25

—

2.4

2.404

9.6

9.615

19.2

57.6

115.2

19.231

62.500

125.000

—

1

—

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 20.000 MHz FOSC = 10.000 MHz

BAUD

RATE

(K)

FOSC = 40.000 MHz

FOSC = 8.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

SPBRG

value

(decimal)

%

Error

%

Error

value

(decimal)

Rate

(K)

value

Rate

(K)

Rate

(K)

Error

(decimal)

0.3

1.2

0.300

1.200

0.00

0.02

0.06

-0.03

0.35

-0.22

33332

8332

4165

1040

520

0.300

1.200

0.00

0.02

-0.03

0.16

-0.22

0.94

16665

4165

2082

520

259

86

0.300

1.200

0.00

0.02

0.06

0.16

0.94

-1.36

8332

2082

1040

259

129

42

300

1200

-0.01

-0.04

-0.16

0.79

6665

1665

832

207

103

34

2.4

2.400

2.402

2400

9.6

9.606

9.596

9.615

9615

19.2

57.6

115.2

19.193

57.803

114.943

19.231

57.471

116.279

19.231

58.140

113.636

19230

57142

117647

172

86

42

21

-2.12

16

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

BAUD

RATE

(K)

Actual

Rate

(K)

SPBRG Actual

SPBRG

value

(decimal)

%

Error

%

Error

%

Error

value

Rate

(K)

value

Rate

(K)

(decimal)

0.3

1.2

0.300

1.200

0.01

0.04

0.16

2.12

-3.55

3332

832

415

103

51

300

1201

2403

9615

19230

55555

—

-0.04

-0.16

3.55

—

1665

415

207

51

300

1201

2403

9615

19230

—

-0.04

-0.16

—

832

207

103

25

2.4

2.404

9.6

9.615

19.2

57.6

115.2

19.231

58.824

111.111

25

12

16

8

—

8

—

 2004 Microchip Technology Inc.

DS30491C-page 235

PIC18F6585/8585/6680/8680

carry occurred for 8-bit modes by checking for 00h in

the SPBRGH register. Refer to Table 18-4 for counter

clock rates to the BRG.

18.1.2

AUTO-BAUD RATE DETECT

The enhanced USART module supports the automatic

detection and calibration of baud rate. This feature is

active only in Asynchronous mode and while the WUE

bit is clear.

While the ABD sequence takes place, the USART state

machine is held in Idle. The RCIF interrupt is set once

the fifth rising edge on RX is detected. The value in the

RCREG needs to be read to clear the RCIF interrupt.

RCREG content should be discarded.

The automatic baud rate measurement sequence

(Figure 18-1) begins whenever a Start bit is received

and the ABDEN bit is set. The calculation is

self-averaging.

Note 1: If the WUE bit is set with the ABDEN bit,

auto-baud rate detection will occur on the

byte following the break character.

In the Auto-Baud Rate Detect (ABD) mode, the clock to

the BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG. In

ABD mode, the internal Baud Rate Generator is used

as a counter to time the bit period of the incoming serial

byte stream.

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator fre-

quency and USART baud rates are not

possible due to bit error rates. Overall

system timing and communication baud

rates must be taken into consideration

when using the auto-baud rate detection

feature.

Once the ABDEN bit is set, the state machine will clear

the BRG and look for a Start bit. The auto-baud detect

must receive a byte with the value 55h (ASCII “U”,

which is also the LIN bus sync character) in order to

calculate the proper bit rate. The measurement is taken

over both a low and a high bit time in order to minimize

any effects caused by asymmetry of the incoming

signal. After a Start bit, the SPBRG begins counting up

using the preselected clock source on the first rising

edge of RX. After eight bits on the RX pin or the fifth

rising edge, an accumulated value totalling the proper

BRG period is left in the SPBRGH:SPBRG registers.

Once the 5th edge is seen (should correspond to the

Stop bit), the ABDEN bit is automatically cleared.

TABLE 18-4: BRG COUNTER CLOCK

RATES

BRG16 BRGH

BRG Counter Clock

0

1

0

1

FOSC/512

FOSC/128

FOSC/32

0

1

While calibrating the baud rate period, the BRG regis-

ters are clocked at 1/8th the preconfigured clock rate.

Note that the BRG clock will be configured by the

BRG16 and BRGH bits. Independent of the BRG16 bit

setting, both the SPBRG and SPBRGH will be used as

a 16-bit counter. This allows the user to verify that no

1

Note:

During the ABD sequence, SPBRG and

SPBRGH are both used as a 16-bit

counter independent of BRG16 setting.

FIGURE 18-1:

AUTOMATIC BAUD RATE CALCULATION

XXXXh

0000h

001Ch

BRG Value

Edge #2

Bit 3

Edge #3

Bit 5

Edge #4

Bit 7

Bit 6

Edge #5

Stop Bit

Edge #1

Start

Bit 1

RX pin

Bit 0

Bit 2

Bit 4

BRG Clock

Auto-Cleared

Set by User

ABDEN bit

RCIF bit

(Interrupt)

Read

RCREG

XXXXh

1Ch

00h

SPBRG

SPBRGH

Note 1: The ABD sequence requires the USART module to be configured in Asynchronous mode and WUE = 0.

DS30491C-page 236

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

Once the TXREG register transfers the data to the TSR

register (occurs in one TCY), the TXREG register is

18.2 USART Asynchronous Mode

The Asynchronous mode of operation is selected by

clearing the SYNC bit (TXSTA<4>). In this mode, the

USART uses standard Non-Return-to-Zero (NRZ) for-

mat (one Start bit, eight or nine data bits and one Stop

bit). The most common data format is 8 bits. An on-chip

dedicated 8-bit/16-bit Baud Rate Generator can be

used to derive standard baud rate frequencies from the

oscillator.

empty and flag bit TXIF (PIR1<4>) is set. This interrupt

can be enabled/disabled by setting/clearing enable bit

TXIE (PIE1<4>). Flag bit TXIF will be set regardless of

the state of enable bit TXIE and cannot be cleared in

software. Flag bit TXIF is not cleared immediately upon

loading the Transmit Buffer register, TXREG. TXIF

becomes valid in the second instruction cycle following

the load instruction. Polling TXIF immediately following

a load of TXREG will return invalid results.

The USART transmits and receives the LSb first. The

USART’s transmitter and receiver are functionally inde-

pendent but use the same data format and baud rate.

The Baud Rate Generator produces a clock, either x16

or x64 of the bit shift rate depending on the BRGH and

BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity is

not supported by the hardware but can be implemented

in software and stored as the 9th data bit.

While flag bit TXIF indicates the status of the TXREG

register, another bit, TRMT (TXSTA<1>), shows the

status of the TSR register. Status bit TRMT is a read-

only bit which is set when the TSR register is empty. No

interrupt logic is tied to this bit, so the user has to poll

this bit in order to determine if the TSR register is

empty.

Asynchronous mode is available in all low-power

modes; it is available in Sleep mode only when auto-

wake-up on sync break is enabled. When in PRI_IDLE

mode, no changes to the Baud Rate Generator values

are required; however, other low-power mode clocks

may operate at another frequency than the primary

clock. Therefore, the Baud Rate Generator values may

need to be adjusted.

Note 1: The TSR register is not mapped in data

memory so it is not available to the user.

2: Flag bit TXIF is set when enable bit TXEN

is set.

To set up an Asynchronous Transmission:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

When operating in Asynchronous mode, the USART

module consists of the following important elements:

• Baud Rate Generator

Note:

When BRGH and BRG16 bits are set,

• Sampling Circuit

SPBRGH:SPBRG must be more than ‘1’.

• Asynchronous Transmitter

• Asynchronous Receiver

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

• Auto-Wake-up on Sync Break Character

• 12-bit Break Character Transmit

• Auto-Baud Rate Detection

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set transmit bit

TX9. Can be used as address/data bit.

5. Enable the transmission by setting bit TXEN

which will also set bit TXIF.

18.2.1

USART ASYNCHRONOUS

TRANSMITTER

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

The USART transmitter block diagram is shown in

Figure 18-2. The heart of the transmitter is the Transmit

(Serial) Shift register (TSR). The Shift register obtains

its data from the read/write transmit buffer, TXREG. The

TXREG register is loaded with data in software. The

TSR register is not loaded until the Stop bit has been

transmitted from the previous load. As soon as the Stop

bit is transmitted, the TSR is loaded with new data from

the TXREG register (if available).

7. Load data to the TXREG register (starts

transmission).

If using interrupts, ensure that the GIE and PEIE bits in

the INTCON register (INTCON<7:6>) are set.

 2004 Microchip Technology Inc.

DS30491C-page 237

PIC18F6585/8585/6680/8680

FIGURE 18-2:

USART TRANSMIT BLOCK DIAGRAM

Data Bus

TXIF

TXREG Register

8

TXIE

RC6/TX/CK pin

MSb

(8)

LSb

0

Pin Buffer

and Control

•

• •

TSR Register

Interrupt

Baud Rate CLK

SPBRG

TXEN

TRMT

SPEN

BRG16

SPBRGH

TX9

TX9D

Baud Rate Generator

FIGURE 18-3:

ASYNCHRONOUS TRANSMISSION

Write to TXREG

Word 1

BRG Output

(Shift Clock)

RC6/TX/CK

(pin)

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

1 TCY

Word 1

Transmit Shift Reg

TRMT bit

(Transmit Shift

Reg. Empty Flag)

FIGURE 18-4:

ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

Write to TXREG

Word 2

Start bit

Word 1

BRG Output

(Shift Clock)

RC6/TX/CK

(pin)

Start bit

Word 2

bit 0

bit 1

bit 7/8

bit 0

Stop bit

Word 2

1 TCY

Word 1

TXIF bit

(Interrupt Reg. Flag)

1 TCY

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Transmit Shift Reg.

Note: This timing diagram shows two consecutive transmissions.

DS30491C-page 238

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 18-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

TMR0IF INT0IF

RBIF

0000 000x 0000 000u

0000 0000 0000 0000

1111 1111 1111 1111

0000 000x 0000 000x

0000 0000 0000 0000

0000 0010 0000 0010

-1-1 0-00 -1-1 0-00

0000 0000 0000 0000

PSPIF

PSPIE

PSPIP

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TXIF

TXIE

TXIP

SSPIF CCP1IF TMR2IF TMR1IF

SSPIE CCP1IE TMR2IE TMR1IE

SSPIP CCP1IP TMR2IP TMR1IP

PIE1

IPR1

RCSTA

TXREG

TXSTA

BAUDCON

CREN ADDEN

FERR

OERR

RX9D

USART Transmit Register

CSRC

—

TX9

TXEN

—

SYNC SENDB BRGH

SCKP BRG16

TRMT

WUE

TX9D

RCIDL

—

ABDEN

SPBRGH Baud Rate Generator Register, High Byte

SPBRG

Baud Rate Generator Register, Low Byte

Legend:

x= unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.

 2004 Microchip Technology Inc.

DS30491C-page 239

PIC18F6585/8585/6680/8680

18.2.2

USART ASYNCHRONOUS

RECEIVER

18.2.3

SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

The receiver block diagram is shown in Figure 18-5.

The data is received on the RC7/RX/DT pin and drives

the data recovery block. The data recovery block is

actually a high-speed shifter operating at x16 times the

baud rate, whereas the main receive serial shifter oper-

ates at the bit rate or at FOSC. This mode would

typically be used in RS-232 systems.

This mode would typically be used in RS-485 systems.

To set up an asynchronous reception with address

detect enable:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate..

To set up an asynchronous reception:

Note:

When BRGH and BRG16 bits are set,

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

SPBRGH:SPBRG must be more than ‘1’.

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If interrupts are required, set the RCEN bit and

select the desired priority level with the RCIP bit.

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

4. Set the RX9 bit to enable 9-bit reception.

5. Set the ADDEN bit to enable address detect.

6. Enable reception by setting the CREN bit.

3. If interrupts are desired, set enable bit RCIE.

4. If 9-bit reception is desired, set bit RX9.

5. Enable the reception by setting bit CREN.

7. The RCIF bit will be set when reception is com-

plete. The interrupt will be Acknowledged if the

RCIE and GIE bits are set.

6. Flag bit RCIF will be set when reception is com-

plete and an interrupt will be generated if enable

bit RCIE was set.

8. Read the RCSTA register to determine if any

error occurred during reception, as well as read

bit 9 of data (if applicable).

7. Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

9. Read RCREG to determine if the device is being

addressed.

8. Read the 8-bit received data by reading the

RCREG register.

10. If any error occurred, clear the CREN bit.

9. If any error occurred, clear the error by clearing

enable bit CREN.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and interrupt the CPU.

10. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 18-5:

USART RECEIVE BLOCK DIAGRAM

CREN

OERR

FERR

x64 Baud Rate CLK

SPBRGH

SPBRG

÷ 64

or

RSR Register

• • •

LSb

Start

MSb

Stop

BRG16

÷ 16

(8)

7

1

0

or

÷ 4

Baud Rate Generator

RX9

RC7/RX/DT

Pin Buffer

Data

and Control

Recovery

RX9D

RCREG Register

FIFO

SPEN

8

Interrupt

RCIF

RCIE

Data Bus

DS30491C-page 240

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

To set up an asynchronous transmission:

5. Enable the transmission by setting bit TXEN

which will also set bit TXIF.

1. Initialize the SPBRG register for the appropriate

baud rate. If a high-speed baud rate is desired,

set bit BRGH (see Section 18.1 “USART Baud

Rate Generator (BRG)”).

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Load data to the TXREG register (starts

transmission).

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

If using interrupts, ensure that the GIE and PEIE bits in

the INTCON register (INTCON<7:6>) are set.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set transmit bit

TX9. Can be used as address/data bit.

FIGURE 18-6:

ASYNCHRONOUS RECEPTION

Start

bit

Start

bit

Start

bit

RX (pin)

bit 0 bit 1

Stop

bit

Stop

bit

bit 7/8 Stop

bit

bit 0

bit 7/8

Rcv Shift

Reg

Rcv Buffer Reg

Word 2

RCREG

Word 1

RCREG

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing

the OERR (overrun) bit to be set.

TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

TMR0IF INT0IF

RBIF

0000 000x

0000 000u

0000 0000

1111 1111

0000 000x

0000 0000

0000 0010

-1-1 0-00

0000 0000

PSPIF

PSPIE

PSPIP

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TXIF

TXIE

TXIP

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000

SSPIP CCP1IP TMR2IP TMR1IP 1111 1111

PIE1

IPR1

RCSTA

RCREG

TXSTA

BAUDCON

CREN ADDEN FERR

OERR

RX9D

0000 000x

0000 0000

0000 0010

USART Receive Register

CSRC

—

TX9

TXEN

—

SYNC SENDB BRGH

TRMT

WUE

TX9D

RCIDL

SCKP BRG16

—

ABDEN -1-1 0-00

0000 0000

SPBRGH Baud Rate Generator Register, High Byte

SPBRG

Baud Rate Generator Register, Low Byte

0000 0000

Legend:

x= unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

 2004 Microchip Technology Inc.

DS30491C-page 241

PIC18F6585/8585/6680/8680

and cause data or framing errors. To work properly,

therefore, the initial character in the transmission must

be all ‘0’s. This can be 00h (8 bytes) for standard RS-232

devices or 000h (12 bits) for LIN bus.

18.2.4

AUTO-WAKE-UP ON SYNC BREAK

CHARACTER

During Sleep mode, all clocks to the USART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper byte reception cannot be per-

formed. The auto-wake-up feature allows the controller

to wake-up due to activity on the RX/DT line while the

USART is operating in Asynchronous mode.

Oscillator start-up time must also be considered,

especially in applications using oscillators with longer

start-up intervals (i.e., XT or HS mode). The sync break

(or wake-up signal) character must be of sufficient

length and be followed by a sufficient interval to allow

enough time for the selected oscillator to start and

provide proper initialization of the USART.

The auto-wake-up feature is enabled by setting the

WUE bit (BAUDCON<1>). Once set, the typical receive

sequence on RX/DT is disabled and the USART

remains in an Idle state monitoring for a wake-up event

independent of the CPU mode. A wake-up event con-

sists of a high-to-low transition on the RX/DT line. (This

coincides with the start of a sync break or a wake-up

signal character for the LIN protocol.)

18.2.4.2

Special Considerations Using

the WUE Bit

The timing of WUE and RCIF events may cause some

confusion when it comes to determining the validity of

received data. As noted, setting the WUE bit places the

USART in an Idle mode. The wake-up event causes a

receive interrupt by setting the RCIF bit. The WUE bit

is cleared after this when a rising edge is seen on

RX/DT. The interrupt condition is then cleared by read-

ing the RCREG register. Ordinarily, the data in RCREG

will be dummy data and should be discarded.

Following a wake-up event, the module generates an

RCIF interrupt. The interrupt is generated synchro-

nously to the Q clocks in normal operating modes

(Figure 18-7) and asynchronously, if the device is in

Sleep mode (Figure 18-8). The interrupt condition is

cleared by reading the RCREG register.

The WUE bit is automatically cleared once a low-to-

high transition is observed on the RX line following the

wake-up event. At this point, the USART module is in

Idle mode and returns to normal operation. This signals

to the user that the sync break event is over.

The fact that the WUE bit has been cleared (or is still

set) and the RCIF flag is set should not be used as an

indicator of the integrity of the data in RCREG. Users

should consider implementing a parallel method in

firmware to verify received data integrity.

To assure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process. If

a receive operation is not occurring, the WUE bit may

then be set just prior to entering the Sleep mode.

18.2.4.1

Special Considerations Using

Auto-Wake-up

Since auto-wake-up functions by sensing rising edge

transitions on RX/DT, information with any state changes

before the Stop bit may signal a false end-of-character

FIGURE 18-7:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit

Auto-Cleared

Bit Set by User

RX/DT Line

RCIF

Cleared due to User Read of RCREG

Note:

The USART remains in Idle while the WUE bit is set.

FIGURE 18-8:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit

Auto-Cleared

Bit Set by User

RX/DT Line

RCIF

Note 1

Cleared due to User Read of RCREG

Sleep Ends

Sleep Command Executed

Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.

This sequence should not depend on the presence of Q clocks.

2: The USART remains in Idle while the WUE bit is set.

DS30491C-page 242

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

18.2.5

BREAK CHARACTER SEQUENCE

18.2.5.1

Break and Sync Transmit Sequence

The enhanced USART module has the capability of

sending the special break character sequences that

are required by the LIN bus standard. The break char-

acter transmit consists of a Start bit, followed by twelve

‘0’ bits and a Stop bit. The frame break character is sent

whenever the SENDB and TXEN bits (TXSTA<3> and

TXSTA<5>) are set while the Transmit Shift register is

loaded with data. Note that the value of data written to

TXREG will be ignored and all ‘0’s will be transmitted.

The following sequence will send a message frame

header made up of a break, followed by an auto-baud

sync byte. This sequence is typical of a LIN bus master.

1. Configure the USART for the desired mode.

2. Set the TXEN and SENDB bits to set up the

break character.

3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG to load the sync character

into the transmit FIFO buffer.

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the break character (typically, the sync

character in the LIN specification).

5. After the break has been sent, the SENDB bit is

reset by hardware. The sync character now

transmits in the preconfigured mode.

When the TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.

Note that the data value written to the TXREG for the

break character is ignored. The write simply serves the

purpose of initiating the proper sequence.

18.2.6

RECEIVING A BREAK CHARACTER

The TRMT bit indicates when the transmit operation is

active or Idle, just as it does during normal transmis-

sion. See Figure 18-9 for the timing of the break

character sequence.

The enhanced USART module can receive a break

character in two ways.

The first method forces the configuration of the baud

rate at a frequency of 9/13 the typical speed. This

allows for the Stop bit transition to be at the correct

sampling location (13 bits for break versus Start bit and

8 data bits for typical data).

The second method uses the auto-wake-up feature

described in Section 18.2.4 “Auto-Wake-up on Sync

Break Character”. By enabling this feature, the

USART will sample the next two transitions on RX/DT,

cause an RCIF interrupt, and receive the next data byte

followed by another interrupt.

Note that following a break character, the user will typ-

ically want to enable the auto-baud rate detect feature.

For both methods, the user can set the ABD bit once

the TXIF interrupt is observed.

FIGURE 18-9:

SEND BREAK CHARACTER SEQUENCE

Write to TXREG

Dummy Write

BRG Output

(Shift Clock)

TX (pin)

Start Bit

Bit 0

Bit 1

Break

Bit 11

Stop Bit

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

SENDB Sampled Here

Auto-Cleared

SENDB

(Transmit Shift

Reg. Empty Flag)

 2004 Microchip Technology Inc.

DS30491C-page 243

PIC18F6585/8585/6680/8680

Once the TXREG register transfers the data to the TSR

18.3 USART Synchronous

Master Mode

register (occurs in one TCYCLE), the TXREG is empty

and interrupt bit TXIF (PIR1<4>) is set. The interrupt

can be enabled/disabled by setting/clearing enable bit,

TXIE (PIE1<4>). Flag bit TXIF will be set regardless of

the state of enable bit TXIE and cannot be cleared in

software. It will reset only when new data is loaded into

the TXREG register.

The Synchronous Master mode is entered by setting

the CSRC bit (TXSTA<7>). In this mode, the data is

transmitted in a half-duplex manner (i.e., transmission

and reception do not occur at the same time). When

transmitting data, the reception is inhibited and vice

versa. Synchronous mode is entered by setting bit

SYNC (TXSTA<4>). In addition, enable bit, SPEN

(RCSTA<7>), is set in order to configure the

RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and

DT (data) lines, respectively.

While flag bit TXIF indicates the status of the TXREG

register, another bit, TRMT (TXSTA<1>), shows the sta-

tus of the TSR register. TRMT is a read-only bit which is

set when the TSR is empty. No interrupt logic is tied to

this bit so the user must poll this bit in order to determine

if the TSR register is empty. The TSR is not mapped in

data memory so it is not available to the user.

The Master mode indicates that the processor trans-

mits the master clock on the CK line. Clock polarity is

selected with the SCKP bit (BAUDCON<5>); setting

SCKP sets the Idle state on CK as high, while clearing

the bit sets the Idle state as low. This option is provided

to support Microwire devices with this module.

To set up a synchronous master transmission:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

18.3.1

USART SYNCHRONOUS MASTER

TRANSMISSION

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

The USART transmitter block diagram is shown in

Figure 18-2. The heart of the transmitter is the Transmit

(Serial) Shift Register (TSR). The Shift register obtains

its data from the Read/Write Transmit Buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available).

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting bit TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmission by loading data to the TXREG

register.

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 18-10:

SYNCHRONOUS TRANSMISSION

Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

RC7/RX/DT

bit 0

bit 1

bit 2

bit 7

bit 0

bit 1

Word 2

bit 7

Word 1

RC6/TX/CK

(SCKP = 0)

RC6/TX/CK

(SCKP = 1)

Write to

TXREG Reg

Write Word 1

Write Word 2

TXIF bit

(Interrupt Flag)

TRMT bit

TXEN bit

‘1’

Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

DS30491C-page 244

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 18-11:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RC7/RX/DT pin

bit 0

bit 1

bit 2

bit 6

bit 7

RC6/TX/CK pin

Write to

TXREG Reg

TXIF bit

TRMT bit

TXEN bit

TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

INT0IF

RBIF

0000 0000 0000 0000

PSPIF

PSPIE

PSPIP

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TXIF

TXIE

TXIP

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111

PIE1

IPR1

RCSTA

TXREG

TXSTA

BAUDCON

CREN ADDEN

FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

0000 0010 0000 0010

-1-0 0-00 -1-0 0-00

0000 0000 0000 0000

USART Transmit Register

CSRC

—

TX9

TXEN

—

SYNC SENDB

SCKP BRG16

BRGH

—

TRMT

WUE

TX9D

RCIDL

ABDEN

SPBRGH Baud Rate Generator Register, High Byte

SPBRG

Baud Rate Generator Register, Low Byte

Legend:

x= unknown, -= unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.

 2004 Microchip Technology Inc.

DS30491C-page 245

PIC18F6585/8585/6680/8680

3. Ensure bits CREN and SREN are clear.

4. If interrupts are desired, set enable bit RCIE.

5. If 9-bit reception is desired, set bit RX9.

18.3.2

USART SYNCHRONOUS MASTER

RECEPTION

Once Synchronous mode is selected, reception is

enabled by setting either the Single Receive Enable bit,

SREN (RCSTA<5>), or the Continuous Receive

Enable bit, CREN (RCSTA<4>). Data is sampled on the

RC7/RX/DT pin on the falling edge of the clock.

6. If a single reception is required, set bit SREN.

For continuous reception, set bit CREN.

7. Interrupt flag bit RCIF will be set when reception

is complete and an interrupt will be generated if

the enable bit RCIE was set.

If enable bit SREN is set, only a single word is received.

If enable bit CREN is set, the reception is continuous

until CREN is cleared. If both bits are set, then CREN

takes precedence.

8. Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

9. Read the 8-bit received data by reading the

RCREG register.

To set up a synchronous master reception:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

10. If any error occurred, clear the error by clearing

bit CREN.

11. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

FIGURE 18-12:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

RC7/RX/DT pin

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

RC7/TX/CK pin

(SCKP = 0)

RC7/TX/CK pin

(SCKP = 1)

Write to

bit SREN

SREN bit

CREN bit

‘0’

RCIF bit

(Interrupt)

Read

RXREG

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.

TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF INT0IF

RBIF

0000 0000 0000 0000

PSPIF

PSPIE

PSPIP

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TXIF

TXIE

TXIP

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111

PIE1

IPR1

RCSTA

RCREG

TXSTA

BAUDCON

CREN ADDEN

FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

0000 0010 0000 0010

-1-0 0-00 -1-0 0-00

0000 0000 0000 0000

USART Receive Register

CSRC

—

TX9

TXEN

—

SYNC SENDB

BRGH

—

TRMT

WUE

TX9D

RCIDL

SCKP

BRG16

ABDEN

SPBRGH Baud Rate Generator Register, High Byte

SPBRG

Baud Rate Generator Register, Low Byte

Legend:

x= unknown, -= unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.

DS30491C-page 246

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

To set up a synchronous slave transmission:

18.4 USART Synchronous Slave Mode

1. Enable the synchronous slave serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

Synchronous Slave mode is entered by clearing bit

CSRC (TXSTA<7>). This mode differs from the

Synchronous Master mode in that the shift clock is sup-

plied externally at the RC6/TX/CK pin (instead of being

supplied internally in Master mode). This allows the

device to transfer or receive data while in any low-power

mode.

2. Clear bits CREN and SREN.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting enable bit

TXEN.

18.4.1

USART SYNCHRONOUS SLAVE

TRANSMIT

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

The operation of the Synchronous Master and Slave

modes are identical except in the case of the Sleep

mode.

7. Start transmission by loading data to the TXREG

register.

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in TXREG register.

c) Flag bit TXIF will not be set.

d) When the first word has been shifted out of TSR,

the TXREG register will transfer the second word

to the TSR and flag bit TXIF will now be set.

e) If enable bit TXIE is set, the interrupt will wake

the chip from Sleep. If the global interrupt is

enabled, the program will branch to the interrupt

vector.

TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

TMR0IF INT0IF

RBIF

0000 000x 0000 000u

PSPIF

PSPIE

PSPIP

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TXIF

TXIE

TXIP

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111

PIE1

IPR1

RCSTA

TXREG

TXSTA

BAUDCON

CREN ADDEN

FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

0000 0010 0000 0010

USART Transmit Register

CSRC

—

TX9

TXEN

—

SYNC SENDB BRGH

SCKP BRG16

TRMT

WUE

TX9D

RCIDL

—

ABDEN -1-1 0-00 -1-1 0-00

0000 0000 0000 0000

SPBRGH Baud Rate Generator Register, High Byte

SPBRG

Baud Rate Generator Register, Low Byte

0000 0000 0000 0000

Legend:

x= unknown, -= unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

 2004 Microchip Technology Inc.

DS30491C-page 247

PIC18F6585/8585/6680/8680

To set up a synchronous slave reception:

18.4.2

USART SYNCHRONOUS SLAVE

RECEPTION

1. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

The operation of the Synchronous Master and Slave

modes is identical, except in the case of Sleep or any

Idle mode and bit SREN, which is a “don’t care” in

Slave mode.

2. If interrupts are desired, set enable bit RCIE.

3. If 9-bit reception is desired, set bit RX9.

4. To enable reception, set enable bit CREN.

If receive is enabled by setting the CREN bit prior to

entering Sleep or any Idle mode, then a word may be

received while in this low-power mode. Once the word

is received, the RSR register will transfer the data to the

RCREG register; if the RCIE enable bit is set, the inter-

rupt generated will wake the chip from low-power

mode. If the global interrupt is enabled, the program will

branch to the interrupt vector.

5. Flag bit RCIF will be set when reception is

complete. An interrupt will be generated if

enable bit RCIE was set.

6. Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

7. Read the 8-bit received data by reading the

RCREG register.

8. If any error occurred, clear the error by clearing

bit CREN.

9. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

TMR0IF INT0IF

RBIF

0000 0000 0000 0000

PSPIF

PSPIE

PSPIP

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TXIF

TXIE

TXIP

SSPIF

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111

IPR1

RCSTA

RCREG

TXSTA

BAUDCON

CREN ADDEN

FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

0000 0010 0000 0010

USART Receive Register

CSRC

—

TX9

TXEN

—

SYNC

SCKP

SENDB

BRG16

BRGH

—

TRMT

WUE

TX9D

RCIDL

ABDEN -1-0 0-00 -1-0 0-00

0000 0000 0000 0000

SPBRGH Baud Rate Generator Register, High Byte

SPBRG

Baud Rate Generator Register, Low Byte

0000 0000 0000 0000

Legend:

x= unknown, -= unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

DS30491C-page 248

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

The module has five registers:

19.0 10-BIT ANALOG-TO-DIGITAL

• A/D Result High Register (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

• A/D Control Register 2 (ADCON2)

CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) converter module has 12

inputs for the PIC18F6X8X devices and 16 inputs for

the PIC18F8X8X devices. This module allows conver-

sion of an analog input signal to a corresponding 10-bit

digital number.

The ADCON0 register, shown in Register 19-1,

controls the operation of the A/D module. The

ADCON1 register, shown in Register 19-2, configures

the functions of the port pins. The ADCON2 register,

shown in Register 19-3, configures the A/D clock

source, programmed acquisition time and justification.

A new feature for the A/D converter is the addition of pro-

grammable acquisition time. This feature allows the user

to select a new channel for conversion and to set the

GO/DONE bit immediately. When the GO/DONE bit is

set, the selected channel is sampled for the

programmed acquisition time before a conversion is

actually started. This removes the firmware overhead

that may have been required to allow for an acquisition

(sampling) period (see Register 19-3 and Section 19.4

“Selecting the A/D Conversion Clock”).

REGISTER 19-1: ADCON0 REGISTER

U-0

—

U-0

—

R/W-0

CHS3

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0

R/W-0

ADON

GO/DONE

bit 7

bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5-2 CHS3:CHS0: Analog Channel Select bits

0000= Channel 0 (AN0)

0001= Channel 1 (AN1)

0010= Channel 2 (AN2)

0011= Channel 3 (AN3)

0100= Channel 4 (AN4)

0101= Channel 5 (AN5)

0110= Channel 6 (AN6)

0111= Channel 7 (AN7)

1000= Channel 8 (AN8)

1001= Channel 9 (AN9)

1010= Channel 10 (AN10)

1011= Channel 11 (AN11)

1100= Channel 12 (AN12)⁽¹⁾

1101= Channel 13 (AN13)⁽¹⁾

1110= Channel 14 (AN14)⁽¹⁾

1111= Channel 15 (AN15)⁽¹⁾

bit 1

bit 0

GO/DONE: A/D Conversion Status bit

When ADON = 1:

1= A/D conversion in progress. This bit is automatically cleared when the A/D conversion is

complete.

0= A/D Idle

ADON: A/D On bit

1= A/D converter module is enabled

0= A/D converter module is disabled and consumes no current

Note 1: These channels are only available on PIC18F8X8X devices.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 249

PIC18F6585/8585/6680/8680

REGISTER 19-2: ADCON1 REGISTER

U-0

—

U-0

—

R/W-0

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

bit 7

bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits

A/D VREF+

A/D VREF-

00

01

10

11

AVDD

AVSS

External VREF+

AVDD

AVSS

External VREF-

External VREF+

bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits

AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A = Analog input

D = Digital I/O

Shaded cells = Additional channels available on the PIC18F8X8X devices

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Note:

Channels AN15 through AN12 are not available on the 68-pin devices.

DS30491C-page 250

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 19-3: ADCON2 REGISTER

R/W-0

ADFM

U-0

—

R/W-0

ACQT2

ACQT1

ACQT0

ADCS2

ADCS1

ADCS0

bit 7

bit 0

bit 7

ADFM: A/D Result Format Select bit

1= Right justified

0= Left justified

bit 6

Unimplemented: Read as ‘0’

bit 5-3

ACQT2:ACQT0: A/D Acquisition Time Select bits

(1)

000= 0 TAD

001= 2 TAD

010= 4 TAD

011= 6 TAD

100= 8 TAD

101= 12 TAD

110= 16 TAD

111= 20 TAD

bit 2-0

ADCS2:ADCS0: A/D Conversion Clock Select bits

000= FOSC/2

001= FOSC/8

010= FOSC/32

011= FRC (clock derived from A/D RC oscillator)⁽¹⁾

100= FOSC/4

101= FOSC/16

110= FOSC/64

111= FRC (clock derived from A/D RC oscillator)⁽¹⁾

Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is

added before the A/D clock starts. This allows the SLEEPinstruction to be executed

before starting a conversion.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 251

PIC18F6585/8585/6680/8680

The analog reference voltage is software selectable to

either the device’s positive and negative supply voltage

(AVDD and AVSS) or the voltage level on the RA3/AN3/

VREF+ and RA2/AN2/VREF- pins.

A device Reset forces all registers to their Reset state.

This forces the A/D module to be turned off and any

conversion in progress is aborted.

Each port pin associated with the A/D converter can be

configured as an analog input or as a digital I/O. The

ADRESH and ADRESL registers contain the result of

the A/D conversion. When the A/D conversion is com-

plete, the result is loaded into the ADRESH/ADRESL

registers, the GO/DONE bit (ADCON0 register) is

cleared and A/D interrupt flag bit ADIF is set. The block

diagram of the A/D module is shown in Figure 19-1.

The A/D converter has a unique feature of being able

to operate while the device is in Sleep mode. To oper-

ate in Sleep, the A/D conversion clock must be derived

from the A/D’s internal RC oscillator.

The output of the sample and hold is the input into the

converter which generates the result via successive

approximation.

FIGURE 19-1:

A/D BLOCK DIAGRAM

CHS3:CHS0

1111

(1)

AN15

1110

(1)

AN14

1101

(1)

AN13

1100

(1)

AN12

1011

AN11

1010

AN10

1001

AN9

1000

AN8

0111

AN7

0110

AN6

0101

AN5

0100

AN4

VAIN

0011

(Input Voltage)

10-bit

Converter

A/D

AN3

0010

AN2

0001

VCFG1:VCFG0

AN1

0000

AN0

VDD

VREF+

VREF-

Reference

Voltage

VSS

Note 1: Channels AN15 through AN12 are not available on the PIC18F6X8X.

2: I/O pins have diode protection to VDD and VSS.

DS30491C-page 252

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

The value in the ADRESH/ADRESL registers is not

The following steps should be followed to do an A/D

conversion:

modified for a Power-on Reset. The ADRESH/

ADRESL registers will contain unknown data after a

Power-on Reset.

1. Configure the A/D module:

• Configure analog pins, voltage reference and

digital I/O (ADCON1)

After the A/D module has been configured as desired,

the selected channel must be acquired before the con-

version is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 19.1

“A/D Acquisition Requirements”. After this acquisi-

tion time has elapsed, the A/D conversion can be

started. An acquisition time can be programmed to

occur between setting the GO/DONE bit and the actual

start of the conversion.

• Select A/D input channel (ADCON0)

• Select A/D acquisition time (ADCON2)

• Select A/D conversion clock (ADCON2)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time (if required).

4. Start conversion:

• Set GO/DONE bit (ADCON0 register)

5. Wait for A/D conversion to complete by either:

• Polling for the GO/DONE bit to be cleared

or

• Waiting for the A/D interrupt

6. Read A/D Result registers (ADRESH:ADRESL);

clear bit ADIF if required.

7. For next conversion, go to step 1 or step 2 as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before next acquisition starts.

FIGURE 19-2:

ANALOG INPUT MODEL

VDD

Sampling

Switch

VT = 0.6V

ANx

SS

RIC ≤ 1k

RSS

Rs

CPIN

5 pF

VAIN

ILEAKAGE

± 500 nA

CHOLD = 120 pF

VT = 0.6V

VSS

Legend: CPIN

= input capacitance

= threshold voltage

6V

VT

5V

VDD 4V

3V

ILEAKAGE = leakage current at the pin due to

various junctions

RIC

= interconnect resistance

= sampling switch

2V

SS

CHOLD

RSS

= sample/hold capacitance (from DAC)

= sampling switch resistance

5

6

7

8 9 10 11

Sampling Switch (kΩ)

 2004 Microchip Technology Inc.

DS30491C-page 253

PIC18F6585/8585/6680/8680

19.1 A/D Acquisition Requirements

19.2 A/D VREF+ and VREF- References

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 19-2. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD). The source impedance affects the offset voltage

at the analog input (due to pin leakage current). The

maximum recommended impedance for analog

sources is 2.5 kΩ. After the analog input channel is

selected (changed), this acquisition must be done

before the conversion can be started.

If external voltage references are used instead of the

internal AVDD and AVSS sources, the source impedance

of the VREF+ and VREF- voltage sources must be consid-

ered. During acquisition, currents supplied by these

sources are insignificant. However, during conversion,

the A/D module sinks and sources current through the

reference sources. The effect of this current, as specified

in parameter A50, along with source impedance must be

considered to meet specified A/D resolution.

Note:

When using external voltage references

with the A/D converter, the source imped-

ance of the external voltage references

must be less than 20Ω to obtain the spec-

ified A/D resolution. Higher reference

source impedances will increase both

offset and gain errors. Resistive voltage

dividers will not provide a sufficiently low

source impedance.

Note:

When the conversion is started, the

holding capacitor is disconnected from the

input pin.

To calculate the minimum acquisition time,

Equation 19-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

To maintain the best possible performance

in A/D conversions, external VREF inputs

should be buffered with an operational

amplifier or other low output impedance

circuit.

Example 19-1 shows the calculation of the minimum

required acquisition time, TACQ. This calculation is based

on the following application system assumptions:

CHOLD

Rs

Conversion Error

VDD

Temperature

VHOLD

=

≤

=

120 pF

2.5 kΩ

1/2 LSb

5V → Rss = 7 kΩ

50°C (system max.)

0V @ time = 0

EQUATION 19-1: ACQUISITION TIME

TACQ

=

Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

TAMP + TC + TCOFF

EQUATION 19-2: A/D MINIMUM CHARGING TIME

VHOLD

or

TC

=

(VREF – (VREF/2048)) • (1 – e^{(-Tc/CHOLD(RIC + RSS + RS))}

)

=

-(120 pF)(1 kΩ + RSS + RS) ln(1/2047)

EXAMPLE 19-1:

CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

TACQ

=

TAMP + TC + TCOFF

Temperature coefficient is only required for temperatures > 25°C.

TACQ

=

2 µs + TC + [(Temp – 25°C)(0.05 µs/°C)]

TC

=

-CHOLD (RIC + RSS + RS) ln(1/2047)

-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885)

-120 pF (10.5 kΩ) ln(0.0004885)

-1.26 µs (-7.6241)

9.61 µs

TACQ

=

2 µs + 9.61 µs + [(50°C – 25°C)(0.05 µs/°C)]

11.61 µs + 1.25 µs

12.86 µs

DS30491C-page 254

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

19.3 Selecting and Configuring

Automatic Acquisition Time

19.4 Selecting the A/D Conversion Clock

The A/D conversion time per bit is defined as TAD. The

A/D conversion requires 11 TAD per 10-bit conversion.

The source of the A/D conversion clock is software

selectable. There are seven possible options for TAD:

The ADCON2 register allows the user to select an

acquisition time that occurs each time the GO/DONE

bit is set.

•

2 TOSC

•

4 TOSC

When the GO/DONE bit is set, sampling is stopped and

a conversion begins. The user is responsible for ensur-

ing the required acquisition time has passed between

selecting the desired input channel and setting the

GO/DONE bit. This occurs when the ACQT2:ACQT0

bits (ADCON2<5:3>) remain in their Reset state (‘000’)

and is compatible with devices that do not offer

programmable acquisition times.

8 TOSC

16 TOSC

64 TOSC

32 TOSC

Internal RC Oscillator

For correct A/D conversions, the A/D conversion clock

(TAD) must be as short as possible but greater than the

minimum TAD (approximately 2 µs, see parameter 130

for more information).

If desired, the ACQT bits can be set to select a pro-

grammable acquisition time for the A/D module. When

the GO/DONE bit is set, the A/D module continues to

sample the input for the selected acquisition time, then

automatically begins a conversion. Since the acquisi-

tion time is programmed, there may be no need to wait

for an acquisition time between selecting a channel and

setting the GO/DONE bit.

Table 19-1 shows the resultant TAD times derived from

the device operating frequencies and the A/D clock

source selected.

19.5 Configuring Analog Port Pins

The ADCON1, TRISA, TRISF and TRISH registers con-

trol the operation of the A/D port pins. The port pins

needed as analog inputs must have their corresponding

TRIS bits set (input). If the TRIS bit is cleared (output),

the digital output level (VOH or VOL) will be converted.

In either case, when the conversion is completed, the

GO/DONE bit is cleared, the ADIF flag is set, and the

A/D begins sampling the currently selected channel

again. If an acquisition time is programmed, there is

nothing to indicate if the acquisition time has ended or

if the conversion has begun.

The A/D operation is independent of the state of the

CHS3:CHS0 bits and the TRIS bits.

Note 1: When reading the port register, all pins

configured as analog input channels will

read as cleared (a low level). Pins config-

ured as digital inputs will convert an

analog input. Analog levels on a digitally

configured input will not affect the

conversion accuracy.

2: Analog levels on any pin defined as a dig-

ital input may cause the input buffer to

consume current out of the device’s

specification limits.

TABLE 19-1: TAD vs. DEVICE OPERATING FREQUENCIES

AD Clock Source (TAD)

Maximum Device Frequency

Operation

2 TOSC

ADCS2:ADCS0

PIC18FXX80/XX85

PIC18LFXX80/XX85

666 kHz

000

100

001

101

010

110

x11

1.25 MHz

2.50 MHz

5.00 MHz

10.0 MHz

20.0 MHz

40.0 MHz

1.00 MHz⁽¹⁾

4 TOSC

1.33 MHz

8 TOSC

2.66 MHz

16 TOSC

32 TOSC

64 TOSC

RC⁽³⁾

5.33 MHz

10.65 MHz

21.33 MHz

1.00 MHz⁽²⁾

Note 1: The RC source has a typical TAD time of 4 µs.

2: The RC source has a typical TAD time of 6 µs.

3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D

accuracy may be out of specification.

 2004 Microchip Technology Inc.

DS30491C-page 255

PIC18F6585/8585/6680/8680

19.6 A/D Conversions

19.7 Use of the CCP2 Trigger

Figure 19-3 shows the operation of the A/D converter

after the GO bit has been set and the ACQT2:ACQT0

bits are cleared. A conversion is started after the follow-

ing instruction to allow entry into Sleep mode before the

conversion begins.

An A/D conversion can be started by the “special event

trigger” of the CCP2 module. This requires that the

CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-

grammed as ‘1011’ and that the A/D module is enabled

(ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, starting the A/D conversion

and the Timer1 (or Timer3) counter will be reset to zero.

Timer1 (or Timer3) is reset to automatically repeat the

A/D acquisition period with minimal software overhead

(moving ADRESH/ADRESL to the desired location).

The appropriate analog input channel must be selected

and the minimum acquisition done before the “special

event trigger” sets the GO/DONE bit (starts a

conversion).

Figure 19-4 shows the operation of the A/D converter

after the GO bit has been set, the ACQT2:ACQT0 bits

are set to ‘010’ and selecting a 4 TAD acquisition time

before the conversion starts.

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The A/D Result register

pair will not be updated with the partially completed A/D

conversion sample. This means the ADRESH:ADRESL

registers will continue to contain the value of the last

completed conversion (or the last value written to the

ADRESH:ADRESL registers).

If the A/D module is not enabled (ADON is cleared), the

“special event trigger” will be ignored by the A/D

module but will still reset the Timer1 (or Timer3)

counter.

After the A/D conversion is completed or aborted, a

2 TAD wait is required before the next acquisition can

be started. After this wait, acquisition on the selected

channel is automatically started.

Note:

The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

FIGURE 19-3:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

TCY - TAD

TAD7 TAD8 TAD9 TAD10 TAD11

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6

b6

b4

b1

b0

b9

b8

b7

b5

b3

b2

Conversion starts

Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO bit

Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

FIGURE 19-4:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

TAD Cycles

TACQT Cycles

7

8

9

10

b1

11

b0

1

2

3

4

1

2

3

4

5

6

b7

b6

b3

b2

b8

b5

b4

b9

Automatic

Acquisition

Time

Conversion starts

(Holding capacitor is disconnected)

Set GO bit

(Holding capacitor continues

acquiring input)

Next Q4: ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is reconnected to analog input.

DS30491C-page 256

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 19-2: SUMMARY OF A/D REGISTERS

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

TMR0IF

INT0IF

TMR2IF

TMR2IE

TMR2IP

TMR3IF

TMR3IE

TMR3IP

RBIF

0000 0000 0000 0000

PIR1

PIE1

IPR1

PIR2

PIE2

IPR2

PSPIF

PSPIE

PSPIP

—

ADIF

ADIE

ADIP

CMIF

CMIE

CMIP

RCIF

RCIE

RCIP

—

TXIF

TXIE

TXIP

EEIF

EEIE

EEIP

SSPIF CCP1IF

SSPIE CCP1IE

SSPIP CCP1IP

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

TMR1IP 1111 1111 1111 1111

CCP2IF -0-0 0000 -0-0 0000

CCP2IE -0-0 0000 -0-0 0000

CCP2IP -1-1 1111 -1-1 1111

xxxx xxxx uuuu uuuu

BCLIF

BCLIE

BCLIP

LVDIF

LVDIE

LVDIP

—

ADRESH A/D Result Register High Byte

ADRESL A/D Result Register Low Byte

xxxx xxxx uuuu uuuu

ADCON0

ADCON1

ADCON2

PORTA

TRISA

—

CHS3

CHS1

CHS0

GO/DONE

PCFG1

ADCS1

RA1

ADON

PCFG0

ADCS0

RA0

--00 0000 --00 0000

0--- -000 0--- -000

--xx xxxx --uu uuuu

--11 1111 --11 1111

xxxx xxxx uuuu uuuu

VCFG1 VCFG0 PCFG3 PCFG2

ADFM

—

ADCS2

RA2

RA6

RA5

RA4

RA3

—

PORTA Data Direction Register

PORTF

LATF

RF7

LATF7

RF6

RF5

RF4

RF3

RF2

RF1

RF0

LATF6

LATF5

LATF4

LATF3

LATF2

LATF1

LATF0

xxxx xxxx

uuuu uuuu

TRISF

PORTF Data Direction Control Register

1111 1111 1111 1111

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

(1)

PORTH

RH7

RH6

RH5

RH4

RH3

RH2

RH1

RH0

(1)

LATH

LATH7

LATH6

LATH5

LATH4 LATH3

LATH2

LATH1

LATH0

(1)

TRISH

PORTH Data Direction Control Register

Legend:

x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.

Note 1: Only available on PIC18F8X8X devices.

 2004 Microchip Technology Inc.

DS30491C-page 257

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 258

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

The CMCON register, shown in Register 20-1, controls

the comparator input and output multiplexers. A block

diagram of the various comparator configurations is

shown in Figure 20-1.

20.0 COMPARATOR MODULE

The comparator module contains two analog

comparators. The inputs to the comparators are

multiplexed with the RF1 through RF6 pins. The on-

chip voltage reference (Section 21.0 “Comparator

Voltage Reference Module”) can also be an input to

the comparators.

REGISTER 20-1: CMCON REGISTER

R-0

R/W-0

C2INV

R/W-0

C1INV

R/W-0

CIS

R/W-0

CM2

R/W-0

CM1

R/W-0

CM0

C2OUT

C1OUT

bit 7

bit 0

bit 7

C2OUT: Comparator 2 Output bit

When C2INV = 0:

1= C2 VIN+ > C2 VIN-

0= C2 VIN+ < C2 VIN-

When C2INV = 1:

1= C2 VIN+ < C2 VIN-

0= C2 VIN+ > C2 VIN-

bit 6

C1OUT: Comparator 1 Output bit

When C1INV = 0:

1= C1 VIN+ > C1 VIN-

0= C1 VIN+ < C1 VIN-

When C1INV = 1:

1= C1 VIN+ < C1 VIN-

0= C1 VIN+ > C1 VIN-

bit 5

bit 4

bit 3

C2INV: Comparator 2 Output Inversion bit

1= C2 output inverted

0= C2 output not inverted

C1INV: Comparator 1 Output Inversion bit

1= C1 output inverted

0= C1 output not inverted

CIS: Comparator Input Switch bit

When CM2:CM0 = 110:

1= C1 VIN- connects to RF5/AN10

C2 VIN- connects to RF3/AN8

0= C1 VIN- connects to RF6/AN11

C2 VIN- connects to RF4/AN9

bit 2-0

CM2:CM0: Comparator Mode bits

Figure 20-1 shows the Comparator modes and CM2:CM0 bit settings.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 259

PIC18F6585/8585/6680/8680

mode is changed, the comparator output level may not

be valid for the specified mode change delay shown in

20.1 Comparator Configuration

There are eight modes of operation for the compara-

tors. The CMCON register is used to select these

modes. Figure 20-1 shows the eight possible modes.

The TRISF register controls the data direction of the

comparator pins for each mode. If the Comparator

Section 27.0 “Electrical Characteristics”.

Note:

Comparator interrupts should be disabled

during Comparator mode change.

Otherwise, a false interrupt may occur.

a

FIGURE 20-1:

COMPARATOR I/O OPERATING MODES

Comparators Reset (POR Default Value)

Comparators Off

CM2:CM0 = 000

CM2:CM0 = 111

A

D

VIN-

RF6/AN11

RF5/AN10

RF6/AN11

Off (Read as ‘0’)

C1

C2

C1

C2

VIN+

A

D

RF5/AN10

A

D

VIN-

RF4/AN9

RF3/AN8

RF4/AN9

VIN+

D

RF3/AN8

Two Independent Comparators with Outputs

CM2:CM0 = 011

Two Independent Comparators

CM2:CM0 = 010

A

VIN-

A

VIN-

RF6/AN11

RF5/AN10

RF6/AN11

RF5/AN10

C1OUT

C2OUT

C1

C2

VIN+

A

C1OUT

C2OUT

C1

C2

VIN+

A

RF2/AN7/C1OUT

A

VIN-

A

VIN-

RF4/AN9

RF3/AN8

RF4/AN9

VIN+

A

RF3/AN8

RF1/AN6/C2OUT

Two Common Reference Comparators

Two Common Reference Comparators with Outputs

CM2:CM0 = 100

CM2:CM0 = 101

A

VIN-

RF6/AN11

RF5/AN10

RF6/AN11

RF5/AN10

C1OUT

C2OUT

C1OUT

C1

C2

C1

C2

VIN+

A

RF2/AN7/C1OUT

A

D

VIN-

RF4/AN9

RF3/AN8

A

VIN-

VIN+

RF4/AN9

C2OUT

VIN+

D

RF3/AN8

RF1/AN6/C2OUT

Four Inputs Multiplexed to Two Comparators

One Independent Comparator with Output

CM2:CM0 = 110

CM2:CM0 = 001

A

VIN-

RF6/AN11

RF5/AN10

CIS = 0

CIS = 1

VIN-

A

C1OUT

C1

C2

VIN+

RF5/AN10

C1OUT

C2OUT

C1

C2

VIN+

RF2/AN7/C1OUT

A

RF4/AN9

RF3/AN8

VIN-

CIS = 0

CIS = 1

VIN+

D

VIN-

RF4/AN9

Off (Read as ‘0’)

VIN+

D

RF3/AN8

CVREF

From VREF Module

A = Analog Input, port reads zeros always

DS30491C-page 260

D = Digital Input

CIS (CMCON<3>) = Comparator Input Switch

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

20.3.2

INTERNAL REFERENCE SIGNAL

20.2 Comparator Operation

The comparator module also allows the selection of an

internally generated voltage reference for the compara-

tors. Section 21.0 “Comparator Voltage Reference

Module” contains a detailed description of the compar-

ator voltage reference module that provides this signal.

The internal reference signal is used when comparators

are in mode CM<2:0> = 110(Figure 20-1). In this mode,

the internal voltage reference is applied to the VIN+ pin

of both comparators.

A single comparator is shown in Figure 20-2, along with

the relationship between the analog input levels and

the digital output. When the analog input at VIN+ is less

than the analog input VIN-, the output of the comparator

is a digital low level. When the analog input at VIN+ is

greater than the analog input VIN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 20-2 represent

the uncertainty due to input offsets and response time.

20.4 Comparator Response Time

20.3 Comparator Reference

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output has a valid level. If the internal

reference is changed, the maximum delay of the inter-

nal voltage reference must be considered when using

the comparator outputs. Otherwise, the maximum

delay of the comparators should be used (Section 27.0

“Electrical Characteristics”).

An external or internal reference signal may be used

depending on the Comparator Operating mode. The

analog signal present at VIN- is compared to the signal

at VIN+ and the digital output of the comparator is

adjusted accordingly (Figure 20-2).

FIGURE 20-2:

SINGLE COMPARATOR

20.5 Comparator Outputs

VIN+

VIN-

+

Output

The comparator outputs are read through the CMCON

register. These bits are read-only. The comparator

outputs may also be directly output to the RF1 and RF2

I/O pins. When enabled, multiplexors in the output path

of the RF1 and RF2 pins will switch and the output of

each pin will be the unsynchronized output of the com-

parator. The uncertainty of each of the comparators is

related to the input offset voltage and the response time

given in the specifications. Figure 20-3 shows the

comparator output block diagram.

–

VIN-

V

IN–

VIN+

V

IN+

The TRISA bits will still function as an output

enable/disable for the RF1 and RF2 pins while in this

mode.

Output

The polarity of the comparator outputs can be changed

using the C2INV and C1INV bits (CMCON<4:5>).

20.3.1

EXTERNAL REFERENCE SIGNAL

When external voltage references are used, the

comparator module can be configured to have the com-

parators operate from the same or different reference

sources. However, threshold detector applications may

require the same reference. The reference signal must

be between VSS and VDD and can be applied to either

pin of the comparator(s).

Note 1: When reading the Port register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert an analog input according to the

Schmitt Trigger input specification.

2: Analog levels on any pin defined as a dig-

ital input may cause the input buffer to

consume more current than is specified.

 2004 Microchip Technology Inc.

DS30491C-page 261

PIC18F6585/8585/6680/8680

FIGURE 20-3:

COMPARATOR OUTPUT BLOCK DIAGRAM

Port pins

MULTIPLEX

+

-

CxINV

To RF1 or

RF2 pin

Bus

Data

Q

D

Read CMCON

EN

Q

Set

CMIF

bit

D

From

other

Comparator

EN

CL

Read CMCON

RESET

20.6 Comparator Interrupts

Note:

If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR

registers) interrupt flag may not get set.

The comparator interrupt flag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<7:6>, to

determine the actual change that occurred. The CMIF

bit (PIR registers) is the Comparator Interrupt Flag. The

CMIF bit must be reset by clearing it to ‘0’. Since it is

also possible to write a ‘1’ to this register, a simulated

interrupt may be initiated.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of CMCON will end the

mismatch condition.

b) Clear flag bit CMIF.

The CMIE bit (PIE registers) and the PEIE bit (INTCON

register) must be set to enable the interrupt. In addition,

the GIE bit must also be set. If any of these bits are

clear, the interrupt is not enabled, though the CMIF bit

will still be set if an interrupt condition occurs.

A mismatch condition will continue to set flag bit CMIF.

Reading CMCON will end the mismatch condition and

allow flag bit CMIF to be cleared.

DS30491C-page 262

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

20.7 Comparator Operation During

20.9 Analog Input Connection

Considerations

Sleep

When a comparator is active and the device is placed

in Sleep mode, the comparator remains active and the

interrupt is functional if enabled. This interrupt will

wake-up the device from Sleep mode when enabled.

While the comparator is powered up, higher Sleep

currents than shown in the power-down current

specification will occur. Each operational comparator

will consume additional current as shown in the com-

parator specifications. To minimize power consumption

while in Sleep mode, turn off the comparators

(CM<2:0> = 111) before entering Sleep. If the device

wakes up from Sleep, the contents of the CMCON

register are not affected.

A simplified circuit for an analog input is shown in

Figure 20-4. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. The analog input, therefore, must be between

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up condition may

occur. A maximum source impedance of 10 kΩ is

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

20.8 Effects of a Reset

A device Reset forces the CMCON register to its Reset

state, causing the comparator module to be in the

Comparator Reset mode (CM<2:0> = 000). This

ensures that all potential inputs are analog inputs.

Device current is minimized when analog inputs are

present at Reset time. The comparators will be

powered down during the Reset interval.

FIGURE 20-4:

COMPARATOR ANALOG INPUT MODEL

VDD

VT = 0.6V

RIC

RS < 10k

AIN

Comparator

Input

ILEAKAGE

±500 nA

CPIN

5 pF

VA

VT = 0.6V

VSS

Legend: CPIN

=

Input Capacitance

VT

= Threshold Voltage

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC

RS

VA

=

Interconnect Resistance

Source Impedance

Analog Voltage

 2004 Microchip Technology Inc.

DS30491C-page 263

PIC18F6585/8585/6680/8680

TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Value on

all other

Resets

Value on

POR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CMCON

C2OUT

C1OUT

CVROE

C2INV

C1INV

CIS

CM2

CM1

CM0

0000 0000 0000 0000

CVRCON CVREN

CVRR CVRSS CVR3

CVR2

CVR1

CVR0 0000 0000 0000 0000

RBIF 0000 0000 0000 0000

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

BCLIF

BCLIE

BCLIP

RF3

TMR0IF INT0IF

EEIF

EEIE

EEIP

RF4

PIR2

—

CMIF

CMIE

CMIP

RF6

—

LVDIF TMR3IF CCP2IF -0-0 0000 -0-0 0000

LVDIE TMR3IE CCP2IE -0-0 0000 -0-0 0000

LVDIP TMR3IP CCP2IP -1-1 1111 -1-1 1111

PIE2

IPR2

—

PORTF

LATF

RF7

RF5

LATF5

RF2

RF1

RF0

xxxx xxxx uuuu uuuu

LATF7

TRISF7

LATF6

TRISF6

LATF4 LATF3

LATF2

LATF1

LATF0 xxxx xxxx uuuu uuuu

TRISF

Legend:

TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111

x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.

DS30491C-page 264

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

21.1 Configuring the Comparator

Voltage Reference

21.0 COMPARATOR VOLTAGE

REFERENCE MODULE

The comparator voltage reference can output 16 distinct

voltage levels for each range. The equations used to

calculate the output of the comparator voltage reference

are as follows:

The comparator voltage reference is a 16-tap resistor

ladder network that provides a selectable voltage

reference. The resistor ladder is segmented to provide

two ranges of CVREF values and has a power-down

function to conserve power when the reference is not

being used. The CVRCON register controls the

operation of the reference as shown in Register 21-1.

The block diagram is given in Figure 21-1.

If CVRR = 1:

CVREF = (CVR<3:0>/24) x CVRSRC

If CVRR = 0:

CVREF = (CVDD x 1/4) + (CVR<3:0>/32) x CVRSRC

The comparator reference supply voltage can come

from either VDD or VSS, or the external VREF+ and

VREF- that are multiplexed with RA3 and RA2. The

comparator reference supply voltage is controlled by

the CVRSS bit.

The settling time of the comparator voltage reference

must be considered when changing the CVREF output

(Section 27.0 “Electrical Characteristics”).

REGISTER 21-1:

CVRCON REGISTER

R/W-0

CVRR

R/W-0

CVR3

R/W-0

CVR2

R/W-0

CVR1

R/W-0

CVR0

CVREN

CVROE

CVRSS

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

CVREN: Comparator Voltage Reference Enable bit

1= CVREF circuit powered on

0= CVREF circuit powered down

CVROE: Comparator VREF Output Enable bit⁽¹⁾

1= CVREF voltage level is also output on the RF5/AN10/C1IN+/CVREF pin

0= CVREF voltage is disconnected from the RF5/AN10/C1IN+/CVREF pin

CVRR: Comparator VREF Range Selection bit

1= 0.00 CVRSRC to 0.625 CVRSRC with CVRSRC/24 step size

0= 0.25 CVRSRC to 0.71875 CVRSRC with CVRSRC/32 step size

CVRSS: Comparator VREF Source Selection bit

1= Comparator reference source, CVRSRC = VREF+ – VREF-

0= Comparator reference source, CVRSRC = VDD – VSS

Note:

To select (VREF+ – VREF-) as the comparator voltage reference source, the voltage

reference configuration bits in the ADCON1 register (ADCON1<5:4>) must also be

set to ‘11’.

bit 3-0

CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ VR3:VR0 ≤ 15)

When CVRR = 1:

CVREF = (CVR<3:0>/24) • (CVRSRC)

When CVRR = 0:

CVREF = 1/4 • (CVRSRC) + (CVR3:CVR0/32) • (CVRSRC)

Note 1: If enabled for output, RF5 must also be configured as an input by setting TRISF<5>

to ‘1’.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 265

PIC18F6585/8585/6680/8680

FIGURE 21-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

VDD

VREF+

16 Stages

CVRSS = 1

CVRSS = 0

CVREN

R

8R

R

CVRR

CVRSS = 0

8R

CVRSS = 1

VREF-

CVR3

CVREF

(From CVRCON<3:0>)

CVR0

16-1 Analog Mux

Note: R is defined in Section 27.0 “Electrical Characteristics”.

21.2 Voltage Reference Accuracy/Error

21.4 Effects of a Reset

The full range of voltage reference cannot be realized

due to the construction of the module. The transistors

on the top and bottom of the resistor ladder network

(Figure 21-1) keep CVREF from approaching the refer-

ence source rails. The voltage reference is derived

from the reference source; therefore, the CVREF output

changes with fluctuations in that source. The tested

absolute accuracy of the voltage reference can be

found in Section 27.0 “Electrical Characteristics”.

A device Reset disables the voltage reference by

clearing bit CVREN (CVRCON<7>). This Reset also

disconnects the reference from the RA2 pin by clearing

bit CVROE (CVRCON<6>) and selects the high-

voltage range by clearing bit CVRR (CVRCON<5>).

The VRSS value select bits, CVRCON<3:0>, are also

cleared.

21.5 Connection Considerations

The voltage reference module operates independently

of the comparator module. The output of the reference

generator may be connected to the RF5 pin if the

TRISF<5> bit is set and the CVROE bit is set. Enabling

the voltage reference output onto the RF5 pin with an

input signal present will increase current consumption.

Connecting RF5 as a digital output with VRSS enabled

will also increase current consumption.

21.3 Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the CVRCON register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

The RF5 pin can be used as a simple D/A output with

limited drive capability. Due to the limited current drive

capability, a buffer must be used on the voltage refer-

ence output for external connections to VREF.

Figure 21-2 shows an example buffering technique.

DS30491C-page 266

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 21-2:

VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

(1)

RF5

R

CVREF

+

–

Module

CVREF Output

Voltage

Reference

Output

Impedance

Note 1: R is dependent upon the voltage reference configuration bits CVRCON<3:0> and CVRCON<5>.

TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE

Value on

all other

Resets

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR

CVRCON CVREN CVROE CVRR CVRSS CVR3

CVR2

CM2

CVR1

CM1

CVR0 0000 0000 0000 0000

CM0 0000 0000 0000 0000

CMCON

TRISF

C2OUT C1OUT C2INV C1INV

CIS

TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111

Legend: x= unknown, u= unchanged, -= unimplemented, read as ‘0’.

Shaded cells are not used with the comparator voltage reference.

 2004 Microchip Technology Inc.

DS30491C-page 267

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 268

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

The Low-Voltage Detect circuitry is completely under

software control. This allows the circuitry to be “turned

off” by the software which minimizes the current

consumption for the device.

22.0 LOW-VOLTAGE DETECT

In many applications, the ability to determine if the

device voltage (VDD) is below a specified voltage level

is a desirable feature. A window of operation for the

application can be created where the application soft-

ware can do “housekeeping tasks” before the device

voltage exits the valid operating range. This can be

done using the Low-Voltage Detect module.

Figure 22-1 shows a possible application voltage curve

(typically for batteries). Over time, the device voltage

decreases. When the device voltage equals voltage VA,

the LVD logic generates an interrupt. This occurs at

time TA. The application software then has the time,

until the device voltage is no longer in valid operating

range, to shut down the system. Voltage point VB is the

minimum valid operating voltage specification. This

occurs at time TB. The difference, TB – TA, is the total

time for shutdown.

This module is a software programmable circuitry

where a device voltage trip point can be specified.

When the voltage of the device becomes lower then the

specified point, an interrupt flag is set. If the interrupt is

enabled, the program execution will branch to the inter-

rupt vector address and the software can then respond

to that interrupt source.

FIGURE 22-1:

TYPICAL LOW-VOLTAGE DETECT APPLICATION

VA

VB

Legend:

VA = LVD trip point

VB = Minimum valid device

operating voltage

TB

TA

Time

The block diagram for the LVD module is shown in

Figure 22-2. A comparator uses an internally gener-

ated reference voltage as the set point. When the

selected tap output of the device voltage crosses the

set point (is lower than), the LVDIF bit is set.

supply voltage is equal to the trip point, the voltage

tapped off of the resistor array is equal to the 1.2V

internal reference voltage generated by the voltage

reference module. The comparator then generates an

interrupt signal setting the LVDIF bit. This voltage is

software programmable to any one of 16 values (see

Figure 22-2). The trip point is selected by

programming the LVDL3:LVDL0 bits (LVDCON<3:0>).

Each node in the resistor divider represents a “trip

point” voltage. The “trip point” voltage is the minimum

supply voltage level at which the device can operate

before the LVD module asserts an interrupt. When the

 2004 Microchip Technology Inc.

DS30491C-page 269

PIC18F6585/8585/6680/8680

FIGURE 22-2:

LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM

VDD

LVDIN

LVD3:LVD0

LVDCON

Register

LVDIF

Internally Generated

LVDEN

Reference Voltage

(Parameter #D423)

The LVD module has an additional feature that allows

the user to supply the trip voltage to the module from an

external source. This mode is enabled when bits

LVDL3:LVDL0 are set to ‘1111’. In this state, the com-

parator input is multiplexed from the external input pin,

LVDIN (Figure 22-3). This gives users flexibility

because it allows them to configure the Low-Voltage

Detect interrupt to occur at any voltage in the valid

operating range.

FIGURE 22-3:

LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM

VDD

LVD3:LVD0

LVDCON

Register

LVDIN

LVDEN

Externally Generated

Trip Point

LVD

VxEN

BODEN

EN

BGAP

DS30491C-page 270

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

22.1 Control Register

The Low-Voltage Detect Control register controls the

operation of the Low-Voltage Detect circuitry.

REGISTER 22-1: LVDCON REGISTER

U-0

—

U-0

—

R-0

R/W-0

LVDL3

R/W-1

LVDL2

R/W-0

LVDL1

R/W-1

LVDL0

IRVST

LVDEN

bit 7

bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5

bit 4

IRVST: Internal Reference Voltage Stable Flag bit

1= Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified

voltage range

0= Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the

specified voltage range and the LVD interrupt should not be enabled

LVDEN: Low-Voltage Detect Power Enable bit

1= Enables LVD, powers up LVD circuit

0= Disables LVD, powers down LVD circuit

bit 3-0 LVDL3:LVDL0: Low-Voltage Detection Limit bits

1111= External analog input is used (input comes from the LVDIN pin)

1110= 4.5V-4.77V

1101= 4.2V-4.45V

1100= 4.0V-4.24V

1011= 3.8V-4.03V

1010= 3.6V-3.82V

1001= 3.5V-3.71V

1000= 3.3V-3.50V

0111= 3.0V-3.18V

0110= 2.8V-2.97V

0101= 2.7V-2.86V

0100= 2.5V-2.65V

0011= 2.4V-2.54V

0010= 2.2V-2.33V

0001= 2.0V-2.12V

0000= Reserved

Note:

LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage

of the device are not tested.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 271

PIC18F6585/8585/6680/8680

The following steps are needed to set up the LVD

module:

22.2 Operation

Depending on the power source for the device voltage,

the voltage normally decreases relatively slowly. This

means that the LVD module does not need to be

constantly operating. To decrease the current require-

ments, the LVD circuitry only needs to be enabled for

short periods where the voltage is checked. After doing

the check, the LVD module may be disabled.

1. Write the value to the LVDL3:LVDL0 bits

(LVDCON register) which selects the desired

LVD trip point.

2. Ensure that LVD interrupts are disabled (the

LVDIE bit is cleared or the GIE bit is cleared).

3. Enable the LVD module (set the LVDEN bit in

the LVDCON register).

Each time that the LVD module is enabled, the circuitry

requires some time to stabilize. After the circuitry has

stabilized, all status flags may be cleared. The module

will then indicate the proper state of the system.

4. Wait for the LVD module to stabilize (the IRVST

bit to become set).

5. Clear the LVD interrupt flag which may have

falsely become set until the LVD module has

stabilized (clear the LVDIF bit).

6. Enable the LVD interrupt (set the LVDIE and the

GIE bits).

Figure 22-4 shows typical waveforms that the LVD

module may be used to detect.

FIGURE 22-4:

LOW-VOLTAGE DETECT WAVEFORMS

CASE 1:

LVDIF may not be set

VDD

VLVD

LVDIF

Enable LVD

Internally Generated

Reference Stable

TIVRST

LVDIF cleared in software

CASE 2:

VDD

VLVD

LVDIF

Enable LVD

TIVRST

Internally Generated

Reference Stable

LVDIF cleared in software

LVDIF cleared in software,

LVDIF remains set since LVD condition still exists

DS30491C-page 272

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

22.2.1

REFERENCE VOLTAGE SET POINT

22.3 Operation During Sleep

The internal reference voltage of the LVD module,

specified in electrical specification parameter #D423,

may be used by other internal circuitry (the Program-

mable Brown-out Reset). If these circuits are disabled

(lower current consumption), the reference voltage

circuit requires a time to become stable before a low-

voltage condition can be reliably detected. This time is

invariant of system clock speed. This start-up time is

specified in electrical specification parameter #36. The

low-voltage interrupt flag will not be enabled until a

stable reference voltage is reached. Refer to the

waveform in Figure 22-4.

When enabled, the LVD circuitry continues to operate

during Sleep. If the device voltage crosses the trip

point, the LVDIF bit will be set and the device will

wake-up from Sleep. Device execution will continue

from the interrupt vector address if interrupts have

been globally enabled.

22.4 Effects of a Reset

A device Reset forces all registers to their Reset state.

This forces the LVD module to be turned off.

22.2.2

CURRENT CONSUMPTION

When the module is enabled, the LVD comparator and

voltage divider are enabled and will consume static cur-

rent. The voltage divider can be tapped from multiple

places in the resistor array. Total current consumption,

when enabled, is specified in electrical specification

parameter #D022B.

 2004 Microchip Technology Inc.

DS30491C-page 273

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 274

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

23.1 Module Overview

23.0 ECAN MODULE

The CAN bus module consists of a protocol engine and

message buffering and control. The CAN protocol

engine automatically handles all functions for receiving

and transmitting messages on the CAN bus. Messages

are transmitted by first loading the appropriate data

registers. Status and errors can be checked by reading

the appropriate registers. Any message detected on

the CAN bus is checked for errors and then matched

against filters to see if it should be received and stored

in one of the two receive registers.

PIC18F6585/8585/6680/8680 devices contain an

Enhanced Controller Area Network (ECAN) module.

The ECAN module is fully backward compatible with

the CAN module available in PIC18CXX8 and

PIC18FXX8 devices.

The Controller Area Network (CAN) module is a serial

interface which is useful for communicating with other

peripherals or microcontroller devices. This interface,

or protocol, was designed to allow communications

within noisy environments.

The CAN module supports the following frame types:

The ECAN module is a communication controller,

implementing the CAN 2.0A or B protocol as defined in

the BOSCH specification. The module will support

CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B

Active versions of the protocol. The module implemen-

tation is a full CAN system; however, the CAN specifi-

cation is not covered within this data sheet. Refer to the

BOSCH CAN specification for further details.

• Standard Data Frame

• Extended Data Frame

• Remote Frame

• Error Frame

• Overload Frame Reception

• Interframe Space Generation/Detection

The CAN module uses the RG0/CANTX1,

RG1/CANTX2 and RG2/CANRX pins to interface with

the CAN bus. In Normal mode, the CAN module

automatically overrides the TRISG0 and TRISG1 bits

of the CAN module pins.

The module features are as follows:

• Implementation of the CAN protocol CAN 1.2,

CAN 2.0A and CAN 2.0B

• DeviceNet^TMdata bytes filter support

• Standard and extended data frames

• 0-8 bytes data length

23.1.1

MODULE FUNCTIONALITY

• Programmable bit rate up to 1 Mbit/sec

• Fully backward compatible with PIC18XX8 CAN

module

• Three modes of operation:

- Mode 0 – Legacy mode

The CAN bus module consists of a protocol engine,

message buffering and control (see Figure 23-1). The

protocol engine can best be understood by defining the

types of data frames to be transmitted and received by

the module.

- Mode 1 – Enhanced Legacy mode with

DeviceNet support

The following sequence illustrates the necessary initial-

ization steps before the ECAN module can be used to

transmit or receive a message. Steps can be added or

removed depending on the requirements of the

application.

- Mode 2 – FIFO mode with DeviceNet support

• Support for remote frames with automated handling

• Double-buffered receiver with two prioritized

received message storage buffers

• Six buffers programmable as RX and TX

message buffers

• 16 full (standard/extended identifier) acceptance

filters that can be linked to one of four masks

• Two full acceptance filter masks that can be

assigned to any filter

• One full acceptance filter that can be used as either

an acceptance filter or acceptance filter mask

• Three dedicated transmit buffers with application

specified prioritization and abort capability

• Programmable wake-up functionality with

integrated low-pass filter

1. Ensure that the ECAN module is in Configuration

mode.

2. Select ECAN Operational mode.

3. Set up the baud rate registers.

4. Set up the filter and mask registers.

5. Set the ECAN module to Normal mode or any

other mode required by the application logic.

• Programmable Loopback mode supports self-test

operation

• Signaling via interrupt capabilities for all CAN

receiver and transmitter error states

• Programmable clock source

• Programmable link to timer module for

time-stamping and network synchronization

• Low-Power Sleep mode

 2004 Microchip Technology Inc.

DS30491C-page 275

PIC18F6585/8585/6680/8680

FIGURE 23-1:

CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM

16-4 to 1 muxs

BUFFERS

Acceptance Filters

(RXF0 – RXF05)

MODE 0

TXB0

TXB1

TXB2

VCC

A

c

e

p

t

RXF15

Acceptance Filters

(RXF06 – RXF15)

MODE 1, 2

MODE 0

2 RX

Buffers

Message

Queue

Control

Identifier

M

A

B

Transmit Byte Sequencer

Data Field

Rcv Byte

MODE 1, 2

6 TX/RX

Buffers

Transmit Option

MESSAGE

BUFFERS

PROTOCOL

ENGINE

Receive

Error

Counter

REC

TEC

Transmit

Error

Counter

Err-Pas

Bus-Off

Transmit<7:0>

Shift<14:0>

Receive<8:0>

{Transmit<5:0>, Receive<8:0>}

Comparator

Protocol

Finite

State

Machine

CRC<14:0>

Bit

Timing

Logic

Transmit

Logic

Clock

Generator

Configuration

Registers

TX

RX

DS30491C-page 276

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

23.2.1

CAN CONTROL AND STATUS

REGISTERS

23.2 CAN Module Registers

Note:

Not all CAN registers are available in the

Access Bank.

The registers described in this section control the

overall operation of the CAN module and show its

operational status.

There are many control and data registers associated

with the CAN module. For convenience, their

descriptions have been grouped into the following

sections:

• Control and Status Registers

• Dedicated Transmit Buffer Registers

• Dedicated Receive Buffer Registers

• Programmable TX/RX and Auto RTR Buffers

• Baud Rate Control Registers

• I/O Control Register

• Interrupt Status and Control Registers

Detailed descriptions of each register and their usage

are described in the following sections.

 2004 Microchip Technology Inc.

DS30491C-page 277

PIC18F6585/8585/6680/8680

REGISTER 23-1: CANCON: CAN CONTROL REGISTER

R/W-1

R/W-0

R/S-0

ABAT

R/W-0

WIN2

R/W-0

WIN1

R/W-0

WIN0

U-0

—

Mode 0

Mode 1

Mode 2

REQOP2 REQOP1 REQOP0

R/W-1

R/W-0

R/S-0

ABAT

U-0

—

U-0

—

U-0

—

U-0

—

REQOP2 REQOP1 REQOP0

R/W-1

R/W-0

R/S-0

ABAT

R-0

REQOP2 REQOP1 REQOP0

bit 7

FP3

FP2

FP1

FP0

bit 0

bit 7-5

REQOP2:REQOP0: Request CAN Operation Mode bits

1xx= Request Configuration mode

011= Request Listen Only mode

010= Request Loopback mode

001= Request Disable mode

000= Request Normal mode

bit 4

ABAT: Abort All Pending Transmissions bit

1= Abort all pending transmissions (in all transmit buffers)

0= Transmissions proceeding as normal

bit 3-1

Mode 0:

WIN2:WIN0: Window Address bits

This selects which of the CAN buffers to switch into the access bank area. This allows access

to the buffer registers from any data memory bank. After a frame has caused an interrupt, the

ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer. See

Example 23-2 for a code example.

111= Receive Buffer 0

110= Receive Buffer 0

101= Receive Buffer 1

100= Transmit Buffer 0

011= Transmit Buffer 1

010= Transmit Buffer 2

001= Receive Buffer 0

000= Receive Buffer 0

bit 0

Unimplemented: Read as ‘0’

bit 3-0

Mode 1:

Unimplemented: Read as ‘0’

Mode 2:

FP3:FP0: FIFO Read Pointer bits

These bits point to the message buffer to be read.

0111:0000= Message buffer to be read

1111:1000= Reserved

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

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REGISTER 23-2: CANSTAT: CAN STATUS REGISTER

R-1

R-0

—

R-0

U-0

—

Mode 0

(1)

OPMODE2 OPMODE1 OPMODE0

ICODE2 ICODE1 ICODE0

R-1

R-0

Mode 1, 2

(1)

OPMODE2 OPMODE1 OPMODE0 EICODE4 EICODE3 EICODE2 EICODE1 EICODE0

bit 7

bit 0

bit 7-5

OPMODE2:OPMODE0: Operation Mode Status bits⁽¹⁾

111= Reserved

110= Reserved

101= Reserved

100= Configuration mode

011= Listen Only mode

010= Loopback mode

001= Disable/Sleep mode

000= Normal mode

bit 4

Mode 0:

Unimplemented: Read as ‘0’

ICODE2:ICODE0: Interrupt Code bits in Mode 0

bit 3-1

When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This

code indicates the source of the interrupt. By copying ICODE2:ICODE0 to WIN2:WIN0, it is pos-

sible to select the correct buffer to map into the Access Bank area. See Example 23-2 for a code

example.

ICODE2:ICODE0 Value

No interrupt

000

001

010

011

100

101

110

111

Error interrupt

TXB2 interrupt

TXB1 interrupt

TXB0 interrupt

RXB1 interrupt

RXB0 interrupt

Wake-up interrupt

bit 0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 279

PIC18F6585/8585/6680/8680

REGISTER 23-2: CANSTAT: CAN STATUS REGISTER (CONTINUED)

bit 4-0

Mode 1,2:

EICODE4:EICODE0: Interrupt Code bits in Mode 1 and Mode 2

When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This

code indicates the source of the interrupt. Unlike ICODE bits in Mode 0, these bits may not be

copied directly to EWIN bits to map interrupted buffer to Access Bank area. If required, user

software may maintain a table in program memory to map EICODE bits to EWIN bits and access

interrupt buffer in Access Bank area.

EICODE4:EICODE0 Value

No interrupt

Error interrupt

00000

00010

TXB2 interrupt

00100

TXB1 interrupt

00110

TXB0 interrupt

RXB1 interrupt

01000

10001/10000⁽²⁾

RXB0 interrupt

10000

Wake-up interrupt

RX/TX B0 interrupt

RX/TX B1 interrupt

RX/TX B2 interrupt

RX/TX B3 interrupt

RX/TX B4 interrupt

01110

10010⁽²⁾

10011⁽²⁾

10100⁽²⁾

10101⁽²⁾

10110⁽²⁾

10111⁽²⁾

Note 1: To achieve maximum power saving and/or able to wake-up on CAN bus activity,

switch CAN module to Disable mode before putting the device to Sleep.

2: In Mode 2, if the buffer is configured as a receiver, EICODE bits will always contain

‘10000’ upon interrupt.

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit

‘0’ = Bit is cleared

- n = Value at POR

x = Bit is unknown

C = Clearable bit

‘1’ = Bit is set

DS30491C-page 280

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PIC18F6585/8585/6680/8680

EXAMPLE 23-1:

CHANGING TO CONFIGURATION MODE

; Request Configuration mode.

MOVLW

MOVWF

B’10000000’

CANCON

; Set to Configuration Mode.

; A request to switch to Configuration mode may not be immediately honored.

; Module will wait for CAN bus to be idle before switching to Configuration Mode.

; Request for other modes such as Loopback, Disable etc. may be honored immediately.

; It is always good practice to wait and verify before continuing.

ConfigWait:

MOVF

ANDLW

CANSTAT, W

B’10000000’

; Read current mode state.

; Interested in OPMODE bits only.

; Is it Configuration mode yet?

; No. Continue to wait...

TSTFSZ WREG

BRA

ConfigWait

; Module is in Configuration mode now.

; Modify configuration registers as required.

; Switch back to Normal mode to be able to communicate.

EXAMPLE 23-2:

WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS

TX/RX BUFFERS

; Save application required context.

; Poll interrupt flags and determine source of interrupt

; This was found to be CAN interrupt

; TempCANCON and TempCANSTAT are variables defined in Access Bank low

MOVFF

CANCON, TempCANCON

; Save CANCON.WIN bits

; This is required to prevent CANCON

; from corrupting CAN buffer access

; in-progress while this interrupt

; occurred

MOVFF

CANSTAT, TempCANSTAT

; Save CANSTAT register

; This is required to make sure that

; we use same CANSTAT value rather

; than one changed by another CAN

; interrupt.

MOVF

ANDLW

ADDWF

TempCANSTAT, W

B’00001110’

PCL, F

; Retrieve ICODE bits

; Perform computed GOTO

; to corresponding interrupt cause

; 000 = No interrupt

; 001 = Error interrupt

; 010 = TXB2 interrupt

; 011 = TXB1 interrupt

; 100 = TXB0 interrupt

; 101 = RXB1 interrupt

; 110 = RXB0 interrupt

; 111 = Wake-up on interrupt

BRA

NoInterrupt

ErrorInterrupt

TXB2Interrupt

TXB1Interrupt

TXB0Interrupt

RXB1Interrupt

RXB0Interrupt

WakeupInterrupt

BCF

PIR3, WAKIF

; Clear the interrupt flag

;

; User code to handle wake-up procedure

;

; Continue checking for other interrupt source or return from here

…

NoInterrupt

…

; PC should never vector here. User may

; place a trap such as infinite loop or pin/port

; indication to catch this error.

 2004 Microchip Technology Inc.

DS30491C-page 281

PIC18F6585/8585/6680/8680

EXAMPLE 23-2:

WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS

TX/RX BUFFERS (CONTINUED)

ErrorInterrupt

BCF

…

PIR3, ERRIF

; Clear the interrupt flag

; Handle error.

RETFIE

TXB2Interrupt

BCF

GOTO

TXB1Interrupt

BCF

GOTO

TXB0Interrupt

BCF

GOTO

RXB1Interrupt

PIR3, TXB2IF

AccessBuffer

; Clear the interrupt flag

PIR3, TXB1IF

AccessBuffer

PIR3, TXB0IF

AccessBuffer

BCF

GOTO

PIR3, RXB1IF

Accessbuffer

RXB0Interrupt

BCF

GOTO

PIR3, RXB0IF

AccessBuffer

; Clear the interrupt flag

AccessBuffer

; This is either TX or RX interrupt

; Copy CANSTAT.ICODE bits to CANCON.WIN bits

MOVF

TempCANCON, W

; Clear CANCON.WIN bits before copying

; new ones.

ANDLW

B’11110001’

; Use previously saved CANCON value to

; make sure same value.

MOVWF

MOVF

ANDLW

TempCANCON

TempCANSTAT, W

B’00001110’

; Copy masked value back to TempCANCON

; Retrieve ICODE bits

; Use previously saved CANSTAT value

; to make sure same value.

IORWF

MOVFF

TempCANCON

TempCANCON, CANCON

; Copy ICODE bits to WIN bits.

; Copy the result to actual CANCON

; Access current buffer…

; User code

; Restore CANCON.WIN bits

MOVF

ANDLW

IORWF

CANCON, W

B’11110001’

TempCANCON

; Preserve current non WIN bits

; Restore original WIN bits

; Do not need to restore CANSTAT - it is read-only register.

; Return from interrupt or check for another module interrupt source

DS30491C-page 282

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REGISTER 23-3: ECANCON: ENHANCED CAN CONTROL REGISTER

R/W-0

R/W-1

R/W-0

MDSEL1^{(1, 2)}MDSEL0^{(1, 2)}FIFOWM EWIN4

EWIN3

EWIN2

EWIN1

EWIN0

bit 7

bit 0

bit 7-6

MDSEL1:MDSEL0: Mode Select bits

00= Legacy mode (Mode 0, default)

01= Enhanced Legacy mode (Mode 1)

10= Enhanced FIFO mode (Mode 2)

11= Reserved

bit 5

FIFOWM: FIFO High Water Mark bit⁽³⁾

1= Will cause FIFO interrupt when one receive buffer remains⁽⁴⁾

0= Will cause FIFO interrupt when four receive buffers remain

bit 4-0

EWIN4:EWIN0: Enhanced Window Address bits

These bits map the group of 16 banked CAN SFRs into access bank addresses 0F60-0F6Dh.

Exact group of registers to map is determined by binary value of these bits.

Mode 0:

Unimplemented: Read as ‘0’

Mode 1, 2:

00000= Acceptance Filters 0, 1, 2 and BRGCON3, 2

00001= Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON

00010= Acceptance Filter Masks, Error and Interrupt Control

00011= Transmit Buffer 0

00100= Transmit Buffer 1

00101= Transmit Buffer 2

00110= Acceptance Filters 6, 7, 8

00111= Acceptance Filters 9, 10, 11

01000= Acceptance Filters 12, 13, 14

01001= Acceptance Filters 15

01010-01111= Reserved

10000 = Receive Buffer 0

10001 = Receive Buffer 1

10010 = TX/RX Buffer 0

10011 = TX/RX Buffer 1

10100 = TX/RX Buffer 2

10101 = TX/RX Buffer 3

10110 = TX/RX Buffer 4

10111 = TX/RX Buffer 5

11000-11111= Reserved

Note 1: These bits can only be changed in Configuration mode. See Register 19-2 to

change to Configuration mode.

2: A new mode takes into effect only after Configuration mode is exited.

3: This bit is used in Mode 2 only.

4: FIFO length of 4 or less will cause this bit to be set.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

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PIC18F6585/8585/6680/8680

REGISTER 23-4: COMSTAT: COMMUNICATION STATUS REGISTER

R/C-0

R-0

Mode 0

Mode 1

Mode 2

RXB0OVFL RXB1OVFL TXBO

TXBP

RXBP

TXWARN RXWARN EWARN

U-0

—

R/C-0

R-0

RXBnOVFL

TXB0

TXBP

RXBP

TXWARN RXWARN EWARN

R/C-0

R-0

FIFOEMPTY RXBnOVFL TXBO

bit 7

TXBP

RXBP

TXWARN RXWARN EWARN

bit 0

bit 7

Mode 0:

RXB0OVFL: Receive Buffer 0 Overflow bit

1= Receive Buffer 0 overflowed

0= Receive Buffer 0 has not overflowed

Mode 1:

Unimplemented: Read as ‘0’

Mode 2:

FIFOEMPTY: FIFO Not Empty bit

1= Receive FIFO is not empty

0= Receive FIFO is empty

bit 6

Mode 0:

RXB1OVFL: Receive Buffer 1 Overflow bit

1= Receive Buffer 1 overflowed

0= Receive Buffer 1 has not overflowed

Mode 1, 2:

RXBnOVFL: Receive Buffer Overflow bit

1= Receive buffer has overflowed

0= Receive buffer has not overflowed

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TXBO: Transmitter Bus-Off bit

1= Transmit error counter > 255

0= Transmit error counter ≤ 255

TXBP: Transmitter Bus Passive bit

1= Transmit error counter > 127

0= Transmit error counter ≤ 127

RXBP: Receiver Bus Passive bit

1= Receive error counter > 127

0= Receive error counter ≤ 127

TXWARN: Transmitter Warning bit

1= 127 ≥ Transmit error counter > 95

0= Transmit error counter ≤ 95

RXWARN: Receiver Warning bit

1= 127 ≥ Receive error counter > 95

0= Receive error counter ≤ 95

EWARN: Error Warning bit

This bit is a flag of the RXWARN and TXWARN bits.

1= The RXWARN or the TXWARN bits are set

0= Neither the RXWARN or the TXWARN bits are set

Legend:

C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR ‘1’ = Bit is set

DS30491C-page 284

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23.2.2

DEDICATED CAN TRANSMIT

BUFFER REGISTERS

This section describes the dedicated CAN Transmit

Buffer registers and their associated control registers.

REGISTER 23-5: TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0 ≤ n ≤ 2]

U-0

R-0

R/W-0

U-0

R/W-0

Mode 0

—

TXABT

TXLARB

TXERR

TXREQ

—

TXPRI1

TXPRI0

R/C-0

TXBIF

R-0

R/W-0

U-0

—

R/W-0

Mode 1, 2

TXABT

TXLARB

TXERR

TXREQ

TXPRI1

TXPRI0

bit 7

bit 0

bit 7

Mode 0:

Unimplemented: Read as ‘0’

Mode 1, 2:

TXBIF: Transmit Buffer Interrupt Flag bit

1= Transmit buffer has completed transmission of message and may be reloaded

0= Transmit buffer has not completed transmission of a message

bit 6

bit 5

bit 4

bit 3

TXABT: Transmission Aborted Status bit⁽¹⁾

1= Message was aborted

0= Message was not aborted

TXLARB: Transmission Lost Arbitration Status bit⁽¹⁾

1= Message lost arbitration while being sent

0= Message did not lose arbitration while being sent

TXERR: Transmission Error Detected Status bit⁽¹⁾

1= A bus error occurred while the message was being sent

0= A bus error did not occur while the message was being sent

TXREQ: Transmit Request Status bit⁽²⁾

1= Requests sending a message. Clears the TXABT, TXLARB, and TXERR bits.

0= Automatically cleared when the message is successfully sent

Note:

Clearing this bit in software while the bit is set, will request a message abort.

bit 2

Unimplemented: Read as ‘0’

bit 1-0

TXPRI1:TXPRI0: Transmit Priority bits⁽³⁾

11= Priority Level 3 (highest priority)

10= Priority Level 2

01= Priority Level 1

00= Priority Level 0 (lowest priority)

Note 1: This bit is automatically cleared when TXREQ is set.

2: While TXREQ is set, Transmit Buffer registers remain read-only.

3: These bits define the order in which transmit buffers will be transferred. They do not

alter the CAN message identifier.

Legend:

C = Clearable bit R = Readable bit W = Writable bit

‘1’ = Bit is set ‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

- n = Value at POR

x = Bit is unknown

 2004 Microchip Technology Inc.

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PIC18F6585/8585/6680/8680

REGISTER 23-6: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS,

HIGH BYTE [0 ≤ n ≤ 2]

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

SID10

SID9

bit 7

bit 0

bit 7-0

SID10:SID3: Standard Identifier bits, if EXIDE (TXBnSIDL<3>) = 0;

Extended Identifier bits EID28:EID21, if EXIDE = 1.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-7: TXBnSIDL: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS,

LOW BYTE [0 ≤ n ≤ 2]

R/W-x

SID0

U-0

—

R/W-x

EXIDE

U-0

—

R/W-x

EID17

R/W-x

EID16

SID2

SID1

bit 7

bit 0

bit 7-5

SID2:SID0: Standard Identifier bits, if EXIDE (TXBnSIDL<3>) = 0;

Extended Identifier bits EID20:EID18, if EXIDE = 1.

Unimplemented: Read as ‘0’

bit 4

bit 3

EXIDE: Extended Identifier Enable bit

1= Message will transmit extended ID, SID10:SID0 becomes EID28:EID18

0= Message will transmit standard ID, EID17:EID0 are ignored

bit 2

Unimplemented: Read as ‘0’

bit 1-0

EID17:EID16: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-8: TXBnEIDH: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS,

HIGH BYTE [0 ≤ n ≤ 2]

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

EID15

EID14

bit 7

bit 0

bit 7-0

EID15:EID8: Extended Identifier bits (not used when transmitting standard identifier message)

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 286

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REGISTER 23-9: TXBnEIDL: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS,

LOW BYTE [0 ≤ n ≤ 2]

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

EID7

EID6

bit 7

bit 0

bit 7-0

EID7:EID0: Extended Identifier bits (not used when transmitting standard identifier message)

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-10: TXBnDm: TRANSMIT BUFFER n DATA FIELD BYTE m REGISTERS

[0 ≤ n ≤ 2, 0 ≤ m ≤ 7]

R/W-x

TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0

bit 7 bit 0

R/W-x

bit 7-0

TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 ≤ m < 8)

Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers:

TXB0D0 to TXB0D7.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 287

PIC18F6585/8585/6680/8680

REGISTER 23-11: TXBnDLC: TRANSMITBUFFER n DATA LENGTHCODE REGISTERS[0 ≤ n≤ 2]

U-0

—

R/W-x

U-0

—

U-0

—

R/W-x

DLC3

R/W-x

DLC2

R/W-x

DLC1

R/W-x

DLC0

TXRTR

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ‘0’

TXRTR: Transmit Remote Frame Transmission Request bit

1= Transmitted message will have TXRTR bit set

0= Transmitted message will have TXRTR bit cleared

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

DLC3:DLC0: Data Length Code bits

1111= Reserved

1110= Reserved

1101= Reserved

1100= Reserved

1011= Reserved

1010= Reserved

1001= Reserved

1000= Data length = 8 bytes

0111= Data length = 7 bytes

0110= Data length = 6 bytes

0101= Data length = 5 bytes

0100= Data length = 4 bytes

0011= Data length = 3 bytes

0010= Data length = 2 bytes

0001= Data length = 1 bytes

0000= Data length = 0 bytes

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-12: TXERRCNT: TRANSMIT ERROR COUNT REGISTER

R-0

TEC7

TEC6

TEC5

TEC4

TEC3

TEC2

TEC1

TEC0

bit 7

bit 0

bit 7-0

TEC7:TEC0: Transmit Error Counter bits

This register contains a value which is derived from the rate at which errors occur. When the

error count overflows, the bus-off state occurs. When the bus has 128 occurrences of

11 consecutive recessive bits, the counter value is cleared.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 288

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PIC18F6585/8585/6680/8680

EXAMPLE 23-3:

TRANSMITTING A CAN MESSAGE USING BANKED METHOD

; Need to transmit Standard Identifier message 123h using TXB0 buffer.

; To successfully transmit, CAN module must be either in Normal or Loopback mode.

; TXB0 buffer is not in access bank. And since we want banked method, we need to make sure

; that correct bank is selected.

BANKSELTXB0CON

; One BANKSEL in beginning will make sure that we are

; in correct bank for rest of the buffer access.

; Now load transmit data into TXB0 buffer.

MOVLW

MOVWF

MY_DATA_BYTE1

TXB0D0

; Load first data byte into buffer

; Compiler will automatically set “BANKED” bit

; Load rest of data bytes - up to 8 bytes into TXB0 buffer.

...

; Load message identifier

MOVLW

MOVWF

MOVLW

MOVWF

60H

TXB0SIDL

24H

; Load SID2:SID0, EXIDE = 0

; Load SID10:SID3

TXB0SIDH

; No need to load TXB0EIDL:TXB0EIDH, as we are transmitting Standard Identifier Message only.

; Now that all data bytes are loaded, mark it for transmission.

MOVLW

MOVWF

B’00001000’

TXB0CON

; Normal priority; Request transmission

; If required, wait for message to get transmitted

BTFSC

BRA

TXB0CON, TXREQ

$-2

; Is it transmitted?

; No. Continue to wait...

; Message is transmitted.

 2004 Microchip Technology Inc.

DS30491C-page 289

PIC18F6585/8585/6680/8680

EXAMPLE 23-4:

TRANSMITTING A CAN MESSAGE USING WIN BITS

; Need to transmit Standard Identifier message 123h using TXB0 buffer.

; To successfully transmit, CAN module must be either in Normal or Loopback mode.

; TXB0 buffer is not in access bank. Use WIN bits to map it to RXB0 area.

MOVF

CANCON, W

; WIN bits are in lower 4 bits only. Read CANCON

; register to preserve all other bits. If operation

; mode is already known, there is no need to preserve

; other bits.

ANDLW

IORLW

MOVWF

B’11110000’

B’00001000’

CANCON

; Clear WIN bits.

; Select Transmit Buffer 0

; Apply the changes.

; Now TXB0 is mapped in place of RXB0. All future access to RXB0 registers will actually

; yield TXB0 register values.

; Load transmit data into TXB0 buffer.

MOVLW

MOVWF

MY_DATA_BYTE1

RXB0D0

; Load first data byte into buffer

; Access TXB0D0 via RXB0D0 address.

; Load rest of the data bytes - up to 8 bytes into “TXB0” buffer using RXB0 registers.

...

; Load message identifier

MOVLW

MOVWF

MOVLW

MOVWF

60H

RXB0SIDL

24H

; Load SID2:SID0, EXIDE = 0

; Load SID10:SID3

RXB0SIDH

; No need to load RXB0EIDL:RXB0EIDH, as we are transmitting Standard Identifier Message only.

; Now that all data bytes are loaded, mark it for transmission.

MOVLW

MOVWF

B’00001000’

RXB0CON

; Normal priority; Request transmission

; If required, wait for message to get transmitted

BTFSC

BRA

RXB0CON, TXREQ

$-2

; Is it transmitted?

; No. Continue to wait...

; Message is transmitted.

; If required, reset the WIN bits to default state.

DS30491C-page 290

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PIC18F6585/8585/6680/8680

23.2.3

DEDICATED CAN RECEIVE

BUFFER REGISTERS

This section shows the dedicated CAN Receive Buffer

registers with their associated control registers.

REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER

R/C-0

R/W-0

RXM1

R/W-0

RXM0

U-0

—

R-0

R/W-0

R-0

Mode 0

Mode 1, 2

bit 7

RXFUL

RXRTRRO RXB0DBEN JTOFF

FILHIT0

R/C-0

R/W-0

RXM1

R-0

RXFUL

RTRRO

FILHIT4

FILHIT3

FILHIT2

FILHIT1 FILHIT0

bit 0

bit 7

RXFUL: Receive Full Status bit

1= Receive buffer contains a received message

0= Receive buffer is open to receive a new message

Note:

This bit is set by the CAN module upon receiving a message and must be cleared

by software after the buffer is read. As long as RXFUL is set, no new message will

be loaded and buffer will be considered full.

bit 6

Mode 0:

RXM1: Receive Buffer Mode bit 1; combines with RXM0 to form RXM<1:0> bits (see bit 5)

11= Receive all messages (including those with errors); filter criteria is ignored

10= Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’

01= Receive only valid messages with standard identifier, EXIDEN in RXFnSIDL must be ‘0’

00= Receive all valid messages as per EXIDEN bit in RXFnSIDL register

Mode 1, 2:

RXM1: Receive Buffer Mode bit

1= Receive all messages (including those with errors); acceptance filters are ignored

0= Receive all valid messages as per acceptance filters

bit 5

Mode 0:

RXM0: Receive Buffer Mode bit 0; combines with RXM1 to form RXM<1:0> bits (see bit 6)

Mode 1, 2:

RTRRO: Remote Transmission Request bit for Received Message (read-only)

1= A remote transmission request is received

0= A remote transmission request is not received

bit 4

bit 3

Mode 0:

Unimplemented: Read as ‘0’

Mode 1, 2:

FILHIT4: Filter Hit bit 4

This bit combines with other bits to form filter acceptance bits <4:0>.

Mode 0:

RXRTRRO: Remote Transmission Request bit for Received Message (read-only)

1= A remote transmission request is received

0= A remote transmission request is not received

Mode 1, 2:

FILHIT3: Filter Hit bit 3

This bit combines with other bits to form filter acceptance bits <4:0>.

Legend:

C = Clearable bit R = Readable bit W = Writable bit

‘1’ = Bit is set ‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

- n = Value at POR

x = Bit is unknown

 2004 Microchip Technology Inc.

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REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED)

bit 2

Mode 0:

RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit

1= Receive Buffer 0 overflow will write to Receive Buffer 1

0= No Receive Buffer 0 overflow to Receive Buffer 1

Mode 1, 2:

FILHIT2: Filter Hit bit 2

This bit combines with other bits to form filter acceptance bits <4:0>.

bit 1

Mode 0:

JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN)

1= Allows jump table offset between 6 and 7

0= Allows jump table offset between 1 and 0

Note:

This bit allows same filter jump table for both RXB0CON and RXB1CON.

Mode 1, 2:

FILHIT1: Filter Hit bit 1

This bit combines with other bits to form filter acceptance bits <4:0>.

bit 0

Mode 0:

FILHIT0: Filter Hit bit 0

This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0.

1= Acceptance Filter 1 (RXF1)

0= Acceptance Filter 0 (RXF0)

Mode 1, 2:

FILHIT0: Filter Hit bit 0

This bit, in combination with FILHIT<4:1>, indicates which acceptance filter enabled the

message reception into this receive buffer.

01111= Acceptance Filter 15 (RXF15)

01110= Acceptance Filter 14 (RXF14)

...

00000= Acceptance Filter 0 (RXF0)

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit

‘0’ = Bit is cleared

- n = Value at POR

x = Bit is unknown

C = Clearable bit

‘1’ = Bit is set

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REGISTER 23-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER

R/C-0

R/W-0

U-0

R-0

R/W-0

R-0

Mode 0

RXFUL

RXM1

RXM0

—

RXRTRRO

FILHIT2

FILHIT1

FILHIT0

R/C-0

R/W-0

RXM1

R-0

Mode 1, 2

RXFUL

RTRRO

FILHIT4

FILHIT3

FILHIT2

FILHIT1

FILHIT0

bit 7

bit 0

bit 7

RXFUL: Receive Full Status bit

1= Receive buffer contains a received message

0= Receive buffer is open to receive a new message

Note:

This bit is set by the CAN module upon receiving a message and must be cleared by software after

the buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be

considered full.

Mode 0:

bit 6

RXM1: Receive Buffer Mode bit 1; combines with RXM0 to form RXM<1:0> bits (see bit 5)

11= Receive all messages (including those with errors); filter criteria is ignored

10= Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’

01= Receive only valid messages with standard identifier, EXIDEN in RXFnSIDL must be ‘0’

00= Receive all valid messages as per EXIDEN bit in RXFnSIDL register

Mode 1, 2:

RXM1: Receive Buffer Mode bit

1= Receive all messages (including those with errors); acceptance filters are ignored

0= Receive all valid messages as per acceptance filters

bit 5

Mode 0:

RXM0: Receive Buffer Mode bit 0; combines with RXM1 to form RXM<1:0> bits (see bit 6)

Mode 1, 2:

RTRRO: Remote Transmission Request bit for Received Message (read-only)

1= A remote transmission request is received

0= A remote transmission request is not received

bit 4

bit 3

Mode 0:

Unimplemented: Read as ‘0’

Mode 1, 2:

FILHIT4: Filter Hit bit 4

This bit combines with other bits to form filter acceptance bits <4:0>.

Mode 0:

RXRTRRO: Remote Transmission Request bit for Received Message (read-only)

1= A remote transmission request is received

0= A remote transmission request is not received

Mode 1, 2:

FILHIT3: Filter Hit bit 3

This bit combines with other bits to form filter acceptance bits <4:0>.

bit 2-0

Mode 0:

FILHIT2:FILHIT0: Filter Hit bits

These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1.

111= Reserved

110= Reserved

101= Acceptance Filter 5 (RXF5)

100= Acceptance Filter 4 (RXF4)

011= Acceptance Filter 3 (RXF3)

010= Acceptance Filter 2 (RXF2)

001= Acceptance Filter 1 (RXF1), only possible when RXB0DBEN bit is set

000= Acceptance Filter 0 (RXF0), only possible when RXB0DBEN bit is set

Mode 1, 2:

FILHIT2:FILHIT0 Filter Hit bits <2:0>

These bits, in combination with FILHIT<4:3>, indicate which acceptance filter enabled the message reception

into this receive buffer.

01111= Acceptance Filter 15 (RXF15)

01110= Acceptance Filter 14 (RXF14)

...

00000= Acceptance Filter 0 (RXF0)

Legend:

U = Unimplemented bit, read as ‘0’

- n = Value at POR

x = Bit is unknown

C = Clearable bit

‘1’ = Bit is set

R = Readable bit

‘0’ = Bit is cleared

W = Writable bit

 2004 Microchip Technology Inc.

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REGISTER 23-15: RXBnSIDH: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS,

HIGH BYTE [0 ≤ n ≤ 1]

R-x

SID10

SID9

SID8

SID7

SID6

SID5

SID4

SID3

bit 7

bit 0

bit 7-0

SID10:SID3: Standard Identifier bits, if EXID = 0(RXBnSIDL<3>);

Extended Identifier bits EID28:EID21, if EXID = 1.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-16: RXBnSIDL: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS,

LOW BYTE [0 ≤ n ≤ 1]

R-x

U-0

—

R-x

SID2

SID1

SID0

SRR

EXID

EID17

EID16

bit 7

bit 0

bit 7-5

bit 4

SID2:SID0: Standard Identifier bits, if EXID = 0;

Extended Identifier bits EID20:EID18, if EXID = 1.

SRR: Substitute Remote Request bit

This bit is always ‘0’ when EXID = 1or equal to the value of RXRTRRO (RBXnCON<3>)

when EXID = 0.

bit 3

EXID: Extended Identifier bit

1= Received message is an extended data frame, SID10:SID0 are EID28:EID18

0= Received message is a standard data frame

bit 2

Unimplemented: Read as ‘0’

bit 1-0

EID17:EID16: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-17: RXBnEIDH: RECEIVE BUFFER n EXTENDED IDENTIFIER REGISTERS,

HIGH BYTE [0 ≤ n ≤ 1]

R-x

EID8

bit 0

EID15

EID14

EID13

EID12

EID11

EID10

EID9

bit 7

bit 7-0

EID15:EID8: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

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REGISTER 23-18: RXBnEIDL: RECEIVE BUFFER n EXTENDED IDENTIFIER REGISTERS,

LOW BYTE [0 ≤ n ≤ 1]

R-x

EID7

EID6

EID5

EID4

EID3

EID2

EID1

EID0

bit 7

bit 0

bit 7-0

EID7:EID0: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-19: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTERS [0 ≤ n ≤ 1]

U-0

R-x

—

RXRTR

RB1

RB0

DLC3

DLC2

DLC1

DLC0

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ‘0’

RXRTR: Receiver Remote Transmission Request bit

1= Remote transfer request

0= No remote transfer request

bit 5

RB1: Reserved bit 1

Reserved by CAN Spec and read as ‘0’.

RB0: Reserved bit 0

bit 4

Reserved by CAN Spec and read as ‘0’.

DLC3:DLC0: Data Length Code bits

bit 3-0

1111= Invalid

1110= Invalid

1101= Invalid

1100= Invalid

1011= Invalid

1010= Invalid

1001= Invalid

1000= Data length = 8 bytes

0111= Data length = 7 bytes

0110= Data length = 6 bytes

0101= Data length = 5 bytes

0100= Data length = 4 bytes

0011= Data length = 3 bytes

0010= Data length = 2 bytes

0001= Data length = 1 bytes

0000= Data length = 0 bytes

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

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PIC18F6585/8585/6680/8680

REGISTER 23-20: RXBnDm: RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS

[0 ≤ n ≤ 1, 0 ≤ m ≤ 7]

R-x

RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0

bit 7 bit 0

R-x

bit 7-0

RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0 ≤ n < 1 and 0 < m < 7)

Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers:

RXB0D0 to RXB0D7.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-21: RXERRCNT: RECEIVE ERROR COUNT REGISTER

R-0

REC7

REC6

REC5

REC4

REC3

REC2

REC1

REC0

bit 7

bit 0

bit 7-0

REC7:REC0: Receive Error Counter bits

This register contains the receive error value as defined by the CAN specifications.

When RXERRCNT > 127, the module will go into an error-passive state. RXERRCNT does not

have the ability to put the module in “bus-off” state.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

EXAMPLE 23-5:

READING A CAN MESSAGE

; Need to read a pending message from RXB0 buffer.

; To receive any message, filter, mask and RXM1:RXM0 bits in RXB0CON registers must be

; programmed correctly.

;

; Make sure that there is a message pending in RXB0.

BTFSS

BRA

RXB0CON, RXFUL

NoMessage

; Does RXB0 contain a message?

; No. Handle this situation...

; We have verified that a message is pending in RXB0 buffer.

; If this buffer can receive both Standard or Extended Identifier messages,

; identify type of message received.

BTFSS

BRA

RXB0SIDL, EXID

StandardMessage

; Is this Extended Identifier?

; No. This is Standard Identifier message.

; Yes. This is Extended Identifier message.

; Read all 29-bits of Extended Identifier message.

...

; Now read all data bytes

MOVFF

...

RXB0DO, MY_DATA_BYTE1

; Once entire message is read, mark the RXB0 that it is read and no longer FULL.

BCF

RXB0CON, RXFUL

; This will allow CAN Module to load new messages

; into this buffer.

...

DS30491C-page 296

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23.2.3.1

Programmable TX/RX and

Auto RTR Buffers

The ECAN module contains 6 message buffers that can

be programmed as transmit or receive buffers. Any of

these buffers can also be programmed to automatically

handle RTR messages.

Note:

These registers are not used in Mode 0.

REGISTER 23-22: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN RECEIVE MODE

[0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0]⁽¹⁾

R/C-0

R/W-0

R-0

RXFUL

RXM1

RTRRO

FILHIT4

FILHIT3

FILHIT2

FILHIT1

FILHIT0

bit 7

bit 0

bit 7

RXFUL: Receive Full Status bit⁽¹⁾

1= Receive buffer contains a received message

0= Receive buffer is open to receive a new message

Note:

This bit is set by the CAN module upon receiving a message and must be cleared

by software after the buffer is read. As long as RXFUL is set, no new message will

be loaded and buffer will be considered full.

bit 6

RXM1: Receive Buffer Mode bit

1= Receive all messages including partial and invalid (acceptance filters are ignored)

0= Receive all valid messages as per acceptance filters

bit 5

RTRRO: Read-Only Remote Transmission Request bit for Received Message

1= Received message is a remote transmission request

0= Received message is not a remote transmission request

bit 4-0

FILHIT4:FILHIT0: Filter Hit bits

These bits indicate which acceptance filter enabled the last message reception into this buffer.

01111= Acceptance Filter 15 (RXF15)

01110= Acceptance Filter 14 (RXF14)

...

00001= Acceptance Filter 1 (RXF1)

00000= Acceptance Filter 0 (RXF0)

Note 1: These registers are available in Mode 1 and 2 only.

Legend:

C = Clearable bit R = Readable bit W = Writable bit

‘1’ = Bit is set ‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

- n = Value at POR

x = Bit is unknown

 2004 Microchip Technology Inc.

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REGISTER 23-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE

[0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1]⁽¹⁾

R/W-0

R-0

R/W-0

TXBIF

TXABT

TXLARB

TXERR

TXREQ

RTREN

TXPRI1

TXPRI0

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

TXBIF: Transmit Buffer Interrupt Flag bit⁽¹⁾

1= A message is successfully transmitted

0= No message was transmitted

TXABT: Transmission Aborted Status bit⁽¹⁾

1= Message was aborted

0= Message was not aborted

TXLARB: Transmission Lost Arbitration Status bit⁽²⁾

1= Message lost arbitration while being sent

0= Message did not lose arbitration while being sent

TXERR: Transmission Error Detected Status bit⁽²⁾

1= A bus error occurred while the message was being sent

0= A bus error did not occur while the message was being sent

TXREQ: Transmit Request Status bit⁽³⁾

1= Requests sending a message; clears the TXABT, TXLARB, and TXERR bits

0= Automatically cleared when the message is successfully sent

Note:

Clearing this bit in software while the bit is set will request a message abort.

bit 2

RTREN: Automatic Remote Transmission Request Enable bit

1= When a remote transmission request is received, TXREQ will be automatically set

0= When a remote transmission request is received, TXREQ will be unaffected

bit 1-0

TXPRI1:TXPRI0: Transmit Priority bits⁽⁴⁾

11= Priority Level 3 (highest priority)

10= Priority Level 2

01= Priority Level 1

00= Priority Level 0 (lowest priority)

Note 1: These registers are available in Mode 1 and 2 only.

2: This bit is automatically cleared when TXREQ is set.

3: While TXREQ is set or transmission is in progress, transmit buffer registers remain

read-only.

4: These bits set the order in which the transmit buffer will be transferred. They do not

alter the CAN message identifier.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

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REGISTER 23-24: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS,

HIGH BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0]⁽¹⁾

R-x

SID10

SID9

SID8

SID7

SID6

SID5

SID4

SID3

bit 7

bit 0

bit 7-0

SID10:SID3: Standard Identifier bits, if EXIDE (BnSIDL<3>) = 0;

Extended Identifier bits EID28:EID21, if EXIDE = 1.

Note 1: These registers are available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-25: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS,

HIGH BYTE IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1]⁽¹⁾

R/W-x

SID3

SID10

SID9

SID8

SID7

SID6

SID5

SID4

bit 7

bit 0

bit 7-0

SID10:SID3: Standard Identifier bits, if EXIDE (BnSIDL<3>) = 0;

Extended Identifier bits EID28:EID21, if EXIDE = 1.

Note 1: These registers are available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

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REGISTER 23-26: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS,

LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0]⁽¹⁾

R-x

U-0

R-x

SID2

SID1

SID0

SRR

EXID

—

EID17

EID16

bit 7

bit 0

bit 7-5

bit 4

SID2:SID0: Standard Identifier bits, if EXID = 0;

Extended Identifier bits EID20:EID18, if EXID = 1.

SRR: Substitute Remote Transmission Request bit (only when EXID = 1)

1= Remote transmission request occurred

0= No remote transmission request occurred

bit 3

EXID: Extended Identifier Enable bit

1= Received message is an extended identifier frame, SID10:SID0 are EID28:EID18

0= Received message is a standard identifier frame

bit 2

Unimplemented: Read as ‘0’

bit 1-0

EID17:EID16: Extended Identifier bits

Note 1: These registers are available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-27: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS,

LOW BYTE IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1]⁽¹⁾

R/W-x

U-0

R/W-x

U-0

R/W-x

EID16

SID2

SID1

SID0

—

EXIDE

—

EID17

bit 7

SID2:SID0: Standard Identifier bits, if EXIDE = 0;

bit 0

bit 7-5

Extended Identifier bits EID20:EID18, if EXIDE = 1.

Unimplemented: Read as ‘0’

bit 4

bit 3

EXIDE: Extended Identifier Enable bit

1= Received message is an extended identifier frame, SID10:SID0 are EID28:EID18

0= Received message is a standard identifier frame

bit 2

Unimplemented: Read as ‘0’

bit 1-0

EID17:EID16: Extended Identifier bits

Note 1: These registers are available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

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REGISTER 23-28: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS,

HIGH BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0]⁽¹⁾

R-x

EID15

EID14

EID13

EID12

EID11

EID10

EID9

EID8

bit 7

bit 0

bit 7-0

EID15:EID8: Extended Identifier bits

Note 1: These registers are available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-29: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS,

HIGH BYTE IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1]⁽¹⁾

R/W-x

EID8

EID15

EID14

EID13

EID12

EID11

EID10

EID9

bit 7

EID15:EID8: Extended Identifier bits

bit 0

bit 7-0

Note 1: These registers are available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

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REGISTER 23-30: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS,

LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 0]⁽¹⁾

R-x

EID7

EID6

EID5

EID4

EID3

EID2

EID1

EID0

bit 7

bit 0

bit 7-0

EID7:EID0: Extended Identifier bits

Note 1: These registers are available in Mode 1 and 2 only.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

REGISTER 23-31: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS,

LOW BYTE IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 1]⁽¹⁾

R/W-x

EID0

EID7

EID6

EID5

EID4

EID3

EID2

EID1

bit 7

bit 0

bit 7-0

EID7:EID0: Extended Identifier bits

Note 1: These registers are available in Mode 1 and 2 only.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

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REGISTER 23-32: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN RECEIVE MODE

[0 ≤ n ≤ 5, 0 ≤ m ≤ 7, TXnEN (BSEL<n>) = 0]⁽¹⁾

R-x

BnDm7

BnDm6

BnDm5

BnDm4

BnDm3

BnDm2

BnDm1

BnDm0

bit 7

bit 0

bit 7-0

BnDm7:BnDm0: Receive Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 < m < 8)

Each receive buffer has an array of registers. For example, Receive Buffer 0 has 7 registers:

B0D0 to B0D7.

Note 1: These registers are available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-33: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN TRANSMIT MODE

[0 ≤ n ≤ 5, 0 ≤ m ≤ 7, TXnEN (BSEL<n>) = 1]⁽¹⁾

R/W-x

BnDm7

BnDm6

BnDm5

BnDm4

BnDm3

BnDm2

BnDm1

BnDm0

bit 7

bit 0

bit 7-0

BnDm7:BnDm0: Transmit Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 < m < 8)

Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers:

TXB0D0 to TXB0D7.

Note 1: These registers are available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

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REGISTER 23-34: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN RECEIVE MODE

[0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 0]⁽¹⁾

U-0

R-x

—

RXRTR

RB1

RB0

DLC3

DLC2

DLC1

DLC0

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ‘0’

RXRTR: Receiver Remote Transmission Request bit

1= This is a remote transmission request

0= This is not a remote transmission request

bit 5

RB1: Reserved bit 1

Reserved by CAN Spec and read as ‘0’.

RB0: Reserved bit 0

bit 4

Reserved by CAN Spec and read as ‘0’.

DLC3:DLC0: Data Length Code bits

bit 3-0

1111= Reserved

1110= Reserved

1101= Reserved

1100= Reserved

1011= Reserved

1010= Reserved

1001= Reserved

1000= Data length = 8 bytes

0111= Data length = 7 bytes

0110= Data length = 6 bytes

0101= Data length = 5 bytes

0100= Data length = 4 bytes

0011= Data length = 3 bytes

0010= Data length = 2 bytes

0001= Data length = 1 bytes

0000= Data length = 0 bytes

Note 1: These registers are available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

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REGISTER 23-35: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN TRANSMIT MODE

[0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 1]⁽¹⁾

U-0

R/W-x

U-0

R/W-x

DLC3

R/W-x

DLC2

R/W-x

DLC1

R/W-x

DLC0

—

TXRTR

—

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ‘0’

TXRTR: Transmitter Remote Transmission Request bit

1= Transmitted message will have RTR bit set

0= Transmitted message will have RTR bit cleared

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

DLC3:DLC0: Data Length Code bits

1111-1001= Reserved

1000= Data length = 8 bytes

0111= Data length = 7 bytes

0110= Data length = 6 bytes

0101= Data length = 5 bytes

0100= Data length = 4 bytes

0011= Data length = 3 bytes

0010= Data length = 2 bytes

0001= Data length = 1 bytes

0000= Data length = 0 bytes

Note 1: These registers are available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-36: BSEL0: BUFFER SELECT REGISTER 0⁽¹⁾

R/W-0

U-0

—

U-0

—

B5TXEN

B4TXEN

B3TXEN B2TXEN B1TXEN B0TXEN

bit 7

bit 0

bit 7-2

bit 1-0

B5TXEN:B0TXEN: Buffer 5 to Buffer 0 Transmit Enable bit

1= Buffer is configured in Transmit mode

0= Buffer is configured in Receive mode

Unimplemented: Read as ‘0’

Note 1: This register is available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

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23.2.3.2

Message Acceptance Filters

and Masks

This subsection describes the message acceptance

filters and masks for the CAN receive buffers.

Note:

These

registers

are

writable

in

Configuration mode only.

REGISTER 23-37: RXFnSIDH: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER

REGISTERS, HIGH BYTE [0 ≤ n ≤ 15]⁽¹⁾

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

SID10

SID9

SID8

SID7

bit 7

bit 0

bit 7-0

SID10:SID3: Standard Identifier Filter bits, if EXIDEN = 0;

Extended Identifier Filter bits EID28:EID21, if EXIDEN = 1.

Note 1: Registers RXF6SIDH:RXF15SIDH are available in Mode 1 and 2 only.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

REGISTER 23-38: RXFnSIDL: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER

REGISTERS, LOW BYTE [0 ≤ n ≤ 15]⁽¹⁾

R/W-x

U-0

R/W-x

U-0

—

R/W-x

EID17

R/W-x

EID16

SID2

SID1

SID0

—

EXIDEN

bit 7

bit 0

bit 7-5

SID2:SID0: Standard Identifier Filter bits, if EXIDEN = 0;

Extended Identifier Filter bits EID20:EID18, if EXIDEN = 1.

Unimplemented: Read as ‘0’

bit 4

bit 3

EXIDEN: Extended Identifier Filter Enable bit

1= Filter will only accept extended ID messages

0= Filter will only accept standard ID messages

Note:

In Mode 0, this bit must be set/cleared as required, irrespective of corresponding

mask register value.

bit 2

Unimplemented: Read as ‘0’

bit 1-0

EID17:EID16: Extended Identifier Filter bits

Note 1: Registers RXF6SIDL:RXF15SIDL are available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

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REGISTER 23-39: RXFnEIDH: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER

REGISTERS, HIGH BYTE [0 ≤ n ≤ 15]⁽¹⁾

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

EID15

EID14

EID13

EID12

bit 7

bit 0

bit 7-0

EID15:EID8: Extended Identifier Filter bits

Note 1: Registers RXF6EIDH:RXF15EIDH are available in Mode 1 and 2 only.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

REGISTER 23-40: RXFnEIDL: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER

REGISTERS, LOW BYTE [0 ≤ n ≤ 15]⁽¹⁾

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

EID7

EID6

EID5

EID4

bit 7

bit 0

bit 7-0

EID7:EID0: Extended Identifier Filter bits

Note 1: Registers RXF6EIDL:RXF15EIDL are available in Mode 1 and 2 only.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

REGISTER 23-41: RXMnSIDH: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK

REGISTERS, HIGH BYTE [0 ≤ n ≤ 1]

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

SID10

SID9

SID8

SID7

bit 7

bit 0

bit 7-0

SID10:SID3: Standard Identifier Mask bits, or Extended Identifier Mask bits EID28:EID21

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 307

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REGISTER 23-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK

REGISTERS, LOW BYTE [0 ≤ n ≤ 1]

R/W-x

U-0

R/W-0

EXIDEN⁽¹⁾

U-0

—

R/W-x

EID17

R/W-x

EID16

SID2

SID1

SID0

—

bit 7

bit 0

bit 7-5

bit 4

SID2:SID0: Standard Identifier Mask bits, or Extended Identifier Mask bits EID20:EID18

Unimplemented: Read as ‘0’

Mode 0:

bit 3

Unimplemented: Read as ‘0’

Mode 1, 2:

EXIDEN: Extended Identifier Filter Enable Mask bit⁽¹⁾

1= Messages selected by EXIDEN bit in RXFnSIDL will be accepted

0= Both standard and extended identifier messages will be accepted

Note 1: This bit is available in Mode 1 and 2 only.

bit 2

Unimplemented: Read as ‘0’

bit 1-0

EID17:EID16: Extended Identifier Mask bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-43: RXMnEIDH: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK

REGISTERS, HIGH BYTE [0 ≤ n ≤ 1]

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

EID15

EID14

EID13

EID12

bit 7

bit 0

bit 7-0

EID15:EID8: Extended Identifier Mask bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-44: RXMnEIDL: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK

REGISTERS, LOW BYTE [0 ≤ n ≤ 1]

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

EID7

EID6

EID5

EID4

bit 7

bit 0

bit 7-0

EID7:EID0: Extended Identifier Mask bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

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REGISTER 23-45: SDFLC: STANDARD DATA BYTES FILTER LENGTH COUNT REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-0

FLC4

R/W-0

FLC3

R/W-0

FLC2

R/W-0

FLC1

R/W-0

FLC0

bit 7

bit 0

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

FLC4:FLC0: Filter Length Count bits

Mode 0:

Not used; forced to ‘00000’.

Mode 1, 2:

00000-10010 = 0

18 bits are available for standard data byte filter. Actual number of bits

used depends on DLC3:DLC0 bits (RXBnDLC<3:0> or BnDLC<3:0> if

configured as RX buffer) of message being received.

If DLC3:DLC0 = 0000No bits will be compared with incoming data bits

If DLC3:DLC0 = 0001Up to 8 data bits of RXFnEID<7:0>, as determined by FLC2:FLC0, will

be compared with the corresponding number of data bits of the

incoming message

If DLC3:DLC0 = 0010Up to 16 data bits of RXFnEID<15:0>, as determined by FLC3:FLC0,

will be compared with the corresponding number of data bits of the

incoming message

If DLC3:DLC0 = 0011Up to 18 data bits of RXFnEID<17:0>, as determined by FLC4:FLC0,

will be compared with the corresponding number of data bits of the

incoming message

Note 1: This register is available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 23-46: RXFCONn: RECEIVE FILTER CONTROL REGISTER n [0 ≤ n ≤ 1]⁽¹⁾

R/W-0

R/W-1

RXFCON0

RXF7EN

RXF6EN

RXF5EN RXF4EN RXF3EN RXF2EN RXF1EN RXF0EN

R/W-0

R/W-1

R/W-0

RXFCON1

RXF15EN RXF14EN RXF13EN RXF12EN RXF11EN RXF10EN RXF9EN RXF8EN

bit 7

bit 0

bit 7-0

RXFnEN: Receive Filter n Enable bit

0= Filter is disabled

1= Filter is enabled

Note 1: This register is available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 309

PIC18F6585/8585/6680/8680

REGISTER 23-47: RXFBCONn: RECEIVE FILTER BUFFER CONTROL REGISTER n⁽¹⁾

R/W-0

RXFBCON0

RXFBCON1

RXFBCON2

RXFBCON3

RXFBCON4

RXFBCON5

RXFBCON6

RXFBCON7

F1BP_3

F1BP_2

F1BP_1 F1BP_0 F0BP_3 F0BP_2 F0BP_1 F0BP_0

R/W-0

R/W-1

R/W-0

R/W-1

F3BP_3

F3BP_2

F3BP_1 F3BP_0 F2BP_3 F2BP_2 F2BP_1 F2BP_0

R/W-0

R/W-1

R/W-0

R/W-1

F5BP_3

F5BP_2

F5BP_1 F5BP_0 F4BP_3 F4BP_2 F4BP_1 F4BP_0

R/W-0

F7BP_3

F7BP_2

F7BP_1 F7BP_0 F6BP_3 F6BP_2 F6BP_1 F6BP_0

R/W-0

F9BP_3

F9BP_2

F9BP_1 F9BP_0 F8BP_3 F8BP_2 F8BP_1 F8BP_0

R/W-0

F11BP_3

F11BP_2 F11BP_1 F11BP_0 F10BP_3 F10BP_2 F10BP_1 F10BP_0

R/W-0

F13BP_3

F13BP_2 F13BP_1 F13BP_0 F12BP_3 F12BP_2 F12BP_1 F12BP_0

R/W-0

F15BP_3

F15BP_2 F15BP_1 F15BP_0 F14BP_3 F14BP_2 F14BP_1 F14BP_0

bit 0

bit 7

bit 7-0

FnBP_3:FnBP_0: Filter n Buffer Pointer Nibble bits

0000= Filter n is associated with RXB0

0001= Filter n is associated with RXB1

0010= Filter n is associated with B0

0011= Filter n is associated with B1

.

0111= Filter n is associated with B5

1111:1000= Reserved

Note 1: This register is available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

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REGISTER 23-48: MSEL0: MASK SELECT REGISTER 0⁽¹⁾

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

FIL3_1

FIL3_0

FIL2_1

FIL2_0

FIL1_1

FIL1_0

FIL0_1

FIL0_0

bit 7

bit 0

bit 7-6

bit 5-4

bit 3-2

bit 1-0

FIL3_1:FIL3_0: Filter 3 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

FIL2_1:FIL2_0: Filter 2 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

FIL1_1:FIL1_0: Filter 1 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

FIL0_1:FIL0_0: Filter 0 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

Note 1: This register is available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

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REGISTER 23-49: MSEL1: MASK SELECT REGISTER 1⁽¹⁾

R/W-0

R/W-1

R/W-0

R/W-1

FIL7_1

FIL7_0

FIL6_1

FIL6_0

FIL5_1

FIL5_0

FIL4_1

FIL4_0

bit 7

bit 0

bit 7-6

bit 5-4

bit 3-2

bit 1-0

FIL7_1:FIL7_0: Filter 7 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

FIL6_1:FIL6_0: Filter 6 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

FIL5_1:FIL5_0: Filter 5 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

FIL4_1:FIL4_0: Filter 4 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

Note 1: This register is available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

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REGISTER 23-50: MSEL2: MASK SELECT REGISTER 2⁽¹⁾

R/W-0

FIL11_1

FIL11_0

FIL10_1 FIL10_0

FIL9_1

FIL9_0

FIL8_1

FIL8_0

bit 7

bit 0

bit 7-6

bit 5-4

bit 3-2

bit 1-0

FIL11_1:FIL11_0: Filter 11 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

FIL10_1:FIL10_0: Filter 10 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

FIL9_1:FIL9_0: Filter 9 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

FIL8_1:FIL8_0: Filter 8 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

Note 1: This register is available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

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REGISTER 23-51: MSEL3: MASK SELECT REGISTER 3⁽¹⁾

R/W-0

FIL14_1 FIL14_0 FIL13_1 FIL13_0 FIL12_1 FIL12_0

bit 0

R/W-0

FIL15_1

FIL15_0

bit 7

bit 7-6

bit 5-4

bit 3-2

bit 1-0

FIL15_1:FIL15_0: Filter 15 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

FIL14_1:FIL14_0: Filter 14 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

FIL13_1:FIL13_0: Filter 13 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

FIL12_1:FIL12_0: Filter 12 Select bits 1 and 0

11= No mask

10= Filter 15

01= Acceptance Mask 1

00= Acceptance Mask 0

Note 1: This register is available in Mode 1 and 2 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 314

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PIC18F6585/8585/6680/8680

23.2.4

CAN BAUD RATE REGISTERS

This subsection describes the CAN Baud Rate

registers.

Note:

These

registers

are

writable

in

Configuration mode only.

REGISTER 23-52: BRGCON1: BAUD RATE CONTROL REGISTER 1

R/W-0

SJW1

R/W-0

SJW0

R/W-0

BRP5

R/W-0

BRP4

R/W-0

BRP3

R/W-0

BRP2

R/W-0

BRP1

R/W-0

BRP0

bit 7

bit 0

bit 7-6

bit 5-0

SJW1:SJW0: Synchronized Jump Width bits

11= Synchronization jump width time = 4 x TQ

10= Synchronization jump width time = 3 x TQ

01= Synchronization jump width time = 2 x TQ

00= Synchronization jump width time = 1 x TQ

BRP5:BRP0: Baud Rate Prescaler bits

111111= TQ = (2 x 64)/FOSC

111110= TQ = (2 x 63)/FOSC

.

000001= TQ = (2 x 2)/FOSC

000000= TQ = (2 x 1)/FOSC

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 315

PIC18F6585/8585/6680/8680

REGISTER 23-53: BRGCON2: BAUD RATE CONTROL REGISTER 2

R/W-0

SEG2PHTS

bit 7

R/W-0

SAM

R/W-0

SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0

bit 0

bit 7

SEG2PHTS: Phase Segment 2 Time Select bit

1= Freely programmable

0= Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater

bit 6

SAM: Sample of the CAN bus Line bit

1= Bus line is sampled three times prior to the sample point

0= Bus line is sampled once at the sample point

bit 5-3

SEG1PH2:SEG1PH0: Phase Segment 1 bits

111= Phase Segment 1 time = 8 x TQ

110= Phase Segment 1 time = 7 x TQ

101= Phase Segment 1 time = 6 x TQ

100= Phase Segment 1 time = 5 x TQ

011= Phase Segment 1 time = 4 x TQ

010= Phase Segment 1 time = 3 x TQ

001= Phase Segment 1 time = 2 x TQ

000= Phase Segment 1 time = 1 x TQ

bit 2-0

PRSEG2:PRSEG0: Propagation Time Select bits

111= Propagation time = 8 x TQ

110= Propagation time = 7 x TQ

101= Propagation time = 6 x TQ

100= Propagation time = 5 x TQ

011= Propagation time = 4 x TQ

010= Propagation time = 3 x TQ

001= Propagation time = 2 x TQ

000= Propagation time = 1 x TQ

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 316

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 23-54: BRGCON3: BAUD RATE CONTROL REGISTER 3

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

WAKDIS WAKFIL

bit 7

SEG2PH2⁽¹⁾SEG2PH1⁽¹⁾SEG2PH0⁽¹⁾

bit 0

bit 7

bit 6

WAKDIS: Wake-up Disable bit

1= Disable CAN bus activity wake-up feature

0= Enable CAN bus activity wake-up feature

WAKFIL: Selects CAN bus Line Filter for Wake-up bit

1= Use CAN bus line filter for wake-up

0= CAN bus line filter is not used for wake-up

bit 5-3

bit 2-0

Unimplemented: Read as ‘0’

SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits⁽¹⁾

111= Phase Segment 2 time = 8 x TQ

110= Phase Segment 2 time = 7 x TQ

101= Phase Segment 2 time = 6 x TQ

100= Phase Segment 2 time = 5 x TQ

011= Phase Segment 2 time = 4 x TQ

010= Phase Segment 2 time = 3 x TQ

001= Phase Segment 2 time = 2 x TQ

000= Phase Segment 2 time = 1 x TQ

Note 1: Ignored if SEG2PHTS bit (BRGCON2<7>) is ‘0’.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 317

PIC18F6585/8585/6680/8680

23.2.5

CAN MODULE I/O CONTROL

REGISTER

This register controls the operation of the CAN module’s

I/O pins in relation to the rest of the microcontroller.

REGISTER 23-55: CIOCON: CAN I/O CONTROL REGISTER

R/W-0

TX2SRC

bit 7

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

TX2EN

ENDRHI CANCAP

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3-0

TX2SRC: CANTX2 Pin Data Source bit

1= CANTX2 pin will output the CAN clock

0= CANTX2 pin will output CANTX1

TX2EN: CANTX2 Pin Enable bit

1= CANTX2 pin will output CANTX1 or CAN clock as selected by TX2SRC bit

0= CANTX2 pin will have digital I/O function

ENDRHI: Enable Drive High bit⁽¹⁾

1= CANTX pin will drive VDD when recessive

0= CANTX pin will be tri-state when recessive

CANCAP: CAN Message Receive Capture Enable bit

1= Enable CAN capture, CAN message receive signal replaces input on RC2/CCP1

0= Disable CAN capture, RC2/CCP1 input to CCP1 module

Unimplemented: Read as ‘0’

Note 1: Always set this bit when using differential bus to avoid signal crosstalk in CANTX

from other nearby pins.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS30491C-page 318

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

23.2.6

CAN INTERRUPT REGISTERS

The registers in this section are the same as described

in Section 9.0 “Interrupts”. They are duplicated here

for convenience.

REGISTER 23-56: PIR3: PERIPHERAL INTERRUPT FLAG REGISTER

R/W-0

IRXIF

R/W-0

ERRIF

R/W-0

WAKIF

TXB2IF/ TXB1IF⁽¹⁾TXB0IF⁽¹⁾RXB1IF/

RXB0IF/

TXBnIF

RXBnIF FIFOWMIF

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

IRXIF: CAN Invalid Received Message Interrupt Flag bit

1= An invalid message has occurred on the CAN bus

0= No invalid message on CAN bus

WAKIF: CAN bus Activity Wake-up Interrupt Flag bit

1= Activity on CAN bus has occurred

0= No activity on CAN bus

ERRIF: CAN bus Error Interrupt Flag bit

1= An error has occurred in the CAN module (multiple sources)

0= No CAN module errors

When CAN is in Mode 0:

TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit

1= Transmit Buffer 2 has completed transmission of a message and may be reloaded

0= Transmit Buffer 2 has not completed transmission of a message

When CAN is in Mode 1 or 2:

TXBnIF: Any Transmit Buffer Interrupt Flag bit

1= One or more transmit buffers has completed transmission of a message and may be reloaded

0= No transmit buffer is ready for reload

bit 3

bit 2

bit 1

TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit⁽¹⁾

1= Transmit Buffer 1 has completed transmission of a message and may be reloaded

0= Transmit Buffer 1 has not completed transmission of a message

TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit⁽¹⁾

1= Transmit Buffer 0 has completed transmission of a message and may be reloaded

0= Transmit Buffer 0 has not completed transmission of a message

When CAN is in Mode 0:

RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit

1= Receive Buffer 1 has received a new message

0= Receive Buffer 1 has not received a new message

When CAN is in Mode 1 or 2:

RXBnIF: Any Receive Buffer Interrupt Flag bit

1= One or more receive buffers has received a new message

0= No receive buffer has received a new message

bit 0

When CAN is in Mode 0:

RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit

1= Receive Buffer 0 has received a new message

0= Receive Buffer 0 has not received a new message

When CAN is in Mode 1:

Unimplemented: Read as ‘0’

When CAN is in Mode 2:

FIFOWMIF: FIFO Watermark Interrupt Flag bit

1= FIFO high watermark is reached

0= FIFO high watermark is not reached

Note 1: In CAN Mode 1 and 2, this bit is forced to ‘0’.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

DS30491C-page 319

PIC18F6585/8585/6680/8680

REGISTER 23-57: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER

R/W-0

IRXIE

R/W-0

ERRIE

R/W-0

WAKIE

TXB2IE/ TXB1IE⁽¹⁾TXB0IE⁽¹⁾RXB1IE/

RXB0IE/

TXBnIE

RXBnIE FIFOWMIE

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

IRXIE: CAN Invalid Received Message Interrupt Enable bit

1= Enable invalid message received interrupt

0= Disable invalid message received interrupt

WAKIE: CAN bus Activity Wake-up Interrupt Enable bit

1= Enable bus activity wake-up interrupt

0= Disable bus activity wake-up interrupt

ERRIE: CAN bus Error Interrupt Enable bit

1= Enable CAN bus error interrupt

0= Disable CAN bus error interrupt

When CAN is in Mode 0:

TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit

1= Enable Transmit Buffer 2 interrupt

0= Disable Transmit Buffer 2 interrupt

When CAN is in Mode 1 or 2:

TXBnIE: CAN Transmit Buffer Interrupts Enable bit

1= Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0

0= Disable all transmit buffer interrupts

bit 3

bit 2

bit 1

TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit⁽¹⁾

1= Enable Transmit Buffer 1 interrupt

0= Disable Transmit Buffer 1 interrupt

TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit⁽¹⁾

1= Enable Transmit Buffer 0 interrupt

0= Disable Transmit Buffer 0 interrupt

When CAN is in Mode 0:

RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit

1= Enable Receive Buffer 1 interrupt

0= Disable Receive Buffer 1 interrupt

When CAN is in Mode 1 or 2:

RXBnIE: CAN Receive Buffer Interrupts Enable bit

1= Enable receive buffer interrupt; individual interrupt is enabled by BIE0

0= Disable all receive buffer interrupts

bit 0

When CAN is in Mode 0:

RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit

1= Enable Receive Buffer 0 interrupt

0= Disable Receive Buffer 0 interrupt

When CAN is in Mode 1:

Unimplemented: Read as ‘0’

When CAN is in Mode 2:

FIFOWMIE: FIFO Watermark Interrupt Enable bit

1= Enable FIFO watermark interrupt

0= Disable FIFO watermark interrupt

Note 1: In CAN Mode 1 and 2, this bit is forced to ‘0’.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 320

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 23-58: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER

R/W-1

IRXIP

R/W-1

ERRIP

R/W-1

WAKIP

TXB2IP/ TXB1IP⁽¹⁾TXB0IP⁽¹⁾RXB1IP/

RXB0IP/

TXBnIP

RXBnIP FIFOWMIP

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

IRXIP: CAN Invalid Received Message Interrupt Priority bit

1= High priority

0= Low priority

WAKIP: CAN bus Activity Wake-up Interrupt Priority bit

1= High priority

0= Low priority

ERRIP: CAN bus Error Interrupt Priority bit

1= High priority

0= Low priority

When CAN is in Mode 0:

TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit

1= High priority

0= Low priority

When CAN is in Mode 1 or 2:

TXBnIP: CAN Transmit Buffer Interrupt Priority bit

1= High priority

0= Low priority

bit 3

bit 2

bit 1

TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit⁽¹⁾

1= High priority

0= Low priority

TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit⁽¹⁾

1= High priority

0= Low priority

When CAN is in Mode 0:

RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit

1= High priority

0= Low priority

When CAN is in Mode 1 or 2:

RXBnIP: CAN Receive Buffer Interrupts Priority bit

1= High priority

0= Low priority

bit 0

When CAN is in Mode 0:

RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit

1= High priority

0= Low priority

When CAN is in Mode 1:

Unimplemented: Read as ‘0’

When CAN is in Mode 2:

FIFOWMIP: FIFO Watermark Interrupt Priority bit

1= High priority

0= Low priority

Note 1: In CAN Mode 1 and 2, this bit is forced to ‘0’.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

 2004 Microchip Technology Inc.

DS30491C-page 321

PIC18F6585/8585/6680/8680

REGISTER 23-59: TXBIE: TRANSMIT BUFFERS INTERRUPT ENABLE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

TXB2IE

TXB1IE

TXB0IE

bit 7

bit 0

bit 7-5

bit 4-2

Unimplemented: Read as ‘0’

TX2BIE:TXB0IE: Transmit Buffer 2-0 Interrupt Enable bit⁽²⁾

1= Transmit buffer interrupt is enabled

0= Transmit buffer interrupt is disabled

bit 1-0

Unimplemented: Read as ‘0’

Note 1: This register is available in Mode 1 and 2 only.

2: TXBIE in PIE3 register must be set to get an interrupt.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

REGISTER 23-60: BIE0: BUFFER INTERRUPT ENABLE REGISTER 0⁽¹⁾

R/W-0

B5IE

R/W-0

B4IE

R/W-0

B3IE

R/W-0

B2IE

R/W-0

B1IE

R/W-0

B0IE

R/W-0

RXB1IE

RXB0IE

bit 7

bit 0

bit 7-2

bit 1-0

B5IE:B0IE: Programmable Transmit/Receive Buffer 5-0 Interrupt Enable bit⁽²⁾

1= Interrupt is enabled

0= Interrupt is disabled

RXB1IE:RXB0IE: Dedicated Receive Buffer 1-0 Interrupt Enable bit⁽²⁾

1= Interrupt is enabled

0= Interrupt is disabled

Note 1: This register is available in Mode 1 and 2 only.

2: Either TXBIE or RXBIE in PIE3 register must be set to get an interrupt.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS30491C-page 322

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 23-1: CAN CONTROLLER REGISTER MAP

Address⁽¹⁾

F7Fh

F7Eh

F7Dh

F7Ch

F7Bh

F7Ah

F79h

F78h

F77h

F76h

F75h

F74h

F73h

F72h

F71h

F70h

F6Fh

Name

Address

Name

Address

Name

Address

Name

SPBRGH⁽³⁾

BAUDCON⁽³⁾

F5Fh CANCON_RO0

F5Eh CANSTAT_RO0

F3Fh CANCON_RO2

F3Eh CANSTAT_RO2

F1Fh RXM1EIDL

F1Eh RXM1EIDH

F1Dh RXM1SIDL

F1Ch RXM1SIDH

F1Bh RXM0EIDL

F1Ah RXM0EIDH

F19h RXM0SIDL

F18h RXM0SIDH

F17h RXF5EIDL

F16h RXF5EIDH

F15h RXF5SIDL

F14h RXF5SIDH

F13h RXF4EIDL

F12h RXF4EIDH

F11h RXF4SIDL

F10h RXF4SIDH

F0Fh RXF3EIDL

(4)

—

F5Dh

F5Ch

F5Bh

F5Ah

F59h

F58h

F57h

F56h

F55h

F54h

F53h

F52h

F51h

F50h

F4Fh

RXB1D7

RXB1D6

F3Dh

F3Ch

F3Bh

F3Ah

F39h

F38h

F37h

F36h

F35h

F34h

F33h

F32h

F31h

F30h

F2Fh

TXB1D7

TXB1D6

(4)

—

(4)

—

RXB1D5

TXB1D5

(4)

—

RXB1D4

TXB1D4

ECCP1DEL⁽³⁾

RXB1D3

TXB1D3

(4)

—

RXB1D2

TXB1D2

ECANCON

TXERRCNT

RXERRCNT

COMSTAT

CIOCON

RXB1D1

TXB1D1

RXB1D0

TXB1D0

RXB1DLC

RXB1EIDL

RXB1EIDH

RXB1SIDL

RXB1SIDH

RXB1CON

TXB1DLC

TXB1EIDL

TXB1EIDH

TXB1SIDL

TXB1SIDH

TXB1CON

BRGCON3

BRGCON2

BRGCON1

CANCON

CANCON_RO1⁽²⁾

CANCON_RO3⁽²⁾

CANSTAT_RO1⁽²⁾

TXB0D7

CANSTAT_RO3⁽²⁾

TXB2D7

F6Eh

CANSTAT

F4Eh

F2Eh

F0Eh RXF3EIDH

F6Dh

F6Ch

F6Bh

F6Ah

F69h

F68h

F67h

F66h

F65h

F64h

F63h

F62h

F61h

F60h

RXB0D7

RXB0D6

F4Dh

F4Ch

F4Bh

F4Ah

F49h

F48h

F47h

F46h

F45h

F44h

F43h

F42h

F41h

F40h

F2Dh

F2Ch

F2Bh

F2Ah

F29h

F28h

F27h

F26h

F25h

F24h

F23h

F22h

F21h

F20h

F0Dh RXF3SIDL

F0Ch RXF3SIDH

F0Bh RXF2EIDL

F0Ah RXF2EIDH

F09h RXF2SIDL

F08h RXF2SIDH

F07h RXF1EIDL

F06h RXF1EIDH

F05h RXF1SIDL

F04h RXF1SIDH

F03h RXF0EIDL

F02h RXF0EIDH

F01h RXF0SIDL

F00h RXF0SIDH

TXB0D6

TXB2D6

RXB0D5

TXB0D5

TXB2D5

RXB0D4

TXB0D4

TXB2D4

RXB0D3

TXB0D3

TXB2D3

RXB0D2

TXB0D2

TXB2D2

RXB0D1

TXB0D1

TXB2D1

RXB0D0

TXB0D0

TXB2D0

RXB0DLC

RXB0EIDL

RXB0EIDH

RXB0SIDL

RXB0SIDH

RXB0CON

TXB0DLC

TXB0EIDL

TXB0EIDH

TXB0SIDL

TXB0SIDH

TXB0CON

TXB2DLC

TXB2EIDL

TXB2EIDH

TXB2SIDL

TXB2SIDH

TXB2CON

Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15.

2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for

each instance of the controller register due to the Microchip header file requirement.

3: These registers are not CAN registers.

4: Unimplemented registers are read as ‘0’.

 2004 Microchip Technology Inc.

DS30491C-page 323

PIC18F6585/8585/6680/8680

TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED)

Address⁽¹⁾

EFFh

EFEh

EFDh

EFCh

EFBh

EFAh

EF9h

EF8h

EF7h

EF6h

EF5h

EF4h

EF3h

EF2h

EF1h

EF0h

EEFh

EEEh

EEDh

EECh

EEBh

EEAh

EE9h

EE8h

EE7h

EE6h

EE5h

EE4h

EE3h

EE2h

EE1h

EE0h

Name

Address

EDFh

EDEh

EDDh

EDCh

EDBh

EDAh

ED9h

ED8h

ED7h

ED6h

ED5h

ED4h

ED3h

ED2h

ED1h

ED0h

ECFh

ECEh

ECDh

ECCh

ECBh

ECAh

EC9h

EC8h

EC7h

EC6h

EC5h

EC4h

EC3h

EC2h

EC1h

EC0h

Name

Address

EBFh

EBEh

EBDh

EBCh

EBBh

EBAh

EB9h

EB8h

EB7h

EB6h

EB5h

EB4h

EB3h

EB2h

EB1h

EB0h

EAFh

EAEh

EADh

EACh

EABh

EAAh

EA9h

EA8h

EA7h

EA6h

EA5h

EA4h

EA3h

EA2h

EA1h

EA0h

Name

Address

E9Fh

E9Eh

E9Dh

E9Ch

E9Bh

E9Ah

E99h

E98h

E97h

E96h

E95h

E94h

E93h

E92h

E91h

E90h

E8Fh

E8Eh

E8Dh

E8Ch

E8Bh

E8Ah

E89h

E88h

E87h

E86h

E85h

E84h

E83h

E82h

E81h

E80h

Name

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15.

2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for

each instance of the controller register due to the Microchip header file requirement.

3: These registers are not CAN registers.

4: Unimplemented registers are read as ‘0’.

DS30491C-page 324

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED)

Address⁽¹⁾

Name Address Name Address

Name

Address

E1Fh

E1Eh

E1Dh

E1Ch

E1Bh

E1Ah

E19h

E18h

E17h

E16h

E15h

E14h

E13h

E12h

E11h

E10h

E0Fh

E0Eh

E0Dh

E0Ch

E0Bh

E0Ah

E09h

E08h

E07h

E06h

E05h

E04h

E03h

E02h

E01h

E00h

Name

E7Fh CANCON_RO4⁽²⁾

E7Eh CANSTAT_RO4⁽²⁾

E5Fh CANCON_RO6⁽²⁾

E5Eh CANSTAT_RO6⁽²⁾

E3Fh CANCON_RO8⁽²⁾

E3Eh CANSTAT_RO8⁽²⁾

—

(4)

—

(4)

E7Dh

E7Ch

E7Bh

E7Ah

E79h

E78h

E77h

E76h

E75h

E74h

E73h

E72h

E71h

E70h

B5D7

B5D6

E5Dh

E5Ch

E5Bh

E5Ah

E59h

E58h

E57h

E56h

E55h

E54h

E53h

E52h

E51h

E50h

B3D7

B3D6

E3Dh

E3Ch

E3Bh

E3Ah

E39h

E38h

E37h

E36h

E35h

E34h

E33h

E32h

E31h

E30h

B1D7

B1D6

—

(4)

—

(4)

B5D5

B3D5

B1D5

—

(4)

B5D4

B3D4

B1D4

—

(4)

B5D3

B3D3

B1D3

—

(4)

B5D2

B3D2

B1D2

—

(4)

B5D1

B3D1

B1D1

—

(4)

B5D0

B3D0

B1D0

—

(4)

B5DLC

B5EIDL

B5EIDH

B5SIDL

B5SIDH

B5CON

B3DLC

B3EIDL

B3EIDH

B3SIDL

B3SIDH

B3CON

B1DLC

B1EIDL

B1EIDH

B1SIDL

B1SIDH

B1CON

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

E6Fh CANCON_RO5

E6Eh CANSTAT_RO5

E4Fh CANCON_RO7

E4Eh CANSTAT_RO7

E2Fh CANCON_RO9

E2Eh CANSTAT_RO9

—

(4)

—

(4)

E6Dh

E6Ch

E6Bh

E6Ah

E69h

E68h

E67h

E66h

E65h

E64h

E63h

E62h

E61h

E60h

B4D7

B4D6

E4Dh

E4Ch

E4Bh

E4Ah

E49h

E48h

E47h

E46h

E45h

E44h

E43h

E42h

E41h

E40h

B2D7

B2D6

E2Dh

E2Ch

E2Bh

E2Ah

E29h

E28h

E27h

E26h

E25h

E24h

E23h

E22h

E21h

E20h

B0D7

B0D6

—

(4)

—

(4)

B4D5

B2D5

B0D5

—

(4)

B4D4

B2D4

B0D4

—

(4)

B4D3

B2D3

B0D3

—

(4)

B4D2

B2D2

B0D2

—

(4)

B4D1

B2D1

B0D1

—

(4)

B4D0

B2D0

B0D0

—

(4)

B4DLC

B4EIDL

B4EIDH

B4SIDL

B4SIDH

B4CON

B2DLC

B2EIDL

B2EIDH

B2SIDL

B2SIDH

B2CON

B0DLC

B0EIDL

B0EIDH

B0SIDL

B0SIDH

B0CON

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15.

2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for

each instance of the controller register due to the Microchip header file requirement.

3: These registers are not CAN registers.

4: Unimplemented registers are read as ‘0’.

 2004 Microchip Technology Inc.

DS30491C-page 325

PIC18F6585/8585/6680/8680

TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED)

Address⁽¹⁾

DFFh

DFEh

DFDh

DFCh

DFBh

DFAh

DF9h

DF8h

DF7h

DF6h

DF5h

DF4h

DF3h

DF2h

DF1h

DF0h

DEFh

DEEh

DEDh

DECh

DEBh

DEAh

DE9h

DE8h

DE7h

DE6h

DE5h

DE4h

DE3h

DE2h

DE1h

DE0h

Name

Address

DDFh

DDEh

DDDh

DDCh

DDBh

DDAh

DD9h

DD8h

DD7h

DD6h

DD5h

DD4h

DD3h

DD2h

DD1h

DD0h

DCFh

DCEh

DCDh

DCCh

DCBh

DCAh

DC9h

DC8h

DC7h

DC6h

DC5h

DC4h

DC3h

DC2h

DC1h

DC0h

Name

Address

DBFh

DBEh

DBDh

DBCh

DBBh

DBAh

DB9h

DB8h

DB7h

DB6h

DB5h

DB4h

DB3h

DB2h

DB1h

DB0h

DAFh

DAEh

DADh

DACh

DABh

DAAh

DA9h

DA8h

DA7h

DA6h

DA5h

DA4h

DA3h

DA2h

DA1h

DA0h

Name

Address

D9Fh

D9Eh

D9Dh

D9Ch

D9Bh

D9Ah

D99h

D98h

D97h

D96h

D95h

D94h

Name

(4)

—

(4)

—

(4)

—

(4)

TXBIE

—

(4)

—

(4)

BIE0

—

(4)

—

(4)

BSEL0

SDFLC

—

(4)

—

(4)

—

(4)

—

RXFCON1

RXFCON0

—

(4)

—

(4)

MSEL3

MSEL2

MSEL1

MSEL0

—

D93h RXF15EIDL

D92h RXF15EIDH

D91h RXF15SIDL

(4)

—

(4)

—

(4)

—

D90h RXF15SIDH

(4)

—

D8Fh

D8Eh

D8Dh

D8Ch

—

(4)

—

(4)

—

(4)

—

(4)

—

D8Bh RXF14EIDL

D8Ah RXF14EIDH

D89h RXF14SIDL

D88h RXF14SIDH

D87h RXF13EIDL

D86h RXF13EIDH

D85h RXF13SIDL

D84h RXF13SIDH

D83h RXF12EIDL

D82h RXF12EIDH

D81h RXF12SIDL

D80h RXF12SIDH

(4)

—

(4)

—

(4)

—

(4)

RXFBCON7

RXFBCON6

RXFBCON5

RXFBCON4

RXFBCON3

RXFBCON2

RXFBCON1

RXFBCON0

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

(4)

—

Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15.

2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for

each instance of the controller register due to the Microchip header file requirement.

3: These registers are not CAN registers.

4: Unimplemented registers are read as ‘0’.

DS30491C-page 326

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED)

Address⁽¹⁾

Name

(4)

D7Fh

D7Eh

D7Dh

D7Ch

D7Bh

D7Ah

D79h

D78h

D77h

D76h

D75h

D74h

D73h

D72h

D71h

D70h

D6Fh

D6Eh

D6Dh

D6Ch

D6Bh

D6Ah

D69h

D68h

D67h

D66h

D65h

D64h

D63h

D62h

D61h

D60h

—

(4)

—

(4)

—

(4)

—

RXF11EIDL

RXF11EIDH

RXF11SIDL

RXF11SIDH

RXF10EIDL

RXF10EIDH

RXF10SIDL

RXF10SIDH

RXF9EIDL

RXF9EIDH

RXF9SIDL

RXF9SIDH

(4)

—

(4)

—

(4)

—

(4)

—

RXF8EIDL

RXF8EIDH

RXF8SIDL

RXF8SIDH

RXF7EIDL

RXF7EIDH

RXF7SIDL

RXF7SIDH

RXF6EIDL

RXF6EIDH

RXF6SIDL

RXF6SIDH

Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15.

2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given

for each instance of the controller register due to the Microchip header file requirement.

3: These registers are not CAN registers.

4: Unimplemented registers are read as ‘0’.

 2004 Microchip Technology Inc.

DS30491C-page 327

PIC18F6585/8585/6680/8680

In the Configuration mode, the module will not transmit

23.3 CAN Modes of Operation

or receive. The error counters are cleared and the inter-

rupt flags remain unchanged. The programmer will

have access to configuration registers that are access

restricted in other modes.

The PIC18F6585/8585/6680/8680 has six main modes

of operation:

• Configuration mode

• Disable mode

23.3.2

DISABLE MODE

• Normal Operation mode

• Listen Only mode

• Loopback mode

In Disable mode, the module will not transmit or

receive. The module has the ability to set the WAKIF bit

due to bus activity; however, any pending interrupts will

remain and the error counters will retain their value.

• Error Recognition mode

All modes, except Error Recognition, are requested by

setting the REQOP bits (CANCON<7:5>); Error Recog-

nition is requested through the RXM bits of the Receive

Buffer register(s). Entry into a mode is Acknowledged

by monitoring the OPMODE bits.

If REQOP<2:0> is set to ‘001’, the module will enter the

Module Disable mode. This mode is similar to disabling

other peripheral modules by turning off the module

enables. This causes the module internal clock to stop

unless the module is active (i.e., receiving or transmit-

ting a message). If the module is active, the module will

wait for 11 recessive bits on the CAN bus, detect that

condition as an Idle bus, then accept the module

disable command. OPMODE<2:0> = 001 indicates

whether the module successfully went into Module

Disable mode.

When changing modes, the mode will not actually

change until all pending message transmissions are

complete. Because of this, the user must verify that the

device has actually changed into the requested mode

before further operations are executed.

23.3.1

CONFIGURATION MODE

The WAKIE interrupt is the only module interrupt that is

still active in the Module Disable mode. If wake-up from

CAN bus activity is required, the CAN module must be

put into Disable mode before putting the core to Sleep.

If the WAKDIS is cleared and WAKIE is set, the proces-

sor will receive an interrupt whenever the module

detects recessive to dominant transition. On wake-up,

the module will automatically be set to the previous

mode of operation. For example, if the module was

switched from Normal to Disable mode on bus activity

wake-up, the module will automatically enter into

Normal mode and the first message that caused the

module to wake-up is lost. The module will not gener-

ate any error frame. Firmware logic must detect this

condition and make sure that retransmission is

requested. If the processor receives a wake-up inter-

rupt while it is sleeping, more than one message may

get lost. The actual number of messages lost would

depend on the processor oscillator start-up time and

incoming message bit rate.

The CAN module must be initialized before the

activation. This is only possible if the module is in the

Configuration mode. The Configuration mode is

requested by setting the REQOP2 bit. Only when the

status bit, OPMODE2, has a high level can the initial-

ization be performed. Once in Configuration mode,

registers such as baud rate control, acceptance mask/

filter and ECAN mode selection can be modified. A new

ECAN mode selection does not take into effect until

Configuration mode is exited. The module is activated

by setting the REQOP control bits to zero.

The module will protect the user from accidentally

violating the CAN protocol through programming

errors. All registers which control the configuration of

the module can not be modified while the module is

online. The CAN module will not be allowed to enter the

Configuration mode while a transmission or reception

is taking place. The CAN module will also not be

allowed, if the CANRX pin is low (i.e., the CAN bus is

busy). The CAN module waits for 11 recessive bits on

the CAN bus (bus Idle condition) before switching to

Configuration mode. The Configuration mode serves

as a lock to protect the following registers:

The I/O pins will revert to normal I/O function when the

module is in the Module Disable mode.

Note:

CAN module must be put in Disable or

Configuration mode prior to putting the

processor to sleep. Failure to do that may

put the CAN module in indeterminate

state.

• Configuration registers

• Functional Mode Selection registers

• Bit Timing registers

• Identifier Acceptance Filter registers

• Identifier Acceptance Mask registers

• Filter and Mask Control registers

• Mask Selection registers

DS30491C-page 328

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

23.3.3

NORMAL MODE

23.3.6

ERROR RECOGNITION MODE

This is the standard operating mode of the

PIC18F6585/8585/6680/8680 devices. In this mode,

the device actively monitors all bus messages and gen-

erates Acknowledge bits, error frames, etc. This is also

the only mode in which the PIC18F6585/8585/6680/

8680 devices will transmit messages over the CAN

bus.

The module can be set to ignore all errors and receive

any message. In functional Mode 0, the Error Recogni-

tion mode is activated by setting the RXM<1:0> bits in

the RXBnCON registers to ‘11’. In this mode, the data

which is in the message assembly buffer until the error

time, is copied in the receive buffer and can be read via

the CPU interface.

23.3.4

LISTEN ONLY MODE

23.4 CAN Module Functional Modes

Listen Only mode provides

a

means for the

In addition to CAN modes of operation, the ECAN

module offers a total of three functional modes. Each of

these modes are identified as Mode 0, Mode 1 and

Mode 2.

PIC18F6585/8585/6680/8680 devices to receive all

messages, including messages with errors. This mode

can be used for bus monitor applications or for

detecting the baud rate in ‘hot plugging’ situations. For

auto-baud detection, it is necessary that there are at

least two other nodes which are communicating with

each other. The baud rate can be detected empirically

by testing different values until valid messages are

received. The Listen Only mode is a silent mode,

meaning no messages will be transmitted while in this

state, including error flags or Acknowledge signals. The

filters and masks can be used to allow only particular

messages to be loaded into the receive registers, or the

filter masks can be set to all zeros to allow a message

with any identifier to pass. The error counters are reset

and deactivated in this state. The Listen Only mode is

activated by setting the mode request bits in the

CANCON register.

23.4.1

MODE 0 – LEGACY MODE

Mode 0 is designed to be fully compatible with CAN

modules used in PIC18CXX8 and PIC18FXX8 devices.

This is the default mode of operation on all Reset

conditions. As a result, module code written for the

PIC18XX8 CAN module may be used on the ECAN

module without any code changes.

The following is the list of resources available in Mode 0:

• Three transmit buffers: TXB0, TXB1 and TXB2

• Two receive buffers: RXB0 and RXB1

• Two acceptance masks, one for each receive

buffer: RXM0, RXM1

• Six acceptance filters, 2 for RXB0 and 4 for RXB1:

RXF0, RXF1, RXF2, RXF3, RXF4, RXF5

23.3.5

LOOPBACK MODE

This mode will allow internal transmission of messages

from the transmit buffers to the receive buffers without

actually transmitting messages on the CAN bus. This

mode can be used in system development and testing.

In this mode, the ACK bit is ignored and the device will

allow incoming messages from itself, just as if they

were coming from another node. The Loopback mode

is a silent mode, meaning no messages will be trans-

mitted while in this state, including error flags or

Acknowledge signals. The CANTX pin will revert to port

I/O while the device is in this mode. The filters and

masks can be used to allow only particular messages

to be loaded into the receive registers. The masks can

be set to all zeros to provide a mode that accepts all

messages. The Loopback mode is activated by setting

the mode request bits in the CANCON register.

23.4.2

MODE 1 – ENHANCED LEGACY

MODE

Mode 1 is similar to Mode 0, with the exception that

more resources are available in Mode 1. There are

16 acceptance filters and two Acceptance Mask regis-

ters. Acceptance Filter 15 can be used as either an

acceptance filter or an Acceptance Mask register. In

addition to three transmit and two receive buffers, there

are six more message buffers. One or more of these

additional buffers can be programmed as transmit or

receive buffers. These additional buffers can also be

programmed to automatically handle RTR messages.

Fourteen of 16 Acceptance Filter registers can be

dynamically associated to any receive buffer and

Acceptance Mask register. This capability can be used

to associate more than one filter to any one buffer.

 2004 Microchip Technology Inc.

DS30491C-page 329

PIC18F6585/8585/6680/8680

When a receive buffer is programmed to use standard

23.5 CAN Message Buffers

identifier messages, part of the full Acceptance Filter

register can be used as data byte filter. The length of

data byte filter is programmable from 0 to 18 bits. This

functionality simplifies implementation of high-level

protocols, such as DeviceNet.

23.5.1 DEDICATED TRANSMIT BUFFERS

The PIC18F6585/8585/6680/8680 devices implement

three dedicated transmit buffers – TXB0, TXB1 and

TXB2. Each of these buffers occupies 14 bytes of

SRAM and are mapped into the SFR memory map.

These are the only transmit buffers available in

Mode 0. Mode 1 and 2 may access these and other

additional buffers.

The following is the list of resources available in Mode 1:

• Three transmit buffers: TXB0, TXB1 and TXB2

• Two receive buffers: RXB0 and RXB1

• Six buffers programmable as TX or RX: B0-B5

• Automatic RTR handling on B0-B5

Each transmit buffer contains one Control register

(TXBnCON), four Identifier registers (TXBnSIDL,

TXBnSIDH, TXBnEIDL, TXBnEIDH), one Data Length

Count register (TXBnDLC) and eight Data Byte

registers (TXBnDm).

• Sixteen dynamically assigned acceptance filters:

RXF0-RXF15

• Two dedicated Acceptance Mask registers;

RXF15 programmable as third mask:

RXM0-RXM1, RXF15

23.5.2

DEDICATED RECEIVE BUFFERS

• Programmable data filter on standard identifier

messages: SDFLC

The PIC18F6585/8585/6680/8680 devices implement

two dedicated receive buffers – RXB0 and RXB1. Each

of these buffers occupies 14 bytes of SRAM and are

mapped into SFR memory map. These are the only

receive buffers available in Mode 0. Mode 1 and 2 may

access these and other additional buffers.

23.4.3

MODE 2 – ENHANCED FIFO MODE

In Mode 2, two or more receive buffers are used to form

the receive FIFO (First In First Out) buffer. There is no

one-to-one relation between the receive buffer and

Acceptance Filter registers. Any filter that is enabled

and linked to any FIFO receive buffer can generate

acceptance and cause FIFO to be updated.

Each receive buffer contains one Control register

(RXBnCON), four Identifier registers (RXBnSIDL,

RXBnSIDH, RXBnEIDL, RXBnEIDH), one Data Length

Count register (RXBnDLC) and eight Data Byte

registers (RXBnDm).

FIFO length is user programmable, from 2-8 buffers

deep. FIFO length is determined by the very first

programmable buffer that is configured as a transmit

buffer. For example, if Buffer 2 (B2) is programmed as

a transmit buffer, FIFO consists of RXB0, RXB1, B0

and B1 – creating a FIFO length of 4. If all programma-

ble buffers are configured as receive buffers, FIFO will

have the maximum length of 8.

There is also a separate Message Assembly Buffer

(MAB) which acts as an additional receive buffer. MAB

is always committed to receiving the next message

from the bus and is not directly accessible to user firm-

ware. The MAB assembles all incoming messages one

by one. A message is transferred to appropriate

receive buffers only if the corresponding acceptance

filter criteria is met.

The following is the list of resources available in Mode 2:

• Three transmit buffers: TXB0, TXB1 and TXB2

• Two receive buffers: RXB0 and RXB1

• Six buffers programmable as TX or RX; receive

buffers form FIFO: B0-B5

• Automatic RTR handling on B0-B5

• Sixteen acceptance filters: RXF0-RXF15

• Two dedicated Acceptance Mask registers;

RXF15 programmable as third mask:

RXM0-RXM1, RXF15

• Programmable data filter on standard identifier

messages: SDFLC, useful for DeviceNet protocol

DS30491C-page 330

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

The following outlines the steps required to

automatically handle RTR messages:

23.5.3

PROGRAMMABLE TRANSMIT/

RECEIVE BUFFERS

1. Set buffer to Transmit mode by setting TXnEN

The ECAN module implements six new buffers: B0-B5.

These buffers are individually programmable as either

transmit or receive buffers. These buffers are available

only in Mode 1 and 2. As with dedicated transmit and

receive buffers, each of these programmable buffers

occupies 14 bytes of SRAM and are mapped into SFR

memory map.

bit to ‘1’ in BSEL0 register.

2. At least one acceptance filter must be associ-

ated with this buffer and preloaded with

expected RTR identifier.

3. Bit RTREN in BnCON register must be set to ‘1’.

4. Buffer must be preloaded with the data to be

sent as a RTR response.

Each buffer contains one Control register (BnCON),

four Identifier registers (BnSIDL, BnSIDH, BnEIDL,

BnEIDH), one Data Length Count register (BnDLC)

and eight Data Byte registers (BnDm). Each of these

registers contains two sets of control bits. Depending

on whether the buffer is configured as transmit or

receive, one would use the corresponding control bit

set. By default, all buffers are configured as receive

buffers. Each buffer can be individually configured as

transmit or receive buffers by setting the corresponding

TXENn bit in the BSEL0 register.

Normally, user firmware will keep Buffer Data registers

up to date. If firmware attempts to update buffer while

an automatic RTR response is in process of

transmission, all writes to buffers are ignored.

23.6 CAN Message Transmission

23.6.1

INITIATING TRANSMISSION

For the MCU to have write access to the message

buffer, the TXREQ bit must be clear, indicating that the

message buffer is clear of any pending message to be

transmitted. At a minimum, the SIDH, SIDL, and DLC

registers must be loaded. If data bytes are present in

the message, the data registers must also be loaded. If

the message is to use extended identifiers, the

EIDH:EIDL registers must also be loaded and the

EXIDE bit set.

When configured as transmit buffers, user firmware

may access transmit buffers in any order similar to

accessing dedicated transmit buffers. In receive config-

uration, with Mode 1 enabled, user firmware may also

access receive buffers in any order required. But in

Mode 2, all receive buffers are combined to form a sin-

gle FIFO. Actual FIFO length is programmable by user

firmware. Access to FIFO must be done through the

FIFO pointer bits (FP<4:0>) in the CANCON register. It

must be noted that there is no hardware protection

against out of order FIFO reads.

To initiate message transmission, the TXREQ bit must

be set for each buffer to be transmitted. When TXREQ

is set, the TXABT, TXLARB and TXERR bits will be

cleared. To successfully complete the transmission,

there must be at least one node with matching baud

rate on the network.

23.5.4

PROGRAMMABLE AUTO-RTR

BUFFERS

Setting the TXREQ bit does not initiate a message

transmission, it merely flags a message buffer as ready

for transmission. Transmission will start when the

device detects that the bus is available. The device will

then begin transmission of the highest priority message

that is ready.

In Mode 1 and 2, any of six programmable transmit/

receive buffers may be programmed to automatically

respond to predefined RTR messages without user

firmware intervention. Automatic RTR handling is

enabled by setting the TXnEN bit in the BSEL0 register

and the RTREN bit in the BnCON register. After this

setup, when an RTR request is received, the TXREQ

bit is automatically set and current buffer content is

automatically queued for transmission as a RTR

response. As with all transmit buffers, once the TXREQ

bit is set, buffer registers become read-only and any

writes to them will be ignored.

When the transmission has completed successfully, the

TXREQ bit will be cleared, the TXBnIF bit will be set, and

an interrupt will be generated if the TXBnIE bit is set.

If the message transmission fails, the TXREQ will

remain set, indicating that the message is still pending

for transmission and one of the following condition flags

will be set. If the message started to transmit but

encountered an error condition, the TXERR and the

IRXIF bits will be set and an interrupt will be generated.

If the message lost arbitration, the TXLARB bit will be

set.

 2004 Microchip Technology Inc.

DS30491C-page 331

PIC18F6585/8585/6680/8680

Once an abort is requested by setting ABAT or TXABT

bits, it cannot be cleared to cancel the abort request.

Only CAN module hardware or a POR condition can

clear it.

23.6.2

ABORTING TRANSMISSION

The MCU can request to abort a message by clearing

the TXREQ bit associated with the corresponding mes-

sage buffer (TXBnCON<3> or BnCON<3>). Setting the

ABAT bit (CANCON<4>) will request an abort of all

pending messages. If the message has not yet started

transmission or if the message started but is inter-

rupted by loss of arbitration or an error, the abort will be

processed. The abort is indicated when the module

sets the TXABT bit for the corresponding buffer

(TXBnCON<6> or BnCON<6>). If the message has

started to transmit, it will attempt to transmit the current

message fully. If the current message is transmitted

fully and is not lost to arbitration or an error, the TXABT

bit will not be set because the message was transmit-

ted successfully. Likewise, if a message is being

transmitted during an abort request and the message is

lost to arbitration or an error, the message will not be

retransmitted and the TXABT bit will be set, indicating

that the message was successfully aborted.

23.6.3

TRANSMIT PRIORITY

prioritization within the

Transmit priority is

a

PIC18F6585/8585/6680/8680 devices of the pending

transmittable messages. This is independent from and

not related to any prioritization implicit in the message

arbitration scheme built into the CAN protocol. Prior to

sending the SOF, the priority of all buffers that are

queued for transmission is compared. The transmit

buffer with the highest priority will be sent first. If more

than one buffer has the same priority setting, the mes-

sage is transmitted in the order of TXB2, TXB1, TXB0,

B5, B4, B3, B2, B1, B0. There are four levels of transmit

priority. If TXP bits for a particular message buffer are

set to ‘11’, that buffer has the highest possible priority.

If TXP bits for a particular message buffer are ‘00’, that

buffer has the lowest possible priority.

FIGURE 23-2:

TRANSMIT BUFFERS

TXB0

TXB1

TXB2

TXB3-TXB8

Message

Queue

Control

Transmit Byte Sequencer

DS30491C-page 332

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

Each receive buffer contains RXM bits to set special

Receive modes. In Mode 0, RXM<1:0> bits in

RXBnCON define a total of four Receive modes. In

Mode 1 and 2, RXM1 bit in combination with the EXID

23.7 Message Reception

23.7.1 RECEIVING A MESSAGE

Of all receive buffers, the MAB is always committed to

receiving the next message from the bus. The MCU

can access one buffer while the other buffer is available

for message reception, or holding a previously received

message.

mask and filter bit define the same four Receive

modes. Normally, these bits are set to ‘00’ to enable

reception of all valid messages as determined by the

appropriate acceptance filters. In this case, the deter-

mination of whether or not to receive standard or

extended messages is determined by the EXIDE bit in

the Acceptance Filter register. In Mode 0, if the RXM

bits are set to ‘01’ or ‘10’, the receiver will accept only

messages with standard or extended identifiers,

respectively. If an acceptance filter has the EXIDE bit

set such that it does not correspond with the RXM

mode, that acceptance filter is rendered useless. In

Mode 1 and 2, setting EXID in the SIDL Mask register

will ensure that only standard or extended identifiers

are received. These two modes of RXM bits can be

used in systems where it is known that only standard or

extended messages will be on the bus. If the RXM bits

are set to ‘11’ (RXM1 = 1in Mode 1 and 2), the buffer

will receive all messages regardless of the values of

the acceptance filters. Also, if a message has an error

before the end of frame, that portion of the message

assembled in the MAB before the error frame, will be

loaded into the buffer. This mode may serve as a valu-

able debugging tool for a given CAN network. It should

not be used in an actual system environment as the

actual system will always have some bus errors and all

nodes on the bus are expected to ignore them.

Note:

The entire contents of the MAB are moved

into the receive buffer once a message is

accepted. This means that regardless of

the type of identifier (standard or

extended) and the number of data bytes

received, the entire receive buffer is over-

written with the MAB contents. Therefore,

the contents of all registers in the buffer

must be assumed to have been modified

when any message is received.

When a message is moved into either of the receive

buffers, the associated RXFUL bit is set. This bit must

be cleared by the MCU when it has completed process-

ing the message in the buffer in order to allow a new

message to be received into the buffer. This bit

provides a positive lockout to ensure that the firmware

has finished with the message before the module

attempts to load a new message into the receive buffer.

If the receive interrupt is enabled, an interrupt will be

generated to indicate that a valid message has been

received.

Once a message is loaded into any matching buffer,

user firmware may determine exactly what filter caused

this reception by checking the filter hit bits in the

RXBnCON or BnCON registers. In Mode 0, FILHIT<3:0>

of RXBnCON serve as filter hit bits. In Mode 1 and 2,

FILHIT<4:0> of BnCON serve as filter hit bits. The same

registers also indicate whether the current message is

RTR frame or not. A received message is considered a

standard identifier message if the EXID bit in RXBnSIDL

or the BnSIDL register is cleared. Conversely, a set

EXID bit indicates an extended identifier message. If the

received message is a standard identifier message, user

firmware needs to read the SIDL and SIDH registers. In

the case of an extended identifier message, firmware

should read the SIDL, SIDH, EIDL and EIDH registers. If

the RXBnDLC or BnDLC register contain non-zero data

count, user firmware should also read the corresponding

number of data bytes by accessing the RXBnDm or

BnDm registers. When a received message is RTR and

if the current buffer is not configured for automatic RTR

handling, user firmware must take appropriate action

and respond manually.

In Mode 1 and 2, when a programmable buffer is

configured as a transmit buffer and one or more accep-

tance filters are associated with it, all incoming mes-

sages matching this acceptance filter criteria will be

discarded. To avoid this scenario, user firmware must

make sure that there are no acceptance filters associ-

ated with a buffer configured as a transmit buffer.

23.7.2

RECEIVE PRIORITY

When in Mode 0, RXB0 is the higher priority buffer and

has two message acceptance filters associated with it.

RXB1 is the lower priority buffer and has four acceptance

filters associated with it. The lower number of acceptance

filters makes the match on RXB0 more restrictive and

implies a higher priority for that buffer. Additionally, the

RXB0CON register can be configured such that if RXB0

contains a valid message and another valid message is

received, an overflow error will not occur and the new

message will be moved into RXB1 regardless of the

acceptance criteria of RXB1. There are also two

programmable acceptance filter masks available, one for

each receive buffer (see Section 4.5).

 2004 Microchip Technology Inc.

DS30491C-page 333

PIC18F6585/8585/6680/8680

In Mode 1 and 2, there are a total of 16 acceptance fil-

ters available and each can be dynamically assigned to

any of the receive buffers. A buffer with a lower number

has higher priority. Given this, if an incoming message

matches with two or more receive buffer acceptance

criteria, the buffer with the lower number will be loaded

with that message.

23.7.4

TIME-STAMPING

The CAN module can be programmed to generate a

time-stamp for every message that is received. When

enabled, the module generates a capture signal for

CCP1, which in turn captures the value of either Timer1

or Timer3. This value can be used as the message

time-stamp.

To use the time-stamp capability, the CANCAP bit

(CIOCAN<4>) must be set. This replaces the capture

input for CCP1 with the signal generated from the CAN

module. In addition, CCP1CON<3:0> must be set to

‘0011’ to enable the CCP special event trigger for CAN

events.

23.7.3

ENHANCED FIFO MODE

When configured for Mode 2, two of the dedicated

receive buffers, in combination with one or more pro-

grammable transmit/receive buffers, are used to create

a maximum of 8 buffers deep FIFO (First In First Out)

buffer. In this mode, there is no direct correlation

between filters and receive buffer registers. Any filter

that has been enabled can generate an acceptance.

When a message has been accepted, it is stored in the

next available receive buffer register and an internal

write pointer is incremented. The FIFO can be a maxi-

mum of 8 buffers deep. The entire FIFO must consist of

contiguous receive buffers. The FIFO head begins at

RXB0 buffer and its tail spans toward B5. The maxi-

mum length of the FIFO is limited by the presence or

absence of the first transmit buffer starting from B0. If a

buffer is configured as a transmit buffer, the FIFO

length is reduced accordingly. For instance, if B3 is

configured as transmit buffer, the actual FIFO will con-

sist of RXB0, RXB1, B0, B1 and B2, a total of 5 buffers.

If B0 is configured as a transmit buffer, the FIFO length

will be 2. If none of the programmable buffers are con-

figured as a transmit buffer, the FIFO will be 8 buffers

deep. A system that requires more transmit buffers

should try to locate transmit buffers at the very end of

B0-B5 buffers to maximize available FIFO length.

23.8 Message Acceptance Filters

and Masks

The message acceptance filters and masks are used to

determine if a message in the message assembly

buffer should be loaded into any of the receive buffers.

Once a valid message has been received into the MAB,

the identifier fields of the message are compared to the

filter values. If there is a match, that message will be

loaded into the appropriate receive buffer. The filter

masks are used to determine which bits in the identifier

are examined with the filters. A truth table is shown

below in Table 23-2 that indicates how each bit in the

identifier is compared to the masks and filters to deter-

mine if a message should be loaded into a receive

buffer. The mask essentially determines which bits to

apply the acceptance filters to. If any mask bit is set to

a zero, then that bit will automatically be accepted

regardless of the filter bit.

When a message is received in FIFO mode, the Inter-

rupt Flag Code bits (EICODE<4:0>) in the CANSTAT

register will have a value of ‘10000’, indicating the

FIFO has received a message. FIFO pointer bits

FP<3:0> in the CANCON register point to the buffer

that contains data not yet read. The FIFO pointer bits,

in this sense, serve as the FIFO read pointer. The user

should use FP bits and read corresponding buffer data.

When receive data is no longer needed, the RXFUL bit

in the current buffer must be cleared, causing FP<3:0>

to be updated by the module.

TABLE 23-2: FILTER/MASK TRUTH TABLE

Message

Identifier

bit n001

Accept or

Reject

bit n

Mask

bit n

Filter

bit n

0

1

x

0

1

x

0

1

0

1

Accept

Reject

Accept

To determine whether FIFO is empty or not, the user

may use FP<3:0> bits to access RXFUL bit in the cur-

rent buffer. If RXFUL is cleared, the FIFO is considered

to be empty. If it is set, the FIFO may contain one or

more messages. In Mode 2, the module also provides

a bit called FIFO High Water Mark (FIFOWM) in the

ECANCON register. This bit can be used to cause an

interrupt whenever the FIFO contains only one or four

empty buffers. The FIFO high water mark interrupt can

serve as an early warning to a full FIFO condition.

Legend: x= don’t care

In Mode 0, acceptance filters RXF0 and RXF1 and filter

mask RXM0 are associated with RXB0. Filters RXF2,

RXF3, RXF4 and RXF5 and mask RXM1 are

associated with RXB1.

DS30491C-page 334

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

In Mode 1 and 2, there are an additional 10 acceptance

The coding of the RXB0DBEN bit enables these three

bits to be used similarly to the FILHIT bits and to distin-

guish a hit on filter RXF0 and RXF1, in either RXB0 or

after a rollover into RXB1.

filters, RXF6-RXF15, creating a total of 16 available

filters. RXF15 can be used either as an acceptance

filter or acceptance mask register. Each of these

acceptance filters can be individually enabled or

disabled by setting or clearing RXFENn bit in the

RXFCONn register. Any of these 16 acceptance filters

can be dynamically associated with any of the receive

buffers. Actual association is made by setting appropri-

ate bits in the RXFBCONn register. Each RXFBCONn

register contains a nibble for each filter. This nibble can

be used to associate a specific filter to any of available

receive buffers. User firmware may associate more

than one filter to any one specific receive buffer.

• 111= Acceptance Filter 1 (RXF1)

• 110= Acceptance Filter 0 (RXF0)

• 001= Acceptance Filter 1 (RXF1)

• 000= Acceptance Filter 0

If the RXB0DBEN bit is clear, there are six codes cor-

responding to the six filters. If the RXB0DBEN bit is set,

there are six codes corresponding to the six filters plus

two additional codes corresponding to RXF0 and RXF1

filters that rollover into RXB1.

In addition to dynamic filter to buffer association, in

Mode 1 and 2, each filter can also be dynamically asso-

ciated to available acceptance mask registers. FILn_m

bits in the MSELn register can be used to link a specific

acceptance filter to an acceptance mask register. As

with filter to buffer association, one can also associate

more than one mask to a specific acceptance filter.

In Mode 1 and 2, each buffer control register contains

5 bits of filter hit bits FILHIT<4:0>. A binary value of ‘0’

indicates a hit from RXF0 and 15 indicates RXF15.

If more than one acceptance filter matches, the FILHIT

bits will encode the binary value of the lowest

numbered filter that matched. In other words, if filter

RXF2 and filter RXF4 match, FILHIT will be loaded with

the value for RXF2. This essentially prioritizes the

acceptance filters with a lower number filter having

higher priority. Messages are compared to filters in

ascending order of filter number.

When a filter matches and a message is loaded into the

receive buffer, the filter number that enabled the

message reception is loaded into the FILHIT bit(s). In

Mode 0 for RXB1, the RXB1CON register contains the

FILHIT<2:0> bits. They are coded as follows:

The mask and filter registers can only be modified

when the PIC18F6585/8585/6680/8680 devices are in

Configuration mode.

• 101= Acceptance Filter 5 (RXF5)

• 100= Acceptance Filter 4 (RXF4)

• 011= Acceptance Filter 3 (RXF3)

• 010= Acceptance Filter 2 (RXF2)

• 001= Acceptance Filter 1 (RXF1)

• 000= Acceptance Filter 0 (RXF0)

Note:

‘000’ and ‘001’ can only occur if the

RXB0DBEN bit is set in the RXB0CON

register, allowing RXB0 messages to

rollover into RXB1.

FIGURE 23-3:

MESSAGE ACCEPTANCE MASK AND FILTER OPERATION

Acceptance Filter Register

Acceptance Mask Register

RXFn

RXMn

0

RXMn

RxRqst

1

RXFn

1

RXFn

RXMn

n

Message Assembly Buffer

Identifier

 2004 Microchip Technology Inc.

DS30491C-page 335

PIC18F6585/8585/6680/8680

The Nominal Bit Time is defined as:

EQUATION 23-1:

23.9 Baud Rate Setting

All nodes on a given CAN bus must have the same

nominal bit rate. The CAN protocol uses Non-Return-

to-Zero (NRZ) coding which does not encode a clock

within the data stream. Therefore, the receive clock

must be recovered by the receiving nodes and

synchronized to the transmitter’s clock.

TBIT = 1/Nominal Bit Rate

The Nominal Bit Time can be thought of as being

divided into separate, non-overlapping time segments.

These segments (Figure 23-4) include:

As oscillators and transmission time may vary from

node to node, the receiver must have some type of

Phase Lock Loop (PLL) synchronized to data transmis-

sion edges to synchronize and maintain the receiver

clock. Since the data is NRZ coded, it is necessary to

include bit stuffing to ensure that an edge occurs at

least every six bit times to maintain the Digital Phase

Lock Loop (DPLL) synchronization.

• Synchronization Segment (Sync_Seg)

• Propagation Time Segment (Prop_Seg)

• Phase Buffer Segment 1 (Phase_Seg1)

• Phase Buffer Segment 2 (Phase_Seg2)

The time segments (and thus the Nominal Bit Time) are

in turn made up of integer units of time called Time

Quanta or TQ (see Figure 23-4). By definition, the Nom-

inal Bit Time is programmable from a minimum of 8 TQ

to a maximum of 25 TQ. Also by definition, the minimum

Nominal Bit Time is 1 µs, corresponding to a maximum

1 Mb/s rate. The actual duration is given by the

relationship:

The bit timing of the PIC18F6585/8585/6680/8680 is

implemented using a DPLL that is configured to syn-

chronize to the incoming data and provides the nominal

timing for the transmitted data. The DPLL breaks each

bit time into multiple segments made up of minimal

periods of time called the Time Quanta (TQ).

EQUATION 23-2:

Bus timing functions executed within the bit time frame,

such as synchronization to the local oscillator, network

transmission delay compensation, and sample point

positioning, are defined by the programmable bit timing

logic of the DPLL.

Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg +

Phase_Seg1 + Phase_Seg2)

The Time Quantum is a fixed unit derived from the

oscillator period. It is also defined by the programmable

baud rate prescaler with integer values from 1 to 64 in

addition to a fixed divide-by-two for clock generation.

Mathematically, this is:

All devices on the CAN bus must use the same bit rate.

However, all devices are not required to have the same

master oscillator clock frequency. For the different clock

frequencies of the individual devices, the bit rate has to

be adjusted by appropriately setting the baud rate

prescaler and number of time quanta in each segment.

EQUATION 23-3:

TQ (µs) = (2 * (BRP+1))/FOSC (MHz)

or

TQ (µs) = (2 * (BRP+1)) * TOSC (µs)

The Nominal Bit Rate is the number of bits transmitted

per second, assuming an ideal transmitter with an ideal

oscillator, in the absence of resynchronization. The

nominal bit rate is defined to be a maximum of 1 Mb/s.

where FOSC is the clock frequency, TOSC is the corre-

sponding oscillator period, and BRP is an integer (0

through 63) represented by the binary values of

BRGCON1<5:0>.

FIGURE 23-4:

BIT TIME PARTITIONING

Input

Signal

Propagation

Segment

Phase

Segment 1

Phase

Sync

Segment

Bit

Time

Intervals

Segment 2

TQ

Sample Point

Nominal Bit Time

DS30491C-page 336

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

23.9.1

TIME QUANTA

23.9.2

SYNCHRONIZATION SEGMENT

As already mentioned, the Time Quanta is a fixed unit

derived from the oscillator period and baud rate

prescaler. Its relationship to TBIT and the Nominal Bit

Rate is shown in Example 23-6.

This part of the bit time is used to synchronize the

various CAN nodes on the bus. The edge of the input

signal is expected to occur during the sync segment.

The duration is 1 TQ.

23.9.3

PROPAGATION SEGMENT

EXAMPLE 23-6:

CALCULATING TQ,

NOMINAL BIT RATE AND

NOMINAL BIT TIME

This part of the bit time is used to compensate for phys-

ical delay times within the network. These delay times

consist of the signal propagation time on the bus line

and the internal delay time of the nodes. The length of

the Propagation Segment can be programmed from

1 TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits.

TQ (µs) = (2 * (BRP+1))/FOSC (MHz)

TBIT (µs) = TQ (µs) * number of TQ per bit interval

Nominal Bit Rate (bits/s) = 1/TBIT

23.9.4

PHASE BUFFER SEGMENTS

CASE 1:

The phase buffer segments are used to optimally

locate the sampling point of the received bit within the

nominal bit time. The sampling point occurs between

Phase Segment 1 and Phase Segment 2. These

segments can be lengthened or shortened by the

resynchronization process. The end of Phase Segment

1 determines the sampling point within a bit time.

Phase Segment 1 is programmable from 1 TQ to 8 TQ

in duration. Phase Segment 2 provides delay before

the next transmitted data transition and is also

programmable from 1 TQ to 8 TQ in duration. However,

due to IPT requirements, the actual minimum length of

Phase Segment 2 is 2 TQ, or it may be defined to be

equal to the greater of Phase Segment 1 or the

Information Processing Time (IPT).

For FOSC = 16 MHz, BRP<5:0> = 00h and

Nominal Bit Time = 8 TQ:

TQ = (2*1)/16 = 0.125 µs (125 ns)

TBIT = 8 * 0.125 = 1 µs (10^-6s)

Nominal Bit Rate = 1/10^-6= 10⁶bits/s (1 Mb/s)

CASE 2:

For FOSC = 20 MHz, BRP<5:0> = 01h and

Nominal Bit Time = 8 TQ:

TQ = (2*2)/20 = 0.2 µs (200 ns)

TBIT = 8 * 0.2 = 1.6 µs (1.6 * 10^-6s)

Nominal Bit Rate = 1/1.6 * 10^-6s =625,000 bits/s

23.9.5

SAMPLE POINT

(625 Kb/s)

The sample point is the point of time at which the bus

level is read and the value of the received bit is deter-

mined. The sampling point occurs at the end of Phase

Segment 1. If the bit timing is slow and contains many

TQ, it is possible to specify multiple sampling of the bus

line at the sample point. The value of the received bit is

determined to be the value of the majority decision of

three values. The three samples are taken at the sam-

ple point and twice before, with a time of TQ/2 between

each sample.

CASE 3:

For FOSC = 25 MHz, BRP<5:0> = 3Fh and

Nominal Bit Time = 25 TQ:

TQ = (2*64)/25 = 5.12 µs

TBIT = 25 * 5.12 = 128 µs (1.28 * 10^-4s)

Nominal Bit Rate = 1/1.28 * 10^-4= 7813 bits/s

(7.8 Kb/s)

23.9.6

INFORMATION PROCESSING TIME

The frequencies of the oscillators in the different nodes

must be coordinated in order to provide a system wide

specified nominal bit time. This means that all oscilla-

tors must have a TOSC that is an integral divisor of TQ.

It should also be noted that although the number of TQ

is programmable from 4 to 25, the usable minimum is

8 TQ. A bit time of less than 8 TQ in length is not

guaranteed to operate correctly.

The Information Processing Time (IPT) is the time

segment starting at the sample point that is reserved

for calculation of the subsequent bit level. The CAN

specification defines this time to be less than or equal

to 2 TQ. The PIC18F6585/8585/6680/8680 devices

define this time to be 2 TQ. Thus, Phase Segment 2

must be at least 2 TQ long.

 2004 Microchip Technology Inc.

DS30491C-page 337

PIC18F6585/8585/6680/8680

The phase error of an edge is given by the position of

the edge relative to Sync_Seg, measured in TQ. The

phase error is defined in magnitude of TQ as follows:

23.10 Synchronization

To compensate for phase shifts between the oscillator

frequencies of each of the nodes on the bus, each CAN

controller must be able to synchronize to the relevant

signal edge of the incoming signal. When an edge in

the transmitted data is detected, the logic will compare

the location of the edge to the expected time

(Sync_Seg). The circuit will then adjust the values of

Phase Segment 1 and Phase Segment 2 as necessary.

There are two mechanisms used for synchronization.

• e = 0 if the edge lies within Sync_Seg.

• e > 0 if the edge lies before the sample point.

• e < 0 if the edge lies after the sample point of the

previous bit.

If the magnitude of the phase error is less than, or equal

to the programmed value of the synchronization jump

width, the effect of a resynchronization is the same as

that of a hard synchronization.

23.10.1 HARD SYNCHRONIZATION

If the magnitude of the phase error is larger than the

synchronization jump width, and if the phase error is

positive, then Phase Segment 1 is lengthened by an

amount equal to the synchronization jump width.

Hard synchronization is only done when there is a

recessive to dominant edge during a bus Idle condition,

indicating the start of a message. After hard synchroni-

zation, the bit time counters are restarted with

Sync_Seg. Hard synchronization forces the edge

which has occurred to lie within the synchronization

segment of the restarted bit time. Due to the rules of

synchronization, if a hard synchronization occurs there

will not be a resynchronization within that bit time.

If the magnitude of the phase error is larger than the

resynchronization jump width, and if the phase error is

negative, then Phase Segment 2 is shortened by an

amount equal to the synchronization jump width.

23.10.3 SYNCHRONIZATION RULES

23.10.2 RESYNCHRONIZATION

• Only one synchronization within one bit time is

allowed.

As a result of resynchronization, Phase Segment 1

may be lengthened or Phase Segment 2 may be short-

ened. The amount of lengthening or shortening of the

phase buffer segments has an upper bound given by

the Synchronization Jump Width (SJW). The value of

the SJW will be added to Phase Segment 1 (see

Figure 23-5) or subtracted from Phase Segment 2 (see

Figure 23-6). The SJW is programmable between 1 TQ

and 4 TQ.

• An edge will be used for synchronization only if

the value detected at the previous sample point

(previously read bus value) differs from the bus

value immediately after the edge.

• All other recessive to dominant edges fulfilling

rules 1 and 2 will be used for resynchronization,

with the exception that a node transmitting a

dominant bit will not perform a resynchronization

as a result of a recessive to dominant edge with a

positive phase error.

Clocking information will only be derived from reces-

sive to dominant transitions. The property that only a

fixed maximum number of successive bits have the

same value, ensures resynchronization to the bit

stream during a frame.

DS30491C-page 338

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 23-5:

LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1)

Input

Signal

Bit

Time

Segments

Prop

Phase

Sync

≤ SJW

Segment

Segment 1

Segment 2

TQ

Sample Point

Nominal Bit Length

Actual Bit Length

FIGURE 23-6:

SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2)

Prop

Phase

Sync

≤ SJW

Segment

Segment 1

Segment 2

TQ

Sample Point

Actual Bit Length

Nominal Bit Length

 2004 Microchip Technology Inc.

DS30491C-page 339

PIC18F6585/8585/6680/8680

23.13.2 BRGCON2

23.11 Programming Time Segments

The PRSEG bits set the length of the propagation seg-

ment in terms of TQ. The SEG1PH bits set the length of

Phase Segment 1 in TQ. The SAM bit controls how

many times the RXCAN pin is sampled. Setting this bit

to a ‘1’ causes the bus to be sampled three times; twice

at TQ/2 before the sample point and once at the normal

sample point (which is at the end of Phase Segment 1).

The value of the bus is determined to be the value read

during at least two of the samples. If the SAM bit is set

to a ‘0’, then the RXCAN pin is sampled only once at

the sample point. The SEG2PHTS bit controls how the

length of Phase Segment 2 is determined. If this bit is

set to a ‘1’, then the length of Phase Segment 2 is

determined by the SEG2PH bits of BRGCON3. If the

SEG2PHTS bit is set to a ‘0’, then the length of Phase

Segment 2 is the greater of Phase Segment 1 and the

information processing time (which is fixed at 2 TQ for

the PIC18F6585/8585/6680/8680).

Some requirements for programming of the time

segments:

• Prop_Seg + Phase_Seg 1 ≥ Phase_Seg 2

• Phase_Seg 2 ≥ Sync Jump Width.

For example, assume that a 125 kHz CAN baud rate is

desired, using 20 MHz for FOSC. With a TOSC of 50 ns,

a baud rate prescaler value of 04h gives a TQ of 500 ns.

To obtain a Nominal Bit Rate of 125 kHz, the Nominal

Bit Time must be 8 µs or 16 TQ.

Using 1 TQ for the Sync_Seg, 2 TQ for the Prop_Seg

and 7 TQ for Phase Segment 1, would place the sample

point at 10 TQ after the transition. This leaves 6 TQ for

Phase Segment 2.

By the rules above, the Sync Jump Width could be the

maximum of 4 TQ. However, normally a large SJW is

only necessary when the clock generation of the

different nodes is inaccurate or unstable, such as using

ceramic resonators. Typically, an SJW of 1 is enough.

23.13.3 BRGCON3

The PHSEG2<2:0> bits set the length (in TQ) of Phase

Segment 2 if the SEG2PHTS bit is set to a ‘1’. If the

SEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0>

bits have no effect.

23.12 Oscillator Tolerance

As a rule of thumb, the bit timing requirements allow

ceramic resonators to be used in applications with

transmission rates of up to 125 Kbit/sec. For the full bus

speed range of the CAN protocol, a quartz oscillator is

required. A maximum node-to-node oscillator variation

of 1.7% is allowed.

23.14 Error Detection

The CAN protocol provides sophisticated error

detection mechanisms. The following errors can be

detected.

23.13 Bit Timing Configuration

Registers

23.14.1 CRC ERROR

With the Cyclic Redundancy Check (CRC), the trans-

mitter calculates special check bits for the bit

sequence, from the start of a frame until the end of the

data field. This CRC sequence is transmitted in the

CRC field. The receiving node also calculates the CRC

sequence using the same formula and performs a

comparison to the received sequence. If a mismatch is

detected, a CRC error has occurred and an error frame

is generated. The message is repeated.

The Configuration registers (BRGCON1, BRGCON2,

BRGCON3) control the bit timing for the CAN bus

interface. These registers can only be modified when

the PIC18F6585/8585/6680/8680 devices are in

Configuration mode.

23.13.1 BRGCON1

The BRP bits control the baud rate prescaler. The

SJW<1:0> bits select the synchronization jump width in

terms of multiples of TQ.

DS30491C-page 340

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

node can transmit messages and activate error frames

(made of dominant bits) without any restrictions. In the

23.14.2 ACKNOWLEDGE ERROR

In the Acknowledge field of a message, the transmitter

checks if the Acknowledge slot (which was sent out as

a recessive bit) contains a dominant bit. If not, no other

node has received the frame correctly. An Acknowl-

edge error has occurred; an error frame is generated

and the message will have to be repeated.

error-passive state, messages and passive error

frames (made of recessive bits) may be transmitted.

The bus-off state makes it temporarily impossible for

the station to participate in the bus communication.

During this state, messages can neither be received

nor transmitted.

23.14.3 FORM ERROR

23.14.7 ERROR MODES AND ERROR

COUNTERS

If a node detects a dominant bit in one of the four

segments, including end of frame, interframe space,

Acknowledge delimiter, or CRC delimiter, then a form

error has occurred and an error frame is generated.

The message is repeated.

The PIC18F6585/8585/6680/8680 devices contain two

error counters: the Receive Error Counter

(RXERRCNT), and the Transmit Error Counter

(TXERRCNT). The values of both counters can be read

by the MCU. These counters are incremented or

decremented in accordance with the CAN bus

specification.

23.14.4 BIT ERROR

A bit error occurs if a transmitter sends a dominant bit

and detects a recessive bit, or if it sends a recessive bit

and detects a dominant bit, when monitoring the actual

bus level and comparing it to the just transmitted bit. In

the case where the transmitter sends a recessive bit

and a dominant bit is detected during the arbitration

field and the Acknowledge slot, no bit error is

generated because normal arbitration is occurring.

The PIC18F6585/8585/6680/8680 devices are error-

active if both error counters are below the error-passive

limit of 128. They are error-passive if at least one of the

error counters equals or exceeds 128. They go to bus-

off if the transmit error counter equals or exceeds the

bus-off limit of 256. The devices remain in this state

until the bus-off recovery sequence is received. The

bus-off recovery sequence consists of 128 occurrences

of 11 consecutive recessive bits (see Figure 23-7).

Note that the CAN module, after going bus-off, will

recover back to error-active without any intervention by

the MCU if the bus remains Idle for 128 x 11 bit times.

If this is not desired, the error Interrupt Service Routine

should address this. The current Error mode of the

CAN module can be read by the MCU via the

COMSTAT register.

23.14.5 STUFF BIT ERROR

lf between the start of frame and the CRC delimiter, six

consecutive bits with the same polarity are detected,

the bit stuffing rule has been violated. A stuff bit error

occurs and an error frame is generated. The message

is repeated.

23.14.6 ERROR STATES

Detected errors are made public to all other nodes via

error frames. The transmission of the erroneous mes-

sage is aborted and the frame is repeated as soon as

possible. Furthermore, each CAN node is in one of the

three error states “error-active”, “error-passive” or “bus-

off” according to the value of the internal error counters.

The error-active state is the usual state where the bus

Additionally, there is an error state warning flag bit,

EWARN, which is set if at least one of the error

counters equals or exceeds the error warning limit of

96. EWARN is reset if both error counters are less than

the error warning limit.

 2004 Microchip Technology Inc.

DS30491C-page 341

PIC18F6585/8585/6680/8680

FIGURE 23-7:

ERROR MODES STATE DIAGRAM

Reset

Error

Active

-

RXERRCNT < 127 or

TXERRCNT < 127

128 occurrences of

11 consecutive

“recessive” bits

RXERRCNT > 127 or

TXERRCNT > 127

Error

-

Passive

TXERRCNT > 255

Bus

Off

-

The transmit related interrupts are:

23.15 CAN Interrupts

• Transmit Interrupts

The module has several sources of interrupts. Each of

these interrupts can be individually enabled or dis-

abled. The PIR3 register contains interrupt flags. The

PIE3 register contains the enables for the 8 main inter-

rupts. A special set of read-only bits in the CANSTAT

register, the ICODE bits, can be used in combination

with a jump table for efficient handling of interrupts.

• Transmitter Warning Interrupt

• Transmitter Error-Passive Interrupt

• Bus-Off Interrupt

23.15.1 INTERRUPT CODE BITS

To simplify the interrupt handling process in user firm-

ware, the ECAN module encodes a special set of bits. In

Mode 0, these bits are ICODE<2:0> in the CANSTAT

register. In Mode 1 and 2, these bits are EICODE<3:0>

in the CANSTAT register. Interrupts are internally priori-

tized such that the higher priority interrupts are assigned

lower values. Once the highest priority interrupt condi-

tion has been cleared, the code for the next highest

priority interrupt that is pending (if any) will be reflected

by the ICODE bits. Note that only those interrupt sources

that have their associated interrupt enable bit set will be

reflected in the ICODE bits.

All interrupts have one source with the exception of the

error interrupt and buffer interrupts in Mode 1 and 2. Any

of the error interrupt sources can set the error interrupt

flag. The source of the error interrupt can be determined

by reading the Communication Status register,

COMSTAT. In Mode 1 and 2, there are two interrupt

enable/disable and flag bits – one for all transmit buffers

and the other for all receive buffers.

The interrupts can be broken up into two categories:

receive and transmit interrupts.

The receive related interrupts are:

In Mode 2, when a receive message interrupt occurs,

EICODE bits will always consist of ‘10000’. User

firmware may use FIFO pointer bits to actually access

the next available buffer.

• Receive Interrupts

• Wake-up Interrupt

• Receiver Overrun Interrupt

• Receiver Warning Interrupt

• Receiver Error-Passive Interrupt

DS30491C-page 342

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

23.15.2 TRANSMIT INTERRUPT

23.15.5 BUS ACTIVITY WAKE-UP

INTERRUPT

When the transmit interrupt is enabled, an interrupt will

be generated when the associated transmit buffer

becomes empty and is ready to be loaded with a new

message. In Mode 0, there are separate interrupt

enable/disable and flag bits for each of the three

dedicated transmit buffers. The TXBnIF bit will be set to

indicate the source of the interrupt. The interrupt is

cleared by the MCU resetting the TXBnIF bit to a ‘0’. In

Mode 1 and 2, all transmit buffers share one interrupt

enable/disable and flag bits. In Mode 1 and 2, TXBIE in

PIE3 and TXBIF in PIR3 indicate when a transmit buffer

has completed transmission of its message. TXBnIF,

TXBnIE and TXBnIP in PIR3, PIE3 and IPR3, respec-

tively, are not used in Mode 1 and 2. Individual transmit

buffer interrupts can be enabled or disabled by setting or

clearing TXBIE and BnIE register bits. When a shared

interrupt occurs, user firmware must poll the TXREQ bit

of all transmit buffers to detect the source of interrupt.

When the PIC18F6585/8585/6680/8680 devices are in

Sleep mode and the bus activity wake-up interrupt is

enabled, an interrupt will be generated and the WAKIF

bit will be set when activity is detected on the CAN bus.

This interrupt causes the PIC18F6585/8585/6680/

8680 devices to exit Sleep mode. The interrupt is reset

by the MCU, clearing the WAKIF bit.

23.15.6 ERROR INTERRUPT

When the error interrupt is enabled, an interrupt is

generated if an overflow condition occurs or if the error

state of the transmitter or receiver has changed. The

error flags in COMSTAT will indicate one of the

following conditions.

23.15.6.1 Receiver Overflow

An overflow condition occurs when the MAB has

assembled a valid received message (the message

meets the criteria of the acceptance filters) and the

receive buffer associated with the filter is not available

for loading of a new message. The associated

COMSTAT.RXnOVFL bit will be set to indicate the

overflow condition. This bit must be cleared by the

MCU.

23.15.3 RECEIVE INTERRUPT

When the receive interrupt is enabled, an interrupt will

be generated when a message has been successfully

received and loaded into the associated receive buffer.

This interrupt is activated immediately after receiving

the End Of Frame (EOF) field.

In Mode 0, the RXBnIF bit is set to indicate the source

of the interrupt. The interrupt is cleared by the MCU

resetting the RXBnIF bit to a ‘0’.

23.15.6.2 Receiver Warning

The receive error counter has reached the MCU

warning limit of 96.

In Mode 1 and 2, all receive buffers share one interrupt.

Individual receive buffer interrupts can be controlled by

the RXBnIE and BIEn registers. In Mode 1, when a

shared receive interrupt occurs, user firmware must

poll the RXFUL bit of each receive buffer to detect the

source of interrupt. In Mode 2, a receive interrupt

indicates that the new message is loaded into FIFO.

FIFO can be read by using FIFO pointer bits, FP.

23.15.6.3 Transmitter Warning

The transmit error counter has reached the MCU

warning limit of 96.

23.15.6.4 Receiver Bus Passive

The receive error counter has exceeded the error-

passive limit of 127 and the device has gone to

error-passive state.

In Mode 2, the FIFOWMIF bit indicates if the FIFO high

watermark is reached. The FIFO high watermark is

defined by the FIFOWM bit in the ECANCON register.

23.15.6.5 Transmitter Bus Passive

23.15.4 MESSAGE ERROR INTERRUPT

The transmit error counter has exceeded the error-

passive limit of 127 and the device has gone to

error-passive state.

When an error occurs during transmission or reception

of a message, the message error flag, IRXIF, will be set

and if the IRXIE bit is set, an interrupt will be generated.

This is intended to be used to facilitate baud rate

determination when used in conjunction with Listen

Only mode.

23.15.6.6 Bus-Off

The transmit error counter has exceeded 255 and the

device has gone to bus-off state.

23.15.6.7 Interrupt Acknowledge

Interrupts are directly associated with one or more sta-

tus flags in the PIR register. Interrupts are pending as

long as one of the flags is set. Once an interrupt flag is

set by the device, the flag can not be reset by the

microcontroller until the interrupt condition is removed.

 2004 Microchip Technology Inc.

DS30491C-page 343

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 344

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

24.1 Configuration Bits

24.0 SPECIAL FEATURES OF THE

CPU

The configuration bits can be programmed (read as ‘0’)

or left unprogrammed (read as ‘1’) to select various

device configurations. These bits are mapped, starting

at program memory location 300000h.

There are several features intended to maximize sys-

tem reliability, minimize cost through elimination of

external components, provide power saving operating

modes and offer code protection. These are:

The user will note that address 300000h is beyond the

user program memory space. In fact, it belongs to the

configuration memory space (300000h through

3FFFFFh) which can only be accessed using table

reads and table writes.

• OSC Selection

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

Programming the Configuration registers is done in a

manner similar to programming the Flash memory. The

EECON1 register WR bit starts a self-timed write to the

Configuration register. In normal Operation mode, a

TBLWTinstruction with the TBLPTR pointed to the Con-

figuration register sets up the address and the data for

the Configuration register write. Setting the WR bit

starts a long write to the Configuration register. The

Configuration registers are written a byte at a time. To

write or erase a configuration cell, a TBLWTinstruction

can write a ‘1’ or a ‘0’ into the cell.

• Watchdog Timer (WDT)

• Sleep

• Code Protection

• ID Locations

• In-Circuit Serial Programming

All PIC18F6585/8585/6680/8680 devices have

a

Watchdog Timer which is permanently enabled via the

configuration bits or software controlled. It runs off its

own RC oscillator for added reliability. There are two

timers that offer necessary delays on power-up. One is

the Oscillator Start-up Timer (OST), intended to keep

the chip in Reset until the crystal oscillator is stable.

The other is the Power-up Timer (PWRT) which pro-

vides a fixed delay on power-up only, designed to keep

the part in Reset while the power supply stabilizes. With

these two timers on-chip, most applications need no

external Reset circuitry.

Sleep mode is designed to offer a very low current

Power-down mode. The user can wake-up from Sleep

through external Reset, Watchdog Timer Wake-up, or

through an interrupt. Several oscillator options are also

made available to allow the part to fit the application.

The RC oscillator option saves system cost, while the

LP crystal option saves power. A set of configuration

bits is used to select various options.

 2004 Microchip Technology Inc.

DS30491C-page 345

PIC18F6585/8585/6680/8680

TABLE 24-1: CONFIGURATION BITS AND DEVICE IDS

Default/

Unprogrammed

Value

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300001h CONFIG1H

300002h CONFIG2L

300003h CONFIG2H

—

OSCSEN

—

FOSC3

BORV1

FOSC2

BORV0

FOSC1

BODEN

FOSC0

PWRTEN

WDTEN

PM0

--1- 1111

---- 1111

---1 1111

1--- --11

1--- -1-1

---- 1111

11-- ----

---- 1111

111- ----

---- 1111

-1-- ----

(Note 3)

—

WDTPS3 WDTPS2 WDTPS1 WDTPS0

(1)

300004h CONFIG3L

WAIT

—

PM1

ECCPMX

—

(4)

300005h CONFIG3H MCLRE

300006h CONFIG4L DEBUG

—

CCP2MX

STVREN

CP0

—

LVP

CP2

—

(2)

300008h CONFIG5L

300009h CONFIG5H

30000Ah CONFIG6L

—

CPD

—

CP3

—

CP1

CPB

—

(2)

—

WRT3

—

WRT2

—

WRT1

—

WRT0

—

30000Bh CONFIG6H WRTD

WRTB

—

WRTC

—

30000Ch CONFIG7L

30000Dh CONFIG7H

3FFFFEh DEVID1

3FFFFFh DEVID2

—

EBTR3

—

EBTR2

—

EBTR1

—

EBTR0

—

EBTRB

DEV1

DEV9

—

DEV2

DEV10

DEV0

DEV8

REV4

DEV7

REV3

DEV6

REV2

DEV5

REV1

DEV4

REV0

DEV3

0000 1010

Legend:

x= unknown, u= unchanged, -= unimplemented, q= value depends on condition.

Shaded cells are unimplemented, read as ‘0’.

Note 1: Unimplemented in PIC18F6X8X devices; maintain this bit set.

2: Unimplemented in PIC18FX585 devices; maintain this bit set.

3: See Register 24-13 for DEVID1 values.

4: Reserved in PIC18F6X8X devices; maintain this bit set.

DS30491C-page 346

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 24-1: CONFIG1H:CONFIGURATIONREGISTER1HIGH(BYTEADDRESS300001h)

U-0

—

U-0

—

R/P-1

U-0

—

R/P-1

OSCSEN

FOSC3

FOSC2

FOSC1

FOSC0

bit 7

bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5

bit 4

OSCSEN: Oscillator System Clock Switch Enable bit

1= Oscillator system clock switch option is disabled (main oscillator is source)

0= Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled)

Unimplemented: Read as ‘0’

bit 3-0 FOSC3:FOSC0: Oscillator Selection bits

1111= RC oscillator with OSC2 configured as RA6

1110= HS oscillator with SW enabled 4x PLL

1101= EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL

1100= EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL

1011= Reserved; do not use

1010= Reserved; do not use

1001= Reserved; do not use

1000= Reserved; do not use

0111= RC oscillator with OSC2 configured as RA6

0110= HS oscillator with HW enabled 4x PLL

0101= EC oscillator with OSC2 configured as RA6

0100= EC oscillator with OSC2 configured as divide by 4 clock output

0011= RC oscillator with OSC2 configured as divide by 4 clock output

0010= HS oscillator

0001= XT oscillator

0000= LP oscillator

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

 2004 Microchip Technology Inc.

DS30491C-page 347

PIC18F6585/8585/6680/8680

REGISTER 24-2: CONFIG2L:CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS300002h)

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

BORV1

BORV0 BOREN PWRTEN

bit 0

bit 7

bit 7-4 Unimplemented: Read as ‘0’

bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits

11= VBOR set to 2.0V

10= VBOR set to 2.7V

01= VBOR set to 4.2V

00= VBOR set to 4.5V

bit 1

bit 0

BOREN: Brown-out Reset Enable bit

1= Brown-out Reset enabled

0= Brown-out Reset disabled

PWRTEN: Power-up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS30491C-page 348

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 24-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)

U-0

—

U-0

—

U-0

—

R/P-1

WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN

bit 0

bit 7

bit 7-5 Unimplemented: Read as ‘0’

bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscaler Select bits

1111 = 1:32768

1110 = 1:16384

1101 = 1:8192

1100 = 1:4096

1011 = 1:2048

1010 = 1:1024

1001 = 1:512

1000 = 1:256

0111= 1:128

0110= 1:64

0101= 1:32

0100= 1:16

0011= 1:8

0010= 1:4

0001= 1:2

0000= 1:1

bit 0

WDTEN: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled (control is placed on the SWDTEN bit)

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

REGISTER 24-4: CONFIG3L:CONFIGURATIONREGISTER3LOW(BYTEADDRESS300004h)⁽¹⁾

R/P-1

WAIT

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

PM1

R/P-1

PM0

bit 7

bit 0

bit 7

WAIT: External Bus Data Wait Enable bit

1= Wait selections unavailable for table reads and table writes

0= Wait selections for table reads and table writes are determined by WAIT1:WAIT0 bits

(MEMCOM<5:4>)

bit 6-2 Unimplemented: Read as ‘0’

bit 1-0 PM1:PM0: Processor Mode Select bits

11= Microcontroller mode

10= Microprocessor mode

01= Microprocessor with Boot Block mode

00= Extended Microcontroller mode

Note 1: This register is unimplemented for PIC18F6X8X devices; maintain these bits set.

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

 2004 Microchip Technology Inc.

DS30491C-page 349

PIC18F6585/8585/6680/8680

REGISTER 24-5: CONFIG3H:CONFIGURATIONREGISTER3HIGH(BYTEADDRESS300005h)

R/P-1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

MCLRE

ECCPMX CCP2MX

bit 0

bit 7

MCLRE: MCLR Enable bit⁽¹⁾

1= MCLR pin enabled, RG5 input pin disabled

0= RG5 input enabled, MCLR disabled

bit 6-2 Unimplemented: Read as ‘0’

bit 1

ECCPMX: CCP1 PWM outputs P1B, P1C mux bit (PIC18F8X8X devices only)⁽²⁾

1= P1B, P1C are multiplexed with RE6, RE5

0= P1B, P1C are multiplexed with RH7, RH6

bit 0

CCP2MX: CCP2 Mux bit

In Microcontroller mode:

1= CCP2 input/output is multiplexed with RC1

0= CCP2 input/output is multiplexed with RE7

In Microprocessor, Microprocessor with Boot Block and Extended Microcontroller modes

(PIC18F8X8X devices only):

1= CCP2 input/output is multiplexed with RC1

0= CCP2 input/output is multiplexed with RB3

Note 1: If MCLR is disabled, either disable low-voltage ICSP or hold RB5/PGM low to

ensure proper entry into ICSP mode.

2: Reserved for PIC18F6X8X devices; maintain this bit set.

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

REGISTER 24-6: CONFIG4L:CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS300006h)

R/P-1

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

LVP

U-0

—

R/P-1

STVREN

bit 0

DEBUG

bit 7

DEBUG: Background Debugger Enable bit

1= Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins.

0= Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug.

bit 6-3 Unimplemented: Read as ‘0’

bit 2

LVP: Low-Voltage ICSP Enable bit

1= Low-voltage ICSP enabled

0= Low-voltage ICSP disabled

bit 1

bit 0

Unimplemented: Read as ‘0’

STVREN: Stack Full/Underflow Reset Enable bit

1= Stack full/underflow will cause Reset

0= Stack full/underflow will not cause Reset

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS30491C-page 350

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 24-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1

CP3⁽¹⁾

R/C-1

CP2

R/C-1

CP1

R/C-1

CP0

bit 7

bit 0

bit 7-4 Unimplemented: Read as ‘0’

bit 3

CP3: Code Protection bit⁽¹⁾

1= Block 3 (00C000-00FFFFh) not code-protected

0= Block 3 (00C000-00FFFFh) code-protected

Note 1: Unimplemented in PIC18FX585 devices; maintain this bit set.

CP2: Code Protection bit

bit 2

bit 1

bit 0

1= Block 2 (008000-00BFFFh) not code-protected

0= Block 2 (008000-00BFFFh) code-protected

CP1: Code Protection bit

1= Block 1 (004000-007FFFh) not code-protected

0= Block 1 (004000-007FFFh) code-protected

CP0: Code Protection bit

1= Block 0 (000800-003FFFh) not code-protected

0= Block 0 (000800-003FFFh) code-protected

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

REGISTER 24-8: CONFIG5H:CONFIGURATIONREGISTER5HIGH(BYTEADDRESS300009h)

R/C-1

CPD

R/C-1

CPB

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

bit 7

bit 6

CPD: Data EEPROM Code Protection bit

1= Data EEPROM not code-protected

0= Data EEPROM code-protected

CPB: Boot Block Code Protection bit

1= Boot block (000000-0007FFh) not code-protected

0= Boot block (000000-0007FFh) code-protected

bit 5-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

 2004 Microchip Technology Inc.

DS30491C-page 351

PIC18F6585/8585/6680/8680

REGISTER 24-9: CONFIG6L:CONFIGURATIONREGISTER6LOW(BYTE ADDRESS30000Ah)

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1

WRT3⁽¹⁾

R/C-1

WRT2

R/C-1

WRT1

R/C-1

WRT0

bit 7

bit 0

bit 7-4 Unimplemented: Read as ‘0’

bit 3

WRT3: Write Protection bit⁽¹⁾

1= Block 3 (00C000-00FFFFh) not write-protected

0= Block 3 (00C000-00FFFFh) write-protected

Note 1: Unimplemented in PIC18FX585 devices; maintain this bit set.

WRT2: Write Protection bit

bit 2

bit 1

bit 0

1= Block 2 (008000-00BFFFh) not write-protected

0= Block 2 (008000-00BFFFh) write-protected

WRT1: Write Protection bit

1= Block 1 (004000-007FFFh) not write-protected

0= Block 1 (004000-007FFFh) write-protected

WR0: Write Protection bit

1= Block 0 (000800-003FFFh) not write-protected

0= Block 0 (000800-003FFFh) write-protected

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

REGISTER 24-10: CONFIG6H:CONFIGURATION REGISTER 6 HIGH(BYTEADDRESS30000Bh)

R/C-1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

WRTD

WRTB

WRTC

bit 7

bit 0

bit 7

bit 6

bit 5

WRTD: Data EEPROM Write Protection bit

1= Data EEPROM not write-protected

0= Data EEPROM write-protected

WRTB: Boot Block Write Protection bit

1= Boot block (000000-0007FFh) not write-protected

0= Boot block (000000-0007FFh) write-protected

WRTC: Configuration Register Write Protection bit

1= Configuration registers (300000-3000FFh) not write-protected

0= Configuration registers (300000-3000FFh) write-protected

bit 4-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS30491C-page 352

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

REGISTER 24-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1

EBTR3⁽¹⁾

R/C-1

EBTR2

EBTR1

EBTR0

bit 7

bit 0

bit 7-4 Unimplemented: Read as ‘0’

bit 3

EBTR3: Table Read Protection bit⁽¹⁾

1= Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks

0= Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks

Note 1: Unimplemented in PIC18FX585 devices; maintain this bit set.

EBTR2: Table Read Protection bit

bit 2

bit 1

bit 0

1= Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks

0= Block 2 (008000-00BFFFh) protected from table reads executed in other blocks

EBTR1: Table Read Protection bit

1= Block 1 (004000-007FFFh) not protected from table reads executed in other blocks

0= Block 1 (004000-007FFFh) protected from table reads executed in other blocks

EBTR0: Table Read Protection bit

1= Block 0 (000800-003FFFh) not protected from table reads executed in other blocks

0= Block 0 (000800-003FFFh) protected from table reads executed in other blocks

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

REGISTER 24-12: CONFIG7H:CONFIGURATION REGISTER 7 HIGH(BYTEADDRESS30000Dh)

U-0

—

R/C-1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

EBTRB

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ‘0’

EBTRB: Boot Block Table Read Protection bit

1= Boot block (000000-0007FFh) not protected from table reads executed in other blocks

0= Boot block (000000-0007FFh) protected from table reads executed in other blocks

bit 5-0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

 2004 Microchip Technology Inc.

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PIC18F6585/8585/6680/8680

REGISTER 24-13: DEVICE ID REGISTER 1 FOR PIC18FXX8X DEVICES (ADDRESS 3FFFFEh)

R

DEV2

DEV1

DEV0

REV4

REV3

REV2

REV1

REV0

bit 7

bit 0

bit 7-5 DEV2:DEV0: Device ID bits

000= PIC18F8680

001= PIC18F6680

010= PIC18F8585

011= PIC18F6585

bit 4-0 REV4:REV0: Revision ID bits

These bits are used to indicate the device revision.

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

REGISTER 24-14: DEVICE ID REGISTER 2 FOR PIC18FXX8X DEVICES (ADDRESS 3FFFFFh)

R-0

R-1

R-0

R-1

R-0

DEV3

bit 0

DEV10

DEV9

DEV8

DEV7

DEV6

DEV5

DEV4

bit 7

bit 7-0 DEV10:DEV3: Device ID bits

These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the

part number.

0000 1010= PIC18F6585/8585/6680/8680

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

- n = Value when device is unprogrammed

DS30491C-page 354

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The WDT time-out period values may be found in

Section 27.0 “Electrical Characteristics” under

24.2 Watchdog Timer (WDT)

The Watchdog Timer is a free-running, on-chip RC

oscillator which does not require any external compo-

nents. This RC oscillator is separate from the RC

oscillator of the OSC1/CLKI pin. That means that the

WDT will run even if the clock on the OSC1/CLKI and

OSC2/CLKO/RA6 pins of the device has been stopped,

for example, by execution of a SLEEPinstruction.

parameter #31. Values for the WDT postscaler may be

assigned using the configuration bits.

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and the postscaler if

assigned to the WDT and prevent it from

timing out and generating a device Reset

condition.

During normal operation, a WDT time-out generates a

device Reset (Watchdog Timer Reset). If the device is

in Sleep mode, a WDT time-out causes the device to

wake-up and continue with normal operation (Watch-

dog Timer wake-up). The TO bit in the RCON register

will be cleared upon a WDT time-out.

2: When a CLRWDT instruction is executed

and the postscaler is assigned to the

WDT, the postscaler count will be cleared

but the postscaler assignment is not

changed.

The Watchdog Timer is enabled/disabled by a device

configuration bit. If the WDT is enabled, software

execution may not disable this function. When the

WDTEN configuration bit is cleared, the SWDTEN bit

enables/disables the operation of the WDT.

24.2.1

CONTROL REGISTER

Register 24-15 shows the WDTCON register. This is a

readable and writable register which contains a control

bit that allows software to override the WDT enable

configuration bit, only when the configuration bit has

disabled the WDT.

REGISTER 24-15: WDTCON REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SWDTEN

bit 0

bit 7

bit 7-1 Unimplemented: Read as ‘0’

bit 0

SWDTEN: Software Controlled Watchdog Timer Enable bit

1= Watchdog Timer is on

0= Watchdog Timer is turned off if the WDTEN configuration bit in the Configuration register = 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

 2004 Microchip Technology Inc.

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24.2.2

WDT POSTSCALER

The WDT has a postscaler that can extend the WDT

Reset period. The postscaler is selected at the time of

the device programming by the value written to the

CONFIG2H Configuration register.

FIGURE 24-1:

WATCHDOG TIMER BLOCK DIAGRAM

WDT Timer

Postscaler

16

WDTPS3:WDTPS0

16-to-1 MUX

WDTEN

Configuration bit

SWDTEN bit

WDT

Time-out

Note:

WDPS3:WDPS0 are bits in register CONFIG2H.

TABLE 24-2: SUMMARY OF WATCHDOG TIMER REGISTERS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CONFIG2H

RCON

—

IPEN

—

WDTPS3 WDTPS2 WDTPS2 WDTPS0

WDTEN

BOR

RI

—

TO

—

PD

—

POR

—

WDTCON

SWDTEN

Legend: Shaded cells are not used by the Watchdog Timer.

DS30491C-page 356

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

Other peripherals cannot generate interrupts since

during Sleep, no on-chip clocks are present.

24.3 Power-down Mode (Sleep)

Power-down mode is entered by executing a SLEEP

External MCLR Reset will cause a device Reset. All

other events are considered a continuation of program

execution and will cause a “wake-up”. The TO and PD

bits in the RCON register can be used to determine the

cause of the device Reset. The PD bit which is set on

power-up is cleared when Sleep is invoked. The TO bit

is cleared if a WDT time-out occurred (and caused

wake-up).

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit (RCON<3>) is cleared, the

TO (RCON<4>) bit is set and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, low, or high-impedance).

For lowest current consumption in this mode, place all

I/O pins at either VDD or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down

the A/D and disable external clocks. Pull all I/O pins

that are high-impedance inputs, high or low externally

to avoid switching currents caused by floating inputs.

The T0CKI input should also be at VDD or VSS for low-

est current consumption. The contribution from on-chip

pull-ups on PORTB should be considered.

When the SLEEPinstruction is being executed, the next

instruction (PC + 2) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOPafter the SLEEPinstruction.

The MCLR pin must be at a logic high level (VIHMC).

24.3.1

WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

24.3.2

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

1. External Reset input on MCLR pin.

2. Watchdog Timer Wake-up (if WDT was

enabled).

• If an interrupt condition (interrupt flag bit and

interrupt enable bits are set) occurs before the

execution of a SLEEPinstruction, the SLEEP

instruction will complete as a NOP. Therefore, the

WDT and WDT postscaler will not be cleared, the

TO bit will not be set and PD bits will not be

cleared.

3. Interrupt from INT pin, RB port change or a

peripheral interrupt.

The following peripheral interrupts can wake the device

from Sleep:

1. PSP read or write.

2. TMR1 interrupt. Timer1 must be operating as an

asynchronous counter.

• If the interrupt condition occurs during or after

the execution of a SLEEPinstruction, the device

will immediately wake-up from Sleep. The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT

3. TMR3 interrupt. Timer3 must be operating as an

asynchronous counter.

4. CCP Capture mode interrupt.

5. Special event trigger (Timer1 in Asynchronous

mode using an external clock).

postscaler will be cleared, the TO bit will be set

and the PD bit will be cleared.

6. MSSP (Start/Stop) bit detect interrupt.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

7. MSSP transmit or receive in Slave mode

(SPI/I²C).

8. USART RX or TX (Synchronous Slave mode).

9. A/D conversion (when A/D clock source is RC).

10. EEPROM write operation complete.

11. LVD interrupt.

To ensure that the WDT is cleared, a CLRWDT

instruction should be executed before a SLEEP

instruction.

12. CAN wake-up interrupt.

 2004 Microchip Technology Inc.

DS30491C-page 357

PIC18F6585/8585/6680/8680

FIGURE 24-2:

WAKE-UP FROM SLEEP THROUGH INTERRUPT^(1,2)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKO⁽⁴⁾

INT pin

(2)

TOST

INTF Flag

(INTCON<1>)

Interrupt Latency⁽³⁾

GIEH bit

(INTCON<7>)

Processor in

Sleep

INSTRUCTION FLOW

PC

PC+2

PC+4

PC + 4

0008h

000Ah

Instruction

Inst(0008h)

Inst(PC + 2)

Inst(PC + 4)

Inst(PC + 2)

Inst(000Ah)

Inst(PC) = Sleep

Fetched

Instruction

Executed

Dummy Cycle

Inst(0008h)

Sleep

Inst(PC - 1)

Note 1: XT, HS or LP Oscillator mode assumed.

2: GIE = 1assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.

3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Oscillator modes.

4: CLKO is not available in these oscillator modes but shown here for timing reference.

DS30491C-page 358

 2004 Microchip Technology Inc.

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Figure 24-3 shows the program memory organization

for 48 and 64-Kbyte devices and the specific code

protection bit associated with each block. The actual

24.4 Program Verification and

Code Protection

The overall structure of the code protection on the

PIC18 Flash devices differs significantly from other

PICmicro^®devices.

locations of the bits are summarized in Table 24-3.

The user program memory is divided on binary bound-

aries into four blocks of 16 Kbytes each. The first block

is further divided into a boot block of 2048 bytes and a

second block (Block 0) of 14 Kbytes.

Each of the blocks has three code protection bits

associated with them. They are:

• Code-Protect bit (CPn)

• Write-Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

FIGURE 24-3:

CODE-PROTECTED PROGRAM MEMORY FOR PIC18FXX8X DEVICES

MEMORY SIZE/DEVICE

Block Code Protection

48 Kbytes

64 Kbytes

Address

Controlled By:

(PIC18FX585

(PIC18FX680)

Range

000000h

0007FFh

Boot Block

Block 0

CPB, WRTB, EBTRB

CP0, WRT0, EBTR0

000800h

003FFFh

Block 0

Block 1

004000h

Block 1

Block 2

Block 3

CP1, WRT1, EBTR1

CP2, WRT2, EBTR2

CP3, WRT3, EBTR3

007FFFh

008000h

Block 2

00BFFFh

00C000h

Unimplemented Read ‘0’

00FFFFh

TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300008h

CONFIG5L

CONFIG5H

CONFIG6L

—

CPD

—

CPB

—

CP3⁽¹⁾

CP2

—

CP1

—

CP0

—

300009h

30000Ah

30000Bh

30000Ch

30000Dh

—

WRT3⁽¹⁾

—

EBTR3⁽¹⁾EBTR2

WRT2

—

WRT1

—

WRT0

—

CONFIG6H WRTD

WRTB

—

WRTC

—

CONFIG7L

CONFIG7H

—

EBTR1

—

EBTR0

—

EBTRB

—

Legend: Shaded cells are unimplemented.

Note 1: Unimplemented in PIC18FX585 devices.

 2004 Microchip Technology Inc.

DS30491C-page 359

PIC18F6585/8585/6680/8680

that block is not allowed to read and will result in read-

ing ‘0’s. Figures 24-4 through 24-6 illustrate table write

and table read protection.

24.4.1

PROGRAM MEMORY

CODE PROTECTION

The user memory may be read to or written from any

location using the table read and table write instruc-

tions. The device ID may be read with table reads. The

Configuration registers may be read and written with

the table read and table write instructions.

Note:

Code protection bits may only be written to

a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ state. Code

protection bits are only set to ‘1’ by a full

chip erase or block erase function. The full

chip erase and block erase functions can

only be initiated via ICSP or an external

programmer.

In User mode, the CPn bits have no direct effect. CPn

bits inhibit external reads and writes. A block of user

memory may be protected from table writes if the

WRTn configuration bit is ‘0’. The EBTRn bits control

table reads. For a block of user memory with the

EBTRn bit set to ‘0’, a table read instruction that exe-

cutes from within that block is allowed to read. A table

read instruction that executes from a location outside of

FIGURE 24-4:

TABLE WRITE (WRTn) DISALLOWED

Register Values

Program Memory

Configuration Bit Settings

000000h

0007FFh

000800h

WRTB, EBTRB = 11

TBLPTR = 000FFFh

PC = 003FFEh

WRT0, EBTR0 = 01

WRT1, EBTR1 = 11

TBLWT *

003FFFh

004000h

007FFFh

008000h

TBLWT *

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

PC = 008FFEh

00BFFFh

00C000h

00FFFFh

Results: All table writes disabled to Block n whenever WRTn = 0.

DS30491C-page 360

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 24-5:

EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED

Register Values

Program Memory Configuration Bit Settings

000000h

0007FFh

000800h

WRTB, EBTRB = 11

WRT0, EBTR0 = 10

TBLPTR = 000FFFh

003FFFh

004000h

TBLRD *

PC = 004FFEh

WRT1, EBTR1 = 11

007FFFh

008000h

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

00BFFFh

00C000h

00FFFFh

Results: All table reads from external blocks to Block n are disabled whenever EBTRn = 0.

TABLAT register returns a value of ‘0’.

FIGURE 24-6:

EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED

Register Values

Program Memory

Configuration Bit Settings

000000h

0007FFh

000800h

WRTB, EBTRB = 11

TBLPTR = 000FFFh

PC = 003FFEh

WRT0, EBTR0 = 10

TBLRD *

003FFFh

004000h

WRT1, EBTR1 = 11

007FFFh

008000h

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

00BFFFh

00C000h

00FFFFh

Results: Table reads permitted within Block n even when EBTRBn = 0.

TABLAT register returns the value of the data at the location TBLPTR.

 2004 Microchip Technology Inc.

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24.4.2

DATA EEPROM CODE

PROTECTION

24.7 In-Circuit Debugger

When the DEBUG bit in Configuration register,

CONFIG4L, is programmed to a ‘0’, the in-circuit

debugger functionality is enabled. This function allows

simple debugging functions when used with MPLAB^®

IDE. When the microcontroller has this feature

enabled, some of the resources are not available for

general use. Table 24-4 shows which features are

consumed by the background debugger.

The entire data EEPROM is protected from external

reads and writes by two bits: CPD and WRTD. CPD

inhibits external reads and writes of data EEPROM.

WRTD inhibits external writes to data EEPROM. The

CPU can continue to read and write data EEPROM

regardless of the protection bit settings.

24.4.3

CONFIGURATION REGISTER

PROTECTION

TABLE 24-4: DEBUGGER RESOURCES

The Configuration registers can be write-protected. The

WRTC bit controls protection of the Configuration regis-

ters. In User mode, the WRTC bit is readable only. WRTC

can only be written via ICSP or an external programmer.

I/O pins

RB6, RB7

Stack

2 levels

512 bytes

10 bytes

Program Memory

Data Memory

24.5 ID Locations

To use the in-circuit debugger function of the micro-

controller, the design must implement In-Circuit Serial

Programming connections to MCLR/VPP, VDD, GND,

RB7 and RB6. This will interface to the in-circuit

debugger module available from Microchip or one of

the third party development tool companies.

Eight memory locations (200000h-200007h) are

designated as ID locations where the user can store

checksum or other code identification numbers. These

locations are accessible during normal execution

through the TBLRD and TBLWT instructions or during

program/verify. The ID locations can be read when the

device is code-protected.

24.6

In-Circuit Serial Programming

PIC18FXX80/XX85 microcontrollers can be serially

programmed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

DS30491C-page 362

 2004 Microchip Technology Inc.

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If Low-Voltage Programming mode is not used, the LVP

24.8 Low-Voltage ICSP Programming

bit can be programmed to a ‘0’ and RB5/KBI1/PGM

becomes a digital I/O pin. However, the LVP bit may

only be programmed when programming is entered

with VIHH on RG5/MCLR/VPP.

The LVP bit in Configuration register, CONFIG4L,

enables Low-Voltage ICSP Programming. This mode

allows the microcontroller to be programmed via ICSP

using a VDD source in the operating voltage range. This

only means that VPP does not have to be brought to VIHH

but can instead be left at the normal operating voltage.

In this mode, the RB5/KBI1/PGM pin is dedicated to the

programming function and ceases to be a general pur-

pose I/O pin. During programming, VDD is applied to the

RG5/MCLR/VPP pin. To enter Programming mode, VDD

must be applied to the RB5/KBI1/PGM pin, provided the

LVP bit is set. The LVP bit defaults to a ‘1’ from the

factory.

It should be noted that once the LVP bit is programmed

to ‘0’, only the High-Voltage Programming mode is

available and only High-Voltage Programming mode

can be used to program the device.

When using low-voltage ICSP, the part must be sup-

plied 4.5V to 5.5V if a bulk erase will be executed. This

includes reprogramming of the code-protect bits from

an on-state to an off-state. For all other cases of low-

voltage ICSP, the part may be programmed at the

normal operating voltage. This means unique user IDs

or user code can be reprogrammed or added.

Note 1: The High-Voltage Programming mode is

always available regardless of the state of

the LVP bit, by applying VIHH to the MCLR

pin.

2: While in Low-Voltage ICSP mode, the

RB5 pin can no longer be used as a

general purpose I/O pin and should be

held low during normal operation.

3: When using Low-Voltage ICSP Program-

ming (LVP) and the pull-ups on PORTB

are enabled, bit 5 in the TRISB register

must be cleared to disable the pull-up on

RB5 and ensure the proper operation of

the device.

4: If the device Master Clear is disabled,

verify that either of the following is done to

ensure proper entry into ICSP mode:

a) disable Low-Voltage Programming

(CONFIG4L<2> = 0); or

b) make certain that RB5/KBI1/PGM is

held low during entry into ICSP.

 2004 Microchip Technology Inc.

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NOTES:

DS30491C-page 364

 2004 Microchip Technology Inc.

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The literal instructions may use some of the following

operands:

25.0 INSTRUCTION SET SUMMARY

The PIC18 instruction set adds many enhancements to

the previous PICmicro instruction sets, while maintain-

ing an easy migration from these PICmicro instruction

sets.

• A literal value to be loaded into a file register

(specified by ‘k’)

• The desired FSR register to load the literal value

into (specified by ‘f’)

Most instructions are a single program memory word

(16 bits) but there are three instructions that require two

program memory locations.

• No operand required (specified by ‘—’)

The control instructions may use some of the following

operands:

Each single-word instruction is a 16-bit word divided

into an opcode, which specifies the instruction type and

one or more operands, which further specify the

operation of the instruction.

• A program memory address (specified by ‘n’)

• The mode of the call or return instructions

(specified by ‘s’)

• The mode of the table read and table write

instructions (specified by ‘m’)

The instruction set is highly orthogonal and is grouped

into four basic categories:

• No operand required (specified by ‘—’)

• Byte-oriented operations

• Bit-oriented operations

• Literal operations

All instructions are a single word except for three

double-word instructions. These three instructions

were made double-word instructions so that all the

required information is available in these 32 bits. In the

second word, the 4 MSbs are ‘1’s. If this second word

is executed as an instruction (by itself), it will execute

as a NOP.

• Control operations

The PIC18 instruction set summary in Table 25-2 lists

byte-oriented, bit-oriented, literal and control

operations. Table 25-1 shows the opcode field

descriptions.

All single-word instructions are executed in a single

instruction cycle unless a conditional test is true or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles with the additional instruction cycle(s) executed

as a NOP.

Most byte-oriented instructions have three operands:

1. The file register (specified by ‘f’)

2. The destination of the result (specified by ‘d’)

3. The accessed memory (specified by ‘a’)

The file register designator ‘f’ specifies which file

register is to be used by the instruction.

The double-word instructions execute in two instruction

cycles.

The destination designator ‘d’ specifies where the

result of the operation is to be placed. If ‘d’ is zero, the

result is placed in the WREG register. If ‘d’ is one, the

result is placed in the file register specified in the

instruction.

One instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1 µs. If a conditional test is

true or the program counter is changed as a result of an

instruction, the instruction execution time is 2 µs.

Two-word branch instructions (if true) would take 3 µs.

All bit-oriented instructions have three operands:

1. The file register (specified by ‘f’)

Figure 25-1 shows the general formats that the

instructions can have.

2. The bit in the file register (specified by ‘b’)

3. The accessed memory (specified by ‘a’)

All examples use the format ‘nnh’ to represent a hexa-

decimal number, where ‘h’ signifies a hexadecimal

digit.

The bit field designator ‘b’ selects the number of the bit

affected by the operation, while the file register desig-

nator ‘f’ represents the number of the file in which the

bit is located.

The Instruction Set Summary, shown in Table 25-2,

lists the instructions recognized by the Microchip

Assembler (MPASM^TM).

Section 25.1 “Instruction Set” provides a description

of each instruction.

 2004 Microchip Technology Inc.

DS30491C-page 365

PIC18F6585/8585/6680/8680

TABLE 25-1: OPCODE FIELD DESCRIPTIONS

Field

Description

a

RAM access bit

a = 0: RAM location in Access RAM (BSR register is ignored)

a = 1: RAM bank is specified by BSR register

bbb

BSR

d

Bit address within an 8-bit file register (0 to 7).

Bank Select Register. Used to select the current RAM bank.

Destination select bit

d = 0: store result in WREG

d = 1: store result in file register f

dest

f

Destination either the WREG register or the specified register file location.

8-bit register file address (0x00 to 0xFF).

fs

12-bit register file address (0x000 to 0xFFF). This is the source address.

12-bit register file address (0x000 to 0xFFF). This is the destination address.

Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).

Label name.

fd

k

label

mm

The mode of the TBLPTR register for the table read and table write instructions.

Only used with table read and table write instructions:

*

No change to register (such as TBLPTR with table reads and writes).

Post-Increment register (such as TBLPTR with table reads and writes).

Post-Decrement register (such as TBLPTR with table reads and writes).

Pre-Increment register (such as TBLPTR with table reads and writes).

*+

*-

+*

n

The relative address (2’s complement number) for relative branch instructions, or the direct address for

call/branch and return instructions.

PRODH

PRODL

s

Product of Multiply High Byte.

Product of Multiply Low Byte.

Fast Call/Return mode select bit

s = 0: do not update into/from shadow registers

s = 1: certain registers loaded into/from shadow registers (Fast mode)

u

Unused or unchanged.

WREG

x

Working register (accumulator).

Don’t care (0 or 1).

The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all

Microchip software tools.

TBLPTR

TABLAT

TOS

21-bit Table Pointer (points to a program memory location).

8-bit Table Latch.

Top-of-Stack.

PC

Program Counter.

PCL

Program Counter Low Byte.

Program Counter High Byte.

Program Counter High Byte Latch.

Program Counter Upper Byte Latch.

Global Interrupt Enable bit.

Watchdog Timer.

PCH

PCLATH

PCLATU

GIE

WDT

TO

Time-out bit.

PD

Power-down bit.

C, DC, Z, OV, N

ALU status bits: Carry, Digit Carry, Zero, Overflow, Negative.

Optional.

[

]

)

(

Contents.

→

< >

∈

Assigned to.

Register bit field.

In the set of.

italics

User defined term (font is courier).

DS30491C-page 366

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 25-1:

GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

15 10

OPCODE f (FILE #)

Example Instruction

9

8

7

0

ADDWF MYREG, W, B

d

a

d = 0for result destination to be WREG register

d = 1for result destination to be file register (f)

a = 0to force Access Bank

a = 1for BSR to select bank

f = 8-bit file register address

Byte to Byte move operations (2-word)

15

12 11

0

OPCODE

f (Source FILE #)

MOVFF MYREG1, MYREG2

15

12 11

1111

f (Destination FILE #)

f = 12-bit file register address

Bit-oriented file register operations

15 12 11 9 8

OPCODE b (BIT #)

7

0

BSF MYREG, bit, B

a

f (FILE #)

b = 3-bit position of bit in file register (f)

a = 0to force Access Bank

a = 1for BSR to select bank

f = 8-bit file register address

Literal operations

15

8

7

0

MOVLW 0x7F

OPCODE

k (literal)

k = 8-bit immediate value

Control operations

CALL, GOTO and Branch operations

15

8 7

0

GOTO Label

OPCODE

12 11

n<7:0> (literal)

15

0

1111

n<19:8> (literal)

n = 20-bit immediate value

15

8

7

0

CALL MYFUNC

OPCODE

12 11

n<7:0> (literal)

S

0

n<19:8> (literal)

S = Fast bit

11 10

15

0

BRA MYFUNC

BC MYFUNC

OPCODE

n<10:0> (literal)

15

OPCODE

8 7

n<7:0> (literal)

 2004 Microchip Technology Inc.

DS30491C-page 367

PIC18F6585/8585/6680/8680

TABLE 25-2: PIC18FXXX INSTRUCTION SET

16-Bit Instruction Word

MSb LSb

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d, a Add WREG and f

ADDWFC f, d, a Add WREG and Carry bit to f

ANDWF f, d, a AND WREG with f

1

0010 01da ffff ffff C, DC, Z, OV, N 1, 2

0010 00da ffff ffff C, DC, Z, OV, N 1, 2

1

0001 01da ffff ffff Z, N

0110 101a ffff ffff Z

0001 11da ffff ffff Z, N

1,2

2

1, 2

4

CLRF

f, a

Clear f

COMF

f, d, a Complement f

CPFSEQ f, a

CPFSGT f, a

CPFSLT f, a

Compare f with WREG, Skip =

Compare f with WREG, Skip >

Compare f with WREG, Skip <

1 (2 or 3) 0110 001a ffff ffff None

1 (2 or 3) 0110 010a ffff ffff None

1 (2 or 3) 0110 000a ffff ffff None

4

1, 2

DECF

f, d, a Decrement f

1

0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4

DECFSZ f, d, a Decrement f, Skip if 0

DCFSNZ f, d, a Decrement f, Skip if Not 0

1 (2 or 3) 0010 11da ffff ffff None

1 (2 or 3) 0100 11da ffff ffff None

1, 2, 3, 4

1, 2

INCF

f, d, a Increment f

1

0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4

INCFSZ f, d, a Increment f, Skip if 0

INFSNZ f, d, a Increment f, Skip if Not 0

1 (2 or 3) 0011 11da ffff ffff None

1 (2 or 3) 0100 10da ffff ffff None

4

1, 2

1

IORWF

MOVF

f, d, a Inclusive OR WREG with f

f, d, a Move f

1

2

0001 00da ffff ffff Z, N

0101 00da ffff ffff Z, N

1100 ffff ffff ffff None

1111 ffff ffff ffff

MOVFF f_s, f_dMove f_s(source) to 1st word

f_d(destination) 2nd word

MOVWF f, a

MULWF f, a

Move WREG to f

Multiply WREG with f

Negate f

1

0110 111a ffff ffff None

0000 001a ffff ffff None

0110 110a ffff ffff C, DC, Z, OV, N 1, 2

0011 01da ffff ffff C, Z, N

0100 01da ffff ffff Z, N

0011 00da ffff ffff C, Z, N

0100 00da ffff ffff Z, N

0110 100a ffff ffff None

NEGF

RLCF

RLNCF

RRCF

f, a

f, d, a Rotate Left f through Carry

f, d, a Rotate Left f (No Carry)

f, d, a Rotate Right f through Carry

1, 2

RRNCF f, d, a Rotate Right f (No Carry)

SETF f, a Set f

SUBFWB f, d, a Subtract f from WREG with

borrow

0101 01da ffff ffff C, DC, Z, OV, N 1, 2

SUBWF f, d, a Subtract WREG from f

SUBWFB f, d, a Subtract WREG from f with

borrow

1

0101 11da ffff ffff C, DC, Z, OV, N

0101 10da ffff ffff C, DC, Z, OV, N 1, 2

SWAPF f, d, a Swap nibbles in f

1

0011 10da ffff ffff None

4

TSTFSZ f, a

Test f, Skip if 0

1 (2 or 3) 0110 011a ffff ffff None

1, 2

XORWF f, d, a Exclusive OR WREG with f

1

0001 10da ffff ffff Z, N

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

BTG

f, b, a Bit Clear f

f, b, a Bit Set f

f, b, a Bit Test f, Skip if Clear

f, b, a Bit Test f, Skip if Set

f, d, a Bit Toggle f

1

1001 bbba ffff ffff None

1000 bbba ffff ffff None

1, 2

3, 4

1, 2

1 (2 or 3) 1011 bbba ffff ffff None

1 (2 or 3) 1010 bbba ffff ffff None

1

0111 bbba ffff ffff None

Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that

value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is

driven low by an external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The

second cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP

unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that

all program memory locations have a valid instruction.

5: If the table write starts the write cycle to internal memory, the write will continue until terminated.

DS30491C-page 368

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED)

16-Bit Instruction Word

MSb LSb

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

CONTROL OPERATIONS

BC

BN

n

Branch if Carry

1 (2)

2

1110 0010 nnnn nnnn None

1110 0110 nnnn nnnn None

1110 0011 nnnn nnnn None

1110 0111 nnnn nnnn None

1110 0101 nnnn nnnn None

1110 0001 nnnn nnnn None

1110 0100 nnnn nnnn None

1101 0nnn nnnn nnnn None

1110 0000 nnnn nnnn None

1110 110s kkkk kkkk None

1111 kkkk kkkk kkkk

Branch if Negative

Branch if Not Carry

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

Branch if Overflow

Branch Unconditionally

Branch if Zero

BNC

BNN

BNOV

BNZ

BOV

BRA

BZ

n

n, s

1 (2)

2

CALL

Call subroutine 1st word

2nd word

CLRWDT —

Clear Watchdog Timer

Decimal Adjust WREG

Go to address 1st word

2nd word

1

2

0000 0000 0000 0100 TO, PD

0000 0000 0000 0111 C

1110 1111 kkkk kkkk None

1111 kkkk kkkk kkkk

DAW

—

n

GOTO

NOP

POP

PUSH

RCALL

RESET

RETFIE

—

n

No Operation

1

2

1

2

0000 0000 0000 0000 None

1111 xxxx xxxx xxxx None

0000 0000 0000 0110 None

0000 0000 0000 0101 None

1101 1nnn nnnn nnnn None

0000 0000 1111 1111 All

0000 0000 0001 000s GIE/GIEH,

PEIE/GIEL

4

Pop top of return stack (TOS)

Push top of return stack (TOS)

Relative Call

Software device Reset

Return from interrupt enable

s

k

RETLW

RETURN s

SLEEP

Return with literal in WREG

Return from Subroutine

Go into Standby mode

2

1

0000 1100 kkkk kkkk None

0000 0000 0001 001s None

0000 0000 0000 0011 TO, PD

—

Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that

value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is

driven low by an external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The

second cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP

unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that

all program memory locations have a valid instruction.

5: If the table write starts the write cycle to internal memory, the write will continue until terminated.

 2004 Microchip Technology Inc.

DS30491C-page 369

PIC18F6585/8585/6680/8680

TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED)

16-Bit Instruction Word

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

LFSR

k

f, k

Add literal and WREG

1

0000 1111 kkkk

0000 1011 kkkk

0000 1001 kkkk

1110 1110 00ff

1111 0000 kkkk

0000 0001 0000

0000 1110 kkkk

0000 1101 kkkk

0000 1100 kkkk

0000 1000 kkkk

0000 1010 kkkk

kkkk C, DC, Z, OV, N

kkkk Z, N

kkkk None

kkkk

kkkk None

kkkk C, DC, Z, OV, N

kkkk Z, N

AND literal with WREG

Inclusive OR literal with WREG

Move literal (12-bit) 2nd word

to FSRx 1st word

Move literal to BSR<3:0>

Move literal to WREG

Multiply literal with WREG

Return with literal in WREG

Subtract WREG from literal

1

2

MOVLB

MOVLW

MULLW

RETLW

SUBLW

XORLW

k

1

2

1

Exclusive OR literal with WREG 1

DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS

TBLRD*

Table Read

2

0000 0000 0000

1000 None

1001 None

1010 None

1011 None

1100 None

1101 None

1110 None

1111 None

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

Table Read with post-increment

Table Read with post-decrement

Table Read with pre-increment

Table Write

Table Write with post-increment

Table Write with post-decrement

Table Write with pre-increment

2 (5)

Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that

value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is

driven low by an external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The

second cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP

unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that

all program memory locations have a valid instruction.

5: If the table write starts the write cycle to internal memory, the write will continue until terminated.

DS30491C-page 370

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

25.1 Instruction Set

ADDLW

ADD literal to W

ADDWF

ADD W to f

Syntax:

[ label ] ADDLW

0 ≤ k ≤ 255

k

Syntax:

[ label ] ADDWF

f [,d [,a] f [,d [,a]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(W) + k → W

N, OV, C, DC, Z

Operation:

(W) + (f) → dest

0000

1111

kkkk

Status Affected:

Encoding:

N, OV, C, DC, Z

Description:

The contents of W are added to the

8-bit literal ‘k’ and the result is

placed in W.

0010

01da

ffff

Description:

Add W to register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘d’

(default). If ‘a’ is ‘0’, the Access

Bank will be selected. If ‘a’ is ‘1’,

the BSR is used.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to W

Words:

Cycles:

1

Q Cycle Activity:

Q1

ADDLW

0x15

Example:

Q2

Q3

Q4

Before Instruction

Decode

Read

register ‘f’

Process

Data

Write to

destination

W

=

0x10

After Instruction

W

=

0x25

ADDWF

REG, 0, 0

Example:

Before Instruction

W

REG

=

0x17

0xC2

After Instruction

W

REG

=

0xD9

0xC2

 2004 Microchip Technology Inc.

DS30491C-page 371

PIC18F6585/8585/6680/8680

ADDWFC

ADD W and Carry bit to f

ANDLW

AND literal with W

Syntax:

[ label ] ADDWFC

f [,d [,a]]

Syntax:

[ label ] ANDLW

0 ≤ k ≤ 255

k

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

Operation:

Status Affected:

Encoding:

(W) .AND. k → W

N, Z

Operation:

(W) + (f) + (C) → dest

0000

1011

kkkk

Status Affected:

Encoding:

N,OV, C, DC, Z

Description:

The contents of W are ANDed with

the 8-bit literal ‘k’. The result is

placed in W.

0010

00da

ffff

Description:

Add W, the Carry Flag and data

memory location ‘f’. If ‘d’ is ‘0’, the

result is placed in W. If ‘d’ is ‘1’, the

result is placed in data memory loca-

tion ‘f’. If ‘a’ is ‘0’, the Access Bank

will be selected. If ‘a’ is ‘1’, the BSR

will not be overridden.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal

‘k’

Process

Data

Write to W

Words:

Cycles:

1

ANDLW

0x5F

Example:

Q Cycle Activity:

Q1

Before Instruction

Q2

Q3

Q4

W

=

0xA3

Decode

Read

register ‘f’

Process

Data

Write to

destination

After Instruction

W

=

0x03

ADDWFC

REG, 0, 1

Example:

Before Instruction

Carry bit =

1

REG

W

=

0x02

0x4D

After Instruction

Carry bit =

0

0x02

REG

=

W

=

0x50

DS30491C-page 372

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

ANDWF

AND W with f

BC

Branch if Carry

[ label ] BC

Syntax:

[ label ] ANDWF

f [,d [,a]]

Syntax:

n

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

Operation:

-128 ≤ n ≤ 127

if carry bit is ‘1’

(PC) + 2 + 2n → PC

Operation:

(W) .AND. (f) → dest

Status Affected:

Encoding:

None

Status Affected:

Encoding:

N, Z

1110

0010

nnnn

0001

01da

ffff

Description:

If the Carry bit is ‘1’, then the

Description:

The contents of W are AND’ed with

register ‘f’. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank will be

selected. If ‘a’ is ‘1’, the BSR will

not be overridden (default).

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

Q1

Q Cycle Activity:

If Jump:

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Decode

Read literal

‘n’

Process

Data

Write to PC

No

operation

No

operation

No

operation

No

operation

ANDWF

REG, 0, 0

Example:

Before Instruction

If No Jump:

Q1

W

REG

=

0x17

0xC2

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

No

operation

After Instruction

W

REG

=

0x02

0xC2

HERE

BC

5

Example:

Before Instruction

PC

=

address (HERE)

After Instruction

If Carry

=

1;

PC

address (HERE+12)

0;

If Carry

PC

address (HERE+2)

 2004 Microchip Technology Inc.

DS30491C-page 373

PIC18F6585/8585/6680/8680

BCF

Bit Clear f

BN

Branch if Negative

[ label ] BN

Syntax:

[ label ] BCF f,b[,a]

Syntax:

n

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operands:

Operation:

-128 ≤ n ≤ 127

if negative bit is ‘1’

(PC) + 2 + 2n → PC

Operation:

0 → f

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0110

nnnn

1001

bbba

ffff

Description:

If the Negative bit is ‘1’, then the

program will branch.

Description:

Bit ‘b’ in register ‘f’ is cleared. If ‘a’

is ‘0’, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

Q1

Q Cycle Activity:

If Jump:

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write

Q1

Q2

Q3

Q4

register ‘f’

Decode

Read literal

‘n’

Process

Data

Write to PC

BCF

FLAG_REG, 7, 0

Example:

No

operation

No

operation

No

operation

No

operation

Before Instruction

FLAG_REG = 0xC7

If No Jump:

Q1

After Instruction

Q2

Q3

Q4

FLAG_REG = 0x47

Decode

Read literal

‘n’

Process

Data

No

operation

HERE

BN Jump

Example:

Before Instruction

PC

=

address (HERE)

After Instruction

If Negative = 1;

PC address (Jump)

If Negative = 0;

PC address (HERE+2)

=

DS30491C-page 374

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

BNC

Branch if Not Carry

BNN

Branch if Not Negative

Syntax:

[ label ] BNC

-128 ≤ n ≤ 127

if carry bit is ‘0’

n

Syntax:

[ label ] BNN

-128 ≤ n ≤ 127

n

Operands:

Operation:

Operands:

Operation:

if negative bit is ‘0’

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0011

nnnn

1110

0111

nnnn

Description:

If the Carry bit is ‘0’, then the

program will branch.

Description:

If the Negative bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Decode

Read literal

‘n’

Process

Data

Write to PC

No

operation

If No Jump:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

No

operation

Decode

Read literal

‘n’

Process

Data

No

operation

HERE

BNC Jump

HERE

BNN Jump

Example:

Before Instruction

PC

=

address (HERE)

0;

address (Jump)

1;

address (HERE+2)

PC

=

address (HERE)

After Instruction

If Carry

PC

If Carry

PC

=

If Negative

PC

If Negative

PC

=

0;

address (Jump)

1;

address (HERE+2)

 2004 Microchip Technology Inc.

DS30491C-page 375

PIC18F6585/8585/6680/8680

BNOV

Branch if Not Overflow

BNZ

Branch if Not Zero

Syntax:

[ label ] BNOV

-128 ≤ n ≤ 127

n

Syntax:

[ label ] BNZ

-128 ≤ n ≤ 127

if zero bit is ‘0’

n

Operands:

Operation:

Operands:

Operation:

if overflow bit is ‘0’

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0101

nnnn

1110

0001

nnnn

Description:

If the Overflow bit is ‘0’, then the

program will branch.

Description:

If the Zero bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Decode

Read literal

‘n’

Process

Data

Write to PC

No

operation

If No Jump:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

No

operation

Decode

Read literal

‘n’

Process

Data

No

operation

HERE

BNOV Jump

HERE

BNZ Jump

Example:

Before Instruction

PC

=

address (HERE)

PC

=

address (HERE)

0;

address (Jump)

1;

address (HERE+2)

After Instruction

If Overflow

PC

If Overflow

PC

=

0;

If Zero

PC

If Zero

PC

=

address (Jump)

1;

address (HERE+2)

DS30491C-page 376

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

BRA

Unconditional Branch

[ label ] BRA

BSF

Bit Set f

Syntax:

n

Syntax:

[ label ] BSF f,b[,a]

Operands:

Operation:

Status Affected:

Encoding:

-1024 ≤ n ≤ 1023

(PC) + 2 + 2n → PC

None

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation:

1 → f

1101

0nnn

nnnn

Status Affected:

Encoding:

None

Description:

Add the 2’s complement number

‘2n’ to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is a

two-cycle instruction.

1000

bbba

ffff

Description:

Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’,

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value.

Words:

Cycles:

1

2

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

No

operation

BSF

FLAG_REG, 7, 1

Example:

Before Instruction

HERE

BRA Jump

Example:

FLAG_REG

=

0x0A

0x8A

Before Instruction

After Instruction

FLAG_REG

PC

=

address (HERE)

address (Jump)

After Instruction

PC

=

 2004 Microchip Technology Inc.

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PIC18F6585/8585/6680/8680

BTFSC

Bit Test File, Skip if Clear

BTFSS

Bit Test File, Skip if Set

Syntax:

[ label ] BTFSC f,b[,a]

Syntax:

[ label ] BTFSS f,b[,a]

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

0 ≤ b < 7

a ∈ [0,1]

Operation:

skip if (f) = 0

Operation:

skip if (f) = 1

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1011

bbba

ffff

1010

bbba

ffff

Description:

If bit ‘b’ in register ‘f’ is ‘0’, then the

next instruction is skipped.

Description:

If bit ‘b’ in register ‘f’ is ‘1’, then the

next instruction is skipped.

If bit ‘b’ is ‘0’, then the next

If bit ‘b’ is ‘1’, then the next

instruction fetched during the current

instruction execution is discarded

and a NOPis executed instead,

making this a two-cycle instruction. If

‘a’ is ‘0’, the Access Bank will be

selected, overriding the BSR value. If

‘a’ = 1, then the bank will be selected

as per the BSR value (default).

instruction fetched during the

current instruction execution is

discarded and a NOPis executed

instead, making this a two-cycle

instruction. If ‘a’ is ‘0’, the Access

Bank will be selected, overriding the

BSR value. If ‘a’ = 1, then the bank

will be selected as per the BSR value

(default).

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

No

operation

Decode

Read

Process

Data

No

operation

register ‘f’

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

HERE

FALSE

TRUE

BTFSC

:

FLAG, 1, 0

Example:

HERE

FALSE

TRUE

BTFSS

:

FLAG, 1, 0

Example:

Before Instruction

PC

=

address (HERE)

Before Instruction

PC

=

address (HERE)

After Instruction

If FLAG<1>

=

0;

After Instruction

PC

address (TRUE)

1;

If FLAG<1>

=

0;

If FLAG<1>

PC

address (FALSE)

1;

address (FALSE)

If FLAG<1>

PC

address (TRUE)

DS30491C-page 378

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

BTG

Bit Toggle f

BOV

Branch if Overflow

Syntax:

[ label ] BTG f,b[,a]

Syntax:

[ label ] BOV

-128 ≤ n ≤ 127

n

Operands:

0 ≤ f ≤ 255

0 ≤ b < 7

a ∈ [0,1]

Operands:

Operation:

if overflow bit is ‘1’

(PC) + 2 + 2n → PC

Operation:

(f) → f

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0100

nnnn

0111

bbba

ffff

Description:

If the Overflow bit is ‘1’, then the

program will branch.

Description:

Bit ‘b’ in data memory location ‘f’ is

inverted. If ‘a’ is ‘0’, the Access Bank

will be selected, overriding the BSR

value. If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

Q1

Q Cycle Activity:

If Jump:

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write

Q1

Q2

Q3

Q4

register ‘f’

Decode

Read literal

‘n’

Process

Data

Write to PC

BTG

PORTC, 4, 0

Example:

No

operation

No

operation

No

operation

No

operation

Before Instruction:

PORTC

=

0111 0101 [0x75]

If No Jump:

Q1

After Instruction:

Q2

Q3

Q4

PORTC

=

0110 0101 [0x65]

Decode

Read literal

‘n’

Process

Data

No

operation

HERE

BOV Jump

Example:

Before Instruction

PC

=

address (HERE)

After Instruction

If Overflow

=

1;

PC

address (Jump)

If Overflow

PC

0;

address (HERE+2)

 2004 Microchip Technology Inc.

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PIC18F6585/8585/6680/8680

BZ

Branch if Zero

[ label ] BZ

CALL

Subroutine Call

Syntax:

n

Syntax:

[ label ] CALL k [,s]

Operands:

Operation:

-128 ≤ n ≤ 127

Operands:

0 ≤ k ≤ 1048575

s ∈ [0,1]

if Zero bit is ‘1’

(PC) + 2 + 2n → PC

Operation:

(PC) + 4 → TOS,

k → PC<20:1>,

if s = 1

Status Affected:

Encoding:

None

1110

0000

nnnn

(W) → WS,

(STATUS) → STATUSS,

(BSR) → BSRS

Description:

If the Zero bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Status Affected:

None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

1110

1111

110s

k kkk

kkkk

7

0

8

k

kkk kkkk

19

Description:

Subroutine call of entire 2-Mbyte

memory range. First, return

address (PC+ 4) is pushed onto the

return stack. If ‘s’ = 1, the W,

Status and BSR registers are also

pushed into their respective

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

shadow registers, WS, STATUSS

and BSRS. If ‘s’ = 0, no update

occurs (default). Then, the 20-bit

value ‘k’ is loaded into PC<20:1>.

CALLis a two-cycle instruction.

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

No

operation

No

operation

No

operation

No

operation

Words:

Cycles:

2

If No Jump:

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

No

operation

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal Push PC to Read literal

HERE

BZ Jump

Example:

‘k’<7:0>,

stack

‘k’<19:8>,

Write to PC

Before Instruction

PC

=

address (HERE)

1;

address (Jump)

0;

address (HERE+2)

No

operation

No

operation

No

operation

No

operation

After Instruction

If Zero

PC

If Zero

PC

=

HERE

CALL THERE,1

Example:

Before Instruction

PC

=

address (HERE)

After Instruction

PC

=

address (THERE)

TOS

=

address (HERE + 4)

WS

BSRS

STATUSS

W

BSR

STATUS

DS30491C-page 380

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

CLRF

Clear f

CLRWDT

Clear Watchdog Timer

Syntax:

[ label ] CLRF f [,a]

Syntax:

[ label ] CLRWDT

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

Operation:

None

000h → WDT,

000h → WDT postscaler,

1 → TO,

Operation:

000h → f

1 → Z

1 → PD

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

TO, PD

0110

101a

ffff

0000

0100

Description:

Clears the contents of the specified

register. If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

Description:

CLRWDTinstruction resets the

Watchdog Timer. It also resets the

postscaler of the WDT. Status bits

TO and PD are set.

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

No

operation

Process

Data

No

operation

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

CLRWDT

Example:

CLRF

FLAG_REG,1

Example:

Before Instruction

WDT Counter

=

?

Before Instruction

FLAG_REG

=

0x5A

0x00

After Instruction

WDT Counter

WDT Postscaler

TO

PD

=

0x00

After Instruction

FLAG_REG

0

1

 2004 Microchip Technology Inc.

DS30491C-page 381

PIC18F6585/8585/6680/8680

COMF

Complement f

CPFSEQ

Compare f with W, skip if f = W

Syntax:

[ label ] COMF f [,d [,a]]

Syntax:

[ label ] CPFSEQ f [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

(f) – (W),

Operation:

(f) → dest

skip if (f) = (W)

(unsigned comparison)

Status Affected:

Encoding:

N, Z

Status Affected:

Encoding:

None

0001

11da

ffff

0110

001a

ffff

Description:

The contents of register ‘f’ are com-

plemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

Description:

Compares the contents of data

memory location ‘f’ to the contents

of W by performing an unsigned

subtraction.

If ‘f’ = W, then the fetched

instruction is discarded and a NOP

is executed instead, making this a

two-cycle instruction. If ‘a’ is ‘0’, the

Access Bank will be selected,

overriding the BSR value. If ‘a’ = 1,

then the bank will be selected as

per the BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Words:

Cycles:

1

Decode

Read

register ‘f’

Process

Data

Write to

1(2)

destination

Note: 3 cycles if skip and followed

by a 2-word instruction.

COMF

REG, 0, 0

Example:

Q Cycle Activity:

Q1

Before Instruction

Q2

Q3

Q4

REG

=

0x13

Decode

Read

register ‘f’

Process

Data

No

operation

After Instruction

REG

=

0x13

W

=

0xEC

If skip:

Q1

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No

operation

No

operation

HERE

CPFSEQ REG, 0

Example:

NEQUAL

EQUAL

:

Before Instruction

PC Address

=

HERE

W

REG

=

?

After Instruction

If REG

PC

=

W;

Address (EQUAL)

If REG

PC

≠

=

W;

Address (NEQUAL)

DS30491C-page 382

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

CPFSGT

Compare f with W, skip if f > W

CPFSLT

Compare f with W, skip if f < W

Syntax:

[ label ] CPFSGT f [,a]

Syntax:

[ label ] CPFSLT f [,a]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

(f) − (W),

Operation:

(f) – (W),

skip if (f) > (W)

(unsigned comparison)

skip if (f) < (W)

(unsigned comparison)

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0110

010a

ffff

0110

000a

ffff

Description:

Compares the contents of data

memory location ‘f’ to the contents

of the W by performing an

Description:

Compares the contents of data

memory location ‘f’ to the contents

of W by performing an unsigned

subtraction.

unsigned subtraction.

If the contents of ‘f’ are greater than

the contents of WREG, then the

fetched instruction is discarded and

a NOPis executed instead, making

this a two-cycle instruction. If ‘a’ is

‘0’, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

If the contents of ‘f’ are less than

the contents of W, then the fetched

instruction is discarded and a NOP

is executed instead, making this a

two-cycle instruction. If ‘a’ is ‘0’, the

Access Bank will be selected. If ’a’

is ‘1’, the BSR will not be overrid-

den (default).

Words:

Cycles:

1

1(2)

Words:

Cycles:

1

Note: 3 cycles if skip and followed

by a 2-word instruction.

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

Read

register ‘f’

Process

Data

No

operation

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

No

operation

If skip:

Q1

Q2

Q3

Q4

If skip:

Q1

No

operation

No

operation

No

operation

No

operation

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

If skip and followed by 2-word instruction:

No

Q1

Q2

Q3

Q4

operation

No

operation

No

operation

HERE

NLESS

LESS

CPFSLT REG, 1

:

Example:

HERE

CPFSGT REG, 0

Example:

NGREATER

GREATER

:

Before Instruction

PC

W

=

Address (HERE)

?

Before Instruction

After Instruction

PC

=

Address (HERE)

W

=

?

If REG

PC

If REG

PC

<

=

≥

=

W;

Address (LESS)

W;

Address (NLESS)

After Instruction

If REG

PC

>

=

W;

Address (GREATER)

If REG

PC

≤

=

W;

Address (NGREATER)

 2004 Microchip Technology Inc.

DS30491C-page 383

PIC18F6585/8585/6680/8680

DAW

Decimal Adjust W Register

DECF

Decrement f

Syntax:

[ label ] DAW

Syntax:

[ label ] DECF f [,d [,a]]

Operands:

Operation:

None

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

If [W<3:0> >9] or [DC = 1] then

(W<3:0>) + 6 → W<3:0>;

else

(W<3:0>) → W<3:0>;

Operation:

(f) – 1 → dest

Status Affected:

Encoding:

C, DC, N, OV, Z

0000

01da

ffff

If [W<7:4> >9] or [C = 1] then

(W<7:4>) + 6 → W<7:4>;

else

Description:

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in W. If ‘d’ is ‘1’,

the result is stored back in register

‘f’ (default). If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

(W<7:4>) → W<7:4>;

Status Affected:

Encoding:

C

0000

0111

Description:

DAW adjusts the eight-bit value in

W, resulting from the earlier

addition of two variables (each in

packed BCD format) and produces

a correct packed BCD result.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register W

Process

Data

Write

W

DECF

CNT,

1, 0

Example:

Before Instruction

CNT

Z

=

0x01

0

DAW

Example1:

After Instruction

Before Instruction

CNT

=

0x00

1

W

=

0xA5

Z

C

DC

=

0

After Instruction

W

=

0x05

C

DC

=

1

0

Example 2:

Before Instruction

W

=

0xCE

C

DC

=

0

After Instruction

W

=

0x34

C

DC

=

1

0

DS30491C-page 384

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

DECFSZ

Decrement f, skip if 0

DCFSNZ

Decrement f, skip if not 0

Syntax:

[ label ] DECFSZ f [,d [,a]]

Syntax:

[ label ] DCFSNZ f [,d [,a]]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) – 1 → dest,

skip if result = 0

Operation:

(f) – 1 → dest,

skip if result ≠ 0

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0010

11da

ffff

0100

11da

ffff

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result

is placed back in register ‘f’

(default).

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result

is placed back in register ‘f’

(default).

If the result is ‘0’, the next

If the result is not ‘0’, the next

instruction which is already fetched

is discarded and a NOPis executed

instead, making it a two-cycle

instruction. If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

instruction which is already fetched

is discarded and a NOPis executed

instead, making it a two-cycle

instruction. If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Decode

Read

register ‘f’

Process

Data

Write to

destination

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

HERE

DECFSZ

GOTO

CNT, 1, 1

LOOP

HERE

ZERO

NZERO

DCFSNZ TEMP, 1, 0

:

Example:

CONTINUE

Before Instruction

TEMP

PC

=

Address (HERE)

=

?

After Instruction

CNT

If CNT

PC

If CNT

PC

=

≠

=

CNT - 1

0;

TEMP

If TEMP

PC

If TEMP

PC

=

≠

=

TEMP - 1,

0;

Address (CONTINUE)

0;

Address (ZERO)

0;

Address (NZERO)

Address (HERE+2)

 2004 Microchip Technology Inc.

DS30491C-page 385

PIC18F6585/8585/6680/8680

GOTO

Unconditional Branch

INCF

Increment f

Syntax:

[ label ] GOTO k

0 ≤ k ≤ 1048575

k → PC<20:1>

None

Syntax:

[ label ] INCF f [,d [,a]]

Operands:

Operation:

Status Affected:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) + 1 → dest

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

Status Affected:

Encoding:

C, DC, N, OV, Z

1110

1111

k kkk

kkkk

7

0

8

k

kkk kkkk

0010

10da

ffff

19

Description:

GOTOallows an unconditional

branch anywhere within entire

2-Mbyte memory range. The 20-bit

value ‘k’ is loaded into PC<20:1>.

GOTOis always a two-cycle

instruction.

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result

is placed back in register ‘f’

(default). If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

2

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Q3

Q4

Decode

Read literal

‘k’<7:0>,

No

operation

Read literal

‘k’<19:8>,

Write to PC

Q Cycle Activity:

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

Decode

Read

register ‘f’

Process

Data

Write to

destination

GOTO THERE

Example:

INCF

CNT, 1, 0

Example:

After Instruction

Before Instruction

PC

=

Address (THERE)

CNT

=

0xFF

Z

=

0

?

C

DC

After Instruction

CNT

=

0x00

Z

1

C

DC

DS30491C-page 386

 2004 Microchip Technology Inc.

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INCFSZ

Increment f, skip if 0

INFSNZ

Increment f, skip if not 0

Syntax:

[ label ] INCFSZ f [,d [,a]]

Syntax:

[ label ] INFSNZ f [,d [,a]]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) + 1 → dest,

skip if result = 0

Operation:

(f) + 1 → dest,

skip if result ≠ 0

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0011

11da

ffff

0100

10da

ffff

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result

is placed back in register ‘f’

(default).

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result

is placed back in register ‘f’

(default).

If the result is ‘0’, the next instruc-

tion which is already fetched is

discarded and a NOPis executed

instead, making it a two-cycle

instruction. If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

If the result is not ‘0’, the next

instruction which is already fetched

is discarded and a NOPis executed

instead, making it a two-cycle

instruction. If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Decode

Read

register ‘f’

Process

Data

Write to

destination

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

HERE

NZERO

ZERO

INCFSZ

:

CNT, 1, 0

HERE

ZERO

NZERO

INFSNZ REG, 1, 0

Example:

Before Instruction

PC

=

Address (HERE)

PC

=

Address (HERE)

After Instruction

CNT

If CNT

PC

If CNT

PC

=

≠

=

CNT + 1

REG

If REG

PC

If REG

PC

=

≠

=

REG + 1

0;

Address (NZERO)

0;

Address (ZERO)

0;

Address (ZERO)

0;

Address (NZERO)

 2004 Microchip Technology Inc.

DS30491C-page 387

PIC18F6585/8585/6680/8680

IORLW

Inclusive OR literal with W

IORWF

Inclusive OR W with f

Syntax:

[ label ] IORLW k

0 ≤ k ≤ 255

Syntax:

[ label ] IORWF f [,d [,a]]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(W) .OR. k → W

N, Z

Operation:

(W) .OR. (f) → dest

0000

1001

kkkk

Status Affected:

Encoding:

N, Z

Description:

The contents of W are OR’ed with

the eight-bit literal ‘k’. The result is

placed in W.

0001

00da

ffff

Description:

Inclusive OR W with register ‘f’. If

‘d’ is ‘0’, the result is placed in W. If

‘d’ is ‘1’, the result is placed back in

register ‘f’ (default). If ‘a’ is ‘0’, the

Access Bank will be selected,

overriding the BSR value. If ‘a’ = 1,

then the bank will be selected as

per the BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to W

Words:

Cycles:

1

IORLW

0x35

Example:

Before Instruction

Q Cycle Activity:

Q1

W

=

0x9A

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

After Instruction

W

=

0xBF

IORWF RESULT, 0, 1

Example:

Before Instruction

RESULT =

0x13

0x91

W

=

After Instruction

RESULT =

0x13

0x93

W

=

DS30491C-page 388

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

LFSR

Load FSR

MOVF

Move f

Syntax:

[ label ] LFSR f,k

Syntax:

[ label ] MOVF f [,d [,a]]

Operands:

0 ≤ f ≤ 2

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

0 ≤ k ≤ 4095

Operation:

k → FSRf

Operation:

f → dest

Status Affected:

Encoding:

None

Status Affected:

Encoding:

N, Z

1110

1111

1110

0000

00ff

k kkk

11

kkkk

k kkk

0101

00da

ffff

7

Description:

The 12-bit literal ‘k’ is loaded into

the file select register pointed to

by ‘f’.

Description:

The contents of register ‘f’ are

moved to a destination dependent

upon the status of ‘d’. If ‘d’ is ‘0’, the

result is placed in W. If ‘d’ is ‘1’, the

result is placed back in register ‘f’

(default). Location ‘f’ can be any-

where in the 256-byte bank. If ‘a’ is

‘0’, the Access Bank will be

Words:

Cycles:

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

Decode

Read literal

‘k’ MSB

Process

Data

Write

literal ‘k’

MSB to

FSRfH

Decode

Read literal

‘k’ LSB

Process

Data

Write literal

‘k’ to FSRfL

Words:

Cycles:

1

Q Cycle Activity:

Q1

LFSR 2, 0x3AB

Example:

Q2

Q3

Q4

After Instruction

Decode

Read

register ‘f’

Process

Data

Write W

FSR2H

FSR2L

=

0x03

0xAB

MOVF

REG, 0, 0

Example:

Before Instruction

REG

W

=

0x22

0xFF

After Instruction

REG

W

=

0x22

 2004 Microchip Technology Inc.

DS30491C-page 389

PIC18F6585/8585/6680/8680

MOVFF

Move f to f

MOVLB

Move literal to low nibble in BSR

Syntax:

[ label ] MOVFF f_s,f_d

Syntax:

[ label ] MOVLB k

0 ≤ k ≤ 255

k → BSR

Operands:

0 ≤ f_s≤ 4095

0 ≤ f_d≤ 4095

Operands:

Operation:

Status Affected:

Encoding:

Operation:

(f_s) → f_d

None

Status Affected:

None

0000

0001

kkkk

Encoding:

1st word (source)

2nd word (destin.)

Description:

The 8-bit literal ‘k’ is loaded into

the Bank Select Register (BSR).

1100

1111

ffff

ffff_s

ffff_d

Words:

Cycles:

1

Description:

The contents of source register ‘f_s’

are moved to destination register

‘f_d’. Location of source ‘f_s’ can be

anywhere in the 4096-byte data

space (000h to FFFh) and location

of destination ‘f_d’ can also be

anywhere from 000h to FFFh.

Either source or destination can be

W (a useful special situation).

MOVFFis particularly useful for

transferring a data memory location

to a peripheral register (such as the

transmit buffer or an I/O port).

The MOVFFinstruction cannot use

the PCL, TOSU, TOSH or TOSL as

the destination register

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal

‘k’

Process

Data

Write

literal ‘k’ to

BSR

MOVLB

5

Example:

Before Instruction

BSR register

=

0x02

0x05

After Instruction

BSR register

Words:

Cycles:

2

2 (3)

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

(src)

Process

Data

No

operation

Decode

No

operation

No

operation

Write

register ‘f’

(dest)

No dummy

read

MOVFF

REG1, REG2

Example:

Before Instruction

REG1

REG2

=

0x33

0x11

After Instruction

REG1

REG2

=

0x33,

0x33

DS30491C-page 390

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

MOVLW

Move literal to W

MOVWF

Move W to f

Syntax:

[ label ] MOVLW k

0 ≤ k ≤ 255

k → W

Syntax:

[ label ] MOVWF f [,a]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

(W) → f

None

Status Affected:

Encoding:

None

0000

1110

kkkk

0110

111a

ffff

Description:

The eight-bit literal ‘k’ is loaded into

W.

Description:

Move data from W to register ‘f’.

Location ‘f’ can be anywhere in the

256-byte bank. If ‘a’ is ‘0’, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to W

Words:

Cycles:

1

MOVLW

0x5A

Example:

Q Cycle Activity:

Q1

After Instruction

Q2

Q3

Q4

W

=

0x5A

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

MOVWF

REG, 0

Example:

Before Instruction

W

REG

=

0x4F

0xFF

After Instruction

W

REG

=

0x4F

 2004 Microchip Technology Inc.

DS30491C-page 391

PIC18F6585/8585/6680/8680

MULLW

Multiply Literal with W

MULWF

Multiply W with f

Syntax:

[ label ] MULLW

0 ≤ k ≤ 255

k

Syntax:

[ label ] MULWF f [,a]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

(W) x k → PRODH:PRODL

Operation:

(W) x (f) → PRODH:PRODL

None

Status Affected:

Encoding:

None

0000

1101

kkkk

0000

001a

ffff

Description:

An unsigned multiplication is

carried out between the contents

of W and the 8-bit literal ‘k’. The

16-bit result is placed in

PRODH:PRODL register pair.

PRODH contains the high byte.

W is unchanged.

None of the status flags are

affected.

Note that neither overflow nor

carry is possible in this

Description:’

An unsigned multiplication is

carried out between the contents

of W and the register file location

‘f’. The 16-bit result is stored in

the PRODH:PRODL register

pair. PRODH contains the high

byte.

Both W and ‘f’ are unchanged.

None of the status flags are

affected.

operation. A zero result is

possible but not detected.

Note that neither overflow nor

carry is possible in this

operation. A zero result is

possible but not detected. If ‘a’ is

‘0’, the Access Bank will be

selected, overriding the BSR

value. If ‘a’ = 1, then the bank

will be selected as per the BSR

value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write

registers

PRODH:

PRODL

Words:

Cycles:

1

Q Cycle Activity:

Q1

MULLW

0xC4

Example:

Q2

Q3

Q4

Before Instruction

Decode

Read

register ‘f’

Process

Data

Write

W

PRODH

PRODL

=

0xE2

registers

PRODH:

PRODL

?

After Instruction

W

=

0xE2

0xAD

0x08

MULWF

REG, 1

Example:

PRODH

PRODL

=

Before Instruction

W

=

0xC4

REG

PRODH

PRODL

=

0xB5

?

After Instruction

W

=

0xC4

REG

PRODH

PRODL

=

0xB5

0x8A

0x94

DS30491C-page 392

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

NEGF

Negate f

NOP

No Operation

Syntax:

[ label ] NEGF f [,a]

Syntax:

[ label ] NOP

None

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

Operation:

Status Affected:

Encoding:

No operation

None

Operation:

( f ) + 1 → f

Status Affected:

Encoding:

N, OV, C, DC, Z

0000

1111

0000

xxxx

0000

xxxx

0000

xxxx

0110

110a

ffff

Description:

Words:

No operation.

Description:

Location ‘f’ is negated using two’s

complement. The result is placed in

the data memory location ‘f’. If ‘a’ is

‘0’, the Access Bank will be

1

Cycles:

Q Cycle Activity:

Q1

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value.

Q2

No

Q3

No

Q4

Decode

No

operation

Words:

Cycles:

1

Example:

None.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

NEGF

REG, 1

Example:

Before Instruction

REG

=

0011 1010 [0x3A]

1100 0110 [0xC6]

After Instruction

REG

=

 2004 Microchip Technology Inc.

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PIC18F6585/8585/6680/8680

POP

Pop Top of Return Stack

PUSH

Push Top of Return Stack

Syntax:

[ label ] POP

None

Syntax:

[ label ] PUSH

None

Operands:

Operation:

Status Affected:

Encoding:

Operands:

Operation:

Status Affected:

Encoding:

(TOS) → bit bucket

None

(PC+2) → TOS

None

0000

0110

0000

0101

Description:

The TOS value is pulled off the

return stack and is discarded. The

TOS value then becomes the

previous value that was pushed

onto the return stack.

This instruction is provided to

enable the user to properly manage

the return stack to incorporate a

software stack.

Description:

The PC+2 is pushed onto the top of

the return stack. The previous TOS

value is pushed down on the stack.

This instruction allows implement-

ing a software stack by modifying

TOS, and then pushing it onto the

return stack.

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

PUSH PC+2

onto return

stack

No

operation

No

operation

Q2

Q3

Q4

Decode

No

operation

POP TOS

value

No

operation

PUSH

Example:

POP

GOTO

Example:

Before Instruction

NEW

TOS

PC

=

00345Ah

000124h

Before Instruction

TOS

=

0031A2h

014332h

After Instruction

Stack (1 level down)=

PC

=

000126h

00345Ah

TOS

After Instruction

Stack (1 level down)=

TOS

PC

=

014332h

NEW

DS30491C-page 394

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

RCALL

Relative Call

RESET

Reset

Syntax:

[ label ] RCALL

-1024 ≤ n ≤ 1023

(PC) + 2 → TOS,

n

Syntax:

[ label ] RESET

Operands:

Operation:

Operands:

Operation:

None

Reset all registers and flags that

are affected by a MCLR Reset.

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

All

1101

1nnn

nnnn

0000

1111

Description:

Subroutine call with a jump up to

1K from the current location. First,

return address (PC+2) is pushed

onto the stack. Then, add the 2’s

complement number ‘2n’ to the PC.

Since the PC will have incremented

to fetch the next instruction, the

new address will be PC+2+2n. This

instruction is a two-cycle

Description:

This instruction provides a way to

execute a MCLR Reset in software.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Start

No

Reset

operation

instruction.

Words:

Cycles:

1

2

RESET

Example:

After Instruction

Registers =

Reset Value

Q Cycle Activity:

Q1

Flags*

=

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Push PC to

stack

No

operation

HERE

RCALL

Jump

Example:

Before Instruction

PC

=

Address (HERE)

After Instruction

PC

=

Address (Jump)

Address (HERE+2)

TOS =

 2004 Microchip Technology Inc.

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PIC18F6585/8585/6680/8680

RETFIE

Return from Interrupt

RETLW

Return Literal to W

Syntax:

[ label ] RETFIE [s]

s ∈ [0,1]

Syntax:

[ label ] RETLW k

0 ≤ k ≤ 255

Operands:

Operation:

Operands:

Operation:

(TOS) → PC,

1 → GIE/GIEH or PEIE/GIEL,

if s = 1

k → W,

(TOS) → PC,

PCLATU, PCLATH are unchanged

(WS) → W,

(STATUSS) → STATUS,

(BSRS) → BSR,

Status Affected:

Encoding:

None

0000

1100

kkkk

PCLATU, PCLATH are unchanged.

Description:

W is loaded with the eight-bit literal

‘k’. The program counter is loaded

from the top of the stack (the return

address). The high address latch

(PCLATH) remains unchanged.

Status Affected:

Encoding:

GIE/GIEH, PEIE/GIEL.

0000

0001

000s

Description:

Return from interrupt. Stack is

popped and Top-of-Stack (TOS) is

loaded into the PC. Interrupts are

enabled by setting either the high

or low priority global interrupt

enable bit. If ‘s’ = 1, the contents of

the shadow registers WS,

STATUSS and BSRS are loaded

into their corresponding registers,

W, Status and BSR. If ‘s’ = 0, no

update of these registers occurs

(default).

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Pop PC from

stack, Write

to W

No

operation

Words:

Cycles:

1

2

Example:

CALL TABLE ; W contains table

; offset value

Q Cycle Activity:

Q1

Q2

Q3

Q4

; W now has

; table value

Decode

No

operation

No

operation

Pop PC from

stack

:

TABLE

ADDWF PCL ; W = offset

Set GIEH or

GIEL

RETLW k0

RETLW k1

:

; Begin table

;

No

operation

No

operation

No

operation

No

operation

:

RETLW kn

; End of table

RETFIE

1

Example:

After Interrupt

Before Instruction

PC

W

=

TOS

WS

W

=

0x07

BSR

STATUS

GIE/GIEH, PEIE/GIEL

BSRS

STATUSS

1

After Instruction

W

=

value of kn

DS30491C-page 396

 2004 Microchip Technology Inc.

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RETURN

Return from Subroutine

RLCF

Rotate Left f through Carry

Syntax:

[ label ] RETURN [s]

s ∈ [0,1]

Syntax:

[ label ] RLCF f [,d [,a]]

Operands:

Operation:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(TOS) → PC,

if s = 1

(WS) → W,

Operation:

(f<n>) → dest<n+1>,

(f<7>) → C,

(STATUSS) → STATUS,

(BSRS) → BSR,

PCLATU, PCLATH are unchanged

(C) → dest<0>

Status Affected:

Encoding:

C, N, Z

Status Affected:

Encoding:

None

0011

01da

ffff

0000

0001

001s

Description:

The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result

is stored back in register ‘f’

(default). If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

Description:

Return from subroutine. The stack

is popped and the top of the stack

(TOS) is loaded into the program

counter. If ‘s’ = 1, the contents of

the shadow registers WS,

STATUSS and BSRS are loaded

into their corresponding registers,

W, Status and BSR. If ‘s’ = 0, no

update of these registers occurs

(default).

register f

C

Words:

Cycles:

1

2

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

No

Process

Data

Pop PC

from stack

operation

Decode

Read

Process

Write to

No

register ‘f’

Data

destination

operation

RLCF

REG, 0, 0

Example:

Before Instruction

RETURN

Example:

REG

C

=

1110 0110

0

After Interrupt

After Instruction

PC

=

TOS

REG

=

1110 0110

W

C

=

1100 1100

1

 2004 Microchip Technology Inc.

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PIC18F6585/8585/6680/8680

RLNCF

Rotate Left f (no carry)

RRCF

Rotate Right f through Carry

Syntax:

[ label ] RLNCF f [,d [,a]]

Syntax:

[ label ] RRCF f [,d [,a]]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f<n>) → dest<n+1>,

(f<7>) → dest<0>

Operation:

(f<n>) → dest<n-1>,

(f<0>) → C,

(C) → dest<7>

Status Affected:

Encoding:

N, Z

Status Affected:

Encoding:

C, N, Z

0100

01da

ffff

0011

00da

ffff

Description:

The contents of register ‘f’ are

rotated one bit to the left. If ‘d’ is ‘0,’

the result is placed in W. If ‘d’ is ‘1’,

the result is stored back in register

‘f’ (default). If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ is ‘1’, then the

bank will be selected as per the

BSR value (default).

Description:

The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result

is placed back in register ‘f’

(default). If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ is ‘1’, then the

bank will be selected as per the

BSR value (default).

register f

Words:

Cycles:

1

register f

C

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

Read

register ‘f’

Process

Data

Write to

destination

Q2

Q3

Q4

Decode

Read

Process

Write to

register ‘f’

Data

destination

RLNCF

REG, 1, 0

Example:

Before Instruction

RRCF

REG, 0, 0

Example:

REG

=

1010 1011

0101 0111

After Instruction

Before Instruction

REG

=

REG

C

=

1110 0110

0

After Instruction

REG

=

1110 0110

W

C

=

0111 0011

0

DS30491C-page 398

 2004 Microchip Technology Inc.

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RRNCF

Rotate Right f (no carry)

SETF

Set f

Syntax:

[ label ] RRNCF f [,d [,a]]

Syntax:

[ label ] SETF f [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

FFh → f

Operation:

(f<n>) → dest<n-1>,

(f<0>) → dest<7>

Status Affected:

Encoding:

None

0110

100a

ffff

Status Affected:

Encoding:

N, Z

Description:

The contents of the specified

0100

00da

ffff

register are set to FFh. If ‘a’ is ‘0’,

the Access Bank will be selected,

overriding the BSR value. If ‘a’ is

‘1’, then the bank will be selected

as per the BSR value (default).

Description:’

The contents of register ‘f’ are

rotated one bit to the right. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is

‘1’, the result is placed back in

register ‘f’ (default). If ‘a’ is ‘0’, the

Access Bank will be selected,

overriding the BSR value. If ‘a’ is

‘1’, then the bank will be selected

as per the BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

register f

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

Words:

Cycles:

1

SETF

REG,1

Example:

Before Instruction

Q Cycle Activity:

Q1

REG

=

0x5A

0xFF

Q2

Q3

Q4

After Instruction

Decode

Read

register ‘f’

Process

Data

Write to

destination

REG

=

RRNCF

REG, 1, 0

Example 1:

Before Instruction

REG

=

1101 0111

1110 1011

RRNCF REG, 0, 0

After Instruction

REG

=

Example 2:

Before Instruction

W

REG

=

?

1101 0111

After Instruction

W

REG

=

1110 1011

1101 0111

 2004 Microchip Technology Inc.

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PIC18F6585/8585/6680/8680

SLEEP

Enter Sleep mode

SUBFWP

Subtract f from W with borrow

Syntax:

[ label ] SLEEP

Syntax:

[ label ] SUBFWB f [,d [,a]]

Operands:

Operation:

None

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

00h → WDT,

0 → WDT postscaler,

1 → TO,

Operation:

(W) – (f) – (C) → dest

0 → PD

Status Affected:

Encoding:

N, OV, C, DC, Z

Status Affected:

Encoding:

TO, PD

0101

01da

ffff

0000

0011

Description:

Subtract register ‘f’ and carry flag

(borrow) from W (2’s complement

method). If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored in register ‘f’ (default). If ‘a’

is ‘0’, the Access Bank will be

selected, overriding the BSR

value. If ‘a’ is ‘1’, then the bank will

be selected as per the BSR value

(default).

Description:

The Power-down status bit (PD) is

cleared. The Time-out status bit

(TO) is set. Watchdog Timer and

its postscaler are cleared.

The processor is put into Sleep

mode with the oscillator stopped.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Q3

Q4

Decode

No

operation

Process

Data

Go to

SLEEP

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

SLEEP

Example:

Before Instruction

SUBFWB

REG, 1, 0

Example 1:

TO

=

?

PD

=

?

Before Instruction

After Instruction

REG

=

3

2

1

W

TO

=

1 †

C

PD

=

0

After Instruction

REG

W

C

=

FF

2

† If WDT causes wake-up, this bit is cleared.

0

Z

0

1

N

; result is negative

SUBFWB

REG, 0, 0

Example 2:

Before Instruction

REG

W

C

=

2

5

1

After Instruction

REG

W

C

=

2

3

1

0

Z

N

; result is positive

SUBFWB

REG, 1, 0

Example 3:

Before Instruction

REG

W

C

=

1

2

0

After Instruction

REG

W

C

=

0

2

1

0

Z

; result is zero

N

DS30491C-page 400

 2004 Microchip Technology Inc.

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SUBLW

Subtract W from literal

SUBWF

Syntax:

Subtract W from f

Syntax:

[ label ] SUBLW k

0 ≤ k ≤ 255

[ label ] SUBWF f [,d [,a]]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

k – (W) → W

N, OV, C, DC, Z

Operation:

(f) – (W) → dest

0000

1000

kkkk

Status Affected:

Encoding:

N, OV, C, DC, Z

Description:

W is subtracted from the eight-bit

literal ‘k’. The result is placed in

W.

0101

11da

ffff

Description:

Subtract W from register ‘f’ (2’s

complement method). If ‘d’ is ‘0’,

the result is stored in W. If ‘d’ is

‘1’, the result is stored back in

register ‘f’ (default). If ‘a’ is ‘0’, the

Access Bank will be selected,

overriding the BSR value. If ‘a’ is

‘1’, then the bank will be selected

as per the BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to W

SUBLW 0x02

Example 1:

Words:

Cycles:

1

Before Instruction

W

=

1

C

=

?

Q Cycle Activity:

Q1

After Instruction

Q2

Q3

Q4

W

C

Z

=

1

0

Decode

Read

register ‘f’

Process

Data

Write to

destination

; result is positive

N

SUBWF

REG, 1, 0

Example 1:

SUBLW 0x02

Example 2:

Before Instruction

REG

=

3

2

?

W

C

=

2

?

W

C

After Instruction

REG

W

C

=

1

2

1

0

W

C

Z

=

0

1

0

; result is zero

; result is positive

Z

N

SUBLW 0x02

Example 3:

SUBWF

REG, 0, 0

Example 2:

Before Instruction

W

C

=

3

?

REG

W

C

=

2

?

After Instruction

W

C

Z

=

FF ; (2’s complement)

After Instruction

0

1

; result is negative

REG

W

C

Z

N

=

2

0

1

0

N

; result is zero

SUBWF

REG, 1, 0

Example 3:

Before Instruction

REG

=

1

2

?

W

C

After Instruction

REG

W

C

=

FFh ;(2’s complement)

2

0

1

; result is negative

Z

N

 2004 Microchip Technology Inc.

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PIC18F6585/8585/6680/8680

SUBWFB

Syntax:

Subtract W from f with Borrow

SWAPF

Swap f

Syntax:

[ label ] SWAPF f [,d [,a]]

[ label ] SUBWFB f [,d [,a]]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f<3:0>) → dest<7:4>,

(f<7:4>) → dest<3:0>

Operation:

(f) – (W) – (C) → dest

Status Affected: N, OV, C, DC, Z

Status Affected:

Encoding:

None

Encoding:

0101

10da

ffff

0011

10da

ffff

Description:

Subtract W and the Carry flag (bor-

row) from register ‘f’ (2’s complement

method). If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default). If

‘a’ is ‘0’, the Access Bank will be

selected, overriding the BSR value. If

‘a’ is ‘1’, then the bank will be

selected as per the BSR value

(default).

Description:

The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is

‘1’, the result is placed in register ‘f’

(default). If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ is ‘1’, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Decode

Read

register ‘f’

Process

Data

Write to

destination

SUBWFB REG, 1, 0

Example 1:

SWAPF

REG, 1, 0

Example:

Before Instruction

REG

W

C

=

0x19

0x0D

1

(0001 1001)

(0000 1101)

REG

=

0x53

0x35

After Instruction

REG

=

REG

W

C

Z

N

=

0x0C

0x0D

(0000 1011)

(0000 1101)

1

0

; result is positive

SUBWFB REG, 0, 0

Example 2:

Before Instruction

REG

W

C

=

0x1B

0x1A

0

(0001 1011)

(0001 1010)

After Instruction

REG

W

C

=

0x1B

(0001 1011)

0x00

1

0

Z

; result is zero

N

SUBWFB REG, 1, 0

Example 3:

Before Instruction

REG

W

C

=

0x03

0x0E

1

(0000 0011)

(0000 1101)

After Instruction

REG

=

0xF5

(1111 0100)

; [2’s comp]

W

C

Z

=

0x0E

(0000 1101)

0

1

N

; result is negative

DS30491C-page 402

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TBLRD

Table Read

TBLRD

Table Read (Continued)

TBLRD *+ ;

Syntax:

[ label ] TBLRD ( *; *+; *-; +*)

Example1:

Operands:

Operation:

None

Before Instruction

TABLAT

TBLPTR

MEMORY(0x00A356)

=

0x55

0x00A356

0x34

if TBLRD *,

(Prog Mem (TBLPTR)) → TABLAT;

TBLPTR – No Change;

if TBLRD *+,

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) + 1 → TBLPTR;

if TBLRD *-,

After Instruction

TABLAT

TBLPTR

=

0x34

0x00A357

TBLRD +* ;

Example2:

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) – 1 → TBLPTR;

if TBLRD +*,

(TBLPTR) + 1 → TBLPTR;

(Prog Mem (TBLPTR)) → TABLAT;

Before Instruction

TABLAT

TBLPTR

=

0xAA

0x01A357

0x12

MEMORY(0x01A357)

MEMORY(0x01A358)

0x34

After Instruction

Status Affected:None

TABLAT

TBLPTR

=

0x34

0x01A358

0000

10nn

nn=0 *

=1 *+

=2 *-

=3 +*

Encoding:

Description:

This instruction is used to read the

contents of Program Memory (P.M.). To

address the program memory, a pointer

called Table Pointer (TBLPTR) is used.

The TBLPTR (a 21-bit pointer) points

to each byte in the program memory.

TBLPTR has a 2-Mbyte address

range.

TBLPTR[0] = 0: Least Significant

Byte of Program

Memory Word

TBLPTR[0] = 1: Most Significant

Byte of Program

Memory Word

The TBLRDinstruction can modify the

value of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

No

operation

No

operation

No operation

(Read

No

operation

No operation

(Write

Program Memory)

TABLAT)

 2004 Microchip Technology Inc.

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PIC18F6585/8585/6680/8680

TBLWT

Table Write

TBLWT

Table Write (Continued)

Syntax:

[ label ] TBLWT ( *; *+; *-; +*)

Words: 1

Cycles: 2

Operands:

Operation:

None

if TBLWT*,

Q Cycle Activity:

Q1

(TABLAT) → Holding Register;

TBLPTR – No Change;

if TBLWT*+,

Q2

Q3

Q4

Decode

No

operation

(TABLAT) → Holding Register;

(TBLPTR) + 1 → TBLPTR;

if TBLWT*-,

(TABLAT) → Holding Register;

(TBLPTR) – 1 → TBLPTR;

if TBLWT+*,

No

operation

No

operation

(Read

No

operation

No

operation

(Write to

Holding

Register )

TABLAT)

(TBLPTR) + 1 → TBLPTR;

(TABLAT) → Holding Register;

Example1:

TBLWT *+;

Status Affected: None

Before Instruction

0000

11nn

nn=0 *

=1 *+

=2 *-

=3 +*

Encoding:

TABLAT

TBLPTR

=

0x55

0x00A356

HOLDING REGISTER

(0x00A356)

=

0xFF

After Instructions (table write completion)

TABLAT

=

0x55

Description:

This instruction uses the 3 LSBs of

TBLPTR to determine which of the

8 holding registers the TABLAT is

written to. The holding registers are

used to program the contents of

Program Memory (P.M.). (Refer

to Section 5.0 “Flash Program

Memory” for additional details on

programming Flash memory.)

The TBLPTR (a 21-bit pointer) points

to each byte in the program memory.

TBLPTR has a 2-MBtye address

range. The LSb of the TBLPTR

selects which byte of the program

memory location to access.

TBLPTR

=

0x00A357

HOLDING REGISTER

(0x00A356)

=

0x55

Example 2:

TBLWT +*;

Before Instruction

TABLAT

TBLPTR

HOLDING REGISTER

(0x01389A)

HOLDING REGISTER

(0x01389B)

=

0x34

0x01389A

=

0xFF

After Instruction (table write completion)

TABLAT

TBLPTR

HOLDING REGISTER

(0x01389A)

HOLDING REGISTER

(0x01389B)

=

0x34

0x01389B

=

0xFF

0x34

TBLPTR[0] = 0:Least Significant

Byte of Program

Memory Word

TBLPTR[0] = 1:Most Significant

Byte of Program

Memory Word

The TBLWT instruction can modify

the value of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

DS30491C-page 404

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

TSTFSZ

Test f, skip if 0

XORLW

Exclusive OR literal with W

Syntax:

[ label ] TSTFSZ f [,a]

Syntax:

[ label ] XORLW k

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

Operation:

Status Affected:

Encoding:

(W) .XOR. k → W

N, Z

Operation:

skip if f = 0

Status Affected:

Encoding:

None

0000

1010

kkkk

0110

011a

ffff

Description:

The contents of W are XORed

with the 8-bit literal ‘k’. The result

is placed in W.

Description:

If ‘f’ = 0, the next instruction,

fetched during the current

instruction execution is discarded

and a NOPis executed, making this

a two-cycle instruction. If ‘a’ is ‘0’,

the Access Bank will be selected,

overriding the BSR value. If ‘a’ is

‘1’, then the bank will be selected

as per the BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to W

Words:

Cycles:

1

1(2)

Example:

XORLW 0xAF

Note: 3 cycles if skip and followed

by a 2-word instruction.

Before Instruction

W

=

0xB5

Q Cycle Activity:

Q1

After Instruction

Q2

Q3

Q4

W

=

0x1A

Decode

Read

register ‘f’

Process

Data

No

operation

If skip:

Q1

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No

operation

No

operation

HERE

NZERO

ZERO

TSTFSZ CNT, 1

:

Example:

Before Instruction

PC

=

Address (HERE)

After Instruction

If CNT

=

≠

=

0x00,

PC

Address (ZERO)

0x00,

If CNT

PC

Address (NZERO)

 2004 Microchip Technology Inc.

DS30491C-page 405

PIC18F6585/8585/6680/8680

XORWF

Exclusive OR W with f

Syntax:

[ label ] XORWF f [,d [,a]]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(W) .XOR. (f) → dest

Status Affected:

Encoding:

N, Z

0001

10da

ffff

Description:

Exclusive OR the contents of W

with register ‘f’. If ‘d’ is ‘0’, the result

is stored in W. If ‘d’ is ‘1’, the result

is stored back in the register ‘f’

(default). If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ is ‘1’, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

XORWF

REG, 1, 0

Example:

Before Instruction

REG

W

=

0xAF

0xB5

After Instruction

REG

W

=

0x1A

0xB5

DS30491C-page 406

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

26.1 MPLAB Integrated Development

Environment Software

26.0 DEVELOPMENT SUPPORT

The PICmicro^®microcontrollers are supported with a

full range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• An interface to debugging tools

- simulator

- MPLAB C17 and MPLAB C18 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- programmer (sold separately)

- emulator (sold separately)

- in-circuit debugger (sold separately)

• A full-featured editor with color coded context

• A multiple project manager

- MPLAB C30 C Compiler

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

• Customizable data windows with direct edit of

contents

- MPLAB SIM Software Simulator

- MPLAB dsPIC30 Software Simulator

• Emulators

• High-level source code debugging

• Mouse over variable inspection

• Extensive on-line help

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

- MPLAB ICD 2

• One touch assemble (or compile) and download

to PICmicro emulator and simulator tools

(automatically updates all project information)

• Device Programmers

- PRO MATE^®II Universal Device Programmer

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration Boards

- PICDEM^TM1 Demonstration Board

- PICDEM.net^TMDemonstration Board

- PICDEM 2 Plus Demonstration Board

- PICDEM 3 Demonstration Board

- PICDEM 4 Demonstration Board

- PICDEM 17 Demonstration Board

- PICDEM 18R Demonstration Board

- PICDEM LIN Demonstration Board

- PICDEM USB Demonstration Board

• Evaluation Kits

• Debug using:

- source files (assembly or C)

- mixed assembly and C

- machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increasing flexibility

and power.

26.2 MPASM Assembler

The MPASM assembler is a full-featured, universal

macro assembler for all PICmicro MCUs.

®

- KEELOQ

- PICDEM MSC

- microID^®

- CAN

The MPASM assembler generates relocatable object

files for the MPLINK object linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol ref-

erence, absolute LST files that contain source lines and

generated machine code and COFF files for

debugging.

- PowerSmart^®

- Analog

The MPASM assembler features include:

• Integration into MPLAB IDE projects

• User defined macros to streamline assembly code

• Conditional assembly for multi-purpose source

files

• Directives that allow complete control over the

assembly process

 2004 Microchip Technology Inc.

DS30491C-page 407

PIC18F6585/8585/6680/8680

26.3 MPLAB C17 and MPLAB C18

C Compilers

26.6 MPLAB ASM30 Assembler, Linker

and Librarian

The MPLAB C17 and MPLAB C18 Code Development

MPLAB ASM30 assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 compiler uses the

assembler to produce it’s object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

Systems are complete ANSI

C

compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microcontrollers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

26.4 MPLINK Object Linker/

MPLIB Object Librarian

• Rich directive set

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C compilers. It can link

relocatable objects from precompiled libraries, using

directives from a linker script.

• Flexible macro language

• MPLAB IDE compatibility

26.7 MPLAB SIM Software Simulator

The MPLAB SIM software simulator allows code devel-

opment in a PC hosted environment by simulating the

PICmicro series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user defined key press, to any pin. The execu-

tion can be performed in Single-Step, Execute Until

Break or Trace mode.

The MPLIB object librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

The MPLAB SIM simulator fully supports symbolic

debugging using the MPLAB C17 and MPLAB C18

C Compilers, as well as the MPASM assembler. The

software simulator offers the flexibility to develop and

debug code outside of the laboratory environment,

making it an excellent, economical software

development tool.

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

26.5 MPLAB C30 C Compiler

26.8 MPLAB SIM30 Software Simulator

The MPLAB C30 C compiler is a full-featured, ANSI

compliant, optimizing compiler that translates standard

ANSI C programs into dsPIC30F assembly language

source. The compiler also supports many command

line options and language extensions to take full

advantage of the dsPIC30F device hardware capabili-

ties and afford fine control of the compiler code

generator.

The MPLAB SIM30 software simulator allows code

development in a PC hosted environment by simulating

the dsPIC30F series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user defined key press, to any of the pins.

The MPLAB SIM30 simulator fully supports symbolic

debugging using the MPLAB C30 C Compiler and

MPLAB ASM30 assembler. The simulator runs in either

a Command Line mode for automated tasks, or from

MPLAB IDE. This high-speed simulator is designed to

debug, analyze and optimize time intensive DSP

routines.

MPLAB C30 is distributed with a complete ANSI C

standard library. All library functions have been vali-

dated and conform to the ANSI C library standard. The

library includes functions for string manipulation,

dynamic memory allocation, data conversion, time-

keeping and math functions (trigonometric, exponential

and hyperbolic). The compiler provides symbolic

information for high-level source debugging with the

MPLAB IDE.

DS30491C-page 408

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

26.9 MPLAB ICE 2000

High-Performance Universal

In-Circuit Emulator

26.11 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

The MPLAB ICE 2000 universal in-circuit emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for

PICmicro microcontrollers. Software control of the

MPLAB ICE 2000 in-circuit emulator is advanced by

the MPLAB Integrated Development Environment,

which allows editing, building, downloading and source

debugging from a single environment.

USB interface. This tool is based on the Flash

PICmicro MCUs and can be used to develop for these

and other PICmicro microcontrollers. The MPLAB

ICD 2 utilizes the in-circuit debugging capability built

into the Flash devices. This feature, along with

Microchip’s In-Circuit Serial Programming^TM(ICSP^TM

)

protocol, offers cost effective in-circuit Flash debugging

from the graphical user interface of the MPLAB

Integrated Development Environment. This enables a

designer to develop and debug source code by setting

breakpoints, single-stepping and watching variables,

CPU status and peripheral registers. Running at full

speed enables testing hardware and applications in

real-time. MPLAB ICD 2 also serves as a development

programmer for selected PICmicro devices.

The MPLAB ICE 2000 is a full-featured emulator sys-

tem with enhanced trace, trigger and data monitoring

features. Interchangeable processor modules allow the

system to be easily reconfigured for emulation of differ-

ent processors. The universal architecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PICmicro microcontrollers.

The MPLAB ICE 2000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

26.12 PRO MATE II Universal Device

Programmer

The PRO MATE II is a universal, CE compliant device

programmer with programmable voltage verification at

VDDMIN and VDDMAX for maximum reliability. It features

an LCD display for instructions and error messages

and a modular detachable socket assembly to support

various package types. In Stand-Alone mode, the

PRO MATE II device programmer can read, verify and

program PICmicro devices without a PC connection. It

can also set code protection in this mode.

26.10 MPLAB ICE 4000

High-Performance Universal

In-Circuit Emulator

The MPLAB ICE 4000 universal in-circuit emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for high-

end PICmicro microcontrollers. Software control of the

MPLAB ICE in-circuit emulator is provided by the

MPLAB Integrated Development Environment, which

allows editing, building, downloading and source

debugging from a single environment.

26.13 MPLAB PM3 Device Programmer

The MPLAB PM3 is a universal, CE compliant device

programmer with programmable voltage verification at

VDDMIN and VDDMAX for maximum reliability. It features

a large LCD display (128 x 64) for menus and error

messages and a modular detachable socket assembly

to support various package types. The ICSP™ cable

assembly is included as a standard item. In Stand-

Alone mode, the MPLAB PM3 device programmer can

read, verify and program PICmicro devices without a

PC connection. It can also set code protection in this

mode. MPLAB PM3 connects to the host PC via an

RS-232 or USB cable. MPLAB PM3 has high-speed

communications and optimized algorithms for quick

programming of large memory devices and incorpo-

rates an SD/MMC card for file storage and secure data

applications.

The MPLAB ICD 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high-speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanced emulator features include complex triggering

and timing, up to 2 Mb of emulation memory and the

ability to view variables in real-time.

The MPLAB ICE 4000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

 2004 Microchip Technology Inc.

DS30491C-page 409

PIC18F6585/8585/6680/8680

26.14 PICSTART Plus Development

Programmer

26.17 PICDEM 2 Plus

Demonstration Board

The PICSTART Plus development programmer is an

easy-to-use, low-cost, prototype programmer. It con-

nects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus development programmer supports

most PICmicro devices up to 40 pins. Larger pin count

devices, such as the PIC16C92X and PIC17C76X,

may be supported with an adapter socket. The

PICSTART Plus development programmer is CE

compliant.

The PICDEM 2 Plus demonstration board supports

many 18, 28 and 40-pin microcontrollers, including

PIC16F87X and PIC18FXX2 devices. All the neces-

sary hardware and software is included to run the dem-

onstration programs. The sample microcontrollers

provided with the PICDEM 2 demonstration board can

be programmed with a PRO MATE II device program-

mer, PICSTART Plus development programmer, or

MPLAB ICD 2 with a Universal Programmer Adapter.

The MPLAB ICD 2 and MPLAB ICE in-circuit emulators

may also be used with the PICDEM 2 demonstration

board to test firmware. A prototype area extends the

circuitry for additional application components. Some

of the features include an RS-232 interface, a 2 x 16

LCD display, a piezo speaker, an on-board temperature

sensor, four LEDs and sample PIC18F452 and

PIC16F877 Flash microcontrollers.

26.15 PICDEM 1 PICmicro

Demonstration Board

The PICDEM 1 demonstration board demonstrates the

capabilities of the PIC16C5X (PIC16C54 to

PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,

PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All

necessary hardware and software is included to run

basic demo programs. The sample microcontrollers

provided with the PICDEM 1 demonstration board can

be programmed with a PRO MATE II device program-

mer or a PICSTART Plus development programmer.

The PICDEM 1 demonstration board can be connected

to the MPLAB ICE in-circuit emulator for testing. A

prototype area extends the circuitry for additional appli-

cation components. Features include an RS-232

interface, a potentiometer for simulated analog input,

push button switches and eight LEDs.

26.18 PICDEM 3 PIC16C92X

Demonstration Board

The PICDEM 3 demonstration board supports the

PIC16C923 and PIC16C924 in the PLCC package. All

the necessary hardware and software is included to run

the demonstration programs.

26.19 PICDEM 4 8/14/18-Pin

Demonstration Board

The PICDEM 4 can be used to demonstrate the capa-

bilities of the 8, 14 and 18-pin PIC16XXXX and

PIC18XXXX MCUs, including the PIC16F818/819,

PIC16F87/88, PIC16F62XA and the PIC18F1320

family of microcontrollers. PICDEM 4 is intended to

showcase the many features of these low pin count

parts, including LIN and Motor Control using ECCP.

Special provisions are made for low-power operation

with the supercapacitor circuit and jumpers allow on-

board hardware to be disabled to eliminate current

draw in this mode. Included on the demo board are pro-

visions for Crystal, RC or Canned Oscillator modes, a

five volt regulator for use with a nine volt wall adapter

or battery, DB-9 RS-232 interface, ICD connector for

programming via ICSP and development with MPLAB

ICD 2, 2 x 16 liquid crystal display, PCB footprints for

H-Bridge motor driver, LIN transceiver and EEPROM.

Also included are: header for expansion, eight LEDs,

four potentiometers, three push buttons and a proto-

typing area. Included with the kit is a PIC16F627A and

a PIC18F1320. Tutorial firmware is included along with

the User’s Guide.

26.16 PICDEM.net Internet/Ethernet

Demonstration Board

The PICDEM.net demonstration board is an Internet/

Ethernet demonstration board using the PIC18F452

microcontroller and TCP/IP firmware. The board

supports any 40-pin DIP device that conforms to the

standard pinout used by the PIC16F877 or

PIC18C452. This kit features a user friendly TCP/IP

stack, web server with HTML, a 24L256 Serial

EEPROM for Xmodem download to web pages into

Serial EEPROM, ICSP/MPLAB ICD 2 interface con-

nector, an Ethernet interface, RS-232 interface and a

16 x 2 LCD display. Also included is the book and

CD-ROM “TCP/IP Lean, Web Servers for Embedded

Systems,” by Jeremy Bentham

DS30491C-page 410

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

26.20 PICDEM 17 Demonstration Board

26.24 PICDEM USB PIC16C7X5

Demonstration Board

The PICDEM 17 demonstration board is an evaluation

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. A pro-

grammed sample is included. The PRO MATE II device

programmer, or the PICSTART Plus development pro-

grammer, can be used to reprogram the device for user

tailored application development. The PICDEM 17

demonstration board supports program download and

execution from external on-board Flash memory. A

generous prototype area is available for user hardware

expansion.

The PICDEM USB Demonstration Board shows off the

capabilities of the PIC16C745 and PIC16C765 USB

microcontrollers. This board provides the basis for

future USB products.

26.25 Evaluation and

Programming Tools

In addition to the PICDEM series of circuits, Microchip

has a line of evaluation kits and demonstration software

for these products.

• KEELOQ evaluation and programming tools for

Microchip’s HCS Secure Data Products

26.21 PICDEM 18R PIC18C601/801

Demonstration Board

• CAN developers kit for automotive network

applications

The PICDEM 18R demonstration board serves to assist

development of the PIC18C601/801 family of Microchip

microcontrollers. It provides hardware implementation

of both 8-bit Multiplexed/Demultiplexed and 16-bit

Memory modes. The board includes 2 Mb external

Flash memory and 128 Kb SRAM memory, as well as

serial EEPROM, allowing access to the wide range of

memory types supported by the PIC18C601/801.

• Analog design boards and filter design software

• PowerSmart battery charging evaluation/

calibration kits

• IrDA^®development kit

• microID development and rfLab^TMdevelopment

software

• SEEVAL^®designer kit for memory evaluation and

endurance calculations

26.22 PICDEM LIN PIC16C43X

Demonstration Board

• PICDEM MSC demo boards for Switching mode

power supply, high-power IR driver, delta sigma

ADC and flow rate sensor

The powerful LIN hardware and software kit includes a

series of boards and three PICmicro microcontrollers.

The small footprint PIC16C432 and PIC16C433 are

used as slaves in the LIN communication and feature

Check the Microchip web page and the latest Product

Selector Guide for the complete list of demonstration

and evaluation kits.

on-board LIN transceivers.

A PIC16F874 Flash

microcontroller serves as the master. All three micro-

controllers are programmed with firmware to provide

LIN bus communication.

26.23 PICkit^TM1 Flash Starter Kit

A complete “development system in a box”, the PICkit

Flash Starter Kit includes a convenient multi-section

board for programming, evaluation and development of

8/14-pin Flash PIC^®microcontrollers. Powered via

USB, the board operates under a simple Windows GUI.

The PICkit 1 Starter Kit includes the User’s Guide (on

CD ROM), PICkit 1 tutorial software and code for

various applications. Also included are MPLAB^®IDE

(Integrated Development Environment) software,

software and hardware “Tips 'n Tricks for 8-pin Flash

PIC^®Microcontrollers” Handbook and a USB interface

cable. Supports all current 8/14-pin Flash PIC

microcontrollers, as well as many future planned

devices.

 2004 Microchip Technology Inc.

DS30491C-page 411

PIC18F6585/8585/6680/8680

NOTES:

DS30491C-page 412

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

27.0 ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-55°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V

Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V

Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V

Total power dissipation (Note 1) ...............................................................................................................................1.0W

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin ..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports ..................................................................................................................200 mA

Note 1: Power dissipation is calculated as follows:

Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL)

2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather

than pulling this pin directly to VSS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

 2004 Microchip Technology Inc.

DS30491C-page 413

PIC18F6585/8585/6680/8680

FIGURE 27-1:

PIC18F6585/8585/6680/8680 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

6.0V

5.5V

5.0V

4.5V

4.0V

PIC18FXX8X

4.2V

3.5V

3.0V

2.5V

2.0V

FMAX

Frequency

FMAX = 40 MHz for PIC18F6X8X and PIC18F8X8X in Microcontroller mode.

FMAX = 25 MHz for PIC18F8X8X in modes other than Microcontroller mode.

FIGURE 27-2:

PIC18LF6585/8585/6680/8680 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

6.0V

5.5V

5.0V

PIC18LFXX8X

4.5V

4.2V

4.0V

3.5V

3.0V

2.5V

2.0V

FMAX

4 MHz

For PIC18F6X8X and PIC18F8X8X in Microcontroller mode:

Frequency

FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V;

FMAX = 40 MHz, if VDDAPPMIN > 4.2V.

For PIC18F8X8X in modes other than Microcontroller mode:

FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V;

FMAX = 25 MHz, if VDDAPPMIN > 4.2V.

Note: VDDAPPMIN is the minimum voltage of the PICmicro^®device in the application.

DS30491C-page 414

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

FIGURE 27-3:

PIC18F6585/8585/6680/8680 VOLTAGE-FREQUENCY GRAPH (EXTENDED)

6.0V

5.5V

5.0V

4.5V

4.0V

PIC18FXX8X

4.2V

3.5V

3.0V

2.5V

2.0V

25 MHz

Frequency

 2004 Microchip Technology Inc.

DS30491C-page 415

PIC18F6585/8585/6680/8680

27.1 DC Characteristics: Supply Voltage

PIC18FXX8X (Industrial, Extended)

PIC18LFXX8X (Industrial)

PIC18LFXX8X

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

(Industrial)

Standard Operating Conditions (unless otherwise stated)

PIC18FXX8X

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param.

No.

Symbol

Characteristic

Supply Voltage

Min

Typ

Max

Units

Conditions

D001 VDD

PIC18LFXX8X

PIC18FXX8X

Analog Supply

2.0

4.2

—

5.5

V

HS, XT, RC and LP Oscillator mode

D001A AVDD

D002 VDR

D003 VPOR

VDD – 0.3

VDD + 0.3

Voltage

RAM Data Retention

Voltage⁽¹⁾

1.5

—

V

VDD Start Voltage

to ensure internal

0.7

See section on Power-on Reset for

details

Power-on Reset signal

D004 SVDD

D005 VBOR

VDD Rise Rate

to ensure internal

Power-on Reset signal

0.05

—

V/ms See section on Power-on Reset for

details

Brown-out Reset Voltage

BORV1:BORV0 = 11

BORV1:BORV0 = 10

BORV1:BORV0 = 01

BORV1:BORV0 = 00

1.96

2.64

4.11

4.41

—

2.18

2.92

4.55

4.87

V

Legend: Shading of rows is to assist in readability of the table.

Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM

data.

DS30491C-page 416

 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

27.2 DC Characteristics: Power-down and Supply Current

PIC18FXX8X (Industrial, Extended)

PIC18LFXX8X (Industrial)

PIC18LFXX8X

Standard Operating Conditions (unless otherwise stated)

(Industrial)

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18FXX8X

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param.

No.

Device

Typ Max Units

Conditions

Power-down Current (IPD)⁽¹⁾

D020

PIC18LFXX8X 0.2

1

µA

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

VDD = 2.0V,

(Sleep mode)

0.2

5.0

10

1

D020A

D020B

PIC18LFXX8X 0.4

VDD = 3.0V,

(Sleep mode)

0.4

1

3.0

All devices 0.7

0.7

18

2

VDD = 5.0V,

(Sleep mode)

2

15.0

32

Legend: Shading of rows is to assist in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and

all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as

I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and

temperature, also have an impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can

be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.

 2004 Microchip Technology Inc.

DS30491C-page 417

PIC18F6585/8585/6680/8680

27.2 DC Characteristics: Power-down and Supply Current

PIC18FXX8X (Industrial, Extended)

PIC18LFXX8X (Industrial) (Continued)

PIC18LFXX8X

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

(Industrial)

Standard Operating Conditions (unless otherwise stated)

PIC18FXX8X

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param.

No.

Device

Typ Max Units

Conditions

Supply Current (IDD)^(2,3)

D010

PIC18LFXX8X 500

300

500

µA

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

VDD = 2.0V

VDD = 3.0V

VDD = 5.0V

VDD = 2.0V

VDD = 3.0V

VDD = 5.0V

850 1000 µA

PIC18LFXX8X 500

900

1.5

2

µA

FOSC = 1 MHZ,

EC oscillator

500

1

mA

All devices

1

2

1.3

1

3

PIC18LFXX8X

2

1

2

1.5

2.5

2

PIC18LFXX8X 1.5

FOSC = 4 MHz,