PIC18F66J15I/PTQTP [MICROCHIP]
64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology; 八十〇分之六十四引脚高性能， 1兆位闪存微控制器采用纳瓦技术
| 型号： | PIC18F66J15I/PTQTP |
| 厂家： | 
MICROCHIP |
| 描述： | 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology |
| 文件： | 总394页 (文件大小：3815K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F87J10 Family
Data Sheet
64/80-Pin High-Performance,
1-Mbit Flash Microcontrollers
with nanoWatt Technology
2005 Microchip Technology Inc.
Advance Information
DS39663A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39663A-page ii
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers
with nanoWatt Technology
Special Microcontroller Features:
Peripheral Highlights:
• Operating voltage range: 2.0V to 3.6V
• 5.5V tolerant input (digital pins only)
• On-chip 2.5V regulator
• High-current sink/source 25 mA/25 mA
(PORTB and PORTC)
• Four programmable external interrupts
• Four input change interrupts
• Low-power, high-speed CMOS Flash technology
• C compiler optimized architecture:
• Two Capture/Compare/PWM (CCP) modules
• Three Enhanced Capture/Compare/PWM (ECCP)
modules:
- Optional extended instruction set designed to
optimize re-entrant code
- One, two or four PWM outputs
- Selectable polarity
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
- Programmable dead time
- Auto-Shutdown and Auto-Restart
• Two Master Synchronous Serial Port (MSSP)
modules supporting 3-wire SPI™ (all 4 modes)
and I2C™ Master and Slave modes
• Single-Supply In-Circuit Serial Programming™
(ICSP™) via two pins
• In-Circuit Debug (ICD) with three Break points via
two pins
• Two Enhanced Addressable USART modules:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-Wake-up on Start bit
• Power-Managed modes:
- Run: CPU on, peripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
- Auto-Baud Detect
• 10-bit, up to 15-channel Analog-to-Digital
Converter module (A/D):
- Auto-acquisition capability
Flexible Oscillator Structure:
- Conversion available during Sleep
- Self-calibration feature
• Two Crystal modes, up to 40 MHz
• 4x Phase Lock Loop (PLL)
• Dual analog comparators with input multiplexing
• Two External Clock modes, up to 40 MHz
• Internal 31 kHz oscillator
External Memory Bus
(PIC18F8XJ10/8XJ15 only):
• Secondary oscillator using Timer1 @ 32 kHz
• Two-Speed Oscillator Start-up
• Fail-Safe Clock Monitor:
• Address capability of up to 2 Mbytes
• 8-bit or 16-bit interface
- Allows for safe shutdown if peripheral clock
stops
• 12-bit, 16-bit and 20-bit Addressing modes
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 1
PIC18F87J10 FAMILY
Program Memory
SRAM Data
MSSP
SPI™
CCP/
ECCP
(PWM)
10-bit
A/D (ch)
Device
Memory
(bytes)
I/O
Flash # Single-Word
(bytes) Instructions
Master
I C™
2
PIC18F65J10
PIC18F65J15
PIC18F66J10
PIC18F66J15
32K
48K
64K
96K
16384
24576
32768
49152
65536
16384
24576
32768
49152
65536
2048
2048
2048
3936
3936
2048
2048
2048
3936
3936
50
50
50
50
50
66
66
66
66
66
11
11
11
11
11
15
15
15
15
15
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2
2
2
2
2
2
2
2
2
2
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
N
N
N
N
N
Y
Y
Y
Y
Y
PIC18F67J10 128K
PIC18F85J10
PIC18F85J15
PIC18F86J10
PIC18F86J15
32K
48K
64K
96K
PIC18F87J10 128K
Pin Diagrams
64-Pin TQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
RB0/INT0/FLT0
RB1/INT1
RE1/WR/P2C
RE0/RD/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
MCLR
RG4/CCP5/P1D
VSS
VDDCORE/VCAP
RF7/SS1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
VSS
OSC2/CLKO
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC5/SDO1
RC4/SDI1/SDA1
PIC18F6XJ10
PIC18F6XJ15
9
10
11
12
13
14
15
16
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RF3/AN8
RF2/AN7/C1OUT
Note 1: The ECCP2/P2A pin placement depends on the setting of the CCP2MX configuration bit.
DS39663A-page 2
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
Pin Diagrams (Continued)
80-Pin TQFP
RH2/A18
1
RJ2/WRL
60
RH3/A19
RJ3/WRH
2
59
RB0/INT0/FLT0
58
RE1/AD9/WR/P2C
3
RB1/INT1
RE0/AD8/RD/P2D
57
4
RB2/INT2
56
RB3/INT3/ECCP2(1)/P2A(1)
55
RB4/KBI0
54
RG2/RX2/DT2
7
RB5/KBI1
RG3/CCP4/P3D
53
8
RB6/KBI2/PGC
52
MCLR
9
PIC18F8XJ10
PIC18F8XJ15
RG4/CCP5/P1D
VSS
51
50
49
48
47
46
45
44
43
42
41
10
VSS
11
OSC2/CLKO
OSC1/CLKI
VDD
VDDCORE/VCAP
12
RF7/SS1
13
RB7/KBI3/PGD
RC5/SDO1
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RJ7/UB
RF6/AN11
14
RF5/AN10/CVREF
15
RF4/AN9
16
RF3/AN8
17
RF2/AN7/C1OUT
18
RH7/AN15/P1B(2)
19
RH6/AN14/P1C(2)
RJ6/LB
20
Note 1: The ECCP2/P2A pin placement depends on the setting of the CCP2MX configuration bit and the program memory mode.
2: P1B, P1C, P3B and P3C pin placement depends on the setting of the ECCPMX configuration bit.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 3
PIC18F87J10 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Oscillator Configurations ............................................................................................................................................................ 27
3.0 Power-Managed Modes ............................................................................................................................................................. 35
4.0 Reset.......................................................................................................................................................................................... 43
5.0 Memory Organization................................................................................................................................................................. 55
6.0 Program Memory........................................................................................................................................................................ 81
7.0 External Memory Bus................................................................................................................................................................. 85
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 97
9.0 Interrupts .................................................................................................................................................................................... 99
10.0 I/O Ports ................................................................................................................................................................................... 115
11.0 Timer0 Module ......................................................................................................................................................................... 141
12.0 Timer1 Module ......................................................................................................................................................................... 145
13.0 Timer2 Module ......................................................................................................................................................................... 151
14.0 Timer3 Module ......................................................................................................................................................................... 153
15.0 Timer4 Module ......................................................................................................................................................................... 157
16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 159
17.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 167
18.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 183
19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 225
20.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 247
21.0 Comparator Module.................................................................................................................................................................. 257
22.0 Comparator Voltage Reference Module................................................................................................................................... 263
23.0 Special Features of the CPU.................................................................................................................................................... 267
24.0 Instruction Set Summary.......................................................................................................................................................... 279
25.0 Development Support............................................................................................................................................................... 329
26.0 Electrical Characteristics.......................................................................................................................................................... 335
27.0 Packaging Information.............................................................................................................................................................. 371
Appendix A: Migration Between High-End Device Families............................................................................................................... 375
Index .................................................................................................................................................................................................. 377
The Microchip Web Site..................................................................................................................................................................... 389
Customer Change Notification Service .............................................................................................................................................. 389
Customer Support.............................................................................................................................................................................. 389
Reader Response .............................................................................................................................................................................. 390
Product Identification System............................................................................................................................................................. 391
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
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To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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Microchip’s Worldwide Web site; http://www.microchip.com
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DS39663A-page 4
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
The internal oscillator block provides a stable reference
source that gives the family additional features for
robust operation:
1.0
DEVICE OVERVIEW
This document contains device specific information for
the following devices:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
• PIC18F65J10
• PIC18F65J15
• PIC18F66J10
• PIC18F66J15
• PIC18F67J10
• PIC18F85J10
• PIC18F85J15
• PIC18F86J10
• PIC18F86J15
• PIC18F87J10
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
This family introduces a new line of low-voltage devices
with the main traditional advantage of all PIC18 micro-
controllers – namely, high computational performance
and a rich feature set – at an extremely competitive
price point. These features make the PIC18F87J10
family a logical choice for many high-performance
applications where cost is a primarily consideration.
1.1.3
EXPANDED MEMORY
The PIC18F87J10 family provides ample room for
application code, from 32 Kbytes to 128 Kbytes of code
space. The Flash cells for program memory are rated
to last up to 100 erase/write cycles. Data retention
without refresh is conservatively estimated to be
greater than 40 years.
1.1
Core Features
1.1.1
nanoWatt TECHNOLOGY
The PIC18F87J10 family also provides plenty of room
for dynamic application data, with up to 3936 bytes of
data RAM.
All of the devices in the PIC18F87J10 family incorporate
a range of features that can significantly reduce power
consumption during operation. Key items include:
1.1.4
EXTERNAL MEMORY BUS
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal RC oscilla-
tor, power consumption during code execution
can be reduced by as much as 90%.
In the unlikely event that 128 Kbytes of memory is
inadequate for an application, the 80-pin members of
the PIC18F87J10 family also implement an external
memory bus. This allows the controller’s internal
program counter to address a memory space of up to
2 Mbytes, permitting a level of data access that few
8-bit devices can claim. This allows additional memory
options, including:
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-Fly Mode Switching: The
power-managed modes are invoked by user code
during operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
• Using combinations of on-chip and external
memory up to the 2-Mbyte limit
• Using external Flash memory for reprogrammable
application code or large data tables
• Using external RAM devices for storing large
amounts of variable data
1.1.2
OSCILLATOR OPTIONS AND
FEATURES
1.1.5
EXTENDED INSTRUCTION SET
All of the devices in the PIC18F87J10 family offer five
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
The PIC18F87J10 family implements the optional
extension to the PIC18 instruction set, adding 8 new
instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as C.
• Two Crystal modes, using crystals or ceramic
resonators.
• Two External Clock modes, offering the option of
a divide-by-4 clock output.
• A Phase Lock Loop (PLL) frequency multiplier,
available to the external oscillator modes which
allows clock speeds of up to 40 MHz.
• An internal RC oscillator with a fixed 31-kHz
output which provides an extremely low-power
option for timing-insensitive applications.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 5
PIC18F87J10 FAMILY
1.1.6
EASY MIGRATION
1.3
Details on Individual Family
Members
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
Devices in the PIC18F87J10 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members, or even
jumping from 64-pin to 80-pin devices.
The devices are differentiated from each other in four
ways:
1. Flash program memory (six sizes, ranging from
32 Kbytes for PIC18FX5J10 devices to
128 Kbytes for PIC18FXJ710).
The PIC18F87J10 family is also pin-compatible with
other PIC18 families, such as the PIC18F8720 and
PIC18F8722. This allows a new dimension to the
evolution of applications, allowing developers to select
different price points within Microchip’s PIC18 portfolio
while maintaining the same feature set.
2. Data
RAM
(2048
bytes
for
PIC18FX5J10/X5J15/X6J10 devices, 3936
bytes for PIC18FX6J15/X7J10 devices).
3. A/D channels (11 for 64-pin devices, 15 for
80-pin devices).
4. I/O ports (7 bidirectional ports on 64-pin devices,
9 bidirectional ports on 80-pin devices).
1.2
Other Special Features
• Communications: The PIC18F87J10 family
incorporates a range of serial communication
peripherals, including 2 independent Enhanced
USARTs and 2 Master SSP modules, capable of
both SPI™ and I2C™ (Master and Slave) modes of
operation. In addition, one of the general purpose
I/O ports can be reconfigured as an 8-bit Parallel
Slave Port for direct processor-to-processor
communications.
All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.
The pinouts for all devices are listed in Table 1-3 and
Table 1-4.
• CCP Modules: All devices in the family incorporate
two Capture/Compare/PWM (CCP) modules and
three Enhanced CCP modules to maximize
flexibility in control applications. Up to four different
time bases may be used to perform several
different operations at once. Each of the three
ECCPs offers up to four PWM outputs, allowing for
a total of 12 PWMs. The ECCPs also offer many
beneficial features, including polarity selection,
programmable dead time, auto-shutdown and
restart and Half-Bridge and Full-Bridge Output
modes.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reducing code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 26.0 “Electrical Characteristics” for
time-out periods.
DS39663A-page 6
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC18F87J10 FAMILY (64-PIN DEVICES)
Features
PIC18F65J10 PIC18F65J15 PIC18F66J10 PIC18F66J15 PIC18F67J10
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Interrupt Sources
DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
32K
16384
2048
48K
24576
2048
64K
96K
49152
3936
128K
65536
3936
32768
2048
26
I/O Ports
Ports A, B, C, D, E, F, G
Timers
5
2
3
Capture/Compare/PWM Modules
Enhanced Capture/
Compare/PWM Modules
Serial Communications
MSSP (2), Enhanced USART (2)
Parallel Communications (PSP)
10-Bit Analog-to-Digital Module
Resets (and Delays)
Yes
11 Input Channels
POR, BOR, RESETInstruction, Stack Full, Stack Underflow, MCLR , WDT
(PWRT, OST)
Instruction Set
Packages
75 Instructions, 83 with Extended Instruction Set enabled
64-pin TQFP
TABLE 1-2:
DEVICE FEATURES FOR THE PIC18F87J10 FAMILY (80-PIN DEVICES)
Features
PIC18F85J10 PIC18F85J15 PIC18F86J10 PIC18F86J15 PIC18F87J10
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Interrupt Sources
DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
32K
16384
2048
48K
24576
2048
64K
32768
2048
26
96K
49152
3936
128K
65536
3936
I/O Ports
Ports A, B, C, D, E, F, G, H, J
Timers
5
2
3
Capture/Compare/PWM Modules
Enhanced Capture/
Compare/PWM Modules
Serial Communications
MSSP (2), Enhanced USART (2)
Parallel Communications (PSP)
10-Bit Analog-to-Digital Module
Resets (and Delays)
Yes
15 Input Channels
POR, BOR, RESETInstruction, Stack Full, Stack Underflow, MCLR , WDT
(PWRT, OST)
Instruction Set
Packages
75 Instructions, 83 with Extended Instruction Set enabled
80-pin TQFP
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 7
PIC18F87J10 FAMILY
FIGURE 1-1:
PIC18F6XJ10/6XJ15 (64-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
inc/dec logic
21
PORTA
Data Latch
8
RA0:RA5(1)
8
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
Address Latch
20
PCU PCH PCL
Program Counter
12
PORTB
Data Address<12>
RB0:RB7(1)
31 Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(96 Kbytes)
12
Data Latch
PORTC
RC0:RC7(1)
inc/dec
logic
8
Table Latch
Address
Decode
ROM Latch
IR
Instruction Bus <16>
PORTD
RD0:RD7(1)
8
State Machine
Control Signals
Instruction
Decode and
Control
PRODH PRODL
8 x 8 Multiply
PORTE
RE0:RE7(1)
3
8
Power-up
Timer
Timing
Generation
OSC2/CLKO
OSC1/CLKI
BITOP
8
W
8
Oscillator
Start-up Timer
8
INTRC
Oscillator
PORTF
8
Power-on
Reset
8
RF1:RF7(1)
Precision
Band Gap
Reference
ALU<8>
8
Watchdog
Timer
ENVREG
Brown-out
Reset(2)
Voltage
Regulator
PORTG
RG0:RG4(1)
VDDCORE/VCAP
VDD,VSS
MCLR
ADC
10-bit
Timer0
ECCP3
Timer1
CCP4
Timer2
CCP5
Timer3
Comparators
Timer4
ECCP1
ECCP2
MSSP1
MSSP2
EUSART1
EUSART2
Note 1: See Table 1-3 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
DS39663A-page 8
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
FIGURE 1-2:
PIC18F8XJ10/8XJ15 (80-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
Data Latch
Table Pointer<21>
inc/dec logic
8
RA0:RA5(1)
8
Data Memory
(3.9 Kbytes)
PCLATH
PCLATU
Address Latch
21
20
PORTB
PCU PCH PCL
Program Counter
RB0:RB7(1)
12
Data Address<12>
31 Level Stack
STKPTR
4
BSR
4
12
FSR0
FSR1
FSR2
Address Latch
PORTC
Access
Bank
Program Memory
(128 Kbytes)
RC0:RC7(1)
12
Data Latch
inc/dec
logic
8
PORTD
Table Latch
ROM Latch
RD0:RD7(1)
Address
Decode
Instruction Bus <16>
PORTE
IR
RE0:RE7(1)
AD15:AD0, A19:A16
(Multiplexed with PORTD,
PORTE and PORTH)
8
PORTF
PRODH PRODL
8 x 8 Multiply
Instruction
Decode &
Control
State Machine
Control Signals
RF1:RF7(1)
3
8
W
BITOP
8
PORTG
8
Power-up
Timer
8
Timing
Generation
OSC2/CLKO
OSC1/CLKI
RG0:RG4(1)
Oscillator
Start-up Timer
8
8
INTRC
Oscillator
ALU<8>
8
Power-on
Reset
PORTH
RH0:RH7(1)
Precision
Band Gap
Reference
Watchdog
Timer
ENVREG
Brown-out
Reset(2)
Voltage
Regulator
PORTJ
RJ0:RJ7(1)
VDDCORE/VCAP
VDD,VSS
Timer1
MCLR
ADC
10-bit
Timer0
Timer2
Timer3
Comparators
Timer4
CCP4
CCP5
MSSP1
MSSP2
ECCP1
ECCP2
ECCP3
EUSART1
EUSART2
Note 1: See Table 1-4 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 9
PIC18F87J10 FAMILY
TABLE 1-3:
Pin Name
PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Buffer
Type
Description
Type
TQFP
MCLR
7
I
ST
Master Clear (Reset) input. This pin is an active-low Reset
to the device.
OSC1/CLKI
OSC1
39
40
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS
otherwise.
I
I
ST
CLKI
CMOS
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
OSC2/CLKO
OSC2
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
CLKO
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
24
23
22
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
21
I/O
TTL
Digital I/O.
AN3
VREF+
I
I
Analog
Analog
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
28
27
I/O
I
ST
ST
Digital I/O.
Timer0 external clock input.
T0CKI
RA5/AN4
RA5
I/O
I
TTL
Analog
Digital I/O.
Analog input 4.
AN4
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when configuration bit CCP2MX is set.
2: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared.
DS39663A-page 10
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 1-3:
PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Pin Name
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
48
I/O
I
I
TTL
ST
ST
Digital I/O.
External interrupt 0.
ECCP1/2/3 Fault input.
INT0
FLT0
RB1/INT1
RB1
47
46
45
44
43
42
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
INT1
RB2/INT2
RB2
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
INT2
RB3/INT3
RB3
I/O
I
TTL
ST
Digital I/O.
External interrupt 3.
INT3
RB4/KBI0
RB4
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
KBI0
RB5/KBI1
RB5
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
KBI1
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock
pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
37
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when configuration bit CCP2MX is set.
2: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 11
PIC18F87J10 FAMILY
TABLE 1-3:
PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Pin Name
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
30
29
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/ECCP2/P2A
RC1
I/O
I
I/O
O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
ECCP2 PWM output A.
T1OSI
ECCP2(1)
P2A(1)
—
RC2/ECCP1/P1A
RC2
33
34
35
I/O
I/O
O
ST
ST
—
Digital I/O.
ECCP1
P1A
Capture 1 input/Compare 1 output/PWM 1 output.
ECCP1 PWM output A.
RC3/SCK1/SCL1
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK1
SCL1
Synchronous serial clock input/output for SPI™ mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI1/SDA1
RC4
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
SDI1
SDA1
RC5/SDO1
RC5
36
31
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO1
RC6/TX1/CK1
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX1
CK1
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
RC7/RX1/DT1
RC7
32
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX1
DT1
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when configuration bit CCP2MX is set.
2: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared.
DS39663A-page 12
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 1-3:
PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Pin Name
Description
PORTD is a bidirectional I/O port.
RD0/PSP0
RD0
58
55
54
53
52
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP0
RD1/PSP1
RD1
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP1
RD2/PSP2
RD2
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP2
RD3/PSP3
RD3
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP3
RD4/PSP4/SDO2
RD4
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
SPI™ data out.
PSP4
SDO2
RD5/PSP5/SDI2/SDA2
51
50
49
RD5
I/O
I/O
I
ST
TTL
ST
Digital I/O.
PSP5
SDI2
SDA2
Parallel Slave Port data.
SPI data in.
I/O
ST
I2C™ data I/O.
RD6/PSP6/SCK2/SCL2
RD6
I/O
I/O
I/O
I/O
ST
TTL
ST
Digital I/O.
Parallel Slave Port data.
PSP6
SCK2
SCL2
Synchronous serial clock input/output for SPI mode.
ST
Synchronous serial clock input/output for I2C mode.
RD7/PSP7/SS2
RD7
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
SPI slave select input.
PSP7
SS2
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when configuration bit CCP2MX is set.
2: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 13
PIC18F87J10 FAMILY
TABLE 1-3:
PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Pin Name
Description
PORTE is a bidirectional I/O port.
RE0/RD/P2D
RE0
2
1
I/O
I
O
ST
TTL
—
Digital I/O.
Read control for Parallel Slave Port.
ECCP2 PWM output D.
RD
P2D
RE1/WR/P2C
RE1
I/O
I
O
ST
TTL
—
Digital I/O.
Write control for Parallel Slave Port.
ECCP2 PWM output C.
WR
P2C
RE2/CS/P2B
RE2
64
I/O
I
O
ST
TTL
—
Digital I/O.
Chip select control for Parallel Slave Port.
ECCP2 PWM output B.
CS
P2B
RE3/P3C
RE3
63
62
61
60
59
I/O
O
ST
—
Digital I/O.
ECCP3 PWM output C.
P3C
RE4/P3B
RE4
I/O
O
ST
—
Digital I/O.
ECCP3 PWM output B.
P3B
RE5/P1C
RE5
I/O
O
ST
—
Digital I/O.
ECCP1 PWM output C.
P1C
RE6/P1B
RE6
I/O
O
ST
—
Digital I/O.
ECCP1 PWM output B.
P1B
RE7/ECCP2/P2A
RE7
I/O
I/O
O
ST
ST
—
Digital I/O.
ECCP2(2)
P2A(2)
Capture 2 input/Compare 2 output/PWM 2 output.
ECCP2 PWM output A.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when configuration bit CCP2MX is set.
2: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared.
DS39663A-page 14
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 1-3:
PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Pin Name
Description
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT
RF1
17
16
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
Comparator 2 output.
AN6
C2OUT
RF2/AN7/C1OUT
RF2
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
Comparator 1 output.
AN7
C1OUT
RF3/AN8
RF3
15
14
13
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
AN8
RF4/AN9
RF4
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
AN9
RF5/AN10/CVREF
RF5
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 10.
Comparator reference voltage output.
AN10
CVREF
RF6/AN11
RF6
12
11
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
AN11
RF7/SS1
RF7
I/O
I
ST
TTL
Digital I/O.
SPI™ slave select input.
SS1
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when configuration bit CCP2MX is set.
2: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 15
PIC18F87J10 FAMILY
TABLE 1-3:
PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Pin Name
Description
PORTG is a bidirectional I/O port.
RG0/ECCP3/P3A
RG0
3
4
5
6
8
I/O
I/O
O
ST
ST
—
Digital I/O.
ECCP3
P3A
Capture 3 input/Compare 3 output/PWM 3 output.
ECCP3 PWM output A.
RG1/TX2/CK2
RG1
I/O
O
I/O
ST
—
ST
Digital I/O.
TX2
CK2
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX2
DT2
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
RG3/CCP4/P3D
RG3
I/O
I/O
O
ST
ST
—
Digital I/O.
CCP4
P3D
Capture 4 input/Compare 4 output/PWM 4 output.
ECCP3 PWM output D.
RG4/CCP5/P1D
RG4
I/O
I/O
O
ST
ST
—
Digital I/O.
CCP5
P1D
Capture 5 input/Compare 5 output/PWM 5 output.
ECCP1 PWM output D.
VSS
9, 25, 41, 56
P
P
P
P
I
—
—
—
—
ST
Ground reference for logic and I/O pins.
Positive supply for peripheral digital logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
VDD
26, 38, 57
AVSS
AVDD
ENVREG
20
19
18
10
Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
P
P
—
—
VCAP
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when configuration bit CCP2MX is set.
2: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared.
DS39663A-page 16
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 1-4:
PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
TQFP
MCLR
9
I
ST
Master Clear (Reset) input. This pin is an active-low Reset to
the device.
OSC1/CLKI
OSC1
49
50
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS
otherwise.
I
I
ST
CLKI
CMOS
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
OSC2/CLKO
OSC2
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
CLKO
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
30
29
28
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
27
I/O
TTL
Digital I/O.
AN3
VREF+
I
I
Analog
Analog
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
34
33
I/O
I
ST
ST
Digital I/O.
Timer0 external clock input.
T0CKI
RA5/AN4
RA5
I/O
I
TTL
Analog
Digital I/O.
Analog input 4.
AN4
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is cleared).
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 17
PIC18F87J10 FAMILY
TABLE 1-4:
PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
TQFP
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
58
I/O
I
I
TTL
ST
ST
Digital I/O.
External interrupt 0.
ECCP1/2/3 Fault input.
INT0
FLT0
RB1/INT1
RB1
57
56
55
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
INT1
RB2/INT2
RB2
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
INT2
RB3/INT3/ECCP2/P2A
RB3
INT3
I/O
I
I/O
O
TTL
ST
ST
—
Digital I/O.
External interrupt 3.
Capture 2 input/Compare 2 output/PWM 2 output.
ECCP2 PWM output A.
(1)
ECCP2
(1)
P2A
RB4/KBI0
RB4
54
53
52
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
KBI0
RB5/KBI1
RB5
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
KBI1
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
47
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is cleared).
DS39663A-page 18
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 1-4:
PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PORTC is a bidirectional I/O port.
TQFP
RC0/T1OSO/T13CKI
RC0
36
35
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/ECCP2/P2A
RC1
T1OSI
I/O
I
I/O
O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
ECCP2 PWM output A.
(2)
ECCP2
(2)
P2A
—
RC2/ECCP1/P1A
RC2
43
44
45
I/O
I/O
O
ST
ST
—
Digital I/O.
ECCP1
P1A
Capture 1 input/Compare 1 output/PWM 1 output.
ECCP1 PWM output A.
RC3/SCK1/SCL1
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK1
SCL1
Synchronous serial clock input/output for SPI™ mode.
Synchronous serial clock input/output for I C™ mode.
2
RC4/SDI1/SDA1
RC4
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI1
SDA1
SPI data in.
2
I C data I/O.
RC5/SDO1
RC5
46
37
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO1
RC6/TX1/CK1
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX1
CK1
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
RC7/RX1/DT1
RC7
38
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX1
DT1
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is cleared).
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 19
PIC18F87J10 FAMILY
TABLE 1-4:
PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PORTD is a bidirectional I/O port.
TQFP
RD0/AD0/PSP0
RD0
72
69
68
67
66
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 0.
Parallel Slave Port data.
AD0
PSP0
RD1/AD1/PSP1
RD1
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 1.
Parallel Slave Port data.
AD1
PSP1
RD2/AD2/PSP2
RD2
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 2.
Parallel Slave Port data.
AD2
PSP2
RD3/AD3/PSP3
RD3
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 3.
Parallel Slave Port data.
AD3
PSP3
RD4/AD4/PSP4/SDO2
RD4
AD4
PSP4
SDO2
I/O
I/O
I/O
O
ST
TTL
TTL
—
Digital I/O.
External memory address/data 4.
Parallel Slave Port data.
SPI™ data out.
RD5/AD5/PSP5/
SDI2/SDA2
RD5
65
64
63
I/O
I/O
I/O
I
ST
TTL
TTL
ST
Digital I/O.
AD5
PSP5
SDI2
SDA2
External memory address/data 5.
Parallel Slave Port data.
SPI data in.
2
I/O
ST
I C™ data I/O.
RD6/AD6/PSP6/
SCK2/SCL2
RD6
I/O
I/O
I/O
I/O
I/O
ST
TTL
TTL
ST
Digital I/O.
External memory address/data 6.
Parallel Slave Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I C mode.
AD6
PSP6
SCK2
SCL2
2
ST
RD7/AD7/PSP7/SS2
RD7
AD7
PSP7
SS2
I/O
I/O
I/O
I
ST
Digital I/O.
TTL
TTL
TTL
External memory address/data 7.
Parallel Slave Port data.
SPI slave select input.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is cleared).
DS39663A-page 20
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 1-4:
PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PORTE is a bidirectional I/O port.
TQFP
RE0/AD8/RD/P2D
4
3
RE0
AD8
RD
I/O
I/O
I
ST
TTL
TTL
—
Digital I/O.
External memory address/data 8.
Read control for Parallel Slave Port.
ECCP2 PWM output D.
P2D
O
RE1/AD9/WR/P2C
RE1
AD9
WR
I/O
I/O
I
ST
TTL
TTL
—
Digital I/O.
External memory address/data 9.
Write control for Parallel Slave Port.
ECCP2 PWM output C.
P2C
O
RE2/AD10/CS/P2B
78
RE2
AD10
CS
I/O
I/O
I
ST
TTL
TTL
—
Digital I/O.
External memory address/data 10.
Chip select control for Parallel Slave Port.
ECCP2 PWM output B.
P2B
O
RE3/AD11/P3C
RE3
77
76
75
74
73
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 11.
ECCP3 PWM output C.
AD11
(3)
P3C
RE4/AD12/P3B
RE4
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 12.
ECCP3 PWM output B.
AD12
(3)
P3B
RE5/AD13/P1C
RE5
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 13.
ECCP1 PWM output C.
AD13
(3)
P1C
RE6/AD14/P1B
RE6
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 14.
ECCP1 PWM output B.
AD14
(3)
P1B
RE7/AD15/ECCP2/P2A
RE7
AD15
I/O
I/O
I/O
O
ST
TTL
ST
—
Digital I/O.
External memory address/data 15.
Capture 2 input/Compare 2 output/PWM 2 output.
ECCP2 PWM output A.
(4)
ECCP2
(4)
P2A
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is cleared).
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 21
PIC18F87J10 FAMILY
TABLE 1-4:
PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PORTF is a bidirectional I/O port.
TQFP
RF1/AN6/C2OUT
RF1
23
18
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
Comparator 2 output.
AN6
C2OUT
RF2/AN7/C1OUT
RF2
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
Comparator 1 output.
AN7
C1OUT
RF3/AN8
RF3
17
16
15
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
AN8
RF4/AN9
RF4
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
AN9
RF5/AN10/CVREF
RF5
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 10.
Comparator reference voltage output.
AN10
CVREF
RF6/AN11
RF6
14
13
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
AN11
RF7/SS1
RF7
I/O
I
ST
TTL
Digital I/O.
SPI™ slave select input.
SS1
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is cleared).
DS39663A-page 22
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 1-4:
PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PORTG is a bidirectional I/O port.
TQFP
RG0/ECCP3/P3A
RG0
5
6
I/O
I/O
O
ST
ST
TTL
Digital I/O.
ECCP3
P3A
Capture 3 input/Compare 3 output/PWM 3 output.
ECCP3 PWM output A.
RG1/TX2/CK2
RG1
I/O
O
I/O
ST
—
ST
Digital I/O.
TX2
CK2
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
7
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX2
DT2
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
RG3/CCP4/P3D
RG3
8
I/O
I/O
O
ST
ST
TTL
Digital I/O.
CCP4
P3D
Capture 4 input/Compare 4 output/PWM 4 output.
ECCP3 PWM output D.
RG4/CCP5/P1D
RG4
10
I/O
I/O
O
ST
ST
TTL
Digital I/O.
CCP5
P1D
Capture 5 input/Compare 5 output/PWM 5 output.
ECCP1 PWM output D.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is cleared).
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 23
PIC18F87J10 FAMILY
TABLE 1-4:
PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PORTH is a bidirectional I/O port.
TQFP
RH0/A16
RH0
79
80
1
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 16.
A16
RH1/A17
RH1
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 17.
A17
RH2/A18
RH2
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 18.
A18
RH3/A19
RH3
2
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 19.
A19
RH4/AN12/P3C
RH4
22
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 12.
ECCP3 PWM output C.
AN12
(5)
P3C
RH5/AN13/P3B
RH5
21
20
19
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 13.
ECCP3 PWM output B.
AN13
(5)
P3B
RH6/AN14/P1C
RH6
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 14.
ECCP1 PWM output C.
AN14
(5)
P1C
RH7/AN15/P1B
RH7
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 15.
ECCP1 PWM output B.
AN15
(5)
P1B
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is cleared).
DS39663A-page 24
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 1-4:
PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PORTJ is a bidirectional I/O port.
TQFP
RJ0/ALE
RJ0
62
61
60
59
39
40
41
42
I/O
O
ST
—
Digital I/O.
External memory address latch enable.
ALE
RJ1/OE
RJ1
I/O
O
ST
—
Digital I/O.
External memory output enable.
OE
RJ2/WRL
RJ2
I/O
O
ST
—
Digital I/O.
External memory write low control.
WRL
RJ3/WRH
RJ3
I/O
O
ST
—
Digital I/O.
External memory write high control.
WRH
RJ4/BA0
RJ4
I/O
O
ST
—
Digital I/O.
External memory byte address 0 control.
BA0
RJ5/CE
RJ5
I/O
O
ST
—
Digital I/O
External memory chip enable control.
CE
RJ6/LB
RJ6
I/O
O
ST
—
Digital I/O.
External memory low byte control.
LB
RJ7/UB
RJ7
I/O
O
ST
—
Digital I/O.
External memory high byte control.
UB
VSS
11, 31, 51, 70
P
P
P
P
I
—
—
—
—
ST
Ground reference for logic and I/O pins.
Positive supply for peripheral digital logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
VDD
32, 48, 71
AVSS
AVDD
ENVREG
26
25
24
12
Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
P
P
—
—
VCAP
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is cleared).
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 25
PIC18F87J10 FAMILY
NOTES:
DS39663A-page 26
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
FIGURE 2-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS OR HSPLL
2.0
2.1
OSCILLATOR
CONFIGURATIONS
CONFIGURATION)
Oscillator Types
(1)
C1
The PIC18F87J10 family of devices can be operated in
five different oscillator modes:
OSC1
To
Internal
Logic
1. HS
High-Speed Crystal/Resonator
(3)
RF
XTAL
2. HSPLL High-Speed Crystal/Resonator
with Software PLL Control
Sleep
OSC2
3. EC
External Clock with FOSC/4 Output
(1)
(2)
RS
PIC18F87J10
C2
4. ECPLL External Clock with Software PLL
Control
Note 1: See Table 2-1 and Table 2-2 for initial values of
5. INTRC Internal 31 kHz Oscillator
C1 and C2.
Four of these are selected by the user by programming
the FOSC2:FOSC0 configuration bits. The fifth mode
(INTRC) may be invoked under software control; it can
also be configured as the default mode on device
Resets.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
TABLE 2-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
2.2
Crystal Oscillator/Ceramic
Resonators (HS Modes)
Typical Capacitor Values Used:
In HS or HSPLL Oscillator modes, a crystal or ceramic
resonator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 2-1 shows the pin
connections.
Mode
Freq.
OSC1
OSC2
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
The oscillator design requires the use of a parallel cut
crystal.
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
Note:
Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer’s
specifications.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following Table 2-2 for additional
information.
Resonators Used:
4.0 MHz
8.0 MHz
16.0 MHz
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 27
PIC18F87J10 FAMILY
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
2.3
External Clock Input (EC Modes)
The EC and ECPLL Oscillator modes require an exter-
nal clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
Typical Capacitor Values
Crystal
Freq.
Tested:
Osc Type
C1
C2
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-2 shows the pin connections for the EC
Oscillator mode.
HS
4 MHz
8 MHz
20 MHz
27 pF
22 pF
15 pF
27 pF
22 pF
15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
FIGURE 2-2:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
OSC1/CLKI
Clock from
Ext. System
PIC18F87J10
OSC2/CLKO
See the notes following this table for additional
information.
FOSC/4
Crystals Used:
4 MHz
8 MHz
20 MHz
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-3. In
this configuration, the divide-by-4 output on OSC2 is
not available.
FIGURE 2-3:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
Note 1: Higher capacitance increases the stability
of oscillator but also increases the
start-up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
OSC1
Clock from
appropriate
components.
values
of
external
Ext. System
PIC18F87J10
(HS Mode)
OSC2
Open
3: Rs may be required to avoid overdriving
crystals with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
DS39663A-page 28
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FIGURE 2-4:
PLL BLOCK DIAGRAM
2.4
PLL Frequency Multiplier
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator. For these
reasons, the HSPLL and ECPLL modes are available.
HSPLL or ECPLL (CONFIG2L)
PLL Enable (OSCTUNE)
OSC2
Phase
Comparator
FIN
HS or EC
OSC1 Mode
FOUT
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external oscil-
lating source to produce frequencies up to 40 MHz.
The PLL is enabled by setting the PLLEN bit in the
OSCTUNE register (Register 2-1).
Loop
Filter
÷4
VCO
SYSCLK
REGISTER 2-1:
OSCTUNE: PLL CONTROL REGISTER
U-0
—
R/W-0(1)
PLLEN(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
PLLEN: Frequency Multiplier PLL Enable bit(1)
1= PLL enabled
0= PLL disabled
Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is
unavailable and read as ‘0’.
bit 5-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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• Primary oscillators
• Secondary oscillators
• Internal oscillator
2.5
Internal Oscillator Block
The PIC18F87J10 family of devices includes an inter-
nal oscillator source (INTRC) which provides a nominal
31 kHz output. The INTRC is enabled on device
power-up and clocks the device during its configuration
cycle until it enters operating mode. INTRC is also
enabled if it is selected as the device clock source or if
any of the following are enabled:
The primary oscillators include the External Crystal
and Resonator modes and the External Clock modes.
The particular mode is defined by the FOSC2:FOSC0
configuration bits. The details of these modes are
covered earlier in this chapter.
• Fail-Safe Clock Monitor
• Watchdog Timer
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.
• Two-Speed Start-up
These features are discussed in greater detail in
Section 23.0 “Special Features of the CPU”.
PIC18F87J10 family devices offer the Timer1 oscillator
as a secondary oscillator. This oscillator, in all
power-managed modes, is often the time base for
functions such as a real-time clock.
The INTRC can also be optionally configured as the
default clock source on device start-up by setting the
FOSC2 configuration bit. This is discussed in
Section 2.6.1 “Oscillator Control Register”.
Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/T13CKI and RC1/T1OSI
pins. Loading capacitors are also connected from each
pin to ground.
2.6
Clock Sources and
Oscillator Switching
The Timer1 oscillator is discussed in greater detail in
The PIC18F87J10 family includes a feature that allows
the device clock source to be switched from the main
oscillator to an alternate clock source. PIC18F87J10
family devices offer two alternate clock sources. When
an alternate clock source is enabled, the various
power-managed operating modes are available.
Section 12.3 “Timer1 Oscillator”.
In addition to being a primary clock source, the internal
oscillator is available as a power-managed mode
clock source. The INTRC source is also used as the
clock source for several special features, such as the
WDT and Fail-Safe Clock Monitor.
Essentially, there are three clock sources for these
devices:
The clock sources for the PIC18F87J10 family devices
are shown in Figure 2-5. See Section 23.0 “Special
Features of the CPU” for Configuration register
details.
FIGURE 2-5:
PIC18F87J10 FAMILY CLOCK DIAGRAM
PIC18F87J10 Family
Primary Oscillator
HS, EC
OSC2
Sleep
HSPLL, ECPLL
4 x PLL
OSC1
Peripherals
Secondary Oscillator
T1OSC
T1OSO
T1OSCEN
Enable
Oscillator
T1OSI
Internal Oscillator
INTRC
Source
CPU
IDLEN
Clock
Control
FOSC2:FOSC0 OSCCON<1:0>
Clock Source Option
for other Modules
WDT, PWRT, FSCM
and Two-Speed Start-up
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2.6.1
OSCILLATOR CONTROL REGISTER
2.6.1.1
System Clock Selection and the
FOSC2 Configuration Bit
The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in full
power operation and in power-managed modes.
The SCS bits are cleared on all forms of Reset. In the
device’s default configuration, this means the primary
oscillator defined by FOSC1:FOSC0 (that is, one of the
HC or EC modes) is used as the primary clock source
on device Resets.
The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC2:FOSC0 configu-
ration bits), the secondary clock (Timer1 oscillator) and
the internal oscillator. The clock source changes after
one or more of the bits are written to, following a brief
clock transition interval.
The default clock configuration on Reset can be
changed with the FOSC2 configuration bit. The effect of
this bit is to set the clock source selected when
SCS1:SCS0 = 00. When FOSC2 = 1 (default), the
oscillator source defined by FOSC1:FOSC0 is selected
whenever SCS1:SCS0 = 00. When FOSC2 = 0, the
The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)
bits indicate which clock source is currently providing
the device clock. The OSTS bit indicates that the
Oscillator Start-up Timer (OST) has timed out and the
primary clock is providing the device clock in primary
clock modes. The T1RUN bit indicates when the
Timer1 oscillator is providing the device clock in sec-
ondary clock modes. In power-managed modes, only
one of these bits will be set at any time. If neither of
these bits are set, the INTRC is providing the clock, or
the internal oscillator has just started and is not yet
stable.
INTRC
oscillator
is
selected
whenever
SCS1:SCS2 = 00. Because the SCS bits are cleared on
Reset, the FOSC2 setting also changes the default
oscillator mode on Reset.
Regardless of the setting of FOSC2, INTRC will always
be enabled on device power-up. It will serve as the
clock source until the device has loaded its configura-
tion values from memory. It is at this point that the
FOSC configuration bits are read and the oscillator
selection of operational mode is made.
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
Note that either the primary clock or the internal
oscillator will have two bit setting options, at any given
time, depending on the setting of FOSC2.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
2.6.2
OSCILLATOR TRANSITIONS
PIC18F87J10 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEPinstruction will be ignored.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEPinstruction or a very
long delay may occur while the Timer1
oscillator starts.
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REGISTER 2-2:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0
IDLEN
U-0
—
U-0
—
U-0
—
R-q(1)
U-0
—
R/W-0
SCS1
R/W-0
SCS0
OSTS
bit 7
bit 0
bit 7
IDLEN: Idle Enable bit
1= Device enters Idle mode on SLEEPinstruction
0= Device enters Sleep mode on SLEEPinstruction
bit 6-4 Unimplemented: Read as ‘0’
bit 3
OSTS: Oscillator Start-up Time-out Status bit(1)
1= Oscillator Start-up Timer time-out has expired; primary oscillator is running
0= Oscillator Start-up Timer time-out is running; primary oscillator is not ready
Note 1: The Reset value is ‘0’ when HS mode and Two-Speed Start-up are both enabled;
otherwise, it is ‘1’.
bit 2
Unimplemented: Read as ‘0’
bit 1-0 SCS1:SCS0: System Clock Select bits
11= Internal oscillator
10= Primary oscillator
01= Timer1 oscillator
When FOSC2 = 1:
00= Primary oscillator
When FOSC2 = 0:
00= Internal oscillator
Legend:
U = Unimplemented, read as ‘0’
‘q’ = Value determined by configuration
‘0’ = Bit is cleared W = Writable bit
-n = Value at POR
R = Readable bit
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
2.7
Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
real-time clock. Other features may be operating that
do not require a device clock source (i.e., SSP slave,
PSP, INTn pins and others). Peripherals that may add
significant current consumption are listed in
Section 26.2 “DC Characteristics: Power-Down and
Supply Current”.
In Secondary Clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In RC_RUN and RC_IDLE modes, the internal oscilla-
tor provides the device clock source. The 31 kHz
INTRC output can be used directly to provide the clock
and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 23.2 “Watchdog Timer (WDT)” through
Section 23.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
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The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS modes). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
2.8
Power-up Delays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 4.5 “Power-up Timer (PWRT)”.
There is a delay of interval TCSD (parameter 38,
Table 26-12), following POR, while the controller
becomes ready to execute instructions.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 26-12). It is always enabled.
TABLE 2-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode
OSC1 Pin
OSC2 Pin
EC, ECPLL
HS, HSPLL
Floating, pulled by external clock
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note:
See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
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NOTES:
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3.1.1
CLOCK SOURCES
3.0
POWER-MANAGED MODES
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power-managed modes. They are:
The PIC18F87J10 family devices provide the ability to
manage power consumption by simply managing clock-
ing to the CPU and the peripherals. In general, a lower
clock frequency and a reduction in the number of circuits
being clocked constitutes lower consumed power. For
the sake of managing power in an application, there are
three primary modes of operation:
• the primary clock, as defined by the
FOSC2:FOSC0 configuration bits
• the secondary clock (Timer1 oscillator)
• the internal oscillator
3.1.2
ENTERING POWER-MANAGED
MODES
• Run mode
• Idle mode
• Sleep mode
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
These modes define which portions of the device are
clocked and at what speed. The Run and Idle modes
may use any of the three available clock sources (pri-
mary, secondary or internal oscillator block); the Sleep
mode does not use a clock source.
The power-managed modes include several
power-saving features offered on previous PICmicro®
devices. One is the clock switching feature, offered in
other PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PICmicro
devices, where all device clocks are stopped.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEPinstruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
3.1
Selecting Power-Managed Modes
Selecting
a power-managed mode requires two
decisions: if the CPU is to be clocked or not and which
clock source is to be used. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table 3-1.
TABLE 3-1:
Mode
POWER-MANAGED MODES
OSCCON bits Module Clocking
IDLEN<7>(1) SCS1:SCS0<1:0> CPU Peripherals
Available Clock and Oscillator Source
Sleep
0
N/A
Off
Off
None – All clocks are disabled
PRI_RUN
N/A
10
Clocked Clocked Primary – HS, EC, HSPLL, ECPLL;
this is the normal full power execution mode.
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
N/A
N/A
1
01
11
10
01
11
Clocked Clocked Secondary – Timer1 Oscillator
Clocked Clocked Internal Oscillator
Off
Off
Off
Clocked Primary – HS, EC, HSPLL, ECPLL
Clocked Secondary – Timer1 Oscillator
Clocked Internal Oscillator
1
1
Note 1: IDLEN reflects its value when the SLEEPinstruction is executed.
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3.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
3.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
3.2.1
PRI_RUN MODE
Two bits indicate the current clock source and its
The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 23.4 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set. (see
Section 2.6.1 “Oscillator Control Register”).
status:
OSTS
(OSCCON<3>)
and
T1RUN
(T1CON<6>). In general, only one of these bits will be
set while in a given power-managed mode. When the
OSTS bit is set, the primary clock is providing the
device clock. When the T1RUN bit is set, the Timer1
oscillator is providing the clock. If neither of these bits
is set, INTRC is clocking the device.
3.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high-accuracy clock source.
Note:
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode or
one of the Idle modes, depending on the
setting of the IDLEN bit.
SEC_RUN mode is entered by setting the SCS1:SCS0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary oscilla-
tor is shut-down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
3.1.4
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEPinstruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
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On transitions from SEC_RUN mode to PRI_RUN, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
When the primary clock becomes ready, a clock switch
back to the primary clock occurs (see Figure 3-2).
When the clock switch is complete, the T1RUN bit is
cleared, the OSTS bit is set and the primary clock is
providing the clock. The IDLEN and SCS bits are not
affected by the wake-up; the Timer1 oscillator
continues to run.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such situa-
tions, initial oscillator operation is far from
stable and unpredictable operation may
result.
FIGURE 3-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
T1OSI
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 3-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
(1)
TOST
(1)
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC + 4
PC
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
SCS1:SCS0 bits Changed
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On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 3-4). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
3.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut-down. This mode provides the best power conser-
vation of all the Run modes, while still executing code.
It works well for user applications which are not highly
timing sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting SCS to ‘11’. When the
clock source is switched to the INTRC (see Figure 3-3),
the primary oscillator is shut-down and the OSTS bit is
cleared.
FIGURE 3-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
INTRC
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 3-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
INTRC
OSC1
(1)
(1)
TOST
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC + 4
PC
SCS1:SCS0 bits Changed
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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3.3
Sleep Mode
3.4
Idle Modes
The power-managed Sleep mode is identical to the leg-
acy Sleep mode offered in all other PICmicro devices.
It is entered by clearing the IDLEN bit (the default state
on device Reset) and executing the SLEEPinstruction.
This shuts down the selected oscillator (Figure 3-5). All
clock source status bits are cleared.
The Idle modes allow the controller’s CPU to be
selectively shut-down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEPinstruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS1:SCS0 bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS1:SCS0 bits
becomes ready (see Figure 3-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see Section 23.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 26-12) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.
FIGURE 3-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
PC + 2
FIGURE 3-6:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2 Q3 Q4 Q1 Q2
Q1
OSC1
(1)
(1)
TOST
TPLL
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
PC + 6
Wake Event
OSTS bit Set
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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3.4.1
PRI_IDLE MODE
3.4.2
SEC_IDLE MODE
This mode is unique among the three Low-Power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEPinstruction. If
the device is in another Run mode, set IDLEN first, then
set SCS1:SCS0 to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut-down, the OSTS bit is cleared
and the T1RUN bit is set.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEPinstruc-
tion. If the device is in another Run mode, set IDLEN
first, then set the SCS bits to ‘10’ and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC1:FOSC0 configuration bits. The OSTS bit
remains set (see Figure 3-7).
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins exe-
cuting code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-8).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code exe-
cution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 3-8).
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEPinstruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
FIGURE 3-7:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q3
Q4
Q1
Q1
Q2
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-8:
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q3
Q4
Q2
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
DS39663A-page 40
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3.4.3
RC_IDLE MODE
3.5.2
EXIT BY WDT TIME-OUT
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator.
This mode allows for controllable power conservation
during Idle periods.
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 23.2 “Watchdog
Timer (WDT)”).
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTRC, the primary oscillator
is shut-down and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the INTRC. After a delay of TCSD fol-
lowing the wake event, the CPU begins executing code
being clocked by the INTRC. The IDLEN and SCS bits
are not affected by the wake-up. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
The WDT timer and postscaler are cleared by one of
the following events:
• executing a SLEEPor CLRWDTinstruction
• the loss of a currently selected clock source (if the
Fail-Safe Clock Monitor is enabled)
3.5.3
EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
3.5
Exiting Idle and Sleep Modes
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes sections (see Section 3.2 “Run Modes”,
Section 3.3 “Sleep Mode” and Section 3.4 “Idle
Modes”).
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode where the primary clock source
is not stopped; and
• the primary clock source is either the EC or
ECPLL mode.
3.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC). However, a
fixed delay of interval TCSD following the wake event is
still required when leaving Sleep and Idle modes to
allow the CPU to prepare for execution. Instruction
execution resumes on the first clock cycle following this
delay.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
A fixed delay of interval TCSD following the wake event
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
2005 Microchip Technology Inc.
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PIC18F87J10 FAMILY
NOTES:
DS39663A-page 42
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4.1
RCON Register
4.0
RESET
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.6 “Reset State of Registers”.
The PIC18F87J10 family of devices differentiate
between various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Brown-out Reset (BOR)
f) RESETInstruction
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 9.0 “Interrupts”.
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.6.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 23.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
VDD
Brown-out
(1)
Reset
S
PWRT
32 µs
Chip_Reset
65.5 ms
PWRT
11-bit Ripple Counter
Q
R
INTRC
Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the
on-chip voltage regulator when there is insufficient source voltage to maintain regulation.
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REGISTER 4-1:
RCON: RESET CONTROL REGISTER
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed (set by firmware only)
0= The RESETinstruction was executed causing a device Reset (must be set in software after
a Brown-out Reset occurs)
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
1= Set by power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-Down Detection Flag bit
1= Set by power-up or by the CLRWDTinstruction
0= Set by execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred (set by firmware only)
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred (set by firmware only)
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been
detected, so that subsequent Power-on Resets may be detected.
2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See
Section 4.4.1 “Detecting BOR” for more information.
3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’
(assuming that POR was set to ‘1’ by software immediately after POR).
DS39663A-page 44
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FIGURE 4-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
4.2
Master Clear (MCLR)
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
VDD
VDD
D
R
The MCLR pin is not driven low by any internal Resets,
including the WDT.
R1
MCLR
PIC18F87J10
C
4.3
Power-on Reset (POR)
A Power-on Reset condition is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004). For a slow rise
time, see Figure 4-2.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
4.4.1
DETECTING BOR
The BOR bit always resets to ‘0’ on any BOR or POR
event. This makes it difficult to determine if a BOR
event has occurred just by reading the state of BOR
alone. A more reliable method is to simultaneously
check the state of both POR and BOR. This assumes
that the POR bit is reset to ‘1’ in software immediately
after any POR event. If BOR is ‘0’ while POR is ‘1’, it
can be reliably assumed that a BOR event has
occurred.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a POR occurs;
it does not change for any other Reset event. POR is
not reset to ‘1’ by any hardware event. To capture
multiple events, the user manually resets the bit to ‘1’
in software following any POR.
4.4
Brown-out Reset (BOR)
If the voltage regulator is disabled, Brown-out Reset
functionality is disabled. In this case, the BOR bit
cannot be used to determine a BOR event. The BOR
bit is still cleared by a POR event.
The PIC18F87J10 family of devices incorporate a
simple BOR function when the internal regulator is
enabled (ENVREG pin is tied to VDD). Any drop of VDD
below VBOR (parameter D005) for greater than time
TBOR (parameter 35) will reset the device. A Reset may
or may not occur if VDD falls below VBOR for less than
TBOR. The chip will remain in Brown-out Reset until
VDD rises above VBOR.
Once a BOR has occurred, the Power-up Timer will
keep the chip in Reset for TPWRT (parameter 33). If
VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be initialized. Once VDD
rises above VBOR, the Power-up Timer will execute the
additional time delay.
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PIC18F87J10 FAMILY
4.5.1
TIME-OUT SEQUENCE
4.5
Power-up Timer (PWRT)
If enabled, the PWRT time-out is invoked after the POR
pulse has cleared. The total time-out will vary based on
the status of the PWRT. Figure 4-3, Figure 4-4,
Figure 4-5 and Figure 4-6 all depict time-out
sequences on power-up with the Power-up Timer
enabled.
PIC18F87J10 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F87J10 fam-
ily devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32 µs = 65.6 ms. While the
PWRT is counting, the device is held in Reset.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXXXX device
operating in parallel.
The power-up time delay depends on the INTRC clock
and will vary from chip to chip due to temperature and
process variation. See DC parameter 33 for details.
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
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FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
3.3V
0V
1V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
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Table 4-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
4.6
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-1.
These bits are used in software to determine the nature
of the Reset.
TABLE 4-1:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
RCON Register
STKPTR Register
Program
Condition
Counter(1)
RI
TO
PD
POR
BOR
STKFUL STKUNF
Power-on Reset
RESETInstruction
Brown-out
0000h
0000h
0000h
0000h
1
0
1
u
1
u
1
1
1
u
1
u
0
u
u
u
0
u
0
u
0
u
u
u
0
u
u
u
MCLR during power-managed
Run modes
MCLR during power-managed
Idle modes and Sleep mode
0000h
0000h
0000h
u
u
u
1
0
u
0
u
u
u
u
u
u
u
u
u
u
u
u
u
u
WDT Time-out during Full Power
or power-managed Run modes
MCLR during Full Power
Execution
Stack Full Reset (STVREN = 1)
0000h
0000h
u
u
u
u
u
u
u
u
u
u
1
u
u
1
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
u
u
u
0
u
0
u
u
u
u
u
u
1
u
WDT Time-out during
power-managed Idle or Sleep
modes
PC + 2
Interrupt Exit from
PC + 2
u
u
0
u
u
u
u
power-managed modes
Legend: u= unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0008h or 0018h).
DS39663A-page 48
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TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction
Stack Resets
TOSU
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 1111
1100 0000
N/A
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 1111
1100 0000
N/A
---0 uuuu(1)
uuuu uuuu(1)
uuuu uuuu(1)
uu-u uuuu(1)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
N/A
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
---- 0000
---- uuuu
uuuu uuuu
---- 0000
---- uuuu
uuuu uuuu
---- uuuu
FSR1L
BSR
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
2005 Microchip Technology Inc.
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PIC18F87J10 FAMILY
TABLE 4-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
INDF2
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0--- q-00
---- ---0
0--1 1100
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0-00 0000
--00 0000
0-00 0000
---- uuuu
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
0--- q-00
---- ---0
0--q qquu
uuuu uuuu
uuuu uuuu
u0uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0-00 0000
--00 0000
0-00 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- q-uu
---- ---u
u--u qquu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u-uu uuuu
--uu uuuu
u-uu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
WDTCON
RCON(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSP1BUF
SSP1ADD
SSP1STAT
SSP1CON1
SSP1CON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
DS39663A-page 50
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction
Stack Resets
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
CCPR3H
CCPR3L
CCP3CON
ECCP1AS
CVRCON
CMCON
TMR3H
TMR3L
T3CON
PSPCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
IPR3
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0111
xxxx xxxx
xxxx xxxx
0000 0000
0000 ----
0000 0000
0000 0000
xxxx xxxx
0000 0010
0000 000x
1111 1111
0000 0000
0000 0000
11-- 1-11
00-- 0-00
00-- 0-00
1111 1111
0000 0000
0000 0000
0-00 --00
-0-- ----
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0111
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 ----
0000 0000
0000 0000
uuuu uuuu
0000 0010
0000 000x
1111 1111
0000 0000
0000 0000
11-- 1-11
00-- 0-00
00-- 0-00
1111 1111
0000 0000
0000 0000
0-00 --00
-0-- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(3)
uuuu uuuu
uu-- u-uu
uu-- u-uu(3)
uu-- u-uu
uuuu uuuu
uuuu uuuu(3)
uuuu uuuu
u-uu --uu
-u-- ----
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
MEMCON
OSCTUNE
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 51
PIC18F87J10 FAMILY
TABLE 4-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
TRISJ
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
---1 1111
1111 111-
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
xxxx xxxx
xxxx xxxx
---x xxxx
xxxx xxx-
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
xxxx xxxx
0000 xxxx
111x xxxx
x000 000-
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--0x 0000
0000 0000
01-0 0-00
0000 0000
01-0 0-00
1111 1111
1111 1111
---1 1111
1111 111-
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
111u uuuu
x000 000-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--0u 0000
0000 0000
01-0 0-00
0000 0000
01-0 0-00
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uu-u u-uu
uuuu uuuu
uu-u u-uu
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
SPBRGH1
BAUDCON1
SPBRG2
BAUDCON2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
DS39663A-page 52
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction
Stack Resets
ECCP1DEL
TMR4
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
-000 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PR4
T4CON
CCPR4H
CCPR4L
CCP4CON
CCPR5H
CCPR5L
CCP5CON
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
ECCP3AS
ECCP3DEL
ECCP2AS
ECCP2DEL
SSP2BUF
SSP2ADD
SSP2STAT
SSP2CON1
SSP2CON2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 53
PIC18F87J10 FAMILY
NOTES:
DS39663A-page 54
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
5.1
Program Memory Organization
5.0
MEMORY ORGANIZATION
PIC18 microcontrollers implement a 21-bit program
counter which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOPinstruction).
There are two types of memory in PIC18 Flash
microcontroller devices:
• Program Memory
• Data RAM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for
concurrent access of the two memory spaces.
The entire PIC18F87J10 family offers a range of
on-chip Flash program memory sizes, from 32 Kbytes
(up to 16,384 single-word instructions) to 128 Kbytes
(65,536 single-word instructions). The program
memory maps for individual family members are shown
in Figure 5-3.
Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Program Memory”.
FIGURE 5-1:
MEMORY MAPS FOR PIC18F87J10 FAMILY DEVICES
PC<20:0>
21
CALL, CALLW, RCALL,
RETURN, RETFIE, RETLW,
ADDULNK, SUBULNK
Stack Level 1
•
•
•
Stack Level 31
PIC18FX5J10
PIC18FX5J15
PIC18FX6J10
PIC18FX6J15
PIC18FX7J10
000000h
On-Chip
Memory
On-Chip
Memory
On-Chip
Memory
On-Chip
Memory
On-Chip
Memory
005FFFh
007FFFh
Config. Words
Config. Words
00BFFFh
00FFFFh
Config. Words
Config. Words
017FFFh
01FFFFh
Config. Words
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
1FFFFFh
Note:
Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 55
PIC18F87J10 FAMILY
5.1.1
HARD MEMORY VECTORS
5.1.2
FLASH CONFIGURATION WORDS
All PIC18 devices have a total of three hard-coded
return vectors in their program memory space. The
Reset vector address is the default value to which the
program counter returns on all device Resets; it is
located at 0000h.
Because the PIC18F87J10 family devices do not have
persistent configuration memory, the top four words of
on-chip program memory are reserved for configuration
information. On Reset, the configuration information is
copied into the Configuration registers.
PIC18 devices also have two interrupt vector
addresses for the handling of high priority and low
priority interrupts. The high priority interrupt vector is
located at 0008h and the low priority interrupt vector is
at 0018h. Their locations in relation to the program
memory map are shown in Figure 5-2.
The Configuration Words are stored in their program
memory location in numerical order, starting with the
lower byte of CONFIG1 at the lowest address and end-
ing with the upper byte of CONFIG4. For these devices,
only Configuration Words, CONFIG1 through
CONFIG3, are used; CONFIG4 is reserved. The actual
addresses of the Flash Configuration Word for devices
in the PIC18F87J10 family are shown in Table 5-1.
Their location in the memory map is shown with the
other memory vectors in Figure 5-2.
FIGURE 5-2:
HARD VECTOR AND
CONFIGURATION WORD
LOCATIONS FOR
PIC18F87J10 FAMILY
DEVICES
Additional details on the device Configuration Words
are provided in Section 23.1 “Configuration Bits”.
TABLE 5-1:
FLASH CONFIGURATION
WORD FOR PIC18F87J10
FAMILY DEVICES
0000h
Reset Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector
0008h
0018h
Program
Memory
(Kbytes)
Configuration
Word
Addresses
Device
PIC18F65J10
PIC18F85J10
PIC18F65J15
PIC18F85J15
PIC18F66J10
PIC18F86J10
PIC18F66J15
PIC18F86J15
PIC18F67J10
PIC18F87J10
32
48
7FF8h to 7FFFh
BFF8h to BFFFh
FFF8h to FFFFh
On-Chip
Program Memory
64
17FF8h to to
17FFFh
(Top of Memory-7)
(Top of Memory)
Flash Configuration Words
96
1FFF8h to to
1FFFFh
128
Read ‘0’
1FFFFFh
Legend:
(Top of Memory) represents upper boundary
of on-chip program memory space (see
Figure 5-1 for device-specific values).
Shaded area represents unimplemented
memory. Areas are not shown to scale.
DS39663A-page 56
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
• The Extended Microcontroller Mode allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip program memory; above
this, the device accesses external program
memory up to the 2-Mbyte program space limit.
Execution automatically switches between the
two memories as required.
5.1.3
PIC18F8XJ10/8XJ15 PROGRAM
MEMORY MODES
The 80-pin devices in this family can address up to a
total of 2 Mbytes of program memory. This is achieved
through the external memory bus. There are two
distinct operating modes available to the controllers:
• Microcontroller (MC)
• Extended Microcontroller (EMC)
The setting of the EMB configuration bits also controls
the address bus width of the external memory bus. This
is covered in more detail in Section 7.0 “External
Memory Bus”.
The program memory mode is determined by setting
the EMB configuration bits (CONFIG3L<5:4>), as
shown in Register 5-1. (See also Section 23.1
“Configuration Bits” for additional details on the
device configuration bits.)
In all modes, the microcontroller has complete access
to data RAM.
The program memory modes operate as follows:
Figure 5-3 compares the memory maps of the different
program memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 5-2.
• The Microcontroller Mode accesses only on-chip
Flash memory. Attempts to read above the top of
on-chip memory causes a read of all ‘0’s (a NOP
instruction).
The Microcontroller mode is also the only operating
mode available to 64-pin devices.
REGISTER 5-1:
CONFIG3L: CONFIGURATION REGISTER 3 LOW
R/WO-1
WAIT
R/WO-1
BW
R/WO-0
EMB1
R/WO-0
EMB0
R/WO-0
EASHFT
U-0
—
U-0
—
U-0
—
bit 7
bit 0
bit 7
WAIT: External Bus Wait Enable bit
1= Wait states on the external bus are disabled
0= Wait states on the external bus are enabled and selected by MEMCON<5:4>
bit 6
BW: Data Bus Width Select bit
1= 16-Bit Data Width modes
0= 8-Bit Data Width modes
bit 5-4
EMB1:EMB0: External Memory Bus Configuration bits
11= Extended Microcontroller mode, 20-bit address width for external bus
10= Extended Microcontroller mode, 16-bit address width for external bus
01= Extended Microcontroller mode, 12-bit address width for external bus
00= Microcontroller mode, external bus disabled
bit 3
EASHFT: External Address Bus Shift Enable bit
1= Address shifting enabled – external address bus is shifted to start at 000000h
0= Address shifting disabled – external address bus reflects the PC value
bit 2-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value after erase
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 57
PIC18F87J10 FAMILY
To avoid this, the Extended Microcontroller mode
implements an address shifting option to enable auto-
matic address translation. In this mode, addresses
presented on the external bus are shifted down by the
size of the on-chip program memory and are remapped
to start at 0000h. This allows the complete use of the
external memory device’s memory space.
5.1.4
EXTENDED MICROCONTROLLER
MODE AND ADDRESS SHIFTING
By default, devices in Extended Microcontroller mode
directly present the program counter value on the
external address bus for those addresses in the range
of the external memory space. In practical terms, this
means addresses in the external memory device below
the top of on-chip memory are unavailable.
FIGURE 5-3:
MEMORY MAPS FOR PIC18F87J10 FAMILY PROGRAM MEMORY MODES
(1)
(2)
Extended Microcontroller Mode
Microcontroller Mode
Extended Microcontroller Mode
(2)
with Address Shifting
On-Chip
Memory
Space
On-Chip
Memory
Space
External
Memory
Space
External
Memory
Space
On-Chip
Memory
Space
000000h
000000h
000000h
On-Chip
Program
Memory
On-Chip
Program
Memory
On-Chip
Program
Memory
No
Access
(Top of Memory)
(Top of Memory) + 1
(Top of Memory)
(Top of Memory) + 1
(Top of Memory)
(Top of Memory) + 1
External
Memory
Mapped
to
External
Memory
Space
Reads
‘0’s
Mapped
to
External
Memory
Space
External
Memory
1FFFFFh –
(Top of Memory)
1FFFFFh
1FFFFFh
1FFFFFh
Legend:
(Top of Memory) represents upper boundary of on-chip program memory space (see Figure 5-1 for device-specific
values). Shaded areas represent unimplemented or inaccessible areas, depending on the mode.
Note 1: This mode is the only available mode on 64-pin devices and the default on 80-pin devices.
2: These modes are only available on 80-pin devices.
TABLE 5-2:
MEMORY ACCESS FOR PIC18F8XJ10/8XJ15 PROGRAM MEMORY MODES
Internal Program Memory External Program Memory
Execution Table Read Table Write Execution Table Read Table Write
Operating Mode
From
From
To
From
From
To
Microcontroller
Yes
Yes
Yes
Yes
No
No
No Access
Yes
No Access
Yes
No Access
Yes
Extended Microcontroller
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The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack Special File Registers. Data can also be
pushed to, or popped from the stack, using these
registers.
5.1.5
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
A CALLtype instruction causes a push onto the stack;
the Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURNtype instruction causes
a pop from the stack; the contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.8.1 “Computed
GOTO”).
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full or has overflowed, or has underflowed.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
5.1.6.1
Only the top of the return address stack (TOS) is read-
able and writable. set of three registers,
Top-of-Stack Access
A
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
TOSU:TOSH:TOSL, hold the contents of the stack
location pointed to by the STKPTR register
(Figure 5-4). This allows users to implement a software
stack if necessary. After a CALL, RCALLor interrupt
(and ADDULNK and SUBULNK instructions if the
extended instruction set is enabled), the software can
5.1.6
RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALLor RCALLinstruc-
tion is executed, or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW
or a RETFIE instruction (and on ADDULNK and
SUBULNKinstructions if the extended instruction set is
enabled). PCLATU and PCLATH are not affected by
any of the RETURNor CALLinstructions.
read
the
pushed
value
by
reading
the
TOSU:TOSH:TOSL registers. These values can be
placed on a user-defined software stack. At return time,
the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-4:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack <20:0>
Stack Pointer
Top-of-Stack Registers
11111
11110
11101
STKPTR<4:0>
TOSU TOSH TOSL
00010
00h
1Ah
34h
00011
00010
00001
00000
001A34h
000D58h
Top-of-Stack
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When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
5.1.6.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 5-2) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
5.1.6.3
PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execu-
tion, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) configuration bit. (Refer to
Section 23.1 “Configuration Bits” for a description of
the device configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
The PUSHinstruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
REGISTER 5-2:
STKPTR: STACK POINTER REGISTER
R/C-0
R/C-0
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
STKFUL(1) STKUNF(1)
bit 7
bit 0
bit 7
bit 6
STKFUL: Stack Full Flag bit(1)
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit(1)
1= Stack underflow occurred
0= Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented
‘0’ = Bit is cleared
C = Clearable only bit
x = Bit is unknown
- n = Value at POR
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5.1.6.4
Stack Full and Underflow Resets
5.1.8
LOOK-UP TABLES IN PROGRAM
MEMORY
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full
or underflow will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.8.1
Computed GOTO
5.1.7
FAST REGISTER STACK
A computed GOTOis accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers, to provide a “fast return”
option for interrupts. This stack is only one level deep
and is neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push values into the stack registers. The values in
the registers are then loaded back into the working
registers if the RETFIE, FAST instruction is used to
return from the interrupt.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nninstructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCLinstruction. The next
instruction executed will be one of the RETLW nn
instructions, that returns the value ‘nn’ to the calling
function.
If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers in software during a low priority interrupt.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
If interrupt priority is not used, all interrupts may use the
fast register stack for returns from interrupt. If no inter-
rupts are used, the Fast Register Stack can be used to
restore the STATUS, WREG and BSR registers at the
end of a subroutine call. To use the Fast Register Stack
for a subroutine call, a CALLlabel, FASTinstruction
must be executed to save the STATUS, WREG and
EXAMPLE 5-2:
COMPUTED GOTO USING
AN OFFSET VALUE
OFFSET, W
TABLE
MOVF
CALL
ORG
TABLE
nn00h
ADDWF
RETLW
RETLW
RETLW
.
PCL
nnh
nnh
nnh
BSR registers to the Fast Register Stack.
A
RETURN, FASTinstruction is then executed to restore
these registers from the Fast Register Stack.
.
Example 5-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
.
5.1.8.2
Table Reads
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
EXAMPLE 5-1:
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
CALL SUB1, FAST
Look-up table data may be stored two bytes per
program word while programming. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from the
program memory. Data is transferred from program
memory one byte at a time.
•
•
SUB1
•
•
RETURN FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
Table read operation is discussed further in
Section 6.1 “Table Reads and Table Writes”.
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5.2.2
INSTRUCTION FLOW/PIPELINING
5.2
PIC18 Instruction Cycle
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change (e.g.,
GOTO), then two cycles are required to complete the
instruction (Example 5-3).
5.2.1
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the instruc-
tion register during Q4. The instruction is decoded and
executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-5.
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-5:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
Internal
Phase
Clock
PC
PC
PC + 2
PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 2)
Fetch INST (PC + 4)
EXAMPLE 5-3:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
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The CALL and GOTO instructions have the absolute
program memory address embedded into the instruc-
tion. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-6 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 24.0 “Instruction Set Summary”
provides further details of the instruction set.
5.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). To maintain alignment
with instruction boundaries, the PC increments in steps
of 2 and the LSB will always read ‘0’ (see Section 5.1.5
“Program Counter”).
Figure 5-6 shows an example of how instruction words
are stored in the program memory.
FIGURE 5-6:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
↓
Program Memory
Byte Locations →
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Instruction 3:
MOVFF
123h, 456h
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 5-4 shows how this works.
5.2.4
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
Note:
See Section 5.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instructions in the
extended instruction set.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
EXAMPLE 5-4:
CASE 1:
TWO-WORD INSTRUCTIONS
Object Code
Source Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
CASE 2:
TSTFSZ
MOVFF
REG1
REG1, REG2 ; No, skip this word
; Execute this word as a NOP
; continue code
; is RAM location 0?
ADDWF
REG3
Object Code
Source Code
TSTFSZ
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
REG1
; is RAM location 0?
MOVFF
REG1, REG2 ; Yes, execute this word
; 2nd word of instruction
ADDWF
REG3
; continue code
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5.3.1
BANK SELECT REGISTER
5.3
Data Memory Organization
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit bank pointer.
Note:
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.6 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. The
PIC18FX5J10/X5J15/X6J10 devices, with up to
64 Kbytes of program memory, implement 8 complete
banks for a total of 2048 bytes. PIC18FX6J15 and
PIC18FX7J10 devices, with 96 or 128 Kbytes of
program memory, implement all available banks and
provide 3936 bytes of data memory available to the
user. Figure 5-7 and Figure 5-8 show the data memory
organization for the devices.
Most instructions in the PIC18 instruction set make use
of the bank pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR3:BSR0). The upper four
bits are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLBinstruction.
The value of the BSR indicates the bank in data mem-
ory; the 8 bits in the instruction show the location in the
bank and can be thought of as an offset from the bank’s
lower boundary. The relationship between the BSR’s
value and the bank division in data memory is shown in
Figure 5-9.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h, while the BSR
is 0Fh, will end up resetting the program counter.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
section.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 5-7 indicates which banks are implemented.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to SFRs and
the lower portion of GPR Bank 0 without using the
BSR. Section 5.3.2 “Access Bank” provides a
detailed description of the Access RAM.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
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FIGURE 5-7:
DATA MEMORY MAP FOR PIC18FX5J10/X5J15/X6J10 DEVICES
When a = 0:
The BSR is ignored and the
BSR<3:0>
Data Memory Map
Access Bank is used.
00h
000h
05Fh
060h
0FFh
100h
Access RAM
GPR
The first 128 bytes are general
purpose RAM (from Bank 0).
= 0000
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
FFh
00h
The second 128 bytes are
Special Function Registers
(from Bank 15).
= 0001
= 0010
= 0011
= 0100
= 0101
= 0110
= 0111
GPR
GPR
GPR
GPR
GPR
GPR
GPR
1FFh
200h
FFh
00h
When a = 1:
The BSR specifies the bank
used by the instruction.
FFh
00h
2FFh
300h
3FFh
400h
FFh
00h
FFh
00h
4FFh
500h
FFh
00h
5FFh
600h
FFh
00h
6FFh
700h
Access Bank
00h
FFh
00h
7FFh
800h
Access RAM Low
5Fh
60h
Access RAM High
(SFRs)
FFh
= 1000
Bank 8
Unused
to
Read as ‘0’
= 1110
= 1111
Bank 14
Bank 15
EFFh
F00h
F5Fh
F60h
FFFh
FFh
00h
Unused
SFR
FFh
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FIGURE 5-8:
DATA MEMORY MAP FOR PIC18FX6J15/X7J10 DEVICES
When a = 0:
The BSR is ignored and the
BSR<3:0>
Data Memory Map
Access Bank is used.
00h
000h
05Fh
060h
0FFh
100h
The first 128 bytes are general
purpose RAM (from Bank 0).
Access RAM
GPR
= 0000
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
Bank 14
Bank 15
The second 128 bytes are
Special Function Registers
(from Bank 15).
FFh
00h
= 0001
= 0010
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 1111
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
1FFh
200h
FFh
00h
When a = 1:
The BSR specifies the bank
used by the instruction.
FFh
00h
2FFh
300h
3FFh
400h
FFh
00h
FFh
00h
4FFh
500h
FFh
00h
5FFh
600h
Access Bank
FFh
00h
6FFh
700h
00h
Access RAM Low
5Fh
60h
FFh
00h
7FFh
800h
Access RAM High
(SFRs)
FFh
FFh
00h
8FFh
900h
FFh
00h
9FFh
A00h
FFh
00h
AFFh
B00h
FFh
00h
BFFh
C00h
FFh
00h
CFFh
D00h
FFh
00h
DFFh
E00h
EFFh
F00h
F5Fh
F60h
FFFh
FFh
00h
Unused
SFR
FFh
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FIGURE 5-9:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Data Memory
Bank 0
(2)
(1)
From Opcode
BSR
000h
100h
7
0
7
0
00h
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
FFh
00h
Bank 1
(2)
Bank Select
FFh
00h
200h
300h
Bank 2
FFh
00h
Bank 3
through
Bank 13
FFh
00h
E00h
Bank 14
Bank 15
FFh
00h
F00h
FFFh
FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 80h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
5.3.2
ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
configuration bit = 1). This is discussed in more detail
in Section 5.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Block 15. The lower half is known
as the “Access RAM” and is composed of GPRs. This
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 5-7).
5.3.3
GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom
of the SFR area. GPRs are not initialized by a
Power-on Reset and are unchanged on all other
Resets.
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 67
PIC18F87J10 FAMILY
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of the
peripheral features are described in the chapter for that
peripheral.
5.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
more than the top half of Bank 15 (F60h to FFFh). A list
of these registers is given in Table 5-3 and Table 5-4.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 5-3:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J10 FAMILY DEVICES
Address
Name
Address
Name
Address
Name
Address
Name
Address
Name
(1)
FFFh
FFEh
FFDh
TOSU
TOSH
TOSL
FDFh
INDF2
FBFh
FBEh
CCPR1H
CCPR1L
F9Fh
F9Eh
F9Dh
IPR1
PIR1
PIE1
F7Fh SPBRGH1
F7Eh BAUDCON1
F7Dh SPBRGH2
(1)
(1)
FDEh POSTINC2
FDDh POSTDEC2
FBDh CCP1CON
(1)
(3)
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
STKPTR
PCLATU
PCLATH
PCL
FDCh PREINC2
FBCh
FBBh
CCPR2H
CCPR2L
F9Ch MEMCON
F7Ch BAUDCON2
(1)
(2)
FDBh PLUSW2
F9Bh OSCTUNE
F7Bh
F7Ah
—
—
(3)
(2)
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FSR2H
FSR2L
FBAh CCP2CON
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
TRISJ
TRISH
(3)
FB9h
FB8h
CCPR3H
CCPR3L
F79h ECCP1DEL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
STATUS
TMR0H
TMR0L
T0CON
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
F78h
F77h
F76h
F75h
F74h
TMR4
PR4
FB7h CCP3CON
FB6h ECCP1AS
T4CON
CCPR4H
CCPR4L
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
CVRCON
CMCON
TMR3H
(2)
—
OSCCON
F73h CCP4CON
(2)
INTCON
INTCON2
INTCON3
—
TMR3L
F72h
F71h
CCPR5H
CCPR5L
(3)
WDTCON
RCON
T3CON
LATJ
(3)
PSPCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
LATH
F70h CCP5CON
(1)
INDF0
TMR1H
TMR1L
T1CON
TMR2
LATG
LATF
LATE
LATD
LATC
LATB
LATA
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
(1)
(1)
FEEh POSTINC0
FEDh POSTDEC0
(1)
FECh PREINC0
(1)
FEBh PLUSW0
PR2
(2)
FEAh
FE9h
FE8h
FE7h
FSR0H
FSR0L
WREG
T2CON
SSP1BUF
SSP1ADD
—
F6Ah ECCP3AS
F69h ECCP3DEL
F68h ECCP2AS
F67h ECCP2DEL
(2)
—
(2)
(3)
—
PORTJ
PORTH
(1)
(2)
(3)
INDF1
FC7h SSP1STAT
FC6h SSP1CON1
FC5h SSP1CON2
—
(1)
(1)
(2)
FE6h POSTINC1
—
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
F66h
SSP2BUF
FE5h POSTDEC1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
F65h SSP2ADD
F64h SSP2STAT
F63h SSP2CON1
(1)
FE4h PREINC1
FC4h
FC3h
FC2h
FC1h
FC0h
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
(1)
FE3h PLUSW1
FE2h
FE1h
FE0h
FSR1H
FSR1L
BSR
F62h SSP2CON2
(2)
F61h
F60h
—
—
(2)
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
3: This register is not available on 64-pin devices.
DS39663A-page 68
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 5-4:
Filename
REGISTER FILE SUMMARY (PIC18F87J10 FAMILY)
Value on
POR, BOR on page:
Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
49, 59
49, 59
49, 59
49, 60
49, 59
49, 59
49, 59
49, 82
49, 82
49, 82
49, 82
49, 97
49, 97
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
bit 21(1)
Return Stack Pointer
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH
RBPU
PEIE/GIEL
INTEDG0
INT1IP
TMR0IE
INTEDG1
INT3IE
INT0IE
INTEDG2
INT2IE
RBIE
INTEDG3
INT1IE
TMR0IF
TMR0IP
INT3IF
INT0IF
INT3IP
INT2IF
RBIF
RBIP
0000 000x 49, 101
1111 1111 49, 102
1100 0000 49, 103
INT2IP
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
N/A
N/A
N/A
N/A
49, 75
49, 76
49, 76
49, 76
49, 76
POSTINC0
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
FSR0H
FSR0L
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
49, 75
49, 75
49
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
WREG
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
49, 75
49, 76
49, 76
49, 76
49, 76
POSTINC1
N/A
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
PREINC1
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
FSR1H
FSR1L
BSR
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- xxxx
xxxx xxxx
---- 0000
N/A
49, 75
49, 75
49, 64
50, 75
50, 76
50, 76
50, 76
50, 76
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
POSTINC2
N/A
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
FSR2H
FSR2L
STATUS
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- xxxx
xxxx xxxx
---x xxxx
50, 75
50, 75
50, 73
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV
Z
DC
C
Legend:
Note 1:
2:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
Bit 21 of the PC is only available in Serial Programming modes.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
3:
This register and its bits are not implemented in 64-pin devices. In 80-pin devices, the bits are unwritable and read as ‘0’ in Microcontroller
mode.
4:
5:
The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 69
PIC18F87J10 FAMILY
TABLE 5-4:
REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED)
Value on
POR, BOR on page:
Details
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0H
TMR0L
Timer0 Register High Byte
Timer0 Register Low Byte
0000 0000 50, 143
xxxx xxxx 50, 143
1111 1111 50, 141
T0CON
OSCCON
WDTCON
RCON
TMR0ON
IDLEN
—
T08BIT
—
T0CS
—
T0SE
—
PSA
OSTS(5)
—
T0PS2
—
T0PS1
SCS1
—
T0PS0
SCS0
0--- q-00
--- ---0
32, 50
—
—
—
—
SWDTEN
BOR
50, 273
IPEN
—
—
RI
TO
PD
POR
0--1 1100 44, 50,
113
TMR1H
TMR1L
T1CON
TMR2
Timer1 Register High Byte
Timer1 Register Low Byte
xxxx xxxx 50, 149
xxxx xxxx 50, 149
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
TMR1ON 0000 0000 50, 145
0000 0000 50, 152
Timer2 Register
PR2
Timer2 Period Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
MSSP1 Receive Buffer/Transmit Register
1111 1111 50, 152
T2CON
SSP1BUF
—
T2CKPS0 -000 0000 50, 151
xxxx xxxx 50, 184,
193
SSP1ADD
SSP1STAT
MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode)
0000 0000 50, 193
SMP
WCOL
GCEN
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
0000 0000 50, 184,
194
SSP1CON1
SSPOV
SSPEN
ACKDT
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
SEN
0000 0000 50, 185,
195
SSP1CON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
CCPR3H
CCPR3L
CCP3CON
ECCP1AS
CVRCON
CMCON
ACKSTAT
ACKEN
0000 0000 50, 196
xxxx xxxx 50, 255
xxxx xxxx 50, 255
0-00 0000 50, 247
--00 0000 50, 248
0-00 0000 50, 249
xxxx xxxx 51, 182
xxxx xxxx 51, 182
0000 0000 51, 167
xxxx xxxx 51, 182
xxxx xxxx 51, 182
0000 0000 51, 167
xxxx xxxx 51, 182
xxxx xxxx 51, 182
0000 0000 51, 167
A/D Result Register High Byte
A/D Result Register Low Byte
ADCAL
—
—
—
—
CHS3
VCFG1
ACQT2
CHS2
VCFG0
ACQT1
CHS1
PCFG3
ACQT0
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADON
PCFG0
ADCS0
ADFM
ADCS1
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP2M3
CCP3M3
CCP1M2
CCP2M2
CCP3M2
CCP1M1
CCP2M1
CCP3M1
CCP1M0
CCP2M0
CCP3M0
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
P2M1
P2M0
DC2B1
DC2B0
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
P3M1
P3M0
DC3B1
DC3B0
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1
PSS1AC0 PSS1BD1(2) PSS1BD0(2) 0000 0000 51, 179
CVREN
C2OUT
CVROE
C1OUT
CVRR
C2INV
CVRSS
C1INV
CVR3
CIS
CVR2
CM2
CVR1
CM1
CVR0
CM0
0000 0000 51, 263
0000 0111 51, 257
xxxx xxxx 51, 155
xxxx xxxx 51, 155
TMR3H
Timer3 Register High Byte
Timer3 Register Low Byte
TMR3L
T3CON
RD16
IBF
T3CCP2
OBF
T3CKPS1
IBOV
T3CKPS0
T3CCP1
—
T3SYNC
—
TMR3CS
—
TMR3ON 0000 0000 51, 153
0000 ---- 51, 139
PSPCON
PSPMODE
—
Legend:
Note 1:
2:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
Bit 21 of the PC is only available in Serial Programming modes.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
3:
This register and its bits are not implemented in 64-pin devices. In 80-pin devices, the bits are unwritable and read as ‘0’ in Microcontroller
mode.
4:
5:
The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
DS39663A-page 70
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 5-4:
REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED)
Value on
POR, BOR on page:
Details
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPBRG1
RCREG1
EUSART1 Baud Rate Generator Register Low Byte
EUSART1 Receive Register
0000 0000 51, 229
0000 0000 51, 237,
238
TXREG1
EUSART1 Transmit Register
xxxx xxxx 51, 235,
236
TXSTA1
RCSTA1
IPR3
CSRC
SPEN
SSP2IP
SSP2IF
SSP2IE
OSCFIP
OSCFIF
OSCFIE
PSPIP
PSPIF
PSPIE
EBDIS
—
TX9
RX9
TXEN
SREN
RC2IP
RC2IF
RC2IE
—
SYNC
CREN
TX2IP
TX2IF
TX2IE
—
SENDB
ADDEN
TMR4IP
TMR4IF
TMR4IE
BCL1IP
BCL1IF
BCL1IE
SSP1IP
SSP1IF
SSP1IE
—
BRGH
FERR
CCP5IP
CCP5IF
CCP5IE
—
TRMT
OERR
CCP4IP
CCP4IF
CCP4IE
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
WM1
TX9D
RX9D
CCP3IP
CCP3IF
CCP3IE
CCP2IP
CCP2IF
CCP2IE
TMR1IP
TMR1IF
TMR1IE
WM0
0000 0010 51, 226
0000 000x 51, 227
1111 1111 51, 112
0000 0000 51, 106
0000 0000 51, 109
11-- 1-11 51, 111
00-- 0-00 51, 105
00-- 0-00 51, 108
1111 1111 51, 110
0000 0000 51, 104
0000 0000 51, 107
BCL2IP
BCL2IF
BCL2IE
CMIP
CMIF
CMIE
ADIP
ADIF
PIR3
PIE3
IPR2
PIR2
—
—
—
PIE2
—
—
—
IPR1
RC1IP
RC1IF
RC1IE
WAIT1
—
TX1IP
TX1IF
TX1IE
WAIT0
—
CCP1IP
CCP1IF
CCP1IE
—
PIR1
PIE1
ADIE
MEMCON(3)
OSCTUNE
TRISJ(2)
TRISH(2)
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ(2)
LATH(2)
LATG
—
0-00 --00
-0-- ----
51, 86
29, 51
PLLEN(4)
TRISJ6
TRISH6
—
—
—
—
—
TRISJ7
TRISH7
—
TRISJ5
TRISH5
—
TRISJ4
TRISH4
TRISG4
TRISF4
TRISE4
TRISD4
TRISC4
TRISB4
TRISA4
LATJ4
LATH4
LATG4
LATF4
LATE4
LATD4
LATC4
LATB4
LATA4
RJ4
TRISJ3
TRISH3
TRISG3
TRISF3
TRISE3
TRISD3
TRISC3
TRISB3
TRISA3
LATJ3
LATH3
LATG3
LATF3
LATE3
LATD3
LATC3
LATB3
LATA3
RJ3
TRISJ2
TRISH2
TRISG2
TRISF2
TRISE2
TRISD2
TRISC2
TRISB2
TRISA2
LATJ2
LATH2
LATG2
LATF2
LATE2
LATD2
LATC2
LATB2
LATA2
RJ2
TRISJ1
TRISH1
TRISG1
TRISF1
TRISE1
TRISD1
TRISC1
TRISB1
TRISA1
LATJ1
LATH1
LATG1
LATF1
LATE1
LATD1
LATC1
LATB1
LATA1
RJ1
TRISJ0
TRISH0
TRISG0
—
1111 1111 52, 137
1111 1111 52, 135
---1 1111 52, 133
1111 111- 52, 131
1111 1111 52, 129
1111 1111 52, 126
1111 1111 52, 123
1111 1111 52, 120
--11 1111 52, 117
xxxx xxxx 52, 137
xxxx xxxx 52, 135
---x xxxx 52, 133
xxxx xxx- 52, 131
xxxx xxxx 52, 129
xxxx xxxx 52, 126
xxxx xxxx 52, 123
xxxx xxxx 52, 120
--xx xxxx 52, 117
xxxx xxxx 52, 137
0000 xxxx 52, 135
111x xxxx 52, 133
x000 000- 52, 131
xxxx xxxx 52, 129
xxxx xxxx 52, 126
xxxx xxxx 52, 123
xxxx xxxx 52, 120
--0x 0000 52, 117
TRISF7
TRISE7
TRISD7
TRISC7
TRISB7
—
TRISF6
TRISE6
TRISD6
TRISC6
TRISB6
—
TRISF5
TRISE5
TRISD5
TRISC5
TRISB5
TRISA5
LATJ5
LATH5
—
TRISE0
TRISD0
TRISC0
TRISB0
TRISA0
LATJ0
LATH0
LATG0
—
LATJ7
LATH7
—
LATJ6
LATH6
—
LATF
LATF7
LATE7
LATD7
LATC7
LATB7
—
LATF6
LATE6
LATD6
LATC6
LATB6
—
LATF5
LATE5
LATD5
LATC5
LATB5
LATA5
RJ5
LATE
LATE0
LATD0
LATC0
LATB0
LATA0
RJ0
LATD
LATC
LATB
LATA
PORTJ(2)
PORTH(2)
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
RJ7
RJ6
RH7
RH6
RH5
RJPU(2)
RH4
RH3
RH2
RH1
RH0
RDPU
RF7
REPU
RF6
RG4
RG3
RG2
RG1
RG0
RF5
RF4
RF3
RF2
RF1
—
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
—
—
RA5
RA4
RA3
RA2
RA1
RA0
Legend:
Note 1:
2:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
Bit 21 of the PC is only available in Serial Programming modes.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
3:
This register and its bits are not implemented in 64-pin devices. In 80-pin devices, the bits are unwritable and read as ‘0’ in Microcontroller
mode.
4:
5:
The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
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TABLE 5-4:
REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED)
Value on
POR, BOR on page:
Details
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPBRGH1
BAUDCON1
SPBRGH2
BAUDCON2
ECCP1DEL
TMR4
EUSART1 Baud Rate Generator Register High Byte
ABDOVF RCMT SCKP
EUSART2 Baud Rate Generator Register High Byte
0000 0000 52, 229
01-0 0-00 52, 228
0000 0000 52, 229
01-0 0-00 52, 228
0000 0000 53, 178
0000 0000 53, 158
1111 1111 53, 158
—
BRG16
—
WUE
ABDEN
ABDOVF
RCMT
—
SCKP
BRG16
P1DC3
—
WUE
ABDEN
P1DC0
P1RSEN
P1DC6
P1DC5
P1DC4
P1DC2
P1DC1
Timer4 Register
PR4
Timer4 Period Register
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0
T4CON
—
TMR4ON
CCP4M2
CCP5M2
T4CKPS1
CCP4M1
CCP5M1
T4CKPS0 -000 0000 53, 157
xxxx xxxx 53, 160
CCPR4H
CCPR4L
CCP4CON
CCPR5H
CCPR5L
CCP5CON
SPBRG2
RCREG2
Capture/Compare/PWM Register 4 High Byte
Capture/Compare/PWM Register 4 Low Byte
xxxx xxxx 53, 160
—
—
DC4B1
DC4B0
CCP4M3
CCP5M3
CCP4M0
CCP5M0
--00 0000 53, 159
xxxx xxxx 53, 160
xxxx xxxx 53, 160
--00 0000 53, 159
0000 0000 53, 229
Capture/Compare/PWM Register 5 High Byte
Capture/Compare/PWM Register 5 Low Byte
—
—
DC5B1
DC5B0
EUSART2 Baud Rate Generator Register Low Byte
EUSART2 Receive Register
0000 0000 53, 237,
238
TXREG2
EUSART2 Transmit Register
0000 0000 53, 235,
236
TXSTA2
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
SENDB
ADDEN
BRGH
FERR
TRMT
OERR
TX9D
RX9D
0000 0010 53, 226
0000 000x 53, 227
RCSTA2
ECCP3AS
ECCP3DEL
ECCP2AS
ECCP2DEL
SSP2BUF
ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1
P3RSEN P3DC6 P3DC5 P3DC4 P3DC3
ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1
P2RSEN P2DC6 P2DC5 P2DC4 P2DC3
MSSP2 Receive Buffer/Transmit Register
PSS3AC0
P3DC2
PSS3BD1
P3DC1
PSS3BD0 0000 0000 53, 179
P3DC0 0000 0000 53, 178
PSS2BD0 0000 0000 53, 179
PSS2AC0
P2DC2
PSS2BD1
P2DC1
P2DC0
0000 0000 53, 178
xxxx xxxx 53, 184,
193
SSP2ADD
SSP2STAT
MSSP2 Address Register (I2C™ Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode)
0000 0000 53, 193
SMP
WCOL
GCEN
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
0000 0000 53, 184,
194
SSP2CON1
SSPOV
SSPEN
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
SEN
0000 0000 53, 185,
195
SSP2CON2
ACKSTAT
ACKDT
ACKEN
0000 0000 53, 196
Legend:
Note 1:
2:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
Bit 21 of the PC is only available in Serial Programming modes.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
3:
This register and its bits are not implemented in 64-pin devices. In 80-pin devices, the bits are unwritable and read as ‘0’ in Microcontroller
mode.
4:
5:
The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
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register then reads back as ‘000u u1uu’. It is recom-
mended, therefore, that only BCF, BSF, SWAPF,
MOVFF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C, DC, OV or N bits in the STATUS
register.
5.3.5
STATUS REGISTER
The STATUS register, shown in Register 5-3, contains
the arithmetic status of the ALU. The STATUS register
can be the operand for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled.
For other instructions not affecting any Status bits, see
the instruction set summaries in Table 24-2 and
Table 24-3.
These bits are set or cleared according to the device
logic. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended. For example, CLRF STATUSwill set the Z bit
but leave the other bits unchanged. The STATUS
Note: The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
REGISTER 5-3:
STATUS REGISTER
U-0
—
U-0
—
U-0
—
R/W-x
N
R/W-x
OV
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude which causes the sign bit (bit 7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the
2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either bit 4 or bit 3 of the source register.
bit 0
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the
2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either the high or low-order bit of the source register.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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Purpose Register File”), or a location in the Access
Bank (Section 5.3.2 “Access Bank”) as the data
source for the instruction.
5.4
Data Addressing Modes
Note:
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 5.6 “Data Memory
and the Extended Instruction Set” for
more information.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.1 “Bank Select Register”) are used with
the address to determine the complete 12-bit address
of the register. When ‘a’ is ‘0’, the address is interpreted
as being a register in the Access Bank. Addressing that
uses the Access RAM is sometimes also known as
Direct Forced Addressing mode.
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their op
codes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its origi-
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on, or the W register.
The addressing modes are:
• Inherent
• Literal
• Direct
• Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST configuration bit = 1). Its operation is
discussed in greater detail in Section 5.6.1 “Indexed
Addressing with Literal Offset”.
5.4.3
INDIRECT ADDRESSING
Indirect addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special File Registers, they can also be directly manip-
ulated under program control. This makes FSRs very
useful in implementing data structures such as tables
and arrays in data memory.
5.4.1
INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device, or they operate implicitly on
one register. This addressing mode is known as
Inherent Addressing. Examples include SLEEP, RESET
and DAW.
The registers for indirect addressing are also imple-
mented with Indirect File Operands (INDFs) that permit
automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing, or offsetting
with another value. This allows for efficient code using
loops, such as the example of clearing an entire RAM
bank in Example 5-5. It also enables users to perform
indexed addressing and other stack pointer operations
for program memory in data memory.
Other instructions work in a similar way, but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode, because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
EXAMPLE 5-5:
HOW TO CLEAR RAM
(BANK 1) USING
5.4.2
DIRECT ADDRESSING
INDIRECT ADDRESSING
Direct addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
LFSR
CLRF
FSR0, 100h
;
NEXT
POSTINC0
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.3 “General
BTFSS
BRA
FSR0H, 1
NEXT
; NO, clear next
; YES, continue
CONTINUE
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the SFR space but are not physically implemented.
Reading or writing to a particular INDF register actually
accesses its corresponding FSR register pair. A read
from INDF1, for example, reads the data at the address
indicated by FSR1H:FSR1L. Instructions that use the
INDF registers as operands actually use the contents
of their corresponding FSR as a pointer to the instruc-
tion’s target. The INDF operand is just a convenient
way of using the pointer.
5.4.3.1
FSR Registers and the
INDF Operand
At the core of indirect addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Because indirect addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
Indirect addressing is accomplished with a set of Indi-
rect File Operands, INDF0 through INDF2. These can
be thought of as “virtual” registers: they are mapped in
FIGURE 5-10:
INDIRECT ADDRESSING
000h
Using an instruction with one of the
indirect addressing registers as the
operand....
Bank 0
Bank 1
ADDWF, INDF1, 1
100h
200h
300h
Bank 2
FSR1H:FSR1L
...uses the 12-bit address stored in
the FSR pair associated with that
register....
7
0
7
0
Bank 3
through
Bank 13
x x x x 1 1 1 1
1 1 0 0 1 1 0 0
...to determine the data memory
location to be used in that operation.
E00h
In this case, the FSR1 pair contains
FCCh. This means the contents of
location FCCh will be added to that
of the W register and stored back in
FCCh.
Bank 14
Bank 15
F00h
FFFh
Data Memory
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5.4.3.2
FSR Registers and POSTINC,
5.4.3.3
Operations by FSRs on FSRs
POSTDEC, PREINC and PLUSW
Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For exam-
ple, using an FSR to point to one of the virtual registers
will not result in successful operations. As a specific
case, assume that FSR0H:FSR0L contains FE7h, the
address of INDF1. Attempts to read the value of the
INDF1, using INDF0 as an operand, will return 00h.
Attempts to write to INDF1, using INDF0 as the
operand, will result in a NOP.
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on its stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by ‘1’ afterwards
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
• POSTINC: accesses the FSR value, then
automatically increments it by ‘1’ afterwards
• PREINC: increments the FSR value by ‘1’, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the new value in the operation
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses indirect addressing.
In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value offset by the value in the W register; neither value
is actually changed in the operation. Accessing the
other virtual registers changes the value of the FSR
registers.
Similarly, operations by indirect addressing are gener-
ally permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, roll-
overs of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of indexed addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
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When using the extended instruction set, this
addressing mode requires the following:
5.5
Program Memory and the
Extended Instruction Set
• The use of the Access Bank is forced (‘a’ = 0);
and
The operation of program memory is unaffected by the
use of the extended instruction set.
• The file address argument is less than or equal to
5Fh.
Enabling the extended instruction set adds five
additional two-word commands to the existing PIC18
instruction set: ADDFSR, CALLW, MOVSF, MOVSS and
SUBFSR. These instructions are executed as described
in Section 5.2.4 “Two-Word Instructions”.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in direct addressing) or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an address pointer
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
5.6
Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifi-
cally, the use of the Access Bank for many of the core
PIC18 instructions is different; this is due to the intro-
duction of a new addressing mode for the data memory
space. This mode also alters the behavior of indirect
addressing using FSR2 and its associated operands.
5.6.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set. Instruc-
tions that only use Inherent or Literal Addressing
modes are unaffected.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing
with FSR0 and FSR1 also remain unchanged.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they use the Access Bank (Access
RAM bit is ‘1’) or include a file address of 60h or above.
Instructions meeting these criteria will continue to
execute as before. A comparison of the different possi-
ble addressing modes when the extended instruction
set is enabled is shown in Figure 5-11.
5.6.1
INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of indirect addressing using the FSR2
register pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented
instructions – can invoke a form of indexed addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset, or Indexed Literal Offset mode.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 24.2.1
“Extended Instruction Syntax”.
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FIGURE 5-11:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
000h
When a = 0 and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and FFFh. This is the same as
locations F60h to FFFh
(Bank 15) of data memory.
060h
100h
Bank 0
00h
60h
Bank 1
through
Bank 14
Valid range
for ‘f’
Locations below 060h are not
available in this addressing
mode.
FFh
F00h
Access RAM
Bank 15
SFRs
F40h
FFFh
Data Memory
When a = 0 and f ≤ 5Fh:
000h
060h
100h
Bank 0
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
F40h
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
Bank 15
SFRs
where ‘k’ is the same as ‘f’.
FFFh
Data Memory
BSR
000h
060h
100h
00000000
When a = 1 (all values of f):
Bank 0
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
001001da ffffffff
Bank 1
through
Bank 14
F00h
F40h
Bank 15
SFRs
FFFh
Data Memory
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Remapping of the Access Bank applies only to opera-
tions using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use direct addressing as before. Any indirect or
indexed operation that explicitly uses any of the indirect
file operands (including FSR2) will continue to operate
as standard indirect addressing. Any instruction that
uses the Access Bank, but includes a register address
of greater than 05Fh, will use direct addressing and the
normal Access Bank map.
5.6.3
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower part of Access RAM
(00h to 5Fh) is mapped. Rather than containing just the
contents of the bottom part of Bank 0, this mode maps
the contents from Bank 0 and a user-defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower bound-
ary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 5.3.2 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 5-12.
5.6.4
BSR IN INDEXED LITERAL
OFFSET MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
FIGURE 5-12:
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
Example Situation:
000h
ADDWF f, d, a
Not Accessible
05Fh
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
Bank 0
100h
120h
17Fh
Window
Bank 1
00h
Bank 1 “Window”
200h
5Fh
60h
Special File Registers at
F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 2
through
Bank 14
SFRs
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
FFh
Access Bank
F00h
Bank 15
SFRs
F60h
FFFh
Data Memory
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NOTES:
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The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
6.0
PROGRAM MEMORY
For the PIC18F87J10 family of devices, the on-chip
program memory is implemented as read-only
memory. It is readable over the entire VDD range during
normal operation; it cannot be written to or erased.
Reads from program memory are executed one byte at
a time.
Table read operations retrieve data from program
memory and place it into the data RAM space. Table
write operations place data from the data memory
space on the external data bus. The actual process of
writing the data to the particular memory device is
determined by the requirements of the device itself.
Figure 6-1 shows the table operations as they relate to
program memory and data RAM.
PIC18F8XJ10/8XJ15 (80-pin) devices also implement
the ability to read, write to and execute code from
external memory devices, using the external memory
bus. In this implementation, external memory is used
as an extension beyond the upper boundary of the
on-chip program memory space. The operation of the
physical interface is discussed in Section 7.0
“External Memory Bus”.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block
can start and end at any byte address. If a table write is
being used to write executable code into an external
program memory, program instructions will need to be
word-aligned.
In all devices, a value written to the program memory
space does not need to be a valid instruction.
Executing a program memory location that forms an
invalid instruction results in a NOP.
Note:
For 64-pin devices, if the TBLWT instruc-
tion is used to attempt a write to the
program memory space, it will have no
effect. Execution will take two instruction
cycles but effectively result in a NOP.
The TBLWT instruction is still available
during In-Circuit Serial Programming
(ICSP).
6.1
Table Reads and Table Writes
To read and write to the program memory space, there
are two operations that allow the processor to move
bytes between the program memory space and the
data RAM: Table Read (TBLRD) and Table Write
(TBLWT).
FIGURE 6-1:
TABLE READ AND TABLE WRITE OPERATIONS
Instruction: TBLRD*
Table Pointer
Data Memory Space
Program Memory Space
(1)
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Instruction: TBLWT*
Data Memory Space
Program Memory Space
(1)
Table Pointer
(2)
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Note 1: Table Pointer register points to a byte in the program memory space.
2: Data is actually written to the memory location by the memory write algorithm. See Section 6.4 “Writing
to Program Memory Space (PIC18F8XJ10/8XJ15 Devices Only)” for more information.
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TABLE 6-1:
Example
TABLE POINTER
OPERATIONS WITH TBLRD
AND TBLWT INSTRUCTIONS
6.2
Control Registers
Two control registers are used in conjunction with the
TBLRD and TBLWT instructions: the TABLAT register
and the TBLPTR register set.
Operation on Table Pointer
TBLRD*
TBLWT*
6.2.1
TABLE LATCH REGISTER (TABLAT)
TBLPTR is not modified
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between the
program memory space and data RAM.
TBLRD*+ TBLPTR is incremented after the
TBLWT*+ read/write
TBLRD*- TBLPTR is decremented after the
TBLWT*- read/write
6.2.2
TABLE POINTER REGISTER
(TBLPTR)
TBLRD+* TBLPTR is incremented before the
TBLWT+* read/write
The Table Pointer register (TBLPTR) addresses a byte
within the program memory. It is comprised of three
SFR registers: Table Pointer Upper Byte, Table Pointer
High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). Only the lower six
bits of TBLPTRU are used with TBLPTRH and
TBLPTRL, to form a 22-bit wide pointer.
6.3
Reading the Flash Program
Memory
The TBLRDinstruction is used to retrieve data from the
program memory space and places it into data RAM.
Table reads from program memory are performed one
byte at a time.
The contents of TBLPTR indicate a location in program
memory space. The low-order 21 bits allow the device
to address the full 2 Mbytes of program memory space.
The 22nd bit allows access to the configuration space,
including the device ID, user ID locations and the
configuration bits.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-2
shows the interface between the internal program
memory and the TABLAT.
The TBLPTR register set is updated when executing a
TBLRDor TBLWT operation in one of four ways, based
on the instruction’s arguments. These are detailed in
Table 6-1. These operations on the TBLPTR only affect
the low-order 21 bits.
A typical method for reading data from program memory
is shown in Example 6-1.
When a TBLRDor TBLWTis executed, all 22 bits of the
TBLPTR determine which address in the program
memory space is to be read or written to.
FIGURE 6-2:
READS FROM PROGRAM MEMORY
Program Memory Space
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register
TABLAT
Read Register
FETCH
TBLRD
(IR)
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EXAMPLE 6-1:
READING A FLASH PROGRAM MEMORY WORD
MOVLW
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVFW
MOVF
; read into TABLAT and increment
; get data
TABLAT, W
WORD_EVEN
; read into TABLAT and increment
; get data
TABLAT, W
WORD_ODD
A complete overview of interface algorithms is beyond
the scope of this data sheet. The best place for timing
and instruction sequence requirements is the data
sheet of the memory device in question. For additional
information algorithm design for the external memory
interface, refer to Microchip application note AN869,
“External Memory Interfacing Techniques for the
PIC18F8XXX” (DS00869).
6.4
Writing to Program Memory Space
(PIC18F8XJ10/8XJ15 Devices
Only)
The table write operation outputs the contents of the
TBLPTR and TABLAT registers to the external address
and data busses of the external memory interface.
Depending on the program memory mode selected, the
operation may target any byte address in the device’s
memory space. What happens to this data depends
largely on the external memory device being used.
6.4.1
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
For PIC18 devices with Enhanced Flash memory, a
single algorithm is used for writing to the on-chip pro-
gram array. In the case of external devices, however,
the algorithm is determined by the type of memory
device and its requirements. In some cases, a specific
instruction sequence must be sent before data can be
written or erased. Address and data demultiplexing,
chip select operation and write time requirements must
all be considered in creating the appropriate code.
6.4.2
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the application writes to external
memory on a frequent basis, it may be necessary to
implement an error trapping routine to handle these
unplanned events.
The connection of the data and address busses to the
memory device are dictated by the interface being
used, the data bus width and the target device. When
using a 16-bit data path, the algorithm must take into
account the width of the target memory.
Another important consideration is the write time
requirement of the target device. If this is longer than
the time that a TBLWToperation makes data available
on the interface, the algorithm must be adjusted to
lengthen this time. It may be possible, for example, to
buy enough time by increasing the length of the wait
state on table operations.
6.5
Erasing External Memory
(PIC18F8XJ10/8XJ15 Devices
Only)
Erasure is implemented in different ways on different
devices. In many cases, it is possible to erase all or part
of the memory by issuing a specific command. In some
devices, it may be necessary to write ‘0’s to the
locations to be erased. For specific information, consult
the data sheet for the memory device in question.
In all cases, it is important to remember that instruc-
tions in the program memory space are word-aligned,
with the Least Significant bit always being written to an
even-numbered address (LSb = 0). If data is being
stored in the program memory space, word alignment
of the data is not required.
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6.6
Writing and Erasing On-Chip
Program Memory (ICSP Mode)
6.7
Flash Program Operation During
Code Protection
While the on-chip program memory is read-only in
normal operating mode, it can be written to and erased
as a function of In-Circuit Serial Programming (ICSP).
In this mode, the TBLWToperation is used in all devices
to write to blocks of 64 bytes (32 words) at one time.
Write blocks are boundary-aligned with the code pro-
tection blocks. Special commands are used to erase
one or more code blocks of the program memory, or the
entire device.
See Section 23.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2:
Name
REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
Reset
Values on
Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
49
49
49
49
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
Program Memory Table Latch
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during program memory access.
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The bus is implemented with 28 pins, multiplexed
across four I/O ports. Three ports (PORTD, PORTE
and PORTH) are multiplexed with the address/data bus
for a total of 20 available lines, while PORTJ is
multiplexed with the bus control signals.
7.0
EXTERNAL MEMORY BUS
Note:
The external memory bus is not
implemented on 64-pin devices.
The external memory bus allows the device to access
external memory devices (such as Flash, EPROM,
SRAM, etc.) as program or data memory. It supports
both 8 and 16-bit Data Width modes and three address
widths of up to 20 bits.
A list of the pins and their functions is provided in
Table 7-1.
TABLE 7-1:
Name
PIC18F8XJ10/8XJ15 EXTERNAL BUS – I/O PORT FUNCTIONS
Port
Bit
External Memory Bus Function
RD0/AD0
RD1/AD1
RD2/AD2
RD3/AD3
RD4/AD4
RD5/AD5
RD6/AD6
RD7/AD7
RE0/AD8
RE1/AD9
RE2/AD10
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/AD15
RH0/A16
RH1/A17
RH2/A18
RH3/A19
RJ0/ALE
RJ1/OE
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTH
PORTH
PORTH
PORTH
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
0
1
2
3
4
5
6
7
Address bit 0 or Data bit 0
Address bit 1 or Data bit 1
Address bit 2 or Data bit 2
Address bit 3 or Data bit 3
Address bit 4 or Data bit 4
Address bit 5 or Data bit 5
Address bit 6 or Data bit 6
Address bit 7 or Data bit 7
Address bit 8 or Data bit 8
Address bit 9 or Data bit 9
Address bit 10 or Data bit 10
Address bit 11 or Data bit 11
Address bit 12 or Data bit 12
Address bit 13 or Data bit 13
Address bit 14 or Data bit 14
Address bit 15 or Data bit 15
Address bit 16
Address bit 17
Address bit 18
Address bit 19
Address Latch Enable (ALE) Control pin
Output Enable (OE) Control pin
Write Low (WRL) Control pin
Write High (WRH) Control pin
Byte Address bit 0 (BA0)
Chip Enable (CE) Control pin
Lower Byte Enable (LB) Control pin
Upper Byte Enable (UB) Control pin
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
Note:
For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional
multiplexed features may be available on some pins.
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The operation of the EBDIS bit is also influenced by the
program memory mode being used. This is discussed
in more detail in Section 7.5 “Program Memory
Modes and the External Memory Bus”.
7.1
External Memory Bus Control
The operation of the interface is controlled by the
MEMCON register (Register 7-1). This register is
available in all program memory operating modes
except Microcontroller mode. In this mode, the register
is disabled and cannot be written to.
The WAIT bits allow for the addition of wait states to
external memory operations. The use of these bits is
discussed in Section 7.3 “Wait States”.
The EBDIS bit (MEMCON<7>) controls the operation
of the bus and related port functions. Clearing EBDIS
enables the interface and disables the I/O functions of
the ports, as well as any other functions multiplexed to
those pins. Setting the bit enables the I/O ports and
other functions, but allows the interface to override
everything else on the pins when an external memory
operation is required. By default, the external bus is
always enabled and disables all other I/O.
The WM bits select the particular operating mode used
when the bus is operating in 16-bit Data Width mode.
These are discussed in more detail in Section 7.6
“16-bit Data Width Modes”. These bits have no effect
when an 8-bit Data Width mode is selected.
REGISTER 7-1:
MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER
R/W-0
EBDIS
U-0
—
R/W-0
WAIT1
R/W-0
WAIT0
U-0
—
U-0
—
R/W-0
WM1
R/W-0
WM0
bit7
bit0
bit 7
EBDIS: External Bus Disable bit
1= External bus enabled when microcontroller accesses external memory; otherwise, all
external bus drivers are mapped as I/O ports
0= External bus always enabled, I/O ports are disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
WAIT1:WAIT0: Table Reads and Writes Bus Cycle Wait Count bits
11= Table reads and writes will wait 0 TCY
10= Table reads and writes will wait 1 TCY
01= Table reads and writes will wait 2 TCY
00= Table reads and writes will wait 3 TCY
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
WM1:WM0: TBLWTOperation with 16-bit Data Bus Width Select bits
1x= Word Write mode: TABLAT0 and TABLAT1 word output, WRH active when
TABLAT1 written
01= Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB)
will activate
00= Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
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7.2.1
ADDRESS SHIFTING ON THE
EXTERNAL BUS
7.2
Address and Data Width
The PIC18F87J10 family of devices can be indepen-
dently configured for different address and data widths
on the same memory bus. Both address and data width
are set by configuration bits in the CONFIG3L register.
As configuration bits, this means that these options can
only be configured by programming the device and are
not controllable in software.
By default, the address presented on the external bus
is the value of the PC. In practical terms, this means
that addresses in the external memory device below
the top of on-chip memory are unavailable to the micro-
controller. To access these physical locations, the glue
logic between the microcontroller and the external
memory must somehow translate addresses.
The BW bit selects an 8-bit or 16-bit data bus width.
Setting this bit (default) selects a data width of 16 bits.
To simplify the interface, the external bus offers an
extension of Extended Microcontroller mode that
automatically performs address shifting. This feature is
controlled by the EASHFT configuration bit. Setting this
bit offsets addresses on the bus by the size of the
microcontroller’s on-chip program memory and sets
the bottom address at 0000h. This allows the device to
use the entire range of physical addresses of the
external memory.
The EMB1:EMB0 bits determine both the program
memory operating mode and the address bus width.
The available options are 20-bit (default), 16-bit and
12-bit, as well as Microcontroller mode (external bus
disabled). Selecting a 16-bit or 12-bit width makes a
corresponding number of high-order lines available for
I/O functions; these pins are no longer affected by the
setting of the EBDIS bit. For example, selecting a 16-bit
Address mode (EMB1:EMB0 = 10) disables A19:A16
and allows PORTH<3:0> to function without interrup-
tions from the bus. Using the smaller address widths
allows users to tailor the memory bus to the size of the
external memory space for a particular design while
freeing up pins for dedicated I/O operation.
7.2.2
21-BIT ADDRESSING
As an extension of 20-bit address width operation, the
external memory bus can also fully address a 2-Mbyte
memory space. This is done by using the Bus Address
Bit 0 (BA0) control line as the Least Significant bit of the
address. The UB and LB control signals may also be
used with certain memory devices to select the upper
and lower bytes within a 16-bit wide data word.
Because the EMB bits have the effect of disabling pins
for memory bus operations, it is important to always
select an address width at least equal to the data width.
If a 12-bit address width is used with a 16-bit data
width, the upper four bits of data will not be available on
the bus.
This addressing mode is available in both 8-bit and
certain 16-bit data width modes. Additional details are
provided in Section 7.6.3 “16-Bit Byte Select Mode”
and Section 7.7 “8-bit Mode”.
All combinations of address and data widths require
multiplexing of address and data information on the
same lines. The address and data multiplexing, as well
as I/O ports made available by the use of smaller
address widths, are summarized in Table 7-2.
TABLE 7-2:
Data Width
ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS
Multiplexed Data and
Address Lines (and
Address-Only
Lines (and
Ports Available
for I/O
Address Width
Corresponding Ports) Corresponding Ports)
AD11:AD8
(PORTE<3:0>)
PORTE<7:4>,
All of PORTH
12-bit
16-bit
AD15:AD8
AD7:AD0
All of PORTH
8-bit
(PORTE<7:0>)
(PORTD<7:0>)
A19:A16, AD15:AD8
(PORTH<3:0>,
20-bit
—
PORTE<7:0>)
16-bit
20-bit
—
All of PORTH
—
AD15:AD0
(PORTD<7:0>,
PORTE<7:0>)
16-bit
A19:A16
(PORTH<3:0>)
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If the device fetches or accesses external memory
while EBDIS = 1, the pins will switch to external bus. If
the EBDIS bit is set by a program executing from exter-
nal memory, the action of setting the bit will be delayed
until the program branches into the internal memory. At
that time, the pins will change from external bus to I/O
ports.
7.3
Wait States
While it may be assumed that external memory devices
will operate at the microcontroller clock rate, this is
often not the case. In fact, many devices require longer
times to write or retrieve data than the time allowed by
the execution of table read or table write operations.
To compensate for this, the external memory bus can
be configured to add a fixed delay to each table opera-
tion using the bus. Wait states are enabled by setting
the WAIT configuration bit. When enabled, the amount
of delay is set by the WAIT1:WAIT0 bits
(MEMCON<5:4>). The delay is based on multiples of
microcontroller instruction cycle time and are added
following the instruction cycle when the table operation
is executed. The range is from no delay to 3 TCY
(default value).
If the device is executing out of internal memory when
EBDIS = 0, the memory bus address/data and control
pins will not be active. They will go to a state where the
active address/data pins are tri-state; the CE, OE,
WRH, WRL, UB and LB signals are ‘1’ and ALE and
BA0 are ‘0’. Note that only those pins associated with
the current address width are forced to tri-state; the
other pins continue to function as I/O. In the case of
16-bit address width, for example, only AD<15:0>
(PORTD and PORTE) are affected; A19:A16
(PORTH<3:0>) continue to function as I/O.
7.4
Port Pin Weak Pull-ups
In all external memory modes, the bus takes priority
over any other peripherals that may share pins with it.
This includes the Parallel Slave Port and serial commu-
nications modules which would otherwise take priority
over the I/O port.
With the exception of the upper address lines,
A19:A16, the pins associated with the external memory
bus are equipped with weak pull-ups. The pull-ups are
controlled by the upper three bits of the PORTG
register. They are named RDPU, REPU and RJPU and
control pull-ups on PORTD, PORTE and PORTJ,
respectively. Setting one of these bits enables the
corresponding pull-ups for that port. All pull-ups are
disabled by default on all device Resets.
7.6
16-bit Data Width Modes
In 16-bit Data Width mode, the external memory
interface can be connected to external memories in
three different configurations:
• 16-bit Byte Write
• 16-bit Word Write
• 16-bit Byte Select
7.5
Program Memory Modes and the
External Memory Bus
The PIC18F87J10 family of devices are capable of
operating in one of two program memory modes, using
combinations of on-chip and external program memory.
The functions of the multiplexed port pins depend on
the program memory mode selected, as well as the
setting of the EBDIS bit.
The configuration to be used is determined by the
WM1:WM0 bits in the MEMCON register
(MEMCON<1:0>). These three different configurations
allow the designer maximum flexibility in using both
8-bit and 16-bit devices with 16-bit data.
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits AD<15:0> are avail-
able on the external memory interface bus. Following
the address latch, the Output Enable signal (OE) will
enable both bytes of program memory at once to form
a 16-bit instruction word. The Chip Enable signal (CE)
is active at any time that the microcontroller accesses
external memory, whether reading or writing; it is
inactive (asserted high) whenever the device is in
Sleep mode.
In Microcontroller Mode, the bus is not active and the
pins have their port functions only. Writes to the
MEMCOM register are not permitted. The Reset value
of EBDIS (‘0’) is ignored and EMB pins behave as I/O
ports.
In Extended Microcontroller Mode, the external
program memory bus shares I/O port functions on the
pins. When the device is fetching or doing table
read/table write operations on the external program
memory space, the pins will have the external bus
function.
In Byte Select mode, JEDEC standard Flash memories
will require BA0 for the byte address line and one I/O
line to select between Byte and Word mode. The other
16-bit modes do not need BA0. JEDEC standard static
RAM memories will use the UB or LB signals for byte
selection.
If the device is fetching and accessing internal program
memory locations only, the EBDIS control bit will
change the pins from external memory to I/O port
functions. When EBDIS = 0, the pins function as the
external bus. When EBDIS = 1, the pins function as I/O
ports.
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During a TBLWTinstruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
7.6.1
16-BIT BYTE WRITE MODE
Figure 7-1 shows an example of 16-bit Byte Write
mode for PIC18F87J10 family devices. This mode is
used for two separate 8-bit memories connected for
16-bit operation. This generally includes basic EPROM
and Flash devices. It allows table writes to byte-wide
external memories.
FIGURE 7-1:
16-BIT BYTE WRITE MODE EXAMPLE
D<7:0>
(MSB)
A<x:0>
(LSB)
PIC18F8XJ10
AD<7:0>
A<19:0>
D<15:8>
373
373
A<x:0>
D<7:0>
D<7:0>
CE
D<7:0>
CE
AD<15:8>
ALE
(2)
(2)
OE WR
OE WR
(1)
A<19:16>
CE
OE
WRH
WRL
Address Bus
Data Bus
Control Lines
Note 1: Upper order address lines are used only for 20-bit address widths.
2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
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During a TBLWT cycle to an odd address
(TBLPTR<0> = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD15:AD0 bus.
7.6.2
16-BIT WORD WRITE MODE
Figure 7-2 shows an example of 16-bit Word Write
mode for PIC18F65J10 devices. This mode is used for
word-wide memories which include some of the
EPROM and Flash-type memories. This mode allows
opcode fetches and table reads from all forms of 16-bit
memory and table writes to any type of word-wide
external memories. This method makes a distinction
between TBLWTcycles to even or odd addresses.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of the TBLPTR, but it is left unconnected.
Instead, the UB and LB signals are active to select both
bytes. The obvious limitation to this method is that the
table write must be done in pairs on a specific word
boundary to correctly write a word location.
During a TBLWT cycle to an even address
(TBLPTR<0> = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is
tri-stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 7-2:
16-BIT WORD WRITE MODE EXAMPLE
PIC18F8XJ10
AD<7:0>
A<20:1>
D<15:0>
JEDEC Word
EPROM Memory
373
A<x:0>
D<15:0>
CE
(2)
OE
WR
AD<15:8>
ALE
373
(1)
A<19:16>
CE
OE
WRH
Address Bus
Data Bus
Control Lines
Note 1: Upper order address lines are used only for 20-bit address widths.
2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
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Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
7.6.3
16-BIT BYTE SELECT MODE
Figure 7-3 shows an example of 16-bit Byte Select
mode. This mode allows table write operations to
word-wide external memories with byte selection
capability. This generally includes both word-wide
Flash and SRAM devices.
During a TBLWTcycle, the TABLAT data is presented
on the upper and lower byte of the AD15:AD0 bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written, based on the Least
Significant bit of the TBLPTR register.
FIGURE 7-3:
16-BIT BYTE SELECT MODE EXAMPLE
PIC18F8XJ10
AD<7:0>
A<20:1>
373
373
JEDEC Word
FLASH Memory
A<x:1>
D<15:0>
D<15:0>
(3)
138
CE
A0
AD<15:8>
ALE
(1)
BYTE/WORD OE WR
(2)
A<19:16>
OE
WRH
WRL
A<20:1>
JEDEC Word
A<x:1>
SRAM Memory
BA0
I/O
D<15:0>
D<15:0>
CE
LB
LB
(1)
UB
OE WR
UB
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
2: Upper order address lines are used only for 20-bit address width.
3: Demultiplexing is only required when multiple memory devices are accessed.
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7.6.4
16-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 7-4 and Figure 7-5.
FIGURE 7-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
0Ch
A<19:16>
CF33h
9256h
AD<15:0>
CE
ALE
OE
Opcode Fetch
TBLRD *
from 000100h
Opcode Fetch
MOVLW55h
from 000102h
TBLRD92h
from 199E67h
Opcode Fetch
ADDLW55h
from 000104h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
TBLRDCycle 1
TBLRDCycle 2
MOVLW
FIGURE 7-5:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
00h
00h
A<19:16>
AD<15:0>
0E55h
0003h
3AAAh
3AABh
CE
ALE
OE
Memory
Cycle
Opcode Fetch
MOVLW55h
Opcode Fetch
SLEEP
Sleep Mode, Bus Inactive
from 007554h
from 007556h
Instruction
Execution
INST(PC – 2)
SLEEP
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will enable one byte of program memory for a portion of
the instruction cycle, then BA0 will change and the
second byte will be enabled to form the 16-bit instruc-
tion word. The Least Significant bit of the address, BA0,
must be connected to the memory devices in this
mode. The Chip Enable signal (CE) is active at any
time that the microcontroller accesses external
memory, whether reading or writing; it is inactive
(asserted high) whenever the device is in Sleep mode.
7.7
8-bit Mode
In 8-bit Data Width mode, the external memory bus
operates only in Multiplexed mode; that is, data shares
the 8 Least Significant bits of the address bus.
Figure 7-6 shows an example of 8-bit Multiplexed
mode for 80-pin devices. This mode is used for a single
8-bit memory connected for 16-bit operation. The
instructions will be fetched as two 8-bit bytes on a
shared data/address bus. The two bytes are sequen-
tially fetched within one instruction cycle (TCY).
Therefore, the designer must choose external memory
devices according to timing calculations based on
1/2 TCY (2 times the instruction rate). For proper mem-
ory speed selection, glue logic propagation delay times
must be considered, along with setup and hold times.
This generally includes basic EPROM and Flash
devices. It allows table writes to byte-wide external
memories.
During a TBLWTinstruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate level of the BA0
control line is strobed on the LSb of the TBLPTR.
The Address Latch Enable (ALE) pin indicates that the
address bits AD<15:0> are available on the external
memory interface bus. The Output Enable signal (OE)
FIGURE 7-6:
8-BIT MULTIPLEXED MODE EXAMPLE
D<7:0>
PIC18F8XJ10
AD<7:0>
A<19:0>
A<x:1>
373
ALE
A0
D<15:8>
D<7:0>
CE
(1)
AD<15:8>
(1)
A<19:16>
(2)
OE WR
BA0
CE
OE
WRL
Address Bus
Data Bus
Control Lines
Note 1: Upper order address bits are only used 20-bit address width. The upper AD byte is used for all
address widths except 8-bit.
2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
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7.7.1
8-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 7-7 and Figure 7-8.
FIGURE 7-7:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
0Ch
CFh
A<19:16>
AD<15:8>
AD<7:0>
CE
33h
92h
ALE
OE
Opcode Fetch
TBLRD *
from 000100h
Opcode Fetch
MOVLW55h
from 000102h
TBLRD92h
from 199E67h
Opcode Fetch
ADDLW55h
from 000104h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
TBLRDCycle 1
TBLRDCycle 2
MOVLW
FIGURE 7-8:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
00h
00h
A<19:16>
AD<15:8>
AD<7:0>
3Ah
0Eh 55h
3Ah
00h 03h
AAh
ABh
BA0
CE
ALE
OE
Memory
Cycle
Opcode Fetch
MOVLW55h
Opcode Fetch
Sleep Mode, Bus Inactive
SLEEP
from 007554h
from 007556h
Instruction
Execution
INST(PC – 2)
SLEEP
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7.8
Operation in Power-Managed
Modes
In alternate power-managed Run modes, the external
bus continues to operate normally. If a clock source
with a lower speed is selected, bus operations will run
at that speed. In these cases, excessive access times
for the external memory may result if wait states have
been enabled and added to external memory opera-
tions. If operations in a lower power Run mode are
anticipated, users should provide in their applications
for adjusting memory access times at the lower clock
speeds.
In Sleep and Idle modes, the microcontroller core does
not need to access data; bus operations are
suspended. The state of the external bus is frozen, with
the address/data pins and most of the control pins hold-
ing at the same state they were in when the mode was
invoked. The only potential changes are the CE, LB
and UB pins, which are held at logic high.
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NOTES:
DS39663A-page 96
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EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8.0
8.1
8 x 8 HARDWARE MULTIPLIER
Introduction
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
MOVF
MULWF
ARG1, W
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
BTFSC
SUBWF
ARG2, SB
PRODH, F
;
- ARG1
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
8.2
Operation
Example 8-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the argu-
ments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
TABLE 8-1:
Routine
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Program
Memory
(Words)
Time
Cycles
(Max)
Multiply Method
@ 40 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 µs
100 ns
9.1 µs
600 ns
24.2 µs
2.8 µs
25.4 µs
4.0 µs
27.6 µs
400 ns
36.4 µs
2.4 µs
69 µs
1 µs
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91 µs
6 µs
Without hardware multiply
Hardware multiply
21
28
52
35
242
28
254
40
96.8 µs
11.2 µs
102.6 µs
16.0 µs
242 µs
28 µs
254 µs
40 µs
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
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Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
16
= (ARG1H • ARG2H • 2 ) +
(ARG1H • ARG2L • 2 ) +
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 2 ) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
8
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
8
16
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
)
16
(ARG1H • ARG2H • 2 ) +
8
(ARG1H • ARG2L • 2 ) +
8
(ARG1L • ARG2H • 2 ) +
EXAMPLE 8-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
(ARG1L • ARG2L)
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1L, W
ARG2H
; ARG1L * ARG2H->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L->
; PRODH:PRODL
;
; Add cross
; products
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
;
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
ARG1H, W
SUBWFB RES3
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
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When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PICmicro® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
0008h in Compatibility mode.
9.0
INTERRUPTS
Members of the PIC18F87J10 family of devices have
multiple interrupt sources and an interrupt priority fea-
ture that allows most interrupt sources to be assigned
a high priority level or a low priority level. The high
priority interrupt vector is at 0008h and the low priority
interrupt vector is at 0018h. High priority interrupt
events will interrupt any low priority interrupts that may
be in progress.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are not
processed while high priority interrupts are in progress.
There are thirteen registers which are used to control
interrupt operation. These registers are:
• RCON
• INTCON
• INTCON2
• INTCON3
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bits must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
• PIR1, PIR2, PIR3
• PIE1, PIE2, PIE3
• IPR1, IPR2, IPR3
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the
assembler/compiler to automatically take care of the
placement of these bits within the specified register.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
In general, interrupt sources have three bits to control
their operation. They are:
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Note:
Do not use the MOVFFinstruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
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FIGURE 9-1:
PIC18F87J10 FAMILY INTERRUPT LOGIC
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
Interrupt to CPU
Vector to Location
0008h
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
GIEH/GIE
PIR2<7:6, 3:0>
PIE2<7:6, 3:0>
IPR2<7:6, 3:0>
IPEN
PIR3<7, 0>
PIE3<7, 0>
IPR3<7, 0>
IPEN
GIEL/PEIE
IPEN
High Priority Interrupt Generation
Low Priority Interrupt Generation
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
PIR2<7:6, 3:0>
PIE2<7:6, 3:0>
IPR2<7:6, 3:0>
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
IPEN
PIR3<7, 0>
PIE3<7, 0>
IPR3<7, 0>
RBIF
RBIE
RBIP
GIEH/GIE
GIEL/PEIE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
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9.1
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
REGISTER 9-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF
GIE/GIEH PEIE/GIEL TMR0IE
bit 7
INT0IE
TMR0IF
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN = 1:
1= Enables all high priority interrupts
0= Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low priority peripheral interrupts
0= Disables all low priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Note:
A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
RBPU
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBIP
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT3IP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG3: External Interrupt 3 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
INT3IP: INT3 External Interrupt Priority bit
1= High priority
0= Low priority
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software should
ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This
feature allows for software polling.
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REGISTER 9-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
INT3IF
R/W-0
INT2IF
R/W-0
INT1IF
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
INT3IE: INT3 External Interrupt Enable bit
1= Enables the INT3 external interrupt
0= Disables the INT3 external interrupt
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
INT3IF: INT3 External Interrupt Flag bit
1= The INT3 external interrupt occurred (must be cleared in software)
0= The INT3 external interrupt did not occur
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared in software)
0= The INT2 external interrupt did not occur
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared in software)
0= The INT1 external interrupt did not occur
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows for software polling.
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9.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
PSPIF
R/W-0
ADIF
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
RC1IF: EUSART1 Receive Interrupt Flag bit
1= The EUSART1 receive buffer, RCREGx, is full (cleared when RCREGx is read)
0= The EUSART1 receive buffer is empty
TX1IF: EUSART1 Transmit Interrupt Flag bit
1= The EUSART1 transmit buffer, TXREGx, is empty (cleared when TXREGx is written)
0= The EUSART1 transmit buffer is full
SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
CCP1IF: ECCP1 Interrupt Flag bit
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
OSCFIF
bit 7
R/W-0
CMIF
U-0
—
U-0
—
R/W-0
U-0
—
R/W-0
R/W-0
BCL1IF
TMR3IF
CCP2IF
bit 0
bit 7
bit 6
OSCFIF: Oscillator Fail Interrupt Flag bit
1= Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0= Device clock operating
CMIF: Comparator Interrupt Flag bit
1= Comparator input has changed (must be cleared in software)
0= Comparator input has not changed
bit 5-4 Unimplemented: Read as ‘0’
bit 3
BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module)
1= A bus collision occurred (must be cleared in software)
0= No bus collision occurred
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed (must be cleared in software)
0= TMR3 register did not overflow
bit 0
CCP2IF: ECCP2 Interrupt Flag bit
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module)
1= A bus collision occurred (must be cleared in software)
0= No bus collision occurred
RC2IF: EUSART2 Receive Interrupt Flag bit
1= The EUSART2 receive buffer, RCREGx, is full (cleared when RCREGx is read)
0= The EUSART2 receive buffer is empty
TX2IF: EUSART2 Transmit Interrupt Flag bit
1= The EUSART2 transmit buffer, TXREGx, is empty (cleared when TXREGx is written)
0= The EUSART2 transmit buffer is full
TMR4IF: TMR4 to PR4 Match Interrupt Flag bit
1= TMR4 to PR4 match occurred (must be cleared in software)
0= No TMR4 to PR4 match occurred
CCP5IF: CCP5 Interrupt Flag bit
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
CCP4IF: CCP4 Interrupt Flag bit
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 0
CCP3IF: ECCP3 Interrupt Flag bit
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 9-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
PSPIE
R/W-0
ADIE
R/W-0
RC1IE
R/W-0
TX1IE
R/W-0
R/W-0
R/W-0
R/W-0
TMR1IE
bit 0
SSP1IE
CCP1IE
TMR2IE
bit 7
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RC1IE: EUSART1 Receive Interrupt Enable bit
1= Enables the EUSART1 receive interrupt
0= Disables the EUSART1 receive interrupt
TX1IE: EUSART1 Transmit Interrupt Enable bit
1= Enables the EUSART1 transmit interrupt
0= Disables the EUSART1 transmit interrupt
SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit
1= Enables the MSSP1 interrupt
0= Disables the MSSP1 interrupt
CCP1IE: ECCP1 Interrupt Enable bit
1= Enables the ECCP1 interrupt
0= Disables the ECCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
OSCFIE
bit 7
R/W-0
CMIE
U-0
—
U-0
—
R/W-0
U-0
—
R/W-0
R/W-0
BCL1IE
TMR3IE
CCP2IE
bit 0
bit 7
bit 6
OSCFIE: Oscillator Fail Interrupt Enable bit
1= Enabled
0= Disabled
CMIE: Comparator Interrupt Enable bit
1= Enabled
0= Disabled
bit 5-4
bit 3
Unimplemented: Read as ‘0’
BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module)
1= Enabled
0= Disabled
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enabled
0= Disabled
bit 0
CCP2IE: ECCP2 Interrupt Enable bit
1= Enabled
0= Disabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit
1= Enabled
0= Disabled
BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1= Enabled
0= Disabled
RC2IE: EUSART2 Receive Interrupt Enable bit
1= Enabled
0= Disabled
TX2IE: EUSART2 Transmit Interrupt Enable bit
1= Enabled
0= Disabled
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1= Enabled
0= Disabled
CCP5IE: CCP5 Interrupt Enable bit
1= Enabled
0= Disabled
CCP4IE: CCP4 Interrupt Enable bit
1= Enabled
0= Disabled
CCP3IE: ECCP3 Interrupt Enable bit
1= Enabled
0= Disabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP
R/W-1
ADIP
R/W-1
RC1IP
R/W-1
TX1IP
R/W-1
R/W-1
R/W-1
R/W-1
TMR1IP
bit 0
SSP1IP
CCP1IP
TMR2IP
bit 7
bit 7
bit 6
bit 5
bit 4
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit
1= High priority
0= Low priority
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RC1IP: EUSART1 Receive Interrupt Priority bit
1= High priority
0= Low priority
TX1IP: EUSART1 Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
SSP1IP: Master Synchronous Serial Port 1 Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: ECCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
OSCFIP
bit 7
R/W1
CMIP
U-0
—
U-0
—
R/W-1
U-0
—
R/W-1
R/W-1
BCL1IP
TMR3IP
CCP2IP
bit 0
bit 7
bit 6
OSCFIP: Oscillator Fail Interrupt Priority bit
1= High priority
0= Low priority
CMIP: Comparator Interrupt Priority bit
1= High priority
0= Low priority
bit 5-4
bit 3
Unimplemented: Read as ‘0’
BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module)
1= High priority
0= Low priority
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
bit 0
CCP2IP: ECCP2 Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
R/W-1
R/W-1
RC2IP
R/W-1
TX2IP
R/W-1
R/W-1
R/W-1
R/W-1
SSP2IP
BCL2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit
1= High priority
0= Low priority
BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)
1= High priority
0= Low priority
RC2IP: EUSART2 Receive Interrupt Priority bit
1= High priority
0= Low priority
TX2IP: EUSART2 Transmit Interrupt Priority bit
1= High priority
0= Low priority
TMR4IE: TMR4 to PR4 Interrupt Priority bit
1= High priority
0= Low priority
CCP5IP: CCP5 Interrupt Priority bit
1= High priority
0= Low priority
CCP4IP: CCP4 Interrupt Priority bit
1= High priority
0= Low priority
CCP3IP: ECCP3 Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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9.5
RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 9-13: RCON: RESET CONTROL REGISTER
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4
bit 3
bit 2
bit 1
bit 0
RI: RESETInstruction Flag bit
For details of bit operation, see Register 4-1.
TO: Watchdog Timer Time-out Flag bit
For details of bit operation, see Register 4-1.
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-1.
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-1.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
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9.6
INTn Pin Interrupts
9.7
TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Flag bit, INTxIF, must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt.
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh → 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt prior-
ity bit, TMR0IP (INTCON2<2>). See Section 11.0
“Timer0 Module” for further details on the Timer0
module.
9.8
PORTB Interrupt-on-Change
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from the power-managed
modes if bit INTxIE was set prior to going into
power-managed modes. If the Global Interrupt Enable
bit, GIE, is set, the processor will branch to the interrupt
vector following wake-up.
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the interrupt priority bits,
INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and
INT3IP (INTCON2<1>). There is no priority bit
associated with INT0. It is always a high priority
interrupt source.
9.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 5.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 9-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 9-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
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10.1 I/O Port Pin Capabilities
10.0 I/O PORTS
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than VDD input levels.
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
10.1.1
PIN OUTPUT DRIVE
The output pin drive strengths vary for groups of pins
intended to meet the needs for a variety of applications.
PORTB and PORTC are designed to drive higher
loads, such as LEDs. The external memory interface
ports (PORTD, PORTE and PORTJ) are designed to
drive medium loads. All other ports are designed for
small loads, typically indication only. Table 10-1 sum-
marizes the output capabilities. Refer to Section 26.0
“Electrical Characteristics” for more details.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• Port register (reads the levels on the pins of the
device)
• LAT register (output latch)
The Data Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
TABLE 10-1: OUTPUT DRIVE LEVELS
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
Port
Drive
Description
PORTA
PORTF
PORTG
PORTH(1)
PORTD
PORTE
PORTJ(1)
PORTB
PORTC
Minimum Intended for indication.
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
RD LAT
Medium Sufficient drive levels for
external memory interfacing
as well as indication.
Data
Bus
D
Q
WR LAT
or Port
I/O pin(1)
CK
Data Latch
High
Suitable for direct LED drive
levels.
D
Q
Note 1: These ports are not available on 64-pin
devices.
WR TRIS
RD TRIS
CK
TRIS Latch
Input
Buffer
Q
D
EN
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
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10.1.2
INPUT PINS AND VOLTAGE
CONSIDERATIONS
10.2 PORTA, TRISA and
LATA Registers
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V, a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
can only tolerate voltages up to VDD. Voltage excursions
beyond VDD on these pins should be avoided.
Table 10-2 summarizes the input capabilities. Refer to
Section 26.0 “Electrical Characteristics” for more
details.
PORTA is a 6-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Data Latch register (LATA) is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
TABLE 10-2: INPUT VOLTAGE LEVELS
Tolerated
Port or Pin
Description
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The other
PORTA pins are multiplexed with the analog VREF+ and
VREF- inputs. The operation of pins RA5:RA0 as A/D
converter inputs is selected by clearing or setting the
PCFG3:PCFG0 control bits in the ADCON1 register.
Input
PORTA<5:0>
PORTC<1:0>
PORTF<6:1>
PORTH<7:4>(1)
PORTB<7:0>
PORTC<7:2>
PORTD<7:0>
PORTE<7:0>
PORTF<7>
VDD
Only VDD input levels
tolerated.
Note:
RA5 and RA3:RA0 are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
5.5V
Tolerates input levels
above VDD, useful for
most standard logic.
The RA4/T0CKI pin is a Schmitt Trigger input. All other
PORTA pins have TTL input levels and full CMOS
output drivers.
PORTG<4:0>
PORTH<3:0>(1)
PORTJ<7:0>(1)
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Note 1: These ports are not available on 64-pin
devices.
EXAMPLE 10-1:
INITIALIZING PORTA
CLRF
PORTA
LATA
07h
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
CLRF
MOVLW
MOVWF
MOVWF
MOVWF
MOVLW
; Configure A/D
ADCON1 ; for digital inputs
07h
CMCON
0CFh
; Configure comparators
; for digital input
; Value used to
; initialize data
; direction
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
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TABLE 10-3: PORTA FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
RA0/AN0
Function
I/O
Description
RA0
0
1
O
I
DIG
TTL
ANA
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
AN0
RA1
I
A/D input channel 0. Default input configuration on POR; does not
affect digital output.
RA1/AN1
0
1
O
I
DIG
TTL
ANA
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
AN1
RA2
I
A/D input channel 1. Default input configuration on POR; does not
affect digital output.
RA2/AN2/VREF-
0
1
1
O
I
DIG
TTL
ANA
LATA<2> data output; not affected by analog input. Disabled when
CVREF output enabled.
PORTA<2> data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.
AN2
I
A/D input channel 2 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
VREF-
RA3
1
0
1
1
1
0
1
x
0
1
1
I
O
I
ANA
DIG
TTL
ANA
ANA
DIG
ST
A/D and Comparator low reference voltage input.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3. Default input configuration on POR.
A/D high reference voltage input.
RA3/AN3/VREF+
AN3
VREF+
RA4
I
I
RA4/T0CKI
RA5/AN4
O
I
LATA<4> data output.
PORTA<4> data input; default configuration on POR.
Timer0 clock input.
T0CKI
RA5
I
ST
O
I
DIG
TTL
ANA
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D input channel 4. Default configuration on POR.
AN4
I
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
—
—
—
—
—
—
—
—
RA5
RA4
RA3
RA2
RA1
RA0
52
52
52
50
LATA
LATA5
TRISA5
VCFG1
LATA4
TRISA4
VCFG0
LATA3
TRISA3
PCFG3
LATA2
TRISA2
PCFG2
LATA1
TRISA1
PCFG1
LATA0
TRISA0
PCFG0
TRISA
ADCON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
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Four of the PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON<0>).
10.3 PORTB, TRISB and
LATB Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
All pins on PORTB are digital only and tolerate voltages
up to 5.5V.
This interrupt can wake the device from
power-managed modes. The user, in the Interrupt
Service Routine, can clear the interrupt in the following
manner:
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
b) Clear flag bit RBIF.
EXAMPLE 10-2:
INITIALIZING PORTB
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
CLRF
LATB
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
MOVLW
MOVWF
0CFh
TRISB
For 80-pin devices, RB3 can be configured as the
alternate peripheral pin for the ECCP2 module and
Enhanced PWM output 2A by clearing the CCP2MX
configuration bit. This applies only to 80-pin devices
operating in Extended Microcontroller mode. If the
device is in Microcontroller mode, the alternate
assignment for ECCP2 is RE7. As with other ECCP2
configurations, the user must ensure that the TRISB<3>
bit is set appropriately for the intended operation.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
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TABLE 10-5: PORTB FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RB0/INT0/FLT0
RB0
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
0
O
I
DIG LATB<0> data output.
TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
INT0
FLT0
RB1
I
ST
ST
External interrupt 0 input.
I
Enhanced PWM Fault input (ECCP1 module); enabled in software.
RB1/INT1
RB2/INT2
O
I
DIG LATB<1> data output.
TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
INT1
RB2
I
ST
External interrupt 1 input.
O
I
DIG LATB<2> data output.
TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.
INT2
RB3
I
ST
External interrupt 2 input.
RB3/INT3/
ECCP2/P2A
O
I
DIG LATB<3> data output.
TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.
INT3
I
ST
DIG CCP2 Compare output and CCP2 PWM output; takes priority over port data.
ST CCP2 Capture input.
External interrupt 3 input.
(1)
ECCP2
O
I
(1)
P2A
O
DIG ECCP2 Enhanced PWM output, channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RB4/KBI0
RB4
0
1
O
I
DIG LATB<4> data output.
TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.
TTL Interrupt on pin change.
KBI0
RB5
I
RB5/KBI1
0
1
O
I
DIG LATB<5> data output.
TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.
TTL Interrupt on pin change.
KBI1
RB6
I
RB6/KBI2/PGC
0
1
1
x
0
1
1
x
x
O
I
DIG LATB<6> data output.
TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.
KBI2
PGC
RB7
I
TTL Interrupt on pin change.
(2)
I
ST
Serial execution (ICSP™) clock input for ICSP and ICD operation.
RB7/KBI3/PGD
O
I
DIG LATB<7> data output.
TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.
TTL Interrupt on pin change.
KBI3
PGD
I
(2)
O
I
DIG Serial execution data output for ICSP and ICD operation.
(2)
ST
Serial execution data input for ICSP and ICD operation.
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignment for ECCP2/P2A when the CCP2MX configuration bit is cleared (Extended Microcontroller mode,
80-pin devices only). Default assignment is RC1.
2: All other pin functions are disabled when ICSP or ICD are enabled.
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TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
52
52
52
49
49
49
LATB
LATB7
TRISB7
LATB6
TRISB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
TRISB
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
INTCON
INTCON2
INTCON3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT1IP INT3IE INT2IE INT1IE INT3IF
RBIE
TMR0IF
INT0IF
INT3IP
INT2IF
RBIF
RBIP
RBPU
INT2IP
INT1IF
Legend: Shaded cells are not used by PORTB.
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10.4 PORTC, TRISC and
LATC Registers
Note:
These pins are configured as digital inputs
on any device Reset.
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
Only PORTC pins RC2 through RC7 are digital only
pins and can tolerate input voltages up to 5.5V.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3:
INITIALIZING PORTC
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
CLRF
LATC
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
MOVLW
MOVWF
0CFh
PORTC is multiplexed with several peripheral functions
(Table 10-7). The pins have Schmitt Trigger input
buffers. RC1 is normally configured by configuration bit
CCP2MX as the default peripheral pin for the ECCP2
module and enhanced PWM output P2A (default state,
CCP2MX = 1).
TRISC
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
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TABLE 10-7: PORTC FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RC0/T1OSO/
T13CKI
RC0
0
1
x
O
I
DIG
ST
LATC<0> data output.
PORTC<0> data input.
T1OSO
O
ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables
digital I/O.
T13CKI
RC1
1
0
1
x
I
O
I
ST
DIG
ST
Timer1/Timer3 counter input.
LATC<1> data output.
RC1/T1OSI/
ECCP2/P2A
PORTC<1> data input.
T1OSI
I
ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables
digital I/O.
(1)
ECCP2
0
1
0
O
I
DIG
ST
CCP2 Compare output and CCP2 PWM output; takes priority over port data.
CCP2 Capture input.
(1)
P2A
O
DIG
ECCP2 Enhanced PWM output, channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RC2/ECCP1/
P1A
RC2
0
1
0
1
0
O
I
DIG
ST
LATC<2> data output.
PORTC<2> data input.
ECCP1
O
I
DIG
ST
CCP1 Compare output and CCP1 PWM output; takes priority over port data.
CCP1 Capture input.
P1A
RC3
O
DIG
ECCP1 Enhanced PWM output, channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RC3/SCK1/
SCL1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
1
1
1
O
I
DIG
ST
LATC<3> data output.
PORTC<3> data input.
SCK1
SCL1
RC4
O
I
DIG
ST
SPI™ clock output (MSSP1 module); takes priority over port data.
SPI clock input (MSSP1 module).
2
O
I
DIG
ST
I C™ clock output (MSSP1 module); takes priority over port data.
2
I C clock input (MSSP1 module); input type depends on module setting.
RC4/SDI1/
SDA1
O
I
DIG
ST
LATC<4> data output.
PORTC<4> data input.
SDI1
I
ST
SPI data input (MSSP1 module).
2
SDA1
O
I
DIG
ST
I C data output (MSSP1 module); takes priority over port data.
2
I C data input (MSSP1 module); input type depends on module setting.
RC5/SDO1
RC5
O
I
DIG
ST
LATC<5> data output.
PORTC<5> data input.
SDO1
RC6
O
O
I
DIG
DIG
ST
SPI data output (MSSP1 module); takes priority over port data.
LATC<6> data output.
RC6/TX1/CK1
PORTC<6> data input.
TX1
CK1
O
O
DIG
DIG
Synchronous serial data output (EUSART1 module); takes priority over port data.
Synchronous serial data input (EUSART1 module). User must configure as
an input.
1
0
1
1
1
I
O
I
ST
DIG
ST
Synchronous serial clock input (EUSART1 module).
LATC<7> data output.
RC7/RX1/DT1
RC7
PORTC<7> data input.
RX1
DT1
I
ST
Asynchronous serial receive data input (EUSART1 module).
O
DIG
Synchronous serial data output (EUSART1 module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART1 module). User must configure as
an input.
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Default assignment for ECCP2/P2A when CCP2MX configuration bit is set.
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TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
52
52
52
LATC
LATC7
LATBC6
LATC5
LATCB4
LATC3
LATC2
LATC1
LATC0
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
Legend: Shaded cells are not used by PORTC.
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PORTD can also be configured to function as an 8-bit
wide, parallel microprocessor port by setting the
PSPMODE control bit (PSPCON<4>). In this mode,
parallel port data takes priority over other digital I/O (but
not the external memory interface). When the parallel
port is active, the input buffers are TTL. For more
information, refer to Section 10.11 “Parallel Slave
Port”.
10.5 PORTD, TRISD and
LATD Registers
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
All pins on PORTD are digital only and tolerate voltages
up to 5.5V.
EXAMPLE 10-4:
INITIALIZING PORTD
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
CLRF
LATD
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
0CFh
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
TRISD
Note:
These pins are configured as digital inputs
on any device Reset.
On 80-pin devices, PORTD is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled, by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
address/data bus (AD7:AD0). The TRISD bits are also
overridden.
Each of the PORTD pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit RDPU (PORTG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
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TABLE 10-9: PORTD FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RD0/AD0/PSP0
RD0
0
1
x
x
O
I
DIG
ST
LATD<0> data output.
PORTD<0> data input.
(2)
(1)
AD0
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 0 output.
(1)
External memory interface, data bit 0 input.
PSP0
RD1
O
I
PSP read output data (LATD<0>); takes priority over port data.
PSP write data input.
RD1/AD1/PSP1
RD2/AD2/PSP2
RD3/AD3/PSP3
0
1
x
x
x
x
0
1
x
x
x
x
0
1
x
x
x
x
0
1
x
x
x
x
0
0
1
x
x
x
x
1
1
1
O
I
LATD<1> data output.
PORTD<1> data input.
(2)
(1)
AD1
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 1 output.
(1)
External memory interface, data bit 1 input.
PSP1
RD2
O
I
PSP read output data (LATD<1>); takes priority over port data.
PSP write data input.
O
I
LATD<2> data output.
PORTD<2> data input.
(2)
(1)
AD2
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 2 output.
(1)
External memory interface, data bit 2 input.
PSP2
RD3
O
I
PSP read output data (LATD<2>); takes priority over port data.
PSP write data input.
O
I
LATD<3> data output.
PORTD<3> data input.
(2)
(1)
AD3
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 3 output.
(1)
External memory interface, data bit 3 input.
PSP3
RD4
O
I
PSP read output data (LATD<3>); takes priority over port data.
PSP write data input.
RD4/AD4/
PSP4/SDO2
O
I
LATD<4> data output.
PORTD<4> data input.
(2)
(1)
AD4
O
I
DIG
TTL
DIG
TTL
DIG
DIG
ST
External memory interface, address/data bit 4 output.
(1)
External memory interface, data bit 4 input.
PSP4
O
I
PSP read output data (LATD<4>); takes priority over port data.
PSP write data input.
SDO2
RD5
O
O
I
SPI™ data output (MSSP2 module); takes priority over port data.
LATD<5> data output.
RD5/AD5/
PSP5/SDI2/
SDA2
PORTD<5> data input.
(2)
(1)
AD5
O
I
DIG
TTL
DIG
TTL
ST
External memory interface, address/data bit 5 output.
(1)
External memory interface, data bit 5 input.
PSP5
O
I
PSP read output data (LATD<5>); takes priority over port data.
PSP write data input.
SDI2
I
SPI data input (MSSP2 module).
2
SDA2
O
I
DIG
ST
I C™ data output (MSSP2 module); takes priority over port data.
2
I C data input (MSSP2 module); input type depends on module
setting.
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: External memory interface I/O takes priority over all other digital and PSP I/O.
2: Available on 80-pin devices only.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 125
PIC18F87J10 FAMILY
TABLE 10-9: PORTD FUNCTIONS (CONTINUED)
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RD6/AD6/
PSP6/SCK2/
SCL2
RD6
0
1
x
x
x
x
0
1
0
1
O
I
DIG
ST
LATD<6> data output.
PORTD<6> data input.
(2)
(1)
AD6
O
I
DIG-3 External memory interface, address/data bit 6 output.
(1)
TTL
DIG
TTL
DIG
ST
External memory interface, data bit 6 input.
PSP6
SCK1
SCL1
O
I
PSP read output data (LATD<6>); takes priority over port data.
PSP write data input.
O
I
SPI™ clock output (MSSP2 module); takes priority over port data.
SPI clock input (MSSP2 module).
2
O
I
DIG
ST
I C™ clock output (MSSP2 module); takes priority over port data.
2
I C clock input (MSSP2 module); input type depends on module
setting.
RD7/AD7/
PSP7/SS2
RD7
0
1
x
x
x
x
x
O
I
DIG
ST
LATD<7> data output.
PORTD<7> data input.
(2)
(1)
AD7
O
I
DIG
TTL
DIG
TTL
TTL
External memory interface, address/data bit 7 output.
(1)
External memory interface, data bit 7 input.
PSP7
SS2
O
I
PSP read output data (LATD<7>); takes priority over port data.
PSP write data input.
I
Slave select input for SSP (MSSP2 module).
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: External memory interface I/O takes priority over all other digital and PSP I/O.
2: Available on 80-pin devices only.
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
RD7
LATD7
TRISD7
RDPU
RD6
LATD6
TRISD6
REPU
RD5
RD4
LATD4
TRISD4
RG4
RD3
LATD3
TRISD3
RG3
RD2
LATD2
TRISD2
RG2
RD1
LATD1
TRISD1
RG1
RD0
LATD0
TRISD0
RG0
52
52
52
52
LATD5
TRISD5
RJPU(1)
TRISD
PORTG
Legend: Shaded cells are not used by PORTD.
Note 1: Unimplemented on 64-pin devices; read as ‘0’.
DS39663A-page 126
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PORTE is also multiplexed with Enhanced PWM
outputs B and C for ECCP1 and ECCP3 and outputs B,
C and D for ECCP2. For all devices, their default
assignments are on PORTE<6:3>. On 80-pin devices,
the multiplexing for the outputs of ECCP1 and ECCP3
is controlled by the ECCPMX configuration bit. Clearing
this bit reassigns the P1B/P1C and P3B/P3C outputs to
PORTH.
10.6 PORTE, TRISE and
LATE Registers
PORTE is a 7-bit wide, bidirectional port. The corre-
sponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output (i.e.,
put the contents of the output latch on the selected pin).
All pins on PORTE are digital only and tolerate voltages
up to 5.5V.
For devices operating in Microcontroller mode, pin RE7
can be configured as the alternate peripheral pin for the
ECCP2 module and Enhanced PWM output 2A. This is
done by clearing the CCP2MX configuration bit.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
When the Parallel Slave Port is active on PORTD, three
of the PORTE pins (RE0, RE1 and RE2) are configured
as digital control inputs for the port. The control
functions are summarized in Table 10-11. The reconfig-
uration occurs automatically when the PSPMODE
control bit (PSPCON<4>) is set. Users must still make
certain the corresponding TRISE bits are set to
configure these pins as digital inputs.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note:
These pins are configured as digital inputs
on any device Reset.
EXAMPLE 10-5:
INITIALIZING PORTE
On 80-pin devices, PORTE is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled, by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTE is the high-order byte of the multiplexed
address/data bus (AD15:AD8). The TRISE bits are also
overridden.
CLRF
PORTE
LATE
03h
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
CLRF
MOVLW
MOVWF
TRISE
; Set RE<1:0> as inputs
; RE<7:2> as outputs
Each of the PORTE pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit REPU (PORTG<6>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
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Advance Information
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PIC18F87J10 FAMILY
TABLE 10-11: PORTE FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RE0/AD8/RD/
P2D
RE0
0
1
x
x
1
0
O
I
DIG
ST
LATE<0> data output.
PORTE<0> data input.
(3)
(2)
AD8
O
I
DIG
TTL
TTL
DIG
External memory interface, address/data bit 8 output.
(2)
External memory interface, data bit 8 input.
RD
I
Parallel Slave Port read enable control input.
P2D
O
ECCP2 Enhanced PWM output, channel D; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE1/AD9/WR/
P2C
RE1
0
1
x
x
1
0
O
I
DIG
ST
LATE<1> data output.
PORTE<1> data input.
(3)
(2)
AD9
O
I
DIG
TTL
TTL
DIG
External memory interface, address/data bit 9 output.
(2)
External memory interface, data bit 9 input.
WR
I
Parallel Slave Port write enable control input.
P2C
O
ECCP2 Enhanced PWM output, channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE2/AD10/CS/
P2B
RE2
0
1
x
x
1
0
O
I
DIG
ST
LATE<2> data output.
PORTE<2> data input.
(3)
(2)
AD10
O
I
DIG
TTL
TTL
DIG
External memory interface, address/data bit 10 output.
(2)
External memory interface, data bit 10 input.
CS
I
Parallel Slave Port chip select control input.
P2B
O
ECCP2 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE3/AD11/
P3C
RE3
0
1
x
x
0
O
I
DIG
ST
LATE<3> data output.
PORTE<3> data input.
(3)
(2)
AD11
O
I
DIG
TTL
DIG
External memory interface, address/data bit 11 output.
(2)
External memory interface, data bit 11 input.
(1)
P3C
O
ECCP3 Enhanced PWM output, channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE4/AD12/
P3B
RE4
0
1
x
x
0
O
I
DIG
ST
LATE<4> data output.
PORTE<4> data input.
(3)
(2)
AD12
O
I
DIG
TTL
DIG
External memory interface, address/data bit 12 output.
(2)
External memory interface, data bit 12 input.
(1)
P3B
O
ECCP3 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE5/AD13/
P1C
RE5
0
1
x
x
0
O
I
DIG
ST
LATE<5> data output.
PORTE<5> data input.
(3)
(2)
AD13
O
I
DIG
TTL
DIG
External memory interface, address/data bit 13 output.
(2)
External memory interface, data bit 13 input.
(1)
P1C
O
ECCP1 Enhanced PWM output, channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Default assignments for P1B/P1C and P3B/P3C when ECCPMX configuration bit is set (80-pin devices only).
2: External memory interface I/O takes priority over all other digital and PSP I/O.
3: Available on 80-pin devices only.
4: Alternate assignment for ECCP2/P2A when CCP2MX configuration bit is cleared (all devices in Microcontroller mode).
DS39663A-page 128
Advance Information
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TABLE 10-11: PORTE FUNCTIONS (CONTINUED)
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RE6/AD14/
P1B
RE6
0
1
x
x
0
O
I
DIG
ST
LATE<6> data output.
PORTE<6> data input.
(3)
(2)
AD14
O
I
DIG
TTL
DIG
External memory interface, address/data bit 14 output.
(2)
External memory interface, data bit 14 input.
(1)
P1B
O
ECCP1 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE7/AD15/
ECCP2/P2A
RE7
0
1
x
x
0
O
I
DIG
ST
LATE<7> data output.
PORTE<7> data input.
(3)
(2)
AD15
O
I
DIG
TTL
DIG
External memory interface, address/data bit 15 output.
(2)
External memory interface, data bit 15 input.
(4)
ECCP2
O
CCP2 compare output and CCP2 PWM output; takes priority over
port data.
1
0
I
ST
CCP2 capture input.
(4)
P2A
O
DIG
ECCP2 Enhanced PWM output, channel A; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Default assignments for P1B/P1C and P3B/P3C when ECCPMX configuration bit is set (80-pin devices only).
2: External memory interface I/O takes priority over all other digital and PSP I/O.
3: Available on 80-pin devices only.
4: Alternate assignment for ECCP2/P2A when CCP2MX configuration bit is cleared (all devices in Microcontroller mode).
TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
PORTE
LATE
RE7
RE6
RE5
RE4
LATE4
TRISE4
RG4
RE3
LATE3
TRISE3
RG3
RE2
LATE2
TRISE2
RG2
RE1
LATE1
TRISE1
RG1
RE0
LATE0
TRISE0
RG0
52
52
52
52
LATE7
TRISE7
RDPU
LATE6
TRISE6
REPU
LATE5
TRISE5
RJPU(1)
TRISE
PORTG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Unimplemented on 64-pin devices; read as ‘0’.
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Advance Information
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10.7 PORTF, LATF and TRISF Registers
Note 1: On device Resets, pins RF6:RF1 are
configured as analog inputs and are read
as ‘0’.
PORTF is a 7-bit wide, bidirectional port. The corre-
sponding data direction register is TRISF. Setting a
TRISF bit (= 1) will make the corresponding PORTF pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISF bit (= 0) will
make the corresponding PORTF pin an output (i.e., put
the contents of the output latch on the selected pin).
Only pin 7 of PORTF has no analog input; it is the only
pin that can tolerate voltages up to 5.5V.
2: To configure PORTF as digital I/O, turn off
comparators and set ADCON1 value.
EXAMPLE 10-6:
INITIALIZING PORTF
CLRF
PORTF
; Initialize PORTF by
; clearing output
; data latches
The Data Latch register (LATF) is also memory
mapped. Read-modify-write operations on the LATF
register read and write the latched output value for
PORTF.
CLRF
LATF
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
07h
CMCON
0Fh;
;
All pins on PORTF are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
; Turn off comparators
ADCON1 ; Set PORTF as digital I/O
0CEh
PORTF is multiplexed with several analog peripheral
functions, including the A/D converter and comparator
inputs, as well as the comparator outputs. Pins RF2
through RF6 may be used as comparator inputs or
outputs by setting the appropriate bits in the CMCON
register. To use RF3:RF6 as digital inputs, it is also
necessary to turn off the comparators.
; Value used to
; initialize data
; direction
; Set RF3:RF1 as inputs
; RF5:RF4 as outputs
; RF7:RF6 as inputs
MOVWF
TRISF
DS39663A-page 130
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TABLE 10-13: PORTF FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RF1/AN6/
C2OUT
RF1
0
1
1
0
0
1
1
0
0
1
1
O
I
DIG
ST
LATF<1> data output; not affected by analog input.
PORTF<1> data input; disabled when analog input enabled.
A/D input channel 6. Default configuration on POR.
Comparator 2 output; takes priority over port data.
LATF<2> data output; not affected by analog input.
PORTF<2> data input; disabled when analog input enabled.
A/D input channel 7. Default configuration on POR.
Comparator 1 output; takes priority over port data.
LATF<3> data output; not affected by analog input.
PORTF<3> data input; disabled when analog input enabled.
AN6
C2OUT
RF2
I
ANA
DIG
DIG
ST
O
O
I
RF2/AN7/
C1OUT
AN7
C1OUT
RF3
I
ANA
TTL
DIG
ST
O
O
I
RF3/AN8
RF4/AN9
AN8
RF4
I
ANA
A/D input channel 8 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
0
1
1
O
I
DIG
ST
LATF<4> data output; not affected by analog input.
PORTF<4> data input; disabled when analog input enabled.
AN9
RF5
I
ANA
A/D input channel 9 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
RF5/AN10/
CVREF
0
1
1
x
O
I
DIG
ST
LATF<5> data output; not affected by analog input. Disabled when
CVREF output enabled.
PORTF<5> data input; disabled when analog input enabled. Disabled
when CVREF output enabled.
AN10
CVREF
RF6
I
ANA
ANA
A/D input channel 10 and Comparator C1+ input. Default input
configuration on POR.
O
Comparator voltage reference output. Enabling this feature disables
digital I/O.
RF6/AN11
0
1
1
O
I
DIG
ST
LATF<6> data output; not affected by analog input.
PORTF<6> data input; disabled when analog input enabled.
AN11
RF7
I
ANA
A/D input channel 11 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
RF7/SS1
0
1
1
O
I
DIG
ST
LATF<7> data output.
PORTF<7> data input.
SS1
I
TTL
Slave select input for SSP (MSSP1 module).
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTF
LATF
RF7
LATF7
TRISF7
—
RF6
LATF6
TRISF6
—
RF5
RF4
RF3
LATF3
TRISF3
PCFG3
CIS
RF2
LATF2
TRISF2
PCFG2
CM2
RF1
LATF1
TRISF1
PCFG1
CM1
—
—
52
52
52
50
51
51
LATF5
TRISF5
VCFG1
C2INV
CVRR
LATF4
TRISF4
VCFG0
C1INV
CVRSS
TRISF
—
ADCON1
CMCON
CVRCON
PCFG0
CM0
CVR0
C2OUT
CVREN
C1OUT
CVROE
CVR3
CVR2
CVR1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.
2005 Microchip Technology Inc.
Advance Information
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Although the port is only five bits wide, PORTG<7:5>
bits are still implemented. These are used to control the
weak pull-ups on the I/O ports associated with the
external memory bus (PORTD, PORTE and PORTJ).
Setting these bits enables the pull-ups. Since these are
control bits and are not associated with port I/O, the
corresponding TRISG and LATG bits are not
implemented.
10.8 PORTG, TRISG and
LATG Registers
PORTG is a 5-bit wide, bidirectional port. The corre-
sponding data direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTG pin an output (i.e.,
put the contents of the output latch on the selected pin).
All pins on PORTG are digital only and tolerate
voltages up to 5.5V.
EXAMPLE 10-7:
INITIALIZING PORTG
CLRF
PORTG
LATG
04h
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register read and write the latched output value for
PORTG.
CLRF
MOVLW
MOVWF
PORTG is multiplexed with EUSART2 functions
(Table 10-15). PORTG pins have Schmitt Trigger input
buffers.
TRISG
; Set RG1:RG0 as outputs
; RG2 as input
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
; RG4:RG3 as inputs
DS39663A-page 132
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TABLE 10-15: PORTG FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RG0/ECCP3/
P3A
RG0
0
1
O
I
DIG
ST
LATG<0> data output.
PORTG<0> data input.
ECCP3
P3A
O
I
DIG
ST
CCP3 Compare and PWM output; takes priority over port data.
CCP3 Capture input.
0
O
DIG
ECCP3 Enhanced PWM output, channel A; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG1/TX2/CK2
R21
0
1
1
O
I
DIG
ST
LATG<1> data output.
PORTG<1> data input.
TX2
CK2
O
DIG
Synchronous serial data output (EUSART2 module); takes priority over
port data.
1
O
DIG
Synchronous serial data input (EUSART2 module). User must configure
as an input.
1
0
1
1
1
I
O
I
ST
DIG
ST
Synchronous serial clock input (EUSART2 module).
LATG<2> data output.
RG2/RX2/DT2
RG2
PORTG<2> data input.
RX2
DT2
I
ST
Asynchronous serial receive data input (EUSART2 module).
O
DIG
Synchronous serial data output (EUSART2 module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART2 module). User must configure
as an input.
RG3/CCP4/
P3D
RG3
CCP4
P3D
0
1
0
1
0
O
I
DIG
ST
LATG<3> data output.
PORTG<3> data input.
O
I
DIG
ST
CCP4 Compare output and CCP4 PWM output; takes priority over port data.
CCP4 Capture input.
O
DIG
ECCP3 Enhanced PWM output, channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG4/CCP5/
P1D
RG4
CCP5
P1D
0
1
0
1
0
O
I
DIG
ST
LATG<4> data output.
PORTG<4> data input.
O
I
DIG
ST
CCP5 Compare output and CCP5 PWM output; takes priority over port data.
CCP5 Capture input.
O
DIG
ECCP1 Enhanced PWM output, channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Reset
Values on
page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTG
RDPU
—
REPU
—
RJPU(1)
RG4
RG3
RG2
RG1
RG0
52
52
52
LATG
—
—
LATG4
LATG3
LATG2
LATG1
LATG0
TRISG
—
—
TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: Unimplemented on 64-pin devices; read as ‘0’.
2005 Microchip Technology Inc.
Advance Information
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PIC18F87J10 FAMILY
When the external memory interface is enabled, four of
the PORTH pins function as the high-order address
lines for the interface. The address output from the
interface takes priority over other digital I/O. The
corresponding TRISH bits are also overridden.
10.9 PORTH, LATH and
TRISH Registers
Note: PORTH is available only on 80-pin
devices.
PORTH pins RH4 through RH7 are multiplexed with
analog converter inputs. The operation of these pins as
analog inputs is selected by clearing or setting the
PCFG3:PCFG0 control bits in the ADCON1 register.
PORTH is an 8-bit wide, bidirectional I/O port. The cor-
responding data direction register is TRISH. Setting a
TRISH bit (= 1) will make the corresponding PORTH
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISH bit (= 0)
will make the corresponding PORTH pin an output (i.e.,
put the contents of the output latch on the selected pin).
PORTH pins <3:0> are digital only and tolerate
voltages up to 5.5V.
PORTH can also be configured as the alternate
Enhanced PWM output channels B and C for the
ECCP1 and ECCP3 modules. This is done by clearing
the ECCPMX configuration bit.
EXAMPLE 10-8:
INITIALIZING PORTH
The Data Latch register (LATH) is also memory
mapped. Read-modify-write operations on the LATH
register read and write the latched output value for
PORTH.
CLRF
PORTH
; Initialize PORTH by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure PORTH as
; digital I/O
; Value used to
CLRF
LATH
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
MOVLW
MOVWF
MOVLW
0Fh
ADCON1
0CFh
; initialize data
; direction
MOVWF
TRISH
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
DS39663A-page 134
Advance Information
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TABLE 10-17: PORTH FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
RH0/A16
Function
I/O
Description
RH0
0
1
x
0
1
x
0
1
x
0
1
x
0
1
O
I
DIG LATH<0> data output.
ST PORTH<0> data input.
A16
O
O
I
DIG External memory interface, address line 16. Takes priority over port data.
DIG LATH<1> data output.
RH1/A17
RH1
ST
PORTH<1> data input.
A17
O
O
I
DIG External memory interface, address line 17. Takes priority over port data.
DIG LATH<2> data output.
RH2/A18
RH2
ST
PORTH<2> data input.
A18
O
O
I
DIG External memory interface, address line 18. Takes priority over port data.
DIG LATH<3> data output.
RH3/A19
RH3
ST
PORTH<3> data input.
A19
O
O
I
DIG External memory interface, address line 19. Takes priority over port data.
DIG LATH<4> data output.
RH4/AN12/P3C
RH4
ST
PORTH<4> data input.
AN12
I
ANA A/D input channel 12. Default input configuration on POR; does not affect
digital output.
(1)
P3C
0
O
DIG ECCP3 Enhanced PWM output, channel C; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RH5/AN13/P3B
RH6/AN14/P1C
RH7/AN15/P1B
RH5
0
1
O
I
DIG LATH<5> data output.
ST
PORTH<5> data input.
AN13
I
ANA A/D input channel 13. Default input configuration on POR; does not affect
digital output.
(1)
P3B
0
O
DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RH6
0
1
O
I
DIG LATH<6> data output.
ST
PORTH<6> data input.
AN14
I
ANA A/D input channel 14. Default input configuration on POR; does not affect
digital output.
(1)
P1C
0
O
DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RH7
0
1
O
I
DIG LATH<7> data output.
ST
PORTH<7> data input.
AN15
I
ANA A/D input channel 15. Default input configuration on POR; does not affect
digital output.
(1)
P1B
0
O
DIG ECCP1 Enhanced PWM output, channel B; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignments for P1B/P1C and P3B/P3C when ECCPMX configuration bit is cleared. Default assignments are
PORTE<6:3>.
TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
PORTH
LATH
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
52
52
52
LATH7
TRISH7
LATH6
TRISH6
LATH5
TRISH5
LATH4
TRISH4
LATH3
TRISH3
LATH2
LATH1
LATH0
TRISH
TRISH2 TRISH1 TRISH0
2005 Microchip Technology Inc.
Advance Information
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PIC18F87J10 FAMILY
When the external memory interface is enabled, all of
the PORTJ pins function as control outputs for the
interface. This occurs automatically when the interface
is enabled by clearing the EBDIS control bit
(MEMCON<7>). The TRISJ bits are also overridden.
10.10 PORTJ, TRISJ and
LATJ Registers
Note: PORTJ is available only on 80-pin devices.
PORTJ is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISJ. Setting a
TRISJ bit (= 1) will make the corresponding PORTJ pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISJ bit (= 0) will
make the corresponding PORTJ pin an output (i.e., put
the contents of the output latch on the selected pin). All
pins on PORTJ are digital only and tolerate voltages up
to 5.5V.
Each of the PORTJ pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit RJPU (PORTG<5>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
The Data Latch register (LATJ) is also memory
mapped. Read-modify-write operations on the LATJ
register read and write the latched output value for
PORTJ.
EXAMPLE 10-9:
INITIALIZING PORTJ
CLRF
PORTJ
; Initialize PORTG by
; clearing output
; data latches
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
CLRF
LATJ
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
MOVLW
MOVWF
0CFh
Note:
These pins are configured as digital inputs
on any device Reset.
TRISJ
DS39663A-page 136
Advance Information
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TABLE 10-19: PORTJ FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
RJ0/ALE
Function
I/O
Description
RJ0
O
I
DIG
ST
LATJ<0> data output.
0
1
x
PORTJ<0> data input.
ALE
RJ1
O
DIG
External memory interface address latch enable control output; takes
priority over digital I/O.
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
0
1
x
O
I
DIG
ST
LATJ<1> data output.
PORTJ<1> data input.
OE
O
DIG
External memory interface output enable control output; takes priority
over digital I/O.
RJ2
0
1
x
O
I
DIG
ST
LATJ<2> data output.
PORTJ<2> data input.
WRL
RJ3
O
DIG
External memory bus write low byte control; takes priority over
digital I/O.
0
1
x
O
I
DIG
ST
LATJ<3> data output.
PORTJ<3> data input.
WRH
RJ4
O
DIG
External memory interface write high byte control output; takes priority
over digital I/O.
0
1
x
O
I
DIG
ST
LATJ<4> data output.
PORTJ<4> data input.
BA0
RJ5
O
DIG
External memory interface byte address 0 control output; takes priority
over digital I/O.
0
1
x
O
I
DIG
ST
LATJ<5> data output.
PORTJ<5> data input.
CE
O
DIG
External memory interface chip enable control output; takes priority
over digital I/O.
RJ6
0
1
x
O
I
DIG
ST
LATJ<6> data output.
PORTJ<6> data input.
LB
O
DIG
External memory interface lower byte enable control output; takes
priority over digital I/O.
RJ7/UB
Legend:
RJ7
0
1
x
O
I
DIG
ST
LATJ<7> data output.
PORTJ<7> data input.
UB
O
DIG
External memory interface upper byte enable control output; takes
priority over digital I/O.
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-20: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTJ
RJ7
RJ6
RJ5
RJ4
LATJ4
TRISJ4
RG4
RJ3
LATJ3
TRISJ3
RG3
RJ2
LATJ2
TRISJ2
RG2
RJ1
LATJ1
TRISJ1
RG1
RJ0
LATJ0
TRISJ0
RG0
52
52
52
52
LATJ
LATJ7
LATJ6
LATJ5
TRISJ5
RJPU
TRISJ
PORTG
TRISJ7 TRISJ6
RDPU REPU
2005 Microchip Technology Inc.
Advance Information
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PIC18F87J10 FAMILY
FIGURE 10-2:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLELSLAVEPORT)
10.11 Parallel Slave Port
PORTD can also function as an 8-bit wide Parallel
Slave Port, or microprocessor port, when control bit
PSPMODE (PSPCON<4>) is set. It is asynchronously
readable and writable by the external world through RD
control input pin, RE0/RD and WR control input pin,
RE1/WR.
Data Bus
D
Q
RDx
pin
WR LATD
or
PORTD
CK
Data Latch
Note: For 80-pin devices, the Parallel Slave Port
TTL
is available only in Microcontroller mode.
Q
D
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit PSPMODE enables port pin RE0/RD to be the RD
input, RE1/WR to be the WR input and RE2/CS to be
the CS (Chip Select) input. For this functionality, the
corresponding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set).
RD PORTD
EN
TRIS Latch
RD LATD
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is set. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
Read
When either the CS or RD lines are detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP; when this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
RD
CS
TTL
Chip Select
TTL
Write
WR
TTL
The timing for the control signals in Write and Read
modes is shown in Figure 10-3 and Figure 10-4,
respectively.
Note: I/O pin has protection diodes to VDD and VSS.
DS39663A-page 138
Advance Information
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REGISTER 10-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
OBF
PSPMODE
bit 7
bit 0
bit 7
bit 6
bit 5
IBF: Input Buffer Full Status bit
1= A word has been received and is waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit
1= A write occurred when a previously input word has not been read
(must be cleared in software)
0= No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0= General Purpose I/O mode
bit 3-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
FIGURE 10-3:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
2005 Microchip Technology Inc.
Advance Information
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PIC18F87J10 FAMILY
FIGURE 10-4:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-21: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
RD7
LATD7
TRISD7
RE7
RD6
LATD6
TRISD6
RE6
RD5
LATD5
TRISD5
RE5
RD4
LATD4
TRISD4
RE4
RD3
RD2
RD1
RD0
52
52
52
52
52
52
51
49
51
51
51
LATD3
LATD2
LATD1
LATD0
TRISD
PORTE
LATE
TRISD3 TRISD2
TRISD1 TRISD0
RE3
LATE3
TRISE3
—
RE2
LATE2
TRISE2
—
RE1
LATE1
TRISE1
—
RE0
LATE0
TRISE0
—
LATE7
TRISE7
IBF
LATE6
TRISE6
OBF
LATE5
TRISE5
IBOV
LATE4
TRISE4
PSPMODE
INT0IE
TX1IF
TRISE
PSPCON
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
RBIE
TMR0IF
INT0IF
RBIF
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RC1IF
RC1IE
RC1IP
SSP1IF
SSP1IE
SSP1IP
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
TX1IE
IPR1
TX1IP
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
DS39663A-page 140
Advance Information
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PIC18F87J10 FAMILY
The T0CON register (Register 11-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
11.0 TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or
counter in both 8-bit or 16-bit modes
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 11-1. Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
TMR0ON
bit 7
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
T08BIT
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-bit/16-bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKO)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 Prescale value
110= 1:128 Prescale value
101= 1:64 Prescale value
100= 1:32 Prescale value
011= 1:16 Prescale value
010= 1:8 Prescale value
001= 1:4 Prescale value
000= 1:2 Prescale value
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
11.1 Timer0 Operation
Timer0 can operate as either a timer or a counter; the
mode is selected with the T0CS bit (T0CON<5>). In
Timer mode (T0CS = 0), the module increments on
every clock by default unless a different prescaler value
is selected (see Section 11.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
11.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0 which is not directly readable nor writ-
able (refer to Figure 11-2). TMR0H is updated with the
contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit, T0SE (T0CON<4>); clearing this bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4
0
1
1
0
Set
TMR0IF
on Overflow
Sync with
Internal
Clocks
TMR0L
8
Programmable
Prescaler
T0CKI pin
(2 TCY Delay)
T0SE
T0CS
3
T0PS2:T0PS0
PSA
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
FOSC/4
0
1
Sync with
Internal
Clocks
Set
TMR0
High Byte
1
TMR0L
TMR0IF
Programmable
Prescaler
on Overflow
T0CKI pin
0
8
(2 TCY Delay)
T0SE
T0CS
3
Read TMR0L
Write TMR0L
T0PS2:T0PS0
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39663A-page 142
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11.3.1
SWITCHING PRESCALER
ASSIGNMENT
11.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable.
Its value is set by the PSA and T0PS2:T0PS0 bits
(T0CON<2:0>) which determine the prescaler
assignment and prescale ratio.
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4 Timer0 Interrupt
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256 in power-of-2 increments are
selectable.
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before
re-enabling the interrupt, the TMR0IF bit must be
cleared in software by the Interrupt Service Routine.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0L
Timer0 Register Low Byte
Timer0 Register High Byte
50
50
49
50
52
TMR0H
INTCON
T0CON
TRISA
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
T0SE
RBIE
PSA
TMR0IF
T0PS2
INT0IF
T0PS1
TRISA1
RBIF
T0PS0
TRISA0
TMR0ON
—
T08BIT
—
T0CS
TRISA5
TRISA4
TRISA3
TRISA2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.
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NOTES:
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A simplified block diagram of the Timer1 module is
shown in Figure 12-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 12-2.
12.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
Timer1 is controlled through the T1CON Control
register (Register 12-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).
• Reset on CCP Special Event Trigger
• Device clock status flag (T1RUN)
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
RD16
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7
bit 6
RD16: 16-Bit Read/Write Mode Enable bit
1= Enables register read/write of TImer1 in one 16-bit operation
0= Enables register read/write of Timer1 in two 8-bit operations
T1RUN: Timer1 System Clock Status bit
1= Device clock is derived from Timer1 oscillator
0= Device clock is derived from another source
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 oscillator is enabled
0= Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• Timer
When Timer1 is enabled, the RC1/T1OSI and
RC0/T1OSO/T13CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR3CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
Timer1 Oscillator
Timer1 Clock Input
1
0
On/Off
T1OSO/T13CKI
T1OSI
1
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
0
2
Sleep Input
T1OSCEN(1)
T1CKPS1:T1CKPS0
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
TMR1L
TMR1IF
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
T1OSO/T13CKI
T1OSI
1
0
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T1CKPS1:T1CKPS0
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1IF
on Overflow
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
TMR1L
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
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TABLE 12-1: CAPACITOR SELECTION FOR
THETIMEROSCILLATOR(2,3,4)
12.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
Oscillator
Freq.
C1
C2
Type
LP
32 kHz
27 pF(1)
27 pF(1)
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
4: Capacitor values are for design guidance
only.
12.3.1
USING TIMER1 AS A
CLOCK SOURCE
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the clock select
bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device
switches to SEC_RUN mode; both the CPU and
peripherals are clocked from the Timer1 oscillator. If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 3.0
“Power-Managed Modes”.
12.3 Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will
continue to run during all power-managed modes. The
circuit for a typical LP oscillator is shown in Figure 12-3.
Table 12-1 shows the capacitor selection for the Timer1
oscillator.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN
(T1CON<6>), is set. This can be used to determine the
controller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
Clock Monitor. If the Clock Monitor is enabled and the
Timer1 oscillator fails while providing the clock, polling
the T1RUN bit will indicate whether the clock is being
provided by the Timer1 oscillator or another source.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 12-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
C1
27 pF
PIC18F87J10
12.3.2
LOW-POWER TIMER1 OPTION
T1OSI
The Timer1 oscillator can operate at two distinct levels
of power consumption based on device configuration.
When the LPT1OSC configuration bit is set, the Timer1
oscillator operates in a low-power mode. When
LPT1OSC is not set, Timer1 operates at a higher power
level. Power consumption for a particular mode is rela-
tively constant regardless of the device’s operating
mode. The default Timer1 configuration is the higher
power mode.
XTAL
32.768 kHz
T1OSO
C2
27 pF
Note:
See the Notes with Table 12-1 for additional
information about capacitor selection.
As the low-power Timer1 mode tends to be more
sensitive to interference, high noise environments may
cause some oscillator instability. The low-power option is,
therefore, best suited for low noise applications where
power conservation is an important design consideration.
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12.3.3
TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
12.5 Resetting Timer1 Using the ECCP
Special Event Trigger
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
If ECCP1 or ECCP2 is configured to use Timer1 and to
generate a Special Event Trigger in Compare mode
(CCPxM3:CCPxM0 = 1011), this signal will reset
Timer3. The trigger from ECCP2 will also start an A/D
conversion if the A/D module is enabled (see
Section 17.2.1 “Special Event Trigger” for more
information).
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRH:CCPRL register pair
effectively becomes a period register for Timer1.
If a high-speed circuit must be located near the oscilla-
tor (such as the ECCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
FIGURE 12-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
Note:
The Special Event Triggers from the
ECCPx module will not set the TMR1IF
interrupt flag bit (PIR1<0>).
VDD
VSS
12.6 Using Timer1 as a Real-Time Clock
OSC1
OSC2
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.3 “Timer1 Oscillator”
above) gives users the option to include RTC function-
ality to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
RC0
RC1
RC2
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine which increments the seconds counter by
one. Additional counters for minutes and hours are
incremented as the previous counter overflows.
Note: Not drawn to scale.
12.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it; the simplest method is to set the MSb of TMR1H
with a BSFinstruction. Note that the TMR1L register is
never preloaded or altered; doing so may introduce
cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
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EXAMPLE 12-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
80h
TMR1H
TMR1L
; Preload TMR1 register pair
; for 1 second overflow
MOVLW
MOVWF
CLRF
b’00001111’
T1CON
secs
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
CLRF
mins
MOVLW
MOVWF
BSF
.12
hours
PIE1, TMR1IE
; Enable Timer1 interrupt
RETURN
RTCisr
BSF
BCF
INCF
MOVLW
CPFSGT
RETURN
CLRF
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
; 60 seconds elapsed?
secs
; No, done
secs
mins, F
.59
; Clear seconds
; Increment minutes
; 60 minutes elapsed?
INCF
MOVLW
CPFSGT
RETURN
CLRF
mins
; No, done
mins
hours, F
.23
; clear minutes
; Increment hours
; 24 hours elapsed?
INCF
MOVLW
CPFSGT
RETURN
CLRF
hours
; No, done
; Reset hours
; Done
hours
RETURN
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
49
51
51
51
50
50
50
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RC1IF
RC1IE
RC1IP
SSP1IF
SSP1IE
SSP1IP
TMR1IF
TMR1IE
TMR1IP
PIE1
IPR1
TMR1L
TMR1H
T1CON
Timer1 Register Low Byte
Timer1 Register High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: Shaded cells are not used by the Timer1 module.
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13.1 Timer2 Operation
13.0 TIMER2 MODULE
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options; these are selected by
the prescaler control bits, T2CKPS1:T2CKPS0
(T2CON<1:0>). The value of TMR2 is compared to that
of the period register, PR2, on each clock cycle. When
the two values match, the comparator generates a
match signal as the timer output. This signal also resets
the value of TMR2 to 00h on the next cycle and drives
the output counter/postscaler (see Section 13.2
“Timer2 Interrupt”).
The Timer2 timer module incorporates the following
features:
• 8-bit timer and period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4 and
1:16)
• Software programmable postscaler (1:1 through
1:16)
• Interrupt on TMR2-to-PR2 match
• Optional use as the shift clock for the
MSSP module
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
The module is controlled through the T2CON register
(Register 13-1) which enables or disables the timer and
configures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON<2>),
to minimize power consumption.
• a write to the TMR2 register
• a write to the T2CON register
A simplified block diagram of the module is shown in
Figure 13-1.
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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13.2 Timer2 Interrupt
13.3 Timer2 Output
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 18.0
“Master Synchronous Serial Port (MSSP) Module”.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
4
1:1 to 1:16
Set TMR2IF
Postscaler
T2OUTPS3:T2OUTPS0
2
TMR2 Output
T2CKPS1:T2CKPS0
(to PWM or MSSP)
TMR2/PR2
Match
Reset
TMR2
1:1, 1:4, 1:16
Prescaler
PR2
FOSC/4
Comparator
8
8
8
Internal Data Bus
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
49
51
51
51
50
50
50
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RC1IF
RC1IE
RC1IP
SSP1IF
SSP1IE
SSP1IP
TMR1IF
TMR1IE
TMR1IP
PIE1
IPR1
TMR2
T2CON
PR2
Timer2 Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
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A simplified block diagram of the Timer3 module is
shown in Figure 14-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 14-2.
14.0 TIMER3 MODULE
The Timer3 timer/counter module incorporates these
features:
The Timer3 module is controlled through the T3CON
register (Register 14-1). It also selects the clock source
options for the CCP and ECCP modules; see
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
Section 16.1.1
Resources” for more information.
“CCP
Modules
and
Timer
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
• Module Reset on CCP Special Event Trigger
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0
RD16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 0
bit 7
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register read/write of Timer3 in one 16-bit operation
0= Enables register read/write of Timer3 in two 8-bit operations
bit 6,3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
11= Timer3 and Timer4 are the clock sources for all CCP/ECCP modules
10= Timer3 and Timer4 are the clock sources for ECCP3, CCP4 and CCP5;
Timer1 and Timer2 are the clock sources for ECCP1 and ECCP2
01= Timer3 and Timer4 are the clock sources for ECCP2, ECCP3, CCP4 and CCP5;
Timer1 and Timer2 are the clock sources for ECCP1
00= Timer1 and Timer2 are the clock sources for all CCP/ECCP modules
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
bit 0
TMR3CS: Timer3 Clock Source Select bit
1= External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first
falling edge)
0= Internal clock (FOSC/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
14.1 Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
As
with
Timer1,
the
RC1/T1OSI
and
RC0/T1OSO/T13CKI pins become inputs when the
Timer1 oscillator is enabled. This means the values of
TRISC<1:0> are ignored and the pins are read as ‘0’.
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
Timer1 Oscillator
Timer1 Clock Input
1
0
T1OSO/T13CKI
T1OSI
1
0
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
TMR3CS
Timer3
On/Off
T3CKPS1:T3CKPS0
T3SYNC
TMR3ON
CCPx Special Event Trigger
Clear TMR3
Set
TMR3
High Byte
TMR3L
TMR3IF
CCPx Select from T3CON<6,3>
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
1
0
T13CKI/T1OSO
T1OSI
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T3CKPS1:T3CKPS0
T3SYNC
Timer3
On/Off
TMR3CS
TMR3ON
CCPx Special Event Trigger
Clear TMR3
Set
TMR3IF
on Overflow
TMR3
High Byte
TMR3L
CCPx Select from T3CON<6,3>
8
Read TMR1L
Write TMR1L
8
8
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
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14.2 Timer3 16-Bit Read/Write Mode
14.4 Timer3 Interrupt
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit
(T3CON<7>) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.5 Resetting Timer3 Using the ECCP
Special Event Trigger
If ECCP1 or ECCP2 is configured to use Timer3 and to
generate a Special Event Trigger in Compare mode
(CCPxM3:CCPxM0 = 1011), this signal will reset
Timer3. The trigger from ECCP2 will also start an A/D
conversion if the A/D module is enabled (see
Section 17.2.1 “Special Event Trigger” for more
information).
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a period register for Timer3.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
14.3 Using the Timer1 Oscillator as the
Timer3 Clock Source
In the event that a write to Timer3 coincides with a
Special Event Trigger from an ECCP module, the write
will take precedence.
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
Note:
The Special Event Triggers from the
ECCPx module will not set the TMR3IF
interrupt flag bit (PIR1<0>).
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
—
RBIE
TMR0IF
INT0IF
TMR3IF
TMR3IE
TMR3IP
RBIF
49
51
51
51
51
51
50
51
OSCFIF
OSCFIE
OSCFIP
CMIF
CMIE
CMIP
—
—
—
BCL1IF
BCL1IE
BCL1IP
—
—
—
CCP2IF
CCP2IE
CCP2IP
PIE2
—
IPR2
—
TMR3L
TMR3H
T1CON
T3CON
Timer3 Register Low Byte
Timer3 Register High Byte
RD16
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
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NOTES:
DS39663A-page 156
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15.1 Timer4 Operation
15.0 TIMER4 MODULE
Timer4 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR4 register is
readable and writable and is cleared on any device
Reset. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits
T4CKPS1:T4CKPS0 (T4CON<1:0>). The match out-
put of TMR4 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR4 interrupt, latched in flag bit TMR4IF (PIR3<3>).
The Timer4 timer module has the following features:
• 8-bit timer register (TMR4)
• 8-bit period register (PR4)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR4 match of PR4
Timer4 has a control register shown in Register 15-1.
Timer4 can be shut off by clearing control bit, TMR4ON
(T4CON<2>), to minimize power consumption. The
prescaler and postscaler selection of Timer4 are also
controlled by this register. Figure 15-1 is a simplified
block diagram of the Timer4 module.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR4 register
• a write to the T4CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR4 is not cleared when T4CON is written.
REGISTER 15-1: T4CON: TIMER4 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T4OUTPS3:T4OUTPS0: Timer4 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR4ON: Timer4 On bit
1= Timer4 is on
0= Timer4 is off
bit 1-0
T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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15.2 Timer4 Interrupt
15.3 Output of TMR4
The Timer4 module has an 8-bit period register, PR4,
which is both readable and writable. Timer4 increments
from 00h until it matches PR4 and then resets to 00h on
the next increment cycle. The PR4 register is initialized
to FFh upon Reset.
The output of TMR4 (before the postscaler) is used
only as a PWM time base for the CCP modules. It is not
used as a baud rate clock for the MSSP as is the
Timer2 output.
FIGURE 15-1:
TIMER4 BLOCK DIAGRAM
4
1:1 to 1:16
Set TMR4IF
Postscaler
T4OUTPS3:T4OUTPS0
2
TMR4 Output
T4CKPS1:T4CKPS0
(to PWM)
TMR4/PR4
Match
Reset
TMR4
1:1, 1:4, 1:16
Prescaler
Comparator
PR4
FOSC/4
8
8
8
Internal Data Bus
TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IP
TX2IF
TX2IE
RBIE
TMR0IF
CCP5IP
CCP5IF
CCP5IE
INT0IF
CCP4IP
CCP4IF
CCP4IE
RBIF
49
51
51
51
53
53
53
IPR3
SSP2IP
SSP2IF
SSP2IE
BCL2IP
BCL2IF
BCL2IE
RC2IP
RC2IF
RC2IE
TMR4IP
TMR4IF
TMR4IE
CCP3IP
CCP3IF
CCP3IE
PIR3
PIE3
TMR4
T4CON
PR4
Timer4 Register
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
Timer4 Period Register
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module.
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PIC18F87J10 FAMILY
register. For the sake of clarity, all CCP module opera-
tion in the following sections is described with respect
to CCP4, but is equally applicable to CCP5.
16.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
Members of the PIC18F87J10 family of devices all have
a total of five CCP (Capture/Compare/PWM) modules.
Two of these (CCP4 and CCP5) implement standard
Capture, Compare and Pulse-Width Modulation (PWM)
modes and are discussed in this section. The other three
modules (ECCP1, ECCP2, ECCP3) implement
standard Capture and Compare modes, as well as
Enhanced PWM modes. These are discussed in
Section 17.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”.
Capture and Compare operations described in this
chapter apply to all standard and Enhanced CCP
modules. The operations of PWM mode, described in
Section 16.4 “PWM Mode”, apply to CCP4 and CCP5
only.
Note: Throughout this section and Section 17.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to register and bit names
that may be associated with a specific CCP
module are referred to generically by the use of
‘x’ or ‘y’ in place of the specific module number.
Thus, “CCPxCON” might refer to the control
register for ECCP1, ECCP2, ECCP3, CCP4 or
CCP5.
Each CCP/ECCP module contains a 16-bit register
which can operate as a 16-bit Capture register, a 16-bit
Compare register or a PWM Master/Slave Duty Cycle
REGISTER 16-1: CCPxCON: CCP CONTROL REGISTER (CCP4 AND CCP5)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
DCxB0
CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DCxB1:DCxB0: CCP Module x PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The
eight Most Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCPx module)
0001= Reserved
0010= Compare mode, toggle output on match (CCPxIF bit is set)
0011= Reserved
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode; initialize CCP pin low; on compare match, force CCP pin high
(CCPIF bit is set)
1001= Compare mode; initialize CCP pin high; on compare match, force CCP pin low
(CCPIF bit is set)
1010= Compare mode; generate software interrupt on compare match (CCPIF bit is set,
CCP pin reflects I/O state)
1011= Reserved
11xx= PWM mode
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2005 Microchip Technology Inc.
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PIC18F87J10 FAMILY
The assignment of a particular timer to a module is
determined by the Timer-to-CCP enable bits in the
T3CON register (Register 14-1, page 153). Depending
on the configuration selected, up to four timers may be
active at once, with modules in the same configuration
(Capture/Compare or PWM) sharing timer resources.
The possible configurations are shown in Figure 16-1.
16.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
16.1.2
ECCP2 PIN ASSIGNMENT
16.1.1
CCP MODULES AND TIMER
RESOURCES
The pin assignment for ECCP2 (Capture input,
Compare and PWM output) can change, based on
device configuration. The CCP2MX configuration bit
determines which pin ECCP2 is multiplexed to. By
default, it is assigned to RC1 (CCP2MX = 1). If the con-
figuration bit is cleared, ECCP2 is multiplexed with RE7
on 64-pin devices and RB3 or RE7 on 80-pin devices
depending on mode setting.
The CCP/ECCP modules utilize Timers 1, 2, 3 or 4,
depending on the mode selected. Timer1 and Timer3
are available to modules in Capture or Compare
modes, while Timer2 and Timer4 are available for
modules in PWM mode.
TABLE 16-1: CCP MODE – TIMER
RESOURCE
Changing the pin assignment of ECCP2 does not auto-
matically change any requirements for configuring the
port pin. Users must always verify that the appropriate
TRIS register is configured correctly for ECCP2
operation regardless of where it is located.
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2 or Timer4
FIGURE 16-1:
CCP AND TIMER INTERCONNECT CONFIGURATIONS
T3CCP<2:1> = 00
T3CCP<2:1> = 01
T3CCP<2:1> = 10
T3CCP<2:1> = 11
TMR1
TMR3
TMR1
TMR3
TMR1
TMR3
TMR1
TMR3
ECCP1
ECCP1
ECCP2
ECCP3
CCP4
ECCP1
ECCP2
ECCP1
ECCP2
ECCP3
CCP4
ECCP2
ECCP3
CCP4
ECCP3
CCP4
CCP5
CCP5
CCP5
CCP5
TMR2
TMR4
TMR2
TMR4
TMR2
TMR4
TMR2
TMR4
Timer1 is used for all Capture Timer1 and Timer2 are used Timer1 and Timer2 are used Timer3 is used for all Capture
and Compare operations for for Capture and Compare or for Capture and Compare or and Compare operations for
all CCP modules. Timer2 is PWM operations for ECCP1 PWM operations for ECCP1 all CCP modules. Timer4 is
used for PWM operations for only (depending on selected and ECCP2 only (depending used for PWM operations for
all CCP modules. Modules mode).
may share either timer
on the mode selected for each all CCP modules. Modules
module). Both modules may may share either timer
use a timer as a common time resource as a common time
base if they are both in base.
All other modules use either
resource as a common time
base.
Timer3 or Timer4. Modules
may share either timer
Capture/Compare or PWM
modes.
Timer3 and Timer4 are not resource as a common time
Timer1 and Timer2 are not
available.
base
if
they
are
in
available.
Capture/Compare or PWM The other modules use either
modes.
Timer3 or Timer4. Modules
may share either timer
resource as a common time
base
if
they
are
in
Capture/Compare or PWM
modes.
DS39663A-page 160
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PIC18F87J10 FAMILY
16.2.3
SOFTWARE INTERRUPT
16.2 Capture Mode
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false
interrupts. The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCPx pin. An event is defined as one of the following:
• every falling edge
• every rising edge
16.2.4
CCP PRESCALER
• every 4th rising edge
• every 16th rising edge
There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
selected by the mode select bits (CCPxM3:CCPxM0).
Whenever the CCP module is turned off or Capture
mode is disabled, the prescaler counter is cleared. This
means that any Reset will clear the prescaler counter.
The event is selected by the mode select bits,
CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture
is made, the interrupt request flag bit, CCPxIF, is set; it
must be cleared in software. If another capture occurs
before the value in register CCPRx is read, the old
captured value is overwritten by the new captured value.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
16.2.1
CCP PIN CONFIGURATION
a
non-zero prescaler. Example 16-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
Note:
If RG4/CCP5 is configured as an output, a
write to the port can cause a capture
condition.
EXAMPLE 16-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP5 SHOWN)
CLRF
CCP5CON
; Turn CCP module off
16.2.2
TIMER1/TIMER3 MODE SELECTION
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation will not work. The timer to be
used with each CCP module is selected in the T3CON
register (see Section 16.1.1 “CCP Modules and Timer
Resources”).
; value and CCP ON
; Load CCP5CON with
; this value
MOVWF CCP5CON
FIGURE 16-2:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
Set CCP4IF
T3CCP2
TMR3
Enable
CCP4 Pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
CCPR4H
CCPR4L
TMR1
Enable
T3CCP2
TMR1H
TMR1L
TMR3L
4
4
CCP4CON<3:0>
Q1:Q4
Set CCP5IF
4
CCP5CON<3:0>
TMR3H
T3CCP1
T3CCP2
TMR3
Enable
CCP5 Pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
CCPR5H
CCPR5L
TMR1L
TMR1
Enable
T3CCP2
T3CCP1
TMR1H
2005 Microchip Technology Inc.
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16.3 Compare Mode
Note:
Clearing the CCP5CON register will force
the RG4 compare output latch (depend-
ing on device configuration) to the default
low level. This is not the PORTB or
PORTC I/O data latch.
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCPx pin
can be:
• driven high
16.3.2
TIMER1/TIMER3 MODE SELECTION
• driven low
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCPxM3:CCPxM0). At the same time, the
interrupt flag bit, CCPxIF, is set.
16.3.3
SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCPxM3:CCPxM0 = 1010), the corresponding CCPx
pin is not affected. Only a CCP interrupt is generated,
if enabled and the CCPxIE bit is set.
16.3.1
CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
FIGURE 16-3:
COMPARE MODE OPERATION BLOCK DIAGRAM
Set CCP4IF
CCPR4H
CCPR4L
CCP4 pin
S
R
Q
Compare
Match
Output
Logic
Comparator
TRIS
Output Enable
4
CCP4CON<3:0>
TMR1H
TMR3H
TMR1L
TMR3L
0
0
1
1
T3CCP1
T3CCP2
Set CCP5IF
CCP5 pin
S
R
Q
Compare
Match
Output
Logic
Comparator
TRIS
Output Enable
4
CCPR5H
CCPR5L
CCP5CON<3:0>
DS39663A-page 162
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TABLE 16-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
49
50
51
51
51
51
51
51
51
51
51
52
50
50
50
51
51
51
53
53
53
53
53
53
IPEN
PSPIF
PSPIE
PSPIP
OSCFIF
OSCFIE
OSCFIP
SSP2IF
SSP2IE
SSP2IP
—
—
—
RC1IF
RC1IE
RC1IP
—
ADIF
TX1IF
TX1IE
TX1IP
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TMR4IF
TMR4IE
TMR4IP
TRISG3
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
ADIE
ADIP
CMIF
CMIE
CMIP
BCL2IF
BCL2IE
BCL2IP
—
IPR1
PIR2
—
—
TMR3IF CCP2IF
TMR3IE CCP2IE
TMR3IP CCP2IP
PIE2
—
—
IPR2
—
—
—
PIR3
RC2IF
RC2IE
RC2IP
—
TX2IF
TX2IE
TX2IP
TRISG4
CCP5IF
CCP4IF
CCP3IF
PIE3
CCP5IE CCP4IE CCP3IE
CCP5IP CCP4IP CCP3IP
TRISG2 TRISG1 TRISG0
IPR3
TRISG
TMR1L
TMR1H
T1CON
TMR3H
TMR3L
T3CON
CCPR4L
CCPR4H
CCPR5L
CCPR5H
CCP4CON
CCP5CON
Timer1 Register Low Byte
Timer1 Register High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Timer3 Register High Byte
Timer3 Register Low Byte
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
Capture/Compare/PWM Register 4 Low Byte
Capture/Compare/PWM Register 4 High Byte
Capture/Compare/PWM Register 5 Low Byte
Capture/Compare/PWM Register 5 High Byte
—
—
—
—
DC4B1
DC5B1
DC4B0
DC5B0
CCP4M3 CCP4M2 CCP4M1 CCP4M0
CCP5M3 CCP5M2 CCP5M1 CCP5M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
2005 Microchip Technology Inc.
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PIC18F87J10 FAMILY
16.4.1
PWM PERIOD
16.4 PWM Mode
The PWM period is specified by writing to the PR2
(PR4) register. The PWM period can be calculated
using Equation 16-1:
In Pulse-Width Modulation (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP4 and CCP5 pins are multiplexed with a
PORTG data latch, the appropriate TRISG bit must be
cleared to make the CCP4 or CCP5 pin an output.
EQUATION 16-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
Note:
Clearing the CCP4CON or CCP5CON
register will force the RG3 or RG4 output
latch (depending on device configuration)
to the default low level. This is not the
PORTG I/O data latch.
PWM frequency is defined as 1/[PWM period].
When TMR2 (TMR4) is equal to PR2 (PR4), the
following three events occur on the next increment
cycle:
Figure 16-4 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up a CCP
module for PWM operation, see Section 16.4.3
“Setup for PWM Operation”.
• TMR2 (TMR4) is cleared
• The CCPx pin is set (exception: if PWM duty
cycle = 0%, the CCPx pin will not be set)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH
FIGURE 16-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note:
The Timer2 and Timer 4 postscalers (see
Section 13.0 “Timer2 Module” and
Section 15.0 “Timer4 Module”) are not
used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
Duty Cycle Register
9
0
CCPR1L
CCP1CON<5:4>
Latch
Duty Cycle
(1)
CCPR1H
Comparator
TMR2
16.4.2
PWM DUTY CYCLE
S
R
Q
ECCP1
pin
The PWM duty cycle is specified by writing to the
CCPRxL register and to the CCPxCON<5:4> bits. Up
to 10-bit resolution is available. The CCPRxL contains
the eight MSbs and the CCPxCON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. Equation 16-2 is used to
calculate the PWM duty cycle in time.
Reset
TMR2 = PR2
Match
2 LSbs latched
from Q clocks
Comparator
PR2
TRIS
Output Enable
Set CCP pin
EQUATION 16-2:
Note 1: The two LSbs of the Duty Cycle register are held by a
2-bit latch that is part of the module’s hardware. It is
physically separate from the CCPR registers.
PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •
TOSC • (TMR2 Prescale Value)
A PWM output (Figure 16-5) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the
period (1/period).
CCPRxL and CCPxCON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPRxH until after a match between PR2 (PR4) and
TMR2 (TMR4) occurs (i.e., the period is complete). In
PWM mode, CCPRxH is a read-only register.
FIGURE 16-5:
PWM OUTPUT
Period
Duty Cycle
TMR2 (TMR4) = PR2 (PR4)
TMR2 (TMR4) = Duty Cycle
TMR2 (TMR4) = PR2 (TMR4)
DS39663A-page 164
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PIC18F87J10 FAMILY
The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
16.4.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 (PR4)
register.
When the CCPRxH and 2-bit latch match TMR2
(TMR4), concatenated with an internal 2-bit Q clock or
2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is
cleared.
2. Set the PWM duty cycle by writing to the
CCPRxL register and CCPxCON<5:4> bits.
3. Make the CCPx pin an output by clearing the
appropriate TRIS bit.
The maximum PWM resolution (bits) for a given PWM
frequency is given by Equation 16-3:
4. Set the TMR2 (TMR4) prescale value, then
enable Timer2 (Timer4) by writing to T2CON
(T4CON).
EQUATION 16-3:
FOSC
5. Configure the CCPx module for PWM operation.
log( )
FPWM
log(2)
PWM Resolution (max) =
bits
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCPx pin will not be
cleared.
TABLE 16-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
2005 Microchip Technology Inc.
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TABLE 16-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
49
50
51
51
51
51
51
51
52
50
50
50
53
53
53
53
53
53
53
53
53
IPEN
PSPIF
PSPIE
PSPIP
SSP2IF
SSP2IE
SSP2IP
—
—
—
ADIF
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
—
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
TRISG4
SSP1IF
SSP1IE
SSP1IP
TMR4IF
TMR4IE
TMR4IP
TRISG3
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
ADIE
ADIP
BCL2IF
BCL2IE
BCL2IP
—
IPR1
PIR3
CCP5IF
CCP4IF
CCP3IF
PIE3
CCP5IE CCP4IE CCP3IE
CCP5IP CCP4IP CCP3IP
TRISG2 TRISG1 TRISG0
IPR3
TRISG
TMR2
PR2
Timer2 Register
Timer2 Period Register
T2CON
TMR4
PR4
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer4 Register
Timer4 Period Register
T4CON
CCPR4L
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
Capture/Compare/PWM Register 4 Low Byte
CCPR4H Capture/Compare/PWM Register 4 High Byte
CCPR5L Capture/Compare/PWM Register 5 Low Byte
CCPR5H Capture/Compare/PWM Register 5 High Byte
CCP4CON
CCP5CON
—
—
—
—
DC4B1
DC5B1
DC4B0
DC5B0
CCP4M3 CCP4M2 CCP4M1 CCP4M0
CCP5M3 CCP5M2 CCP5M1 CCP5M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2 or Timer4.
DS39663A-page 166
Advance Information
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PIC18F87J10 FAMILY
The control register for the Enhanced CCP module is
shown in Register 17-1. It differs from the CCP4CON/
CCP5CON registers in that the two Most Significant
bits are implemented to control PWM functionality.
17.0 ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
In the PIC18F87J10 family of devices, three of the CCP
modules are implemented as standard CCP modules
with Enhanced PWM capabilities. These include the
provision for 2 or 4 output channels, user-selectable
polarity, dead-band control and automatic shutdown
and restart. The Enhanced features are discussed in
detail in Section 17.4 “Enhanced PWM Mode”.
Capture, Compare and single-output PWM functions of
the ECCP module are the same as described for the
standard CCP module.
In addition to the expanded range of modes available
through the Enhanced CCPxCON register, the ECCP
modules each have two additional features associated
with Enhanced PWM operation and auto-shutdown
features. They are:
• ECCPxDEL (Dead-Band Delay)
• ECCPxAS (Auto-Shutdown Configuration)
REGISTER 17-1: CCPxCON:ENHANCEDCCPCONTROLREGISTER(ECCP1/ECCP2/ECCP3)
R/W-0
PxM1
R/W-0
PxM0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCPxM0
bit 0
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
bit 7
bit 7-6
PxM1:PxM0: Enhanced PWM Output Configuration bits
If CCPxM3:CCPxM2 = 00, 01, 10:
xx= PxA assigned as Capture/Compare input/output; PxB, PxC, PxD assigned as port pins
If CCPxM3:CCPxM2 = 11:
00= Single output: PxA modulated; PxB, PxC, PxD assigned as port pins
01= Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10= Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as
port pins
11= Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
bit 5-4
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found
in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: Enhanced CCP Mode Select bits
0000= Capture/Compare/PWM off (resets ECCPx module)
0001= Reserved
0010= Compare mode, toggle output on match
0011= Capture mode
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, initialize ECCP pin low, set output on compare match (set CCPxIF)
1001= Compare mode, initialize ECCP pin high, clear output on compare match (set CCPxIF)
1010= Compare mode, generate software interrupt only, ECCP pin reverts to I/O state
1011= Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CCPxIF bit,
(1)
ECCP2 trigger also starts A/D conversion if A/D module is enabled)
1100= PWM mode; PxA, PxC active-high; PxB, PxD active-high
1101= PWM mode; PxA, PxC active-high; PxB, PxD active-low
1110= PWM mode; PxA, PxC active-low; PxB, PxD active-high
1111= PWM mode; PxA, PxC active-low; PxB, PxD active-low
Note 1: Implemented only for ECCP1 and ECCP2; same as ‘1010’ for ECCP3.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2005 Microchip Technology Inc.
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PIC18F87J10 FAMILY
17.1.2
ECCP2 OUTPUTS AND PROGRAM
MEMORY MODES
17.1 ECCP Outputs and Configuration
Each of the Enhanced CCP modules may have up to
four PWM outputs, depending on the selected
operating mode. These outputs, designated PxA
through PxD, are multiplexed with various I/O pins.
Some ECCP pin assignments are constant, while
others change based on device configuration. For
those pins that do change, the controlling bits are:
For 80-pin devices, the program memory mode of the
device (Section 5.1.3 “PIC18F8XJ10/8XJ15 Program
Memory Modes”) also impacts pin multiplexing for the
module.
The ECCP2 input/output (ECCP2/P2A) can be multi-
plexed to one of three pins. The default assignment
(CCP2MX configuration bit is set) for all devices is
RC1. Clearing CCP2MX reassigns ECCP2/P2A to
RE7.
• CCP2MX configuration bit
• ECCPMX configuration bit (80-pin devices only)
• Program Memory Operating mode, set by the
EMB configuration bits (80-pin devices only)
An additional option exists for 80-pin devices. When
these devices are operating in Microcontroller mode,
the multiplexing options described above still apply. In
Extended Microcontroller mode, clearing CCP2MX
reassigns ECCP2/P2A to RB3.
The pin assignments for the Enhanced CCP modules
are summarized in Table 17-1, Table 17-2 and
Table 17-3. To configure the I/O pins as PWM outputs,
the proper PWM mode must be selected by setting the
PxMx and CCPxMx bits (CCPxCON<7:6> and <3:0>,
respectively). The appropriate TRIS direction bits for
the corresponding port pins must also be set as
outputs.
17.1.3
USE OF CCP4 AND CCP5 WITH
ECCP1 AND ECCP3
Only the ECCP2 module has four dedicated output pins
that are available for use. Assuming that the I/O ports
or other multiplexed functions on those pins are not
needed, they may be used whenever needed without
interfering with any other CCP module.
17.1.1
ECCP1/ECCP3 OUTPUTS AND
PROGRAM MEMORY MODE
In 80-pin devices, the use of Extended Microcontroller
mode has an indirect effect on the use ECCP1 and
ECCP3 in Enhanced PWM modes. By default, PWM
outputs P1B/P1C and P3B/P3C are multiplexed to
PORTE pins, along with the high-order byte of the
external memory bus. When the bus is active in
Extended Microcontroller mode, it overrides the
Enhanced CCP outputs and makes them unavailable.
Because of this, ECCP1 and ECCP3 can only be used
in compatible (single-output) PWM modes when the
device is in Extended Microcontroller mode and default
pin configuration.
ECCP1 and ECCP3, on the other hand, only have
three dedicated output pins: ECCPx/PxA, PxB and
PxC. Whenever these modules are configured for
Quad PWM mode, the pin normally used for CCP4 or
CCP5 becomes the PxD output pins for ECCP3 and
ECCP1, respectively. The CCP4 and CCP5 modules
remain functional but their outputs are overridden.
17.1.4
ECCP MODULES AND TIMER
RESOURCES
Like the standard CCP modules, the ECCP modules
can utilize Timers 1, 2, 3 or 4, depending on the mode
selected. Timer1 and Timer3 are available for modules
in Capture or Compare modes, while Timer2 and
Timer4 are available for modules in PWM mode.
Additional details on timer resources are provided in
An exception to this configuration is when a 12-bit
address width is selected for the external bus
(EMB1:EMB0 configuration bits = 01). In this case, the
upper pins of PORTE continue to operate as digital I/O,
even when the external bus is active; P1B/P1C and
P3B/P3C remain available for use as Enhanced PWM
outputs.
Section 16.1.1
“CCP
Modules
and
Timer
Resources”.
If an application requires the use of additional PWM
outputs during Enhanced microcontroller operation, the
P1B/P1C and P3B/P3C outputs can be reassigned to
the upper bits of PORTH. This is done by clearing the
ECCPMX configuration bit.
DS39663A-page 168
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2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 17-1: PIN CONFIGURATIONS FOR ECCP1
CCP1CON
ECCP Mode
RC2
RE6
RE5
RG4
RH7
RH6
Configuration
All PIC18F6XJ10/6XJ15 Devices:
Compatible CCP 00xx 11xx
ECCP1
P1A
RE6
P1B
P1B
RE5
RE5
P1C
RG4/CCP5
RG4/CCP5
P1D
N/A
N/A
N/A
N/A
N/A
N/A
Dual PWM
Quad PWM
10xx 11xx
x1xx 11xx
P1A
PIC18F8XJ10/8XJ15 Devices, ECCPMX = 0, Microcontroller mode:
Compatible CCP 00xx 11xx
ECCP1
P1A
RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
Dual PWM
Quad PWM
10xx 11xx
x1xx 11xx
RE6/AD14 RE5/AD13 RG4/CCP5
RE6/AD14 RE5/AD13 P1D
P1B
P1B
RH6/AN14
P1C
P1A
PIC18F8XJ10/8XJ15 Devices, ECCPMX = 1, Extended Microcontroller mode, 16-bit or 20-bit Address Width:
Compatible CCP 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
PIC18F8XJ10/8XJ15 Devices, ECCPMX = 1,
Microcontroller mode or Extended Microcontroller mode, 12-bit Address Width:
Compatible CCP 00xx 11xx
ECCP1
P1A
RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
Dual PWM
Quad PWM
10xx 11xx
x1xx 11xx
P1B
P1B
RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
P1C P1D RH7/AN15 RH6/AN14
P1A
Legend: x= Don’t care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.
Note 1: With ECCP1 in Quad PWM mode, CCP5’s output is overridden by P1D; otherwise, CCP5 is fully operational.
TABLE 17-2: PIN CONFIGURATIONS FOR ECCP2
CCP2CON
ECCP Mode
RB3
RC1
RE7
RE2
RE1
RE0
Configuration
All Devices, CCP2MX = 1, either operating mode:
Compatible CCP 00xx 11xx
RB3/INT3
RB3/INT3
RB3/INT3
ECCP2
P2A
RE7
RE7
RE7
RE2
P2B
P2B
RE1
RE1
P2C
RE0
RE0
P2D
Dual PWM
Quad PWM
10xx 11xx
x1xx 11xx
P2A
All Devices, CCP2MX = 0, Microcontroller mode:
Compatible CCP 00xx 11xx
RB3/INT3 RC1/T1OS1
RB3/INT3 RC1/T1OS1
RB3/INT3 RC1/T1OS1
ECCP2
P2A
RE2
P2B
P2B
RE1
RE1
P2C
RE0
RE0
P2D
Dual PWM
Quad PWM
10xx 11xx
x1xx 11xx
P2A
PIC18F8XJ10/8XJ15 Devices, CCP2MX = 0, Extended Microcontroller mode:
Compatible CCP 00xx 11xx
ECCP2
P2A
RC1/T1OS1 RE7/AD15
RC1/T1OS1 RE7/AD15
RC1/T1OS1 RE7/AD15
RE2/CS
P2B
RE1/WR
RE1/WR
P2C
RE0/RD
RE0/RD
P2D
Dual PWM
Quad PWM
10xx 11xx
x1xx 11xx
P2A
P2B
Legend: x= Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode.
2005 Microchip Technology Inc.
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PIC18F87J10 FAMILY
TABLE 17-3: PIN CONFIGURATIONS FOR ECCP3
CCP3CON
ECCP Mode
RG0
RE4
RE3
RG3
RH5
RH4
Configuration
All PIC18F6XJ10/6XJ15 Devices:
Compatible CCP 00xx 11xx
ECCP3
P3A
RE4
P3B
P3B
RE3
RE3
P3C
RG3/CCP4
RG3/CCP4
P3D
N/A
N/A
N/A
N/A
N/A
N/A
Dual PWM
Quad PWM
10xx 11xx
x1xx 11xx
P3A
PIC18F8XJ10/8XJ15 Devices, ECCPMX = 0, Microcontroller mode:
Compatible CCP 00xx 11xx
ECCP3
P3A
RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14
Dual PWM
Quad PWM
10xx 11xx
x1xx 11xx
RE6/AD14 RE5/AD13 RG3/CCP4
RE6/AD14 RE5/AD13 P3D
P3B
P3B
RH6/AN14
P3C
P3A
PIC18F8XJ10/8XJ15 Devices, ECCPMX = 1, Extended Microcontroller mode, 16-bit or 20-bit Address Width:
Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14
PIC18F8XJ10/8XJ15 Devices, ECCPMX = 1,
Microcontroller mode or Extended Microcontroller mode, 12-bit Address Width:
Compatible CCP 00xx 11xx
ECCP3
P3A
RE4/AD12 RE3/AD11 RG3/CCP4 RH5/AN13 RH4/AN12
Dual PWM
Quad PWM
10xx 11xx
x1xx 11xx
P3B
P3B
RE3/AD11 RG3/CCP4 RH5/AN13 RH4/AN12
P3C P3D RH5/AN13 RH4/AN12
P3A
Legend: x= Don’t care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP3 in a given mode.
Note 1: With ECCP3 in Quad PWM mode, CCP4’s output is overridden by P1D; otherwise, CCP4 is fully operational.
Special Event Triggers are not implemented for
17.2 Capture and Compare Modes
ECCP3, CCP4 or CCP5. Selecting the Special Event
Except for the operation of the Special Event Trigger
mode for these modules has the same effect as select-
discussed below, the Capture and Compare modes of
ing the Compare with Software Interrupt mode
the ECCP module are identical in operation to that of
CCP4. These are discussed in detail in Section 16.2
“Capture Mode” and Section 16.3 “Compare
Mode”.
(CCPxM3:CCPxM0 = 1010).
Note:
The Special Event Trigger from ECCP2
will not set the Timer1 or Timer3 interrupt
flag bits.
17.2.1
SPECIAL EVENT TRIGGER
17.3 Standard PWM Mode
ECCP1 and ECCP2 incorporate an internal hardware
trigger that is generated in Compare mode on a match
between the CCPRx register pair and the selected
timer. This can be used in turn to initiate an action. This
mode is selected by setting CCPxCON<3:0> to ‘1011’.
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode as described in Section 16.4
“PWM Mode”. This is also sometimes referred to as
“Compatible CCP” mode as in Tables 17-1
through 17-3.
The Special Event Trigger output of either ECCP1 or
ECCP2 resets the TMR1 or TMR3 register pair,
depending on which timer resource is currently
selected. This allows the CCPRx register to effectively
be a 16-bit programmable period register for Timer1 or
Timer3. In addition, the ECCP2 Special Event Trigger
will also start an A/D conversion if the A/D module is
enabled.
Note:
When setting up single-output PWM
operations, users are free to use either of
the processes described in Section 16.4.3
“Setup for PWM Operation” or
Section 17.4.9 “Setup for PWM Opera-
tion”. The latter is more generic but will
work for either single or multi-output PWM.
DS39663A-page 170
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waveforms do not exactly match the standard PWM
waveforms but are instead offset by one full instruction
cycle (4 TOSC).
17.4 Enhanced PWM Mode
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backward compatible version of
the standard CCP module and offers up to four outputs,
designated PxA through PxD. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity
are configured by setting the PxM1:PxM0 and
CCPxM3CCPxM0 bits of the CCPxCON register
(CCPxCON<7:6> and CCPxCON<3:0>, respectively).
As before, the user must manually configure the
appropriate TRIS bits for output.
17.4.1
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
equation:
EQUATION 17-1:
For the sake of clarity, Enhanced PWM mode operation
is described generically throughout this section with
respect to ECCP1 and TMR2 modules. Control register
names are presented in terms of ECCP1. All three
Enhanced modules, as well as the two timer resources,
can be used interchangeably and function identically.
TMR2 or TMR4 can be selected for PWM operation by
selecting the proper bits in T3CON.
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
Figure 17-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to pre-
vent glitches on any of the outputs. The exception is the
PWM Delay register, ECCP1DEL, which is loaded at
either the duty cycle boundary or the boundary period
(whichever comes first). Because of the buffering, the
module waits until the assigned timer resets instead of
starting immediately. This means that Enhanced PWM
• The ECCP1 pin is set (if PWM duty cycle = 0%,
the ECCP1 pin will not be set)
• The PWM duty cycle is copied from CCPR1L into
CCPR1H
Note:
The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
FIGURE 17-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4>
P1M1<1:0>
CCP1M<3:0>
4
Duty Cycle Registers
2
CCPR1L
ECCP1/P1A
P1B
ECCP1/P1A
P1B
TRISx<x>
TRISx<x>
TRISx<x>
TRISx<x>
CCPR1H (Slave)
Comparator
TMR2
Output
Controller
R
S
Q
P1C
P1C
P1D
(Note 1)
P1D
Comparator
Clear Timer,
set ECCP1 pin and
latch D.C.
PR2
ECCP1DEL
Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit
time base.
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17.4.2
PWM DUTY CYCLE
Note:
If the PWM duty cycle value is longer than
the PWM period, the ECCP1 pin will not
be cleared.
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. The PWM duty cycle is
calculated by the equation:
17.4.3
PWM OUTPUT CONFIGURATIONS
The P1M1:P1M0 bits in the CCP1CON register allow
one of four configurations:
• Single Output
EQUATION 17-2:
• Half-Bridge Output
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
The Single Output mode is the standard PWM mode
discussed in Section 17.4 “Enhanced PWM Mode”.
The Half-Bridge and Full-Bridge Output modes are
covered in detail in the sections that follow.
CCPR1L and CCP1CON<5:4> can be written to at any
time but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
The general relationship of the outputs in all
configurations is summarized in Figure 17-2.
The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the ECCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 17-3:
FOSC
log
(
)
FPWM
bits
PWM Resolution (max) =
log(2)
TABLE 17-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
DS39663A-page 172
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FIGURE 17-2:
PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
0
PR2 + 1
Duty
Cycle
SIGNAL
CCP1CON<7:6>
Period
(Single Output)
(Half-Bridge)
00
10
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(1)
(1)
Delay
Delay
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
01
(Full-Bridge,
Reverse)
11
P1D Inactive
FIGURE 17-3:
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
Duty
Cycle
PR2 + 1
SIGNAL
CCP1CON<7:6>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
(Half-Bridge)
00
10
(1)
(1)
Delay
Delay
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Forward)
01
(Full-Bridge,
Reverse)
11
P1D Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 17.4.6 “Programmable
Dead-Band Delay”).
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17.4.4
HALF-BRIDGE MODE
FIGURE 17-4:
HALF-BRIDGE PWM
OUTPUT
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output
signal is output on the P1A pin, while the complemen-
tary PWM output signal is output on the P1B pin
(Figure 17-4). This mode can be used for half-bridge
applications, as shown in Figure 17-5, or for full-bridge
applications, where four power switches are being
modulated with two PWM signals.
Period
Period
Duty Cycle
(2)
(2)
P1A
td
td
P1B
In Half-Bridge Output mode, the programmable
dead-band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
PDC6:PDC0 sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 17.4.6
“Programmable Dead-Band Delay” for more details
on dead-band delay operations.
(1)
(1)
(1)
td = Dead Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTE<6> data latches, the
TRISC<2> and TRISE<6> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 17-5:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
PIC18F87J10
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18F87J10
FET
FET
Driver
Driver
P1A
Load
FET
FET
Driver
Driver
P1B
V-
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P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTC<2>, PORTE<6:5> and PORTG<4> data
latches. The TRISC<2>, TRISC<6:5> and TRISG<4>
bits must be cleared to make the P1A, P1B, P1C and
P1D pins outputs.
17.4.5
FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as
outputs; however, only two outputs are active at a time.
In the Forward mode, pin P1A is continuously active
and pin P1D is modulated. In the Reverse mode, pin
P1C is continuously active and pin P1B is modulated.
These are illustrated in Figure 17-6.
FIGURE 17-6:
FULL-BRIDGE PWM OUTPUT
Forward Mode
Period
(2)
P1A
Duty Cycle
(2)
(2)
P1B
P1C
(2)
P1D
(1)
(1)
Reverse Mode
Period
Duty Cycle
(2)
P1A
(2)
P1B
(2)
P1C
(2)
P1D
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active-high.
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FIGURE 17-7:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC18F87J10
QC
QA
FET
Driver
FET
Driver
P1A
Load
P1B
FET
Driver
FET
Driver
P1C
P1D
QD
QB
V-
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
17.4.5.1
Direction Change in Full-Bridge Mode
In the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows users to control the forward/
reverse direction. When the application firmware
changes this direction control bit, the module will
assume the new direction on the next PWM cycle.
2. The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on time.
Figure 17-9 shows an example where the PWM direc-
tion changes from forward to reverse at a near 100%
duty cycle. At time t1, the outputs P1A and P1D
become inactive, while output P1C becomes active. In
this example, since the turn-off time of the power
devices is longer than the turn-on time, a shoot-through
current may flow through power devices QC and QD
(see Figure 17-7) for the duration of ‘t’. The same
phenomenon will occur to power devices QA and QB
for PWM direction change from reverse to forward.
Just before the end of the current PWM period, the
modulated outputs (P1B and P1D) are placed in their
inactive state, while the unmodulated outputs (P1A and
P1C) are switched to drive in the opposite direction.
This occurs in a time interval of (4 TOSC * (Timer2
Prescale Value) before the next PWM period begins.
The Timer2 prescaler will be either 1, 4 or 16, depend-
ing on the value of the T2CKPS bit (T2CON<1:0>).
During the interval from the switch of the unmodulated
outputs to the beginning of the next period, the
modulated outputs (P1B and P1D) remain inactive.
This relationship is shown in Figure 17-8.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
Note that in the Full-Bridge Output mode, the ECCP1
module does not provide any dead-band delay. In gen-
eral, since only one output is modulated at all times,
dead-band delay is not required. However, there is a
situation where a dead-band delay might be required.
This situation occurs when both of the following
conditions are true:
1. Reduce PWM for
changing directions.
a PWM period before
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
DS39663A-page 176
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FIGURE 17-8:
PWM DIRECTION CHANGE
(1)
Period
Period
SIGNAL
P1A (Active-High)
P1B (Active-High)
DC
P1C (Active-High)
P1D (Active-High)
(Note 2)
DC
Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written at any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals
of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals
are inactive at this time.
FIGURE 17-9:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
Reverse Period
t1
(1)
(1)
P1A
P1B
DC
(1)
P1C
P1D
(1)
DC
(2)
t
ON
(1)
(1)
External Switch C
External Switch D
(3)
t
OFF
(2,3)
Potential
t = t
– t
ON
OFF
Shoot-Through
(1)
Current
Note 1: All signals are shown as active-high.
2:
3:
t
t
is the turn-on delay of power switch QC and its driver.
ON
is the turn-off delay of power switch QD and its driver.
OFF
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A shutdown event can be caused by either of the two
comparator modules or the INT0 pin (or any combination
of these three sources). The comparators may be used
to monitor a voltage input proportional to a current being
monitored in the bridge circuit. If the voltage exceeds a
threshold, the comparator switches state and triggers a
shutdown. Alternatively, a digital signal on the INT0 pin
can also trigger a shutdown. The auto-shutdown feature
can be disabled by not selecting any auto-shutdown
sources. The auto-shutdown sources to be used are
selected using the ECCP1AS2:ECCP1AS0 bits
(bits<6:4> of the ECCP1AS register).
17.4.6
PROGRAMMABLE DEAD-BAND
DELAY
In half-bridge applications, where all power switches
are modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current
(shoot-through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from flow-
ing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states,
specified
by
the
PSS1AC1:PSS1AC0
and
PSS1BD1:PSS1BD0 bits (ECCP1AS3:ECCP1AS0).
Each pin pair (P1A/P1C and P1B/P1D) may be set to
drive high, drive low or be tri-stated (not driving). The
ECCP1ASE bit (ECCP1AS<7>) is also set to hold the
Enhanced PWM outputs in their shutdown states.
In the Half-Bridge Output mode, a digitally program-
mable dead-band delay is available to avoid
shoot-through current from destroying the bridge
power switches. The delay occurs at the signal
transition from the non-active state to the active state.
See Figure 17-4 for illustration. The lower seven bits of
the ECCPxDEL register (Register 17-2) set the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC).
The ECCP1ASE bit is set by hardware when a shut-
down event occurs. If automatic restarts are not
enabled, the ECCPASE bit is cleared by firmware when
the cause of the shutdown clears. If automatic restarts
are enabled, the ECCPASE bit is automatically cleared
when the cause of the auto-shutdown has cleared.
17.4.7
ENHANCED PWM
AUTO-SHUTDOWN
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
When the ECCP1 is programmed for any of the
Enhanced PWM modes, the active output pins may be
configured for auto-shutdown. Auto-shutdown immedi-
ately places the Enhanced PWM output pins into a
defined shutdown state when a shutdown event
occurs.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
REGISTER 17-2: ECCPxDEL: PWM CONFIGURATION REGISTER
R/W-0
PxRSEN
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PxDC6
PxDC5
PxDC4
PxDC3
PxDC2
PxDC1
PxDC0
bit 0
bit 7
PxRSEN: PWM Restart Enable bit
1= Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event
goes away; the PWM restarts automatically
0= Upon auto-shutdown, ECCPxASE must be cleared in software to restart the PWM
bit 6-0
PxDC6:PxDC0: PWM Delay Count bits
Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for
a PWM signal to transition to active.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 17-3: ECCPxAS: ENHANCED CCP AUTO-SHUTDOWN CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0
bit 7
bit 0
bit 7
ECCPxASE: ECCP Auto-Shutdown Event Status bit
0= ECCP outputs are operating
1= A shutdown event has occurred; ECCP outputs are in shutdown state
bit 6-4
ECCPxAS2:ECCPxAS0: ECCP Auto-Shutdown Source Select bits
000= Auto-shutdown is disabled
001= Comparator 1 output
010= Comparator 2 output
011= Either Comparator 1 or 2
100= INT0
101= INT0 or Comparator 1
110= INT0 or Comparator 2
111= INT0 or Comparator 1 or Comparator 2
bit 3-2
bit 1-0
PSSxAC1:PSSxAC0: Pins A and C Shutdown State Control bits
00= Drive Pins A and C to ‘0’
01= Drive Pins A and C to ‘1’
1x= Pins A and C tri-state
PSSxBD1:PSSxBD0: Pins B and D Shutdown State Control bits
00= Drive Pins B and D to ‘0’
01= Drive Pins B and D to ‘1’
1x= Pins B and D tri-state
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
The Auto-Shutdown mode can be forced by writing a ‘1’
to the ECCPASE bit.
17.4.7.1
Auto-Shutdown and Automatic
Restart
The auto-shutdown feature can be configured to allow
automatic restarts of the module following a shutdown
event. This is enabled by setting the P1RSEN bit of the
ECCP1DEL register (ECCP1DEL<7>).
17.4.8
START-UP CONSIDERATIONS
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external
pull-up and/or pull-down resistors on the PWM output
pins. When the microcontroller is released from Reset,
all of the I/O pins are in the high-impedance state. The
external circuits must keep the power switch devices in
the OFF state until the microcontroller drives the I/O
pins with the proper signal levels, or activates the PWM
output(s).
In Shutdown mode with P1RSEN = 1 (Figure 17-10),
the ECCPASE bit will remain set for as long as the
cause of the shutdown continues. When the shutdown
condition clears, the ECCP1ASE bit is cleared. If
P1RSEN = 0 (Figure 17-11), once a shutdown condi-
tion occurs, the ECCP1ASE bit will remain set until it is
cleared by firmware. Once ECCP1ASE is cleared, the
Enhanced PWM will resume at the beginning of the
next PWM period.
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output
polarities must be selected before the PWM pins are
configured as outputs. Changing the polarity configura-
tion while the PWM pins are configured as outputs is
not recommended since it may result in damage to the
application circuits.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
Independent of the P1RSEN bit setting, if the
auto-shutdown source is one of the comparators, the
shutdown condition is a level. The ECCP1ASE bit
cannot be cleared as long as the cause of the shutdown
persists.
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The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is initialized.
Enabling the PWM pins for output at the same time as
the ECCP module may cause damage to the applica-
tion circuit. The ECCP module must be enabled in the
proper output mode and complete a full PWM cycle
before configuring the PWM pins as outputs. The com-
pletion of a full PWM cycle is indicated by the TMR2IF
bit being set as the second PWM period begins.
FIGURE 17-10:
PWM AUTO-SHUTDOWN (P1RSEN = 1, AUTO-RESTART ENABLED)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
Start of
PWM Period
Shutdown
Event Occurs Event Clears
Shutdown
PWM
Resumes
FIGURE 17-11:
PWM AUTO-SHUTDOWN (P1RSEN = 0, AUTO-RESTART DISABLED)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
ECCPASE
Cleared by
Start of
PWM Period
Shutdown
Event Occurs Event Clears
Shutdown Firmware PWM
Resumes
DS39663A-page 180
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PIC18F87J10 FAMILY
8. If auto-restart operation is required, set the
PxRSEN bit (ECCPxDEL<7>).
17.4.9
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCPx module for PWM operation:
9. Configure and start TMRn (TMR2 or TMR4):
• Clear the TMRn interrupt flag bit by clearing
the TMRnIF bit (PIR1<1> for Timer2 or
PIR3<3> for Timer4).
1. Configure the PWM pins PxA and PxB (and PxC
and PxD, if used) as inputs by setting the
corresponding TRIS bits.
• Set the TMRn prescale value by loading the
TnCKPS bits (TnCON<1:0>).
2. Set the PWM period by loading the PR2 (PR4)
register.
• Enable Timer2 (or Timer4) by setting the
TMRnON bit (TnCON<2>).
3. Configure the ECCPx module for the desired
PWM mode and configuration by loading the
CCPxCON register with the appropriate values:
10. Enable PWM outputs after a new PWM cycle
has started:
• Select one of the available output
configurations and direction with the
PxM1:PxM0 bits.
• Wait until TMRn overflows (TMRnIF bit is set).
• Enable the ECCPx/PxA, PxB, PxC and/or
PxD pin outputs by clearing the respective
TRIS bits.
• Select the polarities of the PWM output
signals with the CCPxM3:CCPxM0 bits.
• Clear the ECCPASE bit (ECCPxAS<7>).
4. Set the PWM duty cycle by loading the CCPRxL
register and the CCPxCON<5:4> bits.
17.4.10 EFFECTS OF A RESET
5. For auto-shutdown:
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the CCP registers to their
Reset states.
• Disable auto-shutdown; ECCPAS = 0
• Configure auto-shutdown source
• Wait for Run condition
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
6. For Half-Bridge Output mode, set the
dead-band delay by loading ECCPxDEL<6:0>
with the appropriate value.
7. If auto-shutdown operation is required, load the
ECCPxAS register:
• Select the auto-shutdown sources using the
ECCPxAS2:ECCPxAS0 bits.
• Select the shutdown states of the PWM
output pins using PSSxAC1:PSSxAC0 and
PSSxBD1:PSSxBD0 bits.
• Set the ECCPxASE bit (ECCPxAS<7>).
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TABLE 17-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TMR0IF
PD
INT0IF
POR
RBIF
BOR
49
50
51
51
51
51
51
51
51
51
51
52
52
52
52
52
50
50
50
50
50
50
51
51
51
53
53
53
51
51,
51
51, 53
53
IPEN
PSPIF
—
—
TO
ADIF
RC1IF
RC1IE
RC1IP
—
TX1IF
TX1IE
TX1IP
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TMR4IF
TMR4IE
TMR4IP
TRISB3
TRISC3
TRISE3
TRISG3
TRISH3
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
PSPIE
PSPIP
OSCFIF
OSCFIE
OSCFIP
SSP2IF
SSP2IE
SSP2IP
TRISB7
TRISC7
TRISE7
—
ADIE
IPR1
ADIP
PIR2
CMIF
—
—
—
TMR3IF CCP2IF
TMR3IE CCP2IE
TMR3IP CCP2IP
PIE2
CMIE
—
—
IPR2
CMIP
—
—
PIR3
BCL2IF
BCL2IE
BCL2IP
TRISB6
TRISC6
TRISE6
—
RC2IF
RC2IE
RC2IP
TRISB5
TRISC5
TRISE5
—
TX2IF
TX2IE
TX2IP
TRISB4
TRISC4
TRISE4
TRISG4
TRISH4
CCP5IF CCP4IF CCP3IF
CCP5IE CCP4IE CCP3IE
CCP5IP CCP4IP CCP3IP
TRISB2 TRISB1 TRISB0
TRISC2 TRISC1 TRISC0
TRISE2 TRISE1 TRISE0
TRISG2 TRISG1 TRISG0
TRISH2 TRISH1 TRISH0
PIE3
IPR3
TRISB
TRISC
TRISE
TRISG
TRISH
TMR1L
TMR1H
T1CON
TMR2
T2CON
PR2
TRISH7
TRISH6
TRISH5
Timer1 Register Low Byte
Timer1 Register High Byte
RD16
Timer2 Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
—
Timer2 Period Register
Timer3 Register Low Byte
Timer3 Register High Byte
TMR3L
TMR3H
T3CON
TMR4
T4CON
PR4
RD16
Timer4 Register
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
T3CCP2
T3CKPS1 T3CKPS0
T3CCP1 T3SYNC TMR3CS TMR3ON
—
Timer4 Period Register
(1)
CCPRxL
CCPRxH
Capture/Compare/PWM Register x Low Byte
Capture/Compare/PWM Register x High Byte
(1)
(1)
CCPxCON
PxM1
PxM0
DCxB1
DCxB0
CCPxM3 CCPxM2 CCPxM1 CCPxM0
(1)
ECCPxAS
ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0
(1)
ECCPxDEL
PxRSEN
PxDC6
PxDC5
PxDC4
PxDC3
PxDC2
PxDC1
PxDC0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: Generic term for all of the identical registers of this name for all Enhanced CCP modules, where ‘x’ identifies the
individual module (ECCP1, ECCP2 or ECCP3). Bit assignments and Reset values for all registers of the same
generic name are identical.
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18.3 SPI Mode
18.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
18.1 Master SSP (MSSP) Module
Overview
• Serial Data Out (SDOx) – RC5/SDO1 or
RD4/SDO2
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Data In (SDIx) – RC4/SDI1/SDA1 or
RD5/SDI2/SDA2
• Serial Clock (SCKx) – RC3/SCK1/SCL1 or
RD6/SCK2/SCL2
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Serial Peripheral Interface (SPI™)
• Inter-Integrated Circuit (I2C™)
- Full Master mode
• Slave Select (SSx) – RF7/SS1 or RD7/SS2
Figure 18-1 shows the block diagram of the MSSP
module when operating in SPI mode.
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
FIGURE 18-1:
MSSP BLOCK DIAGRAM
(SPI™ MODE)
• Master mode
• Multi-Master mode
• Slave mode
Internal
Data Bus
Read
Write
All members of the PIC18F87J10 family have two
MSSP modules, designated as MSSP1 and MSSP2.
Each module operates independently of the other.
SSPxBUF reg
SSPxSR reg
Note:
Throughout this section, generic refer-
ences to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names and module I/O
signals use the generic designator ‘x’ to
indicate the use of a numeral to distinguish
RC4 or RD5
RC5 or RD4
Shift
Clock
bit 0
a
particular module, when required.
RF7 or RD7
Control bit names are not individuated.
Control
Enable
SSx
18.2 Control Registers
Edge
Select
Each MSSP module has three associated control
registers. These include a status register (SSPxSTAT)
and two control registers (SSPxCON1 and
SSPxCON2). The use of these registers and their indi-
vidual configuration bits differ significantly depending
on whether the MSSP module is operated in SPI or I2C
mode.
2
Clock Select
SSPM3:SSPM0
SMP:CKE
2
4
TMR2 Output
(
)
2
Edge
Select
Additional details are provided under the individual
sections.
TOSC
Prescaler
4, 16, 64
RC3 or RD6
Note:
In devices with more than one MSSP
module, it is very important to pay close
attention to SSPCON register names.
SSP1CON1 and SSP1CON2 control
different operational aspects of the same
Data to TXx/RXx in SSPxSR
TRIS bit
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list
of multiplexed functions.
module,
while
SSP1CON1
and
SSP2CON1 control the same features for
two different modules.
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SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
18.3.1
REGISTERS
Each MSSP module has four registers for SPI mode
operation. These are:
In receive operations, SSPxSR and SSPxBUF
together create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
• MSSP Control Register 1 (SSPxCON1)
• MSSP Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
• MSSP Shift Register (SSPxSR) – Not directly
accessible
SSPxCON1 and SSPxSTAT are the control and status
registers in SPI mode operation. The SSPxCON1
register is readable and writable. The lower 6 bits of
the SSPxSTAT are read-only. The upper two bits of the
SSPxSTAT are read/write.
REGISTER 18-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
bit 6
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Select bit
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
Note:
Polarity of clock state is set by the CKP bit (SSPxCON1<4>).
bit 5
bit 4
D/A: Data/Address bit
Used in I2C mode only.
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is
cleared.
bit 3
bit 2
bit 1
bit 0
S: Start bit
Used in I2C mode only.
R/W: Read/Write Information bit
Used in I2C mode only.
UA: Update Address bit
Used in I2C mode only.
BF: Buffer Full Status bit (Receive mode only)
1= Receive complete, SSPxBUF is full
0= Receive not complete, SSPxBUF is empty
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 18-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
bit 6
WCOL: Write Collision Detect bit (Transmit mode only)
1= The SSPxBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0= No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1= A new byte is received while the SSPxBUF register is still holding the previous data. In case
of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be
cleared in software).
0= No overflow
Note:
In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPxBUF register.
bit 5
bit 4
SSPEN: Synchronous Serial Port Enable bit
1= Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins
0= Disables serial port and configures these pins as I/O port pins
Note:
When enabled, these pins must be properly configured as input or output.
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level
0= Idle state for clock is a low level
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101= SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin
0100= SPI Slave mode, clock = SCKx pin, SSx pin control enabled
0011= SPI Master mode, clock = TMR2 output/2
0010= SPI Master mode, clock = FOSC/64
0001= SPI Master mode, clock = FOSC/16
0000= SPI Master mode, clock = FOSC/4
Note:
Bit combinations not specifically listed here are either reserved or implemented in
I2C mode only.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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write to the SSPxBUF register during transmis-
sion/reception of data will be ignored and the Write
Collision detect bit, WCOL (SSPxCON1<7>), will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the
SSPxBUF register completed successfully.
18.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the next
byte of data to transfer is written to the SSPxBUF. The
Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. The SSPxBUF must be read and/or
written. If the interrupt method is not going to be used,
then software polling can be done to ensure that a write
collision does not occur. Example 18-1 shows the
loading of the SSP1BUF (SSP1SR) for data
transmission.
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCKx)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Each MSSP consists of a transmit/receive shift register
(SSPxSR) and a buffer register (SSPxBUF). The
SSPxSR shifts the data in and out of the device, MSb
first. The SSPxBUF holds the data that was written to
the SSPxSR until the received data is ready. Once the
8 bits of data have been received, that byte is moved to
the SSPxBUF register. Then, the Buffer Full detect bit
BF (SSPxSTAT<0>) and the interrupt flag bit SSPxIF
are set. This double-buffering of the received data
(SSPxBUF) allows the next byte to start reception
before reading the data that was just received. Any
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various status conditions.
EXAMPLE 18-1:
LOADING THE SSP1BUF (SSP1SR) REGISTER
LOOP
BTFSS
BRA
SSP1STAT, BF
LOOP
;Has data been received (transmit complete)?
;No
MOVF
SSP1BUF, W
;WREG reg = contents of SSP1BUF
MOVWF
RXDATA
;Save in user RAM, if data is meaningful
MOVF
MOVWF
TXDATA, W
SSP1BUF
;W reg = contents of TXDATA
;New data to xmit
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Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
18.3.3
ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN
(SSPxCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPxCON registers and then set the SSPEN bit. This
configures the SDIx, SDOx, SCKx and SSx pins as
serial port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed as
follows:
18.3.4
TYPICAL CONNECTION
Figure 18-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCKx signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• SDIx is automatically controlled by the SPI module
• SDOx must have TRISC<5> (or TRISD<4>) bit
cleared
• SCKx (Master mode) must have TRISC<3> (or
TRISD<6>) bit cleared
• SCKx (Slave mode) must have TRISC<3> (or
TRISD<6>) bit set
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• SSx must have TRISF<7> (or TRISD<7>) bit set
• Master sends dummy data – Slave sends data
FIGURE 18-2:
SPI™ MASTER/SLAVE CONNECTION
SPI™ Master SSPM3:SSPM0 = 00xxb
SPI™ Slave SSPM3:SSPM0 = 010xb
SDIx
SDOx
Serial Input Buffer
(SSPxBUF)
Serial Input Buffer
(SSPxBUF)
SDIx
SDOx
Shift Register
(SSPxSR)
Shift Register
(SSPxSR)
LSb
MSb
MSb
LSb
Serial Clock
SCKx
SCKx
PROCESSOR 1
PROCESSOR 2
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The clock polarity is selected by appropriately
programming the CKP bit (SSPxCON1<4>). This then,
would give waveforms for SPI communication as
shown in Figure 18-3, Figure 18-5 and Figure 18-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
18.3.5
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCKx. The master determines
when the slave (Processor 2, Figure 18-2) will
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDOx output could be dis-
abled (programmed as an input). The SSPxSR register
will continue to shift in the signal present on the SDIx
pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 18-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDOx data is valid before
there is a clock edge on SCKx. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
FIGURE 18-3:
SPI™ MODE WAVEFORM (MASTER MODE)
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
4 Clock
Modes
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDOx
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDOx
(CKE = 1)
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDIx
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPxIF
Next Q4 Cycle
after Q2↓
SSPxSR to
SSPxBUF
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SDOx pin is driven. When the SSx pin goes high, the
SDOx pin is no longer driven, even if in the middle of a
transmitted byte and becomes a floating output.
External pull-up/pull-down resistors may be desirable
depending on the application.
18.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCKx. When the
last bit is latched, the SSPxIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCKx pin. The Idle
state is determined by the CKP bit (SSPxCON1<4>).
Note 1: When the SPI is in Slave mode with SSx pin
control enabled (SSPxCON1<3:0> = 0100),
the SPI module will reset if the SSx pin is set
to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCKx pin. This
external clock must meet the minimum high and low
times as specified in the electrical specifications.
2: If the SPI is used in Slave mode with CKE
set, then the SSx pin control must be
enabled.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SSx pin to
a high level or clearing the SSPEN bit.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
To emulate two-wire communication, the SDOx pin can
be connected to the SDIx pin. When the SPI needs to
operate as a receiver, the SDOx pin can be configured
as an input. This disables transmissions from the
SDOx. The SDIx can always be left as an input (SDIx
function) since it cannot create a bus conflict.
18.3.7
SLAVE SELECT
SYNCHRONIZATION
The SSx pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SSx pin control
enabled (SSPxCON1<3:0> = 04h). When the SSx pin
is low, transmission and reception are enabled and the
FIGURE 18-4:
SLAVE SYNCHRONIZATION WAVEFORM
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
bit 6
bit 7
bit 7
bit 0
SDOx
bit 7
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2
↓
SSPxSR to
SSPxBUF
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FIGURE 18-5:
SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SSx
Optional
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDOx
bit 7
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPxSR to
SSPxBUF
FIGURE 18-6:
SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SSx
Not Optional
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF
bit 6
bit 3
bit 2
bit 5
bit 4
bit 1
bit 0
SDOx
bit 7
bit 7
SDIx
(SMP = 0)
bit 0
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPxSR to
SSPxBUF
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18.3.8
OPERATION IN POWER-MANAGED
MODES
18.3.10 BUS MODE COMPATIBILITY
Table 18-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of Sleep mode, all clocks are halted.
TABLE 18-1: SPI™ BUS MODES
In Idle modes, a clock is provided to the peripherals.
That clock should be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTOSC source. See Section 2.6 “Clock Sources
and Oscillator Switching” for additional information.
Control Bits State
Standard SPI™ Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
There is also an SMP bit which controls when the data
is sampled.
18.3.11 SPI CLOCK SPEED AND MODULE
INTERACTIONS
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
Because MSSP1 and MSSP2 are independent
modules, they can operate simultaneously at different
data rates. Setting the SSPM3:SSPM0 bits of the
SSPxCON1 register determines the rate for the
corresponding module.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Trans-
mit/Receive Shift register. When all 8 bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
An exception is when both modules use Timer2 as a
time base in Master mode. In this instance, any
changes to the Timer2 operation will affect both MSSP
modules equally. If different bit rates are required for
each module, the user should select one of the other
three time base options for one of the modules.
18.3.9
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
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TABLE 18-2: REGISTERS ASSOCIATED WITH SPI™ OPERATION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
CCP5IF
CCP5IE
CCP5IP
TRISC2
TRISD2
TRISF2
INT0IF
RBIF
49
51
51
51
51
51
51
52
52
52
50
50
50
53
53
53
PSPIF
PSPIE
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
TRISC5
TRISD5
TRISF5
SSP1IF
SSP1IE
SSP1IP
TMR4IF
TMR4IE
TMR4IP
TRISC3
TRISD3
TRISF3
TMR2IF
TMR1IF
PIE1
TX1IE
TX1IP
TX2IF
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
PSPIP
ADIP
PIR3
SSP2IF
SSP2IE
SSP2IP
TRISC7
TRISD7
TRISF7
BCL2IF
BCL2IE
BCL2IP
TRISC6
TRISD6
TRISF6
CCP4IF
CCP4IE
CCP4IP
TRISC1
TRISD1
TRISF1
CCP3IF
CCP3IE
CCP3IP
TRISC0
TRISD0
—
PIE3
TX2IE
TX2IP
TRISC4
TRISD4
TRISF4
IPR3
TRISC
TRISD
TRISF
SSP1BUF MSSP1 Receive Buffer/Transmit Register
SSP1CON1 WCOL
SSP1STAT SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
SSP2BUF MSSP2 Receive Buffer/Transmit Register
SSP2CON1 WCOL
SSP2STAT SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
Legend: Shaded cells are not used by the MSSP module in SPI™ mode.
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2
18.4.1
REGISTERS
18.4 I C Mode
The MSSP module has six registers for I2C operation.
These are:
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
• MSSP Control Register 1 (SSPxCON1)
• MSSP Control Register 2 (SSPxCON2)
• MSSP Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
Two pins are used for data transfer:
• MSSP Shift Register (SSPxSR) – Not directly
accessible
• Serial clock (SCLx) – RC3/SCK1/SCL1 or
RD6/SCK2/SCL2
• MSSP Address Register (SSPxADD)
• Serial data (SDAx) – RC4/SDI1/SDA1 or
RD5/SDI2/SDA2
SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I2C mode operation. The
SSPxCON1 and SSPxCON2 registers are readable and
writable. The lower 6 bits of the SSPxSTAT are
read-only. The upper two bits of the SSPxSTAT are
read/write.
The user must configure these pins as inputs by setting
the TRISC<4:3> or TRISD<5:4> bits.
FIGURE 18-7:
MSSP BLOCK DIAGRAM
(I2C™ MODE)
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
Internal
Data Bus
SSPxADD register holds the slave device address
when the SSP is configured in I2C Slave mode. When
the SSP is configured in Master mode, the lower seven
bits of SSPxADD act as the Baud Rate Generator
reload value.
Read
Write
RC3 or
RD6
SSPxBUF reg
Shift
Clock
In receive operations, SSPxSR and SSPxBUF
together create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
SSPxSR reg
LSb
RC4 or
RD5
MSb
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
Match Detect
Addr Match
SSPxADD reg
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPxSTAT reg)
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list
of multiplexed functions.
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REGISTER 18-3: SSPxSTAT: MSSPx STATUS REGISTER (I2C MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6
bit 5
CKE: SMBus Select bit
In Master or Slave mode:
1= Enable SMBus specific inputs
0= Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
bit 4
bit 3
bit 2
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Note:
This bit is cleared on Reset and when SSPEN is cleared.
S: Start bit
1= Indicates that a Start bit has been detected last
0= Start bit was not detected last
Note:
This bit is cleared on Reset and when SSPEN is cleared.
R/W: Read/Write Information bit (I2C mode only)
In Slave mode:
1= Read
0= Write
Note:
This bit holds the R/W bit information following the last address match. This bit is
only valid from the address match to the next Start bit, Stop bit or not ACK bit.
In Master mode:
1= Transmit is in progress
0= Transmit is not in progress
Note:
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is
in Active mode.
bit 1
bit 0
UA: Update Address bit (10-bit Slave mode only)
1= Indicates that the user needs to update the address in the SSPxADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
In Transmit mode:
1= SSPxBUF is full
0= SSPxBUF is empty
In Receive mode:
1= SSPxBUF is full (does not include the ACK and Stop bits)
0= SSPxBUF is empty (does not include the ACK and Stop bits)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 18-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1= A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0= No collision
In Slave Transmit mode:
1= The SSPxBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0= No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1= A byte is received while the SSPxBUF register is still holding the previous byte (must be
cleared in software)
0= No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
bit 4
SSPEN: Synchronous Serial Port Enable bit
1= Enables the serial port and configures the SDAx and SCLx pins as the serial port pins
0= Disables serial port and configures these pins as I/O port pins
Note:
When enabled, the SDAx and SCLx pins must be properly configured as input or
output.
CKP: SCKx Release Control bit
In Slave mode:
1= Release clock
0= Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011= I2C Firmware Controlled Master mode (Slave Idle)
1000= I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1))
0111= I2C Slave mode, 10-bit address
0110= I2C Slave mode, 7-bit address
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 18-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C MODE)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEN(1)
ACKSTAT
ACKDT
ACKEN(1) RCEN(1) PEN(1) RSEN(1)
bit 7
bit 0
bit 7
bit 6
bit 5
GCEN: General Call Enable bit (Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPxSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1= Not Acknowledge
0= Acknowledge
Note:
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1)
1= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence Idle
bit 3
bit 2
RCEN: Receive Enable bit (Master mode only)(1)
1= Enables Receive mode for I2C
0= Receive Idle
PEN: Stop Condition Enable bit (Master mode only)(1)
1= Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0= Stop condition Idle
bit 1
bit 0
RSEN: Repeated Start Condition Enable bit (Master mode only)(1)
1= Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by
hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enable/Stretch Enable bit(1)
In Master mode:
1= Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0= Start condition Idle
In Slave mode:
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
these bits may not be set (no spooling) and the SSPxBUF may not be written (or
writes to the SSPxBUF are disabled).
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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18.4.2
OPERATION
18.4.3.1
Addressing
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPxCON1<5>).
The SSPxCON1 register allows control of the I2C
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPxSR register. All
incoming bits are sampled with the rising edge of the
clock (SCLx) line. The value of register SSPxSR<7:1>
is compared to the value of the SSPxADD register. The
address is compared on the falling edge of the eighth
clock (SCLx) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
operation.
Four
mode
selection
bits
(SSPxCON1<3:0>) allow one of the following I2C
modes to be selected:
• I2C Master mode,
clock = (FOSC/4) x (SSPxADD + 1)
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode,
slave is Idle
1. The SSPxSR register value is loaded into the
SSPxBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. The MSSP Interrupt Flag bit, SSPxIF, is set (and
interrupt is generated, if enabled) on the falling
edge of the ninth SCLx pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPxSTAT<2>) must specify a write
so the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the
address. The sequence of events for 10-bit address is as
follows, with steps 7 through 9 for the slave-transmitter:
Selection of any I2C mode, with the SSPEN bit set,
forces the SCLx and SDAx pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCLx and SDAx pins.
18.4.3
SLAVE MODE
In Slave mode, the SCLx and SDAx pins must be
configured as inputs (TRISC<4:3> or TRISD<5:4> set).
The MSSP module will override the input state with the
output data when required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
1. Receive first (high) byte of address (bits SSPxIF,
BF and UA (SSPxSTAT<1>) are set).
2. Update the SSPxADD register with second (low)
byte of address (clears bit UA and releases the
SCLx line).
3. Read the SSPxBUF register (clears bit BF) and
clear flag bit SSPxIF.
4. Receive second (low) byte of address (bits
SSPxIF, BF and UA are set).
When an address is matched, or the data transfer after
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK) pulse
and load the SSPxBUF register with the received value
currently in the SSPxSR register.
5. Update the SSPxADD register with the first
(high) byte of address. If match releases SCLx
line, this will clear bit UA.
6. Read the SSPxBUF register (clears bit BF) and
clear flag bit SSPxIF.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
7. Receive Repeated Start condition.
• The Buffer Full bit, BF (SSPxSTAT<0>), was set
before the transfer was received.
8. Receive first (high) byte of address (bits SSPxIF
and BF are set).
• The overflow bit, SSPOV (SSPxCON1<6>), was
set before the transfer was received.
9. Read the SSPxBUF register (clears bit BF) and
clear flag bit SSPxIF.
In this case, the SSPxSR register value is not loaded
into the SSPxBUF, but bit SSPxIF is set. The BF bit is
cleared by reading the SSPxBUF register, while bit
SSPOV is cleared through software.
The SCLx clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101.
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18.4.3.2
Reception
18.4.3.3
Transmission
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPxSTAT
register is cleared. The received address is loaded into
the SSPxBUF register and the SDAx line is held low
(ACK).
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3 or RD6 is held low,
regardless of SEN (see Section 18.4.4 “Clock
Stretching” for more details). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPxBUF regis-
ter which also loads the SSPxSR register. Then pin
RC3 or RD6 should be enabled by setting bit, CKP
(SSPxCON1<4>). The eight data bits are shifted out on
the falling edge of the SCLx input. This ensures that the
SDAx signal is valid during the SCLx high time
(Figure 18-9).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPxSTAT<0>) is
set, or bit SSPOV (SSPxCON1<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. The interrupt flag bit, SSPxIF, must be cleared in
software. The SSPxSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPxCON2<0> = 1), SCKx/SCLx
(RC3 or RD6) will be held low (clock stretch) following
each data transfer. The clock must be released by
setting bit, CKP (SSPxCON1<4>). See Section 18.4.4
“Clock Stretching” for more details.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCLx input pulse. If the
SDAx line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPxSTAT
register) and the slave monitors for another occurrence
of the Start bit. If the SDAx line was low (ACK), the next
transmit data must be loaded into the SSPxBUF regis-
ter. Again, pin RC3 or RD6 must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared in software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.
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FIGURE 18-8:
I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
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FIGURE 18-9:
I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
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FIGURE 18-10:
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
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FIGURE 18-11:
I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
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18.4.4
CLOCK STRETCHING
18.4.4.3
Clock Stretching for 7-bit Slave
Transmit Mode
Both 7-bit and 10-bit Slave modes implement
automatic clock stretching during a transmit sequence.
The 7-bit Slave Transmit mode implements clock
stretching by clearing the CKP bit after the falling edge
of the ninth clock, if the BF bit is clear. This occurs
regardless of the state of the SEN bit.
The SEN bit (SSPxCON2<0>) allows clock stretching
to be enabled during receives. Setting SEN will cause
the SCLx pin to be held low at the end of each data
receive sequence.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCLx line
low, the user has time to service the ISR and load the
contents of the SSPxBUF before the master device
can initiate another transmit sequence (see
Figure 18-9).
18.4.4.1
Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPxCON1 register is
automatically cleared, forcing the SCLx output to be
held low. The CKP being cleared to ‘0’ will assert the
SCLx line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCLx line low, the user has time to service the ISR
and read the contents of the SSPxBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 18-13).
Note 1: If the user loads the contents of
SSPxBUF, setting the BF bit before the
falling edge of the ninth clock, the CKP bit
will not be cleared and clock stretching
will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
18.4.4.4
Clock Stretching for 10-bit Slave
Transmit Mode
Note 1: If the user reads the contents of the
SSPxBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 18-11).
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
18.4.4.2
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPxADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPxADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPxBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
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already asserted the SCLx line. The SCLx output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCLx. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCLx (see
Figure 18-12).
18.4.4.5
Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCLx output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCLx output low until the SCLx output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCLx line until an external I2C master device has
FIGURE 18-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx
SCLx
DX
DX – 1
Master device
asserts clock
CKP
Master device
deasserts clock
WR
SSPxCON
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FIGURE 18-13:
I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
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FIGURE 18-14:
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
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If the general call address matches, the SSPxSR is
transferred to the SSPxBUF, the BF flag bit is set
(eighth bit) and on the falling edge of the ninth bit (ACK
bit), the SSPxIF interrupt flag bit is set.
18.4.5
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPxBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPxADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPxSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 18-15).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General Call Enable bit, GCEN, is enabled
(SSPxCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPxSR and the address is
compared against the SSPxADD. It is also compared to
the general call address and fixed in hardware.
FIGURE 18-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
ACK
R/W = 0
ACK D7 D6
General Call Address
SDAx
SCLx
D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared in software
SSPxBUF is read
SSPOV (SSPxCON1<6>)
GCEN (SSPxCON2<7>)
‘0’
‘1’
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18.4.6
MASTER MODE
Note:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register to
initiate transmission before the Start con-
dition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I2C bus may be taken when the P bit is set, or the
bus is Idle, with both the S and P bits clear.
The following events will cause the SSP Interrupt Flag
bit, SSPxIF, to be set (and SSP interrupt, if enabled):
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
• Start condition
• Stop condition
Once Master mode is enabled, the user has six
options.
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
1. Assert a Start condition on SDAx and SCLx.
2. Assert a Repeated Start condition on SDAx and
SCLx.
3. Write to the SSPxBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDAx and SCLx.
2
FIGURE 18-16:
MSSP BLOCK DIAGRAM (I C™ MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0
SSPxADD<6:0>
Read
Write
SSPxBUF
SSPxSR
Baud
Rate
Generator
SDAx
Shift
Clock
SDAx In
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCLx
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
SCLx In
Bus Collision
Set/Reset S, P, WCOL (SSPxSTAT, SSPxCON1)
Set SSPxIF, BCLxIF
Reset ACKSTAT, PEN (SSPxCON2)
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I2C Master Mode Operation
A typical transmit sequence would go as follows:
18.4.6.1
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPxCON2<0>).
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
2. SSPxIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPxBUF with the slave
address to transmit.
In Master Transmitter mode, serial data is output
through SDAx, while SCLx outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
4. Address is shifted out the SDAx pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDAx, while SCLx outputs
the serial clock. Serial data is received 8 bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
7. The user loads the SSPxBUF with eight bits of
data.
8. Data is shifted out the SDAx pin until all 8 bits
are transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCLx clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 18.4.7 “Baud Rate” for more detail.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPxCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
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Table 18-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
18.4.7
BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPxADD register (Figure 18-17). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
‘0’ and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(TCY) on the Q2 and Q4 clocks. In I2C Master mode, the
BRG is reloaded automatically.
18.4.7.1
Baud Rate and Module
Interdependence
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I2C Master mode at
different baud rates. This is done by using different
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be possi-
ble to change one or both baud rates back to a previous
value by changing the BRG reload value.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
FIGURE 18-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPxADD<6:0>
SSPM3:SSPM0
SCLx
Reload
Control
Reload
BRG Down Counter
CLKO
FOSC/4
TABLE 18-3: I2C™ CLOCK RATE w/BRG
FSCL
FCY
FCY * 2
BRG Value
(2 Rollovers of BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
18h
1Fh
63h
09h
0Ch
27h
02h
09h
00h
400 kHz(1)
312.5 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
333 kHz(1)
100 kHz
1 MHz(1)
Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
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SCLx pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPxADD<6:0> and
begins counting. This ensures that the SCLx high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 18-18).
18.4.7.2
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCLx pin is actually sampled high. When the
FIGURE 18-18:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDAx
DX
DX – 1
SCLx allowed to transition high
SCLx deasserted but slave holds
SCLx low (clock arbitration)
SCLx
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCLx is sampled high, reload takes
place and BRG starts its count
BRG
Reload
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18.4.8
I2C MASTER MODE START
CONDITION TIMING
Note:
If at the beginning of the Start condition,
the SDAx and SCLx pins are already sam-
pled low, or if during the Start condition, the
SCLx line is sampled low before the SDAx
line is driven low, a bus collision occurs.
The Bus Collision Interrupt Flag, BCLxIF,
is set, the Start condition is aborted and
the I2C module is reset into its Idle state.
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPxCON2<0>). If the SDAx and
SCLx pins are sampled high, the Baud Rate Generator
is reloaded with the contents of SSPxADD<6:0> and
starts its count. If SCLx and SDAx are both sampled
high when the Baud Rate Generator times out (TBRG),
the SDAx pin is driven low. The action of the SDAx
being driven low while SCLx is high is the Start condi-
tion and causes the S bit (SSPxSTAT<3>) to be set.
Following this, the Baud Rate Generator is reloaded
with the contents of SSPxADD<6:0> and resumes its
count. When the Baud Rate Generator times out
(TBRG), the SEN bit (SSPxCON2<0>) will be automati-
cally cleared by hardware. The Baud Rate Generator is
suspended, leaving the SDAx line held low and the
Start condition is complete.
18.4.8.1
WCOL Status Flag
If the user writes the SSPxBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPxCON2 is disabled until the Start
condition is complete.
FIGURE 18-19:
FIRST START BIT TIMING
Set S bit (SSPxSTAT<3>)
Write to SEN bit occurs here
SDAx = 1,
At completion of Start bit,
hardware clears SEN bit
and sets SSPxIF bit
SCLx = 1
TBRG
TBRG
Write to SSPxBUF occurs here
2nd bit
1st bit
SDAx
TBRG
SCLx
TBRG
S
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18.4.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
A Repeated Start condition occurs when the RSEN bit
(SSPxCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCLx pin is asserted low. When the SCLx pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPxADD<6:0> and begins counting.
The SDAx pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDAx is sampled high, the SCLx
pin will be deasserted (brought high). When SCLx is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPxADD<6:0> and begins count-
ing. SDAx and SCLx must be sampled high for one
TBRG. This action is then followed by assertion of the
SDAx pin (SDAx = 0) for one TBRG while SCLx is high.
Following this, the RSEN bit (SSPxCON2<1>) will be
automatically cleared and the Baud Rate Generator will
not be reloaded, leaving the SDAx pin held low. As
soon as a Start condition is detected on the SDAx and
SCLx pins, the S bit (SSPxSTAT<3>) will be set. The
SSPxIF bit will not be set until the Baud Rate Generator
has timed out.
2: A bus collision during the Repeated Start
condition occurs if:
• SDAx is sampled low when SCLx
goes from low-to-high.
• SCLx goes low before SDAx is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Immediately following the SSPxIF bit getting set, the
user may write the SSPxBUF with the 7-bit address in
7-bit mode or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
18.4.9.1
WCOL Status Flag
If the user writes the SSPxBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPxCON2 is disabled until the Repeated
Start condition is complete.
FIGURE 18-20:
REPEATED START CONDITION WAVEFORM
S bit set by hardware
SDAx = 1,
SCLx = 1
At completion of Start bit,
hardware clears RSEN bit
and sets SSPxIF
Write to SSPxCON2 occurs here:
SDAx = 1,
SCLx (no change)
TBRG
TBRG
TBRG
1st bit
SDAx
RSEN bit set by hardware
on falling edge of ninth clock,
end of Xmit
Write to SSPxBUF occurs here
TBRG
SCLx
TBRG
Sr = Repeated Start
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18.4.10 I2C MASTER MODE
TRANSMISSION
The user should verify that the WCOL is clear after
each write to SSPBUF to ensure the transfer is correct.
In all cases, WCOL must be cleared in software.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPxBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDAx pin after the falling edge of SCLx is
asserted (see data hold time specification
parameter 106). SCLx is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCLx is released high (see data setup time
specification parameter 107). When the SCLx pin is
released high, it is held that way for TBRG. The data on
the SDAx pin must remain stable for that duration and
some hold time after the next falling edge of SCLx.
After the eighth bit is shifted out (the falling edge of the
eighth clock), the BF flag is cleared and the master
releases SDAx. This allows the slave device being
addressed to respond with an ACK bit during the ninth
bit time if an address match occurred, or if data was
received properly. The status of ACK is written into the
ACKDT bit on the falling edge of the ninth clock. If the
master receives an Acknowledge, the Acknowledge
Status bit, ACKSTAT, is cleared; if not, the bit is set.
After the ninth clock, the SSPxIF bit is set and the
master clock (Baud Rate Generator) is suspended until
the next data byte is loaded into the SSPxBUF, leaving
SCLx low and SDAx unchanged (Figure 18-21).
18.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPxCON2<6>)
is cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
18.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPxCON2<3>).
Note:
The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCLx pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPxSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the con-
tents of the SSPxSR are loaded into the SSPxBUF, the
BF flag bit is set, the SSPxIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCLx low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable bit,
ACKEN (SSPxCON2<4>).
After the write to the SSPxBUF, each bit of the address
will be shifted out on the falling edge of SCLx until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDAx pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDAx pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit
(SSPxCON2<6>). Following the falling edge of the
ninth clock transmission of the address, the SSPxIF is
set, the BF flag is cleared and the Baud Rate Generator
is turned off until another write to the SSPxBUF takes
place, holding SCLx low and allowing SDAx to float.
18.4.11.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPxSR. It
is cleared when the SSPxBUF register is read.
18.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPxSR and the BF flag bit is
already set from a previous reception.
18.4.11.3 WCOL Status Flag
18.4.10.1 BF Status Flag
If the user writes the SSPxBUF when a receive is
already in progress (i.e., SSPxSR is still shifting in a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write doesn’t occur).
In Transmit mode, the BF bit (SSPxSTAT<0>) is set
when the CPU writes to SSPxBUF and is cleared when
all 8 bits are shifted out.
18.4.10.2 WCOL Status Flag
If the user writes to the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur) after
2 TCY after the SSPBUF write. If SSPBUF is rewritten
within 2 TCY, the WCOL bit is set and SSPBUF is
updated. This may result in a corrupted transfer.
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FIGURE 18-21:
I C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
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FIGURE 18-22:
I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
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18.4.12 ACKNOWLEDGE SEQUENCE
TIMING
18.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(TBRG) and the SCLx pin is deasserted (pulled high).
When the SCLx pin is sampled high (clock arbitration),
the Baud Rate Generator counts for TBRG. The SCLx pin
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into Idle mode
(Figure 18-23).
a
receive/transmit, the SCLx line is held low after the fall-
ing edge of the ninth clock. When the PEN bit is set, the
master will assert the SDAx line low. When the SDAx
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit
(SSPxSTAT<4>) is set. A TBRG later, the PEN bit is
cleared and the SSPxIF bit is set (Figure 18-24).
18.4.13.1 WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
18.4.12.1 WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 18-23:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPxCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
ACK
TBRG
SDAx
SCLx
D0
8
9
SSPxIF
Cleared in
software
SSPxIF set at the end
of Acknowledge sequence
SSPxIF set at
the end of receive
Cleared in
software
Note: TBRG = one Baud Rate Generator period.
FIGURE 18-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCLx = 1for TBRG, followed by SDAx = 1for TBRG
after SDAx sampled high. P bit (SSPxSTAT<4>) is set.
Write to SSPxCON2,
set PEN
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
Falling edge of
9th clock
TBRG
SCLx
SDAx
ACK
P
TBRG
TBRG
TBRG
SCLx brought high after TBRG
SDAx asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
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18.4.14 SLEEP OPERATION
18.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDAx pin, arbitration takes place when the master
outputs a ‘1’ on SDAx, by letting SDAx float high and
another master asserts a ‘0’. When the SCLx pin floats
high, data should be stable. If the expected data on
SDAx is a ‘1’ and the data sampled on the SDAx
pin = 0, then a bus collision has taken place. The
master will set the Bus Collision Interrupt Flag, BCLxIF
and reset the I2C port to its Idle state (Figure 18-25).
18.4.15 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
18.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPxSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDAx and SCLx lines are deasserted and
the SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In multi-master operation, the SDAx line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLxIF bit.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the
condition is aborted, the SDAx and SCLx lines are deas-
serted and the respective control bits in the SSPxCON2
register are cleared. When the user services the bus
collision Interrupt Service Routine and if the I2C bus is
free, the user can resume communication by asserting a
Start condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDAx and SCLx
pins. If a Stop condition occurs, the SSPxIF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPxBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 18-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDAx. While SCLx is high,
data doesn’t match what is driven
by the master.
Data changes
while SCLx = 0
SDAx line pulled low
by another source
Bus collision has occurred.
SDAx released
by master
SDAx
SCLx
Set bus collision
interrupt (BCLxIF)
BCLxIF
DS39663A-page 218
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If the SDAx pin is sampled low during this count, the
BRG is reset and the SDAx line is asserted early
(Figure 18-28). If, however, a ‘1’ is sampled on the
SDAx pin, the SDAx pin is asserted low at the end of
the BRG count. The Baud Rate Generator is then
reloaded and counts down to ‘0’. If the SCLx pin is
sampled as ‘0’ during this time, a bus collision does not
occur. At the end of the BRG count, the SCLx pin is
asserted low.
18.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDAx or SCLx are sampled low at the beginning
of the Start condition (Figure 18-26).
b) SCLx is sampled low before SDAx is asserted
low (Figure 18-27).
During a Start condition, both the SDAx and the SCLx
pins are monitored.
Note:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDAx before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDAx pin is already low, or the SCLx pin is
already low, then all of the following occur:
• the Start condition is aborted;
• the BCLxIF flag is set; and
• the MSSP module is reset to its Idle state
(Figure 18-26).
The Start condition begins with the SDAx and SCLx
pins deasserted. When the SDAx pin is sampled high,
the Baud Rate Generator is loaded from
SSPxADD<6:0> and counts down to ‘0’. If the SCLx pin
is sampled low while SDAx is high, a bus collision
occurs, because it is assumed that another master is
attempting to drive a data ‘1’ during the Start condition.
FIGURE 18-26:
BUS COLLISION DURING START CONDITION (SDAx ONLY)
SDAx goes low before the SEN bit is set.
Set BCLxIF,
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
SDAx
SCLx
SEN
Set SEN, enable Start
condition if SDAx = 1, SCLx = 1
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
BCLxIF
SSPxIF and BCLxIF are
cleared in software
S
SSPxIF
SSPxIF and BCLxIF are
cleared in software
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FIGURE 18-27:
BUS COLLISION DURING START CONDITION (SCLx = 0)
SDAx = 0, SCLx = 1
TBRG
TBRG
SDAx
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
SCLx
SEN
SCLx = 0before SDAx = 0,
bus collision occurs. Set BCLxIF.
SCLx = 0before BRG time-out,
bus collision occurs. Set BCLxIF.
BCLxIF
Interrupt cleared
in software
S
‘0’
‘0’
‘0’
‘0’
SSPxIF
FIGURE 18-28:
BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION
SDAx = 0, SCLx = 1
Set S
Set SSPxIF
Less than TBRG
TBRG
SDAx pulled low by other master.
Reset BRG and assert SDAx.
SDAx
SCLx
S
SCLx pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
‘0’
BCLxIF
S
SSPxIF
Interrupts cleared
in software
SDAx = 0, SCLx = 1,
set SSPxIF
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If SDAx is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, see
Figure 18-29). If SDAx is sampled high, the BRG is
reloaded and begins counting. If SDAx goes from
high-to-low before the BRG times out, no bus collision
occurs because no two masters can assert SDAx at
exactly the same time.
18.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDAx when SCLx
goes from low level to high level.
b) SCLx goes low before SDAx is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
If SCLx goes from high-to-low before the BRG times
out and SDAx has not already been asserted, a bus
collision occurs. In this case, another master is
attempting to transmit a data ‘1’ during the Repeated
Start condition (see Figure 18-30).
When the user deasserts SDAx and the pin is allowed
to float high, the BRG is loaded with SSPxADD<6:0>
and counts down to ‘0’. The SCLx pin is then
deasserted and when sampled high, the SDAx pin is
sampled.
If, at the end of the BRG time-out, both SCLx and SDAx
are still high, the SDAx pin is driven low and the BRG
is reloaded and begins counting. At the end of the
count, regardless of the status of the SCLx pin, the
SCLx pin is driven low and the Repeated Start
condition is complete.
FIGURE 18-29:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDAx
SCLx
Sample SDAx when SCLx goes high.
If SDAx = 0, set BCLxIF and release SDAx and SCLx.
RSEN
BCLxIF
Cleared in software
‘0’
S
‘0’
SSPxIF
FIGURE 18-30:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDAx
SCLx
SCLx goes low before SDAx,
set BCLxIF. Release SDAx and SCLx.
BCLxIF
RSEN
Interrupt cleared
in software
‘0’
S
SSPxIF
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The Stop condition begins with SDAx asserted low.
When SDAx is sampled low, the SCLx pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with
SSPxADD<6:0> and counts down to ‘0’. After the BRG
times out, SDAx is sampled. If SDAx is sampled low, a
bus collision has occurred. This is due to another
master attempting to drive a data ‘0’ (Figure 18-31). If
the SCLx pin is sampled low before SDAx is allowed to
float high, a bus collision occurs. This is another case
of another master attempting to drive a data ‘0’
(Figure 18-32).
18.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDAx pin has been deasserted and
allowed to float high, SDAx is sampled low after
the BRG has timed out.
b) After the SCLx pin is deasserted, SCLx is
sampled low before SDAx goes high.
FIGURE 18-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDAx sampled
low after TBRG,
set BCLxIF
TBRG
TBRG
TBRG
SDAx
SDAx asserted low
SCLx
PEN
BCLxIF
P
‘0’
‘0’
SSPxIF
FIGURE 18-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDAx
SCLx goes low before SDAx goes high,
set BCLxIF
Assert SDAx
SCLx
PEN
BCLxIF
P
‘0’
‘0’
SSPxIF
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TABLE 18-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
—
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
—
INT0IF
RBIF
49
51
51
51
51
51
51
51
51
51
52
52
50
53
PSPIF
PSPIE
ADIF
ADIE
RC1IF
RC1IE
RC1IP
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TMR4IF
TMR4IE
TMR4IP
TRISC3
TRISD3
TMR2IF
TMR1IF
PIE1
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
PSPIP
ADIP
PIR2
OSCFIF
OSCFIE
OSCFIP
SSP2IF
SSP2IE
SSP2IP
TRISC7
TRISD7
CMIF
TMR3IF
TMR3IE
TMR3IP
CCP4IF
CCP4IE
CCP4IP
TRISC1
TRISD1
CCP2IF
CCP2IE
CCP2IP
CCP3IF
CCP3IE
CCP3IP
TRISC0
TRISD0
PIE2
CMIE
—
—
—
IPR2
CMIP
—
—
—
PIR3
BCL2IF
BCL2IE
BCL2IP
TRISC6
TRISD6
RC2IF
RC2IE
RC2IP
TRISC5
TRISD5
TX2IF
TX2IE
TX2IP
TRISC4
TRISD4
CCP5IF
CCP5IE
CCP5IP
TRISC2
TRISD2
PIE3
IPR3
TRISC
TRISD
SSP1BUF MSSP1 Receive Buffer/Transmit Register
SSP1ADD MSSP1 Address Register (I2C™ Slave mode),
MSSP1 Baud Rate Reload Register (I2C Master mode)
SSP1CON1 WCOL
SSP1CON2 GCEN
SSPOV
ACKSTAT ACKDT
CKE D/A
SSPEN
CKP
ACKEN
P
SSPM3
RCEN
S
SSPM2
PEN
SSPM1
RSEN
UA
SSPM0
SEN
BF
50
50
50
50
53
SSP1STAT
SMP
R/W
SSP2BUF MSSP2 Receive Buffer/Transmit Register
SSP2ADD MSSP2 Address Register (I2C Slave mode),
MSSP2 Baud Rate Reload Register (I2C Master mode)
SSP2CON1 WCOL
SSP2CON2 GCEN
SSPOV
ACKSTAT ACKDT
CKE D/A
SSPEN
CKP
ACKEN
P
SSPM3
RCEN
S
SSPM2
PEN
SSPM1
RSEN
UA
SSPM0
SEN
BF
53
53
53
SSP2STAT
SMP
R/W
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.
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NOTES:
DS39663A-page 224
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The pins of EUSART1 and EUSART2 are multiplexed
with the functions of PORTC (RC6/TX1/CK1 and
RC7/RX1/DT1) and PORTG (RG1/TX2/CK2 and
RG2/RX2/DT2), respectively. In order to configure
these pins as an EUSART:
19.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
• For EUSART1:
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is one of two
serial I/O modules. (Generically, the EUSART is also
known as a Serial Communications Interface or SCI.)
The EUSART can be configured as a full-duplex
asynchronous system that can communicate with
peripheral devices, such as CRT terminals and
personal computers. It can also be configured as a
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
- bit SPEN (RCSTA1<7>) must be set (= 1)
- bit TRISC<7> must be set (= 1)
- bit TRISC<6> must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- bit TRISC<6> must be set (= 1) for
Synchronous Slave mode
• For EUSART2:
- bit SPEN (RCSTA2<7>) must be set (= 1)
- bit TRISG<2> must be set (= 1)
The Enhanced USART module implements additional
features, including automatic baud rate detection and
calibration, automatic wake-up on Sync Break recep-
tion and 12-bit Break character transmit. These make it
ideally suited for use in Local Interconnect Network bus
(LIN bus) systems.
- bit TRISG<1> must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- bit TRISC<6> must be set (= 1) for
Synchronous Slave mode
All members of the PIC18F87J10 family are equipped
with two independent EUSART modules, referred to as
EUSART1 and EUSART2. They can be configured in
the following modes:
Note:
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
The operation of each Enhanced USART module is
controlled through three registers:
• Asynchronous (full duplex) with:
- Auto-Wake-up on character reception
- Auto-Baud calibration
• Transmit Status and Control (TXSTAx)
• Receive Status and Control (RCSTAx)
• Baud Rate Control (BAUDCONx)
- 12-bit Break character transmission
• Synchronous – Master (half duplex) with
selectable clock polarity
These are detailed on the following pages in
Register 19-1, Register 19-2 and Register 19-3,
respectively.
• Synchronous – Slave (half duplex) with selectable
clock polarity
Note:
Throughout this section, references to
register and bit names that may be associ-
ated with a specific EUSART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “RCSTAx” might refer to the
Receive Status register for either
EUSART1 or EUSART2.
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REGISTER 19-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
R/W-0
R/W-0
BRGH
R-1
R/W-0
TX9D
SENDB
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note:
SREN/CREN overrides TXEN in Sync mode.
bit 4
bit 3
SYNC: EUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 19-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enables interrupt and loads the receive buffer when RSR<8>
is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-bit (RX9 = 0):
Don’t care.
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREGx register and receiving next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 19-3: BAUDCONx: BAUD RATE CONTROL REGISTER
R/W-0
ABDOVF
bit 7
R-1
U-0
—
R/W-0
SCKP
R/W-0
U-0
—
R/W-0
WUE
R/W-0
RCMT
BRG16
ABDEN
bit 0
bit 7
bit 6
ABDOVF: Auto-Baud Acquisition Rollover Status bit
1= A BRG rollover has occurred during Auto-Baud Rate Detect mode
(must be cleared in software)
0= No BRG rollover has occurred
RCMT: Receive Operation Idle Status bit
1= Receive operation is Idle
0= Receive operation is active
bit 5
bit 4
Unimplemented: Read as ‘0’
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
Unused in this mode.
Synchronous mode:
1= Idle state for clock (CKx) is a high level
0= Idle state for clock (CKx) is a low level
bit 3
BRG16: 16-bit Baud Rate Register Enable bit
1= 16-bit Baud Rate Generator – SPBRGHx and SPBRGx
0= 8-bit Baud Rate Generator – SPBRGx only (Compatible mode), SPBRGHx value ignored
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= EUSART will continue to sample the RXx pin – interrupt generated on falling edge; bit
cleared in hardware on following rising edge
0= RXx pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1= Enable baud rate measurement on the next character. Requires reception of a Sync field
(55h); cleared in hardware upon completion
0= Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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the high baud rate (BRGH = 1) or the 16-bit BRG to
reduce the baud rate error, or achieve a slow baud rate
for a fast oscillator frequency.
19.1
Baud Rate Generator (BRG)
The BRG is a dedicated 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>)
selects 16-bit mode.
Writing a new value to the SPBRGHx:SPBRGx regis-
ters causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
The SPBRGHx:SPBRGx register pair controls the period
of a free running timer. In Asynchronous mode, bits
BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) also
control the baud rate. In Synchronous mode, BRGH is
ignored. Table 19-1 shows the formula for computation of
the baud rate for different EUSART modes which only
apply in Master mode (internally generated clock).
19.1.1
OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRGx register pair.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGHx:SPBRGx registers can
be calculated using the formulas in Table 19-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 19-1. Typical baud rates
and error values for the various Asynchronous modes
are shown in Table 19-2. It may be advantageous to use
19.1.2
SAMPLING
The data on the RXx pin (either RC7/RX1/DT1 or
RG2/RX2/DT2) is sampled three times by a majority
detect circuit to determine if a high or a low level is
present at the RXx pin.
TABLE 19-1: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[64 (n + 1)]
FOSC/[16 (n + 1)]
FOSC/[4 (n + 1)]
Legend: x= Don’t care, n = value of SPBRGHx:SPBRGx register pair
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EXAMPLE 19-1:
CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate FOSC/(64 ([SPBRGHx:SPBRGx] + 1))
Solving for SPBRGHx:SPBRGx:
=
X
=
=
=
=
=
=
=
((FOSC/Desired Baud Rate)/64) – 1
((16000000/9600)/64) – 1
[25.042] = 25
16000000/(64 (25 + 1))
9615
Calculated Baud Rate
Error
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
(9615 – 9600)/9600 = 0.16%
TABLE 19-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Reset Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSTAx
RCSTAx
CSRC
SPEN
TX9
RX9
TXEN
SREN
—
SYNC
CREN
SCKP
SENDB
ADDEN
BRG16
BRGH
FERR
—
TRMT
OERR
WUE
TX9D
RX9D
51
51
52
52
52
BAUDCONx ABDOVF
RCMT
ABDEN
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
DS39663A-page 230
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
(decimal)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
255
129
31
15
4
—
—
—
129
64
15
7
—
1201
2403
9615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
—
—
1.221
1.73
0.16
1.73
1.73
8.51
-9.58
1.202
2.404
9.766
19.531
52.083
78.125
0.16
0.16
1.73
1.73
-9.58
-32.18
2.4
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.404
9.6
9.766
19.2
57.6
115.2
19.531
62.500
104.167
2
—
—
—
2
1
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.16
0.16
207
51
25
6
300
1201
2403
—
-0.16
-0.16
-0.16
—
103
25
12
—
300
1201
—
-0.16
-0.16
—
51
12
—
—
—
—
—
2.4
2.404
0.16
9.6
8.929
-6.99
8.51
—
—
19.2
57.6
115.2
20.833
62.500
62.500
2
—
—
—
—
—
8.51
0
—
—
—
—
—
-45.75
0
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
%
Error
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.4
—
—
—
—
—
—
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2403
9615
19230
55555
—
-0.16
-0.16
-0.16
3.55
—
207
51
25
8
9.6
9.766
19.231
58.140
113.636
1.73
0.16
0.94
-1.36
255
129
42
9.615
19.231
56.818
113.636
0.16
0.16
-1.36
-1.36
129
64
21
10
19.2
57.6
115.2
21
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
207
103
25
12
3
—
1201
2403
9615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
300
1201
2403
—
-0.16
-0.16
-0.16
—
207
51
25
—
1.202
0.16
0.16
0.16
0.16
8.51
8.51
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 231
PIC18F87J10 FAMILY
TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
0.02
-0.03
-0.03
0.16
4165
1041
520
129
64
0.300
1.200
0.02
-0.03
0.16
0.16
1.73
-1.36
8.51
2082
520
259
64
300
1201
2403
9615
19230
55555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
2.4
2.402
2.399
2.404
9.6
9.615
9.615
9.615
19.2
57.6
115.2
19.231
58.140
113.636
19.231
56.818
113.636
0.16
19.531
56.818
125.000
31
25
-1.36
-1.36
21
10
8
21
10
4
—
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.04
0.16
0.16
0.16
0.16
8.51
8.51
832
207
103
25
12
3
300
1201
2403
9615
—
-0.16
-0.16
-0.16
-0.16
—
415
103
51
12
—
300
1201
2403
—
-0.16
-0.16
-0.16
—
207
51
25
—
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 10.000 MHz
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG Actual
value
SPBRG
value
(decimal)
%
Error
%
%
%
Error
value
(decimal)
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
Error
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.00
0.00
0.02
0.06
-0.03
0.35
-0.22
33332
8332
4165
1040
520
0.300
1.200
0.00
0.02
0.02
-0.03
0.16
-0.22
0.94
16665
4165
2082
520
259
86
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
300
1200
-0.01
-0.04
-0.04
-0.16
-0.16
0.79
6665
1665
832
207
103
34
2.4
2.400
2.400
2.402
2400
9.6
9.606
9.596
9.615
9615
19.2
57.6
115.2
19.193
57.803
114.943
19.231
57.471
116.279
19.231
58.140
113.636
19230
57142
117647
172
86
42
21
-2.12
16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.01
0.04
0.16
0.16
0.16
2.12
-3.55
3332
832
415
103
51
300
1201
2403
9615
19230
55555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
300
1201
2403
9615
19230
—
-0.04
-0.16
-0.16
-0.16
-0.16
—
832
207
103
25
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
58.824
111.111
25
12
16
8
—
8
—
—
—
—
DS39663A-page 232
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
19.1.3
AUTO-BAUD RATE DETECT
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system tim-
ing and communication baud rates must
be taken into consideration when using the
Auto-Baud Rate Detection feature.
The automatic baud rate measurement sequence
(Figure 19-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RXx signal, the RXx signal is timing the BRG.
In ABD mode, the internal Baud Rate Generator is
used as a counter to time the bit period of the incoming
serial byte stream.
TABLE 19-4: BRG COUNTER
CLOCK RATES
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detect must receive a byte with the value 55h (ASCII
“U”, which is also the LIN bus Sync character) in order to
calculate the proper bit rate. The measurement is taken
over both a low and a high bit time in order to minimize
any effects caused by asymmetry of the incoming signal.
After a Start bit, the SPBRGx begins counting up, using
the preselected clock source on the first rising edge of
RXx. After eight bits on the RXx pin or the fifth rising
edge, an accumulated value totalling the proper BRG
period is left in the SPBRGHx:SPBRGx register pair.
Once the 5th edge is seen (this should correspond to the
Stop bit), the ABDEN bit is automatically cleared.
BRG16 BRGH
BRG Counter Clock
0
0
1
1
0
1
0
1
FOSC/512
FOSC/128
FOSC/128
FOSC/32
Note: During the ABD sequence, SPBRGx and
SPBRGHx are both used as a 16-bit counter,
independent of BRG16 setting.
19.1.3.1
ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisi-
tion, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREGx cannot be written to. Users should also
ensure that ABDEN does not become set during a
transmit sequence. Failing to do this may result in
unpredictable EUSART operation.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCONx<7>). It is set in hardware by BRG roll-
overs and can be set or cleared by the user in software.
ABD mode remains active after rollover events and the
ABDEN bit remains set (Figure 19-2).
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRGx and SPBRGHx will be used
as a 16-bit counter. This allows the user to verify that
no carry occurred for 8-bit modes by checking for 00h
in the SPBRGHx register. Refer to Table 19-4 for
counter clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCxIF interrupt is set
once the fifth rising edge on RXx is detected. The value
in the RCREGx needs to be read to clear the RCxIF
interrupt. The contents of RCREGx should be
discarded.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 233
PIC18F87J10 FAMILY
FIGURE 19-1:
AUTOMATIC BAUD RATE CALCULATION
BRG Value
RXx pin
XXXXh
0000h
001Ch
Edge #5
Stop Bit
Edge #2
Bit 3
Edge #3
Bit 5
Edge #4
Bit 7
Bit 6
Edge #1
Bit 1
Start
Bit 0
Bit 2
Bit 4
BRG Clock
Auto-Cleared
Set by User
ABDEN bit
RCxIF bit
(Interrupt)
Read
RCREGx
XXXXh
XXXXh
1Ch
00h
SPBRGx
SPBRGHx
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 19-2:
BRG OVERFLOW SEQUENCE
BRG Clock
ABDEN bit
RXx pin
Start
Bit 0
ABDOVF bit
BRG Value
FFFFh
XXXXh
0000h
0000h
DS39663A-page 234
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
Once the TXREGx register transfers the data to the TSR
register (occurs in one TCY), the TXREGx register is
empty and the TX1IF flag bit (PIR1<4>) is set. This inter-
rupt can be enabled or disabled by setting or clearing the
interrupt enable bit, TX1IE (PIE1<4>). TX1IF will be set
regardless of the state of TX1IE; it cannot be cleared in
software. TX1IF is also not cleared immediately upon
loading TXREGx, but becomes valid in the second
instruction cycle following the load instruction. Polling
TX1IF immediately following a load of TXREGx will return
invalid results.
19.2 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTAx<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit Baud Rate Generator can be used
to derive standard baud rate frequencies from the
oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate, depending on the BRGH
and BRG16 bits (TXSTAx<2> and BAUDCONx<3>).
Parity is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
While TX1IF indicates the status of the TXREGx regis-
ter, another bit, TRMT (TXSTAx<1>), shows the status
of the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
• Baud Rate Generator
2: Flag bit TX1IF is set when enable bit
• Sampling Circuit
TXEN is set.
• Asynchronous Transmitter
• Asynchronous Receiver
To set up an Asynchronous Transmission:
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
• Auto-Wake-up on Sync Break Character
• 12-bit Break Character Transmit
• Auto-Baud Rate Detection
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
19.2.1
EUSART ASYNCHRONOUS
TRANSMITTER
3. If interrupts are desired, set enable bit TXxIE.
The EUSART transmitter block diagram is shown in
Figure 19-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREGx register (if available).
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN
which will also set bit TXxIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREGx register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-3:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXxIF
TXREGx Register
TXxIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
•
•
•
TSR Register
TXx pin
Interrupt
Baud Rate CLK
TXEN
TRMT
SPEN
BRG16
SPBRGHx SPBRGx
Baud Rate Generator
TX9
TX9D
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 235
PIC18F87J10 FAMILY
FIGURE 19-4:
ASYNCHRONOUS TRANSMISSION
Write to TXREGx
Word 1
BRG Output
(Shift Clock)
TXx (pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 19-5:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREGx
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TXx (pin)
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
1 TCY
Word 1
TXxIF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 19-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
49
51
51
51
51
51
51
51
51
51
52
52
52
PSPIF
PSPIE
PSPIP
SSP2IF
SSP2IE
SSP2IP
SPEN
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SSP1IF
SSP1IE
SSP1IP
TMR4IF
TMR2IF
TMR1IF
PIE1
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
RX9
CCP5IF
CCP4IF
CCP4IE
CCP4IP
OERR
CCP3IF
CCP3IE
CCP3IP
RX9D
PIE3
TMR4IE CCP5IE
TMR4IP CCP5IP
IPR3
RCSTAx
TXREGx
TXSTAx
ADDEN
FERR
EUSARTx Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCONx ABDOVF
RCMT
ABDEN
SPBRGHx
SPBRGx
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
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PIC18F87J10 FAMILY
19.2.2
EUSART ASYNCHRONOUS
RECEIVER
19.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 19-6.
The data is received on the RXx pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
To set up an Asynchronous Reception:
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCxIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCxIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
7. The RCxIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCxIE and GIE bits are set.
6. Flag bit, RCxIF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RCxIE, was set.
8. Read the RCSTAx register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREGx to determine if the device is
being addressed.
10. If any error occurred, clear the CREN bit.
8. Read the 8-bit received data by reading the
RCREGx register.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-6:
EUSART RECEIVE BLOCK DIAGRAM
CREN
OERR
FERR
x64 Baud Rate CLK
÷ 64
RSR Register
• • •
MSb
Stop
LSb
Start
BRG16
SPBRGHx SPBRGx
or
÷ 16
(8)
7
1
0
or
Baud Rate Generator
÷ 4
RX9
Pin Buffer
and Control
Data
Recovery
RXx
RX9D
RCREGx Register
FIFO
SPEN
8
Interrupt
RCxIF
RCxIE
Data Bus
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PIC18F87J10 FAMILY
FIGURE 19-7:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RXx (pin)
Stop
bit
Stop
bit
Stop
bit
bit 0 bit 1
bit 7/8
bit 0
bit 7/8
bit 7/8
Rcv Shift Reg
Rcv Buffer Reg
Word 2
RCREGx
Word 1
RCREGx
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 19-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
INT0IF
RBIF
49
51
51
51
51
51
51
51
51
51
52
52
52
PSPIF
PSPIE
PSPIP
SSP2IF
SSP2IE
SSP2IP
SPEN
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SSP1IF
SSP1IE
SSP1IP
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
RX9
TMR4IF CCP5IF
CCP4IF CCP3IF
PIE3
TMR4IE CCP5IE CCP4IE CCP3IE
TMR4IP CCP5IP CCP4IP CCP3IP
IPR3
RCSTAx
RCREGx
TXSTAx
ADDEN
FERR
OERR
RX9D
EUSARTx Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCONx ABDOVF
RCMT
ABDEN
SPBRGHx
SPBRGx
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
the RXx/DTx line. (This coincides with the start of a
Sync Break or a Wake-up Signal character for the LIN
protocol.)
19.2.4
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RXx/DTx line while the
EUSART is operating in Asynchronous mode.
Following a wake-up event, the module generates an
RCxIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 19-8) and asynchronously if the device is in
Sleep mode (Figure 19-9). The interrupt condition is
cleared by reading the RCREGx register.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RXx/DTx is disabled and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on
The WUE bit is automatically cleared once
a
low-to-high transition is observed on the RXx line
following the wake-up event. At this point, the EUSART
module is in Idle mode and returns to normal operation.
This signals to the user that the Sync Break event is
over.
DS39663A-page 238
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19.2.4.1
Special Considerations Using
Auto-Wake-up
19.2.4.2
Special Considerations Using
the WUE Bit
Since auto-wake-up functions by sensing rising edge
transitions on RXx/DTx, information with any state
changes before the Stop bit may signal a false
end-of-character and cause data or framing errors. To
work properly, therefore, the initial character in the
transmission must be all ‘0’s. This can be 00h (8 bytes)
for standard RS-232 devices or 000h (12 bits) for LIN
bus.
The timing of WUE and RCxIF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes a
receive interrupt by setting the RCxIF bit. The WUE bit
is cleared after this when a rising edge is seen on
RXx/DTx. The interrupt condition is then cleared by
reading the RCREGx register. Ordinarily, the data in
RCREGx will be dummy data and should be discarded.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., HS or HSPLL mode). The Sync
Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient interval
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
The fact that the WUE bit has been cleared (or is still
set) and the RCxIF flag is set should not be used as an
indicator of the integrity of the data in RCREGx. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCMT
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
FIGURE 19-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit set by user
Auto-Cleared
OSC1
WUE bit(1)
RXx/DTx Line
RCxIF
Cleared due to user read of RCREGx
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 19-9:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Auto-Cleared
OSC1
WUE bit(2)
RXx/DTx Line
RCxIF
Bit set by user
Note 1
Cleared due to user read of RCREGx
Sleep Ends
SLEEPCommand Executed
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This
sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
2005 Microchip Technology Inc.
Advance Information
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PIC18F87J10 FAMILY
1. Configure the EUSART for the desired mode.
19.2.5
BREAK CHARACTER SEQUENCE
2. Set the TXEN and SENDB bits to set up the
Break character.
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. The Break character transmit
consists of a Start bit, followed by twelve ‘0’ bits and a
Stop bit. The Frame Break character is sent whenever
the SENDB and TXEN bits (TXSTAx<3> and
TXSTAx<5>) are set while the Transmit Shift Register
is loaded with data. Note that the value of data written
to TXREGx will be ignored and all ‘0’s will be
transmitted.
3. Load the TXREGx with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREGx to load the Sync
character into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
When the TXREGx becomes empty, as indicated by
the TXxIF, the next data byte can be written to
TXREGx.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
19.2.6
RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
Note that the data value written to the TXREGx for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typical data).
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 19-10 for the timing of the Break
character sequence.
The second method uses the auto-wake-up feature
described in Section 19.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on
RXx/DTx, cause an RCxIF interrupt and receive the
next data byte followed by another interrupt.
19.2.5.1
Break and Sync Transmit Sequence
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN bus
master.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABDEN
bit once the TXxIF interrupt is observed.
FIGURE 19-10:
SEND BREAK CHARACTER SEQUENCE
Write to TXREGx
Dummy Write
BRG Output
(Shift Clock)
TXx (pin)
Start Bit
Bit 0
Bit 1
Break
Bit 11
Stop Bit
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here
Auto-Cleared
SENDB bit
(Transmit Shift
Reg. Empty Flag)
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Once the TXREGx register transfers the data to the
TSR register (occurs in one TCY), the TXREGx is empty
and the TX1IF flag bit (PIR1<4>) is set. The interrupt
can be enabled or disabled by setting or clearing the
interrupt enable bit, TX1IE (PIE1<4>). TX1IF is set
regardless of the state of enable bit TX1IE; it cannot be
cleared in software. It will reset only when new data is
loaded into the TXREGx register.
19.3 EUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTAx<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit
SYNC (TXSTAx<4>). In addition, enable bit SPEN
(RCSTAx<7>) is set in order to configure the TXx and
RXx pins to CKx (clock) and DTx (data) lines,
respectively.
While flag bit TX1IF indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit, so the user must poll this bit in order to determine
if the TSR register is empty. The TSR is not mapped in
data memory so it is not available to the user.
The Master mode indicates that the processor trans-
mits the master clock on the CKx line. Clock polarity is
selected with the SCKP bit (BAUDCONx<4>); setting
SCKP sets the Idle state on CKx as high, while clearing
the bit sets the Idle state as low. This option is provided
to support Microwire devices with this module.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGHx:SPBRGx registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
19.3.1
EUSART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXxIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
The EUSART transmitter block diagram is shown in
Figure 19-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREGx (if available).
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREGx register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-11:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
RC6/TX1/CK1 pin
(SCKP = 0)
RC6/TX1/CK1 pin
(SCKP = 1)
Write to
TXREG1 Reg
Write Word 1
Write Word 2
TX1IF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. This example is equally applicable to EUSART2
(RG1/TX2/CK2 and RG2/RX2/DT2).
2005 Microchip Technology Inc.
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PIC18F87J10 FAMILY
FIGURE 19-12:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX1/DT1 pin
bit 0
bit 2
bit 1
bit 6
bit 7
RC6/TX1/CK1 pin
Write to
TXREG1 reg
TX1IF bit
TRMT bit
TXEN bit
Note: This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2).
TABLE 19-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
INT0IF
RBIF
49
51
51
51
51
51
51
51
51
51
52
52
52
PSPIF
PSPIE
PSPIP
SSP2IF
SSP2IE
SSP2IP
SPEN
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SSP1IF
SSP1IE
SSP1IP
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
RX9
TMR4IF CCP5IF
CCP4IF
CCP3IF
PIE3
TMR4IE CCP5IE CCP4IE CCP3IE
TMR4IP CCP5IP CCP4IP CCP3IP
IPR3
RCSTAx
TXREGx
TXSTAx
ADDEN
FERR
OERR
RX9D
EUSARTx Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCONx ABDOVF
RCMT
ABDEN
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
DS39663A-page 242
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4. If interrupts are desired, set enable bit RCxIE.
5. If 9-bit reception is desired, set bit RX9.
19.3.2
EUSART SYNCHRONOUS
MASTER RECEPTION
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTAx<5>) or the Continuous Receive
Enable bit, CREN (RCSTAx<4>). Data is sampled on
the RXx pin on the falling edge of the clock.
7. Interrupt flag bit, RCxIF, will be set when recep-
tion is complete and an interrupt will be generated
if the enable bit, RCxIE, was set.
8. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
9. Read the 8-bit received data by reading the
RCREGx register.
To set up a Synchronous Master Reception:
10. If any error occurred, clear the error by clearing
bit CREN.
1. Initialize the SPBRGHx:SPBRGx registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
FIGURE 19-13:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX1/CK1 pin
(SCKP = 0)
RC6/TX1/CK1 pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RC1IF bit
(Interrupt)
Read
RCREG1
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0. This example is equally applicable to EUSART2
(RG1/TX2/CK2 and RG2/RX2/DT2).
2005 Microchip Technology Inc.
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TABLE 19-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
CCP5IF
CCP5IE
CCP5IP
FERR
INT0IF
RBIF
49
51
51
51
51
51
51
51
51
51
52
52
52
PSPIF
PSPIE
PSPIP
SSP2IF
SSP2IE
SSP2IP
SPEN
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SSP1IF
SSP1IE
SSP1IP
TMR4IF
TMR4IE
TMR4IP
ADDEN
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
RX9
CCP4IF
CCP3IF
PIE3
CCP4IE CCP3IE
CCP4IP CCP3IP
IPR3
RCSTAx
RCREGx
TXSTAx
OERR
RX9D
EUSARTx Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCONx ABDOVF
RCMT
ABDEN
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
To set up a Synchronous Slave Transmission:
19.4 EUSART Synchronous
Slave Mode
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXxIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
19.4.1
EUSART SYNCHRONOUS
SLAVE TRANSMISSION
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
7. Start transmission by loading data to the
TXREGx register.
If two words are written to the TXREGx and then the
SLEEPinstruction is executed, the following will occur:
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREGx
register.
c) Flag bit, TXxIF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREGx register will transfer the second
word to the TSR and flag bit, TXxIF, will now be
set.
e) If enable bit TXxIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
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TABLE 19-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
49
51
51
51
51
51
51
51
51
51
52
52
52
PSPIF
PSPIE
PSPIP
SSP2IF
SSP2IE
SSP2IP
SPEN
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SSP1IF
SSP1IE
SSP1IP
TMR4IF
TMR2IF TMR1IF
PIE1
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
RX9
CCP5IF
CCP4IF
CCP3IF
PIE3
TMR4IE CCP5IE
TMR4IP CCP5IP
CCP4IE CCP3IE
CCP4IP CCP3IP
IPR3
RCSTAx
TXREGx
TXSTAx
ADDEN
FERR
OERR
RX9D
EUSARTx Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCONx ABDOVF
RCMT
ABDEN
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
To set up a Synchronous Slave Reception:
19.4.2
EUSART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
2. If interrupts are desired, set enable bit RCxIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREGx register; if the RCxIE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
5. Flag bit, RCxIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCxIE, was set.
6. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREGx register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
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TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
49
51
51
51
51
51
51
51
51
51
52
52
52
PSPIF
PSPIE
PSPIP
SSP2IF
SSP2IE
SSP2IP
SPEN
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SSP1IF
SSP1IE
SSP1IP
TMR4IF
TMR2IF TMR1IF
PIE1
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
RX9
CCP5IF
CCP4IF
CCP3IF
CCP3IE
CCP3IP
RX9D
PIE3
TMR4IE CCP5IE CCP4IE
TMR4IP CCP5IP CCP4IP
IPR3
RCSTAx
RCREGx
TXSTAx
ADDEN
FERR
OERR
EUSARTx Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCONx ABDOVF
RCMT
ABDEN
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
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The module has five registers:
20.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
The analog-to-digital (A/D) converter module has
11 inputs for the 64-pin devices and 15 for the 80-pin
devices. This module allows conversion of an analog
input signal to a corresponding 10-bit digital number.
The ADCON0 register, shown in Register 20-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 20-2, configures
the functions of the port pins. The ADCON2 register,
shown in Register 20-3, configures the A/D clock
source, programmed acquisition time and justification.
REGISTER 20-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
ADCAL
GO/DONE
bit 7
bit 0
bit 7-6
ADCAL: A/D Calibration bit
1= Calibration is performed on next A/D conversion
0= Normal A/D converter operation (no conversion is performed)
bit 6
Unimplemented: Read as ‘0’
bit 5-2
CHS3:CHS0: Analog Channel Select bits
0000= Channel 00 (AN0)
0001= Channel 01 (AN1)
0010= Channel 02 (AN2)
0011= Channel 03 (AN3)
0100= Channel 04 (AN4)
0101= Unused
0110= Channel 06 (AN6)
0111= Channel 07 (AN7)
1000= Channel 08 (AN8)
1001= Channel 09 (AN9)
1010= Channel 10 (AN10)
1011= Channel 11 (AN11)
1100= Channel 12 (AN12)(1,2)
1101= Channel 13 (AN13)(1,2)
1110= Channel 14 (AN14)(1,2)
1111= Channel 15 (AN15)(1,2)
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress
0= A/D Idle
ADON: A/D On bit
1= A/D converter module is enabled
0= A/D converter module is disabled
Note 1: These channels are not implemented on 64-pin devices.
2: Performing a conversion on unimplemented channels will return random values.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
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REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as ‘0’
VCFG1: Voltage Reference Configuration bit (VREF- source)
1= VREF- (AN2)
0= AVSS
bit 4
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1= VREF+ (AN3)
0= AVDD
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG3:
PCFG0
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A = Analog input
D = Digital I/O
Note 1: AN12 through AN15 are available only in 80-pin devices.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
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REGISTER 20-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111= 20 TAD
110= 16 TAD
101= 12 TAD
100= 8 TAD
011= 6 TAD
010= 4 TAD
001= 2 TAD
(1)
000= 0 TAD
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111= FRC (clock derived from A/D RC oscillator)(1)
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= FRC (clock derived from A/D RC oscillator)(1)
010= FOSC/32
001= FOSC/8
000= FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is
added before the A/D clock starts. This allows the SLEEPinstruction to be executed
before starting a conversion.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
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The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS), or the voltage level on the
RA3/AN3/VREF+ and RA2/AN2/VREF- pins.
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is
cleared and A/D Interrupt Flag bit ADIF is set.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset. These registers will contain unknown
data after a Power-on Reset.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
The block diagram of the A/D module is shown in
Figure 20-1.
Each port pin associated with the A/D converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
FIGURE 20-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1111
AN15(1)
1110
AN14(1)
1101
AN13(1)
1100
AN12(1)
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0100
AN4
VAIN
0011
(Input Voltage)
10-bit
Converter
A/D
AN3
0010
AN2
0001
VCFG1:VCFG0
AN1
0000
AN0
VDD
VREF+
VREF-
Reference
Voltage
VSS
Note 1: Channels AN15 through AN12 are not available on 64-pin devices.
2: I/O pins have diode protection to VDD and VSS.
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After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 20.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0<1>)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
The following steps should be followed to do an A/D
conversion:
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
FIGURE 20-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
RS
CPIN
VAIN
ILEAKAGE
±100 nA
CHOLD = 25 pF
VT = 0.6V
5 pF
VSS
Legend: CPIN
VT
= input capacitance
= threshold voltage
6V
5V
VDD 4V
3V
ILEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
= sampling switch
2V
SS
CHOLD
RSS
= sample/hold capacitance (from DAC)
= sampling switch resistance
1
2
3
4
Sampling Switch (kΩ)
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To calculate the minimum acquisition time,
Equation 20-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
20.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 20-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
Equation 20-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
5V → Rss = 2 kΩ
85°C (system max.)
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 20-1: ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 20-2: A/D MINIMUM CHARGING TIME
VHOLD
or
TC
=
=
(VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))
)
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 20-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
TAMP
TCOFF
=
=
=
TAMP + TC + TCOFF
0.2 µs
(Temp – 25°C)(0.02 µs/°C)
(85°C – 25°C)(0.02 µs/°C)
1.2 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2047) µs
-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) µs
1.05 µs
TACQ
=
0.2 µs + 1 µs + 1.2 µs
2.4 µs
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TABLE 20-1: TAD vs. DEVICE OPERATING
FREQUENCIES
20.2 Selecting and Configuring
Automatic Acquisition Time
AD Clock Source (TAD)
Maximum
Device
Frequency
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
Operation
ADCS2:ADCS0
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC(3)
000
100
001
101
010
110
x11
1.25 MHz
2.50 MHz
5.00 MHz
10.0 MHz
20.0 MHz
40.0 MHz
1.00 MHz(1)
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT2:ACQT0
bits (ADCON2<5:3>) remain in their Reset state (‘000’)
and is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQT bits can be set to select a pro-
grammable acquisition time for the A/D module. When
the GO/DONE bit is set, the A/D module continues to
sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisi-
tion time is programmed, there may be no need to wait
for an acquisition time between selecting a channel and
setting the GO/DONE bit.
Note 1: The RC source has a typical TAD time of
4 ms.
2: The RC source has a typical TAD time of
6 ms.
3: For device frequencies above 1 MHz, the
device must be in Sleep mode for the entire
conversion or the A/D accuracy may be out
of specification.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
20.4 Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
20.3 Selecting the A/D Conversion
Clock
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
There are seven possible options for TAD:
• 2 TOSC
• 4 TOSC
• 8 TOSC
• 16 TOSC
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible but greater than the
minimum TAD (approximately 2 µs, see parameter 130
for more information).
Table 20-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
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20.5 A/D Conversions
20.6 Use of the ECCP2 Trigger
Figure 20-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
An A/D conversion can be started by the “Special Event
Trigger” of the ECCP2 module. This requires that the
CCP2M3:CCP2M0
bits
(CCP2CON<3:0>)
be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to auto-
matically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time is selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
Figure 20-4 shows the operation of the A/D converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 TAD acquisition time before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
conversion
sample.
This
means
the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module but will still reset the Timer1 (or Timer3)
counter.
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 20-3:
A/D CONVERSION TAD CYCLES (ACQT2:ACQT0 = 000, TACQ = 0)
TCY - TAD
TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7
b4
b1
b0
b9
b8
b7
b6
b5
b3
b2
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 20-4:
A/D CONVERSION TAD CYCLES (ACQT2:ACQT0 = 010, TACQ = 4 TAD)
TAD Cycles
TACQT Cycles
7
8
9
10
b1
11
b0
1
2
3
4
1
2
3
4
5
6
b7
b6
b3
b2
b8
b5
b4
b9
Automatic
Acquisition
Time
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
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If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
20.7 A/D Converter Calibration
The A/D converter in the PIC18F87J10 family of
devices includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON0<7>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for offset. Thus, subsequent offsets will
be compensated.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in the Sleep mode requires the A/D RC clock
to be selected. If bits ACQT2:ACQT0 are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEPinstruction and entry to Sleep mode. The IDLEN
and SCS bits in the OSCCON register must have
already been cleared prior to starting the conversion.
20.8 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
TABLE 20-2: SUMMARY OF A/D REGISTERS
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
—
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
—
INT0IF
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
RBIF
49
51
51
51
51
51
51
50
50
50
50
50
51
52
52
52
52
52
52
PSPIF
PSPIE
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
RC1IF
RC1IE
RC1IP
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
PIE1
IPR1
PSPIP
PIR2
OSCFIF
OSCFIE
OSCFIP
PIE2
—
—
—
IPR2
—
—
—
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCP2CON
PORTA
TRISA
A/D Result Register High Byte
A/D Result Register Low Byte
ADCAL
—
—
—
CHS3
VCFG1
ACQT2
DC2B1
RA5
CHS3
VCFG0
ACQT1
CHS1
PCFG3
ACQT0
CHS0 GO/DONE ADON
PCFG2
ADCS2
PCFG1
ADCS1
PCFG0
ADCS0
ADFM
P2M1
—
—
P2M0
—
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
RA4
TRISA4
RF4
RA3
TRISA3
RF3
RA2
TRISA2
RF2
RA1
TRISA1
RF1
RA0
TRISA0
—
—
—
TRISA5
RF5
PORTF
TRISF
PORTH(1)
TRISH(1)
RF7
RF6
TRISF4
RH6
TRISH6
TRISF5
RH7
TRISF5
RH5
TRISF4
RH4
TRISF3
RH3
TRISF2
RH2
TRISF1
RH1
—
RH0
TRISH7
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: This register is not implemented on 64-pin devices.
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NOTES:
DS39663A-page 256
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The CMCON register (Register 21-1) selects the
comparator input and output configuration. Block
diagrams of the various comparator configurations are
shown in Figure 21-1.
21.0 COMPARATOR MODULE
The analog comparator module contains two
comparators that can be configured in a variety of
ways. The inputs can be selected from the analog
inputs multiplexed with pins RF1 through RF6, as well
as the on-chip voltage reference (see Section 22.0
“Comparator Voltage Reference Module”). The digi-
tal outputs (normal or inverted) are available at the pin
level and can also be read through the control register.
REGISTER 21-1: CMCON: COMPARATOR MODULE CONTROL REGISTER
R-0
R-0
R/W-0
C2INV
R/W-0
C1INV
R/W-0
CIS
R/W-1
CM2
R/W-1
CM1
R/W-1
CM0
C2OUT
C1OUT
bit 7
bit 0
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
When C2INV = 1:
1= C2 VIN+ < C2 VIN-
0= C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1= C1 VIN+ > C1 VIN-
0= C1 VIN+ < C1 VIN-
When C1INV = 1:
1= C1 VIN+ < C1 VIN-
0= C1 VIN+ > C1 VIN-
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion bit
1= C2 output inverted
0= C2 output not inverted
C1INV: Comparator 1 Output Inversion bit
1= C1 output inverted
0= C1 output not inverted
CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1= C1 VIN- connects to RF5/AN10/CVREF
C2 VIN- connects to RF3/AN8
0= C1 VIN- connects to RF6/AN11
C2 VIN- connects to RF4/AN9
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 21-1 shows the Comparator modes and the CM2:CM0 bit settings.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Section 26.0 “Electrical Characteristics”.
21.1 Comparator Configuration
There are eight modes of operation for the compara-
tors, shown in Figure 21-1. Bits CM2:CM0 of the
CMCON register are used to select these modes. The
TRISF register controls the data direction of the
comparator pins for each mode. If the Comparator
Note:
Comparator interrupts should be disabled
during Comparator mode change;
otherwise, a false interrupt may occur.
a
FIGURE 21-1:
COMPARATOR I/O OPERATING MODES
Comparator Outputs Disabled
Comparators Off (POR Default Value)
CM2:CM0 = 000
CM2:CM0 = 111
A
D
VIN-
VIN-
RF6/AN11
RF6/AN11
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
C1
C2
C1
C2
VIN+
VIN+
A
D
RF5/AN10/
CVREF
RF5/AN10/
CVREF
A
A
D
VIN-
VIN-
RF4/AN9
RF3/AN8
RF4/AN9
VIN+
VIN+
D
RF3/AN8
Two Independent Comparators
Two Independent Comparators with Outputs
CM2:CM0 = 010
CM2:CM0 = 011
A
A
VIN-
VIN-
RF6/AN11
RF6/AN11
C1OUT
C2OUT
C1OUT
C2OUT
C1
C2
C1
C2
VIN+
VIN+
A
A
RF5/AN10/
CVREF
RF5/AN10/
CVREF
RF2/AN7/C1OUT*
A
A
VIN-
RF4/AN9
RF3/AN8
A
VIN-
RF4/AN9
VIN+
VIN+
A
RF3/AN8
RF1/AN6/C2OUT*
Two Common Reference Comparators
Two Common Reference Comparators with Outputs
CM2:CM0 = 100
CM2:CM0 = 101
A
A
VIN-
VIN-
RF6/AN11
RF6/AN11
C1OUT
C2OUT
C1OUT
C1
C2
C1
C2
VIN+
VIN+
A
A
RF5/AN10/
CVREF
RF5/AN10/
CVREF
RF2/AN7/C1OUT*
A
D
VIN-
RF4/AN9
RF3/AN8
RF4/AN9
RF3/AN8
A
D
VIN-
VIN+
C2OUT
VIN+
RF1/AN6/C2OUT*
Four Inputs Multiplexed to Two Comparators
One Independent Comparator with Output
CM2:CM0 = 110
CM2:CM0 = 001
A
RF6/AN11
A
A
VIN-
RF6/AN11
CIS = 0
CIS = 1
VIN-
A
C1OUT
RF5/AN10/
CVREF
C1
VIN+
C1OUT
C2OUT
RF5/AN10/
CVREF
C1
C2
VIN+
A
A
RF2/AN7/C1OUT*
RF4/AN9
RF3/AN8
VIN-
CIS = 0
CIS = 1
VIN+
D
VIN-
RF4/AN9
Off (Read as ‘0’)
C2
VIN+
D
RF3/AN8
CVREF
From VREF module
A = Analog Input, port reads zeros always
D = Digital Input
CIS (CMCON<3>) is the Comparator Input Switch
* Setting the TRISF<2:1> bits will disable the comparator outputs by configuring the pins as inputs.
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21.3.2
INTERNAL REFERENCE SIGNAL
21.2 Comparator Operation
The comparator module also allows the selection of an
internally generated voltage reference from the
comparator voltage reference module. This module is
described in more detail in Section 22.0 “Comparator
Voltage Reference Module”.
A single comparator is shown in Figure 21-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 21-2 represent
the uncertainty due to input offsets and response time.
The internal reference is only available in the mode
where four inputs are multiplexed to two comparators
(CM2:CM0 = 110). In this mode, the internal voltage
reference is applied to the VIN+ pin of both
comparators.
21.3 Comparator Reference
21.4 Comparator Response Time
Depending on the comparator operating mode, either
an external or internal voltage reference may be used.
The analog signal present at VIN- is compared to the
signal at VIN+ and the digital output of the comparator
is adjusted accordingly (Figure 21-2).
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (see Section 26.0
“Electrical Characteristics”).
FIGURE 21-2:
SINGLE COMPARATOR
VIN+
VIN-
+
21.5 Comparator Outputs
Output
–
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RF1 and RF2
I/O pins. When enabled, multiplexors in the output path
of the RF1 and RF2 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 21-3 shows the comparator output block
diagram.
VIN-
VIN+
Output
The TRISF bits will still function as an output enable/
disable for the RF1 and RF2 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<5:4>).
21.3.1
EXTERNAL REFERENCE SIGNAL
Note 1: When reading the port register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
2: Analog levels on any pin defined as a
digital input may cause the input buffer to
consume more current than is specified.
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FIGURE 21-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port pins
To RF1 or
RF2 pin
D
Q
Bus
Data
CxINV
EN
Read CMCON
D
Q
Set
CMIF
bit
EN
CL
From
other
Comparator
Reset
21.6 Comparator Interrupts
21.7 Comparator Operation
During Sleep
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR2<6>) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional, if enabled. This interrupt will
wake-up the device from Sleep mode, when enabled.
Each operational comparator will consume additional
current, as shown in the comparator specifications. To
minimize power consumption while in Sleep mode, turn
off the comparators (CM2:CM0 = 111) before entering
Sleep. If the device wakes up from Sleep, the contents
of the CMCON register are not affected.
Both the CMIE bit (PIE2<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit (INTCON<7>) must also be set. If
any of these bits are clear, the interrupt is not enabled,
though the CMIF bit will still be set if an interrupt
condition occurs.
21.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator modules to be turned off
(CM2:CM0 = 111). However, the input pins (RF3
through RF6) are configured as analog inputs by
default on device Reset. The I/O configuration for these
pins is determined by the setting of the PCFG3:PCFG0
bits (ADCON1<3:0>). Therefore, device current is
minimized when analog inputs are present at Reset
time.
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2
register) interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
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range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
21.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 21-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
FIGURE 21-4:
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RIC
RS < 10k
AIN
Comparator
Input
ILEAKAGE
±500 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend: CPIN
=
=
Input Capacitance
Threshold Voltage
VT
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
=
=
=
Interconnect Resistance
Source Impedance
Analog Voltage
TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
PIR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
—
RBIE
BCL1IF
BCL1IE
BCL1IP
CIS
TMR0IF
—
INT0IF
RBIF
49
51
51
51
51
51
52
52
52
OSCFIF
OSCFIE
OSCFIP
C2OUT
CVREN
RF7
CMIF
CMIE
—
—
TMR3IF CCP2IF
TMR3IE CCP2IE
TMR3IP CCP2IP
PIE2
—
—
IPR2
CMIP
—
—
—
CMCON
CVRCON
PORTF
LATF
C1OUT
CVROE
RF6
C2INV
CVRR
RF5
C1INV
CVRSS
RF4
CM2
CVR2
RF2
CM1
CVR1
RF1
CM0
CVR0
—
CVR3
RF3
LATF7
LATF6
TRISF6
LATF5
TRISF5
LATF4
TRISF4
LATF3
TRISF3
LATF2
TRISF2
LATF1
TRISF1
—
TRISF
TRISF7
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
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is selected by the CVRR bit (CVRCON<5>). The
primary difference between the ranges is the size of the
steps selected by the CVREF Selection bits
(CVR3:CVR0), with one range offering finer resolution.
The equations used to calculate the output of the
comparator voltage reference are as follows:
22.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable reference
voltage. Although its primary purpose is to provide a
reference for the analog comparators, it may also be
used independently of them.
If CVRR = 1:
CVREF = ((CVR3:CVR0)/24) x (CVRSRC)
A block diagram of the module is shown in Figure 22-1.
The resistor ladder is segmented to provide two ranges
of CVREF values and has a power-down function to
conserve power when the reference is not being used.
The module’s supply reference can be provided from
either device VDD/VSS or an external voltage reference.
If CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) x
(CVRSRC)
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
(CVRCON<4>).
22.1 Configuring the Comparator
Voltage Reference
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output (see Table 26-3 in Section 26.0 “Electrical
Characteristics”).
The voltage reference module is controlled through the
CVRCON register (Register 22-1). The comparator
voltage reference provides two ranges of output volt-
age, each with 16 distinct levels. The range to be used
REGISTER 22-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
CVREN CVROE(1)
bit 7
R/W-0
R/W-0
CVRR
R/W-0
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVRSS
bit 0
bit 7
bit 6
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down
CVROE: Comparator VREF Output Enable bit(1)
1= CVREF voltage level is also output on the RF5/AN10/CVREF pin
0= CVREF voltage is disconnected from the RF5/AN10/CVREF pin
Note 1: CVROE overrides the TRISF<5> bit setting.
bit 5
CVRR: Comparator VREF Range Selection bit
1= 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0= 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
bit 4
CVRSS: Comparator VREF Source Selection bit
1= Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0= Comparator reference source, CVRSRC = VDD – VSS
bit 3-0
CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15)
When CVRR = 1:
CVREF = ((CVR3:CVR0)/24) • (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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FIGURE 22-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
CVRSS = 0
VREF+
VDD
8R
CVR3:CVR0
R
CVREN
R
R
R
16 Steps
CVREF
R
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
22.2 Voltage Reference Accuracy/Error
22.4 Effects of a Reset
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 22-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 26.0 “Electrical Characteristics”.
A device Reset disables the voltage reference by
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>) and selects the high-voltage
range by clearing bit, CVRR (CVRCON<5>). The CVR
value select bits are also cleared.
22.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto RA2 when it is configured as a digital input will
increase current consumption. Connecting RF5 as a
digital output with CVRSS enabled will also increase
current consumption.
22.3 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 22-2 shows an example buffering technique.
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PIC18F87J10 FAMILY
FIGURE 22-2:
COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18F87J10
CVREF
Module
(1)
R
+
–
CVREF Output
RF5
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.
TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVRCON
CMCON
TRISF
CVREN
C2OUT
TRISF7
CVROE
C1OUT
TRISF6
CVRR
C2INV
CVRSS
C1INV
CVR3
CIS
CVR2
CM2
CVR1
CM1
CVR0
CM0
—
51
51
52
TRISF5 TRISF4
TRISF3
TRISF2
TRISF1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.
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NOTES:
DS39663A-page 266
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PIC18F87J10 FAMILY
23.1.1
CONSIDERATIONS FOR
CONFIGURING THE PIC18F87J10
FAMILY DEVICES
23.0 SPECIAL FEATURES OF THE
CPU
PIC18F87J10 family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These are:
Unlike previous PIC18 microcontrollers, devices of the
PIC18F87J10 family do not use persistent memory
registers to store configuration information. The config-
uration bytes are implemented as volatile memory
which means that configuration data must be
programmed each time the device is powered up.
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
Configuration data is stored in the four words at the top
of the on-chip program memory space, known as the
Flash Configuration Words. It is stored in program
memory in the same order shown in Table 23-1, with
CONFIG1L at the lowest address and CONFIG3H at
the highest. The data is automatically loaded in the
proper Configuration registers during device power-up.
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data; this is
to make certain that program code is not stored in this
address when the code is compiled.
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
The volatile memory cells used for the configuration
bits always reset to ‘1’ on Power-on Resets. For all
other type of Reset events, the previously programmed
values are maintained and used without reloading from
program memory.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F87J10 family of
devices have a configurable Watchdog Timer which is
controlled in software.
The four Most Significant bits of CONFIG1H,
CONFIG2H and CONFIG3H in program memory
should also be ‘1111’. This makes these Configuration
Words appear to be NOP instructions in the remote
event that their locations are ever executed by
accident. Since configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed
almost immediately on start-up, while the primary clock
source completes its start-up delays.
To prevent inadvertent configuration changes during
code execution, all programmable configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
23.1 Configuration Bits
The configuration bits can be programmed (read as ‘0’)
or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h. A complete list
is shown in Table 23-1. A detailed explanation of the
various bit functions is provided in Register 23-1
through Register 23-6.
Note that address 300000h is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (300000h-3FFFFFh) which can only be
accessed using table reads and table writes.
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TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs
Default/
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unprogrammed
(1)
Value
300000h CONFIG1L DEBUG
XINST STVREN
—
—
—
—
—
WDTEN 111- ---1
---- 01--
FOSC0 11-- -111
(2)
(2)
(2)
(2)
(3)
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
—
—
—
—
—
CP0
—
IESO
FCMEN
—
—
—
FOSC2
FOSC1
(2)
(2)
(2)
(2)
—
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111
(4)
(4)
(4)
(4)
(4)
300004h CONFIG3L WAIT
BW
EMB1
EMB0
EASHFT
—
—
—
ECCPMX
REV1
—
1111 1---
(2)
(2)
(2)
(2)
(4)
300005h CONFIG3H
3FFFFEh DEVID1
3FFFFFh DEVID2
—
—
—
—
—
CCP2MX ---- --11
(5)
(5)
DEV2
DEV1
DEV9
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV0
DEV3
xxxx xxxx
0000 10x1
DEV10
DEV4
Legend:
x= unknown, u= unchanged, -= unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset
states, the configuration bytes maintain their previously programmed states.
2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOPif it
is accidentally executed.
3: This bit should always be maintained as ‘0’.
4: Implemented in 80-pin devices only.
5: See Register 23-7 and Register 23-8 for DEVID values. These registers are read-only and cannot be programmed by
the user.
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REGISTER 23-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
R/WO-1
DEBUG
R/WO-1
XINST
R/WO-1
U-0
—
U-0
—
U-0
—
U-0
—
R/WO-1
WDTEN
STVREN
bit 7
bit 0
bit 7
bit 6
bit 5
DEBUG: Background Debugger Enable bit
1= Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
0= Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1= Instruction set extension and Indexed Addressing mode enabled
0= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
STVREN: Stack Overflow/Underflow Reset Enable bit
1= Reset on stack overflow/underflow enabled
0= Reset on stack overflow/underflow disabled
bit 4-1
bit 0
Unimplemented: Read as ‘0’
WDTEN: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on SWDTEN bit)
Legend:
R = Readable bit
WO = Write-once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
REGISTER 23-2: CONFIG1H:CONFIGURATIONREGISTER1HIGH(BYTEADDRESS300001h)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
R/WO-1
CP0
U-0
—
U-0
—
(1)
—
bit 7
bit 0
bit 7-3 Unimplemented: Read as ‘0’
bit 2 CP0: Code Protection bit
1= Program memory is not code-protected
0= Program memory is code-protected
bit 1-0 Unimplemented: Read as ‘0’
Note 1: This bit should always be maintained as ‘0’.
Legend:
R = Readable bit
WO = Write-once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
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REGISTER 23-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
R/WO-1
IESO
R/WO-1
FCMEN
U-0
—
U-0
—
U-0
—
R/WO-1
FOSC2
R/WO-1
FOSC1
R/WO-1
FOSC0
bit 7
bit 0
bit 7
bit 6
IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit
1= Two-Speed Start-up enabled
0= Two-Speed Start-up disabled
FCMEN: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor enabled
0= Fail-Safe Clock Monitor disabled
bit 5-3 Unimplemented: Read as ‘0’
bit 2 FOSC2: Default/Reset System Clock Select bit
1= Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
0= INTRC enabled as system clock when OSCCON<1:0> = 00
bit 1-0 FOSC1:FOSC0: Oscillator Selection bits
11= EC oscillator, PLL enabled and under software control, CLKO function on OSC2
10= EC oscillator, CLKO function on OSC2
01= HS oscillator, PLL enabled and under software control
00= HS oscillator
Legend:
R = Readable bit
WO = Write-once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
REGISTER 23-4: CONFIG2H: CONFIGURATIONREGISTER 2HIGH (BYTEADDRESS300003h)
U-0
—
U-0
—
U-0
—
U-0
—
R/WO-1
R/WO-1
R/WO-1
R/WO-1
WDTPS3 WDTPS2 WDTPS1 WDTPS0
bit 0
bit 7
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits
1111= 1:32,768
1110= 1:16,384
1101= 1:8,192
1100= 1:4,096
1011= 1:2,048
1010= 1:1,024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
Legend:
R = Readable bit
WO = Write-once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
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REGISTER 23-5: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)
R/WO-1
WAIT(1)
bit 7
R/WO-1
BW(1)
R/WO-1
EMB1(1)
R/WO-1
EMB0(1) EASHFT(1)
R/WO-1
U-0
—
U-0
—
U-0
—
bit 0
bit 7
bit 6
WAIT: External Bus Wait Enable bit(1)
1= Wait states for operations on external memory bus disabled
0= Wait states for operations on external memory bus enabled
BW: Data Bus Width Select bit(1)
1= 16-bit External Bus mode
0= 8-bit External Bus mode
bit 5-4 EMB1:EMB0: External Memory Bus Configuration bits(1)
11= Extended Microcontroller mode, 20-bit Address mode
10= Extended Microcontroller mode,16-bit Address mode
01= Extended Microcontroller mode,12-bit Address mode
00= Microcontroller mode – external bus disabled
bit 3
EASHFT: External Address Bus Shift Enable bit(1)
1= Address shifting enabled; address on external bus is offset to start at 000000h
0= Address shifting disabled; address on external bus reflects the PC value
bit 2-0 Unimplemented: Read as ‘0’
Note 1: Implemented only on 80-pin devices.
Legend:
R = Readable bit
WO = Write-once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
REGISTER 23-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/WO-1
ECCPMX(1) CCP2MX
R/WO-1
bit 7
bit 0
bit 7-2 Unimplemented: Read as ‘0’
bit 1
ECCPMX: ECCP Mux bit(1)
1= ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5;
ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3
0 = ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6;
ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4
bit 0
CCP2MX: CCP2 Mux bit
1= ECCP2/P2A is multiplexed with RC1
0= ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (all devices)
or with RB3 in Extended Microcontroller mode (80-pin devices only)
Note 1: Available only on 80-pin devices.
Legend:
R = Readable bit
WO = Write-once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
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REGISTER 23-7: DEVICE ID REGISTER 1 FOR PIC18F87J10 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
bit 7-5 DEV2:DEV0: Device ID bits
111= PIC18F85J10
101= PIC18F67J10
100= PIC18F66J15
011= PIC18F66J10 or PIC18F87J10
010= PIC18F65J15 or PIC18F86J15
001= PIC18F65J10 or PIC18F86J10
000= PIC18F85J15
Note:
Where values for DEV2:DEV0 are shared by more than one device number, the
specific device is always identified by using the entire DEV10:DEV0 bit sequence.
bit 4-0 REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
Legend:
R = Read-only bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
REGISTER 23-8: DEVICE ID REGISTER 2 FOR PIC18F87J10 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
bit 7-0 DEV10:DEV3: Device ID bits
These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the
part number.
0001 0101= PIC18F65J10/65J15/66J10/66J15/67J10/85J10 devices
0001 0111= PIC18F85J15/86J10/86J15/87J10 devices
Note:
The values for DEV10:DEV3 may be shared with other device families. The specific
device is always identified by using the entire DEV10:DEV0 bit sequence.
Legend:
R = Read-only bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
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23.2 Watchdog Timer (WDT)
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
For PIC18F87J10 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
2: When a CLRWDTinstruction is executed,
the postscaler count will be cleared.
23.2.1
CONTROL REGISTER
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared whenever a SLEEPor
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
The WDTCON register (Register 23-9) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN configuration bit and enable the WDT only
if it has been disabled by the configuration bit.
FIGURE 23-1:
WDT BLOCK DIAGRAM
Enable WDT
INTRC Control
SWDTEN
WDT Counter
Wake-up from
Power-Managed
Modes
÷128
INTRC Oscillator
WDT
Reset
Reset
CLRWDT
All Device Resets
Programmable Postscaler
1:1 to 1:32,768
WDT
4
WDTPS3:WDTPD0
Sleep
REGISTER 23-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
R/W-0
SWDTEN(1)
bit 0
—
bit 7
bit 7-1 Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1= Watchdog Timer is on
0= Watchdog Timer is off
Note 1: This bit has no effect if the configuration bit, WDTEN, is enabled.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
TABLE 23-2: SUMMARY OF WATCHDOG TIMER REGISTERS
ResetValues
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on page
RCON
WDTCON
IPEN
—
—
—
—
—
RI
—
TO
—
PD
—
POR
—
BOR
50
50
SWDTEN
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
2005 Microchip Technology Inc.
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PIC18F87J10 FAMILY
FIGURE 23-2:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
23.3 On-Chip Voltage Regulator
All of the PIC18F87J10 family devices power their core
digital logic at a nominal 2.5V. This may create an issue
for designs that are required to operate at a higher
typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC18F87J10 family incor-
porate an on-chip regulator that allows the device to
run its core logic from VDD.
Regulator Enabled (ENVREG tied to VDD):
3.3V
PIC18FXXJ10/XXJ15
VDD
ENVREG
The regulator is controlled by the ENVREG pin. Tying
VDD to the pin enables the regulator, which in turn, pro-
vides power to the core from the other VDD pins. When
the regulator is enabled, a low-ESR filter capacitor
must be connected to the VDDCORE/VCAP pin
(Figure 23-2). This helps to maintain the stability of the
regulator. The recommended value for the filer capaci-
tor is provided in Section 26.3 “DC Characteristics:
PIC18F87J10 Family (Industrial)”.
VDDCORE/VCAP
CF
VSS
Regulator Disabled (ENVREG tied to ground):
(1)
(1)
2.5V
3.3V
If ENVREG is tied to VSS, the regulator is disabled. In
this case, separate power for the core logic at a nomi-
nal 2.5V must be supplied to the device on the
VDDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 23-2 for possible
configurations.
PIC18FXXJ10/XXJ15
VDD
ENVREG
VDDCORE/VCAP
VSS
23.3.1
ON-CHIP REGULATOR AND BOR
When the on-chip regulator is enabled, PIC18F87J10
family devices also have a simple brown-out capability.
If the voltage supplied to the regulator is inadequate to
maintain a regulated level, the regulator Reset circuitry
will generate a BOR Reset. This event is captured by
the BOR flag bit (RCON<0>).
Regulator Disabled (VDD tied to VDDCORE):
(1)
2.5V
PIC18FXXJ10/XXJ15
VDD
ENVREG
The operation of the BOR is described in more detail in
Section 4.4 “Brown-out Reset (BOR)” and
Section 4.4.1 “Detecting BOR”. The brown-out voltage
levels are specific in Section 26.1 “DC Characteristics:
Supply Voltage, PIC18F87J10 Family (Industrial)”.
VDDCORE/VCAP
VSS
23.3.2
POWER-UP REQUIREMENTS
Note 1: These are typical operating voltages. Refer
to Section 26.1 “DC Characteristics:
Supply Voltage” for the full operating
ranges of VDD and VDDCORE.
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.
DS39663A-page 274
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In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
23.4 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
configuration bit.
23.4.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
Two-Speed Start-up should be enabled only if the
primary oscillator mode is HS or HSPLL
(Crystal-based) modes. Since the EC and ECPLL
modes do not require an OST start-up delay,
Two-Speed Start-up should be disabled.
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including serial SLEEP instructions (refer to
Section 3.1.4 “Multiple Sleep Commands”). In prac-
tice, this means that user code can change the
SCS1:SCS0 bit settings or issue SLEEP instructions
before the OST times out. This would allow an applica-
tion to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a POR Reset is
enabled. This allows almost immediate code execution
while the primary oscillator starts and the OST is run-
ning. Once the OST times out, the device automatically
switches to PRI_RUN mode.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
FIGURE 23-3:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q4
Q1
Q2 Q3 Q4 Q1 Q2
Q3
Q3
Q1
Q2
INTOSC
OSC1
(1)
(1)
TOST
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC
PC + 2
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
PC + 6
Wake from Interrupt Event
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To use a higher clock speed on wake-up, the INTOSC
or postscaler clock sources can be selected to provide
a higher clock speed by setting bits IRCF2:IRCF0
immediately after Reset. For wake-ups from Sleep, the
INTOSC or postscaler clock sources can be selected
by setting IRCF2:IRCF0 prior to entering Sleep mode.
23.5 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching the
device clock to the internal oscillator block. The FSCM
function is enabled by setting the FCMEN configuration
bit.
The FSCM will detect failures of the primary or second-
ary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any action
be possible.
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide a
backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 23-4) is accomplished by
creating a sample clock signal which is the INTRC out-
put divided by 64. This allows ample time between
FSCM sample clocks for a peripheral clock edge to
occur. The peripheral device clock and the sample
clock are presented as inputs to the Clock Monitor latch
(CM). The CM is set on the falling edge of the device
clock source but cleared on the rising edge of the
sample clock.
23.5.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
As already noted, the clock source is switched to the
INTRC clock when a clock failure is detected; this may
mean a substantial change in the speed of code execu-
tion. If the WDT is enabled with a small prescale value,
a decrease in clock speed allows a WDT time-out to
occur and a subsequent device Reset. For this reason,
fail-safe clock events also reset the WDT and
postscaler, allowing it to start timing from when execu-
tion speed was changed and decreasing the likelihood
of an erroneous time-out.
FIGURE 23-4:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)
(edge-triggered)
Peripheral
Clock
S
C
Q
Q
INTRC
Source
23.5.2
EXITING FAIL-SAFE OPERATION
÷ 64
The fail-safe condition is terminated by either a device
Reset or by entering a power-managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 2H (with any
required start-up delays that are required for the oscil-
lator mode, such as OST or PLL timer). The INTRC
oscillator provides the device clock until the primary
clock source becomes ready (similar to a Two-Speed
Start-up). The clock source is then switched to the
primary clock (indicated by the OSTS bit in the
OSCCON register becoming set). The Fail-Safe Clock
Monitor then resumes monitoring the peripheral clock.
488 Hz
(2.048 ms)
(32 µs)
Clock
Failure
Detected
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure 23-5). This causes the following:
• the FSCM generates an oscillator fail interrupt by
setting bit OSCFIF (PIR2<7>);
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTRC oscillator. The OSCCON register will remain in
its Reset state until a power-managed mode is entered.
• the device clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source – this is the fail-safe
condition); and
• the WDT is reset.
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable
for timing sensitive applications. In these cases, it may
be desirable to select another clock configuration and
enter an alternate power-managed mode. This can be
done to attempt a partial recovery or execute a
controlled shutdown. See Section 3.1.4 “Multiple
Sleep Commands” and Section 23.4.1 “Special
Considerations for Using Two-Speed Start-up” for
more details.
DS39663A-page 276
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FIGURE 23-5:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
Device
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
CM Test
CM Test
Note:
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
23.5.3
FSCM INTERRUPTS IN
23.5.4
POR OR WAKE-UP FROM SLEEP
POWER-MANAGED MODES
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
device clock is either EC or INTRC modes, monitoring
can begin immediately following these events.
By entering a power-managed mode, the clock
multiplexor selects the clock source selected by the
OSCCON register. Fail-Safe Monitoring of the
power-managed clock source resumes in the
power-managed mode.
For HS or HSPLL modes, the situation is somewhat dif-
ferent. Since the oscillator may require a start-up time
considerably longer than the FSCM sample clock time,
a false clock failure may be detected. To prevent this,
the internal oscillator block is automatically configured
as the device clock and functions until the primary clock
is stable (the OST and PLL timers have timed out). This
is identical to Two-Speed Start-up mode. Once the
primary clock is stable, the INTRC returns to its role as
the FSCM source.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTOSC multiplexor. An automatic transition
back to the failed clock source will not occur.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTOSC
source.
Note:
The same logic that prevents false oscilla-
tor failure interrupts on POR, or wake from
Sleep, will also prevent the detection of
the oscillator’s failure to start at all follow-
ing these events. This can be avoided by
monitoring the OSTS bit and using a
timing routine to determine if the oscillator
is taking too long to start. Even so, no
oscillator failure interrupt will be flagged.
As noted in Section 23.4.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alternate
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.
2005 Microchip Technology Inc.
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PIC18F87J10 FAMILY
23.6 Program Verification and
Code Protection
23.7
In-Circuit Serial Programming
PIC18F87J10 family microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
For all devices in the PIC18F87J10 family of devices,
the on-chip program memory space is treated as a
single block. Code protection for this block is controlled
by one configuration bit, CP0. This bit inhibits external
reads and writes to the program memory space. It has
no direct effect in normal execution mode.
23.6.1
CONFIGURATION REGISTER
PROTECTION
23.8 In-Circuit Debugger
The Configuration registers are protected against
untoward changes or reads in two ways. The primary
protection is the write-once feature of the configuration
bits which prevents reconfiguration once the bit has
been programmed during a power cycle. To safeguard
against unpredictable events, configuration bit changes
resulting from individual cell-level disruptions (such as
ESD events) will cause a parity error and trigger a
device Reset.
When the DEBUG configuration bit is programmed to a
‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB® IDE. When the microcontroller has
this feature enabled, some resources are not available
for general use. Table 23-3 shows which resources are
required by the background debugger.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the CP0 bit set, the source data for device
configuration is also protected as a consequence.
TABLE 23-3: DEBUGGER RESOURCES
I/O pins:
RB6, RB7
2 levels
Stack:
Program Memory:
Data Memory:
512 bytes
10 bytes
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PIC18F87J10 FAMILY
The literal instructions may use some of the following
operands:
24.0 INSTRUCTION SET SUMMARY
The PIC18F87J10 family of devices incorporate the
standard set of 75 PIC18 core instructions, as well as
an extended set of 8 new instructions for the optimiza-
tion of code that is recursive or that utilizes a software
stack. The extended set is discussed later in this
section.
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
24.1 Standard Instruction Set
The control instructions may use some of the following
operands:
The standard PIC18 instruction set adds many
enhancements to the previous PICmicro® instruction
sets, while maintaining an easy migration from these
PICmicro instruction sets. Most instructions are a
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
• A program memory address (specified by ‘n’)
• The mode of the CALLor RETURNinstructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required
(specified by ‘—’)
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are 1’s. If this
second word is executed as an instruction (by itself), it
will execute as a NOP.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
• Control operations
The PIC18 instruction set summary in Table 24-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 24-1 shows the opcode field
descriptions.
The double word instructions execute in two instruction
cycles.
Most byte-oriented instructions have three operands:
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 µs.
Two-word branch instructions (if true) would take 3 µs.
1. The file register (specified by ‘f’)
2. The destination of the result (specified by ‘d’)
3. The accessed memory (specified by ‘a’)
The file register designator ‘f’ specifies which file regis-
ter is to be used by the instruction. The destination
designator ‘d’ specifies where the result of the
operation is to be placed. If ‘d’ is zero, the result is
placed in the WREG register. If ‘d’ is one, the result is
placed in the file register specified in the instruction.
Figure 24-1 shows the general formats that the instruc-
tions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The Instruction Set Summary, shown in Table 24-2,
lists the standard instructions recognized by the
Microchip MPASMTM Assembler.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
Section 24.1.1 “Standard Instruction Set” provides
a description of each instruction.
2. The bit in the file register (specified by ‘b’)
3. The accessed memory (specified by ‘a’)
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register desig-
nator ‘f’ represents the number of the file in which the
bit is located.
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TABLE 24-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit file register (0 to 7).
BSR
Bank Select Register. Used to select the current RAM bank.
ALU status bits: Carry, Digit Carry, Zero, Overflow, Negative.
C, DC, Z, OV, N
d
Destination select bit:
d = 0: store result in WREG
d = 1: store result in file register f
dest
f
Destination: either the WREG register or the specified register file location.
8-bit Register file address (00h to FFh), or 2-bit FSR designator (0h to 3h).
12-bit Register file address (000h to FFFh). This is the source address.
12-bit Register file address (000h to FFFh). This is the destination address.
Global Interrupt Enable bit.
f
f
s
d
GIE
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
Label name.
label
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No Change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC
Program Counter.
PCL
Program Counter Low Byte.
Program Counter High Byte.
Program Counter High Byte Latch.
Program Counter Upper Byte Latch.
Power-Down bit.
PCH
PCLATH
PCLATU
PD
PRODH
PRODL
s
Product of Multiply High Byte.
Product of Multiply Low Byte.
Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR
TABLAT
TO
21-bit Table Pointer (points to a Program Memory location).
8-bit Table Latch.
Time-out bit.
TOS
u
Top-of-Stack.
Unused or Unchanged.
Watchdog Timer.
WDT
WREG
x
Working register (accumulator).
Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
z
z
{
7-bit offset value for indirect addressing of register files (source).
7-bit offset value for indirect addressing of register files (destination).
Optional argument.
s
d
}
[text]
(text)
[expr]<n>
→
Indicates an indexed address.
The contents of text.
Specifies bit nof the register indicated by the pointer expr.
Assigned to.
< >
Register bit field.
∈
In the set of.
italics
User-defined term (font is Courier).
DS39663A-page 280
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PIC18F87J10 FAMILY
FIGURE 24-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10
OPCODE f (FILE #)
Example Instruction
9
8
7
0
ADDWF MYREG, W, B
d
a
d = 0for result destination to be WREG register
d = 1for result destination to be file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
OPCODE
f (Source FILE #)
MOVFF MYREG1, MYREG2
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
MOVLW 7Fh
OPCODE
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
n<7:0> (literal)
S
0
1111
n<19:8> (literal)
S = Fast bit
15
11 10
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
n<10:0> (literal)
15
OPCODE
8 7
n<7:0> (literal)
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PIC18F87J10 FAMILY
TABLE 24-2: PIC18F87J10 FAMILY INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f
ADDWFC f, d, a Add WREG and Carry bit to f
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2
0010 00da ffff ffff C, DC, Z, OV, N 1, 2
1
1
1
1
ANDWF
CLRF
COMF
f, d, a AND WREG with f
f, a Clear f
f, d, a Complement f
0001 01da ffff ffff Z, N
0110 101a ffff ffff Z
0001 11da ffff ffff Z, N
1,2
2
1, 2
4
CPFSEQ
CPFSGT
CPFSLT
DECF
f, a
f, a
f, a
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
1 (2 or 3) 0110 001a ffff ffff None
1 (2 or 3) 0110 010a ffff ffff None
1 (2 or 3) 0110 000a ffff ffff None
4
1, 2
f, d, a Decrement f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ
DCFSNZ
INCF
f, d, a Decrement f, Skip if 0
f, d, a Decrement f, Skip if Not 0
f, d, a Increment f
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1, 2, 3, 4
1, 2
1
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ
INFSNZ
IORWF
MOVF
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
fs, fd Move fs (source) to 1st word
fd (destination) 2nd word
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4
1, 2
1, 2
1
1
1
2
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
f, a
f, a
f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
0101 01da ffff ffff C, DC, Z, OV, N
1, 2
1, 2
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
RRNCF
SETF
f, a
Set f
1, 2
SUBFWB f, d, a Subtract f from WREG with
borrow
SUBWF
f, d, a Subtract WREG from f
1
1
0101 11da ffff ffff C, DC, Z, OV, N 1, 2
0101 10da ffff ffff C, DC, Z, OV, N
SUBWFB f, d, a Subtract WREG from f with
borrow
SWAPF
TSTFSZ
XORWF
f, d, a Swap nibbles in f
f, a Test f, skip if 0
f, d, a Exclusive OR WREG with f
1
0011 10da ffff ffff None
4
1, 2
1 (2 or 3) 0110 011a ffff ffff None
0001 10da ffff ffff Z, N
1
Note 1: When a port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: In normal execution modes, table write operations cannot be used to write to any on-chip memory space. For
80-pin devices, table write instructions may also be used to write to an external memory device. For more
information, see Section 6.4 “Writing to Program Memory Space (PIC18F8XJ10/8XJ15 Devices Only)”
and Section 6.6 “Writing and Erasing On-Chip Program Memory (ICSP Mode)”.
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TABLE 24-2: PIC18F87J10 FAMILY INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, b, a Bit Toggle f
1
1
1001 bbba ffff ffff None
1000 bbba ffff ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba ffff ffff None
1 (2 or 3) 1010 bbba ffff ffff None
1
0111 bbba ffff ffff None
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1110 0010 nnnn nnnn None
1110 0110 nnnn nnnn None
1110 0011 nnnn nnnn None
1110 0111 nnnn nnnn None
1110 0101 nnnn nnnn None
1110 0001 nnnn nnnn None
1110 0100 nnnn nnnn None
1101 0nnn nnnn nnnn None
1110 0000 nnnn nnnn None
1110 110s kkkk kkkk None
1111 kkkk kkkk kkkk
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
1 (2)
2
CALL
Call subroutine 1st word
2nd word
CLRWDT
DAW
GOTO
—
—
n
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
1
1
2
0000 0000 0000 0100 TO, PD
0000 0000 0000 0111 C
1110 1111 kkkk kkkk None
1111 kkkk kkkk kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
No Operation
1
1
1
1
2
1
2
0000 0000 0000 0000 None
1111 xxxx xxxx xxxx None
0000 0000 0000 0110 None
0000 0000 0000 0101 None
1101 1nnn nnnn nnnn None
0000 0000 1111 1111 All
0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
4
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
s
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100 kkkk kkkk None
0000 0000 0001 001s None
0000 0000 0000 0011 TO, PD
Note 1: When a port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: In normal execution modes, table write operations cannot be used to write to any on-chip memory space. For
80-pin devices, table write instructions may also be used to write to an external memory device. For more
information, see Section 6.4 “Writing to Program Memory Space (PIC18F8XJ10/8XJ15 Devices Only)”
and Section 6.6 “Writing and Erasing On-Chip Program Memory (ICSP Mode)”.
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TABLE 24-2: PIC18F87J10 FAMILY INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
1
0000 1111 kkkk kkkk C, DC, Z, OV, N
0000 1011 kkkk kkkk Z, N
0000 1001 kkkk kkkk Z, N
1110 1110 00ff kkkk None
1111 0000 kkkk kkkk
1
1
2
to FSR(f)
1st word
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
1
1
1
2
1
0000 0001 0000 kkkk None
0000 1110 kkkk kkkk None
0000 1101 kkkk kkkk None
0000 1100 kkkk kkkk None
0000 1000 kkkk kkkk C, DC, Z, OV, N
0000 1010 kkkk kkkk Z, N
Exclusive OR literal with WREG 1
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000 1000 None
0000 0000 0000 1001 None
0000 0000 0000 1010 None
0000 0000 0000 1011 None
0000 0000 0000 1100 None
0000 0000 0000 1101 None
0000 0000 0000 1110 None
0000 0000 0000 1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2
5
5
5
5
Note 1: When a port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: In normal execution modes, table write operations cannot be used to write to any on-chip memory space. For
80-pin devices, table write instructions may also be used to write to an external memory device. For more
information, see Section 6.4 “Writing to Program Memory Space (PIC18F8XJ10/8XJ15 Devices Only)”
and Section 6.6 “Writing and Erasing On-Chip Program Memory (ICSP Mode)”.
DS39663A-page 284
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PIC18F87J10 FAMILY
24.1.1
STANDARD INSTRUCTION SET
ADDLW
ADD Literal to W
ADDWF
ADD W to f
Syntax:
ADDLW
k
Syntax:
ADDWF
f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + k → W
N, OV, C, DC, Z
Operation:
(W) + (f) → dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
0010
01da
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
ADDLW
15h
Before Instruction
10h
After Instruction
25h
W
=
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWF
REG, 0, 0
Before Instruction
W
REG
=
=
17h
0C2h
After Instruction
W
REG
=
=
0D9h
0C2h
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
2005 Microchip Technology Inc.
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ADDWFC
ADD W and Carry bit to f
ANDLW
AND Literal with W
Syntax:
ADDWFC
f {,d {,a}}
Syntax:
ANDLW
k
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .AND. k → W
N, Z
Operation:
(W) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
0010
00da
ffff
ffff
Description:
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
ANDLW
05Fh
Before Instruction
W
=
A3h
03h
After Instruction
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWFC
REG, 0, 1
Before Instruction
Carry bit =
1
02h
4Dh
REG
W
=
=
After Instruction
Carry bit =
0
02h
50h
REG
W
=
=
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ANDWF
AND W with f
BC
Branch if Carry
BC
Syntax:
ANDWF
f {,d {,a}}
Syntax:
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(W) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ’1’, then the program
Description:
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Words:
Cycles:
1
1
No
No
No
operation
No
operation
operation
operation
Q Cycle Activity:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
ANDWF
REG, 0, 0
Example:
HERE
BC
5
Before Instruction
Before Instruction
W
REG
=
=
17h
C2h
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
1;
W
REG
=
=
02h
C2h
address (HERE + 12)
0;
address (HERE + 2)
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BCF
Bit Clear f
BN
Branch if Negative
BN
Syntax:
BCF f, b {,a}
Syntax:
n
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Negative bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ‘1’, then the
Description:
Bit ‘b’ in register ‘f’ is cleared.
program will branch.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
BCF
FLAG_REG, 7, 0
Before Instruction
FLAG_REG = C7h
After Instruction
FLAG_REG = 47h
Example:
HERE
BN Jump
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
PC
If Negative
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
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BNC
Branch if Not Carry
BNC
BNN
Branch if Not Negative
BNN
Syntax:
n
Syntax:
n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘0’
(PC) + 2 + 2n → PC
if Negative bit is ‘0’
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the program
Description:
If the Negative bit is ‘0’, then the
will branch.
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNC Jump
Example:
HERE
BNN Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
0;
If Negative
PC
If Negative
PC
=
=
=
=
0;
address (Jump)
address (Jump)
1;
1;
address (HERE + 2)
address (HERE + 2)
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BNOV
Branch if Not Overflow
BNOV
BNZ
Branch if Not Zero
BNZ
Syntax:
n
Syntax:
n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if Overflow bit is ‘0’
(PC) + 2 + 2n → PC
if Zero bit is ‘0’
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
Description:
If the Zero bit is ‘0’, then the program
program will branch.
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNOV Jump
Example:
HERE
BNZ Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
0;
If Zero
PC
If Zero
PC
=
=
=
=
0;
address (Jump)
address (Jump)
1;
1;
address (HERE + 2)
address (HERE + 2)
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BRA
Unconditional Branch
BRA
BSF
Bit Set f
Syntax:
n
Syntax:
BSF f, b {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation:
1 → f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
1
2
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
HERE
BRA Jump
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
PC
=
=
address (HERE)
address (Jump)
After Instruction
PC
Example:
BSF
FLAG_REG, 7, 1
0Ah
8Ah
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
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BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSC f, b {,a}
Syntax:
BTFSS f, b {,a}
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Example:
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
1;
address (FALSE)
address (TRUE)
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BTG
Bit Toggle f
BOV
Branch if Overflow
BOV
Syntax:
BTG f, b {,a}
Syntax:
n
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Overflow bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ‘1’, then the
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted.
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
1
Decode
Read literal
‘n’
Process
Data
Write to PC
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
BTG
PORTC, 4, 0
Before Instruction:
PORTC
After Instruction:
PORTC
=
0111 0101 [75h]
0110 0101 [65h]
Example:
HERE
BOV Jump
Before Instruction
=
PC
=
address (HERE)
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
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BZ
Branch if Zero
BZ
CALL
Subroutine Call
Syntax:
n
Syntax:
CALL k {,s}
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
0 ≤ k ≤ 1048575
s ∈ [0,1]
if Zero bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>,
if s = 1
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Description:
If the Zero bit is ‘1’, then the program
will branch.
Status Affected:
None
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2-Mbyte mem-
ory range. First, return address (PC+ 4)
is pushed onto the return stack. If
‘s’ = 1, the W, STATUS and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALLis a two-cycle instruction.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal Push PC to Read literal
‘k’<7:0>,
stack
’k’<19:8>,
Write to PC
Example:
HERE
BZ Jump
No
No
No
No
Before Instruction
operation
operation
operation
operation
PC
=
address (HERE)
After Instruction
Example:
HERE
CALL THERE,1
If Zero
PC
If Zero
PC
=
=
=
=
1;
address (Jump)
Before Instruction
PC
After Instruction
0;
=
address (HERE)
address (HERE + 2)
PC
=
address (THERE)
TOS
WS
=
=
=
address (HERE + 4)
W
BSRS
BSR
STATUS
STATUSS =
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CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
CLRF f {,a}
Syntax:
CLRWDT
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
1
1
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
Process
Data
No
operation
operation
Words:
Cycles:
1
1
Example:
CLRWDT
Before Instruction
Q Cycle Activity:
Q1
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
=
?
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
=
=
=
=
00h
0
1
PD
1
Example:
CLRF
FLAG_REG,1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
5Ah
00h
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CPFSEQ
Compare f with W, Skip if f = W
COMF
Complement f
Syntax:
CPFSEQ f {,a}
Syntax:
COMF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Operation:
(f) → dest
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘f’ = W, then the fetched instruction is
discarded and a NOPis executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
Q2
Q3
Q4
1(2)
Decode
Read
register ‘f’
Process
Data
Write to
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Example:
COMF
REG, 0, 0
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Before Instruction
Decode
REG
=
13h
After Instruction
If skip:
Q1
REG
W
=
=
13h
ECh
Q2
No
Q3
No
Q4
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
No
Q2
No
Q3
No
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
operation
operation
operation
Example:
HERE
CPFSEQ REG, 0
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
=
=
HERE
?
?
W
REG
After Instruction
If REG
PC
If REG
PC
=
=
≠
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
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CPFSGT
Compare f with W, Skip if f > W
CPFSLT
Compare f with W, Skip if f < W
Syntax:
CPFSGT f {,a}
Syntax:
CPFSLT f {,a}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) – (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
Process
Data
No
operation
1(2)
register ‘f’
Note: 3 cycles if skip and followed
by a 2-word instruction.
If skip:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Decode
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
No
Q3
No
Q4
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
No
operation
No
Q2
No
operation
No
Q3
No
operation
No
Q4
No
operation
No
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
operation
operation
operation
operation
Before Instruction
PC
W
=
=
Address (HERE)
?
Example:
HERE
CPFSGT REG, 0
NGREATER
GREATER
:
:
After Instruction
If REG
PC
If REG
PC
<
=
≥
=
W;
Address (LESS)
W;
Before Instruction
PC
W
=
=
Address (HERE)
?
Address (NLESS)
After Instruction
If REG
PC
If REG
PC
>
=
≤
=
W;
Address (GREATER)
W;
Address (NGREATER)
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DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
DAW
None
Syntax:
DECF f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
If [W<3:0> > 9] or [DC = 1] then
(W<3:0>) + 6 → W<3:0>;
else
Operation:
(f) – 1 → dest
(W<3:0>) → W<3:0>
Status Affected:
Encoding:
C, DC, N, OV, Z
0000
01da
ffff
ffff
If [W<7:4> > 9] or [C = 1] then
(W<7:4>) + 6 → W<7:4>;
C = 1;
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
else
(W<7:4>) → W<7:4>
Status Affected:
Encoding:
C
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
0000
0000
0000
0111
Description:
DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
DAW
Before Instruction
W
=
A5h
0
Example:
DECF
CNT,
1, 0
C
=
=
DC
0
Before Instruction
After Instruction
CNT
Z
=
01h
0
W
=
=
=
05h
1
0
=
C
After Instruction
DC
CNT
Z
=
=
00h
1
Example 2:
Before Instruction
W
=
=
=
CEh
0
0
C
DC
After Instruction
W
=
=
=
34h
1
0
C
DC
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DECFSZ
Decrement f, Skip if 0
DCFSNZ
Decrement f, Skip if not 0
Syntax:
DECFSZ f {,d {,a}}
Syntax:
DCFSNZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
Operation:
(f) – 1 → dest,
skip if result = 0
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
Process
Data
Write to
destination
register ‘f’
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
DECFSZ
GOTO
CNT, 1, 1
LOOP
Example:
HERE
ZERO
NZERO
DCFSNZ TEMP, 1, 0
:
:
CONTINUE
Before Instruction
PC
After Instruction
Before Instruction
TEMP
After Instruction
=
Address (HERE)
=
?
CNT
=
CNT – 1
0;
If CNT
=
=
≠
=
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
≠
=
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
PC
Address (CONTINUE)
0;
If CNT
PC
Address (HERE + 2)
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GOTO
Unconditional Branch
GOTO
INCF
Increment f
Syntax:
k
Syntax:
INCF f {,d {,a}}
Operands:
Operation:
Status Affected:
0 ≤ k ≤ 1048575
k → PC<20:1>
None
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C, DC, N, OV, Z
1110
1111
1111
kkk
k kkk
kkkk
kkkk
kkkk
7
0
8
k
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional branch
Description:
The contents of register ‘f’ are
anywhere within entire 2-Mbyte memory
range. The 20-bit value ‘k’ is loaded into
PC<20:1>. GOTOis always a two-cycle
instruction.
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
2
2
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
No
No
No
No
operation
operation
operation
operation
Words:
Cycles:
1
1
Example:
GOTO THERE
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
PC
=
Address (THERE)
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
INCF
CNT, 1, 0
Before Instruction
CNT
Z
=
FFh
0
=
=
=
C
?
DC
?
After Instruction
CNT
Z
=
00h
1
=
=
=
C
1
DC
1
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INFSNZ
Increment f, Skip if not 0
INCFSZ
Increment f, Skip if 0
Syntax:
INFSNZ f {,d {,a}}
Syntax:
INCFSZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Operation:
(f) + 1 → dest,
skip if result = 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0100
10da
ffff
ffff
0011
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’. (default)
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction.
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
Example:
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Before Instruction
PC
After Instruction
Before Instruction
PC
After Instruction
=
Address (HERE)
=
Address (HERE)
REG
If REG
PC
If REG
PC
=
REG + 1
CNT
If CNT
PC
If CNT
PC
=
CNT + 1
≠
=
=
=
0;
=
=
≠
=
0;
Address (NZERO)
0;
Address (ZERO)
Address (ZERO)
0;
Address (NZERO)
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IORLW
Inclusive OR Literal with W
IORLW
IORWF
Inclusive OR W with f
Syntax:
k
Syntax:
IORWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .OR. k → W
N, Z
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed
in W.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
IORLW
35h
Before Instruction
W
=
9Ah
BFh
After Instruction
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
IORWF RESULT, 0, 1
Before Instruction
RESULT =
13h
91h
W
=
After Instruction
RESULT =
13h
93h
W
=
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LFSR
Load FSR
MOVF
Move f
Syntax:
LFSR f, k
Syntax:
MOVF f {,d {,a}}
Operands:
0 ≤ f ≤ 2
0 ≤ k ≤ 4095
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
k → FSRf
Operation:
f → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
1111
1110
0000
00ff
k kkk
k kkk
11
kkkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ‘k’ is loaded into the
file select register pointed to by ‘f’.
Description:
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 3ABh
After Instruction
FSR2H
FSR2L
=
=
03h
ABh
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
W
Example:
MOVF
REG, 0, 0
Before Instruction
REG
W
=
=
22h
FFh
After Instruction
REG
W
=
=
22h
22h
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MOVFF
Move f to f
MOVFF f ,f
MOVLB
Move Literal to Low Nibble in BSR
MOVLW
Syntax:
Syntax:
k
s
d
Operands:
0 ≤ f ≤ 4095
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
k → BSR
None
s
0 ≤ f ≤ 4095
d
Operation:
(f ) → f
s
d
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
1st word (source)
2nd word (destin.)
The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’
1100
1111
ffff
ffff
ffff
ffff
ffff
ffff
s
d
Description:
The contents of source register ‘f ’ are
regardless of the value of k :k .
7 4
s
moved to destination register ‘f ’.
d
Words:
Cycles:
1
1
Location of source ‘f ’ can be anywhere
s
in the 4096-byte data space (000h to
FFFh) and location of destination ‘f ’
can also be anywhere from 000h to
FFFh.
d
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write literal
‘k’ to BSR
Either source or destination can be W
(a useful special situation).
MOVFFis particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
Example:
MOVLB
5
Before Instruction
BSR Register =
After Instruction
BSR Register =
02h
05h
The MOVFFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register
Words:
Cycles:
2
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
REG1, REG2
Before Instruction
REG1
REG2
=
=
33h
11h
After Instruction
REG1
REG2
=
=
33h
33h
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MOVLW
Move Literal to W
MOVLW
MOVWF
Move W to f
Syntax:
k
Syntax:
MOVWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
0 ≤ k ≤ 255
k → W
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) → f
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
The eight-bit literal ‘k’ is loaded into W.
Description:
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
1
1
Cycles:
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
MOVLW
5Ah
After Instruction
W
=
5Ah
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
REG, 0
Before Instruction
W
REG
=
=
4Fh
FFh
After Instruction
W
REG
=
=
4Fh
4Fh
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MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
MULLW
k
Syntax:
MULWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(W) x k → PRODH:PRODL
Operation:
(W) x (f) → PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in PRODH:PRODL register pair.
PRODH contains the high byte.
Description:
An unsigned multiplication is carried out
between the contents of W and the
register file location ‘f’. The 16-bit result is
stored in the PRODH:PRODL register
pair. PRODH contains the high byte. Both
W and ‘f’ are unchanged.
W is unchanged.
None of the status flags are affected.
None of the status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result is
possible but not detected.
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULLW
0C4h
E2h
Words:
Cycles:
1
1
Before Instruction
W
PRODH
PRODL
=
=
=
?
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write
W
PRODH
PRODL
=
=
=
E2h
ADh
08h
registers
PRODH:
PRODL
Example:
MULWF
REG, 1
Before Instruction
W
=
=
=
=
C4h
REG
B5h
?
PRODH
PRODL
?
After Instruction
W
=
=
=
=
C4h
B5h
8Ah
94h
REG
PRODH
PRODL
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NEGF
Negate f
NOP
No Operation
Syntax:
NEGF f {,a}
Syntax:
NOP
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
None
No operation
None
Operation:
( f ) + 1 → f
Status Affected:
Encoding:
N, OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
Description:
Words:
No operation.
1
1
Cycles:
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q Cycle Activity:
Q1
Q2
Q3
No
operation
Q4
Decode
No
operation
No
operation
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
None.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
REG, 1
Before Instruction
REG
After Instruction
REG
=
0011 1010 [3Ah]
1100 0110 [C6h]
=
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POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
POP
Syntax:
PUSH
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
(TOS) → bit bucket
(PC + 2) → TOS
None
None
0000
0000
0000
0110
0000
0000
0000
0101
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
PUSH
No
No
Decode
No
operation
POP TOS
value
No
operation
PC + 2 onto
return stack
operation
operation
Example:
POP
Example:
PUSH
GOTO
NEW
Before Instruction
Before Instruction
TOS
Stack (1 level down)
TOS
PC
=
=
345Ah
0124h
=
=
0031A2h
014332h
After Instruction
After Instruction
PC
=
=
=
0126h
0126h
345Ah
TOS
TOS
PC
=
=
014332h
NEW
Stack (1 level down)
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RCALL
Relative Call
RCALL
RESET
Reset
Syntax:
n
Syntax:
RESET
None
Operands:
Operation:
-1024 ≤ n ≤ 1023
Operands:
Operation:
(PC) + 2 → TOS,
(PC) + 2 + 2n → PC
Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
reset
No
operation
No
operation
Words:
Cycles:
1
2
Example:
RESET
Q Cycle Activity:
Q1
After Instruction
Registers =
Q2
Q3
Q4
Reset Value
Reset Value
Flags*
=
Decode
Read literal
‘n’
Process
Data
Write to PC
PUSH PC
to stack
No
No
No
No
operation
operation
operation
operation
Example:
HERE
RCALL Jump
Before Instruction
PC
After Instruction
PC
TOS =
=
Address (HERE)
=
Address (Jump)
Address (HERE + 2)
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RETFIE
Return from Interrupt
RETLW
Return Literal to W
RETLW
Syntax:
RETFIE {s}
Syntax:
k
Operands:
Operation:
s ∈ [0,1]
Operands:
Operation:
0 ≤ k ≤ 255
(TOS) → PC,
k → W,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged
Description:
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers W,
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
POP PC
from stack,
write to W
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs (default).
No
operation
No
No
No
Words:
Cycles:
1
2
operation
operation
operation
Q Cycle Activity:
Q1
Example:
Q2
Q3
Q4
CALL TABLE ; W contains table
; offset value
Decode
No
operation
No
operation
POP PC
from stack
; W now has
; table value
Set GIEH or
GIEL
:
No
operation
No
operation
No
operation
No
operation
TABLE
ADDWF PCL ; W = offset
RETLW k0
RETLW k1
:
; Begin table
;
Example:
RETFIE
1
After Interrupt
:
PC
=
=
=
=
=
TOS
WS
RETLW kn
; End of table
W
BSR
STATUS
BSRS
STATUSS
1
Before Instruction
GIE/GIEH, PEIE/GIEL
W
=
07h
After Instruction
W
=
value of kn
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RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
RETURN {s}
Syntax:
RLCF f {,d {,a}}
Operands:
Operation:
s ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(TOS) → PC,
if s = 1
(WS) → W,
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
Status Affected:
Encoding:
C, N, Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’ (default).
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
POP PC
register f
C
from stack
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
RETURN
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction:
PC = TOS
Example:
RLCF
REG, 0, 0
Before Instruction
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
=
=
=
1110 0110
1100 1100
1
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RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
RLNCF f {,d {,a}}
Syntax:
RRCF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
C, N, Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
register f
register f
C
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RLNCF
REG, 1, 0
Before Instruction
REG
After Instruction
Example:
RRCF
REG, 0, 0
=
1010 1011
0101 0111
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
=
=
=
1110 0110
0111 0011
0
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RRNCF
Rotate Right f (no carry)
SETF
Set f
Syntax:
RRNCF f {,d {,a}}
Syntax:
SETF f {,a}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N, Z
Description:
The contents of the specified register
are set to FFh.
0100
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘1’, then the bank will be selected as
per the BSR value (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Words:
Cycles:
1
1
Example:
SETF
REG,1
Q Cycle Activity:
Q1
Before Instruction
REG
After Instruction
REG
=
=
5Ah
FFh
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
REG, 1, 0
Before Instruction
REG
After Instruction
REG
=
1101 0111
1110 1011
RRNCF REG, 0, 0
=
Example 2:
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
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SLEEP
Enter Sleep Mode
SUBFWB
Subtract f from W with Borrow
Syntax:
SLEEP
None
Syntax:
SUBFWB f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
00h → WDT,
0 → WDT postscaler,
1 → TO,
Operation:
(W) – (f) – (C) → dest
0 → PD
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored in
W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
Description:
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. The Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
1
1
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Q Cycle Activity:
Q1
Q2
Q3
Q4
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
No
operation
Process
Data
Go to
Sleep
Words:
Cycles:
1
1
Example:
SLEEP
Before Instruction
TO
PD
=
=
?
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
TO
PD
=
=
1 †
0
Example 1:
SUBFWB
REG, 1, 0
†
If WDT causes wake-up, this bit is cleared.
Before Instruction
REG
W
C
=
=
=
3
2
1
After Instruction
REG
W
C
=
FF
2
=
=
=
=
0
Z
0
1
N
; result is negative
Example 2:
Before Instruction
SUBFWB
REG, 0, 0
REG
W
C
=
=
=
2
5
1
After Instruction
REG
W
C
=
2
3
1
0
=
=
=
=
Z
N
0
; result is positive
Example 3:
Before Instruction
SUBFWB
REG, 1, 0
REG
W
C
=
=
=
1
2
0
After Instruction
REG
W
C
=
0
2
1
1
0
=
=
=
=
Z
; result is zero
N
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SUBLW
Subtract W from literal
SUBLW
SUBWF
Subtract W from f
Syntax:
k
Syntax:
SUBWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
k – (W) → W
N, OV, C, DC, Z
Operation:
(f) – (W) → dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
0101
11da
ffff
ffff
Description:
Subtract W from register ‘f’ (2’s
Words:
Cycles:
1
1
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’ (default).
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example 1:
SUBLW 02h
Before Instruction
W
C
=
=
01h
?
After Instruction
W
C
Z
=
01h
=
=
=
1
0
0
; result is positive
Words:
Cycles:
1
1
N
Example 2:
SUBLW 02h
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
W
C
=
=
02h
?
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
C
Z
=
00h
Example 1:
SUBWF
REG, 1, 0
=
=
=
1
1
0
; result is zero
Before Instruction
N
REG
W
C
=
=
=
3
2
?
Example 3:
SUBLW 02h
Before Instruction
After Instruction
W
C
=
=
03h
?
REG
W
C
=
1
2
1
0
0
=
=
=
=
; result is positive
After Instruction
Z
W
C
Z
=
FFh ; (2’s complement)
N
=
=
=
0
0
1
; result is negative
Example 2:
Before Instruction
SUBWF
REG, 0, 0
N
REG
W
C
=
=
=
2
2
?
After Instruction
REG
W
C
=
2
0
1
1
0
=
=
=
=
; result is zero
Z
N
Example 3:
Before Instruction
SUBWF
REG, 1, 0
REG
W
C
=
=
=
1
2
?
After Instruction
REG
W
C
=
FFh ;(2’s complement)
2
0
0
1
=
=
=
=
; result is negative
Z
N
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SUBWFB
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
SUBWFB f {,d {,a}}
Syntax:
SWAPF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) – (C) → dest
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected:
Encoding:
N, OV, C, DC, Z
0101
10da
ffff
ffff
Status Affected:
Encoding:
None
Description:
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
0011
10da
ffff
ffff
Description:
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Decode
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBWFB REG, 1, 0
Before Instruction
REG
W
C
=
=
=
19h
0Dh
1
(0001 1001)
(0000 1101)
Example:
SWAPF
REG, 1, 0
Before Instruction
REG
After Instruction
=
53h
35h
After Instruction
REG
W
C
=
0Ch
0Dh
1
(0000 1011)
(0000 1101)
=
=
=
=
REG
=
Z
0
N
0
; result is positive
Example 2:
Before Instruction
SUBWFB REG, 0, 0
REG
W
C
=
=
=
1Bh
1Ah
0
(0001 1011)
(0001 1010)
After Instruction
REG
W
C
=
1Bh
00h
1
(0001 1011)
=
=
=
=
Z
1
; result is zero
N
0
Example 3:
Before Instruction
SUBWFB REG, 1, 0
REG
W
C
=
=
=
03h
0Eh
1
(0000 0011)
(0000 1101)
After Instruction
REG
=
F5h
(1111 0100)
; [2’s comp]
W
C
Z
=
=
=
=
0Eh
0
0
1
(0000 1101)
N
; result is negative
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TBLRD
Table Read
TBLRD
Table Read (Continued)
Syntax:
TBLRD ( *; *+; *-; +*)
None
Example 1:
TBLRD *+ ;
Operands:
Operation:
Before Instruction
TABLAT
TBLPTR
MEMORY(00A356h)
=
=
=
55h
00A356h
34h
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT;
TBLPTR – No Change
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) + 1 → TBLPTR
if TBLRD *-,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) – 1 → TBLPTR
if TBLRD +*,
(TBLPTR) + 1 → TBLPTR;
(Prog Mem (TBLPTR)) → TABLAT
After Instruction
TABLAT
TBLPTR
=
=
34h
00A357h
Example 2:
TBLRD +* ;
Before Instruction
TABLAT
TBLPTR
MEMORY(01A357h)
MEMORY(01A358h)
After Instruction
=
=
=
=
AAh
01A357h
12h
34h
TABLAT
TBLPTR
=
=
34h
01A358h
Status Affected: None
Encoding:
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description:
This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: Least Significant Byte of
Program Memory Word
TBLPTR[0] = 1: Most Significant Byte of
Program Memory Word
The TBLRDinstruction can modify the value
of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
No
No operation
No
No operation
(Write
TABLAT)
operation (Read Program operation
Memory)
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TBLWT
Table Write
TBLWT
Table Write (Continued)
Syntax:
TBLWT ( *; *+; *-; +*)
None
Example 1:
TBLWT *+;
Operands:
Operation:
Before Instruction
if TBLWT*,
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A356h
(TABLAT) → Holding Register;
TBLPTR – No Change
if TBLWT*+,
(TABLAT) → Holding Register;
(TBLPTR) + 1 → TBLPTR
if TBLWT*-,
(TABLAT) → Holding Register;
(TBLPTR) – 1 → TBLPTR
if TBLWT+*,
(TBLPTR) + 1 → TBLPTR;
(TABLAT) → Holding Register
=
FFh
After Instructions (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A357h
=
55h
Example 2:
TBLWT +*;
Before Instruction
TABLAT
TBLPTR
=
=
34h
01389Ah
HOLDING REGISTER
(01389Ah)
Status Affected: None
=
=
FFh
FFh
Encoding:
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
HOLDING REGISTER
(01389Bh)
After Instruction (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
=
=
34h
01389Bh
Description:
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program Memory
(P.M.). (Refer to Section 5.0 “Memory
Organization” for additional details on
programming Flash memory.)
=
=
FFh
34h
Note:
The TBLWTinstruction cannot be used in
normal operating modes to write to
on-chip program memory. It can only be
used by PIC18F8XJ10/8XJ15 devices
with the external memory interface when
writing to an external memory device.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
The TBLWT instruction can be used to
write to on-chip program memory only in
ICSP™ mode.
TBLPTR[0] = 0: Least Significant Byte
of Program Memory
Word
For more information, refer to Section 6.4
“Writing to Program Memory Space
(PIC18F8XJ10/8XJ15 Devices Only)” and
Section 6.7 “Flash Program Operation
During Code Protection”.
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
1
2
Cycles:
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
No
Decode
operation operation operation
No
No No No
operation operation operation operation
(Read
TABLAT)
(Write to
Holding
Register)
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TSTFSZ
Test f, Skip if 0
XORLW
Exclusive OR Literal with W
XORLW
Syntax:
TSTFSZ f {,a}
Syntax:
k
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .XOR. k → W
N, Z
Operation:
skip if f = 0
Status Affected:
Encoding:
None
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Description:
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOPis executed,
making this a two-cycle instruction.
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
XORLW
0AFh
Before Instruction
W
=
B5h
1Ah
After Instruction
Words:
Cycles:
1
W
=
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
TSTFSZ CNT, 1
:
:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
PC
If CNT
PC
=
=
≠
=
00h,
Address (ZERO)
00h,
Address (NZERO)
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XORWF
Exclusive OR W with f
Syntax:
XORWF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
Encoding:
N, Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
REG, 1, 0
Before Instruction
REG
W
=
=
AFh
B5h
After Instruction
REG
W
=
=
1Ah
B5h
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A summary of the instructions in the extended instruc-
tion set is provided in Table 24-3. Detailed descriptions
are provided in Section 24.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 24-1 (page
280) apply to both the standard and extended PIC18
instruction sets.
24.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, the PIC18F87J10 family of devices also
provide an optional extension to the core CPU function-
ality. The added features include eight additional
instructions that augment indirect and indexed
addressing operations and the implementation of
Indexed Literal Offset Addressing for many of the
standard PIC18 instructions.
Note:
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is
provided as a reference for users who may
be reviewing code that has been
generated by a compiler.
The additional features of the extended instruction set
are enabled by default on unprogrammed devices.
Users must properly set or clear the XINST configura-
tion bit during programming to enable or disable these
features.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers, or use them for indexed
addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
24.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed argu-
ments, using one of the File Select Registers and some
offset to specify a source or destination register. When
an argument for an instruction serves as part of
indexed addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. The MPASM™ Assembler will
flag an error if it determines that an index or offset value
is not bracketed.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in
byte-oriented and bit-oriented instructions. This is in
addition to other changes in their syntax. For more
details, see Section 24.2.3.1 “Extended Instruction
Syntax with Standard PIC18 Commands”.
• dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• function pointer invocation
Note:
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
• software stack pointer manipulation
• manipulation of variables located in a software
stack
TABLE 24-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
ADDFSR
ADDULNK
CALLW
f, k
k
Add literal to FSR
Add literal to FSR2 and return
Call subroutine using WREG
1
2
2
2
1110 1000 ffkk kkkk
1110 1000 11kk kkkk
0000 0000 0001 0100
1110 1011 0zzz zzzz
1111 ffff ffff ffff
1110 1011 1zzz zzzz
1111 xxxx xzzz zzzz
1110 1010 kkkk kkkk
None
None
None
None
MOVSF
zs, fd Move zs (source) to 1st word
fd (destination) 2nd word
zs, zd Move zs (source) to 1st word
zd (destination) 2nd word
MOVSS
PUSHL
2
1
None
None
k
Store literal at FSR2,
decrement FSR2
SUBFSR
SUBULNK
f, k
k
Subtract literal from FSR
Subtract literal from FSR2 and
return
1
2
1110 1001 ffkk kkkk
1110 1001 11kk kkkk
None
None
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24.2.2
EXTENDED INSTRUCTION SET
ADDFSR
Add Literal to FSR
ADDULNK
Add Literal to FSR2 and Return
Syntax:
ADDFSR f, k
Syntax:
ADDULNK k
Operands:
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSR(f) + k → FSR(f)
None
Operands:
Operation:
0 ≤ k ≤ 63
FSR2 + k → FSR2,
(TOS) → PC
None
Operation:
Status Affected:
Encoding:
Status Affected:
Encoding:
1110
1000
ffkk
kkkk
1110
1000
11kk
kkkk
Description:
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Description:
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURNis then
executed by loading the PC with the
TOS.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
The instruction takes two cycles to
execute; a NOPis performed during
the second cycle.
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
This may be thought of as a special
case of the ADDFSRinstruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Example:
ADDFSR 2, 23h
Words:
1
2
Before Instruction
FSR2
After Instruction
FSR2
Cycles:
=
03FFh
0422h
Q Cycle Activity:
Q1
=
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
No
No
No
No
Operation
Operation
Operation
Operation
Example:
ADDULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
0422h
(TOS)
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
DS39663A-page 322
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PIC18F87J10 FAMILY
CALLW
Subroutine Call using WREG
MOVSF
Move Indexed to f
Syntax:
CALLW
None
Syntax:
MOVSF [z ], f
s
d
Operands:
Operation:
Operands:
0 ≤ z ≤ 127
s
0 ≤ f ≤ 4095
d
(PC + 2) → TOS,
(W) → PCL,
Operation:
((FSR2) + z ) → f
s
d
(PCLATH) → PCH,
(PCLATU) → PCU
Status Affected:
None
Encoding:
1st word (source)
2nd word (destin.)
Status Affected:
Encoding:
None
1110
1111
1011
ffff
0zzz
ffff
zzzz
ffff
s
d
0000
0000
0001
0100
Description
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOPinstruction while the
new next instruction is fetched.
Description:
The contents of the source register are
moved to destination register ‘f ’. The
d
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z ’, in the first word, to the value
s
of FSR2. The address of the destination
register is specified by the 12-bit literal
‘f ’ in the second word. Both addresses
d
can be anywhere in the 4096-byte data
space (000h to FFFh).
Unlike CALL, there is no option to
update W, STATUS or BSR.
The MOVSFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Words:
Cycles:
1
2
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
WREG
Push PC to
stack
No
operation
Words:
Cycles:
2
2
No
No
No
No
Q Cycle Activity:
Q1
operation
operation
operation
operation
Q2
Q3
Q4
Decode
Determine
source addr source addr source reg
Determine
Read
Example:
HERE
CALLW
Before Instruction
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
PC
=
address (HERE)
PCLATH =
PCLATU =
10h
00h
06h
No dummy
read
W
=
After Instruction
PC
TOS
=
=
001006h
address (HERE + 2)
Example:
MOVSF
[05h], REG2
PCLATH =
PCLATU =
10h
00h
06h
Before Instruction
W
=
FSR2
=
80h
33h
Contents
of 85h
REG2
=
=
11h
After Instruction
FSR2
=
80h
Contents
of 85h
REG2
=
=
33h
33h
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 323
PIC18F87J10 FAMILY
MOVSS
Move Indexed to Indexed
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax:
MOVSS [z ], [z ]
Syntax:
PUSHL k
s
d
Operands:
0 ≤ z ≤ 127
s
Operands:
Operation:
0 ≤ k ≤ 255
0 ≤ z ≤ 127
d
k → (FSR2),
FSR2 – 1→ FSR2
Operation:
((FSR2) + z ) → ((FSR2) + z )
s d
Status Affected:
None
Status Affected:
Encoding:
None
Encoding:
1st word (source)
2nd word (dest.)
1111
1010
kkkk
kkkk
1110
1111
1011
xxxx
1zzz
xzzz
zzzz
zzzz
s
d
Description:
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2.
FSR2 is decremented by 1 after the
operation.
Description
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
This instruction allows users to push
values onto a software stack.
7-bit literal offsets ‘z ’ or ‘z ’,
s
d
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
The MOVSSinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Q2
Q3
Q4
Decode
Read ‘k’
Process
data
Write to
destination
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a NOP.
Example:
PUSHL 08h
Before Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01ECh
00h
Words:
2
2
After Instruction
Cycles:
FSR2H:FSR2L
Memory (01ECh)
=
=
01EBh
08h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
Determine
Read
source addr source addr source reg
Decode
Determine
dest addr
Determine
dest addr
Write
to dest reg
Example:
MOVSS [05h], [06h]
Before Instruction
FSR2
=
=
=
80h
33h
11h
Contents
of 85h
Contents
of 86h
After Instruction
FSR2
=
=
=
80h
33h
33h
Contents
of 85h
Contents
of 86h
DS39663A-page 324
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SUBFSR
Subtract Literal from FSR
SUBULNK
Subtract Literal from FSR2 and Return
Syntax:
SUBFSR f, k
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSRf – k → FSRf
None
Syntax:
SUBULNK k
Operands:
Operands:
Operation:
0 ≤ k ≤ 63
FSR2 – k → FSR2
(TOS) → PC
Operation:
Status Affected:
Encoding:
Status Affected: None
1110
1001
ffkk
kkkk
Encoding:
1110
1001
11kk
kkkk
Description:
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified
by ‘f’.
Description:
The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURNis then
executed by loading the PC with the
TOS.
Words:
1
1
Cycles:
The instruction takes two cycles to
execute; a NOPis performed during the
second cycle.
Q Cycle Activity:
Q1
Q2
Q3
Q4
This may be thought of as a special case
of the SUBFSRinstruction, where f = 3
(binary ‘11’); it operates only on FSR2.
Decode
Read
register ‘f’
Process
Data
Write to
destination
Words:
1
2
Example:
SUBFSR 2, 23h
03FFh
Cycles:
Before Instruction
FSR2
After Instruction
FSR2
Q Cycle Activity:
Q1
=
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
=
03DCh
No
No
No
No
Operation
Operation
Operation
Operation
Example:
SUBULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
03DCh
(TOS)
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 325
PIC18F87J10 FAMILY
24.2.3
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
24.2.3.1
Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register argument ‘f’ in the standard byte-oriented and
bit-oriented commands is replaced with the literal offset
value ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
it must be indicated by square brackets (“[ ]”). As with
the extended instructions, the use of brackets indicates
to the compiler that the value is to be interpreted as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within the brackets, will
generate an error in the MPASM Assembler.
Note: Enabling the PIC18 instruction set exten-
sion may cause legacy applications to
behave erratically or fail entirely.
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing (Section 5.6.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses embed-
ded in opcodes are treated as literal memory locations:
either as a location in the Access Bank (a = 0) or in a
GPR bank designated by the BSR (a = 1). When the
extended instruction set is enabled and a = 0, however,
a file register argument of 5Fh or less is interpreted as
an offset from the pointer value in FSR2 and not as a
literal address. For practical purposes, this means that
all instructions that use the Access RAM bit as an
argument – that is, all byte-oriented and bit-oriented
instructions, or almost half of the core PIC18 instruc-
tions – may behave differently when the extended
instruction set is enabled.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled), when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument ‘d’ functions as before.
In the latest versions of the MPASM Assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
When the content of FSR2 is 00h, the boundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating
backward-compatible code. If this technique is used, it
may be necessary to save the value of FSR2 and
restore it when moving back and forth between C and
assembly routines in order to preserve the Stack
Pointer. Users must also keep in mind the syntax
requirements of the extended instruction set (see
Section 24.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”).
24.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruc-
tion set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Although the Indexed Literal Offset mode can be very
useful for dynamic stack and pointer manipulation, it
can also be very annoying if a simple arithmetic opera-
tion is carried out on the wrong register. Users who are
accustomed to the PIC18 programming must keep in
mind that, when the extended instruction set is
enabled, register addresses of 5Fh or less are used for
Indexed Literal Offset Addressing.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
mode are provided on the following page to show how
execution is affected. The operand conditions shown in
the examples are applicable to all instructions of these
types.
When porting an application to the PIC18F87J10
family, it is very important to consider the type of code.
A large, re-entrant application that is written in C and
would benefit from efficient compilation will do well
when using the instruction set extensions. Legacy
applications that heavily use the Access Bank will most
likely not benefit from using the extended instruction
set.
DS39663A-page 326
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PIC18F87J10 FAMILY
ADD W to Indexed
(Indexed Literal Offset mode)
Bit Set Indexed
BSF
ADDWF
(Indexed Literal Offset mode)
Syntax:
ADDWF
[k] {,d}
Syntax:
BSF [k], b
Operands:
0 ≤ k ≤ 95
d ∈ [0,1]
Operands:
0 ≤ f ≤ 95
0 ≤ b ≤ 7
Operation:
(W) + ((FSR2) + k) → dest
Operation:
1 → ((FSR2) + k)<b>
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
None
0010
01d0
kkkk
kkkk
1000
bbb0
kkkk
kkkk
Description:
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
Description:
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
Words:
Cycles:
1
1
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’ (default).
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Example:
BSF
[FLAG_OFST], 7
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write to
destination
Before Instruction
FLAG_OFST
FSR2
=
=
0Ah
0A00h
Contents
of 0A0Ah
After Instruction
Example:
ADDWF
[OFST],0
=
55h
D5h
Before Instruction
W
OFST
FSR2
=
=
=
17h
Contents
of 0A0Ah
2Ch
=
0A00h
Contents
of 0A2Ch
=
20h
After Instruction
Set Indexed
(Indexed Literal Offset mode)
SETF
W
=
=
37h
20h
Contents
of 0A2Ch
Syntax:
SETF [k]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 95
FFh → ((FSR2) + k)
None
0110
1000
kkkk
kkkk
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write
register
Example:
SETF
[OFST]
2Ch
Before Instruction
OFST
FSR2
=
=
0A00h
Contents
of 0A2Ch
=
00h
After Instruction
Contents
of 0A2Ch
=
FFh
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 327
PIC18F87J10 FAMILY
24.2.5
SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set for the PIC18F87J10 family. This includes the
MPLAB C18 C Compiler, MPASM assembly language
and MPLAB Integrated Development Environment
(IDE).
When selecting
a
target device for software
development, MPLAB IDE will automatically set default
configuration bits for that device. The default setting for
the XINST configuration is ‘0’, disabling the extended
instruction set and Indexed Literal Offset Addressing.
For proper execution of applications developed to take
advantage of the extended instruction set, XINST must
be set during programming.
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
• A menu option or dialog box within the
environment that allows the user to configure the
language tool and its settings for the project
• A command line option
• A directive in the source code
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompany-
ing their development systems for the appropriate
information.
DS39663A-page 328
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25.1 MPLAB Integrated Development
Environment Software
25.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• An interface to debugging tools
- simulator
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
• Customizable data windows with direct edit of
contents
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
• Emulators
• High-level source code debugging
• Mouse over variable inspection
• Extensive on-line help
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
- MPLAB ICD 2
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM Demonstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
• Debug using:
- source files (assembly or C)
- mixed assembly and C
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increasing flexibility
and power.
25.2 MPASM Assembler
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
®
- KEELOQ Evaluation and Programming Tools
- PICDEM MSC
- microID® Developer Kits
- CAN
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol ref-
erence, absolute LST files that contain source lines and
generated machine code and COFF files for
debugging.
- PowerSmart® Developer Kits
- Analog
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User defined macros to streamline assembly code
• Conditional assembly for multi-purpose source
files
• Directives that allow complete control over the
assembly process
2005 Microchip Technology Inc.
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DS39663A-page 329
PIC18F87J10 FAMILY
25.3 MPLAB C17 and MPLAB C18
C Compilers
25.6 MPLAB ASM30 Assembler, Linker
and Librarian
The MPLAB C17 and MPLAB C18 Code Development
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
Systems are complete ANSI
C
compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
25.4 MPLINK Object Linker/
MPLIB Object Librarian
• Rich directive set
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
• Flexible macro language
• MPLAB IDE compatibility
25.7 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The execu-
tion can be performed in Single-Step, Execute Until
Break or Trace mode.
The MPLIB object librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
25.5 MPLAB C30 C Compiler
25.8 MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command
line options and language extensions to take full
advantage of the dsPIC30F device hardware capabili-
ties and afford fine control of the compiler code
generator.
The MPLAB SIM30 software simulator allows code
development in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high-speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been vali-
dated and conform to the ANSI C library standard. The
library includes functions for string manipulation,
dynamic memory allocation, data conversion, time-
keeping and math functions (trigonometric, exponential
and hyperbolic). The compiler provides symbolic
information for high-level source debugging with the
MPLAB IDE.
DS39663A-page 330
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25.9 MPLAB ICE 2000
High-Performance Universal
25.11 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the Flash devices. This feature, along with
In-Circuit Emulator
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM
)
protocol, offers cost effective in-circuit Flash debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
25.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
25.10 MPLAB ICE 4000
High-Performance Universal
In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for high-
end PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
25.13 MPLAB PM3 Device Programmer
The MPLAB PM3 is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
a large LCD display (128 x 64) for menus and error
messages and a modular detachable socket assembly
to support various package types. The ICSP™ cable
assembly is included as a standard item. In Stand-
Alone mode, the MPLAB PM3 device programmer can
read, verify and program PICmicro devices without a
PC connection. It can also set code protection in this
mode. MPLAB PM3 connects to the host PC via an RS-
232 or USB cable. MPLAB PM3 has high-speed com-
munications and optimized algorithms for quick pro-
gramming of large memory devices and incorporates
an SD/MMC card for file storage and secure data appli-
cations.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, up to 2 Mb of emulation memory and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 331
PIC18F87J10 FAMILY
25.14 PICSTART Plus Development
Programmer
25.17 PICDEM 2 Plus
Demonstration Board
The PICSTART Plus development programmer is an
easy-to-use, low-cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
The PICDEM 2 Plus demonstration board supports
many 18, 28 and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the neces-
sary hardware and software is included to run the dem-
onstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device program-
mer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display, a piezo speaker, an on-board temperature
sensor, four LEDs and sample PIC18F452 and
PIC16F877 Flash microcontrollers.
25.15 PICDEM 1 PICmicro
Demonstration Board
The PICDEM 1 demonstration board demonstrates the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provided with the PICDEM 1 demonstration board can
be programmed with a PRO MATE II device program-
mer or a PICSTART Plus development programmer.
The PICDEM 1 demonstration board can be connected
to the MPLAB ICE in-circuit emulator for testing. A
prototype area extends the circuitry for additional appli-
cation components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
25.18 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
25.19 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capa-
bilities of the 8, 14 and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320
family of microcontrollers. PICDEM 4 is intended to
showcase the many features of these low pin count
parts, including LIN and Motor Control using ECCP.
Special provisions are made for low-power operation
with the supercapacitor circuit and jumpers allow on-
board hardware to be disabled to eliminate current
draw in this mode. Included on the demo board are pro-
visions for Crystal, RC or Canned Oscillator modes, a
five volt regulator for use with a nine volt wall adapter
or battery, DB-9 RS-232 interface, ICD connector for
programming via ICSP and development with MPLAB
ICD 2, 2 x 16 liquid crystal display, PCB footprints for
H-Bridge motor driver, LIN transceiver and EEPROM.
Also included are: header for expansion, eight LEDs,
four potentiometers, three push buttons and a proto-
typing area. Included with the kit is a PIC16F627A and
a PIC18F1320. Tutorial firmware is included along
with the User’s Guide.
25.16 PICDEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface con-
nector, an Ethernet interface, RS-232 interface and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jeremy Bentham
DS39663A-page 332
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
25.20 PICDEM 17 Demonstration Board
25.24 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A pro-
grammed sample is included. The PRO MATE II device
programmer, or the PICSTART Plus development pro-
grammer, can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous prototype area is available for user hardware
expansion.
The PICDEM USB Demonstration Board shows off the
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
25.25 Evaluation and
Programming Tools
In addition to the PICDEM series of circuits, Microchip
has a line of evaluation kits and demonstration software
for these products.
• KEELOQ evaluation and programming tools for
Microchip’s HCS Secure Data Products
25.21 PICDEM 18R PIC18C601/801
Demonstration Board
• CAN developers kit for automotive network
applications
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/Demultiplexed and 16-bit
Memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
• Analog design boards and filter design software
• PowerSmart battery charging evaluation/
calibration kits
• IrDA® development kit
• microID development and rfLabTM development
software
• SEEVAL® designer kit for memory evaluation and
endurance calculations
25.22 PICDEM LIN PIC16C43X
Demonstration Board
• PICDEM MSC demo boards for Switching mode
power supply, high-power IR driver, delta sigma
ADC and flow rate sensor
The powerful LIN hardware and software kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
Check the Microchip web page and the latest Product
Selector Guide for the complete list of demonstration
and evaluation kits.
on-board LIN transceivers.
A PIC16F874 Flash
microcontroller serves as the master. All three micro-
controllers are programmed with firmware to provide
LIN bus communication.
25.23 PICkitTM 1 Flash Starter Kit
A complete “development system in a box”, the PICkit™
Flash Starter Kit includes a convenient multi-section
board for programming, evaluation and development of
8/14-pin Flash PIC® microcontrollers. Powered via USB,
the board operates under a simple Windows GUI. The
PICkit 1 Starter Kit includes the User’s Guide (on CD
ROM), PICkit 1 tutorial software and code for various
applications. Also included are MPLAB® IDE (Integrated
Development Environment) software, software and
hardware “Tips 'n Tricks for 8-pin Flash PIC®
Microcontrollers” Handbook and a USB interface cable.
Supports all current 8/14-pin Flash PIC microcontrollers,
as well as many future planned devices.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 333
PIC18F87J10 FAMILY
NOTES:
DS39663A-page 334
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
26.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any digital-only I/O pin with respect to VSS (except VDD and MCLR) ........................................ -0.3V to 5.5V
Voltage on any combined digital and analog pin with respect to VSS (except VDD and MCLR)...... -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS................................................................................................... -0.3V to 2.75V
Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 3.6V
Voltage on MCLR with respect to VSS (Note 2) ............................................................................................... 0V to 3.6V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA
Maximum output current sunk by PORTB and PORTC I/O pins.............................................................................25 mA
Maximum output current sunk by PORTD, PORTE and PORTJ I/O pins.................................................................8 mA
Maximum output current sunk by PORTA, PORTF, PORTG and PORTH I/O pins ..................................................2 mA
Maximum output current sourced by PORTB and PORTC I/O pins .......................................................................25 mA
Maximum output current sourced by PORTD, PORTE and PORTJ I/O pins............................................................8 mA
Maximum output current sourced by PORTA, PORTF, PORTG and PORTH I/O pins .............................................2 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin, rather than
pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 335
PIC18F87J10 FAMILY
FIGURE 26-1:
PIC18F87J10 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
4.0V
3.5V
3.0V
2.5V
2.0V
3.6V
PIC18F6XJ10/6XJ15/8XJ10/8XJ15
2.15V
40 MHz
4 MHz
Frequency
DS39663A-page 336
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
26.1 DC Characteristics: Supply Voltage, PIC18F87J10 Family (Industrial)
PIC18F87J10 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
Symbol
No.
Characteristic
Supply Voltage
Min
Typ Max Units
Conditions
D001
VDD
VDDCORE
—
—
3.6
V
D001B
VDDCORE External Supply for
1.8
2.75
V
V
V
Microcontroller Core
D002
D003
VDR
RAM Data Retention
Voltage(1)
1.5
—
—
—
—
VPOR
VDD Start Voltage
to ensure internal
0.7
See Section 4.3 “Power-on Reset
(POR)” for details
Power-on Reset signal
D004
SVDD
VBOR
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
TBD
—
—
—
V/ms See Section 4.3 “Power-on Reset
(POR)” for details
D005A
Brown-out Reset Voltage
TBD
V
On-chip voltage regulator enabled.
See Section 4.4 “Brown-out Reset
(BOR)” for details.
Legend: TBD = To Be Determined
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 337
PIC18F87J10 FAMILY
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J10 Family (Industrial)
PIC18F87J10 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Power-Down Current (IPD)
Typ Max Units
Conditions
(1)
All devices TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V,
(Sleep mode)
TBD
TBD
All devices TBD
TBD
VDD = 2.5V,
(Sleep mode)
TBD
All devices TBD
TBD
VDD = 3.3V,
(Sleep mode)
TBD
Legend:
TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39663A-page 338
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J10 Family (Industrial) (Continued)
PIC18F87J10 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)
Typ Max Units
Conditions
(2,3)
All devices TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
TBD
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V
VDD = 2.5V
VDD = 3.3V
VDD = 2.0V
VDD = 2.5V
VDD = 3.3V
TBD
All devices TBD
FOSC = 31 kHz
(RC_RUN mode,
Internal oscillator source)
TBD
TBD
All devices TBD
TBD
TBD
All devices TBD
TBD
TBD
All devices TBD
TBD
FOSC = 31 kHz
(RC_IDLE mode,
Internal oscillator source)
TBD
All devices TBD
TBD
TBD
Legend:
TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 339
PIC18F87J10 FAMILY
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J10 Family (Industrial) (Continued)
PIC18F87J10 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Param
No.
Device
Supply Current (IDD)
Typ
Max Units
Conditions
(2,3)
All devices TBD
TBD
TBD
µA
µA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
TBD
VDD = 2.0V
VDD = 2.5V
VDD = 3.3V
VDD = 2.0V
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µA
µA
All devices TBD
FOSC = 1 MHZ
(PRI_RUN mode,
EC oscillator)
TBD
µA
TBD
µA
All devices TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
TBD
TBD
All devices TBD
TBD
TBD
All devices TBD
FOSC = 4 MHz
(PRI_RUN mode,
EC oscillator)
TBD
TBD
All devices TBD
TBD
TBD
All devices TBD
TBD
FOSC = 40 MHZ
(PRI_RUN mode,
EC oscillator)
TBD
All devices TBD
TBD
TBD
Legend:
TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39663A-page 340
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J10 Family (Industrial) (Continued)
PIC18F87J10 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)
Typ Max Units
Conditions
(2)
All devices TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
FOSC = 4 MHZ.
16 MHz internal
(PRI_RUN HSPLL mode)
TBD
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
TBD
All devices TBD
FOSC = 4 MHZ,
16 MHz internal
(PRI_RUN HSPLL mode)
TBD
TBD
All devices TBD
TBD
FOSC = 10 MHZ,
40 MHz internal
(PRI_RUN HSPLL mode)
TBD
All devices TBD
TBD
FOSC = 10 MHZ,
40 MHz internal
(PRI_RUN HSPLL mode)
TBD
Legend:
TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 341
PIC18F87J10 FAMILY
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J10 Family (Industrial) (Continued)
PIC18F87J10 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Param
No.
Device
Supply Current (IDD)
Typ
Max Units
Conditions
(2,3)
All devices TBD
TBD
TBD
µA
µA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
TBD
VDD = 2.0V
VDD = 2.5V
VDD = 3.3V
VDD = 2.0V
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
All devices TBD
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
TBD
TBD
All devices TBD
TBD
TBD
All devices TBD
TBD
TBD
All devices TBD
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
TBD
TBD
All devices TBD
TBD
TBD
All devices TBD
TBD
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
TBD
All devices TBD
TBD
TBD
Legend:
TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39663A-page 342
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J10 Family (Industrial) (Continued)
PIC18F87J10 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)
Typ Max Units
Conditions
(2,3)
All devices TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-10°C
TBD
+25°C
+70°C
-10°C
+25°C
+70°C
-10°C
+25°C
+70°C
-10°C
+25°C
+70°C
-10°C
+25°C
+70°C
-10°C
+25°C
+70°C
VDD = 2.0V
VDD = 2.5V
VDD = 3.3V
VDD = 2.0V
VDD = 2.5V
VDD = 3.3V
TBD
All devices TBD
(4)
FOSC = 32 kHz
TBD
(SEC_RUN mode,
Timer1 as clock)
TBD
All devices TBD
TBD
TBD
All devices TBD
TBD
TBD
All devices TBD
TBD
(4)
FOSC = 32 kHz
(SEC_IDLE mode,
Timer1 as clock)
TBD
All devices TBD
TBD
TBD
Legend:
TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 343
PIC18F87J10 FAMILY
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J10 Family (Industrial) (Continued)
PIC18F87J10 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Param
No.
Device
Typ
Max Units
Conditions
Module Differential Currents (∆IWDT, ∆IOSCB, ∆IAD)
D022
Watchdog Timer TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
+25°C
(∆IWDT)
VDD = 2.0V
VDD = 2.5V
VDD = 3.3V
VDD = 2.0V
VDD = 2.5V
VDD = 3.3V
TBD
TBD
+85°C
TBD
-40°C
TBD
+25°C
TBD
+85°C
TBD
-40°C
TBD
+25°C
TBD
+85°C
D025
(∆IOSCB)
Timer1 Oscillator TBD
-40°C
(3)
(3)
(3)
32 kHz on Timer1
32 kHz on Timer1
32 kHz on Timer1
TBD
+25°C
TBD
+85°C
TBD
-40°C
TBD
+25°C
TBD
+85°C
TBD
-40°C
TBD
+25°C
TBD
+85°C
D026
(∆IAD)
A/D Converter TBD
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VDD = 2.0V
VDD = 2.5V
VDD = 3.3V
A/D on, not converting
TBD
TBD
Legend:
TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39663A-page 344
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
26.3 DC Characteristics: PIC18F87J10 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VIL
VIH
IIL
Input Low Voltage
I/O ports:
with TTL buffer
D030
D030A
D031
D032
D033
D033A
VSS
—
0.15 VDD
0.8
V
V
V
V
V
V
VDD < 3.3V
3.3V ≤ VDD ≤ 3.6V
with Schmitt Trigger buffer
MCLR
VSS
VSS
VSS
VSS
0.2 VDD
0.2 VDD
0.3 VDD
0.2 VDD
OSC1
OSC1
HS, HSPLL modes
EC modes(1)
D034
T13CKI
VSS
0.3 VDD
V
Input High Voltage
I/O ports:
D040
D040A
D041
D042
D043
D043A
with TTL buffer
0.25 VDD + 0.8V
2.0
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
VDD < 3.3V
3.3V ≤ VDD ≤ 3.6V
with Schmitt Trigger buffer
0.8 VDD
0.8 VDD
0.7 VDD
0.8 VDD
MCLR
OSC1
OSC1
HS, HSPLL modes
EC mode
D044
T13CKI
Input Leakage Current(2,3)
1.6
VDD
V
D060
I/O ports
—
1
µA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061
D063
MCLR
—
—
5
5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD
OSC1
IPU
Weak Pull-up Current
PORTB weak pull-up current
D070
IPURB
50
400
µA VDD = 3.3V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 345
PIC18F87J10 FAMILY
26.3 DC Characteristics: PIC18F87J10 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VOL
VOH
Output Low Voltage
I/O ports
D080
D083
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 3.3V,
-40°C to +85°C
OSC2/CLKO
(EC, ECIO modes)
Output High Voltage(3)
IOL = 1.6 mA, VDD = 3.3V,
-40°C to +85°C
D090
D092
I/O ports
VDD – 0.7
VDD – 0.7
—
—
V
V
IOH = -3.0 mA, VDD = 3.3V,
-40°C to +85°C
OSC2/CLKO
IOH = -1.3 mA, VDD = 3.3V,
(RC, RCIO, EC, ECIO modes)
-40°C to +85°C
Capacitive Loading Specs
on Output Pins
D100(4)
—
COSC2 OSC2 pin
15
pF In HS mode when
external clock is used to
drive OSC1
D101
D102
CIO
CB
All I/O pins and OSC2
(in RC mode)
—
—
50
pF To meet the AC Timing
Specifications
pF I2C™ Specification
SCLx, SDAx
400
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
DS39663A-page 346
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Program Flash Memory
Cell Endurance
D130
D131
EP
100
1K
—
—
E/W -40°C to +85°C
VPR
VDD for Read
VMIN
3.6
V
VMIN = Minimum operating
voltage
D132B VPEW VDD for Self-Timed Write(1)
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D133A TIW
D134 TRETD Characteristic Retention
Self-Timed Write Cycle Time(1)
—
10
20
—
—
ms
10
Year Provided no other
specifications are violated
D135
IDDP
Supply Current during
Programming
—
10
—
mA
†
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications apply only to devices in programming modes.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 347
PIC18F87J10 FAMILY
TABLE 26-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Input Offset Voltage
Min
Typ
Max
Units
Comments
D300
VIOFF
—
0
± 5.0
—
± 10
VDD – 1.5
—
mV
V
D301
D302
300
VICM
Input Common Mode Voltage*
Common Mode Rejection Ratio*
Response Time(1)*
CMRR
TRESP
55
—
—
—
dB
ns
µs
150
—
400
301
TMC2OV Comparator Mode Change to
Output Valid*
10
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 26-3: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Resolution
Min
Typ
Max
Units
Comments
D310
VRES
VDD/24
—
—
—
2k
—
VDD/32
1/2
LSb
LSb
Ω
D311
D312
310
VRAA
VRUR
TSET
Absolute Accuracy
Unit Resistor Value (R)
Settling Time(1)
—
—
—
10
µs
Note 1: Settling time measured while CVRR = 1and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.
TABLE 26-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
Comments
VRGOUT Regulator Output Voltage
—
1
2.5
10
—
—
V
CEFC
External Filter Capacitor
Value
µF
Capacitor must be low
series resistance
*
These parameters are characterized but not tested. Parameter numbers not yet assigned for these
specifications.
DS39663A-page 348
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
26.4 AC (Timing) Characteristics
26.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKO
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T13CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
Fall
P
R
V
Z
Period
H
High
Rise
I
Invalid (High-impedance)
Low
Valid
L
High-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
Hold
SU
Setup
ST
DAT
STA
DATA input hold
Start condition
STO
Stop condition
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 349
PIC18F87J10 FAMILY
26.4.2
TIMING CONDITIONS
The temperature and voltages specified in Table 26-5
apply to all timing specifications unless otherwise
noted. Figure 26-2 specifies the load conditions for the
timing specifications.
TABLE 26-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
Operating voltage VDD range as described in DC spec Section 26.1 and
Section 26.3.
-40°C ≤ TA ≤ +85°C for industrial
AC CHARACTERISTICS
FIGURE 26-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 Load Condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports
VSS
DS39663A-page 350
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
26.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 26-3:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
1
Q2
Q3
Q4
Q1
OSC1
CLKO
3
4
3
4
2
TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
1
FOSC
External CLKI Frequency(1)
Oscillator Frequency(1)
External CLKI Period(1)
DC
DC
25
40
40
MHz HS Oscillator mode
MHz HS Oscillator mode
TOSC
—
ns
ns
HS Oscillator mode
HS Oscillator mode
Oscillator Period(1)
25
250
2
3
TCY
Instruction Cycle Time(1)
100
10
—
—
ns
ns
TCY = 4/FOSC, Industrial
HS Oscillator mode
TOSL,
TOSH
External Clock in (OSC1)
High or Low Time
4
TOSR,
TOSF
External Clock in (OSC1)
Rise or Fall Time
—
7.5
ns
HS Oscillator mode
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 351
PIC18F87J10 FAMILY
TABLE 26-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5V TO 3.6V)
Param
Sym
Characteristic
Min
Typ†
Max
Units Conditions
No.
F10
FOSC Oscillator Frequency Range
4
—
—
—
—
10
40
2
MHz HS mode only
F11
F12
F13
FSYS On-Chip VCO System Frequency
16
—
-2
MHz HS mode only
trc
PLL Start-up Time (Lock Time)
ms
%
∆CLK CLKO Stability (Jitter)
+2
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 26-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY
PIC18F87J10 FAMILY (INDUSTRIAL)
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
INTRC Accuracy @ Freq = 31 kHz(1) 26.562
—
35.938
kHz
-40°C to +85°C, VDD = 2.0-3.3V
Note 1: INTRC frequency after calibration. Change of INTRC frequency as VDD changes.
DS39663A-page 352
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
FIGURE 26-4:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
13
14
12
19
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Refer to Figure 26-2 for load conditions.
Note:
TABLE 26-9: CLKO AND I/O TIMING REQUIREMENTS
Param
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
10
TOSH2CKL OSC1 ↑ to CLKO ↓
TOSH2CKH OSC1 ↑ to CLKO ↑
—
TBD
TBD
TBD
TBD
—
TBD
TBD
TBD
TBD
ns
ns
ns
ns
11
—
12
13
14
15
16
17
18
18A
19
TCKR
TCKF
CLKO Rise Time
CLKO Fall Time
—
—
TCKL2IOV CLKO ↓ to Port Out Valid
TIOV2CKH Port In Valid before CLKO ↑
TCKH2IOI Port In Hold after CLKO ↑
TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
0.5 TCY + 20 ns
0.25 TCY + 25
—
—
—
ns
0
—
—
ns
50
150
—
ns
TOSH2IOI OSC1 ↑ (Q2 cycle) to Port Input Invalid
100
200
0
—
ns
(I/O in hold time)
—
—
ns VDD = 2.0V
ns
TIOV2OSH Port Input Valid to OSC1 ↑
—
—
(I/O in setup time)
20
TIOR
TIOF
Port Output Rise Time
—
—
10
—
10
—
—
—
25
60
25
60
—
—
ns
20A
21
ns VDD = 2.0V
Port Output Fall Time
—
ns
21A
22†
23†
—
ns VDD = 2.0V
TINP
INT pin High or Low Time
TCY
TCY
ns
ns
TRBP
RB7:RB4 Change INT High or Low Time
Legend: TBD = To Be Determined
These parameters are asynchronous events not related to any internal clock edges.
†
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 353
PIC18F87J10 FAMILY
FIGURE 26-5:
PROGRAM MEMORY READ TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
A<19:16>
BA0
Address
Address
Address
Data from External
Address
AD<15:0>
163
162
150
151
160
155
161
166
167
168
ALE
CE
164
169
171
171A
OE
165
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated.
TABLE 26-10: CLKO AND I/O TIMING REQUIREMENTS
Param.
Symbol
Characteristics
Min
Typ
Max
Units
No
150
TadV2alL Address Out Valid to ALE ↓
0.25 TCY – 10
—
—
ns
(address setup time)
151
TalL2adl
ALE ↓ to Address Out Invalid
(address hold time)
5
—
—
ns
155
160
161
162
163
164
165
166
167
168
169
171
171A
TalL2oeL ALE ↓ to OE ↓
10
0.125 TCY
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TadZ2oeL AD high-Z to OE ↓ (bus release to OE)
ToeH2adD OE ↑ to AD Driven
0
—
—
—
0.125 TCY – 5
—
TadV2oeH LS Data Valid before OE ↑ (data setup time)
ToeH2adl OE ↑ to Data In Invalid (data hold time)
20
—
—
0
—
—
—
TalH2alL
ALE Pulse Width
TCY
0.5 TCY
0.25 TCY
—
—
ToeL2oeH OE Pulse Width
0.5 TCY – 5
—
—
TalH2alH ALE ↑ to ALE ↑ (cycle time)
—
Tacc
Address Valid to Data Valid
0.75 TCY – 25
—
0.5 TCY – 25
0.625 TCY + 10
—
Toe
OE ↓ to Data Valid
—
TalL2oeH ALE ↓ to OE ↑
TalH2csL Chip Enable Active to ALE ↓
TubL2oeH AD Valid to Chip Enable Active
0.625 TCY – 10
0.25 TCY – 20
—
—
—
—
10
DS39663A-page 354
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
FIGURE 26-6:
PROGRAM MEMORY WRITE TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
A<19:16>
BA0
Address
Address
166
Data
Address
Address
AD<15:0>
153
150
151
156
ALE
CE
171
171A
154
WRH or
WRL
157A
157
UB or
LB
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated.
TABLE 26-11: PROGRAM MEMORY WRITE TIMING REQUIREMENTS
Param.
Symbol
Characteristics
Min
Typ
Max
Units
No
150
TadV2alL Address Out Valid to ALE ↓ (address setup time)
TalL2adl ALE ↓ to Address Out Invalid (address hold time)
TwrH2adl WRn ↑ to Data Out Invalid (data hold time)
TwrL WRn Pulse Width
0.25 TCY – 10
5
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
151
153
154
156
157
5
—
0.5 TCY – 5
0.5 TCY – 10
0.25 TCY
0.5 TCY
—
TadV2wrH Data Valid before WRn ↑ (data setup time)
TbsV2wrL Byte Select Valid before WRn ↓
—
(byte select setup time)
157A
166
TwrH2bsI WRn ↑ to Byte Select Invalid (byte select hold time)
TalH2alH ALE ↑ to ALE ↑ (cycle time)
0.125 TCY – 5
—
0.25 TCY
—
—
—
—
10
ns
ns
ns
ns
—
0.25 TCY – 20
—
171
TalH2csL Chip Enable Active to ALE ↓
TubL2oeH AD Valid to Chip Enable Active
171A
—
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 355
PIC18F87J10 FAMILY
FIGURE 26-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 26-2 for load conditions.
FIGURE 26-8:
BROWN-OUT RESET TIMING
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
TABLE 26-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCL
TWDT
MCLR Pulse Width (low)
2
—
—
µs
31
Watchdog Timer Time-out Period
(no postscaler)
3.4
4.0
4.6
ms
32
33
34
TOST
Oscillation Start-up Timer Period
1024 TOSC
55.6
—
65.5
2
1024 TOSC
—
ms
µs
TOSC = OSC1 period
TPWRT Power-up Timer Period
75
—
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
38
39
TCSD
CPU Start-up Time
—
—
200
1
—
—
µs
µs
TIOBST Time for INTOSC to Stabilize
DS39663A-page 356
Advance Information
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PIC18F87J10 FAMILY
FIGURE 26-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T13CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 26-2 for load conditions.
TABLE 26-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
40
TT0H
T0CKI High Pulse Width
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
0.5 TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
0.5 TCY + 20
10
TCY + 10
Greater of:
20 ns or
ns N = prescale
value
(TCY + 40)/N
(1, 2, 4,..., 256)
45
46
47
TT1H
TT1L
TT1P
T13CKI High Synchronous, no prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Time
Synchronous, with prescaler
10
Asynchronous
30
0.5 TCY + 5
10
T13CKI Low Synchronous, no prescaler
Time
Synchronous, with prescaler
Asynchronous
30
T13CKI Input Synchronous
Period
Greater of:
20 ns or
ns N = prescale
value
(TCY + 40)/N
(1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
FT1
T13CKI Oscillator Input Frequency Range
48
TCKE2TMRI Delay from External T13CKI Clock Edge to
Timer Increment
2 TOSC
7 TOSC
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 357
PIC18F87J10 FAMILY
FIGURE 26-10:
CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULES)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Refer to Figure 26-2 for load conditions.
Note:
TABLE 26-14: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULES)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
50
TCCL
CCPx Input Low No prescaler
0.5 TCY + 20
—
—
—
—
—
ns
ns
ns
ns
ns
Time
With prescaler
10
0.5 TCY + 20
10
51
52
TCCH
TCCP
CCPx Input
High Time
No prescaler
With prescaler
CCPx Input Period
3 TCY + 40
N
N = prescale
value (1, 4 or 16)
53
54
TCCR
TCCF
CCPx Output Fall Time
CCPx Output Fall Time
—
—
25
25
ns
ns
TABLE 26-15: PARALLEL SLAVE PORT REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
62
TdtV2wrH
TwrH2dtI
TrdL2dtV
TrdH2dtI
TibfINH
Data In Valid before WR ↑ or CS ↑ (setup time)
WR ↑ or CS ↑ to Data–In Invalid (hold time)
RD ↓ and CS ↓ to Data–Out Valid
20
20
—
10
—
—
—
ns
ns
ns
ns
63
64
65
66
80
RD ↑ or CS ↓ to Data–Out Invalid
30
Inhibit of the IBF Flag bit being Cleared from
3 TCY
WR ↑ or CS ↑
DS39663A-page 358
Advance Information
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FIGURE 26-11:
EXAMPLE SPI™ MASTER MODE TIMING (CKE = 0)
SSx
70
SCKx
(CKP = 0)
71
72
78
79
79
SCKx
(CKP = 1)
78
80
MSb
bit 6 - - - - - - 1
LSb
SDOx
SDIx
75, 76
MSb In
74
bit 6 - - - - 1
LSb In
73
Note: Refer to Figure 26-2 for load conditions.
TABLE 26-16: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
SCKx Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCKx Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
ns
75
76
78
79
80
TDOR
TDOF
TSCR
TSCF
SDOx Data Output Rise Time
—
—
—
—
—
25
25
25
25
50
ns
ns
ns
ns
ns
SDOx Data Output Fall Time
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 359
PIC18F87J10 FAMILY
FIGURE 26-12:
EXAMPLE SPI™ MASTER MODE TIMING (CKE = 1)
SSx
81
SCKx
(CKP = 0)
71
72
79
78
73
SCKx
(CKP = 1)
80
LSb
MSb
bit 6 - - - - - - 1
SDOx
SDIx
75, 76
MSb In
74
bit 6 - - - - 1
LSb In
Note: Refer to Figure 26-2 for load conditions.
TABLE 26-17: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
TSCH
Characteristic
Min
Max Units Conditions
71
SCKx Input High Time
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
(Slave mode)
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCKx Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
ns
75
76
78
79
80
TDOR
TDOF
TSCR
TSCF
SDOx Data Output Rise Time
—
—
—
—
—
25
25
25
25
50
ns
ns
ns
ns
ns
SDOx Data Output Fall Time
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
81
TDOV2SCH, SDOx Data Output Setup to SCKx Edge
TDOV2SCL
TCY
—
ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39663A-page 360
Advance Information
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PIC18F87J10 FAMILY
FIGURE 26-13:
EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 0)
SSx
70
SCKx
(CKP = 0)
83
71
72
78
79
79
78
SCKx
(CKP = 1)
80
MSb
LSb
SDOx
SDIx
bit 6 - - - - - - 1
75, 76
77
MSb In
74
bit 6 - - - - 1
LSb In
73
Note:
Refer to Figure 26-2 for load conditions.
TABLE 26-18: EXAMPLE SPI™ MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
SCKx Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCKx Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
ns
75
76
77
78
79
80
TDOR
TDOF
SDOx Data Output Rise Time
SDOx Data Output Fall Time
—
—
10
—
—
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
TSSH2DOZ SSx ↑ to SDOx Output High-impedance
TSCR
TSCF
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
83
TSCH2SSH, SSx ↑ after SCKx Edge
TSCL2SSH
1.5 TCY + 40
—
ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 361
PIC18F87J10 FAMILY
FIGURE 26-14:
EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 1)
82
SSx
70
SCKx
83
(CKP = 0)
71
72
SCKx
(CKP = 1)
80
MSb
bit 6 - - - - - - 1
LSb
SDOx
SDIx
75, 76
77
MSb In
74
bit 6 - - - - 1
LSb In
Note: Refer to Figure 26-2 for load conditions.
TABLE 26-19: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
TSCL
TB2B
SCKx Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
SCKx Input Low Time
(Slave mode)
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
75
76
77
78
79
80
TDOR
TDOF
SDOx Data Output Rise Time
SDOx Data Output Fall Time
—
—
10
—
—
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
TSSH2DOZ SSx ↑ to SDOx Output High-Impedance
TSCR
TSCF
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
82
83
TSSL2DOV SDOx Data Output Valid after SSx ↓ Edge
—
50
—
ns
ns
TSCH2SSH, SSx ↑ after SCKx Edge
TSCL2SSH
1.5 TCY + 40
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39663A-page 362
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
FIGURE 26-15:
SCLx
I2C™ BUS START/STOP BITS TIMING
91
93
90
92
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 26-2 for load conditions.
TABLE 26-20: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
Only relevant for Repeated
Start condition
91
92
93
THD:STA Start Condition
Hold Time
4000
600
ns
ns
ns
After this period, the first
clock pulse is generated
TSU:STO Stop Condition
Setup Time
4700
600
THD:STO Stop Condition
Hold Time
4000
600
FIGURE 26-16:
I2C™ BUS DATA TIMING
103
102
100
101
SCLx
90
106
107
91
92
SDAx
In
110
109
109
SDAx
Out
Note: Refer to Figure 26-2 for load conditions.
2005 Microchip Technology Inc.
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TABLE 26-21: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
100 kHz mode
Min
Max
Units
Conditions
100
THIGH
Clock High Time
4.0
—
µs
PIC18F87J10 must operate at
a minimum of 1.5 MHz
400 kHz mode
0.6
—
µs
PIC18F87J10 must operate at
a minimum of 10 MHz
SSP Module
1.5 TCY
4.7
—
—
101
TLOW
Clock Low Time
100 kHz mode
µs
µs
PIC18F87J10 must operate at
a minimum of 1.5 MHz
400 kHz mode
1.3
—
PIC18F87J10 must operate at
a minimum of 10 MHz
SSP Module
1.5 TCY
—
—
102
103
TR
SDAx and SCLx Rise Time 100 kHz mode
400 kHz mode
1000
300
ns
ns
20 + 0.1 CB
CB is specified to be from
10 to 400 pF
TF
SDAx and SCLx Fall Time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1 CB
CB is specified to be from
10 to 400 pF
90
TSU:STA
Start Condition Setup Time 100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for Repeated
Start condition
91
THD:STA Start Condition Hold Time 100 kHz mode
400 kHz mode
—
After this period, the first clock
pulse is generated
—
106
107
92
THD:DAT Data Input Hold Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
0
0.9
—
TSU:DAT Data Input Setup Time
250
100
4.7
0.6
—
(Note 2)
—
TSU:STO Stop Condition Setup Time 100 kHz mode
400 kHz mode
—
—
109
110
TAA
Output Valid from Clock
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
3500
—
(Note 1)
—
TBUF
Bus Free Time
4.7
1.3
—
Time the bus must be free
before a new transmission can
start
—
D102
CB
Bus Capacitive Loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
2
2
2: A Fast mode I C™ bus device can be used in a Standard mode I C bus system, but the requirement, TSU:DAT ≥ 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal.
If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line,
2
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCLx
line is released.
DS39663A-page 364
Advance Information
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PIC18F87J10 FAMILY
FIGURE 26-17:
SCLx
MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
93
91
90
92
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 26-2 for load conditions.
TABLE 26-22: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated Start
condition
91
92
93
THD:STA Start Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
ns After this period, the
first clock pulse is
generated
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
TSU:STO Stop Condition
Setup Time
100 kHz mode
2(TOSC)(BRG + 1)
ns
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
THD:STO Stop Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
ns
400 kHz mode
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
FIGURE 26-18:
MASTER SSP I2C™ BUS DATA TIMING
103
102
100
101
SCLx
90
106
91
92
107
SDAx
In
110
109
109
SDAx
Out
Note: Refer to Figure 26-2 for load conditions.
2005 Microchip Technology Inc.
Advance Information
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TABLE 26-23: MASTER SSP I2C™ BUS DATA REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock High Time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
ms
ms
ms
ms
ms
ms
ns
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
101
102
103
90
TLOW
TR
Clock Low Time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
—
2(TOSC)(BRG + 1)
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
SDAx and SCLx 100 kHz mode
—
1000
300
300
300
300
100
—
CB is specified to be from
10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
ns
—
—
ns
TF
SDAx and SCLx 100 kHz mode
ns
CB is specified to be from
10 to 400 pF
Fall Time
400 kHz mode
20 + 0.1 CB
—
ns
1 MHz mode(1)
ns
TSU:STA Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
ms Only relevant for
Setup Time
Repeated Start
condition
ms
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
ms
—
91
THD:STA Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
—
ms After this period, the first
Hold Time
clock pulse is generated
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
ns
106
107
92
THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
0
—
0
0.9
—
ms
ns
TBD
250
TSU:DAT Data Input
Setup Time
—
ns
ns
(Note 2)
100
—
TBD
—
ns
TSU:STO Stop Condition
Setup Time
2(TOSC)(BRG + 1)
—
ms
ms
ms
ns
2(TOSC)(BRG + 1)
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
109
110
D102
TAA
TBUF
CB
Output Valid
from Clock
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
—
3500
1000
—
ns
—
ns
Bus Free Time
4.7
1.3
TBD
—
—
ms Time the bus must be free
before a new transmission
—
ms
can start
ms
—
Bus Capacitive Loading
400
pF
Legend: TBD = To Be Determined
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data
bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before
the SCLx line is released.
DS39663A-page 366
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
FIGURE 26-19:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TXx/CKx
pin
121
121
RXx/DTx
pin
120
Note: Refer to Figure 26-2 for load conditions.
122
TABLE 26-24: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TCKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid
—
—
—
40
20
20
ns
ns
ns
121
122
TCKRF
TDTRF
Clock Out Rise Time and Fall Time (Master mode)
Data Out Rise Time and Fall Time
FIGURE 26-20:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TXx/CKx
pin
125
RXx/DTx
pin
126
Note: Refer to Figure 26-2 for load conditions.
TABLE 26-25: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TDTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CKx ↓ (DTx hold time)
10
15
—
—
ns
ns
126
TCKL2DTL Data Hold after CKx ↓ (DTx hold time)
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 367
PIC18F87J10 FAMILY
TABLE 26-26: A/D CONVERTER CHARACTERISTICS: PIC18F87J10 FAMILY (INDUSTRIAL)
Param
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
No.
A01
NR
Resolution
—
—
—
—
—
—
10
<±1
bit ∆VREF ≥ 3.0V
A03
A04
A06
A07
A10
A20
EIL
Integral Linearity Error
Differential Linearity Error
Offset Error
—
LSb ∆VREF ≥ 3.0V
LSb ∆VREF ≥ 3.0V
LSb ∆VREF ≥ 3.0V
LSb ∆VREF ≥ 3.0V
EDL
EOFF
EGN
—
—
<±1
—
<±1.5
<±1
Gain Error
—
Monotonicity
Guaranteed(1)
—
VSS ≤ VAIN ≤ VREF
VDD < 3.0V
VDD ≥ 3.0V
∆VREF Reference Voltage Range
1.8
3
—
—
—
—
V
V
(VREFH – VREFL)
A21
A22
A25
A30
VREFH Reference Voltage High
VSS
—
VREFH
VDD – 3.0V
VREFH
V
V
VREFL
VAIN
Reference Voltage Low
Analog Input Voltage
VSS – 0.3V
VREFL
—
—
—
—
V
ZAIN
Recommended Impedance of
Analog Voltage Source
2.5
kΩ
A50
IREF
VREF Input Current(2)
—
—
—
—
5
150
µA During VAIN acquisition.
µA During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.
FIGURE 26-21:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
TCY
OLD_DATA
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEPinstruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
DS39663A-page 368
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
TABLE 26-27: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/D Clock Period
0.7
TBD
11
25.0(1)
µs TOSC based, VREF ≥ 3.0V
µs A/D RC mode
TAD
1
131
132
TCNV
TACQ
Conversion Time
(not including acquisition time) (Note 2)
12
Acquisition Time (Note 3)
1.4
TBD
—
—
µs -40°C to +85°C
µs
0°C ≤ to ≤ +85°C
135
TSWC
TDIS
Switching Time from Convert → Sample
—
(Note 4)
TBD
Discharge Time
0.2
—
µs
Legend: TBD = To Be Determined
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 369
PIC18F87J10 FAMILY
NOTES:
DS39663A-page 370
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
27.0 PACKAGING INFORMATION
27.1 Package Marking Information
64-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
18F67J10
-I/PT
0510017
e
3
80-Lead TQFP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC18F87J10
-I/PT
0510017
e
3
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 371
PIC18F87J10 FAMILY
27.2 Package Details
The following sections give the technical details of the
packages.
64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
CH x 45°
α
A
c
L
A2
φ
A1
β
(F)
Units
Dimension Limits
INCHES
NOM
64
MILLIMETERS*
NOM
64
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
.020
0.50
16
Pins per Side
n1
A
16
.043
.039
.006
.024
.039
3.5
Overall Height
.039
.047
1.00
1.10
1.00
0.15
0.60
1.00
3.5
1.20
Molded Package Thickness
Standoff
A2
A1
L
.037
.002
.018
.041
.010
.030
0.95
0.05
0.45
1.05
0.25
0.75
Foot Length
(F)
φ
E
D
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.005
.007
.025
5
7
.482
.482
.398
.398
.009
.011
.045
15
0
11.75
11.75
9.90
9.90
0.13
0.17
0.64
5
7
12.25
12.25
10.10
10.10
0.23
0.27
1.14
15
Overall Width
.472
.472
.394
.394
.007
.009
.035
10
12.00
12.00
10.00
10.00
0.18
0.22
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
E1
D1
c
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
β
5
10
15
5
10
15
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed .010" (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-085
DS39663A-page 372
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
CH x 45°
A
α
c
A2
φ
β
L
A1
(F)
Units
Dimension Limits
INCHES
NOM
80
MILLIMETERS*
NOM
80
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
.020
0.50
20
Pins per Side
n1
A
20
.043
.039
.004
.024
.039
3.5
Overall Height
.039
.037
.002
.018
.047
1.00
1.10
1.00
0.10
0.60
1.00
3.5
1.20
Molded Package Thickness
Standoff
A2
A1
L
.041
.006
.030
0.95
0.05
0.45
1.05
0.15
0.75
Foot Length
(F)
Footprint (Reference)
Foot Angle
φ
E
0
.541
.541
.463
.463
.004
.007
.025
5
7
.561
.561
.482
.482
.008
.011
.045
15
0
13.75
13.75
11.75
11.75
0.09
0.17
0.64
5
7
14.25
14.25
12.25
12.25
0.20
0.27
1.14
15
Overall Width
.551
.551
.472
.472
.006
.009
.035
10
14.00
14.00
12.00
12.00
0.15
0.22
0.89
10
Overall Length
D
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
E1
D1
c
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
β
5
10
15
5
10
15
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed .010" (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-092
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 373
PIC18F87J10 FAMILY
NOTES:
DS39663A-page 374
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
APPENDIX A: MIGRATION
BETWEEN HIGH-END
DEVICE FAMILIES
Devices in the PIC18F87J10 and PIC18F8722 families
are very similar in their functions and feature sets.
However, there are some potentially important differ-
ences which should be considered when migrating an
application across device families to achieve a new
design goal. These are summarized in Table A-1. The
areas of difference which could be a major impact on
migration are discussed in greater detail later in this
section.
TABLE A-1:
NOTABLE DIFFERENCES BETWEEN PIC18F8722 AND PIC18F87J10 FAMILIES
Characteristic
PIC18F87J10 Family
PIC18F8722 Family
Operating Frequency
Supply Voltage
40 MHz @ 2.15V
2.0V-3.6V, dual voltage requirement
Low
40 MHz @ 4.2V
2.0V-5.5V
Operating Current
Lower
Program Memory Endurance
I/O Sink/Source at 25 mA
Input Voltage Tolerance on I/O pins
I/O
1,000 write/erase cycles (typical)
PORTB and PORTC only
5.5V on digital only pins
100,000 write/erase cycles (typical)
All ports
VDD on all I/O pins
70
66 (RA7, RA6, RE3 and RF0
not available)
Pull-ups
PORTB, PORTD, PORTE
and PORTJ
PORTB
Oscillator Options
Limited options (EC, HS, PLL,
fixed 32 kHz INTRC)
More options (EC, HS, XT, LP, RC,
PLL, flexible INTRC)
Program Memory Retention
Self-Writes to Program Memory
Programming Time (Normalized)
Programming Entry
10 years (minimum)
Not available
40 years (minimum)
Available
156 µs/byte (10 ms/64-byte block)
Low Voltage, Key Sequence
Single block, all or nothing
15.6 µs/byte (1 ms/64-byte block)
VPP and LVP
Code Protection
Multiple code protection blocks
Configuration Words
Stored in last 4 words of
Program Memory space
Stored in Configuration Space,
starting at 300000h
Start-up Time from Sleep
Power-up Timer
Data EEPROM
200 µs (typical)
Always on
10 µs (typical)
Configurable
Available
Not available
BOR
Simple BOR with Voltage Regulator
Not available
Programmable BOR
Available
LVD
A/D Channels
15
16
A/D Calibration
Required
Not required
Available
Microprocessor mode (EMB)
External Memory Addressing
In-Circuit Emulation
Not available
Address shifting available
Not available
Address shifting not available
Available
2005 Microchip Technology Inc.
DS39663A-page 375
PIC18F87J10 FAMILY
A.1
Power Requirement Differences
A.3
Oscillator Differences
The most significant difference between the
PIC18F87J10 and PIC18F8722 device families is the
power requirements. PIC18F87J10 devices are
designed on a smaller process; this results in lower
maximum voltage and higher leakage current.
PIC18F8722 devices have a greater range of oscillator
options than PIC18F87J10 devices. The latter family is
limited primarily to operating modes that support HS
and EC oscillators.
In addition, the PIC18F87J10 has an internal RC
oscillator with only a fixed 32 kHz output. The higher
frequency RC modes of the PIC18F8722 family are not
available.
The operating voltage range for PIC18F87J10 devices
is 2.0V to 3.6V. In addition, these devices have split
power requirements: one for the core logic and one for
the I/O. One of the VDD pins is separated for the core
logic supply (VDDCORE). This pin has specific voltage
and capacitor requirements as described in
Section 26.0 “Electrical Characteristics”.
Both device families have an internal PLL. For the
PIC18F87J10 family, however, the PLL must be
enabled in software.
The clocking differences should be considered when
making a conversion between the PIC18F8722 and
PIC18F87J10 device families.
The current specifications for PIC18F87J10 devices
are yet to be determined.
A.2
Pin Differences
A.4
Peripherals
There are several differences in the pinouts between
the PIC18F87J10 and the PIC18F8722 families:
Peripherals must also be considered when making a
conversion between the PIC18F87J10 and the
PIC18F8722 families:
• Input voltage tolerance
• Output current capabilities
• Available I/O
• External Memory Bus: The external memory bus
on the PIC18F87J10 does not support Micro-
controller mode; however, it does support external
address offset.
Pins on the PIC18F87J10 that have digital only input
capability will tolerate voltages up to 5.5V and are thus
tolerant to voltages above VDD. Table 10-1 in
Section 10.0 “I/O Ports” contains the complete list.
• A/D Converter: There are only 15 channels on
PIC18F87J10 devices. The converters for these
devices also require a calibration step prior to
normal operation.
In addition to input differences, there are output differ-
ences as well. PIC18F87J10 devices have three
classes of pin output current capability: high, medium
and low. Not all I/O pins can source or sink equal levels
of current. Only PORTB and PORTC support the
25 mA source/sink capability that is supported by all
output pins on the PIC18F8722. Table 10-2 in
Section 10.0 “I/O Ports” contains the complete list of
output capabilities.
• Data EEPROM: PIC18F87J10 devices do not
have this module.
• BOR: PIC18F87J10 devices do not have a
programmable BOR. Simple brown-out capability
is provided through the use of the internal voltage
regulator.
• LVD: PIC18F87J10 devices do not have this
module.
There are additional differences in how some pin func-
tions are implemented on PIC18F87J10 devices. First,
the OSC1/OSC2 oscillator pins are strictly dedicated to
the external oscillator function; there is no option to
re-allocate these pins to I/O (RA6 or RA7) as on
PIC18F8722 devices. Second, the MCLR pin is
dedicated only to MCLR and cannot be configured as
an input (RG5). Finally, RF0 does not exist on
PIC18F87J10 devices.
All of these pin differences (including power pin
differences) should be accounted for when making a
conversion between PIC18F8722 and PIC18F87J10
devices.
DS39663A-page 376
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
B
INDEX
Bank Select Register (BSR) .............................................. 64
Baud Rate Generator ...................................................... 210
BC .................................................................................... 287
BCF ................................................................................. 288
BF .................................................................................... 214
BF Status Flag ................................................................. 214
Block Diagrams
A
A/D ................................................................................... 247
A/D Converter Interrupt, Configuring ....................... 251
Acquisition Requirements ........................................ 252
ADCAL Bit ................................................................ 255
ADCON0 Register .................................................... 247
ADCON1 Register .................................................... 247
ADCON2 Register .................................................... 247
ADRESH Register ............................................ 247, 250
ADRESL Register .................................................... 247
Analog Port Pins ...................................................... 138
Analog Port Pins, Configuring .................................. 253
Associated Registers ............................................... 255
Automatic Acquisition Time ...................................... 253
Calculating the Minimum Required
Acquisition Time .............................................. 252
Calibration ................................................................ 255
Configuring the Module ............................................ 251
Conversion Clock (TAD) ........................................... 253
Conversion Status (GO/DONE Bit) .......................... 250
Conversions ............................................................. 254
Converter Characteristics ........................................ 368
Operation in Power-Managed Modes ...................... 255
Special Event Trigger (ECCP) ......................... 170, 254
Use of the ECCP2 Trigger ....................................... 254
Absolute Maximum Ratings ............................................. 335
AC (Timing) Characteristics ............................................. 349
Load Conditions for Device Timing
16-Bit Byte Select Mode ............................................ 91
16-Bit Byte Write Mode .............................................. 89
16-Bit Word Write Mode ............................................ 90
A/D ........................................................................... 250
Analog Input Model .................................................. 251
Baud Rate Generator .............................................. 210
Capture Mode Operation ......................................... 161
Comparator Analog Input Model .............................. 261
Comparator I/O Operating Modes ........................... 258
Comparator Output .................................................. 260
Comparator Voltage Reference ............................... 264
Comparator Voltage Reference Output
Buffer Example ................................................ 265
Compare Mode Operation ....................................... 162
Connections for On-Chip Voltage Regulator ........... 274
Device Clock .............................................................. 30
Enhanced PWM ....................................................... 171
EUSART Receive .................................................... 237
EUSART Transmit ................................................... 235
External Power-on Reset Circuit
(Slow VDD Power-up) ........................................ 45
Fail-Safe Clock Monitor ........................................... 276
Generic I/O Port Operation ...................................... 115
Interrupt Logic .......................................................... 100
Specifications ................................................... 350
Parameter Symbology ............................................. 349
Temperature and Voltage
2
MSSP (I C Master Mode) ........................................ 208
2
Specifications ................................................... 350
Timing Conditions .................................................... 350
Access Bank ...................................................................... 67
Mapping with Indexed Literal
MSSP (I C Mode) .................................................... 193
MSSP (SPI Mode) ................................................... 183
On-Chip Reset Circuit ................................................ 43
PIC18F6XJ10/6XJ15 ................................................... 8
PIC18F8XJ10/8XJ15 ................................................... 9
PLL ............................................................................ 29
PORTD and PORTE
Offset Mode ....................................................... 79
ACKSTAT ........................................................................ 214
ACKSTAT Status Flag ..................................................... 214
ADCAL Bit ........................................................................ 255
ADCON0 Register ............................................................ 247
GO/DONE Bit ........................................................... 250
ADCON1 Register ............................................................ 247
ADCON2 Register ............................................................ 247
ADDFSR .......................................................................... 322
ADDLW ............................................................................ 285
ADDULNK ........................................................................ 322
ADDWF ............................................................................ 285
ADDWFC ......................................................................... 286
ADRESH Register ............................................................ 247
ADRESL Register .................................................... 247, 250
Analog-to-Digital Converter. See A/D.
(Parallel Slave Port) ......................................... 138
PWM Operation (Simplified) .................................... 164
Reads from Program Memory ................................... 82
Single Comparator ................................................... 259
Table Read and Table Write Operations ................... 81
Timer0 in 16-Bit Mode ............................................. 142
Timer0 in 8-Bit Mode ............................................... 142
Timer1 ..................................................................... 146
Timer1 (16-Bit Read/Write Mode) ............................ 146
Timer2 ..................................................................... 152
Timer3 ..................................................................... 154
Timer3 (16-Bit Read/Write Mode) ............................ 154
Timer4 ..................................................................... 158
Watchdog Timer ...................................................... 273
BN .................................................................................... 288
BNC ................................................................................. 289
BNN ................................................................................. 289
BNOV .............................................................................. 290
BNZ ................................................................................. 290
BOR. See Brown-out Reset.
ANDLW ............................................................................ 286
ANDWF ............................................................................ 287
Assembler
MPASM Assembler .................................................. 329
Auto-Wake-up on Sync Break Character ......................... 238
2005 Microchip Technology Inc.
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PIC18F87J10 FAMILY
BOV ..................................................................................293
BRA ..................................................................................291
Break Character (12-Bit) Transmit
and Receive .............................................................240
BRG. See Baud Rate Generator.
Loading the SSP1BUF
(SSP1SR) Register .......................................... 186
Reading a Flash Program Memory Word .................. 83
Saving STATUS, WREG and
BSR Registers in RAM .................................... 114
Brown-out Reset (BOR) .....................................................45
and On-Chip Voltage Regulator ...............................274
Disabling in Sleep Mode ............................................45
BSF ..................................................................................291
BSR ....................................................................................79
BTFSC .............................................................................292
BTFSS ..............................................................................292
BTG ..................................................................................293
BZ .....................................................................................294
Code Protection ............................................................... 267
COMF .............................................................................. 296
Comparator ...................................................................... 257
Analog Input Connection Considerations ................ 261
Associated Registers ............................................... 261
Configuration ........................................................... 258
Effects of a Reset .................................................... 260
Interrupts ................................................................. 260
Operation ................................................................. 259
Operation During Sleep ........................................... 260
Outputs .................................................................... 259
Reference ................................................................ 259
External Signal ................................................ 259
C
C Compilers
MPLAB C17 .............................................................330
MPLAB C18 .............................................................330
MPLAB C30 .............................................................330
Calibration (A/D Converter) ..............................................255
CALL ................................................................................294
CALLW .............................................................................323
Capture (CCP Module) .....................................................161
Associated Registers ...............................................163
CCP Pin Configuration .............................................161
CCPRxH:CCPRxL Registers ...................................161
Prescaler ..................................................................161
Software Interrupt ....................................................161
Timer1/Timer3 Mode Selection ................................161
Capture (ECCP Module) ..................................................170
Capture/Compare/PWM (CCP) ........................................159
Capture Mode. See Capture.
Internal Signal .................................................. 259
Response Time ........................................................ 259
Comparator Specifications ............................................... 348
Comparator Voltage Reference ....................................... 263
Accuracy and Error .................................................. 264
Associated Registers ............................................... 265
Configuring .............................................................. 263
Connection Considerations ...................................... 264
Effects of a Reset .................................................... 264
Operation During Sleep ........................................... 264
Compare (CCP Module) .................................................. 162
Associated Registers ............................................... 163
CCPRx Register ...................................................... 162
Pin Configuration ..................................................... 162
Software Interrupt .................................................... 162
Timer1/Timer3 Mode Selection ................................ 162
Compare (ECCP Module) ................................................ 170
Special Event Trigger .............................. 155, 170, 254
Computed GOTO ............................................................... 61
Configuration Bits ............................................................ 267
Configuration Register Protection .................................... 278
Context Saving During Interrupts ..................................... 114
CPFSEQ .......................................................................... 296
CPFSGT .......................................................................... 297
CPFSLT ........................................................................... 297
Crystal Oscillator/Ceramic Resonator ................................ 27
Customer Change Notification Service ............................ 387
Customer Notification Service ......................................... 387
Customer Support ............................................................ 387
CCP Mode and Timer Resources ............................160
CCPRxH Register ....................................................160
CCPRxL Register .....................................................160
Compare Mode. See Compare.
Interconnect Configurations .....................................160
Module Configuration ...............................................160
Clock Sources ....................................................................30
Default System Clock on Reset .................................31
Selection Using OSCCON Register ...........................31
Clocking Scheme/Instruction Cycle ....................................62
CLRF ................................................................................295
CLRWDT ..........................................................................295
Code Examples
16 x 16 Signed Multiply Routine ................................98
16 x 16 Unsigned Multiply Routine ............................98
8 x 8 Signed Multiply Routine ....................................97
8 x 8 Unsigned Multiply Routine ................................97
Changing Between Capture Prescalers ...................161
Computed GOTO Using an Offset Value ...................61
Fast Register Stack ....................................................61
How to Clear RAM (Bank 1) Using
D
Data Addressing Modes .................................................... 74
Comparing Addressing Modes with the
Extended Instruction Set Enabled ..................... 78
Direct ......................................................................... 74
Indexed Literal Offset ................................................ 77
Indirect ....................................................................... 74
Inherent and Literal .................................................... 74
Data Memory ..................................................................... 64
Access Bank .............................................................. 67
and the Extended Instruction Set .............................. 77
Bank Select Register (BSR) ...................................... 64
General Purpose Registers ....................................... 67
Map for PIC18FX5J10/X5J15/X6J10 Devices ........... 65
Map for PIC18FX6J15/X7J10 Devices ...................... 66
Special Function Registers ........................................ 68
DAW ................................................................................ 298
Indirect Addressing ............................................74
Implementing a Real-Time Clock
Using a Timer1 Interrupt Service .....................149
Initializing PORTA ....................................................116
Initializing PORTB ....................................................118
Initializing PORTC ....................................................121
Initializing PORTD ....................................................124
Initializing PORTE ....................................................127
Initializing PORTF ....................................................130
Initializing PORTG ...................................................132
Initializing PORTH ....................................................134
Initializing PORTJ ....................................................136
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DC Characteristics ........................................................... 345
Power-Down and Supply Current ............................ 338
Supply Voltage ......................................................... 337
DCFSNZ .......................................................................... 299
DECF ............................................................................... 298
DECFSZ ........................................................................... 299
Default System Clock ......................................................... 31
Demonstration Boards
PICDEM 1 ................................................................ 332
PICDEM 17 .............................................................. 333
PICDEM 18R ........................................................... 333
PICDEM 2 Plus ........................................................ 332
PICDEM 3 ................................................................ 332
PICDEM 4 ................................................................ 332
PICDEM LIN ............................................................ 333
PICDEM USB ........................................................... 333
PICDEM.net Internet/Ethernet ................................. 332
Development Support ...................................................... 329
Device Overview .................................................................. 5
Details on Individual Family Members ......................... 6
Features (64-Pin Devices) ........................................... 7
Features (80-Pin Devices) ........................................... 7
Direct Addressing ............................................................... 75
Baud Rate Generator (BRG) ................................... 229
Associated Registers ....................................... 230
Auto-Baud Rate Detect .................................... 233
Baud Rate Error, Calculating ........................... 230
Baud Rates, Asynchronous Modes ................. 231
High Baud Rate Select (BRGH Bit) ................. 229
Sampling ......................................................... 229
Synchronous Master Mode ...................................... 241
Associated Registers, Receive ........................ 244
Associated Registers, Transmit ....................... 242
Reception ........................................................ 243
Transmission ................................................... 241
Synchronous Slave Mode ........................................ 244
Associated Registers, Receive ........................ 246
Associated Registers, Transmit ....................... 245
Reception ........................................................ 245
Transmission ................................................... 244
Evaluation and Programming Tools ................................. 333
Extended Instruction Set
ADDFSR .................................................................. 322
ADDULNK ............................................................... 322
CALLW .................................................................... 323
MOVSF .................................................................... 323
MOVSS .................................................................... 324
PUSHL ..................................................................... 324
SUBFSR .................................................................. 325
SUBULNK ................................................................ 325
Extended Microcontroller Mode ......................................... 88
External Clock Input (EC Modes) ...................................... 28
External Memory Bus ........................................................ 85
16-Bit Byte Select Mode ............................................ 91
16-Bit Byte Write Mode .............................................. 89
16-Bit Data Width Modes ........................................... 88
16-Bit Mode Timing ................................................... 92
16-Bit Word Write Mode ............................................ 90
8-Bit Mode ................................................................. 93
8-Bit Mode Timing ..................................................... 94
Address and Data Line Usage (table) ....................... 87
Address and Data Width ............................................ 87
Address Shifting ........................................................ 87
and Program Memory Modes ............................ 88
Control ....................................................................... 86
I/O Port Functions ...................................................... 85
Operation in Power-Managed Modes ........................ 95
Wait States ................................................................ 88
Weak Pull-ups on Port Pins ....................................... 88
E
ECCP
Capture and Compare Modes .................................. 170
Standard PWM Mode ............................................... 170
Effect on Standard PIC Instructions ........................... 77, 326
Effects of Power-Managed Modes on
Various Clock Sources ............................................... 32
Electrical Characteristics .................................................. 335
Enhanced Capture/Compare/PWM (ECCP) .................... 167
Capture Mode. See Capture (ECCP Module).
ECCP1/ECCP3 Outputs and
Program Memory Mode ................................... 168
ECCP2 Outputs and Program
Memory Modes ................................................ 168
Outputs and Configuration ....................................... 168
Pin Configurations for ECCP1 ................................. 169
Pin Configurations for ECCP2 ................................. 169
Pin Configurations for ECCP3 ................................. 170
PWM Mode. See PWM (ECCP Module).
Timer Resources ...................................................... 168
Enhanced PWM Mode ..................................................... 171
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART). See EUSART.
ENVREG Pin .................................................................... 274
Equations
A/D Acquisition Time ................................................ 252
A/D Minimum Charging Time ................................... 252
Errata ................................................................................... 4
EUSART
F
Fail-Safe Clock Monitor ........................................... 267, 276
Interrupts in Power-Managed Modes ...................... 277
POR or Wake-up from Sleep ................................... 277
WDT During Oscillator Failure ................................. 276
Fast Register Stack ........................................................... 61
Firmware Instructions ...................................................... 279
Flash Configuration Words ........................................ 56, 267
Flash Program Memory
Associated Registers ................................................. 84
Operation During Code-Protect ................................. 84
Reading ..................................................................... 82
FSCM. See Fail-Safe Clock Monitor.
Asynchronous Mode ................................................ 235
12-bit Break Transmit and Receive ................. 240
Associated Registers, Receive ........................ 238
Associated Registers, Transmit ....................... 236
Auto-Wake-up on Sync Break ......................... 238
Receiver ........................................................... 237
Setting up 9-Bit Mode with
Address Detect ........................................ 237
Transmitter ....................................................... 235
Baud Rate Generator
G
GOTO .............................................................................. 300
Operation in Power-Managed Mode ................ 229
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ANDWF .................................................................... 287
BC ............................................................................ 287
BCF ......................................................................... 288
BN ............................................................................ 288
BNC ......................................................................... 289
BNN ......................................................................... 289
BNOV ...................................................................... 290
BNZ ......................................................................... 290
BOV ......................................................................... 293
BRA ......................................................................... 291
BSF .......................................................................... 291
BSF (Indexed Literal Offset Mode) .......................... 327
BTFSC ..................................................................... 292
BTFSS ..................................................................... 292
BTG ......................................................................... 293
BZ ............................................................................ 294
CALL ........................................................................ 294
CLRF ....................................................................... 295
CLRWDT ................................................................. 295
COMF ...................................................................... 296
CPFSEQ .................................................................. 296
CPFSGT .................................................................. 297
CPFSLT ................................................................... 297
DAW ........................................................................ 298
DCFSNZ .................................................................. 299
DECF ....................................................................... 298
DECFSZ .................................................................. 299
Extended Instructions .............................................. 321
Considerations when Enabling ........................ 326
Syntax .............................................................. 321
Use with MPLAB IDE Tools ............................. 328
General Format ........................................................ 281
GOTO ...................................................................... 300
INCF ........................................................................ 300
INCFSZ .................................................................... 301
INFSNZ .................................................................... 301
IORLW ..................................................................... 302
IORWF ..................................................................... 302
LFSR ....................................................................... 303
MOVF ...................................................................... 303
MOVFF .................................................................... 304
MOVLB .................................................................... 304
MOVLW ................................................................... 305
MOVWF ................................................................... 305
MULLW .................................................................... 306
MULWF .................................................................... 306
NEGF ....................................................................... 307
NOP ......................................................................... 307
POP ......................................................................... 308
PUSH ....................................................................... 308
RCALL ..................................................................... 309
RESET ..................................................................... 309
RETFIE .................................................................... 310
RETLW .................................................................... 310
RETURN .................................................................. 311
RLCF ....................................................................... 311
RLNCF ..................................................................... 312
RRCF ....................................................................... 312
RRNCF .................................................................... 313
SETF ....................................................................... 313
SETF (Indexed Literal Offset Mode) ........................ 327
SLEEP ..................................................................... 314
Standard Instructions ............................................... 279
SUBFWB ................................................................. 314
SUBLW .................................................................... 315
H
Hardware Multiplier ............................................................97
Introduction ................................................................97
Operation ...................................................................97
Performance Comparison ..........................................97
I
I/O Ports ...........................................................................115
2
I C Mode (MSSP)
Acknowledge Sequence Timing ...............................217
Associated Registers ...............................................223
Baud Rate Generator ...............................................210
Bus Collision
During a Repeated Start Condition ..................221
During a Stop Condition ...................................222
Clock Arbitration .......................................................211
Clock Stretching .......................................................203
10-Bit Slave Receive Mode
(SEN = 1) .................................................203
10-Bit Slave Transmit Mode .............................203
7-Bit Slave Receive Mode
(SEN = 1) .................................................203
7-Bit Slave Transmit Mode ...............................203
Clock Synchronization and the CKP Bit ...................204
Effects of a Reset .....................................................218
General Call Address Support .................................207
2
I C Clock Rate w/BRG .............................................210
Master Mode ............................................................208
Baud Rate Generator .......................................210
Operation .........................................................209
Reception .........................................................214
Repeated Start Condition Timing .....................213
Start Condition Timing .....................................212
Transmission ....................................................214
Multi-Master Communication, Bus Collision
and Arbitration ..................................................218
Multi-Master Mode ...................................................218
Operation .................................................................197
Read/Write Bit Information (R/W Bit) ............... 197, 198
Registers ..................................................................193
Serial Clock (SCKx/SCLx) .......................................198
Slave Mode ..............................................................197
Addressing .......................................................197
Reception .........................................................198
Transmission ....................................................198
Sleep Operation .......................................................218
Stop Condition Timing ..............................................217
INCF .................................................................................300
INCFSZ ............................................................................301
In-Circuit Debugger ..........................................................278
In-Circuit Serial Programming (ICSP) ......................267, 278
Indexed Literal Offset Addressing
and Standard PIC18 Instructions .............................326
Indexed Literal Offset Mode ................................. 77, 79, 326
Indirect Addressing ............................................................75
INFSNZ ............................................................................301
Initialization Conditions for all Registers ......................49–53
Instruction Cycle .................................................................62
Instruction Flow/Pipelining .................................................62
Instruction Set ..................................................................279
ADDLW ....................................................................285
ADDWF ....................................................................285
ADDWF (Indexed Literal Offset Mode) ....................327
ADDWFC .................................................................286
ANDLW ....................................................................286
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SUBWF .................................................................... 315
SUBWFB .................................................................. 316
SWAPF .................................................................... 316
TBLRD ..................................................................... 317
TBLWT ..................................................................... 318
TSTFSZ ................................................................... 319
XORLW .................................................................... 319
XORWF .................................................................... 320
MOVSF ............................................................................ 323
MOVSS ............................................................................ 324
MOVWF ........................................................................... 305
MPLAB ASM30 Assembler,
Linker, Librarian ....................................................... 330
MPLAB ICD 2 In-Circuit Debugger .................................. 331
MPLAB ICE 2000 High-Performance
Universal In-Circuit Emulator ................................... 331
MPLAB ICE 4000 High-Performance
INTCON Register
RBIF Bit .................................................................... 118
INTCON Registers ........................................................... 101
Inter-Integrated Circuit. See I C Mode.
Internal Oscillator Block ..................................................... 30
Internal RC Oscillator
Universal In-Circuit Emulator ................................... 331
MPLAB Integrated Development
Environment Software ............................................. 329
MPLAB PM3 Device Programmer ................................... 331
MPLINK Object Linker/MPLIB Object Librarian ............... 330
MSSP
2
Use with WDT .......................................................... 273
Internet Address ............................................................... 387
Interrupt Sources ............................................................. 267
A/D Conversion Complete ....................................... 251
Capture Complete (CCP) ......................................... 161
Compare Complete (CCP) ....................................... 162
Interrupt-on-Change (RB7:RB4) .............................. 118
INTn Pin ................................................................... 114
PORTB, Interrupt-on-Change .................................. 114
TMR0 ....................................................................... 114
TMR0 Overflow ........................................................ 143
TMR1 Overflow ........................................................ 145
TMR2 to PR2 Match (PWM) ............................ 164, 171
TMR3 Overflow ................................................ 153, 155
TMR4 to PR4 Match ................................................ 158
TMR4 to PR4 Match (PWM) .................................... 157
Interrupts ............................................................................ 99
Interrupts, Flag Bits
ACK Pulse ....................................................... 197, 198
Control Registers (general) ..................................... 183
Module Overview ..................................................... 183
SPI Master/Slave Connection .................................. 187
SSPxBUF Register .................................................. 188
SSPxSR Register .................................................... 188
MULLW ............................................................................ 306
MULWF ............................................................................ 306
N
NEGF ............................................................................... 307
NOP ................................................................................. 307
Notable Differences Between PIC18F8722
and PIC18F87J10 Families ..................................... 375
Oscillator Options .................................................... 376
Peripherals .............................................................. 376
Pinouts ..................................................................... 376
Power Requirements ............................................... 376
Interrupt-on-Change (RB7:RB4)
Flag (RBIF Bit) ................................................. 118
INTOSC, INTRC. See Internal Oscillator Block.
IORLW ............................................................................. 302
IORWF ............................................................................. 302
IPR Registers ................................................................... 110
O
Opcode Field Descriptions ............................................... 280
Oscillator Configuration ..................................................... 27
EC .............................................................................. 27
ECPLL ....................................................................... 27
HS .............................................................................. 27
HS Modes .................................................................. 27
HSPLL ....................................................................... 27
Internal Oscillator Block ............................................. 30
INTRC ........................................................................ 27
Oscillator Selection .......................................................... 267
Oscillator Start-up Timer (OST) ......................................... 33
Oscillator Switching ........................................................... 30
Oscillator Transitions ......................................................... 31
Oscillator, Timer1 ..................................................... 145, 155
Oscillator, Timer3 ............................................................. 153
K
Key Features
Easy Migration ............................................................. 6
Expanded Memory ....................................................... 5
Extended Instruction Set .............................................. 5
External Memory Bus ................................................... 5
L
LFSR ................................................................................ 303
M
Master Clear (MCLR) ......................................................... 45
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Maps
P
Packaging ........................................................................ 371
Details ...................................................................... 372
Marking .................................................................... 371
Parallel Slave Port (PSP) ................................................. 138
Associated Registers ............................................... 140
RE0/RD Pin ............................................................. 138
RE1/WR Pin ............................................................ 138
RE2/CS Pin ............................................................. 138
Select (PSPMODE Bit) ............................................ 138
PICkit 1 Flash Starter Kit ................................................. 333
PICSTART Plus Development
Data Memory
PIC18FX5J10/X5J15/X6J10 .............................. 65
PIC18FX6J15/X7J10 ......................................... 66
Memory Organization ......................................................... 55
Data Memory ............................................................. 64
Program Memory ....................................................... 55
Memory Programming Requirements .............................. 347
Microchip Internet Web Site ............................................. 387
Microcontroller Mode ......................................................... 88
MOVF ............................................................................... 303
MOVFF ............................................................................ 304
MOVLB ............................................................................ 304
MOVLW ........................................................................... 305
Programmer ............................................................. 332
PIE Registers ................................................................... 107
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Pin Functions
RF2/AN7/C1OUT ................................................. 15, 22
RF3/AN8 .............................................................. 15, 22
RF4/AN9 .............................................................. 15, 22
RF5/AN10/CVREF ................................................ 15, 22
RF6/AN11 ............................................................ 15, 22
RF7/SS1 .............................................................. 15, 22
RG0/ECCP3/P3A ................................................. 16, 23
RG1/TX2/CK2 ...................................................... 16, 23
RG2/RX2/DT2 ...................................................... 16, 23
RG3/CCP4/P3D ................................................... 16, 23
RG4/CCP5/P1D ................................................... 16, 23
RH0/A16 .................................................................... 24
RH1/A17 .................................................................... 24
RH2/A18 .................................................................... 24
RH3/A19 .................................................................... 24
RH4/AN12/P3C .......................................................... 24
RH5/AN13/P3B .......................................................... 24
RH6/AN14/P1C .......................................................... 24
RH7/AN15/P1B .......................................................... 24
RJ0/ALE .................................................................... 25
RJ1/OE ...................................................................... 25
RJ2/WRL ................................................................... 25
RJ3/WRH ................................................................... 25
RJ4/BA0 .................................................................... 25
RJ5/CE ...................................................................... 25
RJ6/LB ....................................................................... 25
RJ7/UB ...................................................................... 25
VDD ............................................................................ 25
VDD ............................................................................ 16
VDDCORE/VCAP ..................................................... 16, 25
VSS ............................................................................ 25
VSS ............................................................................ 16
Pinout I/O Descriptions
AVDD ..........................................................................25
AVDD ..........................................................................16
AVSS ..........................................................................25
AVSS ..........................................................................16
ENVREG .............................................................. 16, 25
MCLR ................................................................... 10, 17
OSC1/CLKI .......................................................... 10, 17
OSC2/CLKO ........................................................ 10, 17
RA0/AN0 .............................................................. 10, 17
RA1/AN1 .............................................................. 10, 17
RA2/AN2/VREF- .................................................... 10, 17
RA3/AN3/VREF+ ................................................... 10, 17
RA4/T0CKI ........................................................... 10, 17
RA5/AN4 .............................................................. 10, 17
RB0/INT0/FLT0 .................................................... 11, 18
RB1/INT1 ............................................................. 11, 18
RB2/INT2 ............................................................. 11, 18
RB3/INT3 ...................................................................11
RB3/INT3/ECCP2/P2A ..............................................18
RB4/KBI0 ............................................................. 11, 18
RB5/KBI1 ............................................................. 11, 18
RB6/KBI2/PGC .................................................... 11, 18
RB7/KBI3/PGD .................................................... 11, 18
RC0/T1OSO/T13CKI ...........................................12, 19
RC1/T1OSI/ECCP2/P2A ...................................... 12, 19
RC2/ECCP1/P1A ................................................. 12, 19
RC3/SCK1/SCL1 ................................................. 12, 19
RC4/SDI1/SDA1 .................................................. 12, 19
RC5/SDO1 ........................................................... 12, 19
RC6/TX1/CK1 ...................................................... 12, 19
RC7/RX1/DT1 ...................................................... 12, 19
RD0/AD0/PSP0 ..........................................................20
RD0/PSP0 ..................................................................13
RD1/AD1/PSP1 ..........................................................20
RD1/PSP1 ..................................................................13
RD2/AD2/PSP2 ..........................................................20
RD2/PSP2 ..................................................................13
RD3/AD3/PSP3 ..........................................................20
RD3/PSP3 ..................................................................13
RD4/AD4/PSP4/SDO2 ...............................................20
RD4/PSP4/SDO2 .......................................................13
RD5/AD5/PSP5/SDI2/SDA2 ......................................20
RD5/PSP5/SDI2/SDA2 ..............................................13
RD6/AD6/PSP6/SCK2/SCL2 .....................................20
RD6/PSP6/SCK2/SCL2 .............................................13
RD7/AD7/PSP7/SS2 ..................................................20
RD7/PSP7/SS2 ..........................................................13
RE0/AD8/RD/P2D ......................................................21
RE0/RD/P2D ..............................................................14
RE1/AD9/WR/P2C .....................................................21
RE1/WR/P2C .............................................................14
RE2/AD10/CS/P2B ....................................................21
RE2/CS/P2D ..............................................................14
RE3/AD11/P3C ..........................................................21
RE3/P3C ....................................................................14
RE4/AD12/P3B ..........................................................21
RE4/P3B ....................................................................14
RE5/AD13/P1C ..........................................................21
RE5/P1C ....................................................................14
RE6/AD14/P1B ..........................................................21
RE6/P1B ....................................................................14
RE7/AD15/ECCP2/P2A .............................................21
RE7/ECCP2/P2A .......................................................14
RF1/AN6/C2OUT ................................................. 15, 22
PIC18F6XJ10/6XJ15 ................................................. 10
PIC18F8XJ10/8XJ15 ................................................. 17
PIR Registers ................................................................... 104
PLL .................................................................................... 29
ECPLL Oscillator Mode ............................................. 29
HSPLL Oscillator Mode ............................................. 29
POP ................................................................................. 308
POR. See Power-on Reset.
PORTA
Associated Registers ............................................... 117
LATA Register ......................................................... 116
PORTA Register ...................................................... 116
TRISA Register ........................................................ 116
PORTB
Associated Registers ............................................... 120
LATB Register ......................................................... 118
PORTB Register ...................................................... 118
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) ......................................................... 118
TRISB Register ........................................................ 118
PORTC
Associated Registers ............................................... 123
LATC Register ......................................................... 121
PORTC Register ...................................................... 121
RC3/SCK1/SCL1 Pin ............................................... 198
TRISC Register ........................................................ 121
PORTD ............................................................................ 138
Associated Registers ............................................... 126
LATD Register ......................................................... 124
PORTD Register ...................................................... 124
TRISD Register ........................................................ 124
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PORTE
Analog Port Pins ...................................................... 138
PRO MATE II Universal
Device Programmer ................................................. 331
Program Counter ............................................................... 59
PCL, PCH and PCU Registers .................................. 59
PCLATH and PCLATU Registers .............................. 59
Program Memory ............................................................... 81
and the Extended Instruction Set .............................. 77
Control Registers ....................................................... 82
TABLAT (Table Latch) Register ........................ 82
TBLPTR (Table Pointer) Register ...................... 82
Erasing External Memory
Associated Registers ............................................... 129
LATE Register .......................................................... 127
PORTE Register ...................................................... 127
PSP Mode Select (PSPMODE Bit) .......................... 138
RE0/RD Pin .............................................................. 138
RE1/WR Pin ............................................................. 138
RE2/CS Pin .............................................................. 138
TRISE Register ........................................................ 127
PORTF
Associated Registers ............................................... 131
LATF Register .......................................................... 130
PORTF Register ...................................................... 130
TRISF Register ........................................................ 130
(PIC18F8XJ10/8XJ15) ....................................... 83
Instructions ................................................................ 63
Two-Word .......................................................... 63
Interrupt Vector .......................................................... 56
Look-up Tables .......................................................... 61
Maps
Program Memory Modes ................................... 58
Memory Maps ............................................................ 55
Hard Vectors and Configuration Words ............. 56
Modes ........................................................................ 57
Address Shifting
(Extended Microcontroller) ........................ 58
Extended Microcontroller ................................... 57
Memory Access (table) ...................................... 58
Microcontroller ................................................... 57
Reset Vector .............................................................. 56
Table Reads and Table Writes .................................. 81
Writing and Erasing (ICSP) ....................................... 84
Writing To
PORTG
Associated Registers ............................................... 133
LATG Register ......................................................... 132
PORTG Register ...................................................... 132
TRISG Register ........................................................ 132
PORTH
Associated Registers ............................................... 135
LATH Register ......................................................... 134
PORTH Register ...................................................... 134
TRISH Register ........................................................ 134
PORTJ
Associated Registers ............................................... 137
LATJ Register .......................................................... 136
PORTJ Register ....................................................... 136
TRISJ Register ......................................................... 136
Power-Managed Modes ..................................................... 35
and EUSART Operation ........................................... 229
and Multiple Sleep Commands .................................. 36
and SPI Operation ................................................... 191
Clock Transitions and
Unexpected Termination ................................... 83
Writing to
Program Memory Space
(PIC18F8XJ10/8XJ15) .............................. 83
Write Verify ........................................................ 83
Program Memory Modes
Operation of the External Memory Bus ..................... 88
Program Verification and Code Protection ...................... 278
Programming, Device Instructions ................................... 279
PSP.See Parallel Slave Port.
Status Indicators ................................................ 36
Entering ...................................................................... 35
Exiting Idle and Sleep Modes .................................... 41
by Reset ............................................................. 41
by WDT Time-out ............................................... 41
Without an Oscillator
Pulse-Width Modulation. See PWM (CCP Module)
and PWM (ECCP Module).
Start-up Delay ............................................ 41
Idle Modes ................................................................. 39
PRI_IDLE ........................................................... 40
RC_IDLE ............................................................ 41
SEC_IDLE ......................................................... 40
Run Modes ................................................................. 36
PRI_RUN ........................................................... 36
RC_RUN ............................................................ 38
SEC_RUN .......................................................... 36
Selecting .................................................................... 35
Sleep Mode ................................................................ 39
Summary (table) ........................................................ 35
Power-on Reset (POR) ...................................................... 45
Power-up Timer (PWRT) ........................................... 46
Time-out Sequence .................................................... 46
Power-up Delays ................................................................ 33
Power-up Timer (PWRT) ............................................. 33, 46
Prescaler
PUSH ............................................................................... 308
PUSH and POP Instructions .............................................. 60
PUSHL ............................................................................. 324
PWM (CCP Module)
Associated Registers ............................................... 166
Duty Cycle ............................................................... 164
Example Frequencies/Resolutions .......................... 165
Operation Setup ...................................................... 165
Period ...................................................................... 164
TMR2 to PR2 Match ........................................ 164, 171
TMR4 to PR4 Match ................................................ 157
PWM (ECCP Module) ...................................................... 171
Associated Registers ............................................... 182
CCPR1H:CCPR1L Registers .................................. 171
Direction Change in Full-Bridge
Output Mode .................................................... 176
Duty Cycle ............................................................... 172
Effects of a Reset .................................................... 181
Enhanced PWM Auto-Shutdown ............................. 178
Example Frequencies/Resolutions .......................... 172
Full-Bridge Application Example .............................. 176
Full-Bridge Mode ..................................................... 175
Half-Bridge Mode ..................................................... 174
Timer2 ...................................................................... 172
Prescaler, Timer0 ............................................................. 143
Prescaler, Timer2 ............................................................. 165
PRI_IDLE Mode ................................................................. 40
PRI_RUN Mode ................................................................. 36
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 383
PIC18F87J10 FAMILY
Half-Bridge Output Mode
RCSTAx (Receive Status and Control) .................... 227
SSPxCON1 (MSSPx Control 1,
I C Mode) ........................................................ 195
SSPxCON1 (MSSPx Control 1,
Applications Example .......................................174
Output Configurations ..............................................172
Output Relationships (Active-High) ..........................173
Output Relationships (Active-Low) ...........................173
Period .......................................................................171
Programmable Dead-Band Delay ............................178
Setup for PWM Operation ........................................181
Start-up Considerations ...........................................179
2
SPI Mode) ........................................................ 185
SSPxCON2 (MSSPx Control 2,
2
I C Mode) ........................................................ 196
SSPxSTAT (MSSPx Status,
2
I C Mode) ........................................................ 194
SSPxSTAT (MSSPx Status,
Q
SPI Mode) ........................................................ 184
STATUS .................................................................... 73
STKPTR (Stack Pointer) ............................................ 60
T0CON (Timer0 Control) ......................................... 141
T1CON (Timer1 Control) ......................................... 145
T2CON (Timer2 Control) ......................................... 151
T3CON (Timer3 Control) ......................................... 153
T4CON (Timer 4 Control) ........................................ 157
TXSTAx (Transmit Status and Control) ................... 226
WDTCON (Watchdog Timer Control) ...................... 273
Reset ................................................................................. 43
MCLR Reset, During
Q Clock .................................................................... 165, 172
R
RAM. See Data Memory.
RC_IDLE Mode ..................................................................41
RC_RUN Mode ..................................................................38
RCALL ..............................................................................309
RCON Register
Bit Status During Initialization ....................................48
Reader Response ............................................................388
Register File .......................................................................67
Registers
Power-Managed Modes .................................... 43
MCLR Reset, Normal Operation ................................ 43
Power-on Reset (POR) .............................................. 43
Programmable Brown-out Reset (BOR) .................... 43
Stack Full Reset ......................................................... 43
Stack Underflow Reset .............................................. 43
Watchdog Timer (WDT) Reset .................................. 43
Resets .............................................................................. 267
Brown-out Reset (BOR) ........................................... 267
Oscillator Start-up Timer (OST) ............................... 267
Power-on Reset (POR) ............................................ 267
Power-up Timer (PWRT) ......................................... 267
RETFIE ............................................................................ 310
RETLW ............................................................................ 310
RETURN .......................................................................... 311
Return Address Stack ........................................................ 59
Return Stack Pointer (STKPTR) ........................................ 60
RLCF ............................................................................... 311
RLNCF ............................................................................. 312
RRCF ............................................................................... 312
RRNCF ............................................................................ 313
ADCON0 (A/D Control 0) .........................................247
ADCON1 (A/D Control 1) .........................................248
ADCON2 (A/D Control 2) .........................................249
BAUDCONx (Baud Rate Control) ............................228
CCPxCON (CCP Control,
CCP4 and CCP5) .............................................159
CCPxCON (Enhanced Capture/Compare/
PWM Control) ..................................................167
CMCON (Comparator Control) ................................257
CONFIG1H (Configuration 1 High) ..........................269
CONFIG1L (Configuration 1 Low) ............................269
CONFIG2H (Configuration 2 High) ..........................270
CONFIG2L (Configuration 2 Low) ............................270
CONFIG3H (Configuration 3 High) ..........................271
CONFIG3H (Configuration 3 Low) ...........................271
CONFIG3L (Configuration 3 Low) ..............................57
CVRCON (Comparator Voltage
Reference Control) ...........................................263
Device ID Register 1 ................................................272
Device ID Register 2 ................................................272
ECCPxAS (ECCP Auto-Shutdown
S
Control) ............................................................179
ECCPxDEL (PWM Configuration) ............................178
INTCON (Interrupt Control) ......................................101
INTCON2 (Interrupt Control 2) .................................102
INTCON3 (Interrupt Control 3) .................................103
IPR1 (Peripheral Interrupt Priority 1) ........................110
IPR2 (Peripheral Interrupt Priority 2) ........................111
IPR3 (Peripheral Interrupt Priority 3) ........................112
MEMCON (External Memory Bus Control) ................86
OSCCON (Oscillator Control) ....................................32
OSCTUNE (PLL Control) ...........................................29
PIE1 (Peripheral Interrupt Enable 1) ........................107
PIE2 (Peripheral Interrupt Enable 2) ........................108
PIE3 (Peripheral Interrupt Enable 3) ........................109
PIR1 (Peripheral Interrupt Request
SCKx ................................................................................ 183
SDIx ................................................................................. 183
SDOx ............................................................................... 183
SEC_IDLE Mode ............................................................... 40
SEC_RUN Mode ................................................................ 36
Serial Clock, SCKx .......................................................... 183
Serial Data In (SDIx) ........................................................ 183
Serial Data Out (SDOx) ................................................... 183
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 313
Slave Select (SSx) ........................................................... 183
SLEEP ............................................................................. 314
Sleep
OSC1 and OSC2 Pin States ...................................... 33
Sleep Mode ........................................................................ 39
Software Simulator (MPLAB SIM) ................................... 330
Software Simulator (MPLAB SIM30) ............................... 330
Special Event Trigger.
(Flag) 1) ...........................................................104
PIR2 (Peripheral Interrupt Request
(Flag) 2) ...........................................................105
PIR3 (Peripheral Interrupt Request
(Flag) 3) ...........................................................106
PSPCON (Parallel Slave Port Control) ....................139
RCON (Reset Control) ....................................... 44, 113
See Compare (ECCP Module).
Special Features of the CPU ........................................... 267
DS39663A-page 384
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
Special Function Registers ................................................ 68
Map ............................................................................ 68
SPI Mode (MSSP)
Resetting, Using the CCP
Special Event Trigger ...................................... 148
Special Event Trigger (ECCP) ................................. 170
TMR1H Register ...................................................... 145
TMR1L Register ...................................................... 145
Use as a Clock Source ............................................ 147
Use as a Real-Time Clock ....................................... 148
Timer2 ............................................................................. 151
Associated Registers ............................................... 152
Interrupt ................................................................... 152
Operation ................................................................. 151
Output ...................................................................... 152
PR2 Register ................................................... 164, 171
TMR2 to PR2 Match Interrupt .......................... 164, 171
Timer3 ............................................................................. 153
16-Bit Read/Write Mode .......................................... 155
Associated Registers ............................................... 155
Operation ................................................................. 154
Oscillator .......................................................... 153, 155
Overflow Interrupt ............................................ 153, 155
Special Event Trigger (ECCP) ................................. 155
TMR3H Register ...................................................... 153
TMR3L Register ...................................................... 153
Timer4 ............................................................................. 157
Associated Registers ............................................... 158
Operation ................................................................. 157
Postscaler. See Postscaler, Timer4.
Associated Registers ............................................... 192
Bus Mode Compatibility ........................................... 191
Clock Speed and Module Interactions ..................... 191
Effects of a Reset ..................................................... 191
Enabling SPI I/O ...................................................... 187
Master Mode ............................................................ 188
Master/Slave Connection ......................................... 187
Operation ................................................................. 186
Operation in Power-Managed Modes ...................... 191
Serial Clock .............................................................. 183
Serial Data In ........................................................... 183
Serial Data Out ........................................................ 183
Slave Mode .............................................................. 189
Slave Select ............................................................. 183
Slave Select Synchronization .................................. 189
SPI Clock ................................................................. 188
Typical Connection .................................................. 187
SSP
TMR4 Output for Clock Shift .................................... 158
SSPOV ............................................................................. 214
SSPOV Status Flag ......................................................... 214
SSPSTAT Register
R/W Bit ..................................................................... 198
SSPxSTAT Register
R/W Bit ..................................................................... 197
SSx .................................................................................. 183
Stack Full/Underflow Resets .............................................. 61
SUBFSR .......................................................................... 325
SUBFWB .......................................................................... 314
SUBLW ............................................................................ 315
SUBULNK ........................................................................ 325
SUBWF ............................................................................ 315
SUBWFB .......................................................................... 316
SWAPF ............................................................................ 316
PR4 Register ........................................................... 157
Prescaler. See Prescaler, Timer4.
SSP Clock Shift ....................................................... 158
TMR4 Register ........................................................ 157
TMR4 to PR4 Match Interrupt .......................... 157, 158
Timing Diagrams
A/D Conversion ....................................................... 368
Acknowledge Sequence .......................................... 217
Asynchronous Reception ......................................... 238
Asynchronous Transmission ................................... 236
Asynchronous Transmission
(Back to Back) ................................................. 236
Automatic Baud Rate Calculation ............................ 234
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 239
Auto-Wake-up Bit (WUE) During Sleep ................... 239
Baud Rate Generator with Clock Arbitration ............ 211
BRG Overflow Sequence ........................................ 234
BRG Reset Due to SDAx Arbitration
During Start Condition ..................................... 220
Brown-out Reset (BOR) ........................................... 356
Bus Collision During a Repeated
T
Table Pointer Operations (table) ........................................ 82
Table Reads/Table Writes ................................................. 61
TBLRD ............................................................................. 317
TBLWT ............................................................................. 318
Timer0 .............................................................................. 141
Associated Registers ............................................... 143
Operation ................................................................. 142
Overflow Interrupt .................................................... 143
Prescaler .................................................................. 143
Prescaler Assignment (PSA Bit) .............................. 143
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 143
Prescaler. See Prescaler, Timer0.
Start Condition (Case 1) .................................. 221
Bus Collision During a Repeated
Reads and Writes in 16-Bit Mode ............................ 142
Source Edge Select (T0SE Bit) ................................ 142
Source Select (T0CS Bit) ......................................... 142
Switching Prescaler Assignment .............................. 143
Timer1 .............................................................................. 145
16-Bit Read/Write Mode ........................................... 147
Associated Registers ............................................... 149
Interrupt .................................................................... 148
Low-Power Option ................................................... 147
Operation ................................................................. 146
Oscillator .......................................................... 145, 147
Layout Considerations ..................................... 148
Start Condition (Case 2) .................................. 221
Bus Collision During a Start Condition
(SCLx = 0) ....................................................... 220
Bus Collision During a Stop Condition
(Case 1) ........................................................... 222
Bus Collision During a Stop Condition
(Case 2) ........................................................... 222
Bus Collision During Start Condition
(SDAx Only) ..................................................... 219
Bus Collision for Transmit and
Acknowledge ................................................... 218
Capture/Compare/PWM (Including
Oscillator, as Secondary Clock .................................. 30
Overflow Interrupt .................................................... 145
ECCP Modules) ............................................... 358
CLKO and I/O .......................................................... 353
2005 Microchip Technology Inc.
Advance Information
DS39663A-page 385
PIC18F87J10 FAMILY
Clock Synchronization .............................................204
Clock/Instruction Cycle ..............................................62
EUSART Synchronous Receive
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ...................... 46
Time-out Sequence on Power-up
(Master/Slave) ..................................................367
EUSART Synchronous Transmission
(MCLR Not Tied to VDD), Case 2 ...................... 47
Time-out Sequence on Power-up
(Master/Slave) ..................................................367
Example SPI Master Mode (CKE = 0) .....................359
Example SPI Master Mode (CKE = 1) .....................360
Example SPI Slave Mode (CKE = 0) .......................361
Example SPI Slave Mode (CKE = 1) .......................362
External Clock (All Modes Except PLL) ...................351
External Memory Bus for Sleep
(MCLR Tied to VDD, VDD Rise < TPWRT) ........... 46
Timer0 and Timer1 External Clock .......................... 357
Transition for Entry to Idle Mode ................................ 40
Transition for Entry to SEC_RUN Mode .................... 37
Transition for Entry to Sleep Mode ............................ 39
Transition for Two-Speed Start-up
(INTRC to HSPLL) ........................................... 275
Transition for Wake from Idle to
Run Mode .......................................................... 40
Transition for Wake from Sleep (HSPLL) .................. 39
Transition from RC_RUN Mode to
(Extended Microcontroller Mode) ................. 92, 94
External Memory Bus for TBLRD
(Extended Microcontroller Mode) ................. 92, 94
Fail-Safe Clock Monitor ............................................277
First Start Bit Timing ................................................212
Full-Bridge PWM Output ..........................................175
Half-Bridge Output ...................................................174
PRI_RUN Mode ................................................. 38
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 37
Transition to RC_RUN Mode ..................................... 38
Timing Diagrams and Specifications
2
I C Bus Data ............................................................363
2
I C Bus Start/Stop Bits .............................................363
2
I C Master Mode (7 or 10-Bit
A/D Conversion Requirements ................................ 369
AC Characteristics
Internal RC Accuracy ....................................... 352
Capture/Compare/PWM Requirements
Transmission) ..................................................215
I C Master Mode (7-Bit Reception) ..........................216
I C Slave Mode (10-Bit Reception,
2
2
SEN = 0) ..........................................................201
I C Slave Mode (10-Bit Reception,
SEN = 1) ..........................................................206
I C Slave Mode (10-Bit Transmission) .....................202
I C Slave Mode (7-bit Reception, SEN = 0) .............199
I C Slave Mode (7-Bit Reception, SEN = 1) ............205
I C Slave Mode (7-Bit Transmission) .......................200
I C Slave Mode General Call Address
(Including ECCP Modules) .............................. 358
CLKO and I/O Requirements ........................... 353, 354
EUSART Synchronous Receive
Requirements .................................................. 367
EUSART Synchronous Transmission
Requirements .................................................. 367
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 359
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 360
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 361
Example SPI Slave Mode Requirements
2
2
2
2
2
2
Sequence (7 or 10-Bit Address Mode) .............207
I C Stop Condition Receive or
2
Transmit Mode .................................................217
2
Master SSP I C Bus Data ........................................365
2
Master SSP I C Bus Start/Stop Bits ........................365
Parallel Slave Port (PSP) Read ...............................140
Parallel Slave Port (PSP) Write ...............................139
Program Memory Read ............................................354
Program Memory Write ............................................355
PWM Auto-Shutdown (P1RSEN = 0,
(CKE = 1) ......................................................... 362
External Clock Requirements .................................. 351
I C Bus Data Requirements
2
(Slave Mode) ................................................... 364
I C Bus Start/Stop Bits Requirements
2
Auto-Restart Disabled) .....................................180
PWM Auto-Shutdown (P1RSEN = 1,
Auto-Restart Enabled) .....................................180
PWM Direction Change ...........................................177
PWM Direction Change at Near
100% Duty Cycle .............................................177
PWM Output ............................................................164
Repeated Start Condition .........................................213
Reset, Watchdog Timer (WDT),
(Slave Mode) ................................................... 363
2
Master SSP I C Bus Data Requirements ................ 366
2
Master SSP I C Bus Start/Stop Bits
Requirements .................................................. 365
Parallel Slave Port Requirements ............................ 358
PLL Clock ................................................................ 352
Program Memory Write Requirements .................... 355
Reset, Watchdog Timer,
Oscillator Start-up Timer,
Oscillator Start-up Timer (OST)
Power-up Timer and Brown-out
and Power-up Timer (PWRT) ..........................356
Send Break Character Sequence ............................240
Slave Synchronization .............................................189
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................47
SPI Mode (Master Mode) .........................................188
SPI Mode (Slave Mode, CKE = 0) ...........................190
SPI Mode (Slave Mode, CKE = 1) ...........................190
Synchronous Reception
Reset Requirements ........................................ 356
Timer0 and Timer1 External
Clock Requirements ........................................ 357
Top-of-Stack Access .......................................................... 59
TRISE Register
PSPMODE Bit .......................................................... 138
TSTFSZ ........................................................................... 319
Two-Speed Start-up ................................................. 267, 275
Two-Word Instructions
(Master Mode, SREN) ......................................243
Synchronous Transmission ......................................241
Synchronous Transmission
Example Cases .......................................................... 63
TXSTAx Register
BRGH Bit ................................................................. 229
(Through TXEN) ...............................................242
DS39663A-page 386
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10 FAMILY
V
VDDCORE/VCAP Pin ........................................................... 274
Voltage Reference Specifications .................................... 348
Voltage Regulator (On-Chip) ........................................... 274
W
Watchdog Timer (WDT) ........................................... 267, 273
Associated Registers ............................................... 273
Control Register ....................................................... 273
During Oscillator Failure .......................................... 276
Programming Considerations .................................. 273
WCOL ...................................................... 212, 213, 214, 217
WCOL Status Flag ................................... 212, 213, 214, 217
WWW Address ................................................................. 387
WWW, On-Line Support ...................................................... 4
X
XORLW ............................................................................ 319
XORWF ............................................................................ 320
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DS39663A-page 387
PIC18F87J10 FAMILY
NOTES:
DS39663A-page 388
Advance Information
2005 Microchip Technology Inc.
PIC18F87J10
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
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To register, access the Microchip web site at
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DS39663A-page 389
PIC18F87J10
READER RESPONSE
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PIC18F87J10
DS39663A
Literature Number:
Device:
Questions:
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PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
b)
PIC18F86J10-I/PT 301 = Industrial temp.,
TQFP package, QTP pattern #301.
PIC18F65J15T-I/PT = Tape and reel, Industrial
temp., TQFP package.
Device
PIC18F65J10/65J15/66J10/66J15/67J10(1)
PIC18F85J10/85J15/86J10/86J15/87J10(1)
,
,
PIC18F65J10/65J15/66J10/66J15/67J10T(2)
PIC18F85J10/85J15/86J10/86J15/87J10T(2)
,
;
Temperature Range
Package
I
= -40°C to +85°C (Industrial)
PT
=
TQFP (Thin Quad Flatpack)
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
Note 1:
2:
F
T
=
=
Standard Voltage Range
in tape and reel
2005 Microchip Technology Inc.
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DS39663A-page 391
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10/20/04
DS39663A-page 392
Advance Information
2005 Microchip Technology Inc.
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