PIC18F010-I/SO [MICROCHIP]
High Performance Microcontrollers; 高性能微控制器
| 型号： | PIC18F010-I/SO |
| 厂家： | 
MICROCHIP |
| 描述： | High Performance Microcontrollers |
| 文件： | 总176页 (文件大小：2438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F010/020
Data Sheet
High Performance Microcontrollers
2001 Microchip Technology Inc.
Preliminary
DS41142A
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Trademarks
The Microchip name, logo, PIC, PICmicro, PICMASTER, PIC-
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© 2001, Microchip Technology Incorporated, Printed in the
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DS41142A - page ii
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
High Performance Microcontrollers
High Performance RISC CPU:
Pinout Diagram:
• C compiler optimized instruction set
• Linear program memory addressing
- 4096 x 8 on-chip FLASH program memory
PDIP, SOIC
VSS
VDD
RB5/OSC1/CLKIN
RB4/OSC2/CLKOUT
RB3/MCLR/VPP
1
2
3
4
8
7
6
5
RB0/ICSPDAT
RB1/ICSPCLK
RB2/T0CKI/INT0
- 2048 x 8 on-chip FLASH program memory
(PIC18F010)
• Linear data memory addressing
- 256 x 8 general purpose registers
- 64 x 8 EEPROM
• Operating speed:
- DC - 40MHz clock input
- DC - 100 ns instruction cycle
CMOS Technology:
• Low power, high speed CMOS FLASH technology
• Fully static design
- Internal oscillator with 5 program
selectable speeds (32kHz, 500kHz, 1MHz,
4MHz, 8MHz)
• Wide operating voltage range (2.0V to 5.5V)
• 2.0V operation (4MHz)
• Commercial, Industrial and Extended
temperature ranges
• 16-bit wide instructions
• Low power consumption
• 8-bit wide data path
• 31 levels of hardware stack
• Software stack capability
• Multi-vector interrupt capability
• 8 x 8 multiply single cycle hardware
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR)
• Programmable Low Voltage Detection circuitry
(PLVD)
• Watchdog Timer (WDT) with its own on-chip
RC oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode with Wake-up on Pin
Change
• In-Circuit Serial Programming (ICSPTM) via two
pins
• Low cost MPLAB® ICD available
Peripheral Features:
• High current sink/source 25mA/25mA
• Timer0: 8-bit/16-bit timer/counter with 8-bit
programmable prescaler
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 1
PIC18F010/020
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Device Overview ................................................................................................................................................3
Oscillator Configurations ....................................................................................................................................7
Reset................................................................................................................................................................15
Memory Organization.......................................................................................................................................23
Data EEPROM Memory ...................................................................................................................................43
Table Read/Write Instructions..........................................................................................................................47
8 X 8 Hardware Multiplier.................................................................................................................................55
Interrupts..........................................................................................................................................................59
I/O Port.............................................................................................................................................................67
Timer0 Module .................................................................................................................................................73
Low Voltage Detect ..........................................................................................................................................77
Special Features of the CPU............................................................................................................................83
Instruction Set Summary..................................................................................................................................95
Development Support.....................................................................................................................................139
Electrical Characteristics................................................................................................................................145
DC and AC Characteristics Graphs and Tables.............................................................................................157
Packaging Information....................................................................................................................................159
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
Appendix A: Conversion Considerations ..................................................................................................................163
Appendix B: Migration from Baseline to Enhanced Devices.....................................................................................163
Appendix C: Migration from Mid-range to Enhanced Devices ..................................................................................164
Appendix D: Migration from High-end to Enhanced Devices....................................................................................164
Index .......................................................................................................................................................................165
On-Line Support..........................................................................................................................................................169
Reader Response .......................................................................................................................................................170
PIC18F010/020 Product Identification System............................................................................................................171
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DS41142A-page 2
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
1.0
DEVICE OVERVIEW
This document contains device specific information for
the PIC18F010/020 microcontrollers. These devices
come in 8-pin packages. Table 1-1 is an overview of the
features. Figure 1-1 presents the block diagram for the
PIC18F010/020 devices and Table 1-2 gives the pin
descriptions.
TABLE 1-1:
DEVICE FEATURES
Features
PIC18F010
PIC18F020
Operating Frequency
DC - 40 MHz
DC - 40 MHz
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (SRAM)
Data Memory (EEPROM)
Interrupt Sources
2K
4K
1024
2048
256
256
64
5
64
5
I/O Ports
PORTB (6-bit)
1 (8/16-bit)
PORTB (6-bit)
1 (8/16-bit)
Timers
RESETS (and Delays)
POR, BOR,
RESETInstruction,
Stack Full,
POR, BOR,
RESETInstruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Stack Underflow
(PWRT, OST)
Programmable Low Voltage Detect
Programmable Brown-out Reset
Instruction Set
Yes
Yes
75
Yes
Yes
75
Packages
8-pin PDIP
8-pin SOIC
8-pin PDIP
8-pin SOIC
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 3
PIC18F010/020
FIGURE 1-1:
PIC18F010/020 BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
inc/dec logic
Data Latch
21
8
8
Data RAM
256 bytes
21
Address Latch
20
PCLATU
PCU
PCLATH
PORTB
12
RB0/ICSPDAT
Address<12>
PCH PCL
RB1/ICSPCLK
Program Counter
4
12
FSR0
FSR1
FSR2
4
RB2/T0CKI/INT0
RB3/MCLR/VPP
RB4/OSC2/CLKOUT
RB5/OSC1/CLKIN
BSR
Bank0,F
Address Latch
Program Memory
(4 Kbytes)
31 Level Stack
12
Data Latch
inc/dec
logic
Decode
Table Latch
8
16
ROM Latch
IR
8
PRODH PRODL
8 x 8 Multiply
Instruction
Decode &
Control
8
3
W
8
BITOP
8
8
Power-up
Timer
OSC2/CLKOUT
OSC1/CLKIN
Timing
Generation
Oscillator
Start-up Timer
8
ALU<8>
8
Power-on
Reset
Internal
Oscillator
Watchdog
Timer
Brown-out
Reset
Test Mode
Select
MCLR
VDD, VSS
BOR
PLVD
Timer0
EEDATA
64 bytes
DATA
EEPROM
EEADDR
DS41142A-page 4
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
TABLE 1-2:
PIC18F010/020 PRODUCT PINOUT OVERVIEW
Devices
Bondpad Name
Function/Description
8-Pin PDIP
8-Pin SOIC
VDD
1
8
2
1
8
2
Power
VSS
Ground
RB5/OSC1/CLKIN
Bi-directional I/O pin (TTL) with optional interrupt-on-change, clock
input, or oscillator input
RB4/OSC2/CLKOUT
RB3/MCLR/VPP
3
4
5
3
4
5
Bi-directional I/O pin (TTL) with optional interrupt-on-change,
oscillator output, or CLKOUT output
Bi-directional I/O pin (TTL), open drain, with optional
interrupt-on-change, or Master Clear External Reset input (ST)
RB2/T0CKI/INT0
Bi-directional I/O pin (TTL) with optional interrupt-on-change, TMR0
clock input (ST), or interrupt input (ST)
RB1
RB0
6
7
6
7
Bi-directional I/O pin (TTL) with optional interrupt-on-change
Bi-directional I/O pin (TTL) with optional interrupt-on-change
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 5
PIC18F010/020
NOTES:
DS41142A-page 6
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
FIGURE 2-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS, XT OR LP
2.0
2.1
OSCILLATOR
CONFIGURATIONS
OSC CONFIGURATION)
Oscillator Types
(1)
The PIC18F010/020 can be operated in eight different
oscillator modes. Programming these modes is done
via the CONFIG1H register (FOSC2, FOSC1, and
FOSC0).
C1
OSC1
To
internal
logic
XTAL
(3)
RF
1. LP
2. XT
3. HS
4. EC
5. RC
6. RCIO
Low Power Crystal
SLEEP
(2)
Crystal/Resonator
RS
(1)
C2
High Speed Crystal/Resonator
External Clock
OSC2
Note 1: See Table 2-1 and Table 2-2 for recom-
External Resistor/Capacitor
mended values of C1 and C2.
External Resistor/Capacitor with
I/O pin enabled
2: A series resistor (RS) may be required for AT
strip cut crystals.
7. INTOSC
Precision Internal Oscillator
3: RF varies with the crystal chosen.
8. INTOSCIO Precision Internal Oscillator with
I/O pin enabled
2.2
Crystal Oscillator/Ceramic
Resonators
FIGURE 2-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC CONFIGURATION)
In XT, LP, or HS oscillator modes, a crystal or ceramic
resonator is connected to the RB5/OSC1 and RB4/
OSC2 pins to establish oscillation. Figure 2-1 shows the
pin connections. An external clock source may also be
connected to the OSC1 pin in these modes, as shown in
Figure 2-2.
RB5/OSC1
Clock from
ext. system
PIC18F010/020
RB4/OSC2
Open
The PIC18F010/020 oscillator design requires the use
of a parallel cut crystal.
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers
specifications.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 7
PIC18F010/020
TABLE 2-1:
CERAMIC RESONATORS
2.3
RC Oscillator
Ranges Tested:
For applications where precise timing is not a require-
ment, the RC and RCIO oscillator options are available.
The operation and functionality of the RC oscillator is
dependent on a number of variables. The RC oscillator
is a function of the supply voltage, the resistor (REXT)
and capacitor (CEXT) values, and the operating temper-
ature. The oscillator frequency will vary from unit to unit
due to normal process parameter variation. Plus, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency, espe-
cially for low CEXT values. The user also needs to
account for the tolerance of the external R and C com-
ponents. Figure 2-3 shows how the R/C combination is
connected.
Mode
Freq.
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
68 - 100 pF 68 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
HS
These values are for design guidance only.
See notes at bottom of page.
Resonators Used:
455 kHz Panasonic EFO-A455K04B
0.3%
0.5%
0.5%
0.5%
0.5%
2.0 MHz
4.0 MHz
8.0 MHz
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Note: The RC oscillator is not recommended for
applications that require precise timing.
16.0 MHz Murata Erie CSA16.00MX
All resonators used did not have built-in capacitors.
FIGURE 2-3:
RC OSCILLATOR MODE
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
VDD
REXT
Crystal
Freq.
Cap. Range
C1
Cap.
Range C2
Osc Type
Internal
OSC1
Clock
LP
32.0 kHz
200 kHz
200 kHz
1.0 MHz
4.0 MHz
4.0 MHz
8.0 MHz
20.0 MHz
25.0 MHz
33 pF
15 pF
33 pF
15 pF
CEXT
VSS
PIC18F010/020
XT
HS
47-68 pF
15 pF
47-68 pF
15 pF
OSC2/CLKO
FOSC/4
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
15 pF
15 pF
CEXT > 20pF
15 pF
15 pF
15-33 pF
15-33 pF
TBD
15-33 pF
15-33 pF
TBD
In the RC mode, the oscillator frequency divided by 4 is
available on the OSC2 pin. This signal may be used for
test purposes, or to synchronize other logic. In the
RCIO mode, the OSC2 pin becomes a general purpose
I/O pin. This pin is RB4 of PORTB.
These values are for design guidance only.
See notes at bottom of page.
Crystals Used
2.4
The Internal Oscillator
32.0 kHz Epson C-001R32.768K-A
200 kHz STD XTL 200.000KHz
1.0 MHz ECS ECS-10-13-1
4.0 MHz ECS ECS-40-20-1
± 20 PPM
The INTOSC and INTOSCIO device options are avail-
able to minimize part count and cost, while maximizing
the number of I/O pins. There are five different frequen-
cies of which the user has the option to select. They are
32 kHz, 500 kHz, 1 MHz, 4 MHz, and 8 MHz. The 1
MHz, 4 MHz, and 8 MHz internal clock selections are
all derived from one 8 MHz clock source, and the other
two are produced independently. Tuning is available for
the 1 MHz, 4 MHz, and 8 MHz options; refer to
Section 2.10.
± 20 PPM
± 50 PPM
± 50 PPM
8.0 MHz EPSON CA-301 8.000M-C ± 30 PPM
20.0 MHz EPSON CA-301 20.000M-C ± 30 PPM
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 2-1).
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
4: Rs may be required in HS mode, as well as
XT mode, to avoid overdriving crystals with
low drive level specification.
DS41142A-page 8
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
2.5
External Clock Input
The EC oscillator mode requires an external clock
source to be connected to the OSC1 pin. The feedback
device between OSC1 and OSC2 is turned off in this
mode to save current. There is no oscillator start-up
time required after a Power-on Reset or after a recov-
ery from SLEEP mode.
OSC1
Clock from
ext. system
PIC18F010/020
OSC2
FOSC/4
In the EC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
oscillator mode.
FIGURE 2-5:
PIC18F010/020 OSCILLATOR CONFIGURATION
32kHz
Internal
OSC
500kHz
Internal
OSC
8MHz
Internal
OSC
Divider
Configuration bits
8
2
1
IRCF Speed Selects
MUX
Analog
Summation
+
OSCCAL
OSCTUNE
OSCOUT
Ext Osc
and
SYSCLK
Crystal
Osc
OSCIN
External Clock In
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 9
PIC18F010/020
After the OST has timed out, a glitchless switchover will
be made to the oscillator mode selected by FOSCx in
the CONFIG1H register. The software may read the
OSTO bit to determine when the switchover takes
place, so that any software timing delays may be
adjusted.
2.6
Two-Speed Clock Start-up Mode
In order to minimize the latency between oscillator
start-up and code execution, a mode which allows the
system clock to initially use the internal clock, may be
selected with IESO (Internal-External Switchover) bit.
In this mode and upon RESET, the system will begin
execution with the internal oscillator at the frequency
selected by the IRCFx bits of the OSCCON register.
Wake-up from SLEEP causes a unique start-up proce-
dure. The power supply is assumed to be stable, since
neither the POR nor the BOR Resets have been
invoked. This assumption allows the Power-on Timer
(PWRT) time-out to be bypassed, and only the OST
time-out to be used. This results in almost immediate
code execution with the minimum of delay. The internal
oscillator frequency can be selected to be close to final
crystal frequency to reduce timing differences, or a lower
frequency can be chosen to reduce power consumption.
Note: Only on Power-on Reset, the register con-
tents are zeroed by the POR circuitry and
the frequency selection is forced to 32 kHz.
The register is not effected by any other
forms of RESET.
REGISTER 2-1:
OSCCON REGISTER (ADDRESS FD3h)
U-0
R/W-0
IRCF2
R/W-0
IRCF1
R/W-0
IRCF0
R-0
R/W-0
IESO
U-0
R/W-0
SCS
—
OSTO
—
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IRCF<2:0>: Internal Oscillator Frequency Select bits
000= 32 kHz
001= Reserved
010= Reserved
011= 500 kHz
100= 1 MHz
101= Reserved
110= 4 MHz
111= 8 MHz
bit 3
bit 2
OSTO: Oscillator Start-up Time-out Status bit
1= Oscillator Start-up Timer has timed out
0= Oscillator Start-up Timer running
IESO: Internal-External Switchover bit
1= Start with internal oscillator, then switch over to selected oscillator mode after OST
0= No switch from internal oscillator from RESET
bit 1
bit 0
Unimplemented: Read as ‘0’
SCS: System Clock Switch bit
1= Clock source comes from internal oscillator input
0= Clock source comes from external clock source on OSC1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
Note: This register must be unlocked to modify, see Section 12.4.
DS41142A-page 10
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
A timing diagram, indicating the transition from the inter-
nal oscillator to the external crystal is shown in Figure 2-6.
The internal oscillator is assumed to be running all the
time. After the OST bit is set, the processor is frozen at
the next occurring Q1 cycle. After eight synchronization
cycles are counted from the external oscillator, opera-
tion resumes. No additional delays are required after
the synchronization cycles.
2.6.1
OSCILLATOR TRANSITIONS
The PIC18F010/020 devices contain circuitry to pre-
vent "glitches" when switching between oscillator
sources. Essentially, the circuitry waits for eight rising
edges of the clock source that the processor is switch-
ing to. This ensures that the new clock source is stable
and that its pulse width will not be less than the shortest
pulse width of the two clock sources.
FIGURE 2-6:
TIMING DIAGRAM FOR TRANSITION FROM EXTERNAL OSCILLATOR TO
INTERNAL OSCILLATOR
Q1 Q2 Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
1
2
3
4
5
6
7
8
INTOSC
OSC1
TOSC
Internal
System
Clock
OSTO
(OSCCON<0>)
Program
Counter
PC
PC + 2
PC + 4
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
FIGURE 2-7:
TIMING FOR TRANSITION BETWEEN INTERNAL OSCILLATOR AND OSC1 (EC)
Q3
Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
INTOSC
OSC1
TOSC
1
6
4
5
7
8
2
3
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter
PC
PC + 2
PC + 4
Note 1: Internal oscillator mode assumed.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 11
PIC18F010/020
ing currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP will increase the current
consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset or through an interrupt.
2.7
Effects of SLEEP Mode on the
On-chip Oscillator
When the device executes a SLEEPinstruction, the on-
chip clocks and oscillator are turned off and the device
is held at the beginning of an instruction cycle (Q1
state). With the oscillator off, the OSC1 and OSC2 sig-
nals will stop oscillating. Since all the transistor switch-
TABLE 2-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin
OSC Mode
OSC2 Pin
Internal Oscillator
Floating, external resistor should pull
high
At logic low
RCIO
Floating, external resistor should pull
high
Configured as PORTB, RB4
EC
Floating
At logic low
LP, XT, and HS
Feedback inverter disabled, at quiescent Feedback inverter disabled, at quiescent
voltage level voltage level
Note: See Table 3-1 in the RESET Section, for time-outs due to SLEEP and MCLR Reset.
DS41142A-page 12
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
2.8
Power-up Delays
2.10 Frequency Tuning in User Mode
Power-up delays are controlled by two timers, so that
no external RESET circuitry is required for most appli-
cations. The delays ensure that the device is kept in
RESET until the device power supply and clock are sta-
ble. For additional information on RESET operation,
see the “RESET” section.
In addition to the factory calibration, 8 MHz frequency
can be tuned in the user’s application. This frequency
tuning capability allows user to deviate from the factory
calibrated frequency. The user can tune the frequency
by writing to the OSCTUNE register. See Register 2-2
for details of the OSCTUNE register. The tuning range
of the 8 MHz oscillator is ±1 MHz, or ±12.5% nominal.
See the Specifications section for further specification
details.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer OST, intended to keep the
chip in RESET until the crystal oscillator is stable.
Since the 4 MHz and 1 MHz are derived from the 8
MHz, the tuning range of the 4 MHz is ±500 kHz nomi-
nal, and the tuning range of the 1 MHz is ±125 kHz
nominal. The tuning sensitivity (%FINTOSC/bit) is con-
stant throughout the frequency selections and tuning
range.
2.9
Frequency Calibrations
The 8 MHz frequency is calibrated at the factory. Since
the 4 MHz and 1 MHz clock outputs are derived digitally
from the 8 MHz, the accuracy specifications of the 4
MHz and 1 MHz clocks are the same as the 8 MHz.
Note: Frequency tuning is not available in the
500 kHz and 32 kHz frequencies.
The 500 kHz and 32 kHz frequencies are not cali-
brated. The 500 kHz and 32 kHz are nominal frequen-
cies. Their accuracy specifications are shown in the
Specifications section.
REGISTER 2-2:
OSCTUNE REGISTER (ADDRESS 0F9Bh)
U-0
U-0
R/W-0
TUN5
R/W-0
TUN4
R/W-0
TUN3
R/W-0
TUN2
R/W-0
TUN1
R/W-0
TUN0
—
—
bit 7
bit 0
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: 6-bit Frequency Tuning
011111= Maximum frequency
011110
•
•
•
000001
000000= Center frequency. Oscillator module is running at the calibrated frequency.
111111
•
•
•
100000= Minimum frequency
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 13
PIC18F010/020
2.11 Base Frequency Change
2.12 Oscillator Delay Upon Start-up
and Base Frequency Change
There are two methods to change frequency during
normal program operation. One option is to switch fre-
quencies using the internal oscillator only; IRCF<2:0>
in the OSCCON register selects the internal oscillator
frequency. Refer to Register 2-1.
When the INTOSC Oscillator Module starts up, an
8-cycle delay of the base frequency is invoked. During
this delay, the FINTOSC output signal is held at ‘0’.
The INTOSC Oscillator Module also allows user to
change frequency during run time. For example, the
frequency can be changed from 8 MHz to 32 kHz, while
the device is operating. When the application requires
a base frequency change, a delay of 8 cycles of the
new base frequency is invoked.
Switching for an external clock to an internal oscillator
and vice versa is also possible. Use the SCS bit in the
OSCCON register to select an external or internal clock
source.
Note: The OSCEN bit in the CONFIG1H configu-
ration byte must be set to allow clock
switching.
Writing to the OSCTUNE register will not cause any
delay. In applications where the OSCTUNE register is
used to shift the FINTOSC frequency, the application
should not expect the FINTOSC frequency to stabilize
immediately. In this case, the frequency may shift grad-
ually toward the new value. The time for this frequency
shift is less than 8 cycles of the base frequency.
Table 2-4 below, shows examples of when the oscilla-
tor delay is invoked.
TABLE 2-4:
OSCILLATOR DELAY EXAMPLES
New Base
Old Frequency New Frequency
Oscillator Delay
Comments
Frequency
8 MHz
4 MHz or 1 MHz No
None
The 8 MHz, 4 MHz, and 1 MHz are all
running from the same 8 MHz base
frequency.
500 kHz
4 MHz
32 kHz
32 kHz
8 MHz
1 MHz
500 kHz
32 kHz
32 kHz
250µS nominal
250µS nominal
1µS nominal
1µS nominal
16µS nominal
Base frequency changes from 500 kHz
to 32 kHz.
Base frequency changes from 8 MHz to
32 kHz.
500 kHz
8 MHz
8 MHz
500 kHz
Base frequency changes from 500 kHz
to 8 MHz.
Off or SLEEP
mode
Upon power-up and wake-up from
SLEEP, there is always oscillator delay.
Off or SLEEP
mode
Upon power-up and wake-up from
SLEEP, there is always oscillator delay.
DS41142A-page 14
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
state” on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during SLEEP and by the
RESET instruction.
3.0
RESET
The PIC18F010/020 differentiates between various
kinds of RESET:
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
RESET situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
RESET. See Table 3-3 for a full description of the
RESET states of all registers.
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
d) Watchdog Timer (WDT) Reset (during normal
operation)
e) Programmable Brown-out Reset (BOR)
f) RESETInstruction
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 3-1.
g) Stack Full Reset
h) Stack Underflow Reset
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
Most registers are unaffected by a RESET. Their status
is unknown on POR and unchanged by all other
RESETS. The other registers are forced to a “RESET
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLR
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
S
BOREN
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
10-bit Ripple Counter
Q
R
OSC1
PWRT
On-chip
Internal Osc
(1)
Enable PWRT
(2)
Enable OST
Note 1: This is a separate oscillator from the internal oscillator of the CLKIN pin.
2: See Table 3-1 for time-out situations.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 15
PIC18F010/020
3.1
Power-on Reset (POR)
3.2
Power-up Timer (PWRT)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR cir-
cuitry, tie the MCLR pin directly (or through a resistor)
to VDD, or disable MCLR. This will eliminate external
oscillator components usually needed to create a
Power-on Reset delay. A maximum rise time for VDD is
specified (parameter D004). For a slow rise time, see
Figure 3-2.
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR or
BOR, if enabled. The Power-up Timer operates on an
internal oscillator. The chip is kept in RESET as long as
the PWRT is active. The PWRT’s time delay allows
VDD to rise to an acceptable level. A configuration bit is
provided to enable/disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. Brown-out Reset may be used to meet the
voltage start-up condition.
3.3
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
VDD
3.4
Brown-out Reset (BOR)
D
R
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A RESET may not occur if VDD falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. The Power-up Timer will then be invoked and
will keep the chip in RESET an additional time delay
(parameter #33). If VDD drops below BVDD while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initial-
ized. Once VDD rises above BVDD, the Power-up Timer
will execute the additional time delay.
R1
MCLR
PIC18F010/020
C
Note 1: External Power-on Reset circuit is required only
if the VDD power-up slope is too slow. The diode
D helps discharge the capacitor quickly when
VDD powers down.
2: R < 40kΩ is recommended to make sure that
the voltage drop across R does not violate the
device’s electrical specification.
3: R1 = 100Ω to 1kΩ will limit any current flowing
into MCLR from external capacitor C, in the
event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD), or Electrical
Overstress (EOS).
DS41142A-page 16
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18F010/020 device
operating in parallel.
3.5
Time-out Sequence
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after the POR time delay has
expired; then, OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in Internal Oscillator mode
with the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5 and Figure 3-6
depict time-out sequences on power-up.
Table 3-2 shows the RESET conditions for some
Special Function Registers, while Table 3-3 shows the
RESET conditions for all the registers.
TABLE 3-1:
Oscillator
TIME-OUT IN VARIOUS SITUATIONS
Power-up(1)
Wake-up from
SLEEP or
Oscillator Switch
Brown-out(1)
Configuration
PWRTE = 0
PWRTE = 1
HS, XT, LP
EC
External Oscillator
72 ms + 1024Tosc
72 ms
1024Tosc
72 ms + 1024Tosc
72 ms
1024Tosc
—
—
—
—
72 ms
72 ms
Internal Oscillator(2)
72 ms
—
72 ms
—
Note 1: 72 ms is the nominal power-up timer delay.
2: 8-cycle delay.
REGISTER 3-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
IPEN
U-0
U-0
R/W-1
RI
R-1
TO
R-1
PD
R/W-1
POR
R/W-1
BOR
—
—
bit 7
bit 0
TABLE 3-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
Condition
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
0000h
0000h
00-1 1100
00-u uuuu
1
u
1
u
1
u
0
u
0
u
u
u
u
u
MCLR Reset during normal
operation
Software Reset during normal
operation
0000h
0u-0 uuuu
0u-u uu11
0u-u uu11
0
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
1
u
u
u
1
Stack Full Reset during normal 0000h
operation
Stack Underflow Reset during
normal operation
0000h
MCLR Reset during SLEEP
WDT Reset
0000h
0000h
PC + 2
0000h
00-u 10uu
0u-u 01uu
uu-u 00uu
0u-1 11u0
uu-u 00uu
u
1
u
1
u
1
0
0
1
1
0
1
0
1
0
u
u
u
1
u
u
u
u
0
u
u
u
u
u
u
u
u
u
u
u
WDT Wake-up
Brown-out Reset
PC + 2(1)
Interrupt Wake-up from SLEEP
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 17
PIC18F010/020
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Reset
WDT Reset
ResetInstruction
Stack Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
uuuu uuuu(3)
uuuu uuuu(3)
TOSH
TOSL
0000 0000
0000 0000
00-0 0000
0000 0000
0000 0000
00-0 0000
uu-u uuuu(3)
---u uuuu
uuuu uuuu
STKPTR
PCLATU
PCLATH
PCL
---0 0000
0000 0000
0000 0000
---0 0000
0000 0000
0000 0000
PC + 2(2)
---u uu--
---- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
---0 00--
---- 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
---0 00--
---- 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
PRODH
PRODL
uuuu uuuu(1)
INTCON
uu-- -u-u(1)
N/A
INTCON2
11-- -1-1
11-- -1-1
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
xxxx xxxx
N/A
---- 0000
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
---- 0000
N/A
---- 0000
uuuu uuuu
---- 0000
N/A
---- uuuu
uuuu uuuu
---- uuuu
N/A
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: The long write enable is only reset on a POR or MCLR Reset.
DS41142A-page 18
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
ResetInstruction
Stack Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
FSR2H
FSR2L
---- 0000
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
-000 00-0
--00 0101
---- ---0
0--1 11qq
---- 1111
---- 0000
---- 0000
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
-uuu uu-u
--00 0101
---- ---0
0--q qquu
---- 1111
---- 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uu-u
--uu uuuu
---- ---u
u--u qquu
---- uuuu
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON(4,5)
IPR2
---- uuuu(1)
---- uuuu
--uu uuuu
--uu uuuu
--uu uuuu
---- --uu
uuuu uuuu
uuuu uuuu
---- ----
u--u uuuu
--uu uuuu
--uu uuuu
--uu uuuu
PIR2
PIE2
TRISB
---- 0000
--11 1111
--xx xxxx
--xx xxxx
---- --00
xxxx xxxx
xxxx xxxx
---- ----
x--0 x000
--00 0000
--11 1111
--00 0000
---- 0000
--11 1111
--uu uuuu
--uu uuuu
---- --00
uuuu uuuu
uuuu uuuu
---- ----
u--0 u000
--qq qqqq
--11 1111
--00 0000
LATB
PORTB
PSPCON
EEADR
EEDATA
EECON2
EECON1
OSCTUNE
WPUB
IOCB
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: The long write enable is only reset on a POR or MCLR Reset.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 19
PIC18F010/020
FIGURE 3-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 3-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 3-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
DS41142A-page 20
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
FIGURE 3-6:
SLOW RISE TIME (MCLR TIED TO VDD)
5V
1V
0V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
OSCILLATOR
Note: For slow starting crystals, OST can start beyond PWRT.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 21
PIC18F010/020
NOTES:
DS41142A-page 22
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
4.0
MEMORY ORGANIZATION
There are three memory blocks in PIC18F010/020
Enhanced MCU devices. These memory blocks are:
• Program Memory
• Data Memory
• EEPROM Data Memory
The EEPROM Data Memory is described in detail in
Section 5.0.
4.1
Program Memory Organization
The PIC18F010/020 devices have a 21-bit program
counter. Bits 12 through 16 are implemented as ‘0’
internally; therefore, accessing locations 0x01000
through 0x1FFFF actually mirror what is present in pro-
gram memory from 0x0000 through 0x0FFF. The
PIC18F010 device reads all zeros (NOP) from 0x0800
through 0x0FFF.
PIC18F020 has 4 Kbytes of FLASH program memory,
while PIC18F010 has 2 Kbytes of FLASH program
memory. This means the PIC18F020 can store up to 2K
of single word instructions, and the PICF18010 can
store up to 1K of single word instructions.
The RESET vector address is at 0000h and the inter-
rupt vector addresses are at 0008h and 0018h. 0008h
is the high priority interrupt and 0018h is the low priority
interrupt vector.
Figure 4-1 shows the Program Memory Map for
PIC18F010 and Figure 4-2 shows the Program Mem-
ory Map for PIC18F020 devices.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 23
PIC18F010/020
FIGURE 4-1:
PIC18F010 MEMORY
FIGURE 4-2:
PIC18F020 MEMORY
PC<20:0>
PC<20:0>
21
21
Stack Level 1
Stack Level 1
•
•
•
•
•
•
Stack Level 31
Stack Level 31
000000h
000001h
000000h
000001h
RESET Vector LSb
RESET Vector MSb
RESET Vector LSb
RESET Vector MSb
000008h
000009h
000008h
000009h
High Priority Interrupt Vector LSb
High Priority Interrupt Vector MSb
High Priority Interrupt Vector LSb
High Priority Interrupt Vector MSb
000018h
000019h
000018h
000019h
Low Priority Interrupt Vector LSb
Low Priority Interrupt Vector MSb
Low Priority Interrupt Vector LSb
Low Priority Interrupt Vector MSb
User FLASH
User FLASH
Program Memory
0007FFh
000800h
Read ‘0’s
000FFFh
001000h
000FFFh
001000h
Mirror
Mirror
1FFFFFh
200000h
1FFFFFh
200000h
User ID Locations
User ID Locations
200003h
200003h
DS41142A-page 24
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
4.2.2
RETURN STACK POINTER
(STKPTR)
4.2
Return Address Stack
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
PUSH, CALL,or RCALLinstruction is executed, or an
interrupt is acknowledged. The PC value is pulled off
the stack on a POP, RETURN, RETLW, or a RETFIE
instruction. PCLATU and PCLATH are not affected by
any of the return instructions.
The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-1 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At RESET, the stack
pointer value will be 0. The user may read and write the
stack pointer value. This feature can be used by a Real
Time Operating System for return stack maintenance.
The stack operates as a 31-word by 21-bit RAM with a
5-bit stack pointer. Although there are 21 bits in the
TOS latch, bits 12 through 16 are not physically imple-
mented in the stack and are read as zeros. The stack
pointer initializes to 0x00 after all RESETS, and there
is no RAM associated with stack pointer 0x00. This is
only a RESET value. During a CALL type instruction
causing a push onto the stack, the stack pointer is first
incremented and the RAM location pointed to by the
stack pointer is written with the contents of the PC. Dur-
ing a RETURNtype instruction causing a pop from the
stack, the contents of the RAM location pointed to by
the STKPTR is transferred to the PC and then, the
stack pointer is decremented.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) configuration bit. Refer to
Section 12.0 for a description of the device configura-
tion bits. If STVREN is set (default), the 31st push will
push the (PC + 2) value onto the stack, set the STKFUL
bit, and reset the device. The STKFUL bit will remain
set and the stack pointer will be set to 0.
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and
the address on the top of the stack is readable and writ-
able through SFR registers. Data can also be pushed
to, or popped from the stack, using the top-of-stack
SFRs. Status bits indicate if the stack pointer is at, or
beyond, the 31 levels provided.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31.
The 32nd push and beyond will be lost while STKPTR
remains at 31, and the 31st push is maintained.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at 0. The STKUNF bit will remain set
until cleared in software or a POR occurs.
Note: Do not push data onto the stack in bits 12
through 16. This data will be lost. Bits 12
through 16 are always read as ‘0’.
Note: Returning a value of zero to the PC on an
underflow, has the effect of vectoring the
program to the RESET vector, where the
stack conditions can be verified and appro-
priate actions can be taken.
4.2.1
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSH and TOSL hold the contents
of the stack location pointed to by the STKPTR register.
This allows users to implement a software stack, if nec-
essary. After a CALL, RCALLor interrupt, the software
can read the pushed value by reading the TOSH and
TOSL registers. These values can be placed on a user
defined software stack. At return time, the software can
replace the TOSH and TOSL and do a return.
The user must disable the global interrupt enable bits
during this time to prevent inadvertent stack operations.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 25
PIC18F010/020
REGISTER 4-1:
STKPTR - STACK POINTER REGISTER
R/C-0
R/C-0
U-0
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
STKFUL STKUNF
bit7
—
bit0
bit 7(1)
bit 6(1)
STKFUL: Stack Full Flag bit
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit
1= Stack underflow occurred
0= Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 can only be cleared in user software, or by a POR.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
FIGURE 4-3:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
11111
11110
11101
STKPTR<4:0>
TOSH
0x1A
TOSL
0x34
00010
00011
0x0A34 00010
0x0D58 00001
Top-of-Stack
00000
0x0000
DS41142A-page 26
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
If no interrupts are used, the fast register stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the fast register
stack for a subroutine call, a fast call instruction
must be executed.
4.2.3
PUSHAND POPINSTRUCTIONS
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execu-
tion, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the stack pointer and load the cur-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place a return address on the
stack.
Example 4-1 shows a source code example that uses
the fast register stack.
EXAMPLE 4-1:
FAST REGISTER STACK
CODE EXAMPLE
CALL SUB1, FAST
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POPinstruction. The POPinstruc-
tion discards the current TOS by decrementing the
stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
•
•
SUB1
•
•
•
4.2.4
STACK FULL/UNDERFLOW RESETS
RETURN FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
These RESETS are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabled, a full or underflow condition will set the appro-
priate STKFUL or STKUNF bit, but not cause a device
RESET. When the STVREN bit is enabled, a full or
underflow condition will set the appropriate STKFUL or
STKUNF bit and then cause a device RESET. The
STKFUL or STKUNF bits are only cleared by the user
software or a POR Reset.
4.4
PCL, PCLATH and PCLATU
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<11:8>
bits and is not directly readable or writable. Updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:17> bits and is not directly
readable or writable. Updates to the PCU register may
be performed through the PCLATU register.
4.3
Fast Register Stack
A "fast interrupt return" option is available for interrupts.
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers and are only one in depth.
The stack is not readable or writable and is loaded with
the current value of the corresponding register when
the processor vectors for an interrupt. The values in the
registers are then loaded back into the working regis-
ters, if the fast return instruction is used to return
from the interrupt.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of the PCL is fixed to a value of
’0’. The PC increments by 2 to address sequential
instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority inter-
rupt will be overwritten.
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the pro-
gram counter will be transferred to PCLATH and
PCLATU, by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1).
If high priority interrupts are not disabled during low pri-
ority interrupts, users must save the key registers in
software during a low priority interrupt.
Note: Bits 12 through 16 are not implemented in
the PC and PCLAT.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 27
PIC18F010/020
4.5
Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-4.
FIGURE 4-4:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
phase
clock
Q4
PC
PC
PC+2
PC+4
OSC2/CLKOUT
(Internal Oscillator
mode)
Fetch INST (PC)
Execute INST (PC-2)
Fetch INST (PC+2)
Execute INST (PC)
Fetch INST (PC+4)
Execute INST (PC+2)
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
4.6
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO),
then two cycles are required to complete the instruction
(Example 4-2).
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
EXAMPLE 4-2:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch
instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
DS41142A-page 28
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
The CALLand GOTOinstructions have an absolute pro-
gram memory address embedded into the instruction.
Since instructions are always stored on word bound-
aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 4-5 shows how the
instruction "GOTO 000006h’ is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner.
The offset value stored in a branch instruction repre-
sents the number of single word instructions that the
PC will be offset by. Section 13.0 provides further
details of the instruction set.
4.7
Instructions in Program Memory
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The least significant byte of an instruction
word is always stored in a program memory location
with an even address (LSB = ’0’). Figure 4-5 shows an
example of how instruction words are stored in the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ’0’ (see Section 4.4).
FIGURE 4-5:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
↓
Program Memory
Byte Locations
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
→
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
000006h
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Instruction 3:
MOVFF
123h, 456h
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 29
PIC18F010/020
second word of the instruction is executed by itself (first
word was skipped), it will execute as a NOP. This action
is necessary when the two-word instruction is preceded
by a conditional instruction that changes the PC. A pro-
gram example that demonstrates this concept is shown
in Example 4-3. Refer to Section 13.0 for further details
of the instruction set.
4.7.1
TWO-WORD INSTRUCTIONS
The PIC18F010/020 devices have 4 two-word instruc-
tions: MOVFF, CALL, GOTOand LFSR. The second
word of these instructions has the 4 MSB’s set to 1’s
and is a special kind of NOPinstruction. The lower 12
bits of the second word contain data to be used by the
instruction. If the first word of the instruction is exe-
cuted, the data in the second word is accessed. If the
EXAMPLE 4-3:
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
TSTFSZ
MOVFF
REG1
; is RAM location 0?
REG1, REG2 ; No, execute 2-word instruction
; 2nd operand holds address of REG2
ADDWF
REG3
; continue code
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
TSTFSZ
MOVFF
REG1
; is RAM location 0?
REG1, REG2 ; Yes
; 2nd operand becomes NOP
ADDWF
REG3
; continue code
4.8.2
TABLE READS/TABLE WRITES
4.8
Lookup Tables
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Lookup tables are implemented two ways. These are:
• Computed GOTO
• Table Reads
Lookup table data may be stored 2 bytes per program
word by using table reads and writes. The table pointer
(TBLPTR) specifies the byte address and the table
latch (TABLAT) contains the data that is read from, or
written to, program memory. Data is transferred to/from
program memory one byte at a time.
4.8.1
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL).
A lookup table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table, before exe-
cuting a call to that table. The first instruction of the called
routine is the ADDWF PCLinstruction. The next instruc-
tion executed will be one of the RETLW 0xnn instruc-
tions, that returns the value 0xnnto the calling function.
A description of the Table Read/Table Write operation
is shown in Section 6.0.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
DS41142A-page 30
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
4.9.1
GENERAL PURPOSE REGISTER
FILE
4.9
Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 4-6
and Figure 4-7 show the data memory organization for
the PIC18F010/020 devices.
The register file can be accessed either directly or indi-
rectly. Indirect addressing operates through the File
Select Registers (FSR). The operation of indirect
addressing is shown in Section 4.12.
Banking is required to allow more than 256 bytes to be
accessed. The data memory map is divided into 2
banks that contain 256 bytes each. The lower 4 bits of
the Bank Select Register (BSR<3:0>) select which
bank will be accessed. The upper 4 bits for the BSR
are not implemented.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other RESETs.
Data RAM is available for use as GPR registers by all
instructions. Bank 15 (0xF80 to 0xFFF) contains SFRs.
Bank 0 contains GPR registers.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratch pad operations in the user’s appli-
cation. The SFRs start at the last location of Bank 15
(0xFFF) and grow downwards. GPRs start at the first
location of Bank 0 and grow upwards. Any read of an
unimplemented location will read as ’0’s.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for control-
ling the desired operation of the device. These regis-
ters are implemented as static RAM. A list of these
registers is given in Figure 4-7 and Figure 4-8.
The SFRs can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of
the File Select Register (FSR). Each FSR holds a 12-
bit address value that can be used to access any loca-
tion in the Data Memory map, without banking.
The SFRs are typically distributed among the peripher-
als whose functions they control.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indi-
rect addressing, or by the use of the MOVFFinstruction.
The MOVFFinstruction is a two-word/two-cycle instruc-
tion, that moves a value from one register to another.
The unused SFR locations will be unimplemented and
read as '0's. See Figure 4-7 for addresses for the
SFRs.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment
of Bank 15 comprise the Access RAM. Section 4.10
provides a detailed description of the Access RAM.
Note: Only 2 banks are implemented, Bank 0 and
Bank 15.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 31
PIC18F010/020
FIGURE 4-6:
DATA MEMORY MAP PIC18F010/020
BSR<3:0>
Data Memory Map
000h
07Fh
080h
0FFh
100h
00h
FFh
Access GPR
GPR
= 0000b
= 0001b
Bank 0
Access Bank
00h
7Fh
80h
Access GPR
Access SFR
= 0010b
= 1110b
Bank 1
to
Bank 14
FFh
Unused
Read ’00h’
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are
General Purpose RAM
(from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
EFFh
F00h
F7Fh
F80h
FFFh
00h
FFh
SFR
= 1111b
Bank 15
Access SFR
When a = 1,
the BSR is used to specify
the RAM location that the
instruction uses.
DS41142A-page 32
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
FIGURE 4-7:
SPECIAL FUNCTION REGISTER MAP (F80h-FFFh)
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
FEEh
FEDh
FECh
FEBh
FEAh
FE9h
FE8h
FE7h
FE6h
FE5h
FE4h
FE3h
FE2h
FE1h
FE0h
FDFh
FDEh
FDDh
FDCh
FDBh
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
FBFh
FBEh
FBDh
FBCh
FBBh
FBAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
reserved
OSCTUNE
FSR2L
reserved
reserved
reserved
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
STATUS
TMR0H
TMR0L
T0CON
reserved
OSCCON
LVDCON
WDTCON
RCON
TRISB
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
EEADRH
EEADR
LATB
FSR0L
WREG
EEDATA
EECON2
EECON1
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
IPR2
PIR2
PIE2
FSR1L
PORTB
BSR
Note: Shading indicates addresses within Access Bank. Blank areas indicate reserved register space that may or
may not be implemented in this device.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 33
PIC18F010/020
FIGURE 4-8:
SPECIAL FUNCTION REGISTER MAP (F00h-F7Fh)
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
F5Fh
F5Eh
F5Dh
F5Ch
F5Bh
F5Ah
F59h
F58h
F57h
F56h
F55h
F54h
F53h
F52h
F51h
F50h
F4Fh
F4Eh
F4Dh
F4Ch
F4Bh
F4Ah
F49h
F48h
F47h
F46h
F45h
F44h
F43h
F42h
F41h
F40h
F3Fh
F3Eh
F3Dh
F3Ch
F3Bh
F3Ah
F39h
F38h
F37h
F36h
F35h
F34h
F33h
F32h
F31h
F30h
F2Fh
F2Eh
F2Dh
F2Ch
F2Bh
F2Ah
F29h
F28h
F27h
F26h
F25h
F24h
F23h
F22h
F21h
F20h
F1Fh
F1Eh
F1Dh
F1Ch
F1Bh
F1Ah
F19h
F18h
F17h
F16h
F15h
F14h
F13h
F12h
F11h
F10h
F0Fh
F0Eh
F0Dh
F0Ch
F0Bh
F0Ah
F09h
F08h
F07h
F06h
F05h
F04h
F03h
F02h
F01h
F00h
WPUB
IOCB
Note: Shading indicates addresses within Access Bank. Blank areas indicate reserved register space that may or
may not be implemented in this device.
DS41142A-page 34
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
TABLE 4-1:
REGISTER FILE SUMMARY (PIC18F010/020)
Value on
Value on
POR,
BOR
All Other
RESETS
(Note 1)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FFEh TOSH
FFDh TOSL
FFCh STKPTR
Top-of-Stack High Byte (TOS<11:8>)
Top-of-Stack Low Byte (TOS<7:0>)
---- 0000 ---- 0000
0000 0000 0000 0000
00-0 0000 00-0 0000
STKOVF
STKUNF
—
Return Stack Pointer
Holding Register for PC<20:18>
FFBh PCLATU
FFAh PCLATH
FF9h PCL
—
—
—
—
bit21(3)
—
—
—
—
--00 00-- --00 00--
---- 0000 ---- 0000
0000 0000 0000 0000
—
—
Holding Register for PC<11:8>
PC Low Byte (PC<7:0>)
FF8h TBLPTRU
—
—
bit21(2)
Program Memory Table Pointer
Upper Byte (TBLPTR<20:18>)
---0 0000 ---0 0000
FF7h TBLPTRH
—
—
—
—
Program Memory Table Pointer High Byte
(TBLPTR<11:8>)
0000 0000 0000 0000
FF6h TBLPTRL
FF5h TABLAT
FF4h PRODH
FF3h PRODL
FF2h INTCON
FF1h INTCON2
FEFh INDF0
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 000x 0000 000u
11-- -1-1 11-- -1-1
Product Register High Byte
Product Register Low Byte
GIE/GIEH
RBPU
PEIE/GIEL
INTEDG0
T0IE
INT0E
RBIE
T0IF
T0IP
INT0F
RBIF
RBIP
—
—
—
—
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FEEh POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)
FEDh POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register)
FECh PREINC0
FEBh PLUSW0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) -
value of FSR0 offset by W
FEAh FSR0H
FE9h FSR0L
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- 0000 ---- 0000
xxxx xxxx uuuu uuuu
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
FE8h WREG
xxxx xxxx uuuu uuuu
FE7h INDF1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register)
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)
FE6h POSTINC1
FE5h POSTDEC1
FE4h PREINC1
FE3h PLUSW1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) -
value of FSR1 offset by W
FE2h FSR1H
FE1h FSR1L
FE0h BSR
---- 0000 ---- 0000
xxxx xxxx uuuu uuuu
---- 0000 ---- 0000
—
—
—
—
Indirect Data Memory Address Pointer 1 High
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
Bank Select Register
FDFh INDF2
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FDEh POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)
FDDh POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register)
FDCh PREINC2
FDBh PLUSW2
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) -
value of FSR2 offset by W
FDAh FSR2H
FD9h FSR2L
FD8h STATUS
FD7h TMR0H
FD6h TMR0L
FD5h T0CON
—
—
—
—
Indirect Data Memory Address Pointer 2 High
---- 0000 ---- 0000
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV
Z
DC
C
Timer0 Register High Byte
Timer0 Register Low Byte
TMR0ON
T08BIT
T0CS
T0SE
T0PS3
T0PS2
T0PS1
T0PS0
Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: These registers can only be modified when the combination lock is open.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 35
PIC18F010/020
TABLE 4-1:
REGISTER FILE SUMMARY (PIC18F010/020) (CONTINUED)
Value on
All Other
RESETS
(Note 1)
Value on
POR,
BOR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FD3h OSCCON
FD2h LVDCON
FD1h WDTCON
FD0h RCON
FB0h PSPCON
FA9h EEADR
FA8h EEDATA
FA7h EECON2
FA6h EECON1
FA2h IPR2
—
—
IRCF2
—
IRCF1
BGST
—
IRCF0
LVDEN
—
OSTO
LVV3
SWP2
TO
IESO
LVV2
SWP1
PD
—
SCS
LVV0
-000 00-0 -qqq qq-q
--00 0101 --00 0101
---- 0000 ---- 0000
0--1 11qq 0--q qquu
---- --00 ---- --00
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---- ---- ---- ----
x--0 x000 u--0 u000
---1 -1-- ---1 -1--
---0 -0-- ---0 -0--
---0 -0-- ---0 -0--
--00 0000 --qq qqqq
--11 1111 1111 1111
--xx xxxx uuuu uuuu
--xx xxxx uuuu uuuu
--11 1111 0011 1111
--00 0000 0000 0000
LVV1
SWP0
POR
—
—
SWDTE
BOR
IPE
—
—
—
RI
—
—
—
—
—
CMLK1
CMLK0
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
EEPGD
—
—
—
—
—
—
—
—
—
—
—
—
—
FREE
EEIP
EEIF
EEIE
TUN4
WRERR
—
WREN
LVDIP
LVDIF
LVDIE
TUN2
WR
—
RD
—
FA1h PIR2
—
—
—
—
—
FA0h PIE2
—
—
—
—
—
F9Bh OSCTUNE
F93h TRISB
F8Ah LATB
—
TUN5
TUN3
TUN1
TUN0
—
Data Direction Control Register for PORTB
—
Read PORTB Data Latch, Write PORTB Data Latch
Read PORTB pins, Write PORTB Data Latch
F81h PORTB
F79h WPUB
F78h IOCB
—
—
WPUB5
IOCB5
WPUB4
IOCB4
WPUB3
IOCB3
WPUB2
IOCB2
WPUB1
IOCB1
WPUB0
IOCB0
—
Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: These registers can only be modified when the combination lock is open.
DS41142A-page 36
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
4.10 Access Bank
4.11 Bank Select Register (BSR)
The Access Bank is an architectural enhancement
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ’0’s, and
writes will have no effect.
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
A MOVLBinstruction has been provided in the instruc-
tion set to assist in selecting banks.
• Faster evaluation/control of SFRs (no banking)
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
The Access Bank is comprised of the upper 128 bytes
in Bank 15 (SFRs) and the lower 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-6
and Figure 4-7 indicate the Access RAM areas.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register, or in
the Access Bank. This bit is denoted by the ’a’ bit (for
access bit).
A MOVFFinstruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
When forced in the Access Bank (a = ’0’), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function registers, so that these registers
can be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
FIGURE 4-9:
DIRECT ADDRESSING
Direct Addressing
(3)
From Opcode
BSR<3:0>
7
0
(2)
(3)
Bank Select
Location Select
00h
000h
01h
100h
0Eh
E00h
0Fh
F00h
Data
Memory(1)
0FFh
1FFh
Bank 1
EFFh
FFFh
Bank 0
Bank 14
Bank 15
Note 1: For register file map detail, see Table 4-7.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the
registers of the Access Bank.
3: The MOVFFinstruction embeds the entire 12-bit address in the instruction.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 37
PIC18F010/020
4.12.1
INDIRECT ADDRESSING
OPERATION
4.12 Indirect Addressing, INDF and
FSR Registers
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Perform-
ing an operation on one of these five registers deter-
mines how the FSR will be modified during indirect
addressing.
Indirect addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. An SFR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-10
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address
specified by the value of the FSR register.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access (no
change) - INDFn
Indirect addressing is possible by using one of the INDF
registers. Any instruction using the INDF register actu-
ally accesses the register pointed to by the File Select
Register, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirectly results in a no-operation. The FSR register
contains a 12-bit address, which is shown in Figure 4-
10.
• Auto-decrement FSRn after an indirect access
(post-decrement) - POSTDECn
• Auto-increment FSRn after an indirect access
(post-increment) - POSTINCn
• Auto-increment FSRn before an indirect access
(pre-increment) - PREINCn
• Use the signed value of WREG as an offset to
FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) - PLUSWn
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
When using the auto-increment or auto-decrement fea-
tures, the effect on the FSR is not reflected in the STA-
TUS register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bit wide. To store the 12-bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL overflows from an increment,
FSRnH will be incremented automatically.
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
Adding these features allows the FSRn to be used as a
stack pointer, in addition to its uses for table operations
in data memory.
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data.
Each FSR has an address associated with it that per-
forms an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add the signed value in the WREG regis-
ter and the value in FSR to form the address before an
indirect access. The FSR value is not changed.
If an instruction writes a value to INDF0, the value will
be written to the address pointed to by FSR0H:FSR0L.
A read from INDF1, reads the data from the address
pointed to by FSR1H:FSR1L. INDFn can be used in
code anywhere an operand can be used.
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(STATUS bits are not affected).
If INDF0, INDF1, or INDF2 are read indirectly via an
FSR, all ’0’s are read (zero bit is set). Similarly, if
INDF0, INDF1, or INDF2 are written to indirectly, the
operation will be equivalent to a NOPinstruction and the
STATUS bits are not affected.
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register, the
write operation will dominate over the pre- or post-
increment/decrement functions.
DS41142A-page 38
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
FIGURE 4-10:
INDIRECT ADDRESSING
Indirect Addressing
11
FSR Register
0
Location Select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 4-7.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 39
PIC18F010/020
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
4.13 STATUS Register
The STATUS register, shown in Register 4-2, contains
the arithmetic status of the ALU. The STATUS register
can be the destination for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV, or N bits,
then the write to these five bits is disabled. These bits
are set or cleared according to the device logic. There-
fore, the result of an instruction with the STATUS regis-
ter as destination may be different than intended.
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alter the STATUS register, because these instructions
do not affect the Z, C, DC, OVor Nbits from the STA-
TUS register. For other instructions not affecting any
status bits, see Table 13-2.
Note: The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
REGISTER 4-2:
STATUS REGISTER
U-0
U-0
U-0
R/W-x
N
R/W-x
OV
R/W-x
Z
R/W-x
DC
R/W-x
C
—
—
—
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as '0'
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative, (ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude, which causes the sign bit (bit 7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWFinstructions
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the bit 4 or bit 3 of the source register.
bit 0
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWFinstructions
1= A carry-out from the most significant bit of the result occurred
0= No carry-out from the most significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS41142A-page 40
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
4.14 RCON Register
Note 1: If the BOREN configuration bit is set,
BOR is ’1’ on Power-on Reset. If the
BOREN configuration bit is clear, BOR is
unknown on Power-on Reset.
The RESET Control (RCON) register contains flag bits,
that allow differentiation between the sources of a
device RESET. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.
The BOR status bit is a "don't care" and is
not necessarily predictable if the brown-
out circuit is disabled (the BOREN config-
uration bit is clear). BOR must then be set
by the user and checked on subsequent
RESETS to see if it is clear, indicating a
brown-out has occurred.
2: It is recommended that the POR bit be set
after
a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
REGISTER 4-3:
RCON REGISTER
R/W-0
IPEN
U-0
U-0
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
—
—
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6-5
bit 4
Unimplemented: Read as ‘0’
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed
0= The RESETinstruction was executed causing a device RESET
(must be set in software after a Brown-out Reset occurs)
bit 3
bit 2
bit 1
TO: Watchdog Time-out Flag bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down Detection Flag bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred
0= A Power-on Reset occurred
(must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred
0= A Brown-out Reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 41
PIC18F010/020
NOTES:
DS41142A-page 42
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
5.2
EECON1 and EECON2 Registers
5.0
DATA EEPROM MEMORY
EECON1 is the control register for memory accesses.
The Data EEPROM is readable and writable during
normal operation (full VDD range). This memory is not
directly mapped in the register file space. Instead, it is
indirectly addressed through the Special Function Reg-
isters. There are four SFRs used to read and write this
memory. These registers are:
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the memory write sequence.
Control bit EEPGD determines if the access will be a
program or a data memory access. When clear, any
subsequent operations will operate on the data mem-
ory. When set, any subsequent operations will operate
on the program memory.
• EECON1 (0FA6h)
• EECON2 (0FA7h)
• EEDATA (0FA8h)
• EEADR (0FA9h)
Control bits RD and WR initiate read and write opera-
tions, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
When interfacing the data memory block, EEDATA
holds the 8-bit data for read/write, and EEADR holds
the address of the EEPROM location being accessed.
These devices have 64 bytes of data EEPROM with an
address range from 0h to 03Fh.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset, during normal oper-
ation. In these situations, following RESET, the user
can check the WRERR bit and rewrite the location. The
value of the data and address registers and the
EEPGD bit remains unchanged.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write).
The EEPROM data memory is rated for high erase/
write cycles. The write time is controlled by an on-chip
timer. The write time will vary with voltage and temper-
ature, as well as from chip-to-chip. Please refer to the
specifications for exact limits.
Interrupt flag bit EEIF in the PIR2 register, is set when
a write is complete. It must be cleared in software.
When the device is code protected, the CPU may con-
tinue to read and write the data EEPROM memory.
5.1
EEADR
The EEADR register can address up to a maximum of
256 bytes of data.
When the device contains less memory than the full
address reach of the EEADR register, the MSb’s of the
register must be set to ‘0’. For example, this device has
64 bytes of data EE, the Most Significant 2 bits of the
register must be ‘0’.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 43
PIC18F010/020
REGISTER 5-1:
EECON1 REGISTER (ADDRESS 18Ch)
R/W-U
U-0
U-0
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
—
—
WRERR
bit 7
bit 0
bit 7
EEPGD: FLASH Program or Data EEPROM Memory Select bit
1= Access Program FLASH memory
0= Access Data EEPROM memory
bit 6-5
bit 4
Unimplemented: Read as ‘0’
FREE: FLASH Row Erase Enable bit
1= Erase the row addressed by TBLPTR on the next WR command (reset by hardware)
0= Perform write only
bit 3
WRERR: EEPROM Error Flag bit
1= A write operation is prematurely terminated
(any MCLR Reset or any WDT Reset during normal operation)
0= The write operation completed
bit 2
bit 1
WREN: EEPROM Write Enable bit
1= Allows write cycles
0= Inhibits write to the EEPROM
WR: Write Control bit
1= Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR
bit can only be set (not cleared) in software.)
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD
bit can only be set (not cleared) in software.)
0= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS41142A-page 44
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
EXAMPLE 5-2:
DATA EEPROM WRITE
5.3
Reading the Data EEPROM
Memory
MOVLW DATA_EE_ADDR
;
MOVWF EEADR
; Data Memory
Address to write
;
; Data Memory
Value to write
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>), and then set control bit RD
(EECON1<0>). The data is available in the very next
instruction cycle of the EEDATA register, therefore, it
can be read by the next instruction. EEDATA will hold
this value until another read operation or until it is writ-
ten to by the user (during a write operation).
MOVLW DATA_EE_DATA
MOVWF EEDATA
BCF
BSF
BCF
EECON1, EEPGD ; Point to DATA
memory
EECON1, WREN ; Enable writes
INTCON, GIE
; Disable
Interrupts
;
; Write 55h
;
; Write AAh
; Set WR bit to
begin write
; Enable
Interrupts
EXAMPLE 5-1:
DATA EEPROM READ
MOVLW 55h
Required MOVWF EECON2
Sequence MOVLW AAh
MOVWF EECON2
MOVLW DATA_EE_ADDR
MOVWF EEADR
;
;Data Memory Address to read
BCF
BSF
EECON1, EEPGD ;Point to DATA memory
BSF
EECON1, WR
EECON1, RD
;EEPROM Read
;W = EEDATA
MOVF EEDATA, W
BSF
INTCON, GIE
5.4
Writing to the Data EEPROM
Memory
SLEEP
BCF
; Wait for
interrupt to
signal write
complete
To write an EEPROM data location, the address must
first be written to the EEADR register and the data writ-
ten to the EEDATA register. Then the sequence in
Example 5-2 must be followed to initiate the write cycle.
EECON1, WREN ; Disable writes
The write will not initiate if the above required sequence
is not exactly followed (write 55h to EECON2, write
AAh to EECON2, then set WR bit) for each byte. It is
strongly recommended that interrupts be disabled dur-
ing this code segment.
Note: Do not write to program memory or
EECON1 while writing to EEDATA.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. EEIF must be cleared by
software.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 45
PIC18F010/020
5.5
Protection Against Spurious Write
5.6
Operation During Code Protect
Each reprogrammable memory block has its own code
protect mechanism. External Read and Write opera-
tions are disabled if either of these mechanisms are
enabled.
5.5.1
EEPROM DATA MEMORY
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
5.6.1
DATA EEPROM MEMORY
The microcontroller itself can both read and write to the
internal Data EEPROM, regardless of the state of the
code protect configuration bit.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
TABLE 5-1:
REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FA9h
FA8h
FA7h
FA6h
FA2h
FA1h
FA0h
FF2h
EEADR EEPROM Address Register
EEDATA EEPROM Data Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---- ---- ---- ----
x--0 x000 u--0 u000
---1 1--- ---1 1---
---0 0--- ---0 0---
---0 0--- ---0 0---
EECON2 EEPROM Control Register2 (not a physical register)
EECON1 EEPGD
—
—
—
—
—
—
—
—
FREE WRERR WREN
WR
—
RD
—
IPR2
PIR2
PIE2
—
—
—
EEIP
EEIF
—
—
LVDIP
LVDIF
LVDIE
T0IF
—
—
EEIE
—
—
—
INTCON GIE/GIEH PEIE/GIEL T0IE
INT0IE
RBIE
INT0F
RBIF 0000 000x 0000 000u
Legend: x= unknown, u= unchanged, r= reserved, -= unimplemented, read as '0'.
Shaded cells are not used during FLASH/EEPROM access.
Note 1: These bits are reserved; always maintain these bits clear.
DS41142A-page 46
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
6.1.1
EECON1 REGISTER
6.0
TABLE READ/WRITE
INSTRUCTIONS
The EECON1 register holds bits to control erase and
write operations in FLASH memory. The EEPGD bit
selects data EEPROM, if clear, or program FLASH
memory, if set. The FREE bit is used to select erasing
versus writing to FLASH. The WREN bit enables writ-
ing. Finally, the WRERR bit indicates any errors. Refer
to Register 5-1 for details.
The PIC18F010/020 has eight instructions that allow
the processor to move data from the data memory
space to the program memory space, and vice versa.
These eight instructions manipulate the Table Pointer
in a manner similar to the FSR’s.
The TBLRDinstructions are used to read data from the
program memory space to the data memory space.
The TBLWTinstructions are used to write data from the
data memory space to the program memory space.
6.2
Table Reads from FLASH Program
Memory
Table Reads from program memory are performed one
byte at a time. The instruction will access one byte from
the program memory pointed to by the TBLPTR and
transfer that byte to the TABLAT. Figure 6-1 diagrams
the Table Read operation.
6.1
Control Registers
A few control registers are used in conjunction with the
TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• TABLAT register
• TBLPTR registers
The TBLPTR can be updated in one of four ways,
based on the Table Read instructions:
• TBLRD*no-change
• TBLRD*+post-increment
• TBLRD*-post-decrement
• TBLRD+*pre-increment
The internal program memory is normally word wide.
The Least Significant bit of the address selects between
the high and low bytes of the word. Figure 6-2 shows
the typical interface between the internal program
memory and the TABLAT.
FIGURE 6-1:
TBLRD*INSTRUCTION OPERATION
Table Latch (8-bit)
TABLAT
Table Pointer
TBLPTRU TBLPTRH
TBLPTRL
Program Memory
Prog-Mem
(TBLPTR)
Instruction: TBLRD*
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 47
PIC18F010/020
EXAMPLE 6-1:
PROGRAM MEMORY
READ
MOVLW
MOVWF
CODE_ADDR_UPPER; Load TBLPTR
; Register
TBLPTRU
; with Address to
; Read
MOVLW
MOVWF
MOVLW
MOVWF
TBLRD*
MOVF
CODE_ADDR_HIGH ;
TBLPTRH
;
CODE_ADDR_LOW
TBLPTRL
;
;
; Read Memory
; W = Data
TABLAT,W
FIGURE 6-2:
TABLE READS / WRITES TO INTERNAL PROGRAM MEMORY
FLASH word write
done when TBLWTto
address with A0=1
Program Memory
Bank 1
(Odd Address)
Program Memory
Bank 0
(Even Address)
TBLWT
* A0=1
TBLWT
*A0=1
A0=1
A0=0
Buffer Register
Buffer Register
TBLWT
*A0=1
TBLWT *
* A0=0
TABLAT Read Reg.
TBLRD
TABLAT Write Reg.
DS41142A-page 48
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
6.3
Erasing FLASH Program Memory
6.4
FLASH Array Programming
Operations
Word erase in the FLASH array is not supported. The
minimum erase block is one row of a panel, which is
equivalent to 16 words or 32 bytes.
Word or byte programming is not supported. The mini-
mum programming block is 32-bits or 2 words.
Erase operations may be commanded from one of two
sources. Under user program control, the minimum one
row of memory is erased. Under programmer or
ICSPTM control, larger blocks of program memory may
be bulk erased.
6.4.1
PROGRAMMING FLASH PROGRAM
MEMORY IN OPERATIONAL MODE
(TABLE LONG WRITES)
Conceptually, Table Writes are performed one byte at a
time. The instruction will write one byte contained in the
TABLAT register to the internal memory, pointed to by
the TBLPTR, as shown in Figure 6-3.
6.3.1
ERASING FLASH PROGRAM
MEMORY IN OPERATIONAL MODE
In normal mode, a block of 32 bytes of program mem-
ory is erased. The Most Significant 16 bits of the
TBLPTR<21:6> points to the block being erased.
TBLPTR<4:0> are ignored.
The TBLPTR can be updated in one of four ways,
based on the Table Write instructions:
• TBLWT*no-change
• TBLWT*+post-increment
• TBLWT*-post-decrement
• TBLWT+*pre-increment
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the FLASH pro-
gram memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
The program memory FLASH uses a similar mecha-
nism to the data EEPROM. Table Writes are used inter-
nally to load the Write registers used to program the
FLASH memory. The EECON1 register is used to actu-
ally command a write or erase event.
For protection, the write initiate sequence for EECON2
must be used. When the WR bit is set, a long write is nec-
essary for erasing the internal FLASH. Instruction execu-
tion is halted while in a long write cycle. The long write will
be terminated by the internal programming timer. Instruc-
tion execution will resume with no lost instructions.
Each FLASH panel is programmed with 32 of 256 columns
at a time. This translates into 32 write bit latches. These
write latches are accessed using Table Write instructions,
which can write a byte at a time. There are then 4 Table
Writes required to write the latches for one panel.
The sequence of events for erasing a block of internal
program memory location is:
Since the table latch is only a single byte, the TBLWT
instruction has to be executed 4 times for each pro-
gramming operation. All of the Table Write operations
will essentially be short writes, because only the table
latches are written. At the end of updating 4 latches, the
EECON1 register must be written to start the program-
ming operation with a long write.
1. Load Table Pointer with address of row being
erased.
2. Set FREE bit to enable row erase; set WREN bit
to enable writes and set EEPGD bit to point to
program memory.
3. Disable interrupts.
4. Write ’55’ to EECON2.
The long write is necessary for programming the inter-
nal FLASH. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer. Instruction execution
will resume with two lost instructions.
5. Write 'AA’ to EECON2.
6. Set the WR bit. This will begin the row erase cycle.
7. CPU will stall for duration of the erase (about
2ms using internal timer).
The write time is controlled by the EEPROM on-chip
timer. The write/erase voltages are generated by an on-
chip charge pump, rated to operate over the voltage
range of the device for byte or word operations. When
doing block operations, the device must be operating in
the 5V ±10% range.
Note: When writing a block, insure the table
pointer is pointing to the desired block after
the last short write.
The first and second instruction following
the TBLWTmust be NOPs.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 49
PIC18F010/020
The sequence of events for programming an internal
program memory location should be:
8. Write first 3 bytes into table latches with auto-
increment. Write the last byte without auto-
increment.
1. Read 32 bytes of row into RAM.
9. Disable interrupts.
2. Update data values in RAM, as necessary.
10. Write ’55’ to EECON2.
3. Load Table Pointer with address of row being
erased.
11. Write 'AA’ to EECON2.
12. Set the WR bit. This will begin the write cycle.
4. Perform the row erase procedure.
13. CPU will stall for duration of the write (about 2ms
using internal timer).
5. CPU will stall for duration of the erase (about
2ms using internal timer).
14. Repeat steps 7-13, 8 times total to write 32
bytes.
6. Load Table Pointer with address first byte of row
being written.
15. Verify the memory row (Table Read).
7. Set WREN bit to enable writes and set EEPGD
bit to point to program memory.
This procedure will require about 18msec to update 1
row of 32 bytes of memory.
FIGURE 6-3:
TABLE WRITES TO INTERNAL PROGRAM MEMORY
Program Memory
(Column 16-23)
(Column 24-31)
(Column 8-15)
(Column 0-7)
Buffer Register
Buffer Register
Buffer Register
Buffer Register
TBLWT
A=xxxxx3
TBLWT
A=xxxxx2
TBLWT
A=xxxxx1
TBLWT
A=xxxxx0
TABLAT Write Reg.
DS41142A-page 50
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
EXAMPLE 6-2:
PROGRAM MEMORY WRITE
This example will buffer a segment of memory, modify one word in the buffer, erase the segment row, and write the buffer
back to memory.
MOVLW
MOVWF
32
COUNTER
; number of bytes in row
MOVLW
MOVWF
BUFFER_ADDR_HIGH; point to buffer
FSR0H
MOVLW
MOVWF
BUFFER_ADDR_LOW
FSR0L
;
MOVLW
CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF
TBLPTRU
; address of the memory row
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
;
;
;
;
READ_ROW
TBLRD*+
MOVF
MOVWF
DECFSZ COUNTER
READ_ROW
; read into TABLAT, and inc
; get data
; store data
; done?
TABLAT, W
POSTINC0
GOTO
MODIFY_WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
ERASE_ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; repeat
DATA_ADDR_HIGH ; point to buffer
FSR0H
DATA_ADDR_LOW
FSR0L
;
NEW_DATA_LOW
POSTINC0
; update buffer word
NEW_DATA_HIGH
INDF0
CODE_ADDR_UPPER ; Load TBLPTR with the base
TBLPTRU
; address of the memory row
CODE_ADDR_HIGH
TBLPTRH
;
;
CODE_ADDR_LOW
TBLPTRL
;
;
EECON1,WREN
EECON1,FREE
EECON1,EEPGD
55h
; enable write to memory
; Enable Row Erase operation
; Point to FLASH program memory
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON2
; write 55H
AAh
EECON2
; write AAH
EECON1,WR
; start erase (CPU stall)
WRITE_BUFFER_BACK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
TBLRD*-
8
; number of write buffer groups of 4 bytes
COUNTER_HI
BUFFER_ADDR_HIGH; point to buffer
FSR0H
BUFFER_ADDR_LOW
FSR0L
;
; back the TBLPTR up one
PROGRAM_LOOP
MOVLW
MOVWF
4
; number of bytes in write buffer
COUNTER
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 51
PIC18F010/020
EXAMPLE 6-2:
PROGRAM MEMORY WRITE (CONTINUED)
WRITE_WORD_TO_BUFFERS
MOVF
POSTINC0, W
TABLAT
; get low byte of buffer data
; present data to table latch
; write data, perform a short write to pre-increment and load data to
; internal TBLWT holding register.
MOVWF
TBLWT+*
NOP
NOP
; loop until buffers are full
DECFSZ COUNTER
GOTO
WRITE_WORD_TO_BUFFERS
PROGRAM_MEMORY
BSF
EECON1,WREN
; enable write to memory
BSF
EECON1,EEPGD
55h
EECON2
AAh
EECON2
EECON1,WR
; Point to FLASH program memory
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; write 55H
; write AAH
; start program (CPU stall)
; loop until done
DECFSZ COUNTER_HI
GOTO
BCF
PROGRAM_LOOP
EECON1,WREN
; disable write to memory
DS41142A-page 52
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
The table pointer TBLPTR is used by the TBLRD and
TBLWTinstructions. These instructions can update the
TBLPTR in one of four ways, based on the table oper-
ation. These operations are shown in Table 6-1. These
operations on the TBLPTR only affect the low order
21-bits.
6.4.2
TABLAT - TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold 8-
bit data during data transfers between program mem-
ory and data memory.
6.4.3
TBLPTR - TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper byte, High
byte and Low byte). These three registers
(TBLPTRU:TBLPTRH:TBLPTRL) join to form a 22-bit
wide pointer. The low order 21-bits allow the device to
address up to 2 Mbytes of program memory space. The
22nd bit allows access to the Device ID, the User ID
and the Configuration bits.
TABLE 6-1:
Example
TABLE POINTER OPERATIONS WITH TBLRDAND TBLWTINSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 53
PIC18F010/020
NOTES:
DS41142A-page 54
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
7.0
7.1
8 X 8 HARDWARE MULTIPLIER
Introduction
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F010/020 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 7-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
TABLE 7-1:
PERFORMANCE COMPARISON
Program
Time
Cycles
Routine
8 x 8 unsigned
8 x 8 signed
Multiply Method
Memory
(Words)
(Max)
@ 40 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 µs
100 ns
9.1 µs
600 ns
24.2 µs
2.4 µs
25.4 µs
3.6 µs
27.6 µs
400 ns
36.4 µs
2.4 µs
96.8 µs
9.6 µs
69 µs
1 µs
Without hardware multiply
Hardware multiply
33
6
91
6
91 µs
6 µs
242 µs
24 µs
254 µs
36 µs
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
21
24
52
36
242
24
254
36
Without hardware multiply
Hardware multiply
102.6 µs
14.4 µs
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 55
PIC18F010/020
EXAMPLE 7-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
7.2
Operation
Example 7-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required,
when one argument of the multiply is already loaded in
the WREG register.
MOVFF
MULWF
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
;
PRODH:PRODL
MOVFF
MOVFF
PRODH, RES1 ;
PRODL, RES0 ;
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
;
;
MOVFF
MULWF
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
PRODH:PRODL
;
MOVFF
MOVFF
PRODH, RES3 ;
PRODL, RES2 ;
EXAMPLE 7-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MULWF
ARG1L, WREG
ARG2H
MOVFF
MULWF
ARG1, WREG
ARG2
;
; ARG1L * ARG2H ->
; ARG1 * ARG2 ->
;
;
PRODH:PRODL
PRODH:PRODL
MOVFF
ADDWF
MOVFF
ADDWFC
CLRF
PRODL, WREG ;
RES1
PRODH, WREG ;
RES2
WREG
RES3
; Add cross
products
;
;
;
EXAMPLE 7-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
ADDWFC
;
MOVFF
MULWF
ARG1H, WREG ;
ARG2L ; ARG1H * ARG2L ->
MOVFF
MULWF
ARG1, WREG
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
PRODH:PRODL
MOVFF
ADDWF
MOVFF
ADDWFC
CLRF
PRODL, WREG ;
BTFSC
SUBWF
ARG2, SB
PRODH
RES1
; Add cross
PRODH, WREG ;
products
;
- ARG1
RES2
WREG
RES3
;
;
;
MOVFF
BTFSC
SUBWF
ARG2, WREG
ARG1, SB
PRODH
; Test Sign Bit
; PRODH = PRODH
ADDWFC
;
- ARG2
Example 7-4 shows the sequence to do a 16 x 16
signed multiply. Equation 7-2 shows the algorithm
used. The 32-bit result is stored in four registers
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs most significant bit (MSb)
is tested and the appropriate subtractions are done.
Example 7-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 7-1 shows the algorithm
that is used. The 32-bit result is stored in 4 registers
RES3:RES0.
EQUATION 7-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EQUATION 7-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 2 )+
16
RES3:RES0
8
=
=
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 2 )+
(ARG1H • ARG2L • 2 )+
(ARG1L • ARG2H • 2 )+
(ARG1L • ARG2L)
16
8
8
(ARG1H • ARG2L • 2 )+
(ARG1L • ARG2H • 2 )+
8
(ARG1L • ARG2L)+
(-1 • ARG2H<7> • ARG1H:ARG1L • 2 )+
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
16
16
)
DS41142A-page 56
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
EXAMPLE 7-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
MOVFF
MULWF
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
;
PRODH:PRODL
MOVFF
MOVFF
PRODH, RES1 ;
PRODL, RES0 ;
;
;
MOVFF
MULWF
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
PRODH:PRODL
;
MOVFF
MOVFF
PRODH, RES3 ;
PRODL, RES2 ;
MOVFF
MULWF
ARG1L, WREG
ARG2H
; ARG1L * ARG2H ->
;
PRODH:PRODL
MOVFF
ADDWF
MOVFF
ADDWFC
CLRF
PRODL, WREG ;
RES1
; Add cross
PRODH, WREG ;
products
RES2
WREG
RES3
;
;
;
ADDWFC
;
MOVFF
MULWF
ARG1H, WREG ;
ARG2L ; ARG1H * ARG2L ->
;
PRODH:PRODL
MOVFF
ADDWF
MOVFF
ADDWFC
CLRF
PRODL, WREG ;
RES1
; Add cross
PRODH, WREG ;
products
RES2
WREG
RES3
;
;
;
ADDWFC
;
;
BTFSS
GOTO
MOVFF
SUBWF
MOVFF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, WREG ;
RES2
ARG1H, WREG ;
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
SIGN_ARG1
BTFSS
GOTO
ARG1H, 7
CONT_CODE
; ARG1H:ARG1L neg?
; no, done
MOVFF
SUBWF
MOVFF
SUBWFB
;
ARG2L, WREG ;
RES2
ARG2H, WREG ;
RES3
;
CONT_CODE
:
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 57
PIC18F010/020
NOTES:
DS41142A-page 58
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
When the IPEN bit is cleared (default state), the inter-
rupt priority feature is disabled and interrupts are com-
patible with PICmicro® mid-range devices. In
compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit,
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
000008h in compatibility mode.
8.0
INTERRUPTS
The PIC18F010/020 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level, or a low priority level. The high priority interrupt
vector is at 000008h and the low priority interrupt vector
is at 000018h. High priority interrupt events will over-
ride any low priority interrupts that may be in progress.
There are six registers which are used to control inter-
rupt operation. These registers are:
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt.
• RCON
• INTCON
• INTCON2
• PIR2
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
• PIE2
• IPR2
It is recommended that the Microchip header files sup-
plied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
The "return from interrupt" instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
Each interrupt source has three bits to control its oper-
ation. The functions of these bits are:
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit, or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts glo-
bally. Setting the GIEH bit (INTCON<7>), enables all
interrupts that have the priority bit set. Setting the GIEL
bit (INTCON<6>), enables all interrupts that have the
priority bit cleared. When the interrupt flag, enable bit
and appropriate global interrupt enable bit are set, the
interrupt will vector immediately to address 000008h or
000018h, depending on the priority level. Individual
interrupts can be disabled through their corresponding
enable bits.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 59
PIC18F010/020
FIGURE 8-1:
INTERRUPT LOGIC
Wake-up if in SLEEP mode
T0IF
T0IE
T0IP
RBIF
RBIE
RBIP
INT0F
INT0E
Interrupt to CPU
Vector to Location
0008h
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
GIEH/GIE
XXXXIF
XXXXIE
XXXXIP
IPE
IPE
GIEL/PEIE
Additional Peripheral Interrupts
IPE
High Priority Interrupt Generation
Low Priority Interrupt Generation
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
XXXXIF
XXXXIE
XXXXIP
T0IF
T0IE
T0IP
Interrupt to CPU
Vector to Location
0018h
RBIF
RBIE
RBIP
GIEL\PEIE
Additional Peripheral Interrupts
DS41142A-page 60
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
8.1
INTCON Registers
The INTCON Registers are readable and writable reg-
isters, which contain various enable, priority and flag
bits.
REGISTER 8-1:
INTCON REGISTER
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
R/W-x
RBIF
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TMR0IF INT0IF
bit 7
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN = 1:
1= Enables all interrupts
0= Disables all interrupts
bit 6
PEIE/GEIL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low priority peripheral interrupts
0= Disables all priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB5:RB0 pins changed state (must be cleared in software)
0= None of the RB5:RB0 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset ’1’ = Bit is set
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 61
PIC18F010/020
REGISTER 8-2:
INTCON2 REGISTER
R/W-1
RBPU
R/W-1
U-0
U-0
U-0
R/W-1
U-0
R/W-1
RBIP
INTEDG0
—
—
—
TMR0IP
—
bit 7
bit 0
bit 7
bit 6
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0:External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
bit 5-3
bit 2
Unimplemented: Read as '0'
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
Unimplemented: Read as '0'
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset ’1’ = Bit is set
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
DS41142A-page 62
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
8.2
PIR Registers
8.3
PIE Registers
The PIR2 register contains the individual flag bits for
the peripheral interrupts.
The PIE2 register contains the individual enable bits for
the peripheral interrupts. When IPEN = 0, the PEIE bit
must be set to enable any of these peripheral inter-
rupts.
Note 1: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
8.4
IPR Registers
The IPR2 register contains the individual priority bits for
the peripheral interrupts. The operation of the priority
bits requires that the Interrupt Priority Enable (IPEN) bit
be set.
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
8.5
RCON Register
The RCON register contains the bit which is used to
enable prioritized interrupts (IPEN).
REGISTER 8-3:
RCON REGISTER
R/W-0
IPEN
U-0
U-0
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
—
—
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6-5
bit 4
Unimplemented: Read as '0'
RI: RESETInstruction Flag bit
For details of bit operation see Register 4-1
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
For details of bit operation see Register 4-1
PD: Power-down Detection Flag bit
For details of bit operation see Register 4-1
POR: Power-on Reset Status bit
For details of bit operation see Register 4-1
BOR: Brown-out Reset Status bit
For details of bit operation see Register 4-1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset ’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 63
PIC18F010/020
REGISTER 8-4:
PIR2: PERIPHERAL INTERRUPT FLAG REGISTER2 (FA1h)
U-0
U-0
U-0
R/W-0
EEIF
U-0
R/W-0
LVDIF
U-0
U-0
—
—
—
—
—
—
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as ‘0’
EEIF: EEPROM Write Timer Interrupt Flag bit
1= Write complete
bit 3
bit 2
Unimplemented: Read as ‘0’
LVDIF: Low Voltage Detect Interrupt Flag bit
1= The supply voltage has fallen below the specified LVD voltage (must be cleared in software)
0= The supply voltage is greater than the specified LVD voltage
bit 1-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
REGISTER 8-5:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER2 (FA0h)
U-0
U-0
U-0
R/W-0
EEIE
U-0
R/W-0
LVDIE
U-0
U-0
—
—
—
—
—
—
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as ‘0’
EEIE: EEPROM Write Timer Interrupt Enable bit
1= Enables the EEPROM Write Timer interrupt
0= Disables the EEPROM Write Timer interrupt
bit 3
bit 2
Unimplemented: Read as ‘0’
LVDIE: Low Voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
bit 1-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS41142A-page 64
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
REGISTER 8-6:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER2 (FA2h)
U-0
U-0
U-0
R/W-1
EEIP
U-0
R/W-1
LVDIP
U-0
U-0
—
—
—
—
—
—
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as ‘0’
EEIP: EEPROM Write Timer Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
Unimplemented: Read as ‘0’
LVDIP: Low Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
bit 1-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 65
PIC18F010/020
8.5.1
INT0 INTERRUPT
8.5.2
TMR0 INTERRUPT
The external interrupt on the RB2/INT0 pin is edge trig-
gered: either rising if the INTEDG0 bit is set in the
INTCON2 register, or falling if the INTEDG0 bit is clear.
When a valid edge appears on the RB0/INT0 pin, the
flag bit INT0F is set. Clearing the enable bit INT0E will
disable this interrupt. Flag bit INT0F must be cleared in
software in the Interrupt Service Routine before re-
enabling the interrupt. The external interrupt can wake-
up the processor from SLEEP. If the global interrupt
enable bit GIE is set, the processor will branch to the
interrupt vector following wake-up.
In 8-bit mode (which is the default), an overflow (FFh →
00h) in the TMR0 register will set flag bit TMR0IF. In
16-bit mode, an overflow (FFFFh → 0000h) in the
TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit T0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2<2>). See Sec-
tion 8.0 for further details on the Timer0 module.
8.5.3
PORTB INTERRUPT-ON-CHANGE
An interrupt change on any pin in PORTB sets flag bit
RBIF in INTCON. The interrupt can be enabled/dis-
abled by setting clearing the enable bit RBIE in
INTCON. The bit RBIP in INTCON2 determines the pri-
ority of the interrupt.
Note: There is no priority bit associated with
INT0. It is always a high priority interrupt
source.
Each of the PORTB pins is individually configurable as
an interrupt-on-change pin. Control bits IOCBx in the
IOCB register, Register 9-2, enable or disable the inter-
rupt function for each pin. The interrupt-on-change is
disabled on a Power-on Reset.
8.6
Context Saving During Interrupts
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR regis-
ters are saved on the fast return stack. If a fast return
from interrupt is not used (see Section 4.3), the user
may need to save the WREG, STATUS and BSR regis-
ters in software. Depending on the user’s application,
other registers may also need to be saved. Example 6-1
saves and restores the WREG, STATUS and BSR
registers during an Interrupt Service Routine.
EXAMPLE 8-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
DS41142A-page 66
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
9.2.1
WEAK PULL-UP
9.0
I/O PORT
Depending on the device options enabled, there are as
many as six general purpose I/O pins available. Some of
the pins are multiplexed with alternative functions from
the peripheral features on the device. Thus, when a
peripheral is enabled, the associated pin may not be
used as a general purpose I/O pin. On a Power-on Reset,
all pins configured as general I/O are set as inputs.
Each of the PORTB pins has an individually config-
urable weak internal pull-up. Control bits WPUBx
enable or disable each pull-up (see Register 9-1). Each
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
9.2.2
INTERRUPT-ON-CHANGE
9.1
PORTB, TRISB, and LATB Registers
Each of the PORTB pins is individually configurable as
an interrupt-on-change pin. Control bits IOCBx enable
or disable the interrupt function for each pin (see
Register 9-2). The interrupt-on-change is disabled on a
Power-on Reset.
PORTB is a 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a Hi-
Impedance mode). Clearing a TRISB bit (= 0) will make
the corresponding PORTB pin an output (i.e., put the
contents of the output latch on the selected pin). On a
Power-on Reset, these pins are configured as inputs.
Example 9-1 demonstrates PORTB configuration.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTB. The "mismatch" outputs of the last read are
OR’d together to set, or clear the RB Port Change Inter-
rupt flag bit RBIF, in the INTCON register.
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
EXAMPLE 9-1:
INITIALIZING PORTB
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
a) Any read or write of PORTB (except with MOVFF
CLRF
LATB
instruction). This will end the mismatch condition.
b) Clear the flag bit RBIF.
MOVLW
MOVWF
0x03
; Value used to
; initialize data
; direction
; Set RB1:RB0 as inputs
; RB5:RB2 as outputs
9.2.3
RB2/T0CLK/INT0
The RB2 pin is configurable to function as a general
I/O, the clock input for TIMER0, or as an external edge
triggered interrupt. Figure 9-2 shows the block diagram
of this I/O pin. Refer to Section 8.0 for details about
interrupts and Section 10.0 for details about TIMER0.
TRISB
Read-modify-write operations on the LATB register,
read and write the latched output value for PORTB.
Figure 9-1 shows a simplified block diagram of the
PORTB/LATB/TRISB operation.
9.2.4
RB3/MCLR/VPP
The RB3 pin is configurable to function as general I/O
or as the RESET pin, MCLR. This pin is open drain
when configured as an output. Refer to Figure 9-3 for a
block diagram of the I/O pin.
FIGURE 9-1:
SIMPLIFIED BLOCK
DIAGRAM OF PORT/LAT/
TRIS OPERATION
Note: The voltage on RB3 open drain output
must not exceed VDD.
RD LAT
TRIS
9.2.5
RB4/OSC2/CLKOUT
D
Q
The RB4 pin is configurable to function as a general
I/O pin, oscillator connection, or as a clock output.
Figure 9-4 shows the block diagram of this I/O pin.
Refer to Section 2.0 for clock/oscillator information.
WR LAT +
WR Port
CK
Data Latch
Data Bus
9.2.6
RB5/OSC1/CLKIN
I/O pin
The RB5 pin is configurable to function as a general
I/O pin, oscillator connection, or a clock input pin.
Figure 9-5 shows a block diagram of this I/O pin. Refer
to Section 2.0 for clock /oscillator information.
RD Port
9.2
Additional Functions
Each pin is multiplexed with other functions. Refer to
Table 9-1 for information about individual pin functions.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 67
PIC18F010/020
FIGURE 9-2:
BLOCK DIAGRAM OF
RB<2:0> PINS
FIGURE 9-3:
BLOCK DIAGRAM OF
RB3 PIN
VDD
VDD
WPUBx(2)
Data Bus
WPUBx(2)
Data Bus
Weak
Weak
P
P
Pull-up
Pull-up
Data Latch
Open Drain
Data Latch
D
Q
D
Q
I/O
I/O
WR LATB
or
PORTB
pin(1)
WR LATB
or
PORTB
pin(1)
CK
TRIS Latch
CK
TRIS Latch
D
Q
D
Q
WR TRISB
TTL
Input
Buffer
CK
WR TRISB
TTL
Input
Buffer
CK
ST
Buffer
ST
Buffer
RD TRISB
RD LATB
RD TRISB
RD LATB
Latch
Latch
D
Q
D
Q
EN
Q4
RD PORTB
EN
Q4
RD PORTB
IOCB Register
IOCB Register
D
Q
D
Q
WR IOCB
Set RBIF
CK
WR IOCB
Set RBIF
CK
Q
D
From other
RB pins
RD PORTB
Q3
Q
D
EN
From other
RB pins
RD PORTB
Q3
EN
RB2/T0CKI/INT0
RB<1:0> in Serial Programming mode
MCLR
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the WPUB bit(s) and RBPU bit.
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the WPUB bit(s) and RBPU bit.
DS41142A-page 68
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
FIGURE 9-4:
BLOCK DIAGRAM OF
RB4 PIN
FIGURE 9-5:
BLOCK DIAGRAM OF
RB5 PIN
VDD
VDD
WPUBx(2)
Data Bus
WPUBx(2)
Data Bus
Weak
P
Weak
P
Pull-up
Pull-up
Data Latch
Data Latch
D
Q
D
Q
I/O
I/O
WR LATB
or
PORTB
pin(1)
CK
TRIS Latch
WR LATB
or
PORTB
pin(1)
CK
TRIS Latch
D
Q
D
Q
WR TRISB
TTL
Input
Buffer
WR TRISB
TTL
Input
Buffer
CK
CK
ST
Buffer
RD TRISB
RD LATB
RD TRISB
RD LATB
Latch
Latch
Q
D
Q
D
EN
Q4
RD PORTB
EN
Q4
RD PORTB
IOCB Register
IOCB Register
D
Q
D
Q
WR IOCB
Set RBIF
WR IOCB
CK
CK
Q
D
From other
RB pins
Q
D
From other
RB pins
RD PORTB
Q3
RD PORTB
Q3
EN
EN
CLKOUT
CLKIN
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the WPUB bit(s) and RBPU bit.
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the WPUB bit(s) and RBPU bit.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 69
PIC18F010/020
REGISTER 9-1:
WPUB: WEAK PULL-UP REGISTER (ADDRESS 0XF79h)
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
—
—
WPUB5
WPUB4
WPUB3
WPUB2 WPUB1 WPUB0
bit 0
bit 7
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
WPUB<5:0>: Weak Pull-up Register bit
1= Pull-up disabled
0= Pull-up enabled
Note 1: Global RBPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in output mode
(TRIS = 0).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
REGISTER 9-2:
IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER (ADDRESS 0XF78h)
U-0
U-0
R/W-0
IOCB5
R/W-0
IOCB4
R/W-0
IOCB3
R/W-0
IOCB2
R/W-0
IOCB1
R/W-0
IOCB0
—
—
bit 7
bit 0
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
IOCB<5:0>: Interrupt-on-Change PORTB Control bit
1= Interrupt-on-change enabled
0= Interrupt-on-change disabled
Note 1: Global interrupt enables (GIE and RBIE) must be enabled for individual interrupts to
be recognized.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS41142A-page 70
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
TABLE 9-1:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0
bit0
TTL/ST(1)
Input/output port pin (with interrupt-on-change).
Internal software programmable weak pull-up. In-circuit serial
programming data.
RB1
bit1
TTL/ST(1)
Input/output port pin (with interrupt-on-change).
Internal software programmable weak pull-up. In-circuit serial
programming clock.
RB2/T0CKI/
INT0
bit2
bit3
TTL/ST(1)
TTL/ST(1)
Input/output port pin (with interrupt-on-change) or TMR0 clock input or
Interrupt 0 input. Internal software programmable weak pull-up.
RB3/MCLR/
VPP
Input/output (open drain) port pin (with interrupt-on-change) or Master
Clear External Reset input. Internal software programmable
weak pull-up.
RB4/OSC2/
CLKOUT
bit4
bit5
TTL/ST(1)
TTL/ST(1)
Input/output port pin (with interrupt-on-change) or oscillator connection, or
CLKOUT output. Internal software programmable weak pull-up.
RB5/OSC1/
CLKIN
Input/output port pin (with interrupt-on-change) or clock input, or oscillator
connection. Internal software programmable weak pull-up.
Legend:
TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 9-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on:
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISB
PORTB
LATB
—
—
—
—
—
—
RB5
RB4
RB3
RB2
RB1
RB0
--11 1111 --11 1111
PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 --xx xxxx --uu uuuu
LATB5
T0IE
—
LATB4
INT0E
—
LATB3
RBIE
—
LATB2
T0IF
LATB1
INT0F
—
LATB0 --xx xxxx --uu uuuu
INTCON GIE/GIEH PEIE/GIEL
RBIF
RBIP
0000 000x 0000 000u
11-- -1-1 11-- -1-1
INTCON2
WPUB
IOCB
RBPU
—
INTEG0
T0IP
—
—
WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 --11 1111 --11 1111
IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 --00 0000 --00 0000
—
Legend: x= unknown, u= unchanged, - = unimplemented. Shaded cells are not used by PORTB.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 71
PIC18F010/020
NOTES:
DS41142A-page 72
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
Figure 10-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 10-1 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
10.0 TIMER0 MODULE
The Timer0 module has the following features:
• Software selectable as an 8-bit or 16-bit timer/
counter
The T0CON register is a readable and writable register
that controls all the aspects of Timer0, including the
prescale selection.
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt on overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
• Edge select for external clock
REGISTER 10-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
TMR0ON
T08BIT
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-bit/16-bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 prescale value
110= 1:128 prescale value
101= 1:64 prescale value
100= 1:32 prescale value
011= 1:16 prescale value
010= 1:8 prescale value
001= 1:4 prescale value
000= 1:2 prescale value
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 73
PIC18F010/020
FIGURE 10-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
FOSC/4
0
1
8
0
Sync with
Internal
Clocks
TMR0
Programmable
Prescaler
RB2/T0CKI
Pin
1
(2 TCY Delay)
T0SE
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS
Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 10-2:
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
FOSC/4
0
0
Sync with
Set Interrupt
Flag bit TMR0IF
on Overflow
TMR0
High Byte
Internal
Clocks
1
TMR0L
Programmable
Prescaler
T0CKI Pin
1
8
(2 TCY delay)
T0SE
3
Read TMR0L
T0PS2, T0PS1, T0PS0
T0CS
Write TMR0L
PSA
8
8
TMR0H
8
Data Bus<7:0>
Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS41142A-page 74
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
10.2.1
SWITCHING PRESCALER
ASSIGNMENT
10.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
The prescaler assignment is fully under software con-
trol, (i.e., it can be changed “on-the-fly” during program
execution).
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 regis-
ter is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
10.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or FFFFh
to 0000h in 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IE bit must be cleared in soft-
ware by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from SLEEP, since the
timer is shut off during SLEEP.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment either on every
rising, or falling edge, of pin RB2/T0CKI. The incre-
menting edge is determined by the Timer0 Source
Edge Select bit (T0SE). Clearing the T0SE bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
10.4 16-bit Mode Timer Reads and
Writes
TMR0H is not the high byte of the timer/counter in 16-
bit mode, but is actually a buffered version of the high
byte of Timer0 (refer to Figure 10-1). The high byte of
the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16 bits of Timer0 without
having to verify that the read of the high and low byte
were valid, due to a rollover between successive reads
of the high and low byte.
10.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module. The prescaler is not readable or writ-
able.
The PSA and T0PS2:T0PS0 bits determine the pres-
caler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
A write to the high byte of Timer0 must also take place
through the TMR0H buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16 bits of Timer0 to
be updated at once.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF TMR0, MOVWF
TMR0, BSF TMR0, x....etc.) will clear the prescaler
count.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0
Value on all
other
Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
RESETS
TMR0L
TMR0H
Timer0 Module’s Low Byte Register
Timer0 Module’s High Byte Register
xxxx xxxx
0000 0000
0000 000x
uuuu uuuu
0000 0000
0000 000u
1111 1111
--11 1111
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
PSA
TMR0IF INT0IF
RBIF
T0CON
TRISB
TMR0ON
T08BIT
T0CS
T0SE
T0PS2
T0PS1 T0PS0 1111 1111
—
—
PORTB Data Direction Register
--11 1111
Legend: x= unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 75
PIC18F010/020
NOTES:
DS41142A-page 76
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
The Low Voltage Detect circuitry is completely under
software control. This allows the circuitry to be "turned
off" by the software, which minimizes the current con-
sumption for the device.
11.0 LOW VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application soft-
ware can do "housekeeping tasks" before the device
voltage exits the valid operating range. This can be
done using the Low Voltage Detect module.
Figure 11-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shut down the system. Voltage point VB is the
minimum valid operating voltage specification. This
occurs at time TB. TB - TA is the total time for shut
down.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the voltage of the device becomes lower then the
specified point, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the inter-
rupt vector address and the software can then respond
to that interrupt source.
FIGURE 11-1:
TYPICAL LOW VOLTAGE DETECT APPLICATION
VA
VB
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
TB
TA
Time
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 77
PIC18F010/020
Figure 11-2 shows the block diagram for the LVD mod-
ule. A comparator uses an internally generated refer-
ence voltage as the set point. When the selected tap
output of the device voltage crosses the set point (is
lower than), the LVDIF bit is set.
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the voltage
generated by the internal voltage reference module.
The comparator then generates an interrupt signal, set-
ting the LVDIF bit. This voltage is software program-
mable to any one of 16 values (see Figure 11-2). The
trip point is selected by programming the
LVDL3:LVDL0 bits (LVDCON<3:0>).
Each node in the resister divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the
FIGURE 11-2:
LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM
VDD
LVDIN
LVD Control
Register
LVDIF
Internally Generated
Reference Voltage
LVDEN
DS41142A-page 78
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
11.1 Control Register
The Low Voltage Detect Control register controls the
operation of the Low Voltage Detect circuitry.
REGISTER 11-1: LVDCON REGISTER
U-0
U-0
R-0
R/W-0
R/W-0
LVV3
R/W-1
LVV2
R/W-0
LVV1
R/W-1
LVV0
—
—
BGST
LVDEN
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as '0'
BGST: Bandgap Stable Status Flag bit
1= Indicates that the bandgap voltage is stable and LVD interrupt is reliable
0= Indicates that the bandgap voltage is not stable and LVD interrupt should not be enabled
bit 4
LVDEN: Low Voltage Detect Power Enable bit
1= Enables LVD, powers up LVD circuit and bandgap reference generator
0= Disables LVD, powers down LVD and bandgap circuits
bit 3-0
LVV3:LVV0: Low Voltage Detection Limit bits
1111= Reserved
1110= Reserved
1101= 4.0V
1100= 3.5V
1011= 3.0V
1010= 2.9V
1001= 2.8V
1000= 2.7V
0111= 2.6V
0110= 2.5V
0101= 2.4V
0100= 2.3V
0011= 2.2V
0010= 2.1V
0001= 2.0V
0000= 1.9V
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset
Note: This register must be unlocked to modify, see Section 12.4.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 79
PIC18F010/020
The following steps are needed to set up the LVD
module:
11.2 Operation
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be con-
stantly operating. To decrease the current require-
ments, the LVD circuitry only needs to be enabled for
short periods, where the voltage is checked. After
doing the check, the LVD module may be disabled.
1. Unlock the LVDCON register using the unlock
sequence described in Section 12.4.
2. Write the value to the LVDL3:LVDL0 bits
(LVDCON register), which selects the desired
LVD Trip Point.
3. Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
4. Enable the LVD module (set the LVDEN bit in
the LVDCON register).
5. Wait for the LVD module to stabilize (the IRVST
bit to become set).
6. Clear the LVD interrupt flag, which may have
falsely become set until the LVD module has
stabilized (clear the LVDIF bit).
7. Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 11-3 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 11-3:
LOW VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set
VDD
VLVD
LVDIF
Enable LVD
50 ms
Internally Generated
Reference Stable
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
50 ms
Internally Generated
Reference Stable
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
DS41142A-page 80
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
11.2.1
CURRENT CONSUMPTION
11.3 Operation During SLEEP
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static cur-
rent. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D423 on page 147.
When enabled, the LVD circuitry continues to operate
during SLEEP. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wake-
up from SLEEP. Device execution will continue from
the interrupt vector address, if interrupts have been glo-
bally enabled.
11.4 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the LVD module to be turned off.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 81
PIC18F010/020
NOTES:
DS41142A-page 82
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
These devices have a Watchdog Timer, which is per-
manently enabled via the configuration bits or software-
controlled. It runs off its own internal oscillator for
added reliability. There are two timers that offer neces-
sary delays on power-up. One is the Oscillator Start-up
Timer (OST), intended to keep the chip in RESET until
the crystal oscillator is stable. The other is the Power-
up Timer (PWRT), which provides a fixed delay on
power-up only, designed to keep the part in RESET
while the power supply stabilizes. With these two tim-
ers on-chip, most applications need no external
RESET circuitry.
12.0 SPECIAL FEATURES OF THE
CPU
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection. These are:
• OSC Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external RESET, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The internal oscillator option saves system cost, while
the LP crystal option saves power. A set of configura-
tion bits are used to select various options.
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-Circuit Serial ProgrammingTM
12.1 Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h - 3FFFFFh),
which can only be accessed using table reads and
table writes.
TABLE 12-1: CONFIGURATION BITS AND DEVICE IDS
Factory/
Programmed
Value
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300000h
CONFIG1L
CONFIG1H
CONFIG2L
CONFIG2H
FOSCCAL
—
—
TR1
—
TW1
OSCEN
—
CP1
MCLRE
—
DP
—
TR0
FOSC2
—
TW0
CP0
-111 1111
--01 -100
---- --11
1-11 1111
--uu uuuu
0000 0000
01dr rrrr
0000 0011
300001h
300002h
300003h
300104h
300105h
3FFFFEh
3FFFFFh
FOSC1
BOREN
WDPS0
FCAL1
FOSC0
PWRTE
WDTE
FCAL0
—
—
—
reserved
—
—
STVRE
FCAL5
WDTLE
FCAL4
WDPS2
FCAL3
WDPS1
FCAL2
—
Unused. Always reads ‘0’s.
DEVID1
DEVID2
DEV2
DEV1
DEV9
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
DEV10
Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition, grayed cells are unimplemented, read as ‘0’
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 83
PIC18F010/020
REGISTER 12-1: CONFIG1H: CONFIGURATION BYTE (ADDRESS 300001h)
U-0
U-0
U-0
R/P-1
U-0
R/P-1
R/P-0
R/P-0
FOSC0
bit 0
—
—
OSCEN
MCLRE
—
FOSC2 FOSC1
bit 7
bit 7-6
bit 5
Unimplemented: Read as ’0’
OSCEN: Oscillator Enable bit
1= Switching to the internal oscillator is enabled
0= Switching to the internal oscillator is disabled
bit 4
MCLRE: RB3/MCLR Pin Function Select bit
1= RB3/MCLR pin function is MCLR
0= RB3/MCLR pin function is digital I/O, MCLR internally tied to VDD
bit 3
Unimplemented: Read as ’0’
bit 2-0
FOSC2:FOSC0: Oscillator Selection bits
111= External RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin
110= EC external clock/CLKOUT function on RB4/OSC2/CLKOUT pin
101= Internal oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin,
RB5 function on RB5/OSC1/CLKIN pin
100= Internal oscillator/RB4 function on RB4/OSC2/CLKOUT pin,
RB5 function on RB5/OSC1/CLKIN pin
011= External RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin
010= HS oscillator
001= XT oscillator
000= LP oscillator
Legend:
R = Readable bit
W = Writable bit
1 = Bit is set
U = Unimplemented bit, read as ‘0’
0 = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41142A-page 84
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
REGISTER 12-2: CONFIG1L: CONFIGURATION BYTE (ADDRESS 300000h)
U-0
R/P-1
TR1
R/P-1
TW1
R/P-1
CP1
R/P-1
DP
R/P-1
TR0
R/P-1
TW0
R/P-1
CP0
—
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
TR1: Table Read Protection bit (memory area > 0400h byte address)
1= Table reads are enabled
0= Table reads are disabled from access outside of this block
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TW1: Table Write Protection bit (memory area > 0400h byte address)
1= Table writes are enabled
0= Table writes are disabled from access outside of this block
CP1: Code Protection bit (memory area > 0400h byte address)
1= Program memory code protection off
0= Program memory code protected
DP: Data Protection bit for EEDATA Memory
1= External reads and writes are enabled
0= External reads and writes are disabled
TR0: Table Read Protection bit (memory area > 0000h - 03FFh byte address)
1= Table reads are enabled
0= Table reads are disabled from access outside of this block
TW0: Table Write Protection bit (memory area > 0000h - 03FFh byte address)
1= Table writes are enabled
0= Table writes are disabled from access outside of this block
CP0: Code Protection bit (memory area > 0000h - 03FFh byte address)
1= Program memory code protection off
0= Program memory code protected
Legend:
R = Readable bit
W = Writable bit
1 = Bit is set
U = Unimplemented bit, read as ‘0’
0 = Bit is cleared x = Bit is unknown
- n = Value at POR
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 85
PIC18F010/020
REGISTER 12-3: CONFIG2H: CONFIGURATION REGISTER 2H (ADDRESS 300003h)
R/P-1
reserved
bit 7
U-0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
—
STVRE
WDTLE
WDPS2
WDPS1
WDPS0
WDTE
bit 0
bit 7
bit 6
bit 5
Reserved
Unimplemented: Read as ’0’
STVRE: Stack Full/Underflow Reset Enable bit
1= Reset on stack full/underflow enabled
0= Disabled
bit 4
WDTLE: Watchdog Timer Long Delay Enable bit
1= Use WDPS<2:0> bits to set delay
0= Enable long postscaler divider; 16 x WDPS<2:0> bits
bit 3-1
WDPS2:WDPS0: Watchdog Timer Postscale Select bits
111= 1:128
110= 1:64
101= 1:32
100= 1:16
011= 1:8
010= 1:4
001= 1:2
000= 1:1
bit 0
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on the SWDTE bit)
Legend:
R = Readable bit
W = Writable bit
1 = Bit is set
U = Unimplemented bit, read as ‘0’
0 = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41142A-page 86
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
REGISTER 12-4: CONFIG2L: CONFIGURATION REGISTER 2L (ADDRESS 300002h)
U-0
U-0
U-0
U-0
U-0
U-0
R/P-1
R/P-1
PWRTE
bit 0
—
—
—
—
—
—
BOREN
bit 7
bit 7-2
bit 1
Unimplemented: Read as ’0’
BOREN: Brown-out Reset Enable bit(1)
1= Brown-out Reset enabled
0= Brown-out Reset disabled
bit 0
PWRTE: Power-up Timer Enable bit(1)
1= PWRT disabled
0= PWRT enabled
Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT),
regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled any
time Brown-out Reset is enabled.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
1 = Bit is set
U = Unimplemented bit, read as ‘0’
0 = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 87
PIC18F010/020
The WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT postscaler may be assigned using
the configuration bits or in software.
12.2 Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator, which does not require any external compo-
nents. This RC oscillator is separate from the internal
oscillator of the OSC1/CLKI pin. That means that the
WDT will run, even if the clock on the OSC1/CLKI and
OSC2/CLKO/RA6 pins of the device has been stopped,
for example, by execution of a SLEEPinstruction.
Note: The CLRWDTand SLEEPinstructions clear
the WDT and the postscaler, if assigned to
the WDT and prevent it from timing out and
generating a device RESET condition.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the RCON register
will be cleared upon a WDT time-out.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software exe-
cution may not disable this function. When the WDTEN
configuration bit is cleared, the SWDTEN bit enables/
disables the operation of the WDT.
12.2.1
CONTROL REGISTER
Register 12-5 shows the WDTCON register. This is a
readable and writable register, which contains a control
bit that allows software to override the WDT enable
configuration bit, only when the configuration bit has
disabled the WDT.
REGISTER 12-5: WDTCON REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
SWDTEN
bit 0
—
—
—
—
—
—
—
bit 7
bit 7-1
bit 0
Unimplemented: Read as ’0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1= Watchdog Timer is on
0= Watchdog Timer is turned off
Legend:
R = Readable bit
W = Writable bit
1 = Bit is set
U = Unimplemented bit, read as ‘0’
0 = Bit is cleared x = Bit is unknown
- n = Value at POR
Note: This register must be unlocked to modify, see Section 12.4.
DS41142A-page 88
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
The standard settings are also available in software
when not setup in the CONFIG2H configuration. The
WDTCON register allows enabling the WDT and set-
ting the standard postscaler options.
12.2.2
WDT POSTSCALER
The WDT has a postscaler that can extend the WDT
Reset period. The postscaler is selected at the time of
the device programming, by the value written to the
CONFIG2H configuration register. An extended WDT
is also available, multiplying the standard settings by
16.
Note: The WDTCON register must be unlocked
before it can be modified (see
Section 12.4.1).
FIGURE 12-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDT Timer
Postscaler
8
÷ 16
WDTLE
8 - to - 1 MUX
WDTPS2:WDTPS0
WDTEN
Configuration bit
SWDTEN bit
WDT
Time-out
Note: WDPS2:WDPS0 are bits in a configuration register.
TABLE 12-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG2H
RCON
reserved
IPEN
—
—
—
—
STVRE
—
WDTLE
RI
WDTPS2
TO
WDTPS2
PD
WDTPS0
POR
WDTEN
BOR
WDTCON
—
—
—
—
—
SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 89
PIC18F010/020
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
12.3 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and will cause a "wake-up". The TO and PD
bits in the RCON register can be used to determine the
cause of the device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared, if a WDT time-out occurred (and caused
wake-up).
instruction.
If enabled, the Watchdog Timer will be cleared, but
keeps running, the PD bit (RCON<3>) is cleared, the
TO (RCON<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, and disable
external clocks. Pull all I/O pins that are hi-impedance
inputs, high or low externally, to avoid switching cur-
rents caused by floating inputs. The T0CKI input should
also be at VDD or VSS for lowest current consumption.
The contribution from on-chip pull-ups should be
considered.
When the SLEEPinstruction is being executed, the next
instruction (PC + 2) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
The MCLR pin must be at a logic high level (VIHMC), if
enabled.
12.3.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or a
Peripheral Interrupt.
DS41142A-page 90
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
12.3.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If an interrupt condition (interrupt flag bit and inter-
rupt enable bits are set) occurs before the execu-
tion of a SLEEPinstruction, the SLEEPinstruction
will complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
12.3.3
TWO-SPEED CLOCK START-UP
When using an external clock source, wake-up from
SLEEP causes a unique start-up procedure. The inter-
nal oscillator starts immediately upon wake-up, while
the external source is stabilizing. Once the Oscillator
Start-up Time-out (OST) is complete, the clock source
is switched to the external clock. The result is nearly
immediate code execution upon wake-up. Refer to
Section 2.6.
• If the interrupt condition occurs during or after
the execution of a SLEEPinstruction, the device
will immediately wake-up from SLEEP. The
SLEEPinstruction will be completely executed
before the wake-up. Therefore, the WDT and
WDT postscaler will be cleared, the TO bit will be
set and the PD bit will be cleared.
FIGURE 12-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(2)
TOST
(4)
CLKOUT
INT pin
INTF Flag
(INTCON<1>)
(3)
Interrupt Latency
GIEH bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+2
PC+4
PC+4
PC + 4
0008h
000Ah
Instruction
Inst(0008h)
Inst(PC + 2)
Inst(PC + 4)
Inst(000Ah)
Inst(PC) = SLEEP
Inst(PC - 1)
Fetched
Instruction
Executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 2)
Inst(0008h)
Note 1: XT, HS or LP oscillator mode assumed.
2: GIE = ’1’ assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
3: TOST = 1024TOSC (drawing not to scale) This delay will not occur for external RC oscillator, EC osc, and INTOSC modes.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 91
PIC18F010/020
When each bit is set and the combination lock is
opened, the user will have three instruction cycles to
modify the safety critical register of his choice. After
three cycles have expired, the CMLK bits are cleared,
the lock will close, and the user will have to set the
CMLK bits in sequence again, in order to open the lock.
Thus, for each attempt to modify a safety critical regis-
ter, the combination lock must be opened before the
register can be written to. The reason that three instruc-
tion cycles were chosen for the unlock time was to
allow the user to put the "unlock" code in a subroutine
call. This way, the user’s code will only have one
instance of the code that is used to unlock the module.
The user would first set up the WREG register with the
desired data to load into a secured register, then call a
subroutine that contains the two BSFinstructions, return
from the routine, and modify the secured register.
12.4 Secured Access Registers
This device contains programming options for safety
critical peripherals. Because these safety critical
peripherals can be programmed in software, the regis-
ters used to control these peripherals should be given
limited access by the user’s code. This way, errant
code won’t accidentally change settings in peripherals
that could cause catastrophic results.
The registers that are considered safety critical are the
Watchdog Timer Control register (WDTCON), the Low
Voltage Detect register (LVDTCON), and the Oscillator
Control register (OSCCON).
12.4.1
COMBINATION LOCK MODULE
Access is limited to using the Combination Lock
module.
;Setup WREG with data to be stored
; in a safety critical register
MAIN
Two bits called Combination Lock (CMLK) bits are
located in the lower two bits of the PSPCON register.
These two bits, and only these two bits, must be set in
sequence by the user’s code.
MOVLW
CALL
0x5A
UNLOCK
The Combination Lock bits must be set sequentially,
meaning that as soon as Combination Lock bit 1 is set,
the second Combination Lock bit must be set on the
following instruction cycle. If the user waits more than
one machine cycle to set the second bit after setting the
first, both bits will automatically be cleared in hardware,
and the lock will remain closed.
;Write must take place on next
;instruction cycle
MOVWF
OSCCON, 0
.
.
.
UNLOCK
Each instruction must only modify one combination
lock bit at a time. This means that the first write to the
register will write the CMLK1 to a ’1’, but CMLK0 will
equal ’0’. The second write will only modify CMLK0.
This means that the data written to the PSPCON regis-
ter will have CMLK1 set to a ’1’ and CMLK0 set to a ’1’.
This leaves CMLK1 unmodified. This will restrict at
least one of the instructions used to modify this register
to a BSFof the PSPCON register. This will restrict the
combination of instructions that will allow the lock to be
opened, so that random code execution in the event of
a software fault, will not cause the lock to be acciden-
tally opened. The BSF instruction limitation will also
prevent random code from setting both bits at the same
time via a MOVWFinstruction, since they are located in
the same register.
BSF
BSF
RETURN
PSPCON, CMLK1, 0
PSPCON, CMLK0, 0
Note: The Combination lock bits are write only
bits. These bits will always return ‘0’ when
read.
DS41142A-page 92
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
12.5 Program Verification/Code
Protection
12.7
In-Circuit Serial Programming
PIC18F010/020 microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and two
other lines for power and ground. This allows custom-
ers to manufacture boards with unprogrammed
devices, and then program the microcontroller just
before shipping the product. This also allows the most
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
Note: Microchip Technology does not recom-
mend code protecting windowed devices.
recent firmware or
programmed.
a custom firmware to be
12.6 ID Locations
Five memory locations (200000h - 200007h) are desig-
nated as ID locations, where the user can store check-
sum or other code identification numbers. These
locations are accessible during normal execution
through the TBLRD instruction or during program/
verify. The ID locations can be read when the device is
code protected.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 93
PIC18F010/020
NOTES:
DS41142A-page 94
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
The control instructions may use some of the following
operands:
13.0 INSTRUCTION SET SUMMARY
The PIC18F010/020 instruction set adds many
enhancements to the previous PICmicro® instruction
sets, while maintaining an easy migration from these
PICmicro instruction sets.
• A program memory address (specified by the
value of ’n’)
• The mode of the Call or Return instructions (spec-
ified by the value of ’s’)
Most instructions are a single program memory word
(16-bits), but there are four instructions that require two
program memory locations.
• The mode of the Table Read and Table Write
instructions (specified by the value of ’m’)
• No operand required
(specified by the value of ’—’)
Each single word instruction is a 16-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction.
All instructions are a single word, except for four double
word instructions. These four instructions were made
double word instructions so that all the required infor-
mation is available in these 32-bits. In the second word,
the 4 MSb’s are 1’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
All single word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
• Control operations
The PIC18F010/020 instruction set summary in
Table 13-2 lists byte-oriented, bit-oriented, literal
and control operations. Table 13-1 shows the opcode
field descriptions.
The double word instructions execute in two instruction
cycles.
Most byte-oriented instructions have three operands:
1. The file register (specified by the value of ’f’)
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 µs. Two
word branch instructions (if true) would take 3 µs.
2. The destination of the result
(specified by the value of ’d’)
3. The accessed memory
(specified by the value of ’a’)
'f' represents a file register designator and 'd' repre-
sents a destination designator. The file register desig-
nator specifies which file register is to be used by the
instruction.
Figure 13-1 shows the general formats that the instruc-
tions can have.
All examples use the following format to represent a
hexadecimal number:
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the WREG register. If 'd' is one, the result is
placed in the file register specified in the instruction.
0xhh
where h signifies a hexadecimal digit.
The Instruction Set Summary, shown in Table 13-2,
lists the instructions recognized by the Microchip
assembler (MPASMTM).
All bit-oriented instructions have three operands:
1. The file register (specified by the value of ’f’)
Section 13.1 provides a description of each instruction.
2. The bit in the file register
(specified by the value of ’b’)
3. The accessed memory
(specified by the value of ’a’)
'b' represents a bit field designator which selects the
number of the bit affected by the operation, while 'f' rep-
resents the number of the file in which the bit is located.
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
(specified by the value of ’k’)
• The desired FSR register to load the literal value
into (specified by the value of ’f’)
• No operand required
(specified by the value of ’—’)
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 95
PIC18F010/020
TABLE 13-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
ACCESS
BANKED
bbb
ACCESS = 0: RAM access bit symbol
BANKED = 1: RAM access bit symbol
Bit address within an 8-bit file register (0 to 7)
Bank Select Register. Used to select the current RAM bank.
BSR
d
Destination select bit;
d = 0: store result in WREG,
d = 1: store result in file register f.
dest
f
Destination either the WREG register or the specified register file location
8-bit Register file address (0x00 to 0xFF)
fs
12-bit Register file address (0x000 to 0xFFF). This is the source address.
fd
12-bit Register file address (0x000 to 0xFFF). This is the destination address.
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
Label name
The mode of the TBLPTR register for the Table Read and Table Write instructions
Only used with Table Read and Table Write instructions:
label
mm
*
No Change to register (such as TBLPTR with Table reads and writes)
Post-Increment register (such as TBLPTR with Table reads and writes)
Post-Decrement register (such as TBLPTR with Table reads and writes)
Pre-Increment register (such as TBLPTR with Table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions, or the direct
address for Call/Branch and Return instructions
PRODH
PRODL
s
Product of Multiply high byte (Register at address 0xFF4)
Product of Multiply low byte (Register at address 0xFF3)
Fast Call / Return mode select bit.
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
u
Unused or Unchanged (Register at address 0xFE8)
W = 0: Destination select bit symbol
W
WREG
x
Working register (accumulator) (Register at address 0xFE8)
Don't care (0 or 1)
The assembler will generate code with x = 0. It is the recommended form of use for compatibility
with all Microchip software tools.
TBLPTR
TABLAT
TOS
21-bit Table Pointer (points to a Program Memory location) (Register at address 0xFF6)
8-bit Table Latch (Register at address 0xFF5)
Top-of-Stack
PC
Program Counter
PCL
Program Counter Low Byte (Register at address 0xFF9)
Program Counter High Byte
PCH
PCLATH
PCLATU
GIE
Program Counter High Byte Latch (Register at address 0xFFA)
Program Counter Upper Byte Latch (Register at address 0xFFB)
Global Interrupt Enable bit
WDT
Watchdog Timer
TO
Time-out bit
PD
Power-down bit
C, DC, Z, OV, N ALU status bits Carry, Digit Carry, Zero, Overflow, Negative
[ ]
Optional
( )
Contents
→
Assigned to
< >
∈
Register bit field
In the set of
italics
User defined term (font is courier)
DS41142A-page 96
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
FIGURE 13-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
Example Instruction
15
10
9
d
8
7
0
OPCODE
a
f (FILE #)
ADDWF MYREG, W, B
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select Bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
OPCODE
f (Source FILE #)
MOVFF MYREG1, MYREG2
BSF MYREG, bit, B
MOVLW 0x7F
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11
9
8
7
0
OPCODE b (BIT #)
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select Bank
f = 8-bit file register address
Literal operations
15
8
7
0
OPCODE
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
0
OPCODE
12 11
n<7:0> (literal)
GOTO Label
15
1111
n<19:8> (literal)
n = 20-bit immediate value
8 7
15
15
0
0
CALL MYFUNC
OPCODE
12 11
n<7:0> (literal)
S
1111
n<19:8> (literal)
S = Fast bit
11 10
15
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
15
OPCODE
n<10:0> (literal)
8 7
n<7:0> (literal)
4
15
6
0
LFSR FSR0, 0x100
OPCODE
f
k (literal)
15
11
0000
7
0
1111
k (literal)
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 97
PIC18F010/020
TABLE 13-2: PIC18F010/020 INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Status
Affected
Description
Cycles
Notes
Operands
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF f [,d] [,a] Add WREG and f
1
1
1
1
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2, 6
0010 00da ffff ffff C, DC, Z, OV, N 1, 2, 6
0001 01da ffff ffff Z, N
0110 101a ffff ffff Z
0001 11da ffff ffff Z, N
ADDWFC f [,d] [,a] Add WREG and Carry bit to f
ANDWF
CLRF
COMF
f [,d] [,a] AND WREG with f
f [,a] Clear f
f [,d] [,a] Complement f
1,2, 6
2, 6
1, 2, 6
4, 6
4, 6
1, 2, 6
CPFSEQ f [,a]
CPFSGT f [,a]
CPFSLT f [,a]
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
1 (2 or 3) 0110 001a ffff ffff None
1 (2 or 3) 0110 010a ffff ffff None
1 (2 or 3) 0110 000a ffff ffff None
DECF
f [,d] [,a] Decrement f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4, 6
DECFSZ f [,d] [,a] Decrement f, Skip if 0
DCFSNZ f [,d] [,a] Decrement f, Skip if Not 0
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1, 2, 3, 4, 6
1, 2, 6
INCF
f [,d] [,a] Increment f
1
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4, 6
INCFSZ
INFSNZ
IORWF
MOVF
f [,d] [,a] Increment f, Skip if 0
f [,d] [,a] Increment f, Skip if Not 0
f [,d] [,a] Inclusive OR WREG with f
f [,d] [,a] Move f
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4, 6
1, 2, 6
1, 2, 6
1, 6
1
1
2
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF
f , f
Move f (source) to 1st word
s
d
s
f (destination)2nd word
d
MOVWF f [,a]
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N 1, 2, 6
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
6
6
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
f [,a]
f [,a]
f [,d] [,a] Rotate Left f through Carry
f [,d] [,a] Rotate Left f (No Carry)
f [,d] [,a] Rotate Right f through Carry
f [,d] [,a] Rotate Right f (No Carry)
6
1, 2, 6
6
6
6
f [,a]
Set f
SUBFWB f [,d] [,a] Subtract f from WREG with
borrow
0101 01da ffff ffff C, DC, Z, OV, N 1, 2, 6
SUBWF
f [,d] [,a] Subtract WREG from f
1
1
0101 11da ffff ffff C, DC, Z, OV, N
0101 10da ffff ffff C, DC, Z, OV, N 1, 2, 6
6
SUBWFB f [,d] [,a] Subtract WREG from f with
borrow
SWAPF
TSTFSZ f [,a]
XORWF f [,d] [,a] Exclusive OR WREG with f
BIT-ORIENTED FILE REGISTER OPERATIONS
f [,d] [,a] Swap nibbles in f
1
0011 10da ffff ffff None
4, 6
1, 2, 6
6
Test f, skip if 0
1 (2 or 3) 0110 011a ffff ffff None
1
0001 10da ffff ffff Z, N
BCF
BSF
BTFSC
BTFSS
BTG
f, b [,a] Bit Clear f
f, b [,a] Bit Set f
f, b [,a] Bit Test f, Skip if Clear
f, b [,a] Bit Test f, Skip if Set
f [,d] [,a] Bit Toggle f
1
1
1001 bbba ffff
1000 bbba ffff
ffff None
ffff None
ffff None
ffff None
ffff None
1, 2, 6
1, 2, 6
3, 4, 6
3, 4, 6
1, 2, 6
1 (2 or 3) 1011 bbba ffff
1 (2 or 3) 1010 bbba ffff
1
0111 bbba ffff
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
6: Microchip Assembler MASM automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’
according to address of register being used.
DS41142A-page 98
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
TABLE 13-2: PIC18F010/020 INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address1st word
2nd word
1 (2)
1110 0010 nnnn
1110 0110 nnnn
1110 0011 nnnn
1110 0111 nnnn
1110 0101 nnnn
1110 0001 nnnn
1110 0100 nnnn
1101 0nnn nnnn
1110 0000 nnnn
1110 110s kkkk
1111 kkkk kkkk
0000 0000 0000
0000 0000 0000
1110 1111 kkkk
1111 kkkk kkkk
0000 0000 0000
1111 xxxx xxxx
0000 0000 0000
0000 0000 0000
1101 1nnn nnnn
0000 0000 1111
0000 0000 0001
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
kkkk None
kkkk
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
CALL
CLRWDT
DAW
GOTO
—
—
n
1
1
2
0100 TO, PD
0111
C
kkkk None
kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
1
1
1
1
2
1
2
0000 None
xxxx None
0110 None
0101 None
nnnn None
1111 All
No Operation (Note 4)
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device RESET
Return from interrupt enable
s
000s GIE/GIEH,
PEIE/GIEL
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100 kkkk
0000 0000 0001
0000 0000 0000
kkkk None
001s None
0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an
external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
6: Microchip Assembler MASM automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’
according to address of register being used.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 99
PIC18F010/020
TABLE 13-2: PIC18F010/020 INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Load FSR(f) with a 12-bit
literal (k)
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
1
1
1
2
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
1
1
1
2
1
Exclusive OR literal with WREG 1
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2 (5)
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
6: Microchip Assembler MASM automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’
according to address of register being used.
DS41142A-page 100
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
13.1 Instruction Set
ADDLW
ADD literal to WREG
ADDWF
ADD WREG to f
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] ADDWF f [,d] [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(WREG) + k → WREG
N,OV, C, DC, Z
Operation:
(WREG) + (f) → dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
Description:
The contents of WREG are added
to the 8-bit literal ’k’ and the result is
placed in WREG.
0010
01da
ffff
ffff
Description:
Add WREG to register ’f’. If ’d’ is 0,
the result is stored in WREG. If ’d’
is 1, the result is stored back in reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected. If ’a’
is 1, the Bank will be selected as
per the BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write to
WREG
Words:
Cycles:
1
1
ADDLW
0x15
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
WREG
N
OV
C
DC
Z
=
=
=
=
=
=
0x10
Decode
Read
register ’f’
Process
Data
Write to
destination
?
?
?
?
?
ADDWF
REG, W
Example:
Before Instruction
After Instruction
WREG
REG
N
=
0x17
0xC2
WREG
=
=
=
=
=
=
0x25
=
=
=
=
=
=
N
0
0
0
0
0
?
?
?
?
?
OV
C
OV
C
DC
Z
DC
Z
After Instruction
WREG
REG
N
OV
C
=
=
=
=
=
=
=
0xD9
0xC2
1
0
0
0
0
DC
Z
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 101
PIC18F010/020
ANDLW
AND literal with WREG
ADDWFC
Syntax:
ADD WREG and Carry bit to f
[ label ] ADDWFC f [ ,d [,a] ]
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
(WREG) .AND. k → WREG
N,Z
Operation:
(WREG) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
Description:
The contents of WREG are AND’ed
with the 8-bit literal 'k'. The result is
placed in WREG.
0010
00da
ffff
ffff
Description:
Add WREG, the Carry Flag and data
memory location ’f’. If ’d’ is 0, the
result is placed in WREG. If ’d’ is 1,
the result is placed in data memory
location 'f'. If ’a’ is 0, the Access
Bank will be selected. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write to
WREG
’k’
Words:
Cycles:
1
1
ANDLW
0x5F
Example:
Before Instruction
Q Cycle Activity:
Q1
WREG
=
=
=
0xA3
?
?
Q2
Q3
Q4
N
Z
Decode
Read
register ’f’
Process
Data
Write to
destination
After Instruction
WREG
N
Z
=
=
=
0x03
0
0
ADDWFC
REG, W
Example:
Before Instruction
C
=
1
REG
WREG
N
OV
DC
Z
=
=
=
=
=
=
0x02
0x4D
?
?
?
?
After Instruction
C
=
=
=
=
=
=
=
0
0x02
0x50
0
0
0
0
REG
WREG
N
OV
DC
Z
DS41142A-page 102
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
ANDWF
Syntax:
AND WREG with f
BC
Branch if Carry
[ label ] ANDWF f [ ,d [,a] ]
Syntax:
Operands:
Operation:
[ label ] BC
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
-128 ≤ n ≤ 127
if carry bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(WREG) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N,Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ’1’, then the pro-
Description:
The contents of WREG are AND’ed
with register 'f'. If 'd' is 0, the result
is stored in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected. If ’a’ is 1, the
bank will be selected as per the
BSR value.
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
Decode
Read literal
Process
Data
Write to PC
’n’
No
No
No
No
operation
operation
operation
operation
ANDWF
REG, W
Example:
If No Jump:
Q1
Before Instruction
Q2
Q3
Q4
WREG
REG
N
=
0x17
0xC2
?
=
=
=
Decode
Read literal
Process
Data
No
’n’
operation
Z
?
After Instruction
HERE
BC
5
Example:
WREG
REG
N
=
=
=
=
0x02
0xC2
0
Before Instruction
PC
=
address (HERE)
Z
0
After Instruction
If Carry
=
=
=
=
1;
PC
If Carry
PC
address (HERE+12)
0;
address (HERE+2)
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 103
PIC18F010/020
BCF
Bit Clear f
BN
Branch if Negative
[ label ] BN
Syntax:
Operands:
[ label ] BCF f, b [,a]
Syntax:
Operands:
Operation:
n
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
-128 ≤ n ≤ 127
if negative bit is ’1’
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ’1’, then the
Description:
Bit 'b' in register 'f' is cleared. If ’a’
is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ = 1, the Bank will be selected
as per the BSR value.
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
Q Cycle Activity:
Q1
1(2)
Q2
Q3
Q4
Q Cycle Activity:
If Jump:
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Q1
Q2
Q3
Q4
BCF
FLAG_REG,
7
Decode
Read literal
Process
Data
Write to PC
Example:
’n’
Before Instruction
No
operation
No
operation
No
operation
No
operation
FLAG_REG = 0xC7
After Instruction
If No Jump:
Q1
FLAG_REG = 0x47
Q2
Q3
Q4
Decode
Read literal
Process
Data
No
operation
’n’
HERE
BN Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE+2)
If Negative
PC
DS41142A-page 104
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
-128 ≤ n ≤ 127
if carry bit is ’0’
n
Syntax:
[ label ] BNN
-128 ≤ n ≤ 127
n
Operands:
Operation:
Operands:
Operation:
if negative bit is ’0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ’0’, then the pro-
Description:
If the Negative bit is ’0’, then the
gram will branch.
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write to PC
Decode
Read literal
Process
Data
Write to PC
’n’
’n’
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
Process
Data
No
operation
Decode
Read literal
Process
Data
No
operation
’n’
’n’
HERE
BNC Jump
HERE
BNN Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Negative
PC
If Carry
=
=
=
=
0;
=
=
=
=
0;
PC
If Carry
PC
address (Jump)
1;
address (HERE+2)
address (Jump)
1;
address (HERE+2)
If Negative
PC
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 105
PIC18F010/020
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
-128 ≤ n ≤ 127
n
Syntax:
[ label ] BNZ
-128 ≤ n ≤ 127
if zero bit is ’0’
n
Operands:
Operation:
Operands:
Operation:
if overflow bit is ’0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ’0’, then the
Description:
If the Zero bit is ’0’, then the pro-
program will branch.
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write to PC
Decode
Read literal
Process
Data
Write to PC
’n’
’n’
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
Process
Data
No
operation
Decode
Read literal
Process
Data
No
operation
’n’
’n’
HERE
BNOV Jump
HERE
BNZ Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
If Overflow
PC
After Instruction
=
=
=
=
0;
If Zero
=
=
=
=
0;
address (Jump)
1;
address (HERE+2)
PC
If Zero
PC
address (Jump)
1;
address (HERE+2)
If Overflow
PC
DS41142A-page 106
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
BRA
Unconditional Branch
[ label ] BRA
BSF
Bit Set f
Syntax:
n
Syntax:
Operands:
[ label ] BSF f, b [,a]
Operands:
Operation:
Status Affected:
Encoding:
Description:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation:
1 → f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Add the 2’s complement number
’2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a two-
cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit 'b' in register 'f' is set. If ’a’ is 0
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write to PC
’n’
Decode
Read
register ’f’
Process
Data
Write
register ’f’
No
No
No
No
operation
operation
operation
operation
BSF
FLAG_REG, 7, 1
Example:
Before Instruction
HERE
BRA Jump
Example:
FLAG_REG
=
=
0x0A
Before Instruction
After Instruction
FLAG_REG
PC
=
=
address (HERE)
address (Jump)
0x8A
After Instruction
PC
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 107
PIC18F010/020
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f, b [,a]
Syntax:
[ label ] BTFSS f, b [,a]
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
None
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Status Affected:
Encoding:
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit 'b' in register ’f' is 0, then the
next instruction is skipped.
Description:
If bit 'b' in register 'f' is 1 then the next
instruction is skipped.
If bit 'b' is 0, then the next instruction
fetched during the current instruction
execution is discarded, and a NOPis
executed instead, making this a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the BSR
value.
If bit 'b' is 1, then the next instruction
fetched during the current instruc-
tion execution, is discarded and an
NOPis executed instead, making this
a two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the BSR
value.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
No
operation
Decode
Read
register ’f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, ACCESS
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, ACCESS
Example:
Example:
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
If FLAG<1>
PC
After Instruction
If FLAG<1>
PC
=
=
=
=
0;
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
address (FALSE)
1;
address (TRUE)
If FLAG<1>
PC
If FLAG<1>
PC
DS41142A-page 108
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
Operands:
[ label ] BTG f, b [,a]
Syntax:
[ label ] BOV
-128 ≤ n ≤ 127
n
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operands:
Operation:
if overflow bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ’1’, then the
Description:
Bit ’b’ in data memory location ’f’ is
inverted. If ’a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ’a’ is 1, the Bank will be
selected as per the BSR value.
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
Q Cycle Activity:
Q1
1(2)
Q2
Q3
Q4
Q Cycle Activity:
If Jump:
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Q1
Q2
Q3
Q4
BTG
PORTB,
4
Decode
Read literal
Process
Data
Write to PC
Example:
’n’
Before Instruction:
No
operation
No
operation
No
operation
No
operation
PORTB
=
0111 0101[0x35]
After Instruction:
If No Jump:
Q1
PORTB
=
0110 0101[0x25]
Q2
Q3
Q4
Decode
Read literal
Process
Data
No
operation
’n’
HERE
BOV Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Overflow
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE+2)
If Overflow
PC
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 109
PIC18F010/020
BZ
Branch if Zero
[ label ] BZ
CALL
Subroutine Call
Syntax:
Operands:
Operation:
n
Syntax:
Operands:
[ label ] CALL k [,s]
-128 ≤ n ≤ 127
0 ≤ k ≤ 1048575
s ∈ [0,1]
if Zero bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>,
if s = 1
(WREG) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
Description:
If the Zero bit is ’1’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2M byte
memory range. First, return
Words:
Cycles:
1
address (PC+ 4) is pushed onto the
return stack. If ’s’ = 1, the WREG,
STATUS and BSR registers are
also pushed into their respective
shadow registers, WS, STATUSS
and BSRS. If 's' = 0, no update
occurs (default). Then the 20-bit
value ’k’ is loaded into PC<20:1>.
CALLis a two-cycle instruction.
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write to PC
’n’
No
operation
No
No
No
operation
operation
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
Process
Data
No
operation
Q Cycle Activity:
Q1
’n’
Q2
Q3
Q4
Decode
Read literal Push PC to Read literal
HERE
BZ Jump
Example:
’k’<7:0>,
stack
’k’<19:8>,
Write to PC
Before Instruction
No
operation
No
operation
No
operation
No
operation
PC
=
address (HERE)
After Instruction
If Zero
=
=
=
=
1;
HERE
CALL THERE, FAST
Example:
PC
If Zero
PC
address (Jump)
0;
address (HERE+2)
Before Instruction
PC
=
Address(HERE)
After Instruction
PC
TOS
WS
=
=
=
=
Address(THERE)
Address (HERE + 4)
WREGREG
BSRS
BSR
STATUSS = STATUS
DS41142A-page 110
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
CLRF
Clear f
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
Syntax:
Operands:
[label] CLRF f [,a]
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register. If ’a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ’a’ is 1, the Bank will be
selected as per the BSR value.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Decode
No
operation
Process
Data
No
operation
CLRF
FLAG_REG
CLRWDT
Example:
Example:
Before Instruction
Before Instruction
FLAG_REG
Z
=
=
0x5A
?
WDT counter
WDT postscaler
TO
=
=
=
=
?
?
?
?
After Instruction
PD
FLAG_REG
Z
=
=
0x00
0
After Instruction
WDT counter
WDT postscaler
TO
=
=
=
=
0x00
0
1
1
PD
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 111
PIC18F010/020
Compare f with WREG,
skip if f = WREG
CPFSEQ
COMF
Complement f
Syntax:
[ label ] CPFSEQ f [,a]
Syntax:
Operands:
[ label ] COMF f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (WREG),
skip if (f) = (WREG)
(unsigned comparison)
Operation:
(f) → dest
Status Affected:
Encoding:
N,Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ’f’ are com-
plemented. If ’d’ is 0 the result is
stored in WREG. If ’d’ is 1 the result
is stored back in register ’f’
Description:
Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsigned
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
subtraction.
If 'f' = WREG, then the fetched
instruction is discarded and an NOP
is executed instead making this a
two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register ’f’
Process
Data
Write to
destination
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
COMF
REG
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ’f’
Process
Data
No
operation
REG
N
Z
=
=
=
0x13
?
?
If skip:
Q1
Q2
Q3
Q4
After Instruction
No
operation
No
operation
No
operation
No
operation
REG
WREG
N
=
=
=
=
0x13
0xEC
1
If skip and followed by 2-word instruction:
Z
0
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
CPFSEQ REG
Example:
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
WREG
=
=
=
HERE
?
?
REG
After Instruction
If REG
PC
If REG
PC
=
WREG;
Address (EQUAL)
WREG;
=
≠
=
Address (NEQUAL)
DS41142A-page 112
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
Compare f with WREG,
skip if f > WREG
Compare f with WREG,
skip if f < WREG
CPFSGT
CPFSLT
Syntax:
[ label ] CPFSGT f [,a]
Syntax:
[ label ] CPFSLT f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) − (WREG),
Operation:
(f) – (WREG),
skip if (f) > (WREG)
(unsigned comparison)
skip if (f) < (WREG)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data
memory location ’f’ to the contents
of the WREG by performing an
unsigned subtraction.
Description:
Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsigned subtraction.
If the contents of ’f’ are greater than
the contents of , then the fetched
instruction is discarded and a NOP
is executed instead making this a
two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
If the contents of 'f' are less than
the contents of WREG, then the
fetched instruction is discarded and
a NOPis executed instead making
this a two-cycle instruction. If ’a’ is
0, the Access Bank will be
selected. If ’a’ is 1, the Bank will be
selected as per the BSR value.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note:3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
No
operation
Decode
Read
register ’f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NLESS
LESS
CPFSLT REG
:
:
Example:
HERE
NGREATER
GREATER
CPFSGT REG
:
:
Example:
Before Instruction
PC
WREG
=
=
Address (HERE)
?
Before Instruction
PC
WREG
=
=
Address (HERE)
?
After Instruction
After Instruction
If REG
PC
If REG
PC
If REG
PC
If REG
PC
<
=
≥
=
WREG;
Address (LESS)
WREG;
>
=
≤
=
WREG;
Address (GREATER)
WREG;
Address (NLESS)
Address (NGREATER)
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 113
PIC18F010/020
DAW
Decimal Adjust WREG Register
DECF
Decrement f
Syntax:
[label] DAW
Syntax:
Operands:
[ label ] DECF f [ ,d [,a] ]
Operands:
Operation:
None
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
If [WREG<3:0> >9] or [DC = 1]
then
(WREG<3:0>) + 6 → W<3:0>;
Operation:
(f) – 1 → dest
else
Status Affected:
Encoding:
C,DC,N,OV,Z
(WREG<3:0>) → W<3:0>;
0000
01da
ffff
ffff
Description:
Decrement register 'f'. If 'd' is 0, the
result is stored in WREG. If 'd' is 1,
the result is stored back in register
'f' (default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
If [WREG<7:4> >9] or [C = 1] then
(WREG<7:4>) + 6 → WREG<7:4>;
else
(WREG<7:4>) → WREG<7:4>;
Status Affected:
Encoding:
C
0000
0000
0000
0111
Description:
DAW adjusts the eight bit value in
WREG resulting from the earlier
addition of two variables (each in
packed BCD format) and produces
a correct packed BCD result.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
1
Decode
Read
register ’f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
DECF
CNT
Example:
Q2
Q3
Q4
Decode
Read
register WREG
Process
Data
Write
WREG
Before Instruction
CNT
=
0x01
0
Z
=
DAW
Example1:
After Instruction
Before Instruction
CNT
=
0x00
1
WREG
=
=
=
0xA5
0
0
Z
=
C
DC
After Instruction
WREG
C
DC
=
=
=
0x05
1
0
Example 2:
Before Instruction
WREG
C
DC
=
=
=
0xCE
0
0
After Instruction
WREG
C
DC
=
=
=
0x34
1
0
DS41142A-page 114
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
DECFSZ
Syntax:
Decrement f, skip if 0
DCFSNZ
Syntax:
Decrement f, skip if not 0
[ label ] DECFSZ f [ ,d [,a] ]
[label] DCFSNZ f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result = 0
Operation:
(f) – 1 → dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register 'f' are dec-
remented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
Description:
The contents of register 'f' are dec-
remented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOPis executed
instead making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
If the result is not 0, the next
instruction, which is already
fetched, is discarded, and a NOPis
executed instead making it a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ’a’ is
1, the Bank will be selected as per
the BSR value.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
Decode
Read
register ’f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
DECFSZ
GOTO
CNT
LOOP
HERE
ZERO
NZERO
DCFSNZ TEMP
:
:
Example:
Example:
CONTINUE
Before Instruction
Before Instruction
TEMP
PC
=
Address (HERE)
=
?
After Instruction
After Instruction
TEMP
CNT
=
=
=
≠
=
CNT - 1
0;
Address (CONTINUE)
0;
=
=
=
≠
=
TEMP - 1,
0;
Address (ZERO)
0;
If CNT
If TEMP
PC
If TEMP
PC
PC
If CNT
PC
Address (HERE+2)
Address (NZERO)
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 115
PIC18F010/020
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 1048575
k → PC<20:1>
None
INCF
Increment f
Syntax:
Syntax:
Operands:
[ label ] INCF f [ ,d [,a] ]
Operands:
Operation:
Status Affected:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C,DC,N,OV,Z
1110
1111
1111
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional
Description:
The contents of register ’f’ are
incremented. If ’d’ is 0, the result is
placed in WREG. If ’d’ is 1, the
result is placed back in register ’f’
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
branch anywhere within entire 2M
byte memory range. The 20-bit
value ’k’ is loaded into PC<20:1>.
GOTOis always a two-cycle
instruction.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read literal
’k’<7:0>,
No
operation
Read literal
’k’<19:8>,
Write to PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
Read
register ’f’
Process
Data
Write to
destination
GOTO THERE
Example:
INCF
CNT
Example:
After Instruction
Before Instruction
PC
=
Address (THERE)
CNT
=
0xFF
Z
C
DC
=
=
=
0
?
?
After Instruction
CNT
Z
C
DC
=
=
=
=
0x00
1
1
1
DS41142A-page 116
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
INCFSZ
Syntax:
Increment f, skip if 0
INFSNZ
Syntax:
Increment f, skip if not 0
[ label ] INCFSZ f [ ,d [,a] ]
[label] INFSNZ f [, d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result = 0
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0011
11da
ffff
ffff
0100
10da
ffff
ffff
Description:
The contents of register ’f’ are
incremented. If ’d’ is 0, the result is
placed in WREG. If ’d’ is 1, the
result is placed back in register ’f’
(default).
Description:
The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOPis executed
instead making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
If the result is not 0, the next
instruction, which is already
fetched, is discarded, and a NOPis
executed instead making it a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
Decode
Read
register ’f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
NZERO
ZERO
INCFSZ
:
:
CNT
HERE
ZERO
NZERO
INFSNZ REG
Example:
Example:
Before Instruction
Before Instruction
PC
=
Address (HERE)
PC
=
Address (HERE)
After Instruction
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
≠
=
CNT + 1
0;
Address(ZERO)
0;
Address(NZERO)
REG
If REG
PC
If REG
PC
=
≠
=
=
=
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 117
PIC18F010/020
IORLW
Inclusive OR literal with WREG
IORWF
Inclusive OR WREG with f
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
[ label ] IORWF f [ ,d [,a] ]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(WREG) .OR. k → WREG
N,Z
Operation:
(WREG) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N,Z
The contents of WREG are OR’ed
with the eight bit literal 'k'. The
result is placed in WREG.
0001
00da
ffff
ffff
Description:
Inclusive OR WREG with register
'f'. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is
placed back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write to
WREG
Words:
Cycles:
1
1
IORLW
0x35
Example:
Before Instruction
Q Cycle Activity:
Q1
WREG
=
=
=
0x9A
?
?
Q2
Q3
Q4
N
Z
Decode
Read
register ’f’
Process
Data
Write to
destination
After Instruction
WREG
N
Z
=
=
=
0xBF
1
0
IORWF RESULT, W
Example:
Before Instruction
RESULT =
0x13
0x91
?
WREG
=
=
=
N
Z
?
After Instruction
RESULT =
0x13
0x93
1
WREG
=
=
=
N
Z
0
DS41142A-page 118
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
LFSR
Load FSR
MOVF
Move f
Syntax:
Operands:
[ label ] LFSR f,k
Syntax:
Operands:
[ label ] MOVF f [ ,d [,a] ]
0 ≤ f ≤ 2
0 ≤ k ≤ 4095
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
k → FSRf
Operation:
f → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N,Z
1110
1111
1110
0000
00ff
k kkk
11
kkkk
k kkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ’k’ is loaded into
the file select register pointed to
by ’f’
Description:
The contents of register ’f’ is moved
to a destination dependent upon
the status of ’d’. If 'd' is 0, the result
is placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default). Location 'f' can be any-
where in the 256 byte Bank. If ’a’ is
0, the Access Bank will be
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
Decode
Read literal
’k’ MSB
Process
Data
Write
literal ’k’
MSB to
FSRfH
Words:
Cycles:
1
1
Decode
Read literal
’k’ LSB
Process
Data
Write literal
’k’ to FSRfL
Q Cycle Activity:
Q1
LFSR FSR2, 0x3AB
Example:
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write
WREG
After Instruction
FSR2H
=
=
0x03
0xAB
FSR2L
MOVF
REG, W
Example:
Before Instruction
REG
WREG
N
=
=
=
=
0x22
0xFF
?
Z
?
After Instruction
REG
WREG
N
=
=
=
=
0x22
0x22
0
Z
0
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 119
PIC18F010/020
MOVFF
Move f to f
MOVLB
Move literal to low nibble in BSR
Syntax:
[label] MOVFF fs,fd
Syntax:
[ label ] MOVLB k
0 ≤ k ≤ 255
k → BSR
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ fs ≤ 4095
0 ≤ fd ≤ 4095
None
Operation:
(fs) → fd
0000
0001
kkkk
kkkk
Status Affected:
None
The 8-bit literal ’k’ is loaded into
the Bank Select Register (BSR).
Encoding:
1st word (source)
2nd word (destin.)
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Words:
Cycles:
1
1
Description:
The contents of source register ’fs’
are moved to destination register
’fd’. Location of source ’fs’ can be
anywhere in the 4096 byte data
space (000h to FFFh), and location
of destination ’fd’ can also be any-
where from 000h to FFFh.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write
literal ’k’ to
BSR
’k’
Either source or destination can be
WREG (a useful special situation).
MOVLB
0x01
Example:
Before Instruction
MOVFFis particularly useful for
transferring a data memory location
to a peripheral register (such as the
transmit buffer or an I/O port).
BSR register
=
=
0x0F
After Instruction
BSR register
0x01
The MOVFFinstruction cannot use
the PCL, TOSU, TOSH or TOSL as
the destination register.
Words:
Cycles:
2
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ’f’
(dest)
No dummy
read
MOVFF
REG1, REG2
Example:
Before Instruction
REG1
=
=
0x33
0x11
REG2
After Instruction
REG1
=
=
0x33,
0x33
REG2
DS41142A-page 120
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
MOVLW
Move literal to WREG
[ label ] MOVLW k
0 ≤ k ≤ 255
MOVWF
Syntax:
Move WREG to f
Syntax:
[ label ] MOVWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
k → WREG
Operation:
(WREG) → f
None
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
The eight bit literal ’k’ is loaded into
WREG.
Description:
Move data from WREG to register
’f’. Location ’f’ can be anywhere in
the 256 byte Bank. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write to
WREG
Words:
Cycles:
1
1
MOVLW
0x5A
Example:
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
WREG
=
0x5A
Decode
Read
register ’f’
Process
Data
Write
register ’f’
MOVWF
REG
Example:
Before Instruction
WREG
REG
=
=
0x4F
0xFF
After Instruction
WREG
REG
=
=
0x4F
0x4F
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 121
PIC18F010/020
MULLW
Multiply Literal with WREG
MULWF
Syntax:
Multiply WREG with f
Syntax:
[ label ] MULLW
0 ≤ k ≤ 255
k
[ label ] MULWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(WREG) x k → PRODH:PRODL
Operation:
(WREG) x (f) → PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
An unsigned multiplication is car-
ried out between the contents of
WREG and the 8-bit literal ’k’.
The 16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
Description:
An unsigned multiplication is car-
ried out between the contents of
WREG and the register file loca-
tion ’f’. The 16-bit result is stored
in the PRODH:PRODL register
pair. PRODH contains the high
byte.
WREG is unchanged.
None of the status flags are
affected.
Both WREG and ’f’ are
unchanged.
Note that neither overflow nor
carry is possible in this opera-
tion. A zero result is possible but
not detected.
None of the status flags are
affected.
Note that neither overflow nor
carry is possible in this opera-
tion. A zero result is possible but
not detected. If ’a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ’a’ is
1, the Bank will be selected as
per the BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write
registers
PRODH:
PRODL
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
MULLW
0xC4
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ’f’
Process
Data
Write
WREG
PRODH
PRODL
=
=
=
0xE2
registers
PRODH:
PRODL
?
?
After Instruction
WREG
=
=
=
0xE2
0xAD
0x08
MULWF
REG
Example:
PRODH
PRODL
Before Instruction
WREG
REG
PRODH
PRODL
=
=
=
=
0xC4
0xB5
?
?
After Instruction
WREG
=
=
=
=
0xC4
0xB5
0x8A
0x94
REG
PRODH
PRODL
DS41142A-page 122
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
NEGF
Negate f
NOP
No Operation
[ label ] NOP
None
Syntax:
Operands:
[label] NEGF f [,a]
Syntax:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
No operation
None
Operation:
( f ) + 1 → f
Status Affected:
Encoding:
N,OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Words:
No operation.
Description:
Location ’f’ is negated using two’s
complement. The result is placed in
the data memory location 'f'. If ’a’ is
0, the Access Bank will be
1
1
Cycles:
Q Cycle Activity:
Q1
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
Words:
Cycles:
1
1
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write
register ’f’
NEGF
REG
Example:
Before Instruction
REG
N
OV
C
DC
Z
=
=
=
=
=
=
0011 1010[0x3A]
?
?
?
?
?
After Instruction
REG
N
OV
C
DC
Z
=
=
=
=
=
=
1100 0110[0xC6]
1
0
0
0
0
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 123
PIC18F010/020
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
[ label ] PUSH
None
Syntax:
[ label ] POP
None
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
(TOS) → bit bucket
None
(PC+2) → TOS
None
0000
0000
0000
0110
0000
0000
0000
0101
The TOS value is pulled off the
return stack and is discarded. The
TOS value then becomes the previ-
ous value that was pushed onto the
return stack.
The PC+2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implement-
ing a software stack by modifying
TOS, and then push it onto the
return stack.
This instruction is provided to
enable the user to properly manage
the return stack to incorporate a
software stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Push PC+2
onto return
stack
No
operation
No
operation
Q2
Q3
Q4
Decode
No
operation
Pop TOS
value
No
operation
PUSH
Example:
POP
GOTO
Example:
Before Instruction
NEW
TOS
=
=
00345Ah
000124h
PC
Before Instruction
TOS
=
=
0031A2h
014332h
Stack (1 level down)
After Instruction
PC
TOS
=
=
=
000126h
000126h
00345Ah
After Instruction
Stack (1 level down)
TOS
PC
=
=
014332h
NEW
DS41142A-page 124
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
RCALL
Relative Call
RESET
Reset
Syntax:
[ label ] RCALL
-1024 ≤ n ≤ 1023
(PC) + 2 → TOS,
n
Syntax:
[ label ] RESET
None
Operands:
Operation:
Operands:
Operation:
Reset all registers and flags that
are affected by a MCLR Reset.
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to
1K from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ’2n’ to the PC.
Since the PC will have incremented
to fetch the next instruction, the
new address will be PC+2+2n.
This instruction is a two-cycle
instruction.
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
reset
No
operation
No
operation
Words:
Cycles:
1
2
RESET
Example:
After Instruction
Registers =
Reset Value
Reset Value
Q Cycle Activity:
Q1
Flags*
=
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write to PC
’n’
Push PC to
stack
No
No
No
No
operation
operation
operation
operation
HERE
RCALL
Jump
Example:
Before Instruction
PC
=
Address(HERE)
After Instruction
PC
=
Address(Jump)
TOS =
Address (HERE+2)
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 125
PIC18F010/020
RETFIE
Return from Interrupt
[ label ] RETFIE [s]
s ∈ [0,1]
RETLW
Return Literal to WREG
[ label ] RETLW k
0 ≤ k ≤ 255
Syntax:
Syntax:
Operands:
Operation:
Operands:
Operation:
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → WREG,
(STATUSS) → STATUS,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged.
Description:
W is loaded with the eight bit literal
'k'. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
Status Affected:
Encoding:
None
0000
0000
0001
000s
Description:
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS)
is loaded into the PC. Interrupts
are enabled by setting the either
the high or low priority global
interrupt enable bit. If ’s’ = 1, the
contents of the shadow registers
WS, STATUSS and BSRS are
loaded into their corresponding
registers, WREG, STATUS and
BSR. If ’s’ = 0, no update of
these registers occurs (default).
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Pop PC from
stack, write
to WREG
No
No
No
No
operation
operation
operation
operation
Words:
Cycles:
1
2
Example:
CALL TABLE ; WREG contains table
Q Cycle Activity:
Q1
;
;
;
offset value
WREG now has
table value
Q2
Q3
Q4
Decode
No
operation
No
operation
Pop PC from
stack
:
TABLE
Set GIEH or
GIEL
ADDWF PCL
; WREG = offset
; Begin table
;
RETLW k0
RETLW k1
:
No
operation
No
operation
No
operation
No
operation
:
RETFIE
1
Example:
RETLW kn
; End of table
After Interrupt
PC
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
Before Instruction
WREG
BSR
STATUS
GIE/GIEH, PEIE/GIEL
WREG
=
0x07
After Instruction
WREG
=
value of kn
DS41142A-page 126
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
RETURN
Syntax:
Return from Subroutine
[ label ] RETURN [s]
s ∈ [0,1]
RLCF
Rotate Left f through Carry
Syntax:
Operands:
[ label ] RLCF f [ ,d [,a] ]
Operands:
Operation:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(TOS) → PC,
if s = 1
(WS) → W,
Operation:
(f<n>) → dest<n+1>,
(f<7>) → C,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
(C) → dest<0>
Status Affected:
Encoding:
C,N,Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the
result is stored back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
Description:
Return from subroutine. The
stack is popped and the top of the
stack (TOS) is loaded into the
program counter. If ’s’ = 1, the
contents of the shadow registers
WS, STATUSS and BSRS are
loaded into their corresponding
registers, WREG, STATUS and
BSR. If ’s’ = 0, no update of
these registers occurs (default).
register f
C
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
No
Process
Data
Pop PC from
stack
operation
Decode
Read
Process
Data
Write to
destination
No
No
No
No
register ’f’
operation
operation
operation
operation
RLCF
REG, W
Example:
Before Instruction
RETURN
Example:
REG
=
1110 0110
C
N
Z
=
=
=
0
?
?
After Call
PC
=
TOS
RETURN FAST
After Instruction
Before Instruction
REG
WREG
C
N
Z
=
=
=
=
=
1110 0110
1100 1100
1
1
0
WRG
STATUS =
BSR
=
0x04
0x00
0x00
=
After Instruction
WREG
STATUS =
BSR
PC
=
0x04
0x00
0x00
TOS
=
=
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 127
PIC18F010/020
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ] RLNCF f [ ,d [,a] ]
Syntax:
Operands:
[ label ] RRCF f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n+1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n-1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N,Z
Status Affected:
Encoding:
C,N,Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ’f’ are
rotated one bit to the left. If ’d’ is 0
the result is placed in WREG. If ’d’
is 1, the result is stored back in reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Description:
The contents of register 'f' are
rotated one bit to the right through
the Carry Flag. If 'd' is 0, the result
is placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
register f
Words:
Cycles:
1
1
register f
C
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ’f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
RLNCF
REG
Example:
Before Instruction
RRCF
REG, W
Example:
REG
=
1010 1011
N
Z
=
=
?
?
Before Instruction
REG
=
1110 0110
C
N
Z
=
=
=
0
?
?
After Instruction
REG
N
Z
=
=
=
0101 0111
0
0
After Instruction
REG
WREG
C
N
Z
=
=
=
=
=
1110 0110
0111 0011
0
0
0
DS41142A-page 128
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
RRNCF
Syntax:
Rotate Right f (no carry)
SETF
Set f
[ label ] RRNCF f [ ,d [,a] ]
Syntax:
Operands:
[label] SETF f [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
Operation:
(f<n>) → dest<n-1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N,Z
Description:
The contents of the specified regis-
ter are set to FFh. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
0100
00da
ffff
ffff
Description:
The contents of register ’f’ are
rotated one bit to the right. If ’d’ is 0,
the result is placed in WREG. If ’d’
is 1, the result is placed back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Words:
Cycles:
1
1
SETF
REG
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
=
0x5A
0xFF
Q2
Q3
Q4
After Instruction
REG
Decode
Read
register ’f’
Process
Data
Write to
destination
=
RRNCF
REG
Example 1:
Before Instruction
REG
N
Z
=
=
=
1101 0111
?
?
After Instruction
REG
N
Z
=
=
=
1110 1011
1
0
RRNCF
REG, 0, 0
Example 2:
Before Instruction
WREG
REG
N
=
=
=
=
?
1101 0111
?
?
Z
After Instruction
WREG
REG
N
=
=
=
=
1110 1011
1101 0111
1
0
Z
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 129
PIC18F010/020
SLEEP
SUBFWB
Syntax:
Enter SLEEP mode
[ label ] SLEEP
None
Subtract f from WREG with borrow
Syntax:
[ label ] SUBFWB f [ ,d [,a] ]
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
00h → WDT,
0 → WDT postscaler,
1 → TO,
Operation:
(WREG) – (f) – (C) → dest
0 → PD
Status Affected:
Encoding:
N,OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register 'f' and carry flag
(borrow) from WREG (2’s comple-
ment method). If 'd' is 0, the result
is stored in WREG. If 'd' is 1, the
result is stored in register 'f'
(default) . If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
Description:
The power-down status bit (PD) is
cleared. The time-out status bit
(TO) is set. Watchdog Timer and
its postscaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
No
operation
Process
Data
Go to
sleep
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
SLEEP
Example:
Before Instruction
TO
=
?
PD
=
?
After Instruction
TO
=
1 †
PD
=
0
† If WDT causes wake-up, this bit is cleared.
DS41142A-page 130
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
SUBFWB (Cont.)
SUBLW
Subtract WREG from literal
[ label ] SUBLW k
0 ≤ k ≤ 255
SUBFWB
REG
Example 1:
Syntax:
Before Instruction
Operands:
Operation:
Status Affected:
Encoding:
Description:
REG
WREG
C
=
=
=
3
2
1
k – (WREG) → WREG
N,OV, C, DC, Z
After Instruction
0000
1000
kkkk
kkkk
REG
WREG
C
Z
N
=
=
=
=
=
0xFF
WREG is subtracted from the
eight bit literal 'k'. The result is
placed in WREG.
2
0
0
1
; result is negative
Words:
Cycles:
1
1
SUBFWB
REG
Example 2:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
REG
WREG
C
=
=
=
2
5
1
Decode
Read
literal ’k’
Process
Data
Write to
WREG
After Instruction
SUBLW 0x02
Example 1:
REG
=
=
=
=
=
2
3
1
0
0
Before Instruction
WREG
WREG
C
=
=
1
?
C
Z
N
; result is positive
After Instruction
WREG
C
Z
=
=
=
=
1
SUBFWB
REG
Example 3:
1
0
0
; result is positive
Before Instruction
REG
WREG
C
=
=
=
1
2
0
N
SUBLW 0x02
Example 2:
After Instruction
Before Instruction
REG
WREG
C
Z
N
=
=
=
=
=
0
2
1
1
0
WREG
C
=
=
2
?
; result is zero
After Instruction
WREG
C
Z
=
=
=
=
0
1
1
0
; result is zero
N
SUBLW 0x02
Example 3:
Before Instruction
WREG
C
=
=
3
?
After Instruction
WREG
C
Z
=
=
=
=
0xFF ; (2’s complement)
0
0
1
; result is negative
N
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 131
PIC18F010/020
SUBWF
Subtract WREG from f
SUBWF
Subtract WREG from f (cont’d)
SUBWF
REG
Syntax:
[ label ] SUBWF f [ ,d [,a] ]
Example 1:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Before Instruction
REG
WREG
C
=
=
=
3
2
?
Operation:
(f) – (WREG) → dest
After Instruction
Status Affected:
Encoding:
N,OV, C, DC, Z
REG
WREG
C
Z
N
=
=
=
=
=
1
2
1
0
0
0101
11da
ffff
ffff
; result is positive
Description:
Subtract WREG from register 'f'
(2’s complement method). If 'd' is
0, the result is stored in WREG. If
'd' is 1, the result is stored back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ’a’ is
1, the Bank will be selected as per
the BSR value.
SUBWF
REG, W
Example 2:
Before Instruction
REG
WREG
C
=
=
=
2
2
?
After Instruction
REG
WREG
C
Z
N
=
=
=
=
=
2
0
1
1
0
Words:
Cycles:
1
1
; result is zero
Q Cycle Activity:
Q1
Q2
Q3
Q4
SUBWF
REG
Example 3:
Decode
Read
register ’f’
Process
Data
Write to
destination
Before Instruction
REG
WREG
C
=
=
=
1
2
?
After Instruction
REG
WREG
C
Z
N
=
=
=
=
=
0xFF ;(2’s complement)
2
0
0
1
; result is negative
DS41142A-page 132
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
Subtract WREG from f with
Borrow
Subtract WREG from f with
Borrow (cont’d)
SUBWFB
Syntax:
SUBWFB
SUBWFB REG
[ label ]
Example 1:
SUBWFB f [ ,d [,a] ]
Before Instruction
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
REG
WREG
C
=
=
=
0x19
0x0D
1
(0001 1001)
(0000 1101)
Operation:
(f) – (WREG) – (C) → dest
After Instruction
Status Affected:
Encoding:
N,OV, C, DC, Z
REG
WREG
C
Z
N
=
=
=
=
=
0x0C
0x0D
1
0
0
(0000 1011)
(0000 1101)
0101
10da
ffff
ffff
Description:
Subtract WREG and the carry flag
(borrow) from register 'f' (2’s com-
plement method). If 'd' is 0, the
result is stored in WREG. If 'd' is
1, the result is stored back in reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ’a’ is
1, the Bank will be selected as per
the BSR value.
; result is positive
Example 2:
Before Instruction
SUBWFB REG, W
REG
WREG
C
=
=
=
0x1B
0x1A
0
(0001 1011)
(0001 1010)
After Instruction
REG
WREG
C
Z
N
=
=
=
=
=
0x1B
0x00
1
1
0
(0001 1011)
Words:
Cycles:
1
1
; result is zero
Q Cycle Activity:
Q1
Q2
Q3
Q4
Example 3:
Before Instruction
SUBWFB REG
Decode
Read
register ’f’
Process
Data
Write to
destination
REG
WREG
C
=
=
=
0x03
0x0E
1
(0000 0011)
(0000 1101)
After Instruction
REG
WREG
C
Z
N
=
=
=
=
=
0xF5
0x0E
0
0
1
(1111 0100) [2’s comp]
(0000 1101)
; result is negative
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 133
PIC18F010/020
SWAPF
Syntax:
Swap nibbles in f
[ label ] SWAPF f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected:
Encoding:
None
0011
10da
ffff
ffff
Description:
The upper and lower nibbles of reg-
ister ’f’ are exchanged. If ’d’ is 0, the
result is placed in WREG. If ’d’ is 1,
the result is placed in register ’f’
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
SWAPF
REG
Example:
Before Instruction
REG
=
0x53
0x35
After Instruction
REG
=
DS41142A-page 134
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
TBLRD
Table Read
TBLRD
Table Read (cont’d)
TBLRD *+ ;
Syntax:
[ label ] TBLRD ( *; *+; *-; +*)
Example 1:
Operands:
Operation:
None
Before Instruction
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A356
0x34
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT;
TBLPTR - No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) +1 → TBLPTR;
if TBLRD *-,
After Instruction
TABLAT
TBLPTR
=
=
0x34
0x00A357
TBLRD +* ;
Example 2:
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) -1 → TBLPTR;
if TBLRD +*,
(TBLPTR) +1 → TBLPTR;
(Prog Mem (TBLPTR)) → TABLAT;
Before Instruction
TABLAT
=
=
=
=
0xAA
0x01A357
0x12
TBLPTR
MEMORY(0x01A357)
MEMORY(0x01A358)
0x34
After Instruction
Status Affected: None
TABLAT
TBLPTR
=
=
0x34
0x01A358
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Encoding:
Description:
This instruction is used to read the
contents of Program Memory (P.M.).
To address the program memory, a
pointer called Table Pointer (TBLPTR)
is used.
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2 Mbyte address range.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLRDinstruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
No
No
No
No
operation
operation
(Read
operation
operation
(Write
Program
Memory)
TABLAT)
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 135
PIC18F010/020
TBLWT
Table Write
TBLWT
Table Write (Continued)
TBLWT *+;
Syntax:
[ label ]
TBLWT ( *; *+; *-; +*)
Example 1:
Operands:
Operation:
None
Before Instruction
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A356
0xFF
if TBLWT*,
(TABLAT) → Prog Mem (TBLPTR) or
Holding Register;
TBLPTR - No Change;
if TBLWT*+,
(TABLAT) → Prog Mem (TBLPTR) or
Holding Register;
After Instructions (table write completion)
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A357
0x55
TBLWT +*;
Example 2:
(TBLPTR) +1 → TBLPTR;
if TBLWT*-,
Before Instruction
(TABLAT) → Prog Mem (TBLPTR) or
Holding Register;
(TBLPTR) -1 → TBLPTR;
if TBLWT+*,
TABLAT
TBLPTR
MEMORY(0x01389A)
MEMORY(0x01389B)
=
=
=
=
0x34
0x01389A
0xFF
0xFF
(TBLPTR) +1 → TBLPTR;
(TABLAT) → Prog Mem (TBLPTR) or
Holding Register;
After Instruction (table write completion)
TABLAT
=
=
=
=
0x34
TBLPTR
MEMORY(0x01389A)
MEMORY(0x01389B)
0x01389B
0xFF
0x34
Status Affected:
Encoding:
None
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description:
This instruction is used to program the
contents of Program Memory (P.M.).
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2 MBtye address
range. The LSb of the TBLPTR
selects which byte of the program
memory location to access.
TBLPTR[0] = 0:Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1:Most Significant
Byte of Program
Memory Word
The TBLWTinstruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
Cycles:
1
2 (many if long write is to on-chip
EPROM program memory)
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
Decode
No
operation operation
operation
No
No No
No
operation
operation operation
(Read
TABLAT)
operation
(Write to Holding
Register or Memory)
DS41142A-page 136
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
TSTFSZ
Syntax:
Test f, skip if 0
XORLW
Exclusive OR literal with WREG
[ label ] TSTFSZ f [,a]
Syntax:
[ label ]
XORLW k
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(WREG) .XOR. k → WREG
Operation:
skip if f = 0
None
Status Affected:
Encoding:
N,Z
Status Affected:
Encoding:
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
Description:
The contents of WREG are
XOR’ed with the 8-bit literal 'k'.
Description:
If ’f’ = 0, the next instruction,
fetched during the current instruc-
tion execution, is discarded and a
NOPis executed making this a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
The result is placed in WREG.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write to
WREG
Words:
Cycles:
1
1(2)
Example:
XORLW 0xAF
Note: 3 cycles if skip and followed
by a 2-word instruction
Before Instruction
WREG
=
=
=
0xB5
?
?
Q Cycle Activity:
Q1
N
Z
Q2
Q3
Q4
After Instruction
Decode
Read
register ’f’
Process
Data
No
operation
WREG
=
=
=
0x1A
0
0
N
Z
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NZERO
ZERO
TSTFSZ CNT
:
:
Example:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
=
=
≠
=
0x00,
Address (ZERO)
0x00,
PC
If CNT
PC
Address (NZERO)
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 137
PIC18F010/020
XORWF
Syntax:
Exclusive OR WREG with f
[ label ] XORWF f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(WREG) .XOR. (f) → dest
Status Affected:
Encoding:
N,Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of
WREG with register ’f’. If ’d’ is 0, the
result is stored in WREG. If ’d’ is 1,
the result is stored back in the reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
Example:
XORWF
REG
Before Instruction
REG
WREG
N
=
0xAF
0xB5
?
=
=
=
Z
?
After Instruction
REG
WREG
N
=
=
=
=
0x1A
0xB5
0
Z
0
DS41142A-page 138
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
The MPLAB IDE allows you to:
14.0 DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
• Simulators
- MPLAB SIM Software Simulator
• Emulators
14.2 MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PICmicro MCU’s.
- MPLAB ICD
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
14.1 MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
14.3 MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 139
PIC18F010/020
14.4 MPLINK Object Linker/
MPLIB Object Librarian
14.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editing, building, downloading and source
debugging from a single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
14.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
14.5 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS41142A-page 140
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
14.8 MPLAB ICD In-Circuit Debugger
14.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PICmicro MCUs and can be used
to develop for this and other PICmicro microcontrollers.
The MPLAB ICD utilizes the in-circuit debugging capa-
bility built into the FLASH devices. This feature, along
with Microchip’s In-Circuit Serial ProgrammingTM proto-
col, offers cost-effective in-circuit FLASH debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by watch-
ing variables, single-stepping and setting break points.
Running at full speed enables testing hardware in real-
time.
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
14.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program
PICmicro devices. It can also set code protection in this
mode.
14.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
14.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 141
PIC18F010/020
14.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
14.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
14.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS41142A-page 142
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
TABLE 14-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X X F 8 C 1 P I
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X
X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X
X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m e r u b g e g D s m e a r m o g P r r
s t K l a i E d v n a s d r a B o o m D e
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 143
PIC18F010/020
NOTES:
DS41142A-page 144
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
15.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTB........................................................................................................................150 mA
Maximum current sourced by PORTB ..................................................................................................................150 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 145
PIC18F010/020
FIGURE 15-1:
PIC18F010/020 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
PIC18F010/020
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
40 MHz
Frequency
FIGURE 15-2:
PIC18LF010/020 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
PIC18LF010/020
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
40 MHz
Frequency
DS41142A-page 146
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
15.1 DC Characteristics
PIC18F010/020
(Industrial unless otherwise stated)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No.
Symbol
Characteristic
Supply Voltage
Min Typ† Max Units
Conditions
D001
D001A
D002*
VDD
2.0
4.5
—
—
5.5
5.5
V
V
XT, LP, RC, EC and Internal osc mode
HS osc mode
VDR
RAM Data Retention
Voltage(1)
1.5
—
—
V
D003
D004*
D010
VPOR
VDD Start Voltage to
ensure internal
Power-on Reset signal
—
VSS
—
V
SVDD
IDD
VDD Rise Rate to
ensure internal
Power-on Reset signal
Supply Current(2)
0.05
—
—
V/ms
XT, RC, Internal osc modes
—
—
—
TBD
4
mA FOSC = 4 MHz, VDD = 3.0V
HS osc mode
mA FOSC = 25 MHz, VDD = 5.5V
EC osc mode
mA FOSC = 40 MHz, VDD = 5.5V
LP osc mode
µA FOSC = 32 kHz, VDD = 3.0V
TBD 50
TBD 45
TBD 48
—
—
D020
IPD
Power-down
Current(3)
<1
—
µA VDD = 3.0V, -40°C to +85°C
Module Differential
Current(5)
D021
D423.
D022A
∆IWDT
∆ILVD
∆IBOR
Watchdog Timer
Low Voltage Detect
Brown-out Reset
—
—
—
6.5
30
30
12
50
50
µA VDD = 3.0V
µA Brown-out disabled
µA Low Voltage Detect disabled
*
These parameters are characterized, but not tested.
†
Data in “Typ” column is as 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc mode, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: The ∆ current is the additional current consumed when the peripheral is enabled. This current should be
added to the base current.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 147
PIC18F010/020
15.2 DC Characteristics: PIC18F010/020 (Industrial unless otherwise stated)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports:
D030
with TTL buffer
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.15VDD
0.8V
V
V
V
V
V
V
4.5V ≤ VDD ≤ 5.5V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
D030A
D031A
D032
All others (Schmitt Trigger)
MCLR
0.2VDD
0.2VDD
0.2VDD
0.3VDD
D032A
D033
OSC1 (XT, HS, LP modes)
OSC1 (RC mode)
Input High Voltage
I/O ports:
(Note 1)
VIH
D040
with TTL buffer
2.0
0.25VDD + 0.8V
0.8VDD
0.8VDD
0.7VDD
0.9VDD
50
—
—
VDD
VDD
VDD
VDD
VDD
VDD
400
V
V
V
V
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
For entire VDD range
D040A
D041A
D042
All others (Schmitt Trigger)
MCLR
—
—
D042A
D043
OSC1 (XT, HS and LP modes)
OSC1 (RC mode)
—
(Note 1)
—
D070 IPURB PORTB Weak Pull-up
250
µA VDD = 5V, VPIN = VSS
Current
IIL
Input Leakage Current
(Notes 2, 3)
D060
I/O ports
—
—
1
µA VSS ≤ VPIN ≤ VDD,
pin at hi-impedance
D061
D063
MCLR
OSC1
—
—
—
—
5
5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS,
LP and EC osc mode
VOL
VOH
Output Low Voltage
I/O ports
D080
D083
—
—
—
—
0.6
0.6
V
V
IOL = 8.5mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.6mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKOUT (RC or EC
osc mode)
Output High Voltage
D090
D092
I/O ports (Note 3)
VDD - 0.7
VDD - 0.7
—
—
—
—
V
V
IOH = -3.0mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.3mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKOUT (RC or EC
osc mode)
Capacitive Loading Specs
on Output Pins
D100* COSC2 OSC2 pin
—
—
—
—
15
50
pF In XT, HS and LP modes
when external clock is
used to drive OSC1.
pF
D101* CIO
All I/O pins and OSC2
(Internal or EC osc mode)
These parameters are characterized, but not tested.
*
†
Data in “Typ” column is as 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In Internal Oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PICmicro MCU be driven with an external clock in Internal Oscillator mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS41142A-page 148
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
15.3 DC Characteristics: LVD-BOR
FIGURE 15-3: LOW VOLTAGE DETECT CHARACTERISTICS
VDD
VLVD
(LVDIF set by hardware)
LVDIF
TABLE 15-1: ELECTRICAL CHARACTERISTICS: LVD
VCC = 2.5V to 5.5V
Industrial (I):
Symbol
VPLVD
TAMB = -40°C to +85°C
Param
No.
Characteristic
LVD Voltage on VDD LVV = 0000
transition high to low LVV = 0001
LVV = 0010
Min Typ† Max Units
Conditions
D420
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.5
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VPLVD = 2.0V selected
VPLVD = 2.1V selected
VPLVD = 2.2V selected
VPLVD = 2.3V selected
VPLVD = 2.4V selected
VPLVD = 2.5V selected
VPLVD = 2.6V selected
VPLVD = 2.7V selected
VPLVD = 2.8V selected
VPLVD = 2.9V selected
VPLVD = 3.0V selected
VPLVD = 3.1V selected
VPLVD = 3.2V selected
VPLVD = 4.4V selected
VPLVD = 4.7V selected
LVV = 0011
LVV = 0100
LVV = 0101
LVV = 0110
LVV = 0111
LVV = 1000
LVV = 1001
LVV = 1010
LVV = 1011
LVV = 1100
LVV = 1101
LVV = 1110
D421
D422
LVD Voltage Drift Temperature
coefficient
LVD Voltage Drift with respect to VDD
Regulation
TCVOUT
15
50 ppm/°C
∆VLVD/
∆VDD
—
—
50 µV/V
Note 1: Production tested at TAMB = 25°C. Specifications over temp limits are insured by characterization.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 149
PIC18F010/020
FIGURE 15-4:
BROWN-OUT RESET CHARACTERISTICS
VDD
(Device not in Brown-out Reset)
VBOR
(Device in Brown-out Reset)
RESET (due to BOR)
72ms time out
TABLE 15-2: ELECTRICAL CHARACTERISTICS: BOR
VCC = 2.5V to 5.5V
Industrial (I):
TAMB = -40°C to +85°C
Param
No.
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
D005
D006
D006A
BOR Voltage on VDD transition high to low VBOR
BOR Voltage Drift Temperature coefficient TCVOUT
2.0
—
—
—
15
—
2.15
50
50
V
ppm/°C
µV/V
BOR Voltage Drift with respect to VDD
Regulation
∆VBOR/
∆VDD
Note 1: Production tested at TAMB = 25°C. Specifications over temp limits are insured by characterization.
DS41142A-page 150
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
15.4 AC Characteristics: (Commercial, Industrial)
15.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
osc
rd
OSC1
RD
CLKOUT
CS
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
T0CKI
T1CKI
WR
io
I/O port
t1
mc
MCLR
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
R
V
Z
Rise
High
Valid
Invalid (Hi-impedance)
Hi-impedance
L
P
Low
Period
High
Low
High
Low
FIGURE 15-5:
LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 151
PIC18F010/020
15.4.2
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 15-6:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
4
3
2
CLKOUT
TABLE 15-3: EXTERNAL CLOCK TIMING REQUIREMENTS
Param. No. Sym Characteristic Min Typ†
Max
Units
Conditions
FOSC External CLKIN Frequency
DC
DC
DC
DC
DC
DC
0.1
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Tcy
4
4
25
40
200
4
MHz RC osc mode
MHz XT osc mode
MHz HS osc mode
MHz EC osc mode
kHz LP osc mode
MHz RC osc mode
MHz XT osc mode
MHz HS osc mode
MHz HS osc mode
kHz LP osc mode
ns RC osc mode
ns XT osc mode
ns HS osc mode
ns HS osc mode
ns EC osc mode
µs LP osc mode
ns RC osc mode
µs XT osc mode
ns HS osc mode
ns HS osc mode
µs LP osc mode
ns TCY = 4/System Clock,
40 MHz max
(Note 1)
Oscillator Frequency
(Note 1)
4
25
8.25
200
—
—
—
—
—
—
—
4
5
1
TOSC External CLKIN Period
250
100
40
120
30
(Note 1)
5
Oscillator Period
(Note 1)
250
0.1
40
120
5
10
100
100
—
2
3
TCY Instruction Cycle Time
100
DC
(Note 1)
TosL, External Clock in (OSC1) High 30
—
—
—
—
—
—
—
—
—
20
50
7.5
ns XT oscillator
µs LP oscillator
ns HS oscillator
ns XT oscillator
ns LP oscillator
ns HS oscillator
TosH or Low Time
2.5
10
—
—
—
4
TosR, External Clock in (OSC1) Rise
TosF or Fall Time
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "min." values with an external
clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time limit is
"DC" (no clock) for all devices.
DS41142A-page 152
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
FIGURE 15-7:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
14
12
16
18
19
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 15-5 for load conditions.
TABLE 15-4: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
Symbol
Characteristic
Min
Typ†
Max
Units Conditions
No.
10*
11*
12*
13*
14*
15*
16*
17*
18*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
—
—
—
—
75
75
35
35
—
—
—
50
—
200
200
100
100
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
TckR
TckF
CLKOUT rise time
CLKOUT fall time
TckL2ioV CLKOUT ↓ to Port out valid
TioV2ckH Port in valid before CLKOUT ↑
TckH2ioI Port in hold after CLKOUT ↑
TosH2ioV OSC1↑ (Q1 cycle) to Port out valid
0.5TCY + 10 ns (Note 1)
0.25TCY + 25
—
—
ns (Note 1)
0
ns (Note 1)
—
150
—
ns
ns
TosH2ioI OSC1↑ (Q2 cycle) to
100
Port input invalid (I/O in hold time)
19*
TioV2osH Port input valid to OSC1↑
0
—
—
ns
(I/O in setup time)
20*
21*
TioR
TioF
Trbp
Port output rise time
—
—
10
10
—
25
25
—
ns
ns
ns
Port output fall time
23††*
RB5:RB0 change INT high or low time
TCY
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in Internal Oscillator mode where CLKOUT output is 4 x TOSC.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 153
PIC18F010/020
FIGURE 15-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 15-5 for load conditions.
FIGURE 15-9:
BROWN-OUT RESET TIMING
BVDD
VDD
35
DS41142A-page 154
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
TABLE 15-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Unit
s
Sym
Characteristic
Min
Typ†
Max
Conditions
30
TmcL MCLR Pulse Width (low)
100
7
—
—
ns VDD = 5V, -40°C to +85°C
ms VDD = 5V, -40°C to +85°C
31*
TWDT Watchdog Timer Time-out
Period (No Prescaler)
18
33
32
TOST Oscillation Start-up Timer
Period
—
1024TOSC
—
—
TOSC = OSC1 period
33*
34
TPWRT Power up Timer Period
28
72
132
100
ms VDD = 5V, -40°C to +85°C
TIOZ
I/O Hi-Impedance from MCLR
Low or Watchdog Timer Reset
—
—
ns
35
TBOR Brown-out Reset pulse width
100
—
—
µs VDD ≤ BVDD (D005)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
TABLE 15-6: BANDGAP START-UP TIME
Parameter
Symbol
Characteristic
Min
Typ†
Max Units
50
Conditions
No.
36*
TIVR
Internal Voltage Reference
start-up time
—
20
µs Defined as the time between
the instant that the Internal
Voltage Reference is enabled
and the moment that the
Internal Voltage Reference is
stable.
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 155
PIC18F010/020
FIGURE 15-10:
TIMER0 EXTERNAL CLOCK TIMINGS
RB2/T0CKI
41
40
42
48
TMR0
Note: Refer to Figure 15-5 for load conditions.
TABLE 15-7: TIMER0 EXTERNAL CLOCK REQUIREMENTS
Param
Sym
Characteristic
Min
Typ† Max Units
Conditions
No.
40*
Tt0H
T0CKI High Pulse Width No Prescaler
With Prescaler
T0CKI Low Pulse Width No Prescaler
With Prescaler
0.5TCY + 5
10
0.5TCY + 5
10
TCY + 10
Greater of:
20 or TCY + 20
N
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 42
ns
ns Must also meet
41*
42*
Tt0L
Tt0P
parameter 42
ns
ns
T0CKI Period
No Prescaler
With Prescaler
ns N = prescale value
(2, 4, ..., 256)
48 TCKEZtmr1 Delay from external clock edge to timer
increment
2Tosc
—
7Tosc
—
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS41142A-page 156
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
16.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and Tables not available at this time.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 157
PIC18F010/020
NOTES:
DS41142A-page 158
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
17.0 PACKAGING INFORMATION
17.1 Package Marking Information
8-Lead PDIP (Skinny DIP)
Example
18F010-I
XXXXXXXX
XXXXXNNN
YYWW
017
0015
8-Lead SOIC
8-Lead SOIC
XXXXXXXX
XXXXYYWW
NNN
18F010
0015
017
Legend: XX...X Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 159
PIC18F010/020
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS41142A-page 160
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
Overall Height
A
.053
.069
1.35
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.32
0.10
5.79
3.71
4.80
0.25
0.48
0
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 161
PIC18F010/020
NOTES:
DS41142A-page 162
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
APPENDIX A: CONVERSION
CONSIDERATIONS
APPENDIX B: MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This appendix discusses the considerations for con-
verting from previous version of a device to the ones
listed in this data sheet. Typically, these changes are
due to the differences in the process technology used.
An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
This section discusses how to migrate from a Baseline
device (i.e., PIC16C5X) to an Enhanced MCU device
(i.e., PIC18CXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Applicable
Not Currently Available
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 163
PIC18F010/020
APPENDIX C: MIGRATION FROM
MID-RANGE TO
APPENDIX D: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
ENHANCED DEVICES
This section discusses how to migrate from a Mid-
Range device (i.e., PIC16CXXX) to an Enhanced
device (i.e., PIC18CXXX).
This section discusses how to migrate from a High-End
device (i.e., PIC17CXXX) to an Enhanced MCU device
(i.e., PIC18CXXX).
The following are the list of modifications over the
PIC16CXXX microcontroller family:
The following are the list of modifications over the
PIC17CXXX microcontroller family:
Not Currently Available
Not Currently Available
DS41142A-page 164
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
INDEX
A
C
Absolute Maximum Ratings ............................................. 145
AC Characteristics
CALL ................................................................................ 110
CLKOUT and I/O Timing Requirements .......................... 153
Clocking Scheme ............................................................... 28
Clocking Scheme/Instruction Cycle ................................... 28
CLRF ............................................................................... 111
CLRWDT ......................................................................... 111
Code Examples
(Commercial, Industrial) ........................................... 151
Access Bank ...................................................................... 37
ADDLW ............................................................................ 101
ADDWF ............................................................................ 101
ADDWFC ......................................................................... 102
ANDLW ............................................................................ 102
ANDWF ............................................................................ 103
Appendix A
Conversion Considerations ...................................... 163
Appendix B
Migration from Baseline to Enhanced Devices ........ 163
Appendix C
Data EEPROM Read ................................................. 45
Data EEPROM Write ................................................. 45
Fast Register Stack ................................................... 27
Initializing PORTB ..................................................... 67
Program Memory Read ............................................. 48
Program Memory Write ............................................. 51
Saving STATUS, WREG and BSR Registers
Migration from Mid-Range to Enhanced Devices .... 164
Appendix D
Migration from High-End to Enhanced Devices ....... 164
Assembler
in RAM ................................................................... 66
Code Protection ........................................................... 83, 93
COMF .............................................................................. 112
Computed GOTO ............................................................... 30
Configuration Bits .............................................................. 83
Context Saving During Interrupts ....................................... 66
Control Registers ............................................................... 47
CPFSEQ .......................................................................... 112
CPFSGT .......................................................................... 113
CPFSLT ........................................................................... 113
Crystal Oscillator/Ceramic Resonators ................................ 7
MPASM Assembler .................................................. 139
B
Bank Select Register (BSR) ............................................... 37
BC .................................................................................... 103
BCF .................................................................................. 104
Block Diagrams
Low Voltage Detect (LVD) ......................................... 78
PIC18F010/020 ............................................................ 4
RB<2:0> Pins ............................................................. 68
RB3 Pin ...................................................................... 68
RB4 Pin ...................................................................... 69
RB5 Pin ...................................................................... 69
Simplified Block Diagram of
D
Data EEPROM Memory ..................................................... 43
Data Memory ..................................................................... 31
General Purpose Registers ....................................... 31
Special Function Registers ........................................ 31
DAW ................................................................................ 114
DC Characteristics ................................................... 147, 148
DC Characteristics
On-chip Reset Circuit ............................................. 15
Simplified Block Diagram of PORT/LAT/TRIS
Operation ............................................................... 67
Timer0 in 16-bit Mode ................................................ 74
Timer0 in 8-bit Mode .................................................. 74
Watchdog Timer ......................................................... 89
BN .................................................................................... 104
BNC ................................................................................. 105
BNN ................................................................................. 105
BNOV ............................................................................... 106
BNZ .................................................................................. 106
BOR. See Brown-out Reset
BOV ................................................................................. 109
BRA .................................................................................. 107
Brown-out Reset (BOR) ............................................... 16, 83
Brown-out Reset Characteristics ..................................... 150
BSF .................................................................................. 107
BTFSC ............................................................................. 108
BTFSS ............................................................................. 108
BTG .................................................................................. 109
BZ .................................................................................... 110
LVD-BOR ................................................................. 149
DECF ............................................................................... 114
DECFSNZ ........................................................................ 115
DECFSZ .......................................................................... 115
Development Support ...................................................... 139
Device Overview .................................................................. 3
Direct Addressing .............................................................. 39
E
EEADR .............................................................................. 43
EEADR Register ................................................................ 43
EECON1 and EECON2 Registers ..................................... 43
EECON1 Register ........................................................ 44, 47
Effects of SLEEP Mode on the On-chip Oscillator ............. 12
Electrical Characteristics ................................................. 145
BOR ......................................................................... 150
Errata ................................................................................... 2
External Clock Input ............................................................. 9
F
Fast Register Stack ........................................................... 27
Firmware Instructions ........................................................ 95
Frequency Calibrations ...................................................... 13
Frequency Tuning in User Mode ....................................... 13
G
GOTO .............................................................................. 116
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 165
PIC18F010/020
RETLW .................................................................... 126
RETURN .................................................................. 127
RLCF ....................................................................... 127
RLNCF ..................................................................... 128
RRCF ....................................................................... 128
RRNCF .................................................................... 129
SETF ....................................................................... 129
SLEEP ..................................................................... 130
SUBFWB ......................................................... 130, 131
SUBLW .................................................................... 131
SUBWF .................................................................... 132
SUBWFB ................................................................. 133
SWAPF .................................................................... 134
TBLRD ..................................................................... 135
TBLWT .................................................................... 136
TSTFSZ ................................................................... 137
XORLW ................................................................... 137
XORWF ................................................................... 138
Summary Table ......................................................... 98
Instructions in Program Memory ........................................ 29
INT Interrupt (RB0/INT). See Interrupt Sources
INT0 Interrupt ..................................................................... 66
INTCON Registers ............................................................. 61
Internal Oscillator ................................................................. 8
Interrupt Sources ......................................................... 59, 83
RB0/INT Pin, External ................................................ 66
TMR0 Overflow .......................................................... 75
Interrupt-on-Change PORTB Register ............................... 70
IORLW ............................................................................. 118
IORWF ............................................................................. 118
IPR Registers ..................................................................... 63
I
I/O Port
Additional Functions ...................................................67
ICEPIC In-Circuit Emulator ..............................................140
ID Locations ................................................................. 83, 93
INCF .................................................................................116
INCFSNZ ..........................................................................117
INCFSZ ............................................................................117
In-Circuit Serial Programming (ICSP) ..........................83, 93
Indirect Addressing ............................................................39
FSR Register .............................................................38
INDF and FSR Registers ...........................................38
Indirect Addressing Operation ............................................38
Instruction Flow/Pipelining .................................................28
Instruction Format ..............................................................97
Instruction Set ....................................................................95
ADDLW ....................................................................101
ADDWF ....................................................................101
ADDWFC .................................................................102
ANDLW ....................................................................102
ANDWF ....................................................................103
BC ............................................................................103
BCF ..........................................................................104
BN ............................................................................104
BNC .........................................................................105
BNN .........................................................................105
BNOV .......................................................................106
BNZ ..........................................................................106
BOV .........................................................................109
BRA ..........................................................................107
BSF ..........................................................................107
BTFSC .....................................................................108
BTFSS .....................................................................108
BTG ..........................................................................109
BZ ............................................................................110
CALL ........................................................................110
CLRF ........................................................................111
CLRWDT ..................................................................111
COMF ......................................................................112
CPFSEQ ..................................................................112
CPFSGT ..................................................................113
CPFSLT ...................................................................113
DAW .........................................................................114
DECF .......................................................................114
DECFSNZ ................................................................115
DECFSZ ...................................................................115
GOTO ......................................................................116
INCF .........................................................................116
INCFSNZ .................................................................117
INCFSZ ....................................................................117
IORLW .....................................................................118
IORWF .....................................................................118
LFSR ........................................................................119
MOVF .......................................................................119
MOVFF ....................................................................120
MOVLB ....................................................................120
MOVLW ...................................................................121
MOVWF ...................................................................121
MULLW ....................................................................122
MULWF ....................................................................122
NEGF .......................................................................123
NOP .........................................................................123
POP .........................................................................124
PUSH .......................................................................124
RCALL .....................................................................125
RESET .....................................................................125
RETFIE ....................................................................126
K
KEELOQ Evaluation and Programming Tools ................... 142
L
LFSR ................................................................................ 119
Lookup Tables ................................................................... 30
Low Voltage Detect ............................................................ 77
Control Register ......................................................... 79
Current Consumption ................................................. 81
Effects of a RESET .................................................... 81
Operation ................................................................... 80
Operation During SLEEP ........................................... 81
Typical Low Voltage Detect Application ..................... 77
Waveforms ................................................................. 80
Low Voltage Detect Characteristics ................................. 149
LVD
Electrical Characteristics ......................................... 149
LVDCON Register ............................................................. 79
M
Memory Organization ........................................................ 23
Data Memory ............................................................. 31
Program Memory ....................................................... 23
MOVF .............................................................................. 119
MOVFF ............................................................................ 120
MOVLB ............................................................................ 120
MOVLW ........................................................................... 121
MOVWF ........................................................................... 121
MPLAB C17 and MPLAB C18 C Compilers .................... 139
MPLAB ICD In-Circuit Debugger ..................................... 141
MPLAB ICE High Performance Universal
In-Circuit Emulator with MPLAB IDE ........................... 140
MPLAB Integrated Development
Environment Software ................................................. 139
MPLINK Object Linker/MPLIB Object Librarian ............... 140
MULLW ............................................................................ 122
DS41142A-page 166
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
Multiply Examples
16 x 16 Signed Multiply Routine ................................ 57
16 x 16 Unsigned Multiply Routine ............................ 56
8 x 8 Signed Multiply Routine .................................... 56
8 x 8 Unsigned Multiply Routine ................................ 56
MULWF ............................................................................ 122
Power-on Reset (POR) ................................................ 16, 83
Oscillator Start-up Timer (OST) ........................... 16, 83
Power-up Timer (PWRT) ..................................... 16, 83
Time-out Sequence ................................................... 17
Time-out Sequence on Power-up ........................ 20, 21
Power-up Delays ............................................................... 13
Prescaler, Timer0 .............................................................. 75
Assignment (PSA Bit) ................................................ 75
Rate Select (TOPS2:TOPS0 Bits) ............................. 75
Switching Between Timer0 and WDT ........................ 75
PRO MATE II Universal Device Programmer .................. 141
Product Identification System .......................................... 171
Product Pinout Overview ..................................................... 5
Program Counter
PCL, PCLATH and PCLATU Registers ..................... 27
PCLATH Register ...................................................... 27
Program Memory ............................................................... 23
Program Verification .......................................................... 93
Programming, Device Instructions ..................................... 95
Protection Against Spurious Write ..................................... 46
PUSH ............................................................................... 124
PUSH and POP Instructions .............................................. 27
N
NEGF ............................................................................... 123
NOP ................................................................................. 123
O
Operation During Code Protect .......................................... 46
Operation During Code Protect .......................................... 46
OPTION_REG Register
PSA Bit ....................................................................... 75
T0CS Bit ..................................................................... 75
T0SE Bit ..................................................................... 75
TOPS2:TOPS0 Bits ................................................... 75
OSCCON Register ............................................................. 10
Oscillator Configuration ........................................................ 7
EC ................................................................................ 7
HS ................................................................................ 7
INTOSC ....................................................................... 7
INTOSCIO .................................................................... 7
LP ................................................................................. 7
RC ................................................................................ 7
RCIO ............................................................................ 7
XT ................................................................................ 7
Oscillator Delay Upon Start-up and Base
R
RAM. See Data Memory
RCALL ............................................................................. 125
RCON Register ............................................................ 41, 63
Reading the Data EEPROM Memory ................................ 45
Register File ....................................................................... 31
Registers
Frequency Change ........................................................ 14
Oscillator Selection ............................................................ 83
Oscillator Transitions ......................................................... 11
OSCTUNE Register ........................................................... 13
CONFIG1H ................................................................ 84
CONFIG1L ................................................................. 85
CONFIG2H ................................................................ 86
CONFIG2L ................................................................. 87
EECON1 .................................................................... 44
INTCON ..................................................................... 61
INTCON2 ................................................................... 62
IOCB .......................................................................... 70
IPR2 ........................................................................... 65
LVDCON .................................................................... 79
OSCCON ................................................................... 10
OSCTUNE ................................................................. 13
PIE2 ........................................................................... 64
PIR2 ........................................................................... 64
RCON ............................................................ 17, 41, 63
STATUS .................................................................... 40
STKPTR - Stack Pointer ............................................ 26
T0CON ...................................................................... 73
WDTCON .................................................................. 88
WPUB ........................................................................ 70
RESET ................................................................. 15, 83, 125
RESET, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset Requirements . 155
RETFIE ............................................................................ 126
RETLW ............................................................................ 126
RETURN .......................................................................... 127
Return Address Stack ........................................................ 25
Return Stack Pointer (STKPTR) ........................................ 25
RLCF ............................................................................... 127
RLNCF ............................................................................. 128
RRCF ............................................................................... 128
RRNCF ............................................................................ 129
P
Packaging ........................................................................ 159
PICDEM 1 Low Cost PICmicro
Demonstration Board ................................................... 141
PICDEM 17 Demonstration Board ................................... 142
PICDEM 2 Low Cost PIC16CXX
Demonstration Board ................................................... 141
PICDEM 3 Low Cost PIC16CXXX
Demonstration Board ................................................... 142
PICSTART Plus Entry Level
Development Programmer ........................................... 141
PIE Registers ..................................................................... 63
PIR Registers ..................................................................... 63
Pointer, FSR ...................................................................... 38
POP ................................................................................. 124
POR. See Power-on Reset
PORTB
Interrupt-on-Change ................................................... 67
RB0/INT Pin, External ................................................ 66
Weak Pull-up .............................................................. 67
PORTB Interrupt-on-Change ............................................. 66
Postscaler, WDT
Assignment (PSA Bit) ................................................ 75
Rate Select TO(PS2:TOPS0 Bits) ............................. 75
Switching Between Timer0 and WDT ........................ 75
Power-down Mode. See SLEEP
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 167
PIC18F010/020
TMR0 Interrupt ................................................................... 66
Top-of-Stack Access .......................................................... 25
TSTFSZ ........................................................................... 137
Two-Speed Clock Start-up Mode ....................................... 10
Two-Word Instructions ....................................................... 30
S
SETF ................................................................................129
SLEEP .................................................................. 83, 90, 130
Software Simulator (MPLAB SIM) ....................................140
Special Features of the CPU ..............................................83
Special Function Registers ................................................31
Stack Full/Underflow Resets ..............................................27
STATUS Register ...............................................................40
STKPTR - Stack Pointer Register ......................................26
SUBFWB .................................................................. 130, 131
SUBLW ............................................................................131
SUBWF ............................................................................132
SUBWFB ..........................................................................133
SWAPF ............................................................................134
W
Wake-up from SLEEP .................................................. 83, 90
Timing Diagram ......................................................... 91
Watchdog Timer (WDT) ............................................... 83, 88
Block Diagram ........................................................... 89
Control Register ......................................................... 88
Postscaler. See Postscaler, WDT
Programming Considerations .................................... 88
Time-out Period ......................................................... 88
WDTCON Register ............................................................ 88
Weak Pull-up Register ....................................................... 70
Writing to the Data EEPROM Memory .............................. 45
WWW, On-Line Support ...................................................... 2
T
TABLAT - Table Latch Register .........................................53
Table Read/Write Instructions ............................................47
Table Reads/Table Writes ..................................................30
TBLPTR - Table Pointer Register ......................................53
TBLRD .............................................................................135
TBLWT .............................................................................136
Timer0
X
XORLW ............................................................................ 137
XORWF ........................................................................... 138
Clock Source Edge Select (T0SE Bit) ........................75
Clock Source Select (T0CS Bit) .................................75
Overflow Interrupt ......................................................75
Prescaler. See Prescaler, Timer0
TIMER0 Control Register ...................................................73
Timing Diagrams
Brown-out Reset ......................................................154
CLKOUT and I/O ......................................................153
CLKOUT and I/O Timing ..........................................153
External Clock Timing ..............................................152
Power-up Timer .......................................................154
RESET .....................................................................154
Slow Rise Time (MCLR Tied to VDD) .........................21
Start-up Timer ..........................................................154
Time-out Sequence on Power-up (Case 1) ...............20
Time-out Sequence on Power-up (MCLR
Not Tied to VDD) - Case 2 ......................................20
Time-out Sequence on Power-up (MCLR
Tied to VDD) ...........................................................20
Transition Between Internal Oscillator and
OSC1 (EC) .............................................................11
Transition from External Oscillator to
Internal Oscillator ...................................................11
Wake-up from SLEEP via Interrupt ............................91
Watchdog Timer .......................................................154
DS41142A-page 168
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
ConnectingtotheMicrochipInternetWebSite
001024
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 169
PIC18F010/020
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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Literature Number:
DS41142A
Device:
PIC18F010/020
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
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8. How would you improve our software, systems, and silicon products?
DS41142A-page 170
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
PIC18F010/020 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
−
Examples:
Temperature Package
Range
Pattern
a) PIC18LF010 - I/P 301 = Industrial temp.,
PDIP package, 40 MHz, Extended VDD
limits, QTP pattern #301.
b) PIC18LF020 - I/SO = Industrial temp.,
SOIC package, Extended VDD limits.
(1)
(2)
Device
PIC18F0X0 , PIC18F0X0T
VDD range 4.5V to 5.5V
;
c) PIC18F020 - I/P = Industrial temp., PDIP
package, 40MHz, normal VDD
limits.
(1)
(2)
PIC18LF0X0 , PIC18LF0X0T
VDD range 2.0V to 5.5V
;
Temperature
Range
I
= -40°C to +85°C (Industrial)
Note 1:
2:
F
= Standard Voltage range
LF = Wide Voltage Range
= in tape and reel - SOIC
Package
Pattern
SO
P
=
=
SOIC
PDIP
T
QTP, SQTP, Code or Special Requirements
(blank otherwise)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 171
PIC18F010/020
NOTES:
DS41142A-page 172
Preliminary
2001 Microchip Technology Inc.
PIC18F010/020
NOTES:
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 173
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ASIA/PACIFIC (continued)
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01/30/01
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 3/01
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
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tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS41142A-page 174
Preliminary
2001 Microchip Technology Inc.
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