PIC18C858E/PTXXX [MICROCHIP]
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC;
| 型号： | PIC18C858E/PTXXX |
| 厂家： | 
MICROCHIP |
| 描述： | IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC 可编程只读存储器 微控制器 |
| 文件： | 总366页 (文件大小：6058K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18CXX8
High-Performance Microcontrollers with CAN Module
High Performance RISC CPU:
Advanced Analog Features:
• C-compiler optimized architecture instruction set
• Linear program memory addressing to 32 Kbytes
• Linear data memory addressing to 4 Kbytes
Program Memory
• 10-bit Analog-to-Digital Converter module (A/D)
with:
-
-
-
-
Fast sampling rate
Conversion available during SLEEP
DNL = ±1 LSb, INL = ±1 LSb
Up to 16 channels available
On-Chip
Off-Chip On-Chip
Device
RAM
(bytes)
• Analog Comparator Module:
# Single
Word
Instructions
Maximum
Addressing
(bytes)
EPROM
(bytes)
-
-
2 Comparators
Programmable input and output multiplexing
• Comparator Voltage Reference Module
PIC18C658 32 K
PIC18C858 32 K
16384
16384
N/A
N/A
1536
1536
• Programmable Low Voltage Detection (LVD)
module
• Up to 10 MIPS operation:
- DC - 40 MHz clock input
-
Supports interrupt on low voltage detection
• Programmable Brown-out Reset (BOR)
- 4 MHz - 10 MHz osc./clock input with PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
CAN BUS Module Features:
• Message bit rates up to 1 Mbps
• Conforms to CAN 2.0B ACTIVE Spec with:
- 29-bit Identifier Fields
• 8 x 8 Single Cycle Hardware Multiplier
Peripheral Features:
- 8 byte message length
• High current sink/source 25 mA/25 mA
• Up to 76 I/O with individual direction control
• Four external interrupt pins
• 3 Transmit Message Buffers with prioritization
• 2 Receive Message Buffers
• 6 full 29-bit Acceptance Filters
• Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
• Prioritization of Acceptance Filters
• Multiple Receive Buffers for High Priority
Messages to prevent loss due to overflow
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter with 8-bit
period register (time base for PWM)
• Advanced Error Management Features
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Timer (PWRT),
and Oscillator Start-up Timer (OST)
• Timer3 module: 16-bit timer/counter
• Secondary oscillator clock option - Timer1/Timer3
• Two Capture/Compare/PWM (CCP) modules
CCP pins can be configured as:
• Watchdog Timer (WDT) with its own on-chip RC
oscillator
- Capture input: 16-bit, max resolution 6.25 ns
- Compare is 16-bit, max resolution 100 ns (TCY)
- PWM output: PWM resolution is 1- to 10-bit.
Max. PWM freq. @:8-bit resolution = 156 kHz
10-bit resolution = 39 kHz
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options, including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
• Master Synchronous Serial Port (MSSP) with two
modes of operation:
•
In-Circuit Serial Programming (ICSP™) via two pins
- 3-wire SPI™ (Supports all 4 SPI modes)
CMOS Technology:
• Low power, high speed EPROM technology
• Fully static design
- I2C™ Master and Slave mode
• Addressable USART module: Supports Interrupt
on Address bit
• Wide operating voltage range (2.5V to 5.5V)
• Industrial and Extended temperature ranges
• Low power consumption
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 1
PIC18CXX8
Pin Diagrams
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4
RE1/WR
RE0/RD
2
3
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
4
5
6
RB5
7
MCLR/VPP
RG4
RB6
8
VSS
PIC18C658
9
VSS
OSC2/CLKO/RA6
OSC1/CLKI
VDD
10
11
12
13
14
15
16
VDD
RF7
RB7
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RF3/AN8
RF2/AN7/C1OUT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DS30475A-page 2
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Pin Diagrams (Cont.’d)
68-Pin PLCC
9
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
11
60
59
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4
RE1/WR
RE0/RD
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
12
13
14
15
16
17
18
19
20
21
58
57
56
55
54
53
52
51
50
49
RB5
RB6
MCLR/VPP
RG4
VSS
PIC18C658
NC
NC
VSS
VDD
OSC2/CLKO/RA6
OSC1/CLKI
VDD
RF7
22
23
24
25
26
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
48
47
46
45
44
RB7
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
2728 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 3
PIC18CXX8
Pin Diagrams (Cont.’d)
80-Pin TQFP
80 79 78
77 76 75 74 73 72 71 70 69 68 67 66 65
64 63 62 61
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RJ2
RH2
2
RH3
RJ3
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4
RE1/WR
RE0/RD
3
4
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
5
6
7
RB5
8
RB6
9
MCLR/VPP
RG4
VSS
10
11
12
13
14
15
16
17
18
19
20
OSC2/CLKO/RA6
OSC1/CLKI
VDD
VSS
PIC18C858
VDD
RF7
RB7
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RK3
RF3/AN8
RF2/AN7/C1OUT
RH7/AN15
RH6/AN14
RK2
40
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
DS30475A-page 4
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Pin Diagrams (Cont.’d)
84-Pin PLCC
83 82 81
11
9 8
7
6
5
4 3
2
1
84
80
797877 76 75
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RH2
RH3
RE1/WR
RE0/RD
RJ2
RJ3
RB0/INT0
74
73
72
71
70
69
68
67
66
RB1/INT1
RB2/INT2
RB3/INT3
RB4
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RB5
RB6
MCLR/VPP
RG4
65
64
63
VSS
NC
PIC18C858
NC
VSS
VDD
OSC2/CLKO/RA6
OSC1/CLKI
VDD
62
61
60
59
RF7
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RB7
RC5/SDO
58
57
56
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RF3/AN8
RF2/AN7/C1OUT
RH7/AN15
RH6/AN14
55
54
RK3
RK2
33 3435 36 37 38 39 40 41 42 43 44
45
46 47
48 49
51
50
52 53
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 5
PIC18CXX8
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Oscillator Configurations ............................................................................................................................................................ 21
3.0 Reset.......................................................................................................................................................................................... 29
4.0 Memory Organization................................................................................................................................................................. 41
5.0 Table Reads/Table Writes.......................................................................................................................................................... 65
6.0 8 X 8 Hardware Multiplier........................................................................................................................................................... 71
7.0 Interrupts .................................................................................................................................................................................... 75
8.0 I/O Ports ..................................................................................................................................................................................... 89
9.0 Parallel Slave Port.................................................................................................................................................................... 109
10.0 Timer0 Module ......................................................................................................................................................................... 113
11.0 Timer1 Module ......................................................................................................................................................................... 117
12.0 Timer2 Module ......................................................................................................................................................................... 121
13.0 Timer3 Module ......................................................................................................................................................................... 123
14.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 127
15.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 135
16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 167
17.0 CAN Module ............................................................................................................................................................................. 183
18.0 10-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 227
19.0 Comparator Module.................................................................................................................................................................. 237
20.0 Comparator Voltage Reference Module................................................................................................................................... 243
21.0 Low Voltage Detect .................................................................................................................................................................. 247
22.0 Special Features of the CPU.................................................................................................................................................... 251
23.0 Instruction Set Summary.......................................................................................................................................................... 261
24.0 Development Support............................................................................................................................................................... 305
25.0 Electrical Characteristics.......................................................................................................................................................... 311
26.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 341
27.0 Packaging Information.............................................................................................................................................................. 343
Appendix A: Data Sheet Revision History...................................................................................................................................... 349
Appendix B: Device Differences..................................................................................................................................................... 349
Appendix C: Device Migrations ...................................................................................................................................................... 350
Appendix D: Migrating from other PICmicro Devices..................................................................................................................... 350
Appendix E: Development Tool Version Requirements................................................................................................................. 351
Index .................................................................................................................................................................................................. 353
On-Line Support................................................................................................................................................................................. 361
Reader Response .............................................................................................................................................................................. 362
PIC18CXX8 Product Identification System ........................................................................................................................................ 363
DS30475A-page 6
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 7
PIC18CXX8
NOTES:
DS30475A-page 8
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
The following two figures are device block diagrams
sorted by pin count; 64/68-pin for Figure 1-1 and
80/84-pin for Figure 1-2. The 64/68-pin and 80/84-pin
pinouts are listed in Table 1-2.
1.0
DEVICE OVERVIEW
This document contains device specific information for
the following three devices:
1. PIC18C658
2. PIC18C858
The PIC18C658 is available in 64-pin TQFP and 68-pin
PLCC packages. The PIC18C858 is available in 80-pin
TQFP and 84-pin PLCC packages.
An overview of features is shown in Table 1-1.
TABLE 1-1:
DEVICE FEATURES
Features
PIC18C658
PIC18C858
Operating Frequency
DC - 40 MHz
32 K
DC - 40 MHz
32 K
Bytes
Program Memory Internal
# of Single word
Instructions
16384
16384
Data Memory (Bytes)
Interrupt sources
I/O Ports
1536
1536
21
21
Ports A – G
Ports A – H, J, K
Timers
4
2
4
2
Capture/Compare/PWM modules
MSSP, CAN
Addressable USART
MSSP, CAN
Addressable USART
Serial Communications
Parallel Communications
10-bit Analog-to-Digital Module
Analog Comparators
PSP
12 input channels
2
PSP
16 input channels
2
POR, BOR,
POR, BOR,
RESETInstruction, Stack Full, RESETInstruction, Stack Full,
RESETS (and Delays)
Stack Underflow
(PWRT, OST)
Stack Underflow
(PWRT, OST)
Programmable Low Voltage Detect
Programmable Brown-out Reset
CAN Module
Yes
Yes
Yes
Yes
Yes
Yes
In-Circuit Serial Programming (ICSP™)
Instruction Set
Yes
Yes
75 Instructions
75 Instructions
64-pin TQFP
68-pin CERQUAD
(Windowed)
80-pin TQFP
84-pin CERQUAD
(Windowed)
Packages
68-pin PLCC
84-pin PLCC
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 9
PIC18CXX8
FIGURE 1-1: PIC18C658 BLOCK DIAGRAM
Data Bus<8>
PORTA
RA0/AN0
RA1/AN1
Table Pointer<21>
21
Data Latch
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
8
8
Data RAM
( 1.5 K )
21
inc/dec logic
Address Latch
12
20
PCLATU
PCLATH
PORTB
Address<12>
PCH PCL
PCU
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
Program Counter
4
BSR
12
FSR0
FSR1
FSR2
4
Bank0, F
Address Latch
Program Memory
(32 Kbytes)
31 Level Stack
RB7:RB4
12
Data Latch
PORTC
inc/dec
logic
Decode
RC0/T1OSO/T13CKI
RC1/T1OSI
TABLELATCH
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
16
ROMLATCH
IR
PORTD
PORTE
8
RD7/PSP7:RD0/PSP0
PRODH PRODL
8 x 8 Multiply
Instruction
Decode &
Control
RE0/RD
RE1/WR
RE2/CS
RE3
RE4
RE5
8
3
WREG
8
BITOP
8
8
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
RE6
RE7/CCP2
Timing
Generation
Oscillator
Start-up Timer
8
ALU<8>
Power-on
Reset
PORTF
PORTG
RF7
8
Watchdog
Timer
RF6/AN11:RF0/AN5
Precision
Brown-out
Reset
Bandgap
Reference
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
MCLR
VDD, VSS
RG4
BOR
LVD
10-bit
ADC
Timer3
USART
Timer0
CCP1
Timer2
Timer1
Synchronous
Serial Port
Comparator
CCP2
CAN Module
DS30475A-page 10
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 1-2: PIC18C858 BLOCK DIAGRAM
Data Bus<8>
PORTA
RA0/AN0
RA1/AN1
Table Pointer<21>
21
Data Latch
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
8
8
Data RAM
( 1.5 K )
21
inc/dec logic
Address Latch
12
20
PCLATU
PCLATH
PORTB
Address<12>
PCH PCL
PCU
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
Program Counter
4
BSR
12
FSR0
FSR1
FSR2
4
Bank0, F
Address Latch
Program Memory
(32 Kbytes)
31 Level Stack
RB7:RB4
12
Data Latch
PORTC
inc/dec
logic
Decode
RC0/T1OSO/T13CKI
RC1/T1OSI
TABLELATCH
RC2/CCP1
8
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
16
ROMLATCH
IR
PORTD
PORTE
8
RD7/PSP7:RD0/PSP0
PRODH PRODL
8 x 8 Multiply
Instruction
Decode &
Control
RE0/RD
RE1/WR
RE2/CS
RE3
RE4
RE5
8
3
WREG
8
BITOP
8
8
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
RE6
RE7
Oscillator
Start-up Timer
Timing
Generation
8
ALU<8>
Power-on
Reset
PORTF
PORTG
RF7
8
Watchdog
Timer
RF6/AN11:RF0/AN5
Precision
Brown-out
Reset
Bandgap
Reference
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
MCLR
VDD, VSS
RG4
PORTH
PORTK
PORTJ
RH0
RH1
RH2
RK0
RK1
RK2
RK3
RJ0
RJ1
RJ2
RJ3
RH3
RH7/AN15:RH4/AN12
BOR
LVD
10-bit
ADC
Timer3
Timer0
CCP1
Timer2
Timer1
Synchronous
Serial Port
USART
Comparator
CCP2
CAN Module
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 11
PIC18CXX8
TABLE 1-2:
PINOUT I/O DESCRIPTIONS
Pin Number
PIC18C658 PIC18C858
TQFP PLCC TQFP PLCC
Pin
Type
Buffer
Type
Pin Name
Description
MCLR/VPP
MCLR
7
16
9
20
I
ST
—
Master clear (RESET) input. This pin is
an active low RESET to the device.
Programming voltage input
VPP
NC
P
—
1, 18,
35, 52
—
1, 22,
43, 64
—
These pins should be left
unconnected
OSC1/CLKI
OSC1
39
50
49
62
I
I
CMOS/ST
Oscillator crystal input or external
clock source input. ST buffer when
configured in RC mode. Otherwise
CMOS.
External clock source input. Always
associated with pin function OSC1
(see OSC1/CLKI, OSC2/CLKO pins).
CLKI
CMOS
OSC2/CLKO/RA6
OSC2
40
51
50
63
O
O
—
—
Oscillator crystal output.
Connects to crystal or resonator in
Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO,
which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate
General purpose I/O pin
CLKO
RA6
I/O
TTL
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
DS30475A-page 12
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
PIC18C658
PIC18C858
TQFP PLCC TQFP PLCC
Description
PORTA is a bi-directional I/O port
RA0/AN0
RA0
24
23
22
34
33
32
30
29
28
42
41
40
I/O
I
TTL
Analog
Digital I/O
Analog input 0
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O
Analog input 1
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O
AN2
VREF-
I
I
Analog
Analog
Analog input 2
A/D reference voltage (Low) input
RA3/AN3/VREF+
RA3
21
28
27
31
39
38
27
34
33
39
47
46
I/O
I
I
TTL
Analog
Analog
Digital I/O
Analog input 3
A/D reference voltage (High) input
AN3
VREF+
RA4/T0CKI
RA4
I/O
I
ST/OD
ST
Digital I/O – Open drain when
configured as output
Timer0 external clock input
T0CKI
RA5/AN4/SS/LVDIN
RA5
AN4
SS
I/O
TTL
Analog
ST
Digital I/O
Analog input 4
SPI slave select input
Low voltage detect input
I
I
I
LVDIN
Analog
RA6
See the OSC2/CLKO/RA6 pin
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 13
PIC18CXX8
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
PIC18C658 PIC18C858
TQFP PLCC TQFP PLCC
Pin
Type
Buffer
Type
Pin Name
Description
PORTB is a bi-directional I/O port.
PORTB can be software
programmed for internal weak pull-ups on
all inputs.
RB0/INT0
RB0
48
47
46
45
60
59
58
57
58
57
56
55
72
71
70
69
I/O
I
TTL
ST
Digital I/O
External interrupt 0
INT0
RB1/INT1
RB1
I/O
I
TTL
ST
Digital I/O
External interrupt 1
INT1
RB2/INT2
RB2
I/O
I
TTL
ST
Digital I/O
External interrupt 2
INT2
RB3/INT3
RB3
I/O
I/O
TTL
ST
Digital I/O
External interrupt 3
INT3
RB4
RB5
RB6
44
43
42
56
55
54
54
53
52
68
67
66
I/O
I/O
I/O
TTL
TTL
TTL
Digital I/O
Interrupt on change pin
Digital I/O
Interrupt-on-change pin
Digital I/O
Interrupt-on-change pin
ICSP programming clock
I
ST
RB7
37
48
47
60
I/O
TTL
Digital I/O
Interrupt-on-change pin
ICSP programming data
I/O
ST
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
DS30475A-page 14
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
PIC18C658
PIC18C858
TQFP PLCC TQFP PLCC
Description
PORTC is a bi-directional I/O port
RC0/T1OSO/T13CKI
RC0
30
41
36
49
I/O
O
I
ST
—
ST
Digital I/O
Timer1 oscillator output
Timer1/Timer3 external clock input
T1OSO
T13CKI
RC1/T1OSI
RC1
29
33
40
44
35
43
48
56
I/O
I
ST
CMOS
Digital I/O
Timer1 oscillator input
T1OSI
RC2/CCP1
RC2
I/O
I/O
ST
ST
Digital I/O
Capture1 input/Compare1
output/PWM1 output
CCP1
RC3/SCK/SCL
RC3
34
35
45
46
44
45
57
58
I/O
I/O
ST
ST
Digital I/O
SCK
Synchronous serial clock
input/output for SPI mode
Synchronous serial clock
SCL
I/O
ST
2
input/output for I C mode
RC4/SDI/SDA
RC4
I/O
I
I/O
ST
ST
ST
Digital I/O
SPI data in
SDI
SDA
2
I C data I/O
RC5/SDO
RC5
36
31
47
42
46
37
59
50
I/O
O
ST
—
Digital I/O
SPI data out
SDO
RC6/TX/CK
RC6
TX
CK
I/O
O
I/O
ST
—
ST
Digital I/O
USART asynchronous transmit
USART synchronous clock
(See RX/DT)
RC7/RX/DT
32
43
38
51
RC7
RX
DT
I/O
I
I/O
ST
ST
ST
Digital I/O
USART asynchronous receive
USART synchronous data
(See TX/CK)
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 15
PIC18CXX8
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
PIC18C658 PIC18C858
TQFP PLCC TQFP PLCC
Pin
Type
Buffer
Type
Pin Name
Description
PORTD is a bi-directional I/O port. These
pins have TTL input buffers when external
memory is enabled.
RD0/PSP0
RD0
58
55
54
53
52
51
50
49
3
72
69
68
67
66
65
64
63
3
I/O
I/O
ST
TTL
Digital I/O
Parallel slave port data
PSP0
RD1/PSP1
RD1
67
66
65
64
63
62
61
83
82
81
80
79
78
77
I/O
I/O
ST
TTL
Digital I/O
Parallel slave port data
PSP1
RD2/PSP2
RD2
I/O
I/O
ST
TTL
Digital I/O
Parallel slave port data
PSP2
RD3/PSP3
RD3
I/O
I/O
ST
TTL
Digital I/O
Parallel slave port data
PSP3
RD4/PSP4
RD4
I/O
I/O
ST
TTL
Digital I/O
Parallel slave port data
PSP4
RD5/PSP5
RD5
I/O
I/O
ST
TTL
Digital I/O
Parallel slave port data
PSP5
RD6/PSP6
RD6
I/O
I/O
ST
TTL
Digital I/O
Parallel slave port data
PSP6
RD7/PSP7
RD7
I/O
I/O
ST
TTL
Digital I/O
Parallel slave port data
PSP7
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
DS30475A-page 16
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
PIC18C658
PIC18C858
TQFP PLCC TQFP PLCC
Description
PORTE is a bi-directional I/O port
RE0/RD
RE0
2
1
11
10
9
4
3
15
14
9
I/O
I
ST
TTL
Digital I/O
Read control for parallel slave port
(See WR and CS pins)
RD
RE1/WR
RE1
I/O
I
ST
TTL
Digital I/O
Write control for parallel slave port
(See CS and RD pins)
WR
RE2/CS
RE2
64
78
I/O
I
ST
TTL
Digital I/O
Chip select control for parallel slave
port (See RD and WR)
CS
RE3
RE4
RE5
RE6
63
62
61
60
59
8
7
6
5
4
77
76
75
74
73
8
7
6
5
4
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Digital I/O
Digital I/O
Digital I/O
Digital I/O
RE7/CCP2
RE7
I/O
I/O
ST
ST
Digital I/O
Capture2 input, Compare2 output,
PWM2 output
CCP2
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 17
PIC18CXX8
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
PIC18C658 PIC18C858
TQFP PLCC TQFP PLCC
Pin
Type
Buffer
Type
Pin Name
Description
PORTF is a bi-directional I/O port
RF0/AN5
RF0
18
17
28
27
24
23
36
35
I/O
I
ST
Analog
Digital I/O
Analog input 5
AN5
RF1/AN6/C2OUT
RF1
I/O
I
O
ST
Analog
ST
Digital I/O
Analog input 6
Comparator 2 output
AN6
C2OUT
RF2/AN7/C1OUT
RF2
16
26
18
30
I/O
I
O
ST
Analog
ST
Digital I/O
Analog input 7
Comparator 1 output
AN7
C1OUT
RF3/AN8
RF1
15
14
13
25
24
23
17
16
15
29
28
27
I/O
I
ST
Analog
Digital I/O
Analog input 8
AN8
RF4/AN9
RF1
I/O
I
ST
Analog
Digital I/O
Analog input 9
AN9
RF5/AN10/CVREF
RF1
I/O
I
O
ST
Analog
Analog
Digital I/O
Analog input 10
Comparator VREF output
AN10
CVREF
RF6/AN11
RF6
12
11
22
21
14
13
26
25
I/O
I
ST
Analog
Digital I/O
Analog input 11
AN11
RF7
I/O
ST
Digital I/O
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
DS30475A-page 18
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
PIC18C658
PIC18C858
TQFP PLCC TQFP PLCC
Description
PORTG is a bi-directional I/O port
RG0/CANTX1
RG0
3
4
12
13
5
6
16
17
I/O
O
ST
CAN Bus
Digital I/O
CAN bus output
CANTX1
RG1/CANTX2
RG1
I/O
O
ST
CAN Bus
Digital I/O
Complimentary CAN bus output
or CAN bus bit time clock
CANTX2
RG2/CANRX
RG2
5
14
7
18
I/O
I
ST
CAN Bus
Digital I/O
CAN bus input
CANRX
RG3
RG4
6
8
15
17
8
19
21
I/O
I/O
ST
ST
Digital I/O
Digital I/O
10
PORTH is a bi-directional I/O port.
Digital I/O
RH0
RH1
RH2
RH3
—
—
—
—
—
—
—
—
—
—
79
80
1
10
11
12
13
34
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Digital I/O
Digital I/O
2
Digital I/O
RH4/AN12
RH4
22
I/O
I
ST
Analog
Digital I/O
Analog input 12
AN12
RH5/AN13
RH5
—
—
—
—
—
—
21
20
19
33
32
31
I/O
I
ST
Analog
Digital I/O
Analog input 13
AN13
RH6/AN14
RH6
I/O
I
ST
Analog
Digital I/O
Analog input 14
AN14
RH7/AN15
RH7
I/O
I
ST
Analog
Digital I/O
Analog input 15
AN15
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 19
PIC18CXX8
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
PIC18C658 PIC18C858
TQFP PLCC TQFP PLCC
Pin
Type
Buffer
Type
Pin Name
Description
PORTJ is a bi-directional I/O port
RJ0
RJ0
—
—
—
—
62
—
76
—
RJ0
RJ1
RJ2
RJ3
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Digital I/O
Digital I/O
Digital I/O
RJ1
RJ1
—
—
—
—
61
—
75
—
RJ2
RJ2
—
—
—
—
60
—
74
—
RJ3
RJ3
—
—
—
—
59
—
73
—
Digital I/O
PORTK is a bi-directional I/O port
RK0
RK1
RK2
RK3
VSS
—
—
—
—
—
—
—
—
39
40
41
42
52
53
54
55
I/O
I/O
I/O
I/O
P
ST
ST
ST
ST
—
Digital I/O
Digital I/O
Digital I/O
Digital I/O
9, 25, 19, 36, 11, 31, 23, 44,
41, 56 53, 68 51, 70 65, 84
Ground reference for logic and I/O pins
VDD
10, 26, 2, 20, 12, 32, 2, 24,
38, 57 37, 49 48, 71 45, 61
P
—
Positive supply for logic and I/O pins
AVSS
AVDD
20
19
30
29
26
25
38
37
P
P
—
—
Ground reference for analog modules
Positive supply for analog modules
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
DS30475A-page 20
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 2-1: CRYSTAL/CERAMIC
2.0
OSCILLATOR
CONFIGURATIONS
RESONATOR OPERATION
(HS, XT OR LP
2.1
Oscillator Types
OSC CONFIGURATION)
(1)
The PIC18CXX8 can be operated in one of eight oscil-
lator modes, programmable by three configuration bits
(FOSC2, FOSC1, and FOSC0).
C1
C2
OSC1
To
internal
logic
(3)
RF
XTAL
1. LP
2. XT
3. HS
4. HS4
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
High Speed Crystal/Resonator with
PLL enabled
SLEEP
(2)
RS
(1)
PIC18CXX8
OSC2
Note 1: See Table 2-1 and Table 2-2 for recom-
5. RC
6. RCIO
External Resistor/Capacitor
External Resistor/Capacitor with I/O
pin enabled
mended values of C1 and C2.
2: A series resistor (RS) may be required
for AT strip cut crystals.
7. EC
External Clock
8. ECIO
External Clock with I/O pin enabled
3: RF varies with the crystal chosen.
2.2
Crystal Oscillator/Ceramic
Resonators
In XT, LP, HS or HS4 (PLL) oscillator modes, a crystal
or ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections. An external clock source may also
be connected to the OSC1 pin, as shown in Figure 2-3
and Figure 2-4.
The PIC18CXX8 oscillator design requires the use of a
parallel cut crystal.
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer’s
specifications.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 21
PIC18CXX8
TABLE 2-1:
CERAMIC RESONATORS
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 2-1).
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
Ranges Tested:
Mode
Freq
455 kHz
2.0 MHz
4.0 MHz
OSC1
OSC2
XT
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
4: Rs may be required in HS mode, as well as
XT mode, to avoid overdriving crystals with
low drive level specification.
HS
8.0 MHz
10 - 68 pF
10 - 22 pF
TBD
10 - 68 pF
10 - 22 pF
TBD
16.0 MHz
20.0 MHz
25.0 MHz
TBD
TBD
HS+PLL
4.0 MHz
8.0 MHz
10.0 MHz
TBD
10 - 68 pF
TBD
TBD
10 - 68 pF
TBD
These values are for design guidance only. See
notes on this page.
Resonators Used:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
0.3%
0.5%
0.5%
0.5%
0.5%
16.0 MHz Murata Erie CSA16.00MX
All resonators used did not have built-in capacitors.
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
Osc Type
LP
32.0 kHz
200 kHz
200 kHz
1.0 MHz
4.0 MHz
4.0 MHz
8.0 MHz
20.0 MHz
25.0 MHz
4.0 MHz
8.0 MHz
10.0 MHz
33 pF
15 pF
33 pF
15 pF
XT
HS
47-68 pF
15 pF
47-68 pF
15 pF
15 pF
15 pF
15 pF
15 pF
15-33 pF
15-33 pF
TBD
15-33 pF
15-33 pF
TBD
HS+PLL
15 pF
15 pF
15-33 pF
TBD
15-33 pF
TBD
These values are for design guidance only. See
notes on this page.
Crystals Used
32.0 kHz
200 kHz
1.0 MHz
4.0 MHz
8.0 MHz
20.0 MHz
Epson C-001R32.768K-A
STD XTL 200.000KHz
ECS ECS-10-13-1
± 20 PPM
± 20 PPM
± 50 PPM
± 50 PPM
± 30 PPM
± 30 PPM
ECS ECS-40-20-1
EPSON CA-301 8.000M-C
EPSON CA-301 20.000M-C
DS30475A-page 22
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
2.3
RC Oscillator
2.4
External Clock Input
For timing insensitive applications, the “RC” and
"RCIO" device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) val-
ues and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit due
to normal process parameter variation. Furthermore,
the difference in lead frame capacitance between
package types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 2-2 shows how the
R/C combination is connected.
The EC and ECIO oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscilla-
tor start-up time required after a Power-on Reset or
after a recovery from SLEEP mode.
In the EC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
oscillator mode.
FIGURE 2-3: EXTERNAL CLOCK INPUT
OPERATION
In the RC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
(EC OSC CONFIGURATION)
OSC1
OSC2
Clock from
ext. system
FIGURE 2-2: RC OSCILLATOR MODE
PIC18CXX8
FOSC/4
VDD
The ECIO oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-4 shows the pin connections
for the ECIO oscillator mode.
REXT
Internal
OSC1
clock
CEXT
PIC18CXX8
VSS
OSC2/CLKO/RA6
FOSC/4
or I/O
FIGURE 2-4: EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20pF
OSC1
Clock from
ext. system
The RCIO oscillator mode functions like the RC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
PIC18CXX8
I/O (OSC2)
RA6
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 23
PIC18CXX8
The PLL can only be enabled when the oscillator con-
figuration bits are programmed for HS mode. If they
are programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
2.5
HS4 (PLL)
A Phase Locked Loop circuit is provided as a pro-
grammable option for users that want to multiply the
frequency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
The PLL is one of the modes of the FOSC2:FOSC0
configuration bits. The oscillator mode is specified dur-
ing device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out referred to as TPLL.
FIGURE 2-5: PLL BLOCK DIAGRAM
FOSC2:FOSC0 = ‘110’
Phase
OSC2
Comparator
FIN
Loop
Filter
VCO
Crystal
Osc
SYSCLK
FOUT
Divide by 4
OSC1
DS30475A-page 24
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
2.6.1
SYSTEM CLOCK SWITCH BIT
2.6
Oscillator Switching Feature
The system clock source switching is performed under
software control. The system clock switch bit, SCS
(OSCCON register), controls the clock switching. When
the SCS bit is ’0’, the system clock source comes from
the main oscillator selected by the FOSC2:FOSC0 con-
figuration bits. When the SCS bit is set, the system clock
source will come from the Timer1 oscillator. The SCS bit
is cleared on all forms of RESET.
The PIC18CXX8 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low frequency clock source.
For the PIC18CXX8 devices, this alternate clock
source is the Timer1 oscillator. If a low frequency crys-
tal (32 kHz, for example) has been attached to the
Timer1 oscillator pins and the Timer1 oscillator has
been enabled, the device can switch to a low power
execution mode. Figure 2-6 shows a block diagram of
the system clock sources. The clock switching feature
is enabled by programming the Oscillator Switching
Enable (OSCSEN) bit in Configuration register
CONFIG1H to a ’0’. Clock switching is disabled in an
erased device. See Section 9 for further details of the
Timer1 oscillator. See Section 22.0 for Configuration
Register details.
Note: The Timer1 oscillator must be enabled to
switch the system clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 control register
(T1CON). If the Timer1 oscillator is not
enabled, any write to the SCS bit will be
ignored (SCS bit forced cleared) and the
main oscillator will continue to be the sys-
tem clock source.
FIGURE 2-6: DEVICE CLOCK SOURCES
PIC18CXX8
Main Oscillator
OSC2
Tosc/4
4 x PLL
SLEEP
TOSC
TT1P
TSCLK
OSC1
Timer 1 Oscillator
T1OSO
T1OSCEN
Clock
Source
Enable
Oscillator
T1OSI
Clock Source option
for other modules
Note: I/O pins have diode protection to VDD and VSS.
REGISTER 2-1:
OSCCON REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-1
SCS
—
—
—
—
—
—
—
bit 7
bit 0
bit 7-1
bit 0
Unimplemented: Read as '0'
SCS: System Clock Switch bit
when OSCSEN configuration bit = ’0’ and T1OSCEN bit is set:
1= Switch to Timer1 Oscillator/Clock pin
0= Use primary Oscillator/Clock input pin
when OSCSEN is clear or T1OSCEN is clear:
bit is forced clear
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 25
PIC18CXX8
2.6.2
OSCILLATOR TRANSITIONS
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
The PIC18CXX8 devices contain circuitry to prevent
"glitches" when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to.
This ensures that the new clock source is stable and
that its pulse width will not be less than the shortest
pulse width of the two clock sources.
If the main oscillator is configured for an external crys-
tal (HS, XT, LP), the transition will take place after an
oscillator start-up time (TOST) has occurred. A timing
diagram indicating the transition from the Timer1 oscil-
lator to the main oscillator for HS, XT and LP modes is
shown in Figure 2-8.
A timing diagram indicating the transition from the
main oscillator to the Timer1 oscillator is shown in
Figure 2-7. The Timer1 oscillator is assumed to be
running all the time. After the SCS bit is set, the pro-
cessor is frozen at the next occurring Q1 cycle. After
eight synchronization cycles are counted from the
Timer1 oscillator, operation resumes. No additional
delays are required after the synchronization cycles.
FIGURE 2-7: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1 Q2 Q3 Q4 Q1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
TT1P
1
2
3
4
5
6
7
8
T1OSI
OSC1
Tscs
TOSC
Internal
System
Clock
TDLY
SCS
(OSCCON<0>)
Program
Counter
PC
PC + 2
PC + 4
Note 1:
Delay on internal system clock is eight oscillator cycles for synchronization.
FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS,XT,LP)
Q1 Q2 Q3 Q4 Q1 Q2 Q3
Q3
Q4
Q1
TT1P
T1OSI
OSC1
1
2
3
4
5
6
7
8
TOST
TSCS
OSC2
TOSC
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter
PC
PC + 2
PC + 4
Note 1:
TOST = 1024TOSC (drawing not to scale).
DS30475A-page 26
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
If the main oscillator is configured for HS4 (PLL) mode,
an oscillator start-up time (TOST) plus an additional PLL
time-out (TPLL) will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
frequency. A timing diagram indicating the transition
from the Timer1 oscillator to the main oscillator for HS4
mode is shown in Figure 2-9.
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram indicat-
ing the transition from the Timer1 oscillator to the main
oscillator for RC, RCIO, EC and ECIO modes is shown
in Figure 2-10.
FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q4
Q1
T1OSI
OSC1
TOST
TPLL
OSC2
TSCS
TOSC
PLL Clock
Input
1
2
3
4
5
6
7
8
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter
PC
PC + 2
PC + 4
Note 1:
TOST = 1024TOSC (drawing not to scale).
FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3
Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
TT1P
T1OSI
OSC1
TOSC
6
1
4
5
7
8
2
3
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
TSCS
Program Counter
PC
PC + 2
PC + 4
Note 1:
RC oscillator mode assumed.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 27
PIC18CXX8
2.7
Effects of SLEEP Mode on the
On-chip Oscillator
2.8
Power-up Delays
Power up delays are controlled by two timers, so that
no external RESET circuitry is required for most appli-
cations. The delays ensure that the device is kept in
RESET until the device power supply and clock are sta-
ble. For additional information on RESET operation,
see Section 3.0 RESET.
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP will increase the current
consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset or through an interrupt.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of TPWRT (parameter
#33) on power-up only (POR and BOR). The second
timer is the Oscillator Start-up Timer (OST), intended to
keep the chip in RESET until the crystal oscillator is
stable.
With the PLL enabled (HS4 oscillator mode), the
time-out sequence following a Power-on Reset is differ-
ent from other oscillator modes. The time-out sequence
is as follows: the PWRT time-out is invoked after a POR
time delay has expired, then the Oscillator Start-up
Timer (OST) is invoked. However, this is still not a suf-
ficient amount of time to allow the PLL to lock at high
frequencies. The PWRT timer is used to provide an
additional time-out. This time is called TPLL (parameter
#7) to allow the PLL ample time to lock to the incoming
clock frequency.
TABLE 2-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin
OSC Mode
OSC2 Pin
RC
Floating, external resistor should pull high At logic low
RCIO
Floating, external resistor should pull high Configured as PORTA, bit 6
ECIO
Floating
Floating
Configured as PORTA, bit 6
At logic low
EC
LP, XT, and HS
Feedback inverter disabled, at quiescent
voltage level
Feedback inverter disabled, at quiescent
voltage level
Note: See Table 3-1 in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset.
DS30475A-page 28
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
state on Power-on Reset, MCLR, WDT Reset,
Brown-out Reset, MCLR Reset during SLEEP and by
the RESETinstruction.
3.0
RESET
The PIC18CXX8 differentiates between various kinds
of RESET:
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR are set or cleared differently in different
RESET situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
RESET. See Table 3-3 for a full description of the
RESET states of all registers.
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
d) Watchdog Timer (WDT) Reset (during normal
operation)
e) Programmable Brown-out Reset (PBOR)
f) RESETInstruction
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 3-1.
g) Stack Full Reset
h) Stack Underflow Reset
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
Most registers are unaffected by a RESET. Their status
is unknown on POR and unchanged by all other
RESETs. The other registers are forced to a “RESET”
A WDT Reset does not drive MCLR pin low.
FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Full/Underflow Reset
External Reset
Stack
Pointer
MCLR
SLEEP
WDT
Time-out
Reset
WDT
Module
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
BOREN
S
R
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
10-bit Ripple Counter
Q
OSC1
PWRT
On-chip
(1)
RC OSC
Enable PWRT
(2)
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 3-1 for time-out situations.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 29
PIC18CXX8
3.1
Power-on Reset (POR)
3.2
Power-up Timer (PWRT)
A Power-on Reset pulse is generated on-chip when a
VDD rise is detected. To take advantage of the POR cir-
cuitry, connect the MCLR pin directly (or through a
resistor) to VDD. This will eliminate external RC compo-
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for VDD is specified (param-
eter D004). For a slow rise time, see Figure 3-2.
The Power-up Timer provides a fixed nominal time-out
(parameter #33), only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in RESET as long as the PWRT is
active. The PWRT’s time delay allows VDD to rise to an
acceptable level. A configuration bit (PWRTEN in
CONFIG2L register) is provided to enable/disable the
PWRT.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. Brown-out Reset may be used to meet the
voltage start-up condition.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
3.3
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and stabi-
lized.
FIGURE 3-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
The OST time-out is invoked only for XT, LP, HS and
HS4 modes and only on Power-on Reset or wake-up
from SLEEP.
VDD
D
R
3.4
PLL Lock Time-out
R1
MCLR
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(TPLL) is typically 2 ms and follows the oscillator
start-up time-out (OST).
PIC18CXX8
C
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
3.5
Brown-out Reset (BOR)
2: R < 40 kΩ is recommended to make sure
that the voltage drop across R does not
violate the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin break-
down due to Electrostatic Discharge
A
configuration bit, BOREN, can disable (if
clear/programmed) or enable (if set) the Brown-out
Reset circuitry. If VDD falls below parameter D005 for
greater than parameter #35, the brown-out situation
resets the chip. A RESET may not occur if VDD falls
below parameter D005 for less than parameter #35.
The chip will remain in Brown-out Reset until VDD rises
above BVDD. The Power-up Timer will then be invoked
and will keep the chip in RESET an additional time
delay (parameter #33). If VDD drops below BVDD while
the Power-up Timer is running, the chip will go back
into a Brown-out Reset and the Power-up Timer will be
initialized. Once VDD rises above BVDD, the Power-up
Timer will execute the additional time delay.
(ESD) or Electrical Overstress (EOS).
DS30475A-page 30
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18CXX8 device operat-
ing in parallel.
3.6
Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired, then OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Table 3-2 shows the RESET conditions for some Spe-
cial Function Registers, while Table 3-3 shows the
RESET conditions for all registers.
TABLE 3-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2)
Wake-up from
SLEEP or
Oscillator
Configuration
Brown-out(2)
PWRTEN = 0
PWRTEN = 1
Oscillator Switch
HS with PLL enabled(1) 72 ms + 1024Tosc + 2 ms 1024Tosc + 2 ms 72 ms + 1024Tosc + 2 ms 1024Tosc + 2 ms
HS, XT, LP
EC
72 ms + 1024Tosc
72 ms
1024Tosc
72 ms + 1024Tosc
72 ms
1024Tosc
—
—
—
—
External RC
72 ms
72 ms
Note 1: 2 ms = Nominal time required for the 4X PLL to lock.
2: 72 ms is the nominal power-up timer delay.
REGISTER 3-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
IPEN
R/W-0
LWRT
U-0
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-1
POR
R/W-1
BOR
—
bit 7
bit 0
TABLE 3-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
Condition
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
0000h
0000h
00-1 1100
00-u uuuu
1
u
1
u
1
u
0
u
0
u
u
u
u
u
MCLR Reset during normal
operation
Software Reset during normal
operation
0000h
0000h
0000h
0u-0 uuuu
0u-u uu11
0u-u uu11
0
u
u
u
u
u
u
u
u
u
1
1
u
1
1
u
u
1
u
1
u
Stack Full Reset during normal
operation
Stack Underflow Reset during
normal operation
MCLR Reset during SLEEP
WDT Reset
0000h
0000h
PC + 2
0000h
00-u 10uu
0u-u 01uu
uu-u 00uu
0u-1 11u0
u
u
u
1
u
1
0
0
1
0
0
1
0
1
0
u
u
u
u
u
u
u
u
0
u
u
u
u
u
u
u
u
u
u
u
WDT Wake-up
Brown-out Reset
Interrupt wake-up from SLEEP
PC + 2(1) uu-u 00uu
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as '0'
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 31
PIC18CXX8
FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30475A-page 32
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD)
5V
1V
0V
VDD
MCLR
TDEADTIME
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
IINTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
TPLL
OST TIME-OUT
PLL TIME-OUT
INTERNAL RESET
TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 33
PIC18CXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Reset
WDT Reset
RESET Instruction
Stack Resets
Applicable
Devices
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
TOSU
658
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 1111
1100 0000
N/A
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 1111
1100 0000
N/A
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu uuuu(1)
uuuu uuuu(1)
N/A
TOSH
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
xxxx xxxx
N/A
---- 0000
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008hor 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR.
7: Available on PIC18C858 only.
DS30475A-page 34
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
Applicable
Devices
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
RESET Instruction
Stack Resets
FSR1H
658
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
---- 0000
xxxx xxxx
---- 0000
N/A
---- 0000
uuuu uuuu
---- 0000
N/A
---- uuuu
uuuu uuuu
---- uuuu
N/A
FSR1L
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
1111 1111
---- ---0
--00 0101
---- ---0
00-1 11q0
xxxx xxxx
xxxx xxxx
0-00 0000
xxxx xxxx
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
---- 0000
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
1111 1111
---- ---0
--00 0101
---- ---0
00-1 qquu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ---u
--uu uuuu
---- ---u
uu-u qquu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON(4, 6)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008hor 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR.
7: Available on PIC18C858 only.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 35
PIC18CXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
RESET Instruction
Stack Resets
Applicable
Devices
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
CVRCON
CMCON
TMR3H
TMR3L
T3CON
PSPCON
SPBRG
RCREG
TXREG
TXSTA
658
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
xxxx xxxx
xxxx xxxx
--00 0000
--00 0000
0--- -000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 ----
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 -01x
0000 000x
1111 1111
0000 0000
0000 0000
-1-- 1111
-0-- 0000
-0-- 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
--00 0000
--00 0000
0--- -000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 -01u
0000 000u
1111 1111
0000 0000
0000 0000
-1-- 1111
-0-- 0000
-0-- 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
u--- -uuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-- uuuu
-u-- uuuu(1)
-u-- uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu(1)
-uuu uuuu(1)
uuuu uuuu
-uuu uuuu
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
RCSTA
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008hor 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR.
7: Available on PIC18C858 only.
DS30475A-page 36
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
Applicable
Devices
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
RESET Instruction
Stack Resets
TRISJ(7)
TRISH(7)
TRISG
-
858
1111 1111
1111 1111
---1 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
-111 1111(5)
xxxx xxxx
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx(5)
xxxx xxxx
0000 xxxx
---x xxxx
x000 0000
--00 xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x0x 0000(5)
1111 1111
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
1000 ----
-0-- -000
0000 0000
0000 0000
1111 1111
1111 1111
---1 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
-111 1111(5)
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
0000 uuuu
---u uuuu
u000 0000
uuuu u000
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u0u 0000(5)
1111 1111
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
1000 ----
-0-- -000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu ----
-u-- -uuu
uuuu uuuu
uuuu uuuu
-
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
658
658
658
658
658
658
658
-
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA(5)
LATJ(7)
LATH(7)
LATG
-
658
658
658
658
658
658
658
-
LATF
LATE
LATD
LATC
LATB
LATA(5)
PORTJ(7)
PORTH(7)
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA(5)
TRISK
-
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
LATK
PORTK
TXERRCNT
RXERRCNT
COMSTAT
CIOCON
BRGCON3
BRGCON2
BRGCON1
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008hor 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR.
7: Available on PIC18C858 only.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 37
PIC18CXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
RESET Instruction
Stack Resets
Applicable
Devices
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
CANCON
CANSTAT
RXB0D7
RXB0D6
RXB0D5
RXB0D4
RXB0D3
RXB0D2
RXB0D1
RXB0D0
RXB0DLC
RXB0EIDL
RXB0EIDH
RXB0SIDL
RXB0SIDH
RXB0CON
RXB1D7
RXB1D6
RXB1D5
RXB1D4
RXB1D3
RXB1D2
RXB1D1
RXB1D0
RXB1DLC
RXB1EIDL
RXB1EIDH
RXB1SIDL
RXB1SIDH
RXB1CON
TXB0D7
658
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
xxxx xxx-
xxx- xxx-
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx xxxx
000- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x0xx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuu-
uuu- uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
000- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u0uu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuu-
uuu- uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuu- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
TXB0D6
TXB0D5
TXB0D4
TXB0D3
TXB0D2
TXB0D1
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008hor 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR.
7: Available on PIC18C858 only.
DS30475A-page 38
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
Applicable
Devices
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
RESET Instruction
Stack Resets
TXB0D0
658
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
xxxx xxxx
0x00 xxxx
xxxx xxxx
xxxx xxxx
xxx0 x0xx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0x00 xxxx
xxxx xxxx
xxxx xxxx
xxx0 x0xx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0x00 xxxx
xxxx xxxx
xxxx xxxx
xxx0 x0xx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
uuuu uuuu
0u00 uuuu
uuuu uuuu
uuuu uuuu
uuu0 u0uu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0u00 uuuu
uuuu uuuu
uuuu uuuu
uuu0 u0uu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0u00 uuuu
uuuu uuuu
uuuu uuuu
uuu0 u0uu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TXB0DLC
TXB0EIDL
TXB0EIDH
TXB0SIDL
TXB0SIDH
TXB0CON
TXB1D7
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
TXB1D6
TXB1D5
TXB1D4
TXB1D3
TXB1D2
TXB1D1
TXB1D0
TXB1DLC
TXB1EIDL
TXB1EIDH
TXB1SIDL
TXB1SIDH
TXB1CON
TXB2D7
TXB2D6
TXB2D5
TXB2D4
TXB2D3
TXB2D2
TXB2D1
TXB2D0
TXB2DLC
TXB2EIDL
TXB2EIDH
TXB2SIDL
TXB2SIDH
TXB2CON
RXM1EIDL
RXM1EIDH
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008hor 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR.
7: Available on PIC18C858 only.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 39
PIC18CXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
RESET Instruction
Stack Resets
Applicable
Devices
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
RXM1SIDL
RXM1SIDH
RXM0EIDL
RXM0EIDH
RXM0SIDL
RXM0SIDH
RXF5EIDL
RXF5EIDH
RXF5SIDL
RXF5SIDH
RXF4EIDL
RXF4EIDH
RXF4SIDL
RXF4SIDH
RXF3EIDL
RXF3EIDH
RXF3SIDL
RXF3SIDH
RXF2EIDL
RXF2EIDH
RXF2SIDL
RXF2SIDH
RXF1EIDL
RXF1EIDH
RXF1SIDL
RXF1SIDH
RXF0EIDL
RXF0EIDH
RXF0SIDL
RXF0SIDH
658
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
xxx- --xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- --xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
uuu- --uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- --uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuu- --uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- --uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
658
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008hor 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR.
7: Available on PIC18C858 only.
DS30475A-page 40
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR
4.0
MEMORY ORGANIZATION
There are two memory blocks in Enhanced MCU
devices. These memory blocks are:
PIC18C658/858
• Program Memory
• Data Memory
PC<20:0>
21
Each block has its own bus so that concurrent access
can occur.
Stack Level 1
•
•
•
Stack Level 31
4.1
Program Memory Organization
0000h
RESET Vector
The PIC18CXX8 devices have a 21-bit program
counter that is capable of addressing the 2 Mbyte
program memory space.
High Priority Interrupt Vector
Low Priority Interrupt Vector
0008h
0018h
The reset vector address is at 0000h and the interrupt
vector addresses are at 0008h and 0018h. Figure 4-1
shows the diagram for program memory map and stack
for the PIC18C658 and PIC18C858.
4.1.1
INTERNAL PROGRAM MEMORY
OPERATION
On-chip
Program Memory
All devices have 32 Kbytes of internal EPROM program
memory. This means that the PIC18CXX8 devices can
store up to 16K of single word instructions. Accessing
a location between the physically implemented mem-
ory and the 2 Mbyte address will cause a read of all '0's
(a NOPinstruction).
7FFFh
8000h
Read ’1’
1FFFFFh
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 41
PIC18CXX8
4.2.2
RETURN STACK POINTER (STKPTR)
4.2
Return Address Stack
The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-1 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At RESET, the stack
pointer value will be 0. The user may read and write the
stack pointer value. This feature can be used by a Real
Time Operating System for return stack maintenance.
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
PUSH, CALLor RCALLinstruction is executed, or an
interrupt is acknowledged. The PC value is pulled off
the stack on a RETURN, RETLWor a RETFIEinstruc-
tion. PCLATU and PCLATH are not affected by any of
the return instructions.
The stack operates as a 31 word by 21-bit stack mem-
ory and a 5-bit stack pointer, with the stack pointer ini-
tialized to 00000b after all RESETs. There is no RAM
associated with stack pointer 00000b. This is only a
RESET value. During a CALLtype instruction causing
a push onto the stack, the stack pointer is first incre-
mented and the RAM location pointed to by the stack
pointer is written with the contents of the PC. During a
RETURNtype instruction causing a pop from the stack,
the contents of the RAM location indicated by the
STKPTR is transferred to the PC and then the stack
pointer is decremented.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (stack over-
flow RESET enable) configuration bit. Refer to Section
18 for a description of the device configuration bits. If
STVREN is set (default) the 31st push will push the
(PC + 2) value onto the stack, set the STKFUL bit, and
reset the device. The STKFUL bit will remain set and
the stack pointer will be set to 0.
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and
the data on the top of the stack is readable and writable
through SFR registers. Status bits indicate if the stack
pointer is at or beyond the 31 levels provided.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31.
The 32nd push will overwrite the 31st push (and so on),
while STKPTR remains at 31.
4.2.1
TOP-OF-STACK ACCESS
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at 0. The STKUNF bit will remain set
until cleared in software or a POR occurs.
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL allow
access to the contents of the stack location indicated
by the STKPTR register. This allows users to imple-
ment a software stack if necessary. After a CALL,
RCALLor interrupt, the software can read the pushed
value by reading the TOSU, TOSH and TOSL registers.
These values can be placed on a user defined software
stack. At return time, the software can replace the
TOSU, TOSH and TOSL and do a return.
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the RESET vector, where the
stack conditions can be verified and appro-
priate actions can be taken.
The user should disable the global interrupt enable bits
during this time to prevent inadvertent stack opera-
tions.
DS30475A-page 42
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
REGISTER 4-1:
STKPTR - STACK POINTER REGISTER
R/C-0
R/C-0
U-0
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
STKFUL
STKUNF
—
bit 7
bit 0
bit 7
bit 6
bit 5
STKFUL: Stack Full Flag bit
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit
1= Stack underflow occurred
0= Stack underflow did not occur
Unimplemented: Read as '0'
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note: Bit 7 and bit 6 can only be cleared in user software or by a POR.
Legend
R = Readable bit
- n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared C = Clearable bit
’1’ = Bit is set
FIGURE 4-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
11111
11110
11101
STKPTR<4:0>
00010
TOSU
0x00
TOSH
0x1A
TOSL
0x34
00011
0x001A34 00010
0x000D58 00001
0x000000 00000(1)
Top-of-Stack
Note 1: No RAM associated with this address; always maintained ‘0’s.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 43
PIC18CXX8
4.2.3
PUSH AND POP INSTRUCTIONS
4.3
Fast Register Stack
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack without disturbing normal program execu-
tion is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the stack pointer and load the cur-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place a return address on the
stack.
A “fast return” option is available for interrupts and
calls. A fast register stack is provided for the STATUS,
WREG and BSR registers and is only one layer in
depth. The stack is not readable or writable and is
loaded with the current value of the corresponding reg-
ister when the processor vectors for an interrupt. The
values in the fast register stack are then loaded back
into the working registers if the fast returninstruc-
tion is used to return from the interrupt.
The POPinstruction discards the current TOS by decre-
menting the stack pointer. The previous value pushed
onto the stack then becomes the TOS value.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority inter-
rupt will be overwritten.
4.2.4
STACK FULL/UNDERFLOW RESETS
These RESETs are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabled, a full or underflow condition will set the appro-
priate STKFUL or STKUNF bit, but not cause a device
RESET. When the STVREN bit is enabled, a full or
underflow will set the appropriate STKFUL or STKUNF
bit and then cause a device RESET. The STKFUL or
STKUNF bits are only cleared by the user software or
a POR.
If high priority interrupts are not disabled during low pri-
ority interrupts, users must save the key registers in
software during a low priority interrupt.
If no interrupts are used, the fast register stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the fast register
stack for a subroutine call, a fast call instruction
must be executed.
Example 4-1 shows a source code example that uses
the fast register stack.
EXAMPLE 4-1: FAST REGISTER STACK
CODE EXAMPLE
CALL SUB1, FAST
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
•
•
SUB1
•
•
•
RETURN FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
DS30475A-page 44
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the pro-
gram counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (See Section 4.8.1).
4.4
PCL, PCLATH and PCLATU
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable. Updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits and is not directly
readable or writable. Updates to the PCU register may
be performed through the PCLATU register.
4.5
Clocking Scheme/Instruction Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-3.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSb of PCL is fixed to a value of ’0’.
The PC increments by 2 to address sequential instruc-
tions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
FIGURE 4-3: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
phase
clock
Q4
PC
PC
PC+2
PC+4
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-2)
Fetch INST (PC+2)
Execute INST (PC)
Fetch INST (PC+4)
Execute INST (PC+2)
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 45
PIC18CXX8
4.6
Instruction Flow/Pipelining
4.7
Instructions in Program Memory
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
two cycles are required to complete the instruction
(Example 4-2).
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = ’0’). Figure 4-1 shows an
example of how instruction words are stored in the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ’0’ (See Section 4.4).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
The CALLand GOTOinstructions have an absolute pro-
gram memory address embedded into the instruction.
Since instructions are always stored on word bound-
aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 4-1 shows how the
instruction “GOTO 000006h” is encoded in the program
memory. Program branch instructions that encode a rel-
ative address offset operate in the same manner. The
offset value stored in a branch instruction represents the
number of single word instructions by which the PC will
be offset. Section 23.0 provides further details of the
instruction set.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
TABLE 4-1:
INSTRUCTIONS IN PROGRAM MEMORY
Opcode
Instruction
Memory
Address
—
000007h
000008h
000009h
00000Ah
00000Bh
00000Ch
00000Dh
00000Eh
00000Fh
000010h
000011h
000012h
MOVLW 055h
0E55h
55h
0Eh
03h
EFh
00h
F0h
23h
C1h
56h
F4h
GOTO 000006h
EF03h, F000h
MOVFF 123h, 456h
C123h, F456h
—
DS30475A-page 46
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
4.7.1
TWO WORD INSTRUCTIONS
4.8.1
COMPUTED GOTO
The PIC18CXX8 devices have 4 two word instructions:
MOVFF, CALL, GOTOand LFSR. The second word of
these instructions has the 4 MSB’s set to 1’s and is a
special kind of NOPinstruction. The lower 12 bits of the
second word contain data to be used by the instruction.
If the first word of the instruction is executed, the data
in the second word is accessed. If the second word of
the instruction is executed by itself (first word was
skipped), it will execute as a NOP. This action is neces-
sary when the two word instruction is preceded by a
conditional instruction that changes the PC. A program
example that demonstrates this concept is shown in
Example 4-3. Refer to Section 19.0 for further details of
the instruction set.
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL).
A lookup table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before exe-
cuting a call to that table. The first instruction of the called
routine is the ADDWF PCLinstruction. The next instruc-
tion executed will be one of the RETLW 0xnn instruc-
tions that returns the value 0xnnto the calling function.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
4.8
Lookup Tables
Warning: The LSb of PCL is fixed to a value of ‘0’.
Hence, computed GOTO to an odd
address is not possible.
Lookup tables are implemented two ways. These are:
• Computed GOTO
• Table Reads
4.8.2
TABLE READS/TABLE WRITES
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Lookup table data may be stored as 2 bytes per pro-
gram word by using table reads and writes. The table
pointer (TBLPTR) specifies the byte address and the
table latch (TABLAT) contains the data that is read
from, or written to, program memory. Data is trans-
ferred to/from program memory one byte at a time.
A description of the Table Read/Table Write operation
is shown in Section 5.0.
EXAMPLE 4-3: TWO WORD INSTRUCTIONS
Object Code
CASE 1:
Source Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
TSTFSZ
MOVFF
REG1
; is RAM location 0?
REG1, REG2 ; No, execute 2-word instruction
; 2nd operand holds address of REG2
REG3
ADDWF
; continue code
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
TSTFSZ
MOVFF
REG1
; is RAM location 0?
REG1, REG2 ; Yes
; 2nd operand becomes NOP
REG3 ; continue code
ADDWF
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 47
PIC18CXX8
4.9.1
GENERAL PURPOSE REGISTER FILE
4.9
Data Memory Organization
The register file can be accessed either directly or indi-
rectly. Indirect addressing operates through the File
Select Registers (FSR). The operation of indirect
addressing is shown in Section 4.12.
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 4-4
shows the data memory organization for the
PIC18CXX8 devices.
Enhanced MCU devices may have banked memory in
the GPR area. GPR’s are not initialized by a Power-on
Reset and are unchanged on all other RESETS.
The data memory map is divided into as many as 16
banks that contain 256 bytes each. The lower 4 bits of
the Bank Select Register (BSR<3:0>) select which
bank will be accessed. The upper 4 bits for the BSR are
not implemented.
Data RAM is available for use as GPR registers by all
instructions. Bank 15 (0xF00 to 0xFFF) contains
SFR’s. All other banks of data memory contain GPR
registers starting with bank 0.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFR’s are used for control and status of the controller
and peripheral functions, while GPR’s are used for data
storage and scratch pad operations in the user’s appli-
cation. The SFR’s start at the last location of Bank 15
(0xFFF) and grow downwards. GPR’s start at the first
location of Bank 0 and grow upwards. Any read of an
unimplemented location will read as ’0’s.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFR’s) are registers
used by the CPU and Peripheral Modules for control-
ling the desired operation of the device. These regis-
ters are implemented as static RAM. A list of these
registers is given in Table 4-2.
The SFR’s can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of
the File Select Register (FSR). Each FSR holds a
12-bit address value that can be used to access any
location in the Data Memory map without banking.
The SFR’s are typically distributed among the peripher-
als whose functions they control.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing or by the use of the MOVFFinstruction. The
MOVFF instruction is a two word/two cycle instruction
that moves a value from one register to another.
The unused SFR locations will be unimplemented and
read as '0's. See Table 4-2 for addresses for the SFR’s.
To ensure that commonly used registers (SFR’s and
select GPR’s) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10 pro-
vides a detailed description of the Access RAM.
DS30475A-page 48
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 4-4: DATA MEMORY MAP FOR PIC18C658/858
BSR<3:0>
= 0000b
Data Memory Map
000h
05Fh
060h
0FFh
00h
Access GPR’s
GPR’s
Bank 0
FFh
00h
100h
= 0001b
= 0010b
GPR’s
GPR’s
Bank 1
Bank 2
Bank 3
1FFh
200h
FFh
00h
2FFh
300h
FFh
00h
= 0011b
= 0100b
= 0101b
GPR’s
FFh
3FFh
400h
Access Bank
00h
Bank 4
Bank 5
GPR’s
GPR’s
4FFh
500h
Access Bank low
5Fh
00h
FFh
(GPR’s)
5FFh
600h
60h
Access Bank high
FFh
(SFR’s)
= 0110b
= 1110b
When a = 0,
Bank 6
to
Bank 14
Unused
Read ’00h’
the BSR is ignored and the
Access Bank is used.
The first 96 bytes are Gen-
eral Purpose RAM (from
Bank 0).
EFFh
F00h
F5Fh
F60h
FFFh
The next 160 bytes are
SpecialFunctionRegisters
(from Bank 15).
00h
FFh
SFR’s
= 1111b
Bank 15
Access SFR’s
When a = 1,
the BSR is used to specify
the RAM location that the
instruction uses.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 49
PIC18CXX8
TABLE 4-2:
Address
SPECIAL FUNCTION REGISTER MAP
Name
Address
Name
Address
Name
Address
Name
FFFh TOSU
FDFh INDF2(2)
FBFh CCPR1H
F9Fh IPR1
FFEh TOSH
FDEh POSTINC2(2)
FDDh POSTDEC2(2)
FDCh PREINC2(2)
FDBh PLUSW2(2)
FDAh FSR2H
FBEh CCPR1L
FBDh CCP1CON
FBCh CCPR2H
FBBh CCPR2L
FBAh CCP2CON
F9Eh PIR1
F9Dh PIE1
F9Ch
FFDh TOSL
FFCh STKPTR
FFBh PCLATU
FFAh PCLATH
FF9h PCL
—
—
F9Bh
F9Ah TRISJ(5)
F99h TRISH(5)
F98h TRISG
F97h TRISF
F96h TRISE
F95h TRISD
F94h TRISC
F93h TRISB
F92h TRISA
F91h LATJ(5)
F90h LATH(5)
F8Fh LATG
FD9h FSR2L
FB9h
FB8h
FB7h
FB6h
—
—
—
—
FF8h TBLPTRU
FF7h TBLPTRH
FF6h TBLPTRL
FF5h TABLAT
FF4h PRODH
FF3h PRODL
FD8h STATUS
FD7h TMR0H
FD6h TMR0L
FD5h T0CON
FB5h CVRCON
FB4h CMCON
FB3h TMR3H
FB2h TMR3L
FB1h T3CON
FB0h PSPCON
FAFh SPBRG
FAEh RCREG
FADh TXREG
FACh TXSTA
FABh RCSTA
FD4h
—
FD3h OSCCON
FD2h LVDCON
FD1h WDTCON
FD0h RCON
FF2h INTCON
FF1h INTCON2
FF0h INTCON3
FEFh INDF0(2)
FEEh POSTINC0(2)
FEDh POSTDEC0(2)
FECh PREINC0(2)
FEBh PLUSW0(2)
FEAh FSR0H
FCFh TMR1H
FCEh TMR1L
FCDh T1CON
FCCh TMR2
F8Eh LATF
F8Dh LATE
F8Ch LATD
F8Bh LATC
FCBh PR2
FCAh T2CON
FC9h SSPBUF
FC8h SSPADD
FC7h SSPSTAT
FC6h SSPCON1
FC5h SSPCON2
FC4h ADRESH
FC3h ADRESL
FC2h ADCON0
FC1h ADCON1
FC0h ADCON2
FAAh
—
—
—
—
—
F8Ah LATB
FE9h FSR0L
FA9h
F89h LATA
FE8h WREG
FA8h
F88h PORTJ(5)
F87h PORTH(5)
F86h PORTG
F85h PORTF
F84h PORTE
F83h PORTD
F82h PORTC
F81h PORTB
F80h PORTA
FE7h INDF1(2)
FE6h POSTINC1(2)
FE5h POSTDEC1(2)
FE4h PREINC1(2)
FE3h PLUSW1(2)
FE2h FSR1H
FA7h
FA6h
FA5h IPR3
FA4h PIR3
FA3h PIE3
FA2h IPR2
FA1h PIR2
FA0h PIE2
FE1h FSR1L
FE0h BSR
Note 1: Unimplemented registers are read as ’0’.
2: This is not a physical register.
3: Contents of register is dependent on WIN2:WIN0 bits in CANCON register.
4: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the CANSTAT register due to the Microchip Header file requirement.
5: Available on PIC18C858 only.
DS30475A-page 50
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Address
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
Name
TRISK(5)
Address
F5Fh
F5Eh
F5Dh
F5Ch
F5Bh
F5Ah
F59h
F58h
F57h
F56h
F55h
F54h
F53h
F52h
F51h
F50h
F4Fh
F4Eh
F4Dh
F4Ch
F4Bh
F4Ah
F49h
F48h
F47h
F46h
F45h
F44h
F43h
F42h
F41h
F40h
Name
Address
F3Fh
F3Eh
F3Dh
F3Ch
F3Bh
F3Ah
F39h
F38h
F37h
F36h
F35h
F34h
F33h
F32h
F31h
F30h
F2Fh
F2Eh
F2Dh
F2Ch
F2Bh
F2Ah
F29h
F28h
F27h
F26h
F25h
F24h
F23h
F22h
F21h
F20h
Name
Address
F1Fh
F1Eh
F1Dh
F1Ch
F1Bh
F1Ah
F19h
F18h
F17h
F16h
F15h
F14h
F13h
F12h
F11h
F10h
F0Fh
F0Eh
F0Dh
F0Ch
F0Bh
F0Ah
F09h
F08h
F07h
F06h
F05h
F04h
F03h
F02h
F01h
F00h
Name
—
CANSTATRO0(4)
RXB1D7
—
CANSTATRO2(4)
TXB1D7
RXM1EID0
RXM1EID8
RXM1SIDL
RXM1SIDH
RXM0EID0
RXM0EID8
RXM0SIDL
RXM0SIDH
RXF5EID0
RXF5EID8
RXF5SIDL
RXF5SIDH
RXF4EID0
RXF4EID8
RXF4SIDL
RXF4SIDH
RXF3EID0
RXF3EID8
RXF3SIDL
RXF3SIDH
RXF2EID0
RXF2EID8
RXF2SIDL
RXF2SIDH
RXF1EID0
RXF1EID8
RXF1SIDL
RXF1SIDH
RXF0EIDL
RXF0EIDH
RXF0SIDL
RXF0SIDH
LATK(5)
PORTK(5)
—
RXB1D6
TXB1D6
—
RXB1D5
TXB1D5
—
RXB1D4
TXB1D4
—
RXB1D3
TXB1D3
—
RXB1D2
TXB1D2
—
RXB1D1
TXB1D1
TXERRCNT
RXERRCNT
COMSTAT
CIOCON
BRGCON3
BRGCON2
BRGCON1
CANCON
CANSTAT
RXB0D7(3)
RXB0D6(3)
RXB0D5(3)
RXB0D4(3)
RXB0D3(3)
RXB0D2(3)
RXB0D1(3)
RXB0D0(3)
RXB0DLC(3)
RXB0EIDL(3)
RXB0EIDH(3)
RXB0SIDL(3)
RXB0SIDH(3)
RXB0CON(3)
RXB1D0
TXB1D0
RXB1DLC
RXB1EIDL
RXB1EIDH
RXB1SIDL
RXB1SIDH
RXB1CON
—
TXB1DLC
TXB1EIDL
TXB1EIDH
TXB1SIDL
TXB1SIDH
TXB1CON
—
CANSTATRO1(4)
CANSTATRO3(4)
TXB0D7
TXB2D7
TXB0D6
TXB2D6
TXB0D5
TXB2D5
TXB0D4
TXB2D4
TXB0D3
TXB2D3
TXB0D2
TXB2D2
TXB0D1
TXB2D1
TXB0D0
TXB2D0
TXB0DLC
TXB0EIDL
TXB0EIDH
TXB0SIDL
TXB0SIDH
TXB0CON
TXB2DLC
TXB2EIDL
TXB2EIDH
TXB2SIDL
TXB2SIDH
TXB2CON
Note: Shaded registers are available in Bank 15, while the rest are in Access Bank low.
Note 1: Unimplemented registers are read as ’0’.
2: This is not a physical register.
3: Contents of register is dependent on WIN2:WIN0 bits in CANCON register.
4: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the CANSTAT register due to the Microchip Header file requirement.
5: Available on PIC18C858 only.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 51
PIC18CXX8
TABLE 4-3:
Filename
REGISTER FILE SUMMARY
Value on
POR,
BOR
Value on
all other
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESETS(3)
TOSU
Top-of-Stack upper Byte (TOS<20:16>)
---0 0000 ---0 0000
—
—
—
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000 0000 0000
0000 0000 0000 0000
00-0 0000 00-0 0000
TOSL
STKPTR
STKFUL
STKUNF
Return Stack Pointer
—
PCLATU
bit 21(3)
Holding Register for PC<20:16>
--00 0000 --00 0000
—
—
PCLATH
PCL
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
0000 0000 0000 0000
0000 0000 0000 0000
---0 0000 ---0 0000
TBLPTRU
bit 21(2)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
—
—
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 000x 0000 000u
1111 1111 1111 1111
1100 0000 1100 0000
Product Register High Byte
Product Register Low Byte
INTCON
INTCON2
INTCON3
INDF0
GIE/GIEH
RBPU
PEIE/GIEL
INTEDG0
INT1IP
TMR0IE
INTEDG1
INT3IE
INT0IE
INTEDG2
INT2IE
RBIE
INTEDG3
INT1IE
TMR0IF
TMR0IP
INT3IF
INT0IF
INT3IP
INT2IF
RBIF
RBIP
INT2IP
INT1IF
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register)
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value
of FSR0 offset by WREG
FSR0H
Indirect Data Memory Address Pointer 0 High
---- 0000 ---- 0000
—
—
—
—
FSR0L
WREG
INDF1
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Working Register
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register)
POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register)
PREINC1
PLUSW1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - value
of FSR1 offset by WREG
FSR1H
Indirect Data Memory Address Pointer 1 High
---- 0000 ---- 0000
—
—
—
—
FSR1L
BSR
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx uuuu uuuu
---- 0000 ---- 0000
Bank Select Register
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
—
—
—
—
Legend:
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.
4: These registers are reserved on PIC18C658.
DS30475A-page 52
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Value on
POR,
BOR
Value on
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS(3)
INDF2
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)
POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register)
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value
of FSR2 offset by WREG
FSR2H
Indirect Data Memory Address Pointer 2 High
---- 0000 ---- 0000
—
—
—
—
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
STATUS
N
OV
Z
DC
C
—
—
—
TMR0H
TMR0L
Timer0 register high byte
Timer0 register low byte
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
---- ---0 ---- ---0
T0CON
OSCCON
TMR0ON
—
T08BIT
—
T0CS
—
T0SE
—
T0PS3
—
T0PS2
—
T0PS1
—
T0PS0
SCS
LVDCON
WDTCON
RCON
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
--00 0101 --00 0101
---- ---0 ---- ---0
00-1 11qq 00-q qquu
—
—
SWDTEN
BOR
—
—
—
—
—
—
—
—
IPEN
LWRT
RI
TO
PD
POR
TMR1H
TMR1L
T1CON
Timer1 Register High Byte
Timer1 Register Low Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
T1CKPS1
TOUTPS2
T1CKPS0
TOUTPS1
T1OSCEN
TOUTPS0
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
TMR1ON 0-00 0000 u-uu uuuu
—
TMR2
PR2
Timer2 Register
0000 0000 0000 0000
1111 1111 1111 1111
Timer2 Period Register
T2CON
TOUTPS3
T2CKPS0 -000 0000 -000 0000
—
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
SSP Receive Buffer/Transmit Register
SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode.
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
SMP
WCOL
GCEN
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
SSPOV
ACKSTAT
SSPEN
ACKDT
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
SEN
ACKEN
A/D Result Register High Byte
A/D Result Register Low Byte
CHS3
CHS2
CHS1
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADON
PCFG0
ADCS0
—
—
—
—
ADCON1
VCFG1
VCFG0
PCFG3
-000 0000 -000 0000
0--- -000 0--- -000
—
ADCON2
Legend:
ADFM
ADCS1
—
—
—
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.
4: These registers are reserved on PIC18C658.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 53
PIC18CXX8
Value on
POR,
BOR
Value on
all other
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESETS(3)
CCPR1H
CCPR1L
CCP1CON
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
DC1B1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
DC1B0
DC2B0
CCPM3
CCPM3
CCP1M2
CCP2M2
CCP1M1
CCP2M1
CCP1M0
CCP2M0
—
—
CCPR2H
CCPR2L
CCP2CON
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
DC2B1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
—
—
VRCON
CMCON
TMR3H
TMR3L
VREN
C2OUT
VROEN
C1OUT
VRR
VRSS
C1INV
VR3
CIS
VR2
CM2
VR1
CM1
VR0
CM0
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
C2INV
Timer3 Register High Byte
Timer3 Register Low Byte
T3CON
PSPCON
RD16
IBF
T3CCP2
OBF
T3CKPS1
IBOV
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON 0000 0000 uuuu uuuu
PSPMODE
0000 ---- 0000 ----
—
—
—
—
SPBRG
RCREG
TXREG
TXSTA
USART Baud Rate Generator
USART Receive Register
USART Transmit Register
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010 0000 -010
—
RCSTA
IPR3
PIR3
PIE3
SPEN
IRXIP
IRXIF
IRXIE
RX9
SREN
ERRIP
ERRIF
ERRIE
CREN
TXB2IP
TXB2IF
TXB2IE
ADEN
FERR
TXB0IP
TXB0IF
TXB0IE
LVDIP
OERR
RXB1IP
RXB1IF
RXB1IE
TMR3IP
RX9D
0000 000x 0000 000x
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
-1-- 1111 -1-- 1111
WAKIP
WAKIF
WAKIE
CMIP
TXB1IP
TXB1IF
TXB1IE
BCLIP
RXB0IP
RXB0IF
RXB0IE
CCP2IP
IPR2
—
—
—
—
—
—
PIR2
PIE2
CMIF
CMIE
BCLIF
BCLIE
LVDIF
LVDIE
TMR3IF
TMR3IE
CCP2IF
CCP2IE
-0-- 0000 -0-- 0000
-0-- 0000 -0-- 0000
—
—
—
IPR1
PSPIP
PSPIF
PSPIE
ADIP
ADIF
ADIE
RCIP
RCIF
RCIE
TXIP
TXIF
TXIE
SSPIP
SSPIF
SSPIE
CCP1IP
CCP1IF
CCP1IE
TMR2IP
TMR2IF
TMR2IE
TMR1IP
TMR1IF
TMR1IE
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
---1 1111 ---1 1111
PIR1
PIE1
TRISJ(4)
TRISH(4)
TRISG
Data Direction Control Register for PORTJ
Data Direction Control Register for PORTH
Data Direction Control Register for PORTG
—
—
—
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
Legend:
Data Direction Control Register for PORTF
Data Direction Control Register for PORTE
Data Direction Control Register for PORTD
Data Direction Control Register for PORTC
Data Direction Control Register for PORTB
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
--11 1111 --11 1111
Bit 6(1)
Data Direction Control Register for PORTA
—
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.
4: These registers are reserved on PIC18C658.
DS30475A-page 54
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Value on
POR,
BOR
Value on
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS(3)
LATJ(4)
LATH(4)
LATG
Read PORTJ Data Latch, Write PORTJ Data Latch
Read PORTH Data Latch, Write PORTH Data Latch
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
Read PORTG Data Latch, Write PORTG Data Latch
—
—
—
LATF
LATE
LATD
LATC
LATB
LATA
Read PORTF Data Latch, Write PORTF Data Latch
Read PORTE Data Latch, Write PORTE Data Latch
Read PORTD Data Latch, Write PORTD Data Latch
Read PORTC Data Latch, Write PORTC Data Latch
Read PORTB Data Latch, Write PORTB Data Latch
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
Bit 6(1)
Read PORTA Data Latch, Write PORTA Data Latch
—
PORTJ(4)
PORTH(4)
PORTG
Read PORTJ pins, Write PORTJ Data Latch
Read PORTH pins, Write PORTH Data Latch
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---x xxxx uuuu uuuu
Read PORTG pins, Write PORTG Data Latch
—
—
—
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
Read PORTF pins, Write PORTF Data Latch
Read PORTE pins, Write PORTE Data Latch
Read PORTD pins, Write PORTD Data Latch
Read PORTC pins, Write PORTC Data Latch
Read PORTB pins, Write PORTB Data Latch
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
—
Bit 6(1)
Read PORTA pins, Write PORTA Data Latch
TRISK(4)
Data Direction Control Register for PORTK
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1000 ---- 1000 ----
-0-- -000 -0-- -000
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxx- uuuu uuu-
LATK(4)
Read PORTK Data Latch, Write PORTK Data Latch
Read PORTK pins, Write PORTK Data Latch
PORTK(4)
TXERRCNT
RXERRCNT
COMSTAT
CIOCON
TEC7
REC7
TEC6
REC6
TEC5
REC5
TEC4
REC4
TEC3
REC3
RXBP
TEC2
REC2
TEC1
REC1
TEC0
REC0
RXB0OVFL RXB1OVFL
TXBO
TXBP
TXWARN
RXWARN
EWARN
TX1SRC
TX1EN
WAKFIL
SAM
ENDRHI
CANCAP
—
—
—
—
SEG2PH2
SEG2PH1
SEG2PH0
—
—
—
—
BRGCON3
BRGCON2
BRGCON1
CANCON
SEG2PHTS
SEG1PH2
SEG1PH1
SEG1PH0
PRSEG2
BRP2
PRSEG1
BRP1
PRSEG0
BRP0
SJW1
SJW0
BRP5
BRP4
ABAT
BRP3
WIN2
REQOP2
REQOP1
REQOP0
OPMODE0
WIN1
WIN0
—
—
CANSTAT
OPMODE2 OPMODE1
ICODE2
ICODE1
ICOED0
xxx- xxx- uuu- uuu-
—
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.
4: These registers are reserved on PIC18C658.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 55
PIC18CXX8
Value on
POR,
BOR
Value on
all other
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESETS(3)
RXB0D77
RXB0D67
RXB0D57
RXB0D47
RXB0D37
RXB0D27
RXB0D17
RXB0D07
RXB0D76
RXB0D66
RXB0D56
RXB0D46
RXB0D36
RXB0D26
RXB0D16
RXB0D06
RXB0D75
RXB0D65
RXB0D55
RXB0D45
RXB0D35
RXB0D25
RXB0D15
RXB0D05
RXB0D74
RXB0D64
RXB0D54
RXB0D44
RXB0D34
RXB0D24
RXB0D14
RXB0D04
RXB0D73
RXB0D63
RXB0D53
RXB0D43
RXB0D33
RXB0D23
RXB0D13
RXB0D03
RXB0D72
RXB0D62
RXB0D52
RXB0D42
RXB0D32
RXB0D22
RXB0D12
RXB0D02
RXB0D71
RXB0D61
RXB0D51
RXB0D41
RXB0D31
RXB0D21
RXB0D11
RXB0D0?
RXB0D70
RXB0D60
RXB0D50
RXB0D40
RXB0D30
RXB0D20
RXB0D10
RXB0D00
RXB0D7
RXB0D6
RXB0D5
RXB0D4
RXB0D3
RXB0D2
RXB0D1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RXB0D0
xxxx xxxx uuuu uuuu
0xxx xxxx 0uuu uuuu
RXB0DLC
RXRTR
EID6
RESB1
EID5
RESB0
EID4
DLC3
EID3
DLC2
EID2
DLC1
EID1
DLC0
EID0
—
EID7
RXB0EIDL
RXB0EIDH
RXB0SIDL
RXB0SIDH
RXB0CON
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx x-xx uuuu u-uu
xxxx xxxx uuuu uuuu
000- 0000 000- 0000
EID15
SID2
EID14
SID1
EID13
SID0
EID12
SRR
SID7
—
EID11
EXID
SID6
EID10
—
EID9
EID17
SID4
EID8
EID16
SID3
SID10
RXFUL
SID9
SID8
SID5
RXM1
RXM0
RXRTRRO RXB0DBEN
JTOFF
FILHIT0
CANSTAT
OPMODE2 OPMODE1
OPMODE0
RXB1D75
RXB1D65
RXB1D55
RXB1D45
RXB1D35
RXB1D25
RXB1D15
RXB1D05
ICODE2
RXB1D73
RXB1D63
RXB1D53
RXB1D43
RXB1D33
RXB1D23
RXB1D13
RXB1D03
ICODE1
RXB1D72
RXB1D62
RXB1D52
RXB1D42
RXB1D32
RXB1D22
RXB1D12
RXB1D02
ICODE0
RXB1D71
RXB1D61
RXB1D51
RXB1D41
RXB1D31
RXB1D21
RXB1D11
RXB1D01
xxx- xxx- uuu- uuu-
—
—
RXB1D77
RXB1D67
RXB1D57
RXB1D47
RXB1D37
RXB1D27
RXB1D17
RXB1D07
RXB1D76
RXB1D66
RXB1D56
RXB1D46
RXB1D36
RXB1D26
RXB1D16
RXB1D06
RXB1D74
RXB1D70
RXB1D7
RXB1D6
RXB1D5
RXB1D4
RXB1D3
RXB1D2
RXB1D1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RXB1D64
RXB1D54
RXB1D44
RXB1D34
RXB1D24
RXB1D14
RXB1D04
RXB1D60
RXB1D50
RXB1D40
RXB1D30
RXB1D20
RXB1D10
RXB1D00
RXB1D0
xxxx xxxx uuuu uuuu
0xxx xxxx 0uuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RXB1DLC
RXB1EIDL
RXB1EIDH
RXRTR
EID6
RESB1
EID5
RESB0
EID4
DLC3
EID3
DLC2
EID2
DLC1
EID1
EID9
DLC0
EID0
EID8
—
EID7
EID15
EID14
EID13
EID12
EID11
EID10
RXB1SIDL
RXB1SIDH
RXB1CON
SID2
SID10
RXFUL
SID1
SID9
SID0
SID8
SRR
SID7
—
EXID
SID6
EID17
SID4
EID16
SID3
xxxx x0xx uuuu u0uu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
—
SID5
RXM1
RXM0
RXRTRRO
FILHIT2
FILHIT1
FILHIT0
CANSTAT
Legend:
OPMODE2 OPMODE1
OPMODE0
ICODE2
ICODE1
ICODE0
xxx- xxx- uuu- uuu-
—
—
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.
4: These registers are reserved on PIC18C658.
DS30475A-page 56
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Value on
POR,
BOR
Value on
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS(3)
TXB0D77
TXB0D67
TXB0D57
TXB0D47
TXB0D37
TXB0D27
TXB0D17
TXB0D07
TXB0D76
TXB0D66
TXB0D56
TXB0D46
TXB0D36
TXB0D26
TXB0D16
TXB0D06
TXRTR
TXB0D75
TXB0D65
TXB0D55
TXB0D45
TXB0D35
TXB0D25
TXB0D15
TXB0D05
TXB0D74
TXB0D64
TXB0D54
TXB0D44
TXB0D34
TXB0D24
TXB0D14
TXB0D04
TXB0D73
TXB0D63
TXB0D53
TXB0D43
TXB0D33
TXB0D23
TXB0D13
TXB0D03
DLC3
TXB0D72
TXB0D62
TXB0D52
TXB0D42
TXB0D32
TXB0D22
TXB0D12
TXB0D02
DLC2
TXB0D71
TXB0D61
TXB0D51
TXB0D41
TXB0D31
TXB0D21
TXB0D11
TXB0D01
DLC1
TXB0D70
TXB0D60
TXB0D50
TXB0D40
TXB0D30
TXB0D20
TXB0D10
TXB0D00
DLC0
TXB0D7
TXB0D6
TXB0D5
TXB0D4
TXB0D3
TXB0D2
TXB0D1
TXB0D0
TXB0DLC
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0x00 xxxx 0u00 uuuu
—
—
—
EID7
EID6
EID14
SID1
EID5
EID4
EID3
EID11
EID2
EID1
EID9
EID0
EID8
TXB0EIDL
TXB0EIDH
TXB0SIDL
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxx0 x0xx uuu0 u0uu
EID15
SID2
EID13
SID0
EID12
EID10
EXIDEN
EID17
EID16
—
—
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
TXB0SIDH
TXB0CON
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
TXABT
TXLARB
TXERR
TXREQ
TXPRI1
TXPRI0
—
—
CANSTAT
OPMODE2 OPMODE1
OPMODE0
TXB1D75
TXB1D65
TXB1D55
TXB1D45
TXB1D35
TXB1D25
TXB1D15
TXB1D05
ICODE2
TXB1D73
TXB1D63
TXB1D53
TXB1D43
TXB1D33
TXB1D23
TXB1D13
TXB1D03
DLC3
ICODE1
TXB1D72
TXB1D62
TXB1D52
TXB1D42
TXB1D32
TXB1D22
TXB1D12
TXB1D02
DLC2
ICODE0
TXB1D71
TXB1D61
TXB1D51
TXB1D41
TXB1D31
TXB1D21
TXB1D11
TXB1D01
DLC1
xxx- xxx- uuu- uuu-
—
—
TXB1D77
TXB1D67
TXB1D57
TXB1D47
TXB1D37
TXB1D27
TXB1D17
TXB1D07
TXB1D76
TXB1D66
TXB1D56
TXB1D46
TXB1D36
TXB1D26
TXB1D16
TXB1D06
TXRTR
TXB1D74
TXB1D70
TXB1D7
TXB1D6
TXB1D5
TXB1D4
TXB1D3
TXB1D2
TXB1D1
TXB1D0
TXB1DLC
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0x00 xxxx 0u00 uuuu
TXB1D64
TXB1D54
TXB1D44
TXB1D34
TXB1D24
TXB1D14
TXB1D04
TXB1D60
TXB1D50
TXB1D40
TXB1D30
TXB1D20
TXB1D10
TXB1D00
DLC0
—
—
—
EID7
EID6
EID14
SID1
EID5
EID4
EID3
EID11
EXIDE
EID2
EID1
EID9
EID0
EID8
TXB1EIDL
TXB1EIDH
TXB1SIDL
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxx0 x0xx uuu0 u0uu
EID15
SID2
EID13
SID0
EID12
EID10
EID17
EID16
—
—
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
TXB1SIDH
TXB1CON
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
TXABT
TXLARB
TXERR
TXREQ
TXPRI1
TXPRI0
—
—
CANSTAT
Legend:
OPMODE2 OPMODE1
OPMODE0
ICODE2
ICODE1
ICODE0
xxx- xxx- uuu- uuu-
—
—
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.
4: These registers are reserved on PIC18C658.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 57
PIC18CXX8
Value on
POR,
BOR
Value on
all other
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESETS(3)
TXB2D77
TXB2D67
TXB2D57
TXB2D47
TXB2D37
TXB2D27
TXB2D17
TXB2D07
TXB2D76
TXB2D66
TXB2D56
TXB2D46
TXB2D36
TXB2D26
TXB2D16
TXB2D06
TXRTR
TXB2D75
TXB2D65
TXB2D55
TXB2D45
TXB2D35
TXB2D25
TXB2D15
TXB2D05
TXB2D74
TXB2D64
TXB2D54
TXB2D44
TXB2D34
TXB2D24
TXB2D14
TXB2D04
TXB2D73
TXB2D63
TXB2D53
TXB2D43
TXB2D33
TXB2D23
TXB2D13
TXB2D03
DLC3
TXB2D72
TXB2D62
TXB2D52
TXB2D42
TXB2D32
TXB2D22
TXB2D12
TXB2D02
DLC2
TXB2D71
TXB2D61
TXB2D51
TXB2D41
TXB2D31
TXB2D21
TXB2D11
TXB2D01
DLC1
TXB2D70
TXB2D60
TXB2D50
TXB2D40
TXB2D30
TXB2D20
TXB2D10
TXB2D00
DLC0
TXB2D7
TXB2D6
TXB2D5
TXB2D4
TXB2D3
TXB2D2
TXB2D1
TXB2D0
TXB2DLC
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0x00 xxxx 0u00 uuuu
—
—
—
EID7
EID6
EID14
SID1
EID5
EID4
EID3
EID11
EID2
EID1
EID9
EID0
EID8
TXB2EIDL
TXB2EIDH
TXB2SIDL
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxx0 x0xx uuu0 u0uu
EID15
SID2
EID13
SID0
EID12
EID10
EXIDEN
EID17
EID16
—
—
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
TXB2SIDH
TXB2CON
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
TXABT
TXLARB
TXERR
TXREQ
TXPRI1
TXPRI0
—
—
EID7
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID3
EID2
EID1
EID9
EID0
EID8
RXM1EIDL
RXM1EIDH
RXM1SIDL
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxx- --xx uuu- --uu
EID15
SID2
EID12
EID11
EID10
EID17
EID16
—
—
—
SID10
EID7
SID9
EID6
EID14
SID1
SID8
EID5
EID13
SID0
SID7
SID6
SID5
SID4
EID1
EID9
EID17
SID3
EID0
EID8
EID16
RXM1SIDH
RXM0EIDL
RXM0EIDH
RXM0SIDL
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxx- --xx uuu- --uu
EID4
EID3
EID2
EID15
SID2
EID12
EID11
EID10
—
—
—
SID10
EID7
SID9
EID6
EID14
SID1
SID8
EID5
EID13
SID0
SID7
SID6
SID5
SID4
EID1
EID9
EID17
SID3
EID0
EID8
EID16
RXM0SIDH
RXF5EID0
RXF5EID8
RXF5SIDL
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxx- x-xx uuu- u-uu
EID4
EID3
EID11
EID2
EID15
SID2
EID12
EID10
EXIDEN
—
—
SID10
EID7
SID9
EID6
EID14
SID1
SID8
EID5
EID13
SID0
SID7
SID6
EID3
SID5
SID4
EID1
EID9
EID17
SID3
EID0
EID8
EID16
RXF5SIDH
RXF4EID0
RXF4EID8
RXF4SIDL
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxx- x-xx uuu- u-uu
EID4
EID2
EID15
SID2
EID12
EID11
EXIDEN
EID10
—
—
SID10
EID7
SID9
EID6
EID14
SID1
SID8
EID5
EID13
SID0
SID7
SID6
EID3
SID5
SID4
EID1
EID9
EID17
SID3
EID0
EID8
EID16
RXF4SIDH
RXF3EID0
RXF3EID8
RXF3SIDL
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxx- x-xx uuu- u-uu
EID4
EID2
EID15
SID2
EID12
EID11
EXIDEN
EID10
—
—
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
RXF3SIDH
Legend:
xxxx xxxx uuuu uuuu
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.
4: These registers are reserved on PIC18C658.
DS30475A-page 58
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Value on
POR,
BOR
Value on
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS(3)
EID7
EID15
SID2
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID3
EID11
EID2
EID1
EID9
EID0
EID8
RXF2EID0
RXF2EID8
RXF2SIDL
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxx- x-xx uuu- u-uu
EID12
EID10
EXIDEN
EID17
EID16
—
—
SID10
EID7
SID9
EID6
EID14
SID1
SID8
EID5
EID13
SID0
SID7
SID6
EID3
SID5
SID4
EID1
EID9
EID17
SID3
EID0
EID8
EID16
RXF2SIDH
RXF1EIDL
RXF1EIDH
RXF1SIDL
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxx- x-xx uuu- u-uu
EID4
EID2
EID15
SID2
EID12
EID11
EXIDEN
EID10
—
—
SID10
EID7
SID9
EID6
EID14
SID1
SID8
EID5
EID13
SID0
SID7
SID6
EID3
SID5
SID4
EID1
EID9
EID17
SID3
EID0
EID8
EID16
RXF1SIDH
RXF0EIDL
RXF0EIDH
RXF0SIDL
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxx- x-xx uuu- u-uu
EID4
EID2
EID15
SID2
EID12
EID11
EXIDEN
EID10
—
—
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
RXF0SIDH
Legend:
xxxx xxxx uuuu uuuu
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.
4: These registers are reserved on PIC18C658.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 59
PIC18CXX8
4.10
Access Bank
4.11
Bank Select Register (BSR)
The Access Bank is an architectural enhancement that
is very useful for C compiler code optimization. The
techniques used by the C compiler are also be useful
for programs written in assembly.
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ’0’s, and
writes will have no effect.
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
A MOVLBinstruction has been provided in the instruc-
• Faster evaluation/control of SFR’s (no banking)
tion set to assist in selecting banks.
The Access Bank is comprised of the upper 160 bytes
in Bank 15 (SFR’s) and the lower 96 bytes in Bank 0.
These two sections will be referred to as Access Bank
High and Access Bank Low, respectively. Figure 4-4
indicates the Access Bank areas.
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register, or in
the Access Bank.
A MOVFFinstruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
When forced in the Access Bank (a = ’0’), the last
address in Access Bank Low is followed by the first
address in Access Bank High. Access Bank High maps
most of the Special Function Registers so that these
registers can be accessed without any software over-
head.
Section 4.12 provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
FIGURE 4-5: DIRECT ADDRESSING
Direct Addressing
(3)
from opcode
BSR<3:0>
7
0
(2)
(3)
bank select
location select
00h
000h
01h
100h
0Eh
E00h
0Fh
F00h
Data
Memory(1)
0FFh
1FFh
EFFh
FFFh
Bank 0
Bank 1
Bank 14 Bank 15
Note 1: For register file map detail, see Table 4-2.
2: The access bit of the instruction can be used to force an override of the selected bank
(BSR<3:0>) to the registers of the Access Bank.
3: The MOVFFinstruction embeds the entire 12-bit address in the instruction.
DS30475A-page 60
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
If an instruction writes a value to INDF0, the value will
be written to the address indicated by FSR0H:FSR0L.
A read from INDF1 reads the data from the address
indicated by FSR1H:FSR1L. INDFn can be used in
code anywhere an operand can be used.
4.12
Indirect Addressing, INDF and FSR
Registers
Indirect addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. A SFR register is used as a pointer to the
data memory location that is to be read or written.
Since this pointer is in RAM, the contents can be mod-
ified by the program. This can be useful for data tables
in the data memory and for software stacks. Figure 4-6
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address
specified by the value of the FSR register.
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all ’0’s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOPinstruction and the
STATUS bits are not affected.
4.12.1 INDIRECT ADDRESSING OPERATION
Each FSR register has an INDF register associated with
it, plus four additional register addresses. Performing an
operation on one of these five registers determines how
the FSR will be modified during indirect addressing.
Indirect addressing is possible by using one of the
INDF registers. Any instruction using the INDF register
actually accesses the register indicated by the File
Select Register, FSR. Reading the INDF register itself
indirectly (FSR = ’0’) will read 00h. Writing to the INDF
register indirectly results in a no-operation. The FSR
register contains a 12-bit address, which is shown in
Figure 4-6.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access (no
change) - INDFn
The INDFn (0 ≤ n ≤ 2) register is not a physical register.
Addressing INDFn actually addresses the register
whose address is contained in the FSRn register
(FSRn is a pointer). This is indirect addressing.
• Auto-decrement FSRn after an indirect access
(post-decrement) - POSTDECn
• Auto-increment FSRn after an indirect access
(post-increment) - POSTINCn
Example 4-4 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
• Auto-increment FSRn before an indirect access
(pre-increment) - PREINCn
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) - PLUSWn
EXAMPLE 4-4: HOW TO CLEAR RAM
(BANK 1) USING INDIRECT
ADDRESSING
LFSR
NEXT CLRF
FSR0, 0x100
POSTINC0
;
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
STATUS register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
; Clear INDF
; register
; & inc pointer
; All done
; w/ Bank1?
; NO, clear next
;
BTFSS
FSR0H, 1
NEXT
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL overflows from an increment,
FSRnH will be incremented automatically.
GOTO
CONTINUE
:
; YES, continue
Adding these features allows the FSRn to be used as a
software stack pointer in addition to its uses for table
operations in data memory.
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bit wide. To store the 12-bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
Each FSR has an address associated with it that per-
forms an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add the 2’s complement value in the
WREG register and the value in FSR to form the
address before an indirect access. The FSR value is
not changed.
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
If an FSR register contains a value that indicates one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(STATUS bits are not affected).
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data.
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register, the
write operation will dominate over the pre- or
post-increment/decrement functions.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 61
PIC18CXX8
FIGURE 4-6: INDIRECT ADDRESSING
Indirect Addressing
FSR register
7
11
8
0
FSRnH
FSRnL
location select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 4-2.
DS30475A-page 62
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
4.13
STATUS Register
The STATUS register, shown in Register 4-2, contains
the arithmetic status of the ALU. The STATUS register
can be the destination for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled. These bits
are set or cleared according to the device logic. There-
fore, the result of an instruction with the STATUS regis-
ter as destination may be different than intended.
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFFand MOVWFinstructions are used to
alter the STATUS register, because these instruc-
tions do not affect the Z, C, DC, OV or N bits from the
STATUS register. For other instructions which do not
affect the status bits, see Table 23-2.
Note: The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
REGISTER 4-2:
STATUS REGISTER
U-0
U-0
U-0
R/W-x
N
R/W-x
OV
R/W-x
Z
R/W-x
DC
R/W-x
C
—
—
—
bit 7
bit 0
bit 7-5
Unimplemented: Read as '0'
N: Negative bit
bit 4
This bit is used for signed arithmetic (2’s complement). It indicates whether the result of the ALU
operation was negative, (ALU MSb = 1)
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit mag-
nitude, which causes the sign bit (bit 7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLW,and SUBWFinstructions
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRCF, RRNCF, RLCF, and
RLNCF) instructions, this bit is loaded with either the bit 4 or bit 3 of the source
register.
bit 0
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW,and SUBWF instructions
1= A carry-out from the most significant bit of the result occurred
0= No carry-out from the most significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 63
PIC18CXX8
4.13.1 RCON REGISTER
Note 1: If the BOREN configuration bit is set, BOR
is ’1’ on Power-on Reset. If the BOREN
configuration bit is clear, BOR is unknown
on Power-on Reset.
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device RESET. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.
The BOR status bit is a “don't care” and is
not necessarily predictable if the
brown-out circuit is disabled (the BOREN
configuration bit is clear). BOR must then
be set by the user and checked on subse-
quent RESETs to see if it is clear, indicat-
ing a brown-out has occurred.
2: It is recommended that the POR bit be set
after
a
Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
REGISTER 4-3:
RCON REGISTER
R/W-0
IPEN
R/W-0
LWRT
U-0
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-0
POR
R/W-0
BOR
—
bit 7
bit 0
bit 7
bit 6
IPEN: Interrupt Priority Enable bit
1 =Enable priority levels on interrupts
0 =Disable priority levels on interrupts (16CXXX compatibility mode)
LWRT: Long Write Enable bit
1 =Enable TBLWT to internal program memory
Once this bit is set, it can only be cleared by a POR or MCLR Reset
0 =Disable TBLWTto internal program memory; TBLWTonly to external program memory
bit 5
bit 4
Unimplemented: Read as '0'
RI: RESETInstruction Flag bit
1 =The RESETinstruction was not executed
0 =The RESETinstruction was executed causing a device RESET
(must be set in software after a Brown-out Reset occurs)
bit 3
bit 2
bit 1
TO: Watchdog Time-out Flag bit
1 =After power-up, CLRWDTinstruction, or SLEEPinstruction
0 =A WDT time-out occurred
PD: Power-down Detection Flag bit
1 =After power-up or by the CLRWDTinstruction
0 =By execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1 =A Power-on Reset has not occurred
0 =A Power-on Reset occurred
(must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 =A Brown-out Reset has not occurred
0 =A Brown-out Reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS30475A-page 64
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Table Read operations retrieve data from program
memory and place it into the data memory space.
Figure 5-1 shows the operation of a Table Read with
program and data memory.
5.0
TABLE READS/TABLE WRITES
All PICmicro® devices have two memory spaces: the
program memory space and the data memory space.
Table Reads and Table Writes have been provided to
move data between these two memory spaces through
an 8-bit register (TABLAT).
Table Write operations store data from the data mem-
ory space into program memory. Figure 5-2 shows the
operation of a Table Write with program and data
memory.
The operations that allow the processor to move data
between the data and program memory spaces are:
Table operations work with byte entities. A table block
containing data is not required to be word aligned, so a
table block can start and end at any byte address. If a
table write is being used to write an executable pro-
gram to program memory, program instructions will
need to be word aligned.
• Table Read (TBLRD)
• Table Write (TBLWT)
FIGURE 5-1: TABLE READ OPERATION
(1)
TABLE LATCH (8-bit)
TABLAT
TABLE POINTER
TBLPTRU TBLPTRH TBLPTRL
PROGRAM MEMORY
Program Memory
(TBLPTR)
Instruction: TBLRD*
Note 1: Table Pointer points to a byte in program memory.
FIGURE 5-2: TABLE WRITE OPERATION
(1)
TABLE LATCH (8-bit)
TABLAT
TABLE POINTER
TBLPTRU TBLPTRH TBLPTRL
PROGRAM MEMORY
Program Memory
(TBLPTR)
Instruction: TBLWT*
Note 1: Table Pointer points to a byte in program memory.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 65
PIC18CXX8
5.1.1
RCON REGISTER
5.1
Control Registers
The LWRT bit specifies the operation of Table Writes to
internal memory when the VPP voltage is applied to the
MCLR pin. When the LWRT bit is set, the controller
continues to execute user code, but long table writes
are allowed (for programming internal program mem-
ory) from user mode. The LWRT bit can be cleared only
by performing either a POR or MCLR Reset.
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include:
• RCON register
• TABLAT register
• TBLPTR registers
REGISTER 5-1: RCON REGISTER (ADDRESS: 0xFD0h)
R/W-0
IPEN
R/W-0
LWRT
U-0
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-0
POR
R/W-0
BOR
—
bit 7
bit 0
bit 7
bit 6
IPEN: Interrupt Priority Enable
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (16CXXX compatibility mode)
LWRT: Long Write Enable
1= Enable TBLWTto internal program memory
0= Disable TBLWTto internal program memory.
Note 1: Only cleared on a POR or MCLR reset.
This bit has no effect on TBLWTsto external program memory.
bit 5
bit 4
Unimplemented: Read as '0'
RI: RESETInstruction Flag bit
1= No RESETinstruction occurred
0= A RESETinstruction occurred
bit 3
bit 2
bit 1
bit 0
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= No Brown-out Reset nor POR Reset occurred
0= A Brown-out Reset or POR Reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS30475A-page 66
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
5.1.2
TABLAT - TABLE LATCH REGISTER
address up to 2 Mbytes of program memory space. The
22nd bit allows read only access to the Device ID, the
User ID and the Configuration bits.
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data memory.
The table pointer TBLPTR is used by the TBLRDand
TBLWTinstructions. These instructions can update the
TBLPTR in one of four ways based on the table oper-
ation. These operations are shown in Table 5-1.
These operations on the TBLPTR only affect the low
order 21-bits.
5.1.3
TBLPTR - TABLE POINTER REGISTER
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper byte, High
byte and Low byte). These three registers
(TBLPTRU:TBLPTRH:TBLPTRL) join to form a 22-bit
wide pointer. The low order 21-bits allow the device to
TABLE 5-1:
Example
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
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Advanced Information
DS30475A-page 67
PIC18CXX8
When a Table Write occurs to an even program mem-
ory address (TBLPTR<0> = 0), the contents of TABLAT
are transferred to an internal holding register. This is
performed as a short write and the program memory
block is not actually programmed at this time. The
holding register is not accessible by the user.
5.2
Program Memory Read/Writes
TABLE READ OVERVIEW (TBLRD)
5.2.1
The TBLRDinstructions are used to read data from pro-
gram memory to data memory.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified auto-
matically for the next Table Read operation.
When a Table Write occurs to an odd program memory
address (TBLPTR<0> = 1), a long write is started. Dur-
ing the long write, the contents of TABLAT are written
to the high byte of the program memory block and the
contents of the holding register are transferred to the
low byte of the program memory block.
Table Reads from program memory are performed one
byte at a time. The instruction will load TABLAT with the
one byte from program memory pointed to by TBLPTR.
Figure 5-3 shows the holding register and the program
memory write blocks.
5.2.2
PROGRAM MEMORY WRITE BLOCK SIZE
If a single byte is to be programmed, the low (even)
byte of the destination program word should be read
using TBLRD*, modified or changed, if required, and
written back to the same address using TBLWT*+. The
high (odd) byte should be read using TBLRD*, modified
or changed if required, and written back to the same
address using TBLWT. The write to an odd address will
cause a long write to begin. This process ensures that
existing data in either byte will not be changed unless
desired.
The program memory of PIC18CXX8 devices is written
in blocks. For PIC18CXX8 devices, the write block size
is 2 bytes. Consequently, Table Write operations to
program memory are performed in pairs, one byte at a
time.
FIGURE 5-3: HOLDING REGISTER AND THE WRITE
Program Memory
Holding Register
Instruction Execution
; TABLPTR points to address n
MOVLW DataLow ; Load low data
MSB
LSB
MOVWF TABLAT
TBLWT*+
; byte to TABLAT
; Write it to LSB
DataLow
; of Holding register
MOVLW DataHigh ; Load high data
n - 1
MSB
LSB
MOVWF TABLAT
TBLWT*
; byte to TABLAT
; Write it to MSB
; of Holding
n
DataLow
DataHigh
DataHigh
DataLow
n + 1
n + 2
; register and
; begin long
; write
EXAMPLE 5-1: TABLE READ CODE EXAMPLE
; Read a byte from location 0x0020
CLRF
TBLPTRU
; Load upper 5 bits of
; 0x0020
CLRF
TBLPTRH
; Load higher 8 bits of
; 0x0020
MOVLW 0x20
MOVWF TBLPTRL
MOVWF TBLRD*
; Load 0x20 into
; TBLPTRL
; Data is in TABLAT
DS30475A-page 68
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
5.2.2.1
Long Write Operation
5.2.2.2
Sequence of Events
The long write is what actually programs words of data
into the internal memory. When a TBLWTto the MSB of
the write block occurs, instruction execution is halted.
During this time, programming voltage and the data
stored in internal latches is applied to program memory.
The sequence of events for programming an internal
program memory location should be:
1. Enable the interrupt that terminates the long
write. Disable all other interrupts.
2. Clear the source interrupt flag.
For a long write to occur:
3. If Interrupt Service Routine execution is desired
when the device wakes, enable global
interrupts.
1. MCLR/VPP pin must be at the programming
voltage
2. LWRT bit must be set
4. Set LWRT bit in the RCON register.
3. TBLWT to the address of the MSB of the write
5. Raise MCLR/VPP pin to the programming
voltage, VPP.
block
6. Clear the WDT (if enabled).
If the LWRT bit is clear, a short write will occur and pro-
gram memory will not be changed. If the TBLWTis not
to the MSB of the write block, then the programming
phase is not initiated.
7. Set the interrupt source to interrupt at the
required time.
8. Execute the Table Write for the lower (even)
byte. This will be a short write.
Setting the LWRT bit enables long writes when the
MCLR pin is taken to VPP voltage. Once the LWRT bit
is set, it can be cleared only by performing a POR or
MCLR Reset.
9. Execute the Table Write for the upper (odd) byte.
This will be a long write. The controller will HALT
while programming. The interrupt wakes the
controller.
To ensure that the memory location has been well pro-
grammed, a minimum programming time is required.
The long write can be terminated after the program-
ming time has expired by a RESET or an interrupt.
Having only one interrupt source enabled to terminate
the long write, ensures that no unintended interrupts
will prematurely terminate the long write.
10. If GIE was set, service the interrupt request.
11. Go to 7 if more bytes to be programmed.
12. Lower MCLR/VPP pin to VDD.
13. Verify the memory location (table read).
14. Reset the device.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 69
PIC18CXX8
5.2.3
LONG WRITE INTERRUPTS
5.3
Unexpected Termination of Write
Operations
The long write must be terminated by a RESET or any
interrupt.
If a write is terminated by an unplanned event such as
loss of power, an unexpected RESET, or an interrupt
that was not disabled, the memory location just pro-
grammed should be verified and reprogrammed if
needed.
The interrupt source must have its interrupt enable bit
set. When the source sets its interrupt flag, program-
ming will terminate. This will occur regardless of the
settings of interrupt priority bits, the GIE/GIEH bit or the
PIE/GIEL bit.
Depending on the states of interrupt priority bits, the
GIE/GIEH bit or the PIE/GIEL bit, program execution
can either be vectored to the high or low priority Inter-
rupt Service Routine (ISR), or continue execution from
where programming commenced.
In either case, the interrupt flag will not be cleared
when programming is terminated and will need to be
cleared by the software.
TABLE 5-2:
SLEEP MODE, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS
GIE/
GIEH
PIE/
GIEL
Interrupt
Enable
Interrupt
Flag
Priority
Action
X
X
X
0
X
Long write continues even if interrupt flag
becomes set during SLEEP.
(default)
X
X
X
X
1
1
1
0
1
1
Long write continues, will wake when
the interrupt flag is set.
0
0
Terminates long write, executes next instruction.
Interrupt flag not cleared.
(default)
(default)
0
1
1
Terminates long write, executes next instruction.
Interrupt flag not cleared.
(default)
high priority
(default)
1
0
0
low
1
1
1
1
Terminates long write, executes next instruction.
Interrupt flag not cleared.
(default)
0
1
0
low
Terminates long write, branches to low priority
interrupt vector.
(default)
Interrupt flag can be cleared by ISR.
1
0
1
1
1
Terminates long write, branches to high priority
interrupt vector.
Interrupt flag can be cleared by ISR.
(default)
high priority
(default)
DS30475A-page 70
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
6.0
8 X 8 HARDWARE MULTIPLIER
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18CXX8 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the STATUS register.
• Higher computational throughput
• Reduces code size requirements for multiply algo-
rithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 6-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
TABLE 6-1:
Routine
PERFORMANCE COMPARISON
Program
Cycles
(Max)
Time
Multiply Method
Memory
(Words)
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 µs
100 ns
9.1 µs
600 ns
24.2 µs
2.4 µs
25.4 µs
3.6 µs
27.6 µs
400 ns
36.4 µs
2.4 µs
69 µs
1 µs
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91 µs
6 µs
16 x 16 unsigned Without hardware multiply
Hardware multiply
21
24
52
36
242
24
254
36
96.8 µs
9.6 µs
242 µs
24 µs
254 µs
36 µs
16 x 16 signed
Without hardware multiply
Hardware multiply
102.6 µs
14.4 µs
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 71
PIC18CXX8
Example 6-3 shows the sequence to perform a 16 x 16
unsigned multiply. Equation 6-1 shows the algorithm
that is used. The 32-bit result is stored in 4 registers
RES3:RES0.
6.1
Operation
Example 6-1 shows the sequence to perform an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
EQUATION 6-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
Example 6-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
(ARG1H • ARG2H • 2
)
+
+
+
8
(ARG1H • ARG2L • 2 )
8
(ARG1L • ARG2H • 2 )
EXAMPLE 6-1: 8 x 8 UNSIGNED MULTIPLY
ROUTINE
(ARG1L • ARG2L)
MOVFF
MULWF
ARG1, WREG
ARG2
;
; ARG1 * ARG2 ->
;
PRODH:PRODL
EXAMPLE 6-3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MULWF
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
EXAMPLE 6-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
;
;
;
PRODH:PRODL
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVFF
MULWF
ARG1, WREG
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
;
;
MOVFF
MULWF
ARG1H, WREG
ARG2H
BTFSC
SUBWF
ARG2, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
; ARG1H * ARG2H ->
;
;
;
PRODH:PRODL
;
- ARG1
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVFF
BTFSC
SUBWF
ARG2, WREG
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
MOVFF
MULWF
ARG1L, WREG
ARG2H
;
- ARG2
; ARG1L * ARG2H ->
;
;
PRODH:PRODL
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
; Add cross
;
;
;
;
products
RES3, F
;
MOVFF
MULWF
ARG1H, WREG
ARG2L
;
; ARG1H * ARG2L ->
;
;
PRODH:PRODL
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
; Add cross
;
;
;
;
products
RES3, F
DS30475A-page 72
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Example 6-4 shows the sequence to perform an 16 x
16 signed multiply. Equation 6-2 shows the algorithm
used. The 32-bit result is stored in four registers
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs most significant bit (MSb)
is tested and the appropriate subtractions are done.
EXAMPLE 6-4: 16 x 16 SIGNED MULTIPLY
ROUTINE
MOVFF
MULWF
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
;
;
;
PRODH:PRODL
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
;
;
EQUATION 6-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
MOVFF
MULWF
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
;
;
;
PRODH:PRODL
RES3:RES0
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
=
=
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 2
16
)
+
+
+
+
8
(ARG1H • ARG2L • 2 )
(ARG1L • ARG2H • 2 )
(ARG1L • ARG2L)
(-1 • ARG2H<7> • ARG1H:ARG1L • 2
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
MOVFF
MULWF
ARG1L, WREG
ARG2H
8
; ARG1L * ARG2H ->
;
;
PRODH:PRODL
16
16
)
)
+
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
; Add cross
;
;
;
;
products
RES3, F
;
MOVFF
MULWF
ARG1H, WREG
ARG2L
;
; ARG1H * ARG2L ->
;
;
PRODH:PRODL
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
; Add cross
;
;
;
;
products
RES3, F
;
;
BTFSS
GOTO
MOVFF
SUBWF
MOVFF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, WREG
RES2
ARG1H, WREG
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
SIGN_ARG1
BTFSS
GOTO
MOVFF
SUBWF
MOVFF
SUBWFB
;
ARG1H, 7
CONT_CODE
ARG2L, WREG
RES2
ARG2H, WREG
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
CONT_CODE
:
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 73
PIC18CXX8
NOTES:
DS30475A-page 74
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
When the IPEN bit is cleared (default state), the inter-
rupt priority feature is disabled and interrupts are com-
patible with PICmicro® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. The PEIE bit (INTCON register)
enables/disables all peripheral interrupt sources. The
GIE bit (INTCON register) enables/disables all interrupt
sources. All interrupts branch to address 000008h in
Compatibility mode.
7.0
INTERRUPTS
The PIC18CXX8 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level or a low priority level. The high priority interrupt
vector is at 000008h and the low priority interrupt vector
is at 000018h. High priority interrupt events will over-
ride any low priority interrupts that may be in progress.
There are 13 registers that are used to control interrupt
operation. These registers are:
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt prior-
ity levels are used, this will be either the GIEH or GIEL
bit. High priority interrupt sources can interrupt a low
priority interrupt.
• RCON
• INTCON
• INTCON2
• INTCON3
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the interrupt service
routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
• PIR1, PIR2, PIR3
• PIE1, PIE2, PIE3
• IPR1, IPR2, IPR3
It is recommended that the Microchip header files sup-
plied with MPLAB be used for the symbolic bit names
in these registers. This allows the assembler/compiler
to automatically take care of the placement of these
bits within the specified register.
The "return from interrupt" instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
Each interrupt source has three bits to control its oper-
ation. The functions of these bits are:
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when
the flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON register). When interrupt priority is
enabled, there are two bits that enable interrupts glo-
bally. Setting the GIEH bit (INTCON register) enables
all interrupts that have the priority bit set. Setting the
GIEL bit (INTCON register) enables all interrupts that
have the priority bit cleared. When the interrupt flag,
enable bit and appropriate global interrupt enable bit
are set, the interrupt will vector immediately to address
000008h or 000018h, depending on the priority level.
Individual interrupts can be disabled through their cor-
responding enable bits.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 75
PIC18CXX8
FIGURE 7-1: INTERRUPT LOGIC
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
Wake-up if in SLEEP mode
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Interrupt to CPU
Vector to location
0008h
INT3IF
INT3IE
INT3IP
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
GIE/GIEH
TMR1IF
TMR1IE
TMR1IP
IPEN
IPEN
GIEL/PEIE
XXXXIF
XXXXIE
XXXXIP
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR0IF
TMR0IE
TMR0IP
Interrupt to CPU
Vector to Location
0018h
TMR1IF
TMR1IE
TMR1IP
RBIF
RBIE
RBIP
PEIE/GIEL
XXXXIF
XXXXIE
XXXXIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
DS30475A-page 76
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2000 Microchip Technology Inc.
PIC18CXX8
7.1.1
INTCON REGISTERS
7.1
Control Registers
The INTCON Registers are readable and writable
registers, which contain various enable, priority, and
flag bits.
This section contains the control and status registers.
REGISTER 7-1:
INTCON REGISTER
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
R/W-x
RBIF
GIE/GIEH PEIE/GIEL TMR0IE
bit 7
INT0IE
TMR0IF INT0IF
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all un-masked interrupts
0= Disables all interrupts
When IPEN = 1:
1= Enables all high priority interrupts
0= Disables all high priority interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low priority peripheral interrupts
0= Disables all priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software by reading PORTB)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows software polling.
2000 Microchip Technology Inc.
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DS30475A-page 77
PIC18CXX8
REGISTER 7-2:
INTCON2 REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBIP
RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG3: External Interrupt 3 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
INT3IP: INT3 External Interrupt Priority bit
1= High priority
0= Low priority
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows software polling.
DS30475A-page 78
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
REGISTER 7-3:
INTCON3 REGISTER
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
INT3IF
R/W-0
INT2IF
R/W-0
INT1IF
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
INT3IE: INT3 External Interrupt Enable bit
1= Enables the INT3 external interrupt
0= Disables the INT3 external interrupt
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
INT3IF: INT3 External Interrupt Flag bit
1= The INT3 external interrupt occurred
(must be cleared in software)
0= The INT3 external interrupt did not occur
bit 1
bit 0
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred
(must be cleared in software)
0= The INT2 external interrupt did not occur
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred
(must be cleared in software)
0= The INT1 external interrupt did not occur
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows software polling.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 79
PIC18CXX8
7.1.2
PIR REGISTERS
7.1.3
PIE REGISTERS
The Peripheral Interrupt Request (PIR) registers con-
tain the individual flag bits for the peripheral interrupts
(Register 7-5). Due to the number of peripheral inter-
rupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
The Peripheral Interrupt Enable (PIE) registers contain
the individual enable bits for the peripheral interrupts
(Register 7-5). Due to the number of peripheral inter-
rupt sources, there are three Peripheral Interrupt
Enable registers (PIE1, PIE2, PIE3). When IPEN is
clear, the PEIE bit must be set to enable any of these
peripheral interrupts.
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON register).
7.1.4
IPR REGISTERS
The Interrupt Priority (IPR) registers contain the individ-
ual priority bits for the peripheral interrupts
(Register 7-7). Due to the number of peripheral inter-
rupt sources, there are three Peripheral Interrupt Prior-
ity registers (IPR1, IPR2, IPR3). The operation of the
priority bits requires that the Interrupt Priority Enable bit
(IPEN) be set.
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
7.1.5
RCON REGISTER
The Reset Control (RCON) register contains the bit that
is used to enable prioritized interrupts (IPEN).
REGISTER 7-4:
RCON REGISTER
R/W-0
R/W-0
LWRT
U-0
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-0
POR
R/W-0
BOR
IPEN
—
bit 7
bit 0
bit 7
bit 6
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (16CXXX compatibility mode)
LWRT: Long Write Enable
For details of bit operation see Register 4-3
bit 5
bit 4
Unimplemented: Read as '0'
RI: RESETInstruction Flag bit
For details of bit operation see Register 4-3
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
For details of bit operation see Register 4-3
PD: Power-down Detection Flag bit
For details of bit operation see Register 4-3
POR: Power-on Reset Status bit
For details of bit operation see Register 4-3
BOR: Brown-out Reset Status bit
For details of bit operation see Register 4-3
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
DS30475A-page 80
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
REGISTER 7-5:
PIR1
PIR REGISTERS
R/W-0
PSPIF
R/W-0
R-0
R-0
R/W-0
SSPIF
R/W-0
CCP1IF TMR2IF TMR1IF
bit 0
R/W-0
R/W-0
ADIF
RCIF
TXIF
bit 7
U-0
R/W-0
CMIF
U-0
U-0
R/W-0
BCLIF
R/W-0
LVDIF
R/W-0
TMR3IF CCP2IF
bit 0
R/W-0
PIR2
PIR3
—
—
—
bit 7
R/W-0
IRXIF
R/W-0
R/W-0
ERRIF
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXB0IF
bit 0
WAKIF
TXB2IF
TXB1IF
TXB0IF RXB1IF
bit 7
PIR1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place
(must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed
(must be cleared in software)
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer, RCREG, is full
(cleared when RCREG is read)
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer, TXREG, is empty
(cleared when TXREG is written)
0= The USART transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete
(must be cleared in software)
0= Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred
(must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred
(must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred
(must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed
(must be cleared in software)
0= TMR1 register did not overflow
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 81
PIC18CXX8
REGISTER 7-5:
PIR REGISTERS (CONT’D)
PIR2
bit 7
bit 6
Unimplemented: Read as’0’
CMIF: Comparator Interrupt Flag bit
1= Comparator input has changed
0= Comparator input has not changed
bit 5-4 Unimplemented: Read as’0’
bit 3
bit 2
bit 1
bit 0
BCLIF: Bus Collision Interrupt Flag bit
1= A Bus Collision occurred
(must be cleared in software)
0= No Bus Collision occurred
LVDIF: Low Voltage Detect Interrupt Flag bit
1= A low voltage condition occurred
(must be cleared in software)
0= The device voltage is above the Low Voltage Detect trip point
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed
(must be cleared in software)
0= TMR3 register did not overflow
CCP2IF: CCPx Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred
(must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred
(must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
DS30475A-page 82
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
REGISTER 7-5:
PIR3
PIR REGISTERS (CONT’D)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IRXIF: Invalid Message Received Interrupt Flag bit
1= An invalid message has occurred on the CAN bus
0= An invalid message has not occurred on the CAN bus
WAKIF: Bus Activity Wake-up Interrupt Flag bit
1= Activity on the CAN bus has occurred
0= Activity on the CAN bus has not occurred
ERRIF: CAN Bus Error Interrupt Flag bit
1= An error has occurred in the CAN module (multiple sources)
0= An error has not occurred in the CAN module
TXB2IF: Transmit Buffer 2 Interrupt Flag bit
1= Transmit Buffer 2 has completed transmission of a message, and may be reloaded
0= Transmit Buffer 2 has not completed transmission of a message
TXB1IF: Transmit Buffer 1 Interrupt Flag bit
1= Transmit Buffer 1 has completed transmission of a message, and may be reloaded
0= Transmit Buffer 1 has not completed transmission of a message
TXB0IF: Transmit Buffer 0 Interrupt Flag bit
1= Transmit Buffer 0 has completed transmission of a message, and may be reloaded
0= Transmit Buffer 0 has not completed transmission of a message
RXB1IF: Receive Buffer 1 Interrupt Flag bit
1= Receive Buffer 1 has received a new message
0= Receive Buffer 1 has not received a new message
RXB0IF: Receive Buffer 0 Interrupt Flag bit
1= Receive Buffer 0 has received a new message
0= Receive Buffer 0 has not received a new message
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 83
PIC18CXX8
REGISTER 7-6:
PIE REGISTERS
R/W-0
PSPIE
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
CCP1IE TMR2IE TMR1IE
bit 0
R/W-0
R/W-0
PIE1
bit 7
U-0
R/W-0
CMIE
U-0
U-0
R/W-0
BCLIE
R/W-0
LVDIE
R/W-0
TMR3IE CCP2IE
bit 0
R/W-0
PIE2
PIE3
—
—
—
bit 7
R/W-1
IVRE
R/W-1
R/W-1
ERRIE
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RXB0IE
bit 0
WAKIE
TXB2IE
TXB1IE TXB0IE RXB1IE
bit 7
PIE1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
DS30475A-page 84
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
REGISTER 7-6:
PIE REGISTERS (CONT’D)
Unimplemented: Read as ’0’
PIE2
bit 7
bit 6
CMIE: Comparator Interrupt Enable bit
1= Enables the comparator interrupt
0= Disables the comparator interrupt
bit 5-4 Unimplemented: Read as ’0’
bit 3
bit 2
bit 1
bit 0
BCLIE: Bus Collision Interrupt Enable bit
1= Enabled
0= Disabled
LVDIE: Low-voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enables the TMR3 overflow interrupt
0= Disables the TMR3 overflow interrupt
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
PIE3
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IVRE: Invalid CAN Message Received Interrupt Enable bit
1= Enables the Invalid CAN Message Received Interrupt
0= Disables the Invalid CAN Message Received Interrupt
WAKIE: Bus Activity Wake-up Interrupt Enable bit
1= Enables the Bus Activity Wake-Up Interrupt
0= Disables the Bus Activity Wake-Up Interrupt
ERRIE: CAN Bus Error Interrupt Enable bit
1= Enables the CAN Bus Error Interrupt
0= Disables the CAN Bus Error Interrupt
TXB2IE: Transmit Buffer 2 Interrupt Enable bit
1= Enables the Transmit Buffer 2 Interrupt
0= Disables the Transmit Buffer 2 Interrupt
TXB1IE: Transmit Buffer 1 Interrupt Enable bit
1= Enables the Transmit Buffer 1 Interrupt
0= Disables the Transmit Buffer 1 Interrupt
TXB0IE: Transmit Buffer 0 Interrupt Enable bit
1= Enables the Transmit Buffer 0 Interrupt
0= Disables the Transmit Buffer 0 Interrupt
RXB1IE: Receive Buffer 1 Interrupt Enable bit
1= Enables the Receive Buffer 1 Interrupt
0= Disables the Receive Buffer 1 Interrupt
RXB0IE: Receive Buffer 0 Interrupt Enable bit
1= Enables the Receive Buffer 0 Interrupt
0= Disables the Receive Buffer 0 Interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 85
PIC18CXX8
REGISTER 7-7:
IPR REGISTERS
R/W-1
PSPIP
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
R/W-1
SSPIP
R/W-1
CCP1IP TMR2IP TMR1IP
bit 0
R/W-1
R/W-1
IPR1
bit 7
U-0
R/W-1
CMIP
U-0
U-0
R/W-1
BCLIP
R/W-1
LVDIP
R/W-1
TMR3IP CCP2IP
bit 0
R/W-1
IPR2
IPR3
—
—
—
bit 7
R/W-1
IVRP
R/W-1
R/W-1
ERRIP
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RXB0IP
bit 0
WAKIP
TXB2IP
TXB1IP TXB0IP RXB1IP
bit 7
IPR1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit
1= High priority
0= Low priority
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RCIP: USART Receive Interrupt Priority bit
1= High priority
0= Low priority
TXIP: USART Transmit Interrupt Priority bit
1= High priority
0= Low priority
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
DS30475A-page 86
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
REGISTER 7-7:
IPR REGISTERS (CONT’D)
Unimplemented: Read as ’0’
IPR2
bit 7
bit 6
CMIP: Comparator Interrupt Priority bit
1= High priority
0= Low priority
bit 5-4 Unimplemented: Read as ’0’
bit 3
bit 2
bit 1
bit 0
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
LVDIP: Low Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
CCP2IP: CCP2 Interrupt Priority bit
1= High priority
0= Low priority
IPR3
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IVRP: Invalid Message Received Interrupt Priority bit
1= High priority
0= Low priority
WAKIP: Bus Activity Wake-up Interrupt Priority bit
1= High priority
0= Low priority
ERRIP: CAN Bus Error Interrupt Priority bit
1= High priority
0= Low priority
TXB2IP: Transmit Buffer 2 Interrupt Priority bit
1= High priority
0= Low priority
TXB1IP: Transmit Buffer 1 Interrupt Priority bit
1= High priority
0= Low priority
TXB0IP: Transmit Buffer 0 Interrupt Priority bit
1= High priority
0= Low priority
RXB1IP: Receive Buffer 1 Interrupt Priority bit
1= High priority
0= Low priority
RXB0IP: Receive Buffer 0 Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 87
PIC18CXX8
7.1.6
INT INTERRUPTS
TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit TMR0IE (INTCON register). Interrupt priority
for Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2 register). See
Section 10.0 for further details on the Timer0 module.
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2, and RB3/INT3 pins are edge triggered:
either rising if the corresponding INTEDGx bit is set in
the INTCON2 register, or falling, if the INTEDGx bit is
clear. When a valid edge appears on the RBx/INTx pin,
the corresponding flag bit INTxIF is set. This interrupt
can be disabled by clearing the corresponding enable
bit INTxIE. Flag bit INTxIF must be cleared in software
in the Interrupt Service Routine before re-enabling the
interrupt. All external interrupts (INT0, INT1, INT2, and
INT3) can wake-up the processor from SLEEP, if bit
INTxIE was set prior to going into SLEEP. If the global
interrupt enable bit GIE is set, the processor will branch
to the interrupt vector following wake-up.
7.1.8
PORTB INTERRUPT-ON-CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON register). The interrupt can be enabled/
disabled by setting/clearing enable bit RBIE (INTCON
register). Interrupt priority for PORTB interrupt-
on-change is determined by the value contained in the
interrupt priority bit RBIP (INTCON2 register).
7.2
Context Saving During Interrupts
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the interrupt priority bits
INT1IP (INTCON3 register), INT3IP (INTCON3 regis-
ter), and INT2IP (INTCON2 register). There is no prior-
ity bit associated with INT0; it is always a high priority
interrupt source.
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR reg-
isters are saved on the fast return stack. If a fast return
from interrupt is not used (See Section 4.3), the user
may need to save the WREG, STATUS and BSR regis-
ters in software. Depending on the user’s application,
other registers may also need to be saved.
Example 7-1 saves and restores the WREG, STATUS
and BSR registers during an Interrupt Service Routine.
7.1.7
TMR0 INTERRUPT
In 8-bit mode (which is the default), an overflow (FFh →
00h) in the TMR0 register will set flag bit TMR0IF. In
16-bit mode, an overflow (FFFFh → 0000h) in the
EXAMPLE 7-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in Low Access bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
DS30475A-page 88
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
EXAMPLE 8-1: INITIALIZING PORTA
8.0
I/O PORTS
CLRF
PORTA
; Initialize PORTA by
; clearing output
; data latches
Depending on the device selected, there are up to
eleven ports available. Some pins of the I/O ports are
multiplexed with an alternate function from the periph-
eral features on the device. In general, when a periph-
eral is enabled, that pin may not be used as a general
purpose I/O pin.
CLRF
LATA
; Alternate method
; to clear output
; data latches
MOVLW 0x07
MOVWF ADCON1
MOVLW 0xCF
; Configure A/D
; for digital inputs
; Value used to
Each port has three registers for its operation. These
registers are:
; initialize data
; direction
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
MOVWF TRISA
; Set RA3:RA0 as inputs
; RA5:RA4 as outputs
• LAT register (output latch)
The data latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
FIGURE 8-1: RA3:RA0 AND RA5 PINS
BLOCK DIAGRAM
8.1
PORTA, TRISA and LATA Registers
PORTA is a 6-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
On a Power-on Reset, these pins are configured as
inputs and read as '0'.
RD LATA
Data
Bus
D
Q
VDD
P
WR LATA
or
WR PORTA
Q
CK
Data Latch
I/O Pin(1)
N
D
Q
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
WR TRISA
VSS
Analog
Q
CK
Read-modify-write operations on the LATA register,
reads and writes the latched output value for PORTA.
Input
Mode
TRIS Latch
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The
RA4/T0CKI pin is a Schmitt Trigger input and an open
drain output. All other RA port pins have TTL input lev-
els and full CMOS output drivers.
TTL
RD TRISA
Q
Input
Buffer
D
EN
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register1). On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
RD PORTA
SS Input (RA5 only)
To A/D Converter and LVD Modules
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Note 1:
I/O pins have diode protection to VDD and VSS.
2000 Microchip Technology Inc.
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DS30475A-page 89
PIC18CXX8
FIGURE 8-2: RA4/T0CKI PIN BLOCK
DIAGRAM
FIGURE 8-3: RA6 BLOCK DIAGRAM
ECRA6 or
RCRA6 Enable
Data
Bus
RD LATA
Data
Bus
RD LATA
Q
D
D
Q
WR LATA
or
VDD
P
CK
Q
I/O Pin(1)
N
WR PORTA
WR LATA
or
Data Latch
Q
CK
WR PORTA
D
Q
Q
VSS
Data Latch
I/O Pin(1)
N
WR TRISA
D
Q
Q
Schmitt
Trigger
Input
CK
TRIS Latch
WR
TRISA
VSS
Buffer
CK
ECRA6 or
TRIS Latch
RCRA6
RD TRISA
Enable
Data Bus
Data Bus
TTL
Q
D
Input
Buffer
RD TRISA
EN
RD PORTA
TMR0 Clock Input
Note 1: I/O pin has diode protection to VSS only.
Q
D
EN
RD PORTA
Note 1:
I/O pins have diode protection to VDD and VSS.
TABLE 8-1:
Name
PORTA FUNCTIONS
Bit#
Buffer
Function
RA0/AN0
bit0
bit1
bit2
bit3
bit4
bit5
TTL
TTL
TTL
TTL
Input/output or analog input.
Input/output or analog input.
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Input/output or analog input or VREF-.
Input/output or analog input or VREF+.
ST/OD Input/output or external clock input for Timer0 output is open drain type.
RA5/SS/AN4/LVDIN
TTL
Input/output or slave select input for synchronous serial port or analog
input, or low voltage detect input.
OSC2/CLKO/RA6
bit6
TTL
OSC2 or clock output or I/O pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input, OD = Open Drain
TABLE 8-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on Value on all
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
RESETS
PORTA
LATA
—
—
—
RA6
RA5
RA4
RA3
RA2
RA1
RA0
-x0x 0000 -uuu uuuu
-xxx xxxx -uuu uuuu
-111 1111 -111 1111
Latch A Data Output Register
PORTA Data Direction Register
TRISA
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --uu uuuu
Legend: x= unknown, u= unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by PORTA.
DS30475A-page 90
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (INTCON2 register). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
8.2
PORTB, TRISB and LATB Registers
PORTB is an 8-bit wide bi-directional port. The corre-
sponding Data Direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output ( i.e.,
put the contents of the output latch on the selected pin).
Four of PORTB’s pins, RB7:RB4, have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins
(of RB7:RB4) are compared with the old value latched
on the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are OR’d together to generate the RB Port
Change Interrupt with flag bit RBIF (INTCON register).
Read-modify-write operations on the LATB register
read and write the latched output value for PORTB.
EXAMPLE 8-2: INITIALIZING PORTB
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
CLRF
LATB
; Alternate method
; to clear output
; data latches
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
MOVLW
MOVWF
0xCF
; Value used to
; initialize data
; direction
b) Clear flag bit RBIF.
TRISB
; Set RB3:RB0 as inputs
; RB5:RB4 as outputs
; RB7:RB6 as inputs
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 8-4: RB7:RB4 PINS BLOCK
DIAGRAM
VDD
RBPU(2)
Weak
P
Pull-up
Data Latch
Data Bus
FIGURE 8-5: RB3:RB0 PINS BLOCK
D
Q
DIAGRAM
I/O pin(1)
WR LATB
or
WR PORTB
VDD
CK
TRIS Latch
RBPU(2)
Weak
P
Pull-up
D
Q
Data Latch
Data Bus
D
Q
WR TRISB
TTL
Input
Buffer
CK
I/O Pin(1)
WR Port
ST
Buffer
CK
TRIS Latch
RD TRISB
RD LATB
D
Q
TTL
Input
Buffer
WR TRIS
CK
Latch
Q
Q
D
RD TRIS
RD Port
EN
Q1
RD PORTB
Set RBIF
Q
D
EN
D
From other
RB7:RB4 pins
RD PORTB
Q3
Schmitt Trigger
Buffer
EN
RBx/INTx
RBx/INTx
RD Port
Note 1:
2:
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2 register).
Note 1:
2:
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2 register).
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 91
PIC18CXX8
TABLE 8-3:
Name
PORTB FUNCTIONS
Bit#
Buffer
Function
RB0/INT0
bit0
TTL/ST(1)
Input/output pin or external interrupt 0 input. Internal software
programmable weak pull-up.
RB1/INT1
RB2/INT2
RB3/INT3
RB4
bit1
bit2
bit3
bit4
bit5
bit6
bit7
TTL/ST(1)
TTL/ST(1)
TTL/ST(1)
TTL
Input/output pin or external interrupt 1 input. Internal software
programmable weak pull-up.
Input/output pin or external interrupt 2 input. Internal software
programmable weak pull-up.
Input/output pin or external interrupt 3 input. Internal software
programmable weak pull-up.
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB6
TTL/ST(2)
TTL/ST(2)
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming clock.
RB7
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 8-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 000x 0000 000u
LATB
LATB Data Output Register
TRISB
INTCON
PORTB Data Direction Register
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF INT0IF
RBIF
RBIP
INTCON2
RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP
INT1IP INT3IE INT2IE INT1IE INT3IF
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
1111 1111 1111 1111
INTCON3 INT2IP
INT2IF INT1IF 1100 0000 1100 0000
DS30475A-page 92
Advanced Information
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PIC18CXX8
put, while other peripherals override the TRIS bit to make
a pin an input. The user should refer to the correspond-
ing peripheral section for the correct TRIS bit settings.
8.3
PORTC, TRISC and LATC Registers
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 8-3: INITIALIZING PORTC
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
Read-modify-write operations on the LATC register,
read and write the latched output value for PORTC.
CLRF
LATC
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC3:RC0 as inputs
; RC5:RC4 as outputs
; RC7:RC6 as inputs
PORTC is multiplexed with several peripheral functions
(Table 8-5). PORTC pins have Schmitt Trigger input
buffers.
MOVLW
MOVWF
0xCF
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
TRISC
FIGURE 8-6: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Peripheral Out Select
Peripheral Data Out
VDD
P
0
1
RD LATC
Q
Data Bus
D
I/O Pin
WR LATC
or
WR PORTC
Q
CK
Data Latch
N
D
Q
Q
VSS
WR TRISC
TRIS
CK
Override
TRIS Latch
Schmitt
Trigger
RD TRISC
Peripheral Enable
Q
D
EN
RD PORTC
Peripheral Data In
TRIS OVERRIDE
Peripheral
Pin
Override
Yes
RC0
RC1
RC2
RC3
Timer1 OSC for Timer1/Timer3
Timer1 OSC for Timer1/Timer3
—
Yes
No
2
Yes
SPI/I C Master Clock
2
RC4
Yes
I C Data Out
RC5
RC6
RC7
Yes
Yes
Yes
SPI Data Out
USART Async Xmit, Sync Clock
USART Sync Data Out
Note: I/O pins have diode protection to VDD and VSS.
2000 Microchip Technology Inc.
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DS30475A-page 93
PIC18CXX8
TABLE 8-5:
PORTC FUNCTIONS
Name
Bit# Buffer Type
Function
RC0/T1OSO/T13CKI
ST
Input/output port pin or Timer1 oscillator output or Timer1/Timer3 clock
input.
bit0
RC1/T1OSI
RC2/CCP1
ST
Input/output port pin or Timer1 oscillator input.
bit1
ST
Input/output port pin or Capture1 input/Compare1 output/PWM1
output.
bit2
RC3/SCK/SCL
RC4/SDI/SDA
ST
Input/output port pin or Synchronous Serial clock for SPI/I2C.
bit3
ST
Input/output port pin or SPI Data in (SPI mode) or Data I/O
(I2C mode).
bit4
RC5/SDO
ST
Input/output port pin or Synchronous Serial Port data output.
bit5
RC6/TX/CK
ST
Input/output port pin Addressable USART Asynchronous Transmit or
Addressable USART Synchronous Clock.
bit6
RC7/RX/DT
ST
Input/output port pin Addressable USART Asynchronous Receive or
Addressable USART Synchronous Data.
bit7
Legend: ST = Schmitt Trigger input
TABLE 8-6:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on
POR,
Value on all
other
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
PORTC
LATC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
LATC Data Output Register
PORTC Data Direction Register
TRISC
Legend: x= unknown, u= unchanged
DS30475A-page 94
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2000 Microchip Technology Inc.
PIC18CXX8
8.4
PORTD, TRISD and LATD Registers
FIGURE 8-7: PORTD BLOCK DIAGRAM
IN I/O PORT MODE
PORTD is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (=1) will make the corresponding PORTD pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISD bit (=0) will
make the corresponding PORTD pin an output (i.e., put
the contents of the output latch on the selected pin).
RD LATD
Data
Bus
D
Q
I/O Pin
WR LATD
or
WR PORTD
CK
Data Latch
Read-modify-write operations on the LATD register
reads and writes the latched output value for PORTD.
D
Q
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
Schmitt
Trigger
Input
WR TRISD
CK
TRIS Latch
Buffer
PORTD can be configured as an 8-bit wide micro-
processor port (parallel slave port), by setting control
bit PSPMODE (PSPCON register). In this mode, the
input buffers are TTL. See Section 9.0 for additional
information on the Parallel Slave Port (PSP).
RD TRISD
Q
D
EXAMPLE 8-4: INITIALIZING PORTD
EN
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
RD PORTD
CLRF
LATD
; Alternate method
; to clear output
; data latches
Note: I/O pins have diode protection to VDD and VSS.
MOVLW
MOVWF
0xCF
; Value used to
; initialize data
; direction
; Set RD3:RD0 as inputs
; RD5:RD4 as outputs
; RD7:RD6 as inputs
TRISD
2000 Microchip Technology Inc.
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DS30475A-page 95
PIC18CXX8
TABLE 8-7:
Name
PORTD FUNCTIONS
Bit#
Buffer Type
Function
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Input/output port pin or parallel slave port bit0.
Input/output port pin or parallel slave port bit1.
Input/output port pin or parallel slave port bit2.
Input/output port pin or parallel slave port bit3.
Input/output port pin or parallel slave port bit4.
Input/output port pin or parallel slave port bit5.
Input/output port pin or parallel slave port bit6.
Input/output port pin or parallel slave port bit7.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode.
TABLE 8-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on
POR,
Value on all
other
Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
PORTD
RD7 RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 ---- 0000 ----
LATD
LATD Data Output Register
PORTD Data Direction Register
IBF OBF IBOV PSPMODE
TRISD
PSPCON
—
—
—
—
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by PORTD.
DS30475A-page 96
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
8.5
PORTE, TRISE and LATE Registers
EXAMPLE 8-5: INITIALIZING PORTE
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
PORTE is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISE. Setting a
TRISE bit (=1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISE bit (=0) will
make the corresponding PORTE pin an output (i.e., put
the contents of the output latch on the selected pin).
CLRF
LATE
MOVLW
MOVWF
0x03
Read-modify-write operations on the LATE register
reads and writes the latched output value for PORTE.
TRISE
; Set RE1:RE0 as inputs
; RE7:RE2 as outputs
PORTE is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output. PORTE is multiplexed with several peripheral
functions (Table 8-9).
FIGURE 8-8: PORTE BLOCK DIAGRAM
Peripheral Out Select
Peripheral Data Out
VDD
0
1
P
RD LATE
Data Bus
D
Q
Q
(1)
I/O Pin
WR LATE
or
WR PORTE
CK
Data Latch
N
D
Q
Q
VSS
WR TRISE
TRIS
CK
Override
TRIS Latch
Schmitt
Trigger
RD TRISE
Peripheral Enable
Q
D
EN
RD PORTE
Peripheral Data In
TRIS OVERRIDE
Peripheral
Pin
Override
RE0
Yes
PSP
PSP
RE1
RE2
Yes
Yes
PSP
RE3
No
—
—
—
—
—
RE4
RE5
RE6
RE7
No
No
No
No
Note 1: I/O pins have diode protection to VDD and VSS.
2000 Microchip Technology Inc.
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DS30475A-page 97
PIC18CXX8
TABLE 8-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
RE0/RD
RE1/WR
RE2/CS
bit0
bit1
bit2
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
Input/output port pin or Read control input in Parallel Slave Port mode.
Input/output port pin or Write control input in Parallel Slave Port mode.
Input/output port pin or Chip Select control input in Parallel Slave Port
mode.
RE3
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
Input/output port pin.
RE4
Input/output port pin.
RE5
Input/output port pin.
RE6
Input/output port pin.
RE7/CCP2
Input/output port pin or Capture 2 input/Compare 2 output.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode.
TABLE 8-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on:
POR,
Value on all
Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
BOR
RESETS
TRISE
PORTE
LATE
PORTE Data Direction Control Register
Read PORTE pin/Write PORTE Data Latch
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 ---- 0000 ----
Read PORTE Data Latch/Write PORTE Data Latch
PSPCON IBF OBF IBOV PSPMODE
—
—
—
—
Legend: x= unknown, u= unchanged
DS30475A-page 98
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PIC18CXX8
8.6
PORTF, LATF, and TRISF Registers
EXAMPLE 8-6: INITIALIZING PORTF
CLRF
PORTF
; Initialize PORTF by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
PORTF is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISF. Setting a
TRISF bit (=1) will make the corresponding PORTF pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISF bit (=0) will
make the corresponding PORTF pin an output (i.e., put
the contents of the output latch on the selected pin).
CLRF
LATF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
0x07
CMCON
0x0F
ADCON1
0xCF
;
; Turn off comparators
;
; Set PORTF as digital I/O
; Value used to
; initialize data
; direction
; Set RF3:RF0 as inputs
; RF5:RF4 as outputs
; RF7:RF6 as inputs
Read-modify-write operations on the LATF register
reads and writes the latched output value for PORTF.
PORTF is multiplexed with several analog peripheral
functions including the A/D converter inputs and com-
parator inputs, outputs, and voltage reference.
MOVWF
TRISF
Note 1: On a Power-on Reset, the RF6:RF0 pins
are configured as inputs and read as ’0’.
2: To configure PORTF as digital I/O, turn off
comparators and set ADCON1 value.
FIGURE 8-9: PORTF RF1/AN6/C2OUT, RF2/AN5/C1OUT BLOCK DIAGRAM
PORT/Comparator Select
Comparator Data Out
VDD
P
0
1
RD LATF
Q
Data Bus
D
I/O Pin
WR LATF
or
WR PORTF
Q
CK
Data Latch
N
D
Q
Q
VSS
WR TRISF
CK
Analog
TRIS Latch
Input
Mode
Schmitt
Trigger
RD TRISF
Q
D
EN
RD PORTF
To A/D Converter
Note:
I/O pins have diode protection to VDD and VSS.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 99
PIC18CXX8
FIGURE 8-10: RF6:RF3 AND RF0 PINS
BLOCK DIAGRAM
FIGURE 8-11: RF7 PIN BLOCK DIAGRAM
RD LATF
Data
Bus
RD LATF
D
Q
Data
Bus
D
Q
I/O pin
WR LATF
or
WR PORTF
CK
Data Latch
VDD
P
WR LATF
or
WR PORTF
CK
Q
D
Q
Data Latch
Schmitt
Trigger
Input
N
I/O Pin
D
Q
WR TRISF
CK
TRIS Latch
Buffer
WR TRISF
VSS
Analog
CK
TRIS Latch
Q
Input
Mode
RD TRISF
ST
RD TRISF
Q
Q
D
Input
Buffer
D
EN
RD PORTF
EN
RD PORTF
Note:
I/O pins have diode protection to VDD and VSS.
To A/D Converter or Comparator Input
Note: I/O pins have diode protection to VDD and VSS.
TABLE 8-11: PORTF FUNCTIONS
Name
Bit#
Buffer Type
Function
RF0/AN5
bit0
ST
ST
ST
ST
ST
ST
Input/output port pin or analog input.
RF1/AN6/C2OUT bit1
RF2/AN7/C1OUT bit2
Input/output port pin or analog input or comparator 2 output.
Input/output port pin or analog input or comparator 1 output.
Input/output port pin or analog input or comparator input.
Input/output port pin or analog input or comparator input.
RF3/AN8
RF4/AN9
bit3
bit4
bit5
RF5/AN10/
CVREF
Input/output port pin or analog input or comparator input or comparator
reference output.
RF6/AN11
RF7
bit6
bit7
ST
ST
Input/output port pin or analog input or comparator input.
Input/output port pin.
Legend: ST = Schmitt Trigger input
TABLE 8-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Value on:
POR,
BOR
Value on all
other RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISF
PORTF Data Direction Control Register
Read PORTF pin / Write PORTF Data Latch
Read PORTF Data Latch/Write PORTF Data Latch
1111 1111
xxxx xxxx
0000 0000
1111 1111
uuuu uuuu
uuuu uuuu
--00 0000
0000 0000
PORTF
LATF
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000
CMCON C2OUT C1OUT C2INV C1INV
CIS
CM2
CM1
CM0 0000 0000
Legend: x= unknown, u= unchanged
DS30475A-page 100
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
8.7
PORTG, LATG, and TRISG Registers
EXAMPLE 8-7: INITIALIZING PORTG
CLRF
PORTG
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
PORTG is a 5-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISG. Setting a
TRISG bit (=1) will make the corresponding PORTG pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISG bit (=0) will
make the corresponding PORTG pin an output (i.e., put
the contents of the output latch on the selected pin).
CLRF
LATG
MOVLW
MOVWF
0x04
Read-modify-write operations on the LATG register
read and write the latched output value for PORTG.
TRISG
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as outputs
Pins RG0-RG2 on PORTG are multiplexed with the
CAN peripheral. Refer to "CAN Module", Section 17.0
for proper settings of TRISG when CAN is enabled.
FIGURE 8-12: RG0/CANTX0 PIN BLOCK DIAGRAM
OPMODE2:OPMODE0=000
TXD
ENDRHI
0
VDD
RD LATG
1
Data Bus
D
Q
P
WR PORTG or
WR LATG
CK
Q
Data Latch
I/O Pin
D
Q
N
WR TRISG
RD TRISG
CK
Q
VSS
TRIS Latch
OPMODE2:OPMODE0 = 000
Schmitt
Trigger
Q
D
EN
RD PORTG
Note: I/O pins have diode protection to VDD and VSS.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 101
PIC18CXX8
FIGURE 8-13: RG1/CANTX1 PIN BLOCK DIAGRAM
TX1SRC
OPMODE2:OPMODE0=000
TX1EN
TXD
0
1
CANCLK
ENDRHI
0
1
VDD
P
RD LATG
Data Bus
D
Q
WR PORTG or
WR LATG
CK
Q
Data Latch
I/O Pin
D
Q
N
WR TRISG
RD TRISG
CK
Q
TRIS Latch
VSS
OPMODE2:OPMODE0 = 000
Schmitt
Trigger
Q
D
EN
RD PORTG
Note: I/O pins have diode protection to VDD and VSS.
FIGURE 8-14: RG2/CANRX PIN BLOCK
DIAGRAM
FIGURE 8-15: RG4:RG3 PINS BLOCK
DIAGRAM
RD LATG
RD LATG
Data
Bus
Data
Bus
D
Q
D
Q
I/O Pin
I/O Pin
WR LATG
or
WR PORTG
WR LATG
or
WR PORTG
CK
CK
Data Latch
Data Latch
D
Q
D
Q
Schmitt
Trigger
Input
Schmitt
Trigger
Input
WR TRISG
WR TRISG
CK
CK
TRIS Latch
Buffer
Buffer
TRIS Latch
RD TRISG
RD TRISG
Q
D
Q
D
EN
EN
RD PORTG
CANRX
Note: I/O pins have diode protection to VDD and VSS.
RD PORTG
Note: I/O pins have diode protection to VDD and VSS.
DS30475A-page 102
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 8-13: PORTG FUNCTIONS
Name
Bit#
Buffer Type
Function
RG0/CANTX0
RG1/CANTX1
bit0
bit1
ST
ST
Input/output port pin or CAN bus transmit output.
Input/output port pin or CAN bus complimentary transmit output or CAN
bus bit time clock.
RG2/CANRX
RG3
bit2
bit3
bit4
ST
ST
ST
Input/output port pin or CAN bus receive input.
Input/output port pin.
RG4
Input/output port pin.
Legend: ST = Schmitt Trigger input
Note: Refer to "CAN Module", Section 17.0 for usage of CAN pin functions.
TABLE 8-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Value on:
POR,
Value on all
other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
BOR
RESETS
TRISG
PORTG
LATG
PORTG Data Direction Control Register
---1 1111
---x xxxx
---x xxxx
0000 ----
---1 1111
---u uuuu
---u uuuu
0000 ----
Read PORTG pin / Write PORTG Data Latch
Read PORTG Data Latch/Write PORTG Data Latch
CIOCON TX1SRC TX1EN ENDRHI CANCAP
—
—
—
—
Legend: x= unknown, u= unchanged
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 103
PIC18CXX8
8.8
PORTH, LATH, and TRISH Registers
EXAMPLE 8-8: INITIALIZING PORTH
CLRF
PORTH
; Initialize PORTH by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
;
Note: This port is available on PIC18C858.
PORTH is a 5-bit wide, bi-directional port available only
on the PIC18C858 devices. The corresponding Data
Direction register is TRISH. Setting a TRISH bit (=1)
will make the corresponding PORTH pin an input (i.e.,
put the corresponding output driver in a hi-impedance
mode). Clearing a TRISH bit (=0) will make the corre-
sponding PORTH pin an output (i.e., put the contents
of the output latch on the selected pin).
CLRF
LATH
MOVLW
MOVWF
MOVLW
0x0F
ADCON1
0xCF
;
; Value used to
; initialize data
; direction
MOVWF
TRISH
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
Read-modify-write operations on the LATH register
read and write the latched output value for PORTH.
Pins RH0-RH3 on the PIC18C858 are bi-directional I/O
pins with ST input buffers. Pins RH4-RH7 on all devices
are multiplexed with A/D converter inputs.
FIGURE 8-17: RH7:RH4 PINS BLOCK
DIAGRAM
Note: On a Power-on Reset, the RH7:RH4 pins
are configured as inputs and read as ’0’.
FIGURE 8-16: RH3:RH0 PINS BLOCK
DIAGRAM
RD LATH
Data
Bus
D
Q
VDD
P
WR LATH
or
WR PORTH
CK
Q
RD LATH
Data Bus
D
Q
Q
Data Latch
VDD
P
WR LATH
or
CK
N
I/O Pin
D
Q
WR PORTH
Data Latch
WR TRISH
VSS
CK
Q
I/O Pin
D
Q
Q
Analog
TRIS Latch
Input
WR TRISH
N
Mode
CK
TRIS Latch
VSS
ST
Input
Buffer
RD TRISH
RD TRISH
Schmitt
Trigger
Q
D
Q
D
EN
EN
RD
PORTH
RD PORTH
To A/D Converter
Note:
I/O pins have diode protection to VDD and VSS.
Note:
I/O pins have diode protection to VDD and VSS.
DS30475A-page 104
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 8-15: PORTH FUNCTIONS
Name
Bit#
Buffer Type
Function
RH0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
ST
Input/output port pin.
Input/output port pin.
Input/output port pin.
Input/output port pin.
RH1
RH2
RH3
RH4/AN12
RH5/AN13
RH6/AN14
RH7/AN15
Input/output port pin or analog input channel 12.
Input/output port pin or analog input channel 13.
Input/output port pin or analog input channel 14.
Input/output port pin or analog input channel 15.
Legend: ST = Schmitt Trigger input
TABLE 8-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Value on:
POR,
Value on all
other
Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
TRISH
PORTH
LATH
PORTH Data Direction Control Register
Read PORTH pin/Write PORTH Data Latch
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Read PORTH Data Latch/Write PORTH Data Latch
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1
ADCON1
—
—
PCFG0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, - = unimplemented
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 105
PIC18CXX8
8.9
PORTJ, LATJ, and TRISJ Registers
EXAMPLE 8-9: INITIALIZING PORTJ
CLRF
PORTJ
; Initialize PORTJ by
; clearing output
; data latches
Note: This port is available on PIC18C858.
PORTJ is an 8-bit wide, bi-directional port available
only on the PIC18C858 devices. The corresponding
Data Direction register is TRISJ. Setting a TRISJ bit
(=1) will make the corresponding PORTJ pin an input
CLRF
LATJ
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as outputs
; RJ7:RJ6 as inputs
MOVLW
MOVWF
0xCF
(i.e., put the corresponding output driver in
a
hi-impedance mode). Clearing a TRISJ bit (=0) will
make the corresponding PORTJ pin an output (i.e., put
the contents of the output latch on the selected pin).
TRISJ
Read-modify-write operations on the LATJ register
read and write the latched output value for PORTJ.
PORTJ on the PIC18C858 is an 8-bit port with Schmitt
Trigger input buffers. Each pin is individually config-
urable as an input or output.
FIGURE 8-18: PORTJ BLOCK DIAGRAM
RD LATJ
Data Bus
D
Q
VDD
P
WR LATJ
or
CK
Q
WR PORTJ
Data Latch
I/O Pin
N
D
Q
Q
VSS
WR TRISJ
CK
TRIS Latch
RD TRISJ
Schmitt
Trigger
Q
D
EN
RD PORTJ
Note:
I/O pins have diode protection to VDD and VSS.
DS30475A-page 106
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 8-17: PORTJ FUNCTIONS
Name
Bit#
Buffer Type
Function
RJ0
RJ1
RJ2
RJ3
RJ4
RJ5
RJ6
RJ7
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
Input/output port pin.
Input/output port pin.
Input/output port pin.
Input/output port pin.
Input/output port pin.
Input/output port pin.
Input/output port pin.
Input/output port pin.
Legend: ST = Schmitt Trigger input, TTL = TTL input
TABLE 8-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Value on:
POR,
Value on all
other
Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
TRISJ
PORTJ Data Direction Control Register
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
PORTJ Read PORTJ pin/Write PORTJ Data Latch
LATJ Read PORTJ Data Latch/Write PORTJ Data Latch
Legend: x= unknown, u= unchanged
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 107
PIC18CXX8
8.10
PORTK, LATK, and TRISK Registers
FIGURE 8-19: PORTK BLOCK DIAGRAM
Note: This port is available on PIC18C858.
RD LATK
PORTK is an 8-bit wide, bi-directional port available
only on the PIC18C858 devices. The corresponding
Data Direction register is TRISK. Setting a TRISK bit
(=1) will make the corresponding PORTK pin an input
Data
Bus
D
Q
I/O Pin
WR LATK
or
WR PORTK
CK
Data Latch
(i.e., put the corresponding output driver in
a
hi-impedance mode). Clearing a TRISK bit (=0) will
make the corresponding PORTK pin an output (i.e., put
the contents of the output latch on the selected pin).
D
Q
Schmitt
Trigger
Input
WR TRISK
Read-modify-write operations on the LATK register
read and write the latched output value for PORTK.
CK
TRIS Latch
Buffer
PORTK is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
RD TRISK
EXAMPLE 8-10: INITIALIZING PORTK
Q
D
CLRF
PORTK
; Initialize PORTK by
; clearing output
; data latches
EN
RD PORTK
CLRF
LATK
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
0xCF
; Value used to
; initialize data
; direction
; Set RK3:RK0 as inputs
; RK5:RK4 as outputs
; RK7:RK6 as inputs
Note:
I/O pins have diode protection to VDD and VSS.
TRISK
TABLE 8-19: PORTK FUNCTIONS
Name
Bit#
Buffer Type
Function
RK0
RK1
RK2
RK3
RK4
RK5
RK6
RK7
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
ST
Input/output port pin.
Input/output port pin.
Input/output port pin.
Input/output port pin.
Input/output port pin.
Input/output port pin.
Input/output port pin.
Input/output port pin.
Legend: ST = Schmitt Trigger input
TABLE 8-20: SUMMARY OF REGISTERS ASSOCIATED WITH PORTK
Value on:
POR, BOR
Value on all
other RESETS
Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISK PORTK Data Direction Control Register
PORTK Read PORTK pin / Write PORTK Data Latch
LATK Read PORTK Data Latch/Write PORTK Data Latch
1111 1111
xxxx xxxx
xxxx xxxx
1111 1111
uuuu uuuu
uuuu uuuu
Legend: x= unknown, u= unchanged
DS30475A-page 108
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 9-1: PORTD AND PORTE BLOCK
DIAGRAM
9.0
PARALLEL SLAVE PORT
The Parallel Slave Port is an 8-bit parallel interface for
transferring data between the PIC18CXX8 device and
an external device.
(PARALLEL SLAVE PORT)
Data Bus
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit PSPMODE
(PSPCON register) is set. In Slave mode, it is asyn-
chronously readable and writable by the external world
through RD control input pin RE0/RD and WR control
input pin RE1/WR.
D
Q
RDx Pin
WR LATD
or
WR PORTD
CK
Data Latch
TTL
Q
D
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set).
RD PORTD
EN
RD LATD
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
The PORTE I/O pins become control inputs for the
microprocessor port when bit PSPMODE (PSPCON
Register) is set. In this mode, the user must make sure
that the TRISE<2:0> bits are set (pins are configured
as digital inputs). In this mode, the input buffers are
TTL.
Read
RD
CS
WR
TTL
Chip Select
TTL
Write
TTL
Note:
I/O pins have diode protection to VDD and VSS.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 109
PIC18CXX8
REGISTER 9-1:
PSPCON REGISTER
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
U-0
U-0
U-0
OBF
PSPMODE
—
—
—
—
bit 7
bit 0
bit 7
bit 6
bit 5
IBF: Input Buffer Full Status bit
1= A word has been received and waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1= A write occurred when a previously input word has not been read
(must be cleared in software)
0= No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0= General purpose I/O mode
bit 3-0
Unimplemented: Read as ’0’
Legend
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
DS30475A-page 110
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 9-2:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
FIGURE 9-3: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
TABLE 9-1:
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on all
other
Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
RESETS
PORTD Port data latch when written; port pins when read
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
LATD
LATD Data Output Bits
TRISD
PORTE
LATE
PORTD Data Direction Bits
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
LATE Data Output Bits
TRISE
INTCON
PORTE Data Direction Bits
GIE/
PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEL
RBIF 0000 000x 0000 000u
GIEH
PIR1
PIE1
IPR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
Legend: x= unknown, u= unchanged, - = unimplemented, read as ’0’.
Shaded cells are not used by the Parallel Slave Port.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 111
PIC18CXX8
NOTES:
DS30475A-page 112
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Register 10-1 shows the Timer0 Control register
(T0CON).
10.0 TIMER0 MODULE
The Timer0 module has the following features:
Figure 10-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 10-1 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
• Software selectable as an 8-bit or 16-bit
timer/counter
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt on overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
• Edge select for external clock
The T0CON register is a readable and writable register
that controls all the aspects of Timer0, including the
prescale selection.
Note: Timer0 is enabled on POR.
REGISTER 10-1: T0CON REGISTER
R/W-1
TMR0ON
bit 7
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
T08BIT
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-bit/16-bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 prescale value
110= 1:128 prescale value
101= 1:64 prescale value
100= 1:32 prescale value
011= 1:16 prescale value
010= 1:8 prescale value
001= 1:4 prescale value
000= 1:2 prescale value
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 113
PIC18CXX8
FIGURE 10-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
FOSC/4
0
1
8
0
Sync with
Internal
Clocks
TMR0L
Programmable
Prescaler
RA4/T0CKI
Pin(2)
1
(2 TCY delay)
T0SE
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS(1)
Note 1:
2:
Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
I/O pins have diode protection to VDD and VSS.
FIGURE 10-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
FOSC/4
0
1
0
1
Sync with
Internal
Clocks
Set Interrupt
Flag bit TMR0IF
on Overflow
TMR0
High Byte
TMR0L
T0CKI Pin(2)
T0SE
Programmable
Prescaler
8
(2 TCY delay)
3
Read TMR0L
T0PS2, T0PS1, T0PS0
Write TMR0L
T0CS(1)
PSA
8
8
TMR0H
8
Data Bus<7:0>
Note 1:
2:
Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
I/O pins have diode protection to VDD and VSS.
DS30475A-page 114
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
10.1
Timer0 Operation
10.2
Prescaler
Timer0 can operate as a timer or as a counter.
An 8-bit counter is available as a prescaler for the
Timer0 module. The prescaler is not readable or
writable.
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0L reg-
ister is written, the increment is inhibited for the follow-
ing two instruction cycles. The user can work around
this by writing an adjusted value to the TMR0L register.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the ris-
ing edge. Restrictions on the external clock input are
discussed below.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF TMR0,
MOVWF TMR0, BSF TMR0, x.... etc.) will clear the
prescaler count.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count but will not change the prescaler
assignment.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
10.2.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software con-
trol (i.e., it can be changed “on-the-fly” during program
execution).
2000 Microchip Technology Inc.
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DS30475A-page 115
PIC18CXX8
10.3
Timer0 Interrupt
10.4
16-Bit Mode Timer Reads and Writes
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode or FFFFh
to 0000h in 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IF bit must be cleared in soft-
ware by the Timer0 module interrupt service routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from SLEEP, since the
timer is shut off during SLEEP.
Timer0 can be set in 16-bit mode by clearing T0CON
T08BIT. Registers TMR0H and TMR0L are used to
access 16-bit timer value.
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 10-1). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16-bits of Timer0 without
having to verify that the read of the high and low byte
were valid due to a rollover between successive reads
of the high and low byte.
A write to the high byte of Timer0 must also take place
through the TMR0H buffer register. Timer0 high byte is
updated with the contents of buffered value of TMR0H,
when a write occurs to TMR0L. This allows all 16 bits
of Timer0 to be updated at once.
TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0
Value on
all other
Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 POR, BOR RESETS
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
TMR0L
Timer0 Module’s Low Byte Register
TMR0H Timer0 Module’s High Byte Register
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
0000 000x 0000 000u
1111 1111 1111 1111
T0CON
TRISA
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2 T0PS1 T0PS0
—
PORTA Data Direction Register(1)
--11 1111 --11 1111
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator
modes, they are disabled and read as ‘0’.
DS30475A-page 116
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Register 11-1 shows the Timer1 control register. This
register controls the operating mode of the Timer1
module as well as contains the Timer1 oscillator enable
bit (T1OSCEN). Timer1 can be enabled/disabled by
setting/clearing control bit TMR1ON (T1CON register).
11.0 TIMER1 MODULE
The Timer1 module timer/counter has the following fea-
tures:
• 16-bit timer/counter
(Two 8-bit registers: TMR1H and TMR1L)
Figure 11-1 is a simplified block diagram of the Timer1
module.
• Readable and writable (both registers)
• Internal or external clock select
Note: Timer1 is disabled on POR.
• Interrupt on overflow from FFFFh to 0000h
• RESET from CCP module special event trigger
REGISTER 11-1: T1CON REGISTER
R/W-0
RD16
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register Read/Write of TImer1 in one 16-bit operation
0= Enables register Read/Write of Timer1 in two 8-bit operations
bit 6
Unimplemented: Read as '0'
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 Oscillator is enabled
0= Timer1 Oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2000 Microchip Technology Inc.
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DS30475A-page 117
PIC18CXX8
When TMR1CS is clear, Timer1 increments every
instruction cycle. When TMR1CS is set, Timer1 incre-
ments on every rising edge of the external clock input
or the Timer1 oscillator, if enabled.
11.1
Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON register).
Timer1 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 14.0).
FIGURE 11-1: TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Synchronized
TMR1
0
Clock Input
CLR
TMR1L
Flag Bit
TMR1H
T1OSC
1
TMR1ON
On/Off
T1SYNC
1
T13CKI/T1OSO
T1OSI
Synchronize
det
T1OSCEN
Enable
Oscillator
Prescaler
1, 2, 4, 8
FOSC/4
(1)
Internal
Clock
0
2
SLEEP Input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
FIGURE 11-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Special Event Trigger
Read TMR1L
Synchronized
0
TMR1IF
Overflow
Interrupt
TMR1
8
Clock Input
Timer 1
high byte
TMR1L
Flag bit
1
TMR1ON
On/Off
T1SYNC
T1OSC
T13CKI/T1OSO
T1OSI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
Fosc/4
Internal
Clock
0
(1)
2
SLEEP Input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
DS30475A-page 118
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
11.2
Timer1 Oscillator
11.4
Resetting Timer1 using a CCP Trigger
Output
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON register). The
oscillator is a low power oscillator rated up to 200 kHz.
It will continue to run during SLEEP. It is primarily
intended for a 32 kHz crystal. Table 11-1 shows the
capacitor selection for the Timer1 oscillator.
If the CCP module is configured in Compare mode
to generate “special event trigger"
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
a
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR registers).
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
Timer1 must be configured for either timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
TABLE 11-1: CAPACITOR SELECTION FOR
THE ALTERNATE OSCILLATOR
Osc Type
Freq
C1
C2
TBD(1)
TBD(1)
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
LP
32 kHz
Crystal to be Tested:
32.768 kHz Epson C-001R32.768K-A
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair, effectively becomes the period register for
Timer1.
20 PPM
Note 1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
11.5
Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 11-2). When the RD16 control bit (T1CON
register) is set, the address for TMR1H is mapped to a
buffer register for the high byte of Timer1. A read from
TMR1L will load the contents of the high byte of Timer1
into the Timer1 high byte buffer. This provides the user
with the ability to accurately read all 16 bits of Timer1,
without having to determine whether a read of the high
byte followed by a read of the low byte is valid, due to
a rollover between reads.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
4: Capacitor values are for design guidance
only.
11.3
Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit TMR1IF (PIR regis-
ters). This interrupt can be enabled/disabled by set-
ting/clearing TMR1 interrupt enable bit TMR1IE (PIE
registers).
A write to the high byte of Timer1 must also take place
through the TMR1H buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 high byte buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 119
PIC18CXX8
TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PIE1
IPR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR2IF
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IP 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
TXIE
TXIP
CCP1IE TMR2IE
CCP1IP TMR2IP
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
T1CON
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
DS30475A-page 120
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
12.1
Timer2 Operation
12.0 TIMER2 MODULE
The Timer2 module timer has the following features:
Timer2 can be used as the PWM time-base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
RESET. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON Register). The match
output of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit TMR2IF, PIR regis-
ters).
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
• SSP module optional use of TMR2 output to gen-
erate clock shift
The prescaler and postscaler counters are cleared
when any of the following occurs:
Register 12-1 shows the Timer2 Control register.
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON register) to minimize power consumption.
Figure 12-1 is a simplified block diagram of the Timer2
module. The prescaler and postscaler selection of
Timer2 are controlled by this register.
• A write to the TMR2 register
• A write to the T2CON register
• Any device RESET (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset)
TMR2 is not cleared when T2CON is written.
Note: Timer2 is disabled on POR.
REGISTER 12-1: T2CON REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2000 Microchip Technology Inc.
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DS30475A-page 121
PIC18CXX8
12.2
Timer2 Interrupt
12.3
Output of TMR2
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The output of TMR2 (before the postscaler) is a clock
input to the Synchronous Serial Port module, which
optionally uses it to generate the shift clock.
FIGURE 12-1: TIMER2 BLOCK DIAGRAM
Sets Flag
TMR2
bit TMR2IF
Output(1)
Prescaler
RESET
TMR2
FOSC/4
1:1, 1:4, 1:16
Postscaler
2
Comparator
1:16
1:1 to
EQ
T2CKPS1:T2CKPS0
4
PR2
TOUTPS3:TOUTPS0
TMR2 register output can be software selected by the SSP Module as a baud clock.
Note 1:
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL
TMR0IE
RCIF
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
0000 000x
0000 0000
0000 0000
0000 0000
0000 0000
-000 0000
1111 1111
0000 000u
0000 0000
0000 0000
0000 0000
0000 0000
-000 0000
1111 1111
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
TMR1IF
TMR1IE
TMR1IP
PIE1
RCIE
TXIE
TXIP
IPR1
RCIP
TMR2
T2CON
PR2
Timer2 module’s register
TOUTPS3
Timer2 Period Register
—
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
Legend: x= unknown, u= unchanged, -= unimplemented, read as ’0’. Shaded cells are not used by the Timer2 module.
DS30475A-page 122
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Figure 13-1 is a simplified block diagram of the Timer3
module.
13.0 TIMER3 MODULE
The Timer3 module timer/counter has the following
features:
Register 13-1 shows the Timer3 Control Register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
• 16-bit timer/counter
(Two 8-bit registers: TMR3H and TMR3L)
Register 11-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 oscillator
enable bit (T1OSCEN), which can be a clock source for
Timer3.
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• RESET from CCP module trigger
Note: Timer3 is disabled on POR.
REGISTER 13-1: T3CON REGISTER
R/W-0
RD16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1
T3SYNC TMR3CS TMR3ON
bit 0
bit 7
bit 7
RD16: 16-bit Read/Write Mode Enable
1= Enables register Read/Write of Timer3 in one 16-bit operation
0= Enables register Read/Write of Timer3 in two 8-bit operations
bit 6,3
T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x= Timer3 is the clock source for compare/capture CCP modules
01= Timer3 is the clock source for compare/capture of CCP2,
Timer1 is the clock source for compare/capture of CCP1
00= Timer1 is the clock source for compare/capture CCP modules
bit 5-4
bit 2
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3)
When TMR3CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
bit 0
TMR3CS: Timer3 Clock Source Select bit
1= External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling
edge)
0= Internal clock (Fosc/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2000 Microchip Technology Inc.
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DS30475A-page 123
PIC18CXX8
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
13.1
Timer3 Operation
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON register).
Timer3 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 13.0).
FIGURE 13-1: TIMER3 BLOCK DIAGRAM
CCP Special Trigger
TMR3IF
Overflow
Interrupt
T3CCPx
Synchronized
0
Clock Input
Flag bit
CLR
TMR3L
TMR3H
T1OSC
1
TMR3ON
on/off
T3SYNC
T1OSO/
T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Fosc/4
Internal
0
(1)
T1OSI
Oscillator
Clock
2
SLEEP Input
TMR3CS
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 13-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
CCP Special Trigger
T3CCPx
Synchronized
Clock Input
8
TMR3
TMR3IF Overflow
Interrupt Flag
bit
0
CLR
TMR3H
TMR3L
1
To Timer1 Clock Input
TMR3ON
On/Off
T3SYNC
T1OSC
T1OSO/
T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
T1OSI
2
SLEEP Input
T3CKPS1:T3CKPS0
TMR3CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS30475A-page 124
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PIC18CXX8
13.2
Timer1 Oscillator
13.4
Resetting Timer3 Using a CCP Trigger
Output
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN bit (T1CON Register). The oscillator is
a low power oscillator rated up to 200 kHz. Refer to
“Timer1 Module”, Section 11.0 for Timer1 oscillator
details.
If the CCP module is configured in Compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer3.
Note: The special event triggers from the CCP
module will not set interrupt flag bit
TMR3IF (PIR registers).
13.3
Timer3 Interrupt
Timer3 must be configured for either timer or Synchro-
nized Counter mode to take advantage of this feature. If
Timer3 is running in Asynchronous Counter mode, this
RESET operation may not work. In the event that a write
to Timer3 coincides with a special event trigger from
CCP1, the write will take precedence. In this mode of
operation, the CCPR1H:CCPR1L registers pair
becomes the period register for Timer3. Refer to
“Capture/Compare/PWM (CCP) Modules”, Section 14.0
for CCP details.
The TMR3 Register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR3IF (PIR Reg-
isters). This interrupt can be enabled/disabled by set-
ting/clearing TMR3 interrupt enable bit TMR3IE (PIE
Registers).
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR2
—
—
—
CMIF
CMIE
CMIP
—
—
—
—
—
—
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF
CCP2IF -0-- 0000 -0-- 0000
PIE2
TMR3IE CCP2IE -0-- 0000 -0-- 0000
TMR3IP CCP2IP -0-- 0000 -0-- 0000
IPR2
TMR3L
TMR3H
T1CON
T3CON
Holding register for the Least Significant Byte of the 16-bit TMR3 register
Holding register for the Most Significant Byte of the 16-bit TMR3 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
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PIC18CXX8
NOTES:
DS30475A-page 126
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2000 Microchip Technology Inc.
PIC18CXX8
Section 17.0 for CAN operation.) Therefore, operation
of a CCP module in the following sections is described
with respect to CCP1.
14.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register that can operate as a 16-bit capture
register, as a 16-bit compare register, or as a PWM
Duty Cycle register. Table 14-1 shows the timer
resources of the CCP module modes.
Table 14-2 shows the interaction of the CCP modules.
Register 14-1 shows the CCPx Control registers
(CCPxCON). For the CCP1 module, the register is
called CCP1CON and for the CCP2 module, the regis-
ter is called CCP2CON.
The operation of CCP1 is identical to that of CCP2, with
the exception of the special event trigger and the CAN
message timestamp received. (Refer to “CAN Module”,
REGISTER 14-1: CCP1CON REGISTER
CCP2CON REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCP1CON
CCP2CON
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 0
bit 7
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DC2B1
DC2B0
CCP2M3 CCP2M2 CCP2M1 CCP2M0
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as '0'
DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0
Capture Mode:
Unused
Compare Mode:
Unused
PWM Mode:
These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000= Capture/Compare/PWM off (resets CCPx module)
0001= Reserved
0010= Compare mode, toggle output on match (CCPxIF bit is set)
0011= Capture mode, CAN message received (CCP1 only)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode,
Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set)
1001= Compare mode,
Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set)
1010= Compare mode,
Generate software interrupt on compare match
(CCPIF bit is set, CCP pin is unaffected)
1011= Compare mode,
Trigger special event (CCPIF bit is set, reset TMR1 or TMR3)
11xx= PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
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PIC18CXX8
14.1
CCP1 Module
14.3
Capture Mode
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 or TMR3 registers when an
event occurs on pin RC2/CCP1. An event is defined as:
• every falling edge
• every rising edge
14.2
CCP2 Module
• every 4th rising edge
• every 16th rising edge
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR registers) is set. It
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old cap-
tured value will be lost.
TABLE 14-1: CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
14.3.1 CCP PIN CONFIGURATION
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
Note: If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
14.3.2 TIMER1/TIMER3 MODE SELECTION
The timers used with the capture feature (either Timer1
and/or Timer3) must be running in Timer mode or Syn-
chronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer
used with each CCP module is selected in the T3CON
register.
TABLE 14-2: INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Capture
TMR1 or TMR3 time-base. Time-base can be different for each CCP.
Compare
The compare could be configured for the special event trigger, which clears either TMR1
or TMR3, depending upon which time-base is used.
Compare
Compare
The compare(s) could be configured for the special event trigger, which clears TMR1 or
TMR3 depending upon which time-base is used.
PWM
PWM
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
Capture
Compare
None
None
DS30475A-page 128
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2000 Microchip Technology Inc.
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14.3.3 SOFTWARE INTERRUPT
14.3.5 CAN MESSAGE RECEIVED
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE registers) clear to avoid false interrupts
and should clear the flag bit CCP1IF, following any
such change in operating mode.
The CAN capture event occurs when a message is
received in either receive buffer. The CAN module pro-
vides a rising edge to the CCP module to cause a cap-
ture event. This feature is provided to time-stamp the
received CAN messages.
14.3.4 CCP PRESCALER
EXAMPLE 14-1: CHANGING BETWEEN
CAPTURE PRESCALERS
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
CLRF
CCP1CON, F ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF CCP1CON
; Load CCP1CON with
; this value
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 14-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
FIGURE 14-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
CCPR1L
TMR1L
CCP1 Pin
Set Flag bit CCP1IF
T3CCP2
TMR3
Enable
Prescaler
÷ 1, 4, 16
RXB0IF or
RXB1IF
CCPR1H
TMR1
Enable
CCP1CON<3:0>
and
edge detect
T3CCP2
TMR1H
CCP1M3:CCP1M0
Q’s
Set Flag bit CCP2IF
T3CCP1
TMR3H
TMR3L
CCPR2L
TMR1L
T3CCP2
TMR3
Enable
Prescaler
÷ 1, 4, 16
CCP2 Pin
CCPR2H
TMR1
Enable
and
edge detect
T3CCP2
T3CCP1
TMR1H
CCP2M3:CCP2M0
Q’s
Note:
I/O pins have diode protection to VDD and VSS.
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14.4.2 TIMER1/TIMER3 MODE SELECTION
14.4
Compare Mode
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the TMR1
register pair value, or the TMR3 register pair value.
When a match occurs, the RC2/CCP1 (RC1/CCP2) pin
can have one of the following actions:
14.4.3 SOFTWARE INTERRUPT MODE
• Driven high
When Generate Software Interrupt is chosen, the
CCP1 pin is not affected. Only a CCP Interrupt is gen-
erated (if enabled).
• Driven low
• Toggle output (high to low or low to high)
• Remains unchanged
14.4.4 SPECIAL EVENT TRIGGER
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit CCP1IF (CCP2IF) is set.
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
14.4.1 CCP PIN CONFIGURATION
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
The special trigger output of CCPx resets either the
TMR1 or TMR3 register pair. Additionally, the CCP2
Special Event Trigger will start an A/D conversion if the
A/D module is enabled.
Note: The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
FIGURE 14-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit)
Set bit GO/DONE, which starts an A/D conversion (CCP2 only)
Special Event Trigger
Set Flag bit CCP1IF
CCPR1H CCPR1L
Comparator
Q
S
R
Output
Logic
match
RC2/CCP1
Pin
TRISC<2>
Output Enable
1
CCP1M3:CCP1M0
Mode Select
0
T3CCP2
TMR1H TMR1L
TMR3H TMR3L
Special Event Trigger
Set Flag bit CCP2IF
Match
T3CCP1
T3CCP2
0
1
Q
S
R
Output
Logic
Comparator
RC1/CCP2
Pin
TRISC<1>
Output Enable
CCPR2H CCPR2L
CCP2M3:CCP2M0
Mode Select
Note:
I/O pins have diode protection to VDD and VSS.
DS30475A-page 130
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PIC18CXX8
TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF INT0IF
RBIF 0000 000x 0000 000u
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
1111 1111 1111 1111
PIE1
IPR1
TRISC
TMR1L
TMR1H
T1CON
PORTC Data Direction Register
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
CCPR1L Capture/Compare/PWM register1 (LSB)
CCPR1H Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2L Capture/Compare/PWM register2 (LSB)
CCPR2H Capture/Compare/PWM register2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2CON
PIR2
—
—
—
—
—
DC2B1
—
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
CMIF
CMIE
CMIP
—
—
—
BCLIF
BCLIE
BCLIP
LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000
LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000
LVDIP TMR3IP CCP2IP -0-- 0000 -0-- 0000
PIE2
—
IPR2
—
TMR3L
TMR3H
T3CON
Holding register for the Least Significant Byte of the 16-bit TMR3 register
Holding register for the Most Significant Byte of the 16-bit TMR3 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
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14.5.1 PWM PERIOD
14.5
PWM Mode
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
Figure 14-3 shows a simplified block diagram of the
CCP module in PWM mode.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 14.5.3.
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note: The Timer2 postscaler (see Section 12.0)
is not used in the determination of the
PWM frequency. The postscaler could be
used to have a servo update rate at a dif-
ferent frequency than the PWM output.
FIGURE 14-3: SIMPLIFIED PWM BLOCK
DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L (Master)
14.5.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1H (Slave)
Q
R
S
Comparator
RC2/CCP1
(Note 1)
TMR2
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
Note 1:
8-bit timer is concatenated with 2-bit internal Q
clock, or 2 bits of the prescaler, to create 10-bit
time-base.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
A PWM output (Figure 14-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency:
FIGURE 14-4: PWM OUTPUT
Period
FOSC
log ---------------
FPWM
= ----------------------------- b i t s
log(2)
Duty Cycle
TMR2 = PR2
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TMR2 = Duty Cycle
TMR2 = PR2
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14.5.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 14-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz 9.76 kHz 39.06 kHz 156.3 kHz 312.5 kHz 416.6 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
5.5
Maximum Resolution (bits)
TABLE 14-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
all other
RESETS
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
TMR2IF
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IP 0000 0000 0000 0000
1111 1111 1111 1111
PIE1
CCP1IE TMR2IE
CCP1IP TMR2IP
IPR1
TRISC
TMR2
PR2
PORTC Data Direction Register
Timer2 module’s register
0000 0000 0000 0000
Timer2 module’s period register
1111 1111 1111 1111
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM register1 (LSB)
CCPR1H Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
CCPR2L Capture/Compare/PWM register2 (LSB)
CCPR2H Capture/Compare/PWM register2 (MSB)
xxxx xxxx uuuu uuuu
CCP2CON
PIR2
—
—
—
—
—
DC2B1
—
DC2B0
—
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
CMIF
CMIE
CMIP
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF
TMR3IE
TMR3IP
CCP2IF -0-- 0000 -0-- 0000
CCP2IE -0-- 0000 -0-- 0000
CCP2IP -0-- 0000 -0-- 0000
PIE2
—
—
IPR2
—
—
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
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NOTES:
DS30475A-page 134
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15.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
15.1
Master SSP (MSSP) Module Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral InterfaceTM (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
• Master mode
• Multi-master mode
• Slave mode
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Register 15-1 shows the MSSP Status Register
(SSPSTAT), Register 15-2 shows the MSSP Control
Register 1 (SSPCON1), and Register 15-3 shows the
MSSP Control Register 2 (SSPCON2).
15.2
Control Registers
The MSSP module has three associated registers.
These include a status register and two control registers.
REGISTER 15-1: SSPSTAT REGISTER
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master mode
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode
SMP must be cleared when SPI is used in Slave mode
In I2C Master or Slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select
CKP = 0
1= Data transmitted on rising edge of SCK
0= Data transmitted on falling edge of SCK
CKP = 1
1= Data transmitted on falling edge of SCK
0= Data transmitted on rising edge of SCK
bit 5
bit 4
D/A: Data/Address bit (I2C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: STOP bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0= STOP bit was not detected last
bit 3
bit 2
S: START bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0= START bit was not detected last
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from
the address match to the next START bit, STOP bit, or not ACK bit.
In I2C Slave mode:
1= Read
0= Write
In I2C Master mode:
1=Transmit is in progress
0=Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in
IDLE mode.
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PIC18CXX8
bit 1
bit 0
UA: Update Address (10-bit I2C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1= Data Transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0= Data Transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
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PIC18CXX8
REGISTER 15-2: SSPCON1 REGISTER
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3 SSPM2 SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
Master mode:
1= A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started
0= No collision
Slave mode:
1= The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave
mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting
overflow. In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register. (Must be cleared in software.)
0= No overflow
In I2C mode:
1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a
"don’t care" in Transmit mode. (Must be cleared in software.)
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode:
1= Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port
pins
0= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1= Enables the serial port and configures the SDA and SCL pins as the source of the serial
port pins
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level
0= Idle state for clock is a low level
In I2C Slave mode:
SCK release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode
Unused in this mode
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bit 3 - 0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110= I2C Slave mode, 7-bit address
0111= I2C Slave mode, 10-bit address
1000= I2C Master mode, clock = FOSC / (4 * (SSPADD+1) )
1001= Reserved
1010= Reserved
1011= I2C firmware controlled Master mode (Slave idle)
1100= Reserved
1101= Reserved
1110= I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled
1111= I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
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PIC18CXX8
REGISTER 15-3: SSPCON2 REGISTER
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
ACKSTAT
ACKDT
ACKEN
bit 7
bit 0
bit 7
bit 6
GCEN: General Call Enable bit (In I2C Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (In I2C Master mode only)
In Master Transmit mode:
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
bit 5
bit 4
ACKDT: Acknowledge Data bit (In I2C Master mode only)
In Master Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1= Not Acknowledge
0= Acknowledge
ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only)
In Master Receive mode:
1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence idle
bit 3
bit 2
RCEN: Receive Enable bit (In I2C Master mode only)
1= Enables Receive mode for I2C
0= Receive idle
PEN: STOP Condition Enable bit (In I2C Master mode only)
SCK release control
1= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0= STOP condition idle
bit 1
bit 0
RSEN: Repeated START Condition Enabled bit (In I2C Master mode only)
1= Initiate Repeated START condition on SDA and SCL pins. Automatically cleared
by hardware.
0= Repeated START condition idle
SEN: START Condition Enabled bit (In I2C Master mode only)
1= Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0= START condition idle
Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
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PIC18CXX8
15.3
SPI Mode
FIGURE 15-1: MSSP BLOCK DIAGRAM
(SPI MODE)
The SPI mode allows 8 bits of data to be synchronously
transmitted and received, simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
Internal
Data Bus
Read
Write
• Serial Data Out (SDO) - RC5/SDO
• Serial Data In (SDI) - RC4/SDI/SDA
• Serial Clock (SCK) - RC3/SCK/SCL/LVOIN
SSPBUF reg
SSPSR reg
Additionally, a fourth pin may be used when in any
Slave mode of operation:
Shift
Clock
• Slave Select (SS) - RA5/SS/AN4
SDI
bit0
15.3.1 OPERATION
SDO
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits SSPCON1<5:0> and SSPSTAT<7:6>.
These control bits allow the following to be specified:
Control
Enable
SS
SS
Edge
Select
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock polarity (Idle state of SCK)
• Data input sample phase (middle or end of data
output time)
2
Clock Select
• Clock edge (output data on rising/falling edge of
SCK)
• Clock rate (Master mode only)
• Slave Select mode (Slave mode only)
SSPM3:SSPM0
SMP:CKE
2
4
TMR2 Output
(
)
2
Edge
Select
TOSC
Prescaler
4, 16, 64
Figure 15-1 shows the block diagram of the MSSP
module, when in SPI mode.
SCK
Data to TX/RX in SSPSR
TRIS bit
Note: I/O pins have diode protection to VDD and
VSS.
The MSSP consists of a transmit/receive Shift Register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit, BF (SSPSTAT
register), and the interrupt flag bit, SSPIF (PIR regis-
ters), are set. This double buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit, WCOL
(SSPCON1 register), will be set. User software must
clear the WCOL bit so that it can be determined if the
following write(s) to the SSPBUF register completed
successfully.
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When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
buffer full (BF) bit (SSPSTAT register) indicates when
SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP Interrupt
is used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or
written. If the interrupt method is not going to be used,
then software polling can be done to ensure that a write
collision does not occur. Example 15-1 shows the
loading of the SSPBUF (SSPSR) for data transmission.
15.3.2 ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON1 register), must be set. To reset or reconfig-
ure SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers, and then set the SSPEN bit. This
configures the SDI, SDO, SCK, and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISC<4> bit set
The SSPSR is not directly readable or writable, and
can only be accessed by addressing the SSPBUF reg-
ister. Additionally, the MSSP status register (SSPSTAT
register) indicates the various status conditions.
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
EXAMPLE 15-1: LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF
GOTO LOOP
;Has data been received (transmit complete)?
;No
MOVF SSPBUF, W
;WREG reg = contents of SSPBUF
MOVWF RXDATA
;Save in user RAM, if data is meaningful
MOVF TXDATA, W
MOVWF SSPBUF
;W reg = contents of TXDATA
;New data to xmit
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PIC18CXX8
15.3.3 MASTER MODE
shown in Figure 15-2, Figure 15-4, and Figure 15-5,
where the MSb is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave is to broadcast data by the software
protocol.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor” mode.
This allows a maximum data rate (at 40 MHz) of 10.00
Mbps.
Figure 15-2 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
The clock polarity is selected by appropriately program-
ming the CKP bit (SSPCON1 register). This, then,
would give waveforms for SPI communication as
FIGURE 15-2: SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit6
bit6
bit2
bit2
bit5
bit5
bit4
bit4
bit1
bit1
bit0
bit0
SDO
(CKE = 0)
bit7
bit7
bit3
bit3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit0
bit7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
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PIC18CXX8
15.3.4 SLAVE MODE
the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
output. External pull-up/pull-down resistors may be
desirable, depending on the application.
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Note 1: When the SPI is in Slave mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is
set to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times, as
specified in the electrical specifications.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
When the SPI module resets, the bit counter is forced
to 0. This can be done by either forcing the SS pin to a
high level, or clearing the SSPEN bit.
15.3.5 SLAVE SELECT SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control
enabled (SSPCON1<3:0> = 04h). The pin must not
be driven low for the SS pin to function as an input.
The Data Latch must be high. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function),
since it cannot create a bus conflict.
FIGURE 15-3: SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit6
bit7
bit7
bit0
bit0
SDO
bit7
SDI
(SMP = 0)
bit7
Input
Sample
(SMP = 0)
SSPIF
Next Q4 Cycle
SSPSR to
SSPBUF
after Q2↓
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PIC18CXX8
FIGURE 15-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit6
bit2
bit5
bit4
bit1
bit0
SDO
bit7
bit3
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
FIGURE 15-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Required
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit6
bit2
bit5
bit4
bit1
bit0
SDO
bit7
bit7
bit3
SDI
(SMP = 0)
bit0
Input
Sample
(SMP = 0)
SSPIF
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
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15.3.6 SLEEP OPERATION
15.3.8 BUS MODE COMPATIBILITY
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to trans-
mit/receive data.
Table 15-1 shows the compatibility between the stan-
dard SPI modes and the states of the CKP and CKE
control bits.
TABLE 15-1: SPI BUS MODES
Control Bits State
Standard SPI Mode
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode, and data to be
shifted into the SPI transmit/receive shift register.
When all eight bits have been received, the MSSP
interrupt flag bit will be set and, if enabled, will wake the
device from SLEEP.
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
There is also a SMP bit that controls when the data will
be sampled.
15.3.7 EFFECTS OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 15-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Value on Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
all other
RESETS
0000 000x 0000 000u
INTCON
GIE/
GIEH
PEIE/ TMR0IE INT0IE
GIEL
RBIE
TMR0IF INT0IF
RBIF
0000 0000 0000 0000
0000 0000 0000 0000
PIR1
PIE1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF CCP1IF TMR2IF TMR1IF
SSPIE CCP1IE TMR2IE TMR1IE
SSPIP CCP1IP TMR2IP TMR1IP
0000 0000 0000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
IPR1
TRISC
PORTC Data Direction Register
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON
TRISA
WCOL SSPOV SSPEN
CKP
PORTA Data Direction Register(1)
CKE D/A
SSPM3 SSPM2 SSPM1 SSPM0
--11 1111 --11 1111
0000 0000 0000 0000
—
SSPSTAT
SMP
P
S
R/W
UA
BF
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'.
Shaded cells are not used by the MSSP in SPI mode.
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator
modes, they are disabled and read ‘0’.
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PIC18CXX8
The SSPCON1 register allows control of the I2C oper-
ation. The SSPM3:SSPM0 mode selection bits
(SSPCON1 register) allow one of the following I2C
modes to be selected:
15.4
MSSP I2C Operation
The MSSP module in I2C mode, fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine a free bus (Multi-master
mode). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
• I2C Master mode, clock = OSC/4 (SSPADD +1)
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled
Two pins are used for data transfer. These are the
RC3/SCK/SCL pin, which is the clock (SCL), and the
RC4/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISC<4:3> bits.
• I2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled
• I2C Firmware controlled master operation, slave
is idle
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
The MSSP module functions are enabled by setting
MSSP Enable bit SSPEN (SSPCON1 register).
FIGURE 15-6: MSSP BLOCK DIAGRAM
(I2C MODE)
15.4.1 SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
Internal
Data Bus
Read
Write
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse and
load the SSPBUF register with the received value cur-
rently in the SSPSR register.
SSPBUF reg
RC3/SCK/SCL
Shift
Clock
SSPSR reg
If either or both of the following conditions are true, the
MSSP module will not give this ACK pulse:
RC4/
SDI/
SDA
MSb
LSb
a) The buffer full bit BF (SSPCON1 register) was
set before the transfer was received.
Addr Match
Match Detect
b) The overflow bit SSPOV (SSPCON1 register)
was set before the transfer was received.
SSPADD reg
START and
In this event, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR registers) is set.
The BF bit is cleared by reading the SSPBUF register,
while bit SSPOV is cleared through software.
Set, RESET
S, P bits
(SSPSTAT reg)
STOP bit detect
Note:
I/O pins have diode protection to VDD and VSS.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, is shown in timing parameter #100 and
parameter #101.
The MSSP module has these six registers for I2C oper-
ation:
• MSSP Control Register1 (SSPCON1)
• MSSP Control Register2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) - Not directly
accessible
• MSSP Address Register (SSPADD)
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15.4.1.1 Addressing
The sequence of events for 10-bit addressing is as fol-
lows, with steps 7- 9 for slave-transmitter:
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, the eight bits are shifted into the SSPSR register.
All incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
1. Receive first (high) byte of address (the SSPIF,
BF and UA bits (SSPSTAT register) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
a) The SSPSR register value is loaded into the
SSPBUF register.
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
b) The buffer full bit BF is set.
c) An ACK pulse is generated.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
d) MSSP interrupt flag bit SSPIF (PIR registers) is
set on the falling edge of the ninth SCL pulse
(interrupt is generated, if enabled).
7. Receive repeated START condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSb) of the first address byte specify if this is a 10-bit
address. The R/W bit (SSPSTAT register) must specify
a write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘1111 0 A9 A8 0’, where A9and A8are the
two MSb’s of the address.
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
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15.4.1.2 Reception
ter. Then pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON1 register). The master must
monitor the SCL pin prior to asserting another clock
pulse. The slave devices may be holding off the master
by stretching the clock. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time
(Figure 15-8).
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT register) is
set or bit SSPOV (SSPCON1 register) is set.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR registers) must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
As a slave-transmitter, the ACK pulse from the
master-receiver is latched on the rising edge of the
ninth SCL input pulse. If the SDA line is high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset (resets
SSPSTAT register) and the slave monitors for another
occurrence of the START bit. If the SDA line was low
(ACK), the transmit data must be loaded into the SSP-
BUF register, which also loads the SSPSR register. Pin
RC3/SCK/SCL should be enabled by setting bit CKP.
15.4.1.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
FIGURE 15-7: I2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address
A7 A6 A5 A4
R/W=0
Receiving Data
Receiving Data
ACK
Not ACK
D0
ACK
9
SDA
A3 A2 A1
D5
D2
D0
8
D5
D2
D7 D6
D4 D3
D7 D6
D4 D3
D1
7
D1
7
1
2
3
4
5
6
9
1
2
3
4
9
8
5
6
1
2
3
4
5
6
7
8
P
SCL
S
SSPIF
Bus Master
Terminates
Transfer
BF
Cleared in software
SSPBUF register is read
SSPOV
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
FIGURE 15-8: I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
R/W = 0
Not ACK
Receiving Address
R/W = 1
ACK
Transmitting Data
SDA
SCL
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
S
P
SCL held low
while CPU
responds to SSPIF
Data in
Sampled
SSPIF
BF
Cleared in software
SSPBUF is written in software
From SSP interrupt
service routine
CKP
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
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PIC18CXX8
15.4.2 GENERAL CALL ADDRESS SUPPORT
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF bit is set (eighth bit),
and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
acknowledge.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT register). If the general call address
is sampled when the GCEN bit is set, and while the
slave is configured in 10-bit address mode; then, the
second half of the address is not necessary. The UA bit
will not be set, and the slave will begin receiving data
after the Acknowledge (Figure 15-9).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0.
The general call address is recognized (enabled) when
the General Call Enable (GCEN) bit is set (SSPCON2
register). Following a START bit detect, eight bits are
shifted into the SSPSR and the address is compared
against the SSPADD. It is also compared to the general
call address and fixed in hardware.
FIGURE 15-9: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS)
Address is compared to General Call Address
after ACK, set interrupt
Receiving data
D5 D4 D3 D2 D1
ACK
R/W = 0
ACK
General Call Address
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
9
S
SSPIF
BF
Cleared in software
SSPBUF is read
SSPOV
GCEN
’0’
’1’
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15.4.3 MASTER MODE
15.4.4 I2C MASTER MODE SUPPORT
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I2C bus may be taken when the
P bit is set, or the bus is idle, with both the S and P bits
clear.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once Master mode is enabled, the user
has the following six options:
1. Assert a START condition on SDA and SCL.
2. Assert a Repeated START condition on SDA
and SCL.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
3. Write to the SSPBUF register initiating transmis-
sion of data/address.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
4. Generate a STOP condition on SDA and SCL.
5. Configure the I2C port to receive data.
• START condition
• STOP condition
6. Generate an Acknowledge condition at the end
of a received byte of data.
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated START condition
Note: The MSSP module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
imitate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
2
FIGURE 15-10: MSSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA In
MSb
LSb
START bit, STOP bit,
Acknowledge
Generate
SCL
START bit Detect
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
SCL In
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Note: I/O pins have diode protection to VDD and VSS.
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15.4.4.1 I2C Master Mode Operation
A typical transmit sequence would go as follows:
a) The user generates a START condition by set-
ting the START Enable (SEN) bit (SSPCON2
register).
The master device generates all of the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condi-
tion is also the beginning of the next serial transfer, the
I2C bus will not be released.
b) SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
c) The user loads the SSPBUF with the address to
transmit.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ’0’. Serial data is
transmitted eight bits at a time. After each byte is trans-
mitted, an Acknowledge bit is received. START and
STOP conditions are output to indicate the beginning
and the end of a serial transfer.
d) Address is shifted out the SDA pin until all eight
bits are transmitted.
e) The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit (SSPCON2 register).
f) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ’1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ’1’ to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received eight bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. START and STOP conditions indicate the begin-
ning and end of transmission.
g) The user loads the SSPBUF with eight bits of
data.
h) Data is shifted out the SDA pin until all eight bits
are transmitted.
i) The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit (SSPCON2 register).
j) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The baud rate generator used for the SPI mode opera-
tion is now used to set the SCL clock frequency for
either 100 kHz, 400 kHz, or 1 MHz I2C operation. The
baud rate generator reload value is contained in the
lower 7 bits of the SSPADD register. The baud rate
generator will automatically begin counting on a write to
the SSPBUF. Once the given operation is complete
(i.e., transmission of the last data bit is followed by
ACK), the internal clock will automatically stop counting
and the SCL pin will remain in its last state.
k) The user generates a STOP condition by setting
the STOP Enable bit PEN (SSPCON2 register).
l) Interrupt is generated once the STOP condition
is complete.
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15.4.5 BAUD RATE GENERATOR
remented twice per instruction cycle (TCY) on the Q2
and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically. If Clock Arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 15-12).
In I2C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 15-11). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
FIGURE 15-11: BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
BRG Down Counter
CLKOUT
Fosc/4
FIGURE 15-12: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL allowed to transition high
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count.
BRG
reload
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15.4.6 I2C MASTER MODE START CONDITION
TIMING
15.4.6.1 WCOL Status Flag
If the user writes the SSPBUF when a START
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
To initiate a START condition, the user sets the START
Condition Enable (SEN) bit (SSPCON2 register). If the
SDA and SCL pins are sampled high, the baud rate
generator is re-loaded with the contents of
SSPADD<6:0> and starts its count. If SCL and SDA are
both sampled high when the baud rate generator times
out (TBRG), the SDA pin is driven low. The action of the
SDA being driven low, while SCL is high, is the START
condition, and causes the S bit (SSPSTAT register) to
be set. Following this, the baud rate generator is
reloaded with the contents of SSPADD<6:0> and
resumes its count. When the baud rate generator times
out (TBRG), the SEN bit (SSPCON2 register) will be
automatically cleared by hardware, the baud rate gen-
erator is suspended leaving the SDA line held low and
the START condition is complete.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
Note: If at the beginning of the START condition,
the SDA and SCL pins are already sam-
pled low, or if during the START condition
the SCL line is sampled low before the SDA
line is driven low, a bus collision occurs, the
Bus Collision Interrupt Flag BCLIF is set,
the START condition is aborted, and the
I2C module is reset into its IDLE state.
FIGURE 15-13: FIRST START BIT TIMING
Set S bit (SSPSTAT)
Write to SEN bit occurs here
SDA = 1,
At completion of START bit,
Hardware clears SEN bit
and sets SSPIF bit
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
2nd Bit
1st Bit
SDA
TBRG
SCL
TBRG
S
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15.4.7 I2C MASTER MODE REPEATED START
CONDITION TIMING
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional
eight bits of address (10-bit mode) or eight bits of data
(7-bit mode).
A Repeated START condition occurs when the RSEN
bit (SSPCON2 register) is programmed high and the
I2C logic module is in the IDLE state. When the RSEN
bit is set, the SCL pin is asserted low. When the SCL
pin is sampled low, the baud rate generator is loaded
with the contents of SSPADD<5:0> and begins count-
ing. The SDA pin is released (brought high) for one
baud rate generator count (TBRG). When the baud rate
generator times out, if SDA is sampled high, the SCL
pin will be de-asserted (brought high). When SCL is
sampled high, the baud rate generator is re-loaded with
the contents of SSPADD<6:0> and begins counting.
SDA and SCL must be sampled high for one TBRG.
This action is then followed by assertion of the SDA pin
15.4.7.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated
START sequence is in progress, the WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
(SDA = 0) for one TBRG while SCL is high. Following
,
this, the RSEN bit (SSPCON2 register) will be automat-
ically cleared and the baud rate generator will not be
reloaded, leaving the SDA pin held low. As soon as a
START condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT register) will be set. The SSPIF bit
will not be set until the baud rate generator has
timed-out.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated
START condition occurs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
FIGURE 15-14: REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
SDA = 1,
occurs here.
At completion of START bit,
hardware clear RSEN bit
and set SSPIF
SCL = 1
SDA = 1,
SCL(no change)
TBRG
TBRG
TBRG
1st Bit
SDA
Write to SSPBUF occurs here.
TBRG
Falling edge of ninth clock
End of Xmit
SCL
TBRG
Sr = Repeated START
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15.4.8 I2C MASTER MODE TRANSMISSION
15.4.8.2 WCOL Status Flag
Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address, is accomplished by sim-
ply writing a value to the SSPBUF register. This action
will set the Buffer Full bit, BF, and allow the baud rate
generator to begin counting and start the next transmis-
sion. Each bit of address/data will be shifted out onto
the SDA pin after the falling edge of SCL is asserted
(see data hold time specification parameter 106). SCL
is held low for one baud rate generator roll over count
(TBRG). Data should be valid before SCL is released
high (see data setup time specification parameter 107).
When the SCL pin is released high, it is held that way
for TBRG. The data on the SDA pin must remain stable
for that duration and some hold time after the next fall-
ing edge of SCL. After the eighth bit is shifted out (the
falling edge of the eighth clock), the BF bit is cleared
and the master releases SDA, allowing the slave
device being addressed to respond with an ACK bit
during the ninth bit time if an address match occurs, or
if data was received properly. The status of ACK is
written into the ACKDT bit on the falling edge of the
ninth clock. If the master receives an acknowledge, the
Acknowledge Status bit, ACKSTAT, is cleared. If not,
the bit is set. After the ninth clock, the SSPIF bit is set
and the master clock (baud rate generator) is sus-
pended until the next data byte is loaded into the SSP-
BUF, leaving SCL low and SDA unchanged
(Figure 15-15).
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
15.4.8.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2
register) is cleared when the slave has sent an
acknowledge (ACK = 0), and is set when the slave
does not acknowledge (ACK = 1). A slave sends an
acknowledge when it has recognized its address
(including a general call), or when the slave has
properly received its data.
15.4.9 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2 register).
Note: The MSSP module must be in an IDLE
state before the RCEN bit is set, or the
RCEN bit will be disregarded.
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to
low/low to high) and data is shifted into the SSPSR.
After the falling edge of the eighth clock, the RCEN bit
is automatically cleared, the contents of the SSPSR are
loaded into the SSPBUF, the BF bit is set, the SSPIF
flag bit is set and the baud rate generator is suspended
from counting, holding SCL low. The MSSP is now in
IDLE state, awaiting the next command. When the
buffer is read by the CPU, the BF bit is automatically
cleared. The user can then send an Acknowledge bit at
the end of reception, by setting the Acknowledge
Sequence Enable bit ACKEN (SSPCON2 register).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL, until all seven
address bits and the R/W bit, are completed. On the
falling edge of the eighth clock, the master will
de-assert the SDA pin, allowing the slave to respond
with an acknowledge. On the falling edge of the ninth
clock, the master will sample the SDA pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit
(SSPCON2 register). Following the falling edge of the
ninth clock transmission of the address, the SSPIF is
set, the BF bit is cleared and the baud rate generator is
turned off, until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.
15.4.9.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
15.4.9.2 SSPOV Status Flag
15.4.8.1 BF Status Flag
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF bit is
already set from a previous reception.
In Transmit mode, the BF bit (SSPSTAT register) is set
when the CPU writes to SSPBUF, and is cleared when
all eight bits are shifted out.
15.4.9.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
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2
FIGURE 15-15: I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
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2
FIGURE 15-16: I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
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15.4.10 ACKNOWLEDGE SEQUENCE TIMING
15.4.11 STOP CONDITION TIMING
An acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit ACKEN
(SSPCON2 register). When this bit is set, the SCL pin
is pulled low and the contents of the Acknowledge Data
bit (ACKDT) is presented on the SDA pin. If the user
wishes to generate an acknowledge, then the ACKDT
bit should be cleared. If not, the user should set the
ACKDT bit before starting an acknowledge sequence.
The baud rate generator then counts for one rollover
period (TBRG) and the SCL pin is de-asserted (pulled
high). When the SCL pin is sampled high (clock arbitra-
tion), the baud rate generator counts for TBRG. The
SCL pin is then pulled low. Following this, the ACKEN
bit is automatically cleared, the baud rate generator is
turned off and the MSSP module then goes into IDLE
mode (Figure 15-17).
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2 register). At the end of a
receive/transmit, the SCL line is held low after the fall-
ing edge of the ninth clock. When the PEN bit is set, the
master will assert the SDA line low. When the SDA line
is sampled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT register) is set.
A TBRG later, the PEN bit is cleared and the SSPIF bit
is set (Figure 15-18).
15.4.11.1 WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
15.4.10.1 WCOL Status Flag
If the user writes the SSPBUF when an acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-17: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
TBRG
SDA
SCL
D0
ACK
8
9
SSPIF
Cleared in
software
Set SSPIF at the end
of receive
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one baud rate generator period.
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FIGURE 15-18: STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT) is set
Write to SSPCON2
Set PEN
PEN bit (SSPCON2) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to set up STOP condition.
Note: TBRG = one baud rate generator period.
DS30475A-page 160
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
15.4.12 CLOCK ARBITRATION
15.4.13 SLEEP OPERATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated START/STOP condition,
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 15-19).
While in SLEEP mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the MSSP interrupt is enabled).
15.4.14 EFFECT OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
FIGURE 15-19: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval.
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SCL = 1 BRG starts counting
clock high interval.
SCL
SDA
SCL line sampled once every machine cycle (TOSC² 4).
Hold off BRG until SCL is sampled high.
TBRG
TBRG
TBRG
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 161
PIC18CXX8
15.4.15 MULTI-MASTER MODE
15.4.16 MULTI -MASTER COMMUNICATION, BUS
COLLISION, AND BUS ARBITRATION
In Multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET, or
when the MSSP module is disabled. Control of the I2C
bus may be taken when the P bit (SSPSTAT register) is
set, or the bus is idle with both the S and P bits clear.
When the bus is busy, enabling the SSP Interrupt will
generate the interrupt when the STOP condition
occurs.
Multi-master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA, by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a '1' and the data sampled on the SDA pin = '0',
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag (BCLIF) and reset the
I2C port to its IDLE state. (Figure 15-20).
In Multi-master operation, the SDA line must be moni-
tored for arbitration, to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF bit is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision interrupt service routine, and if the I2C
bus is free, the user can resume communication by
asserting a START condition.
Arbitration can be lost in the following states:
• Address transfer
• Data transfer
• A START condition
• A Repeated START condition
• An Acknowledge condition
If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision interrupt service routine, and if
the I2C bus is free, the user can resume communication
by asserting a START condition.
The master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be
set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In Multi-master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
FIGURE 15-20: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
SDA line pulled low
by another source
Data changes
while SCL = 0
Bus collision has occurred.
SDA released
by master
SDA
Set bus collision
interrupt (BCLIF)
SCL
BCLIF
DS30475A-page 162
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
15.4.16.1 Bus Collision During a START Condition
During a START condition, a bus collision occurs if:
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ’1’ during the START condition.
a) SDA or SCL are sampled low at the beginning of
the START condition (Figure 15-21).
b) SCL is sampled low before SDA is asserted low
(Figure 15-22).
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 15-23). If, however, a ’1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pin is
sampled as ’0’, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
During a START condition, both the SDA and the SCL
pins are monitored.
If:
the SDA pin is already low
or the SCL pin is already low,
then:
the START condition is aborted,
and the BCLIF flag is set,
and the MSSP module is reset to its IDLE state
(Figure 15-21).
Note: The reason that bus collision is not a factor
during a START condition is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START or STOP conditions.
FIGURE 15-21: BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
. Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable START
condition if SDA = 1, SCL = 1.
SEN cleared automatically because of bus collision.
SSP module reset into IDLE state.
SEN
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared in software.
S
SSPIF
SSPIF and BCLIF are
cleared in software.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 163
PIC18CXX8
FIGURE 15-22: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
SCL
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
Bus collision occurs, set BCLIF
SCL = 0 before BRG time-out,
Bus collision occurs, set BCLIF
BCLIF
Interrupt cleared
in software
S
’0’
’0’
’0’
’0’
SSPIF
FIGURE 15-23: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master
Reset BRG and assert SDA
SDA
SCL
S
SCL pulled low after BRG
Time-out
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
BCLIF
’0’
S
SSPIF
Interrupts cleared
in software
SDA = 0, SCL = 1
Set SSPIF
DS30475A-page 164
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
15.4.16.2 Bus Collision During a Repeated START
Condition
reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs
because no two masters can assert SDA at exactly the
same time.
During a Repeated START condition, a bus collision
occurs if:
If SCL goes from high to low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ’1’ during the Repeated START condi-
tion (Figure 15-25).
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data ’1’.
If at the end of the BRG time-out both SCL and SDA are
still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is
complete.
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>
and counts down to 0. The SCL pin is then de-asserted,
and when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e, another
master is attempting to transmit a data ’0’, see
Figure 15-24). If SDA is sampled high, the BRG is
FIGURE 15-24: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software.
'0'
S
'0'
SSPIF
FIGURE 15-25: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA.
BCLIF
RSEN
Set BCLIF, release SDA and SCL.
Interrupt cleared
in software.
’0’
S
SSPIF
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 165
PIC18CXX8
15.4.16.3 Bus Collision During a STOP Condition
Bus collision occurs during a STOP condition if:
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ’0’ (Figure 15-26). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master attempt-
ing to drive a data ’0’ (Figure 15-27).
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
FIGURE 15-26: BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
’0’
’0’
SSPIF
FIGURE 15-27: BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
’0’
’0’
SSPIF
DS30475A-page 166
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
The USART can be configured in the following modes:
16.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The SPEN (RCSTA register) and the TRISC<7> bits
have to be set, and the TRISC<6> bit must be
cleared, in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchro-
nous Receiver Transmitter.
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI). The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and personal computers, or it can be configured
as a half duplex synchronous system that can commu-
nicate with peripheral devices, such as A/D or D/A inte-
grated circuits, Serial EEPROMs, etc.
Register 16-1 shows the Transmit Status and Control
Register (TXSTA) and Register 16-2 shows the
Receive Status and Control Register (TXSTA).
REGISTER 16-1: TXSTA REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
R/W-0
BRGH
R-1
R/W-0
TX9D
—
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1= Master mode (Clock generated internally from BRG)
0= Slave mode (Clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3
bit 2
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode
1= High speed
0= Low speed
Synchronous mode
Unused in this mode
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of transmit data. Can be Address/Data bit or a parity bit.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 167
PIC18CXX8
REGISTER 16-2: RCSTA REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (Configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - Master
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - Slave
Unused in this mode
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1)
1= Enables address detection, enable interrupt and load of the receive buffer when RSR<8>
is set
0= Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (Can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (Can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of received data, can be Address/Data bit or a parity bit
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS30475A-page 168
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
16.1
USART Baud Rate Generator (BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA register) also controls the
baud rate. In Synchronous mode, bit BRGH is ignored.
Table 16-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internal clock).
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
16.1.1 SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 16-1. From this, the error in
baud rate can be determined.
Example 16-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
EXAMPLE 16-1: CALCULATING BAUD RATE ERROR
Desired Baud Rate
=
FOSC / (64 (X + 1))
Solving for X:
X
X
X
=
=
=
( (FOSC / Desired Baud Rate) / 64 ) - 1
((16000000 / 9600) / 64) - 1
[25.042] = 25
Calculated Baud Rate
=
=
16000000 / (64 (25 + 1))
9615
Error
=
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
=
=
(9615 - 9600) / 9600
0.16%
TABLE 16-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate = FOSC/(16(X+1))
NA
Legend: X = value in SPBRG (0 to 255)
TABLE 16-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on
POR,
Value on all
other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
TXSTA
RCSTA
SPBRG
CSRC
SPEN
TX9
RX9
TXEN SYNC
—
BRGH TRMT TX9D 0000 -010
0000 -010
0000 000x
0000 0000
SREN CREN ADDEN FERR OERR RX9D 0000 000x
0000 0000
Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 169
PIC18CXX8
TABLE 16-3: BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 40 MHz
33 MHz
25 MHz
20 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD
KBAUD
NA
KBAUD
ERROR
KBAUD ERROR
ERROR
ERROR
0.3
NA
-
-
NA
-
-
-
-
-
-
-
-
NA
-
-
1.2
NA
-
-
NA
-
-
NA
-
NA
-
-
2.4
NA
-
-
NA
-
-
NA
-
NA
-
-
9.6
NA
-
-
NA
-
-
NA
-
NA
-
-
19.2
76.8
96
NA
-
-
NA
-
-
NA
-
NA
-
-
76.92
96.15
303.03
500
+0.16
129
103
32
19
0
77.10
95.93
294.64
485.30
8250
32.23
+0.39
-0.07
-1.79
-2.94
-
106
85
27
16
0
77.16
96.15
297.62
480.77
6250
24.41
+0.47
+0.16
-0.79
-3.85
-
80
64
20
12
0
76.92
96.15
294.12
500
+0.16
64
51
16
9
+0.16
+0.16
300
500
HIGH
LOW
+1.01
-1.96
0
-
0
-
10000
39.06
5000
19.53
0
-
255
-
255
-
255
-
255
FOSC = 16 MHz
%
10 MHz
7.15909 MHz
%
5.0688 MHz
%
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
KBAUD
KBAUD
KBAUD
KBAUD
ERROR
ERROR
ERROR
ERROR
0.3
NA
-
-
NA
-
-
NA
-
-
NA
-
-
1.2
NA
-
-
NA
-
-
NA
-
-
NA
-
-
2.4
NA
-
-
NA
-
-
NA
-
-
NA
-
-
9.6
NA
-
-
NA
-
-
9.62
+0.23
+0.23
+1.32
-1.88
-0.57
-10.51
-
185
92
22
18
5
9.60
0
131
65
16
12
3
19.2
76.8
96
19.23
76.92
95.24
307.70
500
+0.16
+0.16
-0.79
+2.56
0
207
51
41
12
7
19.23
75.76
96.15
312.50
500
+0.16
-1.36
+0.16
+4.17
0
129
32
25
7
19.24
77.82
94.20
298.35
447.44
1789.80
6.99
19.20
74.54
97.48
316.80
422.40
1267.20
4.95
0
-2.94
+1.54
+5.60
-15.52
-
300
500
HIGH
LOW
4
3
2
4000
15.63
-
0
2500
9.77
-
0
0
0
-
255
-
255
-
255
-
255
FOSC = 4 MHz
%
3.579545 MHz
%
1 MHz
32.768 kHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
KBAUD
KBAUD
KBAUD
KBAUD
ERROR
ERROR
ERROR
ERROR
0.3
NA
-
-
NA
-
-
NA
-
-
0.30
1.17
2.73
8.20
NA
+1.14
26
1.2
NA
-
-
NA
-
-
1.20
2.40
9.62
19.23
83.33
83.33
250
+0.16
+0.16
+0.16
+0.16
+8.51
-13.19
-16.67
-
207
103
25
12
2
-2.48
6
2.4
NA
-
-
NA
-
-
+13.78
2
9.6
9.62
19.23
76.92
1000
333.33
500
+0.16
+0.16
+0.16
+4.17
+11.11
0
103
51
12
9
9.62
+0.23
-0.83
-2.90
+3.57
-0.57
-10.51
-
92
46
11
8
-14.67
0
19.2
76.8
96
19.04
74.57
99.43
298.30
447.44
894.89
3.50
-
-
-
-
-
-
-
-
NA
-
2
NA
-
300
500
HIGH
LOW
2
2
0
NA
-
1
1
NA
-
NA
-
1000
3.91
-
0
0
250
-
0
8.20
0.03
0
-
255
-
255
0.98
-
255
255
DS30475A-page 170
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 16-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 40 MHz
33 MHz
25 MHz
20 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD
ERROR
KBAUD
ERROR
KBAUD ERROR
0.3
NA
-
-
NA
-
-
-
NA
-
-
-
NA
-
-
1.2
NA
-
-
NA
-
NA
-
NA
-
-
2.4
NA
-
-
2.40
-0.07
-0.54
-0.54
-4.09
+7.42
-14.06
-
214
53
26
6
2.40
9.53
19.53
78.13
97.66
NA
-0.15
162
40
19
4
2.40
+0.16
-1.36
+1.73
+1.73
+8.51
+4.17
-
129
32
15
3
9.6
9.62
18.94
78.13
89.29
312.50
625
+0.16
-1.36
+1.73
-6.99
+4.17
+25.00
-
64
32
7
9.55
-0.76
9.47
19.2
76.8
96
19.10
73.66
103.13
257.81
NA
+1.73
19.53
78.13
104.17
312.50
NA
+1.73
6
4
+1.73
3
2
300
500
HIGH
LOW
1
1
-
-
-
-
-
0
0
-
NA
-
-
625
0
515.63
2.01
-
0
390.63
1.53
0
312.50
1.22
-
0
2.44
-
255
-
255
255
-
255
FOSC = 16 MHz
10 MHz
7.15909 MHz
%
5.0688 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
KBAUD ERROR
KBAUD
ERROR
KBAUD
ERROR
KBAUD ERROR
0.3
NA
-
-
NA
-
-
NA
-
-
NA
-
-
1.2
1.20
2.40
9.62
19.23
83.33
83.33
250
+0.16
+0.16
+0.16
+0.16
+8.51
-13.19
-16.67
-
207
103
25
12
2
1.20
+0.16
+0.16
+1.73
+1.73
+1.73
-18.62
-47.92
-
129
64
15
7
1.20
2.38
9.32
18.64
111.86
NA
+0.23
92
46
11
5
1.20
2.40
9.90
19.80
79.20
NA
0
65
32
7
2.4
2.40
-0.83
0
9.6
9.77
-2.90
+3.13
19.2
76.8
96
19.53
78.13
78.13
156.25
NA
-2.90
+3.13
3
1
+45.65
0
+3.13
0
2
1
-
-
-
-
-
-
-
-
-
-
-
-
300
500
HIGH
LOW
0
0
NA
-
NA
-
NA
-
-
NA
-
NA
-
250
-
0
156.25
0.61
-
0
111.86
0.44
0
79.20
0.31
0
0.98
-
255
-
255
255
255
FOSC = 4 MHz
3.579545 MHz
%
1 MHz
32.768 kHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
KBAUD ERROR
KBAUD
ERROR
KBAUD
ERROR
KBAUD ERROR
0.3
0.30
1.20
2.40
8.93
20.83
62.50
NA
-0.16
207
51
25
6
0.30
1.19
2.43
9.32
18.64
55.93
NA
+0.23
185
46
22
5
0.30
1.20
2.23
7.81
15.63
NA
+0.16
51
12
6
0.26
NA
-14.67
1
1.2
+1.67
-0.83
+0.16
-
-
-
-
-
-
-
-
-
-
-
2.4
+1.67
+1.32
-6.99
NA
-
9.6
-6.99
-2.90
-18.62
1
NA
-
19.2
76.8
96
+8.51
2
-2.90
2
-18.62
0
NA
-
-18.62
0
-27.17
0
-
-
-
-
-
-
-
NA
-
-
-
-
-
-
-
-
-
-
-
-
-
NA
-
NA
-
300
500
HIGH
LOW
NA
-
NA
-
NA
-
NA
-
NA
-
NA
-
NA
-
NA
-
62.50
0.24
0
55.93
0.22
0
15.63
0.06
0
0.51
0.002
0
255
255
255
255
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 171
PIC18CXX8
TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 40 MHz
33 MHz
25 MHz
20 MHz
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
BAUD
RATE
(Kbps)
%
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
0.3
NA
-
-
-
-
-
NA
-
-
-
-
NA
-
-
-
-
NA
-
-
-
-
1.2
NA
-
NA
-
NA
-
NA
-
2.4
NA
-
NA
-
NA
-
NA
-
9.6
NA
-
9.60
-0.07
+0.39
-0.54
+2.31
-1.79
+3.13
-
214
106
26
20
6
9.59
-0.15
+0.47
+1.73
+1.73
+4.17
+4.17
-
162
80
19
15
4
9.62
+0.16
+0.16
+1.73
+0.16
+4.17
-16.67
-
129
64
15
12
3
19.2
76.8
96
19.23
75.76
96.15
312.50
500
+0.16
-1.36
+0.16
+4.17
0
129
32
25
7
19.28
76.39
98.21
294.64
515.63
2062.50
8,06
19.30
78.13
97.66
312.50
520.83
1562.50
6.10
19.23
78.13
96.15
312.50
416.67
1250
4.88
300
500
HIGH
LOW
4
3
2
2
2500
9.77
-
0
0
0
0
-
255
-
255
-
255
-
255
FOSC = 16 MHz
10 MHz
7.15909 MHz
5.0688 MHz
BAUD
SPBRG
SPBRG
SPBRG
SPBRG
RATE
(Kbps)
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
0.3
NA
-
-
NA
-
-
NA
-
-
NA
-
-
1.2
NA
-
-
NA
-
-
NA
-
-
NA
-
-
2.4
NA
-
-
NA
-
-
2.41
+0.23
-0.83
+1.32
-2.90
-6.78
+49.15
-10.51
-
185
46
22
5
2.40
0
131
32
16
3
9.6
9.62
19.23
76.92
100
+0.16
+0.16
+0.16
+4.17
+11.11
0
103
51
12
9
9.62
18.94
78.13
89.29
312.50
625
+0.16
-1.36
+1.73
-6.99
+4.17
+25.00
-
64
32
7
9.52
9.60
0
19.2
76.8
96
19.45
74.57
89.49
447.44
447.44
447.44
1.75
18.64
79.20
105.60
316.80
NA
-2.94
+3.13
6
4
+10.00
2
300
500
HIGH
LOW
333.33
500
2
1
0
+5.60
0
1
0
0
-
-
-
-
1000
3.91
-
0
625
0
0
316.80
1.24
0
-
255
2.44
-
255
-
255
255
FOSC = 4 MHz
3.579545 MHz
1 MHz
32.768 kHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
0.3
NA
-
-
NA
-
-
0.30
1.20
2.40
8.93
20.83
62.50
NA
+0.16
207
51
25
6
0.29
1.02
2.05
NA
-2.48
6
1.2
1.20
2.40
9.62
19.23
NA
+0.16
207
103
25
12
-
1.20
+0.23
+0.23
+1.32
-2.90
-2.90
+16.52
-25.43
-
185
92
22
11
2
+0.16
-14.67
1
2.4
+0.16
2.41
+0.16
-14.67
0
9.6
+0.16
9.73
-6.99
-
-
-
-
-
-
-
-
-
19.2
76.8
96
+0.16
18.64
74.57
111.86
223.72
NA
+8.51
2
NA
-
-
-
-
-
-
-
-18.62
0
NA
-
NA
-
1
-
-
-
-
-
-
NA
-
300
500
HIGH
LOW
NA
-
0
NA
-
NA
-
NA
-
-
NA
-
NA
-
250
0.98
0
55.93
0.22
-
0
62.50
0.24
0
2.05
0.008
0
255
-
255
255
255
DS30475A-page 172
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is
empty and flag bit TXIF (PIR registers) is set. This inter-
rupt can be enabled/disabled by setting/clearing
enable bit TXIE (PIE registers). Flag bit TXIF will be
set, regardless of the state of enable bit TXIE and can-
not be cleared in software. It will reset only when new
data is loaded into the TXREG register. While flag bit
TXIF indicated the status of the TXREG register,
another bit TRMT (TXSTA register) shows the status of
the TSR register. Status bit TRMT is a read only bit,
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
16.2
USART Asynchronous Mode
In this mode, the USART uses standard
non-return-to-zero (NRZ) format (one START bit, eight
or nine data bits and one STOP bit). The most common
data format is 8-bits. An on-chip dedicated 8-bit baud
rate generator can be used to derive standard baud
rate frequencies from the oscillator. The USART trans-
mits and receives the LSb first. The USART’s transmit-
ter and receiver are functionally independent, but use
the same data format and baud rate. The baud rate
generator produces a clock, either x16 or x64 of the bit
shift rate, depending on the BRGH bit (TXSTA regis-
ter). Parity is not supported by the hardware, but can be
implemented in software (and stored as the ninth data
bit). Asynchronous mode is stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
Asynchronous mode is selected by clearing the SYNC
bit (TXSTA register).
2: Flag bit TXIF is set when enable bit TXEN
is set.
The USART Asynchronous module consists of the fol-
lowing important elements:
Steps to follow when setting up an Asynchronous
Transmission:
• Baud Rate Generator
• Sampling Circuit
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 16.1).
• Asynchronous Transmitter
• Asynchronous Receiver
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
16.2.1 USART ASYNCHRONOUS TRANSMITTER
3. If interrupts are desired, set enable bit TXIE.
The USART transmitter block diagram is shown in
Figure 16-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The TSR register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the STOP
bit has been transmitted from the previous load. As
soon as the STOP bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts trans-
mission).
FIGURE 16-1: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG register
TXIF
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
•
•
•
TSR register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 173
PIC18CXX8
FIGURE 16-2: ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(shift clock)
RC6/TX/CK (pin)
START Bit
Bit 0
Bit 1
Word 1
Bit 7/8
STOP Bit
TXIF bit
(Transmit buffer
register empty flag)
Word 1
Transmit Shift Reg
TRMT bit
(Transmit shift
register empty flag)
FIGURE 16-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(shift clock)
RC6/TX/CK (pin)
START Bit
START Bit
Word 2
Bit 0
Bit 1
Bit 7/8
Bit 0
STOP Bit
TXIF bit
(interrupt reg. flag)
Word 1
TRMT bit
(Transmit shift
reg. empty flag)
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 16-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF
PSPIE
PSPIP
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
PIE1
IPR1
RCSTA
SREN CREN
—
FERR OERR
RX9D 0000 -00x 0000 -00x
0000 0000 0000 0000
TXREG USART Transmit Register
TXSTA CSRC TX9 TXEN SYNC ADDEN BRGH TRMT
TX9D 0000 0010 0000 0010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Transmission.
DS30475A-page 174
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
16.2.2 USART ASYNCHRONOUS RECEIVER
16.2.3 SETTING UP 9-BIT MODE WITH ADDRESS
DETECT
The receiver block diagram is shown in Figure 16-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter, operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at FOSC. This mode would typi-
cally be used in RS-232 systems.
This mode would typically be used in RS-485 systems.
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enable:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is required,
set the BRGH bit.
Steps to follow when setting up an Asynchronous
Reception:
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 16.1).
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
7. The RCIF bit will be set when reception is com-
plete. The interrupt will be acknowledged if the
RCIE and GIE bits are set.
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
8. Read the 8-bit received data by reading the
RCREG register.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
9. If any error occurred, clear the error by clearing
enable bit CREN.
FIGURE 16-4: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
÷ 64
RSR Register
LSb
MSb
or
÷ 16
0
Baud Rate Generator
1
7
STOP (8)
START
• • •
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
Note:
I/O pins have diode protection to VDD and VSS.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 175
PIC18CXX8
FIGURE 16-5: ASYNCHRONOUS RECEPTION
START
bit
START
bit
START
bit7/8 STOP bit
bit
RX (pin)
bit0
bit1
STOP
bit
STOP
bit
bit0
bit7/8
bit7/8
Rcv shift
reg
Rcv buffer reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 16-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
0000 000x
0000 000u
0000 0000
0000 0000
0000 0000
PSPIF
PSPIE
PSPIP
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CREN
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 0000 0000
PIE1
IPR1
RCSTA
—
FERR
OERR
RX9D
0000 -00x
0000 0000
0000 0010
0000 0000
0000 -00x
0000 0000
0000 0010
0000 0000
RCREG
TXSTA
SPBRG
USART Receive Register
CSRC TX9
TXEN
SYNC ADDEN BRGH
TRMT
TX9D
Baud Rate Generator Register
Legend: x= unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
DS30475A-page 176
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
enabled/disabled by setting/clearing enable bit TXIE
(PIE registers). Flag bit TXIF will be set, regardless of
the state of enable bit TXIE, and cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register. While flag bit TXIF indicates the
status of the TXREG register, another bit TRMT
(TXSTA register) shows the status of the TSR register.
TRMT is a read only bit, which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR reg-
ister is empty. The TSR is not mapped in data memory,
so it is not available to the user.
16.3
USART Synchronous Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA register).
In addition, enable bit SPEN (RCSTA register) is set, in
order to configure the RC6/TX/CK and RC7/RX/DT I/O
pins to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA register).
Steps to follow when setting up a Synchronous Master
Transmission:
16.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
1. Initialize the SPBRG register for the appropriate
baud rate (Section 16.1).
The USART transmitter block diagram is shown in
Figure 16-1. The heart of the transmitter is the Transmit
(serial) Shift register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG is empty and interrupt
bit TXIF (PIR registers) is set. The interrupt can be
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
POR,
Value on all
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
BOR
RESETS
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
—
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF
PSPIE
PSPIP
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
IPR1
TXIP
RCSTA
TXREG
TXSTA
CREN
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0010 0000 0010
0000 0000 0000 0000
USART Transmit Register
CSRC TX9
TXEN
SYNC ADDEN
BRGH
TRMT
TX9D
SPBRG Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 177
PIC18CXX8
FIGURE 16-6: SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Bit 0
Bit 1
Bit 2
Bit 7
Bit 0
Bit 1
Word 2
Bit 7
RC7/RX/DT
pin
Word 1
RC6/TX/CK
pin
Write to
TXREG reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt flag)
TRMT bit
’1’
’1’
TXEN bit
Note: Sync Master mode; SPBRG = ’0’; continuous transmission of two 8-bit words.
FIGURE 16-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit2
bit1
bit6
bit7
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS30475A-page 178
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
16.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 16.1).
Once Synchronous Master mode is selected, reception
is enabled by setting either enable bit SREN (RCSTA
register), or enable bit CREN (RCSTA register). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
POR,
BOR
Value on all
other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
—
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
0000 0000
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0010
0000 0000
PIR1
PSPIF
PSPIE
PSPIP
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
CCP1IF TMR2IF TMR1IF 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000
CCP1IP TMR2IP TMR1IP 0000 0000
PIE1
IPR1
TXIP
RCSTA
CREN
FERR
OERR
RX9D
0000 -00x
0000 0000
0000 0010
0000 0000
RCREG USART Receive Register
TXSTA CSRC TX9
TXEN
SYNC
ADDEN
BRGH
TRMT
TX9D
SPBRG Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.
FIGURE 16-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Write to
bit SREN
SREN bit
CREN bit
’0’
’0’
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRGH = ’0’.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 179
PIC18CXX8
16.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
16.4
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master
mode, in that the shift clock is supplied externally at the
RC6/TX/CK pin (instead of being supplied internally in
Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA register).
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode and bit SREN, which is a "don’t care" in Slave
mode.
If receive is enabled by setting bit CREN prior to the
SLEEPinstruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register,
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector.
16.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the SLEEP
mode.
Steps to follow when setting up a Synchronous Slave
Reception:
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will be set.
5. Flag bit RCIF will be set when reception is com-
plete. An interrupt will be generated if enable bit
RCIE was set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Steps to follow when setting up a Synchronous Slave
Transmission:
7. Read the 8-bit received data by reading the
RCREG register.
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
8. If any error occurred, clear the error by clearing
bit CREN.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
DS30475A-page 180
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
POR,
BOR
Value on all
other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PSPIF
PSPIE
PSPIP
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CREN
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
IPR1
RCSTA
TXREG
TXSTA
SPBRG
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0010 0000 0010
0000 0000 0000 0000
USART Transmit Register
CSRC TX9
TXEN
SYNC ADDEN
BRGH
TRMT
TX9D
Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave transmission.
TABLE 16-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
POR,
Value on all
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
BOR
RESETS
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
—
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PSPIF
PSPIE
PSPIP
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CREN
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0010 0000 0010
0000 0000 0000 0000
USART Receive Register
CSRC TX9
TXEN
SYNC
ADDEN
BRGH
TRMT
TX9D
Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave reception.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 181
PIC18CXX8
NOTES:
DS30475A-page 182
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
17.1.1 OVERVIEW OF THE MODULE
17.0 CAN MODULE
The CAN bus module consists of a Protocol Engine
and message buffering and control. The CAN protocol
engine handles all functions for receiving and transmit-
ting messages on the CAN bus. Messages are trans-
mitted by first loading the appropriate data registers.
Status and errors can be checked by reading the
appropriate registers. Any message detected on the
CAN bus is checked for errors and then matched
against filters to see if it should be received and stored
in one of the 2 receive registers.
17.1
Overview
The Controller Area Network (CAN) module is a serial
interface, useful for communicating with other peripher-
als or microcontroller devices. This interface/protocol
was designed to allow communications within noisy
environments.
The CAN module is a communication controller imple-
menting the CAN 2.0 A/B protocol as defined in the
BOSCH specification. The module will support CAN
1.2, CAN 2.0A, CAN2.0B Passive, and CAN 2.0B
Active versions of the protocol. The module implemen-
tation is a Full CAN system. The CAN specification is
not covered within this data sheet. The reader may
refer to the BOSCH CAN specification for further
details.
The CAN Module supports the following Frame types:
• Standard Data Frame
• Extended Data Frame
• Remote Frame
• Error Frame
• Overload Frame Reception
• Interframe Space
The module features are as follows:
• Implementation of the CAN protocol CAN1.2,
CAN2.0A and CAN2.0B
• Standard and extended data frames
• 0 - 8 bytes data length
• Programmable bit rate up to 1 Mbit/sec
• Support for remote frames
• Double buffered receiver with two prioritized
received message storage buffers
• 6 full (standard/extended identifier) acceptance fil-
ters, 2 associated with the high priority receive
buffer, and 4 associated with the low priority
receive buffer
• 2 full acceptance filter masks, one each associ-
ated with the high and low priority receive buffers
• Three transmit buffers with application specified
prioritization and abort capability
• Programmable wake-up functionality with inte-
grated low-pass filter
• Programmable Loopback mode supports self-test
operation
• Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
• Programmable clock source
• Programmable link to timer module for
time-stamping and network synchronization
• Low power SLEEP mode
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 183
PIC18CXX8
17.1.2 TRANSMIT/RECEIVE BUFFERS
The PIC18CXX8 has three transmit and two receive
buffers, two acceptance masks (one for each receive
buffer), and a total of six acceptance filters. Figure 17-1
is a block diagram of these buffers and their connection
to the protocol engine.
FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM
Acceptance Mask
RXM1
BUFFERS
Acceptance Filter
RXF2
A
c
c
e
p
t
Acceptance Mask
Acceptance Filter
RXF3
TXB0
TXB1
TXB2
RXM0
A
c
c
e
p
t
Acceptance Filter
RXF0
Acceptance Filter
RXF4
Acceptance Filter
RXF1
Acceptance Filter
RXF5
R
X
B
0
R
X
B
1
M
A
B
Identifier
Identifier
Message
Queue
Control
Transmit Byte Sequencer
Data Field
Data Field
Receive
Error
Counter
RXERRCNT
TXERRCNT
PROTOCOL
ENGINE
Transmit
Error
ErrPas
BusOff
Counter
Transmit Shift
Receive Shift
CRC Check
Protocol
Finite
State
CRC Generator
Machine
Bit
Timing
Logic
Transmit
Logic
Bit Timing
Generator
TX
RX
DS30475A-page 184
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
17.2.1 CAN CONTROL AND STATUS REGISTERS
17.2
Control Registers for the CAN Module
This section shows the CAN Control and Status
registers.
Note: Not all CAN registers are available in the
access bank.
There are many registers associated with the CAN
module. Descriptions of these registers are grouped
into sections. These sections are:
• Control and Status Registers
• Transmit Buffer Registers
• Receive Buffer Registers
• Baud Rate Control Registers
• Interrupt Status and Control Registers
REGISTER 17-1: CANCON – CAN CONTROL REGISTER
R/W-1
R/W-0
R/W-0
R/W-0
ABAT
R/W-0
WIN2
R/W-0
WIN1
R/W-0
WIN0
U-0
—
REQOP2 REQOP1 REQOP0
bit 7
bit 0
bit 7-5
REQOP2:REQOP0: Request CAN Operation Mode bits
1xx= Request Configuration mode
011= Request Listen Only mode
010= Request Loopback mode
001= Request Disable mode
000= Request Normal mode
bit 4
ABAT: Abort All Pending Transmissions bit
1 = Abort all pending transmissions (in all transmit buffers)
0 = Transmissions proceeding as normal
bit 3-1
WIN2:WIN0: Window Address bits
This selects which of the CAN buffers to switch into the access bank area. This allows access
to the buffer registers from any data memory bank. After a frame has caused an interrupt, the
ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer. See
Example 17-1 for code example.
111= Receive Buffer 0
110= Receive Buffer 0
101= Receive Buffer 1
100= Transmit Buffer 0
011= Transmit Buffer 1
010= Transmit Buffer 2
001= Receive Buffer 0
000= Receive Buffer 0
bit 0
Unimplemented: Read as ’0’
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2000 Microchip Technology Inc.
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DS30475A-page 185
PIC18CXX8
REGISTER 17-2: CANSTAT – CAN STATUS REGISTER
R-1
R-0
R-0
U-0
—
R-0
R-0
R-0
U-0
—
OPMODE2 OPMODE1 OPMODE0
bit 7
ICODE2 ICODE1 ICODE0
bit 0
bit 7-5
OPMODE2:OPMODE0: Operation Mode Status bits
111= Reserved
110= Reserved
101= Reserved
100= Configuration mode
011= Listen Only mode
010= Loopback mode
001= Disable mode
000= Normal mode
Note: Before the device goes into SLEEP mode, select Disable mode.
bit 4
Unimplemented: Read as ’0’
bit 3-1
ICODE2:ICODE0: Interrupt Code bits
When an interrupt occurs, a prioritized coded interrupt value will be present in the
ICODE2:ICODE0 bits. These codes indicate the source of the interrupt. The ICODE2:ICODE0
bits can be copied to the WIN2:WIN0 bits to select the correct buffer to map into the Access
Bank area. See Example 17-1 for code example.
111= Wake-up on Interrupt
110= RXB0 Interrupt
101= RXB1 Interrupt
100= TXB0 Interrupt
011= TXB1 Interrupt
010= TXB2 Interrupt
001= Error Interrupt
000= No Interrupt
bit 0
Unimplemented: Read as ’0’
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30475A-page 186
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
EXAMPLE 17-1: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS
TX/RX BUFFERS
; Save application required context.
; Poll interrupt flags and determine source of interrupt
; This was found to be CAN interrupt
; TempCANCON and TempCANSTAT are variables defined in Access Bank low
movff
CANCON, TempCANCON
; Save CANCON.WIN bits
; This is required to prevent CANCON
; from corrupting CAN buffer access
; in-progress while this interrupt
; occurred
movff
CANSTAT, TempCANSTAT
; Save CANSTAT register
; This is required to make sure that
; we use same CANSTAT value rather
; than one changed by another CAN
; interrupt.
movf
andlw
addwf
TempCANSTAT, W
b’00001110’
PCL, F
; Retrieve ICODE bits
; Perform computed GOTO
; to corresponding interrupt cause
bra
bra
bra
bra
bra
bra
bra
NoInterrupt
; 000 = No interrupt
ErrorInterrupt
TXB2Interrupt
TXB1Interrupt
TXB0Interrupt
RXB1Interrupt
RXB0Interrupt
; 001 = Error interrupt
; 010 = TXB2 interrupt
; 011 = TXB1 interrupt
; 100 = TXB0 interrupt
; 101 = RXB1 interrupt
; 110 = RXB0 interrupt
; 111 = Wake-up on interrupt
WakeupInterrupt
bcf
PIR3, WAKIF
; Clear the interrupt flag
;
; User code to handle wake-up procedure
;
;
; Continue checking for other interrupt source or return from here
…
NoInterrupt
…
; PC should never vector here. User may
; place a trap such as infinite loop or pin/port
; indication to catch this error.
ErrorInterrupt
bcf
…
PIR3, ERRIF
; Clear the interrupt flag
; Handle error.
retfie
TXB2Interrupt
bcf
goto
PIR3, TXB2IF
AccessBuffer
; Clear the interrupt flag
; Clear the interrupt flag
; Clear the interrupt flag
; Clear the interrupt flag
TXB1Interrupt
bcf
goto
PIR3, TXB1IF
AccessBuffer
TXB0Interrupt
bcf
goto
PIR3, TXB0IF
AccessBuffer
RXB1Interrupt
bcf
goto
PIR3, RXB1IF
Accessbuffer
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 187
PIC18CXX8
RXB0Interrupt
bcf
goto
PIR3, RXB0IF
AccessBuffer
; Clear the interrupt flag
AccessBuffer
; This is either TX or RX interrupt
; Copy CANCON.ICODE bits to CANSTAT.WIN bits
movf
TempCANCON, W
; Clear CANCON.WIN bits before copying
; new ones.
andlw
movwf
b’11110001’
; Use previously saved CANCON value to
; make sure same value.
; Copy masked value back to TempCANCON
TempCANCON
movf
TempCANSTAT, W
; Retrieve ICODE bits
andlw
b’00001110’
; Use previously saved CANSTAT value
; to make sure same value.
iorwf
movff
TempCANCON
TempCANCON, CANCON
; Copy ICODE bits to WIN bits.
; Copy the result to actual CANCON
; Access current buffer…
; Your code
; Restore CANCON.WIN bits
movf
andlw
iorwf
CANCON, W
b’11110001’
TempCANCON
; Preserve current non WIN bits
; Restore original WIN bits
; Do not need to restore CANSTAT - it is read-only register.
; Return from interrupt or check for another module interrupt source
DS30475A-page 188
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
REGISTER 17-3: COMSTAT – COMMUNICATION STATUS REGISTER
R/C-0
R/C-0
R-0
R-0
R-0
R-0
R-0
R-0
RXB0OVFL RXB1OVFL TXBO
bit 7
TXBP
RXBP TXWARN RXWARN EWARN
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RXB0OVFL: Receive Buffer 0 Overflow bit
1= Receive Buffer 0 overflowed
0= Receive Buffer 0 has not overflowed
RXB1OVFL: Receive Buffer 1 Overflow bit
1= Receive Buffer 1 overflowed
0= Receive Buffer 1 has not overflowed
TXB0: Transmitter Bus Off bit
1= Transmit Error Counter >255
0= Transmit Error Counter ≤ 255
TXBP: Transmitter Bus Passive bit
1= Transmission Error Counter >127
0= Transmission Error Counter ≤127
RXBP: Receiver Bus Passive bit
1= Receive Error Counter >127
0= Receive Error Counter ≤127
TXWARN: Transmitter Warning bit
1= Transmit Error Counter >95
0= Transmit Error Counter ≤95
RXWARN: Receiver Warning bit
1= Receive Error Counter >95
0= Receive Error Counter ≤ 95
EWARN: Error Warning bit
This bit is a flag of the RXWARN and TXWARN bits
1= The RXWARN or the TXWARN bits are set
0= Neither the RXWARN or the TXWARN bits are set
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2000 Microchip Technology Inc.
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DS30475A-page 189
PIC18CXX8
17.2.2 CAN TRANSMIT BUFFER REGISTERS
This section describes the CAN Transmit Buffer Register
and the associated Transmit Buffer Control Registers.
REGISTER 17-4: TXBnCON – TRANSMIT BUFFER n CONTROL REGISTER
U-0
—
R-0
R-0
R-0
R/W-0
U-0
—
R/W-0
R/W-0
TXABT
TXLARB
TXERR
TXREQ
TXPRI1
TXPRI0
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ’0’
TXABT: Transmission Aborted Status bit
1= Message was aborted
0= Message was not aborted
bit 5
bit 4
bit 3
TXLARB: Transmission Lost Arbitration Status bit
1= Message lost arbitration while being sent
0= Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit
1= A bus error occurred while the message was being sent
0= A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit
1= Requests sending a message. Clears the TXABT, TLARB, and TXERR bits
0= Automatically cleared when the message is successfully sent
Note: Clearing this bit in software, while the bit is set, will request a message abort.
Unimplemented: Read as ’0’
bit 2
bit 1-0
TXPRI1:TXPRI0: Transmit Priority bits
11= Priority Level 3 (Highest Priority)
10= Priority Level 2
01= Priority Level 1
00= Priority Level 0 (Lowest Priority)
Note: These bits set the order in which Transmit buffer will be transferred. They do not
alter CAN message identifier.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
REGISTER 17-5: TXBnSIDH:TRANSMITBUFFERnSTANDARDIDENTIFIERHIGHBYTEREGISTER
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
bit 7-0
SID10:SID3: Standard Identifier bits, if EXIDE = 0 (TXBnSID Register).
Extended Identifier bits EID28:EID21, if EXIDE = 1.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30475A-page 190
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PIC18CXX8
REGISTER 17-6: TXBnSIDL – TRANSMIT BUFFER n STANDARD IDENTIFIER LOW BYTE
REGISTER
R/W-x
R/W-x
SID1
R/W-x
SID0
R/W-x
—
R/W-x
EXIDE
R/W-x
—
R/W-x
EID17
R/W-x
EID16
SID2
bit 7
bit 0
bit 7-5
SID2:SID0: Standard Identifier bits, if EXIDE = 0.
Extended Identifier bits EID20:EID18, if EXIDE = 1.
bit 4
bit 3
Unimplemented: Read as ’0’
EXIDE: Extended Identifier Enable bit
1= Message will transmit Extended ID, SID10:SID0 becomes EID28:EID18
0= Message will transmit Standard ID, EID17:EID0 are ignored
bit 2
Unimplemented: Read as ’0’
bit 1-0
EID17:EID16: Extended Identifier bits
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 17-7: TXBnEIDH – TRANSMIT BUFFER n EXTENDED IDENTIFIER HIGH BYTE
REGISTER
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
bit 7-0
EID15:EID8: Extended Identifier bits
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 17-8: TXBnEIDL – TRANSMIT BUFFER n EXTENDED IDENTIFIER LOW BYTE
REGISTER
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
bit 7-0
EID7:EID0: Extended Identifier bits
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 191
PIC18CXX8
REGISTER 17-9: TXBnDm – TRANSMIT BUFFER n DATA FIELD BYTE m REGISTER
R/W-x
TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0
bit 7 bit 0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 1-0
TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Byte m bits (where 0≤n<3 and 0<m<8)
Each Transmit Buffer has an array of registers. For example, Transmit buffer 0 has 7 registers:
TXB0D0 to TXB0D7.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 17-10: TXBnDLC – TRANSMIT BUFFER n DATA LENGTH CODE REGISTER
U-0
—
R/W-x
U-0
—
U-0
—
R/W-x
DLC3
R/W-x
DLC2
R/W-x
DLC1
R/W-x
DLC0
TXRTR
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ’0’
TXRTR: Transmission Frame Remote Transmission Request bit
1= Transmitted message will have TXRTR bit set
0= Transmitted message will have TXRTR bit cleared.
bit 5-4
bit 3-0
Unimplemented: Read as ’0’
DLC3:DLC0: Data Length Code bits
1111= Reserved
1110= Reserved
1101= Reserved
1100= Reserved
1011= Reserved
1010= Reserved
1001= Reserved
1000= Data Length = 8 bytes
0111= Data Length = 7 bytes
0110= Data Length = 6 bytes
0101= Data Length = 5 bytes
0100= Data Length = 4 bytes
0011= Data Length = 3 bytes
0010= Data Length = 2 bytes
0001= Data Length = 1 bytes
0000= Data Length = 0 bytes
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’0’ = Bit is cleared
x = Bit is unknown
DS30475A-page 192
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
REGISTER 17-11: TXERRCNT – TRANSMIT ERROR COUNT REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
bit 7
bit 0
bit 7-0
TEC7:TEC0: Transmit Error Counter bits
This register contains a value which is derived from the rate at which errors occur. When the
error count overflows, the bus off state occurs. When the bus has 128 occurrences of 11 con-
secutive recessive bits, the counter value is cleared.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 193
PIC18CXX8
17.2.3 CAN RECEIVE BUFFER REGISTERS
This section shows the Receive Buffer registers with its
associated control registers.
REGISTER 17-12: RXB0CON – RECEIVE BUFFER 0 CONTROL REGISTER
R/C-0
R/W-0
RXM1
R/W-0
RXM0
U-0
—
R-0
R/W-0
R-0
R/W-0
RXFUL
RXRTRRO RXB0DBEN
JTOFF
FILHIT0
bit 7
bit 0
bit 7
RXFUL: Receive Full Status bit
1= Receive buffer contains a received message
0= Receive buffer is open to receive a new message
Note: This bit is set by the CAN module and should be cleared by software after the buffer
is read.
bit 6-5
RXM1:RXM0: Receive Buffer Mode bits
11= Receive all messages (including those with errors)
10= Receive only valid messages with extended identifier
01= Receive only valid messages with standard identifier
00= Receive all valid messages
bit 4
bit 3
Unimplemented: Read as ’0’
RXRTRRO: Receive Remote Transfer Request Read Only bit
1= Remote transfer request
0= No remote transfer request
bit 2
bit 1
RXB0DBEN: Receive Buffer 0 Double Buffer Enable bit
1= Receive Buffer 0 overflow will write to Receive Buffer 1
0= No Receive Buffer 0 overflow to Receive Buffer 1
JTOFF: Jump Table Offset bit (read only copy of RX0DBEN)
1= Allows Jump Table offset between 6 and 7
0= Allows Jump Table offset between 1 and 0
Note: This bit allows same filter jump table for both RXB0CON and RXB1CON.
bit 0
FILHIT0: Filter Hit bit
This bit indicates which acceptance filter enabled the message reception into receive buffer 0
1= Acceptance Filter 1 (RXF1)
0= Acceptance Filter 0 (RXF0)
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30475A-page 194
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PIC18CXX8
REGISTER 17-13: RXB1CON – RECEIVE BUFFER 1 CONTROL REGISTER
R/C-0
R/W-0
RXM1
R/W-0
RXM0
U-0
—
R-0
RXRTRRO FILHIT2 FILHIT1 FILHIT0
bit 0
R-0
R-0
R-0
RXFUL
bit 7
bit 7
RXFUL: Receive Full Status bit
1= Receive buffer contains a received message
0= Receive buffer is open to receive a new message
Note: This bit is set by the CAN module and should be cleared by software after the buffer
is read.
bit 6-5
RXM1:RXM0: Receive Buffer Mode bits
11= Receive all messages (including those with errors)
10= Receive only valid messages with extended identifier
01= Receive only valid messages with standard identifier
00= Receive all valid messages
bit 4
bit 3
Unimplemented: Read as ’0’
RXRTRRO: Receive Remote Transfer Request bit (read only)
1= Remote transfer request
0= No remote transfer request
bit 2-0
FILHIT2:FILHIT0: Filter Hit bits
These bits indicate which acceptance filter enabled the last message reception into Receive
Buffer 1.
111= Reserved
110= Reserved
101= Acceptance Filter 5 (RXF5)
100= Acceptance Filter 4 (RXF4)
011= Acceptance Filter 3 (RXF3)
010= Acceptance Filter 2 (RXF2)
001= Acceptance Filter 1 (RXF1) only possible when RXB0DBEN bit is set
000= Acceptance Filter 0 (RXF0) only possible when RXB0DBEN bit is set
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 17-14: RXBnSIDH – RECEIVE BUFFER n STANDARD IDENTIFIER HIGH BYTE
REGISTER
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
bit 7-0
SID10:SID3: Standard Identifier bits, if EXID = 0 (RXBnSIDL Register).
Extended Identifier bits EID28:EID21, if EXID = 1.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 195
PIC18CXX8
REGISTER 17-15: RXBnSIDL – RECEIVE BUFFER n STANDARD IDENTIFIER LOW BYTE
REGISTER
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
R/W-x
SRR
R/W-x
EXID
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
bit 7-5
bit 4
SID2:SID0: Standard Identifier bits, if EXID = 0.
Extended Identifier bits EID20:EID18, if EXID = 1.
SRR: Substitute Remove Request bit (only when EXID = ’1’)
1= Remote transfer request occurred
0= No remote transfer request occurred
bit 3
EXID: Extended Identifier bit
1= Received message is an Extended Data Frame, SID10:SID0 are EID28:EID18
0= Received message is a Standard Data Frame
bit 2
Unimplemented: Read as ’0’
bit 1-0
EID17:EID16: Extended Identifier bits
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 17-16: RXBnEIDH – RECEIVE BUFFER n EXTENDED IDENTIFIER HIGH BYTE
REGISTER
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
bit 7-0
EID15:EID8: Extended Identifier bits
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 17-17: RXBnEIDL – RECEIVE BUFFER n EXTENDED IDENTIFIER LOW BYTE
REGISTER
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
bit 7-0
EID7:EID0: Extended Identifier bits
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’0’ = Bit is cleared
x = Bit is unknown
DS30475A-page 196
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PIC18CXX8
REGISTER 17-18: RXBnDLC – RECEIVE BUFFER n DATA LENGTH CODE REGISTER
U-x
—
R/W-x
R/W-x
RB1
R/W-x
RB0
R/W-x
DLC3
R/W-x
DLC2
R/W-x
DLC1
R/W-x
DLC0
RXRTR
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ’0’
RXRTR: Receiver Remote Transmission Request bit
1= Remote transfer request
0= No remote transfer request
bit 5
RB1: Reserved bit 1
Reserved by CAN Spec and read as ’0’
bit 4
RB0: Reserved bit 0
Reserved by CAN Spec and read as ’0’
bit 3-0
DLC3:DLC0: Data Length Code bits
1111= Invalid
1110= Invalid
1101= Invalid
1100= Invalid
1011= Invalid
1010= Invalid
1001= Invalid
1000= Data Length = 8 bytes
0111= Data Length = 7 bytes
0110= Data Length = 6 bytes
0101= Data Length = 5 bytes
0100= Data Length = 4 bytes
0011= Data Length = 3 bytes
0010= Data Length = 2 bytes
0001= Data Length = 1 bytes
0000= Data Length = 0 bytes
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 17-19: RXBnDm – RECEIVE BUFFER n DATA FIELD BYTE m REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0
bit 7 bit 0
R/W-x
bit 7-0
RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0≤n<1 and 0<m<7)
Each Receive Buffer has an array of registers. For example, Receive buffer 0 has 8 registers:
RXB0D0 to RXB0D7.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 197
PIC18CXX8
REGISTER 17-20: RXERRCNT – RECEIVE ERROR COUNT REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
bit 7
bit 0
bit 7-0
REC7:REC0: Receive Error Counter bits
This register contains the Receive Error value as defined by the CAN specifications.
When RXERRCNT > 127, the module will go into an error passive state. RXERRCNT does not
have the ability to put the module in “Bus Off” state.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30475A-page 198
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2000 Microchip Technology Inc.
PIC18CXX8
17.2.4 MESSAGE ACCEPTANCE FILTERS
This subsection describes the Message Acceptance
filters.
REGISTER 17-21: RXFnSIDH – RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER
HIGH BYTE
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
bit 7-0
SID10:SID3: Standard Identifier Filter bits, if EXIDEN = 0.
Extended Identifier Filter bits EID28:EID21, if EXIDEN = 1,
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 17-22: RXFnSIDL – RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER
LOW BYTE
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
U-0
—
R/W-x
EID17
R/W-x
EID16
EXIDEN
bit 7
bit 0
bit 7-5
SID2:SID0: Standard Identifier Filter bits, if EXIDEN = 0.
Extended Identifier Filter bits EID20:EID18, if EXIDEN = 0.
bit 4
bit 3
Unimplemented: Read as ’0’
EXIDEN: Extended Identifier Filter Enable bit
1 = Filter will only accept Extended ID messages
0 = Filter will only accept Standard ID messages
bit 2
Unimplemented: Read as ’0’
bit 1-0
EID17:EID16: Extended Identifier Filter bits
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 17-23: RXFnEIDH – RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER HIGH
BYTE
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
bit 7-0
EID15:EID8: Extended Identifier Filter bits
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’0’ = Bit is cleared
x = Bit is unknown
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 199
PIC18CXX8
REGISTER 17-24: RXFnEIDL – RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER LOW
BYTE REGISTER
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
bit 7-0
EID7:EID0: Extended Identifier Filter bits
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 17-25: RXMnSIDH – RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK
HIGH BYTE REGISTER
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
bit 7-0
SID10:SID3: Standard Identifier Mask bits, or Extended Identifier Mask bits EID28:EID21
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 17-26: RXMnSIDL – RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK
LOW BYTE REGISTER
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
U-0
—
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
bit 7-5
bit 4-2
bit 1-0
SID2:SID0: Standard Identifier Mask bits, or Extended Identifier Mask bits EID20:EID18
Unimplemented: Read as ’0’
EID17:EID16: Extended Identifier Mask bits
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30475A-page 200
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
REGISTER 17-27: RXMnEIDH – RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK
HIGH BYTE REGISTER
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
bit 1-0
EID15:EID8: Extended Identifier Mask bits
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 17-28: RXMnEIDL – RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK
LOW BYTE REGISTER
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
bit 1-0
EID7:EID0: Extended Identifier Mask bits
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 201
PIC18CXX8
17.2.5 CAN BAUD RATE REGISTERS
This subsection describes the CAN Baud Rate
registers.
REGISTER 17-29: BRGCON1 – BAUD RATE CONTROL REGISTER 1
R/W-0
SJW1
R/W-0
SJW0
R/W-0
BRP5
R/W-0
BRP4
R/W-0
BRP3
R/W-0
BRP2
R/W-0
BRP1
R/W-0
BRP0
bit 7
bit 0
bit 7-6
bit 5-0
SJW1:SJW0: Synchronized Jump Width bits
11= Synchronization Jump Width Time = 4 x TQ
10= Synchronization Jump Width Time = 3 x TQ
01= Synchronization Jump Width Time = 2 x TQ
00= Synchronization Jump Width Time = 1 x TQ
BRP5:BRP0: Baud Rate Prescaler bits
111111= TQ = (2 x 64)/FOSC
111110= TQ = (2 x 63)/FOSC
:
:
000001= TQ = (2 x 2)/FOSC
000000= TQ = (2 x 1)/FOSC
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’0’ = Bit is cleared
x = Bit is unknown
Note: This register is only accessible in Configuration mode.
DS30475A-page 202
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PIC18CXX8
REGISTER 17-30: BRGCON2 – BAUD RATE CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0
R/W-0
R/W-0
R/W-0
bit 7
bit 0
bit 7
SEG2PHTS: Phase Segment 2 Time Select bit
1= Freely programmable
0= Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater
bit 6
SAM: Sample of the CAN Bus Line bit
1= Bus line is sampled three times prior to the sample point
0= Bus line is sampled once at the sample point
bit 5-3
SEG1PH2:SEG1PH0: Phase Segment 1 bits
111= Phase Segment 1 Time = 8 x TQ
110= Phase Segment 1 Time = 7 x TQ
101= Phase Segment 1 Time = 6 x TQ
100= Phase Segment 1 Time = 5 x TQ
011= Phase Segment 1 Time = 4 x TQ
010= Phase Segment 1 Time = 3 x TQ
001= Phase Segment 1 Time = 2 x TQ
000= Phase Segment 1 Time = 1 x TQ
bit 2-0
PRSEG2:PRSEG0: Propagation Time Select bits
111= Propagation Time = 8 x TQ
110= Propagation Time = 7 x TQ
101= Propagation Time = 6 x TQ
100= Propagation Time = 5 x TQ
011= Propagation Time = 4 x TQ
010= Propagation Time = 3 x TQ
001= Propagation Time = 2 x TQ
000= Propagation Time = 1 x TQ
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
Note: This register is only accessible in Configuration mode.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 203
PIC18CXX8
REGISTER 17-31: BRGCON3 – BAUD RATE CONTROL REGISTER 3
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
WAKFIL
SEG2PH2 SEG2PH1 SEG2PH0
bit 0
bit 7
bit 7
bit 6
Unimplemented: Read as ’0’
WAKFIL: Selects CAN Bus Line Filter for Wake-up bit
1= Use CAN bus line filter for wake-up
0= CAN bus line filter is not used for wake-up
bit 5-3
bit 2-0
Unimplemented: Read as ’0’
SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits
111= Phase Segment 2 Time = 8 x TQ
110= Phase Segment 2 Time = 7 x TQ
101= Phase Segment 2 Time = 6 x TQ
100= Phase Segment 2 Time = 5 x TQ
011= Phase Segment 2 Time = 4 x TQ
010= Phase Segment 2 Time = 3 x TQ
001= Phase Segment 2 Time = 2 x TQ
000= Phase Segment 2 Time = 1 x TQ
Note:
Ignored if SEG2PHTS bit is clear.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’0’ = Bit is cleared
x = Bit is unknown
DS30475A-page 204
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
17.2.6 CAN MODULE I/O CONTROL REGISTER
This subsection describes the CAN Module I/O Control
register.
REGISTER 17-32: CIOCON – CAN I/O CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
TX1SRC
TX1EN
ENDRHI CANCAP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3-0
TX1SRC: CAN TX1 Pin Data Source
1= CAN TX1 pin will output the CAN clock
0= CAN TX1 pin will output TXD
TX1EN: CAN TX1 Pin Enable
1= CAN TX1 pin will output TXD or CAN clock
0= CAN TX1 pin will have digital I/O function
ENDRHI: Enable Drive High
1= CAN TX0, CAN TX1 pins will drive VDD when recessive
0= CAN TX0, CAN TX1 pins will tri-state when recessive
CANCAP: CAN Message Receive Capture Enable
1= Enable CAN capture
0= Disable CAN capture
Unimplemented: Read as ’0’
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 205
PIC18CXX8
17.2.7 CAN INTERRUPT REGISTERS
REGISTER 17-33: PIR3 – PERIPHERAL INTERRUPT FLAG REGISTER
R/W-0
IRXIF
R/W-0
R/W-0
ERRIF
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKIF
TXB2IF
TXB1IF
TXB0IF RXB1IF
RXB0IF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IRXIF: CAN Invalid Received Message Interrupt Flag bit
1= An invalid message has occurred on the CAN bus
0= No invalid message on CAN bus
WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit
1= Activity on CAN bus has occurred
0= No activity on CAN bus
ERRIF: CAN Bus Error Interrupt Flag bit
1= An error has occurred in the CAN module (multiple sources)
0= No CAN module errors
TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit
1= Transmit Buffer 2 has completed transmission of a message, and may be re-loaded
0= Transmit Buffer 2 has not completed transmission of a message
TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit
1= Transmit Buffer 1 has completed transmission of a message, and may be re-loaded
0= Transmit Buffer 1 has not completed transmission of a message
TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit
1= Transmit Buffer 0 has completed transmission of a message, and may be re-loaded
0= Transmit Buffer 0 has not completed transmission of a message
RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit
1= Receive Buffer 1 has received a new message
0= Receive Buffer 1 has not received a new message
RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit
1= Receive Buffer 0 has received a new message
0= Receive Buffer 0 has not received a new message
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30475A-page 206
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
REGISTER 17-34: PIE3 – PERIPHERAL INTERRUPT ENABLE REGISTER
R/W-0
IRXIE
R/W-0
R/W-0
ERRIE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKIE
TXB2IE
TXB1IE TXB0IE RXB1IE
RXB0IE
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IRXIE: CAN Invalid Received Message Interrupt Enable bit
1= Enable invalid message received interrupt
0= Disable invalid message received interrupt
WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit
1= Enable bus activity wake-up interrupt
0= Disable bus activity wake-up interrupt
ERRIE: CAN Bus Error Interrupt Enable bit
1= Enable CAN bus error interrupt
0= Disable CAN bus error interrupt
TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit
1= Enable Transmit Buffer 2 interrupt
0= Disable Transmit Buffer 2 interrupt
TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit
1= Enable Transmit Buffer 1 interrupt
0= Disable Transmit Buffer 1 interrupt
TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit
1= Enable Transmit Buffer 0 interrupt
0= Disable Transmit Buffer 0 interrupt
RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit
1= Enable Receive Buffer 1 interrupt
0= Disable Receive Buffer 1 interrupt
RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit
1= Enable Receive Buffer 0 interrupt
0= Disable Receive Buffer 0 interrupt
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 207
PIC18CXX8
REGISTER 17-35: IPR3 – PERIPHERAL INTERRUPT PRIORITY REGISTER
R/W-0
IRXIP
R/W-0
R/W-0
ERRIP
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKIP
TXB2IP
TXB1IP TXB0IP RXB1IP
RXB0IP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IRXIP: CAN Invalid Received Message Interrupt Priority bit
1= High priority
0= Low priority
WAKIP: CAN Bus Activity Wake-up Interrupt Priority bit
1= High priority
0= Low priority
ERRIP: CAN bus Error Interrupt Priority bit
1= High priority
0= Low priority
TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit
1= High priority
0= Low priority
TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit
1= High priority
0= Low priority
TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit
1= High priority
0= Low priority
RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit
1= High priority
0= Low priority
RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30475A-page 208
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 17-1: CAN CONTROLLER REGISTER MAP
Address
Name
Address
Name
Address
Name
Address
Name
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
F5Fh
F3Fh
F1Fh RXM1EIDL
F1Eh RXM1EIDH
F1Dh RXM1SIDL
F1Ch RXM1SIDH
F1Bh RXM0EIDL
F1Ah RXM0EIDH
F19h RXM0SIDL
F18h RXM0SIDH
F17h RXF5EIDL
F16h RXF5EIDH
F15h RXF5SIDL
F14h RXF5SIDH
F13h RXF4EIDL
F12h RXF4EIDH
F11h RXF4SIDL
F10h RXF4SIDH
F0Fh RXF3EIDL
F0Eh RXF3EIDH
F0Dh RXF3SIDL
F0Ch RXF3SIDH
F0Bh RXF2EIDL
F0Ah RXF2EIDH
F09h RXF2SIDL
F08h RXF2SIDH
F07h RXF1EIDL
F06h RXF1EIDH
F05h RXF1SIDL
F04h RXF1SIDH
F03h RXF0EIDH
F02h RXF0EIDL
F01h RXF0SIDL
F00h RXF0SIDH
F5Eh CANSTAT
F5Dh RXB1D7
F5Ch RXB1D6
F5Bh RXB1D5
F5Ah RXB1D4
F59h RXB1D3
F58h RXB1D2
F57h RXB1D1
F56h RXB1D0
F55h RXB1DLC
F54h RXB1EIDL
F53h RXB1EIDH
F52h RXB1SIDL
F51h RXB1SIDH
F50h RXB1CON
F4Fh
F4Eh CANSTAT
F4Dh TXB0D7
F4Ch TXB0D6
F4Bh TXB0D5
F4Ah TXB0D4
F49h TXB0D3
F48h TXB0D2
F47h TXB0D1
F46h TXB0D0
F45h TXB0DLC
F44h TXB0EIDL
F43h TXB0EIDH
F42h TXB0SIDL
F41h TXB0SIDH
F40h TXB0CON
F3Eh CANSTAT
F3Dh TXB1D7
F3Ch TXB1D6
F3Bh TXB1D5
F3Ah TXB1D4
F39h TXB1D3
F38h TXB1D2
F37h TXB1D1
F36h TXB1D0
F35h TXB1DLC
F34h TXB1EIDL
F33h TXB1EIDH
F32h TXB1SIDL
F31h TXB1SIDH
F30h TXB1CON
F2Fh
F2Eh CANSTAT
F2Dh TXB2D7
F2Ch TXB2D6
F2Bh TXB2D5
F2Ah TXB2D4
F29h TXB2D3
F28h TXB2D2
F27h TXB2D1
F26h TXB2D0
F25h TXB2DLC
F24h TXB2EIDL
F23h TXB2EIDH
F22h TXB2SIDL
F21h TXB2SIDH
F20h TXB2CON
F76h TXERRCNT
F75h RXERRCNT
F74h COMSTAT
F73h CIOCON
F72h BRGCON3
F71h BRGCON2
F70h BRGCON1
F6Fh CANCON
F6Eh CANSTAT
F6Dh RXB0D7
F6Ch RXB0D6
F6Bh RXB0D5
F6Ah RXB0D4
F69h RXB0D3
F68h RXB0D2
F67h RXB0D1
F66h RXB0D0
F65h RXB0DLC
F64h RXB0EIDL
F63h RXB0EIDH
F62h RXB0SIDL
F61h RXB0SIDH
F60h RXB0CON
Note: Shaded registers are available in Access Bank Low area while the rest are available in Bank 15.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 209
PIC18CXX8
17.3.2 DISABLE MODE
17.3
CAN Modes of Operation
In Disable mode, the module will not transmit or
receive. The module has the ability to set the WAKIF bit
due to bus activity, however, any pending interrupts will
remain and the error counters will retain their value.
The PIC18CXX8 has the following modes of operation.
These modes are:
• Configuration mode
• Disable mode
If REQOP<2:0> is set to 001, the module will enter the
module Disable mode. This mode is similar to dis-
abling other peripheral modules by turning off the mod-
ule enables. This causes the module internal clock to
stop unless the module is active (i.e., receiving or
transmitting a message). If the module is active, the
module will wait for 11 recessive bits on the CAN bus,
detect that condition as an idle bus, then accept the
module disable command. OPMODE<2:0>=001 indi-
cates whether the module successfully went into mod-
ule Disable mode
• Normal Operation mode
• Listen Only mode
• Loopback mode
• Error Recognition mode (selected through
CANRXM bits)
Modes are requested by setting the REQOP bits,
except the Error Recognition mode, which is requested
through the CANRXM bits. Entry into a mode is
acknowledged by monitoring the OPMODE bits.
When changing modes, the mode will not actually
change until all pending message transmissions are
complete. Because of this, the user must verify that the
device has actually changed into the requested mode
before further operations are executed.
The WAKIF interrupt is the only module interrupt that is
still active in the module Disable mode. If the WAKIE is
set, the processor will receive an interrupt whenever
the CAN bus detects a dominant state, as occurs with
a SOF.
17.3.1 CONFIGURATION MODE
The I/O pins will revert to normal I/O function when the
module is in the module Disable mode.
The CAN module has to be initialized before the activa-
tion. This is only possible if the module is in the Config-
uration mode. The Configuration mode is requested by
setting REQOP2 bit. Only when the status bit
OPMODE2 has a high level, the initialization can be
performed. Afterwards, the configuration registers and
the acceptance mask registers and the acceptance fil-
ter registers can be written. The module is activated by
setting the control bits CFGREQ to zero.
17.3.3 NORMAL MODE
This is the standard operating mode of the
PIC18CXX8. In this mode, the device actively monitors
all bus messages and generates acknowledge bits,
error frames, etc. This is also the only mode in which
the PIC18CXX8 will transmit messages over the CAN
bus.
The module will protect the user from accidentally vio-
lating the CAN protocol through programming errors.
All registers which control the configuration of the mod-
ule can not be modified while the module is on-line.
The CAN module will not be allowed to enter the Con-
figuration mode while a transmission is taking place.
The CONFIG bit serves as a lock to protect the follow-
ing registers.
17.3.4 LISTEN ONLY MODE
Listen Only mode provides
a means for the
PIC18CXX8 to receive all messages, including mes-
sages with errors. This mode can be used for bus mon-
itor applications, or for detecting the baud rate in ‘hot
plugging’ situations. For auto-baud detection, it is nec-
essary that there are at least two other nodes which are
communicating with each other. The baud rate can be
detected empirically by testing different values until
valid messages are received. The Listen Only mode is
a silent mode, meaning no messages will be transmit-
ted while in this state, including error flags or acknowl-
edge signals. The filters and masks can be used to
allow only particular messages to be loaded into the
receive registers, or the filter masks can be set to all
zeros to allow a message with any identifier to pass.
The error counters are reset and deactivated in this
state. The Listen Only mode is activated by setting the
mode request bits in the CANCON register.
• Configuration registers
• Bus Timing registers
• Identifier Acceptance Filter registers
• Identifier Acceptance Mask registers
In the Configuration mode, the module will not transmit
or receive. The error counters are cleared and the inter-
rupt flags remain unchanged. The programmer will
have access to configuration registers that are access
restricted in other modes.
DS30475A-page 210
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
17.3.5 LOOPBACK MODE
17.4.2 TRANSMIT PRIORITY
This mode will allow internal transmission of messages
from the transmit buffers to the receive buffers, without
actually transmitting messages on the CAN bus. This
mode can be used in system development and testing.
In this mode, the ACK bit is ignored and the device will
allow incoming messages from itself just as if they were
coming from another node. The Loopback mode is a
silent mode, meaning no messages will be transmitted
while in this state, including error flags or acknowledge
signals. The TXCAN pin will revert to port I/O while the
device is in this mode. The filters and masks can be
used to allow only particular messages to be loaded into
the receive registers. The masks can be set to all zeros
to provide a mode that accepts all messages. The Loop-
back mode is activated by setting the mode request bits
in the CANCON register.
Transmit priority is a prioritization, within the PIC18CXX8,
of the pending transmittable messages. This is indepen-
dent from, and not related to, any prioritization implicit in
the message arbitration scheme built into the CAN proto-
col. Prior to sending the SOF, the priority of all buffers that
are queued for transmission is compared. The transmit
buffer with the highest priority will be sent first. If two buff-
ers have the same priority setting, the buffer with the
highest buffer number will be sent first. There are four lev-
els of transmit priority. If TXP bits for a particular message
buffer are set to 11, that buffer has the highest possible
priority. If TXP bits for a particular message buffer are 00,
that buffer has the lowest possible priority.
17.4.3 INITIATING TRANSMISSION
To initiate message transmission, the TXREQ bit must be
set for each buffer to be transmitted.
17.3.6 ERROR RECOGNITION MODE
When TXREQ is set, the TXABT, TXLARB and TXERR
bits will be cleared.
The module can be set to ignore all errors and receive
any message. The Error Recognition mode is activated
by setting the RXM<1:0> bits in the RXBnCON regis-
ters to 11. In this mode, the data which is in the mes-
sage assembly buffer until the error time, is copied in
the receive buffer and can be read via the CPU inter-
face. In addition, the data which was on the internal
sampling of the CAN bus at the error time and the state
vector of the protocol state machine and the bit counter
CntCan, are stored in registers and can be read.
Setting the TXREQ bit does not initiate a message
transmission, it merely flags a message buffer as ready
for transmission. Transmission will start when the
device detects that the bus is available. The device will
then begin transmission of the highest priority message
that is ready.
When the transmission has completed successfully, the
TXREQ bit will be cleared, the TXBnIF bit will be set, and
an interrupt will be generated if the TXBnIE bit is set.
17.4
CAN Message Transmission
If the message transmission fails, the TXREQ will remain
set indicating that the message is still pending for trans-
mission and one of the following condition flags will be set.
If the message started to transmit but encountered an
error condition, the TXERR and the IRXIF bits will be set
and an interrupt will be generated. If the message lost
arbitration, the TXLARB bit will be set.
17.4.1 TRANSMIT BUFFERS
The PIC18CXX8 implements three Transmit Buffers.
Each of these buffers occupies 14 bytes of SRAM and
are mapped into the device memory maps.
For the MCU to have write access to the message buffer,
the TXREQ bit must be clear, indicating that the message
buffer is clear of any pending message to be transmitted.
17.4.4 ABORTING TRANSMISSION
At
a minimum, the TXBNSIDH, TXBNSIDL, and
The MCU can request to abort a message by clearing
the TXBnCON.TXREQ bit associated with the corre-
sponding message buffer. Setting CANCON.ABAT bit
will request an abort of all pending messages. If the
message has not yet started transmission, or if the
message started but is interrupted by loss of arbitration
or an error, the abort will be processed. The abort is
indicated when the module sets TXBnCON.ABTF bits.
If the message has started to transmit, it will attempt to
transmit the current message fully. If the current mes-
sage is transmitted fully and is not lost to arbitration or
an error, the ABTF bit will not be set, because the mes-
sage was transmitted successfully. Likewise, if a mes-
sage is being transmitted during an abort request and
the message is lost to arbitration or an error, the mes-
sage will not be re-transmitted and the ABTF bit will be
set, indicating that the message was successfully
aborted.
TXBNDLC registers must be loaded. If data bytes are
present in the message, the TXBNDm registers must also
be loaded. If the message is to use extended identifiers,
the TXBNEIDm registers must also be loaded and the
EXIDE bit set.
Prior to sending the message, the MCU must initialize
the TXINE bit to enable or disable the generation of an
interrupt when the message is sent. The MCU must
also initialize the TXP priority bits (see Section 17.4.2).
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 211
PIC18CXX8
FIGURE 17-2: TRANSMIT MESSAGE FLOWCHART
Start
The message transmission sequence begins when
the device determines that the TXREQ for any of the
transmit registers has been set.
Are any
TXREQ
bits = 1
?
No
Yes
Clearing the TXREQ bit while it is set, or setting
the ABAT bit before the message has started
transmission will abort the message.
Clear: TXABT, TXLARB,
and TXERR
Is
Is
No
No
TXREQ = 0
CAN bus available
to start transmission
?
ABAT = 1
?
Yes
Yes
Examine TXPRI <1:0> to
Determine Highest Priority Message
Begin transmission (SOF)
Was
No
Set
TXERR = 1
Message Transmitted
Successfully?
Yes
Set TXREQ = 0
Is
Yes
Yes
Arbitration lost during
transmission
TXLARB = 1?
Yes
Is
Generate
Interrupt
TXIE = 1?
No
A message can also be
aborted if message
a
error or lost arbitration
condition occurred during
transmission.
is
TXREQ = 0
or TXABT = 1
Set
TXBUFE = 1
?
The TXIE bit determines if an inter-
rupt should be generated when a
message is successfully transmitted.
No
Abort Transmission:
Set TXABT = 1
END
DS30475A-page 212
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
17.5.3 RECEIVE PRIORITY
17.5
Message Reception
RXB0 is the higher priority buffer and has two message
acceptance filters associated with it. RXB1 is the lower
priority buffer and has four acceptance filters associ-
ated with it. The lower number of acceptance filters
makes the match on RXB0 more restrictive and implies
a higher priority for that buffer. Additionally, the
RXB0CON register can be configured such that if
RXB0 contains a valid message, and another valid
message is received, an overflow error will not occur
and the new message will be moved into RXB1,
regardless of the acceptance criteria of RXB1. There
are also two programmable acceptance filter masks
available, one for each receive buffer (see Section 4.5).
17.5.1 RECEIVE MESSAGE BUFFERING
The PIC18CXX8 includes two full receive buffers with
multiple acceptance filters for each. There is also a
separate Message Assembly Buffer (MAB), which acts
as a third receive buffer (see Figure 17-3).
17.5.2 RECEIVE BUFFERS
Of the three receive buffers, the MAB is always commit-
ted to receiving the next message from the bus. The
remaining two receive buffers are called RXB0 and
RXB1 and can receive a complete message from the
protocol engine. The MCU can access one buffer while
the other buffer is available for message reception, or
holding a previously received message.
When a message is received, bits <3:0> of the RXBNCON
register will indicate the acceptance filter number that
enabled reception, and whether the received message is a
remote transfer request.
The MAB assembles all messages received. These
messages will be transferred to the RXBN buffers, only
if the acceptance filter criteria are met.
The RXM bits set special receive modes. Normally,
these bits are set to 00to enable reception of all valid
messages, as determined by the appropriate accep-
tance filters. In this case, the determination of whether
or not to receive standard or extended messages is
determined by the EXIDE bit in the acceptance filter
register. If the RXM bits are set to 01or 10, the receiver
will accept only messages with standard or extended
identifiers, respectively. If an acceptance filter has the
EXIDE bit set such that it does not correspond with the
RXM mode, that acceptance filter is rendered useless.
These two modes of RXM bits can be used in systems
where it is known that only standard or extended mes-
sages will be on the bus. If the RXM bits are set to 11,
the buffer will receive all messages, regardless of the
values of the acceptance filters. Also, if a message has
an error before the end of frame, that portion of the
message assembled in the MAB before the error
frame, will be loaded into the buffer. This mode has
some value in debugging a CAN system and would not
be used in an actual system environment.
Note: The entire contents of the MAB is moved into
the receive buffer once a message is
accepted. This means that regardless of the
type of identifier (standard or extended) and
the number of data bytes received, the entire
receive buffer is overwritten with the MAB
contents. Therefore, the contents of all regis-
ters in the buffer must be assumed to have
been modified when any message is
received.
When a message is moved into either of the receive
buffers, the appropriate RXBnIF bit is set. This bit must
be cleared by the MCU when it has completed process-
ing the message in the buffer, in order to allow a new
message to be received into the buffer. This bit pro-
vides a positive lockout to ensure that the MCU has fin-
ished with the message before the PIC18CXX8
attempts to load a new message into the receive buffer.
If the RXBnIE bit is set, an interrupt will be generated to
indicate that a valid message has been received.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 213
PIC18CXX8
FIGURE 17-3: RECEIVE BUFFER BLOCK DIAGRAM
Acceptance Mask
RXM1
Acceptance Filter
RXF2
Acceptance Mask
RXM0
Acceptance Filter
RXF3
A
c
c
e
p
t
Acceptance Filter
RXF0
Acceptance Filter
RXF4
A
c
c
Acceptance Filter
Acceptance Filter
RXF5
RXF1
e
p
t
R
X
B
0
M
A
B
R
X
B
1
Identifier
Identifier
Data Field
Data Field
DS30475A-page 214
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2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 17-4: MESSAGE RECEPTION FLOWCHART
Start
Detect
Start of
Message?
No
Yes
Begin Loading Message into
Message Assembly Buffer (MAB)
Valid
Generate
Error
Frame
No
Message
Received?
Yes
Yes, meets criteria
for RXB1
Yes, meets criteria
for RXBO
Message
Identifier meets
a filter criteria?
No
Go to Start
The RXRDY bit determines if the
receive register is empty and
able to accept a new message.
The RXB0DBEN bit determines
if RXB0 can roll over into RXB1
if it is full.
Is
Is
Yes
No
RX0DBEN = 1?
RXRDY = 0?
Yes
No
Is
No
Generate Overrun Error:
Set RXB1OVFL
Move message into RXB0
Set RXRDY = 1
Generate Overrun Error:
Set RXB0OVFL
RXRDY = 0?
Yes
Move message into RXB1
No
Is
Set FILHIT <0>
ERRIE = 1?
according to which filter criteria
was met
Set RXRDY = 1
Yes
Go to Start
Set FILHIT <2:0>
according to which filter criteria
was met
Is
Is
Yes
Generate
Interrupt
RXIE = 1?
RXIE = 1?
Yes
No
No
Set CANSTAT <3:0> according
to which receive buffer the
message was loaded into
2000 Microchip Technology Inc.
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DS30475A-page 215
PIC18CXX8
The coding of the RXB0DBEN bit enables these three
bits to be used similarly to the FILHIT bits and to distin-
guish a hit on filter RXF0 and RXF1, in either RXB0, or
after a roll over into RXB1.
17.6
Message Acceptance Filters and
Masks
The Message Acceptance Filters and Masks are used
to determine if a message in the message assembly
buffer should be loaded into either of the receive buff-
ers. Once a valid message has been received into the
MAB, the identifier fields of the message are compared
to the filter values. If there is a match, that message will
be loaded into the appropriate receive buffer. The filter
masks are used to determine which bits in the identifier
are examined with the filters. A truth table is shown
below in Table 17-2 that indicates how each bit in the
identifier is compared to the masks and filters to deter-
mine if a the message should be loaded into a receive
buffer. The mask essentially determines which bits to
apply the acceptance filters to. If any mask bit is set to
a zero, then that bit will automatically be accepted,
regardless of the filter bit.
• 111= Acceptance Filter 1 (RXF1)
• 110= Acceptance Filter 0 (RXF0)
• 001= Acceptance Filter 1 (RXF1)
• 000= Acceptance Filter 0
If the RXB0DBEN bit is clear, there are six codes cor-
responding to the six filters. If the RXB0DBEN bit is set,
there are six codes corresponding to the six filters, plus
two additional codes corresponding to RXF0 and RXF1
filters that roll over into RXB1.
If more than one acceptance filter matches, the FILHIT
bits will encode the binary value of the lowest num-
bered filter that matched. In other words, if filter RXF2
and filter RXF4 match, FILHIT will be loaded with the
value for RXF2. This essentially prioritizes the accep-
tance filters with a lower number filter having higher pri-
ority. Messages are compared to filters in ascending
order of filter number.
TABLE 17-2: FILTER/MASK TRUTH TABLE
Message
Identifier
bit n001
Accept or
Reject
bit n
Mask
bit n
Filter bit n
The mask and filter registers can only be modified
when the PIC18CXX8 is in Configuration mode. The
mask and filter registers cannot be read outside of Con-
figuration mode. When outside of Configuration mode,
all mask and filter registers will be read as ‘0’.
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Accept
Accept
Reject
Reject
Accept
Legend: X = don’t care
As shown in the Receive Buffers Block Diagram
(Figure 17-3), acceptance filters RXF0 and RXF1, and
filter mask RXM0 are associated with RXB0. Filters
RXF2, RXF3, RXF4, and RXF5 and mask RXM1 are
associated with RXB1. When a filter matches and a
message is loaded into the receive buffer, the filter
number that enabled the message reception is loaded
into the FILHIT bit(s). For RXB1, the RXB1CON regis-
ter contains the FILHIT<2:0> bits. They are coded as
follows:
• 101= Acceptance Filter 5 (RXF5)
• 100= Acceptance Filter 4 (RXF4)
• 011= Acceptance Filter 3 (RXF3)
• 010= Acceptance Filter 2 (RXF2)
• 001= Acceptance Filter 1 (RXF1)
• 000= Acceptance Filter 0 (RXF0)
Note: 000 and 001 can only occur if the
RXB0DBEN bit is set in the RXB0CON
register, allowing RXB0 messages to roll
over into RXB1.
DS30475A-page 216
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2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 17-5:
MESSAGE ACCEPTANCE MASK AND FILTER OPERATION
Acceptance Filter Register
Acceptance Mask Register
RXFn0
RXMn0
RXMn1
RxRqst
RXFn1
RXFnn
RXMnn
Message Assembly Buffer
Identifier
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DS30475A-page 217
PIC18CXX8
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different
clock frequencies of the individual devices, the bit rate
has to be adjusted by appropriately setting the baud
rate prescaler and number of time quanta in each seg-
ment.
17.7
Baud Rate Setting
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses
Non-Return-to-Zero (NRZ) coding, which does not
encode a clock within the data stream. Therefore, the
receive clock must be recovered by the receiving
nodes and synchronized to the transmitters clock.
The nominal bit rate is the number of bits transmitted
per second assuming an ideal transmitter with an ideal
oscillator, in the absence of resynchronization. The
nominal bit rate is defined to be a maximum of 1Mb/s.
As oscillators and transmission time may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data transmis-
sion edges, to synchronize and maintain the receiver
clock. Since the data is NRZ coded, it is necessary to
include bit stuffing to ensure that an edge occurs at
least every six bit times, to maintain the Digital Phase
Lock Loop (DPLL) synchronization.
Nominal Bit Time is defined as:
TBIT = 1 / NOMlNAL BlT RATE
The nominal bit time can be thought of as being divided
into separate non-overlapping time segments. These
segments are shown in Figure 17-6.
The bit timing of the PIC18CXX8 is implemented using
a DPLL that is configured to synchronize to the incom-
ing data, and provide the nominal timing for the trans-
mitted data. The DPLL breaks each bit time into
multiple segments, made up of minimal periods of time
called the time quanta (TQ).
• Synchronization Segment (Sync_Seg)
• Propagation Time Segment (Prop_Seg)
• Phase Buffer Segment 1 (Phase_Seg1)
• Phase Buffer Segment 2 [Phase_Seg2)
Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg +
Phase_Seg1 + Phase_Seg2)
Bus timing functions executed within the bit time frame,
such as synchronization to the local oscillator, network
transmission delay compensation, and sample point
positioning, are defined by the programmable bit timing
logic of the DPLL.
The time segments and also, the nominal bit time, are
made up of integer units of time called time quanta or
TQ (see Figure 17-6). By definition, the nominal bit time
is programmable from a minimum of 8 TQ to a maxi-
mum of 25 TQ. Also by definition, the minimum nominal
bit time is 1 µs, corresponding to a maximum 1 Mb/s
rate.
FIGURE 17-6: BIT TIME PARTITIONING
Input Signal
Prop
Sync
Phase
Segment 1
Phase
Segment 2
Segment
Sample Point
TQ
DS30475A-page 218
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PIC18CXX8
17.7.1 TIME QUANTA
17.7.4 PHASE BUFFER SEGMENTS
The Time Quanta is a fixed unit of time derived from the
oscillator period. There is a programmable baud rate
prescaler, with integral values ranging from 1 to 64, in
addition to a fixed divide by two for clock generation.
The Phase Buffer Segments are used to optimally locate
the sampling point of the received bit, within the nominal
bit time. The sampling point occurs between phase seg-
ment 1 and phase segment 2. These segments can be
lengthened or shortened by the resynchronization pro-
cess. The end of phase segment 1 determines the sam-
pling point within a bit time. Phase segment 1 is
programmable from 1 TQ to 8 TQ in duration. Phase seg-
ment 2 provides delay before the next transmitted data
transition and is also programmable from 1 TQ to 8 TQ in
duration (however, due to IPT requirements the actual
minimum length of phase segment 2 is 2 TQ, or it may be
defined to be equal to the greater of phase segment 1 or
the Information Processing Time (IPT) ).
EXAMPLE 17-2: CALCULATION FOR
FOSC = 16MHz
If Fosc = 16 MHz, BRP<5:0> = 00h, and Nominal Bit
Time = 8 TQ; then TQ = 125 nsec and Nominal Bit
Rate = 1 Mb/s
EXAMPLE 17-3: CALCULATION FOR
FOSC = 20MHz
17.7.5 SAMPLE POINT
If FOSC = 20 MHz, BRP<5:0> = 01h, and Nominal Bit
Time = 8 TQ; then TQ = 200nsec and Nominal Bit
Rate = 625 Kb/s
The Sample Point is the point of time at which the bus
level is read and value of the received bit is determined.
The sampling point occurs at the end of phase
segment 1. If the bit timing is slow and contains many
TQ, it is possible to specify multiple sampling of the bus
line at the sample point. The value of the received bit is
determined to be the value of the majority decision of
three values. The three samples are taken at the sam-
ple point, and twice before with a time of TQ/2 between
each sample.
EXAMPLE 17-4: CALCULATION FOR
FOSC = 25MHz
If Fosc = 25 MHz, BRP<5:0> = 3Fh, and Nominal Bit
Time = 25 TQ; then TQ = 5.12 usec and Nominal Bit
Rate = 7.8 Kb/s
The frequencies of the oscillators in the different nodes
must be coordinated in order to provide a system-wide
specified nominal bit time. This means that all oscilla-
tors must have a TOSC that is a integral divisor of TQ. It
should also be noted that although the number of TQ is
programmable from 4 to 25, the usable minimum is
8 TQ. A bit time of less than 8 TQ in length is not guar-
anteed to operate correctly.
17.7.6 INFORMATION PROCESSING TIME
The Information Processing Time (IPT) is the time seg-
ment, starting at the sample point, that is reserved for
calculation of the subsequent bit level. The CAN speci-
fication defines this time to be less than or equal to 2 TQ.
The PIC18CXX8 defines this time to be 2 TQ. Thus,
phase segment 2 must be at least 2 TQ long.
17.7.2 SYNCHRONIZATION SEGMENT
This part of the bit time is used to synchronize the var-
ious CAN nodes on the bus. The edge of the input sig-
nal is expected to occur during the sync segment. The
duration is 1 TQ.
17.7.3 PROPAGATION SEGMENT
This part of the bit time is used to compensate for phys-
ical delay times within the network. These delay times
consist of the signal propagation time on the bus line
and the internal delay time of the nodes. The length of
the Propagation Segment can be programmed from
1 TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits.
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DS30475A-page 219
PIC18CXX8
The phase error of an edge is given by the position of
the edge relative to Sync Seg, measured in TQ. The
phase error is defined in magnitude of TQ as follows:
17.8
Synchronization
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time (Sync
Seg). The circuit will then adjust the values of phase
segment 1 and phase segment 2, as necessary. There
are two mechanisms used for synchronization.
• e = 0 if the edge lies within SYNCESEG.
• e > 0 if the edge lies before the SAMPLE POINT.
• e < 0 if the edge lies after the SAMPLE POINT of
the previous bit.
If the magnitude of the phase error is less than, or equal
to, the programmed value of the synchronization jump
width, the effect of a resynchronization is the same as
that of a hard synchronization.
17.8.1 HARD SYNCHRONIZATION
If the magnitude of the phase error is larger than the
synchronization jump width, and if the phase error is
positive, then phase segment 1 is lengthened by an
amount equal to the synchronization jump width.
Hard Synchronization is only done when there is a
recessive to dominant edge during a BUS IDLE condi-
tion, indicating the start of a message. After hard syn-
chronization, the bit time counters are restarted with
Sync Seg. Hard synchronization forces the edge, which
has occurred to lie within the synchronization segment
of the restarted bit time. Due to the rules of synchroni-
zation, if a hard synchronization occurs, there will not
be a resynchronization within that bit time.
If the magnitude of the phase error is larger than the
resynchronization jump width, and if the phase error is
negative, then phase segment 2 is shortened by an
amount equal to the synchronization jump width.
17.8.3 SYNCHRONIZATION RULES
17.8.2 RESYNCHRONIZATION
• Only one synchronization within one bit time is
allowed.
As a result of Resynchronization, phase segment 1
may be lengthened, or phase segment 2 may be short-
ened. The amount of lengthening or shortening of the
phase buffer segments has an upper bound given by
the Synchronization Jump Width (SJW). The value of
the SJW will be added to phase segment 1 (see
Figure 17-7), or subtracted from phase segment 2 (see
Figure 17-8). The SJW is programmable between 1 TQ
and 4 TQ.
• An edge will be used for synchronization only if
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
• All other recessive to dominant edges, fulfilling
rules 1 and 2, will be used for resynchronization
with the exception that a node transmitting a dom-
inant bit will not perform a resynchronization, as a
result of a recessive to dominant edge with a pos-
itive phase error.
Clocking information will only be derived from reces-
sive to dominant transitions. The property that only a
fixed maximum number of successive bits have the
same value, ensures resynchronization to the bit
stream during a frame.
DS30475A-page 220
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2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 17-7: LENGTHENING A BIT PERIOD
Input Signal
Prop
Segment
Phase
Segment 1
Phase
Segment 2
Sync
≤ SJW
Actual Bit
Length
Nominal
Bit Length
Sample
Point
TQ
FIGURE 17-8:
SHORTENING A BIT PERIOD
Input Signal
Prop
Segment
Phase
Segment 1
Phase
Segment 2
Sync
≤ SJW
Sample
Point
Actual
Bit Length
Nominal
Bit Length
TQ
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DS30475A-page 221
PIC18CXX8
17.9
Programming Time Segments
17.11 Bit Timing Configuration Registers
Some requirements for programming of the time
segments:
The configuration registers (BRGCON1, BRGCON2,
BRGCON3) control the bit timing for the CAN bus inter-
face. These registers can only be modified when the
PIC18CXX8 is in Configuration mode.
• Prop Seg + Phase Seg 1 ≥ Phase Seg 2
• Phase Seg 2 ≥ Sync Jump Width
17.11.1 BRGCON1
For example, assuming that a 125 kHz CAN baud rate
with FOSC = 20 MHz is desired:
The BRP bits control the baud rate prescaler. The
SJW<1:0> bits select the synchronization jump width in
terms of number of TQ’s.
TOSC = 50nsec, choose BRP<5:0> = 04h, then
TQ = 500nsec. To obtain 125 kHz, the bit time must be
16 TQ.
17.11.2 BRGCON2
Sync Seg = 1 TQ; Prop Seg = 2 TQ; So, setting Phase
Seg 1 = 7 TQ would place the sample at 10 TQ after the
transition. This would leave 6 TQ for Phase Seg 2.
The PRSEG bits set the length, in TQ’s, of the propaga-
tion segment. The SEG1PH bits set the length, in TQ’s,
of phase segment 1. The SAM bit controls how many
times the RXCAN pin is sampled. Setting this bit to a ‘1’
causes the bus to be sampled three times; twice at
TQ/2 before the sample point, and once at the normal
sample point (which is at the end of phase segment 1).
The value of the bus is determined to be the value read
during at least two of the samples. If the SAM bit is set
to a ‘0’, then the RXCAN pin is sampled only once at
the sample point. The SEG2PHTS bit controls how the
length of phase segment 2 is determined. If this bit is
set to a ‘1’, then the length of phase segment 2 is deter-
mined by the SEG2PH bits of BRGCON3. If the
SEG2PHTS bit is set to a ‘0’, then the length of phase
segment 2 is the greater of phase segment 1 and the
information processing time (which is fixed at 2 TQ for
the PIC18CXX8).
Since Phase Seg 2 is 6, by the rules, SJW could be the
maximum of 4 TQ. However, normally a large SJW is
only necessary when the clock generation of the differ-
ent nodes is inaccurate or unstable, such as using
ceramic resonators. So an SJW of 1 is typically
enough.
17.10 Oscillator Tolerance
The bit timing requirements allow ceramic resonators
to be used in applications with transmission rates of up
to 125 kbit/sec, as a rule of thumb. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. A maximum node-to-node oscillator variation
of 1.7% is allowed.
17.11.3 BRGCON3
The PHSEG2<2:0> bits set the length, in TQ’s, of
phase segment 2, if the SEG2PHTS bit is set to a ‘1’. If
the SEG2PHTS bit is set to
PHSEG2<2:0> bits have no effect.
a ‘0’, then the
DS30475A-page 222
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PIC18CXX8
17.12.6 ERROR STATES
17.12 Error Detection
Detected errors are made public to all other nodes via
error frames. The transmission of the erroneous mes-
sage is aborted and the frame is repeated as soon as
possible. Furthermore, each CAN node is in one of the
three error states “error-active”, “error-passive” or
“bus-off” according to the value of the internal error
counters. The error-active state is the usual state,
where the bus node can transmit messages and active
error frames (made of dominant bits), without any
restrictions. In the error-passive state, messages and
passive error frames (made of recessive bits) may be
transmitted. The bus-off state makes it temporarily
impossible for the station to participate in the bus com-
munication. During this state, messages can neither be
received nor transmitted.
The CAN protocol provides sophisticated error detec-
tion mechanisms. The following errors can be detected.
17.12.1 CRC ERROR
With the Cyclic Redundancy Check (CRC), the trans-
mitter calculates special check bits for the bit
sequence, from the start of a frame until the end of the
data field. This CRC sequence is transmitted in the
CRC Field. The receiving node also calculates the
CRC sequence using the same formula and performs
a comparison to the received sequence. If a mismatch
is detected, a CRC error has occurred and an error
frame is generated. The message is repeated.
17.12.2 ACKNOWLEDGE ERROR
17.12.7 ERROR MODES AND ERROR COUNTERS
In the acknowledge field of a message, the transmitter
checks if the acknowledge slot (which has sent out as
a recessive bit) contains a dominant bit. If not, no other
node has received the frame correctly. An acknowl-
edge error has occurred; an error frame is generated
and the message will have to be repeated.
The PIC18CXX8 contains two error counters: the
Receive Error Counter (RXERRCNT), and the Trans-
mit Error Counter (TXERRCNT). The values of both
counters can be read by the MCU. These counters are
incremented or decremented in accordance with the
CAN bus specification.
17.12.3 FORM ERROR
The PIC18CXX8 is error-active if both error counters
are below the error-passive limit of 128. It is
error-passive if at least one of the error counters equals
or exceeds 128. It goes to bus-off if the transmit error
counter equals or exceeds the bus-off limit of 256. The
device remains in this state, until the bus-off recovery
sequence is received. The bus-off recovery sequence
consists of 128 occurrences of 11 consecutive reces-
sive bits (see Figure 17-9). Note that the CAN module,
after going bus-off, will recover back to error-active,
without any intervention by the MCU, if the bus remains
idle for 128 X 11 bit times. If this is not desired, the error
interrupt service routine should address this. The cur-
rent error mode of the CAN module can be read by the
MCU via the COMSTAT register.
lf a node detects a dominant bit in one of the four seg-
ments, including end of frame, interframe space,
acknowledge delimiter, or CRC delimiter, then a form
error has occurred and an error frame is generated.
The message is repeated.
17.12.4 BIT ERROR
A Bit Error occurs if a transmitter sends a dominant bit
and detects a recessive bit, or if it sends a recessive bit
and detects a dominant bit, when monitoring the actual
bus level and comparing it to the just transmitted bit. In
the case where the transmitter sends a recessive bit
and a dominant bit is detected during the arbitration
field and the acknowledge slot, no bit error is generated
because normal arbitration is occurring.
Additionally, there is an error state warning flag bit,
EWARN, which is set if at least one of the error
counters equals or exceeds the error warning limit of
96. EWARN is reset if both error counters are less than
the error warning limit.
17.12.5 STUFF BIT ERROR
lf, between the start of frame and the CRC delimiter, six
consecutive bits with the same polarity are detected,
the bit stuffing rule has been violated. A Stuff Bit Error
occurs and an error frame is generated. The message
is repeated.
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PIC18CXX8
FIGURE 17-9: ERROR MODES STATE DIAGRAM
RESET
Error
RXERRCNT < 127 or
TXERRCNT < 127
Active
128 occurrences of
11 consecutive
"recessive" bits
RXERRCNT > 127 or
TXERRCNT > 127
Error
Passive
TXERRCNT > 255
Bus
Off
DS30475A-page 224
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PIC18CXX8
17.13.2 TRANSMIT INTERRUPT
17.13 CAN Interrupts
When the Transmit Interrupt is enabled, an interrupt will
be generated when the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. The TXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU resetting the TXBnIF bit to a ‘0’.
The module has several sources of interrupts. Each of
these interrupts can be individually enabled or dis-
abled. The CANINTF register contains interrupt flags.
The CANINTE register contains the enables for the 8
main interrupts. A special set of read only bits in the
CANSTAT register (ICODE bits) can be used in combi-
nation with a jump table for efficient handling of inter-
rupts.
17.13.3 RECEIVE INTERRUPT
All interrupts have one source, with the exception of the
Error Interrupt. Any of the Error Interrupt sources can
set the Error Interrupt Flag. The source of the Error
Interrupt can be determined by reading the Communi-
cation Status register COMSTAT.
When the Receive Interrupt is enabled, an interrupt will
be generated when a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving the
EOF field. The RXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU resetting the RXBnIF bit to a ‘0’.
The interrupts can be broken up into two categories:
receive and transmit interrupts.
The receive related interrupts are:
17.13.4 MESSAGE ERROR INTERRUPT
• Receive Interrupts
When an error occurs during transmission or reception
of a message, the message error flag IRXIF will be set
and, if the IRXIE bit is set, an interrupt will be gener-
ated. This is intended to be used to facilitate baud rate
determination when used in conjunction with Listen
Only mode.
• Wake-up Interrupt
• Receiver Overrun Interrupt
• Receiver Warning Interrupt
• Receiver Error Passive Interrupt
The Transmit related interrupts are
17.13.5 BUS ACTIVITY WAKE-UP INTERRUPT
• Transmit Interrupts
• Transmitter Warning Interrupt
• Transmitter Error Passive Interrupt
• Bus Off Interrupt
When the PIC18CXX8 is in SLEEP mode and the bus
activity wake-up interrupt is enabled, an interrupt will be
generated, and the WAKIF bit will be set, when activity
is detected on the CAN bus. This interrupt causes the
PIC18CXX8 to exit SLEEP mode. The interrupt is reset
by the MCU clearing the WAKIF bit.
17.13.1 INTERRUPT CODE BITS
The source of a pending interrupt is indicated in the
ICODE (interrupt code) bits. Interrupts are internally
prioritized, such that the lower the ICODE value, the
higher the interrupt priority. Once the highest priority
interrupt condition has been cleared, the code for the
next highest priority interrupt that is pending (if any),
will be reflected by the ICODE bits (see Table 17-3).
Note that only those interrupt sources that have their
associated CANINTE enable bit set will be reflected in
the ICODE bits.
TABLE 17-3: ICODE<2:0> DECODE
ICODE<2:0>
Boolean Expression
000
001
010
011
100
101
110
111
ERR•WAK•TX0•TX1•TX2•RX0•RX1
ERR
ERR•WAK
ERR•WAK•TX0
ERR•WAK•TX0•TX1
ERR•WAK•TX0•TX1•TX2
ERR•WAK•TX0•TX1•TX2•RX0
ERR•WAK•TX0•TX1•TX2•RX0•RX1
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PIC18CXX8
17.13.6 ERROR INTERRUPT
17.13.6.4 Receiver Bus-Passive
When the error interrupt is enabled, an interrupt is gen-
erated if an overflow condition occurs, or if the error
state of transmitter or receiver has changed. The Error
Flags in COMSTAT will indicate one of the following
conditions.
The receive error counter has exceeded the
error-passive limit of 127 and the device has gone to
error-passive state.
17.13.6.5 Transmitter Bus-Passive
The transmit error counter has exceeded the error-
passive limit of 127 and the device has gone to error-
passive state.
17.13.6.1 Receiver Overflow
An overflow condition occurs when the MAB has assem-
bled a valid received message (the message meets the
criteria of the acceptance filters) and the receive buffer
associated with the filter is not available for loading of a
new message. The associated COMSTAT.RXNOVFL bit
will be set to indicate the overflow condition. This bit
must be cleared by the MCU.
17.13.6.6 Bus-Off
The transmit error counter has exceeded 255 and the
device has gone to bus-off state.
17.13.7 INTERRUPT ACKNOWLEDGE
17.13.6.2 Receiver Warning
Interrupts are directly associated with one or more sta-
tus flags in the PIF register. Interrupts are pending as
long as one of the flags is set. Once an interrupt flag is
set by the device, the flag can not be reset by the MCU
until the interrupt condition is removed.
The receive error counter has reached the MCU warn-
ing limit of 96.
17.13.6.3 Transmitter Warning
The transmit error counter has reached the MCU warn-
ing limit of 96.
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PIC18CXX8
The A/D module has five registers:
18.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The analog-to-digital (A/D) converter module has
twelve inputs for the PIC18C658 devices and sixteen
for the PIC18C858 devices. This module has the
ADCON0, ADCON1, and ADCON2 registers.
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
The A/D allows conversion of an analog input signal to
a corresponding 10-bit digital number.
The ADCON0 register, shown in Register 18-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 18-2, configures the func-
tions of the port pins. The ADCON2, shown in Register
16-3, configures the A/D clock source and justification.
REGISTER 18-1: ADCON0 REGISTER
U-0
—
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
GO/DONE ADON
bit 0
R/W-0
bit 7
bit 7-6
bit 5-2
Unimplemented: Read as '0'
CHS3:CHS0: Analog Channel Select bits
0000= channel 00, (AN0)
0001= channel 01, (AN1)
0010= channel 02, (AN2)
0011= channel 03, (AN3)
0100= channel 04, (AN4)
0101= channel 05, (AN5)
0110= channel 06, (AN6)
0111= channel 07, (AN7)
1000= channel 08, (AN8)
1001= channel 09, (AN9)
1010= channel 10, (AN10)
1011= channel 11, (AN11)
1100= channel 12, (AN12)(1)
1101= channel 13, (AN13)(1)
1110= channel 14, (AN14)(1)
1111= channel 15, (AN15)(1)
Note 1: These channels are not available on the PIC18C658 devices.
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1
1= A/D conversion in progress. Setting this bit starts an A/D conversion cycle. This bit is auto-
matically cleared by hardware when the A/D conversion is complete.
0= A/D conversion not in progress
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shut off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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PIC18CXX8
REGISTER 18-2: ADCON1 REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7-6 Unimplemented: Read as '0'
bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits
A/D VREF+
A/D VREF-
00
01
10
11
AVDD
AVSS
External VREF+
AVDD
AVSS
External VREF-
External VREF-
External VREF+
bit 3:0 PCFG3:PCFG0: A/D Port Configuration Control bits
AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
Shaded cells = additional A/D channels available on the PIC18C858 devices.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
Note: Channels AN15 through AN12 are not available on the 68-pin devices.
DS30475A-page 228
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2000 Microchip Technology Inc.
PIC18CXX8
REGISTER 18-3: ADCON2 REGISTER
R/W-0
ADFM
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
ADCS0
bit 0
ADCS2
ADCS1
bit 7
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6-3
bit 2-0
Unimplemented: Read as '0'
ADCS1:ADCS0: A/D Conversion Clock Select bits
000= FOSC/2
001= FOSC/8
010= FOSC/32
011= FRC (clock derived from an RC oscillator = 1 MHz max)
100= FOSC/4
101= FOSC/16
110= FOSC/64
111= FRC (clock derived from an RC oscillator = 1 MHz max)
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2000 Microchip Technology Inc.
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DS30475A-page 229
PIC18CXX8
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the
RA3/AN3/VREF+ pin and RA2/AN2/VREF-.
Each port pin associated with the A/D converter can
be configured as an analog input (RA3 can also be a
voltage reference), or as a digital I/O.
The ADRESH and ADRESL registers contain the result
of the A/D conversion. When the A/D conversion is
The A/D converter has a unique feature of being able to
operate while the device is in SLEEP mode. To operate
in SLEEP, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
complete,
the
result
is
loaded
into
the
ADRESH/ADRESL registers, the GO/DONE bit
(ADCON0 register) is cleared, and A/D interrupt flag bit
ADIF is set. The block diagram of the A/D module is
shown in Figure 18-1.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off and
any conversion is aborted.
FIGURE 18-1: A/D BLOCK DIAGRAM
CHS3:CHS0
1111
AN15 (1)
1110
AN14 (1)
1101
AN13 (1)
1100
AN12 (1)
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
0100
AN4
VAIN
0011
AN3
(Input Voltage)
10-bit
Converter
A/D
0010
AN2
0001
AN1
VCFG1:VCFG0
0000
AN0
VDD
VREF+
VREF-
Reference
Voltage
VSS
Note 1: Channels AN15 through AN12 are not available on the PIC18C658.
2: I/O pins have diode protection to VDD and VSS.
DS30475A-page 230
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PIC18CXX8
The value in the ADRESH/ADRESL registers is not
modified for a Power-on Reset. The ADRESH/ADRESL
registers will contain unknown data after a Power-on
Reset.
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 18.1.
After this acquisition time has elapsed, the A/D conver-
sion can be started. The following steps should be fol-
lowed to do an A/D conversion:
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
1. Configure the A/D module:
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
FIGURE 18-2: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6 V
ANx
Rs
SS
RIC ≤ 1 k
RSS
CPIN
VAIN
I leakage
± 500 nA
CHOLD = 120 pF
VT = 0.6 V
5 pF
VSS
Legend: CPIN
VT
= input capacitance
= threshold voltage
6V
5V
VDD 4V
3V
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
= sampling switch
2V
SS
CHOLD
RSS
= sample/hold capacitance (from DAC)
= sampling switch resistance
5
6
7
8 9 10 11
Sampling Switch ( kΩ )
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PIC18CXX8
To calculate the minimum acquisition time,
Equation 18-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
18.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 18-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5kΩ. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
Example 18-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system assump-
tions:
CHOLD
Rs
Conversion Error
VDD
Temperature
VHOLD
=
=
≤
=
=
=
120 pF
2.5 kΩ
1/2 LSb
5V → Rss = 7 kΩ
50°C (system max.)
0V @ time = 0
Note: When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
EQUATION 18-1: ACQUISITION TIME
TACQ
=
Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 18-2: A/D MINIMUM CHARGING TIME
VHOLD
or
=
(VREF - (VREF/2048)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS))
)
Tc
=
-(120 pF)(1 kΩ + RSS + RS) ln(1/2047)
EXAMPLE 18-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ =
TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25°C.
TACQ =
TC =
2 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)]
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885)
-120 pF (10.5 kΩ) ln(0.0004885)
-1.26 µs (-7.6241)
9.61 µs
TACQ =
2 µs + 9.61 µs + [(50°C - 25°C)(0.05 µs/°C)]
11.61 µs + 1.25 µs
12.86 µs
DS30475A-page 232
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PIC18CXX8
18.2
Selecting the A/D Conversion Clock
18.3
Configuring Analog Port Pins
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 12 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
• 2TOSC
• 4TOSC
• 8TOSC
• 16TOSC
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
• 32TOSC
• 64TOSC
• Internal RC oscillator
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
Table 18-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
2: Analog levels on any pin defined as a dig-
ital input may cause the input buffer to
consume current out of the device’s spec-
ification limits.
TABLE 18-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
ADCS2:ADCS0
Maximum Device Frequency
PIC18CXX8
PIC18LCXX8(6)
Operation
2TOSC
4TOSC
8TOSC
16TOSC
32TOSC
64TOSC
RC
000
100
001
101
010
110
x11
1.25 MHz
2.50 MHz
5.00 MHz
10.0 MHz
20.0 MHz
40.0 MHz
—
666 kHz
1.33 MHz
2.67 MHz
5.33 MHz
10.67 MHz
21.33 MHz
—
Note 1: The RC source has a typical TAD time of 4 ms.
2: The RC source has a typical TAD time of 6 ms.
3: These values violate the minimum required TAD time.
4: For faster conversion times, the selection of another clock source is recommended.
5: For device frequencies above 1 MHz, the device must be in SLEEP for the entire conversion or the A/D
accuracy may be out of specification.
6: This column is for the LC devices only.
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PIC18CXX8
18.4
A/D Conversions
18.5
Use of the CCP2 Trigger
Figure 18-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL reg-
isters). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, acquisition on the selected channel is
automatically started.
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as 1011and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a conver-
sion).
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D mod-
ule, but will still reset the Timer1 (or Timer3) counter.
FIGURE 18-3: A/D CONVERSION TAD CYCLES
Tcy - TAD
TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7
b4
b3
b2
b1
b0
b0
b7
b6
b5
b8
b9
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
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2000 Microchip Technology Inc.
PIC18CXX8
TABLE 18-2: SUMMARY OF A/D REGISTERS
Value on all
Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
POR, BOR
RESETS
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
PIR1
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
—
SSPIF CCP1IF
SSPIE CCP1IE
SSPIP CCP1IP
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TMR1IF 0000 0000
TMR1IE 0000 0000
TMR1IP 0000 0000
CCP2IF -0-- 0000
CCP2IE -0-- 0000
CCP2IP -0-- 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
-0-- 0000
-0-- 0000
-0-- 0000
uuuu uuuu
uuuu uuuu
0000 00-0
---- -000
0--- -000
--0u 0000
--11 1111
u000 0000
uuuu uuuu
1111 1111
0000 xxxx
uuuu uuuu
1111 1111
PIE1
IPR1
PIR2
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
PIE2
—
—
—
IPR2
—
—
—
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTF
LATF
A/D Result Register
A/D Result Register
xxxx xxxx
—
—
—
—
CHS3
CHS3
CHS1
CHS0
GO/DONE
PCFG1
ADCS1
RA1
ADON
PCFG0
ADCS0
RA0
0000 00-0
---- -000
0--- -000
--0x 0000
--11 1111
x000 0000
xxxx xxxx
1111 1111
0000 xxxx
xxxx xxxx
1111 1111
VCFG1 VCFG0 PCFG3 PCFG2
ADFM
—
—
—
—
—
ADCS2
RA2
RA6
RA5
RA4
RA3
—
PORTA Data Direction Register
RF7
LATF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
TRISF
PORTF Data Direction Control Register
(1)
PORTH
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
(1)
LATH
LATH7
LATH6
LATH5
LATH4 LATH3
LATH2
LATH1
LATH0
(1)
TRISH
PORTH Data Direction Control Register
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Only available on PIC18C858 devices.
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DS30475A-page 235
PIC18CXX8
NOTES:
DS30475A-page 236
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2000 Microchip Technology Inc.
PIC18CXX8
The CMCON register, shown as Register 19-1, con-
trols the comparator input and output multiplexers. A
block diagram of the comparator is shown in
Figure 19-1.
19.0 COMPARATOR MODULE
The comparator module contains two analog compara-
tors. The inputs to the comparators are multiplexed
with the RF1 through RF6 pins. The on-chip Voltage
Reference (Section 20.0) can also be an input to the
comparators.
REGISTER 19-1: CMCON REGISTER
R-0
R-0
R/W-0
C2INV
R/W-0
C1INV
R/W-0
CIS
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
C2OUT
C1OUT
bit 7
bit 0
bit 7
C2OUT: Comparator 2 Output
When C2INV = 0:
1= C2 VIN+ > C2 VIN–
0= C2 VIN+ < C2 VIN–
When C2INV = 1:
1= C2 VIN+ < C2 VIN–
0= C2 VIN+ > C2 VIN–
bit 6
C1OUT: Comparator 1 Output
When C1INV = 0:
1= C1 VIN+ > C1 VIN–
0= C1 VIN+ < C1 VIN–
When C1INV = 1:
1= C1 VIN+ < C1 VIN–
0= C1 VIN+ > C1 VIN–
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion
1= C2 output inverted
0= C2 output not inverted
C1INV: Comparator 1 Output Inversion
1= C1 Output inverted
0= C1 Output not inverted
CIS: Comparator Input Switch
When CM2:CM0 = 110:
1= C1 VIN– connects to RF5/AN10
C2 VIN– connects to RF3/AN8
0= C1 VIN– connects to RF6/AN11
C2 VIN– connects to RF4/AN9
bit 2-0 CM2:CM0: Comparator Mode
Figure 19-1 shows the Comparator modes and CM2:CM0 bit settings
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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DS30475A-page 237
PIC18CXX8
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Electrical Specifications (Section 25.0).
19.1
Comparator Configuration
There are eight modes of operation for the compara-
tors. The CMCON register is used to select these
modes. Figure 19-1 shows the eight possible modes.
The TRISF register controls the data direction of the
comparator pins for each mode. If the Comparator
Note: Comparator interrupts should be disabled
during a Comparator mode change. Other-
wise, a false interrupt may occur.
FIGURE 19-1: COMPARATOR I/O OPERATING MODES
Comparators Reset (POR Default Value)
Comparators Off
CM2:CM0 = 000
CM2:CM0 = 111
A
D
VIN-
VIN-
RF6/AN11
RF5/AN10
RF6/AN11
Off (Read as ’0’)
Off (Read as ’0’)
Off (Read as ’0’)
Off (Read as ’0’)
C1
C2
C1
C2
VIN+
VIN+
A
D
RF5/AN10
A
A
D
VIN-
VIN-
RF4/AN9
RF3/AN8
RF4/AN9
VIN+
VIN+
D
RF3/AN8
Two Independent Comparators with Outputs
CM2:CM0 = 011
Two Independent Comparators
CM2:CM0 = 010
A
VIN-
A
VIN-
RF6/AN11
RF5/AN10
RF6/AN11
RF5/AN10
C1OUT
C2OUT
C1
C2
VIN+
A
C1OUT
C2OUT
C1
C2
VIN+
A
RF2/AN7/C1OUT
A
A
VIN-
A
VIN-
RF4/AN9
RF3/AN8
RF4/AN9
VIN+
VIN+
A
RF3/AN8
RF1/AN6/C2OUT
Two Common Reference Comparators
Two Common Reference Comparators with Outputs
CM2:CM0 = 100
CM2:CM0 = 101
A
A
VIN-
VIN-
RF6/AN11
RF5/AN10
RF6/AN11
RF5/AN10
C1OUT
C2OUT
C1OUT
C1
C2
C1
C2
VIN+
VIN+
A
A
RF2/AN7/C1OUT
A
D
VIN-
RF4/AN9
RF3/AN8
A
VIN-
VIN+
RF4/AN9
C2OUT
VIN+
D
RF3/AN8
RF1/AN6/C2OUT
Four Inputs Multiplexed to Two Comparators
One Independent Comparator with Output
CM2:CM0 = 110
CM2:CM0 = 001
A
A
A
VIN-
RF6/AN11
RF6/AN11
RF5/AN10
CIS = 0
CIS = 1
VIN-
A
C1OUT
C1
C2
VIN+
RF5/AN10
C1OUT
C2OUT
C1
C2
VIN+
RF2/AN7/C1OUT
A
A
RF4/AN9
RF3/AN8
VIN-
CIS = 0
CIS = 1
VIN+
D
VIN-
RF4/AN9
Off (Read as ’0’)
VIN+
D
RF3/AN8
CVREF
From VREF Module
A = Analog Input, port reads zeros always.
D = Digital Input.
CIS (CMCON<3>) is the Comparator Input Switch.
DS30475A-page 238
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
19.2
Comparator Operation
19.4
Comparator Response Time
A single comparator is shown in Figure 19-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN–, the output of the
comparator is a digital low level. When the analog input
at VIN+ is greater than the analog input VIN–, the output
of the comparator is a digital high level. The shaded
areas of the output of the comparator in Figure 19-2
represent the uncertainty due to input offsets and
response time.
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise the maximum delay of
the comparators should be used (Section 25.0).
19.5
Comparator Outputs
The comparator outputs are read through the CMCON
Register. These bits are read-only. The comparator
outputs may also be directly output to the RF1 and RF2
I/O pins. When enabled, multiplexors in the output path
of the RF1 and RF2 pins will switch and the output of
each pin will be the unsynchronized output of the com-
parator. The uncertainty of each of the comparators is
related to the input offset voltage and the response
time given in the specifications. Figure 19-3 shows the
comparator output block diagram.
19.3
Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal present at VIN– is compared to the signal
at VIN+, and the digital output of the comparator is
adjusted accordingly (Figure 19-2).
FIGURE 19-2: SINGLE COMPARATOR
The TRISA bits will still function as an output
enable/disable for the RF1 and RF2 pins while in this
mode.
VIN+
+
–
Output
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<4:5>).
VIN–
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input, according to the
Schmitt Trigger input specification.
VIN–
2: Analog levels on any pin defined as a dig-
ital input, may cause the input buffer to
consume more current than is specified.
VIN+
Output
19.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same, or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD, and can be applied to either
pin of the comparator(s).
19.3.2
INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 20.0 contains a detailed descrip-
tion of the Comparator Voltage Reference Module that
provides this signal. The internal reference signal is
used when comparators are in mode CM<2:0> = 110
(Figure 19-1). In this mode, the internal voltage refer-
ence is applied to the VIN+ pin of both comparators.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 239
PIC18CXX8
FIGURE 19-3: COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
+
-
CxINV
To RF1 or
RF2 Pin
Bus
Data
Q
D
Read CMCON
EN
Q
Set
CMIF
bit
D
From
Other
Comparator
EN
CL
Read CMCON
RESET
DS30475A-page 240
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2000 Microchip Technology Inc.
PIC18CXX8
19.6
Comparator Interrupts
19.7
Comparator Operation During SLEEP
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR registers) is the comparator interrupt flag. The
CMIF bit must be RESET by clearing ‘0’. Since it is also
possible to write a '1' to this register, a simulated inter-
rupt may be initiated.
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
wake-up the device from SLEEP mode, when enabled.
While the comparator is powered up, higher SLEEP
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current, as shown in the com-
parator specifications. To minimize power consumption
while in SLEEP mode, turn off the comparators,
CM<2:0> = 111, before entering SLEEP. If the device
wakes up from SLEEP, the contents of the CMCON
register are not affected.
The CMIE bit (PIE registers) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
19.8
Effects of a RESET
.
A device RESET forces the CMCON register to its
RESET state, causing the comparator module to be in
the comparator RESET mode, CM<2:0> = 000. This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at RESET time. The comparators will be
powered down during the RESET interval.
Note: If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR regis-
ters) interrupt flag may not get set.
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the mis-
match condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
2000 Microchip Technology Inc.
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DS30475A-page 241
PIC18CXX8
19.9
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 19-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6 V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is rec-
ommended for the analog sources. Any external com-
ponent connected to an analog input pin, such as a
capacitor or a Zener diode, should have very little leak-
age current.
FIGURE 19-4: ANALOG INPUT MODEL
VDD
VT = 0.6 V
RIC
RS < 10k
AIN
ILEAKAGE
500 nA
CPIN
5 pF
VA
VT = 0.6 V
VSS
Legend:
CPIN
VT
ILEAKAGE
RIC
RS
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the pin due to various junctions
Interconnect Resistance
Source Impedance
Analog Voltage
VA
TABLE 19-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
All Other
RESETS
Value on
POR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMCON C2OUT C1OUT C2INV C1INV
CIS
CM2
VR2
CM1
VR1
CM0
VR0
0000 0000 0000 0000
0000 0000 0000 0000
VRCON
VREN
VROE
VRR
VRSS
VR3
GIE/
GIEH
PEIE/
GIEL
INTCON
TMR0IE INTIE
RBIE TMR0IF INTIF
RBIF
0000 000x 0000 000u
PIR2
—
—
CMIF
CMIE
CMIP
RF6
—
—
—
—
BCLIF LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000
BCLIE LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000
BCLIP LVDIP TMR3IP CCP2IP -1-- 1111 -1-- 1111
PIE2
IPR2
—
—
—
PORTF
LATF
TRISF
RF7
LATF7
RF5
RF4
RF3
RF2
RF1
RF0
x000 0000 u000 0000
LATF6 LATF5 LATF4 LATF3 LATF2
LATF1
LATF0 xxxx xxxx uuuu uuuu
PORTF Data Direction Register
1111 1111 1111 1111
Legend: x= unknown, u= unchanged, - = unimplemented, read as "0"
DS30475A-page 242
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2000 Microchip Technology Inc.
PIC18CXX8
20.1
Configuring the Comparator Voltage
Reference
20.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The Comparator Voltage Reference is a 16-tap resistor
ladder network that provides a selectable voltage refer-
ence. The resistor ladder is segmented to provide two
ranges of CVREF values and has a power-down func-
tion to conserve power when the reference is not being
used. The CVRCON register controls the operation of
the reference as shown in Register 20-1. The block dia-
gram is given in Figure 20-1.
The Comparator Voltage Reference can output 16 dis-
tinct voltage levels for each range. The equations used
to calculate the output of the Comparator Voltage Ref-
erence are as follows:
If CVRR = 1:
CVREF= (CVR<3:0>/24) x CVRSRC
If CVRR = 0:
CVREF = (CVDD x 1/4) + (CVR<3:0>/32) x CVRSRC
The comparator reference supply voltage can come
from either VDD or VSS, or the external VREF+ and
VREF- that are multiplexed with RA3 and RA2. The
comparator reference supply voltage is controlled by
the CVRSS bit.
The settling time of the Comparator Voltage Reference
must be considered when changing the CVREF output
(Section 25.0).
REGISTER 20-1: VRCON REGISTER
R/W-0
VREN
R/W-0
VROE
R/W-0
VRR
R/W-0
VRSS
R/W-0
VR3
R/W-0
VR2
R/W-0
VR1
R/W-0
VR0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
VREN: Comparator Voltage Reference Enable
1= CVREF circuit powered on
0= CVREF circuit powered down
VROE: Comparator VREF Output Enable
1= CVREF voltage level is also output on the RF5/AN10/CVREF pin
0= CVREF voltage is disconnected from the RF5/AN10/CVREF pin
VRR: Comparator VREF Range Selection
1= 0.00 CVRSRC to 0.75 CVRSRC, with CVRSRC/24 step size
0= 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
VRSS: Comparator VREF Source Selection
1= Comparator reference source CVRSRC = VREF+-VREF-
0= Comparator reference source CVRSRC = VDD-VSS
bit 3-0 VR3:VR0: Comparator VREF Value Selection 0 ≤ VR3:VR0 ≤ 15
When VRR = 1:
CVREF = (VR<3:0>/ 24) • (CVRSRC)
When VRR = 0:
CVREF = 1/4 • (CVRSRC) + (VR3:VR0/ 32) • (CVRSRC)
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2000 Microchip Technology Inc.
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DS30475A-page 243
PIC18CXX8
FIGURE 20-1: VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
VREF+
16 Stages
CVRSS=1
CVRSS=0
CVREN
R
R
R
R
8R
CVRR
VRSS=0
8R
VRSS=1
VREF-
(From VRCON<3:0>)
CVR3
CVR0
CVREF
16-1 Analog Mux
Note: R is defined in Section 25.0.
DS30475A-page 244
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2000 Microchip Technology Inc.
PIC18CXX8
20.2
Voltage Reference Accuracy/Error
20.5
Connection Considerations
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 20-1) keep VREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the VREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 25.0.
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
TRISF<5> bit is set and the VROE bit (VRCON regis-
ter) is set. Enabling the voltage reference output onto
the RF5 pin, with an input signal present, will increase
current consumption. Connecting RF5 as a digital
output with VRSS enabled will also increase current
consumption.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage refer-
ence output for external connections to VREF.
Figure 20-2 shows an example buffering technique.
20.3
Operation During SLEEP
When the device wakes up from SLEEP through an
interrupt or a Watchdog Timer time-out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the voltage
reference should be disabled.
20.4
Effects of a RESET
A device RESET disables the voltage reference by
clearing bit VREN (VRCON register). This RESET also
disconnects the reference from the RA2 pin by clearing
bit VROE (VRCON register) and selects the high volt-
age range by clearing bit CVRR (VRCON register). The
VRSS value select bits, CVRCON<3:0>, are also
cleared.
FIGURE 20-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
(1)
R
RF5
CVREF
Module
+
–
•
CVREF Output
•
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Value On
Value On
All Other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
VRCON
VREN
VROE
VRR
VRSS
VR3
CIS
VR2
CM2
VR1
CM1
VR0
CM0
0000 0000 0000 0000
0000 0000 0000 0000
CMCON C2OUT C1OUT C2INV C1INV
TRISF
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111
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DS30475A-page 245
PIC18CXX8
NOTES:
DS30475A-page 246
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Figure 21-2 shows the block diagram for the LVD mod-
ule. A comparator uses an internally generated refer-
ence voltage as the set point. When the selected tap
output of the device voltage crosses the set point (is
lower than), the LVDIF bit (PIR registers) is set.
21.0 LOW VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application soft-
ware can do "housekeeping tasks" before the device
voltage exits the valid operating range. This can be
done using the Low Voltage Detect module.
Each node in the resister divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array (or external LVDIN input
pin) is equal to the voltage generated by the internal
voltage reference module. The comparator then gener-
ates an interrupt signal setting the LVDIF bit. This volt-
age is software programmable to any one of 16 values
(See Figure 21-2). The trip point is selected by pro-
gramming the LVDL3:LVDL0 bits (LVDCON<3:0>).
This module is software programmable circuitry, where
a device voltage trip point can be specified (internal ref-
erence voltage or external voltage input). When the
voltage of the device becomes lower than the specified
point, an interrupt flag is set. If the interrupt is enabled,
the program execution will branch to the interrupt vec-
tor address and the software can then respond to that
interrupt source.
The Low Voltage Detect circuitry is completely under
software control. This allows the circuitry to be "turned
off" by the software, which minimizes the current con-
sumption for the device.
FIGURE 21-2: LOW VOLTAGE DETECT
(LVD) BLOCK DIAGRAM
Figure 21-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage
VA, the LVD logic generates an interrupt. This occurs at
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shut down the system. Voltage point VB is the
minimum valid operating voltage specification. This
occurs at time TB. TB - TA is the total time for shutdown.
VDD LVDIN
LVD Control
Register
FIGURE 21-1: TYPICAL LOW VOLTAGE
DETECT APPLICATION
LVDIF
VA
VB
LVDEN
Internally Generated
Reference Voltage
TB
TA
Time
Legend:
VA = LVD trip point
VB = Minimum valid device operating range
2000 Microchip Technology Inc.
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PIC18CXX8
21.1
Control Register
The Low Voltage Detect Control register (Register 21-1)
controls the operation of the Low Voltage Detect
circuitry.
REGISTER 21-1: LVDCON REGISTER
U-0
—
U-0
—
R-0
R/W-0
R/W-0
LVDL3
R/W-1
LVDL2
R/W-0
LVDL1
R/W-1
LVDL0
IRVST
LVDEN
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as '0'
IRVST: Internal Reference Voltage Stable Flag bit
1= Indicates that the Low Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0= Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the spec-
ified voltage range and the LVD interrupt should not be enabled
bit 4
LVDEN: Low Voltage Detect Power Enable bit
1= Enables LVD, powers up LVD circuit
0= Disables LVD, powers down LVD circuit
bit 3-0
LVDL3:LVDL0: Low Voltage Detection Limit bits
1111= External analog input is used (input comes from the LVDIN pin)
1110= 4.5V min - 4.77V max.
1101= 4.2V min - 4.45V max.
1100= 4.0V min - 4.24V max.; Reserved on PIC18CXX8
1011= 3.8V min - 4.03V max.; Reserved on PIC18CXX8
1010= 3.6V min - 3.82V max.; Reserved on PIC18CXX8
1001= 3.5V min - 3.71V max.; Reserved on PIC18CXX8
1000= 3.3V min - 3.50V max.; Reserved on PIC18CXX8
0111= 3.0V min - 3.18V max.; Reserved on PIC18CXX8
0110= 2.8V min - 2.97V max.; Reserved on PIC18CXX8
0101= 2.7V min - 2.86V max.; Reserved on PIC18CXX8
0100= 2.5V min - 2.65V max.; Reserved on PIC18CXX8
0011= Reserved on PIC18CXX8 and PIC18LCXX8
0010= Reserved on PIC18CXX8 and PIC18LCXX8
0001= Reserved on PIC18CXX8 and PIC18LCXX8
0000= Reserved on PIC18CXX8 and PIC18LCXX8
Note: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of
the device are not tested.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30475A-page 248
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
The following steps are needed to setup the LVD
module:
21.2
Operation
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be con-
stantly operating. To decrease current consumption,
the LVD circuitry only needs to be enabled for short
periods, where the voltage is checked. After doing the
check, the LVD module may be disabled.
1. Write the value to the LVDL3:LVDL0 bits
(LVDCON register), which selects the desired
LVD Trip Point.
2. Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
3. Enable the LVD module (set the LVDEN bit in
the LVDCON register).
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
4. Wait for the LVD module to stabilize (the IRVST
bit to become set).
5. Clear the LVD interrupt flag, which may have
falsely become set, until the LVD module has
stabilized (clear the LVDIF bit).
6. Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 21-3 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 21-3: LOW VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set
VDD
.
VLVD
LVDIF
Enable LVD
50 ms
Internally Generated
Reference Stable
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
50 ms
Internally Generated
Reference Stable
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
2000 Microchip Technology Inc.
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DS30475A-page 249
PIC18CXX8
21.2.1 REFERENCE VOLTAGE SET POINT
21.4
Operation During SLEEP
The Internal Reference Voltage of the LVD module may
be used by other internal circuitry (the programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires time to become stable before a low voltage
condition can be reliably detected. This time is invariant
of system clock speed. This start-up time is specified in
electrical specification parameter #36. The low voltage
interrupt flag will not be enabled until a stable reference
voltage is reached. Refer to the waveform in
Figure 21-3.
When enabled, the LVD circuitry continues to operate
during SLEEP. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wake-
up from SLEEP. Device execution will continue from
the interrupt vector address if interrupts have been glo-
bally enabled.
21.5
Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the LVD module to be turned off.
21.2.2 CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static cur-
rent. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
21.3
External Analog Voltage Input
The LVD module has an additional feature that allows
the user to supply the trip point voltage to the module
from an external source (the LVDIN pin). The LVDIN pin
is used as the trip point when the LVDL3:LVDL0 bits =
’1111’. This state connects the LVDIN pin voltage to
the comparator. The other comparator input is con-
nected to an internal reference voltage source.
DS30475A-page 250
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2000 Microchip Technology Inc.
PIC18CXX8
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
22.0 SPECIAL FEATURES OF THE
CPU
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection:
• OSC Selection
• RESET
22.1
Configuration Bits
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Programmable Brown-out Reset (BOR)
• Interrupts
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h - 3FFFFFh),
which can only be accessed using table reads and
table writes.
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-circuit Serial Programming
PIC18CXX8 devices have a Watchdog Timer, which is
permanently enabled via the configuration bits or it can
be software-controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer nec-
essary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
RESET until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT), which provides a fixed
delay on power-up only, designed to keep the part in
RESET while the power supply stabilizes. With these
two timers on-chip, most applications need no external
RESET circuitry.
TABLE 22-1: CONFIGURATION BITS AND DEVICE ID’S
Default/
Unprogrammed
Value
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300006h CONFIG4L
3FFFFEh DEVID1
CP
r
CP
r
CP
OSCSEN
—
CP
—
CP
—
CP
CP
CP
1111 1111
111- -111
---- 1111
---- 1111
---- --11
1111 1111
1111 1111
FOSC2
BORV0
FOSC1
FOSC0
—
—
—
—
—
—
—
BORV1
BODEN PWRTEN
—
—
WDTPS2 WDTPS1 WDTPS0 WDTEN
—
—
—
—
r
STVREN
REV0
DEV2 DEV1
DEV10 DEV9
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
3FFFFFh DEVID2
DEV3
Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition, r = reserved.
Grayed cells are unimplemented, read as ’0’.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 251
PIC18CXX8
REGISTER 22-1: CONFIGURATION REGISTER 1 LOW (CONFIG1L: BYTE ADDRESS 0x300000)
R/P-1
CP
R/P-1
CP
R/P-1
CP
R/P-1
CP
R/P-1
CP
R/P-1
CP
R/P-1
CP
R/P-1
CP
bit 7
bit 0
bit 7-0
CP: Code Protection bits (apply when in Code Protected Microcontroller mode)
1= Program memory code protection off
0= All of program memory code protected
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 22-2: CONFIGURATION REGISTER 1 HIGH (CONFIG1H: BYTE ADDRESS 0x300001)
R/P-1
R/P-1
R/P-1
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
Reserved Reserved OSCSEN
bit 7
FOSC2 FOSC1
FOSC0
bit 0
bit 7-6
bit 5
Reserved: Maintain this bit set
OSCSEN: Oscillator System Clock Switch Enable bit
1= Oscillator system clock switch option is disabled (Main oscillator is source)
0= Oscillator system clock switch option is enabled (Oscillator switching is enabled)
bit 4-3
bit 2-0
Unimplemented: Read as ’0’
FOSC2:FOSC0: Oscillator Selection bits
111= RC oscillator w/ OSC2 configured as RA6
110= HS4 oscillator with PLL enabled/Clock frequency = (4 x Fosc)
101= EC oscillator w/ OSC2 configured as RA6
100= EC oscillator w/ OSC2 configured as divide by 4 clock output
011= RC oscillator
010= HS oscillator
001= XT oscillator
000= LP oscillator
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
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2000 Microchip Technology Inc.
PIC18CXX8
REGISTER 22-3: CONFIGURATIONREGISTER2LOW(CONFIG2L:BYTEADDRESS0x300002)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
BORV1
BORV0 BOREN PWRTEN
bit 0
bit 7
bit 7-4
bit 3-2
Unimplemented: Read as ’0’
BORV1:BORV0: Brown-out Reset Voltage bits
11=VBOR set to 2.5V
10=VBOR set to 2.7V
01=VBOR set to 4.2V
00=VBOR set to 4.5V
bit 1
bit 0
BOREN: Brown-out Reset Enable bit(1)
1= Brown-out Reset enabled
0= Brown-out Reset disabled
PWRTEN: Power-up Timer Enable bit(1)
1= PWRT disabled
0= PWRT enabled
Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT),
regardless of the value of bit PWRTEN. Ensure the Power-up Timer is enabled any
time Brown-out Reset is enabled.
Legend:
R = Readable bit
- n = Value when device is unprogrammed
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
REGISTER 22-4:
CONFIGURATIONREGISTER2HIGH(CONFIG2H:BYTEADDRESS0x300003)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 0
bit 7
bit 7-4
bit 3-1
Unimplemented: Read as ’0’
WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
000= 1:128
001= 1:64
010= 1:32
011= 1:16
100= 1:8
101= 1:4
110= 1:2
111= 1:1
bit 0
WDTEN: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
2000 Microchip Technology Inc.
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DS30475A-page 253
PIC18CXX8
REGISTER 22-5: CONFIGURATION REGISTER 4 LOW (CONFIG4L: BYTE ADDRESS 0x300006)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
Reserved STVREN
bit 0
bit 7
bit 7-2
bit 1
Unimplemented: Read as ’0’
Reserved: Maintain this bit set
bit 0
STVREN: Stack Full/Underflow RESET Enable bit
1= Stack Full/Underflow will cause RESET
0= Stack Full/Underflow will not cause RESET
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
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2000 Microchip Technology Inc.
PIC18CXX8
The WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT postscaler may be assigned using
the configuration bits.
22.2
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKI pin. That means that the WDT will run,
even if the clock on the OSC1/CLKI and
OSC2/CLKO/RA6 pins of the device has been stopped;
for example, by execution of a SLEEPinstruction.
Note: The CLRWDTand SLEEPinstructions clear
the WDT and the postscaler if assigned to
the WDT, and prevent it from timing out
and generating a device RESET condition.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the RCON register
will be cleared upon a WDT time-out.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
22.2.1 CONTROL REGISTER
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software exe-
cution may not disable this function. When the WDTEN
configuration bit is cleared, the SWDTEN bit
enables/disables the operation of the WDT.
Register 22-6 shows the WDTCON register. This is a
readable and writable register, which contains a control
bit that allows software to override the WDT enable
configuration bit, only when the configuration bit has
disabled the WDT.
REGISTER 22-6: WDTCON REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SWDTEN
bit 0
bit 7
bit 7-1
bit 0
Unimplemented: Read as ’0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1= Watchdog Timer is on
0= Watchdog Timer is turned off if the WDTEN configuration bit in the configuration register = ’0’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’ - n = Value at POR
2000 Microchip Technology Inc.
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DS30475A-page 255
PIC18CXX8
22.2.2 WDT POSTSCALER
The WDT has a postscaler that can extend the WDT
Reset period. The postscaler is selected at the time of
the device programming, by the value written to the
CONFIG2H configuration register.
FIGURE 22-1: WATCHDOG TIMER BLOCK DIAGRAM
WDT Timer
Postscaler
8
8 - to - 1 MUX
WDTPS2:WDTPS0
WDTEN
SWDTEN bit
Configuration bit
WDT
Time-out
Note: WDPS2:WDPS0 are bits in a configuration register.
TABLE 22-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG2H
RCON
—
IPEN
—
—
LWRT
—
—
—
—
—
RI
—
WDTPS2
TO
WDTPS2
PD
WDTPS0
POR
WDTEN
BOR
WDTCON
—
—
—
SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
DS30475A-page 256
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
The following peripheral interrupts can wake the device
from SLEEP:
22.3
Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
1. PSP read or write.
2. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
Upon entering into Power-down mode, the following
actions are performed:
3. TMR3 interrupt. Timer3 must be operating as
an asynchronous counter.
1. Watchdog Timer is cleared and kept running.
2. PD bit in RCON register is cleared.
3. TO bit in RCON register is set.
4. CCP Capture mode interrupt.
5. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
4. Oscillator driver is turned off.
5. I/O ports maintain the status they had before the
6. MSSP (START/STOP) bit detect interrupt.
SLEEPinstruction was executed.
7. MSSP transmit or receive in Slave mode
(SPI/I2C).
To achieve lowest current consumption, follow these
steps before switching to Power-down mode:
8. USART RX or TX (Synchronous Slave mode).
9. A/D conversion (when A/D clock source is RC).
10. Activity on CAN bus receive line.
1. Place all I/O pins at either VDD or VSS and
ensure no external circuitry is drawing current
from I/O pin.
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
2. Power-down A/D and external clocks.
3. Pull all hi-impedance inputs to high or low
externally.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and will cause a "wake-up". The TO and PD
bits in the RCON register can be used to determine the
cause of the device RESET. The PD bit, which is set on
power-up, is cleared when SLEEPis invoked. The TO
bit is cleared, if a WDT time-out occurred (and caused
wake-up).
4. Place T0CKI at VSS or VDD.
5. Current consumption by PORTB on-chip
pull-ups should be taken into account and dis-
abled if necessary.
The MCLR pin must be at a logic high level (VIHMC).
22.3.1 WAKE-UP FROM SLEEP
When the SLEEPinstruction is being executed, the next
instruction (PC + 2) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
The device can wake-up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or a
Peripheral Interrupt.
2000 Microchip Technology Inc.
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DS30475A-page 257
PIC18CXX8
22.3.2 WAKE-UP USING INTERRUPTS
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If an interrupt condition (interrupt flag bit and inter-
rupt enable bits are set) occurs before the execu-
tion of a SLEEPinstruction, the SLEEPinstruction
will complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
• If the interrupt condition occurs during or after
the execution of a SLEEPinstruction, the device
will immediately wake-up from sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
FIGURE 22-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
(2)
TOST
INTIF bit
GIEH bit
Interrupt Latency(3)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+2
PC+4
PC+4
PC + 4
0008h
000Ah
Instruction
Inst(0008h)
Inst(PC + 2)
Inst(PC + 4)
Inst(000Ah)
Inst(PC) = SLEEP
Inst(PC - 1)
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 2)
Inst(0008h)
Note 1:
2:
XT, HS or LP oscillator mode assumed.
GIE set is assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
If GIE is cleared, execution will continue in-line.
3:
4:
TOST = 1024TOSC (drawing not to scale). This delay will not occur for RC and EC osc modes.
CLKOUT is not available in these oscillator modes, but shown here for timing reference.
DS30475A-page 258
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2000 Microchip Technology Inc.
PIC18CXX8
22.4
Program Verification/Code Protection
22.6
In-Circuit Serial Programming
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
PIC18CXX8 microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
Note: Microchip Technology does not recom-
mend code protecting windowed devices.
22.5
ID Locations
Five memory locations (200000h - 200004h) are desig-
nated as ID locations, where the user can store check-
sum or other code identification numbers. These
locations are accessible during normal execution
through the TBLRDinstruction, or during program/ver-
ify. The ID locations can be read when the device is
code protected.
22.7
Device ID Bits
Device ID bits are located in program memory at
3FFFFEh and 3FFFFFh. The Device ID bits are used
by programmers to retrieve part number and revision
information about a device. These registers may also
be accessed using a TBLRDinstruction (Register 22-8
and Register 22-7).
REGISTER 22-7: DEVID1 ID REGISTER FOR THE PIC18CXX8 DEVICE (0x3FFFFE)
R/P-1
DEV2
R/P-1
DEV1
R/P-1
DEV0
R/P-1
REV4
R/P-1
REV3
R/P-1
REV2
R/P-1
REV1
R/P-1
REV0
bit 7
bit 0
bit 7-5 DEV2:DEV0: Device ID bits
These bits are used with the DEV10:DEV3 bits in the Device ID register 2
to identify the part number
bit 4-0 REV4:REV0: Revision ID bits
These bits are used to indicate the revision of the device
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Unprogrammed Value
(x = unknown)
REGISTER 22-8: DEVID2 ID REGISTER FOR THE PIC18CXX8 DEVICE (0x3FFFFF)
R/P-1
R/P-1
DEV9
R/P-1
DEV8
R/P-1
DEV7
R/P-1
DEV6
R/P-1
DEV5
R/P-1
DEV4
R/P-1
DEV3
DEV10
bit 7
bit 0
bit 7-0 DEV10:DEV3: Device ID bits
These bits are used with the DEV2:DEV0 bits in the Device ID register 1
to identify the part number
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Unprogrammed Value
(x = unknown)
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DS30475A-page 259
PIC18CXX8
NOTES:
DS30475A-page 260
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
The control instructions may use some of the following
operands:
23.0 INSTRUCTION SET SUMMARY
The PIC18CXX8 instruction set adds many enhance-
ments to the previous PICmicro® instruction sets, while
maintaining an easy migration from these PICmicro
instruction sets.
• A program memory address (specified by the
value of ’n’)
• The mode of the Call or Return instructions (spec-
ified by the value of ’s’)
• The mode of the Table Read and Table Write
instructions (specified by the value of ’m’)
• No operand required
Most instructions are a single program memory word
(16-bits), but there are three instructions that require
two program memory locations.
Each single word instruction is a 16-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction.
(specified by the value of ’—’)
All instructions are a single word, except for four double
word instructions. These three instructions were made
double word instructions so that all the required infor-
mation is available in these 32-bits. In the second word,
the 4-MSb’s are 1’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
All single word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
• Control operations
The PIC18CXX8 instruction set summary in
Table 23-2 lists byte-oriented, bit-oriented, literal
and control operations. Table 23-1 shows the opcode
field descriptions.
The double word instructions execute in two instruction
cycles.
Most byte-oriented instructions have three operands:
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 µs. Two
word branch instructions (if true) would take 3 µs.
1. The file register (specified by the value of ’f’)
2. The destination of the result
(specified by the value of ’d’)
3. The accessed memory
(specified by the value of ’a’)
'f' represents a file register designator and 'd' repre-
sents a destination designator. The file register desig-
nator specifies which file register is to be used by the
instruction.
Figure 23-1 shows the general formats that the instruc-
tions can have.
All examples use the following format to represent a
hexadecimal number:
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the WREG register. If 'd' is one, the result is
placed in the file register specified in the instruction.
0xhh
where h signifies a hexadecimal digit.
The Instruction Set Summary, shown in Table 23-2,
lists the instructions recognized by the Microchip
assembler (MPASMTM).
All bit-oriented instructions have three operands:
1. The file register (specified by the value of ’f’)
Section 23.1 provides a description of each instruction.
2. The bit in the file register
(specified by the value of ’b’)
3. The accessed memory
(specified by the value of ’a’)
'b' represents a bit field designator which selects the
number of the bit affected by the operation, while 'f' rep-
resents the number of the file in which the bit is located.
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
(specified by the value of ’k’)
• The desired FSR register to load the literal value
into (specified by the value of ’f’)
• No operand required
(specified by the value of ’—’)
2000 Microchip Technology Inc.
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DS30475A-page 261
PIC18CXX8
TABLE 23-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
ACCESS = 0: RAM access bit symbol
ACCESS
BANKED
bbb
BANKED = 1: RAM access bit symbol
Bit address within an 8-bit file register (0 to 7)
Bank Select Register. Used to select the current RAM bank.
Destination select bit;
BSR
d
d = 0: store result in WREG,
d = 1: store result in file register f.
dest
f
Destination either the WREG register or the specified register file location
8-bit Register file address (0x00 to 0xFF)
fs
12-bit Register file address (0x000 to 0xFFF). This is the source address.
fd
12-bit Register file address (0x000 to 0xFFF). This is the destination address.
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
Label name
label
mm
The mode of the TBLPTR register for the Table Read and Table Write instructions
Only used with Table Read and Table Write instructions:
No Change to register (such as TBLPTR with Table reads and writes)
Post-Increment register (such as TBLPTR with Table reads and writes)
Post-Decrement register (such as TBLPTR with Table reads and writes)
Pre-Increment register (such as TBLPTR with Table reads and writes)
The relative address (2’s complement number) for relative branch instructions, or the direct
address for Call/Branch and Return instructions
Product of Multiply high byte (Register at address 0xFF4)
Product of Multiply low byte (Register at address 0xFF3)
Fast Call / Return mode select bit.
*
*+
*-
+*
n
PRODH
PRODL
s
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
Unused or Unchanged (Register at address 0xFE8)
W = 0: Destination select bit symbol
u
W
WREG
x
Working register (accumulator) (Register at address 0xFE8)
Don't care (0 or 1)
The assembler will generate code with x = 0. It is the recommended form of use for compatibility
with all Microchip software tools.
TBLPTR
TABLAT
TOS
21-bit Table Pointer (points to a Program Memory location) (Register at address 0xFF6)
8-bit Table Latch (Register at address 0xFF5)
Top-of-Stack
PC
Program Counter
PCL
Program Counter Low Byte (Register at address 0xFF9)
Program Counter High Byte
PCH
PCLATH
PCLATU
GIE
Program Counter High Byte Latch (Register at address 0xFFA)
Program Counter Upper Byte Latch (Register at address 0xFFB)
Global Interrupt Enable bit
WDT
Watchdog Timer
TO
Time-out bit
PD
Power-down bit
C, DC, Z, OV, N ALU status bits Carry, Digit Carry, Zero, Overflow, Negative
[ ]
Optional
( )
Contents
→
Assigned to
< >
∈
Register bit field
In the set of
italics
User defined term (font is courier)
DS30475A-page 262
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 23-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
Example Instruction
15
10
9
d
8
7
0
OPCODE
a
f (FILE #)
ADDWF MYREG, W, B
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select Bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
OPCODE
f (Source FILE #)
MOVFF MYREG1, MYREG2
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11
9
8
7
0
OPCODE b (BIT #)
a
f (FILE #)
BSF MYREG, bit, B
b = 3-bit position of bit in file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select Bank
f = 8-bit file register address
Literal operations
15
8
7
0
OPCODE
k (literal)
MOVLW 0x7F
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
0
OPCODE
12 11
n<7:0> (literal)
GOTO Label
15
1111
n<19:8> (literal)
n = 20-bit immediate value
8 7
15
15
0
0
CALL MYFUNC
OPCODE
12 11
n<7:0> (literal)
S
1111
n<19:8> (literal)
S = Fast bit
11 10
15
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
15
OPCODE
n<10:0> (literal)
n<7:0> (literal)
4
8 7
15
6
0
LFSR FSR0, 0x100
OPCODE
f
k (literal)
15
11
0000
7
0
1111
k (literal)
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 263
PIC18CXX8
TABLE 23-2: PIC18CXX8 INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Status
Affected
Description
Cycles
Notes
Operands
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF f [,d] [,a] Add WREG and f
1
1
1
1
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2, 6
0010 00da ffff ffff C, DC, Z, OV, N 1, 2, 6
0001 01da ffff ffff Z, N
0110 101a ffff ffff Z
0001 11da ffff ffff Z, N
ADDWFC f [,d] [,a] Add WREG and Carry bit to f
ANDWF
CLRF
COMF
f [,d] [,a] AND WREG with f
f [,a] Clear f
f [,d] [,a] Complement f
1,2, 6
2, 6
1, 2, 6
4, 6
4, 6
1, 2, 6
CPFSEQ f [,a]
CPFSGT f [,a]
CPFSLT f [,a]
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
1 (2 or 3) 0110 001a ffff ffff None
1 (2 or 3) 0110 010a ffff ffff None
1 (2 or 3) 0110 000a ffff ffff None
DECF
f [,d] [,a] Decrement f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4, 6
DECFSZ f [,d] [,a] Decrement f, Skip if 0
DCFSNZ f [,d] [,a] Decrement f, Skip if Not 0
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1, 2, 3, 4, 6
1, 2, 6
INCF
f [,d] [,a] Increment f
1
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4, 6
INCFSZ
INFSNZ
IORWF
MOVF
f [,d] [,a] Increment f, Skip if 0
f [,d] [,a] Increment f, Skip if Not 0
f [,d] [,a] Inclusive OR WREG with f
f [,d] [,a] Move f
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4, 6
1, 2, 6
1, 2, 6
1, 6
1
1
2
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF
f , f
Move f (source) to 1st word
s
d
s
f (destination)2nd word
d
MOVWF f [,a]
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N 1, 2, 6
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
6
6
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
f [,a]
f [,a]
f [,d] [,a] Rotate Left f through Carry
f [,d] [,a] Rotate Left f (No Carry)
f [,d] [,a] Rotate Right f through Carry
f [,d] [,a] Rotate Right f (No Carry)
6
1, 2, 6
6
6
6
f [,a]
Set f
SUBFWB f [,d] [,a] Subtract f from WREG with
borrow
0101 01da ffff ffff C, DC, Z, OV, N 1, 2, 6
SUBWF
f [,d] [,a] Subtract WREG from f
1
1
0101 11da ffff ffff C, DC, Z, OV, N
0101 10da ffff ffff C, DC, Z, OV, N 1, 2, 6
6
SUBWFB f [,d] [,a] Subtract WREG from f with
borrow
SWAPF
TSTFSZ f [,a]
XORWF f [,d] [,a] Exclusive OR WREG with f
BIT-ORIENTED FILE REGISTER OPERATIONS
f [,d] [,a] Swap nibbles in f
1
0011 10da ffff ffff None
4, 6
1, 2, 6
6
Test f, skip if 0
1 (2 or 3) 0110 011a ffff ffff None
1
0001 10da ffff ffff Z, N
BCF
BSF
BTFSC
BTFSS
BTG
f, b [,a] Bit Clear f
f, b [,a] Bit Set f
f, b [,a] Bit Test f, Skip if Clear
f, b [,a] Bit Test f, Skip if Set
f [,d] [,a] Bit Toggle f
1
1
1001 bbba ffff
1000 bbba ffff
ffff None
ffff None
ffff None
ffff None
ffff None
1, 2, 6
1, 2, 6
3, 4, 6
3, 4, 6
1, 2, 6
1 (2 or 3) 1011 bbba ffff
1 (2 or 3) 1010 bbba ffff
1
0111 bbba ffff
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
6: Microchip Assembler MASM automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’
according to address of register being used.
DS30475A-page 264
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 23-2: PIC18CXX8 INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address1st word
2nd word
1 (2)
1110 0010 nnnn
1110 0110 nnnn
1110 0011 nnnn
1110 0111 nnnn
1110 0101 nnnn
1110 0001 nnnn
1110 0100 nnnn
1101 0nnn nnnn
1110 0000 nnnn
1110 110s kkkk
1111 kkkk kkkk
0000 0000 0000
0000 0000 0000
1110 1111 kkkk
1111 kkkk kkkk
0000 0000 0000
1111 xxxx xxxx
0000 0000 0000
0000 0000 0000
1101 1nnn nnnn
0000 0000 1111
0000 0000 0001
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
kkkk None
kkkk
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
CALL
CLRWDT
DAW
GOTO
—
—
n
1
1
2
0100 TO, PD
0111
C
kkkk None
kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
1
1
1
1
2
1
2
0000 None
xxxx None
0110 None
0101 None
nnnn None
1111 All
No Operation (Note 4)
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device RESET
Return from interrupt enable
s
000s GIE/GIEH,
PEIE/GIEL
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100 kkkk
0000 0000 0001
0000 0000 0000
kkkk None
001s None
0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an
external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
6: Microchip Assembler MASM automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’
according to address of register being used.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 265
PIC18CXX8
TABLE 23-2: PIC18CXX8 INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Load FSR(f) with a 12-bit
literal (k)
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
1
1
1
2
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
1
1
1
2
1
Exclusive OR literal with WREG 1
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2 (5)
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
6: Microchip Assembler MASM automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’
according to address of register being used.
DS30475A-page 266
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
23.1
Instruction Set
ADDLW
ADDWF
ADD literal to W
ADD W to f
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] ADDWF f [,d] [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(WREG) + k → WREG
N,OV, C, DC, Z
Operation:
(WREG) + (f) → dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
Description:
The contents of WREG are added
to the 8-bit literal ’k’ and the result is
placed in WREG.
0010
01da
ffff
ffff
Description:
Add WREG to register ’f’. If ’d’ is 0,
the result is stored in WREG. If ’d’
is 1, the result is stored back in reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected. If ’a’
is 1, the Bank will be selected as
per the BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write to W
Words:
Cycles:
1
1
ADDLW
0x15
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
WREG
N
OV
C
DC
Z
=
=
=
=
=
=
0x10
Decode
Read
register ’f’
Process
Data
Write to
destination
?
?
?
?
?
ADDWF
REG, W
Example:
Before Instruction
After Instruction
WREG
REG
N
OV
C
=
0x17
0xC2
WREG
N
OV
C
DC
Z
=
=
=
=
=
=
0x25
=
=
=
=
=
=
0
0
0
0
0
?
?
?
?
?
DC
Z
After Instruction
WREG
REG
N
OV
C
=
=
=
=
=
=
=
0xD9
0xC2
1
0
0
0
0
DC
Z
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 267
PIC18CXX8
ADDWFC
Syntax:
ADD WREG and Carry bit to f
ANDLW
AND literal with WREG
[ label ] ADDWFC f [ ,d [,a] ]
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
(WREG) .AND. k → WREG
N,Z
Operation:
(WREG) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
Description:
The contents of WREG are AND’ed
with the 8-bit literal 'k'. The result is
placed in WREG.
0010
00da
ffff
ffff
Description:
Add WREG, the Carry Flag and data
memory location ’f’. If ’d’ is 0, the
result is placed in WREG. If ’d’ is 1,
the result is placed in data memory
location 'f'. If ’a’ is 0, the Access
Bank will be selected. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
’k’
Process
Data
Write to W
Words:
Cycles:
1
1
ANDLW
0x5F
Example:
Q Cycle Activity:
Q1
Before Instruction
WREG
=
=
=
0xA3
?
?
Q2
Q3
Q4
N
Z
Decode
Read
register ’f’
Process
Data
Write to
destination
After Instruction
WREG
N
Z
=
=
=
0x03
0
0
ADDWFC
REG, W
Example:
Before Instruction
C
=
1
REG
WREG
N
OV
DC
Z
=
=
=
=
=
=
0x02
0x4D
?
?
?
?
After Instruction
C
=
=
=
=
=
=
=
0
0x02
0x50
0
0
0
0
REG
WREG
N
OV
DC
Z
DS30475A-page 268
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
ANDWF
Syntax:
AND WREG with f
BC
Branch if Carry
[ label ] BC
[ label ] ANDWF f [ ,d [,a] ]
Syntax:
Operands:
Operation:
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
-128 ≤ n ≤ 127
if carry bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(WREG) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N,Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ’1’, then the pro-
gram will branch.
Description:
The contents of WREG are AND’ed
with register 'f'. If 'd' is 0, the result
is stored in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected. If ’a’ is 1, the
bank will be selected as per the
BSR value.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
Decode
Read literal
’n’
Process
Data
Write to PC
No
No
No
No
operation
operation
operation
operation
ANDWF
REG, W
Example:
If No Jump:
Q1
Before Instruction
Q2
Q3
Q4
WREG
REG
N
=
0x17
0xC2
?
=
=
=
Decode
Read literal
’n’
Process
Data
No
operation
Z
?
After Instruction
HERE
BC
5
Example:
WREG
REG
N
=
=
=
=
0x02
0xC2
0
Before Instruction
PC
=
address (HERE)
Z
0
After Instruction
If Carry
=
=
=
=
1;
PC
If Carry
PC
address (HERE+12)
0;
address (HERE+2)
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 269
PIC18CXX8
BCF
Bit Clear f
BN
Branch if Negative
[ label ] BN
Syntax:
Operands:
[ label ] BCF f, b [,a]
Syntax:
Operands:
Operation:
n
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
-128 ≤ n ≤ 127
if negative bit is ’1’
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ’1’, then the
program will branch.
Description:
Bit 'b' in register 'f' is cleared. If ’a’
is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ = 1, the Bank will be selected
as per the BSR value.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
Q Cycle Activity:
Q1
1(2)
Q2
Q3
Q4
Q Cycle Activity:
If Jump:
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Q1
Q2
Q3
Q4
BCF
FLAG_REG,
7
Decode
Read literal
’n’
Process
Data
Write to PC
Example:
Before Instruction
No
operation
No
operation
No
operation
No
operation
FLAG_REG = 0xC7
After Instruction
If No Jump:
Q1
FLAG_REG = 0x47
Q2
Q3
Q4
Decode
Read literal
’n’
Process
Data
No
operation
HERE
BN Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE+2)
If Negative
PC
DS30475A-page 270
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
-128 ≤ n ≤ 127
if carry bit is ’0’
n
Syntax:
[ label ] BNN
-128 ≤ n ≤ 127
n
Operands:
Operation:
Operands:
Operation:
if negative bit is ’0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ’0’, then the pro-
gram will branch.
Description:
If the Negative bit is ’0’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
’n’
Process
Data
Write to PC
Decode
Read literal
’n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
’n’
Process
Data
No
operation
Decode
Read literal
’n’
Process
Data
No
operation
HERE
BNC Jump
HERE
BNN Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Negative
PC
If Carry
=
=
=
=
0;
=
=
=
=
0;
PC
If Carry
PC
address (Jump)
1;
address (HERE+2)
address (Jump)
1;
address (HERE+2)
If Negative
PC
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 271
PIC18CXX8
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
-128 ≤ n ≤ 127
n
Syntax:
[ label ] BNZ
-128 ≤ n ≤ 127
if zero bit is ’0’
n
Operands:
Operation:
Operands:
Operation:
if overflow bit is ’0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ’0’, then the
program will branch.
Description:
If the Zero bit is ’0’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
’n’
Process
Data
Write to PC
Decode
Read literal
’n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
’n’
Process
Data
No
operation
Decode
Read literal
’n’
Process
Data
No
operation
HERE
BNOV Jump
HERE
BNZ Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
If Overflow
PC
After Instruction
=
=
=
=
0;
If Zero
=
=
=
=
0;
address (Jump)
1;
address (HERE+2)
PC
If Zero
PC
address (Jump)
1;
address (HERE+2)
If Overflow
PC
DS30475A-page 272
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
BRA
Unconditional Branch
[ label ] BRA
BSF
Bit Set f
Syntax:
n
Syntax:
Operands:
[ label ] BSF f, b [,a]
Operands:
Operation:
Status Affected:
Encoding:
Description:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation:
1 → f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Add the 2’s complement number
’2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a two-
cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit 'b' in register 'f' is set. If ’a’ is 0
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
’n’
Process
Data
Write to PC
Decode
Read
register ’f’
Process
Data
Write
register ’f’
No
No
No
No
operation
operation
operation
operation
BSF
FLAG_REG, 7, 1
Example:
Before Instruction
HERE
BRA Jump
Example:
FLAG_REG
=
=
0x0A
Before Instruction
After Instruction
FLAG_REG
PC
=
=
address (HERE)
address (Jump)
0x8A
After Instruction
PC
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 273
PIC18CXX8
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f, b [,a]
Syntax:
[ label ] BTFSS f, b [,a]
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
None
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Status Affected:
Encoding:
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit 'b' in register ’f' is 0, then the
next instruction is skipped.
Description:
If bit 'b' in register 'f' is 1 then the next
instruction is skipped.
If bit 'b' is 0, then the next instruction
fetched during the current instruction
execution is discarded, and a NOPis
executed instead, making this a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the BSR
value.
If bit 'b' is 1, then the next instruction
fetched during the current instruc-
tion execution, is discarded and an
NOPis executed instead, making this
a two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the BSR
value.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
No
operation
Decode
Read
register ’f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, ACCESS
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, ACCESS
Example:
Example:
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
If FLAG<1>
PC
After Instruction
If FLAG<1>
PC
=
=
=
=
0;
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
address (FALSE)
1;
address (TRUE)
If FLAG<1>
PC
If FLAG<1>
PC
DS30475A-page 274
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
Operands:
[ label ] BTG f, b [,a]
Syntax:
[ label ] BOV
-128 ≤ n ≤ 127
n
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operands:
Operation:
if overflow bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ’1’, then the
program will branch.
Description:
Bit ’b’ in data memory location ’f’ is
inverted. If ’a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ’a’ is 1, the Bank will be
selected as per the BSR value.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
Q Cycle Activity:
Q1
1(2)
Q2
Q3
Q4
Q Cycle Activity:
If Jump:
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Q1
Q2
Q3
Q4
BTG
PORTC,
4
Decode
Read literal
’n’
Process
Data
Write to PC
Example:
Before Instruction:
No
operation
No
operation
No
operation
No
operation
PORTC
=
0111 0101[0x75]
After Instruction:
If No Jump:
Q1
PORTC
=
0110 0101[0x65]
Q2
Q3
Q4
Decode
Read literal
’n’
Process
Data
No
operation
HERE
BOV Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Overflow
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE+2)
If Overflow
PC
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 275
PIC18CXX8
BZ
Branch if Zero
[ label ] BZ
CALL
Subroutine Call
Syntax:
Operands:
Operation:
n
Syntax:
Operands:
[ label ] CALL k [,s]
-128 ≤ n ≤ 127
0 ≤ k ≤ 1048575
s ∈ [0,1]
if Zero bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>,
if s = 1
(WREG) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
Description:
If the Zero bit is ’1’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2M byte
memory range. First, return
Words:
Cycles:
1
address (PC+ 4) is pushed onto the
return stack. If ’s’ = 1, the WREG,
STATUS and BSR registers are
also pushed into their respective
shadow registers, WS, STATUSS
and BSRS. If 's' = 0, no update
occurs (default). Then the 20-bit
value ’k’ is loaded into PC<20:1>.
CALLis a two-cycle instruction.
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
’n’
Process
Data
Write to PC
No
operation
No
No
No
operation
operation
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
’n’
Process
Data
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal Push PC to Read literal
HERE
BZ Jump
Example:
’k’<7:0>,
stack
’k’<19:8>,
Write to PC
Before Instruction
No
operation
No
operation
No
operation
No
operation
PC
=
address (HERE)
After Instruction
If Zero
=
=
=
=
1;
HERE
CALL THERE, FAST
Example:
PC
If Zero
PC
address (Jump)
0;
address (HERE+2)
Before Instruction
PC
=
Address(HERE)
After Instruction
PC
TOS
WS
=
=
=
=
Address(THERE)
Address (HERE + 4)
WREG
BSRS
BSR
STATUSS = STATUS
DS30475A-page 276
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
CLRF
Clear f
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
Syntax:
Operands:
[label] CLRF f [,a]
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register. If ’a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ’a’ is 1, the Bank will be
selected as per the BSR value.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Decode
No
operation
Process
Data
No
operation
CLRF
FLAG_REG
CLRWDT
Example:
Example:
Before Instruction
Before Instruction
FLAG_REG
Z
=
=
0x5A
?
WDT counter
WDT postscaler
TO
=
=
=
=
?
?
?
?
After Instruction
PD
FLAG_REG
Z
=
=
0x00
0
After Instruction
WDT counter
WDT postscaler
TO
=
=
=
=
0x00
0
1
1
PD
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 277
PIC18CXX8
Compare f with WREG,
skip if f = WREG
CPFSEQ
COMF
Complement f
Syntax:
[ label ] CPFSEQ f [,a]
Syntax:
Operands:
[ label ] COMF f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (WREG),
skip if (f) = (WREG)
(unsigned comparison)
Operation:
(f) → dest
Status Affected:
Encoding:
N,Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ’f’ are com-
plemented. If ’d’ is 0 the result is
stored in W. If ’d’ is 1 the result is
stored back in register ’f’ (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
Description:
Compares the contents of data
memory location 'f' to the contents
of W by performing an unsigned
subtraction.
If 'f' = WREG, then the fetched
instruction is discarded and an NOP
is executed instead making this a
two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register ’f’
Process
Data
Write to
destination
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
COMF
REG
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ’f’
Process
Data
No
operation
REG
N
Z
=
=
=
0x13
?
?
If skip:
Q1
Q2
Q3
Q4
After Instruction
No
operation
No
operation
No
operation
No
operation
REG
WREG
N
=
=
=
=
0x13
0xEC
1
If skip and followed by 2-word instruction:
Z
0
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
CPFSEQ REG
Example:
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
WREG
=
=
=
HERE
?
?
REG
After Instruction
If REG
PC
If REG
PC
=
WREG;
Address (EQUAL)
WREG;
=
≠
=
Address (NEQUAL)
DS30475A-page 278
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Compare f with WREG,
skip if f > WREG
Compare f with WREG,
skip if f < WREG
CPFSGT
CPFSLT
Syntax:
[ label ] CPFSGT f [,a]
Syntax:
[ label ] CPFSLT f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) − (WREG),
Operation:
(f) – (WREG),
skip if (f) > (WREG)
(unsigned comparison)
skip if (f) < (WREG)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data
memory location ’f’ to the contents
of the WREG by performing an
unsigned subtraction.
Description:
Compares the contents of data
memory location 'f' to the contents
of W by performing an unsigned
subtraction.
If the contents of ’f’ are greater than
the contents of , then the fetched
instruction is discarded and a NOP
is executed instead making this a
two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
If the contents of 'f' are less than
the contents of WREG, then the
fetched instruction is discarded and
a NOPis executed instead making
this a two-cycle instruction. If ’a’ is
0, the Access Bank will be
selected. If ’a’ is 1, the Bank will be
selected as per the BSR value.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note:3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
No
operation
Decode
Read
register ’f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NLESS
LESS
CPFSLT REG
:
:
Example:
HERE
NGREATER
GREATER
CPFSGT REG
:
:
Example:
Before Instruction
PC
WREG
=
=
Address (HERE)
?
Before Instruction
PC
WREG
=
=
Address (HERE)
?
After Instruction
After Instruction
If REG
PC
If REG
PC
If REG
PC
If REG
PC
<
=
≥
=
WREG;
Address (LESS)
WREG;
>
=
≤
=
WREG;
Address (GREATER)
WREG;
Address (NLESS)
Address (NGREATER)
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 279
PIC18CXX8
DAW
Decimal Adjust WREG Register
DECF
Decrement f
Syntax:
[label] DAW
Syntax:
Operands:
[ label ] DECF f [ ,d [,a] ]
Operands:
Operation:
None
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
If [WREG<3:0> >9] or [DC = 1]
then
(WREG<3:0>) + 6 → W<3:0>;
Operation:
(f) – 1 → dest
else
Status Affected:
Encoding:
C,DC,N,OV,Z
(WREG<3:0>) → W<3:0>;
0000
01da
ffff
ffff
Description:
Decrement register 'f'. If 'd' is 0, the
result is stored in WREG. If 'd' is 1,
the result is stored back in register
'f' (default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
If [WREG<7:4> >9] or [C = 1] then
(WREG<7:4>) + 6 → WREG<7:4>;
else
(WREG<7:4>) → WREG<7:4>;
Status Affected:
Encoding:
C
0000
0000
0000
0111
Description:
DAW adjusts the eight bit value in
WREG resulting from the earlier
addition of two variables (each in
packed BCD format) and produces
a correct packed BCD result.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
1
Decode
Read
register ’f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
DECF
CNT
Example:
Q2
Q3
Q4
Decode
Read
register WREG
Process
Data
Write
WREG
Before Instruction
CNT
=
0x01
0
Z
=
DAW
Example1:
After Instruction
Before Instruction
CNT
=
0x00
1
WREG
=
=
=
0xA5
0
0
Z
=
C
DC
After Instruction
WREG
C
DC
=
=
=
0x05
1
0
Example 2:
Before Instruction
WREG
C
DC
=
=
=
0xCE
0
0
After Instruction
WREG
C
DC
=
=
=
0x34
1
0
DS30475A-page 280
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
DECFSZ
Syntax:
Decrement f, skip if 0
DCFSNZ
Syntax:
Decrement f, skip if not 0
[ label ] DECFSZ f [ ,d [,a] ]
[label] DCFSNZ f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result = 0
Operation:
(f) – 1 → dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register 'f' are dec-
remented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
Description:
The contents of register 'f' are dec-
remented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOPis executed
instead making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
If the result is not 0, the next
instruction, which is already
fetched, is discarded, and a NOPis
executed instead making it a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ’a’ is
1, the Bank will be selected as per
the BSR value.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
Decode
Read
register ’f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
DECFSZ
GOTO
CNT
LOOP
HERE
ZERO
NZERO
DCFSNZ TEMP
:
:
Example:
Example:
CONTINUE
Before Instruction
Before Instruction
TEMP
PC
=
Address (HERE)
=
?
After Instruction
After Instruction
TEMP
CNT
=
=
=
≠
=
CNT - 1
0;
Address (CONTINUE)
0;
=
=
=
≠
=
TEMP - 1,
0;
Address (ZERO)
0;
If CNT
If TEMP
PC
If TEMP
PC
PC
If CNT
PC
Address (HERE+2)
Address (NZERO)
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 281
PIC18CXX8
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
[ label ] GOTO k
0 ≤ k ≤ 1048575
k → PC<20:1>
None
Syntax:
Operands:
[ label ] INCF f [ ,d [,a] ]
Operands:
Operation:
Status Affected:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C,DC,N,OV,Z
1110
1111
1111
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional
Description:
The contents of register ’f’ are
incremented. If ’d’ is 0, the result is
placed in WREG. If ’d’ is 1, the
result is placed back in register ’f’
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
branch anywhere within entire 2M
byte memory range. The 20-bit
value ’k’ is loaded into PC<20:1>.
GOTOis always a two-cycle
instruction.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read literal
’k’<7:0>,
No
operation
Read literal
’k’<19:8>,
Write to PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
Read
register ’f’
Process
Data
Write to
destination
GOTO THERE
Example:
INCF
CNT
Example:
After Instruction
Before Instruction
PC
=
Address (THERE)
CNT
=
0xFF
Z
C
DC
=
=
=
0
?
?
After Instruction
CNT
Z
C
DC
=
=
=
=
0x00
1
1
1
DS30475A-page 282
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
INCFSZ
Syntax:
Increment f, skip if 0
INFSNZ
Syntax:
Increment f, skip if not 0
[ label ] INCFSZ f [ ,d [,a] ]
[label] INFSNZ f [, d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result = 0
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0011
11da
ffff
ffff
0100
10da
ffff
ffff
Description:
The contents of register ’f’ are
incremented. If ’d’ is 0, the result is
placed in WREG. If ’d’ is 1, the
result is placed back in register ’f’
(default).
Description:
The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOPis executed
instead making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
If the result is not 0, the next
instruction, which is already
fetched, is discarded, and a NOPis
executed instead making it a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
Decode
Read
register ’f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
NZERO
ZERO
INCFSZ
:
:
CNT
HERE
ZERO
NZERO
INFSNZ REG
Example:
Example:
Before Instruction
Before Instruction
PC
=
Address (HERE)
PC
=
Address (HERE)
After Instruction
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
≠
=
CNT + 1
0;
Address(ZERO)
0;
Address(NZERO)
REG
If REG
PC
If REG
PC
=
≠
=
=
=
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 283
PIC18CXX8
IORLW
Inclusive OR literal with WREG
IORWF
Inclusive OR WREG with f
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
[ label ] IORWF f [ ,d [,a] ]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(WREG) .OR. k → WREG
N,Z
Operation:
(WREG) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N,Z
The contents of WREG are OR’ed
with the eight bit literal 'k'. The
result is placed in WREG.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register 'f'. If 'd'
is 0, the result is placed in WREG.
If 'd' is 1, the result is placed back
in register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write to W
Words:
Cycles:
1
1
IORLW
0x35
Example:
Before Instruction
Q Cycle Activity:
Q1
WREG
=
=
=
0x9A
?
?
Q2
Q3
Q4
N
Z
Decode
Read
register ’f’
Process
Data
Write to
destination
After Instruction
WREG
N
Z
=
=
=
0xBF
1
0
IORWF RESULT, W
Example:
Before Instruction
RESULT =
0x13
0x91
?
WREG
=
=
=
N
Z
?
After Instruction
RESULT =
0x13
0x93
1
WREG
=
=
=
N
Z
0
DS30475A-page 284
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
LFSR
Load FSR
MOVF
Move f
Syntax:
Operands:
[ label ] LFSR f,k
Syntax:
Operands:
[ label ] MOVF f [ ,d [,a] ]
0 ≤ f ≤ 2
0 ≤ k ≤ 4095
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
k → FSRf
Operation:
f → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N,Z
1110
1111
1110
0000
00ff
k kkk
11
kkkk
k kkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ’k’ is loaded into
the file select register pointed to
by ’f’
Description:
The contents of register ’f’ is moved
to a destination dependent upon
the status of ’d’. If 'd' is 0, the result
is placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default). Location 'f' can be any-
where in the 256 byte Bank. If ’a’ is
0, the Access Bank will be
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
Decode
Read literal
’k’ MSB
Process
Data
Write
literal ’k’
MSB to
FSRfH
Words:
Cycles:
1
1
Decode
Read literal
’k’ LSB
Process
Data
Write literal
’k’ to FSRfL
Q Cycle Activity:
Q1
LFSR FSR2, 0x3AB
Example:
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write W
After Instruction
FSR2H
=
=
0x03
0xAB
FSR2L
MOVF
REG, W
Example:
Before Instruction
REG
WREG
N
=
=
=
=
0x22
0xFF
?
Z
?
After Instruction
REG
WREG
N
=
=
=
=
0x22
0x22
0
Z
0
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 285
PIC18CXX8
MOVFF
Move f to f
MOVLB
Move literal to low nibble in BSR
Syntax:
[label] MOVFF fs,fd
Syntax:
[ label ] MOVLB k
0 ≤ k ≤ 255
k → BSR
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ fs ≤ 4095
0 ≤ fd ≤ 4095
None
Operation:
(fs) → fd
0000
0001
kkkk
kkkk
Status Affected:
None
The 8-bit literal ’k’ is loaded into
the Bank Select Register (BSR).
Encoding:
1st word (source)
2nd word (destin.)
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Words:
Cycles:
1
1
Description:
The contents of source register ’fs’
are moved to destination register
’fd’. Location of source ’fs’ can be
anywhere in the 4096 byte data
space (000h to FFFh), and location
of destination ’fd’ can also be any-
where from 000h to FFFh.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
’k’
Process
Data
Write
literal ’k’ to
BSR
Either source or destination can be
WREG (a useful special situation).
MOVLB
0x05
Example:
Before Instruction
MOVFFis particularly useful for
transferring a data memory location
to a peripheral register (such as the
transmit buffer or an I/O port).
BSR register
=
=
0x02
After Instruction
BSR register
0x05
The MOVFFinstruction cannot use
the PCL, TOSU, TOSH or TOSL as
the destination register.
Words:
Cycles:
2
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ’f’
(dest)
No dummy
read
MOVFF
REG1, REG2
Example:
Before Instruction
REG1
=
=
0x33
0x11
REG2
After Instruction
REG1
=
=
0x33,
0x33
REG2
DS30475A-page 286
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
MOVLW
Move literal to WREG
[ label ] MOVLW k
0 ≤ k ≤ 255
MOVWF
Syntax:
Move WREG to f
Syntax:
[ label ] MOVWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
k → WREG
Operation:
(WREG) → f
None
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
The eight bit literal ’k’ is loaded into
WREG.
Description:
Move data from WREG to register
’f’. Location ’f’ can be anywhere in
the 256 byte Bank. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write to W
Words:
Cycles:
1
1
MOVLW
0x5A
Example:
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
WREG
=
0x5A
Decode
Read
register ’f’
Process
Data
Write
register ’f’
MOVWF
REG
Example:
Before Instruction
WREG
REG
=
=
0x4F
0xFF
After Instruction
WREG
REG
=
=
0x4F
0x4F
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 287
PIC18CXX8
MULLW
Multiply Literal with WREG
MULWF
Syntax:
Multiply WREG with f
Syntax:
[ label ] MULLW
0 ≤ k ≤ 255
k
[ label ] MULWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(WREG) x k → PRODH:PRODL
Operation:
(WREG) x (f) → PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
An unsigned multiplication is car-
ried out between the contents of
WREG and the 8-bit literal ’k’.
The 16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
Description:
An unsigned multiplication is car-
ried out between the contents of
WREG and the register file loca-
tion ’f’. The 16-bit result is stored
in the PRODH:PRODL register
pair. PRODH contains the high
byte.
WREG is unchanged.
None of the status flags are
affected.
Both WREG and ’f’ are
unchanged.
Note that neither overflow nor
carry is possible in this opera-
tion. A zero result is possible but
not detected.
None of the status flags are
affected.
Note that neither overflow nor
carry is possible in this opera-
tion. A zero result is possible but
not detected. If ’a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ’a’ is
1, the Bank will be selected as
per the BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write
registers
PRODH:
PRODL
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
MULLW
0xC4
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ’f’
Process
Data
Write
WREG
PRODH
PRODL
=
=
=
0xE2
registers
PRODH:
PRODL
?
?
After Instruction
WREG
=
=
=
0xE2
0xAD
0x08
MULWF
REG
Example:
PRODH
PRODL
Before Instruction
WREG
REG
PRODH
PRODL
=
=
=
=
0xC4
0xB5
?
?
After Instruction
WREG
=
=
=
=
0xC4
0xB5
0x8A
0x94
REG
PRODH
PRODL
DS30475A-page 288
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
NEGF
Negate f
NOP
No Operation
Syntax:
Operands:
[label] NEGF f [,a]
Syntax:
[ label ] NOP
None
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
No operation
None
Operation:
( f ) + 1 → f
Status Affected:
Encoding:
N,OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Words:
No operation.
Description:
Location ’f’ is negated using two’s
complement. The result is placed in
the data memory location 'f'. If ’a’ is
0, the Access Bank will be
1
1
Cycles:
Q Cycle Activity:
Q1
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
Words:
Cycles:
1
1
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write
register ’f’
NEGF
REG
Example:
Before Instruction
REG
N
OV
C
DC
Z
=
=
=
=
=
=
0011 1010[0x3A]
?
?
?
?
?
After Instruction
REG
N
OV
C
DC
Z
=
=
=
=
=
=
1100 0110[0xC6]
1
0
0
0
0
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 289
PIC18CXX8
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
[ label ] PUSH
None
Syntax:
[ label ] POP
None
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
(TOS) → bit bucket
None
(PC+2) → TOS
None
0000
0000
0000
0110
0000
0000
0000
0101
The TOS value is pulled off the
return stack and is discarded. The
TOS value then becomes the previ-
ous value that was pushed onto the
return stack.
The PC+2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implement-
ing a software stack by modifying
TOS, and then push it onto the
return stack.
This instruction is provided to
enable the user to properly manage
the return stack to incorporate a
software stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Push PC+2
onto return
stack
No
operation
No
operation
Q2
Q3
Q4
Decode
No
operation
Pop TOS
value
No
operation
PUSH
Example:
POP
GOTO
Example:
Before Instruction
NEW
TOS
=
=
00345Ah
000124h
PC
Before Instruction
TOS
=
=
0031A2h
014332h
Stack (1 level down)
After Instruction
PC
TOS
=
=
=
000126h
000126h
00345Ah
After Instruction
Stack (1 level down)
TOS
PC
=
=
014332h
NEW
DS30475A-page 290
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
RCALL
Relative Call
RESET
Reset
Syntax:
[ label ] RCALL
-1024 ≤ n ≤ 1023
(PC) + 2 → TOS,
n
Syntax:
[ label ] RESET
Operands:
Operation:
Operands:
Operation:
None
Reset all registers and flags that
are affected by a MCLR Reset.
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to
1K from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ’2n’ to the PC.
Since the PC will have incremented
to fetch the next instruction, the
new address will be PC+2+2n.
This instruction is a two-cycle
instruction.
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
reset
No
operation
No
operation
Words:
Cycles:
1
2
RESET
Example:
After Instruction
Registers =
Reset Value
Reset Value
Q Cycle Activity:
Q1
Flags*
=
Q2
Q3
Q4
Decode
Read literal
’n’
Process
Data
Write to PC
Push PC to
stack
No
No
No
No
operation
operation
operation
operation
HERE
RCALL
Jump
Example:
Before Instruction
PC
=
Address(HERE)
After Instruction
PC
=
Address(Jump)
TOS =
Address (HERE+2)
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 291
PIC18CXX8
RETFIE
Return from Interrupt
RETLW
Return Literal to WREG
[ label ] RETLW k
0 ≤ k ≤ 255
Syntax:
[ label ] RETFIE [s]
s ∈ [0,1]
Syntax:
Operands:
Operation:
Operands:
Operation:
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged.
Description:
W is loaded with the eight bit literal
'k'. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
Status Affected:
Encoding:
None
0000
0000
0001
000s
Description:
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS)
is loaded into the PC. Interrupts
are enabled by setting the either
the high or low priority global
interrupt enable bit. If ’s’ = 1, the
contents of the shadow registers
WS, STATUSS and BSRS are
loaded into their corresponding
registers, WREG, STATUS and
BSR. If ’s’ = 0, no update of
these registers occurs (default).
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Pop PC from
stack, write
to W
No
No
No
No
operation
operation
operation
operation
Words:
Cycles:
1
2
Example:
CALL TABLE ; WREG contains table
Q Cycle Activity:
Q1
;
;
;
offset value
WREG now has
table value
Q2
Q3
Q4
Decode
No
operation
No
operation
Pop PC from
stack
:
TABLE
Set GIEH or
GIEL
ADDWF PCL
; WREG = offset
; Begin table
;
RETLW k0
RETLW k1
:
No
operation
No
operation
No
operation
No
operation
:
RETFIE
1
Example:
RETLW kn
; End of table
After Interrupt
PC
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
Before Instruction
WREG
BSR
STATUS
GIE/GIEH, PEIE/GIEL
WREG
=
0x07
After Instruction
WREG
=
value of kn
DS30475A-page 292
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
RETURN
Syntax:
Return from Subroutine
[ label ] RETURN [s]
s ∈ [0,1]
RLCF
Rotate Left f through Carry
Syntax:
Operands:
[ label ] RLCF f [ ,d [,a] ]
Operands:
Operation:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(TOS) → PC,
if s = 1
(WS) → W,
Operation:
(f<n>) → dest<n+1>,
(f<7>) → C,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
(C) → dest<0>
Status Affected:
Encoding:
C,N,Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the
result is stored back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
Description:
Return from subroutine. The
stack is popped and the top of the
stack (TOS) is loaded into the
program counter. If ’s’ = 1, the
contents of the shadow registers
WS, STATUSS and BSRS are
loaded into their corresponding
registers, WREG, STATUS and
BSR. If ’s’ = 0, no update of
these registers occurs (default).
register f
C
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
No
Process
Data
Pop PC from
stack
operation
Decode
Read
Process
Write to
No
No
No
No
register ’f’
Data
destination
operation
operation
operation
operation
RLCF
REG, W
Example:
Before Instruction
RETURN
Example:
REG
=
1110 0110
C
N
Z
=
=
=
0
?
?
After Call
PC
=
TOS
RETURN FAST
After Instruction
Before Instruction
REG
WREG
C
N
Z
=
=
=
=
=
1110 0110
1100 1100
1
1
0
WRG
STATUS =
BSR
=
0x04
0x00
0x00
=
After Instruction
WREG
STATUS =
BSR
PC
=
0x04
0x00
0x00
TOS
=
=
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 293
PIC18CXX8
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ] RLNCF f [ ,d [,a] ]
Syntax:
Operands:
[ label ] RRCF f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n+1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n-1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N,Z
Status Affected:
Encoding:
C,N,Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ’f’ are
rotated one bit to the left. If ’d’ is 0
the result is placed in WREG. If ’d’
is 1, the result is stored back in reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Description:
The contents of register 'f' are
rotated one bit to the right through
the Carry Flag. If 'd' is 0, the result
is placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
register f
Words:
Cycles:
1
1
register f
C
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ’f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
RLNCF
REG
Example:
Before Instruction
RRCF
REG, W
Example:
REG
=
1010 1011
N
Z
=
=
?
?
Before Instruction
REG
=
1110 0110
C
N
Z
=
=
=
0
?
?
After Instruction
REG
N
Z
=
=
=
0101 0111
0
0
After Instruction
REG
WREG
C
N
Z
=
=
=
=
=
1110 0110
0111 0011
0
0
0
DS30475A-page 294
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
RRNCF
Syntax:
Rotate Right f (no carry)
SETF
Set f
[ label ] RRNCF f [ ,d [,a] ]
Syntax:
Operands:
[label] SETF f [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
Operation:
(f<n>) → dest<n-1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N,Z
Description:
The contents of the specified regis-
ter are set to FFh. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
0100
00da
ffff
ffff
Description:
The contents of register ’f’ are
rotated one bit to the right. If ’d’ is 0,
the result is placed in WREG. If ’d’
is 1, the result is placed back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Words:
Cycles:
1
1
SETF
REG
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
=
0x5A
0xFF
Q2
Q3
Q4
After Instruction
REG
Decode
Read
register ’f’
Process
Data
Write to
destination
=
RRNCF
REG
Example 1:
Before Instruction
REG
N
Z
=
=
=
1101 0111
?
?
After Instruction
REG
N
Z
=
=
=
1110 1011
1
0
RRNCF
REG, 0, 0
Example 2:
Before Instruction
WREG
REG
N
=
=
=
=
?
1101 0111
?
?
Z
After Instruction
WREG
REG
N
=
=
=
=
1110 1011
1101 0111
1
0
Z
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 295
PIC18CXX8
SLEEP
SUBFWB
Syntax:
Enter SLEEP mode
[ label ] SLEEP
None
Subtract f from WREG with borrow
Syntax:
[ label ] SUBFWB f [ ,d [,a] ]
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
00h → WDT,
0 → WDT postscaler,
1 → TO,
Operation:
(WREG) – (f) – (C) → dest
0 → PD
Status Affected:
Encoding:
N,OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register 'f' and carry flag
(borrow) from WREG (2’s comple-
ment method). If 'd' is 0, the result
is stored in WREG. If 'd' is 1, the
result is stored in register 'f'
(default) . If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
Description:
The power-down status bit (PD) is
cleared. The time-out status bit
(TO) is set. Watchdog Timer and
its postscaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
No
operation
Process
Data
Go to
sleep
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
SLEEP
Example:
Before Instruction
TO
=
?
PD
=
?
After Instruction
TO
=
1 †
PD
=
0
† If WDT causes wake-up, this bit is cleared.
DS30475A-page 296
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
SUBFWB (Cont.)
SUBLW
Subtract WREG from literal
[ label ] SUBLW k
0 ≤ k ≤ 255
SUBFWB
REG
Example 1:
Syntax:
Before Instruction
Operands:
Operation:
Status Affected:
Encoding:
Description:
REG
WREG
C
=
=
=
3
2
1
k – (WREG) → WREG
N,OV, C, DC, Z
After Instruction
0000
1000
kkkk
kkkk
REG
WREG
C
Z
N
=
=
=
=
=
0xFF
WREG is subtracted from the
eight bit literal 'k'. The result is
placed in WREG.
2
0
0
1
; result is negative
Words:
Cycles:
1
1
SUBFWB
REG
Example 2:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
REG
WREG
C
=
=
=
2
5
1
Decode
Read
literal ’k’
Process
Data
Write to W
After Instruction
SUBLW 0x02
Example 1:
REG
=
=
=
=
=
2
3
1
0
0
Before Instruction
WREG
WREG
C
=
=
1
?
C
Z
N
; result is positive
After Instruction
WREG
C
Z
=
=
=
=
1
SUBFWB
REG
Example 3:
1
0
0
; result is positive
Before Instruction
REG
WREG
C
=
=
=
1
2
0
N
SUBLW 0x02
Example 2:
After Instruction
Before Instruction
REG
WREG
C
Z
N
=
=
=
=
=
0
2
1
1
0
WREG
C
=
=
2
?
; result is zero
After Instruction
WREG
C
Z
=
=
=
=
0
1
1
0
; result is zero
N
SUBLW 0x02
Example 3:
Before Instruction
WREG
C
=
=
3
?
After Instruction
WREG
C
Z
=
=
=
=
0xFF ; (2’s complement)
0
0
1
; result is negative
N
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 297
PIC18CXX8
SUBWF
Subtract WREG from f
SUBWF
Subtract WREG from f (cont’d)
SUBWF
REG
Syntax:
[ label ] SUBWF f [ ,d [,a] ]
Example 1:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Before Instruction
REG
WREG
C
=
=
=
3
2
?
Operation:
(f) – (WREG) → dest
After Instruction
Status Affected:
Encoding:
N,OV, C, DC, Z
REG
WREG
C
Z
N
=
=
=
=
=
1
2
1
0
0
0101
11da
ffff
ffff
; result is positive
Description:
Subtract WREG from register 'f'
(2’s complement method). If 'd' is
0, the result is stored in WREG. If
'd' is 1, the result is stored back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ’a’ is
1, the Bank will be selected as per
the BSR value.
SUBWF
REG, W
Example 2:
Before Instruction
REG
WREG
C
=
=
=
2
2
?
After Instruction
REG
WREG
C
Z
N
=
=
=
=
=
2
0
1
1
0
Words:
Cycles:
1
1
; result is zero
Q Cycle Activity:
Q1
Q2
Q3
Q4
SUBWF
REG
Example 3:
Decode
Read
register ’f’
Process
Data
Write to
destination
Before Instruction
REG
WREG
C
=
=
=
1
2
?
After Instruction
REG
WREG
C
Z
N
=
=
=
=
=
0xFF ;(2’s complement)
2
0
0
1
; result is negative
DS30475A-page 298
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
Subtract WREG from f with
Borrow
Subtract WREG from f with
Borrow (cont’d)
SUBWFB
Syntax:
SUBWFB
SUBWFB REG
[ label ]
Example 1:
SUBWFB f [ ,d [,a] ]
Before Instruction
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
REG
=
=
=
0x19
0x0D
1
(0001 1001)
(0000 1101)
WREG
C
Operation:
(f) – (WREG) – (C) → dest
After Instruction
Status Affected:
Encoding:
N,OV, C, DC, Z
REG
WREG
C
Z
N
=
=
=
=
=
0x0C
0x0D
1
0
0
(0000 1011)
(0000 1101)
0101
10da
ffff
ffff
Description:
Subtract WREG and the carry flag
(borrow) from register 'f' (2’s com-
plement method). If 'd' is 0, the
result is stored in WREG. If 'd' is
1, the result is stored back in reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ’a’ is
1, the Bank will be selected as per
the BSR value.
; result is positive
Example 2:
Before Instruction
SUBWFB REG, W
REG
WREG
C
=
=
=
0x1B
0x1A
0
(0001 1011)
(0001 1010)
After Instruction
REG
WREG
C
Z
N
=
=
=
=
=
0x1B
0x00
1
1
0
(0001 1011)
Words:
Cycles:
1
1
; result is zero
Q Cycle Activity:
Q1
Q2
Q3
Q4
Example 3:
Before Instruction
SUBWFB REG
Decode
Read
register ’f’
Process
Data
Write to
destination
REG
WREG
C
=
=
=
0x03
0x0E
1
(0000 0011)
(0000 1101)
After Instruction
REG
WREG
C
Z
N
=
=
=
=
=
0xF5
0x0E
0
0
1
(1111 0100) [2’s comp]
(0000 1101)
; result is negative
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 299
PIC18CXX8
SWAPF
Syntax:
Swap nibbles in f
[ label ] SWAPF f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected:
Encoding:
None
0011
10da
ffff
ffff
Description:
The upper and lower nibbles of reg-
ister ’f’ are exchanged. If ’d’ is 0, the
result is placed in WREG. If ’d’ is 1,
the result is placed in register ’f’
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
SWAPF
REG
Example:
Before Instruction
REG
=
0x53
0x35
After Instruction
REG
=
DS30475A-page 300
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TBLRD
Table Read
TBLRD
Table Read (cont’d)
TBLRD *+ ;
Syntax:
[ label ] TBLRD ( *; *+; *-; +*)
Example 1:
Operands:
Operation:
None
Before Instruction
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A356
0x34
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT;
TBLPTR - No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) +1 → TBLPTR;
if TBLRD *-,
After Instruction
TABLAT
TBLPTR
=
=
0x34
0x00A357
TBLRD +* ;
Example 2:
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) -1 → TBLPTR;
if TBLRD +*,
(TBLPTR) +1 → TBLPTR;
(Prog Mem (TBLPTR)) → TABLAT;
Before Instruction
TABLAT
=
=
=
=
0xAA
0x01A357
0x12
TBLPTR
MEMORY(0x01A357)
MEMORY(0x01A358)
0x34
After Instruction
Status Affected: None
TABLAT
TBLPTR
=
=
0x34
0x01A358
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Encoding:
Description:
This instruction is used to read the
contents of Program Memory (P.M.).
To address the program memory, a
pointer called Table Pointer (TBLPTR)
is used.
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2 Mbyte address range.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLRDinstruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
No
No
No
No
operation
operation
(Read
operation
operation
(Write
Program
Memory)
TABLAT)
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 301
PIC18CXX8
TBLWT
Table Write
TBLWT
Table Write (Continued)
TBLWT *+;
Syntax:
[ label ]
TBLWT ( *; *+; *-; +*)
Example 1:
Operands:
Operation:
None
Before Instruction
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A356
0xFF
if TBLWT*,
(TABLAT) → Prog Mem (TBLPTR) or
Holding Register;
TBLPTR - No Change;
if TBLWT*+,
(TABLAT) → Prog Mem (TBLPTR) or
Holding Register;
(TBLPTR) +1 → TBLPTR;
if TBLWT*-,
(TABLAT) → Prog Mem (TBLPTR) or
Holding Register;
(TBLPTR) -1 → TBLPTR;
if TBLWT+*,
After Instructions (table write completion)
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A357
0x55
TBLWT +*;
Example 2:
Before Instruction
TABLAT
TBLPTR
MEMORY(0x01389A)
MEMORY(0x01389B)
=
=
=
=
0x34
0x01389A
0xFF
0xFF
(TBLPTR) +1 → TBLPTR;
(TABLAT) → Prog Mem (TBLPTR) or
Holding Register;
After Instruction (table write completion)
TABLAT
=
=
=
=
0x34
TBLPTR
MEMORY(0x01389A)
MEMORY(0x01389B)
0x01389B
0xFF
0x34
Status Affected:
Encoding:
None
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description:
This instruction is used to program the
contents of Program Memory (P.M.).
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2 MBtye address
range. The LSb of the TBLPTR
selects which byte of the program
memory location to access.
TBLPTR[0] = 0:Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1:Most Significant
Byte of Program
Memory Word
The TBLWTinstruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
Cycles:
1
2 (many if long write is to on-chip
EPROM program memory)
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
Decode
No
operation operation
operation
No
No No
No
operation
operation operation
(Read
TABLAT)
operation
(Write to Holding
Register or Memory)
DS30475A-page 302
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TSTFSZ
Syntax:
Test f, skip if 0
XORLW
Exclusive OR literal with WREG
[ label ] TSTFSZ f [,a]
Syntax:
[ label ]
XORLW k
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(WREG) .XOR. k → WREG
Operation:
skip if f = 0
None
Status Affected:
Encoding:
N,Z
Status Affected:
Encoding:
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
Description:
The contents of WREG are
XOR’ed with the 8-bit literal 'k'.
The result is placed in WREG.
Description:
If ’f’ = 0, the next instruction,
fetched during the current instruc-
tion execution, is discarded and a
NOPis executed making this a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write to
WREG
Words:
Cycles:
1
1(2)
Example:
XORLW 0xAF
Note: 3 cycles if skip and followed
by a 2-word instruction
Before Instruction
WREG
N
Z
=
=
=
0xB5
?
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ’f’
Process
Data
No
operation
WREG
=
=
=
0x1A
0
0
N
Z
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NZERO
ZERO
TSTFSZ CNT
:
:
Example:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
=
=
≠
=
0x00,
Address (ZERO)
0x00,
PC
If CNT
PC
Address (NZERO)
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 303
PIC18CXX8
XORWF
Syntax:
Exclusive OR WREG with f
[ label ] XORWF f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(WREG) .XOR. (f) → dest
Status Affected:
Encoding:
N,Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of
WREG with register ’f’. If ’d’ is 0, the
result is stored in WREG. If ’d’ is 1,
the result is stored back in the reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
Example:
XORWF
REG
Before Instruction
REG
WREG
N
=
0xAF
0xB5
?
=
=
=
Z
?
After Instruction
REG
WREG
N
=
=
=
=
0x1A
0xB5
0
Z
0
DS30475A-page 304
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
The MPLAB IDE allows you to:
24.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
full range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- object code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Linker/MPLIBTM Librarian
• Simulators
The ability to use MPLAB IDE with Microchip’s MPLAB
SIM simulator, allows a consistent platform and the
ability to easily switch from the cost effective simulator
to the full featured emulator with minimal retraining.
- MPLAB SIM Software Simulator
• Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
24.2
MPASM Assembler
The MPASM assembler is a full featured universal
macro assembler for all PICmicro MCU’s. It can pro-
duce absolute code directly in the form of HEX files for
device programmers, or it can generate relocatable
objects for the MPLINK object linker.
- MPLAB ICD for PIC16F877
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
The MPASM assembler has a command line interface
and a Windows shell and can be used as a stand-alone
application on a Windows 3.x, or greater, system. The
MPASM assembler generates relocatable object files,
Intel® standard HEX files, MAP files to detail memory
usage and symbol reference, an absolute LST file,
which contains source lines and generated machine
code, and a COD file for debugging.
Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
24.1
MPLAB Integrated Development
Environment Software
• MPASM assembler and MPLINK object linker are
integrated into MPLAB IDE projects.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application which contains:
• MPASM assembler allows user defined macros to
be created for streamlined assembly.
• MPASM assembler allows conditional assembly
for multi-purpose source files.
• Multiple functionality
- editor
• MPASM assembler directives allow complete
control over the assembly process.
- simulator
24.3
MPLAB C17 and MPLAB C18
C Compilers
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other compilers.
• On-line help
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 305
PIC18CXX8
24.4
MPLINK Linker/MPLIB Librarian
24.6
MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker is a relocatable linker for the
MPASM assembler and the MPLAB C17 and MPLAB
C18 C compilers. It can link relocatable objects from
assembly or C source files, along with pre-compiled
libraries, using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editing, “make” and download and source
debugging from a single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB ICE
in-circuit emulator allows expansion to support new
PICmicro microcontrollers.
The MPLINK object linker features include:
• MPLINK object linker works with MPASM assem-
bler and MPLAB C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows 3.x/95/98 environment were cho-
sen to best make these features available to you, the
end user.
• MPLINK object linker allows all memory areas to
be defined as sections to provide link-time
flexibility.
The MPLIB object librarian features include:
• MPLIB object librarian makes linking easier
because single libraries can be included instead
of many smaller files.
The MPLAB ICE in-circuit emulator is available in two
versions: MPLAB ICE 1000 and MPLAB ICE 2000.
The MPLAB ICE 1000 is a basic, low cost emulator
system with simple trace capabilities. The MPLAB ICE
2000 is a full featured emulator system with enhanced
trace, trigger and data monitoring features. Both sys-
tems use the same processor modules and will operate
across the full operating speed range of the PICmicro
MCU.
• MPLIB object librarian helps keep code maintain-
able by grouping related modules together.
• MPLIB object librarian commands allow libraries
to be created and modules to be added, listed,
replaced, deleted or extracted.
24.5
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC host environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
24.7
ICEPIC In-Circuit Emulator
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and the MPLAB C18
C compilers and the MPASM assembler. The software
simulator offers the flexibility to develop and debug
code outside of the laboratory environment, making it
an excellent multi-project software development tool.
DS30475A-page 306
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
24.8
MPLAB ICD In-Circuit Debugger
24.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PIC16F877 and can be used to
develop this and other PICmicro microcontrollers from
the PIC16CXXX family. The MPLAB ICD utilizes the in-
circuit debugging capability built into the PIC16F87X.
This feature, along with Microchip’s In-Circuit Serial
ProgrammingTM protocol, offers cost effective in-circuit
FLASH programming and debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by watching variables, single-step-
ping and setting break points. Running at full speed
enables testing hardware in real-time. The MPLAB ICD
is also a programmer for the FLASH PIC16F87X family.
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
24.9
PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a full
featured programmer, capable of operating in stand-
alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
24.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for
maximum reliability. It has an LCD display for instruc-
tions and error messages, keys to enter commands
and a modular detachable socket assembly to support
various package types. In stand-alone mode, the PRO
MATE II device programmer can read, verify, or pro-
gram PICmicro devices. It can also set code-protect
bits in this mode.
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
Serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
24.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via one of the COM (RS-232) ports.
MPLAB Integrated Development Environment software
makes using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 307
PIC18CXX8
24.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
24.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports down-loading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is an LCD panel, with
4 commons and 12 segments, that is capable of dis-
playing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows 3.1 software for show-
ing the demultiplexed LCD signals on a PC. A simple
serial interface allows the user to construct a hardware
demultiplexer for the LCD signals.
24.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS
evaluation kit includes an LCD display to show chang-
ing codes, a decoder to decode transmissions and a
programming interface to program test transmitters.
DS30475A-page 308
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 24-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X
X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X
X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m e r u b g e g D s m e a r m o g P r r
s t K l a i E d v n a s d r a B o o m D e
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 309
PIC18CXX8
NOTES:
DS30475A-page 310
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
25.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2)......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports (combined) ....................................................................................................200 mA
Maximum current sourced by all ports (combined) ...............................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 311
PIC18CXX8
FIGURE 25-1: PIC18CXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
PIC18CXX8
4.2V
3.5 V
3.0 V
2.5 V
2.0 V
40 MHz
Frequency
FIGURE 25-2: PIC18LCXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0 V
5.5 V
5.0 V
PIC18LCXX8
4.5 V
4.2V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
40 MHz
6 MHz
Frequency
FMAX = (20.0 MHz/V) (VDDAPPMIN - 2.5 V) + 6 MHz
Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
DS30475A-page 312
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
25.1
DC Characteristics
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18LCXX8
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC18CXX8
(Industrial, Extended)
Param Symbol
No.
Characteristic/
Device
Min Typ Max Units
Conditions
D001
VDD
Supply Voltage
PIC18LCXX8 2.5
PIC18CXX8 4.2
—
—
—
—
5.5
5.5
—
V
V
V
V
HS, XT, RC and LP osc mode
D001
D002
D003
VDR
RAM Data Retention Voltage(1)
1.5
—
VPOR
VDD Start Voltage to ensure inter-
0.7
See section on Power-on Reset for
details
nal Power-on Reset signal
D004
D005
SVDD
VBOR
VDD Rise Rate to ensure internal
Power-on Reset signal
0.05
—
—
V/ms See section on Power-on Reset for
details
Brown-out Reset Voltage
PIC18LCXX8 BORV1:BORV0 = 11 2.5
BORV1:BORV0 = 10 2.7
—
—
—
—
—
—
—
2.66
2.86
4.46
4.78
N.A.
4.46
4.78
V
V
V
V
BORV1:BORV0 = 01 4.2
BORV1:BORV0 = 00 4.5
D005
PIC18CXX8 BORV1:BORV0 = 1x N.A.
BORV1:BORV0 = 01 4.2
V
V
V
Not in operating voltage range of device
BORV1:BORV0 = 00 4.5
Legend: Rows are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all fea-
tures that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 313
PIC18CXX8
25.1
DC Characteristics (cont’d)
Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C≤ TA ≤ +85°C for industrial
PIC18LCXX8
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC18CXX8
(Industrial, Extended)
Param Symbol
No.
Characteristic/
Device
Supply Current(2,4)
Min Typ Max Units
Conditions
D010 IDD
PIC18LCXX8
XT, RC, RCIO osc configurations
—
—
4
mA FOSC = 4 MHz, VDD = 2.5V
D010
PIC18CXX8
PIC18LCXX8
PIC18CXX8
PIC18LCXX8
PIC18CXX8
PIC18LCXX8
XT, RC, RCIO osc configurations
TBD mA FOSC = 4 MHz, VDD = 4.2V
—
—
—
—
D010A
D010A
D010C
D010C
D013
48
µA LP osc configuration
FOSC = 32 kHz, VDD = 2.5V
—
—
—
—
—
—
TBD µA LP osc configuration
FOSC = 32 kHz, VDD = 4.2V
mA EC, ECIO osc configurations,
45
45
Fosc = 40 MHz, VDD = 5.5V
mA EC, ECIO osc configurations,
Fosc = 40 MHz, VDD = 5.5V
HS osc configurations
—
—
—
—
—
—
TBD mA Fosc = 6 MHz, VDD = 2.5V
50
50
mA Fosc = 25 MHz, VDD = 5.5V
mA HS + PLL osc configuration
Fosc = 10 MHz, VDD = 5.5V
D013
PIC18CXX8
—
—
—
—
50
50
mA HS osc configurations
Fosc = 25 MHz, VDD = 5.5V
mA HS + PLL osc configuration
Fosc = 10 MHz, VDD = 5.5V
D014
D014
PIC18LCXX8
PIC18CXX8
Timer1 osc configuration
µA FOSC = 32 kHz, VDD = 2.5V
TBD µA FOSC = 32 kHz, VDD = 2.5V, 25°C
—
—
—
—
48
OSCB osc configuration
—
—
—
—
TBD µA FOSC = 32 kHz, VDD = 4.2V
TBD µA FOSC = 32 kHz, VDD = 4.2V, 25°C
Legend: Rows are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS, and
all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
DS30475A-page 314
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
25.1
DC Characteristics (cont’d)
Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C≤ TA ≤ +85°C for industrial
PIC18LCXX8
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC18CXX8
(Industrial, Extended)
Param Symbol
No.
Characteristic/
Device
Power-down Current(3)
Min Typ Max Units
Conditions
D020
IPD
PIC18LCXX8
—
—
—
<2.5
—
—
5
36
µA VDD = 2.5V, -40°C to +85°C
µA VDD = 5.5V, -40°C to +85°C
TBD µA VDD = 2.5V, 25°C
D020
PIC18CXX8
—
—
<1 TBD µA VDD = 4.2V, -40°C to +85°C
—
36
µA VDD = 5.5V, -40°C to +85°C
D020A
D021B
—
—
TBD µA VDD = 4.2V, 25°C
—
—
TBD TBD µA VDD = 4.2V, -40°C to +125°C
—
42
VDD = 5.5V, -40°C to +125°C
D022
∆IWDT
Module Differential Current
PIC18LCXX8
Watchdog Timer
—
—
—
—
—
—
12
25
µA VDD = 2.5V
µA VDD = 5.5V
TBD µA VDD = 2.5V, 25°C
25 µA VDD = 5.5V, -40°C to +85°C
TBD µA VDD = 5.5V, -40°C to +125°C
TBD µA VDD = 4.2V, 25°C
D022
PIC18CXX8
Watchdog Timer
—
—
—
—
—
—
D022A ∆IBOR
PIC18LCXX8
Brown-out Reset
—
—
—
—
50
TBD µA VDD = 2.5V, 25°C
50 µA VDD = 5.5V, -40°C to +85°C
TBD µA VDD = 5.5V, -40°C to +125°
TBD µA VDD = 4.2V, 25°C
µA VDD = 5.5V
D022A
PIC18CXX8
Brown-out Reset
—
—
—
—
—
—
D022B ∆ILVD
PIC18LCXX8
Low Voltage Detect
—
—
—
—
50
µA VDD = 2.5V
TBD µA VDD = 2.5V, 25°C
D022B
PIC18CXX8
Low Voltage Detect
—
—
—
—
—
—
TBD µA VDD = 4.2V, -40°C to +85°C
TBD µA VDD = 4.2V, -40°C to +125°C
TBD µA VDD = 4.2V, 25°C
D025
D025
∆IOSCB
PIC18LCXX8
Timer1 Oscillator
—
—
—
—
3
µA VDD = 2.5V
TBD µA VDD = 2.5V, 25°C
PIC18CXX8
Timer1 Oscillator
—
—
—
—
—
—
TBD µA VDD = 4.2V, -40°C to +85°C
TBD µA VDD = 4.2V, -40°C to +125°C
TBD µA VDD = 4.2V, 25°C
Legend: Rows are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS, and
all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 315
PIC18CXX8
25.2
DC Characteristics: PIC18CXX8 (Industrial, Extended) and PIC18LCXX8 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param Symbol
No.
Characteristic/
Device
Min
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports:
with TTL buffer
D030
D030A
D031
VSS
—
0.15VDD
0.8
V
V
VDD < 4.5V
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
RC3 and RC4
VSS
VSS
0.2VDD
0.3VDD
V
V
D032
MCLR
VSS
VSS
0.2VDD
0.3VDD
V
V
D032A
OSC1 (in XT, HS and LP modes)
and T1OSI
D033
OSC1(in RC mode)(1)
Input High Voltage
I/O ports:
VSS
0.2VDD
V
VIH
D040
with TTL buffer
0.25VDD +
0.8V
VDD
VDD
V
V
VDD < 4.5V
D040A
D041
2.0
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
RC3 and RC4
0.8VDD
0.7VDD
VDD
VDD
V
V
D042
MCLR
0.8VDD
0.7VDD
VDD
VDD
V
V
D042A
OSC1 (in XT, HS and LP modes)
and T1OSI
OSC1 (RC mode)(1)
D043
D050
D060
0.9VDD
VDD
TBD
1
V
V
VHYS
IIL
Hysteresis of Schmitt Trigger Inputs
TBD
—
Input Leakage Current(2,3)
I/O ports
µA VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061
D063
MCLR
—
—
5
5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD
OSC1
IPU
Weak Pull-up Current
PORTB weak pull-up current
D070 IPURB
50
400
µA VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
DS30475A-page 316
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
25.2
DC Characteristics: PIC18CXX8 (Industrial, Extended) and PIC18LCXX8 (Industrial) (cont’d)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param Symbol
No.
Characteristic/
Device
Min
Max
Units
Conditions
VOL
VOH
VOD
Output Low Voltage
D080
I/O ports
—
—
—
—
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
D080A
D083
OSC2/CLKO
(RC mode)
D083A
Output High Voltage(3)
D090
I/O ports
VDD - 0.7
VDD - 0.7
VDD - 0.7
VDD - 0.7
—
—
—
—
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D090A
D092
OSC2/CLKO
(RC mode)
D092A
Open-drain High Voltage
D150
—
7.5
V
RA4 pin
Capacitive Loading Specs on Output Pins
D101
D102
CIO
CB
All I/O pins and OSC2
(in RC mode)
—
50
pF To meet the AC Timing Specifications
pF In I2C mode
SCL, SDA
—
400
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 317
PIC18CXX8
FIGURE 25-3:
LOW VOLTAGE DETECT CHARACTERISTICS
VDD
(LVDIF can be
cleared in software)
VLVD
(LVDIF set by hardware)
LVDIF
TABLE 25-1: LOW VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
Characteristic/
Min
Max
Units
Conditions
D420
VLVD
LVDL<3:0> = 0100
2.5
2.7
2.8
3.0
3.3
3.5
3.6
3.8
4.0
4.2
4.5
2.66
2.86
2.98
3.2
3.52
3.72
3.84
4.04
4.26
4.46
4.78
V
V
V
V
V
V
V
V
V
V
V
LVD Voltage
LVDL<3:0> = 0101
LVDL<3:0> = 0110
LVDL<3:0> = 0111
LVDL<3:0> = 1000
LVDL<3:0> = 1001
LVDL<3:0> = 1010
LVDL<3:0> = 1011
LVDL<3:0> = 1100
LVDL<3:0> = 1101
LVDL<3:0> = 1110
DS30475A-page 318
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 25-2: EPROM PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +40°C
DC CHARACTERISTICS
Param.
No.
Sym
Characteristic
Min
Max Units
Conditions
Internal Program Memory Programming Specs (Note 1)
D110
VPP
Voltage on MCLR/VPP pin
12.75
4.75
13.25
5.25
V
V
(Note 2)
D111
VDDP Supply voltage during
programming
D112
D113
IPP
Current into MCLR/VPP pin
—
—
50
30
mA
mA
IDDP
Supply current during
programming
D114
D115
TPROG Programming pulse width
100
1000
µs Terminated via internal/external
interrupt or a RESET
TERASE EPROM erase time
Device operation ≤ 3V
Device operation ≥ 3V
4
TBD
—
—
hrs
hrs
Note 1: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC18CXX8 Program-
ming Specifications (Literature number DS39028).
2: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 319
PIC18CXX8
25.3
AC (Timing) Characteristics
25.3.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created fol-
lowing one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKO
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data-in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
DS30475A-page 320
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
25.3.2 TIMING CONDITIONS
The temperature and voltages specified in Table 25-3
apply to all timing specifications, unless otherwise
noted. Figure 25-4 specifies the load conditions for the
timing specifications.
TABLE 25-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
AC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 25.1.
LC parts operate for industrial temperatures only.
FIGURE 25-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 Load condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports
VSS
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 321
PIC18CXX8
25.3.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 25-5: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
3
4
2
CLKOUT
TABLE 25-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Param. No. Symbol
1A Fosc
Characteristic
Min
Max
Units
Conditions
External CLKIN
DC
DC
4
DC
DC
40
40
10
40
40
MHz XT osc
MHz HS osc
MHz HS + PLL osc
kHz LP osc
MHz EC
Frequency(1)
Oscillator Frequency(1)
DC
0.1
4
4
5
4
4
25
10
200
MHz RC osc
MHz XT osc
MHz HS osc
MHz HS + PLL osc
kHz LP osc mode
1
Tosc
External CLKIN Period(1)
Oscillator Period(1)
250
40
100
5
—
—
—
—
—
ns
ns
ns
µs
ns
XT and RC osc
HS osc
HS + PLL osc
LP osc
5
EC
250
250
100
40
—
ns
ns
ns
ns
µs
RC osc
XT osc
HS osc
HS + PLL osc
LP osc
10,000
10,000
100
5
—
2
3
TCY
TosL,
TosH
Instruction Cycle Time(1)
External Clock in (OSC1)
High or Low Time
100
30
2.5
10
—
—
—
—
ns
ns
ns
µs
ns
ns
ns
TCY = 4/FOSC
XT osc
LP osc
HS osc
XT osc
LP osc
—
4
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
20
50
7.5
—
—
HS osc
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "Min." values with an external
clock applied to the OSC1/CLKI pin. When an external clock input is used, the "Max." cycle time limit is "DC"
(no clock) for all devices.
DS30475A-page 322
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 25-5: PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
7
TPLL
PLL Start-up Time
(Lock Time)
—
2
ms
%
∆CLK
CLKOUT Stability (Jitter) using PLL
-2
+2
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 323
PIC18CXX8
FIGURE 25-6: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
12
19
18
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-6: CLKOUT AND I/O TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
(1)
10
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
75
75
35
35
—
—
—
50
—
—
200
200
100
100
ns
(1)
11
—
ns
(1)
12
13
14
15
16
17
18
18A
TckR
CLKOUT rise time
—
ns
(1)
TckF
CLKOUT fall time
—
ns
(1)
TckL2ioV CLKOUT ↓ to Port out valid
—
0.5TCY + 20 ns
(1)
(1)
TioV2ckH Port in valid before CLKOUT ↑
TckH2ioI Port in hold after CLKOUT ↑
TosH2ioV OSC1↑ (Q1 cycle) to Port out valid
TosH2ioI OSC1↑ (Q2 cycle) to PIC18CXX8
0.25TCY + 25
—
—
ns
ns
ns
ns
ns
0
—
150
—
100
200
Port input invalid
(I/O in hold time)
PIC18LCXX8
—
19
TioV2osH Port input valid to OSC1↑
0
—
—
ns
(I/O in setup time)
20
TioR
TioF
Port output rise time
Port output fall time
INT pin high or low time
PIC18CXX8
PIC18LCXX8
PIC18CXX8
PIC18LCXX8
—
—
10
—
10
—
—
—
—
25
60
25
60
—
—
—
ns
ns
ns
ns
ns
ns
ns
20A
21
—
21A
22††
23††
24††
—
TINP
TCY
TCY
20
TRBP
TRCP
RB7:RB4 change INT high or low time
RC7:RC4 change INT high or low time
††These parameters are asynchronous events, not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKO pin output is 4 x TOSC.
DS30475A-page 324
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 25-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 25-4 for load conditions.
FIGURE 25-8: BROWN-OUT RESET TIMING
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal Reference Voltage
Internal Reference Voltage stable
36
TABLE 25-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TmcL
TWDT
MCLR Pulse Width (low)
2
7
—
—
µs
31
Watchdog Timer Time-out Period
(No Prescaler)
18
33
ms
32
33
34
TOST
TPWRT
TIOZ
Oscillation Start-up Timer Period
Power up Timer Period
1024TOSC
—
72
2
1024TOSC
132
—
ms
µs
TOSC = OSC1 period
28
—
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
—
35
36
TBOR
Brown-out Reset Pulse Width
200
—
—
—
µs
µs
VDD ≤ BVDD (See
D005)
TIVRST
Time for Internal Reference
Voltage to become stable
20
50
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 325
PIC18CXX8
FIGURE 25-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units Conditions
No.
40
Tt0H
T0CKI High Pulse Width No Prescaler
With Prescaler
0.5TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
Tt0L
Tt0P
T0CKI Low Pulse Width No Prescaler
With Prescaler
0.5TCY + 20
10
T0CKI Period
No Prescaler
TCY + 10
With Prescaler
Greater of:
20 nS or TCY + 40
N
ns N = prescale
value
(1, 2, 4,..., 256)
45
46
Tt1H
Tt1L
T1CKI Synchronous, no prescaler
0.5TCY + 20
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
High
Time
Synchronous,
with prescaler
PIC18CXX8
10
PIC18LCXX8
25
30
—
Asynchronous PIC18CXX8
PIC18LCXX8
—
50
—
T1CKI Synchronous, no prescaler
0.5TCY + 5
10
—
Low
Time
Synchronous,
with prescaler
PIC18CXX8
—
PIC18LCXX8
25
—
Asynchronous PIC18CXX8
PIC18LCXX8
30
—
TBD
TBD
—
47
48
Tt1P
Ft1
T1CKI Synchronous
Input
Period
Greater of:
20 nS or TCY + 40
N
ns N = prescale
value
(1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
T1CKI oscillator input frequency range
Tcke2tmrI Delay from external T1CKI clock edge to
timer increment
2Tosc
7Tosc
DS30475A-page 326
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 25-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-9: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
50
TccL
CCPx input low No Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
time
With
PIC18CXX8
10
Prescaler
PIC18LCXX8
20
0.5TCY + 20
10
51
TccH
CCPx input
high time
No Prescaler
With
PIC18CXX8
Prescaler
PIC18LCXX8
20
52
53
TccP
TccR
CCPx input period
3TCY + 40
N
N = prescale
value (1,4 or 16)
CCPx output fall time
PIC18CXX8
PIC18LCXX8
PIC18CXX8
PIC18LCXX8
—
—
—
—
25
45
25
45
ns
ns
ns
ns
54
TccF
CCPx output fall time
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 327
PIC18CXX8
FIGURE 25-11: PARALLEL SLAVE PORT TIMING (PIC18C658 AND PIC18C858)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18C658 AND PIC18C858)
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
62
TdtV2wrH Data-in valid before WR↑ or CS↑
20
25
—
—
ns
ns
(setup time)
Extended Temp range
63
64
TwrH2dtI
WR↑ or CS↑ to data-in invalid PIC18CXX8
(hold time)
20
35
—
—
ns
ns
PIC18LCXX8
TrdL2dtV RD↓ and CS↓ to data-out valid
—
—
80
90
ns
ns
Extended Temp range
65
66
TrdH2dtI
TibfINH
RD↑ or CS↓ to data-out invalid
Inhibit the IBF flag bit being cleared from
10
—
30
ns
ns
3TCY
WR↑ or CS↑
DS30475A-page 328
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 25-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
Bit6 - - - - - -1
Bit6 - - - -1
MSb
LSb
SDO
SDI
75, 76
MSb In
74
LSb In
73
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
Symbol
Characteristic
Min
Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
ns
71
TscH
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25TCY + 30
40
ns (Note 1)
TscL
SCK input low time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
ns
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock edge of
Byte2
1.5TCY + 40
100
—
—
ns (Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
ns
75
TdoR
SDO data output rise time
PIC18CXX8
—
—
—
—
—
—
—
—
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LCXX8
76
78
TdoF
TscR
SDO data output fall time
SCK output rise time
(Master mode)
PIC18CXX8
PIC18LCXX8
79
80
TscF
SCK output fall time (Master mode)
TscH2doV, SDO data output valid after
TscL2doV SCK edge
PIC18CXX8
PIC18LCXX8
Note 1: Requires the use of parameter # 73A.
2: Only if parameter #s 71A and 72A are used.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 329
PIC18CXX8
FIGURE 25-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
Bit6 - - - - - -1
Bit6 - - - -1
SDO
SDI
75, 76
MSb In
74
LSb In
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
Symbol
TscH
Characteristic
Min
Max Units Conditions
No.
71
SCK input high time
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
ns
(Slave mode)
71A
72
40
1.25TCY + 30
40
ns (Note 1)
TscL
SCK input low time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
ns
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock edge of
Byte2
1.5TCY + 40
100
—
—
ns (Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
ns
75
TdoR
SDO data output rise time
PIC18CXX8
—
—
25
45
25
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LCXX8
76
78
TdoF
TscR
SDO data output fall time
—
SCK output rise time
(Master mode)
PIC18CXX8
—
PIC18LCXX8
—
79
80
TscF
SCK output fall time (Master mode)
—
TscH2doV, SDO data output valid after
TscL2doV SCK edge
PIC18CXX8
—
PIC18LCXX8
—
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
Note 1: Requires the use of parameter # 73A.
2: Only if parameter #s 71A and 72A are used.
DS30475A-page 330
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 25-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
Bit6 - - - - - -1
77
75, 76
MSb In
74
Bit6 - - - -1
LSb In
73
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))
Parm.
Symbol
Characteristic
Min
Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
ns
71
TscH
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25TCY + 30
40
ns (Note 1)
TscL
SCK input low time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
ns
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40
—
—
ns (Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
ns
75
TdoR
SDO data output rise time
PIC18CXX8
—
25
45
25
50
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LCXX8
76
77
78
TdoF
SDO data output fall time
—
10
—
TssH2doZ SS↑ to SDO output hi-impedance
TscR
SCK output rise time
(Master mode)
PIC18CXX8
PIC18LCXX8
79
80
TscF
SCK output fall time (Master mode)
—
—
TscH2doV, SDO data output valid after SCK
TscL2doV edge
PIC18CXX8
PIC18LCXX8
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5TCY + 40
Note 1: Requires the use of parameter # 73A.
2: Only if parameter #s 71A and 72A are used.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 331
PIC18CXX8
FIGURE 25-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
Bit6 - - - - - -1
Bit6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb In
74
LSb In
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Parm.
Symbol
Characteristic
Min
Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
ns
71
TscH
TscL
TB2B
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25TCY + 30
40
ns (Note 1)
ns
SCK input low time
(Slave mode)
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
75
TdoR
SDO data output rise time
PIC18CXX8
—
25
45
25
50
25
45
25
50
100
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LCXX8
—
76
77
78
TdoF
SDO data output fall time
—
TssH2doZ SS↑ to SDO output hi-impedance
10
TscR
SCK output rise time
(Master mode)
PIC18CXX8
—
PIC18LCXX8
—
79
80
TscF
SCK output fall time (Master mode)
—
TscH2doV, SDO data output valid after SCK
TscL2doV edge
PIC18CXX8
PIC18LCXX8
PIC18CXX8
PIC18LCXX8
—
—
82
83
TssL2doV SDO data output valid after SS↓
—
—
edge
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5TCY + 40
Note 1: Requires the use of parameter # 73A.
2: Only if parameter #s 71A and 72A are used.
DS30475A-page 332
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 25-16: I2C BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Parm.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA START condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Only relevant for Repeated
START condition
91
92
93
THD:STA START condition
Hold time
4000
600
After this period, the first
clock pulse is generated
TSU:STO STOP condition
Setup time
4700
600
THD:STO STOP condition
Hold time
4000
600
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 333
PIC18CXX8
FIGURE 25-17: I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
100 kHz mode
Min
Max
Units
Conditions
100
THIGH
Clock high time
4.0
—
µs
PIC18CXX8 must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
µs
PIC18CXX8 must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
4.7
—
—
101
TLOW
Clock low time
100 kHz mode
µs
µs
PIC18CXX8 must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
PIC18CXX8 must operate at a
minimum of 10 MHz
SSP module
1.5TCY
—
—
ns
ns
ns
102
103
TR
TF
SDA and SCL rise
time
100 kHz mode
400 kHz mode
1000
300
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
SDA and SCL fall
time
100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
90
TSU:STA
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
START condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for repeated
START condition
91
START condition hold 100 kHz mode
time
—
After this period the first clock
pulse is generated
400 kHz mode
—
106
107
92
Data input hold time
100 kHz mode
400 kHz mode
—
0
0.9
—
Data input setup time 100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
(Note 2)
—
STOP condition
setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
—
109
110
Output valid from
clock
3500
—
(Note 1)
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission can
start
—
D102
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2
2: A fast mode I C bus device can be used in a standard mode I C bus system, but the requirement tsu;DAT ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
2
Before the SCL line is released, TR max. + tsu;DAT = 1000 + 250 = 1250 ns (according to the standard mode I C bus
specification).
DS30475A-page 334
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 25-18: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
SCL
SDA
93
91
90
92
STOP
Condition
START
Condition
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-17: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
TSU:STA START condition
Setup time
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
Only relevant for
Repeated START
condition
90
ns
ns
ns
ns
91
92
93
THD:STA START condition
Hold time
After this period, the
first clock pulse is
generated
TSU:STO STOP condition
Setup time
THD:STO STOP condition
Hold time
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 335
PIC18CXX8
FIGURE 25-19: MASTER SSP I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-18: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
Symbol Characteristic
Min
Max Units Conditions
No.
THIGH
TLOW
TR
Clock high time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
ms
ms
100
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
ms
ms
Clock low time
101
102
103
90
2(TOSC)(BRG + 1)
—
—
1000
300
ms
ns
ns
SDA and SCL
rise time
Cb is specified to be from
10 to 400 pF
20 + 0.1Cb
—
—
300
300
300
ns
ns
ns
TF
SDA and SCL
fall time
Cb is specified to be from
10 to 400 pF
20 + 0.1Cb
1 MHz mode(1)
—
100
—
—
ns
ms
ms
TSU:STA
START condition 100 kHz mode
setup time
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
Only relevant for
Repeated START
condition
400 kHz mode
1 MHz mode(1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
THD:STA START condition 100 kHz mode
ms After this period the first
ms
91
hold time
clock pulse is generated
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
—
—
0.9
ms
ns
ms
THD:DAT Data input
hold time
0
0
106
107
92
TBD
250
100
—
—
—
ns
ns
ns
TSU:DAT
TSU:STO
TAA
Data input
setup time
(Note 2)
1 MHz mode(1)
TBD
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ns
ms
ms
STOP condition 100 kHz mode
setup time
400 kHz mode
1 MHz mode(1)
Output valid from 100 kHz mode
2(TOSC)(BRG + 1)
—
3500
1000
ms
ns
ns
—
—
109
110
clock
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
—
4.7
1.3
—
—
—
ns
TBUF
Bus free time
ms Time the bus must be free
ms
before a new transmis-
sion can start
1 MHz mode(1)
TBD
—
—
400
ms
pF
D102 Cb
Bus capacitive loading
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
Before the SCL line is released, parameter #102+ parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode).
DS30475A-page 336
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
FIGURE 25-20: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 25-4 for load conditions.
122
TABLE 25-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TckH2dtV SYNC XMIT (Master & Slave)
Clock high to data-out valid
PIC18CXX8
PIC18LCXX8
PIC18CXX8
PIC18LCXX8
PIC18CXX8
PIC18LCXX8
—
—
—
—
—
—
40
100
20
ns
ns
ns
ns
ns
ns
121
122
Tckrf
Tdtrf
Clock out rise time and fall time
(Master mode)
50
Data-out rise time and fall time
20
50
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 337
PIC18CXX8
FIGURE 25-21: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
125
pin
RC7/RX/DT
pin
126
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TdtV2ckl SYNC RCV (Master & Slave)
Data-hold before CK ↓ (DT hold time)
Data-hold after CK ↓ (DT hold time)
10
15
—
—
ns
ns
126
TckL2dtl
DS30475A-page 338
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
TABLE 25-21: A/D CONVERTER CHARACTERISTICS: PIC18CXX8 (INDUSTRIAL, EXTENDED)
PIC18LCXX8 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Resolution
Min
Typ
Max
Units
Conditions
A01
NR
—
—
—
—
10
TBD
bit VREF = VDD ≥ 3.0V
bit VREF = VDD < 3.0V
A03
A04
A05
A06
EIL
Integral linearity error
Differential linearity error
Full scale error
—
—
—
—
<±1
TBD
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD < 3.0V
EDL
EFS
EOFF
—
—
—
—
<±1
TBD
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD < 3.0V
—
—
—
—
<±1
TBD
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD < 3.0V
Offset error
—
—
—
—
<±1
TBD
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD < 3.0V
A10
A20
A20A
A21
A22
A25
A30
—
Monotonicity
guaranteed(3)
—
V
VSS ≤ VAIN ≤ VREF
VREF
Reference voltage
(VREFH - VREFL)
0V
3V
—
—
—
—
V
For 10-bit resolution
VREFH
VREFL
VAIN
Reference voltage High
Reference voltage Low
Analog input voltage
AVSS
—
—
—
—
AVDD + 0.3V
AVDD
V
AVSS - 0.3V
AVSS - 0.3V
—
V
VREF + 0.3V
10.0
V
ZAIN
Recommended impedance of
analog voltage source
kΩ
A40
A50
IAD
A/D conversion PIC18CXX8
—
—
180
90
—
—
µA Average current
current (VDD)
consumption when
PIC18LCXXX
µA
A/D is on(1)
.
IREF
VREF input current(2)
10
—
1000
µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN. To charge
CHOLD see Section 18.0.
During A/D conversion
µA cycle.
—
—
10
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec
includes any such leakage from the A/D module.
VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is selected
as reference input.
2: VSS ≤ VAIN ≤ VREF
3: The A/D conversion result either increases or remains constant as the analog input increases.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 339
PIC18CXX8
FIGURE 25-22: A/D CONVERSION TIMING
BSF ADCON0, GO
Note 2
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
NEW_DATA
TCY
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1:
2:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.This allows the SLEEPinstruction to
be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 25-22: A/D CONVERSION REQUIREMENTS
Param Sym-
Characteristic
Min
Max
Units
Conditions
No.
bol
20(5)
µs
TOSC based, VREF ≥ 3.0V
130
TAD
A/D clock period
PIC18CXX8
1.6
PIC18LCXX8
PIC18CXX8
PIC18LCXX8
3.0
2.0
3.0
11
20(5)
6.0
9.0
12
µs TOSC based, VREF full range
µs A/D RC mode
µs A/D RC mode
TAD
131
132
TCNV Conversion time
(not including acquisition time)(1)
TACQ Acquisition time(3)
15
10
—
—
µs -40°C ≤ Temp ≤ 125°C
µs
0°C ≤ Temp ≤ 125°C
135
136
TSWC Switching time from convert → sample
—
1
(Note 4)
TAMP Amplifier settling time (Note 2)
—
µs This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 18.0 for minimum conditions, when input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage, when the voltage changes full scale
after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is
50 Ω.
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
DS30475A-page 340
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
26.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and Tables are not available at this time.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 341
PIC18CXX8
NOTES:
DS30475A-page 342
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
27.0 PACKAGING INFORMATION
27.1
Package Marking Information
64-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
PIC18C658-I/PT
YYWWNNN
0017017
68-Lead PLCC
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC18C658-I/L
0017017
80-Lead TQFP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC18C858-I/PT
0017017
Legend: XX...X Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code and traceability code.
For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales
Office. For QTP devices, any special marking adders are included in QTP price.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 343
PIC18CXX8
Package Marking Information (Cont’d)
84-Lead PLCC
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC18C858-I/L
0017017
DS30475A-page 344
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
°
CH x 45
α
A
c
L
A2
φ
β
A1
(F)
Units
INCHES
NOM
MILLIMETERS*
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
64
64
.020
16
0.50
16
Pins per Side
Overall Height
n1
A
.039
.043
.039
.006
.024
.039
3.5
.047
1.00
1.10
1.00
0.15
0.60
1.00
3.5
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.037
.002
.018
.041
.010
.030
0.95
0.05
0.45
1.05
0.25
0.75
§
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.005
.007
.025
5
7
.482
.482
.398
.398
.009
.011
.045
15
0
11.75
11.75
9.90
9.90
0.13
0.17
0.64
5
7
12.25
12.25
10.10
10.10
0.23
0.27
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.007
.009
.035
10
12.00
12.00
10.00
10.00
0.18
0.22
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-085
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 345
PIC18CXX8
68-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
E
E1
#leads=n1
D1 D
n 1 2
°
°
α
CH2 x 45
CH1 x 45
A3
A2
A
32°
c
B1
B
A1
p
β
D2
E2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
68
MAX
n
p
Number of Pins
Pitch
68
.050
17
1.27
17
Pins per Side
Overall Height
n1
A
.165
.173
.153
.028
.029
.045
.005
.990
.990
.954
.954
.920
.920
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
25.02
25.02
24.13
24.13
22.61
22.61
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
25.15
25.15
24.23
24.23
23.37
23.37
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.145
.020
.024
.040
.000
.985
.985
.950
.950
.890
.890
.008
.026
.013
0
.160
.035
.034
.050
.010
.995
.995
.958
.958
.930
.930
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
25.27
25.27
24.33
24.33
23.62
23.62
0.33
0.81
0.53
10
§
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-049
DS30475A-page 346
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
B
c
1
n
°
CH x 45
A
α
A2
φ
β
L
A1
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
80
MAX
n
p
Number of Pins
Pitch
80
.020
20
0.50
20
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.043
.039
.004
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.00
3.5
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.041
.006
.030
1.05
0.15
0.75
§
0.05
0.45
Foot Length
Footprint (Reference)
Foot Angle
0
.541
.541
.463
.463
.004
.007
.025
5
7
.561
.561
.482
.482
.008
.011
.045
15
0
13.75
13.75
11.75
11.75
0.09
0.17
0.64
5
7
14.25
14.25
12.25
12.25
0.20
0.27
1.14
15
Overall Width
E
D
.551
.551
.472
.472
.006
.009
.035
10
14.00
14.00
12.00
12.00
0.15
0.22
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-092
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 347
PIC18CXX8
84-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
E
E1
#leads=n1
D1 D
n 1 2
α
CH2 x 45°
CH1 x 45°
A3
A2
A
32°
c
B1
B
A1
p
β
D2
E2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
68
MAX
n
p
Number of Pins
Pitch
68
.050
17
1.27
17
Pins per Side
Overall Height
n1
A
.165
.173
.153
.028
.029
.045
.005
.990
.990
.954
.954
.920
.920
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
25.02
25.02
24.13
24.13
22.61
22.61
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
25.15
25.15
24.23
24.23
23.37
23.37
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.145
.020
.024
.040
.000
.985
.985
.950
.950
.890
.890
.008
.026
.013
0
.160
.035
.034
.050
.010
.995
.995
.958
.958
.930
.930
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
25.27
25.27
24.33
24.33
23.62
23.62
0.33
0.81
0.53
10
§
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-093
DS30475A-page 348
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
APPENDIX A: DATA SHEET
REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
The differences between the PIC18CXX8 devices
listed in this data sheet are shown in Table B-1.
Revision A
This is a new data sheet.
TABLE B-1:
DEVICE DIFFERENCES
Feature
PIC18C658
32K
PIC18C858
Program Memory (Bytes)
Data Memory (Bytes)
A/D Channels
32K
1.5K
1.5K
16
12
Parallel Slave Port (PSP)
Yes
Yes
External Memory Capability No
No
Package
Types
TQFP
64-pin
68-pin
68-pin
80-pin
84-pin
84-pin
PLCC
JCERPACK
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 349
PIC18CXX8
APPENDIX C: DEVICE MIGRATIONS
APPENDIX D: MIGRATING FROM
OTHER PICMICRO
This section is intended to describe the functional and
electrical specification differences when migrating
between functionally similar devices (such as from a
PIC16C74A to a PIC16C74B).
DEVICES
This discusses some of the issues in migrating from
other PICmicro devices to the PIC18CXXX family of
devices.
Not Applicable
D.1
PIC16CXXX to PIC18CXXX
See application note AN716.
D.2
PIC17CXXX to PIC18CXXX
See application note AN726.
DS30475A-page 350
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
APPENDIX E: DEVELOPMENT
TOOL VERSION
REQUIREMENTS
This lists the minimum requirements (software/firm-
ware) of the specified development tool to support the
devices listed in this data sheet.
MPLAB-IDE:
version 5.11
version 7.10
MPLAB-SIM:
MPLAB-ICE 2000:
PIC18CXX8 Processor Module:
Part Number -
PCM 18XB0
PIC18CXX8 Device Adapter:
Socket
Part Number
64-pin TQFP
68-pin PLCC
80-pin TQFP
84-pin PLCC
DVD18P2640
DVD18XL680
DVD18PQ800
DVD18XL840
MPLAB-ICD:
Not Available
version 5.20
version 2.20
version 2.50
version 1.00
PROMATE II:
PICSTART Plus:
MPASM:
MPLAB-C18:
CAN-TOOL:
Not available at time of
printing.
Note: Please read all associated README.TXT
files that are supplied with the develop-
ment tools. These "read me" files will dis-
cuss product support and any known
limitations.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 351
PIC18CXX8
NOTES:
DS30475A-page 352
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
INDEX
BSF .......................... 269, 270, 271, 272, 273, 275, 276, 291
BTFSC ............................................................................. 274
BTFSS ............................................................................. 274
BTG ................................................................................. 275
Bus Activity Wake-up Interrupt ........................................ 225
Bus Collision During a RESTART Condition ................... 165
Bus Collision During a START Condition ........................ 163
Bus Collision During a STOP Condition .......................... 166
Bus Off ............................................................................. 226
A
A/D ................................................................................... 227
A/D Converter Flag (ADIF Bit) ................................. 230
A/D Converter Interrupt, Configuring ....................... 231
ADCON0 Register ............................................ 227, 229
ADCON1 Register ............................................ 227, 228
ADCON2 Register .................................................... 227
ADRES Register .............................................. 227, 230
Analog Port Pins, Configuring .................................. 233
Block Diagram .......................................................... 230
Block Diagram, Analog Input Model ......................... 231
Configuring the Module ............................................ 231
Conversion Clock (TAD) ........................................... 233
Conversion Status (GO/DONE Bit) .......................... 230
Conversions ............................................................. 234
Converter Characteristics ........................................ 339
converter characteristics .......................................... 318
Effects of a RESET .................................................. 250
Equations ................................................................. 232
Operation During SLEEP ......................................... 250
Sampling Requirements ........................................... 232
Sampling Time ......................................................... 232
Special Event Trigger (CCP) ............................ 130, 234
Timing Diagram ........................................................ 340
Absolute Maximum Ratings ............................................. 311
Acknowledge Error ........................................................... 223
ADCON0 Register .................................................... 227, 229
GO/DONE Bit ........................................................... 230
ADCON1 Register .................................................... 227, 228
ADCON2 Register ............................................................ 227
ADDLW ............................................................................ 267
ADDWF ............................................................................ 267
ADDWFC ......................................................................... 268
ADRES Register ...................................................... 227, 230
AKS .................................................................................. 156
Analog-to-Digital Converter. See A/D
C
CALL ................................................................................ 276
CAN Buffers and Protocol Engine Block Diagram ........... 184
Capture (CCP Module) .................................................... 128
Block Diagram ......................................................... 129
CCP Pin Configuration ............................................ 128
CCPR1H:CCPR1L Registers .................................. 128
Changing Between Capture Prescalers .................. 129
Software Interrupt .................................................... 129
Timer1 Mode Selection ............................................ 128
Capture/Compare/PWM (CCP) ....................................... 127
Capture Mode. See Capture
CCP1 ....................................................................... 128
CCPR1H Register ........................................... 128
CCPR1L Register ............................................ 128
CCP2 ....................................................................... 128
CCPR2H Register ........................................... 128
CCPR2L Register ............................................ 128
Compare Mode. See Compare
Interaction of Two CCP Modules ............................. 128
PWM Mode. See PWM
Timer Resources ..................................................... 128
Timing Diagram ....................................................... 327
Clocking Scheme ............................................................... 45
CLRF ....................................................................... 277, 295
CLRWDT ......................................................................... 277
Code Examples
ANDLW ............................................................................ 268
ANDWF ............................................................................ 269
Assembler
Loading the SSPBUF Register ................................ 142
Code Protection ....................................................... 251, 259
COMF .............................................................................. 278
Comparator Interrupts ...................................................... 241
Comparator Operation ..................................................... 239
Comparator Reference .................................................... 239
Compare (CCP Module) .................................................. 130
Block Diagram ......................................................... 130
CCP Pin Configuration ............................................ 130
CCPR1H:CCPR1L Registers .................................. 130
Software Interrupt .................................................... 130
Special Event Trigger ...................... 119, 125, 130, 234
Timer1 Mode Selection ............................................ 130
Configuration Bits ............................................................ 251
Configuration Mode ......................................................... 210
Configuring the Voltage Reference .................................. 243
CPFSEQ .......................................................................... 278
CPFSGT .......................................................................... 279
CPFSLT ........................................................................... 279
CRC Error ........................................................................ 223
CVRCON Register ........................................................... 243
MPASM Assembler .................................................. 305
B
Baud Rate Generator ....................................................... 153
BCF .................................................................................. 270
BF .................................................................................... 156
Bit Error ............................................................................ 223
Bit Timing ......................................................................... 218
Bit Timing Configuration Registers .................................. 222
Block Diagrams
Baud Rate Generator ............................................... 153
Comparator I/O Operating Modes ............................ 238
PORTK ..................................................................... 108
SSP (SPI Mode) ....................................................... 141
Timer3 ...................................................................... 124
BOR. See Brown-out Reset
BRG ................................................................................. 153
Brown-out Reset (BOR) ............................................. 30, 251
Timing Diagram ........................................................ 325
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 353
PIC18CXX8
Bus Collision timing ................................................. 162
Clock Arbitration ...................................................... 161
Clock Arbitration Timing (Master Transmit) ............. 161
General Call Address Support ................................. 150
Master Mode 7-bit Reception timing ........................ 158
Master Mode Operation ........................................... 152
Master Mode Start Condition ................................... 154
Master Mode Transmission ..................................... 156
Master Mode Transmit Sequence ............................ 152
Multi-Master Mode ................................................... 162
Repeat START Condition timing .............................. 155
STOP Condition Receive or Transmit timing ........... 160
STOP Condition timing ............................................ 159
Waveforms for 7-bit Reception ................................ 149
Waveforms for 7-bit Transmission ........................... 149
ID Locations ............................................................. 251, 259
INCF ................................................................................ 282
INCFSNZ ......................................................................... 283
INCFSZ ............................................................................ 283
In-Circuit Serial Programming (ICSP) ...................... 251, 259
Indirect Addressing ............................................................ 62
FSR Register ............................................................. 61
Information Processing Time ........................................... 219
Initiating Message Transmission ..................................... 211
Instruction Cycle ................................................................ 45
Instruction Flow/Pipelining ................................................. 46
Instruction Format ............................................................ 263
Instruction Set .................................................................. 261
ADDLW .................................................................... 267
ADDWF .................................................................... 267
ADDWFC ................................................................. 268
ANDLW .................................................................... 268
ANDWF .................................................................... 269
BCF ......................................................................... 270
BSF .................. 269, 270, 271, 272, 273, 275, 276, 291
BTFSC ..................................................................... 274
BTFSS ..................................................................... 274
BTG ......................................................................... 275
CALL ........................................................................ 276
CLRF ............................................................... 277, 295
CLRWDT ................................................................. 277
COMF ...................................................................... 278
CPFSEQ .................................................................. 278
CPFSGT .................................................................. 279
CPFSLT ................................................................... 279
DAW ........................................................................ 280
DECF ....................................................................... 280
DECFSNZ ................................................................ 281
DECFSZ .................................................................. 281
GOTO ...................................................................... 282
INCF ........................................................................ 282
INCFSNZ ................................................................. 283
INCFSZ .................................................................... 283
IORLW ..................................................................... 284
IORWF ..................................................................... 284
MOVFP .................................................................... 286
MOVLB .................................................................... 285
MOVLR ............................................................ 285, 286
MOVLW ................................................................... 287
MOVWF ................................................................... 287
MULLW .................................................................... 288
MULWF .................................................................... 288
NEGW ..................................................................... 289
NOP ......................................................................... 289
RETFIE ............................................................ 291, 292
RETLW .................................................................... 292
D
Data Memory ......................................................................48
General Purpose Registers ........................................48
Special Function Registers ........................................48
DAW .................................................................................280
DC Characteristics ...........................313, 314, 315, 316, 317
DECF ...............................................................................280
DECFSNZ ........................................................................281
DECFSZ ...........................................................................281
Device Differences ...........................................................349
Device Functionality .........................................................184
Direct Addressing ...............................................................62
E
Electrical Characteristics ..................................................311
Errata ...................................................................................7
Error Detection .................................................................223
Error Interrupt ...................................................................226
Error Modes .....................................................................224
Error Modes and Error Counters ......................................223
Error States ......................................................................223
F
Filter/Mask Truth Table ....................................................216
Firmware Instructions .......................................................261
Form Error ........................................................................223
G
General Call Address Sequence ......................................150
General Call Address Support .........................................150
GOTO ...............................................................................282
H
Hard Synchronization .......................................................220
I
I/O Ports .............................................................................89
2
I C (SSP Module) .............................................................147
ACK Pulse ................................................147, 148, 149
Addressing ...............................................................148
Block Diagram ..........................................................147
Read/Write Bit Information (R/W Bit) ............... 148, 149
Reception .................................................................149
Serial Clock (RC3/SCK/SCL) ...................................149
Slave Mode ..............................................................147
Timing Diagram, Data ..............................................334
Timing Diagram, Start/Stop Bits ...............................333
Transmission ............................................................149
2
I C Master Mode Reception .............................................156
2
I C Master Mode Restart Condition .................................155
2
I C Module
Acknowledge Sequence timing ................................159
Baud Rate Generator ...............................................153
BRG Block Diagram .................................................153
BRG Reset due to SDA Collision .............................164
BRG Timing .............................................................153
Bus Collision
Acknowledge ....................................................162
Restart Condition .............................................165
Restart Condition Timing (Case1) ....................165
Restart Condition Timing (Case2) ....................165
START Condition .............................................163
Start Condition Timing ............................. 163, 164
STOP Condition ...............................................166
STOP Condition Timing (Case1) .....................166
STOP Condition Timing (Case2) .....................166
Transmit Timing ...............................................162
DS30475A-page 354
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
RETURN .................................................................. 293
RLCF ........................................................................ 293
RLNCF ..................................................................... 294
RRCF ....................................................................... 294
RRNCF .................................................................... 295
SLEEP ..................................................................... 296
SUBLW .................................................................... 297
SUBWF ............................................................ 297, 298
SUBWFB .................................................................. 299
SWAPF .................................................................... 300
TABLRD ................................................................... 301
TABLWT .................................................................. 302
TSTFSZ ................................................................... 303
XORLW .................................................................... 303
XORWF .................................................................... 304
Summary Table ........................................................ 264
INT Interrupt (RB0/INT). See Interrupt Sources
MPLAB Integrated Development
Environment Software ..................................................... 305
MULLW ............................................................................ 288
Multi-Master Mode ........................................................... 162
Multiply Examples
16 x 16 Routine ......................................................... 72
16 x 16 Signed Routine ............................................. 73
8 x 8 Routine ............................................................. 72
8 x 8 Signed Routine ................................................. 72
MULWF ............................................................................ 288
N
NEGW ............................................................................. 289
NOP ................................................................................. 289
Normal Mode ................................................................... 210
O
OPTION_REG Register ..................................................... 64
PS2:PS0 Bits ........................................................... 115
PSA Bit .................................................................... 115
T0CS Bit .................................................................. 115
T0SE Bit .................................................................. 115
OSCCON ........................................................................... 25
OSCCON Register ............................................................. 25
Oscillator Configuration ............................................. 21, 251
HS .............................................................................. 21
HS + PLL ................................................................... 21
LP .............................................................................. 21
RC ....................................................................... 21, 23
RCIO .......................................................................... 21
XT .............................................................................. 21
Oscillator Tolerance ......................................................... 222
Oscillator, Timer1 ............................................. 117, 119, 123
Oscillator, Timer3 ............................................................. 125
Oscillator, WDT ................................................................ 255
Overview .......................................................................... 183
INTCON Register
RBIF Bit ...................................................................... 91
2
Inter-Integrated Circuit. See I C
Interrupt Acknowledge ..................................................... 226
Interrupt Sources ....................................................... 75, 251
A/D Conversion Complete ....................................... 231
Capture Complete (CCP) ......................................... 129
Compare Complete (CCP) ....................................... 130
Interrupt-on-Change (RB7:RB4 ) ............................... 91
RB0/INT Pin, External ................................................ 88
SSP Receive/Transmit Complete ............................ 135
TMR0 Overflow ........................................................ 116
TMR1 Overflow ................................................ 117, 119
TMR2 to PR2 Match ................................................ 122
TMR2 to PR2 Match (PWM) ............................ 121, 132
TMR3 Overflow ................................................ 123, 125
USART Receive/Transmit Complete ....................... 167
Interrupts .......................................................................... 225
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit) ...................................... 129
Interrupts, Flag Bits
P
Packaging ........................................................................ 343
Parallel Slave Port (PSP) ........................................... 95, 109
Block Diagram ......................................................... 109
RE0/RD ................................................................... 109
RE1/WR ................................................................... 109
RE2/CS .................................................................... 109
Read Waveforms ..................................................... 111
Select (PSPMODE Bit) ...................................... 95, 109
Timing Diagram ....................................................... 328
Write Waveforms ..................................................... 111
Phase Buffer Segments ................................................... 219
PICDEM 1 Low Cost PICmicro Demo Board ................... 307
PICDEM 2 Low Cost PIC16CXX Demo Board ................ 307
PICDEM 3 Low Cost PIC16CXXX Demo Board .............. 308
PICSTART Plus Entry Level Development System ......... 307
Pin Functions
A/D Converter Flag (ADIF Bit) ................................. 230
CCP1 Flag (CCP1IF Bit) .......................... 128, 129, 130
Interrupt on Change (RB7:RB4) Flag (RBIF Bit) ........ 91
IORLW ............................................................................. 284
IORWF ............................................................................. 284
K
KEELOQ Evaluation and Programming Tools ................... 308
L
Lengthening a Bit Period .................................................. 221
Listen Only Mode ............................................................. 210
Loopback Mode ............................................................... 211
M
Memory Organization
Data Memory ............................................................. 48
Program Memory ....................................................... 41
Message Acceptance Filter .............................................. 217
Message Acceptance Filters and Masks ......................... 216
Message Reception ......................................................... 213
Message Reception Flowchart ......................................... 215
MOVFP ............................................................................ 286
MOVLB ............................................................................ 285
MOVLR .................................................................... 285, 286
MOVLW ........................................................................... 287
MOVWF ........................................................................... 287
AVDD .......................................................................... 20
AVSS .......................................................................... 20
MCLR/VPP ................................................................. 12
OSC1/CLKI ................................................................ 12
OSC2/CLKO .............................................................. 12
RA0/AN0 .................................................................... 13
RA1/AN1 .................................................................... 13
RA2/AN2/VREF- ......................................................... 13
RA3/AN3/VREF+ ........................................................ 13
RA4/T0CKI ................................................................ 13
RA5/AN4/SS/LVDIN .................................................. 13
RA6 ............................................................................ 13
RB0/INT0 ................................................................... 14
2000 Microchip Technology Inc.
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DS30475A-page 355
PIC18CXX8
RB1/INT1 ...................................................................14
RB2/INT2 ...................................................................14
RB3/INT3 ...................................................................14
RB4 ............................................................................14
RB5 ............................................................................14
RB6 ............................................................................14
RB7 ............................................................................14
RC0/T1OSO/T1CKI ...................................................15
RC1/T1OSI ................................................................15
RC2/CCP1 .................................................................15
RC3/SCK/SCL ...........................................................15
RC4/SDI/SDA ............................................................15
RC5/SDO ...................................................................15
RC6/TX/CK ................................................................15
RC7/RX/DT ................................................................15
RD0/AD0 ....................................................................16
RD0/PSP0 ..................................................................16
RD1/AD1 ....................................................................16
RD1/PSP1 ..................................................................16
RD2/AD2 ....................................................................16
RD2/PSP2 ..................................................................16
RD3/AD3 ....................................................................16
RD3/PSP3 ..................................................................16
RD4/AD4 ....................................................................16
RD4/PSP4 ..................................................................16
RD5/AD5 ....................................................................16
RD5/PSP5 ..................................................................16
RD6/AD6 ....................................................................16
RD6/PSP6 ..................................................................16
RD7/AD7 ....................................................................16
RD7/PSP7 ..................................................................16
RE0/ALE ....................................................................17
RE0/RD ......................................................................17
RE1/OE ......................................................................17
RE1/WR .....................................................................17
RE2/CS ......................................................................17
RE2/WRL ...................................................................17
RE3/WRH ..................................................................17
RE4 ............................................................................17
RE5 ............................................................................17
RE6 ............................................................................17
RE7/CCP2 .................................................................17
RF0/AN5 ....................................................................18
RF1/AN6 ....................................................................18
RF2/AN7 ....................................................................18
RF3/AN8 ....................................................................18
RF4/AN9 ....................................................................18
RF5/AN10 ..................................................................18
RF6/AN11 ..................................................................18
RF7 ............................................................................18
RG0/CANTX1 ............................................................19
RG1/CANTX2 ............................................................19
RG2/CANRX ..............................................................19
RG3 ............................................................................19
RG4 ............................................................................19
RH0/A16 ....................................................................19
RH1/A17 ....................................................................19
RH2/A18 ....................................................................19
RH3/A19 ....................................................................19
RH4/AN12 ..................................................................19
RH5/AN13 ..................................................................19
RH6/AN14 ..................................................................19
RH7/AN15 ..................................................................19
RJ0/AD8 .....................................................................20
RJ1/AD9 .....................................................................20
RJ2/AD10 ...................................................................20
RJ3/AD11 ...................................................................20
RK0 ............................................................................ 20
RK1 ............................................................................ 20
RK2 ............................................................................ 20
RK3 ............................................................................ 20
VDD ............................................................................ 20
VSS ............................................................................ 20
Pointer, FSR ...................................................................... 61
POR. See Power-on Reset
PORTA
Initialization ................................................................ 89
PORTA Register ........................................................ 89
RA3:RA0 and RA5 Port Pins ..................................... 89
RA4/T0CKI Pin .......................................................... 90
TRISA Register .......................................................... 89
PORTB
Initialization ................................................................ 91
PORTB Register ........................................................ 91
RB0/INT Pin, External ................................................ 88
RB3:RB0 Port Pins .................................................... 91
RB7:RB4 Interrupt on Change Flag (RBIF Bit) .......... 91
RB7:RB4 Port Pins .................................................... 91
TRISB Register .......................................................... 91
PORTC
Block Diagram ........................................................... 93
Initialization ................................................................ 93
PORTC Register ........................................................ 93
RC3/SCK/SCL Pin ................................................... 149
RC7/RX/DT Pin ........................................................ 169
TRISC Register .................................................. 93, 167
PORTD ............................................................................ 109
Block Diagram ........................................................... 95
Initialization ................................................................ 95
Parallel Slave Port (PSP) Function ............................ 95
PORTD Register ........................................................ 95
TRISD Register .......................................................... 95
PORTE
Block Diagram ........................................................... 97
Initialization ................................................................ 97
PORTE Register ........................................................ 97
PSP Mode Select (PSPMODE Bit) .................... 95, 109
RE0/RD ................................................................... 109
RE1/WR ................................................................... 109
RE2/CS .................................................................... 109
TRISE Register .......................................................... 97
PORTF
Block Diagram ........................................................... 99
Block Diagram of RF7 Pin ....................................... 100
C1OUT, C2OUT ........................................................ 99
Initialization ................................................................ 99
PORTF Register ........................................................ 99
RF6/RF3 and RF0 Pins Block Diagram ................... 100
TRISF ........................................................................ 99
PORTG
Initialization .............................................................. 101
PORTG .................................................................... 101
RG0/CANTX0 Pin Block Diagram ............................ 101
RG1/CANTX1 Pin Block Diagram ............................ 102
RG2 Pin Block Diagram ........................................... 102
RG4/RG3 Pins Block Diagram ................................. 102
TRISG ...................................................................... 101
PORTH
Initialization .............................................................. 104
PORTH .................................................................... 104
RH3/RH0 Pins Block Diagram ................................. 104
RH7/RH4 Pins Block Diagram ................................. 104
TRISH ...................................................................... 104
DS30475A-page 356
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
PORTJ
Initialization .............................................................. 106
PORTJ ..................................................................... 106
TRISJ ....................................................................... 106
PORTJ Block Diagram ..................................................... 106
PORTK
Initialization .............................................................. 108
PORTK ..................................................................... 108
TRISK ...................................................................... 108
Postscaler, WDT
Assignment (PSA Bit) .............................................. 115
Rate Select (PS2:PS0 Bits) ..................................... 115
Switching Between Timer0 and WDT ...................... 115
Power-down Mode. See SLEEP
Power-on Reset (POR) .............................................. 30, 251
Oscillator Start-up Timer (OST) ......................... 30, 251
Power-up Timer (PWRT) ................................... 30, 251
Time-out Sequence .................................................... 31
Time-out Sequence on Power-up ........................ 32, 33
Timing Diagram ........................................................ 325
Prescaler, Capture ........................................................... 129
Prescaler, Timer0 ............................................................. 115
Assignment (PSA Bit) .............................................. 115
Rate Select (PS2:PS0 Bits) ..................................... 115
Switching Between Timer0 and WDT ...................... 115
Prescaler, Timer1 ............................................................. 118
Prescaler, Timer2 ............................................................. 132
PRO MAT“ II Universal Programmer ............................... 307
Program Counter
PCL Register .............................................................. 45
PCLATH Register ...................................................... 45
Program Memory ............................................................... 41
Program Verification ........................................................ 259
Programmable ................................................................. 251
Programming Time Segments ......................................... 222
Programming, Device Instructions ................................... 261
Propagation Segment ...................................................... 219
PSPCON Register
Registers
SSPSTAT ................................................................ 136
T3CON
Diagram ........................................................... 123
Section ............................................................ 123
RESET ....................................................................... 29, 251
Timing Diagram ....................................................... 325
Resynchronization ........................................................... 220
RETFIE .................................................................... 291, 292
RETLW ............................................................................ 292
RETURN .......................................................................... 293
Revision History ............................................................... 349
RLCF ............................................................................... 293
RLNCF ............................................................................. 294
RRCF ............................................................................... 294
RRNCF ............................................................................ 295
S
Sample Point ................................................................... 219
SCI. See USART
SCK ................................................................................. 141
SDI ................................................................................... 141
SDO ................................................................................. 141
Serial Clock, SCK ............................................................ 141
Serial Communication Interface. See USART
Serial Data In, SDI ........................................................... 141
Serial Data Out, SDO ...................................................... 141
Serial Peripheral Interface. See SPI
Shortening a Bit Period .................................................... 221
Simplified Block Diagram of On-Chip Reset Circuit ........... 29
Slave Select Synchronization .......................................... 144
Slave Select, SS .............................................................. 141
SLEEP ............................................................. 251, 257, 296
Software Simulator (MPLAB-SIM) ................................... 306
Special Event Trigger. See Compare
Special Features of the CPU ................................... 247, 251
Special Function Registers ................................................ 48
SPI
Master Mode ............................................................ 143
Serial Clock ............................................................. 141
Serial Data In ........................................................... 141
Serial Data Out ........................................................ 141
Slave Select ............................................................. 141
SPI Clock ................................................................. 143
SPI Mode ................................................................. 141
SPI Module
PSPMODE Bit .................................................... 95, 109
PWM (CCP Module) ........................................................ 132
Block Diagram .......................................................... 132
CCPR1H:CCPR1L Registers ................................... 132
Duty Cycle ................................................................ 132
Example Frequencies/Resolutions .......................... 133
Output Diagram ........................................................ 132
Period ....................................................................... 132
Setup for PWM Operation ........................................ 133
TMR2 to PR2 Match ........................................ 121, 132
Slave Mode .............................................................. 144
Slave Select Synchronization .................................. 144
Slave Synch Timing ................................................. 144
Slave Timing with CKE = 0 ...................................... 145
Slave Timing with CKE = 1 ...................................... 145
SS .................................................................................... 141
SSP ................................................................................. 135
Block Diagram (SPI Mode) ...................................... 141
Q
Q-Clock ............................................................................ 132
R
RAM. See Data Memory
RCSTA Register
2
2
I C Mode. See I C
SPEN Bit .................................................................. 167
Receive Buffers ................................................................ 213
Receive Buffers Diagram ................................................. 214
Receive Interrupt .............................................................. 225
Receive Message Buffering ............................................. 213
Receiver Error Passive .................................................... 226
Receiver Overrun ............................................................. 226
Receiver Warning ............................................................ 226
Register File ....................................................................... 48
SPI Mode ................................................................. 141
SPI Mode. See SPI
SSPBUF .................................................................. 143
SSPCON1 ............................................................... 138
SSPCON2 ............................................................... 140
SSPSR .................................................................... 143
SSPSTAT ................................................................ 136
TMR2 Output for Clock Shift ............................ 121, 122
SSP Module
SPI Master Mode ..................................................... 143
SPI Slave Mode ....................................................... 144
SSPCON1 ....................................................................... 138
SSPCON2 ....................................................................... 140
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 357
PIC18CXX8
SSPOV .............................................................................156
SSPSTAT .........................................................................136
SSPSTAT Register
Master Mode Transmit Clock Arbitration ................. 161
Repeat Start Condition ............................................ 155
Slave Synchronization ............................................. 144
Slow Rise Time .......................................................... 33
SPI Mode Timing (Master Mode) SPI Mode
R/W Bit ............................................................. 148, 149
Stuff Error .........................................................................223
SUBLW ............................................................................297
SUBWF .................................................................... 297, 298
SUBWFB ..........................................................................299
SWAPF ............................................................................300
Synchronization ................................................................220
Synchronization Rules .....................................................220
Synchronization Segment ................................................219
Synchronous Serial Port. See SSP
Master Mode Timing Diagram ......................... 143
SPI Mode Timing (Slave Mode with CKE = 0) ......... 145
SPI Mode Timing (Slave Mode with CKE = 1) ......... 145
Stop Condition Receive or Transmit ........................ 160
Time-out Sequence on Power-up .............................. 32
USART Asynchronous Master Transmission .......... 174
USART Asynchronous Reception ............................ 176
USART Synchronous Reception ............................. 179
USART Synchronous Transmission ........................ 178
Wake-up from SLEEP via Interrupt .......................... 258
Timing Diagrams and Specifications ............................... 322
A/D Conversion ........................................................ 340
Brown-out Reset (BOR) ........................................... 325
Capture/Compare/PWM (CCP) ............................... 327
CLKOUT and I/O ..................................................... 324
External Clock .......................................................... 322
T
TABLRD ...........................................................................301
TABLWT ...........................................................................302
Time Quanta ....................................................................219
Timer Modules
Timer3
Block Diagram ..................................................124
Timer0 ..............................................................................113
Clock Source Edge Select (T0SE Bit) ......................115
Clock Source Select (T0CS Bit) ...............................115
Overflow Interrupt ....................................................116
Prescaler. See Prescaler, Timer0
Timing Diagram ........................................................326
Timer1 ..............................................................................117
Block Diagram ..........................................................118
Oscillator .......................................................... 117, 119
Overflow Interrupt ............................................ 117, 119
Prescaler. See Prescaler, Timer1
Special Event Trigger (CCP) ............................ 119, 130
Timing Diagram ........................................................326
TMR1H Register ......................................................117
TMR1L Register .......................................................117
TMR3L Register .......................................................123
Timer2
2
I C Bus Data ............................................................ 334
2
I C Bus START/STOP Bits ...................................... 333
Oscillator Start-up Timer (OST) ............................... 325
Parallel Slave Port (PSP) ......................................... 328
Power-up Timer (PWRT) ......................................... 325
Reset ....................................................................... 325
Timer0 and Timer1 .................................................. 326
USART Synchronous Receive ( Master/Slave) ....... 338
USART Synchronous Transmission ( Master/Slave) 337
Watchdog Timer (WDT) ........................................... 325
Transmit Interrupt ............................................................ 225
Transmit Message Aborting ............................................. 211
Transmit Message Buffering ............................................ 211
Transmit Message Buffers ............................................... 211
Transmit Message flowchart ............................................ 212
Transmit Message Priority ............................................... 211
Transmitter Error Passive ................................................ 226
Transmitter Warning ........................................................ 226
TRISE Register .................................................................. 97
TSTFSZ ........................................................................... 303
TXSTA Register
Block Diagram ..........................................................122
Postscaler. See Postscaler, Timer2
PR2 Register .................................................... 121, 132
Prescaler. See Prescaler, Timer2
SSP Clock Shift ................................................ 121, 122
TMR2 Register .........................................................121
TMR2 to PR2 Match Interrupt ..................121, 122, 132
Timer3 ..............................................................................123
Oscillator .......................................................... 123, 125
Overflow Interrupt ............................................ 123, 125
Special Event Trigger (CCP) ....................................125
TMR3H Register ......................................................123
Timing Diagrams
BRGH Bit ................................................................. 169
U
Universal Synchronous Asynchronous Receiver
Transmitter. See USART
USART ............................................................................. 167
Asynchronous Mode ................................................ 173
Master Transmission ....................................... 174
Receive Block Diagram ................................... 175
Reception ........................................................ 176
Transmit Block Diagram .................................. 173
Baud Rate Generator (BRG) ................................... 169
Baud Rate Error, Calculating ........................... 169
Baud Rate Formula ......................................... 169
High Baud Rate Select (BRGH Bit) ................. 169
Sampling .......................................................... 169
Serial Port Enable (SPEN Bit) ................................. 167
Synchronous Master Mode ...................................... 177
Reception ........................................................ 179
Timing Diagram, Synchronous Receive .......... 338
Timing Diagram, Synchronous Transmission .. 337
Transmission ................................................... 178
Synchronous Slave Mode ........................................ 180
Acknowledge Sequence Timing ...............................159
Baud Rate Generator with Clock Arbitration ............153
BRG Reset Due to SDA Collision ............................164
Bus Collision
START Condition Timing .................................163
Bus Collision During a RESTART Condition
(Case 1) ...................................................................165
Bus Collision During a RESTART Condition
(Case2) ....................................................................165
Bus Collision During a START Condition (SCL = 0) 164
Bus Collision During a STOP Condition ...................166
Bus Collision for Transmit and Acknowledge ...........162
2
I C Bus Data ............................................................336
2
I C Master Mode First Start bit timing ......................154
2
I C Master Mode Reception timing ..........................158
2
I C Master Mode Transmission timing .....................157
DS30475A-page 358
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
W
Wake-up from SLEEP .............................................. 251, 257
Timing Diagram ........................................................ 258
Watchdog Timer (WDT) ........................................... 251, 255
Block Diagram .......................................................... 256
Postscaler. See Postscaler, WDT
Programming Considerations .................................. 255
RC Oscillator ............................................................ 255
Time-out Period ....................................................... 255
Timing Diagram ........................................................ 325
Waveform for General Call Address Sequence ............... 150
WCOL .............................................................. 154, 156, 159
WCOL Status Flag ........................................................... 154
WWW, On-Line Support ...................................................... 7
X
XORLW ............................................................................ 303
XORWF ............................................................................ 304
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 359
PIC18CXX8
NOTES:
DS30475A-page 360
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2000 Microchip Technology Inc.
PIC18CXX8
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PIC18CXX8 PRODUCT IDENTIFICATION SYSTEM
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/XX
XXX
Examples:
Temperature Package
Range
Pattern
a)
PIC18LC658 - I/L 301 = Industrial temp., PLCC
package, Extended VDD limits, QTP pattern
#301.
b)
c)
PIC18LC858 - I/PT = Industrial temp., TQFP
package, Extended VDD limits.
Device
PIC18CXX8(1), PIC18CXX8T(2)
VDD range 4.2V to 5.5V
;
PIC18C658 - E/L = Extended temp., PLCC
package, normal VDD limits.
PIC18LCXX5(1), PIC18LCXX8T(2)
VDD range 2.5V to 5.5V
;
Temperature Range
Package
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
Note 1:
C
LC
T
=
=
=
Standard Voltage Range
Wide Voltage Range
in tape and reel PLCC, and TQFP
packages only.
CL
PT
L
=
=
=
Windowed JCERPACK
TQFP (Thin Quad Flatpack)
PLCC
2:
3:
CL devices are UV erasable and can be pro-
grammed to any device configuration. CL
devices meet the electrical requirement of
each oscillator type (including LC devices).
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 363
PIC18CXX8
NOTES:
DS30475A-page 364
Advanced Information
2000 Microchip Technology Inc.
PIC18CXX8
NOTES:
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 365
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC (continued)
Corporate Office
China - Beijing
Microchip Technology Beijing Office
Unit 915
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
New China Hong Kong Manhattan Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
#07-02 Prime Centre
Singapore, 188980
Tel: 65-334-8870 Fax: 65-334-8850
Rocky Mountain
Taiwan
Microchip Technology Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
China - Shanghai
Microchip Technology Shanghai Office
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-7456
Atlanta
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3838 Fax: 978-692-3821
EUROPE
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Hong Kong
Microchip Asia Pacific
RM 2101, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
France
India
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Microchip Technology Inc.
India Liaison Office
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Divyasree Chambers
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
4570 Westgrove Drive, Suite 160
Addison, TX 75001
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Two Prestige Place, Suite 130
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Tel: 949-263-1888 Fax: 949-263-1338
Tel: 82-2-554-7200 Fax: 82-2-558-5934
New York
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
10/01/00
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
All rights reserved. © 2000 Microchip Technology Incorporated. Printed in the USA. 11/00
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec-
tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30475A-page 366
Advanced Information
2000 Microchip Technology Inc.
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