PIC16LF1906-I/MV_技术文档

PIC16LF1904/6/7

28/40/44-Pin 8-Bit Flash Microcontrollers with XLP Technology

• Extended Watchdog Timer (WDT)

High-Performance RISC CPU:

• In-Circuit Serial Programming™ (ICSP™) via

Two Pins

• C Compiler Optimized Architecture

• Only 49 Instructions

• In-Circuit Debug (ICD) via Two Pins

• Up to 14 Kbytes Self-Write/Read Flash Program

• Enhanced Low-Voltage Programming (LVP)

Memory Addressing

• Programmable Code Protection

• Up to 256 Bytes Data Memory Addressing

• Power-Saving Sleep mode

• Operating Speed:

- DC – 20 MHz clock input @ 3.6V

eXtreme Low-Power (XLP) Features

(PIC16LF1904/6/7):

- DC – 16 MHz clock input @ 1.8V

- DC – 200 ns instruction cycle

• Sleep Current:

• Interrupt Capability with Automatic Context

- 30 nA @ 1.8V, typical

• Watchdog Timer Current:

- 300 nA @ 1.8V, typical

• Secondary Oscillator:

Saving

• 16-Level Deep Hardware Stack with Optional

Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

- FSRs can read program and data memory

- 500 nA @ 32 kHz, 1.8V, typical

Analog Features:

Memory

•

Analog-to-Digital Converter (ADC):

- 10-bit resolution, up to 14 channels

- Conversion available during Sleep

- Dedicated ADC RC oscillator

• Up to 14 Kbytes Self-Write/Read Flash Program

Memory Addressing

• Up to 256 Bytes Data Memory Addressing

• High-Endurance Flash Data Memory (HEF)

- 128B of nonvolatile data storage

- 100K erase/write cycles

- Fixed Voltage Reference (FVR) as channel

• Integrated Temperature Indicator

• Voltage Reference module:

- Fixed Voltage Reference (FVR) with 1.024V

and 2.048V output levels

Flexible Oscillator Structure:

• 16 MHz Internal Oscillator Block:

- Accuracy to ± 3%, typical

Peripheral Highlights:

- Software selectable frequency range from

16 MHz to 31.25 kHz

• Up to 36 I/O Pins and 1 Input-only Pin:

- High current 25 mA sink/source

• 31 kHz Low-Power Internal Oscillator

• Three External Clock modes up to 20 MHz

• Two-Speed Oscillator Start-up

- Individually programmable weak pull-ups

- Individually programmable interrupt-on-

change (IOC) pins

• Low-Power RTC Implementation via LPT1OSC

• Integrated LCD Controller:

- At least 19 segment pins and as many as 116

total segments

Special Microcontroller Features:

- Variable clock input

• Operating Voltage Range:

- 1.8V-3.6V

- Contrast control

- Internal voltage reference selections

• Self-Programmable under Software Control

• Power-on Reset (POR)

• Timer0: 8-Bit Timer/Counter with 8-Bit

Programmable Prescaler

• Power-up Timer (PWRT)

• Low-Power Brown-Out Reset (LPBOR)

 2011-2016 Microchip Technology Inc.

DS40001569D-page 1

PIC16LF1904/6/7

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Dedicated low-power 32 kHz oscillator driver

• Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART):

- RS-232, RS-485 and LIN compatible

- Auto-Baud Detect

- Auto-wake-up on start

PIC16LF190X Family Types

LCD

Device

PIC16LF1902

PIC16LF1903

PIC16LF1904

PIC16LF1906

PIC16LF1907

(1)

(2)

2048

4096

8192

128

256

512

128

25

36

25

36

11

14

11

14

1/1

—

1

4

19 72⁽³⁾

29 116

H

Y

I/H

1

19 72⁽³⁾I/H

1

29

116

I/H

Note 1: Debugging Methods: (I) – Integrated on Chip; (H) – using Debug Header; (E) – using Emulation Header.

2: One pin is input-only.

3: COM3 and SEG15 share a pin, so the total segments are limited to 72 for 28-pin devices.

Data Sheet Index: (Unshaded devices are described in this document.)

1: DS40001455

2: DS40001569

PIC16LF1902/3 Data Sheet, 28-Pin Flash, 8-bit Microcontrollers.

PIC16LF1904/6/7 Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers.

Note:

For other small form-factor package availability and marking information, please visit

http://www.microchip.com/packaging or contact your local sales office.

DS40001569D-page 2

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 1:

28-PIN PDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16LF1906

RB7/ICSPDAT/ICDDAT/SEG13

RB6/ICSPCLK/ICDCLK/SEG14

RB5/AN13/COM1

28

27

26

25

1

2

3

4

5

6

VPP/MCLR/RE3

SEG12/AN0/RA0

SEG7/AN1/RA1

RB4/AN11/COM0

COM2/AN2/RA2

24

23

RB3/AN9/SEG26/VLCD3

RB2/AN8/SEG25/VLCD2

RB1/AN10/SEG24/VLCD1

RB0/AN12/INT/SEG0

SEG15/COM3/VREF+/AN3/RA3

SEG4/T0CKI/RA4

22

21

20

19

18

17

16

15

SEG5/AN4/RA5

VSS

7

8

9

VDD

SEG2/CLKIN/RA7

SEG1/CLKOUT/RA6

T1CKI/T1OSO/RC0

VSS

10

11

RC7/RX/DT/SEG8

RC6/TX/CK/SEG9

RC5/SEG10

12

13

14

T1OSI/RC1

SEG3/RC2

RC4/T1G/SEG11

SEG6/RC3

 2011-2016 Microchip Technology Inc.

DS40001569D-page 3

PIC16LF1904/6/7

FIGURE 2:

28-PIN UQFN PACKAGE DIAGRAM FOR PIC16LF1906

COM2/AN2/RA2

SEG15/COM3/VREF+/AN3/RA3

SEG4/T0CKI/RA4

RB3/AN9/SEG26/VLCD3

1

2

3

4

5

6

7

21

20 RB2/AN8/SEG25/VLCD2

19 RB1/AN10/SEG24/VLCD1

PIC16LF1906

SEG5/AN4/RA5

18

17

16

15

RB0/AN12/INT/SEG0

VSS

VDD

SEG2/CLKIN/RA7

SEG1/CLKOUT/RA6

VSS

RC7/RX/DT/SEG8

DS40001569D-page 4

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 3:

40-PIN PDIP PACKAGE DIAGRAM FOR PIC16LF1904/7

RB7/ICSPDAT/ICDDAT/SEG13

RB6/ICSPCLK/ICDCLK/SEG14

RB5/AN13/COM1

VPP/MCLR/RE3

SEG12/AN0/RA0

40

39

38

37

36

35

1

2

3

4

5

6

SEG7/AN1/RA1

COM2/AN2/RA2

RB4/AN11/COM0

RB3/AN9/SEG26/VLCD3

SEG15/VREF+/AN3/RA3

SEG4/T0CKI/RA4

RB2/AN8/SEG25/VLCD2

RB1/AN10/SEG24/VLCD1

RB0/AN12/INT/SEG0

SEG5/AN4/RA5

SEG21/AN5/RE0

34

33

32

31

30

7

8

9

VDD

SEG22/AN6/RE1

SEG23/AN7/RE2

VDD

VSS

10

11

RD7/SEG20

RD6/SEG19

VSS

29

12

SEG2/CLKIN/RA7

RD5/SEG18

28

27

26

25

13

14

15

16

RD4/SEG17

SEG1/CLKOUT/RA6

T1CKI/T1OSO/RC0

T1OSI/RC1

RC7/RX/DT/SEG8

RC6/TX/CK/SEG9

RC5/SEG10

SEG3/RC2

SEG6/RC3

24

23

17

18

RC4/T1G/SEG11

RD3/SEG16

COM3/RD0

SEG27/RD1

22

21

19

20

RD2/SEG28

 2011-2016 Microchip Technology Inc.

DS40001569D-page 5

PIC16LF1904/6/7

FIGURE 4:

44-PIN TQFP (10X10) PACKAGE DIAGRAM FOR PIC16LF1904/7

SEG8/DT/RX/RC7

SEG17/RD4

33

32

31

30

NC

1

RC0/T1OSO/T1CKI

RA6/CLKOUT/SEG1

RA7/CLKIN/SEG2

2

3

4

SEG18/RD5

SEG19/RD6

SEG20/RD7

VSS

VDD

29

28

5

6

PIC16LF1904/7

VSS

RE2/AN7/SEG23

RE1/AN6/SEG22

RE0/AN5/SEG21

RA5/AN4/SEG5

RA4/T0CKI/SEG4

27

26

25

24

23

VDD

7

8

SEG0/INT/AN12/RB0

VLCD1/SEG24/AN10/RB1

VLCD2/SEG25/AN8/RB2

VLCD3/SEG26/AN9/RB3

9

10

11

DS40001569D-page 6

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 5:

40-PIN UQFN (5X5) PACKAGE DIAGRAM FOR PIC16LF1904/7

SEG8/DT/RX/RC7

SEG17/RD4

1

2

30 RC0/T1OSO/T1CKI

SEG18/RD5

3

29

28

27

26

25

24

23

22

21

RA6/CLKOUT/SEG1

RA7/CLKIN/SEG2

VSS

4

SEG19/RD6

SEG20/RD7

5

PIC16LF1904/7

VSS

VDD

6

VDD

RE2/AN7/SEG23

RE1/AN6/SEG22

RE0/AN5/SEG21

RA5/AN4/SEG5

RA4/T0CKI/SEG4

7

SEG0/INT/AN12/RB0

VLCD1/SEG24/AN10/RB1

VLCD2/SEG25/AN8/RB2

8

9

10

 2011-2016 Microchip Technology Inc.

DS40001569D-page 7

PIC16LF1904/6/7

TABLE 1:

28/40/44-PIN ALLOCATION TABLE (PIC16LF1904/6/7)

RA0

RA1

RA2

RA3

2

3

4

5

27

28

1

2

3

4

5

19

20

21

22

17

18

19

20

AN0

AN1

AN2

—

SEG12

SEG7

COM2

—

2

AN3/

VREF+

SEG15/

COM3⁽²⁾

RA4

RA5

6

7

3

4

6

23

24

31

30

8

21

22

29

28

8

—

AN4

—

T0CKI

—

SEG4

SEG5

SEG1

SEG2

SEG0

—

Y

—

7

RA6

RA7

RB0

10

9

7

14

13

33

—

CLKOUT

CLKIN

—

6

—

21

18

AN12

—

INT/

IOC

RB1

RB2

RB3

22

23

24

19

20

21

34

35

36

9

AN10

AN8

AN9

—

VLCD1/

SEG24

IOC

Y

—

10

11

10

11

VLCD2/

SEG25

VLCD3/

SEG26

RB4

RB5

RB6

25

26

27

22

23

24

37

38

39

14

15

16

12

13

14

AN11

AN13

—

COM0

COM1

SEG14

IOC

Y

—

ICSPCLK/

ICDCLK

RB7

RC0

28

11

25

8

40

15

17

32

15

30

—

SEG13

—

IOC

—

Y

ICSPDAT/

ICDDAT

T1OSO/

T1CKI

—

RC1

RC2

RC3

RC4

RC5

RC6

RC7

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

RE0

RE1

RE2

12

13

14

15

16

17

18

—

9

16

17

18

23

24

25

26

19

20

21

22

27

28

29

30

8

35

36

37

42

43

44

1

31

32

33

38

39

40

1

—

T1OSI

—

10

11

12

13

14

15

—

SEG3

—

SEG6

—

T1G

—

SEG11

SEG10

SEG9

—

TX/CK

RX/DT

—

SEG8

38

39

40

41

2

34

35

36

37

2

—

COM3⁽³⁾

SEG27

SEG28

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

—

3

—

4

—

5

—

25

26

27

23

24

25

AN5⁽⁴⁾

AN6⁽⁴⁾

AN7⁽⁴⁾

—

9

—

10

—

RE3

VDD

Vss

NC

1

20

26

17

1

18

16

7, 26

6, 27

—

Y⁽¹⁾

—

MCLR/VPP

VDD

11,32

12,31

—

7,28

6,29

8,19

—

5,16

—

VSS

12,13,

33,34

—

VDD

Note 1: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.

2: 28-pin only pin location (PIC16LF1906). Location different on 40/44-pin device.

3: 40/44-pin only pin location (PIC16LF1904/7). Location different on 28-pin device.

4: ADC channel is reserved on the PIC16LF1906 28-pin devices.

DS40001569D-page 8

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 10

2.0 Enhanced Mid-range CPU ......................................................................................................................................................... 15

3.0 Memory Organization................................................................................................................................................................. 16

4.0 Device Configuration.................................................................................................................................................................. 38

5.0 Resets ........................................................................................................................................................................................ 43

6.0 Oscillator Module........................................................................................................................................................................ 51

7.0 Interrupts .................................................................................................................................................................................... 60

8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 71

9.0 Watchdog Timer ......................................................................................................................................................................... 73

10.0 Flash Program Memory Control ................................................................................................................................................. 77

11.0 I/O Ports ..................................................................................................................................................................................... 93

12.0 Interrupt-On-Change ................................................................................................................................................................ 109

13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 112

14.0 Temperature Indicator Module.................................................................................................................................................. 114

15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 115

16.0 Timer0 Module ......................................................................................................................................................................... 128

17.0 Timer1 Module with Gate Control............................................................................................................................................. 130

18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 142

19.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 171

20.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 205

21.0 Instruction Set Summary.......................................................................................................................................................... 207

22.0 Electrical Specifications............................................................................................................................................................ 221

23.0 DC and AC Characteristics Graphs and Charts....................................................................................................................... 238

24.0 Development Support............................................................................................................................................................... 239

25.0 Packaging Information.............................................................................................................................................................. 243

Appendix A: Data Sheet Revision History.......................................................................................................................................... 261

The Microchip WebSite...................................................................................................................................................................... 262

Customer Change Notification Service .............................................................................................................................................. 262

Customer Support.............................................................................................................................................................................. 262

Product Identification System ............................................................................................................................................................ 263

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

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enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Website; http://www.microchip.com

Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

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 2011-2016 Microchip Technology Inc.

DS40001569D-page 9

PIC16LF1904/6/7

1.0

DEVICE OVERVIEW

The PIC16LF1904/6/7 are described within this data

sheet. They are available in 28, 40 and 44-pin

packages. Figure 1-1 shows a block diagram of the

PIC16LF1904/6/7 devices. Table 1-2 shows the pinout

descriptions.

Reference Table 1-1 for peripherals available per

device.

TABLE 1-1:

DEVICE PERIPHERAL

SUMMARY

Peripheral

ADC

●

EUSART

Fixed Voltage Reference (FVR)

●

LCD

Temperature Indicator

Timers

Timer0

Timer1

●

DS40001569D-page 10

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 1-1:

PIC16LF1904/6/7 BLOCK DIAGRAM

Program

Flash Memory

RAM

PORTA

PORTB

CLKOUT

CLKIN

Timing

Generation

CPU

PORTC

PORTD

PORTE

INTRC

Oscillator

Figure 2-1

MCLR

LCD

Timer1

EUSART

Timer0

Temp.

Indicator

ADC

10-Bit

FVR

Note 1: See applicable chapters for more information on peripherals.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 11

PIC16LF1904/6/7

TABLE 1-2:

PIC16LF1904/6/7 PINOUT DESCRIPTION

Input Output

Name

Function

Description

Type

RA0/AN0/SEG12

RA1/AN1/SEG7

RA2/AN2/COM2

RA0

AN0

TTL

AN

—

CMOS General purpose I/O.

—

A/D Channel 0 input.

LCD Analog output.

SEG12

AN

RA1

AN1

TTL

AN

—

CMOS General purpose I/O.

—

A/D Channel 1 input.

LCD Analog output.

SEG7

AN

RA2

AN2

TTL

AN

—

CMOS General purpose I/O.

—

A/D Channel 2 input.

LCD Analog output.

COM2

RA3

AN

(2)

RA3/AN3/VREF+/COM3

SEG15

/

TTL

AN

—

CMOS General purpose I/O.

AN3

—

A/D Channel 3 input.

VREF+

COM3

SEG15

A/D Voltage Reference input.

LCD Analog output.

AN

—

LCD Analog output.

RA4/T0CKI/SEG4

RA5/AN4/SEG5

RA4

TTL

ST

—

CMOS General purpose I/O.

T0CKI

SEG4

—

Timer0 clock input.

LCD Analog output.

AN

RA5

AN4

TTL

AN

—

CMOS General purpose I/O.

—

A/D Channel 4 input.

LCD Analog output.

SEG5

AN

RA6/CLKOUT/SEG1

RA6

CLKOUT

SEG1

TTL

—

CMOS General purpose I/O.

CMOS FOSC/4 output.

—

AN

LCD Analog output.

RA7/CLKIN/SEG2

RA7

CLKIN

SEG2

RB0

TTL

CMOS

—

CMOS General purpose I/O.

—

External clock input (EC mode).

LCD Analog output.

AN

RB0/AN12/INT/SEG0

TTL

AN

CMOS General purpose I/O.

AN12

INT

—

A/D Channel 12 input.

External interrupt.

ST

SEG0

RB1

—

AN

LCD Analog output.

(1)

RB1 /AN10/SEG24/VLCD1

TTL

AN

CMOS General purpose I/O.

AN10

SEG24

VLCD1

RB2

—

AN

—

A/D Channel 10 input.

LCD Analog output.

LCD analog input.

—

AN

(1)

RB2 /AN8/SEG25/VLCD2

TTL

AN

CMOS General purpose I/O.

AN8

—

AN

—

A/D Channel 8 input.

LCD Analog output.

LCD analog input.

SEG25

VLCD2

—

AN

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open-Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: These pins have interrupt-on-change functionality.

2: PIC16LF1906/7 only.

DS40001569D-page 12

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 1-2:

PIC16LF1904/6/7 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

(1)

RB3 /AN9/SEG26/VLCD3

RB3

AN9

TTL

AN

—

CMOS General purpose I/O.

—

AN

—

A/D Channel 9 input.

LCD Analog output.

LCD analog input.

SEG26

VLCD3

AN

(1)

RB4 /AN11/COM0

RB4

AN11

COM0

TTL

AN

—

CMOS General purpose I/O.

—

A/D Channel 11 input.

LCD Analog output.

AN

(1)

RB5 /AN13/COM1

RB5

AN13

COM1

TTL

AN

—

CMOS General purpose I/O.

—

A/D Channel 13 input.

LCD Analog output.

AN

(1)

RB6 /ICSPCLK/ICDCLK/

RB6

TTL

ST

—

CMOS General purpose I/O.

SEG14

ICSPCLK

ICDCLK

SEG14

—

Serial Programming Clock.

In-Circuit Debug Clock.

LCD Analog output.

AN

(1)

RB7 /ICSPDAT/ICDDAT/

RB7

TTL

ST

—

CMOS General purpose I/O.

Serial Programming Clock.

CMOS In-Circuit Data I/O.

AN LCD Analog output.

CMOS General purpose I/O.

XTAL Timer1 oscillator connection.

Timer1 clock input.

SEG13

ICSPDAT

ICDDAT

SEG13

—

RC0/T1OSO/T1CKI

RC0

TTL

XTAL

ST

T1OSO

T1CKI

—

RC1/T1OSI

RC2/SEG3

RC1

TTL

CMOS General purpose I/O.

T1OSI

XTAL

XTAL Timer1 oscillator connection.

RC2

TTL

—

CMOS General purpose I/O.

SEG3

AN

CMOS General purpose I/O.

AN LCD Analog output.

LCD Analog output.

RC3/SEG6

RC3

TTL

—

SEG6

RC4/T1G/SEG11

RC4

T1G

TTL

XTAL

—

CMOS General purpose I/O.

XTAL Timer1 oscillator connection.

SEG11

AN

CMOS General purpose I/O.

AN LCD Analog output.

LCD Analog output.

RC5/SEG10

RC5

TTL

—

SEG10

RC6/TX/CK/SEG9

RC6

TX

TTL

—

CMOS General purpose I/O.

CMOS USART asynchronous transmit.

CMOS USART synchronous clock.

CK

ST

—

SEG9

AN

LCD Analog output.

RC7/RX/DT/SEG8

RC7

RX

TTL

ST

—

CMOS General purpose I/O.

—

USART asynchronous input.

DT

CMOS USART synchronous data.

SEG8

AN

LCD Analog output.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open-Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: These pins have interrupt-on-change functionality.

2: PIC16LF1906/7 only.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 13

PIC16LF1904/6/7

TABLE 1-2:

PIC16LF1904/6/7 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

(2)

RD0 /COM3

RD0

TTL

—

CMOS General purpose I/O.

COM3

AN

CMOS General purpose I/O.

AN LCD Analog output.

CMOS General purpose I/O.

AN LCD Analog output.

CMOS General purpose I/O.

AN LCD Analog output.

CMOS General purpose I/O.

AN LCD Analog output.

CMOS General purpose I/O.

AN LCD Analog output.

CMOS General purpose I/O.

AN LCD Analog output.

CMOS General purpose I/O.

AN LCD Analog output.

CMOS General purpose I/O.

LCD Analog output.

(2)

RD1 /SEG27

RD1

TTL

—

SEG27

(2)

RD2 /SEG28

RD2

TTL

—

SEG28

(2)

RD3 /SEG16

RD3

TTL

—

SEG16

(2)

RD4 /SEG17

RD4

TTL

—

SEG17

(2)

RD5 /SEG18

RD5

TTL

—

SEG18

(2)

RD6 /SEG19

RD6

TTL

—

SEG19

(2)

RD7 /SEG20

RD7

TTL

—

SEG20

(2)

RE0 /AN5/SEG21

RE0

AN5

TTL

AN

—

A/D Channel 5 input.

LCD Analog output.

SEG21

AN

(2)

RE1 /AN6/SEG22

RE1

AN6

TTL

AN

—

CMOS General purpose I/O.

—

A/D Channel 6 input.

LCD Analog output.

SEG22

AN

(2)

RE2 /AN7/SEG23

RE2

AN7

TTL

AN

—

CMOS General purpose I/O.

—

A/D Channel 7 input.

LCD Analog output.

SEG23

AN

RE3/MCLR/VPP

RE3

MCLR

VPP

TTL

ST

CMOS General purpose I/O.

—

Master Clear with internal pull-up.

HV

Programming voltage.

Positive supply.

VDD

VSS

VDD

Power

VSS

Ground reference.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open-Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: These pins have interrupt-on-change functionality.

2: PIC16LF1906/7 only.

DS40001569D-page 14

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

2.0

ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range

8-bit CPU core. The CPU has 49 instructions. Interrupt

capability includes automatic context saving. The

hardware stack is 16 levels deep and has Overflow and

Underflow Reset capability. Direct, Indirect, and

Relative addressing modes are available. Two File

Select Registers (FSRs) provide the ability to read

program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1

Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically

saved in shadow registers and restored when returning

from the interrupt. This saves stack space and user

code. See Section 7.5 “Automatic Context Saving”,

for more information.

2.2

16-Level Stack with Overflow and

Underflow

These devices have an external stack memory 15 bits

wide and 16 words deep. A Stack Overflow or Under-

flow will set the appropriate bit (STKOVF or STKUNF)

in the PCON register, and if enabled, will cause a soft-

ware Reset. See Section 3.4 “Stack” for more details.

2.3

File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs

can access all file registers and program memory,

which allows one Data Pointer for all memory. When an

FSR points to program memory, there is one additional

instruction cycle in instructions using INDF to allow the

data to be fetched. General purpose memory can now

also be addressed linearly, providing the ability to

access contiguous data larger than 80 bytes. There are

also new instructions to support the FSRs. See

Section 3.5 “Indirect Addressing” for more details.

2.4

Instruction Set

There are 49 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 21.0 “Instruction Set Summary” for more

details.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 15

PIC16LF1904/6/7

FIGURE 2-1:

CORE BLOCK DIAGRAM

15

Configuration

8

15

Data Bus

RAM

Program Counter

Flash

Program

Memory

186-LLeevveellSStatacckk

(153-bit)

Program

Bus

14

RAM Addr

Program Memory

Read (PMR)

12

Addr MUX

IInnssttrruuccttiioonnRreegg

Indirect

Addr

7

Direct Addr

12

5

BSR Reg

FSR reg

15

FSR0 Reg

reg

FSR1 Reg

FSR reg

15

SSTTAATTUUSSRreegg

8

3

MUX

Power-up

Timer

Oscillator

Instruction

DDeeccooddeea&nd

Control

Start-up Timer

ALU

Power-on

Reset

CLKIN

8

Timing

Generation

Watchdog

Timer

W Reg

CLKOUT

Brown-out

Reset

Internal

Oscillator

Block

VDD

VSS

DS40001569D-page 16

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

3.1

Program Memory Organization

3.0

MEMORY ORGANIZATION

The enhanced mid-range core has a 15-bit program

counter capable of addressing 32K x 14 program

memory space. Table 3-1 shows the memory sizes

implemented for the PIC16LF1904/6/7 family. Accessing

a location above these boundaries will cause a wrap-

around within the implemented memory space. The

Reset vector is at 0000h and the interrupt vector is at

0004h (see Figures 3-1, and 3-2).

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

- User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

The following features are associated with access and

control of program memory and data memory:

• PCL and PCLATH

• Stack

• Indirect Addressing

TABLE 3-1:

Device

DEVICE SIZES AND ADDRESSES

Program Memory

Space (Words)

Last Program Memory

Address

High-Endurance Flash

Memory Address Range ⁽¹⁾

PIC16LF1904

4,096

8,192

0FFFh

1FFFh

0F80h-0FFFh

1F80h-1FFFh

PIC16LF1906/7

Note 1: High-endurance Flash applies to low byte of each address in the range.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 17

PIC16LF1904/6/7

FIGURE 3-1:

PROGRAM MEMORY MAP

AND STACK FOR

PIC16LF1904

FIGURE 3-2:

PROGRAM MEMORY MAP

AND STACK FOR

PIC16LF1906/7

PC<14:0>

15

PC<14:0>

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

15

Stack Level 0

Stack Level 1

Stack Level 0

Stack Level 1

Stack Level 15

Reset Vector

Stack Level 15

Reset Vector

0000h

Interrupt Vector

Page 0

0004h

0005h

Interrupt Vector

Page 0

0004h

0005h

On-chip

Program

Memory

07FFh

0800h

07FFh

0800h

Page 1

Page 2

On-chip

Program

Memory

0FFFh

1000h

0FFFh

1000h

Rollover to Page 0

17FFh

1800h

Page 3

1FFFh

2000h

Rollover to Page 0

Rollover to Page 1

Rollover to Page 3

7FFFh

DS40001569D-page 18

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

3.1.1

READING PROGRAM MEMORY AS

DATA

EXAMPLE 3-2:

ACCESSING PROGRAM

MEMORY VIA FSR

constants

RETLW DATA0

There are two methods of accessing constants in pro-

gram memory. The first method is to use tables of

RETLW instructions. The second method is to set an

FSR to point to the program memory.

;Index0 data

;Index1 data

RETLW DATA1

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

3.1.1.1

RETLWInstruction

MOVLW

MOVWF

MOVLW

MOVWF

LOW constants

FSR1L

HIGH constants

FSR1H

The RETLWinstruction can be used to provide access

to tables of constants. The recommended way to create

such a table is shown in Example 3-1.

MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

EXAMPLE 3-1:

RETLW INSTRUCTION

constants

BRW

;Add Index in W to

;program counter to

;select data

RETLW DATA0

RETLW DATA1

RETLW DATA2

RETLW DATA3

;Index0 data

;Index1 data

my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

call constants

;… THE CONSTANT IS IN W

The BRWinstruction makes this type of table very sim-

ple to implement. If your code must remain portable

with previous generations of microcontrollers, then the

BRWinstruction is not available so the older table read

method must be used.

3.1.1.2

Indirect Read with FSR

The program memory can be accessed as data by set-

ting bit 7 of the FSRxH register and reading the match-

ing INDFx register. The MOVIWinstruction will place the

lower eight bits of the addressed word in the W register.

Writes to the program memory cannot be performed via

the INDF registers. Instructions that access the pro-

gram memory via the FSR require one extra instruction

cycle to complete. Example 3-2 demonstrates access-

ing the program memory via an FSR.

The HIGH directive will set bit<7> if a label points to a

location in program memory.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 19

PIC16LF1904/6/7

3.2.1

CORE REGISTERS

3.2

Data Memory Organization

The core registers contain the registers that directly

affect the basic operation. The core registers occupy

the first 12 addresses of every data memory bank

(addresses x00h/x08h through x0Bh/x8Bh). These

registers are listed below in Table 3-2. For detailed

information, see Table 3-4.

The data memory is partitioned in 32 memory banks

with 128 bytes in a bank. Each bank consists of

(Figure 3-3):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

TABLE 3-2:

CORE REGISTERS

The active bank is selected by writing the bank number

into the Bank Select Register (BSR). Unimplemented

memory will read as ‘0’. All data memory can be

accessed either directly (via instructions that use the

file registers) or indirectly via the two File Select

Registers (FSR). See Section 3.5 “Indirect

Addressing” for more information.

Addresses

BANKx

x00h or x80h

x01h or x81h

x02h or x82h

x03h or x83h

x04h or x84h

x05h or x85h

x06h or x86h

x07h or x87h

x08h or x88h

x09h or x89h

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

Data memory uses a 12-bit address. The upper seven

bits of the address define the Bank Address and the

lower five bits select the registers/RAM in that bank.

WREG

PCLATH

INTCON

x0Ah or x8Ah

x0Bh or x8Bh

DS40001569D-page 20

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u= unchanged).

3.2.1.1

STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section 21.0

“Instruction Set Summary”).

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note:

The C and DC bits operate as Borrow and

Digit Borrow out bits, respectively, in

subtraction.

REGISTER 3-1:

STATUS: STATUS REGISTER

U-0

—

U-0

—

U-0

—

R-1/q

TO

R-1/q

PD

R/W-0/u

Z

R/W-0/u

DC⁽¹⁾

R/W-0/u

C⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-5

bit 4

Unimplemented: Read as ‘0’

TO: Time-out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

bit 3

bit 2

bit 1

bit 0

PD: Power-Down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)⁽¹⁾

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

C: Carry/Borrow bit⁽¹⁾(ADDWF, ADDLW, SUBLW, SUBWF instructions)⁽¹⁾

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 21

PIC16LF1904/6/7

3.2.2

SPECIAL FUNCTION REGISTER

FIGURE 3-3:

BANKED MEMORY

PARTITIONING

The Special Function Registers are registers used by

the application to control the desired operation of

peripheral functions in the device. The Special Function

Registers occupy the 20 bytes after the core registers of

every data memory bank (addresses x0Ch/x8Ch

through x1Fh/x9Fh). The registers associated with the

operation of the peripherals are described in the

appropriate peripheral chapter of this data sheet.

Memory Region

7-bit Bank Offset

00h

Core Registers

(12 bytes)

0Bh

0Ch

3.2.3

GENERAL PURPOSE RAM

Special Function Registers

(20 bytes maximum)

There are up to 80 bytes of GPR in each data memory

bank. The Special Function Registers occupy the 20

bytes after the core registers of every data memory

bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

1Fh

20h

3.2.3.1

Linear Access to GPR

The general purpose RAM can be accessed in a non-

banked method via the FSRs. This can simplify access

to large memory structures. See Section 3.5.2 “Linear

Data Memory” for more information.

General Purpose RAM

(80 bytes maximum)

3.2.4

COMMON RAM

There are 16 bytes of common RAM accessible from all

banks.

6Fh

70h

Common RAM

(16 bytes)

7Fh

3.2.5

DEVICE MEMORY MAPS

The memory maps for PIC16LF1904/6/7 are as shown

in Table 3-3.

DS40001569D-page 22

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 3-3:

PIC16LF1904/6/7 MEMORY MAP (CONTINUED)

BANK 15

BANK 31

780h

F80h

Core Registers

(Table 3-2)

Core Registers

(Table 3-2)

78Bh

78Ch

F8Bh

F8Ch

Unimplemented

Read as ‘0’

790h

791h

792h

793h

794h

795h

796h

797h

798h

799h

FE3h

FE4h

FE5h

FE6h

FE7h

FE8h

FE9h

FEAh

FEBh

FECh

STATUS_SHAD

WREG_SHAD

BSR_SHAD

PCLATH_SHAD

FSR0L_SHAD

FSR0H_SHAD

FSR1L_SHAD

FSR1H_SHAD

—

LCDCON

LCDPS

LCDREF

LCDCST

LCDRL

—

LCDSE0

LCDSE1

LCDSE2⁽¹⁾

79Ah

79Bh

79Ch

FEDh

FEEh

FEFh

FF0h

STKPTR

TOSL

LCDSE3

TOSH

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

79Fh

7A0h

7A1h

7A2h

7A3h

7A4h

7A5h

7A6h

7A7h

7A8h

7A9h

7AAh

7ABh

7ACh

7ADh

7AEh

7AFh

7B0h

7B1h

7B2h

7B3h

7B4h

7B5h

7B6h

7B7h

7B8h

LCDDATA0

LCDDATA1

LCDDATA2⁽¹⁾

LCDDATA3

LCDDATA4

LCDDATA5⁽¹⁾

LCDDATA6

LCDDATA7

LCDDATA8⁽¹⁾

LCDDATA9

LCDDATA10

LCDDATA11⁽¹⁾

LCDDATA12

—

FFFh

—

LCDDATA15

—

LCDDATA18

—

LCDDATA21

—

Unimplemented

Read as ‘0’

7EFh

Legend:

= Unimplemented data memory locations, read as ‘0’.

Note 1: PIC16LF1904/7 only.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 25

PIC16LF1904/6/7

3.2.6

CORE FUNCTION REGISTERS

SUMMARY

The Core Function registers listed in Table 3-4 can be

addressed from any Bank.

TABLE 3-4:

CORE FUNCTION REGISTERS SUMMARY

Value on

POR, BOR other Resets

Value on all

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 0-31

x00h or

x80h

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

INDF0

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 0000 0000 0000

x01h or

x81h

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

INDF1

PCL

x02h or

x82h

Program Counter (PC) Least Significant Byte

x03h or

x83h

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

—

TO

PD

Z

DC

C

x04h or

x84h

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

x05h or

x85h

x06h or

x86h

x07h or

x87h

x08h or

x88h

—

BSR4

BSR3

BSR2

BSR1

INTF

BSR0

IOCIF

x09h or

x89h

WREG

PCLATH

INTCON

Working Register

x0Ahor

x8Ah

—

Write Buffer for the upper 7 bits of the Program Counter

PEIE TMR0IE INTE IOCIE TMR0IF

x0Bhor

x8Bh

GIE

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

DS40001569D-page 26

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 3-5:

SPECIAL FUNCTION REGISTER SUMMARY

Value on all

Value on

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

other

POR, BOR

Resets

Bank 0

00Ch PORTA

00Dh PORTB

00Eh PORTC

00Fh PORTD⁽³⁾

010h PORTE

011h PIR1

PORTA Data Latch when written: PORTA pins when read

PORTB Data Latch when written: PORTB pins when read

PORTC Data Latch when written: PORTC pins when read

PORTD Data Latch when written: PORTD pins when read

xxxx xxxx uuuu uuuu

—

RE3

—

RE2⁽²⁾

—

RE1⁽²⁾

—

RE0⁽²⁾---- xxxx ---- uuuu

TMR1GIF

ADIF

RCIF

TXIF

TMR1IF 0000 ---0 0000 ---0

012h PIR2

—

LCDIF

—

---0 -0-- ---0 -0--

013h

014h

—

Unimplemented

—

Unimplemented

015h TMR0

Timer0 Module Register

xxxx xxxx uuuu uuuu

016h TMR1L

017h TMR1H

018h T1CON

019h T1GCON

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

—

TMR1ON 0000 00-0 uuuu uu-u

T1GSS0 0000 0x00 uuuu uxuu

TMR1GE T1GPOL

T1GTM

T1GSPM

T1GGO/

DONE

T1GVAL

T1GSS1

01Ah

to

—

Unimplemented

—

01Fh

Bank 1

08Ch TRISA

08Dh TRISB

08Eh TRISC

08Fh TRISD⁽³⁾

090h TRISE

091h PIE1

PORTA Data Direction Register

PORTB Data Direction Register

PORTC Data Direction Register

PORTD Data Direction Register

1111 1111 1111 1111

(2)

—

TRISE2⁽³⁾TRISE1⁽³⁾TRISE0⁽³⁾---- 1111 ---- 1111

TMR1GIE

ADIE

RCIE

TXIE

—

TMR1IE 0000 ---0 0000 ---0

—

092h PIE2

—

LCDIE

—

---- -0-- ---- -0--

093h

094h

—

Unimplemented

—

095h OPTION_REG

096h PCON

WPUEN

INTEDG

T0CS

—

T0SE

PSA

PS2

RI

PS1

PS0

1111 1111 1111 1111

00-1 11qq qq-q qquu

STKOVF STKUNF

RWDT

RMCLR

POR

BOR

097h WDTCON

—

WDTPS4 WDTPS3

WDTPS2 WDTPS1 WDTPS0 SWDTEN --01 0110 --01 0110

098h

—

Unimplemented

—

099h OSCCON

09Ah OSCSTAT

09Bh ADRESL

09Ch ADRESH

09Dh ADCON0

09Eh ADCON1

—

IRCF3

—

IRCF2

OSTS

IRCF1

IRCF0

—

SCS1

SCS0

-011 1-00 -011 1-00

T1OSCR

HFIOFR

LFIOFR

HFIOFS 0-q0 --00 q-qq --0q

xxxx xxxx uuuu uuuu

A/D Result Register Low

A/D Result Register High

xxxx xxxx uuuu uuuu

—

CHS4

CHS3

CHS2

CHS1

—

CHS0

—

GO/DONE

ADON

-000 0000 -000 0000

ADFM

ADCS2

ADCS1

ADCS0

ADPREF1 ADPREF0 0000 ---- 0000 ----

09Fh

—

Unimplemented

—

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

These registers can be addressed from any bank.

Unimplemented, read as ‘1’.

Note 1:

2:

3:

PIC16LF1904/7 only.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 27

PIC16LF1904/6/7

TABLE 3-5:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 2

10Ch LATA

10Dh LATB

10Eh LATC

10Eh LATD⁽³⁾

10Eh LATE⁽³⁾

111h

PORTA Data Latch

PORTB Data Latch

PORTC Data Latch

PORTD Data Latch

xxxx xxxx uuuu uuuu

—

LATE2

LATE1

—

LATE0 ---- -xxx ---- -uuu

to

—

Unimplemented

—

115h

116h BORCON

117h FVRCON

118h

SBOREN

FVREN

BORFS

—

BORRDY 10-- ---q uu-- ---u

FVRRDY

TSEN

TSRNG

ADFVR1 ADFVR0 0q00 --00 0q00 --00

to

11Fh

—

Unimplemented

—

Bank 3

18Ch ANSELA

18Dh ANSELB

—

ANSA5

ANSB5

—

ANSA3

ANSB3

ANSA2

ANSB2

ANSA1

ANSB1

ANSA0 --1- 1111 --11 1111

ANSB0 --11 1111 --11 1111

—

ANSB4

18Eh

18Fh

—

Unimplemented

—

190h ANSELE⁽³⁾

191h PMADRL

192h PMADRH

193h PMDATL

194h PMDATH

195h PMCON1

196h PMCON2

—

ANSE2

ANSE1

ANSE0 ---- -111 ---- -111

0000 0000 0000 0000

1000 0000 1000 0000

xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu

Program Memory Address Register Low Byte

(2)

—

Program Memory Address Register High Byte

Program Memory Read Data Register Low Byte

—

Program Memory Read Data Register High Byte

(2)

—

CFGS

LWLO

FREE

WRERR

WREN

WR

RD

1000 x000 1000 q000

0000 0000 0000 0000

Program Memory Control Register 2

Unimplemented

197h

198h

—

Unimplemented

199h RCREG

19Ah TXREG

19Bh SPBRG

19Ch SPBRGH

19Dh RCSTA

19Eh TXSTA

19Fh BAUD1CON

Bank 4

USART Receive Data Register

USART Transmit Data Register

0000 0000 0000 0000

0000 000x 0000 000x

0000 0010 0000 0010

BRG<7:0>

BRG<15:8>

SPEN

CSRC

RX9

TX9

SREN

TXEN

—

CREN

ADDEN

SENDB

BRG16

FERR

BRGH

—

OERR

TRMT

WUE

RX9D

TX9D

SYNC

SCKP

ABDOVF

RCIDL

ABDEN 01-0 0-00 01-0 0-00

20Ch

—

Unimplemented

—

20Dh WPUB

WPUB7

WPUB6

WPUB5

—

WPUB4

—

WPUB3

WPUE3

WPUB2

—

WPUB1

—

WPUB0 1111 1111 1111 1111

20Eh

20Fh

—

Unimplemented

—

210h WPUE

—

---- 1--- ---- 1---

211h

to

—

Unimplemented

—

21Fh

Bank 5

28Ch

—

Unimplemented

—

29Fh

Bank 6

30Ch

—

Unimplemented

—

31Fh

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

These registers can be addressed from any bank.

Unimplemented, read as ‘1’.

Note 1:

2:

3:

PIC16LF1904/7 only.

DS40001569D-page 28

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 3-5:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 7

38Ch

—

Unimplemented

—

393h

394h IOCBP

395h IOCBN

396h IOCBF

IOCBP7

IOCBN7

IOCBF7

IOCBP6

IOCBP5

IOCBN5

IOCBF5

IOCBP4

IOCBN4

IOCBF4

IOCBP3

IOCBN3

IOCBF3

IOCBP2

IOCBN2

IOCBF2

IOCBP1

IOCBN1

IOCBF1

IOCBP0 0000 0000 0000 0000

IOCBN0 0000 0000 0000 0000

IOCBF0 0000 0000 0000 0000

IOCBN6

IOCBF6

397h

—

Unimplemented

—

39Fh

Bank 8-14

x0Ch

or

x8Ch

to

x1Fh

or

—

Unimplemented

—

x9Fh

Bank 15

78Ch

—

790h

791h LCDCON

792h LCDPS

793h LCDREF

794h LCDCST

795h LCDRL

LCDEN

WFT

SLPEN

WERR

LCDA

LCDIRI

—

WA

CS1

LP3

CS0

LP2

LMUX1

LP1

LMUX0 000- 0011 000- 0011

BIASMD

—

LP0

—

0000 0000 0000 0000

0-0- 000- 0-0- 000-

LCDIRE

—

VLCD3PE VLCD2PE VLCD1PE

—

LCDCST2 LCDCST1 LCDCST0 ---- -000 ---- -000

LRLAP1

LRLAP0

LRLBP1

LRLBP0

LRLAT2

LRLAT1

LRLAT0 0000 -000 0000 -000

796h

797h

—

Unimplemented

—

798h LCDSE0

799h LCDSE1

79Ah LCDSE2

79Bh LCDSE3

SE7

SE15

SE23

—

SE6

SE5

SE13

SE21

—

SE4

SE12

SE20

SE28

SE3

SE11

SE19

SE27

SE2

SE10

SE18

SE26

SE1

SE9

SE0

SE8

0000 0000 uuuu uuuu

---0 0000 ---u uuuu

SE14

SE22

—

SE17

SE25

SE16

SE24

79Dh

—

Unimplemented

—

79Fh

7A0h LCDDATA0

7A1h LCDDATA1

7A2h LCDDATA2⁽³⁾

7A3h LCDDATA3

7A4h LCDDATA4

7A5h LCDDATA5⁽³⁾

7A6h LCDDATA6

7A7h LCDDATA7

7A8h LCDDATA8⁽³⁾

SEG7

COM0

SEG6

COM0

SEG5

COM0

SEG4

COM0

SEG3

COM0

SEG2

COM0

SEG1

COM0

SEG0

COM0

xxxx xxxx uuuu uuuu

SEG15

COM0

SEG14

COM0

SEG13

COM0

SEG12

COM0

SEG11

COM0

SEG10

COM0

SEG9

COM0

SEG8

COM0

SEG23

COM0

SEG22

COM0

SEG21

COM0

SEG20

COM0

SEG19

COM0

SEG18

COM0

SEG17

COM0

SEG16 xxxx xxxx uuuu uuuu

COM0

SEG7

COM1

SEG6

COM1

SEG5

COM1

SEG4

COM1

SEG3

COM1

SEG2

COM1

SEG1

COM1

SEG0

COM1

xxxx xxxx uuuu uuuu

SEG15

COM1

SEG14

COM1

SEG13

COM1

SEG12

COM1

SEG11

COM1

SEG10

COM1

SEG9

COM1

SEG8

COM1

SEG23

COM1

SEG22

COM1

SEG21

COM1

SEG20

COM1

SEG19

COM1

SEG18

COM1

SEG17

COM1

SEG16 xxxx xxxx uuuu uuuu

COM1

SEG7

COM2

SEG6

COM2

SEG5

COM2

SEG4

COM2

SEG3

COM2

SEG2

COM2

SEG1

COM2

SEG0

COM2

xxxx xxxx uuuu uuuu

SEG15

COM2

SEG14

COM2

SEG13

COM2

SEG12

COM2

SEG11

COM2

SEG10

COM2

SEG9

COM2

SEG8

COM2

SEG23

COM2

SEG22

COM2

SEG21

COM2

SEG20

COM2

SEG19

COM2

SEG18

COM2

SEG17

COM2

SEG16 xxxx xxxx uuuu uuuu

COM2

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

These registers can be addressed from any bank.

Unimplemented, read as ‘1’.

Note 1:

2:

3:

PIC16LF1904/7 only.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 29

PIC16LF1904/6/7

TABLE 3-5:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 15 (Continued)

7A9h LCDDATA9

SEG7

COM3

SEG6

COM3

SEG5

COM3

SEG4

COM3

SEG3

COM3

SEG2

COM3

SEG1

COM3

SEG0

COM3

xxxx xxxx uuuu uuuu

7AAh LCDDATA10

7ABh LCDDATA11⁽³⁾

7ACh LCDDATA12

SEG15

COM3

SEG14

COM3

SEG13

COM3

SEG12

COM3

SEG11

COM3

SEG10

COM3

SEG9

COM3

SEG8

COM3

SEG23

COM3

SEG22

COM3

SEG20

COM3

SEG19

COM3

SEG18

COM3

SEG17

COM3

SEG16

COM3

SEG15 xxxx xxxx uuuu uuuu

COM3

—

SEG28

COM0

SEG27

COM0

SEG26

COM0

SEG25

COM0

SEG24 ---x xxxx ---u uuuu

COM0

7ADh

7AEh

—

Unimplemented

—

7AFh LCDDATA15

—

SEG28

COM1

SEG27

COM1

SEG26

COM1

SEG25

COM1

SEG24 ---x xxxx ---u uuuu

COM1

7B0h

7B1h

—

Unimplemented

—

7B2h LCDDATA18

SEG28

COM2

SEG27

COM2

SEG26

COM2

SEG25

COM2

SEG24 ---x xxxx ---u uuuu

COM2

7B3h

7B4h

—

Unimplemented

—

7B5h LCDDATA21

SEG28

COM3

SEG27

COM3

SEG26

COM3

SEG25

COM3

SEG24 ---x xxxx ---u uuuu

COM3

7B6h

—

7EFh

—

Unimplemented

—

Bank 16-30

x0Ch

or

x8Ch

to

x1Fh

or

x9Fh

—

Bank 31

F8Ch

—

FE3h

—

Unimplemented

—

FE4h STATUS_SHAD

FE5h WREG_SHAD

FE6h BSR_SHAD

FE7h PCLATH_SHAD

FE8h FSR0L_SHAD

FE9h FSR0H_SHAD

FEAh FSR1L_SHAD

FEBh FSR1H_SHAD

FECh —

—

Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu

Working Register Normal (Non-ICD) Shadow

xxxx xxxx uuuu uuuu

—

Bank Select Register Normal (Non-ICD) Shadow

---x xxxx ---u uuuu

-xxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

Program Counter Latch High Register Normal (Non-ICD) Shadow

Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow

Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow

Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow

Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow

Unimplemented

—

FEDh

FEEh

FEFh

—

Current Stack Pointer

---1 1111 ---1 1111

xxxx xxxx uuuu uuuu

-xxx xxxx -uuu uuuu

STKPTR

TOSL

Top of Stack Low byte

Top of Stack High byte

—

TOSH

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

These registers can be addressed from any bank.

Unimplemented, read as ‘1’.

Note 1:

2:

3:

PIC16LF1904/7 only.

DS40001569D-page 30

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

3.3.2

COMPUTED GOTO

3.3

PCL and PCLATH

A computed GOTOis accomplished by adding an offset to

the program counter (ADDWF PCL). When performing a

table read using a computed GOTOmethod, care should

be exercised if the table location crosses a PCL memory

boundary (each 256-byte block). Refer to Application

Note AN556, “Implementing a Table Read” (DS00556).

The Program Counter (PC) is 15 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<14:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 3-4 shows the five

situations for the loading of the PC.

3.3.3

COMPUTED FUNCTION CALLS

FIGURE 3-4:

LOADING OF PC IN

A computed function CALLallows programs to maintain

tables of functions and provide another way to execute

state machines or look-up tables. When performing a

table read using a computed function CALL, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block).

DIFFERENT SITUATIONS

Instruction with

14

0

PCH

7

PCL

PCL as

PC

Destination

8

6

0

PCLATH

ALU Result

If using the CALLinstruction, the PCH<2:0> and PCL

registers are loaded with the operand of the CALL

instruction. PCH<6:3> is loaded with PCLATH<6:3>.

14

0

PCH

PCL

GOTO, CALL

PC

The CALLWinstruction enables computed calls by com-

bining PCLATH and W to form the destination address.

A computed CALLWis accomplished by loading the W

register with the desired address and executing CALLW.

The PCL register is loaded with the value of W and

PCH is loaded with PCLATH.

11

4

6

0

PCLATH

OPCODE <10:0>

14

0

PCH

7

PCL

CALLW

PC

3.3.4

BRANCHING

8

6

0

PCLATH

W

The branching instructions add an offset to the PC.

This allows relocatable code and code that crosses

page boundaries. There are two forms of branching,

BRW and BRA. The PC will have incremented to fetch

the next instruction in both cases. When using either

branching instruction, a PCL memory boundary may be

crossed.

14

0

PCH

PCL

PC

BRW

15

PC + W <8:0>

If using BRW, load the W register with the desired

unsigned address and execute BRW. The entire PC will

be loaded with the address PC + 1 + W.

14

0

PCH

PCL

PC

BRA

15

PC + OPCODE <8:0>

If using BRA, the entire PC will be loaded with PC + 1 +,

the signed value of the operand of the BRAinstruction.

3.3.1

MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<14:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

contents of the program counter to be changed by writ-

ing the desired upper seven bits to the PCLATH regis-

ter. When the lower eight bits are written to the PCL

register, all 15 bits of the program counter will change

to the values contained in the PCLATH register and

those being written to the PCL register.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 31

PIC16LF1904/6/7

3.4.1

ACCESSING THE STACK

3.4

Stack

The stack is available through the TOSH, TOSL and

STKPTR registers. STKPTR is the current value of the

Stack Pointer. TOSH:TOSL register pair points to the

TOP of the stack. Both registers are read/writable. TOS

is split into TOSH and TOSL due to the 15-bit size of the

PC. To access the stack, adjust the value of STKPTR,

which will position TOSH:TOSL, then read/write to

TOSH:TOSL. STKPTR is five bits to allow detection of

overflow and underflow.

All devices have a 16-level x 15-bit wide hardware

stack (refer to Figure 3-5). The stack space is not part

of either program or data space. The PC is PUSHed

onto the stack when CALL or CALLW instructions are

executed or an interrupt causes a branch. The stack is

POPed in the event of a RETURN, RETLWor a RETFIE

instruction execution. PCLATH is not affected by a

PUSH or POP operation.

The stack operates as a circular buffer if the STVREN

bit is programmed to ‘0‘ (Configuration Word 2). This

means that after the stack has been PUSHed sixteen

times, the seventeenth PUSH overwrites the value that

was stored from the first PUSH. The eighteenth PUSH

overwrites the second PUSH (and so on). The

STKOVF and STKUNF flag bits will be set on an Over-

flow/Underflow, regardless of whether the Reset is

enabled.

Note:

Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLW and

Interrupts will increment STKPTR while RETLW,

RETURN, and RETFIEwill decrement STKPTR. At any

time STKPTR can be inspected to see how much stack

is left. The STKPTR always points at the currently used

place on the stack. Therefore, a CALL or CALLW will

increment the STKPTR and then write the PC, and a

return will unload the PC and then decrement the

STKPTR.

Note:

There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL,

CALLW, RETURN, RETLW and RETFIE

instructions or the vectoring to an interrupt

address.

Reference Figure 3-5 through Figure 3-8 for examples

of accessing the stack.

FIGURE 3-5:

ACCESSING THE STACK EXAMPLE 1

Stack Reset Disabled

(STVREN = 0)

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x1F

STKPTR = 0x1F

Initial Stack Configuration:

After Reset, the stack is empty. The

empty stack is initialized so the Stack

Pointer is pointing at 0x1F. If the Stack

Overflow/Underflow Reset is enabled, the

TOSH/TOSL registers will return ‘0’. If

the Stack Overflow/Underflow Reset is

disabled, the TOSH/TOSL registers will

return the contents of stack address 0x0F.

Stack Reset Enabled

STKPTR = 0x1F

TOSH:TOSL

0x0000

(STVREN = 1)

DS40001569D-page 32

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 3-6:

ACCESSING THE STACK EXAMPLE 2

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

This figure shows the stack configuration

after the first CALLor a single interrupt.

If a RETURN instruction is executed, the

return address will be placed in the

Program Counter and the Stack Pointer

decremented to the empty state (0x1F).

TOSH:TOSL

0x00

Return Address

STKPTR = 0x00

FIGURE 3-7:

ACCESSING THE STACK EXAMPLE 3

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

After seven CALLs or six CALLs and an

interrupt, the stack looks like the figure

on the left. A series of RETURNinstructions

will repeatedly place the return addresses

into the Program Counter and pop the stack.

STKPTR = 0x06

TOSH:TOSL

0x06

0x05

0x04

0x03

0x02

0x01

0x00

Return Address

 2011-2016 Microchip Technology Inc.

DS40001569D-page 33

PIC16LF1904/6/7

FIGURE 3-8:

ACCESSING THE STACK EXAMPLE 4

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

Return Address

When the stack is full, the next CALLor

an interrupt will set the Stack Pointer to

0x10. This is identical to address 0x00

so the stack will wrap and overwrite the

return address at 0x00. If the Stack

Overflow/Underflow Reset is enabled, a

Reset will occur and location 0x00 will

not be overwritten.

TOSH:TOSL

STKPTR = 0x10

3.4.2

OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Word 2 is

programmed to ‘1’, the device will be reset if the stack

is PUSHed beyond the sixteenth level or POPed

beyond the first level, setting the appropriate bits

(STKOVF or STKUNF, respectively) in the PCON

register.

3.5

Indirect Addressing

The INDFn registers are not physical registers. Any

instruction that accesses an INDFn register actually

accesses the register at the address specified by the

File Select Registers (FSR). If the FSRn address

specifies one of the two INDFn registers, the read will

return ‘0’ and the write will not occur (though Status bits

may be affected). The FSRn register value is created

by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an

addressing space with 65536 locations. These locations

are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

DS40001569D-page 34

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 3-9:

INDIRECT ADDRESSING

0x0000

Traditional

Data Memory

0x0FFF

0x1000

0x1FFF

0x2000

Reserved

Linear

Data Memory

0x29AF

0x29B0

Reserved

0x0000

FSR

Address

Range

0x7FFF

0x8000

Program

Flash Memory

0xFFFF

0x7FFF

Note:

Not all memory regions are completely implemented. Consult device memory tables for memory limits.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 35

PIC16LF1904/6/7

3.5.1

TRADITIONAL DATA MEMORY

The traditional data memory is a region from FSR

address 0x000 to FSR address 0xFFF. The addresses

correspond to the absolute addresses of all SFR, GPR

and common registers.

FIGURE 3-10:

TRADITIONAL DATA MEMORY MAP

Direct Addressing

From Opcode

Indirect Addressing

4

BSR

6

7

FSRxH

0

7

FSRxL

0

Location Select

Bank Select

Location Select

00000 00001 00010

11111

0x00

0x7F

Bank 0 Bank 1 Bank 2

Bank 31

DS40001569D-page 36

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

3.5.2

LINEAR DATA MEMORY

3.5.3

PROGRAM FLASH MEMORY

The linear data memory is the region from FSR

address 0x2000 to FSR address 0x29AF. This region is

a virtual region that points back to the 80-byte blocks of

GPR memory in all the banks.

To make constant data access easier, the entire

program Flash memory is mapped to the upper half of

the FSR address space. When the MSB of FSRnH is

set, the lower 15 bits are the address in program

memory which will be accessed through INDF. Only the

lower eight bits of each memory location is accessible

via INDF. Writing to the program Flash memory cannot

be accomplished via the FSR/INDF interface. All

instructions that access program Flash memory via the

FSR/INDF interface will require one additional

instruction cycle to complete.

Unimplemented memory reads as 0x00. Use of the

linear data memory region allows buffers to be larger

than 80 bytes because incrementing the FSR beyond

one bank will go directly to the GPR memory of the next

bank.

The 16 bytes of common memory are not included in

the linear data memory region.

FIGURE 3-12:

PROGRAM FLASH

MEMORY MAP

FIGURE 3-11:

LINEAR DATA MEMORY

MAP

7

0

FSRnH

FSRnL

7

1

7

0

FSRnH

FSRnL

0

1

0

Location Select

0x8000

0x0000

Location Select

0x2000

0x020

Bank 0

0x06F

0x0A0

Bank 1

0x0EF

0x120

Program

Flash

Memory

(low 8

bits)

Bank 2

0x16F

0xF20

Bank 30

0x7FFF

0xFFFF

0xF6F

0x29AF

 2011-2016 Microchip Technology Inc.

DS40001569D-page 37

PIC16LF1904/6/7

4.0

DEVICE CONFIGURATION

Device Configuration consists of Configuration Word 1

and Configuration Word 2, Code Protection and Device

ID.

4.1

Configuration Words

There are several Configuration Word bits that allow

different oscillator and memory protection options.

These are implemented as Configuration Word 1 at

8007h and Configuration Word 2 at 8008h.

Note:

The DEBUG bit in Configuration Words is

managed automatically by device

development tools including debuggers

and programmers. For normal device

operation, this bit should be maintained as

a ‘1’.

DS40001569D-page 38

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

REGISTER 4-1:

CONFIGURATION WORD 1

U-1

—

U-1

—

R/P-1

U-1

—

CLKOUTEN

BOREN<1:0>

bit 13

bit 8

R/P-1

CP

R/P-1

U-1

—

R/P-1 R/P-1

FOSC<1:0>

MCLRE

PWRTE

WDTE<1:0>

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘1’

-n = Value when blank or after Bulk Erase

‘0’ = Bit is cleared

bit 13-12

bit 11

Unimplemented: Read as ‘1’

CLKOUTEN: Clock Out Enable bit

1= CLKOUT function is disabled. I/O function on the CLKOUT pin.

0= CLKOUT function is enabled on the CLKOUT pin

bit 10-9

BOREN<1:0>: Brown-out Reset Enable bits

11= BOR enabled

10= BOR enabled during operation and disabled in Sleep

01= BOR controlled by SBOREN bit of the BORCON register

00= BOR disabled

bit 8

bit 7

Unimplemented: Read as ‘1’

CP: Code Protection bit

1= Program memory code protection is disabled

0= Program memory code protection is enabled

bit 6

MCLRE: MCLR/VPP Pin Function Select bit

If LVP bit = 1:

This bit is ignored.

If LVP bit = 0:

1= MCLR/VPP pin function is MCLR; Weak pull-up enabled.

0= MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUE3 bit.

bit 5

PWRTE: Power-up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

bit 4-3

WDTE<1:0>: Watchdog Timer Enable bit

11= WDT enabled

10= WDT enabled while running and disabled in Sleep

01= WDT controlled by the SWDTEN bit in the WDTCON register

00= WDT disabled

bit 2

Unimplemented: Read as ‘1’

bit 1-0

FOSC<1:0>: Oscillator Selection bits

00= INTOSC oscillator: I/O function on CLKIN pin

01= ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin

10= ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin

11= ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin

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REGISTER 4-2:

CONFIGURATION WORD 2

R/P-1

LVP⁽¹⁾

R/P-1

DEBUG⁽³⁾

R/P-1

BORV⁽²⁾

R/P-1

U-1

—

STVREN

LPBOR

bit 13

bit 8

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

R/P-1

WRT<1:0>

bit 7

bit 0

Legend:

R = Readable bit

‘0’ = Bit is cleared

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘1’

-n = Value when blank or after Bulk Erase

bit 13

bit 12

bit 11

bit 10

bit 9

LVP: Low-Voltage Programming Enable bit⁽¹⁾

1= Low-voltage programming enabled

0= High-voltage on MCLR must be used for programming

DEBUG: In-Circuit Debugger Mode bit⁽³⁾

1= In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins

0= In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

LPBOR: Low-Power BOR bit

1= Low-Power BOR is disabled

0= Low-Power BOR is enabled

BORV: Brown-out Reset Voltage Selection bit⁽²⁾

1= Brown-out Reset voltage (VBOR), low trip point selected

0= Brown-out Reset voltage (VBOR), high trip point selected

STVREN: Stack Overflow/Underflow Reset Enable bit

1= Stack Overflow or Underflow will cause a Reset

0= Stack Overflow or Underflow will not cause a Reset

bit 8-2

bit 1-0

Unimplemented: Read as ‘1’

WRT<1:0>: Flash Memory Self-Write Protection bits

4 kW Flash memory (PIC16LF1904 only):

11= Write protection off

10= 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON control

01= 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON control

00= 000h to FFFh write-protected, no addresses may be modified by PMCON control

8 kW Flash memory (PIC16LF1906/7 only):

11= Write protection off

10= 0000h to 01FFh write-protected, 200h to 1FFFh may be modified by PMCON control

01= 0000h to 0FFFh write-protected, 1000h to 1FFFh may be modified by PMCON control

00= 0000h to 1FFFh write-protected, no addresses may be modified by PMCON control

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.

2: See VBOR parameter for specific trip point voltages.

3: The DEBUG bit in Configuration Words is managed automatically by device development tools including

debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.

DS40001569D-page 40

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4.2

Code Protection

Code protection allows the device to be protected from

unauthorized access. Program memory protection is

controlled independently. Internal access to the

program memory is unaffected by any code protection

setting.

4.2.1

PROGRAM MEMORY PROTECTION

The entire program memory space is protected from

external reads and writes by the CP bit in Configuration

Word 1. When CP = 0, external reads and writes of

program memory are inhibited and a read will return all

‘0’s. The CPU can continue to read program memory,

regardless of the protection bit settings. Writing the

program memory is dependent upon the write

protection

setting.

See

Section 4.3

“Write

Protection” for more information.

4.3

Write Protection

Write protection allows the device to be protected from

unintended self-writes. Applications, such as boot

loader software, can be protected while allowing other

regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Word 2 define the

size of the program memory block that is protected.

4.4

User ID

Four memory locations (8000h-8003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

readable and writable during normal execution. See

Section 10.4 “User ID, Device ID and Configuration

Word Access” for more information on accessing

these memory locations. For more information on

checksum

“PIC16F193X/LF193X/PIC16F194X/LF194X/PIC16LF

190X Memory Programming Specification”

(DS41397).

calculation,

see

the

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PIC16LF1904/6/7

4.5

Device ID and Revision ID

The memory location 8006h is where the Device ID and

Revision ID are stored. The upper nine bits hold the

Device ID. The lower five bits hold the Revision ID. See

Section 10.4 “User ID, Device ID and Configuration

Word Access” for more information on accessing

these memory locations.

Development tools, such as device programmers and

debuggers, may be used to read the Device ID and

Revision ID.

REGISTER 4-3:

DEVICEID: DEVICE ID REGISTER

R

DEV<8:3>

bit 13

bit 8

bit 0

R

DEV<2:0>

REV<4:0>

bit 7

Legend:

R = Readable bit

U = Unimplemented bit, read as ‘1’

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

P = Programmable bit

bit 13-5

DEV<8:0>: Device ID bits

DEVICEID<13:0> Values

Device

DEV<8:0>

REV<4:0>

PIC16LF1904

PIC16LF1906

PIC16LF1907

10 1100 100

10 1100 011

10 1100 010

x xxxx

bit 4-0

REV<4:0>: Revision ID bits

These bits are used to identify the revision (see Table under DEV<8:0> above).

DS40001569D-page 42

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A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 5-1.

5.0

RESETS

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Low-Power Brown-out Reset (LPBOR)

• MCLR Reset

• WDT Reset

• RESETinstruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To allow VDD to stabilize, an optional Power-up Timer

can be enabled to extend the Reset time after a BOR

or POR event.

FIGURE 5-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Programming Mode Exit

RESET Instruction

Stack Overflow/Underflow Reset

Stack

Pointer

External Reset

MCLRE

MCLR

Sleep

WDT

Time-out

Device

Reset

Power-on

Reset

VDD

Brown-out

Reset

LPBOR

Reset

BOR

Enable

PWRT

72 ms

Zero

LFINTOSC

PWRTEN

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PIC16LF1904/6/7

5.1

Power-on Reset (POR)

5.2

Brown-Out Reset (BOR)

The POR circuit holds the device in Reset until VDD has

reached an acceptable level for minimum operation.

Slow rising VDD, fast operating speeds or analog

performance may require greater than minimum VDD.

The PWRT, BOR or MCLR features can be used to

extend the start-up period until all device operation

conditions have been met.

The BOR circuit holds the device in Reset when VDD

reaches a selectable minimum level. Between the

POR and BOR, complete voltage range coverage for

execution protection can be implemented.

The Brown-out Reset module has four operating

modes controlled by the BOREN<1:0> bits in Configu-

ration Word 1. The four operating modes are:

• BOR is always on

5.1.1

POWER-UP TIMER (PWRT)

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

The Power-up Timer provides a nominal 64 ms

time-out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.

The PWRT delay allows additional time for the VDD to

rise to an acceptable level. The Power-up Timer is

enabled by clearing the PWRTE bit in Configuration

Word 1.

Refer to Table 5-1 for more information.

The Brown-out Reset voltage level is selectable by

configuring the BORV bit in Configuration Word 2.

A VDD noise rejection filter prevents the BOR from trig-

gering on small events. If VDD falls below VBOR for a

duration greater than parameter TBORDC, the device

will reset. See Figure 5-2 for more information.

The Power-up Timer starts after the release of the POR

and BOR.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

TABLE 5-1:

BOREN<1:0>

BOR OPERATING MODES

Device Operation

upon release of POR

SBOREN

Device Mode

BOR Mode

upon wake- up from

Sleep

11

10

X

Awake

Sleep

X

Active

Waits for BOR ready⁽¹⁾

Waits for BOR ready

Disabled

Active

1

0

X

Waits for BOR ready⁽¹⁾

Begins immediately

01

00

X

Disabled

X

Note 1: In these specific cases, “release of POR” and “wake-up from Sleep,” there is no delay in start-up. The BOR

ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR

circuit is forced on by the BOREN<1:0> bits.

5.2.1

BOR IS ALWAYS ON

5.2.3

BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Word 1 are set

to ‘11’, the BOR is always on. The device start-up will

be delayed until the BOR is ready and VDD is higher

than the BOR threshold.

When the BOREN bits of Configuration Word 1 are set

to ‘01’, the BOR is controlled by the SBOREN bit of the

BORCON register. The device start-up is not delayed

by the BOR ready condition or the VDD level.

BOR protection is active during Sleep. The BOR does

not delay wake-up from Sleep.

BOR protection begins as soon as the BOR circuit is

ready. The status of the BOR circuit is reflected in the

BORRDY bit of the BORCON register.

5.2.2

BOR IS OFF IN SLEEP

BOR protection is unchanged by Sleep.

When the BOREN bits of Configuration Word 1 are set

to ‘10’, the BOR is on, except in Sleep. The device

start-up will be delayed until the BOR is ready and VDD

is higher than the BOR threshold.

BOR protection is not active during Sleep. The device

wake-up will be delayed until the BOR is ready.

DS40001569D-page 44

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FIGURE 5-2:

BROWN-OUT SITUATIONS

VDD

VBOR

Internal

Reset

(1)

TPWRT

VDD

VBOR

Internal

Reset

< TPWRT

(1)

TPWRT

VDD

VBOR

Internal

Reset

(1)

TPWRT

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

REGISTER 5-1:

BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u

SBOREN

bit 7

R/W-0/u

BORFS

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-q/u

BORRDY

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

SBOREN: Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Word 1  01:

SBOREN is read/write, but has no effect on the BOR.

If BOREN <1:0> in Configuration Word 1 = 01:

1= BOR Enabled

0= BOR Disabled

(1)

BORFS: Brown-out Reset Fast Start bit

If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)

BORFS is Read/Write, but has no effect.

If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):

1= Band gap is forced on always (covers Sleep/wake-up/operating cases)

0= Band gap operates normally, and may turn off

bit 5-1

bit 0

Unimplemented: Read as ‘0’

BORRDY: Brown-out Reset Circuit Ready Status bit

1= The Brown-out Reset circuit is active

0= The Brown-out Reset circuit is inactive

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5.3

Low-Power Brown-out Reset

(LPBOR)

5.5

Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware

does not issue a CLRWDTinstruction within the time-out

period. The TO and PD bits in the STATUS register are

changed to indicate the WDT Reset. See Section 9.0

“Watchdog Timer” for more information.

The Low-Power Brown-Out Reset (LPBOR) is an

essential part of the Reset subsystem. Refer to

Figure 5-1 to see how the BOR interacts with other

modules.

The LPBOR is used to monitor the external VDD pin.

When too low of a voltage is detected, the device is

held in Reset. When this occurs, a register bit (BOR) is

changed to indicate that a BOR Reset has occurred.

The same bit is set for both the BOR and the LPBOR.

Refer to Register 5-2.

5.6

RESET Instruction

A RESETinstruction will cause a device Reset. The RI

bit in the PCON register will be set to ‘0’. See Table 5-4

for default conditions after a RESET instruction has

occurred.

5.3.1

ENABLING LPBOR

5.7

Stack Overflow/Underflow Reset

The LPBOR is controlled by the LPBOR bit of

Configuration Word 2. When the device is erased, the

LPBOR module defaults to disabled.

The device can reset when the Stack Overflows or

Underflows. The STKOVF or STKUNF bits of the PCON

register indicate the Reset condition. These Resets are

enabled by setting the STVREN bit in Configuration Word

2. See Section 5.7 “Stack Overflow/Underflow Reset”

for more information.

5.3.1.1

LPBOR Module Output

The output of the LPBOR module is a signal indicating

whether or not a Reset is to be asserted. This signal is

to be OR’d together with the Reset signal of the BOR

module to provide the generic BOR signal, which goes

to the PCON register and to the power control block.

5.8

Programming Mode Exit

Upon exit of Programming mode, the device will

behave as if a POR had just occurred.

5.4

MCLR

5.9

Power-Up Timer

The MCLR is an optional external input that can reset

the device. The MCLR function is controlled by the

MCLRE bit of Configuration Word 1 and the LVP bit of

Configuration Word 2 (Table 5-2).

The Power-up Timer optionally delays device execution

after a BOR or POR event. This timer is typically used to

allow VDD to stabilize before allowing the device to start

running.

TABLE 5-2:

MCLRE

MCLR CONFIGURATION

The Power-up Timer is controlled by the PWRTE bit of

Configuration Word 1.

LVP

MCLR

0

1

x

0

1

Disabled

Enabled

5.10 Start-up Sequence

Upon the release of a POR or BOR, the following must

occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

5.4.1

MCLR ENABLED

2. Oscillator start-up timer runs to completion (if

required for oscillator source).

When MCLR is enabled and the pin is held low, the

device is held in Reset. The MCLR pin is connected to

VDD through an internal weak pull-up.

3. MCLR must be released (if enabled).

The total time-out will vary based on oscillator configu-

ration and Power-up Timer configuration. See

Section 6.0 “Oscillator Module” for more informa-

tion.

The device has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

Note:

A Reset does not drive the MCLR pin low.

The Power-up Timer and oscillator start-up timer run

independently of MCLR Reset. If MCLR is kept low

long enough, the Power-up Timer and oscillator

start-up timer will expire. Upon bringing MCLR high, the

device will begin execution immediately (see

Figure 5-3). This is useful for testing purposes or to

synchronize more than one device operating in parallel.

5.4.2

MCLR DISABLED

When MCLR is disabled, the pin functions as a general

purpose input and the internal weak pull-up is under

software control. See Section 11.5 “PORTE Regis-

ters” for more information.

DS40001569D-page 46

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FIGURE 5-3:

RESET START-UP SEQUENCE

VDD

Internal POR

TPWRT

Power-Up Timer

MCLR

TMCLR

Internal RESET

Oscillator Modes

External Crystal

TOST

Oscillator Start-Up Timer

Oscillator

FOSC

Internal Oscillator

Oscillator

FOSC

External Clock (EC)

CLKIN

FOSC

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5.11 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and

PCON registers are updated to indicate the cause of

the Reset. Table 5-3 and Table 5-4 show the Reset

conditions of these registers.

TABLE 5-3:

RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR

RI

POR

BOR

TO

PD

Condition

Power-on Reset

0

u

1

u

0

u

1

u

0

u

1

u

0

u

1

u

0

u

0

u

x

0

u

1

0

x

1

0

1

u

1

u

1

x

0

1

u

0

u

0

u

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WDT Reset

WDT Wake-up from Sleep

Interrupt Wake-up from Sleep

MCLR Reset during normal operation

MCLR Reset during Sleep

RESETInstruction Executed

Stack Overflow Reset (STVREN = 1)

Stack Underflow Reset (STVREN = 1)

TABLE 5-4:

RESET CONDITION FOR SPECIAL REGISTERS⁽²⁾

Program

STATUS

Register

PCON

Register

Condition

Counter

Power-on Reset

0000h

---1 1000

---u uuuu

00-1 110x

uu-u 0uuu

MCLR Reset during normal operation

0000h

MCLR Reset during Sleep

WDT Reset

0000h

---1 0uuu

---0 uuuu

---0 0uuu

---1 1uuu

---1 0uuu

---u uuuu

uu-u 0uuu

uu-0 uuuu

uu-u uuuu

00-1 11u0

uu-u uuuu

uu-u u0uu

1u-u uuuu

u1-u uuuu

WDT Wake-up from Sleep

Brown-out Reset

PC + 1

0000h

Interrupt Wake-up from Sleep

RESETInstruction Executed

Stack Overflow Reset (STVREN = 1)

Stack Underflow Reset (STVREN = 1)

PC + 1⁽¹⁾

0000h

Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

DS40001569D-page 48

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The PCON register bits are shown in Register 5-2.

5.12 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits

to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI)

• MCLR Reset (RMCLR)

• Watchdog Timer Reset (RWDT)

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

REGISTER 5-2:

PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q

U-0

—

R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF

bit 7

STKUNF

RWDT

RMCLR

RI

POR

BOR

bit 0

Legend:

HC = Bit is cleared by hardware

HS = Bit is set by hardware

U = Unimplemented bit, read as ‘0’

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

-m/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

STKOVF: Stack Overflow Flag bit

1= A Stack Overflow occurred

0= A Stack Overflow has not occurred or set to ‘0’ by firmware

STKUNF: Stack Underflow Flag bit

1= A Stack Underflow occurred

0= A Stack Underflow has not occurred or set to ‘0’ by firmware

bit 5

bit 4

Unimplemented: Read as ‘0’

RWDT: Watchdog Timer Reset Flag bit

1= A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware

0= A Watchdog Timer Reset has occurred (set to ‘0’ in hardware when a Watchdog Timer Reset)

bit 3

bit 2

bit 1

bit 0

RMCLR: MCLR Reset Flag bit

1= A MCLR Reset has not occurred or set to ‘1’ by firmware

0= A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)

RI: RESETInstruction Flag bit

1= A RESETinstruction has not been executed or set to ‘1’ by firmware

0= A RESETinstruction has been executed (set to ‘0’ in hardware upon executing a RESETinstruction)

POR: Power-on Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

BOR: Brown-out Reset Status bit

1= No Brown-out Reset occurred

0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

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TABLE 5-5:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Register

on Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BORCON SBOREN BORFS

—

RWDT

TO

—

RMCLR

PD

—

RI

Z

—

POR

DC

BORRDY

BOR

45

49

21

75

PCON

STKOVF STKUNF

STATUS

WDTCON

—

C

WDTPS<4:0>

SWDTEN

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

DS40001569D-page 50

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6.0

6.1

OSCILLATOR MODULE

Overview

The oscillator module has a wide variety of clock

sources and selection features that allow it to be used

in a wide range of applications while maximizing perfor-

mance and minimizing power consumption. Figure 6-1

illustrates a block diagram of the oscillator module.

Clock sources can be supplied from external clock

circuits. In addition, the system clock source can be

supplied from one of two internal oscillators, with a

choice of speeds selectable via software. Additional

clock features include:

• Selectable system clock source between external

or internal sources via software.

• Fast start-up oscillator allows internal circuits to

power up and stabilize before switching to the 16

MHz HFINTOSC

The oscillator module can be configured in one of the

following clock modes:

1. ECL – External Clock Low-Power mode

(0 MHz to 0.5 MHz)

2. ECM – External Clock Medium-Power mode

(0.5 MHz to 4 MHz)

3. ECH – External Clock High-Power mode

(4 MHz to 20 MHz)

4. INTOSC – Internal oscillator (31 kHz to 16 MHz).

Clock Source modes are selected by the FOSC<1:0>

bits in the Configuration Word 1. The FOSC bits

determine the type of oscillator that will be used when

the device is first powered.

The EC clock mode relies on an external logic level

signal as the device clock source.

The INTOSC internal oscillator block produces a low

and high-frequency clock source, designated

LFINTOSC and HFINTOSC (see Internal Oscillator

Block, Figure 6-1). A wide selection of device clock

frequencies may be derived from these two clock

sources.

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FIGURE 6-1:

SIMPLIFIED PIC^®MCU CLOCK SOURCE BLOCK DIAGRAM

Low Power Mode

Event Switch

(SCS<1:0>)

CLKIN

EC

2

CLKIN

Primary Clock

00

01

Secondary Oscillator

T1CKI/

T1OSO

Secondary

Oscillator

(T1OSC)

Secondary Clock

T1OSI

INTOSC

1x

Internal Oscillator

IRCF<3:0>

4

HF-16 MHz

HF-8 MHz

HF-4 MHz

HF-2 MHz

HF-1 MHz

Start-up

Control

Logic

1111

1110

1101

1100

1011

/1

/2

/4

/8

/16

16 MHz

Primary Osc

HF-500 kHz 1010/

/32

/64

0111

HF-250 kHz 1001/

Start-Up Osc

0110

HF-125 kHz

HF-62.5 kHz

1000/

0101

/128

/256

0100

HF-31.25 kHz 0011

/512

0010

LF-31 kHz

LF-INTOSC

(31 kHz)

0001

0000

DS40001569D-page 52

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PIC16LF1904/6/7

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC^®MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

6.2

Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the

clock source to function. An example is: oscillator mod-

ule (EC mode) circuit.

Internal clock sources are contained internally within the

oscillator module. The internal oscillator block has two

internal oscillators that are used to generate the internal

system clock sources: the 16 MHz High-Frequency

Internal Oscillator and the 31 kHz Low-Frequency

Internal Oscillator (LFINTOSC).

FIGURE 6-2:

EXTERNAL CLOCK (EC)

MODE OPERATION

The system clock can be selected between external or

internal clock sources via the System Clock Select

(SCS) bits in the OSCCON register. See Section 6.3

“Clock Switching” for additional information.

CLKIN

Clock from

Ext. System

PIC^®MCU

CLKOUT

(1)

FOSC/4 or

I/O

6.2.1

EXTERNAL CLOCK SOURCES

An external clock source can be used as the device

system clock by performing one of the following

actions:

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Word 1.

• Program the FOSC<1:0> bits in the Configuration

Word 1 to select an external clock source that will

be used as the default system clock upon a

device Reset.

• Write the SCS<1:0> bits in the OSCCON register

to switch the system clock source to:

- Secondary oscillator during run-time, or

- An external clock source determined by the

value of the FOSC bits.

See Section 6.3 “Clock Switching”for more informa-

tion.

6.2.1.1

EC Mode

The External Clock (EC) mode allows an externally

generated logic level signal to be the system clock

source. When operating in this mode, an external clock

source is connected to the CLKIN input. CLKOUT is

available for general purpose I/O or CLKOUT.

Figure 6-2 shows the pin connections for EC mode.

EC mode has three power modes to select from through

Configuration Word 1:

• High power, 4-20 MHz (FOSC = 11)

• Medium power, 0.5-4 MHz (FOSC = 10)

• Low power, 0-0.5 MHz (FOSC = 01)

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6.2.1.2

Secondary Oscillator

6.2.2

INTERNAL CLOCK SOURCES

The secondary oscillator is a separate crystal oscillator

that is associated with the Timer1 peripheral. It is opti-

mized for timekeeping operations with a 32.768 kHz

crystal connected between the T1CKI/T1OSO and

T1OSI device pins.

The device may be configured to use the internal oscil-

lator block as the system clock by performing one of the

following actions:

• Program the FOSC<1:0> bits in Configuration

Word 1 to select the INTOSC clock source, which

will be used as the default system clock upon a

device Reset.

The secondary oscillator can be used as an alternate

system clock source and can be selected during

run-time using clock switching. Refer to Section 6.3

“Clock Switching” for more information.

• Write the SCS<1:0> bits in the OSCCON register

to switch the system clock source to the internal

oscillator during run-time. See Section 6.3

“Clock Switching”for more information.

FIGURE 6-3:

QUARTZ CRYSTAL

OPERATION

In INTOSC mode, CLKIN is available for general

purpose I/O. CLKOUT is available for general purpose

I/O or CLKOUT.

(SECONDARY

OSCILLATOR)

The function of the CLKOUT pin is determined by the

state of the CLKOUTEN bit in Configuration Word 1.

PIC^®MCU

The internal oscillator block has two independent

oscillators that provides the internal system clock

source.

T1CKI/T1OSO

C1

C2

To Internal

Logic

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at

16 MHz.

32.768 kHz

Quartz

Crystal

2. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at

31 kHz.

T1OSI

6.2.2.1

HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is

a factory calibrated 16 MHz internal clock source.

Note 1: Quartz

crystal

characteristics

vary

according to type, package and

manufacturer. The user should consult the

manufacturer data sheets for specifications

and recommended application.

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 6-1). The frequency derived

from the HFINTOSC can be selected via software using

the IRCF<3:0> bits of the OSCCON register. See

Section 6.2.2.4 “Internal Oscillator Clock Switch

Timing” for more information.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

The HFINTOSC is enabled by:

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• Configure the IRCF<3:0> bits of the OSCCON

register for the desired HF frequency, and

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and PIC^®

Devices” (DS00826)

• AN849, “Basic PIC^®Oscillator Design”

• FOSC<1:0> = 11, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’.

(DS00849)

• AN943, “Practical PIC^®Oscillator

Analysis and Design” (DS00943)

The High-Frequency Internal Oscillator Ready bit

(HFIOFR) of the OSCSTAT register indicates when the

HFINTOSC is running and can be utilized.

• AN949, “Making Your Oscillator Work”

(DS00949)

The High-Frequency Internal Oscillator Status Stable

bit (HFIOFS) of the OSCSTAT register indicates when

the HFINTOSC is running within 0.5% of its final value.

• TB097, “Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork

Crystal to a PIC16F690/SS” (DS91097)

• AN1288, “Design Practices for

Low-Power External Oscillators”

(DS01288)

DS40001569D-page 54

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PIC16LF1904/6/7

6.2.2.2

LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is

an uncalibrated 31 kHz internal clock source.

Note:

Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’

and the frequency selection is set to

500 kHz. The user can modify the IRCF

bits to select a different frequency.

The output of the LFINTOSC connects to a multiplexer

(see Figure 6-1). Select 31 kHz, via software, using the

IRCF<3:0> bits of the OSCCON register. See

Section 6.2.2.4 “Internal Oscillator Clock Switch

Timing” for more information. The LFINTOSC is also

the frequency for the Power-up Timer (PWRT) and

Watchdog Timer (WDT).

The IRCF<3:0> bits of the OSCCON register allow

duplicate selections for some frequencies. These dupli-

cate choices can offer system design trade-offs. Lower

power consumption can be obtained when changing

oscillator sources for a given frequency. Faster transi-

tion times can be obtained between frequency changes

that use the same oscillator source.

The LFINTOSC is enabled by selecting 31 kHz

(IRCF<3:0> bits of the OSCCON register = 000) as the

system clock source (SCS bits of the OSCCON

register = 1x), or when any of the following are enabled:

6.2.2.4

Internal Oscillator Clock Switch

Timing

• Configure the IRCF<3:0> bits of the OSCCON

register for the desired LF frequency, and

When switching between the HFINTOSC and the

LFINTOSC, the new oscillator may already be shut

down to save power (see Figure 6-4). If this is the case,

there is a delay after the IRCF<3:0> bits of the

OSCCON register are modified before the frequency

selection takes place. The OSCSTAT register will

reflect the current active status of the HFINTOSC and

LFINTOSC oscillators. The sequence of a frequency

selection is as follows:

• FOSC<1:0> = 01, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

The Low-Frequency Internal Oscillator Ready bit

(LFIOFR) of the OSCSTAT register indicates when the

LFINTOSC is running and can be utilized.

1. IRCF<3:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

6.2.2.3

Internal Oscillator Frequency

Selection

3. Clock switch circuitry waits for a falling edge of

the current clock.

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select bits

IRCF<3:0> of the OSCCON register.

4. The current clock is held low and the clock

switch circuitry waits for a rising edge in the new

clock.

The output of the 16 MHz HFINTOSC and 31 kHz

LFINTOSC connects to a postscaler and multiplexer

(see Figure 6-1). The Internal Oscillator Frequency

Select bits IRCF<3:0> of the OSCCON register select

the frequency output of the internal oscillators. One of

the following frequencies can be selected via software:

5. The new clock is now active.

6. The OSCSTAT register is updated as required.

7. Clock switch is complete.

See Figure 6-4 for more details.

• 16 MHz

If the internal oscillator speed is switched between two

clocks of the same source, there is no start-up delay

before the new frequency is selected. Clock switching

time delays are shown in Table 6-2.

• 8 MHz

• 4 MHz

• 2 MHz

• 1 MHz

Start-up delay specifications are located in the

oscillator tables of Section 22.0 “Electrical

Specifications”.

• 500 kHz (default after Reset)

• 250 kHz

• 125 kHz

• 62.5 kHz

• 31.25 kHz

• 31 kHz (LFINTOSC)

 2011-2016 Microchip Technology Inc.

DS40001569D-page 55

PIC16LF1904/6/7

FIGURE 6-4:

INTERNAL OSCILLATOR SWITCH TIMING

HFINTOSC

LFINTOSC (WDT disabled)

HFINTOSC

(1)

Oscillator Delay

2-cycle Sync

Running

LFINTOSC

0

0

IRCF <3:0>

System Clock

HFINTOSC

LFINTOSC (WDT enabled)

HFINTOSC

2-cycle Sync

Running

LFINTOSC

IRCF <3:0>

0

0

System Clock

LFINTOSC

HFINTOSC

LFINTOSC turns off unless WDT is enabled

Running

LFINTOSC

Oscillator Delay⁽¹⁾2-cycle Sync

HFINTOSC

IRCF <3:0>

= 0

 0

System Clock

Note 1: See Table 6-1, “Oscillator Switching Delays” for more information.

TABLE 6-1:

OSCILLATOR SWITCHING DELAYS

Switch To

Switch From

Oscillator Delay

LFINTOSC

1 cycle of each clock source

2 s (approx.)

HFINTOSC

Any clock source

ECH, ECM, ECL

Secondary Oscillator

2 cycles

1024 Secondary Oscillator Cycles

DS40001569D-page 56

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PIC16LF1904/6/7

6.3.3

SECONDARY OSCILLATOR

6.3

Clock Switching

The secondary oscillator is a separate crystal oscillator

associated with the Timer1 peripheral. It is optimized

for timekeeping operations with a 32.768 kHz crystal

connected between the T1OSI and T1CKI/T1OSO

device pins.

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bits of the OSCCON

register. The following clock sources can be selected

using the SCS bits:

The secondary oscillator is enabled using the

T1OSCEN control bit in the T1CON register. See

Section 17.0 “Timer1 Module with Gate Control” for

more information about the Timer1 peripheral.

• Default system oscillator determined by FOSC

bits in Configuration Word 1

• Secondary oscillator 32 kHz crystal

• Internal Oscillator Block (INTOSC)

6.3.4

SECONDARY OSCILLATOR READY

(T1OSCR) BIT

6.3.1

SYSTEM CLOCK SELECT (SCS)

BITS

The user must ensure that the secondary oscillator is

ready to be used before it is selected as a system clock

source. The Secondary Oscillator Ready (T1OSCR) bit

of the OSCSTAT register indicates whether the

secondary oscillator is ready to be used. After the

T1OSCR bit is set, the SCS bits can be configured to

select the secondary oscillator.

The System Clock Select (SCS) bits of the OSCCON

register selects the system clock source that is used for

the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00,

the system clock source is determined by value of

the FOSC<1:0> bits in the Configuration Word 1.

• When the SCS bits of the OSCCON register = 01,

the system clock source is the secondary

oscillator.

• When the SCS bits of the OSCCON register = 1x,

the system clock source is chosen by the internal

oscillator frequency selected by the IRCF<3:0>

bits of the OSCCON register. After a Reset, the

SCS bits of the OSCCON register are always

cleared.

When switching between clock sources, a delay is

required to allow the new clock to stabilize. These oscil-

lator delays are shown in Table 6-2.

6.3.2

OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of

the OSCSTAT register indicates whether the system

clock is running from the external clock source, as

defined by the FOSC<1:0> bits in the Configuration

Word 1, or from the internal clock source. The OST

does not reflect the status of the secondary oscillator.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 57

PIC16LF1904/6/7

6.4

Oscillator Control Registers

REGISTER 6-1:

OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1

IRCF<3:0>

U-0

—

U-0

—

R/W-0/0

SCS<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-3

IRCF<3:0>: Internal Oscillator Frequency Select bits

000x= 31 kHz LF

001x= 31.25 kHz

0100= 62.5 kHz

0101= 125 kHz

0110= 250 kHz

0111= 500 kHz (default upon Reset)

1000= 125 kHz⁽¹⁾

1001= 250 kHz⁽¹⁾

1010= 500 kHz⁽¹⁾

1011= 1 MHz

1100= 2 MHz

1101= 4 MHz

1110= 8 MHz

1111= 16 MHz

bit 2

Unimplemented: Read as ‘0’

bit 1-0

SCS<1:0>: System Clock Select bits

1x= Internal oscillator block

01= Secondary oscillator

00= Clock determined by FOSC<1:0> in Configuration Word 1.

Note 1: Duplicate frequency derived from HFINTOSC.

DS40001569D-page 58

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REGISTER 6-2:

OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q

T1OSCR

bit 7

U-0

—

R-q/q

R-0/q

U-0

—

U-0

—

R-0/0

R-0/q

OSTS

HFIOFR

LFIOFR

HFIOFS

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Conditional

bit 7

T1OSCR: Timer1 Oscillator Ready bit

If T1OSCEN = 1:

1= Timer1 oscillator is ready

0= Timer1 oscillator is not ready

If T1OSCEN = 0:

1= Timer1 clock source is always ready

bit 6

bit 5

Unimplemented: Read as ‘0’

OSTS: Oscillator Start-up Time-out Status bit

1= Running from the external clock source (EC)

0= Running from an internal oscillator (FOSC<1:0> = 00)

bit 4

HFIOFR: High-Frequency Internal Oscillator Ready bit

1= HFINTOSC is ready

0= HFINTOSC is not ready

bit 3-2

bit 1

Unimplemented: Read as ‘0’

LFIOFR: Low-Frequency Internal Oscillator Ready bit

1= LFINTOSC is ready

0= LFINTOSC is not ready

bit 0

HFIOFS: High-Frequency Internal Oscillator Stable bit

1= HFINTOSC 16 MHz oscillator is stable and is driving the INTOSC

0= HFINTOSC 16 MHz oscillator is not stable, the start-up oscillator is driving INTOSC

TABLE 6-2:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCCON

OSCSTAT

T1CON

—

IRCF<3:0>

—

SCS<1:0>

58

59

T1OSCR

—

OSTS

HFIOFR

—

LFIOFR

—

HFIOFS

TMR1CS<1:0>

T1CKPS<1:0>

T1OSCEN

T1SYNC

TMR1ON

139

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

TABLE 6-3:

SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

—

CLKOUTEN

BOREN<1:0>

13:8

7:0

—

CONFIG1

39

CP

MCLRE

PWRTE

WDTE<1:0>

—

FOSC<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

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DS40001569D-page 59

PIC16LF1904/6/7

A block diagram of the interrupt logic is shown in

Figure 7.1.

7.0

INTERRUPTS

The interrupt feature allows certain events to preempt

normal program flow. Firmware is used to determine

the source of the interrupt and act accordingly. Some

interrupts can be configured to wake the MCU from

Sleep mode.

This chapter contains the following information for

Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

• INT Pin

• Automatic Context Saving

Many peripherals produce Interrupts. Refer to the

corresponding chapters for details.

FIGURE 7-1:

INTERRUPT LOGIC

TMR0IF

TMR0IE

Wake-up

(If in Sleep mode)

INTF

INTE

Peripheral Interrupts

(TMR1IF) PIR1<0>

IOCIF

IOCIE

Interrupt

to CPU

PEIE

GIE

PIRn<7>

PIEn<7>

DS40001569D-page 60

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

7.1

Operation

7.2

Interrupt Latency

Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:

Interrupt latency is defined as the time from when the

interrupt event occurs to the time code execution at the

interrupt vector begins. The latency for synchronous

interrupts is three or four instruction cycles. For asyn-

chronous interrupts, the latency is three to five instruc-

tion cycles, depending on when the interrupt occurs.

See Figure 7-2 and Figure 7.3 for more details.

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt

event(s)

• PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt event is contained in the

PIE1 and PIE2 registers)

The INTCON, PIR1 and PIR2 registers record individ-

ual interrupts via interrupt flag bits. Interrupt flag bits will

be set, regardless of the status of the GIE, PEIE and

individual interrupt enable bits.

The following events happen when an interrupt event

occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the

stack

• Critical registers are automatically saved to the

shadow registers (See Section 7.5 “Automatic

Context Saving”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR)

should determine the source of the interrupt by polling

the interrupt flag bits. The interrupt flag bits must be

cleared before exiting the ISR to avoid repeated

interrupts. Because the GIE bit is cleared, any interrupt

that occurs while executing the ISR will be recorded

through its interrupt flag, but will not cause the

processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the

previous address from the stack, restoring the saved

context from the shadow registers and setting the GIE

bit.

For additional information on a specific interrupt’s

operation, refer to its peripheral chapter.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other

enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring

while the GIE bit is clear will be serviced

when the GIE bit is set again.

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DS40001569D-page 61

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FIGURE 7-2:

INTERRUPT LATENCY

CLKIN

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKOUT

Interrupt Sampled

during Q1

Interrupt

GIE

PC-1

PC

PC+1

0004h

0005h

PC

1 Cycle Instruction at PC

Execute

Inst(PC)

NOP

Inst(0004h)

Interrupt

GIE

PC+1/FSR

ADDR

New PC/

PC+1

PC-1

PC

0004h

0005h

PC

Execute

2 Cycle Instruction at PC

Inst(PC)

NOP

Inst(0004h)

Interrupt

GIE

PC-1

PC

FSR ADDR

INST(PC)

PC+1

PC+2

0004h

0005h

PC

Execute

3 Cycle Instruction at PC

NOP

Inst(0004h)

Inst(0005h)

Interrupt

GIE

PC-1

PC

FSR ADDR

INST(PC)

PC+1

PC+2

0004h

0005h

PC

NOP

Execute

3 Cycle Instruction at PC

NOP

Inst(0004h)

DS40001569D-page 62

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PIC16LF1904/6/7

FIGURE 7-3:

INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN

(3)

CLKOUT

(4)

INT pin

INTF

(1)

(2)

(5)

Interrupt Latency

GIE

INSTRUCTION FLOW

PC

PC + 1

—

0004h

0005h

PC

Inst (PC)

PC + 1

Instruction

Fetched

Inst (PC + 1)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

Executed

Dummy Cycle

Inst (PC)

Inst (PC – 1)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT not available in all Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 22.0 “Electrical Specifications””.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

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7.3

Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To

wake from Sleep, the peripheral must be able to

operate without the system clock. The interrupt source

must have the appropriate interrupt enable bit(s) set

prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the

processor will branch to the interrupt vector. Otherwise,

the processor will continue executing instructions after

the SLEEPinstruction. The instruction directly after the

SLEEP instruction will always be executed before

branching to the ISR. Refer to Section 8.0

“Power-Down Mode (Sleep)” for more details.

7.4

INT Pin

The INT pin can be used to generate an asynchronous

edge-triggered interrupt. This interrupt is enabled by

setting the INTE bit of the INTCON register. The

INTEDG bit of the OPTION_REG register determines on

which edge the interrupt will occur. When the INTEDG

bit is set, the rising edge will cause the interrupt. When

the INTEDG bit is clear, the falling edge will cause the

interrupt. The INTF bit of the INTCON register will be set

when a valid edge appears on the INT pin. If the GIE and

INTE bits are also set, the processor will redirect

program execution to the interrupt vector.

7.5

Automatic Context Saving

Upon entering an interrupt, the return PC address is

saved on the stack. Additionally, the following registers

are automatically saved in the shadow registers:

• W register

• STATUS register (except for TO and PD)

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these regis-

ters are automatically restored. Any modifications to

these registers during the ISR will be lost. If modifica-

tions to any of these registers are desired, the corre-

sponding shadow register should be modified and the

value will be restored when exiting the ISR. The

shadow registers are available in Bank 31 and are

readable and writable. Depending on the user’s appli-

cation, other registers may also need to be saved.

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7.6

Interrupt Control Registers

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

7.6.1

INTCON REGISTER

The INTCON register is a readable and writable

register, which contains the various enable and flag bits

for TMR0 register overflow, interrupt-on-change and

external INT pin interrupts.

REGISTER 7-1:

INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0

GIE

R/W-0/0

PEIE

R/W-0/0

TMR0IE

R/W-0/0

INTE

R/W-0/0

IOCIE

R/W-0/0

TMR0IF

R/W-0/0

INTF

R-0/0

IOCIF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

GIE: Global Interrupt Enable bit

1= Enables all active interrupts

0= Disables all interrupts

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PEIE: Peripheral Interrupt Enable bit

1= Enables all active peripheral interrupts

0= Disables all peripheral interrupts

TMR0IE: Timer0 Overflow Interrupt Enable bit

1= Enables the Timer0 interrupt

0= Disables the Timer0 interrupt

INTE: INT External Interrupt Enable bit

1= Enables the INT external interrupt

0= Disables the INT external interrupt

IOCIE: Interrupt-on-Change Interrupt Enable bit

1= Enables the interrupt-on-change interrupt

0= Disables the interrupt-on-change interrupt

TMR0IF: Timer0 Overflow Interrupt Flag bit

1= TMR0 register has overflowed

0= TMR0 register did not overflow

INTF: INT External Interrupt Flag bit

1= The INT external interrupt occurred

0= The INT external interrupt did not occur

IOCIF: Interrupt-on-Change Interrupt Flag bit

1= When at least one of the interrupt-on-change pins changed state

0= None of the interrupt-on-change pins have changed state

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7.6.2

PIE1 REGISTER

The PIE1 register contains the interrupt enable bits, as

shown in Register 7-2.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 7-2:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0

TMR1GIE

bit 7

R/W-0/0

ADIE

R/W-0/0

RCIE

R/W-0/0

TXIE

U-0

—

U-0

—

U-0

—

R/W-0/0

TMR1IE

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

TMR1GIE: Timer1 Gate Interrupt Enable bit

1= Enables the Timer1 gate acquisition interrupt

0= Disables the Timer1 gate acquisition interrupt

ADIE: A/D Converter (ADC) Interrupt Enable bit

1= Enables the ADC interrupt

0= Disables the ADC interrupt

RCIE: USART Receive Interrupt Enable bit

1= Enables the USART receive interrupt

0= Disables the USART receive interrupt

TXIE: USART Transmit Interrupt Enable bit

1= Enables the USART transmit interrupt

0= Disables the USART transmit interrupt

bit 3-1

bit 0

Unimplemented: Read as ‘0’

TMR1IE: Timer1 Overflow Interrupt Enable bit

1= Enables the Timer1 overflow interrupt

0= Disables the Timer1 overflow interrupt

.

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7.6.3

PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as

shown in Register 7-3.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 7-3:

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

LCDIE

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-3

bit 2

Unimplemented: Read as ‘0’

LCDIE: LCD Module Interrupt Enable bit

1= Enables the LCD module interrupt

0= Disables the LCD module interrupt

bit 1-0

Unimplemented: Read as ‘0’

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7.6.4

PIR1 REGISTER

The PIR1 register contains the interrupt flag bits, as

shown in Register 7-4.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

REGISTER 7-4:

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0

TMR1GIF

bit 7

R/W-0/0

ADIF

R/W-0/0

RCIF

R/W-0/0

TXIF

U-0

—

U-0

—

U-0

—

R/W-0/0

TMR1IF

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

bit 6

bit 5

bit 4

TMR1GIF: Timer1 Gate Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

ADIF: A/D Converter Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

RCIF: USART Receive Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

TXIF: USART Transmit Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 3-1

bit 0

Unimplemented: Read as ‘0’

TMR1IF: Timer1 Overflow Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

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7.6.5

PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as

shown in Register 7-5.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

REGISTER 7-5:

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

LCDIF

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-3

bit 2

Unimplemented: Read as ‘0’

LCDIF: LCD Module Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 1-0

Unimplemented: Read as ‘0’

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TABLE 7-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Register

on Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

PEIE

TMR0IE

T0CS

RCIE

—

INTE

T0SE

TXIE

—

IOCIE

PSA

—

TMR0IF

INTF

IOCIF

65

130

66

OPTION_REG WPUEN INTEDG

PS<2:0>

PIE1

PIE2

PIR1

PIR2

TMR1GIE

—

ADIE

—

TMR1IE

—

LCDIE

—

67

TMR1GIF

—

ADIF

—

RCIF

—

TXIF

—

TMR1IF

—

68

—

LCDIF

69

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts.

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8.1

Wake-up from Sleep

8.0

POWER-DOWN MODE (SLEEP)

The device can wake-up from Sleep through one of the

following events:

The Power-Down mode is entered by executing a

SLEEPinstruction.

1. External Reset input on MCLR pin, if enabled

2. BOR Reset, if enabled

Upon entering Sleep mode, the following conditions

exist:

3. POR Reset

1. WDT will be cleared but keeps running, if

enabled for operation during Sleep.

4. Watchdog Timer, if enabled

5. Any external interrupt

2. PD bit of the STATUS register is cleared.

3. TO bit of the STATUS register is set.

4. CPU clock is disabled.

6. Interrupts by peripherals capable of running

during Sleep (see individual peripheral for more

information)

5. 31 kHz LFINTOSC is unaffected and peripherals

that operate from it may continue operation in

Sleep.

The first three events will cause a device Reset. The

last three events are considered a continuation of pro-

gram execution. To determine whether a device Reset

or wake-up event occurred, refer to Section 5.11,

Determining the Cause of a Reset.

6. Secondary oscillator is unaffected and peripher-

als that operate from it may continue operation

in Sleep.

7. ADC is unaffected, if the dedicated FRC clock is

selected.

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be enabled. Wake-up will

occur regardless of the state of the GIE bit. If the GIE

bit is disabled, the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

enabled, the device executes the instruction after the

SLEEPinstruction, the device will call the Interrupt Ser-

vice Routine. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOPafter the SLEEPinstruction.

8. Capacitive Sensing oscillator is unaffected.

9. I/O ports maintain the status they had before

SLEEP was executed (driving high, low or

high-impedance).

10. Resets other than WDT are not affected by

Sleep mode.

Refer to individual chapters for more details on

peripheral operation during Sleep.

To minimize current consumption, the following condi-

tions should be considered:

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• Modules using Secondary oscillator

I/O pins that are high-impedance inputs should be

pulled to VDD or VSS externally to avoid switching cur-

rents caused by floating inputs.

Examples of internal circuitry that might be sourcing

current include the FVR module. See 13.0 “Fixed Volt-

age Reference (FVR)” for more information.

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• If the interrupt occurs during or after the execu-

tion of a SLEEPinstruction

8.1.1

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

- SLEEPinstruction will be completely

executed

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

- TO bit of the STATUS register will be set

- PD bit of the STATUS register will be cleared.

• If the interrupt occurs before the execution of a

SLEEPinstruction

- SLEEPinstruction will execute as a NOP.

- WDT and WDT prescaler will not be cleared

- TO bit of the STATUS register will not be set

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

- PD bit of the STATUS register will not be

cleared.

FIGURE 8-1:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN⁽¹⁾

CLKOUT⁽²⁾

Interrupt Latency⁽¹⁾

Interrupt flag

GIE bit

(INTCON reg.)

Processor in

Sleep

Instruction Flow

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Fetched

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Instruction

Executed

Dummy Cycle

Sleep

Inst(PC + 1)

Inst(PC - 1)

Inst(0004h)

Note 1:

GIE = 1assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

TABLE 8-1:

SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Register on

Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

IOCBF

IOCBN

IOCBP

PIE1

GIE

PEIE

IOCBF6

IOCBN6

IOCBP6

ADIE

TMR0IE

IOCBF5

IOCBN5

IOCBP5

RCIE

—

INTE

IOCBF4

IOCBN4

IOCBP4

TXIE

—

IOCIE

TMR0IF

IOCBF2

IOCBN2

IOCBP2

—

INTF

IOCBF1

IOCBN1

IOCBP1

—

IOCIF

IOCBF0

IOCBN0

IOCBP0

TMR1IE

—

65

110

66

IOCBF7

IOCBN7

IOCBP7

TMR1GIE

—

IOCBF3

IOCBN3

IOCBP3

—

PIE2

—

LCDIE

—

67

TMR1GIF

ADIF

TMR1IF

PIR1

RCIF

—

TXIF

—

68

PIR2

—

PD

LCDIF

Z

—

C

69

STATUS

WDTCON

—

TO

DC

21

WDTPS<4:0>

SWDTEN

75

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used in Power-down mode.

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9.0

WATCHDOG TIMER

The Watchdog Timer is a system timer that generates

a Reset if the firmware does not issue a CLRWDT

instruction within the time-out period. The Watchdog

Timer is typically used to recover the system from

unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256

seconds (typical)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 9-1:

WATCHDOG TIMER BLOCK DIAGRAM

WDTE<1:0> = 01

SWDTEN

23-bit Programmable

WDT Time-out

WDTE<1:0> = 11

LFINTOSC

Prescaler WDT

WDTE<1:0> = 10

Sleep

WDTPS<4:0>

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9.1

Independent Clock Source

9.3

Time-Out Period

The WDT derives its time base from the 31 kHz

LFINTOSC internal oscillator. Time intervals in this

chapter are based on a nominal interval of 1ms. See

Section 22.0 “Electrical Specifications” for the

LFINTOSC tolerances.

The WDTPS bits of the WDTCON register set the

time-out period from 1 ms to 256 seconds (nominal).

After a Reset, the default time-out period is two

seconds.

9.4

Clearing the WDT

9.2

WDT Operating Modes

The WDT is cleared when any of the following condi-

tions occur:

The Watchdog Timer module has four operating modes

controlled by the WDTE<1:0> bits in Configuration

Word 1. See Table 9-1.

• Any Reset

• CLRWDTinstruction is executed

• Device enters Sleep

9.2.1

WDT IS ALWAYS ON

• Device wakes up from Sleep

• Oscillator fail event

When the WDTE bits of Configuration Word 1 are set to

‘11’, the WDT is always on.

• WDT is disabled

WDT protection is active during Sleep.

• Oscillator Start-up TImer (OST) is running

9.2.2

WDT IS OFF IN SLEEP

See Table 9-2 for more information.

When the WDTE bits of Configuration Word 1 are set to

‘10’, the WDT is on, except in Sleep.

9.5

Operation During Sleep

WDT protection is not active during Sleep.

When the device enters Sleep, the WDT is cleared. If

the WDT is enabled during Sleep, the WDT resumes

counting.

9.2.3

WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Word 1 are set to

‘01’, the WDT is controlled by the SWDTEN bit of the

WDTCON register.

When the device exits Sleep, the WDT is cleared

again. The WDT remains clear until the OST, if

enabled, completes. See Section 6.0 “Oscillator

Module” for more information on the OST.

WDT protection is unchanged by Sleep. See Table 9-1

for more details.

When a WDT time-out occurs while the device is in

Sleep, no Reset is generated. Instead, the device

wakes up and resumes operation. The TO and PD bits

in the STATUS register are changed to indicate the

event. See Section 3.0 “Memory Organization” and

STATUS register (Register 3-1) for more information.

TABLE 9-1:

WDTE<1:0>

WDT OPERATING MODES

Device

Mode

WDT

Mode

SWDTEN

11

10

X

Active

Awake

Sleep Disabled

1

0

X

Active

X

01

Disabled

00

X

Disabled

TABLE 9-2:

WDT CLEARING CONDITIONS

Conditions

WDT

WDTE<1:0> = 00

WDTE<1:0> = 01 and SWDTEN = 0

WDTE<1:0> = 10 and enter Sleep

CLRWDTCommand

Cleared

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK

Change INTOSC divider (IRCF bits)

Unaffected

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9.6

Watchdog Control Register

REGISTER 9-1:

WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0

—

U-0

—

R/W-0/0

R/W-1/1

R/W-0/0

R/W-1/1

R/W-0/0

WDTPS<4:0>

SWDTEN

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-m/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-1

Unimplemented: Read as ‘0’

WDTPS<4:0>: Watchdog Timer Period Select bits⁽¹⁾

Bit Value = Prescale Rate

00000 = 1:32 (Interval 1 ms nominal)

00001 = 1:64 (Interval 2 ms nominal)

00010 = 1:128 (Interval 4 ms nominal)

00011 = 1:256 (Interval 8 ms nominal)

00100 = 1:512 (Interval 16 ms nominal)

00101 = 1:1024 (Interval 32 ms nominal)

00110 = 1:2048 (Interval 64 ms nominal)

00111 = 1:4096 (Interval 128 ms nominal)

01000 = 1:8192 (Interval 256 ms nominal)

01001 = 1:16384 (Interval 512 ms nominal)

01010 = 1:32768 (Interval 1s nominal)

01011 = 1:65536 (Interval 2s nominal) (Reset value)

01100 = 1:131072 (2¹⁷) (Interval 4s nominal)

01101 = 1:262144 (2¹⁸) (Interval 8s nominal)

01110 = 1:524288 (2¹⁹) (Interval 16s nominal)

01111 = 1:1048576 (2²⁰) (Interval 32s nominal)

10000 = 1:2097152 (2²¹) (Interval 64s nominal)

10001 = 1:4194304 (2²²) (Interval 128s nominal)

10010 = 1:8388608 (2²³) (Interval 256s nominal)

10011 = Reserved. Results in minimum interval (1:32)

•

11111 = Reserved. Results in minimum interval (1:32)

bit 0

SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> = 00:

This bit is ignored.

If WDTE<1:0> = 01:

1= WDT is turned on

0= WDT is turned off

If WDTE<1:0> = 1x:

This bit is ignored.

Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

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TABLE 9-3:

SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCCON

STATUS

—

IRCF<3:0>

—

Z

SCS<1:0>

DC

58

21

75

—

TO

PD

C

WDTCON

WDTPS<4:0>

SWDTEN

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.

TABLE 9-4:

SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

CLKOUTEN

BOREN<1:0>

—

CONFIG1

39

CP

MCLRE

PWRTE

WDTE<1:0>

—

FOSC<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

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10.1.1

PMCON1 AND PMCON2

REGISTERS

10.0 FLASH PROGRAM MEMORY

CONTROL

PMCON1 is the control register for Flash Program

Memory accesses.

The Flash Program Memory is readable and writable

during normal operation over the full VDD range.

Program memory is indirectly addressed using Special

Function Registers (SFRs). The SFRs used to access

program memory are:

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared by hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

• PMCON1

• PMCON2

• PMDATL

• PMDATH

• PMADRL

• PMADRH

The WREN bit, when set, will allow a write operation to

occur. On power-up, the WREN bit is clear. The

WRERR bit is set when a write operation is interrupted

by a Reset during normal operation. In these situations,

following Reset, the user can check the WRERR bit

and execute the appropriate error handling routine.

When accessing the program memory, the

PMDATH:PMDATL register pair forms a 2-byte word

that holds the 14-bit data for read/write, and the

PMADRH:PMADRL register pair forms a 2-byte word

that holds the 15-bit address of the program memory

location being read.

The PMCON2 register is a write-only register. Attempting

to read the PMCON2 register will return all ‘0’s.

To enable writes to the program memory, a specific

pattern (the unlock sequence), must be written to the

PMCON2 register. The required unlock sequence

prevents inadvertent writes to the program memory

write latches and Flash Program Memory.

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip charge

pump rated to operate over the operating voltage range

of the device.

10.2 Flash Program Memory Overview

The Flash Program Memory can be protected in two

ways; by code protection (CP bit in Configuration Word 1)

and write protection (WRT<1:0> bits in Configuration

Word 2).

Code protection (CP = 0)⁽¹⁾, disables access, reading

and writing, to the Flash Program Memory via external

device programmers. Code protection does not affect

the self-write and erase functionality. Code protection

can only be reset by a device programmer performing

a Bulk Erase to the device, clearing all Flash Program

Memory, Configuration bits and User IDs.

It is important to understand the Flash Program Memory

structure for erase and programming operations. Flash

Program Memory is arranged in rows. A row consists of

a fixed number of 14-bit program memory words. A row

is the minimum size that can be erased by user software.

After a row has been erased, the user can reprogram

all or a portion of this row. Data to be written into the

program memory row is written to 14-bit wide data write

latches. These write latches are not directly accessible

to the user, but may be loaded via sequential writes to

the PMDATH:PMDATL register pair.

Write protection prohibits self-write and erase to a

portion or all of the Flash Program Memory as defined

by the bits WRT<1:0>. Write protection does not affect

a device programmers ability to read, write or erase the

device.

Note:

If the user wants to modify only a portion

of a previously programmed row, then the

contents of the entire row must be read

and saved in RAM prior to the erase.

Then, new data and retained data can be

written into the write latches to reprogram

the row of Flash Program Memory. How-

ever, any unprogrammed locations can be

written without first erasing the row. In this

case, it is not necessary to save and

rewrite the other previously programmed

locations.

Note 1: Code protection of the entire Flash

Program Memory array is enabled by

clearing the CP bit of Configuration Word 1.

10.1 PMADRL and PMADRH Registers

The PMADRH:PMADRL register pair can address up

to a maximum of 32K words of program memory. When

selecting a program address value, the MSB of the

address is written to the PMADRH register and the LSB

is written to the PMADRL register.

See Table 10-1 for Erase Row size and the number of

write latches for Flash program memory.

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FIGURE 10-1:

FLASH PROGRAM

MEMORY READ

FLOWCHART

TABLE 10-1: FLASH MEMORY

ORGANIZATION BY DEVICE

Write

Latches

(words)

Row Erase

(words)

Device

Start

Read Operation

PIC16LF1904/6/7

32

Select

10.2.1

READING THE FLASH PROGRAM

MEMORY

Program or Configuration Memory

(CFGS)

To read a program memory location, the user must:

1. Write the desired address to the

PMADRH:PMADRL register pair.

2. Clear the CFGS bit of the PMCON1 register.

Select

Word Address

(PMADRH:PMADRL)

3. Then, set control bit RD of the PMCON1 register.

Once the read control bit is set, the program memory

Flash controller will use the second instruction cycle to

read the data. This causes the second instruction

immediately following the “BSF PMCON1,RD” instruction

to be ignored. The data is available in the very next cycle,

in the PMDATH:PMDATL register pair; therefore, it can

be read as two bytes in the following instructions.

Initiate Read operation

(RD = 1)

Instruction Fetched ignored

NOPexecution forced

PMDATH:PMDATL register pair will hold this value until

another read or until it is written to by the user.

Instruction Fetched ignored

Note:

The two instructions following a program

memory read are required to be NOPs.

This prevents the user from executing a

2-cycle instruction on the next instruction

after the RD bit is set.

NOPexecution forced

Data read now in

PMDATH:PMDATL

End

Read Operation

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FIGURE 10-2:

FLASH PROGRAM MEMORY READ CYCLE EXECUTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

PC + 1

PMADRH,PMADRL

PC + 3

PC+3

PC + 4

PC + 5

Flash ADDR

Flash Data

INSTR (PC)

INSTR (PC + 1)

PMDATH,PMDATL

INSTR (PC + 3)

INSTR (PC + 4)

INSTR(PC + 1)

INSTR(PC + 2)

instruction ignored instruction ignored

BSF PMCON1,RD

executed here

INSTR(PC - 1)

executed here

INSTR(PC + 3)

executed here

INSTR(PC + 4)

executed here

Forced NOP

executed here

RD bit

PMDATH

PMDATL

Register

EXAMPLE 10-1:

FLASH PROGRAM MEMORY READ

* This code block will read 1 word of program

* memory at the memory address:

PROG_ADDR_HI : PROG_ADDR_LO

*

data will be returned in the variables;

PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL

; Select Bank for PMCON registers

MOVLW

MOVWF

MOVLW

MOVWL

PROG_ADDR_LO

PMADRL

PROG_ADDR_HI

PMADRH

;

; Store LSB of address

;

; Store MSB of address

BCF

BSF

NOP

PMCON1,CFGS

PMCON1,RD

; Do not select Configuration Space

; Initiate read

; Ignored (Figure 10-1)

MOVF

PMDATL,W

; Get LSB of word

MOVWF

MOVF

PROG_DATA_LO

PMDATH,W

; Store in user location

; Get MSB of word

MOVWF

PROG_DATA_HI

; Store in user location

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10.2.2

FLASH MEMORY UNLOCK

SEQUENCE

FIGURE 10-3:

FLASH PROGRAM

MEMORY UNLOCK

SEQUENCE FLOWCHART

The unlock sequence is a mechanism that protects the

Flash Program Memory from unintended self-write pro-

gramming or erasing. The sequence must be executed

and completed without interruption to successfully

complete any of the following operations:

Start

Unlock Sequence

• Row Erase

• Load program memory write latches

Write 055h to

PMCON2

• Write of program memory write latches to

program memory

• Write of program memory write latches to User

IDs

Write 0AAh to

PMCON2

The unlock sequence consists of the following steps:

1. Write 55h to PMCON2

Initiate

Write or Erase operation

(WR = 1)

2. Write AAh to PMCON2

3. Set the WR bit in PMCON1

4. NOPinstruction

5. NOPinstruction

Instruction Fetched ignored

NOP execution forced

Once the WR bit is set, the processor will always force

two NOP instructions. When an Erase Row or Program

Row operation is being performed, the processor will stall

internal operations (typical 2 ms), until the operation is

complete and then resume with the next instruction.

When the operation is loading the program memory write

latches, the processor will always force the two NOP

instructions and continue uninterrupted with the next

instruction.

Instruction Fetched ignored

NOP execution forced

End

Unlock Sequence

Since the unlock sequence must not be interrupted,

global interrupts should be disabled prior to the unlock

sequence and re-enabled after the unlock sequence is

completed.

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10.2.3

ERASING FLASH PROGRAM

MEMORY

FIGURE 10-4:

FLASH PROGRAM

MEMORY ERASE

FLOWCHART

While executing code, program memory can only be

erased by rows. To erase a row:

1. Load the PMADRH:PMADRL register pair with

any address within the row to be erased.

Start

Erase Operation

2. Clear the CFGS bit of the PMCON1 register.

3. Set the FREE and WREN bits of the PMCON1

register.

Disable Interrupts

(GIE = 0)

4. Write 55h, then AAh, to PMCON2 (Flash

programming unlock sequence).

5. Set control bit WR of the PMCON1 register to

begin the erase operation.

Select

Program or Configuration Memory

(CFGS)

See Example 10-2.

After the “BSF PMCON1,WR” instruction, the processor

requires two cycles to set up the erase operation. The

user must place two NOPinstructions after the WR bit is

set. The processor will halt internal operations for the

typical 2 ms erase time. This is not Sleep mode as the

clocks and peripherals will continue to run. After the

erase cycle, the processor will resume operation with

the third instruction after the PMCON1 write instruction.

Select Row Address

(PMADRH:PMADRL)

Select Erase Operation

(FREE = 1)

Enable Write/Erase Operation

(WREN = 1)

Unlock Sequence

Figure 10-3

(FIGURE x x)

CPU stalls while

Erase operation completes

(2 ms typical)

Disable Write/Erase Operation

(WREN = 0)

Re-enable Interrupts

(GIE = 1)

End

Erase Operation

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EXAMPLE 10-2:

ERASING ONE ROW OF PROGRAM MEMORY

; This row erase routine assumes the following:

; 1. A valid address within the erase row is loaded in ADDRH:ADDRL

; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

BCF

INTCON,GIE

PMADRL

ADDRL,W

PMADRL

ADDRH,W

; Disable ints so required sequences will execute properly

; Load lower 8 bits of erase address boundary

; Load upper 6 bits of erase address boundary

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

BCF

PMADRH

PMCON1,CFGS

PMCON1,FREE

PMCON1,WREN

; Not configuration space

; Specify an erase operation

; Enable writes

BSF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

55h

PMCON2

0AAh

PMCON2

PMCON1,WR

; Start of required sequence to initiate erase

; Write 55h

;

; Write AAh

; Set WR bit to begin erase

NOP

; NOP instructions are forced as processor starts

; row erase of program memory.

;

; The processor stalls until the erase process is complete

; after erase processor continues with 3rd instruction

BCF

BSF

PMCON1,WREN

INTCON,GIE

; Disable writes

; Enable interrupts

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The following steps should be completed to load the

write latches and program a row of program memory.

These steps are divided into two parts. First, each write

latch is loaded with data from the PMDATH:PMDATL

using the unlock sequence with LWLO = 1. When the

last word to be loaded into the write latch is ready, the

LWLO bit is cleared and the unlock sequence

executed. This initiates the programming operation,

writing all the latches into Flash Program Memory.

10.2.4

WRITING TO FLASH PROGRAM

MEMORY

Program memory is programmed using the following

steps:

1. Load the address in PMADRH:PMADRL of the

row to be programmed.

2. Load each write latch with data.

3. Initiate a programming operation.

4. Repeat steps 1 through 3 until all data is written.

Note:

The special unlock sequence is required

to load a write latch with data or initiate a

Flash programming operation. If the

unlock sequence is interrupted, writing to

the latches or program memory will not be

initiated.

Before writing to program memory, the word(s) to be

written must be erased or previously unwritten. Pro-

gram memory can only be erased one row at a time. No

automatic erase occurs upon the initiation of the write.

Program memory can be written one or more words at

a time. The maximum number of words written at one

time is equal to the number of write latches. See

Figure 10-2 (row writes to program memory with 32

write latches) for more details.

1. Set the WREN bit of the PMCON1 register.

2. Clear the CFGS bit of the PMCON1 register.

3. Set the LWLO bit of the PMCON1 register.

When the LWLO bit of the PMCON1 register is

‘1’, the write sequence will only load the write

latches and will not initiate the write to Flash

Program Memory.

The write latches are aligned to the Flash row address

boundary defined by the upper ten bits of

PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>)

with the lower five bits of PMADRL, (PMADRL<4:0>)

determining the write latch being loaded. Write opera-

tions do not cross these boundaries. At the completion

of a program memory write operation, the data in the

write latches is reset to contain 0x3FFF.

4. Load the PMADRH:PMADRL register pair with

the address of the location to be written.

5. Load the PMDATH:PMDATL register pair with

the program memory data to be written.

6. Execute the unlock sequence (Section 10.2.2

“Flash Memory Unlock Sequence”). The write

latch is now loaded.

7. Increment the PMADRH:PMADRL register pair

to point to the next location.

8. Repeat steps 5 through 7 until all but the last

write latch has been loaded.

9. Clear the LWLO bit of the PMCON1 register.

When the LWLO bit of the PMCON1 register is

‘0’, the write sequence will initiate the write to

Flash Program Memory.

10. Load the PMDATH:PMDATL register pair with

the program memory data to be written.

11. Execute the unlock sequence (Section 10.2.2

“Flash Memory Unlock Sequence”). The

entire program memory latch content is now

written to Flash Program Memory.

Note:

The program memory write latches are

reset to the blank state (0x3FFF) at the

completion of every write or erase

operation. As a result, it is not necessary

to load all the program memory write

latches. Unloaded latches will remain in

the blank state.

An example of the complete write sequence is shown in

Example 10-3. The initial address is loaded into the

PMADRH:PMADRL register pair; the data is loaded

using indirect addressing.

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FIGURE 10-6:

FLASH PROGRAM MEMORY WRITE FLOWCHART

Start

Write Operation

Determine number of words

to be written into Program or

Configuration Memory.

The number of words cannot

exceed the number of words

per row.

Enable Write/Erase

Operation (WREN = 1)

Load the value to write

(PMDATH:PMDATL)

(word_cnt)

Update the word counter

(word_cnt--)

Write Latches to Flash

Disable Interrupts

(LWLO = 0)

(GIE = 0)

Unlock Sequence

(Figure x-x)

Figure 10-3

Select

Program or Config. Memory

(CFGS)

Yes

Last word to

write ?

CPU stalls while Write

operation completes

(2 ms typical)

No

Select Row Address

(PMADRH:PMADRL)

Unlock Sequence

(Figure x-x)

Figure 10-3

Select Write Operation

(FREE = 0)

Disable

Write/Erase Operation

(WREN = 0)

No delay when writing to

Program Memory Latches

Load Write Latches Only

(LWLO = 1)

Re-enable Interrupts

(GIE = 1)

Increment Address

(PMADRH:PMADRL++)

End

Write Operation

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EXAMPLE 10-3:

WRITING TO FLASH PROGRAM MEMORY

; This write routine assumes the following:

; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR

; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,

;

stored in little endian format

; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL

; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

;

BCF

INTCON,GIE

PMADRH

ADDRH,W

PMADRH

ADDRL,W

PMADRL

; Disable ints so required sequences will execute properly

; Bank 3

; Load initial address

;

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BCF

LOW DATA_ADDR ; Load initial data address

FSR0L

HIGH DATA_ADDR ; Load initial data address

;

FSR0H

;

PMCON1,CFGS

PMCON1,WREN

PMCON1,LWLO

; Not configuration space

; Enable writes

; Only Load Write Latches

BSF

LOOP

MOVIW

MOVWF

MOVIW

MOVWF

FSR0++

PMDATL

FSR0++

PMDATH

; Load first data byte into lower

;

; Load second data byte into upper

;

MOVF

PMADRL,W

0x1F

STATUS,Z

START_WRITE

; Check if lower bits of address are '00000'

; Check if we're on the last of 32 addresses

;

; Exit if last of 32 words,

;

XORLW

ANDLW

BTFSC

GOTO

MOVLW

MOVWF

MOVLW

MOVWF

BSF

55h

PMCON2

0AAh

PMCON2

PMCON1,WR

; Start of required write sequence:

; Write 55h

;

; Write AAh

; Set WR bit to begin write

; NOP instructions are forced as processor

; loads program memory write latches

;

NOP

INCF

GOTO

PMADRL,F

LOOP

; Still loading latches Increment address

; Write next latches

START_WRITE

BCF

PMCON1,LWLO

; No more loading latches - Actually start Flash program

; memory write

MOVLW

55h

PMCON2

0AAh

PMCON2

PMCON1,WR

; Start of required write sequence:

; Write 55h

;

MOVWF

MOVLW

MOVWF

BSF

; Write AAh

; Set WR bit to begin write

; NOP instructions are forced as processor writes

; all the program memory write latches simultaneously

; to program memory.

NOP

; After NOPs, the processor

; stalls until the self-write process in complete

; after write processor continues with 3rd instruction

; Disable writes

BCF

BSF

PMCON1,WREN

INTCON,GIE

; Enable interrupts

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FIGURE 10-7:

FLASH PROGRAM

MEMORY MODIFY

FLOWCHART

10.3 Modifying Flash Program Memory

When modifying existing data in a program memory

row, and data within that row must be preserved, it must

first be read and saved in a RAM image. Program

memory is modified using the following steps:

Start

Modify Operation

1. Load the starting address of the row to be

modified.

2. Read the existing data from the row into a RAM

image.

Read Operation

(Figure x.x)

Figure 10-1

3. Modify the RAM image to contain the new data

to be written into program memory.

4. Load the starting address of the row to be

rewritten.

An image of the entire row read

must be stored in RAM

5. Erase the program memory row.

6. Load the write latches with data from the RAM

image.

7. Initiate a programming operation.

Modify Image

The words to be modified are

changed in the RAM image

Erase Operation

(Figure x.x)

Figure 10-4

Write Operation

use RAM image

(Figure x.x)

Figure 10-5

End

Modify Operation

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10.4 User ID, Device ID and

Configuration Word Access

Instead of accessing program memory, the User ID’s,

Device ID/Revision ID and Configuration Words can be

accessed when CFGS = 1 in the PMCON1 register.

This is the region that would be pointed to by

PC<15> = 1, but not all addresses are accessible.

Different access may exist for reads and writes. Refer

to Table 10-2.

When read access is initiated on an address outside

the

parameters

listed

in

Table 10-2,

the

PMDATH:PMDATL register pair is cleared, reading

back ‘0’s.

TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)

Address

Function

Read Access

Write Access

8000h-8003h

8006h

User IDs

Yes

No

Device ID/Revision ID

8007h-8008h

Configuration Words 1 and 2

EXAMPLE 10-4:

CONFIGURATION WORD AND DEVICE ID ACCESS

* This code block will read 1 word of program memory at the memory address:

*

PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;

PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL

; Select correct Bank

;

; Store LSB of address

; Clear MSB of address

MOVLW

MOVWF

CLRF

PROG_ADDR_LO

PMADRL

PMADRH

BSF

BCF

BSF

NOP

BSF

PMCON1,CFGS

INTCON,GIE

PMCON1,RD

; Select Configuration Space

; Disable interrupts

; Initiate read

; Executed (See Figure 10-1)

; Ignored (See Figure 10-1)

; Restore interrupts

INTCON,GIE

MOVF

PMDATL,W

; Get LSB of word

MOVWF

MOVF

PROG_DATA_LO

PMDATH,W

; Store in user location

; Get MSB of word

MOVWF

PROG_DATA_HI

; Store in user location

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10.5 Write Verify

It is considered good programming practice to verify that

program memory writes agree with the intended value.

Since program memory is stored as a full page then the

stored program memory contents are compared with the

intended data stored in RAM after the last write is

complete.

FIGURE 10-8:

FLASH PROGRAM

MEMORY VERIFY

FLOWCHART

Start

Verify Operation

This routine assumes that the last row

of data written was from an image

saved in RAM. This image will be used

to verify the data currently stored in

Flash program memory.

Read Operation

(Figure x.x)

Figure 10-1

PMDAT =

RAM image

?

No

Fail

Verify Operation

Yes

No

Last

Word ?

Yes

End

Verify Operation

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10.6 Flash Program Memory Control Registers

REGISTER 10-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

R/W-x/u

PMDAT<7:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

PMDAT<7:0>: Read/write value for Least Significant bits of program memory

REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0

—

U-0

—

R/W-x/u

PMDAT<13:8>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

PMDAT<13:8>: Read/write value for Most Significant bits of program memory

REGISTER 10-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

R/W-0/0

PMADR<7:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

PMADR<7:0>: Specifies the Least Significant bits for program memory address

REGISTER 10-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-1

—

R/W-0/0

PMADR<14:8>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

Unimplemented: Read as ‘1’

PMADR<14:8>: Specifies the Most Significant bits for program memory address

bit 6-0

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REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

U-1⁽¹⁾

—

R/W-0/0

CFGS

R/W-0/0

LWLO

R/W/HC-0/0 R/W/HC-x/q⁽²⁾

FREE WRERR

R/W-0/0

WREN

R/S/HC-0/0

WR

R/S/HC-0/0

RD

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

S = Bit can only be set

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7

bit 6

Unimplemented: Read as ‘1’

CFGS: Configuration Select bit

1= Access Configuration, User ID and Device ID registers

0= Access Flash Program Memory

bit 5

LWLO: Load Write Latches Only bit⁽³⁾

1= Only the addressed program memory write latch is loaded/updated on the next WR command

0= The addressed program memory write latch is loaded/updated and a write of all program memory write latches

will be initiated on the next WR command

bit 4

bit 3

FREE: Program Flash Erase Enable bit

1= Performs an erase operation on the next WR command (hardware cleared upon completion)

0= Performs a write operation on the next WR command

WRERR: Program/Erase Error Flag bit

1= Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically

on any set attempt (write ‘1’) of the WR bit).

0= The program or erase operation completed normally.

bit 2

bit 1

WREN: Program/Erase Enable bit

1= Allows program/erase cycles

0= Inhibits programming/erasing of program Flash

WR: Write Control bit

1= Initiates a program Flash program/erase operation.

The operation is self-timed and the bit is cleared by hardware once operation is complete.

The WR bit can only be set (not cleared) in software.

0= Program/erase operation to the Flash is complete and inactive.

bit 0

RD: Read Control bit

1= Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set

(not cleared) in software.

0= Does not initiate a program Flash read.

Note 1: Unimplemented bit, read as ‘1’.

2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1) .

3: The LWLO bit is ignored during a program memory erase operation (FREE = 1).

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REGISTER 10-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER

W-0/0

bit 0

Program Memory Control Register 2

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

S = Bit can only be set

‘1’ = Bit is set

bit 7-0

Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the

PMCON1 register. The value written to this register is used to unlock the writes. There are specific

timing requirements on these writes.

TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

Register on

Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

PMCON1

PMCON2

PMADRL

CFGS

LWLO

FREE

WRERR

WREN

WR

RD

—

91

92

90

65

Program Memory Control Register 2

PMADRL<7:0>

(1)

PMADRH

PMDATL

—

PMADRH<6:0>

PMDATL<7:0>

PMDATH

INTCON

Legend:

—

PMDATH<5:0>

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

— = unimplemented location, read as ‘0’. Shaded cells are not used by the Flash Program Memory module.

Note 1: Unimplemented, read as ‘1’.

TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

CP

—

MCLRE

—

PWRTE

LVP

—

CLKOUTEN

BOREN<1:0>

—

CONFIG1

39

40

WDTE<1:0>

—

BORV

—

FOSC<1:0>

13:8

7:0

DEBUG

—

LPBOR

—

STVREN

WRT<1:0>

—

CONFIG2

—

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by the Flash Program Memory.

DS40001569D-page 92

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 11-1:

GENERIC I/O PORT

OPERATION

11.0 I/O PORTS

In general, when a peripheral is enabled on a port pin,

that pin cannot be used as a general purpose output.

However, the pin can still be read.

Each port has three standard registers for its operation.

These registers are:

Read LATx

TRISx

D

Q

• TRISx registers (data direction)

• PORTx registers (reads the levels on the pins of

the device)

Write LATx

Write PORTx

CK

Data Register

VDD

• LATx registers (output latch)

Some ports may have one or more of the following

additional registers. These registers are:

Data Bus

I/O pin

• ANSELx (analog select)

• WPUx (weak pull-up)

Read PORTx

To peripherals

VSS

ANSELx

TABLE 11-1: PORT AVAILABILITY PER

DEVICE

EXAMPLE 11-1:

INITIALIZING PORTA

Device

; This code example illustrates

; initializing the PORTA register. The

; other ports are initialized in the same

; manner.

PIC16LF1906

●

PIC16LF1904/7

●

BANKSEL PORTA

CLRF PORTA

BANKSEL LATA

CLRF LATA

BANKSEL ANSELA

CLRF ANSELA

BANKSEL TRISA

;

The data latch (LATA register) is useful for

read-modify-write operations on the value that the I/O

pins are driving.

;Init PORTA

;Data Latch

;

;digital I/O

;

A write operation to the LATA register has the same

affect as a write to the corresponding PORTA register.

A read of the LATA register reads of the values held in

the I/O port latches, while a read of the PORTA register

reads the actual I/O pin value.

MOVLW

MOVWF

B'00111000' ;Set RA<5:3> as inputs

TRISA

;and set RA<2:0> as

;outputs

Ports that support analog inputs have an associated

ANSELx register. When an ANSEL bit is set, the digital

input buffer associated with that bit is disabled.

Disabling the input buffer prevents analog signal levels

on the pin between a logic high and low from causing

excessive current in the logic input circuitry. A

simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in Figure 11-1.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 93

PIC16LF1904/6/7

11.1.2

PORTA FUNCTIONS AND OUTPUT

PRIORITIES

11.1 PORTA Registers

PORTA is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 11-2). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., disable the

output driver). Clearing a TRISA bit (= 0) will make the

corresponding PORTA pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). The exception is RA3, which is

input only and its TRIS bit will always read as ‘1’.

Example 11-1 shows how to initialize PORTA.

Each PORTA pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are shown in Table 11-2.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

Analog input functions, such as ADC, comparator and

CapSense inputs, are not shown in the priority lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx registers. Digital

output functions may control the pin when it is in Analog

mode with the priority shown in Table 11-2.

Reading the PORTA register (Register 11-1) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch (LATA).

TABLE 11-2: PORTA OUTPUT PRIORITY

Pin Name

Function Priority⁽¹⁾

The TRISA register (Register 11-2) controls the

PORTA pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits

in the TRISA register are maintained set when using

them as analog inputs. I/O pins configured as analog

input always read ‘0’.

RA0

SEG12 (LCD)

AN0

RA0

RA1

RA2

RA3

SEG7

AN1

RA1

11.1.1

ANSELA REGISTER

COM2

AN2

RA2

The ANSELA register (Register 11-4) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

VREF+

COM3

SEG15

AN3

The state of the ANSELA bits has no effect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

RA3

RA4

RA5

RA6

RA7

SEG4

T0CKI

RA4

SEG5

AN4

RA5

Note:

The ANSELA bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

CLKOUT

SEG1

RA6

CLKIN

SEG2

RA7

Note 1: Priority listed from highest to lowest.

DS40001569D-page 94

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

REGISTER 11-1: PORTA: PORTA REGISTER

R/W-x/x

RA7

R/W-x/x

RA6

R/W-x/x

RA5

R/W-x/x

RA4

R-x/x

RA3

R/W-x/x

RA2

R/W-x/x

RA1

R/W-x/x

RA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

(1)

bit 7-0

RA<7:0>: PORTA I/O Value bits

1= Port pin is > VIH

0= Port pin is < VIL

Note 1: Writes to PORTA are actually written to the corresponding LATA register. Reads from the PORTA register is

return of actual I/O pin values.

REGISTER 11-2: TRISA: PORTA TRI-STATE REGISTER

R/W-1/1

TRISA7

R/W-1/1

TRISA6

R/W-1/1

TRISA5

R/W-1/1

TRISA4

R-1/1

R/W-1/1

TRISA2

R/W-1/1

TRISA1

R/W-1/1

TRISA0

bit 0

TRISA3

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-4

TRISA<7:4>: PORTA Tri-State Control bits

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

bit 3

TRISA3: RA3 Port Tri-State Control bit

This bit is always ‘1’ as RA3 is an input only

bit 2-0

TRISA<2:0>: PORTA Tri-State Control bits

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

REGISTER 11-3: LATA: PORTA DATA LATCH REGISTER

R/W-x/u

LATA7

R/W-x/u

LATA6

R/W-x/u

LATA5

R/W-x/u

LATA4

R/W-x/u

LATA3

R/W-x/u

LATA2

R/W-x/u

LATA1

R/W-x/u

LATA0

bit 0

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

(1)

bit 7-4

LATA<7:0>: RA<7:4> Output Latch Value bits

Note 1: Writes to PORTA are actually written to the corresponding LATA register. Reads from the PORTA register is

return of actual I/O pin values.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 95

PIC16LF1904/6/7

REGISTER 11-4: ANSELA: PORTA ANALOG SELECT REGISTER

U-0

—

U-0

—

R/W-1/1

ANSA5

U-0

—

R/W-1/1

ANSA3

R/W-1/1

ANSA2

R/W-1/1

ANSA1

R/W-1/1

ANSA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-6

bit 5

Unimplemented: Read as ‘0’

ANSA5: Analog Select between Analog or Digital Function on pins RA5, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

bit 4

Unimplemented: Read as ‘0’

bit 3-0

ANSA<3:0>: Analog Select between Analog or Digital Function on pins RA<3:0>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Register

on Page

Name

ANSELA

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

—

ANSA5

LATA5

—

ANSA3

LATA3

PSA

ANSA2

LATA2

ANSA1

LATA1

PS<2:0>

RA1

ANSA0

LATA0

96

95

LATA

LATA7

WPUEN

RA7

LATA6

INTEDG

RA6

LATA4

TMR0SE

RA4

OPTION_REG

PORTA

TMR0CS

RA5

130

95

RA3

RA2

RA0

TRISA

TRISA7

TRISA6

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

95

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH PORTA

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

CLKOUTEN

BOREN<1:0>

—

CONFIG1

39

CP

MCLRE

PWRTE

WDTE<1:0>

—

FOSC<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.

DS40001569D-page 96

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

11.2.2

PORTB FUNCTIONS AND OUTPUT

PRIORITIES

11.2 PORTB Registers

PORTB is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISB

(Register 11-6). Setting a TRISB bit (= 1) will make the

corresponding PORTB pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISB bit (= 0) will make the corresponding

PORTB pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 11-1 shows how to initialize an I/O port.

Each PORTB pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are shown in Table 11-5.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

Analog input and some digital input functions are not

included in the list below. These input functions can

remain active when the pin is configured as an output.

Certain digital input functions override other port

functions and are included in Table 11-5.

Reading the PORTB register (Register 11-5) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch (LATB).

TABLE 11-5: PORTB OUTPUT PRIORITY

Pin Name

Function Priority⁽¹⁾

RB0

SEG0

AN12

INT

IOC

RB0

The TRISB register (Register 11-6) controls the PORTB

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISB register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

RB1

RB2

RB3

SEG24

AN10

VLCD1

IOC

11.2.1

ANSELB REGISTER

The ANSELB register (Register 11-8) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELB bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

RB1

SEG25

AN8

VLCD2

IOC

The state of the ANSELB bits has no effect on digital out-

put functions. A pin with TRIS clear and ANSELB set will

still operate as a digital output, but the Input mode will be

analog. This can cause unexpected behavior when exe-

cuting read-modify-write instructions on the affected

port.

RB2

SEG26

AN9

VLCD3

IOC

RB3

Note:

The ANSELB bits default to the Analog

mode after reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

RB4

RB5

RB6

RB7

COM0

AN11

IOC

RB4

COM1

AN13

IOC

RB5

ICDCLK

SEG14

IOC

RB6

ICDDAT

SEG13

IOC

RB7

Note 1: Priority listed from highest to lowest.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 97

PIC16LF1904/6/7

REGISTER 11-5: PORTB: PORTB REGISTER

R/W-x/u

RB7

R/W-x/u

RB6

R/W-x/u

RB5

R/W-x/u

RB4

R/W-x/u

RB3

R/W-x/u

RB2

R/W-x/u

RB1

R/W-x/u

RB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

RB<7:0>: PORTB General Purpose I/O Pin bits⁽¹⁾

1= Port pin is > VIH

0= Port pin is < VIL

Note 1: Writes to PORTB are actually written to the corresponding LATB register. Reads from the PORTB register is

return of actual I/O pin values.

REGISTER 11-6: TRISB: PORTB TRI-STATE REGISTER

R/W-1/1

TRISB7

R/W-1/1

TRISB6

R/W-1/1

TRISB5

R/W-1/1

TRISB4

R/W-1/1

TRISB3

R/W-1/1

TRISB2

R/W-1/1

TRISB1

R/W-1/1

TRISB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

TRISB<7:0>: PORTB Tri-State Control bits

1= PORTB pin configured as an input (tri-stated)

0= PORTB pin configured as an output

REGISTER 11-7: LATB: PORTB DATA LATCH REGISTER

R/W-x/u

LATB7

R/W-x/u

LATB6

R/W-x/u

LATB5

R/W-x/u

LATB4

R/W-x/u

LATB3

R/W-x/u

LATB2

R/W-x/u

LATB1

R/W-x/u

LATB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

LATB<7:0>: PORTB Output Latch Value bits⁽¹⁾

Note 1: Writes to PORTB are actually written to the corresponding LATB register. Reads from the PORTB register

is return of actual I/O pin values.

DS40001569D-page 98

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

REGISTER 11-8: ANSELB: PORTB ANALOG SELECT REGISTER

U-0

—

U-0

—

R/W-1/1

ANSB5

R/W-1/1

ANSB4

R/W-1/1

ANSB3

R/W-1/1

ANSB2

R/W-1/1

ANSB1

R/W-1/1

ANSB0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

ANSB<5:0>: Analog Select between Analog or Digital Function on pins RB<5:0>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external

control of the voltage on the pin.

REGISTER 11-9: WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1/1

WPUB7

R/W-1/1

WPUB6

R/W-1/1

WPUB5

R/W-1/1

WPUB4

R/W-1/1

WPUB3

R/W-1/1

WPUB2

R/W-1/1

WPUB1

R/W-1/1

WPUB0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

WPUB<7:0>: Weak Pull-up Register bits

1= Pull-up enabled

0= Pull-up disabled

Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in configured as an output.

TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELB

—

ANSB5

LATB5

RB5

ANSB4

LATB4

RB4

ANSB3

LATB3

RB3

ANSB2

LATB2

RB2

ANSB1

LATB1

RB1

ANSB0

LATB0

RB0

99

98

99

LATB

LATB7

RB7

LATB6

RB6

PORTB

TRISB

TRISB7

WPUB7

TRISB6

WPUB6

TRISB5

WPUB5

TRISB4

WPUB4

TRISB3

WPUB3

TRISB2

WPUB2

TRISB1

WPUB1

TRISB0

WPUB0

WPUB

Legend:

x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 99

PIC16LF1904/6/7

11.3.1

PORTC FUNCTIONS AND OUTPUT

PRIORITIES

11.3 PORTC Registers

PORTC is an 8-bit wide bidirectional port. The

corresponding data direction register is TRISC

(Register 11-6). Setting a TRISC bit (= 1) will make the

corresponding PORTC pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISC bit (= 0) will make the corresponding

PORTC pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 11-1 shows how to initialize an I/O port.

Each PORTC pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are shown in Table 11-7.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

Analog input and some digital input functions are not

included in the list below. These input functions can

remain active when the pin is configured as an output.

Certain digital input functions override other port

functions and are included in Table 11-7.

Reading the PORTC register (Register 11-5) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch (LATC).

TABLE 11-7: PORTC OUTPUT PRIORITY

Pin Name

Function Priority⁽¹⁾

RC0

T1OSO

T1CKI

RC0

The TRISC register (Register 11-6) controls the PORTC

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISC register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

RC1

RC2

RC3

RC4

T1OSI

RC1

SEG2

RC2

SEG6

RC3

SEG11

T1G

RC4

RC5

RC6

SEG10

RC5

SEG9

RC6

TX/CK

RC7

SEG8

RC7

RX/DT

Note 1: Priority listed from highest to lowest.

DS40001569D-page 100

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

REGISTER 11-10: PORTC: PORTC REGISTER

R/W-x/u

RC7

R/W-x/u

RC6

R/W-x/u

RC5

R/W-x/u

RC4

R/W-x/u

RC3

R/W-x/u

RC2

R/W-x/u

RC1

R/W-x/u

RC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

RC<7:0>: PORTC General Purpose I/O Pin bits⁽¹⁾

1= Port pin is > VIH

0= Port pin is < VIL

Note 1: Writes to PORTC are actually written to the corresponding LATC register. Reads from the PORTC register is

return of actual I/O pin values.

REGISTER 11-11: TRISC: PORTC TRI-STATE REGISTER

R/W-1/1

TRISC7

R/W-1/1

TRISC6

R/W-1/1

TRISC5

R/W-1/1

TRISC4

R/W-1/1

TRISC3

R/W-1/1

TRISC2

R/W-1/1

TRISC1

R/W-1/1

TRISC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

TRISC<7:0>: PORTC Tri-State Control bits

1= PORTC pin configured as an input (tri-stated)

0= PORTC pin configured as an output

REGISTER 11-12: LATC: PORTC DATA LATCH REGISTER

R/W-x/u

LATC7

R/W-x/u

LATC6

R/W-x/u

LATC5

R/W-x/u

LATC4

R/W-x/u

LATC3

R/W-x/u

LATC2

R/W-x/u

LATC1

R/W-x/u

LATC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

LATC<7:0>: PORTC Output Latch Value bits⁽¹⁾

Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is

return of actual I/O pin values.

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TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LATC

LATC7

RC7

LATC6

RC6

LATC5

RC5

LATC4

RC4

LATC3

RC3

LATC2

RC2

LATC1

RC1

LATC0

RC0

98

PORTC

TRISC

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

Legend:

x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

DS40001569D-page 102

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11.4.1

PORTD FUNCTIONS AND OUTPUT

PRIORITIES

11.4 PORTD Registers

(PIC16LF1904/7 only)

Each PORTD pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are shown in Table 11-9.

PORTD is

a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISD

(Register 11-14). Setting a TRISD bit (= 1) will make the

corresponding PORTD pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISD bit (= 0) will make the corresponding

PORTD pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 11-1 shows how to initialize an I/O port.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

Analog input and some digital input functions are not

included in the list below. These input functions can

remain active when the pin is configured as an output.

Certain digital input functions override other port

functions and are included in Table 11-9.

Reading the PORTD register (Register 11-13) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch (LATD).

TABLE 11-9: PORTD OUTPUT PRIORITY

Pin Name

Function Priority⁽¹⁾

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

The TRISD register (Register 11-14) controls the

PORTD pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits in

the TRISD register are maintained set when using them

as analog inputs. I/O pins configured as analog input

always read ‘0’.

Note 1: Priority listed from highest to lowest.

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REGISTER 11-13: PORTD: PORTD REGISTER

R/W-x/u

RD7

R/W-x/u

RD6

R/W-x/u

RD5

R/W-x/u

RD4

R/W-x/u

RD3

R/W-x/u

RD2

R/W-x/u

RD1

R/W-x/u

RD0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

RD<7:0>: PORTD General Purpose I/O Pin bits⁽¹⁾

1= Port pin is > VIH

0= Port pin is < VIL

Note 1: Writes to PORTD are actually written to the corresponding LATD register. Reads from the PORTD register

is return of actual I/O pin values.

REGISTER 11-14: TRISD: PORTD TRI-STATE REGISTER

R/W-1/1

TRISD7

R/W-1/1

TRISD6

R/W-1/1

TRISD5

R/W-1/1

TRISD4

R/W-1/1

TRISD5

R/W-1/1

TRISD5

R/W-1/1

TRISD5

R/W-1/1

TRISD4

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

TRISD<7:0>: PORTD Tri-State Control bits

1= PORTD pin configured as an input (tri-stated)

0= PORTD pin configured as an output

REGISTER 11-15: LATD: PORTB DATA LATCH REGISTER

R/W-x/u

LATD7

R/W-x/u

LATD6

R/W-x/u

LATD5

R/W-x/u

LATD4

R/W-x/u

LATD3

R/W-x/u

LATD2

R/W-x/u

LATD1

R/W-x/u

LATD0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

LATD<7:0>: PORTD Output Latch Value bits⁽¹⁾

Note 1: Writes to PORTD are actually written to the corresponding LATD register. Reads from the PORTD register

is return of actual I/O pin values.

DS40001569D-page 104

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TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD⁽¹⁾

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LATD

LATD7

RD7

LATD6

RD6

LATD5

RD5

LATD4

RD4

LATD3

RD3

LATD2

RD2

LATD1

RD1

LATD0

RD0

104

PORTD

TRISD

TRISD7

TRISD6

TRISD5

TRISD4

TRISD3

TRISD2

TRISD1

TRISD0

Legend:

x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.

Note 1: PIC16LF1904/7 only.

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PIC16LF1904/6/7

11.5.1

PORTE FUNCTIONS AND OUTPUT

PRIORITIES

11.5 PORTE Registers

RE3 is input only, and also functions as MCLR. The

MCLR feature can be disabled via a configuration fuse.

RE3 also supplies the programming voltage. The TRIS bit

for RE3 (TRISE3) always reads ‘1’.

No output priorities, RE3 is an input only pin.

REGISTER 11-16: PORTE: PORTE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R-x/u

RE3

U-0

RE2⁽¹⁾

U-0

RE1⁽¹⁾

U-0

RE0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

RE<3:0>: PORTE Input Pin bit⁽¹⁾

1= Port pin is > VIH

0= Port pin is < VIL

2: RE<2:0> are not implemented on the PIC16LF1906. Read as ‘0’. Writes to RE<2:0> are actually written to

the corresponding LATE register. Reads from the PORTE register is the return of actual I/O pin values.

REGISTER 11-17: TRISE: PORTE TRI-STATE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-1⁽¹⁾

—

R/W-1/1⁽²⁾

TRISE2

R/W-1/1⁽²⁾

TRISE1

R/W-1/1⁽²⁾

TRISE0

bit 7

bit 0

Legend:

R = Readable bit

u = bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3

Unimplemented: Read as ‘0’

Unimplemented: Read as ‘1’

bit 2-0

TRISE<2:0>: PORTE Tri-State Control bits⁽²⁾

1= Port output driver is disabled

0= Port output driver is enabled

Note 1: Unimplemented, read as ‘1’.

2: TRISE<2:0> are not implemented on the PIC16LF1906. Read as ‘0’.

DS40001569D-page 106

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REGISTER 11-18: LATE: PORTE DATA LATCH REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x/u

LATE2⁽²⁾

R/W-x/u

LATE1⁽²⁾

R/W-x/u

LATE0⁽²⁾

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

LATE<2:0>: PORTE Output Latch Value bits⁽¹⁾

Note 1: Writes to PORTE are actually written to the corresponding LATE register. Reads from the PORTE register

is return of actual I/O pin values.

2: LATE<2:0> are not implemented on the PIC16LF1906. Read as ‘0’.

REGISTER 11-19: ANSELE: PORTE ANALOG SELECT REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1/1

ANSE2⁽²⁾

R/W-1/1

ANSE1⁽²⁾

R/W-1/1

ANSE0⁽²⁾

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

ANSE<2:0>: Analog Select between Analog or Digital Function on pins RE<2:0>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

2: ANSE<2:0> are not implemented on the PIC16LF1906. Read as ‘0’.

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REGISTER 11-20: WPUE: WEAK PULL-UP PORTE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1/1

WPUE3

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3

Unimplemented: Read as ‘0’

WPUE3: Weak Pull-up Register bit

1= Pull-up enabled

0= Pull-up disabled

bit 2-0

Unimplemented: Read as ‘0’

Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in configured as an output.

TABLE 11-11: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CHS<4:0>

121

99

ADCON0

ANSELE

LATE

—

GO/DONE

ADON

(2)

—

ANSE2

ANSE1

ANSE0

(2)

LATE2

LATE1

LATE0

106

108

(2)

PORTE

TRISE

RE3

RE2

RE1

RE0

(1)

TRISE2⁽²⁾TRISE1⁽²⁾TRISE0⁽²⁾

—

WPUE

WPUE3

—

Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.

Note 1: Unimplemented, read as ‘1’.

2: PIC16LF1904/7 only.

DS40001569D-page 108

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12.3 Interrupt Flags

12.0 INTERRUPT-ON-CHANGE

The IOCBFx bits located in the IOCBF register are

status flags that correspond to the interrupt-on-change

pins of PORTB. If an expected edge is detected on an

appropriately enabled pin, then the status flag for that pin

will be set, and an interrupt will be generated if the IOCIE

bit is set. The IOCIF bit of the INTCON register reflects

the status of all IOCBFx bits.

The PORTB pins can be configured to operate as

Interrupt-On-Change (IOC) pins. An interrupt can be

generated by detecting a signal that has either a rising

edge or a falling edge. Any individual PORTB pin, or

combination of PORTB pins, can be configured to

generate an interrupt. The interrupt-on-change module

has the following features:

• Interrupt-on-Change enable (Master Switch)

• Individual pin configuration

12.4 Clearing Interrupt Flags

• Rising and falling edge detection

• Individual pin interrupt flags

The individual status flags, (IOCBFx bits), can be

cleared by resetting them to zero. If another edge is

detected during this clearing operation, the associated

status flag will be set at the end of the sequence,

regardless of the value actually being written.

Figure 12-1 is a block diagram of the IOC module.

12.1 Enabling the Module

In order to ensure that no detected edge is lost while

clearing flags, only AND operations masking out known

changed bits should be performed. The following

sequence is an example of what should be performed.

To allow individual PORTB pins to generate an interrupt,

the IOCIE bit of the INTCON register must be set. If the

IOCIE bit is disabled, the edge detection on the pin will

still occur, but an interrupt will not be generated.

EXAMPLE 12-1:

12.2 Individual Pin Configuration

MOVLW 0xff

XORWF IOCBF, W

ANDWF IOCBF, F

For each PORTB pin, a rising edge detector and a falling

edge detector are present. To enable a pin to detect a

rising edge, the associated IOCBPx bit of the IOCBP

register is set. To enable a pin to detect a falling edge,

the associated IOCBNx bit of the IOCBN register is set.

12.5 Operation in Sleep

The interrupt-on-change interrupt sequence will wake

the device from Sleep mode, if the IOCIE bit is set.

A pin can be configured to detect rising and falling

edges simultaneously by setting both the IOCBPx bit

and the IOCBNx bit of the IOCBP and IOCBN registers,

respectively.

If an edge is detected while in Sleep mode, the IOCBF

register will be updated prior to the first instruction

executed out of Sleep.

FIGURE 12-1:

INTERRUPT-ON-CHANGE BLOCK DIAGRAM

IOCIE

IOCBFx

IOCBNx

D

Q

From all other IOCBFx

individual pin detectors

CK

R

IOC Interrupt to

CPU Core

RBx

IOCBPx

D

Q

CK

R

Q2 Clock Cycle

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12.6 Interrupt-On-Change Registers

REGISTER 12-1: IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER

R/W-0/0

IOCBP7

R/W-0/0

IOCBP6

R/W-0/0

IOCBP5

R/W-0/0

IOCBP4

R/W-0/0

IOCBP3

R/W-0/0

IOCBP2

R/W-0/0

IOCBP1

R/W-0/0

IOCBP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and

interrupt flag will be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

REGISTER 12-2: IOCBN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER

R/W-0/0

IOCBN7

R/W-0/0

IOCBN6

R/W-0/0

IOCBN5

R/W-0/0

IOCBN4

R/W-0/0

IOCBN3

R/W-0/0

IOCBN2

R/W-0/0

IOCBN1

R/W-0/0

IOCBN0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

IOCBN<7:0>: Interrupt-on-Change Negative Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and

interrupt flag will be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

REGISTER 12-3: IOCBF: INTERRUPT-ON-CHANGE FLAG REGISTER

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

IOCBF7

bit 7

IOCBF6

IOCBF5

IOCBF4

IOCBF3

IOCBF2

IOCBF1

IOCBF0

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

bit 7-0

IOCBF<7:0>: Interrupt-on-Change Flag bits

1= An enabled change was detected on the associated pin.

Set when IOCBPx = 1and a rising edge was detected on RBx, or when IOCBNx = 1and a falling

edge was detected on RBx.

0= No change was detected, or the user cleared the detected change.

DS40001569D-page 110

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TABLE 12-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

ANSELB

INTCON

IOCBF

—

ANSB5

ANSB4

INTE

ANSB3

IOCIE

ANSB2

ANSB1

INTF

ANSB0

IOCIF

99

65

GIE

PEIE

TMR0IE

TMR0IF

IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0

IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0

IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

110

98

IOCBN

IOCBP

TRISB

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.

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13.1 Independent Gain Amplifiers

13.0 FIXED VOLTAGE REFERENCE

(FVR)

The output of the FVR supplied to the ADC is routed

through two independent programmable gain

amplifiers. Each amplifier can be configured to amplify

the reference voltage by 1x or 2x, to produce the two

possible voltage levels.

The Fixed Voltage Reference (FVR) is a stable voltage

reference, independent of VDD, with 1.024V or 2.048V

selectable output levels. The output of the FVR can be

configured as the FVR input channel on the ADC.

The ADFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the ADC module. Refer-

ence Section 15.0 “Analog-to-Digital Converter

(ADC) Module” for additional information.

The FVR can be enabled by setting the FVREN bit of

the FVRCON register.

13.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it

requires time for the reference and amplifier circuits to

stabilize. Once the circuits stabilize and are ready for use,

the FVRRDY bit of the FVRCON register will be set. See

Section 22.0 “Electrical Specifications” for the

minimum delay requirement.

FIGURE 13-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

ADFVR<1:0>

2

x1

x2

FVR BUFFER1

(To ADC Module)

1.024V Fixed

Reference

+

-

FVREN

FVRRDY

Any peripheral requiring

the Fixed Reference

(See Table 13-1)

TABLE 13-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)

Peripheral

Conditions

Description

HFINTOSC

FOSC<2:0> = 100and

IRCF<3:0> = 000x

INTOSC is active and device is not in Sleep.

BOREN<1:0> = 11

BOR always enabled.

BOR

BOREN<1:0> = 10and BORFS = 1

BOREN<1:0> = 01and BORFS = 1

BOR disabled in Sleep mode, BOR Fast Start enabled.

BOR under software control, BOR Fast Start enabled.

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13.3 FVR Control Registers

REGISTER 13-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0/0

FVREN

R-q/q

FVRRDY⁽¹⁾

R/W-0/0

TSEN

R/W-0/0

TSRNG

U-0

—

U-0

—

R/W-0/0

ADFVR<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

bit 5

bit 4

FVREN: Fixed Voltage Reference Enable bit

0= Fixed Voltage Reference is disabled

1= Fixed Voltage Reference is enabled

FVRRDY: Fixed Voltage Reference Ready Flag bit⁽¹⁾

0= Fixed Voltage Reference output is not ready or not enabled

1= Fixed Voltage Reference output is ready for use

TSEN: Temperature Indicator Enable bit

0= Temperature Indicator is disabled

1= Temperature Indicator is enabled

TSRNG: Temperature Indicator Range Selection bit

0= VOUT = VDD - 2VT (Low Range)

1= VOUT = VDD - 4VT (High Range)

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit

00= ADC Fixed Voltage Reference Peripheral output is off.

01= ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)

10= ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)⁽²⁾

11= Reserved

Note 1: FVRRDY will output the true state of the band gap.

2: Fixed Voltage Reference output cannot exceed VDD.

TABLE 13-2: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FVRCON

FVREN

FVRRDY

TSEN

TSRNG

ADFVR1

ADFVR0

113

—

Legend:

Shaded cells are not used with the Fixed Voltage Reference.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 113

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FIGURE 14-1:

TEMPERATURE CIRCUIT

DIAGRAM

14.0 TEMPERATURE INDICATOR

MODULE

This family of devices is equipped with a temperature

circuit designed to measure the operating temperature

of the silicon die. The circuit’s range of operating

temperature falls between of -40°C and +85°C. The

output is a voltage that is proportional to the device

temperature. The output of the temperature indicator is

internally connected to the device ADC.

VDD

TSEN

TSRNG

The circuit may be used as a temperature threshold

detector or a more accurate temperature indicator,

depending on the level of calibration performed. A one-

point calibration allows the circuit to indicate a

temperature closely surrounding that point. A two-point

calibration allows the circuit to sense the entire range

of temperature more accurately. Reference Application

Note AN1333, “Use and Calibration of the Internal

Temperature Indicator” (DS01333) for more details

regarding the calibration process.

VOUT

ADC

MUX

ADC

n

CHS bits

(ADCON0 register)

14.1 Circuit Operation

14.2 Minimum Operating VDD vs.

Minimum Sensing Temperature

Figure 14-1 shows a simplified block diagram of the

temperature circuit. The proportional voltage output is

achieved by measuring the forward voltage drop across

multiple silicon junctions.

When the temperature circuit is operated in low range,

the device may be operated at any operating voltage

that is within specifications.

Equation 14-1 describes the output characteristics of

the temperature indicator.

When the temperature circuit is operated in high range,

the device operating voltage, VDD, must be high

enough to ensure that the temperature circuit is

correctly biased.

EQUATION 14-1: VOUT RANGES

High Range: VOUT = VDD - 4VT

Low Range: VOUT = VDD - 2VT

Table 14-1 shows the recommended minimum VDD vs.

range setting.

TABLE 14-1: RECOMMENDED VDD VS.

RANGE

The temperature sense circuit is integrated with the

Fixed Voltage Reference (FVR) module. See

Section 13.0 “Fixed Voltage Reference (FVR)” for

more information.

Min. VDD, TSRNG = 1

Min. VDD, TSRNG = 0

3.6V

1.8V

The circuit is enabled by setting the TSEN bit of the

FVRCON register. When disabled, the circuit draws no

current.

14.3 Temperature Output

The output of the circuit is measured using the internal

Analog-to-Digital Converter. A channel is reserved for

the temperature circuit output. Refer to Section 15.0

“Analog-to-Digital Converter (ADC) Module” for

detailed information.

The circuit operates in either high or low range. The high

range, selected by setting the TSRNG bit of the

FVRCON register, provides a wider output voltage. This

provides more resolution over the temperature range,

but may be less consistent from part to part. This range

requires a higher bias voltage to operate and thus, a

higher VDD is needed.

14.4 ADC Acquisition Time

To ensure accurate temperature measurements, the

user must wait at least 200 s after the ADC input

multiplexer is connected to the temperature indicator

output before the conversion is performed. In addition,

the user must wait 200 s between sequential

conversions of the temperature indicator output.

The low range is selected by clearing the TSRNG bit of

the FVRCON register. The low range generates a lower

voltage drop and thus, a lower bias voltage is needed to

operate the circuit. The low range is provided for low

voltage operation.

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The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

15.0 ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates a 10-bit binary result via successive

approximation and stores the conversion result into the

ADC result registers (ADRESH:ADRESL register pair).

Figure 15-1 shows the block diagram of the ADC.

The ADC voltage reference is software selectable to be

either internally generated or externally supplied.

FIGURE 15-1:

ADC BLOCK DIAGRAM

VDD

ADPREF = 00

VREF+

ADPREF = 10

AN0

AN1

AN2

00000

00001

00010

00011

00100

00101

VREF+/AN3

AN4

AN5⁽³⁾

AN6⁽³⁾

AN7⁽³⁾

AN8

00110

00111

01000

01001

01010

01011

01100

01101

ADC

AN9

10

GO/DONE

AN10

AN11

0= Left Justify

1= Right Justify

ADFM

AN12

AN13

ADON⁽¹⁾

16

ADRESH ADRESL

VSS

11101

11110

11111

Temperature Indicator

Reserved

FVR Buffer1

CHS<4:0>⁽²⁾

Note 1: When ADON = 0, all multiplexer inputs are disconnected.

2: See ADCON0 register (Example 15-1) for detailed analog channel selection per device.

3: ADC channel is reserved on the PIC16LF1906 28-pin device.

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15.1.4

CONVERSION CLOCK

15.1 ADC Configuration

The source of the conversion clock is software select-

able via the ADCS bits of the ADCON1 register. There

are seven possible clock options:

When configuring and using the ADC the following

functions must be considered:

• Port configuration

• FOSC/2

• Channel selection

• FOSC/4

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• FOSC/8

• FOSC/16

• FOSC/32

• Result formatting

• FOSC/64

15.1.1

PORT CONFIGURATION

• FRC (dedicated internal oscillator)

The ADC can be used to convert both analog and

digital signals. When converting analog signals, the I/O

pin should be configured for analog by setting the

associated TRIS and ANSEL bits. Refer to

Section 11.0 “I/O Ports” for more information.

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11.5 TAD

periods as shown in Figure 15-2.

For correct conversion, the appropriate TAD specifica-

tion must be met. Refer to the A/D conversion require-

ments in Section 22.0 “Electrical Specifications” for

more information. Table 15-1 gives examples of

appropriate ADC clock selections.

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

15.1.2

CHANNEL SELECTION

There are up to 11 channel selections available:

• AN<13:0> pins

• Temperature Indicator

• FVR (Fixed Voltage Reference) Output

Refer to Section 13.0 “Fixed Voltage Reference

(FVR)” and Section 14.0 “Temperature Indicator

Module” for more information on these channel selec-

tions.

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 15.2

“ADC Operation” for more information.

15.1.3

ADC VOLTAGE REFERENCE

The ADPREF bits of the ADCON1 register provides

control of the positive voltage reference. The positive

voltage reference can be:

• VREF+ pin

• VDD

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TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

ADC Clock Period (TAD)

Device Frequency (FOSC)

ADC

Clock Source

ADCS<2:0>

20 MHz

16 MHz

8 MHz

4 MHz

1 MHz

FOSC/2

000

100

001

101

010

110

x11

100 ns⁽²⁾

200 ns⁽²⁾

400 ns⁽²⁾

800 ns

125 ns⁽²⁾

250 ns⁽²⁾

0.5 s⁽²⁾

1.0 s

250 ns⁽²⁾

500 ns⁽²⁾

1.0 s

500 ns⁽²⁾

1.0 s

2.0 s

4.0 s

8.0 s⁽³⁾

16.0 s⁽³⁾

32.0 s⁽³⁾

64.0 s⁽³⁾

1.0-6.0 s^(1,4)

FOSC/4

FOSC/8

FOSC/16

FOSC/32

FOSC/64

FRC

2.0 s

4.0 s

1.6 s

2.0 s

4.0 s

8.0 s⁽³⁾

1.0-6.0 s^(1,4)

8.0 s⁽³⁾

16.0 s⁽³⁾

1.0-6.0 s^(1,4)

3.2 s

1.0-6.0 s^(1,4)

4.0 s

1.0-6.0 s^(1,4)

Legend:

Shaded cells are outside of recommended range.

Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the

system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the

device in Sleep mode.

FIGURE 15-2:

ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

TCY - TAD

TAD8 TAD9 TAD10 TAD11

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7

b4

b1

b0

b9

b8

b7

b6

b5

b3

b2

Conversion starts

Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO bit

On the following cycle:

ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

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15.1.5

INTERRUPTS

15.1.6

RESULT FORMATTING

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC Interrupt Flag is the ADIF bit in

the PIR1 register. The ADC Interrupt Enable is the

ADIE bit in the PIE1 register. The ADIF bit must be

cleared in software.

The 10-bit A/D conversion result can be supplied in two

formats, left justified or right justified. The ADFM bit of

the ADCON1 register controls the output format.

Figure 15-3 shows the two output formats.

Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

2: The ADC operates during Sleep only

when the FRC oscillator is selected.

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEPinstruc-

tion is always executed. If the user is attempting to

wake-up from Sleep and resume in-line code execu-

tion, the GIE and PEIE bits of the INTCON register

must be disabled. If the GIE and PEIE bits of the

INTCON register are enabled, execution will switch to

the Interrupt Service Routine.

FIGURE 15-3:

10-BIT A/D CONVERSION RESULT FORMAT

ADRESH

ADRESL

LSB

(ADFM = 0)

MSB

bit 7

bit 0

bit 7

bit 0

10-bit A/D Result

Unimplemented: Read as ‘0’

(ADFM = 1)

MSB

LSB

bit 0

bit 7

Unimplemented: Read as ‘0’

10-bit A/D Result

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15.2.4

ADC OPERATION DURING SLEEP

15.2 ADC Operation

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC waits one additional instruction before starting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

15.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the

GO/DONE bit of the ADCON0 register to a ‘1’ will start

the Analog-to-Digital conversion.

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the ADC.

Refer to Section 15.2.5 “A/D Conversion

Procedure”.

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present conver-

sion to be aborted and the ADC module is turned off,

although the ADON bit remains set.

15.2.2

COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF Interrupt Flag bit

• Update the ADRESH and ADRESL registers with

new conversion result

15.2.3

TERMINATING A CONVERSION

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The

ADRESH and ADRESL registers will be updated with

the partially complete Analog-to-Digital conversion

sample. Incomplete bits will match the last bit

converted.

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

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15.2.5

A/D CONVERSION PROCEDURE

EXAMPLE 15-1:

A/D CONVERSION

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

;This code block configures the ADC

;for polling, Vdd and Vss references, Frc

;clock and AN0 input.

;

;Conversion start & polling for completion

; are included.

;

1. Configure Port:

• Disable pin output driver (Refer to the TRIS

register)

• Configure pin as analog (Refer to the ANSEL

register)

BANKSEL

MOVLW

ADCON1

;

B’11110000’ ;Right justify, Frc

;clock

2. Configure the ADC module:

• Select ADC conversion clock

• Configure voltage reference

• Select ADC input channel

• Turn on ADC module

MOVWF

BANKSEL

BSF

BANKSEL

BSF

BANKSEL

MOVLW

MOVWF

CALL

ADCON1

TRISA

TRISA,0

ANSEL

ANSEL,0

ADCON0

;Vdd and Vss Vref

;

;Set RA0 to input

;

;Set RA0 to analog

;

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

B’00000001’ ;Select channel AN0

ADCON0

SampleTime

;Turn ADC On

;Acquisiton delay

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt⁽¹⁾

4. Wait the required acquisition time⁽²⁾

BSF

BTFSC

GOTO

BANKSEL

MOVF

MOVWF

BANKSEL

MOVF

ADCON0,ADGO ;Start conversion

ADCON0,ADGO ;Is conversion done?

$-1

ADRESH

;No, test again

;

.

5. Start conversion by setting the GO/DONE bit.

ADRESH,W

RESULTHI

ADRESL

;Read upper 2 bits

;store in GPR space

;

6. Wait for ADC conversion to complete by one of

the following:

ADRESL,W

RESULTLO

;Read lower 8 bits

;Store in GPR space

• Polling the GO/DONE bit

MOVWF

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result.

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: Refer to Section 15.3 “A/D Acquisition

Requirements”.

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15.2.6

ADC REGISTER DEFINITIONS

The following registers are used to control the

operation of the ADC.

REGISTER 15-1: ADCON0: A/D CONTROL REGISTER 0

U-0

—

R/W-0/0

ADON

CHS<4:0>

GO/DONE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-2

CHS<4:0>: Analog Channel Select bits

00000= AN0

00001= AN1

00010= AN2

00011= AN3

00100= AN4

00101= AN5⁽³⁾

00110= AN6⁽³⁾

00111= AN7⁽³⁾

01000= AN8

01001= AN9

01010= AN10

01011= AN11

01100= AN12

01101= AN13

01110= Reserved. No channel connected.

•

11100= Reserved. No channel connected.

11101= Temperature Indicator⁽²⁾

11110= Reserved. No channel connected.

11111=FVR (Fixed Voltage Reference) Buffer 1 Output⁽¹⁾

GO/DONE: A/D Conversion Status bit

bit 1

bit 0

1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0= A/D conversion completed/not in progress

ADON: ADC Enable bit

1= ADC is enabled

0= ADC is disabled and consumes no operating current

Note 1: See Section 13.0 “Fixed Voltage Reference (FVR)” for more information.

2: See Section 14.0 “Temperature Indicator Module” for more information.

3: ADC channel is reserved on the PIC16LF1906 28-pin device.

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REGISTER 15-2: ADCON1: A/D CONTROL REGISTER 1

R/W-0/0

ADFM

R/W-0/0

U-0

—

U-0

—

R/W-0/0

ADCS<2:0>

ADPREF<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

ADFM: A/D Result Format Select bit

1= Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is

loaded.

0= Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is

loaded.

bit 6-4

ADCS<2:0>: A/D Conversion Clock Select bits

000= FOSC/2

001= FOSC/8

010= FOSC/32

011= FRC (clock supplied from a dedicated RC oscillator)

100= FOSC/4

101= FOSC/16

110= FOSC/64

111= FRC (clock supplied from a dedicated RC oscillator)

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits

00= VREF+ is connected to VDD

01= Reserved

10= VREF+ is connected to external VREF+ pin⁽¹⁾

11= Reserved

Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a

minimum voltage specification exists. See Section 22.0 “Electrical Specifications” for details.

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REGISTER 15-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x/u

bit 0

ADRES<9:2>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ADRES<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result

REGISTER 15-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

ADRES<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-0

ADRES<1:0>: ADC Result Register bits

Lower two bits of 10-bit conversion result

Reserved: Do not use.

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REGISTER 15-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

ADRES<9:8>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-2

bit 1-0

Reserved: Do not use.

ADRES<9:8>: ADC Result Register bits

Upper two bits of 10-bit conversion result

REGISTER 15-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

R/W-x/u

bit 0

ADRES<7:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

ADRES<7:0>: ADC Result Register bits

Lower eight bits of 10-bit conversion result

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source impedance is decreased, the acquisition time

may be decreased. After the analog input channel is

selected (or changed), an A/D acquisition must be

done before the conversion can be started. To calculate

the minimum acquisition time, Equation 15-1 may be

used. This equation assumes that 1/2 LSb error is used

(1,024 steps for the ADC). The 1/2 LSb error is the

maximum error allowed for the ADC to meet its

specified resolution.

15.3 A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 15-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), refer

to Figure 15-4. The maximum recommended

impedance for analog sources is 10 k. As the

EQUATION 15-1: ACQUISITION TIME EXAMPLE

Temperature = 50°C and external impedance of 10k 5.0V VDD

Assumptions:

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

= 2µs + TC + Temperature - 25°C0.05µs/°C

The value for TC can be approximated with the following equations:

1





;[1] VCHOLD charged to within 1/2 lsb

^VAPPLIED^{1 – -------------------------- = VCHOLD}



2^{n + 1} – 1

–TC

---------





RC

VAPPLIED 1 – e

= V^CHOLD







;[2] VCHOLD charge response to VAPPLIED

;combining [1] and [2]



–Tc

--------









RC

1







^{= VAPPLIED}^{1 – --------------------------}

2^{n + 1} – 1

VAPPLIED 1 – e





Note: Where n = number of bits of the ADC.

Solving for TC:

TC = –CHOLDRIC + RSS + RS ln(1/2047)

= –12.5pF1k + 7k + 10k ln(0.0004885)

= 1.715µs

Therefore:

TACQ = 2µs + 1.715µs + 50°C- 25°C0.05µs/°C

= 4.96µs

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

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FIGURE 15-4:

ANALOG INPUT MODEL

Rev. 10-000070B

8/5/2014

VDD

Sampling

switch

Analog

VT § 0.6V

SS

Input pin

RS

RIC 1K

RSS

(1)

ILEAKAGE

CHOLD = 12.5 pF

Ref-

CPIN

5pF

VA

6V

5V

Legend: CHOLD

CPIN

= Sample/Hold Capacitance

= Input Capacitance

VDD 4V

3V

RSS

ILEAKAGE = Leakage Current at the pin due to varies injunctions

2V

RIC

RSS

SS

VT

= Interconnect Resistance

= Resistance of Sampling switch

= Sampling Switch

5 6 7 8 91011

Sampling Switch

= Threshold Voltage

(k )

Note 1: Refer to Section 22.0 “Electrical Specifications”.

FIGURE 15-5:

ADC TRANSFER FUNCTION

Full-Scale Range

3FFh

3FEh

3FDh

3FCh

3FBh

03h

02h

01h

00h

Analog Input Voltage

1.5 LSB

0.5 LSB

Zero-Scale

Transition

VREF-

Full-Scale

Transition

VREF+

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PIC16LF1904/6/7

TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH ADC

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

121

122

ADCON0

ADCON1

ADRESH

—

CHS4

CHS3

CHS2

CHS1

—

CHS0

—

GO/DONE

ADON

ADFM

ADCS2

ADCS1

ADCS0

ADPREF1 ADPREF0

A/D Result Register High

A/D Result Register Low

123, 124

96

ADRESL

ANSELA

ANSELB

INTCON

—

ANSA5

ANSB5

TMR0IE

—

ANSA3

ANSB3

IOCIE

ANSA2

ANSB2

TMR0IF

ANSA1

ANSB1

INTF

ANSA0

ANSB0

IOCIF

—

ANSB4

INTE

99

GIE

PEIE

65

TMR1GIE

TMR1GIF

TRISA7

TRISB7

FVREN

PIE1

ADIE

ADIF

RCIE

RCIF

TXIE

TXIF

—

TMR1IE

TMR1IF

TRISA0

TRISB0

ADFVR0

66

PIR1

—

68

TRISA

TRISB

FVRCON

Legend:

TRISA6

TRISB6

FVRRDY

TRISA5

TRISB5

TSEN

TRISA4

TRISB4

TSRNG

TRISA3

TRISB3

—

TRISA2

TRISB2

—

TRISA1

TRISB1

ADFVR1

95

98

113

x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends on condition. Shaded cells are not

used for ADC module.

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16.1.2

8-BIT COUNTER MODE

16.0 TIMER0 MODULE

In 8-Bit Counter mode, the Timer0 module will increment

on every rising or falling edge of the T0CKI pin.

The Timer0 module is an 8-bit timer/counter with the

following features:

8-Bit Counter mode using the T0CKI pin is selected by

setting the TMR0CS bit in the OPTION_REG register to

‘1’ .

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (independent of Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

The rising or falling transition of the incrementing edge

is determined by the TMR0SE bit in the OPTION_REG

register.

• TMR0 can be used to gate Timer1

Figure 16-1 is a block diagram of the Timer0 module.

16.1 Timer0 Operation

The Timer0 module can be used as either an 8-bit timer

or an 8-bit counter.

16.1.1

8-BIT TIMER MODE

The Timer0 module will increment every instruction

cycle, if used without a prescaler. 8-Bit Timer mode is

selected by clearing the TMR0CS bit of the

OPTION_REG register.

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

Note:

The value written to the TMR0 register

can be adjusted, in order to account for

the two instruction cycle delay when

TMR0 is written.

FIGURE 16-1:

BLOCK DIAGRAM OF THE TIMER0

FOSC/4

Data Bus

0

1

8

T0CKI

1

Sync

TMR0

2 TCY

0

Set Flag bit TMR0IF

on Overflow

PSA

TMR0SE

TMR0CS

8-bit

Prescaler

Overflow to Timer1

8

PS<2:0>

DS40001569D-page 128

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PIC16LF1904/6/7

16.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

A software programmable prescaler is available for

exclusive use with Timer0. The prescaler is enabled by

clearing the PSA bit of the OPTION_REG register.

Note:

The Watchdog Timer (WDT) uses its own

independent prescaler.

There are eight prescaler options for the Timer0 mod-

ule ranging from 1:2 to 1:256. The prescale values are

selectable via the PS<2:0> bits of the OPTION_REG

register. In order to have a 1:1 prescaler value for the

Timer0 module, the prescaler must be disabled by set-

ting the PSA bit of the OPTION_REG register.

The prescaler is not readable or writable. All instructions

writing to the TMR0 register will clear the prescaler.

16.1.4

TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0

register overflows from FFh to 00h. The TMR0IF

interrupt flag bit of the INTCON register is set every

time the TMR0 register overflows, regardless of

whether or not the Timer0 interrupt is enabled. The

TMR0IF bit can only be cleared in software. The Timer0

interrupt enable is the TMR0IE bit of the INTCON

register.

Note:

The Timer0 interrupt cannot wake the pro-

cessor from Sleep since the timer is fro-

zen during Sleep.

16.1.5

8-BIT COUNTER MODE

SYNCHRONIZATION

When in 8-Bit Counter mode, the incrementing edge on

the T0CKI pin must be synchronized to the instruction

clock. Synchronization can be accomplished by

sampling the prescaler output on the Q2 and Q4 cycles

of the instruction clock. The high and low periods of the

external clocking source must meet the timing

requirements as shown in Section 22.0 “Electrical

Specifications”.

16.1.6

OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep

mode. The contents of the TMR0 register will remain

unchanged while the processor is in Sleep mode.

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REGISTER 16-1: OPTION_REG: OPTION REGISTER

R/W-1/1

WPUEN

R/W-1/1

INTEDG

R/W-1/1

PSA

R/W-1/1

PS<2:0>

R/W-1/1

bit 0

TMR0CS

TMR0SE

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

WPUEN: Weak Pull-up Enable bit

1= All weak pull-ups are disabled (except MCLR, if it is enabled)

0= Weak pull-ups are enabled by individual WPUx latch values

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of INT pin

0= Interrupt on falling edge of INT pin

TMR0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

TMR0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is not assigned to the Timer0 module

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

Bit Value

Timer0 Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register

on Page

Name

INTCON

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GIE

PEIE

TMR0IE

INTE

IOCIE

PSA

TMR0IF

INTF

IOCIF

65

130

128*

95

OPTION_REG WPUEN INTEDG TMR0CS TMR0SE

PS<2:0>

TMR0

TRISA

Timer0 Module Register

TRISA7 TRISA6 TRISA5 TRISA4

TRISA3

TRISA2

TRISA1 TRISA0

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.

Page provides register information.

*

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Figure 17-1 is a block diagram of the Timer1 module.

17.0 TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is a 16-bit timer/counter with the

following features:

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 2-bit prescaler

• Dedicated 32 kHz oscillator circuit

• Multiple Timer1 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Selectable Gate Source Polarity

• Gate Toggle mode

• Gate Single-pulse mode

• Gate Value Status

• Gate Event Interrupt

FIGURE 17-1:

T1GSS<1:0>

T1G

TIMER1 BLOCK DIAGRAM

T1GSPM

0

From Timer0

Overflow

0

1

T1G_IN

D

Data Bus

T1GVAL

0

1

D

Q

Single Pulse

Acq. Control

RD

1

T1GCON

Q1 EN

Q

Interrupt

Set

TMR1GIF

T1GGO/DONE

CK

R

TMR1ON

T1GTM

det

T1GPOL

TMR1GE

Set flag bit

TMR1IF on

Overflow

TMR1ON

TMR1⁽²⁾

EN

D

Synchronized

clock input

0

T1CLK

TMR1H

TMR1L

Q

1

TMR1CS<1:0>

Reserved

T1SYNC

T1OSO

T1OSI

OUT

11

10

Synchronize⁽³⁾

det

T1OSC

EN

Prescaler

1, 2, 4, 8

1

0

2

T1CKPS<1:0>

FOSC

Internal

Clock

01

00

FOSC/2

Internal

Clock

T1OSCEN

Sleep input

FOSC/4

Internal

Clock

(1)

T1CKI

To LCD and Clock Switching Modules

Note 1: ST Buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

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17.1 Timer1 Operation

17.2 Clock Source Selection

The Timer1 module is a 16-bit incrementing counter

which is accessed through the TMR1H:TMR1L register

pair. Writes to TMR1H or TMR1L directly update the

counter.

The TMR1CS<1:0> and T1OSCEN bits of the T1CON

register are used to select the clock source for Timer1.

Table 17-2 displays the clock source selections.

17.2.1

INTERNAL CLOCK SOURCE

When used with an internal clock source, the module is

a timer and increments on every instruction cycle.

When used with an external clock source, the module

can be used as either a timer or counter and incre-

ments on every selected edge of the external source.

When the internal clock source is selected, the

TMR1H:TMR1L register pair will increment on multiples

of FOSC as determined by the Timer1 prescaler.

When the FOSC internal clock source is selected, the

Timer1 register value will increment by four counts every

instruction clock cycle. Due to this condition, a 2 LSB

error in resolution will occur when reading the Timer1

value. To utilize the full resolution of Timer1, an

asynchronous input signal must be used to gate the

Timer1 clock input.

Timer1 is enabled by configuring the TMR1ON and

TMR1GE bits in the T1CON and T1GCON registers,

respectively. Table 17-1 displays the Timer1 enable

selections.

TABLE 17-1: TIMER1 ENABLE

SELECTIONS

The following asynchronous source may be used:

• Asynchronous event on the T1G pin to Timer1

gate

Timer1

Operation

TMR1ON

TMR1GE

17.2.2

EXTERNAL CLOCK SOURCE

0

1

0

1

0

1

Off

When the external clock source is selected, the Timer1

module may work as a timer or a counter.

Always On

When enabled to count, Timer1 is incremented on the

rising edge of the external clock input T1CKI or the

capacitive sensing oscillator signal. Either of these

external clock sources can be synchronized to the

microcontroller system clock or they can run

asynchronously.

Count Enabled

When used as a timer with a clock oscillator, an

external 32.768 kHz crystal can be used in conjunction

with the dedicated internal oscillator circuit.

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after any one or

more of the following conditions:

• Timer1 enabled after POR

• Write to TMR1H or TMR1L

• Timer1 is disabled

• Timer1 is disabled (TMR1ON = 0)

when T1CKI is high then Timer1 is

enabled (TMR1ON = 1) when T1CKI

is low.

TABLE 17-2: CLOCK SOURCE SELECTIONS

TMR1CS1

TMR1CS0

T1OSCEN

Clock Source

0

1

0

1

0

1

x

0

1

x

Instruction Clock (FOSC/4)

System Clock (FOSC)

External Clocking on T1CKI Pin

Osc. Circuit on T1OSI/T1OSO Pins

Reserved

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17.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

17.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

17.4 Timer1 Oscillator

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TMR1L register pair.

A dedicated low-power 32.768 kHz oscillator circuit is

built-in between pins T1OSI (input) and T1OSO. This

internal circuit is to be used in conjunction with an

external 32.768 kHz crystal.

The oscillator circuit is enabled by setting the

T1OSCEN bit of the T1CON register. The oscillator will

continue to run during Sleep.

17.6 Timer1 Gate

Timer1 can be configured to count freely or the count

can be enabled and disabled using Timer1 gate

circuitry. This is also referred to as Timer1 Gate Enable.

Note:

The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to using Timer1. A

suitable delay similar to the OST delay

can be implemented in software by

clearing the TMR1IF bit then presetting

the TMR1H:TMR1L register pair to

FC00h. The TMR1IF flag will be set when

1024 clock cycles have elapsed, thereby

indicating that the oscillator is running and

reasonably stable.

Timer1 gate can also be driven by multiple selectable

sources.

17.6.1

TIMER1 GATE ENABLE

The Timer1 Gate Enable mode is enabled by setting

the TMR1GE bit of the T1GCON register. The polarity

of the Timer1 Gate Enable mode is configured using

the T1GPOL bit of the T1GCON register.

When Timer1 Gate Enable mode is enabled, Timer1

will increment on the rising edge of the Timer1 clock

source. When Timer1 Gate Enable mode is disabled,

no incrementing will occur and Timer1 will hold the

current count. See Figure 17-3 for timing details.

17.5 Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If the external clock source is selected then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 17.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

TABLE 17-3: TIMER1 GATE ENABLE

SELECTIONS

T1CLK T1GPOL

T1G

Timer1 Operation



0

1

0

1

0

1

Counts

Holds Count

Counts

Note:

When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

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17.6.2

TIMER1 GATE SOURCE

SELECTION

17.6.4

TIMER1 GATE SINGLE-PULSE

MODE

The Timer1 gate source can be selected from one of

four different sources. Source selection is controlled by

the T1GSS bits of the T1GCON register. The polarity

for each available source is also selectable. Polarity

selection is controlled by the T1GPOL bit of the

T1GCON register.

When Timer1 Gate Single-Pulse mode is enabled, it is

possible to capture a single pulse gate event. Timer1

Gate Single-Pulse mode is first enabled by setting the

T1GSPM bit in the T1GCON register. Next, the

T1GGO/DONE bit in the T1GCON register must be set.

The Timer1 will be fully enabled on the next incrementing

edge. On the next trailing edge of the pulse, the

T1GGO/DONE bit will automatically be cleared. No other

gate events will be allowed to increment Timer1 until the

T1GGO/DONE bit is once again set in software. See

Figure 17-5 for timing details.

TABLE 17-4: TIMER1 GATE SOURCES

T1GSS

Timer1 Gate Source

Timer1 Gate Pin

00

01

Overflow of Timer0

If the Single Pulse Gate mode is disabled by clearing the

T1GSPM bit in the T1GCON register, the T1GGO/DONE

bit should also be cleared.

(TMR0 increments from FFh to 00h)

17.6.2.1

T1G Pin Gate Operation

Enabling the Toggle mode and the Single-Pulse mode

simultaneously will permit both sections to work

together. This allows the cycle times on the Timer1 gate

source to be measured. See Figure 17-6 for timing

details.

The T1G pin is one source for Timer1 gate control. It

can be used to supply an external source to the Timer1

gate circuitry.

17.6.2.2

Timer0 Overflow Gate Operation

17.6.5

TIMER1 GATE VALUE STATUS

When Timer0 increments from FFh to 00h,

a

When Timer1 Gate Value Status is utilized, it is possible

to read the most current level of the gate control value.

The value is stored in the T1GVAL bit in the T1GCON

register. The T1GVAL bit is valid even when the Timer1

gate is not enabled (TMR1GE bit is cleared).

low-to-high pulse will automatically be generated and

internally supplied to the Timer1 gate circuitry.

17.6.3

TIMER1 GATE TOGGLE MODE

When Timer1 Gate Toggle mode is enabled, it is possi-

ble to measure the full-cycle length of a Timer1 gate

signal, as opposed to the duration of a single level

pulse.

17.6.6

TIMER1 GATE EVENT INTERRUPT

When Timer1 Gate Event Interrupt is enabled, it is pos-

sible to generate an interrupt upon the completion of a

gate event. When the falling edge of T1GVAL occurs,

the TMR1GIF flag bit in the PIR1 register will be set. If

the TMR1GIE bit in the PIE1 register is set, then an

interrupt will be recognized.

The Timer1 gate source is routed through a flip-flop that

changes state on every incrementing edge of the

signal. See Figure 17-4 for timing details.

Timer1 Gate Toggle mode is enabled by setting the

T1GTM bit of the T1GCON register. When the T1GTM

bit is cleared, the flip-flop is cleared and held clear. This

is necessary in order to control which edge is

measured.

The TMR1GIF flag bit operates even when the Timer1

gate is not enabled (TMR1GE bit is cleared).

Note:

Enabling Toggle mode at the same time

as changing the gate polarity may result in

indeterminate operation.

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17.7 Timer1 Interrupt

17.8 Timer1 Operation During Sleep

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 register is

set. To enable the interrupt on rollover, you must set

these bits:

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

• T1SYNC bit of the T1CON register must be set

• TMR1ON bit of the T1CON register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

• TMR1CS bits of the T1CON register must be

configured

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

• T1OSCEN bit of the T1CON register must be

configured

Note:

The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

The device will wake-up on an overflow and execute

the next instructions. If the GIE bit of the INTCON

register is set, the device will call the Interrupt Service

Routine.

Timer1 oscillator will continue to operate in Sleep

regardless of the T1SYNC bit setting.

FIGURE 17-2:

TIMER1 INCREMENTING EDGE

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

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FIGURE 17-3:

TIMER1 GATE ENABLE MODE

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

Timer1

N

N + 1

N + 2

N + 3

N + 4

FIGURE 17-4:

TIMER1 GATE TOGGLE MODE

TMR1GE

T1GPOL

T1GTM

T1G_IN

T1CKI

T1GVAL

Timer1

N

N + 1 N + 2 N + 3 N + 4

N + 5 N + 6 N + 7 N + 8

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FIGURE 17-5:

TIMER1 GATE SINGLE-PULSE MODE

TMR1GE

T1GPOL

T1GSPM

Cleared by hardware on

falling edge of T1GVAL

T1GGO/

DONE

Set by software

Counting enabled on

rising edge of T1G

T1G_IN

T1CKI

T1GVAL

Timer1

N

N + 1

N + 2

Cleared by

software

Set by hardware on

falling edge of T1GVAL

Cleared by software

TMR1GIF

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FIGURE 17-6:

TMR1GE

T1GPOL

TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

T1GSPM

T1GTM

Cleared by hardware on

falling edge of T1GVAL

T1GGO/

DONE

Set by software

Counting enabled on

rising edge of T1G

T1G_IN

T1CKI

T1GVAL

Timer1

N + 4

N + 2 N + 3

N

N + 1

Set by hardware on

falling edge of T1GVAL

Cleared by

software

Cleared by software

TMR1GIF

DS40001569D-page 138

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17.9 Timer1 Control Register

The Timer1 Control register (T1CON), shown in

Register 17-1, is used to control Timer1 and select the

various features of the Timer1 module.

REGISTER 17-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0/u

T1SYNC

U-0

—

R/W-0/u

TMR1CS<1:0>

T1CKPS<1:0>

T1OSCEN

TMR1ON

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

TMR1CS<1:0>: Timer1 Clock Source Select bits

11=Reserved

10=Timer1 clock source is pin or oscillator:

If T1OSCEN = 0:

External clock from T1CKI pin (on the rising edge)

If T1OSCEN = 1:

Crystal oscillator on T1OSI/T1OSO pins

01=Timer1 clock source is system clock (FOSC)

00=Timer1 clock source is instruction clock (FOSC/4)

bit 5-4

T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3

bit 2

T1OSCEN: LP Oscillator Enable Control bit

1= Dedicated Timer1 oscillator circuit enabled

0= Dedicated Timer1 oscillator circuit disabled

T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS<1:0> = 1X

1= Do not synchronize external clock input

0= Synchronize external clock input with system clock (FOSC)

TMR1CS<1:0> = 0X

This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.

bit 1

bit 0

Unimplemented: Read as ‘0’

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

Clears Timer1 gate flip-flop

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17.10 Timer1 Gate Control Register

The Timer1 Gate Control register (T1GCON), shown in

Register 17-2, is used to control Timer1 gate.

REGISTER 17-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0/u

T1GPOL

R/W-0/u

T1GTM

R/W-0/u

R/W/HC-0/u

R-x/x

R/W-0/u

TMR1GE

T1GSPM

T1GGO/

DONE

T1GVAL

T1GSS<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7

TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1= Timer1 counting is controlled by the Timer1 gate function

0= Timer1 counts regardless of Timer1 gate function

bit 6

bit 5

T1GPOL: Timer1 Gate Polarity bit

1= Timer1 gate is active-high (Timer1 counts when gate is high)

0= Timer1 gate is active-low (Timer1 counts when gate is low)

T1GTM: Timer1 Gate Toggle Mode bit

1= Timer1 Gate Toggle mode is enabled

0= Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared

Timer1 gate flip-flop toggles on every rising edge.

bit 4

T1GSPM: Timer1 Gate Single-Pulse Mode bit

1= Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate

0= Timer1 gate Single-Pulse mode is disabled

bit 3

T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit

1= Timer1 gate single-pulse acquisition is ready, waiting for an edge

0= Timer1 gate single-pulse acquisition has completed or has not been started

bit 2

T1GVAL: Timer1 Gate Current State bit

Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.

Unaffected by Timer1 Gate Enable (TMR1GE).

bit 1-0

T1GSS<1:0>: Timer1 Gate Source Select bits

00= Timer1 gate pin

01= Timer0 overflow output

10= Reserved

11= Reserved

DS40001569D-page 140

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 17-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

PEIE

ADIE

ADIF

TMR0IE

RCIE

INTE

TXIE

TXIF

IOCIE

—

TMR0IF

INTF

—

IOCIF

TMR1IE

TMR1IF

65

66

TMR1GIE

TMR1GIF

PIE1

—

PIR1

RCIF

—

68

TMR1H

TMR1L

TRISC

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

135*

101

139

140

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2 TRISC1 TRISC0

TMR1ON

TMR1CS1 TMR1CS0

TMR1GE T1GPOL

T1CKPS<1:0>

T1OSCEN T1SYNC

—

T1CON

T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0

DONE

T1GCON

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.

Page provides register information.

*

 2011-2016 Microchip Technology Inc.

DS40001569D-page 141

PIC16LF1904/6/7

The EUSART module includes the following capabilities:

18.0 ENHANCED UNIVERSAL

SYNCHRONOUS

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is a serial I/O

communications peripheral. It contains all the clock

generators, shift registers and data buffers necessary

to perform an input or output serial data transfer

independent of device program execution. The

EUSART, also known as a Serial Communications

Interface (SCI), can be configured as a full-duplex

asynchronous system or half-duplex synchronous

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Programmable clock and data polarity

The EUSART module implements the following

additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

system.

Full-Duplex

mode

is

useful

for

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These devices typically do not have internal clocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

• Automatic detection and calibration of the baud rate

• Wake-up on Break reception

• 13-bit Break character transmit

Block diagrams of the EUSART transmitter and

receiver are shown in Figure 18-1 and Figure 18-2.

FIGURE 18-1:

EUSART TRANSMIT BLOCK DIAGRAM

Data Bus

TXIE

Interrupt

TXIF

TXREG Register

8

TX/CK pin

MSb

(8)

LSb

0

Pin Buffer

and Control

• • •

Transmit Shift Register (TSR)

TXEN

TRMT

Baud Rate Generator

BRG16

FOSC

÷ n

TX9

n

+ 1

Multiplier x4

x16 x64

TX9D

SYNC

BRGH

BRG16

1

X

1

0

1

0

1

0

SPBRGH SPBRGL

DS40001569D-page 142

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 18-2:

EUSART RECEIVE BLOCK DIAGRAM

CREN

OERR

RCIDL

RX/DT pin

RSR Register

MSb

Stop (8)

LSb

0

START

Pin Buffer

and Control

Data

Recovery

7

1

• • •

Baud Rate Generator

FOSC

RX9

÷ n

BRG16

n

+ 1

Multiplier x4

x16 x64

SYNC

BRGH

BRG16

1

X

1

0

1

0

1

0

FIFO

SPBRGH SPBRGL

RX9D

FERR

RCREG Register

8

Data Bus

RCIF

RCIE

Interrupt

The operation of the EUSART module is controlled

through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCON)

These registers are detailed in Register 18-1,

Register 18-2 and Register 18-3, respectively.

For all modes of EUSART operation, the TRIS control

bits corresponding to the RX/DT and TX/CK pins should

be set to ‘1’. The EUSART control will automatically

reconfigure the pin from input to output, as needed.

When the receiver or transmitter section is not enabled

then the corresponding RX/DT or TX/CK pin may be

used for general purpose input and output.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 143

PIC16LF1904/6/7

18.1.1.2

Transmitting Data

18.1 EUSART Asynchronous Mode

A transmission is initiated by writing a character to the

TXREG register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately

transferred to the TSR register. If the TSR still contains

all or part of a previous character, the new character

data is held in the TXREG until the Stop bit of the

previous character has been transmitted. The pending

character in the TXREG is then transferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the Start bit, data bits

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TXREG.

The EUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH Mark state which

represents a ‘1’ data bit, and a VOL Space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output level of that bit without returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the Mark state. Each character

transmission consists of one Start bit followed by eight

or nine data bits and is always terminated by one or

more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is eight bits. Each transmitted bit persists for a

period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-

bit Baud Rate Generator is used to derive standard

baud rate frequencies from the system oscillator. See

Table 18-5 for examples of baud rate configurations.

18.1.1.3

Transmit Data Polarity

The polarity of the transmit data can be controlled with

the SCKP bit of the BAUDCON register. The default

state of this bit is ‘0’ which selects high true transmit

Idle and data bits. Setting the SCKP bit to ‘1’ will invert

the transmit data resulting in low true Idle and data bits.

The SCKP bit controls transmit data polarity only in

Asynchronous mode. In Synchronous mode the SCKP

bit has a different function. See Section 18.5.1.2

“Clock Polarity”.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent, but share the same data format and baud

rate. Parity is not supported by the hardware, but can

be implemented in software and stored as the ninth

data bit.

18.1.1

EUSART ASYNCHRONOUS

TRANSMITTER

18.1.1.4

Transmit Interrupt Flag

The TXIF interrupt flag bit of the PIR1 register is set

whenever the EUSART transmitter is enabled and no

character is being held for transmission in the TXREG.

In other words, the TXIF bit is only clear when the TSR

is busy with a character and a new character has been

queued for transmission in the TXREG. The TXIF flag bit

is not cleared immediately upon writing TXREG. TXIF

becomes valid in the second instruction cycle following

the write execution. Polling TXIF immediately following

the TXREG write will return invalid results. The TXIF bit

is read-only, it cannot be set or cleared by software.

The EUSART transmitter block diagram is shown in

Figure 18-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXREG register.

18.1.1.1

Enabling the Transmitter

The EUSART transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

• TXEN = 1

• SYNC = 0

• SPEN = 1

The TXIF interrupt can be enabled by setting the TXIE

interrupt enable bit of the PIE1 register. However, the

TXIF flag bit will be set whenever the TXREG is empty,

regardless of the state of the TXIE enable bit.

All other EUSART control bits are assumed to be in

their default state.

To use interrupts when transmitting data, set the TXIE

bit only when there is more data to send. Clear the

TXIE interrupt enable bit upon writing the last character

of the transmission to the TXREG.

Setting the TXEN bit of the TXSTA register enables the

transmitter circuitry of the EUSART. Clearing the SYNC

bit of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART. The programmer

must set the corresponding TRIS bit to configure the TX/

CK I/O pin as an output. If the TX/CK pin is shared with

an analog peripheral, the analog I/O function must be

disabled by clearing the corresponding ANSEL bit.

Note:

The TXIF transmitter interrupt flag is set

when the TXEN enable bit is set.

DS40001569D-page 144

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

18.1.1.5

TSR Status

18.1.1.7

Asynchronous Transmission Set-up:

The TRMT bit of the TXSTA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

register from the TXREG. The TRMT bit remains clear

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user needs to

poll this bit to determine the TSR status.

1. Initialize the SPBRGH:SPBRGL register pair and

the BRGH and BRG16 bits to achieve the desired

baud rate (see Section 18.4 “EUSART Baud

Rate Generator (BRG)”).

2. Set the RX/DT and TX/CK TRIS controls to ‘1’.

3. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

4. If 9-bit transmission is desired, set the TX9

control bit. A set ninth data bit will indicate that

the eight Least Significant data bits are an

address when the receiver is set for address

detection.

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

18.1.1.6

Transmitting 9-Bit Characters

The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTA register is set, the

EUSART will shift 9 bits out for each character transmit-

ted. The TX9D bit of the TXSTA register is the ninth,

and Most Significant, data bit. When transmitting 9-bit

data, the TX9D data bit must be written before writing

the eight Least Significant bits into the TXREG. All nine

bits of data will be transferred to the TSR shift register

immediately after the TXREG is written.

5. Set the SCKP control bit if inverted transmit data

polarity is desired.

6. Enable the transmission by setting the TXEN

control bit. This will cause the TXIF interrupt bit

to be set.

7. If interrupts are desired, set the TXIE interrupt

enable bit. An interrupt will occur immediately

provided that the GIE and PEIE bits of the

INTCON register are also set.

A special 9-bit Address mode is available for use with

multiple receivers. See Section 18.1.2.7 “Address

Detection” for more information on the Address mode.

8. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

9. Load 8-bit data into the TXREG register. This

will start the transmission.

FIGURE 18-3:

ASYNCHRONOUS TRANSMISSION

Write to TXREG

Word 1

BRG Output

(Shift Clock)

TX/CK pin

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

1 TCY

Word 1

Transmit Shift Reg

TRMT bit

(Transmit Shift

Reg. Empty Flag)

 2011-2016 Microchip Technology Inc.

DS40001569D-page 145

PIC16LF1904/6/7

FIGURE 18-4:

ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Write to TXREG

Word 2

Start bit

Word 1

BRG Output

(Shift Clock)

TX/CK

Start bit

Word 2

bit 0

bit 1

bit 7/8

bit 0

Stop bit

Word 2

1 TCY

Word 1

TXIF bit

(Interrupt Reg. Flag)

1 TCY

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Transmit Shift Reg

Note:

This timing diagram shows two consecutive transmissions.

TABLE 18-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUD1CON ABDOVF

BAUD2CON ABDOVF

RCIDL

PEIE

—

SCKP

INTE

BRG16

IOCIE

—

WUE

INTF

—

ABDEN

IOCIF

153

65

INTCON

PIE1

GIE

TMR0IE

TMR0IF

—

(1)

TMR1GIE

TMR1GIF

SPEN

ADIE

ADIF

RX9

RCIE

TXIE

TMR1IE

TMR1IF

RX9D

66

(1)

PIR1

RCIF

TXIF

—

68

RCSTA

SPBRGL

SPBRGH

TXREG

TXSTA

SREN

CREN

ADDEN

FERR

OERR

152

154*

144*

151

EUSART Baud Rate Generator, Low Byte

EUSART Baud Rate Generator, High Byte

EUSART Transmit Register

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission.

Page provides register information.

*

Note 1: PIC16LF1904/7 only.

DS40001569D-page 146

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

18.1.2

EUSART ASYNCHRONOUS

RECEIVER

18.1.2.2

Receiving Data

The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,

also known as the Start bit, is always a zero. The data

recovery circuit counts one-half bit time to the center of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit counts a full bit time to the center of the

next bit. The bit is then sampled by a majority detect

circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.

This repeats until all data bits have been sampled and

shifted into the RSR. One final bit time is measured and

the level sampled. This is the Stop bit, which is always

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

character, otherwise the framing error is cleared for this

character. See Section 18.1.2.4 “Receive Framing

Error” for more information on framing errors.

The Asynchronous mode would typically be used in

RS-232 systems. The receiver block diagram is shown

in Figure 18-2. The data is received on the RX/DT pin

and drives the data recovery block. The data recovery

block is actually a high-speed shifter operating at 16

times the baud rate, whereas the serial Receive Shift

Register (RSR) operates at the bit rate. When all eight

or nine bits of the character have been shifted in, they

are immediately transferred to a two character First-In-

First-Out (FIFO) memory. The FIFO buffering allows

reception of two complete characters and the start of a

third character before software must start servicing the

EUSART receiver. The FIFO and RSR registers are not

directly accessible by software. Access to the received

data is via the RCREG register.

18.1.2.1

Enabling the Receiver

The EUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the EUSART receive FIFO and the RCIF interrupt

flag bit of the PIR1 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RCREG register.

• CREN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCSTA register enables the

receiver circuitry of the EUSART. Clearing the SYNC bit

of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART. The programmer

must set the corresponding TRIS bit to configure the

RX/DT I/O pin as an input.

Note:

If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition is cleared. See Section 18.1.2.5

“Receive Overrun Error” for more

information on overrun errors.

Note 1: If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

If the RX/DT pin is shared with an analog peripheral the

analog I/O function must be disabled by clearing the

corresponding ANSEL bit.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 147

PIC16LF1904/6/7

18.1.2.3

Receive Interrupts

18.1.2.6

Receiving 9-bit Characters

The RCIF interrupt flag bit of the PIR1 register is set

whenever the EUSART receiver is enabled and there is

an unread character in the receive FIFO. The RCIF

interrupt flag bit is read-only, it cannot be set or cleared

by software.

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set, the EUSART

will shift nine bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth and Most Significant data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCREG.

RCIF interrupts are enabled by setting the following

bits:

• RCIE interrupt enable bit of the PIE1 register

• PEIE peripheral interrupt enable bit of the INTCON

register

18.1.2.7

Address Detection

• GIE global interrupt enable bit of the INTCON

register

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCSTA

register.

The RCIF interrupt flag bit will be set when there is an

unread character in the FIFO, regardless of the state of

interrupt enable bits.

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffer, thereby setting the RCIF interrupt

bit. All other characters will be ignored.

18.1.2.4

Receive Framing Error

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indicates that a Stop bit was not seen at the expected

time. The framing error status is accessed via the

FERR bit of the RCSTA register. The FERR bit

represents the status of the top unread character in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RCREG.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

The FERR bit is read-only and only applies to the top

unread character in the receive FIFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCSTA register which resets the EUSART.

Clearing the CREN bit of the RCSTA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

Note:

If all receive characters in the receive

FIFO have framing errors, repeated reads

of the RCREG will not clear the FERR bit.

18.1.2.5

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated If a third character, in its

entirety, is received before the FIFO is accessed. When

this happens the OERR bit of the RCSTA register is set.

The characters already in the FIFO buffer can be read

but no additional characters will be received until the

error is cleared. The error must be cleared by either

clearing the CREN bit of the RCSTA register or by

resetting the EUSART by clearing the SPEN bit of the

RCSTA register.

DS40001569D-page 148

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

18.1.2.8

Asynchronous Reception Set-up:

18.1.2.9

9-bit Address Detection Mode Set-up

1. Initialize the SPBRGH:SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 18.4 “EUSART

Baud Rate Generator (BRG)”).

This mode would typically be used in RS-485 systems.

To set up an asynchronous reception with address

detect enable:

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 18.4 “EUSART

Baud Rate Generator (BRG)”).

2. Set the RX/DT and TX/CK TRIS controls to ‘1’.

3. Enable the serial port by setting the SPEN bit

and the RX/DT pin TRIS bit. The SYNC bit must

be clear for asynchronous operation.

2. Set the RX/DT and TX/CK TRIS controls to ‘1’.

4. If interrupts are desired, set the RCIE interrupt

enable bit and set the GIE and PEIE bits of the

INTCON register.

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

5. If 9-bit reception is desired, set the RX9 bit.

6. Enable reception by setting the CREN bit.

4. If interrupts are desired, set the RCIE interrupt

enable bit and set the GIE and PEIE bits of the

INTCON register.

7. The RCIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RCIE interrupt enable bit was also set.

5. Enable 9-bit reception by setting the RX9 bit.

6. Enable address detection by setting the ADDEN

bit.

8. Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

7. Enable reception by setting the CREN bit.

8. The RCIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the RSR to the receive buffer. An interrupt

will be generated if the RCIE interrupt enable bit

was also set.

9. Get the received eight Least Significant data bits

from the receive buffer by reading the RCREG

register.

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

9. Read the RCSTA register to get the error flags.

The ninth data bit will always be set.

10. Get the received eight Least Significant data bits

from the receive buffer by reading the RCREG

register. Software determines if this is the

device’s address.

11. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

12. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

FIGURE 18-5:

ASYNCHRONOUS RECEPTION

Start

bit

Start

bit

Start

bit

RX/DT pin

bit 7/8

bit 0 bit 1

Stop

bit

Stop

bit

Stop

bit

bit 0

bit 7/8

Rcv Shift

Reg

Rcv Buffer Reg

Word 2

RCREG

Word 1

RCREG

RCIDL

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note:

This timing diagram shows three words appearing on the RX/DT input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 149

PIC16LF1904/6/7

TABLE 18-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUD1CON

BAUD2CON

INTCON

PIE1

ABDOVF

GIE

RCIDL

PEIE

—

SCKP

INTE

BRG16

IOCIE

—

WUE

INTF

—

ABDEN

IOCIF

153

65

TMR0IE

TMR0IF

—

(1)

TMR1GIE

TMR1GIF

ADIE

ADIF

RCIE

TXIE

TMR1IE

TMR1IF

66

(1)

PIR1

RCIF

TXIF

—

68

RCREG

RCSTA

EUSART Receive Register

CREN ADDEN

147*

152

154*

101

151

SPEN

RX9

SREN

FERR

OERR

RX9D

SPBRGL

SPBRGH

TRISC

EUSART Baud Rate Generator, Low Byte

EUSART Baud Rate Generator, High Byte

TRISC7

CSRC

TRISC6

TX9

TRISC5 TRISC4 TRISC3

TXEN SYNC SENDB

TRISC2

BRGH

TRISC1

TRMT

TRISC0

TX9D

TXSTA

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.

Page provides register information.

*

Note 1: PIC16LF1904/7 only.

DS40001569D-page 150

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

The Auto-Baud Detect feature (see Section 18.4.1

“Auto-Baud Detect”) can be used to compensate for

changes in the INTOSC frequency.

18.2 Clock Accuracy with

Asynchronous Operation

The factory calibrates the internal oscillator block

output (INTOSC). However, the INTOSC frequency

may drift as VDD or temperature changes, and this

directly affects the asynchronous baud rate.

There may not be fine enough resolution when

adjusting the Baud Rate Generator to compensate for

a gradual change in the peripheral clock frequency.

18.3 Register Definitions: EUSART Control

REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0

CSRC

R/W-0

TX9

R/W-0

TXEN⁽¹⁾

R/W-0

SYNC

R/W-0

BRGH

R-1

R/W-0

TX9D

SENDB

TRMT

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

bit 4

bit 3

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

TXEN: Transmit Enable bit⁽¹⁾

1= Transmit enabled

0= Transmit disabled

SYNC: EUSART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

SENDB: Send Break Character bit

Asynchronous mode:

1= Send Sync Break on next transmission (cleared by hardware upon completion)

0= Sync Break transmission completed

Synchronous mode:

Don’t care

bit 2

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 151

PIC16LF1904/6/7

REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0

SPEN

R/W-0

RX9

R/W-0

SREN

R/W-0

CREN

R/W-0

R-0

R-x

ADDEN

FERR

OERR

RX9D

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit

1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0= Serial port disabled (held in Reset)

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave

Don’t care

bit 4

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables receiver

0= Disables receiver

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

0= Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Don’t care

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receive next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

DS40001569D-page 152

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER

R-0/0

R-1/1

U-0

—

R/W-0/0

SCKP

R/W-0/0

BRG16

U-0

—

R/W-0/0

WUE

R/W-0/0

ABDEN

ABDOVF

RCIDL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:

1= Auto-baud timer overflowed

0= Auto-baud timer did not overflow

Synchronous mode:

Don’t care

RCIDL: Receive Idle Flag bit

Asynchronous mode:

1= Receiver is Idle

0= Start bit has been received and the receiver is receiving

Synchronous mode:

Don’t care

bit 5

bit 4

Unimplemented: Read as ‘0’

SCKP: Synchronous Clock Polarity Select bit

Asynchronous mode:

1= Transmit inverted data to the TX/CK pin

0= Transmit non-inverted data to the TX/CK pin

Synchronous mode:

1= Data is clocked on rising edge of the clock

0= Data is clocked on falling edge of the clock

bit 3

BRG16: 16-bit Baud Rate Generator bit

1= 16-bit Baud Rate Generator is used

0= 8-bit Baud Rate Generator is used

bit 2

bit 1

Unimplemented: Read as ‘0’

WUE: Wake-up Enable bit

Asynchronous mode:

1= Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE

will automatically clear after RCIF is set.

0= Receiver is operating normally

Synchronous mode:

Don’t care

bit 0

ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:

1= Auto-Baud Detect mode is enabled (clears when auto-baud is complete)

0= Auto-Baud Detect mode is disabled

Synchronous mode:

Don’t care

 2011-2016 Microchip Technology Inc.

DS40001569D-page 153

PIC16LF1904/6/7

If the system clock is changed during an active receive

operation, a receive error or data loss may result. To

avoid this problem, check the status of the RCIDL bit to

make sure that the receive operation is Idle before

changing the system clock.

18.4 EUSART Baud Rate Generator

(BRG)

The Baud Rate Generator (BRG) is an 8-bit or 16-bit

timer that is dedicated to the support of both the

asynchronous and synchronous EUSART operation.

By default, the BRG operates in 8-bit mode. Setting the

BRG16 bit of the BAUDCON register selects 16-bit

mode.

EXAMPLE 18-1:

CALCULATING BAUD

RATE ERROR

For a device with FOSC of 16 MHz, desired baud rate

of 9600, Asynchronous mode, 8-bit BRG:

The SPBRGH:SPBRGL register pair determines the

period of the free running baud rate timer. In

Asynchronous mode the multiplier of the baud rate

period is determined by both the BRGH bit of the TXSTA

register and the BRG16 bit of the BAUDCON register. In

Synchronous mode, the BRGH bit is ignored.

FOSC

Desired Baud Rate = --------------------------------------------------------------------

64[SPBRGH:SPBRG] + 1

Solving for SPBRGH:SPBRGL:

FOSC

---------------------------------------------

Example 18-1 provides a sample calculation for deter-

mining the desired baud rate, actual baud rate, and

baud rate % error.

Desired Baud Rate

SPBRGH: SPBRGL = --------------------------------------------- – 1

64

16000000

-----------------------

9600

Typical baud rates and error values for various

Asynchronous modes have been computed for your

convenience and are shown in Table 18-5. It may be

advantageous to use the high baud rate (BRGH = 1),

or the 16-bit BRG (BRG16 = 1) to reduce the baud rate

error. The 16-bit BRG mode is used to achieve slow

baud rates for fast oscillator frequencies.

= ----------------------- – 1

64

= 25.042 = 25

16000000

ActualBaudRate = --------------------------

6425 + 1

= 9615

Writing a new value to the SPBRGH, SPBRGL register

pair causes the BRG timer to be reset (or cleared). This

ensures that the BRG does not wait for a timer overflow

before outputting the new baud rate.

Calc. Baud Rate – Desired Baud Rate

Baud Rate % Error =--------------------------------------------------------------------------------------------

Desired Baud Rate

9615 – 9600

= ---------------------------------- = 0 . 1 6 %

9600

TABLE 18-3: BAUD RATE FORMULAS

Configuration Bits

Baud Rate Formula

BRG/EUSART Mode

SYNC

BRG16

BRGH

0

1

0

1

0

1

0

1

0

1

x

8-bit/Asynchronous

16-bit/Asynchronous

8-bit/Synchronous

16-bit/Synchronous

FOSC/[64 (n+1)]

FOSC/[16 (n+1)]

FOSC/[4 (n+1)]

Legend:

x= Don’t care, n = value of SPBRGH, SPBRGL register pair

DS40001569D-page 154

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 18-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Reset

Valueson

page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUD1CON

BAUD2CON

RCSTA

ABDOVF

SPEN

RCIDL

RX9

—

SCKP

CREN

BRG16

ADDEN

—

WUE

ABDEN

RX9D

153

152

154*

151

SREN

FERR

OERR

SPBRGL

SPBRGH

TXSTA

EUSART Baud Rate Generator, Low Byte

EUSART Baud Rate Generator, High Byte

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

Legend:

— = unimplemented, read as ‘0’. Shaded bits are not used by the BRG.

*

Page provides register information.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 155

PIC16LF1904/6/7

TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 20.000 MHz

FOSC = 18.432 MHz

FOSC = 16.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

—

255

129

32

—

239

119

29

—

207

103

25

—

143

71

17

16

8

1221

2404

9470

10417

19.53k

1.73

0.16

-1.36

0.00

1.73

1200

2400

9600

10286

19.20k

0.00

-1.26

0.00

—

1202

2404

9615

10417

19.23k

0.16

0.00

0.16

—

1200

2400

9600

10165

19.20k

0.00

-2.42

0.00

—

2400

9600

10417

19.2k

57.6k

115.2k

29

27

23

15

14

12

2

—

57.60k

—

7

—

57.60k

—

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

0.00

—

300

1200

—

1202

2404

9615

10417

—

0.16

0.00

—

103

51

12

11

300

1202

2404

—

0.16

—

207

51

25

—

5

300

1200

2400

9600

—

191

47

23

5

300

1202

—

0.16

—

51

12

—

2400

9600

—

10417

19.2k

57.6k

115.2k

10417

—

0.00

—

2

—

19.20k

0.00

—

0

—

57.60k

—

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 18.432 MHz FOSC = 16.000 MHz

FOSC = 20.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

—

300

1200

2400

9600

10417

19.2k

57.6k

—

71

65

35

11

5

9615

10417

19.23k

56.82k

0.16

0.00

0.16

-1.36

129

119

64

9600

10378

19.20k

57.60k

115.2k

0.00

-0.37

0.00

119

110

59

19

9

9615

10417

19.23k

58.82k

111.1k

0.16

0.00

0.16

2.12

-3.55

103

95

51

16

8

9600

0.00

0.53

0.00

10473

19.20k

57.60k

115.2k

21

115.2k 113.64k -1.36

10

DS40001569D-page 156

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

—

300

1200

—

1202

2404

9615

10417

19.23k

—

207

103

25

—

191

95

23

21

11

3

300

1202

2404

—

0.16

—

207

51

25

—

5

0.16

0.00

0.16

—

1200

0.00

0.53

0.00

2400

2404

9615

10417

19231

55556

—

0.16

0.00

0.16

-3.55

—

207

51

47

25

8

2400

9600

10417

19.2k

57.6k

115.2k

23

10473

19.2k

57.60k

115.2k

10417

—

0.00

—

12

—

1

—

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 18.432 MHz FOSC = 16.000 MHz

FOSC = 20.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

300

1200

2400

9600

10417

19.2k

57.6k

300.0

1200

-0.01

-0.03

0.16

0.00

0.16

-1.36

4166

1041

520

129

119

64

300.0

1200

0.00

-0.37

0.00

3839

959

479

119

110

59

300.03

1200.5

2398

0.01

0.04

-0.08

0.16

0.00

0.16

2.12

3332

832

416

103

95

300.0

1200

0.00

0.53

0.00

2303

575

287

71

2399

2400

9615

9600

9615

9600

10417

19.23k

56.818

10378

19.20k

57.60k

115.2k

10417

19.23k

58.82k

10473

19.20k

57.60k

115.2k

65

51

35

21

19

16

11

115.2k 113.636 -1.36

10

9

111.11k -3.55

8

5

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

Error

(decimal)

300

1200

299.9

1199

-0.02

-0.08

0.16

0.00

0.16

-3.55

—

1666

416

207

51

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

300.0

1200

0.00

0.53

0.00

767

191

95

23

21

11

3

300.5

1202

2404

—

0.16

—

207

51

25

—

5

2400

2404

9615

10417

19.23k

55556

—

2400

9600

10417

19.2k

57.6k

115.2k

47

23

10473

19.20k

57.60k

115.2k

10417

—

0.00

—

25

12

—

8

—

1

—

 2011-2016 Microchip Technology Inc.

DS40001569D-page 157

PIC16LF1904/6/7

TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 20.000 MHz

FOSC = 18.432 MHz

FOSC = 16.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

300.0

1200

0.00

-0.01

0.02

-0.03

0.00

0.16

-0.22

0.94

16665

4166

2082

520

479

259

86

300.0

1200

0.00

0.08

0.00

15359

3839

1919

479

441

239

79

300.0

1200.1

2399.5

9592

0.00

0.01

-0.02

-0.08

0.00

0.16

0.64

13332

3332

1666

416

383

207

68

300.0

1200

0.00

0.16

0.00

9215

2303

1151

287

264

143

47

2400

9600

9597

9600

10417

19.2k

57.6k

115.2k

10417

19.23k

57.47k

116.3k

10425

19.20k

57.60k

115.2k

10417

19.23k

57.97k

10433

19.20k

57.60k

115.2k

42

39

114.29k -0.79

34

23

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

300.0

1200

0.00

-0.02

0.04

0.16

0

6666

1666

832

207

191

103

34

300.0

1200

0.01

0.04

0.08

0.16

0.00

0.16

2.12

-3.55

3332

832

416

103

95

300.0

1200

0.00

0.53

0.00

3071

767

383

95

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

2400

2401

2398

2400

9600

9615

9600

10417

19.2k

57.6k

115.2k

10417

19.23k

57.14k

117.6k

10417

19.23k

58.82k

111.1k

10473

19.20k

57.60k

115.2k

87

23

0.16

-0.79

2.12

51

47

12

16

15

—

16

8

7

—

DS40001569D-page 158

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

and SPBRGL registers are clocked at 1/8th the BRG

base clock rate. The resulting byte measurement is the

average bit time when clocked at full speed.

18.4.1

AUTO-BAUD DETECT

The EUSART module supports automatic detection

and calibration of the baud rate.

Note 1: If the WUE bit is set with the ABDEN bit,

auto-baud detection will occur on the byte

following the Break character (see

Section 18.4.3 “Auto-Wake-up on

Break”).

In the Auto-Baud Detect (ABD) mode, the clock to the

BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG.

The Baud Rate Generator is used to time the period of

a received 55h (ASCII “U”) which is the Sync character

for the LIN bus. The unique feature of this character is

that it has five rising edges including the Stop bit edge.

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible.

Setting the ABDEN bit of the BAUDCON register starts

the auto-baud calibration sequence (Figure 18.4.2).

While the ABD sequence takes place, the EUSART

state machine is held in Idle. On the first rising edge of

the receive line, after the Start bit, the SPBRGL begins

counting up using the BRG counter clock as shown in

Table 18-6. The fifth rising edge will occur on the RX/

DT pin at the end of the eighth bit period. At that time,

an accumulated value totaling the proper BRG period

is left in the SPBRGH:SPBRGL register pair, the

ABDEN bit is automatically cleared, and the RCIF

interrupt flag is set. A read operation on the RCREG

needs to be performed to clear the RCIF interrupt.

RCREG content should be discarded. When calibrating

for modes that do not use the SPBRGH register the

user can verify that the SPBRGL register did not

overflow by checking for 00h in the SPBRGH register.

3: During the auto-baud process, the auto-

baud counter starts counting at 1. Upon

completion of the auto-baud sequence, to

achieve maximum accuracy, subtract 1

from the SPBRGH:SPBRGL register pair.

TABLE 18-6: BRG COUNTER CLOCK

RATES

BRG Base

Clock

BRG ABD

Clock

BRG16 BRGH

0

1

FOSC/64

FOSC/16

FOSC/512

FOSC/128

The BRG auto-baud clock is determined by the BRG16

and BRGH bits as shown in Table 18-6. During ABD,

both the SPBRGH and SPBRGL registers are used as

a 16-bit counter, independent of the BRG16 bit setting.

While calibrating the baud rate period, the SPBRGH

1

0

1

FOSC/16

FOSC/4

FOSC/128

FOSC/32

Note:

During the ABD sequence, SPBRGL and

SPBRGH registers are both used as a 16-

bit counter, independent of BRG16 setting.

FIGURE 18-6:

AUTOMATIC BAUD RATE CALIBRATION

XXXXh

0000h

001Ch

BRG Value

Edge #5

Stop bit

Edge #1

bit 1

Edge #2

bit 3

Edge #3

bit 5

bit 4

Edge #4

bit 7

RX/DT pin

BRG Clock

Start

bit 0

bit 2

bit 6

Auto Cleared

Set by User

ABDEN bit

RCIDL

RCIF bit

(Interrupt)

Read

RCREG

XXh

1Ch

00h

SPBRGL

SPBRGH

Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 159

PIC16LF1904/6/7

18.4.2

AUTO-BAUD OVERFLOW

18.4.3.1

Special Considerations

During the course of automatic baud detection, the

ABDOVF bit of the BAUDCON register will be set if the

baud rate counter overflows before the fifth rising edge

is detected on the RX pin. The ABDOVF bit indicates

that the counter has exceeded the maximum count that

can fit in the 16 bits of the SPBRGH:SPBRGL register

pair. After the ABDOVF has been set, the counter con-

tinues to count until the fifth rising edge is detected on

the RX/DT pin. Upon detecting the fifth RX/DT edge,

the hardware will set the RCIF interrupt flag and clear

the ABDEN bit of the BAUDCON register. The RCIF

flag can be subsequently cleared by reading the

RCREG. The ABDOVF flag can be cleared by software

directly.

Break Character

To avoid character errors or character fragments during

a wake-up event, the wake-up character must be all

zeros.

When the wake-up is enabled the function works

independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is

received, the low time from the Start bit to the first rising

edge will be interpreted as the wake-up event. The

remaining bits in the character will be received as a

fragmented character and subsequent characters can

result in framing or overrun errors.

Therefore, the initial character in the transmission must

be all ‘0’s. This must be ten or more bit times, 13-bit

times recommended for LIN bus, or any number of bit

times for standard RS-232 devices.

To terminate the auto-baud process before the RCIF

flag is set, clear the ABDEN bit then clear the ABDOVF

bit. The ABDOVF bit will remain set if the ABDEN bit is

not cleared first.

Oscillator Startup Time

Oscillator start-up time must be considered, especially

in applications using oscillators with longer start-up

intervals (i.e., LP, XT or HS/PLL mode). The Sync

Break (or wake-up signal) character must be of

sufficient length, and be followed by a sufficient

interval, to allow enough time for the selected oscillator

to start and provide proper initialization of the EUSART.

18.4.3

AUTO-WAKE-UP ON BREAK

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper character reception cannot be

performed. The Auto-Wake-up feature allows the

controller to wake-up due to activity on the RX/DT line.

This feature is available only in Asynchronous mode.

WUE Bit

The Auto-Wake-up feature is enabled by setting the

WUE bit of the BAUDCON register. Once set, the normal

receive sequence on RX/DT is disabled, and the

EUSART remains in an Idle state, monitoring for a wake-

up event independent of the CPU mode. A wake-up

event consists of a high-to-low transition on the RX/DT

line. (This coincides with the start of a Sync Break or a

wake-up signal character for the LIN protocol.)

The wake-up event causes a receive interrupt by

setting the RCIF bit. The WUE bit is cleared by

hardware by a rising edge on RX/DT. The interrupt

condition is then cleared by software by reading the

RCREG register and discarding its contents.

To ensure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process

before setting the WUE bit. If a receive operation is not

occurring, the WUE bit may then be set just prior to

entering the Sleep mode.

The EUSART module generates an RCIF interrupt

coincident with the wake-up event. The interrupt is

generated synchronously to the Q clocks in normal CPU

operating modes (Figure 18-7), and asynchronously if

the device is in Sleep mode (Figure 18-8). The interrupt

condition is cleared by reading the RCREG register.

The WUE bit is automatically cleared by the low-to-high

transition on the RX line at the end of the Break. This

signals to the user that the Break event is over. At this

point, the EUSART module is in Idle mode waiting to

receive the next character.

DS40001569D-page 160

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 18-7:

AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4

OSC1

Auto Cleared

Bit set by user

WUE bit

RX/DT Line

RCIF

Cleared due to User Read of RCREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

FIGURE 18-8:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q4

Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3

Q1

Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4

Auto Cleared

OSC1

Bit Set by User

WUE bit

RX/DT Line

RCIF

Note 1

Cleared due to User Read of RCREG

Sleep Command Executed

Sleep Ends

Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is

still active. This sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 161

PIC16LF1904/6/7

When the TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.

18.4.4

BREAK CHARACTER SEQUENCE

The EUSART module has the capability of sending the

special Break character sequences that are required by

the LIN bus standard. A Break character consists of a

Start bit, followed by 12 ‘0’ bits and a Stop bit.

18.4.5

RECEIVING A BREAK CHARACTER

The Enhanced EUSART module can receive a Break

character in two ways.

To send a Break character, set the SENDB and TXEN

bits of the TXSTA register. The Break character trans-

mission is then initiated by a write to the TXREG. The

value of data written to TXREG will be ignored and all

‘0’s will be transmitted.

The first method to detect a Break character uses the

FERR bit of the RCSTA register and the Received data

as indicated by RCREG. The Baud Rate Generator is

assumed to have been initialized to the expected baud

rate.

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN specification).

A Break character has been received when;

• RCIF bit is set

• FERR bit is set

• RCREG = 00h

The TRMT bit of the TXSTA register indicates when the

transmit operation is active or Idle, just as it does during

normal transmission. See Figure 18-9 for the timing of

the Break character sequence.

The second method uses the Auto-Wake-up feature

described in Section 18.4.3 “Auto-Wake-up on

Break”. By enabling this feature, the EUSART will

sample the next two transitions on RX/DT, cause an

RCIF interrupt, and receive the next data byte followed

by another interrupt.

18.4.4.1

Break and Sync Transmit Sequence

The following sequence will start a message frame

header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus

master.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Detect feature.

For both methods, the user can set the ABDEN bit of

the BAUDCON register before placing the EUSART in

Sleep mode.

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to enable the

Break sequence.

3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG to load the Sync character

into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is

reset by hardware and the Sync character is

then transmitted.

FIGURE 18-9:

SEND BREAK CHARACTER SEQUENCE

Write to TXREG

Dummy Write

BRG Output

(Shift Clock)

TX/CK (pin)

Start bit

bit 0

bit 1

Break

bit 11

Stop bit

TXIF bit

(Transmit

interrupt Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

SENDB Sampled Here

Auto Cleared

SENDB

(send Break

control bit)

DS40001569D-page 162

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

18.5.1.2

Clock Polarity

18.5 EUSART Synchronous Mode

A clock polarity option is provided for Microwire

compatibility. Clock polarity is selected with the SCKP

bit of the BAUDCON register. Setting the SCKP bit sets

the clock Idle state as high. When the SCKP bit is set,

the data changes on the falling edge of each clock and

is sampled on the rising edge of each clock. Clearing

the SCKP bit sets the Idle state as low. When the SCKP

bit is cleared, the data changes on the rising edge of

each clock and is sampled on the falling edge of each

clock.

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary

circuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the

internal clock generation circuitry.

There are two signal lines in Synchronous mode: a

bidirectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and

transmit shift registers. Since the data line is

bidirectional, synchronous operation is half-duplex

only. Half-duplex refers to the fact that master and

slave devices can receive and transmit data but not

both simultaneously. The EUSART can operate as

either a master or slave device.

18.5.1.3

Synchronous Master Transmission

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are automat-

ically enabled when the EUSART is configured for

synchronous master transmit operation.

A transmission is initiated by writing a character to the

TXREG register. If the TSR still contains all or part of a

previous character the new character data is held in the

TXREG until the last bit of the previous character has

been transmitted. If this is the first character, or the pre-

vious character has been completely flushed from the

TSR, the data in the TXREG is immediately transferred

to the TSR. The transmission of the character com-

mences immediately following the transfer of the data

to the TSR from the TXREG.

Start and Stop bits are not used in synchronous

transmissions.

18.5.1

SYNCHRONOUS MASTER MODE

The following bits are used to configure the EUSART

for synchronous master operation:

• SYNC = 1

• CSRC = 1

Each data bit changes on the leading edge of the

master clock and remains valid until the subsequent

leading clock edge.

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

Setting the SYNC bit of the TXSTA register configures

the device for synchronous operation. Setting the CSRC

bit of the TXSTA register configures the device as a

master. Clearing the SREN and CREN bits of the RCSTA

register ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART. If the RX/DT or TX/CK pins are shared with an

analog peripheral the analog I/O functions must be

disabled by clearing the corresponding ANSEL bits.

18.5.1.4

Synchronous Master Transmission

Set-up:

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 18.4 “EUSART

Baud Rate Generator (BRG)”).

2. Set the RX/DT and TX/CK TRIS controls to ‘1’.

The TRIS bits corresponding to the RX/DT and TX/CK

pins should be set.

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC. Set the

TRIS bits corresponding to the RX/DT and TX/

CK I/O pins.

18.5.1.1

Master Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured

as a master transmits the clock on the TX/CK line. The

TX/CK pin output driver is automatically enabled when

the EUSART is configured for synchronous transmit or

receive operation. Serial data bits change on the leading

edge to ensure they are valid at the trailing edge of each

clock. One clock cycle is generated for each data bit.

Only as many clock cycles are generated as there are

data bits.

4. Disable Receive mode by clearing bits SREN

and CREN.

5. Enable Transmit mode by setting the TXEN bit.

6. If 9-bit transmission is desired, set the TX9 bit.

7. If interrupts are desired, set the TXIE, GIE and

PEIE interrupt enable bits.

8. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

9. Start transmission by loading data to the TXREG

register.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 163

PIC16LF1904/6/7

FIGURE 18-10:

SYNCHRONOUS TRANSMISSION

RX/DT

bit 0

bit 1

bit 2

bit 7

bit 0

bit 1

Word 2

bit 7

Word 1

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

TXREG Reg

Write Word 1

Write Word 2

TXIF bit

(Interrupt Flag)

TRMT bit

‘1’

TXEN bit

Note:

Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.

FIGURE 18-11:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin

bit 0

bit 2

bit 1

bit 6

bit 7

TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

TXEN bit

DS40001569D-page 164

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUD1CON ABDOVF

BAUD2CON ABDOVF

RCIDL

PEIE

ADIE

ADIF

RX9

—

SCKP

INTE

BRG16

IOCIE

—

WUE

INTF

—

ABDEN

IOCIF

153

65

INTCON

PIE1

GIE

TMR0IE

TMR0IF

—

(1)

TMR1GIE

TMR1GIF

SPEN

RCIE

TXIE

TMR1IE

TMR1IF

RX9D

66

(1)

PIR1

RCIF

TXIF

—

68

RCSTA

SPBRGL

SPBRGH

TRISC

TRISG

TXREG

TXSTA

SREN

CREN

ADDEN

FERR

OERR

152

154*

98

EUSART Baud Rate Generator, Low Byte

EUSART Baud Rate Generator, High Byte

TRISC7

—

TRISC6

—

TRISC5

—

TRISC4

TRISG4

TRISC3

TRISG3

TRISC2

TRISG2

TRISC1

TRISG1

TRISC0

TRISG0

98

EUSART Transmit Register

SYNC SENDB

144*

151

CSRC

TX9

TXEN

BRGH

TRMT

TX9D

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master transmission.

Page provides register information.

*

Note 1: PIC16LF1904/7 only.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 165

PIC16LF1904/6/7

If the overrun occurred when the CREN bit is set then

the error condition is cleared by either clearing the

CREN bit of the RCSTA register or by clearing the

SPEN bit which resets the EUSART.

18.5.1.5

Synchronous Master Reception

Data is received at the RX/DT pin. The RX/DT pin

output driver must be disabled by setting the

corresponding TRIS bits when the EUSART is

configured for synchronous master receive operation.

18.5.1.8

Receiving 9-bit Characters

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCSTA register) or the Continuous Receive Enable bit

(CREN of the RCSTA register).

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set the EUSART

will shift nine bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth, and Most Significant, data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCREG.

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the completion of one character. When CREN is set,

clocks are continuously generated until CREN is

cleared. If CREN is cleared in the middle of a character

the CK clock stops immediately and the partial charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cleared at the completion of the first character

and CREN takes precedence.

18.5.1.9

Synchronous Master Reception Set-

up:

1. Initialize the SPBRGH, SPBRGL register pair for

the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

Register (RSR). When a complete character is

received into the RSR, the RCIF bit is set and the

character is automatically transferred to the two

character receive FIFO. The Least Significant eight bits

of the top character in the receive FIFO are available in

RCREG. The RCIF bit remains set as long as there are

un-read characters in the receive FIFO.

2. Set the RX/DT and TX/CK TRIS controls to ‘1’.

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC. Disable

RX/DT and TX/CK output drivers by setting the

corresponding TRIS bits.

4. Ensure bits CREN and SREN are clear.

5. If using interrupts, set the GIE and PEIE bits of

the INTCON register and set RCIE.

18.5.1.6

Slave Clock

6. If 9-bit reception is desired, set bit RX9.

7. Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured

as a slave receives the clock on the TX/CK line. The TX/

CK pin output driver must be disabled by setting the

associated TRIS bit when the device is configured for

synchronous slave transmit or receive operation. Serial

data bits change on the leading edge to ensure they are

valid at the trailing edge of each clock. One data bit is

transferred for each clock cycle. Only as many clock

cycles should be received as there are data bits.

8. Interrupt flag bit RCIF will be set when reception

of a character is complete. An interrupt will be

generated if the enable bit RCIE was set.

9. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RCREG register.

11. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit which resets

the EUSART.

18.5.1.7

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before RCREG is read to access

the FIFO. When this happens the OERR bit of the

RCSTA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

will be received until the error is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RCREG.

DS40001569D-page 166

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 18-12:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

bit SREN

SREN bit

‘0’

CREN bit

RCIF bit

(Interrupt)

Read

RCREG

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.

TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUD1CON

BAUD2CON

INTCON

PIE1

ABDOVF

GIE

RCIDL

PEIE

—

SCKP

INTE

BRG16

IOCIE

—

WUE

INTF

—

ABDEN

IOCIF

153

65

TMR0IE

TMR0IF

—

(1)

TMR1GIE

TMR1GIF

ADIE

RCIE

TXIE

TXIF

TMR1IE

TMR1IF

66

(1)

PIR1

ADIF

RCIF

—

68

RCREG

RCSTA

EUSART Receive Register

CREN ADDEN

147*

152

154*

151

SPEN

CSRC

RX9

TX9

SREN

FERR

OERR

RX9D

SPBRGL

SPBRGH

TXSTA

EUSART Baud Rate Generator, Low Byte

EUSART Baud Rate Generator, High Byte

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.

Page provides register information.

*

Note 1: PIC16LF1904/7 only.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 167

PIC16LF1904/6/7

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

18.5.2

SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART

for Synchronous slave operation:

1. The first character will immediately transfer to

the TSR register and transmit.

• SYNC = 1

2. The second word will remain in TXREG register.

3. The TXIF bit will not be set.

• CSRC = 0

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

4. After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

Setting the SYNC bit of the TXSTA register configures the

device for synchronous operation. Clearing the CSRC bit

of the TXSTA register configures the device as a slave.

Clearing the SREN and CREN bits of the RCSTA register

ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART. If the RX/DT or TX/CK pins are shared with an

analog peripheral the analog I/O functions must be

disabled by clearing the corresponding ANSEL bits.

5. If the PEIE and TXIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

18.5.2.2

Synchronous Slave Transmission

Set-up:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

RX/DT and TX/CK pin output drivers must be disabled

by setting the corresponding TRIS bits.

2. Set the RX/DT and TX/CK TRIS controls to ‘1’.

3. Clear the CREN and SREN bits.

4. If using interrupts, ensure that the GIE and PEIE

bits of the INTCON register are set and set the

TXIE bit.

18.5.2.1

EUSART Synchronous Slave

Transmit

The operation of the Synchronous Master and Slave

modes are identical (see Section 18.5.1.3

“Synchronous Master Transmission”), except in the

5. If 9-bit transmission is desired, set the TX9 bit.

6. Enable transmission by setting the TXEN bit.

7. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

case of the Sleep mode.

8. Start transmission by writing the Least

Significant eight bits to the TXREG register.

DS40001569D-page 168

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUD1CON ABDOVF

BAUD2CON ABDOVF

RCIDL

PEIE

ADIE

ADIF

RX9

—

SCKP

INTE

BRG16

IOCIE

—

WUE

INTF

—

ABDEN

IOCIF

153

65

INTCON

PIE1

GIE

TMR0IE

TMR0IF

—

(1)

TMR1GIE

TMR1GIF

SPEN

RCIE

TXIE

TMR1IE

TMR1IF

RX9D

66

(1)

PIR1

RCIF

TXIF

—

68

RCSTA

SPBRGL

SPBRGH

TRISC

TXREG

TXSTA

SREN

CREN

ADDEN

FERR

OERR

152

154*

98

EUSART Baud Rate Generator, Low Byte

EUSART Baud Rate Generator, High Byte

TRISC7

CSRC

TRISC6

TX9

TRISC5

EUSART Transmit Register

SYNC SENDB

TRISC4 TRISC3

TRISC2

TRISC1

TRMT

TRISC0

TX9D

144*

151

TXEN

BRGH

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave transmission.

Page provides register information.

*

Note 1: PIC16LF1904/7 only.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 169

PIC16LF1904/6/7

18.5.2.3

EUSART Synchronous Slave

Reception

18.5.2.4

Synchronous Slave Reception Set-

up:

The operation of the Synchronous Master and Slave

modes is identical (Section 18.5.1.5 “Synchronous

Master Reception”), with the following exceptions:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Set the RX/DT and TX/CK TRIS controls to ‘1’.

• Sleep

3. If using interrupts, ensure that the GIE and PEIE

bits of the INTCON register are set and set the

RCIE bit.

• CREN bit is always set, therefore the receiver is

never Idle

4. If 9-bit reception is desired, set the RX9 bit.

5. Set the CREN bit to enable reception.

• SREN bit, which is a “don’t care” in Slave mode

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCREG register. If the RCIE enable bit is set, the

interrupt generated will wake the device from Sleep

and execute the next instruction. If the GIE bit is also

set, the program will branch to the interrupt vector.

6. The RCIF bit will be set when reception is

complete. An interrupt will be generated if the

RCIE bit was set.

7. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

register.

8. Retrieve the eight Least Significant bits from the

receive FIFO by reading the RCREG register.

9. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit which resets

the EUSART.

TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUD1CON

BAUD2CON

INTCON

PIE1

ABDOVF

GIE

RCIDL

PEIE

—

SCKP

INTE

TXIE

TXIF

BRG16

IOCIE

—

WUE

INTF

—

ABDEN

IOCIF

153

65

TMR0IE

RCIE

RCIF

TMR0IF

—

TMR1GIE

TMR1GIF

ADIE

TMR1IE

TMR1IF

66

PIR1

ADIF

—

68

RCREG

RCSTA

EUSART Receive Register

CREN ADDEN

147*

152

154*

151

SPEN

RX9

SREN

FERR

OERR

RX9D

SPBRGL

SPBRGH

TXSTA

EUSART Baud Rate Generator, Low Byte

EUSART Baud Rate Generator, High Byte

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception.

Page provides register information.

*

DS40001569D-page 170

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

19.1 LCD Registers

19.0 LIQUID CRYSTAL DISPLAY

(LCD) DRIVER MODULE

The module contains the following registers:

The Liquid Crystal Display (LCD) driver module

generates the timing control to drive a static or

multiplexed LCD panel. In the PIC16LF1904/6/7

device, the module drives the panels of up to four

commons and up to 116 total segments. The LCD

module also provides control of the LCD pixel data.

• LCD Control register (LCDCON)

• LCD Phase register (LCDPS)

• LCD Reference Ladder register (LCDRL)

• LCD Contrast Control register (LCDCST)

• LCD Reference Voltage Control register

(LCDREF)

The LCD driver module supports:

• Up to 4 LCD Segment Enable registers (LCDSEn)

• Up to 16 LCD data registers (LCDDATAn)

• Direct driving of LCD panel

• Three LCD clock sources with selectable prescaler

• Up to four common pins:

- Static (1 common)

- 1/2 multiplex (2 commons)

- 1/3 multiplex (3 commons)

- 1/4 multiplex (4 commons)

• 19 Segment pins (PIC16LF1906 only)

• 29 Segment pins (PIC16LF1904/7 only)

• Static, 1/2 or 1/3 LCD Bias

Note:

COM3 and SEG15 share the same

physical pin on the PIC16LF1906,

therefore SEG15 is not available when

using 1/4 multiplex displays.

FIGURE 19-1:

LCD DRIVER MODULE BLOCK DIAGRAM

SEG<28:0>⁽²⁾

LCDDATAx

Registers

Data Bus

To I/O Pads⁽¹⁾

MUX

Timing Control

LCDCON

LCDPS

COM<3:0>

To I/O Pads⁽¹⁾

LCDSEn

FOSC/256

Clock Source

Select and

Prescaler

T1OSC

LFINTOSC

Note 1: These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of

the LCD module.

2: COM3 and SEG15 share the same physical pin, therefore SEG15 is not available when using 1/4 multi-

plex displays. For the PIC16LF1906 device only.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 171

PIC16LF1904/6/7

TABLE 19-1: LCD SEGMENT AND DATA

REGISTERS

# of LCD Registers

Device

Segment

Enable

Data

PIC16LF1904/7

PIC16LF1906

3

4

16

12

The LCDCON register (Register 19-1) controls the

operation of the LCD driver module. The LCDPS regis-

ter (Register 19-2) configures the LCD clock source

prescaler and the type of waveform; Type-A or Type-B.

The LCDSEn registers (Register 19-5) configure the

functions of the port pins.

The following LCDSEn registers are available:

• LCDSE0 SE<7:0>

• LCDSE1 SE<15:8>

• LCDSE2 SE<23:16>⁽¹⁾

• LCDSE3 SE<28:24>⁽¹⁾(SE<26:24>⁽²⁾

)

Once the module is initialized for the LCD panel, the

individual bits of the LCDDATAn registers are

cleared/set to represent a clear/dark pixel, respectively:

• LCDDATA0 SEG<7:0>COM0

• LCDDATA1 SEG<15:8>COM0

• LCDDATA2 SEG<23:16>COM0⁽¹⁾

• LCDDATA3 SEG<7:0>COM1

• LCDDATA4 SEG<15:8>COM1

• LCDDATA5 SEG<23:16>COM1⁽¹⁾

• LCDDATA6 SEG<7:0>COM2

• LCDDATA7 SEG<15:8>COM2

• LCDDATA8 SEG<23:16>COM2⁽¹⁾

• LCDDATA9 SEG<7:0>COM3

• LCDDATA10 SEG<15:8>COM3

• LCDDATA11 SEG<23:16>COM3⁽¹⁾

• LCDDATA12 SEG<28:24>COM0⁽¹⁾

(SEG<26:24>)⁽²⁾

• LCDDATA15 SEG<28:24>COM1⁽¹⁾

(SEG<26:24>)⁽²⁾

• LCDDATA18 SEG<28:24>COM2⁽¹⁾

(SEG<26:24>)⁽²⁾

• LCDDATA21 SEG<28:24>COM3⁽¹⁾

(SEG<26:24>)⁽²⁾

Note 1: PIC16LF1904/7 only.

2: PIC16LF1906 only.

As an example, LCDDATAn is detailed in

Register 19-6.

Once the module is configured, the LCDEN bit of the

LCDCON register is used to enable or disable the LCD

module. The LCD panel can also operate during Sleep

by clearing the SLPEN bit of the LCDCON register.

DS40001569D-page 172

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

REGISTER 19-1: LCDCON: LIQUID CRYSTAL DISPLAY (LCD) CONTROL REGISTER

R/W-0/0

LCDEN

R/W-0/0

SLPEN

R/C-0/0

WERR

U-0

—

R/W-0/0

R/W-1/1

CS<1:0>

LMUX<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

C = Only clearable bit

bit 7

bit 6

bit 5

LCDEN: LCD Driver Enable bit

1= LCD driver module is enabled

0= LCD driver module is disabled

SLPEN: LCD Driver Enable in Sleep Mode bit

1= LCD driver module is disabled in Sleep mode

0= LCD driver module is enabled in Sleep mode

WERR: LCD Write Failed Error bit

1 = LCDDATAn register written while the WA bit of the LCDPS register = 0 (must be cleared in

software)

0= No LCD write error

bit 4

Unimplemented: Read as ‘0’

bit 3-2

CS<1:0>: Clock Source Select bits

00= FOSC/256

01= T1OSC (Timer1)

1x= LFINTOSC (31 kHz)

bit 1-0

LMUX<1:0>: Commons Select bits

Maximum Number of Pixels

LMUX<1:0>

Multiplex

Bias

PIC16LF1906 PIC16LF1904/7

00

01

10

11

Static (COM0)

1/2 (COM<1:0>)

1/3 (COM<2:0>)

1/4 (COM<3:0>)

19

38

29

58

Static

1/2 or 1/3

1/3

57

72⁽¹⁾

87

116

Note 1: On these devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 72 segments.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 173

PIC16LF1904/6/7

REGISTER 19-2: LCDPS: LCD PHASE REGISTER

R/W-0/0

WFT

R/W-0/0

BIASMD

R-0/0

LCDA

R-0/0

WA

R/W-0/0

R/W-1/1

bit 0

LP<3:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

C = Only clearable bit

bit 7

bit 6

WFT: Waveform Type bit

1= Type-B phase changes on each frame boundary

0= Type-A phase changes within each common type

BIASMD: Bias Mode Select bit

When LMUX<1:0> = 00:

0= Static Bias mode (do not set this bit to ‘1’)

When LMUX<1:0> = 01:

1= 1/2 Bias mode

0= 1/3 Bias mode

When LMUX<1:0> = 10:

1= 1/2 Bias mode

0= 1/3 Bias mode

When LMUX<1:0> = 11:

0= 1/3 Bias mode (do not set this bit to ‘1’)

LCDA: LCD Active Status bit

bit 5

1= LCD driver module is active

0= LCD driver module is inactive

bit 4

WA: LCD Write Allow Status bit

1= Writing to the LCDDATAn registers is allowed

0= Writing to the LCDDATAn registers is not allowed

bit 3-0

LP<3:0>: LCD Prescaler Selection bits

1111= 1:16

1110= 1:15

1101= 1:14

1100= 1:13

1011= 1:12

1010= 1:11

1001= 1:10

1000= 1:9

0111= 1:8

0110= 1:7

0101= 1:6

0100= 1:5

0011= 1:4

0010= 1:3

0001= 1:2

0000= 1:1

DS40001569D-page 174

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

REGISTER 19-3: LCDREF: LCD REFERENCE VOLTAGE CONTROL REGISTER

R/W-0/0

LCDIRE

U-0

—

R/W-0/0

LCDIRI

U-0

—

R/W-0/0

U-0

—

VLCD3PE

VLCD2PE

VLCD1PE

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

C = Only clearable bit

bit 7

LCDIRE: LCD Internal Reference Enable bit

1= Internal LCD Reference is enabled and connected to the Internal Contrast Control circuit

0= Internal LCD Reference is disabled

bit 6

bit 5

Unimplemented: Read as ‘0’

LCDIRI: LCD Internal Reference Ladder Idle Enable bit

Allows the Internal FVR buffer to shut down when the LCD Reference Ladder is in power mode ‘B’

1= When the LCD Reference Ladder is in power mode ‘B’, the LCD Internal FVR buffer is disabled.

0= The LCD Internal FVR Buffer ignores the LCD Reference Ladder Power mode.

bit 4

bit 3

Unimplemented: Read as ‘0’

VLCD3PE: VLCD3 Pin Enable bit

1= The VLCD3 pin is connected to the internal bias voltage LCDBIAS3⁽¹⁾

0= The VLCD3 pin is not connected

bit 2

bit 1

bit 0

VLCD2PE: VLCD2 Pin Enable bit

1= The VLCD2 pin is connected to the internal bias voltage LCDBIAS2⁽¹⁾

0= The VLCD2 pin is not connected

VLCD1PE: VLCD1 Pin Enable bit

1= The VLCD1 pin is connected to the internal bias voltage LCDBIAS1⁽¹⁾

0= The VLCD1 pin is not connected

Unimplemented: Read as ‘0’

Note 1: Normal pin controls of TRISx and ANSELx are unaffected.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 175

PIC16LF1904/6/7

REGISTER 19-4: LCDCST: LCD CONTRAST CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

bit 0

LCDCST<2:0>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

C = Only clearable bit

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

LCDCST<2:0>: LCD Contrast Control bits

Selects the resistance of the LCD contrast control resistor ladder

Bit Value = Resistor ladder

000= Minimum Resistance (Maximum contrast). Resistor ladder is shorted.

001= Resistor ladder is at 1/7th of maximum resistance

010= Resistor ladder is at 2/7th of maximum resistance

011= Resistor ladder is at 3/7th of maximum resistance

100= Resistor ladder is at 4/7th of maximum resistance

101= Resistor ladder is at 5/7th of maximum resistance

110= Resistor ladder is at 6/7th of maximum resistance

111= Resistor ladder is at maximum resistance (Minimum contrast).

DS40001569D-page 176

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PIC16LF1904/6/7

REGISTER 19-5: LCDSEn: LCD SEGMENT ENABLE REGISTERS

R/W-0/0

SEn

R/W-0/0

SEn

R/W-0/0

SEn

R/W-0/0

SEn

R/W-0/0

SEn

R/W-0/0

SEn

R/W-0/0

SEn

R/W-0/0

SEn

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

SEn: Segment Enable bits

1= Segment function of the pin is enabled

0= I/O function of the pin is enabled

REGISTER 19-6: LCDDATAn: LCD DATA REGISTERS

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy

R/W-x/u

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

SEGx-COMy: Pixel On bits

1= Pixel on (dark)

0= Pixel off (clear)

 2011-2016 Microchip Technology Inc.

DS40001569D-page 177

PIC16LF1904/6/7

Using bits CS<1:0> of the LCDCON register can select

any of these clock sources.

19.2 LCD Clock Source Selection

The LCD module has three possible clock sources:

19.2.1

LCD PRESCALER

• FOSC/256

• T1OSC

A 4-bit counter is available as a prescaler for the LCD

clock. The prescaler is not directly readable or writable;

its value is set by the LP<3:0> bits of the LCDPS register,

which determine the prescaler assignment and prescale

ratio.

• LFINTOSC

The first clock source is the system clock divided by

256 (FOSC/256). This divider ratio is chosen to provide

about 1 kHz output when the system clock is 8 MHz.

The divider is not programmable. Instead, the LCD

prescaler bits LP<3:0> of the LCDPS register are used

to set the LCD frame clock rate.

The prescale values are selectable from 1:1 through

1:16.

The second clock source is the T1OSC. This also gives

about 1 kHz when a 32.768 kHz crystal is used with the

Timer1 oscillator. To use the Timer1 oscillator as a

clock source, the T1OSCEN bit of the T1CON register

should be set.

The third clock source is the 31 kHz LFINTOSC, which

provides approximately 1 kHz output.

The second and third clock sources may be used to

continue running the LCD while the processor is in

Sleep.

FIGURE 19-2:

LCD CLOCK GENERATION

FOSC

÷256

To Ladder

Power Control

Static

÷4

÷2

T1OSC 32 kHz

Crystal Osc.

Segment

÷1, 2, 3, 4

Ring Counter

4-bit Prog

Prescaler

÷ 32

Counter

1/2

Clock

1/3,

1/4

LFINTOSC

Nominal = 31 kHz

LP<3:0>

CS<1:0>

LMUX<1:0>

DS40001569D-page 178

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 19-2: LCD BIAS VOLTAGES

19.3 LCD Bias Voltage Generation

Static Bias

1/2 Bias

1/3 Bias

The LCD module can be configured for one of three

bias types:

LCD Bias 0

LCD Bias 1

LCD Bias 2

LCD Bias 3

VSS

—

VSS

1/2 VDD

VLCD3

1/3 VDD

2/3 VDD

VLCD3

• Static Bias (2 voltage levels: VSS and VLCD)

—

• 1/2 Bias (3 voltage levels: VSS, 1/2 VLCD and

VLCD)

VLCD3

• 1/3 Bias (4 voltage levels: VSS, 1/3 VLCD,

2/3 VLCD and VLCD)

So that the user is not forced to place external compo-

nents and use up to three pins for bias voltage generation,

internal contrast control and an internal reference ladder

are provided internally to the PIC16LF1904/6/7. Both of

these features may be used in conjunction with the exter-

nal VLCD<3:1> pins, to provide maximum flexibility. Refer

to Figure 19-3.

FIGURE 19-3:

LCD BIAS VOLTAGE GENERATION BLOCK DIAGRAM

LCDIRE

LCDA

VDD

Power Mode Switching

(LRLAP or LRLBP)

A

B

2

LCDCST<2:0>

VLCD3PE

VLCD2PE

VLCD1PE

LCDA

VLCD3

VLCD2

VLCD1

lcdbias3

lcdbias2

BIASMD

lcdbias1

lcdbias0

 2011-2016 Microchip Technology Inc.

DS40001569D-page 179

PIC16LF1904/6/7

19.4.2

POWER MODES

19.4 LCD Bias Internal Reference

Ladder

The internal reference ladder may be operated in one of

three power modes. This allows the user to trade off LCD

contrast for power in the specific application. The larger

the LCD glass, the more capacitance is present on a

physical LCD segment, requiring more current to

maintain the same contrast level.

The internal reference ladder can be used to divide the

LCD bias voltage two or three equally spaced voltages

that will be supplied to the LCD segment pins. To create

this, the reference ladder consists of three matched

resistors. Refer to Figure 19-3.

Three different power modes are available, LP, MP and

HP. The internal reference ladder can also be turned off

for applications that wish to provide an external ladder

or to minimize power consumption. Disabling the

internal reference ladder results in all of the ladders

being disconnected, allowing external voltages to be

supplied.

19.4.1

BIAS MODE INTERACTION

When in 1/2 Bias mode (BIASMD = 1), then the middle

resistor of the ladder is shorted out so that only two

voltages are generated. The current consumption of the

ladder is higher in this mode, with the one resistor

removed.

Whenever the LCD module is inactive (LCDA = 0), the

internal reference ladder will be turned off.

TABLE 19-3:

LCD INTERNAL LADDER

POWER MODES (1/3 BIAS)

Power

Mode

Nominal Resistance of

Entire Ladder

Nominal

IDD

Low

3 Mohm

300 kohm

30 kohm

1 µA

10 µA

100 µA

Medium

High

DS40001569D-page 180

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

The LCDRL register allows switching between two

power modes, designated ‘A’ and ‘B’. ‘A’ Power mode

is active for a programmable time, beginning at the

time when the LCD segments transition. ‘B’ Power

mode is the remaining time before the segments or

commons change again. The LRLAT<2:0> bits select

how long, if any, that the ‘A’ Power mode is active.

Refer to Figure 19-4.

19.4.3

AUTOMATIC POWER MODE

SWITCHING

As an LCD segment is electrically only a capacitor, cur-

rent is drawn only during the interval where the voltage

is switching. To minimize total device current, the LCD

internal reference ladder can be operated in a different

power mode for the transition portion of the duration.

This is controlled by the LCDRL Register

(Register 19-7).

To implement this, the 5-bit prescaler used to divide

the 32 kHz clock down to the LCD controller’s 1 kHz

base rate is used to select the power mode.

FIGURE 19-4:

LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM –

TYPE A

Single Segment Time

32 kHz Clock

Ladder Power

Control

‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07

‘H0E ‘H0F ‘H00 ‘H01

Segment Clock

LRLAT<2:0>

‘H3

Segment Data

LRLAT<2:0>

Power Mode

COM0

Power Mode A

Power Mode B

Mode A

V₁

V₀

V₁

V₀

SEG0

V₁

V₀

COM0-SEG0

-V₁

 2011-2016 Microchip Technology Inc.

DS40001569D-page 181

PIC16LF1904/6/7

REGISTER 19-7: LCDRL: LCD REFERENCE LADDER CONTROL REGISTERS

R/W-0/0

U-0

—

R/W-0/0

LRLAP<1:0>

LRLBP<1:0>

LRLAT<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-4

LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits

During Time interval A (Refer to Figure 19-4):

00= Internal LCD Reference Ladder is powered down and unconnected

01= Internal LCD Reference Ladder is powered in low-power mode

10= Internal LCD Reference Ladder is powered in medium-power mode

11= Internal LCD Reference Ladder is powered in high-power mode

LRLBP<1:0>: LCD Reference Ladder B Time Power Control bits

During Time interval B (Refer to Figure 19-4):

00= Internal LCD Reference Ladder is powered down and unconnected

01= Internal LCD Reference Ladder is powered in low-power mode

10= Internal LCD Reference Ladder is powered in medium-power mode

11= Internal LCD Reference Ladder is powered in high-power mode

bit 3

Unimplemented: Read as ‘0’

bit 2-0

LRLAT<2:0>: LCD Reference Ladder A Time Interval Control bits

Sets the number of 32 kHz clocks that the A Time interval power mode is active

For type A waveforms (WFT = 0):

000= Internal LCD Reference Ladder is always in ‘B’ Power mode

001= Internal LCD Reference Ladder is in ‘A’ Power mode for 1 clock and ‘B’ Power mode for 15 clocks

010= Internal LCD Reference Ladder is in ‘A’ Power mode for 2 clocks and ‘B’ Power mode for 14 clocks

011= Internal LCD Reference Ladder is in ‘A’ Power mode for 3 clocks and ‘B’ Power mode for 13 clocks

100= Internal LCD Reference Ladder is in ‘A’ Power mode for 4 clocks and ‘B’ Power mode for 12 clocks

101= Internal LCD Reference Ladder is in ‘A’ Power mode for 5 clocks and ‘B’ Power mode for 11 clocks

110= Internal LCD Reference Ladder is in ‘A’ Power mode for 6 clocks and ‘B’ Power mode for 10 clocks

111= Internal LCD Reference Ladder is in ‘A’ Power mode for 7 clocks and ‘B’ Power mode for 9 clocks

For type B waveforms (WFT = 1):

000= Internal LCD Reference Ladder is always in ‘B’ Power mode.

001= Internal LCD Reference Ladder is in ‘A’ Power mode for 1 clock and ‘B’ Power mode for 31 clocks

010= Internal LCD Reference Ladder is in ‘A’ Power mode for 2 clocks and ‘B’ Power mode for 30 clocks

011= Internal LCD Reference Ladder is in ‘A’ Power mode for 3 clocks and ‘B’ Power mode for 29 clocks

100= Internal LCD Reference Ladder is in ‘A’ Power mode for 4 clocks and ‘B’ Power mode for 28 clocks

101= Internal LCD Reference Ladder is in ‘A’ Power mode for 5 clocks and ‘B’ Power mode for 27 clocks

110= Internal LCD Reference Ladder is in ‘A’ Power mode for 6 clocks and ‘B’ Power mode for 26 clocks

111= Internal LCD Reference Ladder is in ‘A’ Power mode for 7 clocks and ‘B’ Power mode for 25 clocks

DS40001569D-page 184

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The contrast control circuit is used to decrease the

output voltage of the signal source by a total of

approximately 10%, when LCDCST = 111.

19.4.4

CONTRAST CONTROL

The LCD contrast control circuit consists of a

seven-tap resistor ladder, controlled by the LCDCST

bits. Refer to Figure 19-7.

Whenever the LCD module is inactive (LCDA = 0), the

contrast control ladder will be turned off (open).

FIGURE 19-7:

INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM

7 Stages

VDD

R

Analog

MUX

7

0

To top of

Reference Ladder

LCDCST<2:0>

3

Internal Reference

INTERNAL REFERENCE

Contrast control

19.4.5

19.4.6

VLCD<3:1> PINS

Under firmware control, an internal reference for the

LCD bias voltages can be enabled. When enabled, the

source of this voltage can be VDD. When no internal

reference is selected, the LCD contrast control circuit is

disabled and LCD bias must be provided externally.

The VLCD<3:1> pins provide the ability for an external

LCD bias network to be used instead of the internal lad-

der. Use of the VLCD<3:1> pins does not prevent use

of the internal ladder. Each VLCD pin has an indepen-

dent control in the LCDREF register (Register 19-3),

allowing access to any or all of the LCD Bias signals.

This architecture allows for maximum flexibility in differ-

ent applications

Whenever the LCD module is inactive (LCDA = 0), the

internal reference will be turned off.

When the internal reference is enabled and the Fixed

Voltage Reference is selected, the LCDIRI bit can be

used to minimize power consumption by tying into the

LCD reference ladder automatic power mode switching.

When LCDIRI = 1 and the LCD reference ladder is in

Power mode ‘B’, the LCD internal FVR buffer is

disabled.

For example, the VLCD<3:1> pins may be used to add

capacitors to the internal reference ladder, increasing

the drive capacity.

For applications where the internal contrast control is

insufficient, the firmware can choose to only enable the

VLCD3 pin, allowing an external contrast control circuit

to use the internal reference divider.

Note:

The LCD module automatically turns on the

Fixed Voltage Reference when needed.

 2011-2016 Microchip Technology Inc.

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TABLE 19-5: FRAME FREQUENCY

19.5 LCD Multiplex Types

FORMULAS

The LCD driver module can be configured into one of

four multiplex types:

(2)

Multiplex

Frame Frequency

=

Static

1/2

Clock source⁽¹⁾/(4 x (LCD Prescaler) x 32 x 1))

Clock source⁽¹⁾/(2 x (LCD Prescaler) x 32 x 2))

Clock source⁽¹⁾/(1 x (LCD Prescaler) x 32 x 3))

Clock source⁽¹⁾/(1 x (LCD Prescaler) x 32 x 4))

• Static (only COM0 is used)

• 1/2 multiplex (COM<1:0> are used)

• 1/3 multiplex (COM<2:0> are used)

• 1/4 multiplex (COM<3:0> are used)

1/3

1/4

Note 1: Clock source is FOSC/256, T1OSC or LFIN-

The LMUX<1:0> bit setting of the LCDCON register

decides which of the LCD common pins are used (see

Table 19-4 for details).

TOSC.

2: See Figure 19-2.

If the pin is a digital I/O, the corresponding TRIS bit

controls the data direction. If the pin is a COM drive,

then the TRIS setting of that pin is overridden.

TABLE 19-6: APPROXIMATE FRAME

FREQUENCY (IN Hz) USING

FOSC @ 8 MHz, TIMER1 @

32.768 kHz OR LFINTOSC

TABLE 19-4: COMMON PIN USAGE

LP<3:0>

Static

1/2

1/3

1/4

LMUX

<1:0>

Multiplex

COM3

COM2

COM1

2

3

4

5

6

7

122

81

61

49

41

35

122

81

61

49

41

35

162

108

81

122

81

61

49

41

35

Static

1/2

00

01

10

11

Unused Unused Unused Active

Unused Unused Active

Active

1/3

Unused Active

Active Active

Active

65

1/4

54

47

19.6 Segment Enables

The LCDSEn registers are used to select the pin

function for each segment pin. The selection allows

each pin to operate as either an LCD segment driver or

as one of the pin’s alternate functions. To configure the

pin as a segment pin, the corresponding bits in the

LCDSEn registers must be set to ‘1’.

If the pin is a digital I/O, the corresponding TRIS bit

controls the data direction. Any bit set in the LCDSEn

registers overrides any bit settings in the corresponding

TRIS register.

Note:

On a Power-on Reset, these pins are

configured as normal I/O, not LCD pins.

19.7 Pixel Control

The LCDDATAx registers contain bits which define the

state of each pixel. Each bit defines one unique pixel.

Register 19-6 shows the correlation of each bit in the

LCDDATAx registers to the respective common and

segment signals.

Any LCD pixel location not being used for display can

be used as general purpose RAM.

19.8 LCD Frame Frequency

The rate at which the COM and SEG outputs change is

called the LCD frame frequency.

DS40001569D-page 186

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The LCDs can be driven by two types of waveform:

Type-A and Type-B. In Type-A waveform, the phase

changes within each common type, whereas in Type-B

waveform, the phase changes on each frame

boundary. Thus, Type-A waveform maintains 0 VDC

over a single frame, whereas Type-B waveform takes

two frames.

19.9 LCD Waveform Generation

LCD waveforms are generated so that the net AC

voltage across the dark pixel should be maximized and

the net AC voltage across the clear pixel should be

minimized. The net DC voltage across any pixel should

be zero.

The COM signal represents the time slice for each

common, while the SEG contains the pixel data.

Note 1: If Sleep has to be executed with LCD

Sleep disabled (LCDCON<SLPEN> is

‘1’), then care must be taken to execute

Sleep only when VDC on all the pixels is

‘0’.

The pixel signal (COM-SEG) will have no DC

component and it can take only one of the two RMS

values. The higher RMS value will create a dark pixel

and a lower RMS value will create a clear pixel.

2: When the LCD clock source is FOSC/256,

if Sleep is executed, irrespective of the

LCDCON<SLPEN> setting, the LCD

immediately goes into Sleep. Thus, take

care to see that VDC on all pixels is ‘0’

when Sleep is executed.

As the number of commons increases, the delta

between the two RMS values decreases. The delta

represents the maximum contrast that the display can

have.

Figure 19-8 through Figure 19-18 provide waveforms

for static, half-multiplex, 1/3-multiplex and 1/4-multiplex

drives for Type-A and Type-B waveforms.

FIGURE 19-8:

TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE

V₁

COM0 pin

SEG0 pin

SEG1 pin

V₀

V₁

COM0

V₀

V₁

V₀

V₁

V₀

COM0-SEG0

segment voltage

(active)

-V₁

COM0-SEG1

segment voltage

(inactive)

V₀

1 Frame

 2011-2016 Microchip Technology Inc.

DS40001569D-page 187

PIC16LF1904/6/7

FIGURE 19-9:

TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE

V₂

V₁

V₀

COM0 pin

COM1 pin

COM1

V₂

V₁

V₀

COM0

V₂

V₁

V₀

SEG0 pin

SEG1 pin

V₂

V₁

V₀

V₂

V₁

V₀

COM0-SEG0

segment voltage

(active)

-V₁

-V₂

V₂

V₁

V₀

COM0-SEG1

segment voltage

(inactive)

-V₁

-V₂

1 Frame

1 Segment Time

Note:

1 Frame = 2 single segment times.

DS40001569D-page 188

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 19-10:

TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE

V₂

V₁

V₀

COM1

COM0 pin

COM0

V₂

V₁

V₀

COM1 pin

SEG0 pin

V₂

V₁

V₀

V₂

V₁

V₀

SEG1 pin

V₂

V₁

V₀

COM0-SEG0

segment voltage

(active)

-V₁

-V₂

V₂

V₁

V₀

COM0-SEG1

segment voltage

(inactive)

-V₁

-V₂

2 Frames

1 Segment Time

Note:

1 Frame = 2 single segment times.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 189

PIC16LF1904/6/7

FIGURE 19-11:

TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

COM1

COM0 pin

COM0

COM1 pin

SEG0 pin

SEG1 pin

V₃

V₂

V₁

V₀

COM0-SEG0

segment voltage

(active)

-V₁

-V₂

-V₃

V₃

V₂

V₁

V₀

COM0-SEG1

segment voltage

(inactive)

-V₁

-V₂

-V₃

1 Frame

1 Segment Time

Note:

1 Frame = 2 single segment times.

DS40001569D-page 190

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 19-12:

TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

COM1

COM0 pin

COM0

COM1 pin

SEG0 pin

SEG1 pin

V₃

V₂

V₁

V₀

COM0-SEG0

segment voltage

(active)

-V₁

-V₂

-V₃

V₃

V₂

V₁

V₀

COM0-SEG1

segment voltage

(inactive)

-V₁

-V₂

-V₃

2 Frames

1 Segment Time

Note:

1 Frame = 2 single segment times.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 191

PIC16LF1904/6/7

FIGURE 19-13:

TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE

V₂

V₁

V₀

COM0 pin

V₂

V₁

V₀

COM2

COM1 pin

COM2 pin

COM1

COM0

V₂

V₁

V₀

V₂

V₁

V₀

SEG0 and

SEG2 pins

V₂

V₁

V₀

SEG1 pin

V₂

V₁

V₀

COM0-SEG0

segment voltage

(inactive)

-V₁

-V₂

V₂

V₁

V₀

COM0-SEG1

segment voltage

(active)

-V₁

-V₂

1 Frame

1 Segment Time

Note:

1 Frame = 2 single segment times.

DS40001569D-page 192

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 19-14:

TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE

V₂

V₁

V₀

COM0 pin

COM1 pin

COM2 pin

SEG0 pin

SEG1 pin

COM2

V₂

V₁

V₀

COM1

COM0

V₂

V₁

V₀

V₂

V₁

V₀

V₂

V₁

V₀

V₂

V₁

V₀

COM0-SEG0

segment voltage

(inactive)

-V₁

-V₂

V₂

V₁

V₀

COM0-SEG1

segment voltage

(active)

-V₁

-V₂

2 Frames

1 Segment Time

Note:

1 Frame = 2 single segment times.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 193

PIC16LF1904/6/7

FIGURE 19-15:

TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

-V₁

-V₂

-V₃

V₃

V₂

V₁

V₀

-V₁

-V₂

-V₃

COM0 pin

COM1 pin

COM2 pin

COM2

COM1

COM0

SEG0 and

SEG2 pins

SEG1 pin

COM0-SEG0

segment voltage

(inactive)

COM0-SEG1

segment voltage

(active)

1 Frame

1 Segment Time

Note:

1 Frame = 2 single segment times.

DS40001569D-page 194

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 19-16:

TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

-V₁

-V₂

-V₃

V₃

V₂

V₁

V₀

-V₁

-V₂

-V₃

COM0 pin

COM1 pin

COM2 pin

SEG0 pin

SEG1 pin

COM2

COM1

COM0

COM0-SEG0

segment voltage

(inactive)

COM0-SEG1

segment voltage

(active)

2 Frames

1 Segment Time

Note:

1 Frame = 2 single segment times.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 195

PIC16LF1904/6/7

FIGURE 19-17:

TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE

COM3

V

3

2

1

0

COM0 pin

COM1 pin

COM2

V

3

2

1

0

COM1

COM0

V

3

2

1

0

COM2 pin

COM3 pin

SEG0 pin

SEG1 pin

V

3

2

1

0

V

3

2

1

0

V

3

2

1

0

V

-V

3

2

1

0

COM0-SEG0

segment voltage

(active)

1

2

3

V

-V

3

2

1

0

COM0-SEG1

segment voltage

(inactive)

1

2

3

1 Frame

1 Segment Time

Note:

1 Frame = 2 single segment times.

DS40001569D-page 196

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 19-18:

COM3

TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE

V

3

2

1

0

COM0 pin

COM1 pin

COM2

V

3

2

1

0

COM1

COM0

V

3

2

1

0

COM2 pin

COM3 pin

SEG0 pin

SEG1 pin

V

3

2

1

0

V

3

2

1

0

V

3

2

1

0

V

-V

3

2

1

0

COM0-SEG0

segment voltage

(active)

1

2

3

V

-V

3

2

1

0

COM0-SEG1

segment voltage

(inactive)

1

2

3

2 Frames

1 Segment Time

Note:

1 Frame = 2 single segment times.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 197

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19.10 LCD Interrupts

The LCD module provides an interrupt in two cases. An

interrupt when the LCD controller goes from active to

inactive controller. An interrupt also provides unframe

boundaries for Type B waveform. The LCD timing gen-

eration provides an interrupt that defines the LCD

frame timing.

19.10.1 LCD INTERRUPT ON MODULE

SHUTDOWN

An LCD interrupt is generated when the module com-

pletes shutting down (LCDA goes from ‘1’ to ‘0’).

19.10.2 LCD FRAME INTERRUPTS

A new frame is defined to begin at the leading edge of

the COM0 common signal. The interrupt will be set

immediately after the LCD controller completes access-

ing all pixel data required for a frame. This will occur at

a fixed interval before the frame boundary (TFINT), as

shown in Figure 19-19. The LCD controller will begin to

access data for the next frame within the interval from

the interrupt to when the controller begins to access

data after the interrupt (TFWR). New data must be writ-

ten within TFWR, as this is when the LCD controller will

begin to access the data for the next frame.

When the LCD driver is running with Type-B waveforms

and the LMUX<1:0> bits are not equal to ‘00’ (static

drive), there are some additional issues that must be

addressed. Since the DC voltage on the pixel takes two

frames to maintain zero volts, the pixel data must not

change between subsequent frames. If the pixel data

were allowed to change, the waveform for the odd

frames would not necessarily be the complement of the

waveform generated in the even frames and a DC

component would be introduced into the panel.

Therefore, when using Type-B waveforms, the user

must synchronize the LCD pixel updates to occur within

a subframe after the frame interrupt.

To correctly sequence writing while in Type-B, the

interrupt will only occur on complete phase intervals. If

the user attempts to write when the write is disabled,

the WERR bit of the LCDCON register is set and the

write does not occur.

Note:

The LCD frame interrupt is not generated

when the Type-A waveform is selected

and when the Type-B with no multiplex

(static) is selected.

DS40001569D-page 198

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FIGURE 19-19:

WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE

(EXAMPLE – TYPE-B, NON-STATIC)

LCD

Interrupt

Occurs

Controller Accesses

Next Frame Data

V

3

2

1

0

COM0

COM1

V

3

2

1

0

V

3

2

1

0

COM2

COM3

V

3

2

1

0

2 Frames

Frame

TFINT

TFWR

Frame

Boundary

Frame

Boundary

TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2

TFINT = (TFWR/2 – (2 TCY + 40 ns))  minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns)

(TFWR/2 – (1 TCY + 40 ns))  maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns)

 2011-2016 Microchip Technology Inc.

DS40001569D-page 199

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Table 19-7 shows the status of the LCD module during

a Sleep while using each of the three available clock

sources.

19.11 Operation During Sleep

The LCD module can operate during Sleep. The

selection is controlled by bit SLPEN of the LCDCON

register. Setting the SLPEN bit allows the LCD module

to go to Sleep. Clearing the SLPEN bit allows the

module to continue to operate during Sleep.

Note:

When the LCDEN bit is cleared, the LCD

module will be disabled at the completion

of frame. At this time, the port pins will

revert to digital functionality. To minimize

power consumption due to floating digital

inputs, the LCD pins should be driven low

using the PORT and TRIS registers.

If a SLEEPinstruction is executed and SLPEN = 1, the

LCD module will cease all functions and go into a very

low-current Consumption mode. The module will stop

operation immediately and drive the minimum LCD

voltage on both segment and common lines.

Figure 19-20 shows this operation.

If a SLEEPinstruction is executed and SLPEN = 0, the

module will continue to display the current contents of

the LCDDATA registers. To allow the module to

continue operation while in Sleep, the clock source

must be either the LFINTOSC or T1OSC external

oscillator. While in Sleep, the LCD data cannot be

changed. The LCD module current consumption will

not decrease in this mode; however, the overall

consumption of the device will be lower due to shut

down of the core and other peripheral functions.

The LCD module can be configured to operate during

Sleep. The selection is controlled by bit SLPEN of the

LCDCON register. Clearing SLPEN and correctly con-

figuring the LCD module clock will allow the LCD mod-

ule to operate during Sleep. Setting SLPEN and

correctly executing the LCD module shutdown will dis-

able the LCD module during Sleep and save power.

If a SLEEPinstruction is executed and SLPEN = 1, the

LCD module will immediately cease all functions, drive

the outputs to Vss and go into a very low-current mode.

The SLEEP instruction should only be executed after

the LCD module has been disabled and the current

cycle completed, thus ensuring that there are no DC

voltages on the glass. To disable the LCD module,

clear the LCDEN bit. The LCD module will complete the

disabling process after the current frame, clear the

LCDA bit and optionally cause an interrupt.

Table 19-7 shows the status of the LCD module during

Sleep while using each of the three available clock

sources:

TABLE 19-7: LCD MODULE STATUS

DURING SLEEP

Operational

During Sleep

Clock Source

T1OSC

SLPEN

0

1

0

1

0

1

Yes

No

Yes

No

The steps required to properly enter Sleep with the

LCD disabled are:

• Clear LCDEN

LFINTOSC

FOSC/4

• Wait for LCDA = 0either by polling or by interrupt

• Execute SLEEP

If SLPEN = 0 and SLEEP is executed while the LCD

module clock source is FOSC/4, then the LCD module

will halt with the pin driving the last LCD voltage pat-

tern. Prolonged exposure to a fixed LCD voltage pat-

tern will cause damage to the LCD glass. To prevent

LCD glass damage, either perform the proper LCD

module shutdown prior to Sleep, or change the LCD

module clock to allow the LCD module to continue

operation during Sleep.

Note:

The LFINTOSC or external T1OSC

oscillator must be used to operate the

LCD module during Sleep.

If LCD interrupts are being generated (Type-B wave-

form with a Multiplex mode not static) and LCDIE = 1,

the device will awaken from Sleep on the next frame

boundary.

If a SLEEPinstruction is executed and SLPEN = 0and

the LCD module clock is either T1OSC or LFINTOSC,

the module will continue to display the current contents

of the LCDDATA registers. While in Sleep, the LCD

data cannot be changed. If the LCDIE bit is set, the

device will wake from Sleep on the next LCD frame

boundary. The LCD module current consumption will

not decrease in this mode; however, the overall device

power consumption will be lower due to the shutdown

of the CPU and other peripherals.

DS40001569D-page 200

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FIGURE 19-20:

SLEEP ENTRY/EXIT WHEN SLPEN = 1

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

COM0

COM1

COM2

SEG0

2 Frames

Wake-up

SLEEPInstruction Execution

 2011-2016 Microchip Technology Inc.

DS40001569D-page 201

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19.12 Configuring the LCD Module

19.14 LCD Current Consumption

The following is the sequence of steps to configure the

LCD module.

When using the LCD module the current consumption

consists of the following three factors:

1. Select the frame clock prescale using bits

LP<3:0> of the LCDPS register.

• Oscillator Selection

• LCD Bias Source

2. Configure the appropriate pins to function as

segment drivers using the LCDSEn registers.

• Capacitance of the LCD segments

The current consumption of just the LCD module can

be considered negligible compared to these other

factors.

3. Configure the LCD module for the following

using the LCDCON register:

- Multiplex and Bias mode, bits LMUX<1:0>

- Timing source, bits CS<1:0>

- Sleep mode, bit SLPEN

19.14.1 OSCILLATOR SELECTION

The current consumed by the clock source selected

must be considered when using the LCD module. See

Section 22.0 “Electrical Specifications” for oscillator

current consumption information.

4. Write initial values to pixel data registers, LCD-

DATA0 through LCDDATA21.

5. Clear LCD Interrupt Flag, LCDIF bit of the PIR2

register and if desired, enable the interrupt by

setting bit LCDIE of the PIE2 register.

19.14.2 LCD BIAS SOURCE

The LCD bias source, internal or external, can contrib-

ute significantly to the current consumption. Use the

highest possible resistor values while maintaining

contrast to minimize current.

6. Configure bias voltages by setting the LCDRL,

LCDREF and the associated ANSELx

registers as needed.

7. Enable the LCD module by setting bit LCDEN of

the LCDCON register.

19.14.3 CAPACITANCE OF THE LCD

SEGMENTS

19.13 Disabling the LCD Module

The LCD segments which can be modeled as capaci-

tors which must be both charged and discharged every

frame. The size of the LCD segment and its technology

determines the segment’s capacitance.

To disable the LCD module, write all ‘0’s to the

LCDCON register.

DS40001569D-page 202

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 19-8: SUMMARY OF REGISTERS ASSOCIATED WITH LCD OPERATION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

LCDEN

—

PEIE

SLPEN

—

TMR0IE

WERR

—

INTE

—

IOCIE

CS1

—

TMR0IF

CS0

INTF

IOCIF

65

LCDCON

LCDCST

LMUX<1:0>

173

176

177

—

LCDCST<2:0>

LCDDATA0

SEG7

COM0

SEG6

COM0

SEG5

COM0

SEG4

COM0

SEG3

COM0

SEG2

COM0

SEG1

COM0

SEG0

COM0

LCDDATA1

LCDDATA2⁽¹⁾

LCDDATA3

LCDDATA4

LCDDATA5⁽¹⁾

LCDDATA6

LCDDATA7

LCDDATA8⁽¹⁾

LCDDATA9

LCDDATA10

LCDDATA11⁽¹⁾

LCDDATA12

LCDDATA15

LCDDATA18

LCDDATA21

SEG15

COM0

SEG14

COM0

SEG13

COM0

SEG12

COM0

SEG11

COM0

SEG10

COM0

SEG9

COM0

SEG8

COM0

177

SEG23

COM0

SEG22

COM0

SEG21

COM0

SEG20

COM0

SEG19

COM0

SEG18

COM0

SEG17

COM0

SEG16

COM0

SEG7

COM1

SEG6

COM1

SEG5

COM1

SEG4

COM1

SEG3

COM1

SEG2

COM1

SEG1

COM1

SEG0

COM1

SEG15

COM1

SEG14

COM1

SEG13

COM1

SEG12

COM1

SEG11

COM1

SEG10

COM1

SEG9

COM1

SEG8

COM1

SEG23

COM1

SEG22

COM1

SEG21

COM1

SEG20

COM1

SEG19

COM1

SEG18

COM1

SEG17

COM1

SEG16

COM1

SEG7

COM2

SEG6

COM2

SEG5

COM2

SEG4

COM2

SEG3

COM2

SEG2

COM2

SEG1

COM2

SEG0

COM2

SEG15

COM2

SEG14

COM2

SEG13

COM2

SEG12

COM2

SEG11

COM2

SEG10

COM2

SEG9

COM2

SEG8

COM2

SEG23

COM2

SEG22

COM2

SEG21

COM2

SEG20

COM2

SEG19

COM2

SEG18

COM2

SEG17

COM2

SEG16

COM2

SEG7

COM3

SEG6

COM3

SEG5

COM3

SEG4

COM3

SEG3

COM3

SEG2

COM3

SEG1

COM3

SEG0

COM3

SEG15

COM3

SEG14

COM3

SEG13

COM3

SEG12

COM3

SEG11

COM3

SEG10

COM3

SEG9

COM3

SEG8

COM3

SEG23

COM3

SEG22

COM3

SEG20

COM3

SEG19

COM3

SEG18

COM3

SEG17

COM3

SEG16

COM3

SEG15

COM3

—

SEG28

COM0

SEG27

COM0

SEG26

COM0

SEG25

COM0

SEG24

COM0

SEG28

COM1

SEG27

COM1

SEG26

COM1

SEG25

COM1

SEG24

COM1

SEG28

COM2

SEG27

COM2

SEG26

COM2

SEG25

COM2

SEG24

COM2

SEG28

COM3

SEG27

COM3

SEG26

COM3

SEG25

COM3

SEG24

COM3

LCDPS

LCDREF

LCDRL

LCDSE0

LCDSE1

LCDSE2

LCDSE3

PIE2

WFT

BIASMD

—

LCDA

WA

—

LP<3:0>

VLCD3PE VLCD2PE VLCD1PE

174

175

184

177

67

LCDIRE

LCDIRI

—

LRLAP<1:0>

LRLBP<1:0>

—

LRLAT<2:0>

SE<7:0>

SE<15:8>

SE<23:16>

—

SE<28:24>

LCDIE

—

PIR2

LCDIF

69

T1CON

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1ON

139

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by the LCD module.

Note 1: PIC16LF1904/7 only.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 203

PIC16LF1904/6/7

20.3 Common Programming Interfaces

20.0 IN-CIRCUIT SERIAL

PROGRAMMING™ (ICSP™)

Connection to a target device is typically done through

an ICSP™ header. A commonly found connector on

development tools is the RJ-11 in the 6P6C (6-pin, 6

connector) configuration. See Figure 20-1.

ICSP™ programming allows customers to manufacture

circuit boards with unprogrammed devices. Programming

can be done after the assembly process, allowing the

device to be programmed with the most recent firmware

or a custom firmware. Five pins are needed for ICSP™

programming:

FIGURE 20-1:

ICD RJ-11 STYLE

CONNECTOR INTERFACE

• ICSPCLK

• ICSPDAT

• MCLR/VPP

• VDD

ICSPDAT

• VSS

NC

2 4 6

VDD

In Program/Verify mode the program memory, User IDs

and the Configuration Words are programmed through

serial communications. The ICSPDAT pin is

bidirectional I/O used for transferring the serial data and

the ICSPCLK pin is the clock input. For more

ICSPCLK

1 3

5

Target

PC Board

Bottom Side

a

VPP/MCLR

VSS

information

on

ICSP™

refer

to

the

“PIC16F193X/LF193X/PIC16F194X/LF194X/PIC16LF

190X Memory Programming Specification” (DS41397).

Pin Description*

1 = VPP/MCLR

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

20.1 High-Voltage Programming Entry

Mode

5 = ICSPCLK

The device is placed into High-Voltage Programming

Entry mode by holding the ICSPCLK and ICSPDAT

pins low then raising the voltage on MCLR/VPP to VIHH.

6 = No Connect

Another connector often found in use with the PICkit™

programmers is a standard 6-pin header with 0.1 inch

spacing. Refer to Figure 20-2.

20.2 Low-Voltage Programming Entry

Mode

For additional interface recommendations, refer to your

specific device programmer manual prior to PCB

design.

The Low-Voltage Programming Entry mode allows the

PIC^®Flash MCUs to be programmed using VDD only,

without high voltage. When the LVP bit of Configuration

Words is set to ‘1’, the low-voltage ICSP programming

entry is enabled. To disable the Low-Voltage ICSP

mode, the LVP bit must be programmed to ‘0’.

It is recommended that isolation devices be used to

separate the programming pins from other circuitry.

The type of isolation is highly dependent on the specific

application and may include devices such as resistors,

diodes, or even jumpers. See Figure 20-3 for more

information.

Entry into the Low-Voltage Programming Entry mode

requires the following steps:

1. MCLR is brought to VIL.

2.

A

32-bit key sequence is presented on

ICSPDAT, while clocking ICSPCLK.

Once the key sequence is complete, MCLR must be

held at VIL for as long as Program/Verify mode is to be

maintained.

If low-voltage programming is enabled (LVP = 1), the

MCLR Reset function is automatically enabled and

cannot be disabled. See Section 5.4 “MCLR” for more

information.

The LVP bit can only be reprogrammed to ‘0’ by using

the High-Voltage Programming mode.

DS40001569D-page 204

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 20-2:

PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE

Pin 1 Indicator

Pin Description*

1 = VPP/MCLR

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

1

2

3

4

5

6

5 = ICSPCLK

6 = No Connect

*

The 6-pin header (0.100" spacing) accepts 0.025" square pins.

FIGURE 20-3:

TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

External

Programming

Signals

Device to be

Programmed

VDD

VPP

VSS

MCLR/VPP

VSS

Data

ICSPDAT

ICSPCLK

Clock

*

To Normal Connections

Isolation devices (as required).

*

 2011-2016 Microchip Technology Inc.

DS40001569D-page 205

PIC16LF1904/6/7

21.1 Read-Modify-Write Operations

21.0 INSTRUCTION SET SUMMARY

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

Each PIC16 instruction is a 14-bit word containing the

operation code (opcode) and all required operands.

The opcodes are broken into three broad categories.

• Byte Oriented

• Bit Oriented

• Literal and Control

The literal and control category contains the most var-

ied instruction word format.

TABLE 21-1: OPCODE FIELD

DESCRIPTIONS

Table 21-3 lists the instructions recognized by the

MPASM^TMassembler.

Field

Description

All instructions are executed within a single instruction

cycle, with the following exceptions, which may take

two or three cycles:

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

Bit address within an 8-bit file register

Literal field, constant data or label

• Subroutine takes two cycles (CALL, CALLW)

• Returns from interrupts or subroutines take two

cycles (RETURN, RETLW, RETFIE)

k

x

Don’t care location (= 0or 1).

• Program branching takes two cycles (GOTO, BRA,

BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)

• One additional instruction cycle will be used when

any instruction references an indirect file register

and the file select register is pointing to program

memory.

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

One instruction cycle consists of 4 oscillator cycles; for

an oscillator frequency of 4 MHz, this gives a nominal

instruction execution rate of 1 MHz.

n

FSR or INDF number. (0-1)

mm

Pre-post increment-decrement mode

selection

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

TABLE 21-2: ABBREVIATION

DESCRIPTIONS

Field

Description

PC

TO

C

Program Counter

Time-out bit

Carry bit

DC

Z

Digit carry bit

Zero bit

PD

Power-down bit

DS40001569D-page 206

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 21-1:

GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

13

8

7

6

0

OPCODE

d

f (FILE #)

d = 0for destination W

d = 1for destination f

f = 7-bit file register address

Bit-oriented file register operations

13 10 9

7 6

0

OPCODE

b (BIT #)

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

General

13

8

7

0

OPCODE

k (literal)

k = 8-bit immediate value

CALLand GOTOinstructions only

13 11 10

OPCODE

0

k (literal)

k = 11-bit immediate value

MOVLPinstruction only

13

7

6

0

OPCODE

k (literal)

k = 7-bit immediate value

MOVLBinstruction only

13

5 4

OPCODE

k (literal)

k = 5-bit immediate value

BRAinstruction only

13

9

8

0

OPCODE

k (literal)

k = 9-bit immediate value

FSR Offset instructions

13

7

6

5

0

OPCODE

n

k (literal)

n = appropriate FSR

k = 6-bit immediate value

FSRIncrement instructions

13

3

2

n

1

OPCODE

m (mode)

n = appropriate FSR

m = 2-bit mode value

OPCODE only

13

0

OPCODE

 2011-2016 Microchip Technology Inc.

DS40001569D-page 207

PIC16LF1904/6/7

TABLE 21-3: PIC16LF1904/6/7 ENHANCED INSTRUCTION SET

14-Bit Opcode

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ADDWFC f, d

ANDWF

ASRF

LSLF

f, d

Add W and f

Add with Carry W and f

AND W with f

Arithmetic Right Shift

Logical Left Shift

Logical Right Shift

Clear f

Clear W

Complement f

Decrement f

Increment f

Inclusive OR W with f

Move f

Move W to f

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Subtract with Borrow W from f

Swap nibbles in f

Exclusive OR W with f

1

00 0111 dfff ffff C, DC, Z

11 1101 dfff ffff C, DC, Z

00 0101 dfff ffff Z

11 0111 dfff ffff C, Z

11 0101 dfff ffff C, Z

11 0110 dfff ffff C, Z

2

f, d

f

LSRF

CLRF

CLRW

COMF

DECF

INCF

IORWF

MOVF

MOVWF

RLF

RRF

SUBWF

SUBWFB f, d

SWAPF

XORWF

00 0001 lfff ffff

00 0001 0000 00xx

00 1001 dfff ffff

00 0011 dfff ffff

00 1010 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 1fff ffff

00 1101 dfff ffff

00 1100 dfff ffff

Z

–

f, d

f

f, d

2

C

00 0010 dfff ffff C, DC, Z

11 1011 dfff ffff C, DC, Z

00 1110 dfff ffff

f, d

00 0110 dfff ffff

Z

BYTE ORIENTED SKIP OPERATIONS

f, d

Decrement f, Skip if 0

Increment f, Skip if 0

1(2)

00

1011 dfff ffff

1111 dfff ffff

1, 2

DECFSZ

INCFSZ

BIT-ORIENTED FILE REGISTER OPERATIONS

f, b

Bit Clear f

Bit Set f

1

01

00bb bfff ffff

01bb bfff ffff

2

BCF

BSF

BIT-ORIENTED SKIP OPERATIONS

BTFSC

BTFSS

f, b

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

01

10bb bfff ffff

11bb bfff ffff

1, 2

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

MOVLB

MOVLP

MOVLW

SUBLW

XORLW

k

Add literal and W

AND literal with W

Inclusive OR literal with W

Move literal to BSR

Move literal to PCLATH

Move literal to W

1

11

00

11

1110 kkkk kkkk C, DC, Z

1001 kkkk kkkk

1000 kkkk kkkk

0000 001k kkkk

0001 1kkk kkkk

0000 kkkk kkkk

Z

Subtract W from literal

Exclusive OR literal with W

1100 kkkk kkkk C, DC, Z

1010 kkkk kkkk

Z

Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle

is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one

additional instruction cycle.

DS40001569D-page 208

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 21-3: PIC16LF1904/6/7 ENHANCED INSTRUCTION SET (CONTINUED)

14-Bit Opcode

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

CONTROL OPERATIONS

BRA

BRW

CALL

CALLW

GOTO

RETFIE

RETLW

RETURN

k

–

Relative Branch

Relative Branch with W

Call Subroutine

Call Subroutine with W

Go to address

Return from interrupt

Return with literal in W

Return from Subroutine

2

11

00

10

00

10

00

11

00

001k kkkk kkkk

0000 0000 1011

0kkk kkkk kkkk

0000 0000 1010

1kkk kkkk kkkk

0000 0000 1001

0100 kkkk kkkk

0000 0000 1000

k

–

k

–

INHERENT OPERATIONS

CLRWDT

NOP

OPTION

RESET

SLEEP

TRIS

–

f

Clear Watchdog Timer

No Operation

Load OPTION_REG register with W

Software device Reset

Go into Standby mode

Load TRIS register with W

1

00

0000 0110 0100 TO, PD

0000 0000 0000

0000 0110 0010

0000 0000 0001

0000 0110 0011 TO, PD

0000 0110 0fff

C-COMPILER OPTIMIZED

ADDFSR n, k

Add Literal k to FSRn

Move Indirect FSRn to W with pre/post inc/dec

modifier, mm

1

11 0001 0nkk kkkk

00 0000 0001 0nmm

MOVIW

n mm

Z

2, 3

k[n]

n mm

Move INDFn to W, Indexed Indirect.

Move W to Indirect FSRn with pre/post inc/dec

modifier, mm

1

11 1111 0nkk kkkk

00 0000 0001 1nmm

2

2, 3

MOVWI

k[n]

Move W to INDFn, Indexed Indirect.

1

11 1111 1nkk kkkk

2

Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle

is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require

one additional instruction cycle.

3: See Table in the MOVIW and MOVWI instruction descriptions.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 209

PIC16LF1904/6/7

21.2 Instruction Descriptions

ADDFSR

Add Literal to FSRn

ANDLW

AND literal with W

Syntax:

[ label ] ADDFSR FSRn, k

Syntax:

[ label ] ANDLW

0  k  255

k

Operands:

-32  k  31

n  [ 0, 1]

Operands:

Operation:

Status Affected:

Description:

(W) .AND. (k)  (W)

Operation:

FSR(n) + k  FSR(n)

Z

Status Affected:

Description:

None

The contents of W register are

AND’ed with the 8-bit literal ‘k’. The

result is placed in the W register.

The signed 6-bit literal ‘k’ is added to

the contents of the FSRnH:FSRnL

register pair.

FSRn is limited to the range 0000h -

FFFFh. Moving beyond these bounds

will cause the FSR to wrap-around.

ANDWF

AND W with f

ADDLW

Add literal and W

Syntax:

[ label ] ANDWF f,d

Syntax:

[ label ] ADDLW

0  k  255

k

Operands:

0  f  127

d 0,1

Operands:

Operation:

Status Affected:

Description:

(W) + k  (W)

C, DC, Z

Operation:

(W) .AND. (f)  (destination)

Status Affected:

Description:

Z

The contents of the W register are

added to the 8-bit literal ‘k’ and the

result is placed in the W register.

AND the W register with register ‘f’. If

‘d’ is ‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

ASRF

Arithmetic Right Shift

ADDWF

Add W and f

Syntax:

[ label ] ASRF f {,d}

Syntax:

[ label ] ADDWF f,d

Operands:

0  f  127

d [0,1]

Operands:

0  f  127

d 0,1

Operation:

(f<7>) dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Operation:

(W) + (f)  (destination)

Status Affected:

Description:

C, DC, Z

Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the result is

stored in the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. The MSb remains unchanged. If

‘d’ is ‘0’, the result is placed in W. If ‘d’

is ‘1’, the result is stored back in reg-

ister ‘f’.

ADDWFC

ADD W and CARRY bit to f

C

register f

Syntax:

[ label ] ADDWFC

f {,d}

Operands:

0  f  127

d [0,1]

Operation:

(W) + (f) + (C)  dest

Status Affected:

Description:

C, DC, Z

Add W, the Carry flag and data mem-

ory location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

DS40001569D-page 210

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

BTFSC

Bit Test f, Skip if Clear

BCF

Bit Clear f

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] BCF f,b

Operands:

0  f  127

0  b  7

Operands:

0  f  127

0  b  7

Operation:

skip if (f<b>) = 0

Operation:

0 (f<b>)

Status Affected:

Description:

None

Status Affected:

Description:

None

If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

Bit ‘b’ in register ‘f’ is cleared.

If bit ‘b’, in register ‘f’, is ‘0’, the next

instruction is discarded, and a NOPis

executed instead, making this a

2-cycle instruction.

BTFSS

Bit Test f, Skip if Set

BRA

Relative Branch

Syntax:

[ label ] BTFSS f,b

Syntax:

[ label ] BRA label

[ label ] BRA $+k

Operands:

0  f  127

0  b < 7

Operands:

-256  label - PC + 1  255

-256  k  255

Operation:

skip if (f<b>) = 1

Operation:

(PC) + 1 + k  PC

Status Affected:

Description:

None

Status Affected:

Description:

None

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

If bit ‘b’ is ‘1’, then the next

instruction is discarded and a NOPis

executed instead, making this a

2-cycle instruction.

Add the signed 9-bit literal ‘k’ to the

PC. Since the PC will have incre-

mented to fetch the next instruction,

the new address will be PC + 1 + k.

This instruction is a 2-cycle instruc-

tion. This branch has a limited range.

BRW

Relative Branch with W

Syntax:

[ label ] BRW

None

Operands:

Operation:

Status Affected:

Description:

(PC) + (W)  PC

None

Add the contents of W (unsigned) to

the PC. Since the PC will have incre-

mented to fetch the next instruction,

the new address will be PC + 1 + (W).

This instruction is a 2-cycle instruc-

tion.

BSF

Bit Set f

Syntax:

[ label ] BSF f,b

Operands:

0  f  127

0  b  7

Operation:

1 (f<b>)

Status Affected:

Description:

None

Bit ‘b’ in register ‘f’ is set.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 211

PIC16LF1904/6/7

CALL

Call Subroutine

CLRWDT

Clear Watchdog Timer

Syntax:

[ label ] CALL

0  k  2047

k

Syntax:

[ label ] CLRWDT

Operands:

Operation:

Operands:

Operation:

None

(PC)+ 1 TOS,

k  PC<10:0>,

(PCLATH<6:3>)  PC<14:11>

00h  WDT

0 WDT prescaler,

1 TO

1 PD

Status Affected:

Description:

None

Status Affected:

Description:

TO, PD

Call Subroutine. First, return address

(PC + 1) is pushed onto the stack.

The 11-bit immediate address is

loaded into PC bits <10:0>. The upper

bits of the PC are loaded from

PCLATH. CALLis a 2-cycle instruc-

tion.

CLRWDTinstruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT. Status bits TO and PD

are set.

COMF

Complement f

CALLW

Subroutine Call With W

Syntax:

[ label ] COMF f,d

Syntax:

[ label ] CALLW

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

None

(PC) +1  TOS,

(W)  PC<7:0>,

Operation:

(f)  (destination)

(PCLATH<6:0>) PC<14:8>

Status Affected:

Description:

Z

The contents of register ‘f’ are com-

plemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Status Affected:

Description:

None

Subroutine call with W. First, the

return address (PC + 1) is pushed

onto the return stack. Then, the con-

tents of W is loaded into PC<7:0>,

and the contents of PCLATH into

PC<14:8>. CALLWis a 2-cycle

instruction.

DECF

Decrement f

CLRF

Clear f

Syntax:

[ label ] DECF f,d

Syntax:

[ label ] CLRF

0  f  127

f

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

00h  (f)

1 Z

Operation:

(f) - 1  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If ‘d’

is ‘1’, the result is stored back in regis-

ter ‘f’.

The contents of register ‘f’ are cleared

and the Z bit is set.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

Operation:

None

00h  (W)

1 Z

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z) is

set.

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DECFSZ

Decrement f, Skip if 0

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Syntax:

[ label ] INCFSZ f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) - 1  (destination);

skip if result = 0

Operation:

(f) + 1  (destination),

skip if result = 0

Status Affected:

Description:

None

Status Affected:

Description:

None

The contents of register ‘f’ are decre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, then a

NOPis executed instead, making it a

2-cycle instruction.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, a NOPis

executed instead, making it a 2-cycle

instruction.

GOTO

Unconditional Branch

IORLW

Inclusive OR literal with W

Syntax:

[ label ] GOTO

0  k  2047

k

Syntax:

[ label ] IORLW

0  k  255

(W) .OR. k  (W)

Z

k

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

k  PC<10:0>

PCLATH<6:3>  PC<14:11>

Status Affected:

Description:

None

The contents of the W register are

OR’ed with the 8-bit literal ‘k’. The

result is placed in the W register.

GOTOis an unconditional branch. The

11-bit immediate value is loaded into

PC bits <10:0>. The upper bits of PC

are loaded from PCLATH<4:3>. GOTO

is a 2-cycle instruction.

INCF

Increment f

IORWF

Inclusive OR W with f

Syntax:

[ label ] INCF f,d

Syntax:

[ label ] IORWF f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) + 1  (destination)

Operation:

(W) .OR. (f)  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

Inclusive OR the W register with regis-

ter ‘f’. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

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LSLF

Logical Left Shift

MOVF

Move f

Syntax:

[ label ] LSLF f {,d}

Syntax:

[ label ] MOVF f,d

Operands:

0  f  127

d [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f<7>)  C

Operation:

(f)  (dest)

(f<6:0>)  dest<7:1>

0  dest<0>

Status Affected:

Description:

Z

The contents of register f is moved to

a destination dependent upon the

status of d. If d = 0, destination is W

register. If d = 1, the destination is file

register f itself. d = 1is useful to test a

file register since status flag Z is

affected.

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the left through the Carry flag.

A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,

the result is placed in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

Words:

1

C

register f

0

Cycles:

Example:

MOVF

FSR, 0

After Instruction

LSRF

Logical Right Shift

W

Z

=

value in FSR register

1

Syntax:

[ label ] LSRF f {,d}

Operands:

0  f  127

d [0,1]

Operation:

0  dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. A ‘0’ is shifted into the MSb. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is stored back in register ‘f’.

0

C

register f

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MOVIW

Move INDFn to W

MOVLP

Move literal to PCLATH

Syntax:

[ label ] MOVIW ++FSRn

[ label ] MOVIW --FSRn

[ label ] MOVIW FSRn++

[ label ] MOVIW FSRn--

[ label ] MOVIW k[FSRn]

Syntax:

[ label ] MOVLP

0  k  127

k  PCLATH

None

k

Operands:

Operation:

Status Affected:

Description:

Operands:

Operation:

n  [0,1]

mm  [00,01, 10, 11]

-32  k  31

The 7-bit literal ‘k’ is loaded into the

PCLATH register.

INDFn  W

Effective address is determined by

MOVLW

Move literal to W

•

FSR + 1 (preincrement)

FSR - 1 (predecrement)

FSR + k (relative offset)

Syntax:

[ label ] MOVLW

0  k  255

k  (W)

k

Operands:

Operation:

Status Affected:

Description:

After the Move, the FSR value will be

either:

None

•

FSR + 1 (all increments)

FSR - 1 (all decrements)

Unchanged

The 8-bit literal ‘k’ is loaded into W reg-

ister. The “don’t cares” will assemble as

‘0’s.

Status Affected:

Z

Words:

1

Cycles:

Example:

Mode

Syntax

mm

00

01

10

11

MOVLW

0x5A

Preincrement

Predecrement

Postincrement

Postdecrement

++FSRn

--FSRn

FSRn++

FSRn--

After Instruction

W

=

0x5A

MOVWF

Move W to f

[ label ] MOVWF

0  f  127

(W)  (f)

Syntax:

f

Description:

This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

Operands:

Operation:

Status Affected:

Description:

None

Move data from W register to register

‘f’.

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

Words:

1

Cycles:

Example:

MOVWF

Before Instruction

OPTION_REG = 0xFF

W = 0x4F

OPTION_REG

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to

wrap-around.

After Instruction

OPTION_REG = 0x4F

W = 0x4F

MOVLB

Move literal to BSR

Syntax:

[ label ] MOVLB

0  k  15

k  BSR

None

k

Operands:

Operation:

Status Affected:

Description:

The 5-bit literal ‘k’ is loaded into the

Bank Select Register (BSR).

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NOP

No Operation

MOVWI

Move W to INDFn

Syntax:

[ label ] NOP

Syntax:

[ label ] MOVWI ++FSRn

[ label ] MOVWI --FSRn

[ label ] MOVWI FSRn++

[ label ] MOVWI FSRn--

[ label ] MOVWI k[FSRn]

Operands:

Operation:

Status Affected:

Description:

Words:

None

No operation

None

No operation.

Operands:

Operation:

n  [0,1]

mm  [00,01, 10, 11]

-32  k  31

1

Cycles:

1

W  INDFn

Effective address is determined by

Example:

NOP

•

FSR + 1 (preincrement)

FSR - 1 (predecrement)

FSR + k (relative offset)

After the Move, the FSR value will be

either:

Load OPTION_REG Register

with W

OPTION

•

FSR + 1 (all increments)

FSR - 1 (all decrements)

Syntax:

[ label ] OPTION

None

Unchanged

Operands:

Operation:

Status Affected:

Description:

Status Affected:

None

(W)  OPTION_REG

None

Mode

Syntax

mm

00

01

10

11

Move data from W register to

OPTION_REG register.

Preincrement

Predecrement

Postincrement

Postdecrement

++FSRn

--FSRn

FSRn++

FSRn--

Words:

1

Cycles:

Example:

1

OPTION

Before Instruction

OPTION_REG = 0xFF

W = 0x4F

After Instruction

OPTION_REG = 0x4F

W = 0x4F

Description:

This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

RESET

Software Reset

Syntax:

[ label ] RESET

Operands:

Operation:

None

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to

wrap-around.

Execute a device Reset. Resets the

RI flag of the PCON register.

Status Affected:

Description:

None

This instruction provides a way to

execute a hardware Reset by soft-

ware.

The increment/decrement operation on

FSRn WILL NOT affect any Status bits.

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RETURN

Return from Subroutine

RETFIE

Syntax:

Return from Interrupt

[ label ] RETFIE

None

Syntax:

[ label ] RETURN

None

Operands:

Operation:

Operands:

Operation:

TOS  PC

TOS  PC,

1 GIE

Status Affected:

Description:

None

Status Affected:

Description:

None

Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.

This is a 2-cycle instruction.

Return from Interrupt. Stack is POPed

and Top-of-Stack (TOS) is loaded in

the PC. Interrupts are enabled by

setting Global Interrupt Enable bit,

GIE (INTCON<7>). This is a 2-cycle

instruction.

Words:

1

Cycles:

Example:

2

RETFIE

After Interrupt

PC

=

TOS

GIE =

1

RETLW

Syntax:

Return with literal in W

RLF

Rotate Left f through Carry

[ label ] RETLW

0  k  255

k

Syntax:

Operands:

[ label ]

RLF f,d

Operands:

Operation:

0  f  127

d  [0,1]

k  (W);

TOS  PC

Operation:

See description below

C

Status Affected:

Description:

None

Status Affected:

Description:

The W register is loaded with the 8-bit

literal ‘k’. The program counter is

loaded from the top of the stack (the

return address). This is a 2-cycle

instruction.

The contents of register ‘f’ are rotated

one bit to the left through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Words:

1

2

C

Register f

Cycles:

Example:

CALL TABLE;W contains table

;offset value

Words:

1

Cycles:

Example:

•

;W now has table value

TABLE

RLF

REG1,0

Before Instruction

ADDWF PC ;W = offset

RETLW k1 ;Begin table

REG1

C

=

1110 0110

0

RETLW k2

;

After Instruction

•

REG1

W

C

=

1110 0110

1100 1100

1

RETLW kn ; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

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SUBLW

Subtract W from literal

RRF

Rotate Right f through Carry

Syntax:

[ label ] SUBLW

0 k 255

k

Syntax:

[ label ] RRF f,d

Operands:

Operation:

Status Affected:

Description:

Operands:

0  f  127

d  [0,1]

k - (W) W)

C, DC, Z

Operation:

See description below

C

The W register is subtracted (2’s com-

plement method) from the 8-bit literal

‘k’. The result is placed in the W regis-

ter.

Status Affected:

Description:

The contents of register ‘f’ are rotated

one bit to the right through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

C = 0

W  k

C = 1

W  k

C

Register f

DC = 0

DC = 1

W<3:0>  k<3:0>

W<3:0>  k<3:0>

SUBWF

Subtract W from f

SLEEP

Enter Sleep mode

[ label ] SLEEP

None

Syntax:

[ label ] SUBWF f,d

Syntax:

Operands:

0 f 127

d  [0,1]

Operands:

Operation:

00h  WDT,

0 WDT prescaler,

1 TO,

Operation:

(f) - (W) destination)

Status Affected:

Description:

C, DC, Z

0 PD

Subtract (2’s complement method) W

register from register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W

register. If ‘d’ is ‘1’, the result is stored

back in register ‘f.

Status Affected:

Description:

TO, PD

The power-down Status bit, PD is

cleared. Time-out Status bit, TO is

set. Watchdog Timer and its pres-

caler are cleared.

C = 0

W  f

The processor is put into Sleep mode

with the oscillator stopped.

C = 1

W  f

DC = 0

DC = 1

W<3:0>  f<3:0>

W<3:0>  f<3:0>

SUBWFB

Subtract W from f with Borrow

Syntax:

SUBWFB f {,d}

Operands:

0  f  127

d  [0,1]

Operation:

(f) – (W) – (B) dest

Status Affected:

Description:

C, DC, Z

Subtract W and the BORROW flag

(CARRY) from register ‘f’ (2’s comple-

ment method). If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

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SWAPF

Swap Nibbles in f

XORLW

Exclusive OR literal with W

Syntax:

[ label ] SWAPF f,d

Syntax:

[ label ] XORLW

0 k 255

k

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

Status Affected:

Description:

(W) .XOR. k W)

Z

Operation:

(f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

The contents of the W register are

XOR’ed with the 8-bit literal ‘k’. The

result is placed in the W register.

Status Affected:

Description:

None

The upper and lower nibbles of regis-

ter ‘f’ are exchanged. If ‘d’ is ‘0’, the

result is placed in the W register. If ‘d’

is ‘1’, the result is placed in register ‘f’.

XORWF

Exclusive OR W with f

TRIS

Load TRIS Register with W

Syntax:

[ label ] XORWF f,d

Syntax:

[ label ] TRIS f

5  f  7

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

Status Affected:

Description:

Operation:

(W) .XOR. (f) destination)

(W)  TRIS register ‘f’

None

Status Affected:

Description:

Z

Exclusive OR the contents of the W

register with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If ‘d’

is ‘1’, the result is stored back in regis-

ter ‘f’.

Move data from W register to TRIS

register.

When ‘f’ = 5, TRISA is loaded.

When ‘f’ = 6, TRISB is loaded.

When ‘f’ = 7, TRISC is loaded.

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NOTES:

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22.0 ELECTRICAL SPECIFICATIONS

(†)

Absolute Maximum Ratings

Ambient temperature under bias....................................................................................................... -40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on pins with respect to VSS

on VDD ................................................................................................................................... -0.3V to +4.0V

on MCLR ................................................................................................................................ -0.3V to +9.0V

on all other pins ........................................................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾...............................................................................................................................800 mW

Maximum current

out of VSS pin

-40°C  TA  +85°C for industrial ......................................................................................... 300 mA

-40°C  TA  +125°C for extended......................................................................................... 95 mA

into VDD pin

-40°C  TA  +85°C for industrial ......................................................................................... 250 mA

-40°C  TA  +125°C for extended......................................................................................... 70 mA

Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA

Maximum output current

sunk by any I/O pin.............................................................................................................................. 25 mA

sourced by any I/O pin......................................................................................................................... 25 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for

extended periods may affect device reliability.

22.1 Standard Operating Conditions

The standard operating conditions for any device are defined as:

Operating Voltage:

Operating Temperature:

VDDMIN VDD VDDMAX

TA_MIN TA TA_MAX

VDD — Operating Supply Voltage⁽²⁾

VDDMIN (Fosc  16 MHz) ......................................................................................................... +1.8V

VDDMIN (Fosc  20 MHz) ......................................................................................................... +2.3V

VDDMAX .................................................................................................................................... +3.6V

TA — Operating Ambient Temperature Range

Industrial Temperature

TA_MIN...................................................................................................................................... -40°C

TA_MAX.................................................................................................................................... +85°C

Extended Temperature

TA_MIN...................................................................................................................................... -40°C

TA_MAX.................................................................................................................................. +125°C

Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be

limited by the device package power dissipation characterizations, see Section TABLE 22-6: “Thermal

Considerations” to calculate device specifications.

2: See Parameter D001, DS Characteristics: Supply Voltage.

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FIGURE 22-1:

VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C

3.6

EC Mode

Only

2.5

2.3

Internal Oscillator

or EC Mode

2.0

1.8

20

0

4

10

Frequency (MHz)

16

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 22-7 for each Oscillator mode’s supported frequencies.

FIGURE 22-2:

HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE

125

- 15% to + 12.5%

85

60

± 8%

± 6.5%

25

0

-20

- 15% to + 12.5%

-40

1.8

2.0

2.5

3.5

3.6

3.0

VDD (V)

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22.2

DC Characteristics

TABLE 22-1: SUPPLY VOLTAGE

Standard Operating Conditions (unless otherwise stated)

PIC16LF1904/6/7

Param.

No.

Sym.

Characteristic

Min.

Typ† Max.

Units

Conditions

D001

VDD

1.8

2.3

—

3.6

V

FOSC  16 MHz

FOSC  20 MHz (EC mode only)

(1)

D002*

VDR

RAM Data Retention Voltage

1.5

1.54

—

1.64

1.7

—

1.74

—

V

Device in Sleep mode

D002A* VPOR*

D002B* VPORR*

Power-on Reset Release Voltage

Power-on Reset Rearm Voltage

V

Device in Sleep mode

D003

VADFVR

Fixed Voltage Reference Voltage for

ADC, Initial Accuracy

6

7

8

—

4

6

%

1.024V, VDD  1.8V, 85°C

1.024V, VDD  1.8V, 125°C

2.048V, VDD  2.5V, 85°C

2.048V, VDD  2.5V, 125°C

D003A

VCDAFVR

Fixed Voltage Reference Voltage for

Comparator and DAC, Initial

Accuracy

7

8

9

—

5

7

%

1.024V, VDD  1.8V, 85°C

1.024V, VDD  1.8V, 125°C

2.048V, VDD  2.5V, 85°C

2.048V, VDD  2.5V, 125°C

D003B

VLCDFVR

Fixed Voltage Reference Voltage for

LCD Bias, Initial Accuracy

9

9.5

—

9

%

3.072V, VDD  3.6V, 85°C

3.072V, VDD  3.6V, 125°C

D003C* TCVFVR

Temperature Coefficient, Fixed

Voltage Reference

—

-130

0.270

—

ppm/°C

%/V

D003D* VFVR/

VIN

Line Regulation, Fixed Voltage

Reference

D004*

SVDD

VDD Rise Rate to ensure internal

0.05

V/ms

See Section 5.1 “Power-on Reset

(POR)” for details.

Power-on Reset signal

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

Note 1:

FIGURE 22-3:

POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR

VPORR

VSS

NPOR

POR REARM

VSS

(3)

(2)

TPOR

TVLOW

Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.

3: TVLOW 2.7 s typical.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 223

PIC16LF1904/6/7

TABLE 22-2: SUPPLY CURRENT (IDD)^(1,2)

Standard Operating Conditions (unless otherwise stated)

Conditions

Note

PIC16LF1904/6/7

Param

Device

Min.

Typ†

Max.

Units

No.

Characteristics

VDD

(1, 2)

Supply Current (IDD)

D010

—

58

115

133

130

245

290

218

283

314

233

309

347

305

433

500

395

600

700

567

915

1087

2.7

75

140

176

200

300

350

275

375

395

325

425

475

360

520

600

480

720

850

670

1100

1300

7.2

A

1.8

3.0

3.6

1.8

3.0

3.6

1.8

3.0

3.6

FOSC = 1 MHz

EC Oscillator mode

High Power mode

D011

D012

FOSC = 4 MHz

EC Oscillator mode

High Power mode

FOSC = 500 kHz

HFINTOSC mode

D013

D014

D015

D016

D017

D017A

D018

D018A

—

A

1.8

3.0

3.6

FOSC = 1 MHz

HFINTOSC mode

—

A

1.8

3.0

3.6

FOSC = 4 MHz

HFINTOSC mode

—

A

1.8

3.0

3.6

FOSC = 8 MHz

HFINTOSC mode

—

A

1.8

3.0

3.6

FOSC = 16 MHz

HFINTOSC mode

—

A

1.8

3.0

3.6

FOSC = 31 kHz

LFINTOSC mode

-40°C  TA  +125°C

4.5

9.7

5.2

12.0

6.5

2.7

—

A

1.8

3.0

3.6

FOSC = 31 kHz

LFINTOSC mode

-40°C  TA  +85°C

4.5

9.0

5.2

11.0

6.7

2.4

—

A

1.8

3.0

3.6

FOSC = 32 kHz

EC Oscillator mode, Low-Power mode

-40°C  TA  +125°C

4.2

9.2

4.8

11.5

6.0

2.4

—

A

1.8

3.0

3.6

FOSC = 32 kHz

EC Oscillator mode, Low-Power mode

-40°C  TA  +85°C

4.2

8.5

4.8

10.5

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: FVR and BOR are disabled.

DS40001569D-page 224

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 22-3: POWER-DOWN CURRENTS (IPD)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1904/6/7

Conditions

Param

No.

Max.

+85°C +125°C

Max.

Device Characteristics

Min.

Typ†

Units

VDD

Note

(2)

Power-down Base Current (IPD)

D023

—

0.15

0.16

0.65

0.27

0.56

0.75

17.5

17.7

17.8

0.15

0.21

7.0

1.0

2.0

3.0

2.0

3.0

4.0

31

3.0

4.0

5.0

4.0

5.0

6.0

35

A

1.8

3.0

3.6

1.8

3.0

3.6

1.8

3.0

3.6

3.0

3.6

3.0

3.6

1.8

3.0

3.6

1.8

3.0

3.6

1.8

3.0

3.6

WDT, BOR, FVR, and T1OSC

disabled, all Peripherals Inactive

D024

D025

WDT Current (Note 1)

FVR current

33

38

35

41

2.30

3.40

10

3.56

4.70

12

LPBOR current

BOR Current

D026

D027

D028

7.5

12

14

0.50

0.60

0.70

0.40

0.70

0.90

—

2.0

3.0

4.0

2.0

3.0

4.0

250

4.0

5.0

6.0

4.0

5.0

6.0

—

T1OSC Current

D029

D030

D031

ADC Current (Note 1, Note 3),

no conversion in progress

ADC Current (Note 1, Note 3),

conversion in progress

—

LCD Bias Ladder

Low power

—

1

2

6

A

1.8

3.0

3.6

Medium Power

High Power

10

13

21

100

111

120

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: A/D oscillator source is FRC.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 225

PIC16LF1904/6/7

TABLE 22-4: I/O PORTS

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Param

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

VIL

Input Low Voltage

I/O PORT:

D032

D033

D034

with TTL buffer

with Schmitt Trigger buffer

MCLR, OSC1

—

0.15 VDD

0.2 VDD

V

1.8V  VDD  3.6V

VIH

Input High Voltage

I/O ports:

D040

with TTL buffer

0.25 VDD +

0.8

—

V

1.8V  VDD  3.6V

D041

D042

with Schmitt Trigger buffer

MCLR

0.8 VDD

—

V

(2)

IIL

Input Leakage Current

D060

I/O ports

—

± 5

± 125

nA

VSS  VPIN  VDD, Pin at

high-impedance @ 85°C

± 5

± 1000

± 200

nA 125°C

D061

D070*

D080

MCLR⁽³⁾

—

± 50

nA

VSS  VPIN  VDD @ 85°C

IPUR

VOL

Weak Pull-up Current

25

100

—

200

0.6

A

VDD = 3.3V, VPIN = VSS

Output Low Voltage

I/O ports

IOL = 6mA, VDD = 3.3V

IOL = 1.8mA, VDD = 1.8V

V

—

VOH

Output High Voltage

D090

I/O ports

IOH = 3mA, VDD = 3.3V

IOH = 1mA, VDD = 1.8V

VDD - 0.7

—

V

Capacitive Loading Specs on Output Pins

All I/O pins

D101*

CIO

—

50

pF

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Negative current is defined as current sourced by the pin.

DS40001569D-page 226

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

TABLE 22-5: MEMORY PROGRAMMING REQUIREMENTS

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Param

Sym.

No.

Characteristic

Min.

Typ†

Max.

Units

Conditions

Program Memory Programming

Specifications

D110

D111

D112

VIHH

IDDP

Voltage on MCLR/VPP/RE3 pin

Supply Current during Programming

VDD for Bulk Erase

8.0

—

9.0

10

V

mA

V

(Note 2)

2.7

VDD

max.

D113

VPEW

VDD for Write or Row Erase

VDD

min.

—

VDD

max.

V

D114

D115

IPPPGM Current on MCLR/VPP during

Erase/Write

—

1.0

5.0

—

mA

IDDPGM Current on VDD during Erase/Write

—

Program Flash Memory

D121

D122

EP

Cell Endurance

VDD for Read

1K

10K

—

E/W -40C to +85C (Note 1)

VPR

VDD

min.

VDD

max.

V

D123

D124

TIW

Self-timed Write Cycle Time

—

2

2.5

—

ms

TRETD Characteristic Retention

40

—

Year Provided no other

specifications are violated

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Self-write and Block Erase.

2: Required only if single-supply programming is disabled.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 227

PIC16LF1904/6/7

TABLE 22-6: THERMAL CONSIDERATIONS

Standard Operating Conditions (unless otherwise stated)

Param

Sym.

Characteristic

Typ.

Units

Conditions

28-pin SPDIP package

No.

TH01

JA

Thermal Resistance Junction to Ambient

60

80

C/W

C

28-pin SOIC package

90

28-pin SSOP package

27.5

47.2

41.0

46.0

31.4

24

28-pin UQFN 4x4mm package

40-pin PDIP package

40-pin UQFN 5x5mm package

44-pin TQFP package

TH02

JC

Thermal Resistance Junction to Case

28-pin SPDIP package

28-pin SOIC package

24

28-pin SSOP package

24

28-pin UQFN 4x4mm package

40-pin PDIP package

24.7

50.5

14.5

150

—

40-pin UQFN 5x5mm package

44-pin TQFP package

TH03

TH04

TH05

TH06

TH07

TJMAX

PD

Maximum Junction Temperature

Power Dissipation

W

PD = PINTERNAL + PI/O

(1)

PINTERNAL Internal Power Dissipation

—

W

PINTERNAL = IDD x VDD

PI/O

I/O Power Dissipation

Derated Power

—

W

PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))

(2)

PDER

—

W

PDER = PDMAX (TJ - TA)/JA

Note 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature

3: TJ = Junction Temperature

DS40001569D-page 228

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

22.3

AC Characteristics

The timing parameter symbols have been created with

one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase letters (pp) and their meanings:

pp

cc

T

Time

CCP1

CLKOUT

CS

osc

rd

OSC1

RD

ck

cs

di

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O PORT

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (High-impedance)

Low

Valid

L

High-impedance

FIGURE 22-4:

LOAD CONDITIONS

Load Condition

CL

VSS

Legend: CL = 50 pF for all pins, 15 pF for

OSC2 output

 2011-2016 Microchip Technology Inc.

DS40001569D-page 229

PIC16LF1904/6/7

TABLE 22-7: CLOCK OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

No.

OS01

FOSC

External CLKIN Frequency⁽¹⁾

DC

—

0.5

4

MHz External Clock (ECL)

MHz

External Clock (ECM)

DC

—

20

External Clock (ECH)

External Clock (EC)

TCY = 4/FOSC

OS02

OS03

TOSC

TCY

External CLKIN Period⁽¹⁾

Instruction Cycle Time⁽¹⁾

50

—



ns

200

TCY

DC

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing code.

Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-

sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external

clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

TABLE 22-8: OSCILLATOR PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Freq.

Tolerance

Sym.

Characteristic

Min. Typ† Max. Units

Conditions

OS08

HFOSC

Internal Calibrated HFINTOSC

Frequency⁽²⁾

8%

±6.5%

—

16

—

MHz 0°C  TA  +85°C

MHz VDD = 3.0V @ +25°C

OS10A* TIOSC ST HFINTOSC 16 MHz

Oscillator Wake-up from Sleep

Start-up Time

—

5

15

s

VDD = 2.0V, -40°C to +85°C

VDD = 3.0V, -40°C to +85°C

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current

consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an

external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

DS40001569D-page 230

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 22-5:

CLKOUT AND I/O TIMING

Cycle

Write

Q4

Fetch

Q1

Read

Q2

Execute

Q3

FOSC

OS12

OS11

OS20

OS21

CLKOUT

OS19

OS13

OS18

OS16

OS17

I/O pin

(Input)

OS14

OS15

I/O pin

(Output)

New Value

Old Value

OS18, OS19

TABLE 22-9: CLKOUT AND I/O TIMING PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Param

No.

Sym.

Characteristic

Min.

Typ† Max. Units

Conditions

OS11 TosH2ckL FOSC to CLKOUT ⁽¹⁾

OS12 TosH2ckH FOSC to CLKOUT ⁽¹⁾

OS13 TckL2ioV CLKOUT to Port out valid⁽¹⁾

—

70

72

20

ns VDD = 3.3-5.0V

ns

—

OS14 TioV2ckH Port input valid before CLKOUT⁽¹⁾

OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid

TOSC + 200 ns

—

50

—

70*

—

ns

—

ns VDD = 3.3-5.0V

OS16 TosH2ioI

Fosc (Q2 cycle) to Port input invalid

50

(I/O in hold time)

OS17 TioV2osH Port input valid to Fosc(Q2 cycle)

20

—

ns

(I/O in setup time)

OS18 TioR

OS19 TioF

Port output rise time

—

40

15

72

32

ns

VDD = 1.8V

VDD = 3.3-5.0V

Port output fall time

—

28

15

55

30

VDD = 1.8V

VDD = 3.3-5.0V

OS20* Tinp

OS21* Tioc

INT pin input high or low time

25

—

ns

Interrupt-on-change new input level

time

*

†

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25C unless otherwise stated.

Note 1: Measurements are taken in EC mode where CLKOUT output is 4 x TOSC.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 231

PIC16LF1904/6/7

FIGURE 22-6:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Start-Up Time

Internal Reset⁽¹⁾

Watchdog Timer

Reset⁽¹⁾

31

34

I/O pins

Note 1: Asserted low.

FIGURE 22-7:

BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

VBOR and VHYST

VBOR

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

37

Reset

33⁽¹⁾

(due to BOR)

Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.

2 ms delay if PWRTE = 0and VREGEN = 1.

DS40001569D-page 232

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 22-8:

MINIMUM PULSE WIDTH FOR LPBOR DETECTION

VDD

(Monitored Voltage)

VLPBOR

500 nVs < VBPW

10 nVs < VBPW < 500 nVs

Maybe Detected

VBPW < 10 nVs

Pulse Rejected

 2011-2016 Microchip Technology Inc.

DS40001569D-page 233

PIC16LF1904/6/7

TABLE 22-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Param

Sym.

Characteristic

Min. Typ† Max. Units

Conditions

No.

30

TMCL

MCLR Pulse Width (low)

2

5

—

s VDD = 3.0V, -40°C to +85°C

s VDD = 3.0V

31

FWDTLP Low Frequency Internal Oscillator

Frequency

19

33

52

kHz

32

TOST

Oscillator Start-up Timer Period⁽¹⁾

—

1024

2048

—

Tosc (Note 2)

33*

34*

TPWRT Power-up Timer Period, PWRTE = 0

Tosc Clocked by LFINTOSC

TIOZ

I/O High-Impedance from MCLR

Low or Watchdog Timer Reset

2.0

s

35

VBOR

Brown-out Reset Voltage: BORV = 0 2.55 2.70 2.85

BORV = 1 1.80 1.90 2.05

V

35A* VHYST

Brown-out Reset Hysteresis

25

—

50

—

75

100

mV -40°C to +85°C

mV -40°C to +125°C

35B* TBORDC Brown-out Reset DC Response

Time

1

—

3

—

5

10

s VDD  VBOR, -40°C to +85°C

s VDD  VBOR

35C

TBORAC Brown-out Reset AC Response

Time

—

100

—

ns Transient Response immunity

for a noise spike that goes

from VDD to VSS and back with

10 ns rise and fall times.

Guidance only.

36

TFVRS

Fixed Voltage Reference Turn-on

Time

—

5

s Turn on to specified stability

37

VLPBOR Low-Power Brown-out Reset

Voltage

1.85 1.95 2.10

V

-40°C to +85°C

38*

39*

VZPHYST Zero-Power Brown-out Reset

Hysteresis

0

25

—

60

mV -40°C to +85°C

TZPBPW Zero-Power Brown-out Reset AC

Response Time for BOR detection

10

500

nVs VDD  VBOR, -40°C to +85°C

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at “min” values with an external

clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no

clock) for all devices.

2: Period of the slower clock.

3: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

DS40001569D-page 234

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 22-9:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40

41

42

T1CKI

45

46

49

47

TMR0 or

TMR1

TABLE 22-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions(unless otherwise stated)

Param

Sym.

TT0H

Characteristic

Min.

Typ†

Max.

Units

Conditions

No.

40*

T0CKI High Pulse Width

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20

—

ns

10

0.5 TCY + 20

10

41*

42*

TT0L

TT0P

T0CKI Low Pulse Width

T0CKI Period

Greater of:

20 or TCY + 40

N

ns N = prescale value

(2, 4, ..., 256)

45*

TT1H

T1CKI High Synchronous, No Prescaler

0.5 TCY + 20

15

—

ns

Time

Synchronous,

with Prescaler

Asynchronous

30

—

ns

46*

47*

TT1L

TT1P

T1CKI Low Synchronous, No Prescaler

0.5 TCY + 20

Time

Synchronous, with Prescaler

Asynchronous

15

30

T1CKI Input Synchronous

Period

Greater of:

30 or TCY + 40

N

ns N = prescale value

(1, 2, 4, 8)

Asynchronous

60

—

ns

48

FT1

Timer1 Oscillator Input Frequency Range

(oscillator enabled by setting bit T1OSCEN)

32.4

32.768

33.1

kHz

49*

TCKEZTMR1 Delay from External Clock Edge to Timer

Increment

2 TOSC

—

7 TOSC

—

Timers in Sync

mode

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 235

PIC16LF1904/6/7

TABLE 22-12: PIC16LF1904/6/7 A/D CONVERTER (ADC) CHARACTERISTICS:

Operating Conditions (unless otherwise stated)

VDD = 3.0V, TA = 25°C

Param

No.

Sym.

Characteristic

Resolution

Min.

Typ†

Max. Units

Conditions

AD01 NR

AD02 EIL

AD03 EDL

—

±1

10

±1.7

±1

bit

Integral Error

LSb VREF = 3.0V

Differential Error

LSb No missing codes

VREF = 3.0V

AD04 EOFF Offset Error

—

±1

—

±2

±1.5

VDD

VREF

10

LSb VREF = 3.0V

AD05 EGN Gain Error

AD06 VREF Reference Voltage⁽³⁾

1.8

VSS

—

V

VREF = (VRPOS - VRNEG)

AD07 VAIN Full-Scale Range

AD08 ZAIN Recommended Impedance of

Analog Voltage Source

k Can go higher if external 0.01F capacitor is

present on input pin.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Total Absolute Error includes integral, differential, offset and gain errors.

2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

3: ADC VREF is from external VREF, VDD pin or FVREF, whichever is selected as reference input.

4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification

includes any such leakage from the ADC module.

TABLE 22-13: PIC16LF1902/3 A/D CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max. Units

Conditions

AD130* TAD

ADC Clock Period (TADC)

ADC Internal FRC Oscillator Period (TFRC)

AD131 TCNV Conversion Time

(not including Acquisition Time)⁽¹⁾

1.0

—

2.0

11

6.0

—

s FOSC-based

s ADCS<2:0> = x11(ADC FRC mode)

TAD Set GO/DONE bit to conversion

complete

AD132* TACQ Acquisition Time

—

5.0

—

s

AD133* THCD Holding Capacitor Disconnect Time

—

1/2 TAD

1/2 TAD + 1TCY

—

FOSC-based

ADCS<2:0> = x11(ADC FRC mode)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: The ADRES register may be read on the following TCY cycle.

DS40001569D-page 236

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

FIGURE 22-10:

PIC16LF1904/6/7 A/D CONVERSION TIMING (NORMAL MODE)

BSF ADCON0, GO

1 TCY

(TOSC/2⁽¹⁾

)

AD131

Q4

AD130

A/D CLK

7

6

5

4

3

2

1

0

A/D Data

ADRES

NEW_DATA

1 TCY

OLD_DATA

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

FIGURE 22-11:

PIC16LF1904/6/7 A/D CONVERSION TIMING (SLEEP MODE)

BSF ADCON0, GO

(1)

(TOSC/2 + TCY

1 TCY

)

AD131

Q4

AD130

A/D CLK

A/D Data

7

6

5

3

2

1

0

4

NEW_DATA

1 TCY

OLD_DATA

ADRES

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 237

PIC16LF1904/6/7

23.0 DC AND AC

CHARACTERISTICS GRAPHS

AND CHARTS

Graphs and charts are not available at this time.

DS40001569D-page 238

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

24.1 MPLAB X Integrated Development

Environment Software

24.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers (MCU) and dsPIC^®digital

signal controllers (DSC) are supported with a full range

of software and hardware development tools:

The MPLAB X IDE is a single, unified graphical user

interface for Microchip and third-party software, and

hardware development tool that runs on Windows^®,

Linux and Mac OS^®X. Based on the NetBeans IDE,

MPLAB X IDE is an entirely new IDE with a host of free

software components and plug-ins for high-

performance application development and debugging.

Moving between tools and upgrading from software

simulators to hardware debugging and programming

tools is simple with the seamless user interface.

• Integrated Development Environment

- MPLAB^®X IDE Software

• Compilers/Assemblers/Linkers

- MPLAB XC Compiler

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

With complete project management, visual call graphs,

a configurable watch window and a feature-rich editor

that includes code completion and context menus,

MPLAB X IDE is flexible and friendly enough for new

users. With the ability to support multiple tools on

multiple projects with simultaneous debugging, MPLAB

X IDE is also suitable for the needs of experienced

users.

• Simulators

- MPLAB X SIM Software Simulator

• Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers/Programmers

- MPLAB ICD 3

Feature-Rich Editor:

- PICkit™ 3

• Color syntax highlighting

• Device Programmers

- MPLAB PM3 Device Programmer

• Smart code completion makes suggestions and

provides hints as you type

• Low-Cost Demonstration/Development Boards,

Evaluation Kits and Starter Kits

• Automatic code formatting based on user-defined

rules

• Third-party development tools

• Live parsing

User-Friendly, Customizable Interface:

• Fully customizable interface: toolbars, toolbar

buttons, windows, window placement, etc.

• Call graph window

Project-Based Workspaces:

• Multiple projects

• Multiple tools

• Multiple configurations

• Simultaneous debugging sessions

File History and Bug Tracking:

• Local file history feature

• Built-in support for Bugzilla issue tracker

 2011-2016 Microchip Technology Inc.

DS40001569D-page 239

PIC16LF1904/6/7

24.2 MPLAB XC Compilers

24.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB XC Compilers are complete ANSI C

compilers for all of Microchip’s 8, 16, and 32-bit MCU

and DSC devices. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use. MPLAB XC Compilers run on Windows,

Linux or MAC OS X.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler. It can link

relocatable objects from precompiled libraries, using

directives from a linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

debug information that is optimized to the MPLAB X

IDE.

The free MPLAB XC Compiler editions support all

devices and commands, with no time or memory

restrictions, and offer sufficient code optimization for

most applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

MPLAB XC Compilers include an assembler, linker and

utilities. The assembler generates relocatable object

files that can then be archived or linked with other relo-

catable object files and archives to create an execut-

able file. MPLAB XC Compiler uses the assembler to

produce its object file. Notable features of the assem-

bler include:

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

24.5 MPLAB Assembler, Linker and

Librarian for Various Device

Families

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC DSC devices. MPLAB XC Compiler

uses the assembler to produce its object file. The

assembler generates relocatable object files that can

then be archived or linked with other relocatable object

files and archives to create an executable file. Notable

features of the assembler include:

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

24.3 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code, and COFF files for

debugging.

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

The MPASM Assembler features include:

• Integration into MPLAB X IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multipurpose

source files

• Directives that allow complete control over the

assembly process

DS40001569D-page 240

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

24.6 MPLAB X SIM Software Simulator

24.8 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB X SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB ICD 3 In-Circuit Debugger System is

Microchip’s most cost-effective, high-speed hardware

debugger/programmer for Microchip Flash DSC and

MCU devices. It debugs and programs PIC Flash

microcontrollers and dsPIC DSCs with the powerful,

yet easy-to-use graphical user interface of the MPLAB

IDE.

The MPLAB ICD 3 In-Circuit Debugger probe is

connected to the design engineer’s PC using a high-

speed USB 2.0 interface and is connected to the target

with a connector compatible with the MPLAB ICD 2 or

MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3

supports all MPLAB ICD 2 headers.

The MPLAB X SIM Software Simulator fully supports

symbolic debugging using the MPLAB XC Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

24.9 PICkit 3 In-Circuit Debugger/

Programmer

The MPLAB PICkit 3 allows debugging and program-

ming of PIC and dsPIC Flash microcontrollers at a most

affordable price point using the powerful graphical user

interface of the MPLAB IDE. The MPLAB PICkit 3 is

connected to the design engineer’s PC using a full-

speed USB interface and can be connected to the tar-

get via a Microchip debug (RJ-11) connector (compati-

ble with MPLAB ICD 3 and MPLAB REAL ICE). The

connector uses two device I/O pins and the Reset line

to implement in-circuit debugging and In-Circuit Serial

Programming™ (ICSP™).

24.7 MPLAB REAL ICE In-Circuit

Emulator System

The MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs all 8, 16 and 32-bit MCU, and DSC devices

with the easy-to-use, powerful graphical user interface of

the MPLAB X IDE.

The emulator is connected to the design engineer’s

PC using a high-speed USB 2.0 interface and is

connected to the target with either a connector

compatible with in-circuit debugger systems (RJ-11)

or with the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

24.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages, and a mod-

ular, detachable socket assembly to support various

package types. The ICSP cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices, and incorporates an MMC card for file

storage and data applications.

The emulator is field upgradable through future firmware

downloads in MPLAB X IDE. MPLAB REAL ICE offers

significant advantages over competitive emulators

including full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, logic

probes, a ruggedized probe interface and long (up to

three meters) interconnection cables.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 241

PIC16LF1904/6/7

24.11 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

24.12 Third-Party Development Tools

Microchip also offers a great collection of tools from

third-party vendors. These tools are carefully selected

to offer good value and unique functionality.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully

functional systems. Most boards include prototyping

areas for adding custom circuitry and provide applica-

tion firmware and source code for examination and

modification.

• Device Programmers and Gang Programmers

from companies, such as SoftLog and CCS

• Software Tools from companies, such as Gimpel

and Trace Systems

• Protocol Analyzers from companies, such as

Saleae and Total Phase

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

• Demonstration Boards from companies, such as

MikroElektronika, Digilent^®and Olimex

• Embedded Ethernet Solutions from companies,

such as EZ Web Lynx, WIZnet and IPLogika^®

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™

demonstration/development board series of circuits,

Microchip has a line of evaluation kits and demonstra-

®

tion software for analog filter design, KEELOQ security

ICs, CAN, IrDA^®, PowerSmart battery management,

SEEVAL^®evaluation system, Sigma-Delta ADC, flow

rate sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS40001569D-page 242

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

25.0 PACKAGING INFORMATION

25.1 Package Marking Information

28-Lead PDIP (600 mil)

Example

XXXXXXXXXXXXXXX

YYWWNNN

PIC16LF1906-I/P

1048017

28-Lead SOIC (7.50 mm)

Example

PIC16LF1906

-E/SO

XXXXXXXXXXXXXXXXXXXX

e

3

1048017

YYWWNNN

28-Lead SSOP (5.30 mm)

Example

PIC16LF1906

e

3

-E/SS

1048017

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC^®designator for Matte Tin (Sn)

e

3

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 243

PIC16LF1904/6/7

Package Marking Information (Continued)

28-Lead UQFN (4x4x0.5 mm)

Example

PIN 1

PIC16

LF1906

e

3

E/MV

048017

40-Lead PDIP (600 mil)

Example

XXXXXXXXXXXXXXXXXX

PIC16LF1904

-I/P

e

3

1010017

YYWWNNN

40-Lead UQFN (5x5x0.5 mm)

Example

PIN 1

PIC16

F1904

e

3

-I/MV

1010017

Example

44-Lead TQFP (10x10x1 mm)

PIC16F1907

-E/PT

XXXXXXXXXX

YYWWNNN

e

3

1048017

DS40001569D-page 244

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

25.2 Package Details

The following sections give the technical details of the packages.

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ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢁꢣꢀꢣꢤꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ

ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢻꢸꢩ

 2011-2016 Microchip Technology Inc.

DS40001569D-page 245

PIC16LF1904/6/7

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40001569D-page 246

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011-2016 Microchip Technology Inc.

DS40001569D-page 247

PIC16LF1904/6/7

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40001569D-page 248

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢟꢠꢡꢌꢑꢢꢇꢟꢗꢅꢉꢉꢇꢣꢏꢋꢉꢌꢑꢄꢇꢒꢟꢟꢓꢇꢔꢇꢤꢥꢦꢖꢇꢗꢗꢇꢘꢙꢆꢚꢇꢛꢟꢟꢣꢈꢜ

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

D

N

E

E1

1

2

b

NOTE 1

e

c

A2

A

φ

A1

L

L1

ꢯꢄꢃꢏꢇ

ꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ

ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ

ꢢꢰꢱ

ꢱꢴꢢ

ꢢꢦꢵ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ

ꢂꢃꢏꢖꢘ

ꢱ

ꢌ

ꢙꢶ

ꢣꢁꢺꢨꢅꢩꢛꢝ

ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢛꢏꢉꢄꢋꢕꢎꢎꢅ

ꢴꢆꢌꢐꢉꢊꢊꢅꢹꢃꢋꢏꢘ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢹꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

ꢬꢕꢕꢏꢅꢳꢌꢄꢜꢏꢘ

ꢬꢕꢕꢏꢡꢐꢃꢄꢏ

ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢬꢕꢕꢏꢅꢦꢄꢜꢊꢌ

ꢦ

ꢷ

ꢀꢁꢻꢨ

ꢷ

ꢻꢁꢶꢣ

ꢨꢁꢞꢣ

ꢀꢣꢁꢙꢣ

ꢣꢁꢻꢨ

ꢀꢁꢙꢨꢅꢼꢠꢬ

ꢷ

ꢙꢁꢣꢣ

ꢀꢁꢶꢨ

ꢷ

ꢶꢁꢙꢣ

ꢨꢁꢺꢣ

ꢀꢣꢁꢨꢣ

ꢣꢁꢸꢨ

ꢦꢙ

ꢦꢀ

ꢠ

ꢠꢀ

ꢟ

ꢳ

ꢳꢀ

ꢖ

ꢀꢁꢺꢨ

ꢣꢁꢣꢨ

ꢻꢁꢥꢣ

ꢨꢁꢣꢣ

ꢸꢁꢸꢣ

ꢣꢁꢨꢨ

ꢣꢁꢣꢸ

ꢣꢾ

ꢣꢁꢙꢨ

ꢶꢾ

ꢀ

ꢥꢾ

ꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ

ꢔ

ꢣꢁꢙꢙ

ꢷ

ꢣꢁꢞꢶ

ꢝꢙꢋꢄꢊꢞ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢣꢁꢙꢣꢅꢑꢑꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢼꢠꢬꢪ ꢼꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢻꢞꢩ

 2011-2016 Microchip Technology Inc.

DS40001569D-page 249

PIC16LF1904/6/7

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40001569D-page 250

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011-2016 Microchip Technology Inc.

DS40001569D-page 251

PIC16LF1904/6/7

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40001569D-page 252

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

 2011-2016 Microchip Technology Inc.

DS40001569D-page 253

PIC16LF1904/6/7

ꢧꢖꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢅꢉꢇꢐꢑꢂꢃꢌꢑꢄꢇꢒꢈꢓꢇꢔꢇꢕꢖꢖꢇꢗꢌꢉꢇꢘꢙꢆꢚꢇꢛꢈꢎꢐꢈꢜ

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

N

NOTE 1

E1

1 2 3

D

E

A2

A

L

c

b1

b

A1

e

eB

ꢯꢄꢃꢏꢇ

ꢰꢱꢝꢲꢠꢛ

ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ

ꢢꢰꢱ

ꢱꢴꢢ

ꢢꢦꢵ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ

ꢂꢃꢏꢖꢘ

ꢱ

ꢌ

ꢥꢣ

ꢁꢀꢣꢣꢅꢩꢛꢝ

ꢫꢕꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢩꢉꢇꢌꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢛꢘꢕꢈꢊꢋꢌꢐꢅꢏꢕꢅꢛꢘꢕꢈꢊꢋꢌꢐꢅꢹꢃꢋꢏꢘ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢹꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

ꢫꢃꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢯꢡꢡꢌꢐꢅꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ

ꢦ

ꢷ

ꢁꢙꢨꢣ

ꢁꢀꢸꢨ

ꢷ

ꢦꢙ

ꢦꢀ

ꢠ

ꢠꢀ

ꢟ

ꢳ

ꢖ

ꢔꢀ

ꢔ

ꢌꢩ

ꢁꢀꢙꢨ

ꢁꢣꢀꢨ

ꢁꢨꢸꢣ

ꢁꢥꢶꢨ

ꢀꢁꢸꢶꢣ

ꢁꢀꢀꢨ

ꢁꢣꢣꢶ

ꢁꢣꢞꢣ

ꢁꢣꢀꢥ

ꢷ

ꢁꢺꢙꢨ

ꢁꢨꢶꢣ

ꢙꢁꢣꢸꢨ

ꢁꢙꢣꢣ

ꢁꢣꢀꢨ

ꢁꢣꢻꢣ

ꢁꢣꢙꢞ

ꢁꢻꢣꢣ

ꢳꢕꢗꢌꢐꢅꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢼꢕꢗꢅꢛꢡꢉꢖꢃꢄꢜꢅꢅꢚ

ꢝꢙꢋꢄꢊꢞ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢁꢣꢀꢣꢤꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ

ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢀꢺꢩ

DS40001569D-page 254

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

D1

B

E

NOTE 2

(DATUM A)

(DATUM B)

E1

A

NOTE 1

2X

N

0.20 H A B

2X

1 2 3

0.20 H A B

4X 11 TIPS

TOP VIEW

0.20 C A B

A

A2

C

SEATING PLANE

0.10 C

A1

SIDE VIEW

1 2 3

N

NOTE 1

44 X b

0.20

C A B

e

BOTTOM VIEW

Microchip Technology Drawing C04-076C Sheet 1 of 2

 2011-2016 Microchip Technology Inc.

DS40001569D-page 255

PIC16LF1904/6/7

44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

H

c

θ

L

(L1)

SECTION A-A

Units

MILLIMETERS

Dimension Limits

MIN

NOM

44

0.80 BSC

-

MAX

Number of Leads

Lead Pitch

Overall Height

Standoff

N

e

A

A1

-

1.20

0.15

1.05

0.05

0.95

-

Molded Package Thickness

Overall Width

A2

E

1.00

12.00 BSC

10.00 BSC

12.00 BSC

10.00 BSC

0.37

Molded Package Width

Overall Length

E1

D

Molded Package Length

Lead Width

D1

b

c

0.30

0.09

0.45

0.20

0.75

Lead Thickness

Lead Length

Footprint

-

L

L1

θ

0.60

1.00 REF

3.5°

Foot Angle

0°

7°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Exact shape of each corner is optional.

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-076C Sheet 2 of 2

DS40001569D-page 256

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

44-Lead Plastic Thin Quad Flatpack (PT) - 10X10X1 mm Body, 2.00 mm Footprint [TQFP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

C1

44

1

2

G

C2

Y1

X1

E

SILK SCREEN

RECOMMENDED LAND PATTERN

Units

MILLIMETERS

Dimension Limits

MIN

0.25

NOM

0.80 BSC

11.40

MAX

Contact Pitch

Contact Pad Spacing

E

C1

C2

11.40

Contact Pad Width (X44)

Contact Pad Length (X44)

Distance Between Pads

X1

Y1

G

0.55

1.50

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2076B

 2011-2016 Microchip Technology Inc.

DS40001569D-page 257

PIC16LF1904/6/7

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40001569D-page 258

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011-2016 Microchip Technology Inc.

DS40001569D-page 259

PIC16LF1904/6/7

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40001569D-page 260

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

APPENDIX A: DATA SHEET

REVISION HISTORY

Revision A (03/2011)

Original release.

Revision B (08/2014)

Added Tables 9-3 and 9-4.

Updated PIC16LF190X Family Types Table.

Updated Equation 15-1; Example 3-2; Figures 1

through 5, 6-4, 15-1, 15-4, 19-7 22-2, 22-8; Registers

4-1, 4-2, 11-17, 15-1; Sections 4.1, 6.2.2.2, 10.0, 13.0,

15.1.3, 18.1.1.2, 18.1.1.3, 18.1.1.7, 18.1.2.9,

18.1.2.10, 18.2, 18.4.1.2, 19.1, 19.4.5, 22.0, 22.1, 22.5,

22.6, 22.7, 22-8, 22-10; Tables 1, 3-1, 3-3, 3-5, 5-1, 9-2,

10-3, 10-4, 17-2, 19-1, 22-2, 22-3, 22-4, 22-5, 22-6,

22-7, 22-8, 22-12.

Updated Package Marking Information.

Removed Section 18.1.2.3: Receive Data Polarity and

Section 18.4.1.4: Data Polarity.

Data sheet went from Preliminary to Final data sheet.

Revision C (01/2016)

Added ‘Memory’ section and updated the

‘PIC16LF190X Family Types’ table; Other minor

corrections.

Revision D (05/2016)

Minor changes to Figure 22-2, Table 22-8, and Table

22-10, in Electrical Specifications chapter; Updated

Packaging: 28L SOIC, 44L TQFP, 28L UQFN, 40L

UQFN. Removed Table 19-7, LCD Worksheet.

 2011-2016 Microchip Technology Inc.

DS40001569D-page 261

PIC16LF1904/6/7

THE MICROCHIP WEBSITE

CUSTOMER SUPPORT

Microchip provides online support via our website at

www.microchip.com. This website is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the website contains the following information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

Customers

should

contact

their

distributor,

representative or Field Application Engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the website

at: http://microchip.com/support

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip website at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

DS40001569D-page 262

 2011-2016 Microchip Technology Inc.

PIC16LF1904/6/7

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

(1)

[X]

PART NO.

X

/XX

XXX

-

Examples:

Device Tape and Reel

Option

Temperature

Range

Package

Pattern

a)

PIC16LF1904T - I/MV 301

Tape and Reel,

Industrial temperature,

UQFN package,

QTP pattern #301

b)

c)

PIC16LF1906 - I/P

Industrial temperature

PDIP package

Device:

PIC16LF1904, PIC16LF1906, PIC16LF1907

Blank = Standard packaging (tube or tray)

Tape and Reel

Option:

PIC16LF1906 - E/SS

Extended temperature,

SSOP package

T

= Tape and Reel⁽¹⁾

Temperature

Range:

I

E

=

-40C to +85C (Industrial)

-40C to +125C (Extended)

Package:

MV

P

= UQFN (4x4x0.5)

= PDIP

PT

SO

SS

= TQFP (44-pin)

= SOIC

Note 1:

Tape and Reel identifier only appears in the

catalog part number description. This

identifier is used for ordering purposes and is

not printed on the device package. Check

with your Microchip Sales Office for package

availability with the Tape and Reel option.

= SSOP

Pattern:

QTP, SQTP, Code or Special Requirements

(blank otherwise)

 2011-2016 Microchip Technology Inc.

DS40001569D-page 263

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate,

dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,

KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,

MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,

RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O

are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company,

ETHERSYNCH, Hyper Speed Control, HyperLight Load,

IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,

BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,

EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip

Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,

motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,

MPLINK, MultiTRAK, NetDetach, Omniscient Code

Generation, PICDEM, PICDEM.net, PICkit, PICtail,

PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,

Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

ISBN: 978-1-5224-0545-0

== ISO/TS 16949 ==

DS40001569D-page 264

 2011-2016 Microchip Technology Inc.

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

Germany - Dusseldorf

Tel: 49-2129-3766400

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Germany - Karlsruhe

Tel: 49-721-625370

India - Pune

Tel: 91-20-3019-1500

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Austin, TX

Tel: 512-257-3370

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Boston

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

China - Dongguan

Tel: 86-769-8702-9880

Italy - Venice

Tel: 39-049-7625286

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Hangzhou

Tel: 86-571-8792-8115

Fax: 86-571-8792-8116

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

Cleveland

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

Poland - Warsaw

Tel: 48-22-3325737

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Sweden - Stockholm

Tel: 46-8-5090-4654

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Detroit

Novi, MI

UK - Wokingham

Tel: 44-118-921-5800

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Tel: 248-848-4000

Fax: 44-118-921-5820

Houston, TX

Tel: 281-894-5983

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-213-7828

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

New York, NY

Tel: 631-435-6000

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

San Jose, CA

Tel: 408-735-9110

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Canada - Toronto

Tel: 905-673-0699

Fax: 905-673-6509

07/14/15

 2011-2016 Microchip Technology Inc.

DS40001569D-page 265


型号：	PIC16LF1906-I/MV
厂家：	MICROCHIP
描述：	8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQCC28, 4 X 4 MM, 0.50 MM HEIGHT, LEAD FREE, PLASTIC, UQFN-28 时钟微控制器外围集成电路
文件：	总265页 (文件大小：3106K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16LF1906-I/MV [MICROCHIP]

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