PIC16LC925-T/L [MICROCHIP]
64/68-Pin CMOS Microcontrollers with LCD Driver; 六十八分之六十四针CMOS微控制器与LCD驱动器
| 型号： | PIC16LC925-T/L |
| 厂家： | 
MICROCHIP |
| 描述： | 64/68-Pin CMOS Microcontrollers with LCD Driver |
| 文件： | 总182页 (文件大小：3150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16C925/926
Data Sheet
64/68-Pin CMOS Microcontrollers
with LCD Driver
2001 Microchip Technology Inc.
Preliminary
DS39544A
“All rights reserved. Copyright © 2001, Microchip Technology
Incorporated, USA. Information contained in this publication
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conveyed, implicitly or otherwise, under any intellectual prop-
erty rights.”
Trademarks
The Microchip name, logo, PIC, PICmicro, PICMASTER, PIC-
START, PRO MATE, KEELOQ, SEEVAL, MPLAB and The
Embedded Control Solutions Company are registered trade-
marks of Microchip Technology Incorporated in the U.S.A. and
other countries.
Total Endurance, ICSP, In-Circuit Serial Programming, Filter-
Lab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM,
MPLINK, MPLIB, PICDEM, ICEPIC, Migratable Memory,
FanSense, ECONOMONITOR, SelectMode and microPort
are trademarks of Microchip Technology Incorporated in the
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Serialized Quick Term Programming (SQTP) is a service mark
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© 2001, Microchip Technology Incorporated, Printed in the
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system for the design and manufacture of
development systems is ISO 9001 certified.
DS39544A - page ii
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
64/68-Pin CMOS Microcontrollers with LCD Driver
High Performance RISC CPU:
Analog Features:
• Only 35 single word instructions to learn
• 10-bit 5-channel Analog-to-Digital Converter (A/D)
• Brown-out Reset (BOR)
• All single cycle instructions except for program
branches which are two-cycle
Special Microcontroller Features:
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Power-on Reset (POR)
• Up to 8K x 14-bit words of EPROM program memory,
336 bytes general purpose registers (SRAM),
60 special function registers
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Pinout compatible with PIC16C923/924
• Programmable code protection
• Selectable oscillator options
Peripheral Features:
• 25 I/O pins with individual direction control and
25-27 input only pins
• In-Circuit Serial Programming™ (ICSP™) via
two pins
• Timer0 module: 8-bit timer/counter with program-
mable 8-bit prescaler
• Processor read access to program memory
• Timer1 module: 16-bit timer/counter, can be incre-
mented during SLEEP via external crystal/clock
CMOS Technology:
• Low power, high speed CMOS/EPROM
technology
• Timer2 module: 8-bit timer/counter with 8-bit
period register, prescaler, and postscaler
• Fully static design
• One Capture, Compare, PWM module
• Wide operating voltage range: 2.5V to 5.5V
• Commercial and Industrial temperature ranges
• Low power consumption
• Synchronous Serial Port (SSP) module with
two modes of operation:
- 3-wire SPI™ (supports all 4 SPI modes)
- I2C™ Slave mode
• Programmable LCD timing module:
- Multiple LCD timing sources available
- Can drive LCD panel while in SLEEP mode
- Static, 1/2, 1/3, 1/4 multiplex
- Static drive and 1/3 bias capability
- 16 bytes of dedicated LCD RAM
- Up to 32 segments, up to 4 commons
Common
Segment
Pixels
1
2
3
4
32
31
30
29
32
62
90
116
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 1
PIC16C925/926
Pin Diagrams
PLCC, CLCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
RA4/T0CKI
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
RD5/SEG29/COM3
RG6/SEG26
RG5/SEG25
RG4/SEG24
RG3/SEG23
RG2/SEG22
RG1/SEG21
RG0/SEG20
RG7/SEG28
RF7/SEG19
RF6/SEG18
RF5/SEG17
RF4/SEG16
RF3/SEG15
RF2/SEG14
RF1/SEG13
RF0/SEG12
RA5/AN4/SS
RB1
RB0/INT
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
C1
C2
VLCD2
VLCD3
AVDD
VDD
PIC16C92X
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
LEGEND:
Input Pin
Output Pin
Input/Output Pin
Digital Input/LCD Output Pin
LCD Output Pin
DS39544A-page 2
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
Pin Diagrams (Continued)
TQFP
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RD5/SEG29/COM3
RG6/SEG26
RG5/SEG25
RA4/T0CKI
RA5/AN4/SS
RB1
RB0/INT
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
C1
RG4/SEG24
RG3/SEG23
RG2/SEG22
RG1/SEG21
RG0/SEG20
RF7/SEG19
RF6/SEG18
RF5/SEG17
RF4/SEG16
RF3/SEG15
RF2/SEG14
RF1/SEG13
RF0/SEG12
9
C2
VLCD2
VLCD3
PIC16C92X
10
11
12
13
14
15
16
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
LEGEND:
Input Pin
Output Pin
Input/Output Pin
Digital Input/LCD Output Pin
LCD Output Pin
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 3
PIC16C925/926
Table of Contents
1.0 Device Overview ...................................................................................................................................................5
2.0 Memory Organization ..........................................................................................................................................11
3.0 Reading Program Memory.................................................................................................................................. 27
4.0 I/O Ports ..............................................................................................................................................................29
5.0 Timer0 Module ....................................................................................................................................................41
6.0 Timer1 Module ....................................................................................................................................................47
7.0 Timer2 Module ....................................................................................................................................................51
8.0 Capture/Compare/PWM (CCP) Module ..............................................................................................................53
9.0 Synchronous Serial Port (SSP) Module ..............................................................................................................59
10.0 Analog-to-Digital Converter (A/D) Module ...........................................................................................................75
11.0 LCD Module ........................................................................................................................................................83
12.0 Special Features of the CPU............................................................................................................................... 97
13.0 Instruction Set Summary ...................................................................................................................................113
14.0 Development Support .......................................................................................................................................133
15.0 Electrical Characteristics ...................................................................................................................................139
16.0 DC and AC Characteristics Graphs and Tables ................................................................................................159
17.0 Packaging Information ......................................................................................................................................161
Appendix A: Revision History.................................................................................................................................... 167
Appendix B: Device Differences ............................................................................................................................... 167
Appendix C: Conversion Considerations .................................................................................................................. 168
Index .......................................................................................................................................................................... 169
On-Line Support......................................................................................................................................................... 175
Reader Response ...................................................................................................................................................... 176
PIC16C925/926 Product Identification System.......................................................................................................... 177
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DS39544A-page 4
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
These devices come in 64-pin and 68-pin packages, as
well as die form. Both configurations offer identical
peripheral devices and other features. The only differ-
ence between the PIC16C925 and PIC16C926 is the
additional EPROM and data memory offered in the lat-
ter. An overview of features is presented in Table 1-1.
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
1. PIC16C925
2. PIC16C926
A UV-erasable, CERQUAD packaged version (compat-
ible with PLCC) is also available for both the
PIC16C925 and PIC16C926. This version is ideal for
cost effective code development.
The PIC16C925/926 series is a family of low cost, high
performance, CMOS, fully static, 8-bit microcontrollers
with an integrated LCD Driver module, in the
PIC16CXXX mid-range family.
A block diagram for the PIC16C925/926 family archi-
tecture is presented in Figure 1-1.
For the PIC16C925/926 family, there are two device
“types” as indicated in the device number:
1. C, as in PIC16C926. These devices operate
over the standard voltage range.
2. LC, as in PIC16LC926. These devices operate
over an extended voltage range.
TABLE 1-1:
PIC16C925/926 DEVICE FEATURES
Features
PIC16C925
PIC16C926
Operating Frequency
DC-20 MHz
DC-20 MHz
EPROM Program Memory (words)
Data Memory (bytes)
4K
8K
176
336
Timer Module(s)
TMR0,TMR1,TMR2
1
TMR0,TMR1,TMR2
1
Capture/Compare/PWM Module(s)
Serial Port(s)
SPI/I2C
SPI/I2C
(SPI/I2C, USART)
Parallel Slave Port
A/D Converter (10-bit) Channels
LCD Module
—
—
5
5
4 Com, 32 Seg
4 Com, 32 Seg
Interrupt Sources
I/O Pins
9
25
9
25
Input Pins
27
27
Voltage Range (V)
In-Circuit Serial Programming
Brown-out Reset
2.5-5.5
Yes
Yes
2.5-5.5
Yes
Yes
64-pin TQFP
68-pin PLCC
68-pin CLCC (CERQUAD)
Die
64-pin TQFP
68-pin PLCC
68-pin CLCC (CERQUAD)
Die
Packages
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 5
PIC16C925/926
FIGURE 1-1:
PIC16C925/926 BLOCK DIAGRAM
13
8
PORTA
Data Bus
Program Counter
RA0/AN0
RA1/AN1
EPROM
RA2/AN2
Program
Memory
RAM
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
8 Level Stack
(13-bit)
File
Registers
Program
Bus
14
RAM Addr
PORTB
9
Addr MUX
Instruction reg
RB0/INT
7
Direct Addr
Indirect
Addr
8
RB1-RB7
FSR reg
STATUS reg
MUX
PORTC
8
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
3
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
ALU
Power-on
Reset
PORTD
PORTE
PORTF
PORTG
8
Timing
Generation
Watchdog
Timer
W reg
RD0-RD4/SEGnn
OSC1/CLKIN
OSC2/CLKOUT
RD5-RD7/SEGnn/COMn
MCLR
VDD, VSS
RE0-RE7/SEGnn
RF0-RF7/SEGnn
RG0-RG7/SEGnn
Timer1, Timer2,
CCP1
Timer0
A/D
COM0
VLCD1
VLCD2
VLCD3
C1
Synchronous
Serial Port
LCD
C2
VLCDADJ
DS39544A-page 6
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
TABLE 1-2:
PIC16C925/926 PINOUT DESCRIPTION
PLCC,
CLCC
Pin#
TQFP
Pin#
Pin
Type
Buffer
Type
Pin Name
Description
OSC1/CLKIN
24
14
15
I
ST/CMOS
Oscillator crystal input or external clock source input. This
buffer is a Schmitt Trigger input when configured in RC
oscillator mode and a CMOS input otherwise.
OSC2/CLKOUT
MCLR/VPP
25
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT, which has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
2
57
I/P
ST
Master Clear (Reset) input or programming voltage input. This
pin is an active low RESET to the device.
PORTA is a bi-directional I/O port.
RA0 can also be Analog input0.
RA1 can also be Analog input1.
RA2 can also be Analog input2.
RA0/AN0
5
6
8
9
60
61
63
64
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA3 can also be Analog input3 or A/D Voltage
Reference.
RA4/T0CKI
10
11
1
2
I/O
I/O
ST
RA4 can also be the clock input to the Timer0
timer/counter. Output is open drain type.
RA5/AN4/SS
TTL
RA5 can be the slave select for the synchronous serial port
or Analog input4.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT
13
4
I/O
TTL/ST
RB0 can also be the external interrupt pin. This buffer is a
Schmitt Trigger input when configured as an
external interrupt.
RB1
RB2
RB3
RB4
RB5
RB6
12
4
3
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
59
58
56
55
53
3
TTL
68
67
65
TTL
Interrupt-on-change pin.
Interrupt-on-change pin.
TTL
TTL/ST
Interrupt-on-change pin. Serial programming clock. This
buffer is a Schmitt Trigger input when used in Serial
Programming mode.
RB7
66
54
I/O
TTL/ST
Interrupt-on-change pin. Serial programming data. This
buffer is a Schmitt Trigger input when used in Serial
Programming mode.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
26
16
I/O
ST
RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI
RC2/CCP1
27
28
17
18
I/O
I/O
ST
ST
RC1 can also be the Timer1 oscillator input.
RC2 can also be the Capture1 input/Compare1
output/PWM1 output.
RC3/SCK/SCL
RC4/SDI/SDA
14
15
5
6
I/O
I/O
ST
ST
ST
RC3 can also be the synchronous serial clock input/
output for both SPI and I C modes.
2
RC4 can also be the SPI Data In (SPI mode) or
2
data I/O (I C mode).
RC5/SDO
16
17
18
63
7
I/O
P
RC5 can also be the SPI Data Out (SPI mode).
LCD Voltage Generation.
LCD Voltage Generation.
Common Driver0.
C1
8
C2
9
51
P
COM0
L
Legend: I = input
O = output
P = power
L = LCD Driver
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 7
PIC16C925/926
TABLE 1-2:
PIC16C925/926 PINOUT DESCRIPTION (CONTINUED)
PLCC,
CLCC
Pin#
TQFP
Pin#
Pin
Type
Buffer
Type
Pin Name
Description
PORTD is a digital input/output port. These pins are also used
as LCD Segment and/or Common Drivers.
RD0/SEG00
31
32
33
34
35
60
61
62
21
22
23
24
25
48
49
50
I/O/L
I/O/L
I/O/L
I/O/L
I/O/L
I/L
ST
ST
ST
ST
ST
ST
ST
ST
Segment Driver 00/Digital input/output.
Segment Driver 01/Digital input/output.
Segment Driver 02/Digital input/output.
Segment Driver 03/Digital input/output.
Segment Driver04/Digital input/output.
Segment Driver29/Common Driver 3/Digital input.
Segment Driver30/Common Driver 2/Digital input.
Segment Driver31/Common Driver 1/Digital input.
PORTE is a Digital input or LCD Segment Driver port.
Segment Driver 05.
RD1/SEG01
RD2/SEG02
RD3/SEG03
RD4/SEG04
RD5/SEG29/COM3
RD6/SEG30/COM2
RD7/SEG31/COM1
I/L
I/L
RE0/SEG05
RE1/SEG06
RE2/SEG07
RE3/SEG08
RE4/SEG09
RE5/SEG10
RE6/SEG11
RE7/SEG27
37
38
39
40
41
42
43
36
26
27
28
29
30
31
32
-
I/L
I/L
I/L
I/L
I/L
I/L
I/L
I/L
ST
ST
ST
ST
ST
ST
ST
ST
Segment Driver 06.
Segment Driver 07.
Segment Driver 08.
Segment Driver 09.
Segment Driver 10.
Segment Driver 11.
Segment Driver 27 (not available on 64-pin devices).
PORTF is a Digital input or LCD Segment Driver port.
Segment Driver 12.
RF0/SEG12
RF1/SEG13
RF2/SEG14
RF3/SEG15
RF4/SEG16
RF5/SEG17
RF6/SEG18
RF7/SEG19
44
45
46
47
48
49
50
51
33
34
35
36
37
38
39
40
I/L
I/L
I/L
I/L
I/L
I/L
I/L
I/L
ST
ST
ST
ST
ST
ST
ST
ST
Segment Driver 13.
Segment Driver 14.
Segment Driver 15.
Segment Driver 16.
Segment Driver 17.
Segment Driver 18.
Segment Driver 19.
PORTG is a Digital input or LCD Segment Driver port.
Segment Driver 20.
RG0/SEG20
RG1/SEG21
RG2/SEG22
RG3/SEG23
RG4/SEG24
RG5/SEG25
RG6/SEG26
RG7/SEG28
VLCDADJ
AVDD
53
54
41
42
I/L
I/L
I/L
I/L
I/L
I/L
I/L
I/L
P
ST
ST
ST
ST
ST
ST
ST
ST
—
Segment Driver 21.
55
43
Segment Driver 22.
56
44
Segment Driver 23.
57
45
Segment Driver 24.
58
46
Segment Driver 25.
59
47
Segment Driver 26.
52
—
Segment Driver 28 (not available on 64-pin devices).
LCD Voltage Generation.
30
20
21
—
P
—
Analog Power (PLCC and CLCC packages only).
LCD Voltage.
VLCD1
29
19
P
—
VLCD2
19
10
P
—
LCD Voltage.
VLCD3
20
11
P
—
LCD Voltage.
VDD
22, 64
7, 23
1
12, 52
13, 62
—
P
—
Digital power.
VSS
P
—
Ground reference.
NC
—
—
These pins are not internally connected. These pins should be
left unconnected.
Legend: I = input
O = output
P = power
L = LCD Driver
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
DS39544A-page 8
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
1.1
Clocking Scheme/Instruction
Cycle
1.2
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined, such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO),
then two cycles are required to complete the instruction
(Example 1-1).
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 1-2.
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” in cycle Q1. This instruc-
tion is then decoded and executed during the Q2, Q3,
and Q4 cycles. Data memory is read during Q2 (oper-
and read) and written during Q4 (destination write).
FIGURE 1-2:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
Phase
Clock
Q4
PC
PC
PC+1
PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 1-1:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 9
PIC16C925/926
NOTES:
DS39544A-page 10
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
The PIC16C925/926 family has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space.
For the PIC16C925, only the first 4K x 14 (0000h-
0FFFh) are physically implemented. Accessing a loca-
tion above the physically implemented addresses will
cause a wraparound. The RESET vector is at 0000h
and the interrupt vector is at 0004h.
FIGURE 2-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC16C926
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC16C925
PC<12:0>
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
Stack Level 8
RESET Vector
0000h
0000h
Interrupt Vector
Page 0
0004h
0005h
Interrupt Vector
Page 0
0004h
0005h
07FFh
0800h
On-chip
Program
Memory
07FFh
0800h
Page 1
On-chip
Program
Memory
Page 1
0FFFh
1000h
0FFFh
1000h
Page 2
Page 3
17FFh
1800h
Reads
0000h-0FFFh
1FFFh
2000h
1FFFh
2000h
2003h
ID Locations
Reserved
2003h
2004h
ID Locations
Reserved
2004h
2007h
2007h
Configuration Word
Configuration Word
Reserved
3FFFh
Reserved
3FFFh
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 11
PIC16C925/926
2.2.1
GENERAL PURPOSE REGISTER
FILE
2.2
Data Memory Organization
The data memory is partitioned into four banks which
contain the General Purpose Registers and the Special
Function Registers. Bits RP1 and RP0 are the bank
select bits.
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR
(Section 2.6).
The following General Purpose Registers are not phys-
ically implemented:
RP1:RP0
Bank
(STATUS<6:5>)
• F0h-FFh of Bank 1
• 170h-17Fh of Bank 2
• 1F0h-1FFh of Bank 3
11
10
01
00
3 (180h-1FFh)
2 (100h-17Fh)
1 (80h-FFh)
0 (00h-7Fh)
These locations are used for common access across
banks.
The lower locations of each Bank are reserved for the
Special Function Registers. Above the Special Func-
tion Registers are General Purpose Registers imple-
mented as static RAM. All four banks contain special
function registers. Some “high use” special function
registers are mirrored in other banks for code reduction
and quicker access.
DS39544A-page 12
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
FIGURE 2-3:
REGISTER FILE MAP — PIC16C925
File
Address
File
Address
File
Address
File
Address
Indirect addr.(*)
Indirect addr.(*)
OPTION
PCL
Indirect addr.(*)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
Indirect addr.(*)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
TMR0
TMR0
PCL
OPTION
PCL
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
TRISA
TRISB
TRISC
TRISD
TRISE
TRISB
TRISF
TRISG
PORTB
PORTF
PORTG
PCLATH
INTCON
PMCON1
LCDSE
PCLATH
INTCON
PMDATA
PCLATH
INTCON
PIE1
PMADR
PMDATH
PMADRH
TMR1L
TMR1H
LCDPS
PCON
LCDCON
LCDD00
T1CON
TMR2
LCDD01
LCDD02
LCDD03
LCDD04
LCDD05
LCDD06
LCDD07
LCDD08
LCDD09
LCDD10
LCDD11
LCDD12
LCDD13
LCDD14
T2CON
PR2
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
SSPADD
SSPSTAT
ADRESH
ADCON0
ADRESL
ADCON1
LCDD15
1A0h
A0h
General
Purpose
Register
General
Purpose
Register
1EFh
1F0h
EFh
F0h
16Fh
170h
accesses
70h - 7Fh
accesses
70h - 7Fh
accesses
70h - 7Fh
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Bank 0
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 13
PIC16C925/926
FIGURE 2-4:
REGISTER FILE MAP— PIC16C926
File
Address
File
Address
File
Address
File
Address
Indirect addr.(*)
Indirect addr.(*)
OPTION
PCL
Indirect addr.(*)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
Indirect addr.(*)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
TMR0
TMR0
PCL
OPTION
PCL
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
TRISA
TRISB
TRISC
TRISD
TRISE
TRISB
TRISF
TRISG
PORTB
PORTF
PORTG
PCLATH
INTCON
PMCON1
LCDSE
PCLATH
INTCON
PMDATA
PCLATH
INTCON
PIE1
PMADR
PMDATH
PMADRH
TMR1L
TMR1H
LCDPS
PCON
LCDCON
LCDD00
LCDD01
LCDD02
LCDD03
LCDD04
LCDD05
LCDD06
LCDD07
LCDD08
LCDD09
LCDD10
LCDD11
LCDD12
LCDD13
LCDD14
T1CON
TMR2
T2CON
PR2
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
SSPADD
SSPSTAT
ADRESL
ADCON1
ADRESH
ADCON0
LCDD15
1A0h
A0h
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
96 Bytes
General
Purpose
Register
80 Bytes
BFh
C0h
EFh
F0h
1EFh
1F0h
16Fh
170h
accesses
70h - 7Fh
accesses
70h - 7Fh
accesses
70h - 7Fh
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Bank 0
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
DS39544A-page 14
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
The special function registers can be classified into two
sets, core and peripheral. Those registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
2.3
Special Function Registers
The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for control-
ling the desired operation of the device. These regis-
ters are implemented as static RAM.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on
Power-on
Reset
Details on
page
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--0x 0000
xxxx xxxx
--xx xxxx
0000 0000
0000 0000
---0 0000
0000 000x
00-- 0000
—
26
41
25
19
26
29
31
33
34
36
25
21
23
—
TMR0
PCL
Program Counter (PC) Least Significant Byte
STATUS
FSR
IRP
Indirect Data Memory Address Pointer
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
RP1
RP0
TO
PD
Z
DC
C
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
—
—
—
—
PORTD Data Latch when written: PORTD pins when read
PORTE pins when read
—
—
—
TMR0IE
—
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
ADIF
INTE
RBIE
TMR0IF
CCP1IF
INTF
RBIF
LCDIF
—
SSPIF
TMR2IF
TMR1IF
—
Unimplemented
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
—
Holding register for the Least Significant Byte of the 16-bit TMR1 Register
Holding register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
xxxx xxxx
47
47
47
51
52
64, 72
60
58
58
53
—
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON --00 0000
Timer2 Module Register
0000 0000
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
Capture/Compare/PWM Register (LSB)
Capture/Compare/PWM Register (MSB)
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0 --00 0000
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADRESH
A/D Result Register High
ADCS1 ADCS0
xxxx xxxx
80, 81
1Fh
ADCON0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 0000
75
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These pixels do not display, but can be used as general purpose RAM.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 15
PIC16C925/926
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
Power-on
Reset
Details on
page
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
1111 1111
--11 1111
1111 1111
1111 1111
---0 0000
0000 000x
26
20
25
19
26
29
31
33
34
36
25
21
24
—
81h
OPTION
PCL
RBPU
Program Counter (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect Data Memory Address Pointer
PORTA Data Direction Register
PORTB Data Direction Register
PORTC Data Direction Register
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
82h
83h
STATUS
FSR
PD
Z
DC
C
84h
85h
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
—
—
86h
87h
—
—
88h
PORTD Data Direction Register
PORTE Data Direction Register
89h
8Ah
8Bh
8Ch
8Dh
—
—
—
TMR0IE
—
Write Buffer for the upper 5 bits of the PC
GIE
PEIE
ADIE
INTE
RBIE
TMR0IF
CCP1IE
INTF
RBIF
LCDIE
—
SSPIE
TMR2IE
TMR1IE 00-- 0000
—
Unimplemented
—
8Eh
8Fh
90h
91h
92h
93h
PCON
—
—
—
—
—
—
—
POR
BOR
---- --0-
24
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
PR2
SSPADD
Timer2 Period Register
Synchronous Serial Port (I2C mode) Address Register
1111 1111
0000 0000
51
69, 72
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
59
—
—
—
—
—
—
—
—
—
79
76
95h
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
96h
—
—
97h
—
—
98h
—
—
99h
—
—
—
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
—
—
—
—
—
—
—
ADRESL
ADCON1
A/D Result Register Low
xxxx xxxx
---- -000
—
—
—
—
—
PCFG2
PCFG1
PCFG0
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These pixels do not display, but can be used as general purpose RAM.
DS39544A-page 16
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
Power-on
Reset
Details on
page
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
—
26
41
25
19
26
—
TMR0
PCL
Program Counter (PC) Least Significant Byte
STATUS
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
Unimplemented
—
PORTB
PORTF
PORTG
—
PORTB Data Latch when written: PORTB pins when read
PORTF pins when read
xxxx xxxx
0000 0000
0000 0000
—
31
37
38
—
PORTG pins when read
Unimplemented
PCLATH
INTCON
PMCON1
—
—
PEIE
—
—
TMR0IE
—
Write Buffer for the upper 5 bits of the PC
---0 0000
0000 000x
1--- ---0
25
21
27
GIE
INTE
RBIE
TMR0IF
INTF
RBIF
RD
reserved
—
—
—
—
10Dh
10Eh
10Fh
110h
LCDSE
SE29
—
SE27
—
SE20
—
SE16
—
SE12
LP3
SE9
LP2
CS0
SE5
LP1
SE0
1111 1111
---- 0000
00-0 0000
xxxx xxxx
94
84
83
92
LCDPS
LP0
LCDCON
LCDD00
LCDEN
SLPEN
—
VGEN
CS1
LMUX1
LMUX0
SEG07
COM0
SEG06
COM0
SEG05
COM0
SEG04
COM0
SEG03
COM0
SEG02
COM0
SEG01
COM0
SEG00
COM0
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
Legend:
LCDD01
LCDD02
LCDD03
LCDD04
LCDD05
LCDD06
LCDD07
LCDD08
LCDD09
LCDD10
LCDD11
LCDD12
LCDD13
LCDD14
LCDD15
SEG15
COM0
SEG14
COM0
SEG13
COM0
SEG12
COM0
SEG11
COM0
SEG10
COM0
SEG09
COM0
SEG08
COM0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
SEG23
COM0
SEG22
COM0
SEG21
COM0
SEG20
COM0
SEG19
COM0
SEG18
COM0
SEG17
COM0
SEG16
COM0
SEG31
COM0
SEG30
COM0
SEG29
COM0
SEG28
COM0
SEG27
COM0
SEG26
COM0
SEG25
COM0
SEG24
COM0
SEG07
COM1
SEG06
COM1
SEG05
COM1
SEG04
COM1
SEG03
COM1
SEG02
COM1
SEG01
COM1
SEG00
COM1
SEG15
COM1
SEG14
COM1
SEG13
COM1
SEG12
COM1
SEG11
COM1
SEG10
COM1
SEG09
COM1
SEG08
COM1
SEG23
COM1
SEG22
COM1
SEG21
COM1
SEG20
COM1
SEG19
COM1
SEG18
COM1
SEG17
COM1
SEG16
COM1
SEG31
SEG30
COM1
SEG29
COM1
SEG28
COM1
SEG27
COM1
SEG26
COM1
SEG25
COM1
SEG24
COM1
COM1(1)
SEG07
COM2
SEG06
COM2
SEG05
COM2
SEG04
COM2
SEG03
COM2
SEG02
COM2
SEG01
COM2
SEG00
COM2
SEG15
COM2
SEG14
COM2
SEG13
COM2
SEG12
COM2
SEG11
COM2
SEG10
COM2
SEG09
COM2
SEG08
COM2
SEG23
COM2
SEG22
COM2
SEG21
COM2
SEG20
COM2
SEG19
COM2
SEG18
COM2
SEG17
COM2
SEG16
COM2
SEG31
SEG30
SEG29
COM2
SEG28
COM2
SEG27
COM2
SEG26
COM2
SEG25
COM2
SEG24
COM2
COM2(1)
COM2(1)
SEG07
COM3
SEG06
COM3
SEG05
COM3
SEG04
COM3
SEG03
COM3
SEG02
COM3
SEG01
COM3
SEG00
COM3
SEG15
COM3
SEG14
COM3
SEG13
COM3
SEG12
COM3
SEG11
COM3
SEG10
COM3
SEG09
COM3
SEG08
COM3
SEG23
COM3
SEG22
COM3
SEG21
COM3
SEG20
COM3
SEG19
COM3
SEG18
COM3
SEG17
COM3
SEG16
COM3
SEG31
SEG30
SEG29
SEG28
COM3
SEG27
COM3
SEG26
COM3
SEG25
COM3
SEG24
COM3
COM3(1)
COM3(1)
COM3(1)
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These pixels do not display, but can be used as general purpose RAM.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 17
PIC16C925/926
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
Power-on
Reset
Details on
page
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 3
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
—
26
20
25
19
26
—
OPTION
PCL
RBPU
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
STATUS
FSR
PD
Z
DC
C
Indirect Data Memory Address Pointer
Unimplemented
—
TRISB
TRISF
TRISG
—
PORTB Data Direction Register
PORTF Data Direction Register
PORTG Data Direction Register
Unimplemented
1111 1111
1111 1111
1111 1111
—
31
37
38
—
PCLATH
INTCON
PMDATA
—
—
—
Write Buffer for the upper 5 bits of the PC
INTE RBIE TMR0IF
---0 0000
0000 000x
xxxx xxxx
25
21
27
GIE
PEIE
TMR0IE
INTF
RBIF
Data Register Low Byte
18Dh
18Eh
18Fh
PMADR
Address Register Low Byte
xxxx xxxx
xxxx xxxx
xxxx xxxx
27
27
27
PMDATH
PMADRH
—
—
—
—
Data Register High Byte
—
Address Register High Byte
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
Legend:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These pixels do not display, but can be used as general purpose RAM.
DS39544A-page 18
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
2.3.1
STATUS REGISTER
The STATUS register, shown in Register 2-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
“Instruction Set Summary.”
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1:
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
0= Bank 0, 1 (00h - FFh)
bit 6-5
RP1:RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)
(for borrow the polarity is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow the polarity is reversed)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note: A subtraction is executed by adding the two’s complement of the second operand.
For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order
bit of the source register.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 19
PIC16C925/926
2.3.2
OPTION REGISTER
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
The OPTION register is a readable and writable regis-
ter, which contains various control bits to configure the
TMR0/WDT prescaler, the external RB0/INT pin inter-
rupt, TMR0, and the weak pull-ups on PORTB.
REGISTER 2-2:
OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
DS39544A-page 20
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
2.3.3
INTCON REGISTER
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
The INTCON Register is a readable and writable regis-
ter which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and external
RB0/INT pin interrupts.
REGISTER 2-3:
INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
R/W-0
INTE
R/W-0
RBIE
R/W-0
R/W-0
INTF
R/W-x
RBIF
TMR0IE
TMR0IF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1= Enables all unmasked interrupts
0= Disables all interrupts
PEIE/GEIL: Peripheral Interrupt Enable bit
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INTE: RB0/INT0 External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT0 External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 21
PIC16C925/926
2.3.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
This register contains the individual enable bits for the
peripheral interrupts.
enable any peripheral interrupt.
REGISTER 2-4:
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
LCDIE
R/W-0
ADIE
U-0
U-0
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
TMR1IE
bit 0
—
—
CCP1IE
TMR2IE
bit 7
bit 7
bit 6
LCDIE: LCD Interrupt Enable bit
1= Enables the LCD interrupt
0= Disables the LCD interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
bit 5-4
bit 3
Unimplemented: Read as ‘0’
SSPIE: Synchronous Serial Port Interrupt Enable bit
1= Enables the SSP interrupt
0= Disables the SSP interrupt
bit 2
bit 1
bit 0
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39544A-page 22
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
2.3.5
PIR1 REGISTER
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5:
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
LCDIF
R/W-0
ADIF
U-0
U-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
—
—
CCP1IF TMR2IF TMR1IF
bit 0
bit 7
bit 7
bit 6
LCDIF: LCD Interrupt Flag bit
1= LCD interrupt has occurred (must be cleared in software)
0= LCD interrupt did not occur
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
bit 5-4
Unimplemented: Read as ‘0’
bit 3
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 23
PIC16C925/926
2.3.6
PCON REGISTER
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
For various RESET conditions, see Table 12-4 and
Table 12-5.
REGISTER 2-6:
PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
POR
R/W-1
BOR
—
—
—
—
—
—
bit 7
bit 0
bit 7-2
bit 1
Unimplemented: Read as '0'
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39544A-page 24
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
2.4
PCL and PCLATH
Note 1: There are no status bits to indicate stack
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will be cleared. Figure 2-5 shows the two situations
for the loading of the PC. The upper example in the fig-
ure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig-
ure shows how the PC is loaded during a CALLor GOTO
instruction (PCLATH<4:3> → PCH).
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW, and RETFIE
instructions, or the vectoring to an
interrupt address.
2.5
Program Memory Paging
PIC16C925/926 devices are capable of addressing a
continuous 8K word block of program memory. The
CALL and GOTO instructions provide only 11-bits of
address to allow branching within any 2K program
memory page. When doing a CALLor GOTOinstruction,
the upper 2-bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruc-
tion, the user must ensure that the page select bits are
programmed so that the desired program memory
page is addressed. If a return from a CALLinstruction
(or interrupt) is executed, the entire 13-bit PC is pushed
onto the stack. Therefore, manipulation of the
PCLATH<4:3> bits is not required for the RETURN
instructions (which POPs the address from the stack).
FIGURE 2-5:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
Instruction with
PCL as
Destination
PC
8
PCLATH<4:0>
PCLATH
5
ALU Result
PCH
12 11 10
PC
PCL
8
7
0
Note: The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the PCLATH for any subsequent
CALLor GOTOinstructions.
GOTO, CALL
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine (if interrupts are used).
2.4.1
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read” (AN556).
EXAMPLE 2-1:
CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
ORG 0x500
BCF
BSF
PCLATH,4
PCLATH,3 ;Select page 1 (800h-FFFh)
2.4.2
STACK
CALL
SUB1_P1
;Call subroutine in
;page 1 (800h-FFFh)
:
:
:
The PIC16CXXX family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
ORG 0x900
SUB1_P1:
;called subroutine
;page 1 (800h-FFFh)
:
:
RETURN
;return to Call subroutine
;in page 0 (000h-7FFh)
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 25
PIC16C925/926
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
2.6
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 2-2:
INDIRECT ADDRESSING
MOVLW 0x20
MOVWF FSR
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister (FSR). Reading the INDF register itself, indirectly
(FSR = ’0’), will produce 00h. Writing to the INDF regis-
ter indirectly results in a no operation (although status
bits may be affected). An effective 9-bit address is
obtained by concatenating the 8-bit FSR register and
the IRP bit (STATUS<7>), as shown in Figure 2-6.
NEXT
CLRF INDF
INCF FSR,F
BTFSS FSR,4
GOTO NEXT
CONTINUE
:
;yes continue
FIGURE 2-6:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
From Opcode
7
RP1:RP0
6
0
0
IRP
FSR Register
Bank Select
00h
Location Select
Bank Select
Location Select
00
01
10
11
00h
Data
Memory
7Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
Note: For memory map detail, see Figure 2-3.
DS39544A-page 26
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
When interfacing to the program memory block, the
PMDATH:PMDATA registers form a two-byte word,
which holds the 14-bit data for reads. The
PMADRH:PMADR registers form a two-byte word,
which holds the 13-bit address of the location being
accessed. These devices can have from 4K words to
8K words of program memory, with an address range
from 0h to 3FFFh.
3.0
READING PROGRAM MEMORY
The Program Memory is readable during normal oper-
ation over the entire VDD range. It is indirectly
addressed through Special Function Registers (SFR).
Up to 14-bit numbers can be stored in memory for use
as calibration parameters, serial numbers, packed 7-bit
ASCII, etc. Executing a program memory location con-
taining data that forms an invalid instruction results in a
NOP.
The unused upper bits in both the PMDATH and
PMADRH registers are not implemented and read as
“0’s”.
There are five SFRs used to read the program and
memory. These registers are:
3.1
PMADR
• PMCON1
• PMDATA
• PMDATH
• PMADR
The address registers can address up to a maximum of
8K words of program memory.
When selecting a program address value, the MSByte
of the address is written to the PMADRH register and
the LSByte is written to the PMADR register. The upper
MSbits of PMADRH must always be clear.
• PMADRH
The program memory allows word reads. Program
memory access allows for checksum calculation and
reading calibration tables.
3.2
PMCON1 Register
PMCON1 is the control register for memory accesses.
The control bit RD initiates read operations. This bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the read operation.
REGISTER 3-1: PMCON1 REGISTER (ADDRESS 10Ch)
R-1
r
U-0
U-0
U-0
U-x
U-0
U-0
R/S-0
RD
—
—
—
—
—
—
bit 7
bit 0
bit 7
Reserved: Read as ‘1’
bit 6-1
bit 0
Unimplemented: Read as ‘0’
RD: Read Control bit
1= Initiates a read, RD is cleared in hardware. The RD bit can only be set (not cleared)
in software.
0= Does not initiate a read
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 27
PIC16C925/926
data is available in the PMDATA and PMDATH regis-
ters after the NOPinstruction. Therefore, it can be read
as two bytes in the following instructions. The PMDATA
and PMDATH registers will hold this value until another
read operation.
3.3
Reading the Program Memory
A program memory location may be read by writing two
bytes of the address to the PMADR and PMADRH reg-
isters, and then setting control bit RD (PMCON1<0>).
Once the read control bit is set, the microcontroller will
use the next two instruction cycles to read the data. The
EXAMPLE 3-1:
PROGRAM READ
BSF
STATUS, RP1
;
BSF
STATUS, RP0
MS_PROG_PM_ADDR
PMADRH
LS_PROG_PM_ADDR
PMADR
; Bank 3
;
MOVLW
MOVWF
MOVLW
MOVWF
BCF
; MS Byte of Program Address to read
;
; LS Byte of Program Address to read
; Bank 2
STATUS, RP0
PMCON1, RD
BSF
; PM Read
;
; First instruction after BSF PMCON1,RD executes normally
; Bank 3
BSF
STATUS, RP0
;
NOP
; Any instructions here are ignored as program
; memory is read in second cycle after BSF PMCON1,RD
;
MOVF
MOVF
PMDATA, W
PMDATH, W
; W = LS Byte of Program PMDATA
; W = MS Byte of Program PMDATA
3.4
Operation During Code Protect
If only part of the program memory is code protected,
the program memory control can read the unprotected
segment and cannot read the protected segment. The
protected area cannot be read, because it may be
possible to write a downloading routine into the
unprotected segment.
If the program memory is not code protected, the pro-
gram memory control can read anywhere within the
program memory.
If the entire program memory is code protected, the
program memory control can read anywhere within the
program memory.
TABLE 3-1:
REGISTERS ASSOCIATED WITH PROGRAM MEMORY
Value on
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS
10Ch
18Ch
PMCON1
(1)
—
—
—
—
—
—
RD
1--- ---0 1--- ---0
xxxx xxxx uuuu uuuu
PMDATA Data Register Low Byte
18Dh
18Eh
18Fh
PMADR
Address Register Low Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
PMDATH
PMADRH
—
—
—
—
Data Register High Byte
Address Register High Byte
—
Legend: x= unknown, u= unchanged, r = reserved, -= unimplemented, read as '0'.
Shaded cells are not used during FLASH access.
Note 1: This bit always reads as a ‘1’.
DS39544A-page 28
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
FIGURE 4-1:
BLOCK DIAGRAM OF
PINS RA3:RA0 AND RA5
4.0
I/O PORTS
Some pins for these ports are multiplexed with an alter-
nate function for the peripheral features on the device.
In general, when a peripheral is enabled, that pin may
not be used as a general purpose I/O pin.
Data
Bus
D
Q
VDD
WR
Port
4.1
PORTA and TRISA Register
Q
CK
P
N
Data Latch
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input levels and full CMOS output drivers. All RA pins
have data direction bits (TRISA register), which can
configure these pins as output or input.
I/O pin(1)
D
Q
WR
TRIS
VSS
Q
CK
Setting a bit in the TRISA register puts the correspond-
ing output driver in a Hi-Impedance mode. Clearing a
bit in the TRISA register puts the contents of the output
latch on the selected pin.
Analog
Input Mode
TRIS Latch
RD
TRIS
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
TTL
Input
Buffer
Q
D
EN
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The other PORTA
pins are multiplexed with analog inputs and the analog
VREF input. The operation of each pin is selected by
clearing/setting the control bits in the ADCON1 register
(A/D Control Register1).
RD Port
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and VSS.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as ’0’.
FIGURE 4-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Data
Bus
D
Q
Q
WR
Port
CK
EXAMPLE 4-1:
INITIALIZING PORTA
I/O pin(1)
N
BCF
BCF
CLRF
BSF
STATUS, RP0 ; Select Bank0
STATUS, RP1
Data Latch
D
Q
VSS
PORTA
; Initialize PORTA
WR
TRIS
STATUS, RP0 ; Select Bank1
Schmitt
Trigger
Input
MOVLW 0xCF
MOVWF TRISA
; Value used to
; initialize data
; direction
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; RA<7:6> are always
CK
Q
TRIS Latch
Buffer
RD
TRIS
; read as ’0’.
Q
D
EN
RD Port
TMR0 Clock Input
Note 1: I/O pin has protection diodes to VSS only.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 29
PIC16C925/926
TABLE 4-1:
PORTA FUNCTIONS
Name
Bit#
Buffer
Function
RA0/AN0
bit0
bit1
bit2
bit3
bit4
bit5
TTL
TTL
TTL
TTL
ST
Input/output or analog input.
Input/output or analog input.
Input/output or analog input.
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
Input/output or analog input or VREF.
Input/output or external clock input for Timer0. Output is open drain type.
Input/output or analog input or slave select input for synchronous serial port.
TTL
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 4-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
Power-on
Reset
Value on
all other
RESETS
Address
Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h
85h
9Fh
PORTA
TRISA
—
—
—
—
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000 --0x 0000
--11 1111 --11 1111
PORTA Data Direction Control Register
ADCON1
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by PORTA.
DS39544A-page 30
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
Four of the PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are OR’ed together to generate the RB Port
Change Interrupt with flag bit RBIF (INTCON<0>).
4.2
PORTB and TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a Hi-Impedance Input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
EXAMPLE 4-2:
INITIALIZING PORTB
STATUS, RP0 ; Select Bank0
STATUS, RP1
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
BCF
BCF
CLRF
BSF
PORTB
; Initialize PORTB
STATUS, RP0 ; Select Bank1
a) Any read or write of PORTB. This will end the
mismatch condition.
MOVLW 0xCF
; Value used to
; initialize data
; direction
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
MOVWF TRISB
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
This interrupt-on-mismatch feature, together with soft-
ware configurable pull-ups on these four pins, allow easy
interface to a keypad and make it possible for wake-up on
key depression. Refer to the Embedded Control Hand-
book, “Implementing Wake-Up on Key Stroke” (AN552).
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are also disabled
on a Power-on Reset.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 4-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
VDD
RBPU(2)
Weak
FIGURE 4-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
P
Pull-up
Data Latch
Data Bus
WR Port
D
Q
VDD
I/O
RBPU(2)
Weak
P
pin(1)
CK
TRIS Latch
Pull-up
Data Latch
Data Bus
WR Port
D
Q
Q
D
TTL
I/O
pin(1)
Input
Buffer
CK
TRIS Latch
WR TRIS
CK
D
Q
RD TRIS
RD Port
WR TRIS
RD TRIS
TTL
Input
Buffer
CK
ST
Buffer
Q
D
EN
Latch
Schmitt Trigger
Buffer
Q
D
RB0/INT
RD Port
EN
Q1
RD Port
Set RBIF
Note 1: I/O pins have diode protection to VDD and VSS.
Q
D
2: To enable weak pull-ups, set the appropriate TRIS
RD Port
Q3
bit(s) and clear the RBPU bit (OPTION<7>).
From other
RB7:RB4 pins
EN
RB7:RB6 in Serial Programming Mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION<7>).
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 31
PIC16C925/926
TABLE 4-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0/INT
bit0
TTL/ST
Input/output pin or external interrupt input. Internal software
programmable weak pull-up. This buffer is a Schmitt Trigger input when
configured as the external interrupt.
RB1
RB2
RB3
RB4
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
RB6
bit5
bit6
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
TTL/ST
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming clock. This buffer is a Schmitt Trigger
input when used in Serial Programming mode.
RB7
bit7
TTL/ST
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming data. This buffer is a Schmitt Trigger
input when used in Serial Programming mode.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 4-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
Power-on
Reset
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
06h, 106h PORTB
86h, 186h TRISB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
1111 1111 1111 1111
PORTB Data Direction Control Register
T0SE
81h, 181h OPTION RBPU INTEDG T0CS
PSA
PS2
PS1
PS0
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS39544A-page 32
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
FIGURE 4-5:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
4.3
PORTC and TRISC Register
PORTC is a 6-bit, bi-directional port. Each pin is individ-
ually configurable as an input or output through the
TRISC register. PORTC is multiplexed with several
peripheral functions (Table 4-5). PORTC pins have
Schmitt Trigger input buffers.
VDD
RBPU(2)
Weak
P
Pull-up
Data Latch
Data Bus
WR Port
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-
modify-write instructions (BSF, BCF, XORWF) with
TRISC as destination should be avoided. The user
should refer to the corresponding peripheral section for
the correct TRIS bit settings.
D
Q
I/O
pin(1)
CK
TRIS Latch
D
Q
TTL
Input
Buffer
WR TRIS
CK
RD TRIS
RD Port
Q
D
EXAMPLE 4-3:
INITIALIZING PORTC
STATUS,RP0 ; Select Bank0
BCF
BCF
CLRF
BSF
EN
STATUS,RP1
PORTC
; Initialize PORTC
RB0/INT
STATUS,RP0 ; Select Bank1
MOVLW 0xCF
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> always read 0
Schmitt Trigger
Buffer
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
MOVWF TRISC
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION<7>).
TABLE 4-5:
Name
PORTC FUNCTIONS
Bit# Buffer Type
Function
RC0/T1OSO/T1CKI
RC1/T1OSI
bit0
bit1
bit2
bit3
ST
ST
ST
ST
Input/output port pin or Timer1 oscillator output or Timer1 clock input.
Input/output port pin or Timer1 oscillator input.
RC2/CCP1
Input/output port pin or Capture input/Compare output/PWM output.
RC3/SCK/SCL
Input/output port pin or the synchronous serial clock for both SPI and
I2C modes.
RC4/SDI/SDA
bit4
ST
ST
Input/output port pin or the SPI Data In (SPI mode) or data I/O
(I2C mode).
RC5/SDO
bit5
Input/output port pin or Synchronous Serial Port data out.
Legend: ST = Schmitt Trigger input
TABLE 4-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on
Power-on
Reset
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
07h
87h
PORTC
TRISC
—
—
—
—
RC5
RC4
RC3
RC2
RC1
RC0
--xx xxxx --uu uuuu
--11 1111 --11 1111
PORTC Data Direction Control Register
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by PORTC.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 33
PIC16C925/926
FIGURE 4-7:
PORTD<7:5> BLOCK
DIAGRAM
4.4
PORTD and TRISD Registers
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. The first five pins are configurable as general pur-
pose I/O pins or LCD segment drivers. Pins RD5, RD6
and RD7 can be digital inputs, or LCD segment, or
common drivers.
LCD
Segment Data
LCD Segment
Output Enable
TRISD controls the direction of pins RD0 through RD4
when PORTD is configured as a digital port.
LCD
Common Data
Note 1: On a Power-on Reset, these pins are
configured as LCD segment drivers.
Digital Input/
LCD Output pin
LCD Common
Output Enable
2: To configure the pins as a digital port, the
corresponding bits in the LCDSE register
must be cleared. Any bit set in the LCDSE
register overrides any bit settings in the
corresponding TRIS register.
LCDSE<n>
Schmitt
Trigger
Input
Buffer
EXAMPLE 4-4:
INITIALIZING PORTD
BCF
BSF
BCF
BCF
BSF
BCF
STATUS,RP0
;Select Bank2
;
;Make RD<7:5> digital
;Make RD<4:0> digital
;Select Bank1
;
Data Bus
RD Port
Q
D
STATUS,RP1
LCDSE, SE29
LCDSE, SE0
STATUS,RP0
STATUS,RP1
EN
MOVLW 0xE0
MOVWF TRISD
;Make RD<4:0> outputs
;Make RD<7:5> inputs
VDD
FIGURE 4-6:
PORTD <4:0> BLOCK
DIAGRAM
RD TRIS
LCD
Segment Data
LCD Segment
Output Enable
Data
Bus
D
Q
WR
Port
I/O pin
CK
Data Latch
D
Q
WR
TRIS
CK
TRIS Latch
Schmitt
Trigger
Input
RD
TRIS
Buffer
LCDSE<n>
Q
D
EN
RD
Port
DS39544A-page 34
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
TABLE 4-7:
Name
PORTD FUNCTIONS
Buffer
Bit#
Function
Type
RD0/SEG00
RD1/SEG01
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
ST
Input/output port pin or Segment Driver00.
Input/output port pin or Segment Driver01.
RD2/SEG02
Input/output port pin or Segment Driver02.
RD3/SEG03
Input/output port pin or Segment Driver03.
RD4/SEG04
Input/output port pin or Segment Driver04.
RD5/SEG29/COM3
RD6/SEG30/COM2
RD7/SEG31/COM1
Digital input pin or Segment Driver29 or Common Driver3.
Digital input pin or Segment Driver30 or Common Driver2.
Digital input pin or Segment Driver31 or Common Driver1.
Legend: ST = Schmitt Trigger input
TABLE 4-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on
Power-on
Reset
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
PORTD
TRISD
LCDSE
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
88h
PORTD Data Direction Control Register
SE29 SE27 SE20 SE16
10Dh
SE12
SE9
SE5
SE0
Legend: Shaded cells are not used by PORTD.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 35
PIC16C925/926
FIGURE 17-1: PORTE BLOCK DIAGRAM
4.5
PORTE and TRISE Register
PORTE is a digital input only port. Each pin is multi-
plexed with an LCD segment driver. These pins have
Schmitt Trigger input buffers.
LCD
Segment Data
LCD Segment
Output Enable
Note 1: On a Power-on Reset, these pins are
LCD
Common Data
configured as LCD segment drivers.
2: To configure the pins as a digital port, the
corresponding bits in the LCDSE register
must be cleared. Any bit set in the LCDSE
register overrides any bit settings in the
corresponding TRIS register.
Digital Input/
LCD Output pin
LCD Common
Output Enable
LCDSE<n>
EXAMPLE 4-5:
INITIALIZING PORTE
Schmitt
Trigger
Input
BCF STATUS, RP0
BSF STATUS, RP1
BCF LCDSE,
BCF LCDSE,
BCF LCDSE,
;Select Bank2
;
Buffer
SE27
;Make all PORTE
;and PORTG<7>
;digital inputs
Data Bus
RD Port
SE5
SE9
Q
D
EN
VDD
RD TRIS
TABLE 4-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
RE0/SEG05
RE1/SEG06
RE2/SEG07
RE3/SEG08
RE4/SEG09
RE5/SEG10
RE6/SEG11
RE7/SEG27
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
ST
Digital input or Segment Driver05.
Digital input or Segment Driver06.
Digital input or Segment Driver07.
Digital input or Segment Driver08.
Digital input or Segment Driver09.
Digital input or Segment Driver10.
Digital input or Segment Driver11.
Digital input or Segment Driver27 (not available on 64-pin devices).
Legend: ST = Schmitt Trigger input
TABLE 4-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on
Power-on
Reset
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
09h
PORTE
TRISE
LCDSE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
89h
PORTE Data Direction Control Register
SE29 SE27 SE20 SE16
10Dh
SE12
SE9
SE5
SE0
Legend: Shaded cells are not used by PORTE.
DS39544A-page 36
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
FIGURE 4-8:
PORTF BLOCK DIAGRAM
4.6
PORTF and TRISF Register
PORTF is a digital input only port. Each pin is multi-
plexed with an LCD segment driver. These pins have
Schmitt Trigger input buffers.
LCD
Segment Data
LCD Segment
Output Enable
Note 1: On a Power-on Reset, these pins are
configured as LCD segment drivers.
LCD
Common Data
2: To configure the pins as a digital port, the
corresponding bits in the LCDSE register
must be cleared. Any bit set in the LCDSE
register overrides any bit settings in the
corresponding TRIS register.
LCD Common
Output Enable
Digital Input/
LCD Output pin
LCDSE<n>
EXAMPLE 4-6:
INITIALIZING PORTF
BCF STATUS, RP0
BSF STATUS, RP1
;Select Bank2
;
;Make all PORTF
;digital inputs
Schmitt
Trigger
Input
BCF LCDSE,
BCF LCDSE,
SE16
SE12
Buffer
Data Bus
RD Port
Q
D
EN
VDD
RD TRIS
TABLE 4-11: PORTF FUNCTIONS
Name
Bit#
Buffer Type
Function
RF0/SEG12
RF1/SEG13
RF2/SEG14
RF3/SEG15
RF4/SEG16
RF5/SEG17
RF6/SEG18
RF7/SEG19
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
ST
Digital input or Segment Driver12.
Digital input or Segment Driver13.
Digital input or Segment Driver14.
Digital input or Segment Driver15.
Digital input or Segment Driver16.
Digital input or Segment Driver17.
Digital input or Segment Driver18.
Digital input or Segment Driver19.
Legend: ST = Schmitt Trigger input
TABLE 4-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Value on
Power-on
Reset
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
RF3
Bit 2
RF2
SE9
Bit 1
RF1
SE5
Bit 0
RF0
SE0
107h
187h
10Dh
PORTF
TRISF
RF7
RF6
RF5
RF4
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
PORTF Data Direction Control Register
SE29 SE27 SE20 SE16
LCDSE
SE12
Legend: Shaded cells are not used by PORTF.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 37
PIC16C925/926
FIGURE 4-9:
PORTG BLOCK DIAGRAM
4.7
PORTG and TRISG Register
PORTG is a digital input only port. Each pin is multi-
plexed with an LCD segment driver. These pins have
Schmitt Trigger input buffers.
LCD
Segment Data
LCD Segment
Output Enable
Note 1: On a Power-on Reset, these pins are
configured as LCD segment drivers.
LCD
Common Data
2: To configure the pins as a digital port, the
corresponding bits in the LCDSE register
must be cleared. Any bit set in the LCDSE
register overrides any bit settings in the
corresponding TRIS register.
LCD Common
Output Enable
Digital Input/
LCD Output pin
LCDSE<n>
EXAMPLE 4-7:
INITIALIZING PORTG
Schmitt
Trigger
Input
BCF
BSF
BCF
BCF
STATUS,
STATUS,
LCDSE,
LCDSE,
RP0
;Select Bank2
RP1
;
Buffer
SE27
SE20
;Make all PORTG
;and PORTE<7>
;digital inputs
Data Bus
RD Port
Q
D
EN
VDD
RD TRIS
TABLE 4-13: PORTG FUNCTIONS
Name
Bit#
Buffer Type
Function
RG0/SEG20
RG1/SEG21
RG2/SEG22
RG3/SEG23
RG4/SEG24
RG5/SEG25
RG6/SEG26
RG7/SEG28
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
ST
Digital input or Segment Driver20.
Digital input or Segment Driver21.
Digital input or Segment Driver22.
Digital input or Segment Driver23.
Digital input or Segment Driver24.
Digital input or Segment Driver25.
Digital input or Segment Driver26.
Digital input or Segment Driver28 (not available on 64-pin devices).
Legend: ST = Schmitt Trigger input
TABLE 4-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Value on
Power-on
Reset
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
RG3
Bit 2
RG2
SE9
Bit 1
RG1
SE5
Bit 0
RG0
SE0
108h
188h
10Dh
PORTG
TRISG
LCDSE
RG7
RG6
RG5
RG4
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
PORTG Data Direction Control Register
SE29 SE27 SE20 SE16
SE12
Legend: Shaded cells are not used by PORTG.
DS39544A-page 38
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
EXAMPLE 4-8:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
4.8
I/O Programming Considerations
4.8.1
BI-DIRECTIONAL I/O PORTS
;Initial PORT settings: PORTB<7:4> Inputs
Any instruction which writes, operates internally as a
read followed by a write operation. The BCFand BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSFoperation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSFoperation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However,
if bit0 is switched into output mode later on, the con-
tents of the data latch may now be unknown.
;
PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
;
;
PORT latch
----------
; 01pp pppp
; 10pp pppp
PORT pins
---------
11pp pppp
11pp pppp
BCF PORTB,
BCF PORTB,
7
6
BCF STATUS, RP1 ; Select Bank1
BSF STATUS, RP0 ;
BCF TRISB,
BCF TRISB,
7
6
; 10pp pppp
; 10pp pppp
11pp pppp
10pp pppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
4.8.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
Reading the port register reads the values of the port
pins. Writing to the port register, writes the value to the
port latch. When using read-modify-write instructions
(e.g. BCF, BSF) on a port, the value of the port pins is
read, the desired operation is done to this value, and
this value is then written to the port latch.
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 4-10). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load depen-
dent) before the next instruction, which causes that file
to be read into the CPU, is executed. Otherwise, the
previous state of that pin may be read into the CPU,
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP, or another
instruction not accessing this I/O port.
Example 4-8 shows the effect of two sequential
read-modify-write instructions on an I/O port. A pin
actively outputting a Low or High should not be driven
from external devices at the same time, in order to
change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
FIGURE 4-10:
SUCCESSIVE I/O OPERATION
Note:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
This example shows a write to PORTB
followed by a read from PORTB.
PC + 3
NOP
PC
PC
PC + 1
PC + 2
NOP
MOVWF PORTB MOVF PORTB,W
write to
Instruction
Fetched
Note that:
data setup time = (0.25TCY - TPD)
PORTB
where TCY
TPD
=
=
instruction cycle
propagation delay
RB7:RB0
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
Port pin
sampled here
TPD
MOVF PORTB,W
NOP
MOVWF PORTB
write to
Instruction
Executed
PORTB
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 39
PIC16C925/926
NOTES:
DS39544A-page 40
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
bit T0SE selects the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 5.2.
5.0
TIMER0 MODULE
The Timer0 module has the following features:
• 8-bit timer/counter
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The
prescaler assignment is controlled in software by con-
trol bit PSA (OPTION<3>). Clearing bit PSA will assign
the prescaler to the Timer0 module. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale values of 1:2,
1:4,..., 1:256 are selectable. Section 5.3 details the
operation of the prescaler.
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt-on-overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 5-2 and
Figure 5-3). The user can work around this by writing
an adjusted value to the TMR0 register.
5.1
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
TMR0IF (INTCON<2>). The interrupt can be masked
by clearing bit T0IE (INTCON<5>). Bit TMR0IF must be
cleared in software by the Timer0 module Interrupt Ser-
vice Routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut-off during SLEEP.
Figure 5-4 displays the Timer0 interrupt timing.
Counter mode is selected by setting bit T0CS
(OPTION<5>). In Counter mode, Timer0 will increment
either on every rising, or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the Timer0
Source Edge Select bit T0SE (OPTION<4>). Clearing
FIGURE 5-1:
TIMER0 BLOCK DIAGRAM
Data Bus
FOSC/4
0
1
PSout
8
1
0
Sync with
Internal
Clocks
TMR0
Programmable
Prescaler
RA4/T0CKI
pin
PSout
(2 cycle delay)
T0SE
3
Set Interrupt
Flag bit TMR0IF
on Overflow
PSA
PS2, PS1, PS0
T0CS
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).
2: The prescaler is shared with the Watchdog Timer (refer to Figure 5-6 for detailed block diagram).
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 41
PIC16C925/926
FIGURE 5-2:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetched
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
TMR0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
FIGURE 5-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetched
T0
T0+1
NT0+1
NT0
TMR0
Instruction
Executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
FIGURE 5-4:
TIMER0 INTERRUPT TIMING
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
OSC1
CLKOUT(3)
Timer0
FEh
FFh
00h
01h
02h
1
1
TMR0IF bit
(INTCON<2>)
GIE bit
(INTCON<7>)
INSTRUCTION
FLOW
PC
PC
PC +1
PC +1
0004h
0005h
Instruction
Fetched
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Instruction
Executed
Inst (PC-1)
Dummy cycle
Dummy cycle
Inst (0004h)
Inst (PC)
Note 1: Interrupt flag bit TMR0IF is sampled here (every Q1).
2: Interrupt latency = 4TCY where TCY = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
DS39544A-page 42
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter type pres-
caler, so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple counter must be taken into account. There-
fore, it is necessary for T0CKI to have a period of at
least 4TOSC (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the mini-
mum pulse width requirement of 10 ns. Refer to param-
eters 40, 41 and 42 in the electrical specification of the
desired device.
5.2
Using Timer0 with an External
Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
5.2.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 5-5).
Therefore, it is necessary for T0CKI to be high for at
least 2TOSC (and a small RC delay of 20 ns) and low for
at least 2TOSC (and a small RC delay of 20 ns). Refer
to the electrical specification of the desired device.
5.2.2
TMR0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 mod-
ule is actually incremented. Figure 5-5 shows the delay
from the external clock edge to the timer incrementing.
FIGURE 5-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
misses sampling
External Clock Input or
Prescaler Output
(2)
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC.) Therefore, the error
in measuring the interval between two edges on Timer0 input = 4TOSC max.
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 43
PIC16C925/926
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
5.3
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (Figure 5-6). For simplicity, this counter is being
referred to as “prescaler” throughout this data sheet.
Note that the prescaler may be used by either the
Timer0 module or the WDT, but not both. Thus, a pres-
caler assignment for the Timer0 module means that
there is no prescaler for the Watchdog Timer, and vice-
versa.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler count. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler count along with the Watchdog Timer. The
prescaler is not readable or writable.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
FIGURE 5-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKOUT (= FOSC/4)
Data Bus
8
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
pin
SYNC
2
TMR0 reg
Cycles
T0SE
T0CS
Set Flag bit TMR0IF
PSA
on Overflow
0
1
8-bit Prescaler
M
U
X
8
Watchdog
Timer
8 - to - 1 MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
DS39544A-page 44
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
5.3.1
SWITCHING PRESCALER
ASSIGNMENT
Note: To avoid an unintended device RESET,
the following instruction sequence (shown
in Example 5-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This precaution must
be followed even if the WDT is disabled.
The prescaler assignment is fully under software con-
trol, i.e., it can be changed “on the fly” during program
execution.
EXAMPLE 5-1:
CHANGING PRESCALER (TIMER0→WDT)
1) BSF
STATUS, RP0
;Select Bank1
2) MOVLW b’xx0x0xxx’
3) MOVWF OPTION_REG
;Select clock source and prescale value of
Lines 2 and 3 do NOT have to
be included if the final desired
prescale value is other than 1:1.
If 1:1 is final desired value, then
a temporary prescale value is
set in lines 2 and 3 and the final
prescale value will be set in lines
10 and 11.
;other than 1:1
4) BCF
5) CLRF
6) BSF
STATUS, RP0
TMR0
;Select Bank0
;Clear TMR0 and prescaler
STATUS, RP1
;Select Bank1
7) MOVLW b’xxxx1xxx’
8) MOVWF OPTION_REG
9) CLRWDT
;Select WDT, do not change prescale value
;
;Clears WDT and prescaler
10) MOVLW b’xxxx1xxx’
11) MOVWF OPTION_REG
;Select new prescale value and WDT
;
12) BCF
STATUS, RP0
;Select Bank0
To change prescaler from the WDT to the Timer0 mod-
ule use the precaution shown in Example 5-2.
EXAMPLE 5-2:
CHANGING PRESCALER (WDT→TIMER0)
CLRWDT
;Clear WDT and precaler
STATUS, RP0 ;Select Bank1
MOVLW b’xxxx0xxx’ ;Select TMR0,
;new prescale value and
;clock source
STATUS, RP0 ;Select Bank0
BSF
MOVWF OPTION_REG
BCF
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Bit 1 Bit 0 Power-on all other
Reset RESETS
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
xxxx xxxx uuuu uuuu
0000 000x 0000 000u
01h, 101h
TMR0
Timer0 Module Register
PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
0Bh, 8Bh,
10Bh, 18Bh
INTCON GIE
1111 1111 1111 1111
--11 1111 --11 1111
81h, 181h
85h
OPTION RBPU INTEDG T0CS
T0SE PSA
PS2
PS1
PS0
TRISA PORTA Data Direction Control Register
—
—
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'.
Shaded cells are not used by Timer0.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 45
PIC16C925/926
NOTES:
DS39544A-page 46
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
6.0
TIMER1 MODULE
Timer1 is a 16-bit timer/counter consisting of two 8-bit
registers (TMR1H and TMR1L), which are readable
and
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit, TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit, TMR1IE (PIE1<0>).
Timer1 can be turned on and off using the control bit
TMR1ON (T1CON<0>).
writable.
The
TMR1
Register
pair
Timer1 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 8.0). Register 6-1 shows the Timer1 control
register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs, regardless of the TRISC<1:0>. RC1
and RC0 will be read as ‘0’.
Timer1 can operate in one of two modes:
• As a timer
• As a counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
REGISTER 6-1:
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as '0'
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut-off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
TMR1CS: Timer1 Clock Source Select bit
bit 1
bit 0
1= External clock from pin T1CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 47
PIC16C925/926
6.2.1
EXTERNAL CLOCK INPUT TIMING
FOR SYNCHRONIZED COUNTER
MODE
6.1
Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
When an external clock input is used for Timer1 in Syn-
chronized Counter mode, it must meet certain require-
ments. The external clock requirement is due to
internal phase clock (TOSC) synchronization. Also,
there is a delay in the actual incrementing of TMR1
after synchronization.
6.2
Timer1 Operation in Synchronized
Counter Mode
When the prescaler is 1:1, the external clock input is
the same as the prescaler output. The synchronization
of T1CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T1CKI to be high for at least 2TOSC (and
a small RC delay of 20 ns), and low for at least 2TOSC
(and a small RC delay of 20 ns). Refer to the appropri-
ate electrical specifications, parameters 45, 46, and 47.
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI when bit T1OSCEN is
set, or pin RC0/T1OSO/T1CKI when bit T1OSCEN is
cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler is an asynchronous ripple counter.
When a prescaler other than 1:1 is used, the external
clock input is divided by the asynchronous ripple
counter type prescaler, so that the prescaler output is
symmetrical. In order for the external clock to meet the
sampling requirement, the ripple counter must be taken
into account. Therefore, it is necessary for T1CKI to
have a period of at least 4TOSC (and a small RC delay
of 40 ns), divided by the prescaler value. The only
requirement on T1CKI high and low time is that they do
not violate the minimum pulse width requirements of
10 ns). Refer to the appropriate electrical specifica-
tions, parameters 40, 42, 45, 46, and 47.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The pres-
caler however will continue to increment.
FIGURE 6-1:
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
Synchronized
0
TMR1
Clock Input
TMR1L
TMR1H
1
TMR1ON
On/Off
T1SYNC
T1OSC
RC0/T1OSO/T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
FOSC/4
Internal
Clock
0
(1)
Oscillator
RC1/T1OSI
2
SLEEP Input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39544A-page 48
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
6.3.2
READING AND WRITING TMR1 IN
ASYNCHRONOUS COUNTER
MODE
6.3
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt-on-overflow which will wake-up
the processor. However, special precautions in soft-
ware are needed to read from, or write to the Timer1
register pair (TMR1H:TMR1L) (Section 6.3.2).
Reading TMR1H or TMR1L, while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself, poses certain problems, since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers while the
register is incrementing. This may produce an unpre-
dictable value in the timer register.
In Asynchronous Counter mode, Timer1 cannot be
used as a time-base for capture or compare opera-
tions.
6.3.1
EXTERNAL CLOCK INPUT TIMING
WITH UNSYNCHRONIZED CLOCK
Reading the 16-bit value requires some care.
Example 6-1 is an example routine to read the 16-bit
timer value. This is useful if the timer cannot be
stopped.
If control bit T1SYNC is set, the timer will increment
completely asynchronously. The input clock must meet
certain minimum high time and low time requirements,
as specified in timing parameters 45, 46, and 47.
EXAMPLE 6-1:
READING A 16-BIT FREE-RUNNING TIMER
; All interrupts are disabled
;
MOVF
TMR1H, W
;Read high byte
MOVWF TMPH
;
MOVF
MOVWF TMPL
TMR1L, W
;Read low byte
;
MOVF
TMR1H, W
;Read high byte
SUBWF TMPH,
BTFSC STATUS,Z
GOTO CONTINUE
W
;Sub 1st read with 2nd read
;Is result = 0
;Good 16-bit read
;
; TMR1L may have rolled over between the read of the high and low bytes.
; Reading the high and low bytes now will read a good value.
;
MOVF
TMR1H, W
;Read high byte
MOVWF TMPH
;
MOVF
MOVWF TMPL
TMR1L, W
;Read low byte
;
; Re-enable the Interrupt (if required)
;
CONTINUE
;Continue with your code
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 49
PIC16C925/926
6.4
Timer1 Oscillator
6.5
Resetting Timer1 Using the CCP
Trigger Output
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 6-1 shows the capacitor
selection for the Timer1 oscillator.
If the CCP1 module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1.
Note: The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
Timer1 must be configured for either Timer or Synchro-
nized Counter mode, to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this reset operation may not work.
TABLE 6-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take pre-
cedence.
Osc Type
Freq
C1
C2
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair effectively become the period register for
Timer1.
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
6.6
Resetting of Timer1 Register Pair
(TMR1H:TMR1L)
32.768 kHz Epson C-001R32.768K-A
20 PPM
TMR1H and TMR1L registers are not reset on a POR
or any other RESET, except by the CCP1 special event
trigger.
100 kHz
200 kHz
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
20 PPM
20 PPM
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
T1CON register is reset to 00h on a Power-on Reset.
In any other RESET, the register is unaffected.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
6.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TABLE 6-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
Power-on
Reset
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
0Eh
0Fh
10h
PIR1
PIE1
LCDIF
LCDIE
ADIF
ADIE
—
—
—
—
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000
CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by theTimer1 module.
DS39544A-page 50
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
7.1
Timer2 Prescaler and Postscaler
7.0
TIMER2 MODULE
The prescaler and postscaler counters are cleared
when any of the following occurs:
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module. It can also be used
as a time-base for the Master mode SPI clock. The
TMR2 register is readable and writable, and is cleared
on any device RESET.
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (Power-on Reset, MCLR
Reset, or Watchdog Timer Reset)
The input clock (FOSC/4) has a prescale option of 1:1,
TMR2 will not clear when T2CON is written.
1:4,
or
1:16
(selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON<1:0>)).
7.2
Output of TMR2
The Timer2 module has an 8-bit period register, PR2.
TMR2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
set during RESET.
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module, which optionally uses
it to generate the shift clock.
FIGURE 7-1:
TIMER2 BLOCK DIAGRAM
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Sets Flag
TMR2
Output(1)
bit TMR2IF
RESET
Prescaler
1:1, 1:4, 1:16
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
TMR2 reg
FOSC/4
Postscaler
1:16 to 1:1
2
Comparator
Figure 7-1 shows the Timer2 control register.
EQ
4
PR2 reg
Note 1: TMR2 register output can be software selected by the
SSP Module as the source clock.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 51
PIC16C925/926
REGISTER 7-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
Power-on
Reset
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
10Bh, 18Bh
0Ch
8Ch
11h
12h
92h
PIR1
LCDIF
LCDIE
ADIF
ADIE
—
—
—
—
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF 00-- 0000 00-- 0000
TMR1IE 00-- 0000 00-- 0000
0000 0000 0000 0000
PIE1
TMR2
T2CON
PR2
Timer2 Module’s Register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register 1111 1111 1111 1111
Legend: x= unknown, u= unchanged, -= unimplemented, read as ’0’. Shaded cells are not used by the Timer2 module.
DS39544A-page 52
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
Register 8-1 shows the CCP1CON register.
8.0
CAPTURE/COMPARE/PWM
(CCP) MODULE
For use of the CCP module, refer to the Embedded
Control Handbook, “Using the CCP Modules” (AN594).
The CCP (Capture/Compare/PWM) module contains a
16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register, or as a PWM
master/slave duty cycle register. Table 8-1 shows the
timer resources used by the CCP module.
TABLE 8-1:
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
The Capture/Compare/PWM Register1 (CCPR1) is
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte). The CCP1CON register con-
trols the operation of CCP1. All three are readable and
writable.
Capture
Compare
PWM
Timer1
Timer1
Timer2
REGISTER 8-1:
CCP1CON REGISTER (ADDRESS 17h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 0
bit 7
Unimplemented: Read as '0'
bit 7-6
bit 5-4
CCP1X:CCP1Y: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0
CCP1M3:CCP1M0: CCP1 Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCP1 module)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (bit CCP1IF is set)
1001= Compare mode, clear output on match (bit CCP1IF is set)
1010= Compare mode, generate software interrupt-on-match (bit CCP1IF is set, CCP1 pin is
unaffected)
1011= Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1)
11xx= PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 53
PIC16C925/926
8.1.3
SOFTWARE INTERRUPT
8.1
Capture Mode
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep
enable bit CCP1IE (PIE1<2>) clear to avoid false inter-
rupts and should clear flag bit CCP1IF following any
such change in operating mode.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1 (Figure 8-1). An event can be
selected to be one of the following:
• Every falling edge
• Every rising edge
8.1.4
CCP PRESCALER
• Every 4th rising edge
• Every 16th rising edge
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten with the new captured value.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
8.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a cap-
ture condition.
EXAMPLE 8-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
; Turn CCP module off
CLRF
CCP1CON
MOVLW NEW_CAPT_PS ; Load the W reg with
; the new prescaler
FIGURE 8-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
; mode value and CCP ON
MOVWF CCP1CON
; Load CCP1CON with
; this value
CCP
Prescaler
Set CCP1IF
PIR1<2>
÷ 1, 4, 16
RC2/CCP1
pin
CCPR1H CCPR1L
Capture
Enable
and
edge detect
TMR1H
TMR1L
CCP1CON<3:0>
Q’s
8.1.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
DS39544A-page 54
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
8.2.2
TIMER1 MODE SELECTION
8.2
Compare Mode
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
8.2.3
SOFTWARE INTERRUPT MODE
• Remains unchanged
When Generate Software Interrupt is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is gen-
erated (if enabled).
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, a compare interrupt is also generated.
8.2.4
SPECIAL EVENT TRIGGER
FIGURE 8-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion. This
allows the CCPR1H:CCPR1L register pair to effectively
be a 16-bit programmable period register for Timer1.
Special event trigger will reset Timer1, but not
set interrupt flag bit TMR1IF (PIR1<0>).
Set CCP1IF
PIR1<2>
Note: The “special event trigger” from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
CCPR1H CCPR1L
Comparator
Q
S
R
Output
Logic
Match
RC2/CCP1
TRISC<2>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
8.2.1
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 55
PIC16C925/926
8.3.1
PWM PERIOD
8.3
PWM Mode
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
PWM period = [ (PR2) + 1 ] • 4 • TOSC •
(TMR2 prescale value)
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3.
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FIGURE 8-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note: The Timer2 postscaler (Section 7.0) is not
used in the determination of the PWM fre-
quency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
8.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available; the CCPR1L contains
the eight MSbs and CCP1CON<5:4> contains the two
LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1H (Slave)
Comparator
Q
R
S
RC2/CCP1
TMR2
(Note 1)
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
A PWM output (Figure 8-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock, or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
FIGURE 8-4:
PWM OUTPUT
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
Period
FOSC
---------------
log
FPWM
PWM Resolution (max)
= ----------------------------- b i t s
TMR2 = PR2
log(2)
Duty Cycle
TMR2 = Duty Cycle
TMR2 = PR2
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
DS39544A-page 56
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
EQUATION 8-1:
EXAMPLES OF PWM PERIOD AND DUTY CYCLE CALCULATION
1. Find the value of the PR2 register, given:
• Desired PWM frequency = 31.25 kHz
• FOSC = 8 MHz
• TMR2 prescale = 1
From the equation for PWM period in Section 8.3.1,
1 / 31.25 kHz = [ (PR2) + 1 ] • 4 • 1/8 MHz • 1
or
32 µs
PR2
PR2
= [ (PR2) + 1 ] • 4 • 125 ns • 1 = [ (PR2) + 1 ] • 0.5 µs
= (32 µs / 0.5 µs) - 1
= 63
2. Find the maximum resolution of the duty cycle that can be used with a 31.25 kHz frequency and
8 MHz oscillator.
From the equation from maximum PWM resolution in Section 8.3.2,
1 / 31.25 kHz = 2PWM RESOLUTION • 1 / 8 MHz • 1
or
32 µs
256
= 2PWM RESOLUTION • 125 ns • 1
= 2PWM RESOLUTION
log(256)
8.0
= (PWM Resolution) • log(2)
= PWM Resolution
At most, an 8-bit resolution duty cycle can be obtained
from a 31.25 kHz frequency and a 8 MHz oscillator, i.e.,
0 ≤ CCPR1L:CCP1CON<5:4> ≤ 255. Any value greater
than 255 will result in a 100% duty cycle.
8.3.3
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
In order to achieve higher resolution, the PWM fre-
quency must be decreased. In order to achieve higher
PWM frequency, the resolution must be decreased.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Table 8-2 lists example PWM frequencies and resolu-
tions for FOSC = 8 MHz. TMR2 prescaler and PR2 val-
ues are also shown.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP module for PWM operation.
TABLE 8-2:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 8 MHz
PWM Frequency
488 Hz
1.95 kHz
7.81 kHz 31.25 kHz 62.5 kHz
250 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0x07
5
0xFF
10
0xFF
10
Maximum Resolution (bits)
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 57
PIC16C925/926
TABLE 8-3:
REGISTERS ASSOCIATED WITH TIMER1, CAPTURE AND COMPARE
Value on
Power-on
Reset
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
LCDIF ADIF
LCDIE ADIE
—
—
—
—
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000
CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000
8Ch
PIE1
87h
TRISC
TMR1L
TMR1H
T1CON
CCPR1L
—
—
PORTC Data Direction Control Register
--11 1111 --11 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0Eh
Holding register for the Least Significant Byte of the 16-bit TMR1 Register
Holding register for the Most Significant Byte of the 16-bit TMR1 Register
0Fh
10h
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h
Capture/Compare/PWM1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
CCPR1H Capture/Compare/PWM1 (MSB)
CCP1CON CCP1X CCP1Y
17h
—
—
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0’. Shaded cells are not used in these modes.
TABLE 8-4:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
Power-on
Reset
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
LCDIF
LCDIE
—
ADIF
ADIE
—
—
—
—
—
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000
CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000
8Ch
PIE1
87h
TRISC
TMR2
PR2
PORTC Data Direction Control Register
--11 1111 --11 1111
0000 0000 0000 0000
1111 1111 1111 1111
11h
Timer2 Module Register
92h
Timer2 Module Period Register
12h
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h
CCPR1L Capture/Compare/PWM1 (LSB)
CCPR1H Capture/Compare/PWM1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
17h
CCP1CON
—
—
CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0’. Shaded cells are not used in this mode.
DS39544A-page 58
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
• Serial Peripheral Interface (SPITM
• Inter-Integrated Circuit (I2CTM
)
9.0
SYNCHRONOUS SERIAL PORT
(SSP) MODULE
)
Refer to Application Note AN578, "Use of the SSP
Module in the I 2C Multi-Master Environment.”
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
REGISTER 9-1:
SSPSTAT: SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
bit 6
SMP: SPI Data Input Sample Phase bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
CKE: SPI Clock Edge Select bit (see Figure 9-3, Figure 9-4, and Figure 9-5)
CKP = 0:
1= Data transmitted on rising edge of SCK
0= Data transmitted on falling edge of SCK
CKP = 1:
1= Data transmitted on falling edge of SCK
0= Data transmitted on rising edge of SCK
2
bit 5
bit 4
D/A: Data/Address bit (I C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
2
P: STOP bit (I C mode only. This bit is cleared when the SSP module is disabled, or when the START
bit was detected last.)
1= Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0= STOP bit was not detected last
2
bit 3
bit 2
S: START bit (I C mode only. This bit is cleared when the SSP module is disabled, or when the STOP
bit was detected last.)
1= Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0= START bit was not detected last
2
R/W: Read/Write bit Information (I C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next START bit, STOP bit, or ACK bit.
1= Read
0= Write
2
bit 1
bit 0
UA: Update Address (10-bit I C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
2
Receive (SPI and I C modes):
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
2
Transmit (I C mode only)
1= Transmit in progress, SSPBUF is full
0= Transmit complete, SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 59
PIC16C925/926
REGISTER 9-2:
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
bit 6
WCOL: Write Collision Detect bit
1= SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0= No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1= A new byte is received while SSPBUF is holding previous data. Data in SSPSR is lost on overflow.
Overflow only occurs in Slave mode. The user must read the SSPBUF, even if only transmitting data,
to avoid setting overflows. In Master mode, the overflow bit is not set since each operation is initiated
by writing to the SSPBUF register. (Must be cleared in software.)
0= No overflow
2
In I C mode:
1= A byte is received while the SSPBUF is holding the previous byte. SSPOV is a “don’t care” in transmit
mode. (Must be cleared in software.)
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
When enabled, these pins must be properly configured as input or output.
1= Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0= Disables serial port and configures these pins as I/O port pins
2
In I C mode:
When enabled, these pins must be properly configured as input or output.
1= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level
0= Idle state for clock is a low level
2
In I C mode:
SCK release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin (SS pin control enabled)
0101= SPI Slave mode, clock = SCK pin (SS pin control disabled, SS can be used as I/O pin)
2
0110= I C Slave mode, 7-bit address
2
0111= I C Slave mode, 10-bit address
2
1011= I C firmware controlled Master mode (slave idle)
2
1110= I C firmware controlled Master mode, 7-bit address with START and STOP bit interrupts enabled
2
1111= I C firmware controlled Master mode, 10-bit address with START and STOP bit interrupts enabled
1000, 1001, 1010, 1100, 1101= reserved
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39544A-page 60
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
EXAMPLE 9-1:
LOADING THE SSPBUF
(SSPSR) REGISTER
9.1
SPI Mode
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
BCF
BSF
STATUS, RP1 ;Select Bank1
STATUS, RP0
;
LOOP
BTFSS SSPSTAT, BF ;Has data been
;received
;(transmit
;complete)?
;No
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI
• Serial Clock (SCK) RC3/SCK
GOTO LOOP
BCF STATUS, RP0 ;Select Bank0
MOVF SSPBUF, W
;W reg = contents
;of SSPBUF
;Save in user RAM
Additionally, a fourth pin may be used when in a Slave
mode of operation:
MOVWF RXDATA
• Slave Select (SS) RA5/AN4/SS
MOVF TXDATA, W
;W reg = contents
; of TXDATA
;New data to xmit
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specified:
MOVWF SSPBUF
The block diagram of the SSP module, when in SPI
mode (Figure 9-1), shows that the SSPSR is not
directly readable or writable, and can only be accessed
from addressing the SSPBUF register. Additionally, the
SSP status register (SSPSTAT) indicates the various
status conditions.
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Clock Edge (output data on rising/falling edge of
SCK)
FIGURE 9-1:
SSP BLOCK DIAGRAM
(SPI MODE)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Internal
Data Bus
The SSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the buffer full detect bit, BF
(SSPSTAT<0>), and interrupt flag bit, SSPIF
(PIR1<3>), are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit, WCOL (SSPCON<7>), will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the
SSPBUF register completed successfully. When the
application software is expecting to receive valid data,
the SSPBUF should be read before the next byte of
data to transfer is written to the SSPBUF. Buffer full bit,
BF (SSPSTAT<0>), indicates when SSPBUF has been
loaded with the received data (transmission is com-
plete). When the SSPBUF is read, bit BF is cleared.
This data may be irrelevant if the SPI is only a transmit-
ter. Generally, the SSP interrupt is used to determine
when the transmission/reception has completed. The
SSPBUF must be read and/or written. If the interrupt
method is not going to be used, then software polling
can be done to ensure that a write collision does not
occur. Example 9-1 shows the loading of the SSPBUF
(SSPSR) for data transmission. The MOVWF RXDATA
instruction (shaded) is only required if the received data
is meaningful.
Read
Write
SSPBUF reg
SSPSR reg
RC4/SDI/SDA
RC5/SDO
Shift
Clock
bit0
Control
Enable
SS
RA5/AN4/SS
Edge
Select
2
Clock Select
SSPM3:SSPM0
4
TMR2 Output
2
Edge
Select
TCY
Prescaler
4, 16, 64
RC3/SCK/
SCL
TRISC<3>
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 61
PIC16C925/926
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure
SPI mode, clear bit SSPEN, re-initialize the SSPCON
register, and then set bit SSPEN. This configures the
SDI, SDO, SCK, and SS pins as serial port pins. For the
pins to behave as the serial port function, they must
have their data direction bits (in the TRISC register)
appropriately programmed. That is:
• Master sends dummy data — Slave sends data
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2) is to broadcast data by
the firmware protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SCK output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate. As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set and ADCON must
be configured such that RA5 is a digital I/O
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the interrupt flag bit SSPIF (PIR1<3>)
is set.
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value. An example
would be in Master mode, where you are only sending
data (to a display driver), then both SDI and SS could
be used as general purpose outputs by clearing their
corresponding TRIS register bits.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This then, would give
waveforms for SPI communication as shown in
Figure 9-3, Figure 9-4, and Figure 9-5, where the MSB
is transmitted first. In Master mode, the SPI clock rate
(bit rate) is user programmable to be one of the
following:
Figure 9-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite
edge of the clock. Both processors should be pro-
grammed to same Clock Polarity (CKP), then both con-
trollers would send and receive data at the same time.
Whether the data is meaningful (or dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum bit clock frequency (at 8 MHz)
of 2 MHz. When in Slave mode, the external clock must
meet the minimum high and low times.
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
In SLEEP mode, the slave can transmit and receive
data and wake the device from SLEEP.
FIGURE 9-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
Shift Register
(SSPSR)
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
PROCESSOR 2
DS39544A-page 62
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode (SSPCON<3:0> = 04h)
and the TRISA<5> bit must be set for the Synchro-
nous Slave mode to be enabled. When the SS pin
is low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte and becomes a floating
output. External pull-up/pull-down resistors may be
desirable, depending on the application.
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: If the SPI is used in Slave mode with
CKE = ’1’, then the SS pin control must be
enabled.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 9-3:
SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SDI (SMP = 1)
SSPIF
bit7
bit0
FIGURE 9-4:
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SSPIF
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 63
PIC16C925/926
FIGURE 9-5:
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
(not optional)
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDI (SMP = 0)
SSPIF
bit7
bit0
TABLE 9-1:
REGISTERS ASSOCIATED WITH SPI OPERATION
Value on
Power-on
Reset
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE TMR0IE INTE
RBIE TMR0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
13h
14h
85h
87h
PIR1
LCDIF ADIF
LCDIE ADIE
—
—
—
—
SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000
SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000
PIE1
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA
TRISC
—
—
—
—
PORTA Data Direction Control Register
PORTC Data Direction Control Register
--11 1111 --11 1111
--11 1111 --11 1111
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode.
DS39544A-page 64
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
2
The output stages of the clock (SCL) and data (SDA)
lines must have an open drain or open collector, in
order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high
level when no device is pulling the line down. The num-
ber of devices that may be attached to the I2C bus is
limited only by the maximum bus loading specification
of 400 pF.
9.2
I C Overview
This section provides an overview of the Inter-
Integrated Circuit (I2C) bus, with Section 9.3 discuss-
ing the operation of the SSP module in I2C mode.
The I2C bus is a two-wire serial interface developed by
the Philips Corporation. The original specification, or
standard mode, was for data transfers of up to 100
Kbps. An enhanced specification, or fast mode is not
supported. This device will communicate with fast
mode devices if attached to the same bus.
9.2.1
INITIATING AND TERMINATING
DATA TRANSFER
The I2C interface employs a comprehensive protocol to
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
which initiates transfer on the bus and generates the
clock signals to permit that transfer, while the other
device(s) acts as the “slave.” All portions of the slave
protocol are implemented in the SSP module’s hard-
ware, except general call support, while portions of the
master protocol need to be addressed in the
PIC16CXXX software. Table 9-2 defines some of the
I2C bus terminology. For additional information on the
I2C interface specification, refer to the Philips docu-
ment #939839340011, “The I2C bus and how to use it”,
which can be obtained from the Philips Corporation.
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP conditions determine the start and stop of data
transmission. The START condition is defined as a
high to low transition of the SDA when the SCL is high.
The STOP condition is defined as a low to high transi-
tion of the SDA when the SCL is high. Figure 9-6 shows
the START and STOP conditions. The master gener-
ates these conditions for starting and terminating data
transfer. Due to the definition of the START and STOP
conditions, when data is being transmitted, the SDA
line can only change state when the SCL line is low.
In the I2C interface protocol, each device has an
address. When a master wishes to initiate a data trans-
fer, it first transmits the address of the device that it
wishes to “talk” to. All devices “listen” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read from/write to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data trans-
fer. That is, they can be thought of as operating in either
of these two relations:
FIGURE 9-6:
START AND STOP
CONDITIONS
SDA
S
SCL
P
Change
of Data
Allowed
Change
of Data
Allowed
START
Condition
STOP
Condition
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
In both cases, the master generates the clock signal.
TABLE 9-2:
Term
I2C BUS TERMINOLOGY
Description
Transmitter
Receiver
Master
The device that sends the data to the bus.
The device that receives the data from the bus.
The device which initiates the transfer, generates the clock and terminates the transfer.
The device addressed by a master.
Slave
Multi-master
More than one master device in a system. These masters can attempt to control the bus at the
same time without corrupting the message.
Arbitration
Procedure that ensures that only one of the master devices will control the bus. This ensures that
the transfer data does not get corrupted.
Synchronization
Procedure where the clock signals of two or more devices are synchronized.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 65
PIC16C925/926
9.2.2
ADDRESSING I2C DEVICES
9.2.3
TRANSFER ACKNOWLEDGE
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure 9-7). The
more complex is the 10-bit address with a R/W bit
(Figure 9-8). For 10-bit address format, two bytes must
be transmitted with the first five bits specifying this to be
a 10-bit address.
All data must be transmitted per byte, with no limit to
the number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an Acknowl-
edge bit (ACK) (see Figure 9-9). When a slave-receiver
doesn’t acknowledge the slave address or received
data, the master must abort the transfer. The slave
must leave SDA high so that the master can generate
the STOP condition (Figure 9-6).
FIGURE 9-7:
7-BIT ADDRESS FORMAT
MSb
LSb
FIGURE 9-9:
SLAVE-RECEIVER
ACKNOWLEDGE
R/W ACK
S
Data
Output by
Slave Address
Sent by
Slave
Transmitter
Data
Output by
Receiver
Not Acknowledge
Acknowledge
S
R/W
ACK
START Condition
Read/Write pulse
Acknowledge
SCL from
Master
9
8
1
2
S
Clock Pulse for
Acknowledgment
START
Condition
FIGURE 9-8:
I2C 10-BIT ADDRESS
FORMAT
If the master is receiving the data (master-receiver), it
generates an Acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an Acknowledge (Not Acknowledge). The
slave then releases the SDA line so the master can
generate the STOP condition. The master can also
generate the STOP condition during the Acknowledge
pulse for valid termination of data transfer.
S
1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
Sent by Slave
= 0 for Write
S
- START Condition
R/W - Read/Write Pulse
ACK - Acknowledge
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the slave to move
the received data, or fetch the data it needs to transfer
before allowing the clock to start. This wait state tech-
nique can also be implemented at the bit level,
Figure 9-10. The slave will inherently stretch the clock
when it is a transmitter, but will not when it is a receiver.
The slave will have to clear the SSPCON<4> bit to
enable clock stretching when it is a receiver.
FIGURE 9-10:
DATA TRANSFER WAIT STATE
SDA
MSB
Acknowledgment
Signal from Receiver
Acknowledgment
Signal from Receiver
Byte Complete
Interrupt with Receiver
Clock Line Held Low while
Interrupts are Serviced
SCL
S
1
2
7
8
9
1
2
3 • 8
9
P
START
Condition
STOP
Condition
Address
R/W ACK Wait
State
Data
ACK
DS39544A-page 66
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
Figure 9-11 and Figure 9-12 show master-transmitter
and Master-receiver data transfer sequences.
while SCL is high), but occurs after a data transfer
Acknowledge pulse (not the bus-free state). This allows
a master to send “commands” to the slave and then
receive the requested information, or to address a dif-
ferent slave device. This sequence is shown in
Figure 9-13.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a Repeated START
condition (Sr) must be generated. This condition is
identical to the START condition (SDA goes high-to-low
FIGURE 9-11:
MASTER-TRANSMITTER SEQUENCE
For 7-bit address:
For 10-bit address:
SSlave AddressR/W A1Slave Address A2
S Slave AddressR/W A Data A Data A/A P
First 7 bits
Second byte
'0' (write)
data transferred
(n bytes - Acknowledge)
(write)
A master-transmitter addresses a slave-receiver with a
7-bit address. The transfer direction is not changed.
Data A
Data A/A P
A = Acknowledge (SDA low)
A = Not Acknowledge (SDA high)
From master to slave
From slave to master
S = START Condition
A master-transmitter addresses a slave-receiver
with a 10-bit address.
P = STOP Condition
FIGURE 9-12:
MASTER-RECEIVER SEQUENCE
For 7-bit address:
For 10-bit address:
SSlave AddressR/W A1Slave Address A2
First 7 bits Second byte
(write)
S Slave AddressR/W A Data A Data
A P
'1' (read) data transferred
(n bytes - Acknowledge)
A master reads a slave immediately after the first byte.
SrSlave AddressR/W A3 Data A Data A P
First 7 bits
A = Acknowledge (SDA low)
A = Not Acknowledge (SDA high)
From master to slave
(read)
S = START Condition
A master-transmitter addresses a slave-receiver
with a 10-bit address.
From slave to master
P = STOP Condition
FIGURE 9-13:
COMBINED FORMAT
(read or write)
(n bytes + Acknowledge)
S Slave AddressR/W A Data A/A Sr Slave Address R/W A Data A/A P
(write)
Direction of transfer
may change at this point
(read)
Sr = repeated
START Condition
Transfer direction of data and Acknowledgment bits depends on R/W bits.
Combined format:
SrSlave Address R/W A Slave Address A Data A
First 7 bits Second byte
Data A/A Sr Slave Address R/W A Data A
First 7 bits
Data A P
(read)
(write)
Combined format - A master addresses a slave with a 10-bit address, then transmits
data to this slave and reads data from this slave.
A = Acknowledge (SDA low)
A = Not Acknowledge (SDA high)
From master to slave
S = START Condition
From slave to master
P = STOP Condition
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 67
PIC16C925/926
9.2.4
MULTI-MASTER
9.2.4.2
Clock synchronization occurs after the devices have
started arbitration. This is performed using
Clock Synchronization
The I2C protocol allows a system to have more than
one master. This is called multi-master. When two or
more masters try to transfer data at the same time,
arbitration and synchronization occur.
a
wired-AND connection to the SCL line. A high to low
transition on the SCL line causes the concerned
devices to start counting off their low period. Once a
device clock has gone low, it will hold the SCL line low
until its SCL high state is reached. The low to high tran-
sition of this clock may not change the state of the SCL
line, if another device clock is still within its low period.
The SCL line is held low by the device with the longest
low period. Devices with shorter low periods enter a
high wait state, until the SCL line comes high. When the
SCL line comes high, all devices start counting off their
high periods. The first device to complete its high
period will pull the SCL line low. The SCL line high time
is determined by the device with the shortest high
period, Figure 9-15.
9.2.4.1
Arbitration
Arbitration takes place on the SDA line, while the SCL
line is high. The master, which transmits a high when
the other master transmits a low, loses arbitration
(Figure 9-14) and turns off its data output stage. A mas-
ter, which lost arbitration can generate clock pulses
until the end of the data byte where it lost arbitration.
When the master devices are addressing the same
device, arbitration continues into the data.
FIGURE 9-14:
MULTI-MASTER
ARBITRATION
(TWO MASTERS)
FIGURE 9-15:
CLOCK
SYNCHRONIZATION
Transmitter 1 Loses Arbitration
DATA 1 SDA
Start Counting
HIGH Period
Wait
State
DATA 1
DATA 2
SDA
CLK
1
Counter
Reset
CLK
2
SCL
SCL
Masters that also incorporate the slave function and
have lost arbitration, must immediately switch over to
Slave-Receiver mode. This is because the winning
master-transmitter may be addressing it.
Arbitration is not allowed between:
• A Repeated START condition
• A STOP condition and a data bit
• A Repeated START condition and a STOP
condition
Care needs to be taken to ensure that these conditions
do not occur.
DS39544A-page 68
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled
• I2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled
• I2C Firmware controlled Master mode, slave is
2
9.3
SSP I C Operation
The SSP module in I2C mode fully implements all slave
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to
facilitate firmware implementations of the master func-
tions. The SSP module implements the standard mode
specifications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RC3/SCK/SCL pin, which is the clock (SCL), and the
RC4/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISC<4:3> bits. The SSP module functions are
enabled by setting SSP enable bit, SSPEN
(SSPCON<5>).
idle
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
FIGURE 9-16:
SSP BLOCK DIAGRAM
(I2C MODE)
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address, if the next byte is the completion of
10-bit address, and if this will be a read or write data
transfer. The SSPSTAT register is read only.
Internal
Data Bus
Read
Write
SSPBUF reg
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
RC3/SCK/SCL
Shift
Clock
SSPSR reg
RC4/
SDI/
SDA
MSb
LSb
Addr Match
Match Detect
SSPADD reg
START and
The SSPADD register holds the slave address. In
10-bit mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
Set, Reset
S, P bits
(SSPSTAT reg)
STOP bit Detect
The SSP module has five registers for I2C operation.
These are the:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly
accessible
• SSP Address Register (SSPADD)
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 69
PIC16C925/926
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
9.3.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
a) The SSPSR register value is loaded into the
SSPBUF register.
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave (Figure 9-8). The five Most Sig-
nificant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the sec-
ond address byte. For a 10-bit address the first byte
would equal ‘1111 0 A9 A8 0’, where A9and A8are
the two MSbs of the address. The sequence of events
for a 10-bit address is as follows, with steps 7- 9 for
slave-transmitter:
There are certain conditions that will cause the SSP
module not to give this ACK pulse. These are if either
(or both):
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b) The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 9-3 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister while bit SSPOV is cleared through software.
1. Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I2C specification as well as the requirement of
the SSP module is shown in timing parameter #100
and parameter #101.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD register with the first (high)
byte of Address, if match releases SCL line, this
will clear bit UA.
9.3.1.1
Addressing
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
7. Receive Repeated START condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
TABLE 9-3:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
Generate ACK
(SSP Interrupt occurs
Pulse
SSPSR → SSPBUF
if enabled)
BF
SSPOV
0
1
1
0
0
0
1
1
Yes
No
No
No
Yes
No
No
No
Yes
Yes
Yes
Yes
DS39544A-page 70
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set.
9.3.1.2
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
FIGURE 9-17:
I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address
A7 A6 A5 A4
R/W=0
Receiving Data
Receiving Data
ACK
ACK
9
ACK
9
SDA
SCL
A3 A2 A1
D5
D2
D0
8
D5
D2
D0
8
D7 D6
D4 D3
D1
7
D7 D6
D4 D3
D1
7
3
7
1
2
4
9
5
4
3
6
5
6
1
2
3
6
1
2
4
8
5
P
S
SSPIF (PIR1<3>)
Cleared in software
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
9.3.1.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then, pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON<4>). The master must monitor
the SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 9-18).
As a slave-transmitter, the ACK pulse from the mas-
ter-receiver is latched on the rising edge of the ninth
SCL input pulse. If the SDA line was high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset and the
slave then monitors for another occurrence of the
START bit. If the SDA line was low (ACK), the transmit
data must be loaded into the SSPBUF register, which
also loads the SSPSR register. Then, pin
RC3/SCK/SCL should be enabled by setting bit CKP.
FIGURE 9-18:
I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address
R/W = 1
ACK
Transmitting Data
ACK
9
SDA
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
P
SCL held low
while CPU
responds to SSPIF
Data in
sampled
Cleared in software
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
From SSP Interrupt
Service Routine
SSPBUF is written in software
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 71
PIC16C925/926
9.3.2
MASTER MODE
9.3.3
MULTI-MASTER MODE
Master mode of operation is supported, in firmware,
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a RESET, or when the
SSP module is disabled. The STOP and START bits
will toggle based on the START and STOP conditions.
Control of the I2C bus may be taken when the P bit is
set, or the bus is idle with both the S and P bits clear.
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the SSP module is disabled. The STOP and
START bits will toggle based on the START and STOP
conditions. Control of the I2C bus may be taken when
bit P (SSPSTAT<4>) is set, or the bus is idle, with both
the S and P bits clear. When the bus is busy, enabling
the SSP interrupt will generate the interrupt when the
STOP condition occurs.
In Master mode, the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
’1’ data bit must have the TRISC<4> bit set (input) and
a ’0’ data bit must have the TRISC<4> bit cleared (out-
put). The same scenario is true for the SCL line with the
TRISC<3> bit.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, they are:
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• Address Transfer
• Data Transfer
• START condition
• STOP condition
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time.
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode idle (SSPM3:SSPM0 = 1011), or with the
slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 9-4:
REGISTERS ASSOCIATED WITH I2C OPERATION
Value on
Power-on
Reset
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE TMR0IE INTE
RBIE TMR0IF INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
PIE1
LCDIF
LCDIE
ADIF
ADIE
—
—
—
—
SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000
SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000
8Ch
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
2
93h
SSPADD Synchronous Serial Port (I C mode) Address Register
14h
SSPCON
SSPSTAT
TRISC
WCOL SSPOV SSPEN
CKP
P
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h
SMP
CKE
D/A
S
R/W
UA
BF
0000 0000 0000 0000
87h
—
—
PORTC Data Direction Control Register
--11 1111 --11 1111
2
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by SSP in I C mode.
DS39544A-page 72
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
FIGURE 9-19:
OPERATION OF THE I2C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE
IDLE_MODE (7-bit):
if (Addr_match)
{
Set interrupt;
if (R/W = 1)
{
}
Send ACK = 0;
set XMIT_MODE;
else if (R/W = 0) set RCV_MODE;
}
RCV_MODE:
if ((SSPBUF = Full) OR (SSPOV = 1))
{
Set SSPOV;
Do not acknowledge;
}
{
else
transfer SSPSR → SSPBUF;
send ACK = 0;
}
Receive 8-bits in SSPSR;
Set interrupt;
XMIT_MODE:
While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low;
Send byte;
Set interrupt;
if ( ACK Received = 1)
{
}
End of transmission;
Go back to IDLE_MODE;
else if ( ACK Received = 0) Go back to XMIT_MODE;
IDLE_MODE (10-Bit):
If (High_byte_addr_match AND (R/W = 0))
{
PRIOR_ADDR_MATCH = FALSE;
Set interrupt;
if ((SSPBUF = Full) OR ((SSPOV = 1))
{
Set SSPOV;
Do not acknowledge;
}
{
else
Set UA = 1;
Send ACK = 0;
While (SSPADD not updated) Hold SCL low;
Clear UA = 0;
Receive Low_addr_byte;
Set interrupt;
Set UA = 1;
If (Low_byte_addr_match)
{
PRIOR_ADDR_MATCH = TRUE;
Send ACK = 0;
while (SSPADD not updated) Hold SCL low;
Clear UA = 0;
Set RCV_MODE;
}
}
}
else if (High_byte_addr_match AND (R/W = 1))
if (PRIOR_ADDR_MATCH)
{
{
send ACK = 0;
set XMIT_MODE;
}
else PRIOR_ADDR_MATCH = FALSE;
}
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 73
PIC16C925/926
NOTES:
DS39544A-page 74
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
The A/D module has four registers. These registers
are:
10.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register0 (ADCON0)
• A/D Control Register1 (ADCON1)
The Analog-to-Digital (A/D) Converter module has five
inputs.
The analog input charges a sample and hold capacitor.
The output of the sample and hold capacitor is the input
into the converter. The converter then generates a dig-
ital result of this analog level via successive approxima-
tion. The A/D conversion of the analog input signal
results in a corresponding 10-bit digital number. The
A/D module has high and low voltage reference input,
that is software selectable to some combination of VDD,
VSS, RA2 or RA3.
The ADCON0 register, shown in Register 10-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 10-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be the voltage refer-
ence), or as digital I/O.
Additional information on using the A/D module can be
found in the PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023).
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To
operate in SLEEP, the A/D clock must be derived from
the A/D’s internal RC oscillator.
REGISTER 10-1: ADCON0 REGISTER (ADDRESS: 1Fh)
R/W-0
R/W-0
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
U-0
R/W-0
ADON
ADCS1
ADCS0
GO/DONE
—
bit 7
bit 0
bit 7-6
bit 5-3
ADCS<1:0>: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from the internal A/D module RC oscillator)
CHS<2:0>: Analog Channel Select bits
000= channel 0 (RA0/AN0)
001= channel 1 (RA1/AN1)
010= channel 2 (RA2/AN2)
011= channel 3 (RA3/AN3)
100= channel 4 (RA5/AN4)
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1= A/D conversion in progress (setting this bit starts the A/D conversion)
0= A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D
conversion is complete)
bit 1
bit 0
Unimplemented: Read as '0'
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 75
PIC16C925/926
REGISTER 10-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
—
—
—
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1= Right justified. 6 Most Significant bits of ADRESH are read as ‘0’.
0= Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
bit 6-4
bit 3-0
Unimplemented: Read as '0'
PCFG<3:0>: A/D Port Configuration Control bits:
AN4
RA5
AN3
RA3
AN2
RA2
AN1
RA1
AN0
RA0
CHAN/
PCFG<3:0>
VREF+ VREF-
Refs(1)
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
A
VREF+
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
RA3
RA3
RA3
VDD
RA3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RA2
VSS
VSS
RA2
RA2
RA2
VSS
RA2
5/0
4/1
5/0
4/1
3/0
2/1
0/0
3/2
5/0
4/1
3/2
3/2
2/2
1/0
1/2
VREF+
A
VREF+
D
VREF+ VREF-
A
A
A
VREF+
VREF+ VREF-
VREF+ VREF-
VREF+ VREF-
D
D
VREF+ VREF-
D = Digital I/O
A = Analog input
Note 1: This column indicates the number of analog channels available as A/D inputs and
the number of analog channels used as voltage reference inputs.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result reg-
ister pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/D interrupt flag bit ADIF is set. The block dia-
gram of the A/D module is shown in Figure 10-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 10.1. After this
acquisition time has elapsed, the A/D conversion can
be started.
DS39544A-page 76
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
The following steps should be followed for doing an A/D
conversion:
3. Wait the required acquisition time.
4. Start conversion:
1. Configure the A/D module:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Configure analog pins/voltage reference/
and digital I/O (ADCON1)
• Polling for the GO/DONE bit to be cleared
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
(interrupts disabled)
OR
• Waiting for the A/D interrupt
6. Read
A/D
Result
register
pair
(ADRESH:ADRESL), clear bit ADIF if required.
• Set ADIE bit
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
• Set PEIE bit
• Set GIE bit
FIGURE 10-1:
A/D BLOCK DIAGRAM
CHS<2:0>
100
RA5/AN4
VAIN
011
(Input Voltage)
RA3/AN3/VREF+
010
RA2/AN2/VREF-
001
RA1/AN1
000
VDD
RA0/AN0
VREF+
A/D
Converter
(Reference
Voltage)
PCFG<3:0>
VREF-
(Reference
Voltage)
VSS
PCFG<3:0>
2001 Microchip Technology Inc.
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be decreased. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
10.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), see Figure 10-2. The maximum recom-
mended impedance for analog sources is 10 kΩ. As
the impedance is decreased, the acquisition time may
To calculate the minimum acquisition time,
Equation 10-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range Reference Manual
(DS33023).
EQUATION 10-1: ACQUISITION TIME EXAMPLE
TACQ
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
=
=
=
=
=
=
=
TAMP + TC + TCOFF
2µS + TC + [(Temperature -25°C)(0.05µS/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120pF (1kΩ + 7kΩ + 10kΩ) In(0.0004885)
16.47µS
2µS + 16.47µS + [(50°C -25°C)(0.05µS/°C)
19.72µS
TC
TACQ
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leak-
age specification.
4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 10-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
RS
CHOLD
CPIN
5 pF
= DAC Capacitance
= 120 pF
VA
I LEAKAGE
± 500 nA
VT = 0.6V
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
VDD 4V
3V
2V
= interconnect resistance
= sampling switch
SS
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 1011
Sampling Switch
(kΩ)
DS39544A-page 78
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For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
10.2 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The four possible options for TAD
are:
Table 10-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
• 2TOSC
• 8TOSC
• 32TOSC
• Internal A/D module RC oscillator
TABLE 10-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
Maximum Device Frequency
Max.
Operation
ADCS<1:0>
2TOSC
8TOSC
00
01
10
11
1.25 MHz
5 MHz
32TOSC
RC(1, 2, 3)
20 MHz
(Note 1)
Note 1: The RC source has a typical TAD time of 4 µs, but can vary between 2-6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recom-
mended for SLEEP operation.
3: For extended voltage devices (LC), please refer to the Electrical Specifications section.
2001 Microchip Technology Inc.
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10.3 Configuring Analog Port Pins
10.4 A/D Conversions
The ADCON1 and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2TAD wait is required before the next
acquisition is started. After this 2TAD wait, acquisition
on the selected channel is automatically started. After
this, the GO/DONE bit can be set to start the
conversion.
The A/D operation is independent of the state of the
CHS<2:0> bits and the TRIS bits.
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
In Figure 10-3, after the GO bit is set, the first time seg-
ment has a minimum of TCY and a maximum of TAD.
Note: The GO/DONE bit should NOT be set in
2: Analog levels on any pin that is defined as
a digital input (including the AN<4:0>
pins), may cause the input buffer to con-
sume current that is out of the device
specifications.
the same instruction that turns on the A/D.
FIGURE 10-3:
A/D CONVERSION TAD CYCLES
TCY to TAD
TAD1
TAD3
b8
TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b6 b5 b4 b3 b2 b1 b0
TAD2
b9
TAD4
b7
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input.
A 2TAD wait is necessary before the next
acquisition is started.
10.4.1
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 10-4 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ’0’s’. When an
A/D result will not overwrite these locations (A/D dis-
able), these registers may be used as two general pur-
pose 8-bit registers.
DS39544A-page 80
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2001 Microchip Technology Inc.
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FIGURE 10-4:
A/D RESULT JUSTIFICATION
10-Bit Result
ADFM = 0
ADFM = 1
0
7
7
2 1 0 7
0 7 6 5
0
0000 00
0000 00
ADRESH
ADRESL
ADRESH
ADRESL
10-bit Result
Right Justified
10-bit Result
Left Justified
Turning off the A/D places the A/D module in its lowest
current consumption state.
10.5 A/D Operation During SLEEP
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS<1:0> = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS<1:0> = 11). To allow the conver-
sion to occur during SLEEP, ensure the
SLEEPinstruction immediately follows the
instruction that sets the GO/DONE bit.
10.6 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion is aborted. All A/D input pins are con-
figured as analog inputs.
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
The value that is in the ADRESH:ADRESL registers is
not modified for
a
Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH A/D
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh
0Ch
8Ch
1Eh
9Eh
1Fh
9Fh
85h
05h
INTCON
PIR1
GIE
PEIE TMR0IE INTE
RBIE
SSPIF
SSPIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
LCDIF
LCDIE
ADIF
ADIE
(1)
(1)
(1)
(1)
CCP1IF TMR2IF TMR1IF r0rr 0000 r0rr 0000
CCP1IE TMR2IE TMR1IE r0rr 0000 r0rr 0000
xxxx xxxx uuuu uuuu
PIE1
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
ADCON0 ADCS1 ADCS0 CHS2
xxxx xxxx uuuu uuuu
CHS1
CHS0 GO/DONE
PCFG3 PCFG2
—
ADON 0000 00-0 0000 00-0
ADCON1
TRISA
ADFM
—
—
—
—
—
—
PCFG1 PCFG0 --0- 0000 --0- 0000
PORTA Data Direction Register
PORTA Data Latch when written: PORTA pins when read
--11 1111 --11 1111
PORTA
—
--0x 0000 --0u 0000
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These bits are reserved; always maintain these bits clear.
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NOTES:
DS39544A-page 82
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2001 Microchip Technology Inc.
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selecting the number of commons required by the LCD
panel, and then specifying the LCD frame clock rate to
be used by the panel.
11.0 LCD MODULE
The LCD module generates the timing control to drive
a static or multiplexed LCD panel, with support for up to
32 segments multiplexed with up to four commons. It
also provides control of the LCD pixel data.
Once the module is initialized for the LCD panel, the
individual bits of the LCD data registers are cleared/set
to represent a clear/dark pixel, respectively.
The interface to the module consists of 3 control regis-
ters (LCDCON, LCDSE, and LCDPS), used to define
the timing requirements of the LCD panel and up to 16
LCD data registers (LCD00-LCD15) that represent the
array of the pixel data. In normal operation, the control
registers are configured to match the LCD panel being
used. Primarily, the initialization information consists of
Once the module is configured, the LCDEN
(LCDCON<7>) bit is used to enable or disable the LCD
module. The LCD panel can also operate during
SLEEP by clearing the SLPEN (LCDCON<6>) bit.
Figure 11-2 through Figure 11-5 provides waveforms
for static, half-duty cycle, one-third-duty cycle, and
quarter-duty cycle drives.
REGISTER 11-1: LCDCON REGISTER (ADDRESS 10Fh)
R/W-0
R/W-0
R/W-0
WERR
R/W-0
BIAS
R/W-0
CS1
R/W-0
CS0
R/W-0
R/W-0
LCDEN
SLPEN
LMUX1
LMUX0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3-2
LCDEN: Module Drive Enable bit
1= LCD drive enabled
0= LCD drive disabled
SLPEN: LCD Display Enabled to SLEEP bit
1= LCD module will stop driving in SLEEP
0= LCD module will continue driving in SLEEP
WERR: Write Failed Error bit
1= System tried to write LCDD register during disallowed time. (Must be reset in software.)
0= No error
BIAS: Bias Generator Enable bit
0= Internal bias generator powered down, bias is expected to be provided externally
1= Internal bias generator enabled, powered up
CS<1:0>: Clock Source bits
00= FOSC/256
01= T1CKI (Timer1)
1x= Internal RC oscillator
bit 1-0
LMUX<1:0>: Common Selection bits
Specifies the number of commons
00= Static(COM0)
01= 1/2 (COM0, 1)
10= 1/3 (COM0, 1, 2)
11= 1/4 (COM0, 1, 2, 3)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 83
PIC16C925/926
FIGURE 11-1:
LCD MODULE BLOCK DIAGRAM
128
to
LCD
RAM
SEG<31:0>
Data Bus
To I/O Pads
32 x 4
32
MUX
Timing Control
LCDCON
LCDPS
LCDSE
COM3:COM0
To I/O Pads
Internal RC osc
T1CKI
Clock
Source
Select
and
FOSC/4
Divide
REGISTER 11-2: LCDPS REGISTER (ADDRESS 10Eh)
U-0
U-0
U-0
U-0
R/W-0
LP3
R/W-0
LP2
R/W-0
LP1
R/W-0
LP0
—
—
—
—
bit 7
bit 0
bit 7-4
bit 3-0
Unimplemented: Read as '0'
LP<3:0>: Frame Clock Prescale Selection bits (see Section 11.1.2)
LMUX1:LMUX0
Multiplex
Frame Frequency
00
01
10
11
Static
1/2
Clock source/(128 * (LP3:LP0 + 1))
Clock source/(128 * (LP3:LP0 + 1))
Clock source/(96 * (LP3:LP0 + 1))
Clock source/(128 * (LP3:LP0 + 1))
1/3
1/4
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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Preliminary
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FIGURE 11-2:
WAVEFORMS IN STATIC DRIVE
Liquid Crystal Display
and Terminal Connection
1/1 V
PIN
COM0
0/1 V
1/1 V
COM0
SEG7
PIN
SEG0
0/1 V
1/1 V
PIN
SEG1
SEG6
SEG5
0/1 V
1/1 V
COM0 - SEG0
0/1 V
Selected Waveform
-1/1 V
0/1 V
1 frame
t
f
COM0 - SEG1
Non-selected Waveform
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 85
PIC16C925/926
FIGURE 11-3:
WAVEFORMS IN HALF-DUTY CYCLE DRIVE (B TYPE)
Liquid Crystal Display
and Terminal Connection
2/2 V
1/2 V
PIN
COM0
0/2 V
2/2 V
1/2 V
COM1
COM0
PIN
COM1
0/2 V
2/2 V
PIN
SEG0
0/2 V
2/2 V
0/2 V
PIN
SEG1
2/2 V
1/2 V
0/2 V
-1/2 V
-2/2 V
COM0 - SEG0
Selected Waveform
2/2 V
0/2 V
-2/2 V
COM0 - SEG1
Non-selected Waveform
1 frame
t
f
DS39544A-page 86
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2001 Microchip Technology Inc.
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FIGURE 11-4:
WAVEFORMS IN ONE-THIRD DUTY CYCLE DRIVE (B TYPE)
3/3 V
2/3 V
Liquid Crystal Display
and Terminal Connection
PIN
COM0
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
COM2
PIN
COM1
COM1
COM0
3/3 V
2/3 V
1/3 V
PIN
COM2
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
PIN
SEG0
3/3 V
2/3 V
1/3 V
0/3 V
SEG0
SEG2
SEG1
PIN
SEG1
3/3 V
2/3 V
1/3 V
0/3 V
-1/3 V
COM0 - SEG1
Selected Waveform
-2/3 V
-3/3 V
1/3 V
0/3 V
-1/3 V
COM0 - SEG0
Non-selected Waveform
1 frame
t
f
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 87
PIC16C925/926
FIGURE 11-5:
WAVEFORMS IN QUARTER-DUTY CYCLE DRIVE (B TYPE)
3/3 V
2/3 V
Liquid Crystal Display
and Terminal Connection
PIN
COM0
COM3
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
COM2
PIN
COM1
COM1
COM0
3/3 V
2/3 V
1/3 V
PIN
COM2
0/3 V
3/3 V
PIN
COM3
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
PIN
SEG0
SEG0 SEG1
3/3 V
2/3 V
1/3 V
0/3 V
PIN
SEG1
3/3 V
2/3 V
1/3 V
0/3 V
-1/3 V
COM3 - SEG0
Selected Waveform
-2/3 V
-3/3 V
1/3 V
0/3 V
-1/3 V
COM0 - SEG0
Non-selected Waveform
1 frame
t
f
DS39544A-page 88
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
The second source is the Timer1 external oscillator.
This oscillator provides a lower speed clock which may
be used to continue running the LCD while the proces-
sor is in SLEEP. It is assumed that the frequency pro-
vided on this oscillator will be 32 kHz. To use the
Timer1 oscillator as a LCD module clock source, it is
only necessary to set the T1OSCEN (T1CON<3>) bit.
11.1 LCD Timing
The LCD module has 3 possible clock source inputs
and supports static, 1/2, 1/3, and 1/4 multiplexing.
11.1.1
TIMING CLOCK SOURCE
SELECTION
The clock sources for the LCD timing generation are:
The third source is the system clock divided by 256.
This divider ratio is chosen to provide about 32 kHz
output when the external oscillator is 8 MHz. The
divider is not programmable. Instead the LCDPS regis-
ter is used to set the LCD frame clock rate.
• Internal RC oscillator
• Timer1 oscillator
• System clock divided by 256
The first timing source is an internal RC oscillator which
runs at a nominal frequency of 14 kHz. This oscillator
provides a lower speed clock which may be used to
continue running the LCD while the processor is in
SLEEP. The RC oscillator will power-down when it is
not selected or when the LCD module is disabled.
All of the clock sources are selected with bits CS1:CS0
(LCDCON<3:2>). Refer to Register 11-1 for details of
the register programming.
FIGURE 11-6:
LCD CLOCK GENERATION
FOSC
÷256
CPCLK
Static
1/2
÷4
÷2
÷1,2,3,4
Ring Counter
÷32
4-bit Programmable
Prescaler
TMR1 32 kHz
Crystal Oscillator
1/3
1/4
LCDPS<3:0>
LMUX1:LMUX0
LMUX1:LMUX0
Internal RC Oscillator
Nominal FRC = 14 kHz
CS1:CS0
internal
Data Bus
2001 Microchip Technology Inc.
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11.1.2
MULTIPLEX TIMING GENERATION
TABLE 11-2: APPROXIMATE FRAME
FREQUENCY (IN Hz)
The timing generation circuitry will generate one to four
common clocks based on the display mode selected.
The mode is specified by bits LMUX1:LMUX0
(LCDCON<1:0>). Table 11-1 shows the formulas for
calculating the frame frequency.
USING TIMER1 @ 32.768 kHz
OR FOSC @ 8 MHz
LP3:LP0
Static
1/2
1/3
1/4
2
3
4
5
6
7
85
64
51
43
37
32
85
64
51
43
37
32
114
85
68
57
49
43
85
64
51
43
37
32
TABLE 11-1: FRAME FREQUENCY
FORMULAS
Multiplex
Frame Frequency =
Static
1/2
Clock source/(128 * (LP3:LP0 + 1))
Clock source/(128 * (LP3:LP0 + 1))
Clock source/(96 * (LP3:LP0 + 1))
Clock source/(128 * (LP3:LP0 + 1))
1/3
TABLE 11-3: APPROXIMATE FRAME
FREQUENCY (IN Hz)
1/4
USING INTERNAL RC OSC
@ 14 kHz
LP3:LP0
Static
1/2
1/3
1/4
0
1
2
3
109
55
109
55
146
73
109
55
36
36
49
36
27
27
36
27
DS39544A-page 90
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A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes
accessing all pixel data required for a frame. This will
occur at a fixed interval before the frame boundary
(TFINT), as shown in Figure 11-7. The LCD controller
will begin to access data for the next frame within the
interval from the interrupt to when the controller begins
to access data after the interrupt (TFWR). New data
must be written within TFWR, as this is when the LCD
controller will begin to access the data for the next
frame.
11.2 LCD Interrupts
The LCD timing generation provides an interrupt that
defines the LCD frame timing. This interrupt can be
used to coordinate the writing of the pixel data with the
start of a new frame. Writing pixel data at the frame
boundary allows a visually crisp transition of the image.
This interrupt can also be used to synchronize external
events to the LCD. For example, the interface to an
external segment driver, such as a Microchip AY0438,
can be synchronized for segment data update to the
LCD frame.
FIGURE 11-7:
EXAMPLE WAVEFORMS AND INTERRUPT TIMING
IN QUARTER-DUTY CYCLE DRIVE
LCD
Interrupt
Occurs
Controller Accesses
Next Frame Data
3/3 V
2/3 V
1/3 V
0/3 V
COM0
COM1
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
COM2
COM3
3/3 V
2/3 V
1/3 V
0/3 V
1 Frame
TFINT
TFWR
Frame
Boundary
Frame
Boundary
TFWR = TFRAME/(LMUX1:LMUX0 + 1) + TCY/2
TFINT = (TFWR /2 - (2TCY + 40 ns)) → minimum = 1.5(TFRAME/4) - (2TCY + 40ns)
(TFWR /2 - (1TCY + 40 ns)) → maximum = 1.5(TFRAME/4) - (1TCY + 40 ns)
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Table 11-4 shows the correlation of each bit in the
LCDD registers to the respective common and seg-
ment signals.
11.3 Pixel Control
11.3.1
LCDD (PIXEL DATA) REGISTERS
Any LCD pixel location not being used for display can
be used as general purpose RAM.
The pixel registers contain bits which define the state of
each pixel. Each bit defines one unique pixel.
REGISTER 11-3: GENERIC LCDD REGISTER LAYOUT
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SEGs
COMc
SEGs
COMc
SEGs
COMc
SEGs
COMc
SEGs
COMc
SEGs
COMc
SEGs
COMc
SEGs
COMc
bit 7
bit 0
bit 7-0
SEGsCOMc: Pixel Data bit for Segment S and Common C
1= Pixel on (dark)
0= Pixel off (clear)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39544A-page 92
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If a SLEEPinstruction is executed and SLPEN = ’0’, the
module will continue to display the current contents of
the LCDD registers. To allow the module to continue
operation while in SLEEP, the clock source must be
either the internal RC oscillator or Timer1 external
oscillator. While in SLEEP, the LCD data cannot be
changed. The LCD module current consumption will
not decrease in this mode, however, the overall con-
sumption of the device will be lower due to shut-down
of the core and other peripheral functions.
11.4 Operation During SLEEP
The LCD module can operate during SLEEP. The
selection is controlled by bit SLPEN (LCDCON<6>).
Setting the SLPEN bit allows the LCD module to go to
SLEEP. Clearing the SLPEN bit allows the module to
continue to operate during SLEEP.
If a SLEEPinstruction is executed and SLPEN = ’1’, the
LCD module will cease all functions and go into a very
low current consumption mode. The module will stop
operation immediately and drive the minimum LCD
voltage on both segment and common lines. Figure
11-8 shows this operation. To ensure that the LCD com-
pletes the frame, the SLEEPinstruction should be exe-
cuted immediately after a LCD frame boundary. The
LCD interrupt can be used to determine the frame
boundary. See Section 11.2 for the formulas to calcu-
late the delay.
Note: The internal RC oscillator or external
Timer1 oscillator must be used to operate
the LCD module during SLEEP.
FIGURE 11-8:
SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS1:CS0 = 00
3/3V
2/3V
1/3V
Pin
COM0
0/3V
3/3V
2/3V
1/3V
0/3V
3/3V
2/3V
Pin
COM1
Pin
COM3
1/3V
0/3V
3/3V
2/3V
Pin
SEG0
1/3V
0/3V
Interrupted
Frame
Wake-up
SLEEPInstruction Execution
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 93
PIC16C925/926
11.4.1
SEGMENT ENABLES
EXAMPLE 11-1:
STATIC MUX WITH 32
SEGMENTS
The LCDSE register is used to select the pin function
for groups of pins. The selection allows each group of
pins to operate as either LCD drivers or digital only
pins. To configure the pins as a digital port, the corre-
sponding bits in the LCDSE register must be cleared.
BCF
BSF
BCF
BCF
STATUS,RP0
STATUS,RP1
LCDCON,LMUX1 ;Select Static MUX
LCDCON,LMUX0 ;
;Select Bank 2
;
MOVLW 0xFF
MOVWF LCDSE
. . .
;Make PortD,E,F,G
;LCD pins
;configure rest of LCD
If the pin is a digital I/O the corresponding TRIS bit con-
trols the data direction. Any bit set in the LCDSE regis-
ter overrides any bit settings in the corresponding TRIS
register.
EXAMPLE 11-2:
ONE-THIRD DUTY CYCLE
WITH 13 SEGMENTS
Note 1: On a Power-on Reset, these pins are
BCF
BSF
BSF
BCF
STATUS,RP0
STATUS,RP1
LCDCON,LMUX1 ;Select 1/3 MUX
LCDCON,LMUX0 ;
;Select Bank 2
;
configured as LCD drivers.
2: The LMUX1:LMUX0 takes precedence
over the LCDSE bit settings for pins RD7,
RD6 and RD5.
MOVLW 0x87
MOVWF LCDSE
. . .
;Make PORTD<7:0> &
;PORTE<6:0> LCD pins
;configure rest of LCD
REGISTER 11-4:
LCDSE REGISTER (ADDRESS 10Dh)
R/W-1
SE29
R/W-1
SE27
R/W-1
SE20
R/W-1
SE16
R/W-1
SE12
R/W-1
SE9
R/W-1
SE5
R/W-1
SE0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SE29: Pin Function Select RD7/COM1/SEG31 - RD5/COM3/SEG29
1= Pins have LCD drive function
0= Pins have digital Input function
SE27: Pin Function Select RG7/SEG28 and RE7/SEG27
1= Pins have LCD drive function
0= Pins have LCD drive function
SE20: Pin Function Select RG6/SEG26 - RG0/SEG20
1= Pins have LCD drive function
0= Pins have digital Input function
SE16: Pin Function Select RF7/SEG19 - RF4/SEG16
1= Pins have LCD drive function
0= Pins have digital Input function
SE12: Pin Function Select RF3/SEG15 - RF0/SEG12
1= Pins have LCD drive function
0= Pins have digital Input function
SE9: Pin Function Select RE6/SEG11 - RE4/SEG09
1= Pins have LCD drive function
0= Pins have digital Input function
SE5: Pin Function Select RE3/SEG08 - RE0/SEG05
1= Pins have LCD drive function
0= Pins have digital Input function
SE0: Pin Function Select RD4/SEG04 - RD0/SEG00
1= Pins have LCD drive function
0= Pins have digital Input function
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39544A-page 94
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
pump. The charge pump boosts VLCD1 into VLCD2 =
2*VLCD1 and VLCD3 = 3 * VLCD1. When the charge
pump is not operating, Vlcd3 will be internally tied to
VDD. See the Electrical Specifications section for
charge pump capacitor and potentiometer values.
11.5 Voltage Generation
There are two methods for LCD voltage generation:
internal charge pump, or external resistor ladder.
11.5.1
CHARGE PUMP
11.5.2
EXTERNAL R-LADDER
The LCD charge pump is shown in Figure 11-9. The
1.0V - 2.3V regulator will establish a stable base volt-
age from the varying battery voltage. This regulator is
adjustable through the range by connecting a variable
external resistor from VLCDADJ to ground. The poten-
tiometer provides contrast adjustment for the LCD. This
base voltage is connected to VLCD1 on the charge
The LCD module can also use an external resistor lad-
der (R-Ladder) to generate the LCD voltages.
Figure 11-9 shows external connections for static and
1/3 bias. The VGEN (LCDCON<4>) bit must be cleared
to use an external R-Ladder.
FIGURE 11-9:
CHARGE PUMP AND RESISTOR LADDER
CPCLK
VGEN
Control
Logic
3
2
C
C
VDD
2
3
10 µA
C+ VGEN
VGEN
2
3
Regulator
VLCD3
VLCD2
VLCD1
VLCD0
To
LCD
Drivers
VLCD3
VLCD2
VLCD1
C1 C2
VLCDADJ
100 kΩ*
130 kΩ*
0.47 µF*
0.47 µF*
0.47 µF*
Connections for
internal charge
pump, VGEN = 1
0.47 µF*
Connections for
external R-ladder,
1/3 Bias,
10 kΩ*
10 kΩ*
10 kΩ*
10 kΩ*
5 kΩ*
VGEN = 0
VLCD3
VLCD3
Connections for
external R-ladder,
Static Bias,
5 kΩ*
VGEN = 0
* These values are provided for design guidance only and should be optimized to the application by the designer.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 95
PIC16C925/926
4. Write initial values to pixel data registers,
LCDD00 through LCDD15.
11.6 Configuring the LCD Module
The following is the sequence of steps to follow to con-
figure the LCD module.
5. Clear LCD interrupt flag, LCDIF (PIR1<7>), and
if desired, enable the interrupt by setting bit
LCDIE (PIE1<7>).
1. Select the frame clock prescale using bits
LP3:LP0 (LCDPS<3:0>).
6. Enable the LCD module, by setting bit LCDEN
(LCDCON<7>).
2. Configure the appropriate pins to function as
segment drivers using the LCDSE register.
3. Configure the LCD module for the following
using the LCDCON register:
- Multiplex mode and Bias, bits
LMUX1:LMUX0
- Timing source, bits CS1:CS0
- Voltage generation, bit VGEN
- SLEEP mode, bit SLPEN
TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE LCD MODULE
Value on
Power-on
Reset
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
PIR1
PIE1
LCDIF
LCDIE
ADIF
ADIE
—
—
—
—
SSPIF
SSPIE
CCP1IF TMR2IF
CCP1IE TMR2IE
TMR1IF 00-- 0000 00-- 0000
TMR1IE 00-- 0000 00-- 0000
10h
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
--00 0000 --uu uuuu
xxxx xxxx uuuu uuuu
SEG07
COM0
SEG06
COM0
SEG05
COM0
SEG04
COM0
SEG03
COM0
SEG02
COM0
SEG01
COM0
SEG00
COM0
110h
LCDD00
SEG15
COM0
SEG14
COM0
SEG13
COM0
SEG12
COM0
SEG11
COM0
SEG10
COM0
SEG09
COM0
SEG08
COM0
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
LCDD01
LCDD02
LCDD03
LCDD04
LCDD05
LCDD06
LCDD07
LCDD08
LCDD09
LCDD10
LCDD11
LCDD12
LCDD13
LCDD14
LCDD15
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
SEG23
COM0
SEG22
COM0
SEG21
COM0
SEG20
COM0
SEG19
COM0
SEG18
COM0
SEG17
COM0
SEG16
COM0
SEG31
COM0
SEG30
COM0
SEG29
COM0
SEG28
COM0
SEG27
COM0
SEG26
COM0
SEG25
COM0
SEG24
COM0
SEG07
COM1
SEG06
COM1
SEG05
COM1
SEG04
COM1
SEG03
COM1
SEG02
COM1
SEG01
COM1
SEG00
COM1
SEG15
COM1
SEG14
COM1
SEG13
COM1
SEG12
COM1
SEG11
COM1
SEG10
COM1
SEG09
COM1
SEG08
COM1
SEG23
COM1
SEG22
COM1
SEG21
COM1
SEG20
COM1
SEG19
COM1
SEG18
COM1
SEG17
COM1
SEG16
COM1
SEG31
SEG30
COM1
SEG29
COM1
SEG28
COM1
SEG27
COM1
SEG26
COM1
SEG25
COM1
SEG24
COM1
COM1(1)
SEG07
COM2
SEG06
COM2
SEG05
COM2
SEG04
COM2
SEG03
COM2
SEG02
COM2
SEG01
COM2
SEG00
COM2
SEG15
COM2
SEG14
COM2
SEG13
COM2
SEG12
COM2
SEG11
COM2
SEG10
COM2
SEG09
COM2
SEG08
COM2
SEG23
COM2
SEG22
COM2
SEG21
COM2
SEG20
COM2
SEG19
COM2
SEG18
COM2
SEG17
COM2
SEG16
COM2
SEG31
SEG30
SEG29
COM2
SEG28
COM2
SEG27
COM2
SEG26
COM2
SEG25
COM2
SEG24
COM2
COM2(1) COM2(1)
SEG07
COM3
SEG06
COM3
SEG05
COM3
SEG04
COM3
SEG03
COM3
SEG02
COM3
SEG01
COM3
SEG00
COM3
SEG15
COM3
SEG14
COM3
SEG13
COM3
SEG12
COM3
SEG11
COM3
SEG10
COM3
SEG09
COM3
SEG08
COM3
SEG23
COM3
SEG22
COM3
SEG21
COM3
SEG20
COM3
SEG19
COM3
SEG18
COM3
SEG17
COM3
SEG16
COM3
SEG31
SEG30
SEG29
SEG28
COM3
SEG27
COM3
SEG26
COM3
SEG25
COM3
SEG24
COM3
COM3(1) COM3(1) COM3(1)
10Dh
10Eh
LCDSE
LCDPS
SE29
SE27
—
SE20
—
SE16
—
SE12
LP3
SE9
LP2
CS0
SE5
LP1
SE0
LP0
1111 1111 1111 1111
---- 0000 ---- 0000
00-0 0000 00-0 0000
—
10Fh
LCDCON LCDEN
SLPEN
—
VGEN
CS1
LMUX1
LMUX0
Legend:
x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the LCD module.
Note 1: These pixels do not display, but can be used as general purpose RAM.
DS39544A-page 96
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
RESET while the power supply stabilizes. With these
two timers on-chip, most applications need no external
RESET circuitry.
12.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of real
time applications. The PIC16CXXX family has a host of
such features, intended to maximize system reliability,
minimize cost through elimination of external compo-
nents, provide power saving operating modes and offer
code protection. These are:
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external RESET, Watchdog Timer Wake-up, or
through an interrupt.
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost, while the LP crystal option
saves power. A set of configuration bits are used to
select various options.
• Oscillator Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
12.1 Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
• Watchdog Timer (WDT)
• SLEEP
The user will note that address 2007h is beyond the user
program memory space and can be accessed only dur-
ing programming.
• Code Protection
• ID Locations
• In-Circuit Serial Programming
The PIC16CXXX has a Watchdog Timer which can be
shut-off only through configuration bits. It runs off its
own RC oscillator for added reliability.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nomi-
nal) on power-up only, designed to keep the part in
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 97
PIC16C925/926
REGISTER 12-1: CONFIGURATION WORD (ADDRESS 2007h)
—
—
—
—
—
—
—
BOREN CP1
CP0 PWRTE WDTE F0SC1 F0SC0
bit0
bit13
bit 13-7
bit 6
Unimplemented
BOREN: Brown-out Reset Enable bit
1= BOR enabled
0= BOR disabled
bit 5-4
CP1:CP0: Program Memory Code Protection bits
PIC16C926 (8K program memory):
11= Code protection off
10= 0000h to 0FFFh code protected (1/2 protected)
01= 0000h to 1EFFh code protected (all but last 256 protected)
00= 0000h to 1FFFh code protected (all protected)
PIC16C925 (4K program memory):
11= Code protection off
10= 0000h to 07FFh code protected (1/2 protected)
01= 0000h to 0EFFh code protected (all but last 256 protected)
00= 0000h to 0FFFh code protected (all protected)
1000h to 1FFFh wraps around to 0000h to 0FFFh
bit 3
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
bit 2
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
DS39544A-page 98
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
TABLE 12-1: CERAMIC RESONATORS
Ranges Tested:
12.2 Oscillator Configurations
12.2.1 OSCILLATOR TYPES
Mode
Freq.
C1
C2
The PIC16CXXX can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF 68 - 100 pF
15 - 68 pF
15 - 68 pF
XT
HS
15 - 68 pF
15 - 68 pF
• LP
• XT
• HS
• RC
Low Power Crystal
8.0 MHz
10 - 68 pF
10 - 68 pF
Crystal/Resonator
These values are for design guidance only.
See notes following Table 12-2.
High Speed Crystal/Resonator
Resistor/Capacitor
TABLE 12-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
12.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
Cap.
Range
C2
Crystal
Freq.
Cap. Range
C1
In XT, LP, or HS modes a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 12-1). The
PIC16CXXX oscillator design requires the use of a par-
allel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifica-
tions. When in XT, LP, or HS modes, the device can
have an external clock source to drive the
OSC1/CLKIN pin (Figure 12-2).
Osc Type
32 kHz
200 kHz
200 kHz
1 MHz
33 pF
15 pF
33 pF
15 pF
LP
XT
HS
47-68 pF
15 pF
47-68 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
FIGURE 12-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS, XT OR LP
8 MHz
15-33 pF
15-33 pF
These values are for design guidance only.
See notes following this table.
OSC CONFIGURATION)
OSC1
Note 1: Recommended ranges of C1 and C2 are
depicted in Table 12-1.
To Internal
Logic
SLEEP
C1
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
XTAL
OSC2
RS
C2 (Note 1)
RF
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents.
PIC16CXXX
See Table 12-1 and Table 12-2 for recommended values
of C1 and C2.
4: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
Note 1: A series resistor may be required for AT strip
cut crystals.
FIGURE 12-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
OSC1
Clock from
Ext. System
PIC16CXXX
OSC2
Open
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 99
PIC16C925/926
12.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
12.2.4
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used. Figure 12-5 shows how the R/C combina-
tion is connected to the PIC16CXXX. For REXT values
below 2.2 kΩ, the oscillator operation may become
unstable, or stop completely. For very high REXT values
(e.g. 1 MΩ), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend to keep
REXT between 3 kΩ and 100 kΩ.
Either a prepackaged oscillator can be used, or a sim-
ple oscillator circuit with TTL gates can be built. Pre-
packaged oscillators provide a wide operating range
and better stability. A well designed crystal oscillator
will provide good performance with TTL gates. Two
types of crystal oscillator circuits can be used: one with
series resonance, or one with parallel resonance.
Figure 12-3 shows implementation of a parallel reso-
nant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a par-
allel oscillator requires. The 4.7 kΩ resistor provides
the negative feedback for stability. The 10 kΩ potenti-
ometer biases the 74AS04 in the linear region. This
could be used for external oscillator designs.
FIGURE 12-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance, or pack-
age lead frame capacitance.
+5V
To Other
Devices
10k
74AS04
4.7k
PIC16CXXX
74AS04
CLKIN
See characterization data for desired device for RC fre-
quency variation from part to part, due to normal pro-
cess variation. The variation is larger for larger R (since
leakage current variation will affect RC frequency more
for large R) and for smaller C (since variation of input
capacitance will affect RC frequency more).
10k
XTAL
10k
See characterization data for desired device for varia-
tion of oscillator frequency, due to VDD for given
REXT/CEXT values, as well as frequency variation due
to operating temperature for given R, C, and VDD
values.
20 pF
20 pF
Figure 12-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental fre-
quency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 kΩ resistors provide the negative feed-
back to bias the inverters in their linear region.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test pur-
poses or to synchronize other logic (see Figure 1-2 for
waveform).
FIGURE 12-5:
RC OSCILLATOR MODE
FIGURE 12-4:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
VDD
REXT
Internal
OSC1
To Other
Devices
330 kΩ
330 kΩ
Clock
74AS04
74AS04
74AS04
CEXT
VSS
PIC16CXXX
CLKIN
0.1 µF
OSC2/CLKOUT
FOSC/4
XTAL
PIC16CXXX
DS39544A-page 100
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
SLEEP. They are not affected by a WDT Wake-up,
which is viewed as the resumption of normal operation.
The TO and PD bits are set or cleared differently in dif-
ferent RESET situations, as indicated in Table 12-4.
These bits are used in software to determine the nature
of the RESET. See Table 12-6 for a full description of
RESET states of all registers.
12.3 RESET
The PIC16C9XX differentiates between various kinds
of RESET:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (normal operation)
• Brown-out Reset (BOR)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 12-6.
The devices all have a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
Some registers are not affected in any RESET condi-
tion; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset (POR), on the
MCLR and WDT Reset, and on MCLR Reset during
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 12-6:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT
Module
WDT
Time-out
Reset
VDD Rise
Detect
Power-on
Reset
VDD
Brown-out
Reset
S
BOREN
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
R
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple Counter
Enable PWRT(2)
Enable OST(2)
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: See Table 12-3 for various time-out situations.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 101
PIC16C925/926
12.4.4
BROWN-OUT RESET (BOR)
12.4 Power-on Reset (POR),
Power-up Timer (PWRT),
The configuration bit, BOREN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100µS), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a RESET may not occur.
Brown-out Reset (BOR) and
Oscillator Start-up Timer (OST)
12.4.1
POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will elimi-
nate external RC components usually needed to create
a Power-on Reset. A maximum rise time for VDD is
specified. See Electrical Specifications for details.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer, if enabled, then keeps the device in
RESET for TPWRT (parameter #33, about 72mS). If
VDD should fall below VBOR during TPWRT, the
Brown-out Reset process will restart when VDD rises
above VBOR with the Power-up Timer Reset. The
Power-up Timer is enabled separately from Brown-out
Reset.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met.
12.4.5
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 12-7, Figure 12-8, and Figure 12-9 depict
time-out sequences on power-up.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting.”
12.4.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in RESET as long as the PWRT is
active. The PWRT’s time delay allows VDD to rise to an
acceptable level. A configuration bit is provided to
enable/disable the PWRT.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 12-8). This is useful for testing purposes or to
synchronize more than one PIC16CXXX device oper-
ating in parallel.
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variation. See DC
parameters for details.
Table 12-5 shows the RESET conditions for some spe-
cial function registers, while Table 12-6 shows the
RESET conditions for all the registers.
12.4.3
OSCILLATOR START-UP TIMER
(OST)
12.4.6
POWER CONTROL/STATUS
REGISTER (PCON)
The Oscillator Start-up Timer (OST), if enabled, pro-
vides 1024 oscillator cycle (from OSC1 input) delay
after the PWRT delay (if the PWRT is enabled). This
helps to ensure that the crystal oscillator or resonator
has started and stabilized.
The Power Control/Status Register, PCON, has up to
two bits depending upon the device.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent RESETS to see if
bit BOR cleared, indicating a BOR occurred. When the
Brown-out Reset is disabled, the state of the BOR bit is
unpredictable and is, therefore, not valid at any time.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
Bit1 is Power-on Reset Status bit POR. It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
TABLE 12-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up
Oscillator Configuration
Wake-up from SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
RC
1024TOSC
72 ms + 1024TOSC
72 ms
1024 TOSC
—
—
DS39544A-page 102
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
TABLE 12-4: STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
Condition
0
0
0
1
1
1
1
1
x
x
x
0
1
1
1
1
1
0
x
1
0
0
u
1
1
x
0
1
1
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 12-5: RESET CONDITION FOR SPECIAL REGISTERS
Program
STATUS
Register
PCON
Register
Condition
Counter
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
WDT Wake-up
PC + 1
Brown-out Reset
000h
PC + 1(1)
Interrupt wake-up from SLEEP
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 103
PIC16C925/926
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Wake-up via
WDT or
Interrupt
MCLR Resets
WDT Reset
Register
Power-on Reset
W
xxxx xxxx
N/A
uuuu uuuu
N/A
uuuu uuuu
N/A
INDF
TMR0
xxxx xxxx
0000h
uuuu uuuu
uuuu uuuu
PC + 1(2)
PCL
0000h
STATUS
FSR
0001 1xxx
xxxx xxxx
--0x 0000
xxxx xxxx
--xx xxxx
0000 0000
0000 0000
---0 0000
0000 000x
00-- 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
000q quuu(3)
uuuu uuuu
--0u 0000
uuuu uuuu
--uu uuuu
0000 0000
0000 0000
---0 0000
0000 000u
00-- 0000
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuq quuu(3)
uuuu uuuu
--uu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu(1)
uu-- uuuu(1)
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRES
xxxx xxxx
0000 00-0
1111 1111
--11 1111
1111 1111
--11 1111
1111 1111
1111 1111
00-- 0000
---- --0-
uuuu uuuu
0000 00-0
1111 1111
--11 1111
1111 1111
--11 1111
1111 1111
1111 1111
00-- 0000
---- --u-
uuuu uuuu
uuuu uu-u
uuuu uuuu
--uu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uu-- uuuu
---- --u-
ADCON0
OPTION_REG
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
PCON
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for RESET value for specific condition.
DS39544A-page 104
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Wake-up via
WDT or
Interrupt
MCLR Resets
WDT Reset
Register
Power-on Reset
PR2
1111 1111
0000 0000
0000 0000
---- -000
0000 0000
0000 0000
1111 1111
---- 0000
00-0 0000
1111 1111
0000 0000
0000 0000
---- -000
0000 0000
0000 0000
1111 1111
---- 0000
00-0 0000
1111 1111
uuuu uuuu
uuuu uuuu
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
uu-u uuuu
SSPADD
SSPSTAT
ADCON1
PORTF
PORTG
LCDSE
LCDPS
LCDCON
LCDD00
to
xxxx xxxx
uuuu uuuu
uuuu uuuu
LCDD15
TRISF
TRISG
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
uuuu uuuu
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for RESET value for specific condition.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 105
PIC16C925/926
FIGURE 12-7:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 12-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 12-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
DS39544A-page 106
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
12.5 Interrupts
The PIC16C925/926 family has nine sources of
interrupt:
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
• External interrupt RB0/INT
• TMR0 overflow interrupt
• PORTB change interrupts
(pins RB7:RB4)
The peripheral interrupt flags are contained in the spe-
cial function register, PIR1. The corresponding inter-
rupt enable bits are contained in special function
register, PIE1, and the peripheral interrupt enable bit is
contained in special function register, INTCON.
• A/D Interrupt
• TMR1 overflow interrupt
• TMR2 matches period interrupt
• CCP1 interrupt
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupts, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
• Synchronous serial port interrupt
• LCD module interrupt
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
Note: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit, or the GIE bit.
For external interrupt events, such as the RB0/INT pin
or RB Port change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs
(Figure 12-11). The latency is the same for one or two
cycle instructions. Individual interrupt flag bits are set,
regardless of the status of their corresponding mask
bit, PEIE bit, or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
FIGURE 12-10:
INTERRUPT LOGIC
TMR1IF
TMR1IE
Wake-up (If in SLEEP mode)
TMR0IF
TMR0IE
INTF
INTE
TMR2IF
TMR2IE
Interrupt to CPU
RBIF
RBIE
LCDIF
LCDIE
PEIF
PEIE
GIE
CCP1IF
CCP1IE
SSPIF
SSPIE
ADIF
ADIE
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 107
PIC16C925/926
FIGURE 12-11:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
3
4
INT pin
1
1
INTF Flag
(INTCON<1>)
Interrupt Latency
5
2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
0004h
0005h
PC
PC+1
PC+1
Instruction
Inst (PC)
Inst (PC+1)
—
Inst (0004h)
Inst (0005h)
Inst (0004h)
Fetched
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC-1)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single
cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF can be set any time during the Q4-Q1 cycles.
12.5.1
INT INTERRUPT
12.5.2
TMR0 INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit, GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 12.8 for details on SLEEP mode.
An overflow (FFh → 00h) in the TMR0 register will set
flag bit, TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>) (Section 5.0).
12.5.3
PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<4>)
(Section 4.2).
DS39544A-page 108
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
The code in the example:
12.6 Context Saving During Interrupts
e) Stores the W register.
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt, i.e., the W and STATUS reg-
isters. This will have to be implemented in software.
f) Stores the STATUS register in bank 0.
g) Stores the PCLATH register.
h) Executes the ISR code.
Example 12-1 stores and restores the STATUS, W, and
PCLATH registers. The register, W_TEMP, must be
defined in each bank and must be defined at the same
offset from the bank base address (i.e., if W_TEMP is
defined at 0x20 in bank 0, it must also be defined at
0xA0 in bank 1).
i) Restores the STATUS register (and bank select
bit).
j) Restores the W and PCLATH registers.
EXAMPLE 12-1:
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
BCF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
STATUS, IRP
FSR, W
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Return to Bank 0
MOVF
MOVWF
:
;Copy FSR to W
;Copy FSR from W to FSR_TEMP
FSR_TEMP
:(ISR)
;Insert user code here
:
MOVF
MOVWF
SWAPF
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 109
PIC16C925/926
assigned to the WDT under software control, by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
12.7 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEPinstruction. Dur-
ing normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled by clearing configuration bit WDTE
(Section 12.1).
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, prevent it
from timing out and generating a device RESET
condition.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
12.7.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
Max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
12.7.1
WDT PERIOD
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with tempera-
DD
ture, V and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
FIGURE 12-12:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-6)
0
Postscaler
8
M
1
U
WDT Timer
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable bit
To TMR0 (Figure 5-6)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
FIGURE 12-13:
Address
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PWRTE(1) WDTE
PSA PS2
Bit 2
Bit 1
Bit 0
2007h
Config. bits
OPTION
(1)
BOREN(1)
INTEDG
CP1
CP0
FOSC1 FOSC0
81h, 181h
RBPU
T0CS
T0SE
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
DS39544A-page 110
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
12.8 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD, or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D, disable external clocks. Pull all I/O pins that
are hi-impedance inputs, high or low externally, to avoid
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
12.8.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
The MCLR pin must be at a logic high level (VIHMC).
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
12.8.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake-up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
1. External RESET input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from RB0/INT pin, RB port change, or
peripheral interrupt.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up is cleared when SLEEPis invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
The following peripheral interrupts can wake the device
from SLEEP:
1. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
2. SSP (START/STOP) bit detect interrupt.
3. SSP transmit or receive in Slave mode
(SPI/I2C).
4. CCP Capture mode interrupt.
5. A/D conversion (when A/D clock source is RC).
6. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
7. LCD module.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 111
PIC16C925/926
FIGURE 12-14:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(2)
TOST
CLKOUT(4)
INT pin
INTF Flag
Interrupt Latency
(INTCON<1>)
(Note 2)
GIE bit
Processor in
SLEEP
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Fetched
Instruction
Executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake-up, the processor jumps to the interrupt routine.
If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
After RESET, to place the device into Program/Verify
mode, the program counter (PC) is at location 00h. A
6-bit command is then supplied to the device. Depend-
ing on the command, 14-bits of program data are then
supplied to or from the device, depending if the com-
mand was a load or a read. For complete details of
serial programming, please refer to the PIC16C6X/7X
Programming Specifications (Literature #DS30228).
12.9 Program Verification/Code
Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
Note: Microchip does not recommend code pro-
tecting windowed devices.
FIGURE 12-15:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
12.10 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the four Least Significant bits of the
ID location are used.
To Normal
Connections
External
Connector
Signals
PIC16CXXX
+5V
0V
VDD
12.11 In-Circuit Serial Programming
VSS
VPP
MCLR/VPP
PIC16CXXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
RB6
RB7
CLK
Data I/O
VDD
To Normal
Connections
The device is placed into a Program/Verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
DS39544A-page 112
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
TABLE 13-1: OPCODE FIELD
13.0 INSTRUCTION SET SUMMARY
DESCRIPTIONS
Each PIC16CXXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXXX instruc-
tion set summary in Table 13-2 lists byte-oriented, bit-
oriented, and literal and control operations.
Table 13-1 shows the opcode field descriptions.
Field
Description
f
W
b
k
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
The instruction set is highly orthogonal and is grouped
into three basic categories:
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for com-
patibility with all Microchip software tools.
x
d
• Byte-oriented operations
• Bit-oriented operations
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
• Literal and control operations
For byte-oriented instructions, 'f' represents a file reg-
ister designator and 'd' represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
label Label name
TOS
PC
Top-of-Stack
Program Counter
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
PCLATH Program Counter High Latch
GIE
WDT
TO
Global Interrupt Enable bit
Watchdog Timer/Counter
Time-out bit
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the address of the
file in which the bit is located.
PD
Power-down bit
Destination either the W register or the
specified register file location
dest
Options
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
[ ]
( )
Contents
Assigned to
→
FIGURE 13-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Register bit field
In the set of
< >
∈
Byte-oriented file register operations
13
User defined term (font is courier)
8
7
6
0
0
italics
OPCODE
d
f (FILE #)
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true, or the pro-
gram counter is changed, as a result of an instruction.
In this case, the execution takes two instruction cycles,
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true, or the
program counter is changed, as a result of an instruc-
tion, the instruction execution time is 2 µs.
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Table 13-2 lists the instructions recognized by the
MPASMTM assembler.
Literal and control operations
General
Figure 13-1 shows the general formats that the instruc-
tions can have.
13
8
7
0
0
OPCODE
k (literal)
Note: To maintain upward compatibility with
future PIC16CXXX products, do not use
the OPTIONand TRISinstructions.
k = 8-bit immediate value
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
All examples use the format ‘0xnn’ to represent a
hexadecimal number.
k (literal)
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 113
PIC16C925/926
TABLE 13-2: PIC16CXXX INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C,DC,Z
1,2
1,2
2
00 0101 dfff ffff
00 0001 lfff ffff
00 0001 0xxx xxxx
00 1001 dfff ffff
00 0011 dfff ffff
00 1011 dfff ffff
00 1010 dfff ffff
00 1111 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 lfff ffff
00 0000 0xx0 0000
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
1,2
1,2
1,2,3
1,2
1,2,3
1,2
DECFSZ f, d
INCF
f, d
f, d
f, d
f, d
f
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
1,2
Move W to f
No Operation
-
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
00 0010 dfff ffff C,DC,Z
00 1110 dfff ffff
00 0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
1,2
1,2
3
01 00bb bfff ffff
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
C,DC,Z
Z
11 111x kkkk kkkk
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
00 0000 0110 0100
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
00 0000 0110 0011
11 110x kkkk kkkk
11 1010 kkkk kkkk
TO,PD
Z
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS39544A-page 114
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
13.1 Instruction Descriptions
ADDWF
Add W and f
ADDLW
Add Literal and W
Syntax:
[ label ] ADDWF f [,d]
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
(W) + k → (W)
C, DC, Z
Operation:
(W) + (f) → (destination)
Status Affected:
Encoding:
C, DC, Z
11
111x
kkkk
kkkk
00
0111
dfff
ffff
Description:
The contents of the W register are
added to the eight-bit literal ’k’ and
the result is placed in the W
register.
Description:
Add the contents of the W register
with register ’f’. If ’d’ is 0, the result is
stored in the W register. If ’d’ is 1, the
result is stored back in register ’f’.
Words:
1
1
Words:
1
1
Cycles:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode Read Process Write to
Decode
Read Process Write to
literal ’k’
data
W
register ’f’ data destination
ADDLW
0x15
Example:
Example
ADDWF FSR,
0
Before Instruction:
0x10
Before Instruction:
W
=
W
FSR
=
=
0x17
0xC2
After Instruction:
0x25
W
=
After Instruction:
W
FSR
=
=
0xD9
0xC2
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 115
PIC16C925/926
ANDLW
AND Literal with W
ANDWF
AND W with f
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] ANDWF f [,d]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
(W) .AND. (k) → (W)
Z
Operation:
(W).AND. (f) → (destination)
11
1001
kkkk
kkkk
Status Affected:
Encoding:
Z
Description:
The contents of W register are
AND’ed with the eight-bit literal 'k'.
The result is placed in the W
register.
00
0101
dfff
ffff
Description:
AND the W register with register ’f’.
If ’d’ is 0, the result is stored in the
W register. If ’d’ is 1, the result is
stored back in register ’f’.
Words:
1
1
Cycles:
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read Process Write to
literal ‘k’
Decode
Q1
Q2
Q3
Q4
data
W
Q Cycle Activity:
Read
Decode register
'f'
Process Write to
data destination
ANDLW
0x5F
Example
Before Instruction:
W
=
0xA3
ANDWF
FSR,
Example
1
After Instruction:
W
=
0x03
Before Instruction:
W
=
0x17
FSR
After Instruction
W
=
0xC2
=
=
0x17
0x02
FSR
DS39544A-page 116
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
[ label ] BCF f [,b]
Syntax:
[ label ] BTFSC f [,b]
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
Encoding:
None
01
00bb
bfff
ffff
01
10bb
bfff
ffff
Encoding:
Description:
Words:
Bit ’b’ in register ’f’ is cleared.
Description:
If bit ’b’ in register ’f’ is ’1’, then the
next instruction is executed.
If bit ’b’ in register ’f’ is ’0’, then the
next instruction is discarded, and a
NOPis executed instead, making this a
2TCY instruction.
1
1
Cycles:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Read
Decode register
1
Process
data register ’f’
Write
Words:
’f’
1(2)
Cycles:
Q1
Q2
Q3
Q4
Q Cycle Activity:
BCF
FLAG_REG, 7
Example
Read
register ’f’
Process
data
No
Operation
Decode
Before Instruction:
FLAG_REG =
After Instruction:
FLAG_REG =
0xC7
0x47
If Skip:
(2nd Cycle)
Q1
Q2
No
Q3
No
Q4
No
No
Operation Operation Operation Operation
HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Example
BSF
Bit Set f
Syntax:
[ label ] BSF f [,b]
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Before Instruction:
PC address HERE
=
Operation:
1 → (f<b>)
After Instruction:
if FLAG<1>
PC
Status Affected:
None
=
=
=
=
0,
address TRUE
1,
address FALSE
01
01bb
bfff
ffff
Encoding:
Description:
Words:
if FLAG<1>
PC
Bit ’b’ in register ’f’ is set.
1
1
Cycles:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Decode Read Process
Write
register
data register ’f’
’f’
BSF
FLAG_REG,
7
Example
Before Instruction:
FLAG_REG
After Instruction:
FLAG_REG
=
=
0x0A
0x8A
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 117
PIC16C925/926
BTFSS
Bit Test f, Skip if Set
CALL
Call Subroutine
Syntax:
[ label ] BTFSS f [,b]
Syntax:
[ label ] CALL k
0 ≤ k ≤ 2047
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Operation:
skip if (f<b>) = 1
None
Status Affected:
Status Affected:
None
01
11bb
bfff
ffff
Encoding:
10
0kkk
kkkk
kkkk
Encoding:
Description:
If bit ’b’ in register ’f’ is ’0’, then the
next instruction is executed.
If bit ’b’ is ’1’, then the next instruc-
tion is discarded and a NOPis exe-
cuted instead, making this a 2TCY
instruction.
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto the
stack. The eleven-bit immediate
address is loaded into PC bits
<10:0>. The upper bits of the PC are
loaded from PCLATH. CALLis a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Words:
1
2
Q1
Q2
Q3
Q4
Q Cycle Activity:
Cycles:
Decode
Read
register ’f’
Process
data
No
Operation
Q1
Q2
Q3
Q4
Q Cycle Activity:
Read
If Skip:
(2nd Cycle)
Q1
literal ’k’, Process Write to
Push PC
to Stack
Decode
1st Cycle
2nd Cycle
Q2
No
Q3
No
Q4
No
data
PC
No
No
No
No
No
Operation Operation Operation Operation
Operation Operation Operation Operation
HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Example
HERE
CALL
THERE
Example
Before Instruction:
PC = Address HERE
After Instruction:
Before Instruction:
PC
= Address THERE
= Address HERE+1
PC
=
address HERE
TOS
After Instruction:
if FLAG<1>
PC
=
=
=
=
0,
address FALSE
1,
address TRUE
if FLAG<1>
PC
DS39544A-page 118
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2001 Microchip Technology Inc.
PIC16C925/926
CLRF
Clear f
CLRW
Clear W
Syntax:
[ label ] CLRF
0 ≤ f ≤ 127
f
Syntax:
[ label ] CLRW
Operands:
Operation:
Operands:
Operation:
None
00h → (f)
1 → Z
00h → (W)
1 → Z
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
0001
1fff
ffff
00
0001
0xxx
xxxx
Description:
The contents of register ’f’ are
cleared and the Z bit is set.
Description:
W register is cleared. Zero bit (Z) is
set.
Words:
1
1
Words:
1
1
Cycles:
Cycles:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Q2
No
Q3
Q4
Q Cycle Activity:
Read
Decode register
Write
register
’f’
Process
data
Process Write to
Decode
Operation data
W
’f’
CLRW
Example
CLRF
FLAG_REG
Example
Before Instruction:
0x5A
Before Instruction:
FLAG_REG = 0x5A
W
=
After Instruction:
After Instruction:
FLAG_REG = 0x00
W
Z
=
=
0x00
1
Z
=
1
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 119
PIC16C925/926
CLRWDT
Clear Watchdog Timer
COMF
Complement f
Syntax:
[ label ] CLRWDT
Syntax:
[ label ] COMF f [,d]
Operands:
Operation:
None
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
00h → WDT
0 → WDT prescaler,
1 → TO
Operation:
(f) → (destination)
Status Affected:
Z
1 → PD
00
1001
dfff
ffff
Encoding:
Status Affected:
Encoding:
TO, PD
The contents of register ’f’ are com-
plemented. If ’d’ is 0, the result is
stored in W. If ’d’ is 1, the result is
stored back in register ’f’.
Description:
00
0000
0110
0100
CLRWDTinstruction resets the
Description:
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits TO
and PD are set.
1
1
Words:
Cycles:
1
1
Words:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Cycles:
Read Process Write to
Decode
Q1
Q2
No
Q3
Q4
Q Cycle Activity:
register ’f’ data destination
Clear
WDT
Counter
Process
Decode
Operation data
COMF
REG1,0
Example
Before Instruction:
REG1
=
0x13
CLRWDT
Example
After Instruction:
Before Instruction:
REG1
W
=
=
0x13
0xEC
WDT counter
=
?
After Instruction:
WDT counter
WDT prescaler
TO
=
=
=
=
0x00
0
1
1
PD
DS39544A-page 120
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
DECF
Decrement f
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECF f [,d]
Syntax:
[ label ] DECFSZ f [,d]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination)
Operation:
(f) - 1 → (destination);
skip if result = 0
Status Affected:
Z
Status Affected:
None
00
0011
dfff
ffff
Encoding:
00
1011
dfff
ffff
Encoding:
Decrement register ’f’. If ’d’ is 0, the
result is stored in the W register. If ’d’
is 1, the result is stored back in
register ’f’.
Description:
Description:
The contents of register ’f’ are decre-
mented. If ’d’ is 0, the result is placed
in the W register. If ’d’ is 1, the result
is placed back in register ’f’.
If the result is 1, the next instruction is
executed. If the result is 0, then a NOP
is executed instead, making it a 2TCY
instruction.
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Q Cycle Activity:
Read
Process Write to
data
Words:
Cycles:
1
Decode register
destination
’f’
1(2)
Q1
Q2
Q3
Q4
Q Cycle Activity:
DECF
CNT,
Example
1
Read
register ’f’
Process Write to
Decode
data
destination
Before Instruction:
CNT
Z
=
=
0x01
0
If Skip: (2nd Cycle)
Q1
Q2
No
Q3
No
Q4
No
After Instruction:
No
CNT
Z
=
=
0x00
1
Operation Operation Operation Operation
HERE
DECFSZ
GOTO
CNT, 1
LOOP
Example
CONTINUE •
•
•
Before Instruction:
PC = address HERE
After Instruction:
CNT
if CNT
=
=
CNT - 1
0,
PC
if CNT
PC
=
≠
=
address CONTINUE
0,
address HERE+1
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 121
PIC16C925/926
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
[ label ] GOTO k
0 ≤ k ≤ 2047
Syntax:
[ label ] INCF f [,d]
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(f) + 1 → (destination)
Status Affected:
Encoding:
None
Status Affected:
Z
10
1kkk
kkkk
kkkk
00
1010
dfff
ffff
Encoding:
GOTOis an unconditional branch. The
eleven-bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTOis a two-cycle instruction.
The contents of register ’f’ are incre-
mented. If ’d’ is 0, the result is placed
in the W register. If ’d’ is 1, the result
is placed back in register ’f’.
Description:
Description:
Words:
Cycles:
1
1
Words:
Cycles:
1
2
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
1st Cycle
Read
Decode register
Process Write to
data destination
Decode
Read
Process Write to
’f’
literal ’k’
data
PC
No
No
No
No
2nd Cycle
Operation Operation Operation Operation
INCF
CNT, 1
Example
Before Instruction:
GOTO THERE
Example
CNT
Z
=
=
0xFF
0
After Instruction:
PC = Address THERE
After Instruction:
CNT
Z
=
=
0x00
1
DS39544A-page 122
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
INCFSZ
Increment f, Skip if 0
IORLW
Inclusive OR Literal with W
Syntax:
[ label ] INCFSZ f [,d]
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
(W) .OR. k → (W)
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected:
Encoding:
Z
11
1000
kkkk
kkkk
Status Affected:
Encoding:
None
The contents of the W register is
OR’ed with the eight-bit literal 'k'.
The result is placed in the W
register.
Description:
00
1111
dfff
ffff
The contents of register ’f’ are incre-
mented. If ’d’ is 0, the result is placed
in the W register. If ’d’ is 1, the result is
placed back in register ’f’.
If the result is 1, the next instruction is
executed. If the result is 0, a NOPis
executed instead, making it a 2TCY
instruction.
Description:
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read Process Write to
literal ’k’
Decode
data
W
Words:
Cycles:
1
1(2)
IORLW
0x35
Example
Q1
Q2
Q3
Q4
Q Cycle Activity:
Before Instruction:
0x9A
Read
register ’f’
Process Write to
data destination
W
=
Decode
After Instruction:
If Skip: (2nd Cycle)
W
Z
=
=
0xBF
0
Q1
No
Q2
No
Q3
No
Q4
No
Operation Operation Operation Operation
HERE
INCFSZ CNT,
GOTO LOOP
1
Example
CONTINUE •
•
•
Before Instruction:
PC
=
address HERE
After Instruction:
CNT
if CNT
PC
if CNT
PC
=
=
=
≠
=
CNT + 1
0,
address CONTINUE
0,
address HERE +1
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 123
PIC16C925/926
IORWF
Inclusive OR W with f
MOVF
Move f
Syntax:
[ label ] IORWF f [,d]
Syntax:
[ label ] MOVF f [,d]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W).OR. (f) → (destination)
Operation:
(f) → (destination)
Status Affected:
Z
Status Affected:
Z
00
0100
dfff
ffff
00
1000
dfff
ffff
Encoding:
Encoding:
Description:
Inclusive OR the W register with reg-
ister ’f’. If ’d’ is 0, the result is placed
in the W register. If ’d’ is 1, the result
is placed back in register ’f’.
Description:
The contents of register f are moved
to a destination dependant upon the
status of d. If d = 0, the destination is
W register. If d = 1, the destination is
file register f itself. d = 1 is useful to
test a file register, since status flag Z
is affected.
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Q Cycle Activity:
Words:
Cycles:
1
1
Read
Decode register
Process Write to
data destination
Q1
Q2
Q3
Q4
’f’
Q Cycle Activity:
Read
Decode register
Process Write to
data destination
IORWF
RESULT, 0
Example
’f’
Before Instruction:
RESULT
W
=
=
0x13
0x91
MOVF
FSR,
0
Example
After Instruction:
After Instruction:
RESULT
W
Z
=
=
=
0x13
0x93
0
W
Z
=
=
value in FSR register
1 if W = 0
MOVLW
Move Literal to W
Syntax:
[ label ] MOVLW k
0 ≤ k ≤ 255
k → (W)
Operands:
Operation:
Status Affected:
Encoding:
None
11
00xx
kkkk
kkkk
The eight-bit literal ’k’ is loaded into
W register. The don’t cares will
assemble as 0’s.
Description:
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Q Cycle Activity:
Read Process Write to
Decode
literal ’k’
data
W
MOVLW
0x5A
Example
After Instruction:
0x5A
W
=
DS39544A-page 124
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
MOVWF
Move W to f
NOP
No Operation
Syntax:
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
f
Syntax:
[ label ] NOP
None
Operands:
Operation:
Status Affected:
Operands:
Operation:
No operation
None
Status Affected:
Encoding:
None
00
0000
1fff
ffff
00
0000
0xx0
0000
Encoding:
Move data from W register to
register ’f’.
Description:
Description:
Words:
No operation.
1
1
Words:
Cycles:
1
1
Cycles:
Q1
Q2
Q3
No
Q4
No
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
No
Decode
Read
Decode register
Operation Operation Operation
Process
data register ’f’
Write
’f’
NOP
Example
Example
MOVWF
OPTION_REG
Before Instruction:
OPTION
Load Option Register
OPTION
W
=
=
0xFF
0x4F
Syntax:
[ label ] OPTION
None
Operands:
Operation:
Status Affected:
Encoding:
After Instruction:
OPTION
W
(W) → OPTION
None
=
=
0x4F
0x4F
00
0000
0110
0010
Description:
The contents of the W register are
loaded in the OPTION register.
This instruction is supported for
code compatibility with PIC16C5X
products. Since OPTION is a
readable/writable register, the user
can directly address it.
Words:
Cycles:
Example
1
1
To maintain upward compatibility
with future PIC16CXXX products,
do not use this instruction.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 125
PIC16C925/926
RETFIE
Return from Interrupt
RETLW
Return with Literal in W
Syntax:
[ label ] RETFIE
Syntax:
[ label ] RETLW k
0 ≤ k ≤ 255
Operands:
Operation:
None
Operands:
Operation:
TOS → PC,
1 → GIE
k → (W);
TOS → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
00
0000
0000
1001
11
01xx
kkkk
kkkk
Description:
Return from Interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by set-
ting Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two-cycle
instruction.
Description:
The W register is loaded with the eight-
bit literal ’k’. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
Words:
Cycles:
1
2
Words:
Cycles:
1
2
Q1
Q2
Q3
No
Q4
Q Cycle Activity:
1st Cycle
Q1
Q2
No
Q3
Q4
Q Cycle Activity:
1st Cycle
Write to W,
Pop from
the Stack
Read
literal ’k’ Operation
Decode
No
Decode
Set the Pop from
Operation GIE bit the Stack
No No
No
No
No No No
2nd Cycle
Example
2nd Cycle
Operation Operation Operation Operation
Operation Operation Operation Operation
CALL TABLE ;W contains table
RETFIE
Example
;offset value
After Interrupt:
;W now has table value
PC = TOS
GIE =
•
•
1
TABLE ADDWF PC
;W = offset
;Begin table
;
RETLW k1
RETLW k2
•
•
•
RETLW kn
; End of table
Before Instruction:
0x07
W
=
After Instruction:
value of k8
W
=
DS39544A-page 126
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
RETURN
Return from Subroutine
RLF
Rotate Left f through Carry
Syntax:
[ label ] RETURN
None
Syntax:
[ label ] RLF f [,d]
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
TOS → PC
Operation:
See description below
Status Affected:
Encoding:
None
Status Affected:
Encoding:
C
00
0000
0000
1000
00
1101
dfff
ffff
Description:
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two-cycle instruction.
Description:
The contents of register ’f’ are rotated
one bit to the left through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
stored back in register ’f’.
Words:
Cycles:
1
2
C
Register f
Q1
Q2
No
Q3
No
Q4
Q Cycle Activity:
1st Cycle
Words:
Cycles:
1
1
Pop from
Decode
No
Operation Operation the Stack
No No No
Q1
Q2
Q3
Q4
2nd Cycle
Q Cycle Activity:
Operation Operation Operation Operation
Read
Decode register
Process Write to
data destination
RETURN
’f’
Example
After Interrupt:
PC = TOS
RLF
REG1,0
Example
Before Instruction:
REG1
C
=
=
1110 0110
0
After Instruction:
REG1
W
C
=
=
=
1110 0110
1100 1100
1
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 127
PIC16C925/926
RRF
Rotate Right f through Carry
SLEEP
Syntax:
[ label ] RRF f [,d]
Syntax:
[ label ] SLEEP
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
None
00h → WDT,
0 → WDT prescaler,
1 → TO,
Operation:
See description below
C
Status Affected:
Encoding:
0 → PD
00
1100
dfff
ffff
Status Affected:
Encoding:
TO, PD
Description:
The contents of register ’f’ are rotated
one bit to the right through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
placed back in register ’f’.
00
0000
0110
0011
Description:
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its
prescaler are cleared.
C
Register f
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 12.8 for more details.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Q Cycle Activity:
Read
Decode register
Q1
Q2
No
Q3
No
Q4
Q Cycle Activity:
Process Write to
data destination
Go to
’f’
Decode
Operation Operation Sleep
RRF
REG1,0
Example
SLEEP
Example:
Before Instruction:
REG1
C
=
=
1110 0110
0
After Instruction:
REG1
W
C
=
=
=
1110 0110
0111 0011
0
DS39544A-page 128
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
Syntax:
[ label ] SUBLW k
0 ≤ k ≤ 255
Syntax:
[ label ] SUBWF f [,d]
Operands:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
k - (W) → (W)
Operation:
(f) - (W) → (destination)
Status Affected: C, DC, Z
Status Affected: C, DC, Z
11
110x
kkkk
kkkk
Encoding:
00
0010
dfff
ffff
Encoding:
Description:
The W register is subtracted (2’s
complement method) from the eight-
bit literal 'k'. The result is placed in the
W register.
Description:
Subtract (2’s complement method) W
register from register 'f'. If 'd' is 0, the
result is stored in the W register. If 'd' is
1, the result is stored back in register 'f'.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Read
literal ’k’
Process
data
Decode
Write to W
Read
register ’f’
Process Write to
data destination
Decode
SUBLW
0x02
Example 1:
Example 1:
SUBWF REG1,1
Before Instruction:
W
C
Z
=
=
=
1
?
?
Before Instruction:
REG1
=
=
=
=
3
2
?
?
W
C
Z
After Instruction:
W
C
Z
=
=
=
1
1; result is positive
0
After Instruction:
REG1
=
=
=
=
1
2
W
C
Z
Example 2:
1; result is positive
0
Before Instruction:
W
C
Z
=
=
=
2
?
?
Example 2:
Before Instruction:
REG1
=
=
=
=
2
2
?
?
After Instruction:
W
C
Z
W
C
Z
=
=
=
0
1; result is zero
1
After Instruction:
Example 3:
REG1
=
=
=
=
0
2
Before Instruction:
W
C
Z
W
C
Z
=
=
=
3
?
?
1; result is zero
1
Example 3:
After Instruction:
Before Instruction:
W
C
Z
=
=
=
0xFF
0; result is negative
0
REG1
=
=
=
=
1
2
?
?
W
C
Z
After Instruction:
REG1
=
=
=
=
0xFF
2
0; result is negative
0
W
C
Z
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 129
PIC16C925/926
SWAPF
Syntax:
Swap Nibbles in f
TRIS
Load TRIS Register
Syntax:
[ label ] TRIS
5 ≤ f ≤ 7
f
[ label ] SWAPF f [,d]
Operands:
Operation:
Status Affected:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
(W) → TRIS register f;
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
None
00
0000
0110
0fff
Encoding:
Status Affected:
None
Description:
The instruction is supported for
code compatibility with the
PIC16C5X products. Since TRIS
registers are readable and writ-
able, the user can directly address
them.
00
1110
dfff
ffff
Encoding:
Description:
The upper and lower nibbles of reg-
ister ’f’ are exchanged. If ’d’ is 0, the
result is placed in W register. If ’d’ is
1, the result is placed in register ’f’.
Words:
Cycles:
Example
1
1
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
To maintain upward compatibil-
ity with future PIC16CXXX
products, do not use this
instruction.
Read Process Write to
register ’f’ data destination
Decode
SWAPF
REG,
0
Example
Before Instruction:
REG1
=
0xA5
After Instruction:
REG1
W
=
=
0xA5
0x5A
DS39544A-page 130
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
XORLW
Exclusive OR Literal with W
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] XORWF f [,d]
Operands:
Operation:
Status Affected:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
(W) .XOR. k → (W)
Operation:
(W) .XOR. (f) → (destination)
Z
Status Affected:
Encoding:
Z
11
1010
kkkk
kkkk
Encoding:
00
0110
dfff
ffff
Description:
The contents of the W register are
XOR’ed with the eight-bit literal
'k'. The result is placed in the W
register.
Description:
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0, the
result is stored in the W register. If
'd' is 1, the result is stored back in
register 'f'.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Q Cycle Activity:
Decode Read Process Write to
literal ’k’ data
Q1
Q2
Q3
Q4
Q Cycle Activity:
W
Read Process Write to
register ’f’ data destination
Decode
XORLW 0xAF
Example:
Before Instruction:
0xB5
XORWF
REG
1
Example
W
=
Before Instruction:
After Instruction:
0x1A
REG
W
=
=
0xAF
0xB5
W
=
After Instruction:
REG
W
=
=
0x1A
0xB5
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 131
PIC16C925/926
NOTES:
DS39544A-page 132
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
The MPLAB IDE allows you to:
14.0 DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
• Simulators
- MPLAB SIM Software Simulator
• Emulators
14.2 MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PICmicro MCU’s.
- MPLAB ICD for PIC16F87X
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
14.1 MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
14.3 MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 133
PIC16C925/926
14.4 MPLINK Object Linker/
MPLIB Object Librarian
14.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editing, building, downloading and source
debugging from a single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
14.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
14.5 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS39544A-page 134
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
14.8 MPLAB ICD In-Circuit Debugger
14.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PIC16F87X and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. The MPLAB ICD utilizes
the in-circuit debugging capability built into the
PIC16F87X. This feature, along with Microchip’s
In-Circuit Serial ProgrammingTM protocol, offers cost-
effective in-circuit FLASH debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by watching variables, single-
stepping and setting break points. Running at full
speed enables testing hardware in real-time.
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
14.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program
PICmicro devices. It can also set code protection in this
mode.
14.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
14.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 135
PIC16C925/926
14.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
14.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
14.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS39544A-page 136
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
TABLE 14-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X
X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X
X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m e r u b g e g D s m e a r m o g P r r
s t K l a i E d v n a s d r a B o o m D e
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 137
PIC16C925/926
NOTES:
DS39544A-page 138
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
15.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................. 0V to +7.5V
Voltage on MCLR with respect to VSS........................................................................................................ 0V to +13.25V
Voltage on RA4 with respect to VSS............................................................................................................... 0V to +8.5V
Voltage on VLCD2, VLCD3 with respect to VSS.............................................................................................. 0V to +10V
Total power dissipation (Note 1) ..............................................................................................................................1.0 W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin .........................................................................................................25 mA
Maximum output current sourced by any I/O pin ...................................................................................................25 mA
Maximum current sunk by all Ports combined .....................................................................................................200 mA
Maximum current sourced by all Ports combined ................................................................................................200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 139
PIC16C925/926
FIGURE 15-1:
PIC16C925/926 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
PIC16C925/926
3.5 V
3.0 V
2.5 V
2.0 V
20 MHz
Frequency
FIGURE 15-2:
PIC16LC925/926 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
PIC16LC925/926
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
10 MHz
4 MHz
Frequency
FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
Note 2: FMAX has a maximum frequency of 10MHz.
DS39544A-page 140
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
15.1 DC Characteristics
Standard Operating Conditions (unless otherwise stated)
PIC16LC925/926
(Commercial, Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
Standard Operating Conditions (unless otherwise stated)
PIC16C925/926
(Commercial, Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
Param
No.
Sym
Characteristic
Min Typ† Max Units
Conditions
VDD
Supply Voltage
PIC16LC925/926 2.5
D001
D001A
—
—
5.5
5.5
V
V
LP, XT and RC osc configuration
HS osc configuration
4.5
D001
D001A
PIC16C925/926 4.0
4.5
—
—
5.5
5.5
V
V
XT, RC and LP osc configuration
HS osc configuration
D002
D003
VDR
RAM Data Retention
Voltage (Note 1)
—
1.5
—
V
Device in SLEEP mode
VPOR
VDD Start Voltage
to ensure internal
—
VSS
—
V
See Power-on Reset section for details
Power-on Reset signal
D004
D005
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
3.65
—
—
—
V/ms See Power-on Reset section for details
(Note 6)
VBOR
IDD
Brown-out Reset
voltage trip point
4.35
V
BODEN bit set
Supply Current (Note 2)
D010
D011
PIC16LC925/926
—
—
.6
2.0 mA XT and RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
225 48
µA LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D010
D011
D012
PIC16C925/926
—
—
—
2.7
35
7
5
mA XT and RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
µA LP osc configuration
FOSC = 32 kHz, VDD = 4.0V
mA HS osc configuration
70
10
FOSC = 20 MHz, VDD = 5.5V
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin load-
ing and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on
the current consumption.The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail;
all I/O pins tri-stated, pulled to VDD
MCLR = VDD.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
6: PWRT must be enabled for slow ramps.
7: ∆ΙLCDT1 and ∆ΙLCDRC includes the current consumed by the LCD Module and the voltage generation
circuitry. This does not include current dissipated by the LCD panel.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 141
PIC16C925/926
15.1 DC Characteristics (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LC925/926
(Commercial, Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
Standard Operating Conditions (unless otherwise stated)
PIC16C925/926
(Commercial, Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
Param
No.
Sym
Characteristic
Min Typ† Max Units
Conditions
IPD
Power-down Current (Note 3)
D020
D020
PIC16LC925/926
PIC16C925/926
—
—
0.9
1.5
5
µA VDD = 3.0V
21
µA VDD = 4.0V
Module Differential Current (Note 5)
D021
D021
D022
∆IWDT
Watchdog Timer
PIC16LC925/926
—
—
—
6.0
9.0
36
20
25
50
µA VDD = 3.0V
Watchdog Timer
PIC16C925/926
µA VDD = 4.0V
∆ILCDT1
LCD Voltage
Generation with
µA VDD = 3.0V (Note 7)
internal RC osc enabled
PIC16LC925/926
D022
LCD Voltage
Generation with
—
40
55
µA VDD = 4.0V (Note 7)
internal RC osc enabled
PIC16C925/926
D022A ∆IBOR
Brown-out Reset
—
—
100 150 µA BODEN bit set, VDD = 5.0
D024
∆ILCDT1
LCD Voltage
Generation with
15
29
µA VDD = 3.0V (Note 7)
Timer1 @ 32.768 kHz
PIC16LC925/926
D024
LCD Voltage
Generation with
—
33
60
µA VDD = 4.0V (Note 7)
Timer1 @ 32.768 kHz
PIC16C925/926
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin load-
ing and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on
the current consumption.The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail;
all I/O pins tri-stated, pulled to VDD
MCLR = VDD.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
6: PWRT must be enabled for slow ramps.
7: ∆ΙLCDT1 and ∆ΙLCDRC includes the current consumed by the LCD Module and the voltage generation
circuitry. This does not include current dissipated by the LCD panel.
DS39544A-page 142
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
15.1 DC Characteristics (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LC925/926
(Commercial, Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
Standard Operating Conditions (unless otherwise stated)
PIC16C925/926
(Commercial, Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
Param
No.
Sym
Characteristic
Min Typ† Max Units
Conditions
D025
∆IT1OSC
Timer1 Oscillator
PIC16LC925/926
—
—
—
—
—
—
50
50
—
—
µA VDD = 3.0V
D025
D026
D026
Timer1 Oscillator
PIC16C925/926
µA VDD = 4.0V
∆IAD
A/D Converter
PIC16LC925/926
1.0
1.0
µA A/D on, not converting
µA A/D on, not converting
A/D Converter
PIC16C925/926
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin load-
ing and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on
the current consumption.The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail;
all I/O pins tri-stated, pulled to VDD
MCLR = VDD.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
6: PWRT must be enabled for slow ramps.
7: ∆ΙLCDT1 and ∆ΙLCDRC includes the current consumed by the LCD Module and the voltage generation
circuitry. This does not include current dissipated by the LCD panel.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 143
PIC16C925/926
15.2 DC Characteristics: PIC16C925/926 (Commercial, Industrial)
PIC16LC925/926 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec
Param
Sym
No.
Characteristic
Min Typ† Max Units Conditions
Input Low Voltage
VIL I/O ports
with TTL buffer
D030
VSS
Vss
VSS
VSS
VSS
—
—
—
—
—
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
D031
D032
D033
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP)
(Note 1)
Input High Voltage
VIH I/O ports
—
—
—
D040
D040A
with TTL buffer
2.0
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
0.25VDD
+ 0.8V
0.8VDD
0.8VDD
0.7VDD
0.9VDD
D041
D042
D042A
D043
with Schmitt Trigger buffer
MCLR
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
—
—
—
—
VDD
VDD
VDD
VDD
V
V
V
V
(Note 1)
D070
IPURB PORTB Weak Pull-up Current
50
250
400
µA VDD = 5V, VPIN = VSS
Input Leakage Current
(Notes 2, 3)
D060
D061
D063
IIL I/O ports
—
—
—
—
—
—
1.0
5
5
µA Vss ≤ VPIN ≤ VDD, Pin at hi-Z
µA Vss ≤ VPIN ≤ VDD
MCLR, RA4/T0CKI
OSC1
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
Output Low Voltage
VOL I/O ports
D080
D083
—
—
—
—
0.6
0.6
V
V
IOL = 4.0 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V
OSC2/CLKOUT (RC osc mode)
Output High Voltage
D090
D092
VOH I/O ports (Note 3)
VDD - 0.7 —
—
—
V
V
IOH = -3.0 mA, VDD = 4.5V
IOH = -1.3 mA, VDD = 4.5V
OSC2/CLKOUT (RC osc mode) VDD - 0.7 —
Capacitive Loading Specs on
Output Pins
D100 COSC2 OSC2 pin
—
—
15
pF In XT, HS and LP modes when
external clock is used to drive
OSC1.
D101
D102
CIO All I/O pins and OSC2 (in RC)
—
—
—
—
50
400
pF
pF
CB SCL, SDA in I2C mode
D150
VDD Open Drain High Voltage
—
—
8.5
V
RA4 pin
†
Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C925/926 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
DS39544A-page 144
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
FIGURE 15-3:
LCD VOLTAGE WAVEFORM
D223
D224
VLCD3
VLCD2
VLCD1
VSS
TABLE 15-1: LCD MODULE ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
No.
D200
VLCD3
LCD Voltage on pin
VLCD3
VDD - 0.3
—
Vss + 7.0
V
D201
D202
D220
D221
D222
D223
VLCD2
VLCD1
VOH
LCD Voltage on pin
VLCD2
Vss - 0.3
Vss - 0.3
Max VLCDN - 0.1
Min VLCDN
5
—
—
—
—
14
—
VLCD3
VLCD3
V
V
V
V
LCD Voltage on pin
VLCD1
Output High
Voltage
Max VLCDN
Min VLCDN + 0.1
22
COM outputs IOH = 25 µA
SEG outputs IOH = 3 µA
VOL
Output Low Voltage
COM outputs IOL = 25 µA
SEG outputs IOL = 3 µA
FLCDRC
TrLCD
LCDRC Oscillator
Frequency
kHz VDD = 5V, -40°C to +85°C
Output Rise Time
—
200
µs
µs
COM outputs Cload = 5,000 pF
SEG outputs Cload = 500 pF
VDD = 5.0V, T = 25°C
(1)
D224
TfLCD
Output Fall Time
TrLCD - 0.05
TrLCD
—
TrLCD + 0.05
TrLCD
COM outputs Cload = 5,000 pF
SEG outputs Cload = 500 pF
VDD = 5.0V, T = 25°C
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: 0 ohm source impedance at VLCD.
TABLE 15-2: VLCD CHARGE PUMP ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Characteristic
Min Typ
Max
Units Conditions
No.
D250
IVADJ
VLCDADJ Regulated Current Output
—
—
10
—
—
—
0.1
µA
µA/V
V
D252
D265
∆ IVADJ/∆ VDD VLCDADJ Current VDD Rejection
VVADJ
VLCDADJ Voltage
Limits
PIC16C925/926
1.0
2.3
PIC16LC925/926 1.0
VDD - 0.7V
V
VDD < 3V
Note 1: For design guidance only.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 145
PIC16C925/926
15.3 Timing Parameter Symbology
The timing parameter symbols have been created fol-
lowing one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST (I2C specifications only)
4. Ts (I2C specifications only)
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
Fall
P
R
V
Z
Period
H
High
Rise
I
L
Invalid (Hi-impedance)
Low
Valid
Hi-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
Hold
SU
Setup
ST
DAT
STA
DATA input hold
START condition
STO
STOP condition
FIGURE 15-4:
LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL
CL
=
=
464 Ω
50 pF for all pins except OSC2 unless otherwise noted.
15 pF for OSC2 output
DS39544A-page 146
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
15.4 Timing Diagrams and Specifications
FIGURE 15-5:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
3
4
2
CLKOUT
TABLE 15-3: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
Sym
Characteristic
Min Typ†
Max
Units
Conditions
No.
FOSC External CLKIN Frequency
DC
DC
DC
DC
0.1
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
20
MHz XT and RC osc mode
MHz HS osc mode
kHz LP osc mode
MHz RC osc mode
MHz XT osc mode
MHz HS osc mode
kHz LP osc mode
ns XT and RC osc mode
ns HS osc mode
µs LP osc mode
ns RC osc mode
ns XT osc mode
ns HS osc mode
µs LP osc mode
ns TCY = 4/FOSC
ns XT oscillator
(Note 1)
200
4
Oscillator Frequency
(Note 1)
4
20
5
200
—
1
TOSC
External CLKIN Period
250
125
5
(Note 1)
—
—
Oscillator Period
(Note 1)
250
250
125
5
—
10,000
250
—
2
3
TCY
Instruction Cycle Time (Note 1)
500
DC
—
TosL, External Clock in (OSC1) High or 50
TosH Low Time
2.5
—
µs LP oscillator
ns HS oscillator
10
—
4
TosR, External Clock in (OSC1) Rise or
TosF Fall Time
—
—
—
25
ns XT oscillator
50
ns LP oscillator
15
ns HS oscillator
†
Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 147
PIC16C925/926
FIGURE 15-6:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
12
18
19
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Refer to Figure 15-4 for load conditions.
Note:
TABLE 15-4: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
Symbol
Characteristic
Min
Typ†
Max
Units Conditions
No.
10
11
12
13
14
15
16
17
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
—
—
—
—
75
75
35
35
—
—
—
50
200
200
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
TckR
CLKOUT rise time
100
TckF
CLKOUT fall time
100
TckL2ioV
CLKOUT ↓ to Port out valid
0.5TCY + 20
—
TioV2ckH Port in valid before CLKOUT ↑
TckH2ioI Port in hold after CLKOUT ↑
Tosc + 200
0
—
TosH2ioV OSC1↑ (Q1 cycle) to
—
150
Port out valid
18
TosH2ioI
OSC1↑ (Q2 cycle) to
Port input invalid
(I/O in hold time)
PIC16C925/926
PIC16LC925/926
100
200
—
—
—
—
ns
ns
19
20
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
0
—
—
10
—
10
—
—
—
—
40
80
40
80
—
—
ns
ns
ns
ns
ns
ns
ns
TioR
Port output rise time
Port output fall time
INT pin high or low time
PIC16C925/926
PIC16LC925/926
PIC16C925/926
PIC16LC925/926
—
21
TioF
—
—
22††
23††
Tinp
Trbp
TCY
TCY
RB7:RB4 change INT high or low time
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
DS39544A-page 148
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
FIGURE 15-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note:
Refer to Figure 15-4 for load conditions.
TABLE 15-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
Symbol
Characteristic
Min
Typ†
Max Units
Conditions
No.
30
31
TmcL
TWDT
MCLR Pulse Width (low)
2
7
—
—
µs
ms VDD = 5V, -40°C to +85°C
Watchdog Timer Time-out Period
(No Prescaler)
18
33
32
33
34
TOST
TPWRT
TIOZ
Oscillation Start-up Timer Period
Power-up Timer Period
—
28
—
1024TOSC
—
132
2.1
—
TOSC = OSC1 period
72
ms VDD = 5V, -40°C to +85°C
µs
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
—
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 149
PIC16C925/926
FIGURE 15-8:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
46
40
45
42
RC0/T1OSO/T1CKI
47
48
TMR0 or
TMR1
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Symbol
Tt0H
Characteristic
Min
Typ† Max Units
Conditions
40
41
42
T0CKI High Pulse Width
T0CKI Low Pulse Width
T0CKI Period
No Prescaler
0.5TCY + 20
10
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 42
ns Must also meet
With Prescaler
No Prescaler
With Prescaler
No Prescaler
With Prescaler
ns
Tt0L
Tt0P
0.5TCY + 20
10
parameter 42
ns
ns
TCY + 40
Greater of:
TCY + 40
ns N = prescale value
(2, 4,..., 256)
20 or
N
0.5TCY + 20
15
45
46
47
Tt1H
Tt1L
Tt1P
T1CKI High Synchronous, Prescaler = 1
—
—
—
—
—
—
ns Must also meet
Time
parameter 47
Synchronous, PIC16C925/926
ns
ns
Prescaler =
2,4,8
PIC16LC925/926
25
Asynchronous PIC16C925/926
PIC16LC925/926
30
50
—
—
—
—
—
—
—
—
ns
ns
ns
ns
T1CKI Low
Time
Synchronous, Prescaler = 1
Synchronous, PIC16C925/926
0.5TCY + 20
15
Prescaler =
Must also meet
parameter 47
PIC16LC925/926
25
—
—
ns
2,4,8
Asynchronous PIC16C925/926
PIC16LC925/926
30
50
—
—
—
—
ns
ns
T1CKI Input Synchronous PIC16C925/926
Period
Greater of:
TCY + 40
N = prescale value
(1, 2, 4, 8)
—
—
ns
30 or
N
Greater of:
TCY + 40
PIC16LC925/926
N = prescale value
(1, 2, 4, 8)
50 or
N
Asynchronous PIC16C925/926
PIC16LC925/926
60
—
—
—
—
ns
ns
100
Ft1
Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
DC
—
—
200 kHz
7Tosc
48
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
—
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS39544A-page 150
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
FIGURE 15-9:
CAPTURE/COMPARE/PWM TIMINGS
RC2/CCP1
(Capture Mode)
50
51
52
RC2/CCP1
(Compare or PWM Mode)
53
54
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-7: CAPTURE/COMPARE/PWM REQUIREMENTS
Parameter
Symbol
Characteristic
Min
Typ† Max Units
Conditions
No.
50
51
TccL
Input Low Time No Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
With Prescaler PIC16C925/926
PIC16LC925/926
10
20
0.5TCY + 20
10
TccH
Input High Time No Prescaler
With Prescaler PIC16C925/926
PIC16LC925/926
20
52
53
TccP
TccR
Input Period
3TCY + 40
N
ns N = prescale value
(1,4 or 16)
Output Rise Time
PIC16C925/926
PIC16LC925/926
PIC16C925/926
PIC16LC925/926
—
—
—
—
10
25
10
25
25
45
25
45
ns
ns
ns
ns
54
TccF
Output Fall Time
†
Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 151
PIC16C925/926
FIGURE 15-10:
SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
BIT6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 15-4 for load conditions.
FIGURE 15-11:
SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
BIT6 - - - - - -1
BIT6 - - - -1
SDO
SDI
75, 76
MSb IN
74
LSb IN
Note: Refer to Figure 15-4 for load conditions.
DS39544A-page 152
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
FIGURE 15-12:
SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
BIT6 - - - - - -1
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note:
Refer to Figure 15-4 for load conditions.
FIGURE 15-13:
SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Note: Refer to Figure 15-4 for load conditions.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 153
PIC16C925/926
TABLE 15-8: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units Conditions
70
71
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
TscH
SCK input high time (Slave
mode)
Continuous
Single Byte
1.25TCY + 30
40
—
—
—
—
ns
ns
71A
72
TscL
SCK input low time (Slave
mode)
Continuous
Single Byte
1.25TCY + 30
40
—
—
ns
72A
73
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
Hold time of SDI data input to SCK edge
50
50
—
—
—
—
ns
ns
74
TscH2diL,
TscL2diL
75
76
77
78
79
80
TdoR
SDO data output rise time
—
—
10
—
—
—
10
10
—
10
10
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
TdoF
SDO data output fall time
TssH2doZ
TscR
SS↑ to SDO output hi-impedance
SCK output rise time (Master mode)
SCK output fall time (Master mode)
SDO data output valid after SCK edge
TscF
TscH2doV,
TscL2doV
81
TdoV2scH,
TdoV2scL
SDO data output setup to SCK edge
TCY
—
—
ns
82
83
TssL2doV
SDO data output valid after SS↓ edge
SS ↑ after SCK edge
—
—
—
50
ns
ns
TscH2ssH,
TscL2ssH
1.5TCY + 40
—
84
Tb2b
Delay between consecutive bytes
1.5TCY + 40
—
—
ns
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS39544A-page 154
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
FIGURE 15-14:
I2C BUS START/STOP BITS TIMING
SCL
SDA
93
91
90
92
STOP
Condition
START
Condition
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-9: I2C BUS START/STOP BITS REQUIREMENTS
Parameter
Symbol
Characteristic
Min Typ Max Units
Conditions
No.
90
91
92
93
TSU:STA
START condition 100 kHz mode
Setup time
4700
4000
4700
4000
—
—
—
—
—
—
—
—
ns Only relevant for Repeated
START condition
THD:STA
TSU:STO
THD:STO
START condition 100 kHz mode
Hold time
ns After this period the first clock
pulse is generated
STOP condition
Setup time
100 kHz mode
ns
STOP condition
Hold time
100 kHz mode
ns
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 155
PIC16C925/926
FIGURE 15-15:
I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-10: I2C BUS DATA REQUIREMENTS
Parameter
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
101
THIGH
Clock high time
Clock low time
100 kHz mode
4.0
—
µs
Device must operate at a
minimum of 1.5 MHz
SSP Module
1.5TCY
4.7
—
—
TLOW
100 kHz mode
µs
Device must operate at a
minimum of 1.5 MHz
SSP Module
1.5TCY
—
102
103
90
TR
SDA and SCL rise 100 kHz mode
time
—
1000
ns
ns
µs
µs
ns
ns
µs
ns
µs
TF
SDA and SCL fall 100 kHz mode
time
—
4.7
4.0
0
300
—
TSU:STA
THD:STA
START condition 100 kHz mode
setup time
Only relevant for Repeated
START condition
91
START condition 100 kHz mode
hold time
—
After this period the first
clock pulse is generated
106
107
92
THD:DAT Data input hold
time
100 kHz mode
100 kHz mode
100 kHz mode
—
TSU:DAT
TSU:STO
TAA
Data input setup
time
250
4.7
—
—
STOP condition
setup time
—
109
110
Output valid from 100 kHz mode
clock
3500
—
(Note 1)
TBUF
Bus free time
100 kHz mode
4.7
Time the bus must be free
before a new transmission
can start
D102
CB
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
DS39544A-page 156
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
TABLE 15-11: A/D CONVERTER CHARACTERISTICS:
PIC16C925/926 (COMMERCIAL, INDUSTRIAL)
PIC16LC925/926 (COMMERCIAL, INDUSTRIAL)
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
A01
NR
Resolution
—
—
10-bits
bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A02
A03
A04
A05
A06
A07
EABS Total Absolute error
EIL Integral linearity error
—
—
—
—
—
—
—
—
—
—
—
—
—
< ± 1
< ± 1
< ± 1
< ± 1
< ± 2
< ± 1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
EDL Differential linearity error
EFS Full scale error
EOFF Offset error
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
EGN Gain error
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10
A20
—
Monotonicity
guaranteed
—
—
VSS ≤ VAIN ≤ VREF
VREF Reference voltage
AVDD -
2.5V
—
AVDD + 0.3
V
A25
A30
VAIN Analog input voltage
VSS - 0.3
—
—
VREF + 0.3
10.0
V
ZAIN Recommended impedance of
analog voltage source
—
kΩ
A40
A50
IAD
A/D conversion current PIC16C925/926
—
—
220
90
—
—
µA Average current consump-
(VDD)
tion when A/D is on.
(Note 1)
PIC16LC925/926
µA
IREF VREF input current (Note 2)
10
—
1000
µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD.
—
—
10
µA During A/D Conversion
cycle
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 157
PIC16C925/926
FIGURE 15-16:
A/D CONVERSION TIMING
BSF ADCON0, GO
134
131
Q4
130
132
A/D CLK
9
8
7
...
...
2
1
0
A/D DATA
NEW_DATA
OLD_DATA
ADRES
ADIF
GO
DONE
133
SAMPLING STOPPED
SAMPLE
133
TABLE 15-12: A/D CONVERSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
130
TAD
A/D clock period PIC16C925/926
1.6
3.0
2.0
3.0
—
—
—
—
—
µs
µs
TOSC based, VREF ≥ 3.0V
TOSC based, VREF ≥ 2.0V
PIC16LC925/926
PIC16C925/926
PIC16LC925/926
4.0
6.0
—
6.0
9.0
12
µs A/D RC Mode
µs A/D RC Mode
TAD
131
132
TCNV Conversion time (not including S/H time)
(Note 1)
TACQ Acquisition time
(Note 2)
40
—
—
µs
10
—
µs The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1 LSb (i.e.,
5 mV @ 5.12V) from the last sam-
pled voltage (as stated on CHOLD).
134
135
TGO
Q4 to A/D clock start
—
TOSC/2
—
—
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEPinstruction to be
executed.
TSWC Switching from convert → sample time
1.5
—
TAD
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 10.1 for min. conditions.
DS39544A-page 158
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
16.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and Tables are not available at this time.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 159
PIC16C925/926
NOTES:
DS39544A-page 160
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
17.0 PACKAGING INFORMATION
17.1 Package Marking Information
64-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16C925
-I/PT
0010017
68-Lead PLCC
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC16C926/L
0010017
Legend: XX...X Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code and traceability code.
For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 161
PIC16C925/926
Package Marking Information (Continued)
68-Lead CERQUAD Windowed
Example
XXXXXXXXXXXXXXX
YYWWNNN
PIC16C926/CL
0010017
DS39544A-page 162
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
17.2 Package Details
64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
°
CH x 45
α
A
c
A2
L
φ
β
A1
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
64
MAX
n
p
Number of Pins
Pitch
64
.020
16
0.50
16
Pins per Side
Overall Height
n1
A
.039
.043
.039
.006
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.15
0.60
1.00
3.5
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.037
.002
.018
.041
.010
.030
1.05
0.25
0.75
§
0.05
0.45
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.005
.007
.025
5
7
.482
.482
.398
.398
.009
.011
.045
15
0
11.75
11.75
9.90
9.90
0.13
0.17
0.64
5
7
12.25
12.25
10.10
10.10
0.23
0.27
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.007
.009
.035
10
12.00
12.00
10.00
10.00
0.18
0.22
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-085
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 163
PIC16C925/926
68-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
E
E1
#leads=n1
D1 D
n 1 2
°
°
α
CH2 x 45
CH1 x 45
A3
A2
A
32°
c
B1
B
A1
p
β
D2
E2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
68
MAX
n
p
Number of Pins
Pitch
68
.050
17
1.27
17
Pins per Side
Overall Height
n1
A
.165
.173
.153
.028
.029
.045
.005
.990
.990
.954
.954
.920
.920
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
25.02
25.02
24.13
24.13
22.61
22.61
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
25.15
25.15
24.23
24.23
23.37
23.37
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.145
.020
.024
.040
.000
.985
.985
.950
.950
.890
.890
.008
.026
.013
0
.160
.035
.034
.050
.010
.995
.995
.958
.958
.930
.930
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
25.27
25.27
24.33
24.33
23.62
23.62
0.33
0.81
0.53
10
§
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-049
DS39544A-page 164
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
68-Lead Ceramic Leaded (CL) Chip Carrier with Window – Square (CERQUAD)
E
E1
#leads=n1
W
D1
D
n 1 2
A3
R
CH1 x 45°
A2
A
45°
c
B1
B
p
A1
E2
D2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
68
MAX
n
p
Number of Pins
Pitch
68
.050
.175
.137
.040
.035
.040
.025
.988
.988
.950
.950
.910
.910
17
1.27
Overall Height
A
A2
A1
A3
CH1
R
.165
.185
4.19
3.00
4.45
3.48
1.02
0.89
1.02
0.64
25.10
25.10
24.13
24.13
23.11
23.11
17
4.70
Package Thickness
Standoff
.118
.030
.030
.030
.020
.983
.983
.942
.942
.890
.890
.155
.050
.040
.050
.030
.993
.993
.958
.958
.930
.930
3.94
1.27
§
0.76
0.76
Side One Chamfer Dim.
Corner Chamfer (1)
1.02
0.76
1.27
Corner Radius (Others)
Overall Package Width
Overall Package Length
Ceramic Package Width
0.51
0.76
E
24.97
24.97
23.93
23.93
22.61
22.61
25.22
25.22
24.33
24.33
23.62
23.62
D
E1
Ceramic Package Length
Footprint Width
D1
E2
D2
n1
c
Footprint Length
Pins each side
Lead Thickness
.008
.026
.015
.370
.010
.029
.018
.380
.012
.031
.021
.390
0.20
0.66
0.38
9.40
0.25
0.72
0.46
9.65
0.30
0.79
0.53
9.91
Upper Lead Width
Lower Lead Width
Window Diameter
B1
B
W
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-087
Drawing No. C04-097
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 165
PIC16C925/926
NOTES:
DS39544A-page 166
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
Version
Date
Description
The differences between the devices listed in this data
sheet are listed in Table B-1.
A
February 2001 This is a new data sheet.
However, these devices
are similar to those
TABLE B-1:
DEVICE DIFFERENCES
described in the
PIC16C923/924 data
Feature
PIC16C925
PIC16C926
sheet (DS30444).
EPROM Program
Memory (words)
4K
8K
Data Memory
(bytes)
176
336
Note: On 64-pin TQFP, pins RG7 and RE7 are not
available.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 167
PIC16C925/926
APPENDIX C: CONVERSION
CONSIDERATIONS
Considerations for converting to the devices listed in
this data sheet from previous device types are summa-
rized in Table C-1.
TABLE C-1:
CONVERSION
CONSIDERATIONS
PIC16C923/
924
PIC16C925/
Feature
926
Operating
Frequency
DC - 8 MHz
DC - 20 MHz
EPROM Program
Memory (words)
4K (925)
8K (926)
4K
Data Memory
(bytes)
176 (925)
336 (926)
176
A/D Converter
Resolution
8-bit
(924 only)
10-bit
A/D Converter
Channels
none (923)
5 (924)
5
8 (923)
9 (924)
Interrupt Sources
Brown-out Reset
9
No
Yes
DS39544A-page 168
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
INDEX
PORTC ...................................................................... 33
PORTD
A
A/D ..................................................................................... 75
ADCON0 Register ...................................................... 75
ADCON1 Register ...................................................... 76
ADIF bit ...................................................................... 76
Block Diagrams
Pins <4:0> ......................................................... 34
Pins <7:5> ......................................................... 34
PORTE ...................................................................... 36
PORTF ...................................................................... 37
PORTG ...................................................................... 38
PWM Mode ................................................................ 56
RC Oscillator ........................................................... 100
SSP
Analog Input Model ............................................ 78
Converter ........................................................... 77
Configuring Analog Port Pins ..................................... 80
Configuring the Interrupt ............................................ 77
Configuring the Module .............................................. 77
Conversion Clock ....................................................... 79
Conversions ............................................................... 80
Converter Characteristics ........................................ 157
Delays ........................................................................ 78
Effects of a RESET .................................................... 81
GO/DONE bit ............................................................. 76
Internal Sampling Switch (Rss) Impedence ............... 78
Operation During SLEEP ........................................... 81
Register Initialization States ............................. 104, 105
Sampling Requirements ............................................. 78
Source Impedence ..................................................... 78
Time Delays ............................................................... 78
Absolute Maximum Ratings ............................................. 139
ACK Pulse .......................................................................... 66
ACK pulse .............................................................. 70, 71, 72
Analog-to-Digital Converter. See A/D
2
I C Mode ........................................................... 69
SPI Mode ........................................................... 61
Timer0 ....................................................................... 41
Timer0/WDT Prescaler .............................................. 44
Timer1 ....................................................................... 48
Timer2 ....................................................................... 51
Watchdog Timer ...................................................... 110
BOR. See Brown-out Reset.
Brown-out Reset (BOR) ..................................... 97, 102, 103
BOR Status (BOR Bit) ............................................... 24
C
C (Carry) bit ....................................................................... 19
Capture Mode (CCP)
Associated Registers ................................................. 58
Block Diagram ........................................................... 54
Changing Between Prescalers .................................. 54
Pin Configuration ....................................................... 54
Prescaler ................................................................... 54
Software Interrupt ...................................................... 54
Capture/Compare/PWM (CCP)
CCP1CON Register ................................................... 53
CCPR1 Register ........................................................ 53
CCPR1H Register ..................................................... 53
CCPR1L Register ...................................................... 53
Register Initialization States .................................... 104
Timer Resources ....................................................... 53
CCP. See Capture/Compare/PWM (CCP).
Appendic C
Conversion Considerations ...................................... 168
Appendix A
Revision History ....................................................... 167
Appendix B
Device Differences ................................................... 167
Application Notes
AN552 ........................................................................ 31
AN556 ........................................................................ 25
AN578 ........................................................................ 59
AN594 ........................................................................ 53
AN607 ...................................................................... 102
Assembler
Charge Pump (LCD) .......................................................... 95
CKP (Clock Polarity Select) bit .......................................... 60
Clocking Scheme ................................................................. 9
Code Examples
MPASM Assembler .................................................. 133
Associated Registers ......................................................... 81
Call of a Subroutine in Page 1 from Page 0 .............. 25
Changing Between Capture Prescalers .................... 54
Changing Prescaler (Timer0 to WDT) ....................... 45
Changing Prescaler (WDT to Timer0) ....................... 45
I/O Programming ....................................................... 39
B
BF bit .................................................................................. 70
Block Diagrams
A/D Converter ............................................................ 77
Analog Input Model .................................................... 78
Capture Mode ............................................................ 54
Compare Mode .......................................................... 55
External Parallel Cystal Oscillator ............................ 100
External Series Crystal Oscillator ............................ 100
Interrupt Logic .......................................................... 107
LCD Charge Pump ..................................................... 95
LCD Module ............................................................... 84
LCD Resistor Ladder ................................................. 95
On-Chip Reset Circuit .............................................. 101
PIC16C925/926 Architecture ....................................... 6
PORTA
2
I C Module Operation ................................................ 73
Indirect Addressing .................................................... 26
Initializing PORTA ..................................................... 29
Initializing PORTB ..................................................... 31
Initializing PORTC ..................................................... 33
Initializing PORTD ..................................................... 34
Initializing PORTE ..................................................... 36
Initializing PORTF ...................................................... 37
Initializing PORTG ..................................................... 38
Loading the SSPBUF Register .................................. 61
Program Read ........................................................... 28
Reading a 16-bit Free-running Timer ........................ 49
Saving STATUS, W and PCLATH Registers
RA3:RA0 and RA5 Port Pins ............................. 29
RA4/T0CKI Pin .................................................. 29
PORTB
in RAM ............................................................. 109
Segment Enable
One-Third-Duty with 13 Segments .................... 94
Static MUX with 32 Segments ........................... 94
RB3:RB0 Port Pins ............................................ 31
RB7:RB4 Port Pins ............................................ 31
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 169
PIC16C925/926
Code Protection ......................................................... 97, 112
Compare Mode (CCP)
BSF .......................................................................... 117
BTFSC ..................................................................... 117
BTFSS ..................................................................... 118
CALL ........................................................................ 118
CLRF ....................................................................... 119
CLRW ...................................................................... 119
CLRWDT ................................................................. 120
COMF ...................................................................... 120
DECF ....................................................................... 121
DECFSZ .................................................................. 121
GOTO ...................................................................... 122
INCF ........................................................................ 122
INCFSZ .................................................................... 123
IORLW ..................................................................... 123
IORWF ..................................................................... 124
MOVF ...................................................................... 124
MOVLW ................................................................... 124
MOVWF ................................................................... 125
NOP ......................................................................... 125
OPTION ................................................................... 125
RETFIE .................................................................... 126
RETLW .................................................................... 126
RETURN .................................................................. 127
RLF .......................................................................... 127
RRF ......................................................................... 128
SLEEP ..................................................................... 128
SUBLW .................................................................... 129
SUBWF .................................................................... 129
SWAPF .................................................................... 130
TRIS ........................................................................ 130
XORLW ................................................................... 131
XORWF ................................................................... 131
Instruction Set Summary ......................................... 113–131
INT Interrupt ..................................................................... 108
INTCON Register ....................................................... 21, 107
Initialization States ................................................... 104
Associated Registers .................................................58
Block Diagram ............................................................55
Pin Configuration .......................................................55
Software Interrupt Mode ............................................55
Special Event Trigger .................................................55
Timer1 Mode ..............................................................55
Computed GOTO ...............................................................25
Configuration Bits ...............................................................97
Configuration Word ............................................................98
D
DC and AC Characteristics Graphs and Tables ...............159
DC bit .................................................................................19
Development Support ......................................................133
Device DC Characteristics .......................................141–145
LC Devices ...............................................................144
Direct Addressing ...............................................................26
E
Errata ...................................................................................4
F
FSR Register ......................................................................26
Initialization States ...................................................104
G
GIE bit ..............................................................................107
I
I/O Programming Considerations .......................................39
Read-Modify-Write Example ......................................39
2
I C
2
Addressing I C Devices .............................................66
Arbitration ...................................................................68
BF ........................................................................ 70, 71
CKP ............................................................................71
Clock Synchronization ...............................................68
Combined Format ......................................................67
Initiating and Terminating Data Transfer ....................65
Master-Receiver Sequence .......................................67
Master-Transmitter Sequence ...................................67
Multi-Master ...............................................................68
Overview ....................................................................65
START .......................................................................65
STOP ................................................................... 65, 66
Transfer Acknowledge ...............................................66
ICEPIC In-Circuit Emulator ..............................................134
IDLE_MODE ......................................................................73
In-Circuit Serial Programming .................................... 97, 112
INDF Register ....................................................................26
Initialization States ...................................................104
Indirect Addressing ............................................................26
Instruction Cycle ...................................................................9
Instruction Flow/Pipelining ...................................................9
Instruction Format ............................................................113
Instruction Set
2
2
Inter-Integrated Circuit (I C). See I C.
Internal Sampling Switch (Rss) Impedence ....................... 78
Interrupt Flag ................................................................... 107
Interrupts .................................................................... 97, 107
RB7:RB4 Port Change ............................................... 31
IRP bit ................................................................................ 19
K
KEELOQ Evaluation and Programming Tools ................... 136
L
LCD Module
Associated Registers ................................................. 96
Block Diagram ........................................................... 84
Charge Pump ............................................................ 95
Block Diagram ................................................... 95
Electrical Specifications ........................................... 145
External R-Ladder ...................................................... 95
Block Diagram ................................................... 95
Generic LCDD Register ............................................. 92
LCDCON Register ..................................................... 83
LCDPS Register ........................................................ 84
LCDSE Register ........................................................ 94
Register Initialization States .................................... 105
Voltage Generation .................................................... 95
Loading PC Register (Diagram) ......................................... 25
ADDLW ....................................................................115
ADDWF ....................................................................115
ANDLW ....................................................................116
ANDWF ....................................................................116
BCF ..........................................................................117
DS39544A-page 170
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
Pin Functions
M
MCLR/VPP ................................................................... 7
OSC1/CLKIN ............................................................... 7
OSC2/CLKOUT ........................................................... 7
RA0/AN0 ...................................................................... 7
RA1/AN1 ...................................................................... 7
RA2/AN2 ...................................................................... 7
RA3/AN3/VREF ............................................................ 7
RA4/T0CKI .................................................................. 7
RA5/AN4/SS ................................................................ 7
RB0/INT ....................................................................... 7
RB1 .............................................................................. 7
RB2 .............................................................................. 7
RB3 .............................................................................. 7
RB4 .............................................................................. 7
RB5 .............................................................................. 7
RB6 .............................................................................. 7
RB7 .............................................................................. 7
RC0/T1OSO/T1CKI ..................................................... 7
RC1/T1OSI .................................................................. 7
RC2/CCP1 ................................................................... 7
RC3/SCK/SCL ............................................................. 7
RC4/SDI/SDA .............................................................. 7
RC5/SDO ..................................................................... 7
RD0/SEG00 ................................................................. 8
RD1/SEG01 ................................................................. 8
RD2/SEG02 ................................................................. 8
RD3/SEG03 ................................................................. 8
RD4/SEG04 ................................................................. 8
RD5/SEG29/COM3 ..................................................... 8
RD6/SEG30/COM2 ..................................................... 8
RD7/SEG31/COM1 ..................................................... 8
RE0/SEG05 ................................................................. 8
RE1/SEG06 ................................................................. 8
RE2/SEG07 ................................................................. 8
RE3/SEG08 ................................................................. 8
RE4/SEG09 ................................................................. 8
RE5/SEG10 ................................................................. 8
RE6/SEG11 ................................................................. 8
RE7/SEG27 ................................................................. 8
RF0/SEG12 ................................................................. 8
RF1/SEG13 ................................................................. 8
RF2/SEG14 ................................................................. 8
RF3/SEG15 ................................................................. 8
RF4/SEG16 ................................................................. 8
RF5/SEG17 ................................................................. 8
RF6/SEG18 ................................................................. 8
RF7/SEG19 ................................................................. 8
RG0/SEG20 ................................................................. 8
RG1/SEG21 ................................................................. 8
RG2/SEG22 ................................................................. 8
RG3/SEG23 ................................................................. 8
RG4/SEG24 ................................................................. 8
RG5/SEG25 ................................................................. 8
RG6/SEG26 ................................................................. 8
RG7/SEG28 ................................................................. 8
VDD .............................................................................. 8
VSS .............................................................................. 8
PIR1 Register ............................................................ 23, 107
Initialization States ................................................... 104
POP ................................................................................... 25
Master Clear (MCLR) ....................................................... 101
MCLR Initialization Condition for Registers ............. 104
MCLR Reset, Normal Operation .............................. 103
MCLR Reset, SLEEP ............................................... 103
MCLR. See Master Clear.
Memory
Data Memory ............................................................. 12
Maps, PIC16C9XX ..................................................... 11
Program Memory ....................................................... 11
MPLAB C17 and MPLAB C18 C Compilers ..................... 133
MPLAB ICD In-Circuit Debugger ..................................... 135
MPLAB ICE High Performance Universal
In-Circuit Emulator with MPLAB IDE ........................ 134
MPLAB Integrated Development
Environment Software .............................................. 133
MPLINK Object Linker/MPLIB Object Librarian ............... 134
O
OPCODE ......................................................................... 113
OPTION_REG Register ..................................................... 20
Initialization States ................................................... 104
INTEDG Bit ................................................................ 20
PS2:PS0 Bits ............................................................. 20
PSA Bit ....................................................................... 20
T0CS Bit ..................................................................... 20
T0SE Bit ..................................................................... 20
OSC selection .................................................................... 97
Oscillator
HS ...................................................................... 99, 102
LP ....................................................................... 99, 102
Oscillator Configurations .................................................... 99
P
Package Details ............................................................... 163
Package Marking Information .......................................... 161
Packaging Information ..................................................... 161
Paging, Program Memory .................................................. 25
PCL Register ...................................................................... 25
Initialization States ................................................... 104
PCLATH Register .............................................................. 25
Initialization States ................................................... 104
PCON Register .................................................................. 24
BOR Bit ...................................................................... 24
Initialization States ................................................... 104
POR Bit ...................................................................... 24
PD bit ......................................................................... 19, 101
PICDEM 1 Low Cost PICmicro
Demonstration Board ............................................... 135
PICDEM 17 Demonstration Board ................................... 136
PICDEM 2 Low Cost PIC16CXX
Demonstration Board ............................................... 135
PICDEM 3 Low Cost PIC16CXXX
Demonstration Board ............................................... 136
PICSTART Plus Entry Level
Development Programmer ....................................... 135
PIE1 Register ............................................................. 22, 107
Initialization States ................................................... 104
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 171
PIC16C925/926
POR .................................................................................102
Oscillator Start-up Timer (OST) ......................... 97, 102
POR Status (POR Bit) ................................................24
Power Control Register (PCON) ..............................102
Power-on Reset (POR) .............................. 97, 102, 104
Power-up Timer (PWRT) ................................... 97, 102
RESET Condition for Special Registers ...................103
Time-out Sequence ..................................................102
Time-out Sequence on Power-up ............................106
TO ............................................................................101
Port RB Interrupt ..............................................................108
PORTA
Associated Registers .................................................30
Initialization ................................................................29
Initialization States ...................................................104
Pin Functions .............................................................30
RA3:RA0 and RA5 Port Pins .....................................29
RA4/T0CKI Pin ...........................................................29
Register ......................................................................29
TRISA Register ..........................................................29
PORTB
PORTG
Associated Registers ................................................. 38
Block Diagram ........................................................... 38
Initialization ................................................................ 38
Initialization States ................................................... 105
Pin Functions ............................................................. 38
Register ..................................................................... 38
TRISG Register ......................................................... 38
Postscaler, WDT
Assignment (PSA Bit) ................................................ 20
Rate Select (PS2:PS0 Bits) ....................................... 20
Power-down Mode (SLEEP) ............................................ 111
Power-on Reset. See POR.
PR2 .................................................................................. 105
Prescaler, Timer0
Assignment (PSA Bit) ................................................ 20
Rate Select (PS2:PS0 Bits) ....................................... 20
Switching Between Timer0 and WDT ........................ 45
PRO MATE II Universal Device Programmer .................. 135
Product Identification System .......................................... 177
Program Counter
Associated Registers .................................................32
Initialization ................................................................31
Initialization States ...................................................104
Pin Functions .............................................................32
RB0/INT Edge Select (INTEDG Bit) ...........................20
RB3:RB0 Port Pins ....................................................31
RB7:RB4 Port Pins ....................................................31
Register ......................................................................31
TRISB Register ..........................................................31
PORTC
Associated Registers .................................................33
Block Diagram (Peripheral Output Override) .............33
Initialization ................................................................33
Initialization States ...................................................104
Pin Functions .............................................................33
Register ......................................................................33
TRISC Register ..........................................................33
PORTD
Associated Registers .................................................35
Initialization ................................................................34
Initialization States ...................................................104
Pin Functions .............................................................35
Pins <4:0> ..................................................................34
Pins <7:5> ..................................................................34
Register ......................................................................34
TRISD Register ..........................................................34
PORTE
RESET Conditions ................................................... 103
Program Memory
Associated Registers ................................................. 28
Operation During Code Protect ................................. 28
PMADR Register ....................................................... 27
PMCON1 Register ..................................................... 27
Program Read (Code Example) ................................ 28
Read .......................................................................... 28
Program Memory and Stack Maps .................................... 11
PUSH ................................................................................. 25
PWM Mode (CCP) ............................................................. 56
Associated Registers ................................................. 58
Block Diagram ........................................................... 56
Example Frequencies/Resolutions ............................ 57
Example Period and Duty Cycle Calculations ........... 57
R
R/W bit ................................................................... 66, 70, 71
RBIF bit ...................................................................... 31, 108
RC Oscillator ...................................................... 99, 100, 102
RCV_MODE ...................................................................... 73
Read-Modify-Write ............................................................. 39
Register File ....................................................................... 12
Register File Map
PIC16C925 ................................................................ 13
PIC16C926 ................................................................ 14
Registers
ADCON0 (A/D Control 0) ........................................... 75
ADCON1 (A/D Control 1) ........................................... 76
CCP1CON (CCP Control) .......................................... 53
Flag ............................................................................ 23
Initialization Conditions .................................... 104–105
INTCON (Interrupt Control) ........................................ 21
LCDCON (LCD Control) ............................................ 83
LCDD (LCD Pixel Data, General Format) .................. 92
LCDPS (LCD Prescale) ............................................. 84
LCDSE (LCD Segment Enable) ................................. 94
OPTION_REG ........................................................... 20
PCON (Power Control) .............................................. 24
PIE2 (Peripheral Interrupt Enable 1) .......................... 22
PIR1 (Peripheral Interrupt Request) .......................... 23
PMCON1 (Program Memory Control) ........................ 27
SSPCON (Sync Serial Port Control) .......................... 60
SSPSTAT (Sync Serial Port Status) .......................... 59
STATUS .................................................................... 19
Associated Registers .................................................36
Block Diagram ............................................................36
Initialization ................................................................36
Initialization States ...................................................104
Pin Functions .............................................................36
Register ......................................................................36
TRISE Register ..........................................................36
PORTF
Associated Registers .................................................37
Block Diagram ............................................................37
Initialization ................................................................37
Initialization States ...................................................105
Pin Functions .............................................................37
Register ......................................................................37
TRISF Register ..........................................................37
DS39544A-page 172
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
T1CON (Timer1 Control) ............................................ 47
T2CON (Timer2 Control) ............................................ 52
RESET ....................................................................... 97, 101
Block Diagram .......................................................... 101
RESET Conditions for PCON Register .................... 103
RESET Conditions for Program Counter ................. 103
RESET Conditions for STATUS Register ................ 103
Resistor Ladder (LCD) ....................................................... 95
RP1:RP0 (Bank Select) bits ......................................... 12, 19
T
TAD .................................................................................... 79
Timer0
Associated Registers ................................................. 45
Block Diagram ........................................................... 41
Clock Source Edge Select (T0SE Bit) ....................... 20
Clock Source Select (T0CS Bit) ................................ 20
External Clock ........................................................... 43
Synchronization ................................................. 43
Timing ................................................................ 43
Increment Delay ........................................................ 43
Initialization States ................................................... 104
Interrupt ..................................................................... 41
Interrupt Timing ......................................................... 42
Prescaler ................................................................... 44
Block Diagram ................................................... 44
Timing ........................................................................ 42
TMR0 Interrupt ........................................................ 108
Timer1
S
SCL ........................................................................ 70, 71, 72
SDA .............................................................................. 71, 72
Slave Mode
SCL pin ...................................................................... 70
SDA pin ...................................................................... 70
SLEEP ....................................................................... 97, 101
Software Simulator (MPLAB SIM) .................................... 134
Special Features of the CPU ............................................. 97
Special Function Registers, Summary ............................... 15
SPI
Associated Registers ................................................. 64
Master Mode .............................................................. 62
Serial Clock ................................................................ 61
Serial Data In ............................................................. 61
Serial Data Out .......................................................... 61
Serial Peripheral Interface (SPI) ................................ 59
Slave Select ............................................................... 61
SPI Clock ................................................................... 62
SPI Mode ................................................................... 61
SSP
Associated Registers ................................................. 50
Asynchronous Counter Mode .................................... 49
Block Diagram ........................................................... 48
Capacitor Selection ................................................... 50
External Clock Input
Synchronized Counter Mode ............................. 48
Timing with Unsynchronized Clock .................... 49
Unsynchronized Clock Timing ........................... 49
Oscillator .................................................................... 50
Prescaler ................................................................... 50
Reading a Free-running Timer .................................. 49
Register Initialization States .................................... 104
Resetting Register Pair .............................................. 50
Resetting with a CCP Trigger Output ........................ 50
Switching Prescaler Assignment ............................... 45
Synchronized Counter Mode ..................................... 48
T1CON Register ........................................................ 47
Timer Mode ............................................................... 48
Timer2
Block Diagrams
2
I C Mode ............................................................ 69
SPI Mode ........................................................... 61
Register Initialization States ............................. 104, 105
SSPADD Register ................................................ 69, 70
SSPBUF Register .................................... 62, 69, 70, 71
SSPCON Register ............................................... 60, 69
SSPIF bit ........................................................ 70, 71, 72
SSPOV bit .................................................................. 70
SSPSR ....................................................................... 62
SSPSR Register .................................................. 70, 71
SSPSTAT ................................................................... 71
SSPSTAT Register ........................................ 59, 69, 71
Block Diagram ........................................................... 51
Output ........................................................................ 51
Register Initialization States .................................... 104
T2CON Register ........................................................ 52
Timing Diagrams (Operational)
Clock/Instruction Cycle ................................................ 9
2
SSP I C
2
I C Clock Synchronization ......................................... 68
Addressing ................................................................. 70
Associated Registers ................................................. 72
Multi-Master Mode ..................................................... 72
Reception ................................................................... 71
2
I C Data Transfer Wait State ..................................... 66
2
I C Multi-Master Arbitration ....................................... 68
2
I C Reception (7-bit address) .................................... 71
2
I C Slave-Receiver Acknowledge .............................. 66
2
SSP I C Operation ..................................................... 69
2
I C STARTand STOP Conditions .............................. 65
START ....................................................................... 71
START (S) ................................................................. 72
STOP (P) ................................................................... 72
Transmission .............................................................. 71
SSPEN (Sync Serial Port Enable) bit ................................. 60
SSPM3:SSPM0 .................................................................. 60
SSPOV (Receive Overflow Indicator) bit ........................... 60
SSPOV bit .......................................................................... 70
Stack .................................................................................. 25
Overflows ................................................................... 25
Underflow ................................................................... 25
STATUS Register .............................................................. 19
Initialization States ................................................... 104
Synchronous Serial Port Mode Select bits,
2
I C Transmission (7-bit address) ............................... 71
INT Pin Interrupt Timing .......................................... 108
LCD Half-Duty Cycle Drive ........................................ 86
LCD Interrupt Timing in Quarter-Duty Cycle Drive .... 91
LCD One-Third Duty Cycle Drive .............................. 87
LCD Quarter-Duty Cycle Drive .................................. 88
LCD SLEEP Entry/Exit (SLPEN=1) ........................... 93
LCD Static Drive ........................................................ 85
SPI (Master Mode) .................................................... 63
SPI (Slave Mode, CKE = 0) ....................................... 63
SPI (Slave Mode, CKE = 1) ....................................... 64
Successive I/O Operation .......................................... 39
Time-out Sequences on Power-up .......................... 106
Timer0 Interrupt Timing ............................................. 42
Timer0 with External Clock ........................................ 43
SSPM3:SSPM0 .......................................................... 60
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 173
PIC16C925/926
Timer0,Internal Timing ...............................................42
Wake-up from SLEEP through Interrupt ..................112
Timing Diagrams and Specifications ................................147
Timing Parameter Symbology ..........................................146
TO bit .................................................................................19
TRISA Register ..................................................................29
Initialization State .....................................................104
TRISB Register ..................................................................31
Initialization State .....................................................104
TRISC Register ..................................................................33
Initialization State .....................................................104
TRISD Register ..................................................................34
Initialization State .....................................................104
TRISE Register ..................................................................36
Initialization State .....................................................104
TRISF Register ..................................................................37
Initialization States ...................................................105
TRISG Register ..................................................................38
Initialization States ...................................................105
W
W Register
Initialization States ................................................... 104
Wake-up from SLEEP ...................................................... 111
Interrupts ................................................................. 103
Watchdog Timer (WDT) ..................................... 97, 101, 110
Associated Registers ............................................... 110
WDT Reset, Normal Operation ................................ 103
WDT Reset, SLEEP ................................................. 103
WCOL ................................................................................ 60
WDT
Period ...................................................................... 110
Programming Considerations .................................. 110
Timeout .................................................................... 104
Write Collision Detect bit, WCOL ....................................... 60
WWW, On-Line Support .............................................. 4, 175
X
XMIT_MODE ..................................................................... 73
XT .............................................................................. 99, 102
Z
Z (Zero) bit ......................................................................... 19
DS39544A-page 174
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
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Microchip provides on-line support on the Microchip
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The web site is used by Microchip as a means to make
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Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
013001
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
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• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 175
PIC16C925/926
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Literature Number:
DS39544A
Device:
PIC16C925/926
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
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DS39544A-page 176
Preliminary
2001 Microchip Technology Inc.
PIC16C925/926
PIC16C925/926 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
−
Examples:
Temperature Package
Range
Pattern
a) PIC16C926/P 301 = Commercial
Temp., normal VDD limits, QTP
pattern #301
b) PIC16LC925/PT
=
Commercial
Device
PIC16C92X(1), PIC16C92XT(2)
VDD range 4.0V to 5.5V
;
Temp., TQFP package, extended
VDD limits
PIC16LC92X(1), PIC16LC92XT(2)
VDD range 2.5V to 5.5V
;
c) PIC16C925-I/CL = Industrial Temp.,
windowed CERQUAD package,
normal VDD limits
Temperature
Range
I
S
-
=
=
=
=
-40°C to +85°C (Industrial)
-40°C to +85°C (Industrial, tape/reel)
0°C to +70°C (Commercial)
0°C to +70°C (Commercial,
tape/reel)
Note 1: C = Standard Voltage range
T
LC = Wide Voltage Range
2:
T
= in tape and reel -
PLCC and TQFP
packages only.
Package
Pattern
CL = Windowed CERQUAD(3)
PT = TQFP (Thin Quad Flatpack)
3: CL Devices are UV erasable and
L
=
PLCC
can be programmed to any
device
devices meet the electrical
requirement of each oscillator
type (including LC devices).
configuration.
CL
QTP, SQTP, Code or Special Requirements
(blank otherwise)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 177
PIC16C925/926
NOTES:
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 178
PIC16C925/926
NOTES:
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 179
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01/30/01
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 3/01
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
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tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS39544A-page 180
Preliminary
2001 Microchip Technology Inc.
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