PIC16LC715-20I/SP_技术文档

PIC16C71X

8-Bit CMOS Microcontrollers with A/D Converter

Devices included in this data sheet:

PIC16C71X Peripheral Features:

• PIC16C710

• PIC16C71

• PIC16C711

• PIC16C715

• Timer0: 8-bit timer/counter with 8-bit prescaler

• 8-bit multichannel analog-to-digital converter

• Brown-out detection circuitry for

Brown-out Reset (BOR)

• 13 I/O Pins with Individual Direction Control

PIC16C71X Microcontroller Core Features:

PIC16C7X Features

710 71 711 715

• High-performance RISC CPU

• Only 35 single word instructions to learn

Program Memory (EPROM)

x 14

512 1K 1K 2K

• All single cycle instructions except for program

branches which are two cycle

Data Memory (Bytes) x 8

I/O Pins

36 36 68 128

13 13 13 13

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

Timer Modules

A/D Channels

1

4

1

4

1

4

1

4

• Up to 2K x 14 words of Program Memory,

up to 128 x 8 bytes of Data Memory (RAM)

• Interrupt capability

In-Circuit Serial Programming Yes Yes Yes Yes

• Eight level deep hardware stack

• Direct, indirect, and relative addressing modes

• Power-on Reset (POR)

Brown-out Reset

Interrupt Sources

Yes

4

—

4

Yes Yes

4

• Power-up Timer (PWRT) and

Oscillator Start-up Timer (OST)

Pin Diagrams

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

PDIP, SOIC, Windowed CERDIP

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

MCLR/VPP

VSS

• 1

2

18

17

16

15

14

RA1/AN1

RA0/AN0

3

OSC1/CLKIN

OSC2/CLKOUT

VDD

4

5

• Low-power, high-speed CMOS EPROM

technology

RB0/INT

RB1

6

7

8

13

12

11

RB7

RB6

RB5

RB2

• Fully static design

RB3

9

10

RB4

• Wide operating voltage range: 2.5V to 6.0V

• High Sink/Source Current 25/25 mA

• Commercial, Industrial and Extended temperature

ranges

SSOP

• Program Memory Parity Error Checking Circuitry

with Parity Error Reset (PER) (PIC16C715)

RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

MCLR/VPP

VSS

• 1

2

20

19

18

17

16

RA1/AN1

RA0/AN0

3

OSC1/CLKIN

OSC2/CLKOUT

VDD

• Low-power consumption:

- < 2 mA @ 5V, 4 MHz

4

5

VSS

RB0/INT

RB1

6

7

8

15

14

13

VDD

RB7

RB6

- 15 µA typical @ 3V, 32 kHz

- < 1 µA typical standby current

RB2

9

12

11

RB5

RB4

RB3

10

1997 Microchip Technology Inc.

DS30272A-page 1

PIC16C71X

Table of Contents

1.0 General Description.................................................................................................................................................................... 3

2.0 PIC16C71X Device Varieties...................................................................................................................................................... 5

3.0 Architectural Overview................................................................................................................................................................ 7

4.0 Memory Organization ............................................................................................................................................................... 11

5.0 I/O Ports.................................................................................................................................................................................... 25

6.0 Timer0 Module.......................................................................................................................................................................... 31

7.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................ 37

8.0 Special Features of the CPU .................................................................................................................................................... 47

9.0 Instruction Set Summary .......................................................................................................................................................... 69

10.0 Development Support............................................................................................................................................................... 85

11.0 Electrical Characteristics for PIC16C710 and PIC16C711....................................................................................................... 89

12.0 DC and AC Characteristics Graphs and Tables for PIC16C710 and PIC16C711.................................................................. 101

13.0 Electrical Characteristics for PIC16C715................................................................................................................................ 111

14.0 DC and AC Characteristics Graphs and Tables for PIC16C715 ............................................................................................ 125

15.0 Electrical Characteristics for PIC16C71.................................................................................................................................. 135

16.0 DC and AC Characteristics Graphs and Tables for PIC16C71 .............................................................................................. 147

17.0 Packaging Information............................................................................................................................................................ 155

Appendix A: ...................................................................................................................................................................................... 161

Appendix B: Compatibility................................................................................................................................................................. 161

Appendix C: What’s New.................................................................................................................................................................. 162

Appendix D: What’s Changed .......................................................................................................................................................... 162

Index .................................................................................................................................................................................................. 163

PIC16C71X Product Identification System......................................................................................................................................... 173

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional

amount of time to ensure that these documents are correct. However, we realize that we may have missed a few

things. If you ﬁnd any information that is missing or appears in error, please use the reader response form in the

back of this data sheet to inform us. We appreciate your assistance in making this a better document.

DS30272A-page 2

1997 Microchip Technology Inc.

PIC16C71X

A highly reliable Watchdog Timer with its own on-chip

RC oscillator provides protection against software lock-

up.

1.0

GENERAL DESCRIPTION

The PIC16C71X is a family of low-cost, high-perfor-

mance, CMOS, fully-static, 8-bit microcontrollers with

integrated analog-to-digital (A/D) converters, in the

PIC16CXX mid-range family.

A UV erasable CERDIP packaged version is ideal for

code development while the cost-effective One-Time-

Programmable (OTP) version is suitable for production

in any volume.

All PIC16/17 microcontrollers employ an advanced

RISC architecture.The PIC16CXX microcontroller fam-

ily has enhanced core features, eight-level deep stack,

and multiple internal and external interrupt sources.

The separate instruction and data buses of the Harvard

architecture allow a 14-bit wide instruction word with

the separate 8-bit wide data. The two stage instruction

pipeline allows all instructions to execute in a single

cycle, except for program branches which require two

cycles. A total of 35 instructions (reduced instruction

set) are available. Additionally, a large register set gives

some of the architectural innovations used to achieve a

very high performance.

The PIC16C71X family ﬁts perfectly in applications

ranging from security and remote sensors to appliance

control and automotive. The EPROM technology

makes customization of application programs (trans-

mitter codes, motor speeds, receiver frequencies, etc.)

extremely fast and convenient. The small footprint

packages make this microcontroller series perfect for

all applications with space limitations. Low cost, low

power, high performance, ease of use and I/O ﬂexibility

make the PIC16C71X very versatile even in areas

where no microcontroller use has been considered

before (e.g. timer functions, serial communication, cap-

ture and compare, PWM functions and coprocessor

applications).

PIC16CXX microcontrollers typically achieve a 2:1

code compression and a 4:1 speed improvement over

other 8-bit microcontrollers in their class.

1.1

Family and Upward Compatibility

The PIC16C710/71 devices have 36 bytes of RAM, the

PIC16C711 has 68 bytes of RAM and the PIC16C715

has 128 bytes of RAM. Each device has 13 I/O pins. In

addition a timer/counter is available. Also a 4-channel

high-speed 8-bit A/D is provided.The 8-bit resolution is

ideally suited for applications requiring low-cost analog

interface, e.g. thermostat control, pressure sensing,

etc.

Users familiar with the PIC16C5X microcontroller fam-

ily will realize that this is an enhanced version of the

PIC16C5X architecture. Please refer to Appendix A for

a detailed list of enhancements. Code written for the

PIC16C5X can be easily ported to the PIC16CXX fam-

ily of devices (Appendix B).

1.2

Development Support

The PIC16C71X family has special features to reduce

external components, thus reducing cost, enhancing

system reliability and reducing power consumption.

There are four oscillator options, of which the single pin

RC oscillator provides a low-cost solution, the LP oscil-

lator minimizes power consumption, XT is a standard

crystal, and the HS is for High Speed crystals. The

SLEEP (power-down) feature provides a power saving

mode. The user can wake up the chip from SLEEP

through several external and internal interrupts and

resets.

PIC16C71X devices are supported by the complete

line of Microchip Development tools.

Please refer to Section 10.0 for more details about

Microchip’s development tools.

1997 Microchip Technology Inc.

DS30272A-page 3

PIC16C71X

TABLE 1-1:

PIC16C71X FAMILY OF DEVICES

(1)

PIC16C710 PIC16C71 PIC16C711 PIC16C715

PIC16C72 PIC16CR72

Maximum Frequency

of Operation (MHz)

20

1K

—

20

1K

—

20

2K

—

20

Clock

EPROM Program Memory

(x14 words)

512

—

2K

—

Memory

ROM Program Memory

(14K words)

2K

128

Data Memory (bytes)

Timer Module(s)

36

68

128

TMR0

TMR0,

TMR1,

TMR2

TMR0,

TMR1,

TMR2

Capture/Compare/PWM

Module(s)

—

1

Peripherals

2

Serial Port(s)

SPI/I C

2

(SPI/I C, USART)

Parallel Slave Port

—

A/D Converter (8-bit) Channels 4

4

5

Interrupt Sources

I/O Pins

4

8

13

22

Voltage Range (Volts)

2.5-6.0

3.0-6.0

Yes

—

2.5-6.0

Yes

2.5-5.5

Yes

2.5-6.0

Yes

3.0-5.5

Yes

In-Circuit Serial Programming Yes

Features

Brown-out Reset

Packages

Yes

18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP,

SOIC;

SOIC

SOIC;

SOIC, SSOP SOIC, SSOP

20-pin SSOP

20-pin SSOP 20-pin SSOP

PIC16C73A

PIC16C74A

PIC16C76

PIC16C77

Maximum Frequency

of Operation (MHz)

20

Clock

EPROM Program Memory

(x14 words)

4K

192

4K

192

8K

376

Memory

Data Memory (bytes)

Timer Module(s)

376

TMR0,

TMR1,

TMR2

TMR0,

TMR1,

TMR2

TMR0,

TMR1,

TMR2

TMR0,

TMR1,

TMR2

Capture/Compare/PWM

Module(s)

2

Peripherals

2

Serial Port(s)

(SPI/I C, USART)

SPI/I C, USART

2

Parallel Slave Port

—

Yes

8

—

Yes

8

A/D Converter (8-bit) Channels 5

5

Interrupt Sources

I/O Pins

11

12

11

12

22

33

22

33

Voltage Range (Volts)

2.5-6.0

Yes

2.5-6.0

Yes

2.5-6.0

Yes

In-Circuit Serial Programming Yes

Features

Brown-out Reset

Packages

Yes

28-pin SDIP,

SOIC

40-pin DIP;

44-pin PLCC,

MQFP, TQFP

28-pin SDIP,

SOIC

40-pin DIP;

44-pin PLCC,

MQFP, TQFP

All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capabil-

ity. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7.

Note 1: Please contact your local Microchip sales ofﬁce for availability of these devices.

DS30272A-page 4

1997 Microchip Technology Inc.

PIC16C71X

2.3

Quick-Turnaround-Production (QTP)

Devices

2.0

PIC16C71X DEVICE VARIETIES

A variety of frequency ranges and packaging options

are available. Depending on application and production

requirements, the proper device option can be selected

using the information in the PIC16C71X Product Iden-

tiﬁcation System section at the end of this data sheet.

When placing orders, please use that page of the data

sheet to specify the correct part number.

Microchip offers a QTP Programming Service for fac-

tory production orders. This service is made available

for users who choose not to program a medium to high

quantity of units and whose code patterns have stabi-

lized. The devices are identical to the OTP devices but

with all EPROM locations and conﬁguration options

already programmed by the factory. Certain code and

prototype veriﬁcation procedures apply before produc-

tion shipments are available. Please contact your local

Microchip Technology sales ofﬁce for more details.

For the PIC16C71X family, there are two device “types”

as indicated in the device number:

1. C, as in PIC16C71. These devices have

EPROM type memory and operate over the

standard voltage range.

2.4

Serialized Quick-Turnaround

Production (SQTP^SM) Devices

2. LC, as in PIC16LC71. These devices have

EPROM type memory and operate over an

extended voltage range.

Microchip offers a unique programming service where

a few user-deﬁned locations in each device are pro-

grammed with different serial numbers.The serial num-

bers may be random, pseudo-random, or sequential.

2.1

UV Erasable Devices

The UV erasable version, offered in CERDIP package

is optimal for prototype development and pilot

programs. This version can be erased and

reprogrammed to any of the oscillator modes.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password, or ID number.

Microchip's PICSTART

Plus and PRO MATE II

programmers both support programming of the

PIC16C71X.

2.2

One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers who need the ﬂexibility for frequent code

updates and small volume applications.

The OTP devices, packaged in plastic packages, per-

mit the user to program them once. In addition to the

program memory, the conﬁguration bits must also be

programmed.

1997 Microchip Technology Inc.

DS30272A-page 5

PIC16C71X

NOTES:

DS30272A-page 6

1997 Microchip Technology Inc.

PIC16C71X

PIC16CXX devices contain an 8-bit ALU and working

register. The ALU is a general purpose arithmetic unit.

It performs arithmetic and Boolean functions between

the data in the working register and any register ﬁle.

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC16CXX family can be

attributed to a number of architectural features com-

monly found in RISC microprocessors. To begin with,

the PIC16CXX uses a Harvard architecture, in which,

program and data are accessed from separate memo-

ries using separate buses. This improves bandwidth

over traditional von Neumann architecture in which pro-

gram and data are fetched from the same memory

using the same bus. Separating program and data

buses further allows instructions to be sized differently

than the 8-bit wide data word. Instruction opcodes are

14-bits wide making it possible to have all single word

instructions. A 14-bit wide program memory access

bus fetches a 14-bit instruction in a single cycle. A two-

stage pipeline overlaps fetch and execution of instruc-

tions (Example 3-1). Consequently, all instructions (35)

execute in a single cycle (200 ns @ 20 MHz) except for

program branches.

The ALU is 8-bits wide and capable of addition, sub-

traction, shift and logical operations. Unless otherwise

mentioned, arithmetic operations are two's comple-

ment in nature. In two-operand instructions, typically

one operand is the working register (W register). The

other operand is a ﬁle register or an immediate con-

stant. In single operand instructions, the operand is

either the W register or a ﬁle register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register.The C and DC bits

operate as a borrow bit and a digit borrow out bit,

respectively, in subtraction. See the SUBLWand SUBWF

instructions for examples.

The table below lists program memory (EPROM) and

data memory (RAM) for each PIC16C71X device.

Program

Memory

Device

Data Memory

PIC16C710

PIC16C71

PIC16C711

PIC16C715

512 x 14

1K x 14

2K x 14

36 x 8

68 x 8

128 x 8

The PIC16CXX can directly or indirectly address its

register ﬁles or data memory. All special function regis-

ters, including the program counter, are mapped in the

data memory.The PIC16CXX has an orthogonal (sym-

metrical) instruction set that makes it possible to carry

out any operation on any register using any addressing

mode. This symmetrical nature and lack of ‘special

optimal situations’ make programming with the

PIC16CXX simple yet efﬁcient. In addition, the learning

curve is reduced signiﬁcantly.

1997 Microchip Technology Inc.

DS30272A-page 7

PIC16C71X

FIGURE 3-1: PIC16C71X BLOCK DIAGRAM

Device

Program Memory Data Memory (RAM)

PIC16C710

PIC16C71

PIC16C711

PIC16C715

512 x 14

1K x 14

2K x 14

36 x 8

68 x 8

128 x 8

13

8

PORTA

Data Bus

Program Counter

EPROM

RA0/AN0

RA1/AN1

RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

Program

Memory

RAM

8 Level Stack

(13-bit)

File

Registers

Program

Bus

14

RAM Addr ⁽¹⁾

PORTB

9

Addr MUX

Instruction reg

RB0/INT

RB7:RB1

Indirect

Addr

7

Direct Addr

8

FSR reg

STATUS reg

8

3

MUX

Power-up

Timer

Instruction

Decode &

Control

Oscillator

Start-up Timer

ALU

8

Power-on

Reset

Timing

Generation

W reg

Watchdog

Timer

OSC1/CLKIN

OSC2/CLKOUT

Brown-out

Reset⁽²⁾

Timer0

MCLR VDD, VSS

A/D

Note 1: Higher order bits are from the STATUS register.

2: Brown-out Reset is not available on the PIC16C71.

DS30272A-page 8

1997 Microchip Technology Inc.

PIC16C71X

TABLE 3-1:

PIC16C710/71/711/715 PINOUT DESCRIPTION

SSOP

DIP

Pin#

SOIC I/O/P

Buffer

Type

Pin Name

Description

(4)

Pin#

Type

Pin#

(3)

OSC1/CLKIN

16

18

17

16

15

I

Oscillator crystal input/external clock source input.

ST/CMOS

—

OSC2/CLKOUT 15

O

Oscillator crystal output. Connects to crystal or resonator in crystal

oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has

1/4 the frequency of OSC1, and denotes the instruction cycle rate.

4

I/P

ST

Master clear (reset) input or programming voltage input. This pin is

an active low reset to the device.

MCLR/VPP

PORTA is a bi-directional I/O port.

RA0 can also be analog input0

RA0/AN0

17

18

1

19

20

1

17

18

1

I/O

TTL

ST

RA1/AN1

RA1 can also be analog input1

RA2/AN2

RA2 can also be analog input2

RA3/AN3/VREF

RA4/T0CKI

2

RA3 can also be analog input3 or analog reference voltage

3

RA4 can also be the clock input to the Timer0 module. Output is

open drain type.

PORTB is a bi-directional I/O port. PORTB can be software pro-

grammed for internal weak pull-up on all inputs.

(1)

RB0/INT

6

7

8

6

7

I/O

P

TTL/ST

TTL

RB0 can also be the external interrupt pin.

RB1

RB2

8

9

8

TTL

RB3

9

10

11

12

13

14

4, 6

9

TTL

RB4

10

11

12

13

5

10

11

12

13

5

TTL

Interrupt on change pin.

RB5

TTL

Interrupt on change pin.

(2)

RB6

TTL/ST

—

Interrupt on change pin. Serial programming clock.

Interrupt on change pin. Serial programming data.

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

(2)

RB7

VSS

VDD

14 15, 16

O = output

— = Not used

14

P

—

Legend: I = input

I/O = input/output

TTL = TTL input

P = power

ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

3: This buffer is a Schmitt Trigger input when conﬁgured in RC oscillator mode and a CMOS input otherwise.

4: The PIC16C71 is not available in SSOP package.

1997 Microchip Technology Inc.

DS30272A-page 9

PIC16C71X

3.1

Clocking Scheme/Instruction Cycle

3.2

Instruction Flow/Pipelining

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, the pro-

gram counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clocks and instruction execution ﬂow

is shown in Figure 3-2.

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g. GOTO) then

two cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register” (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Internal

phase

clock

Q4

PC

PC+1

PC+2

OSC2/CLKOUT

(RC mode)

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Tcy0

Tcy1

Tcy2

Tcy3

Tcy4

Tcy5

1. MOVLW 55h

2. MOVWF PORTB

3. CALL SUB_1

Fetch 1

Execute 1

Fetch 2

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF PORTA, BIT3 (Forced NOP)

5. Instruction @ address SUB_1

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

DS30272A-page 10

1997 Microchip Technology Inc.

PIC16C71X

FIGURE 4-2: PIC16C71/711 PROGRAM

MEMORY MAP AND STACK

4.0

MEMORY ORGANIZATION

4.1

Program Memory Organization

PC<12:0>

The PIC16C71X family has a 13-bit program counter

capable of addressing an 8K x 14 program memory

space. The amount of program memory available to

each device is listed below:

CALL, RETURN

RETFIE, RETLW

13

Stack Level 1

Stack Level 8

Program

Memory

Device

Address Range

PIC16C710

PIC16C71

PIC16C711

PIC16C715

512 x 14

1K x 14

2K x 14

0000h-01FFh

0000h-03FFh

0000h-07FFh

Reset Vector

0000h

For those devices with less than 8K program memory,

accessing a location above the physically implemented

address will cause a wraparound.

Interrupt Vector

0004h

0005h

On-chip Program

Memory

The reset vector is at 0000h and the interrupt vector is

at 0004h.

03FFh

0400h

FIGURE 4-1: PIC16C710 PROGRAM

MEMORY MAP AND STACK

PC<12:0>

1FFFh

CALL, RETURN

RETFIE, RETLW

13

FIGURE 4-3: PIC16C715 PROGRAM

MEMORY MAP AND STACK

Stack Level 1

Stack Level 8

PC<12:0>

CALL, RETURN

RETFIE, RETLW

13

Stack Level 1

Stack Level 8

Reset Vector

0000h

Interrupt Vector

0004h

0005h

On-chip Program

Memory

Reset Vector

0000h

01FFh

0200h

Interrupt Vector

0004h

0005h

1FFFh

On-chip Program

Memory

07FFh

0800h

1FFFh

1997 Microchip Technology Inc.

DS30272A-page 11

PIC16C71X

4.2

Data Memory Organization

FIGURE 4-4: PIC16C710/71 REGISTER FILE

MAP

The data memory is partitioned into two Banks which

contain the General Purpose Registers and the Special

Function Registers. Bit RP0 is the bank select bit.

File

Address

File

Address

RP0 (STATUS<5>) = 1 → Bank 1

RP0 (STATUS<5>) = 0 → Bank 0

(1)

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

INDF

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

TMR0

PCL

OPTION

PCL

Each Bank extends up to 7Fh (128 bytes). The lower

locations of each Bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers implemented as

static RAM. Both Bank 0 and Bank 1 contain special

function registers. Some "high use" special function

registers from Bank 0 are mirrored in Bank 1 for code

reduction and quicker access.

STATUS

FSR

STATUS

FSR

PORTA

PORTB

TRISA

TRISB

(2)

PCON

ADCON0

ADRES

ADCON1

ADRES

4.2.1

GENERAL PURPOSE REGISTER FILE

PCLATH

INTCON

PCLATH

INTCON

The register ﬁle can be accessed either directly, or indi-

rectly through the File Select Register FSR

(Section 4.5).

General

Purpose

Register

General

Purpose

Register

Mapped

(3)

in Bank 0

AFh

B0h

2Fh

30h

FFh

7Fh

Bank 0

Bank 1

Unimplemented data memory locations, read

as '0'.

Note 1: Not a physical register.

2: The PCON register is not implemented on the

PIC16C71.

3: These locations are unimplemented in Bank 1.

Any access to these locations will access the

corresponding Bank 0 register.

DS30272A-page 12

1997 Microchip Technology Inc.

PIC16C71X

FIGURE 4-5: PIC16C711 REGISTER FILE

MAP

FIGURE 4-6: PIC16C715 REGISTER FILE

MAP

File

Address

(1)

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

INDF

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

(1)

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

INDF

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

TMR0

PCL

OPTION

PCL

TMR0

PCL

OPTION

PCL

STATUS

FSR

STATUS

FSR

STATUS

FSR

STATUS

FSR

PORTA

PORTB

TRISA

TRISB

PORTA

PORTB

TRISA

TRISB

PCON

ADCON1

ADCON0

ADRES

PCLATH

INTCON

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCLATH

INTCON

General

Purpose

Register

PCON

General

Purpose

Register

Mapped

(2)

in Bank 0

CFh

D0h

4Fh

50h

FFh

7Fh

Bank 0

Bank 1

ADRES

Unimplemented data memory locations, read

as '0'.

ADCON0

ADCON1

Note 1: Not a physical register.

A0h

General

Purpose

Register

General

Purpose

Register

2: These locations are unimplemented in Bank 1.

Any access to these locations will access the

corresponding Bank 0 register.

BFh

C0h

FFh

7Fh

Bank 0

Bank 1

Unimplemented data memory locations, read

as '0'.

Note 1: Not a physical register.

1997 Microchip Technology Inc.

DS30272A-page 13

PIC16C71X

4.2.2

SPECIAL FUNCTION REGISTERS

The special function registers can be classiﬁed into two

sets (core and peripheral). Those registers associated

with the “core” functions are described in this section,

and those related to the operation of the peripheral fea-

tures are described in the section of that peripheral

feature.

The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the

desired operation of the device. These registers are

implemented as static RAM.

TABLE 4-1:

PIC16C710/71/711 SPECIAL FUNCTION REGISTER SUMMARY

Value on: Value on all

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

BOR

other resets

(1)

Bank 0

00h⁽³⁾

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 module’s register

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

01h

TMR0

PCL

02h⁽³⁾

03h⁽³⁾

Program Counter's (PC) Least Signiﬁcant Byte

IRP⁽⁵⁾

RP1⁽⁵⁾

STATUS

RP0

Indirect data memory address pointer

PORTA Data Latch when written: PORTA pins when read

TO

PD

Z

DC

C

04h⁽³⁾

05h

FSR

xxxx xxxx uuuu uuuu

---x 0000 ---u 0000

xxxx xxxx uuuu uuuu

PORTA

PORTB

—

06h

PORTB Data Latch when written: PORTB pins when read

Unimplemented

07h

—

08h

ADCON0

ADRES

ADCS1

ADCS0

(6)

CHS1

CHS0

GO/DONE

ADIF

ADON

00-0 0000 00-0 0000

xxxx xxxx uuuu uuuu

09h⁽³⁾

A/D Result Register

0Ah^(2,3)

PCLATH

INTCON

—

Write Buffer for the upper 5 bits of the Program Counter

INTE RBIE T0IF INTF RBIF

---0 0000 ---0 0000

0000 000x 0000 000u

0Bh⁽³⁾

GIE

ADIE

T0IE

Bank 1

80h⁽³⁾

81h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000 0000 0000

1111 1111 1111 1111

0000 0000 0000 0000

0001 1xxx 000q quuu

OPTION

PCL

RBPU

Program Counter's (PC) Least Signiﬁcant Byte

RP0 TO

Indirect data memory address pointer

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

82h⁽³⁾

83h⁽³⁾

IRP⁽⁵⁾

RP1⁽⁵⁾

STATUS

PD

Z

DC

C

84h⁽³⁾

85h

FSR

xxxx xxxx uuuu uuuu

---1 1111 ---1 1111

1111 1111 1111 1111

---- --qq ---- --uu

---- --00 ---- --00

xxxx xxxx uuuu uuuu

TRISA

TRISB

PCON

ADCON1

ADRES

—

PORTA Data Direction Register

86h

PORTB Data Direction Control Register

87h⁽⁴⁾

88h

—

POR

BOR

PCFG1

PCFG0

89h⁽³⁾

A/D Result Register

8Ah^(2,3)

8Bh⁽³⁾

PCLATH

INTCON

—

Write Buffer for the upper 5 bits of the Program Counter

INTE RBIE T0IF INTF RBIF

---0 0000 ---0 0000

0000 000x 0000 000u

GIE

ADIE

T0IE

Legend: x= unknown, u= unchanged, q= value depends on condition, -= unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

3: These registers can be addressed from either bank.

4: The PCON register is not physically implemented in the PIC16C71, read as ’0’.

5: The IRP and RP1 bits are reserved on the PIC16C710/71/711, always maintain these bits clear.

6: Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is unimplemented,

read as '0'.

DS30272A-page 14

1997 Microchip Technology Inc.

PIC16C71X

TABLE 4-2:

PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY

Value on: Value on all

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

BOR, PER

other resets

(3)

Bank 0

00h⁽¹⁾

01h

INDF

TMR0

PCL

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 module’s register

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

---x 0000 ---u 0000

xxxx xxxx uuuu uuuu

02h⁽¹⁾

03h⁽¹⁾

04h⁽¹⁾

05h

Program Counter's (PC) Least Signiﬁcant Byte

STATUS

FSR

IRP⁽⁴⁾

Indirect data memory address pointer

PORTA Data Latch when written: PORTA pins when read

RP1⁽⁴⁾

RP0

TO

PD

Z

DC

C

PORTA

PORTB

—

06h

PORTB Data Latch when written: PORTB pins when read

07h

Unimplemented

—

08h

—

09h

—

0Ah^(1,2)PCLATH

—

GIE

—

T0IE

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

0000 000x 0000 000u

-0-- ---- -0-- ----

0Bh⁽¹⁾

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

INTCON

PEIE

ADIF

INTE

—

RBIE

—

T0IF

—

INTF

—

RBIF

—

PIR1

—

Unimplemented

A/D Result Register

—

ADRES

ADCON0

xxxx xxxx uuuu uuuu

0000 00-0 0000 00-0

ADCS1

ADCS0

CHS2

CHS1

CHS0

GO/DONE

—

ADON

Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear.

1997 Microchip Technology Inc.

DS30272A-page 15

PIC16C71X

TABLE 4-2:

Address Name

Bank 1

PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Value on: Value on all

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

other resets

(3)

BOR, PER

80h⁽¹⁾

81h

INDF

OPTION

PCL

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000 0000 0000

1111 1111 1111 1111

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

--11 1111 --11 1111

1111 1111 1111 1111

RBPU

Program Counter's (PC) Least Signiﬁcant Byte

IRP⁽⁴⁾RP1⁽⁴⁾

RP0 TO

Indirect data memory address pointer

PORTA Data Direction Register

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

82h⁽¹⁾

83h⁽¹⁾

84h⁽¹⁾

85h

STATUS

FSR

PD

Z

DC

C

TRISA

TRISB

—

86h

PORTB Data Direction Register

Unimplemented

87h

—

88h

—

Unimplemented

89h

—

Unimplemented

8Ah^(1,2)PCLATH

—

GIE

—

T0IE

—

Write Buffer for the upper 5 bits of the PC

---0 0000 ---0 0000

0000 000x 0000 000u

-0-- ---- -0-- ----

8Bh⁽¹⁾

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

INTCON

PEIE

ADIE

INTE

—

RBIE

—

T0IF

—

INTF

—

RBIF

—

PIE1

—

Unimplemented

MPEEN

—

PCON

—

PER

POR

BOR

u--- -1qq u--- -1uu

Unimplemented

—

ADCON1

—

PCFG1

PCFG0

---- --00 ---- --00

Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear.

DS30272A-page 16

1997 Microchip Technology Inc.

PIC16C71X

4.2.2.1

STATUS REGISTER

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register because these instructions do not

affect the Z, C or DC bits from the STATUS register. For

other instructions, not affecting any status bits, see the

"Instruction Set Summary."

Applicable Devices 710 71 711 715

The STATUS register, shown in Figure 4-7, contains

the arithmetic status of the ALU, the RESET status and

the bank select bits for data memory.

Note 1: For those devices that do not use bits IRP

and RP1 (STATUS<7:6>), maintain these

bits clear to ensure upward compatibility

with future products.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled.These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note 2: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in sub-

traction. See the SUBLW and SUBWF

instructions for examples.

For example, CLRF STATUSwill clear the upper-three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

FIGURE 4-7: STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0

IRP

R/W-0

RP1

R/W-0

RP0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

R = Readable bit

W = Writable bit

bit7

bit0

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11= Bank 3 (180h - 1FFh)

10= Bank 2 (100h - 17Fh)

01= Bank 1 (80h - FFh)

00= Bank 0 (00h - 7Fh)

Each bank is 128 bytes

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

TO: Time-out bit

1 = After power-up, CLRWDTinstruction, or SLEEPinstruction

0 = A WDT time-out occurred

PD: Power-down bit

1 = After power-up or by the CLRWDTinstruction

0 = By execution of the SLEEPinstruction

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)(for borrow the polarity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most signiﬁcant bit of the result occurred

0 = No carry-out from the most signiﬁcant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of

the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order

bit of the source register.

1997 Microchip Technology Inc.

DS30272A-page 17

PIC16C71X

4.2.2.2

OPTION REGISTER

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to

the Watchdog Timer by setting bit PSA

(OPTION<3>).

Applicable Devices 710 71 711 715

The OPTION register is a readable and writable regis-

ter which contains various control bits to conﬁgure the

TMR0/WDT prescaler, the External INT Interrupt,

TMR0, and the weak pull-ups on PORTB.

FIGURE 4-8: OPTION REGISTER (ADDRESS 81h, 181h)

R/W-1

RBPU

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

R

= Readable bit

W = Writable bit

bit7

bit0

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6:

bit 5:

bit 4:

bit 3:

INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

Bit Value

TMR0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

DS30272A-page 18

1997 Microchip Technology Inc.

PIC16C71X

4.2.2.3

INTCON REGISTER

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

Applicable Devices 710 71 711 715

The INTCON Register is a readable and writable regis-

ter which contains various enable and ﬂag bits for the

TMR0 register overﬂow, RB Port change and External

RB0/INT pin interrupts.

FIGURE 4-9: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0

GIE

R/W-0

ADIE

R/W-0

T0IE

R/W-0

INTE

R/W-0

RBIE

R/W-0

T0IF

R/W-0

INTF

R/W-x

RBIF

R

= Readable bit

W = Writable bit

bit7

bit0

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

(1)

bit 7:

GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit 6:

bit 5:

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

ADIE: A/D Converter Interrupt Enable bit

1 = Enables A/D interrupt

0 = Disables A/D interrupt

T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register has overﬂowed (must be cleared in software)

0 = TMR0 register did not overﬂow

INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

Note 1: For the PIC16C71, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may be uninten-

tionally re-enabled by the RETFIEinstruction in the user’s Interrupt Service Routine. Refer to Section 8.5

for a detailed description.

Interrupt ﬂag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to

enabling an interrupt.

1997 Microchip Technology Inc.

DS30272A-page 19

PIC16C71X

4.2.2.4

PIE1 REGISTER

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

Applicable Devices 710 71 711 715

This register contains the individual enable bits for the

Peripheral interrupts.

FIGURE 4-10: PIE1 REGISTER (ADDRESS 8Ch)

U-0

—

R/W-0

ADIE

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R

= Readable bit

W = Writable bit

bit7

bit0

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

Unimplemented: Read as '0'

bit 6:

ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

bit 5-0: Unimplemented: Read as '0'

DS30272A-page 20

1997 Microchip Technology Inc.

PIC16C71X

4.2.2.5

PIR1 REGISTER

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt ﬂag bits are clear prior to enabling an

interrupt.

Applicable Devices 710 71 711 715

This register contains the individual ﬂag bits for the

Peripheral interrupts.

FIGURE 4-11: PIR1 REGISTER (ADDRESS 0Ch)

U-0

—

R/W-0

ADIF

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R

= Readable bit

W = Writable bit

bit7

bit0

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

Unimplemented: Read as '0'

bit 6:

ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed

0 = The A/D conversion is not complete

bit 5-0: Unimplemented: Read as '0'

1997 Microchip Technology Inc.

DS30272A-page 21

PIC16C71X

4.2.2.6

PCON REGISTER

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked

on subsequent resets to see if BOR is

clear, indicating a brown-out has occurred.

The BOR status bit is a don't care and is

not necessarily predictable if the brown-out

circuit is disabled (by clearing the BODEN

bit in the Conﬁguration word).

Applicable Devices 710 71 711 715

The Power Control (PCON) register contains a ﬂag bit

to allow differentiation between a Power-on Reset

(POR) to an external MCLR Reset or WDT Reset.

Those devices with brown-out detection circuitry con-

tain an additional bit to differentiate a Brown-out Reset

(BOR) condition from a Power-on Reset condition. For

the PIC16C715 the PCON register also contains status

bits MPEEN and PER. MPEEN reﬂects the value of the

MPEEN bit in the conﬁguration word. PER indicates a

parity error reset has occurred.

FIGURE 4-12: PCON REGISTER (ADDRESS 8Eh), PIC16C710/711

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

POR

R/W-q

BOR

R

= Readable bit

W = Writable bit

bit7

bit0

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7-2: Unimplemented: Read as '0'

bit 1:

POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0:

BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

FIGURE 4-13: PCON REGISTER (ADDRESS 8Eh), PIC16C715

R-U

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

PER

R/W-0

POR

R/W-q

(1)

MPEEN

BOR

R

= Readable bit

W = Writable bit

bit7

bit0

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

MPEEN: Memory Parity Error Circuitry Status bit

Reﬂects the value of conﬁguration word bit, MPEEN

bit 6-3: Unimplemented: Read as '0'

bit 2:

bit 1:

bit 0:

PER: Memory Parity Error Reset Status bit

1 = No Error occurred

0 = Program Memory Fetch Parity Error occurred (must be set in software after a Parity Error Reset)

POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

DS30272A-page 22

1997 Microchip Technology Inc.

PIC16C71X

4.3.2

STACK

4.3

PCL and PCLATH

The program counter (PC) is 13-bits wide.The low byte

comes from the PCL register, which is a readable and

writable register. The upper bits (PC<12:8>) are not

readable, but are indirectly writable through the

PCLATH register. On any reset, the upper bits of the

PC will be cleared. Figure 4-14 shows the two situa-

tions for the loading of the PC. The upper example in

the ﬁgure shows how the PC is loaded on a write to

PCL (PCLATH<4:0> → PCH).The lower example in the

ﬁgure shows how the PC is loaded during a CALL or

GOTOinstruction (PCLATH<4:3> → PCH).

The PIC16CXX family has an 8 level deep x 13-bit wide

hardware stack. The stack space is not part of either

program or data space and the stack pointer is not

readable or writable.The PC is PUSHed onto the stack

when a CALL instruction is executed or an interrupt

causes a branch. The stack is POPed in the event of a

RETURN, RETLW or a RETFIE instruction execution.

PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer.This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the ﬁrst

push. The tenth push overwrites the second push (and

so on).

FIGURE 4-14: LOADING OF PC IN

DIFFERENT SITUATIONS

Note 1: There are no status bits to indicate stack

PCH

PCL

overﬂow or stack underﬂow conditions.

12

8

7

0

Instruction with

PCL as

Destination

Note 2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL,

RETURN, RETLW, and RETFIE instruc-

tions, or the vectoring to an interrupt

address.

PC

8

PCLATH<4:0>

PCLATH

5

ALU

PCH

12 11 10

PCL

4.4

Program Memory Paging

8

7

0

The PIC16C71X devices ignore both paging bits

(PCLATH<4:3>, which are used to access program

memory when more than one page is available. The

use of PCLATH<4:3> as general purpose read/write

bits for the PIC16C71X is not recommended since this

may affect upward compatibility with future products.

GOTO, CALL

PC

PCLATH<4:3>

PCLATH

11

2

Opcode <10:0>

4.3.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an off-

set to the program counter (ADDWF PCL).When doing a

table read using a computed GOTO method, care

should be exercised if the table location crosses a PCL

memory boundary (each 256 byte block). Refer to the

application note “Implementing a Table Read" (AN556).

1997 Microchip Technology Inc.

DS30272A-page 23

PIC16C71X

Example 4-1 shows the calling of a subroutine in

page 1 of the program memory.This example assumes

that PCLATH is saved and restored by the interrupt ser-

vice routine (if interrupts are used).

4.5

Indirect Addressing, INDF and FSR

Registers

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF reg-

ister. Any instruction using the INDF register actually

accesses the register pointed to by the File Select Reg-

ister, FSR. Reading the INDF register itself indirectly

(FSR = '0') will read 00h. Writing to the INDF register

indirectly results in a no-operation (although status bits

may be affected). An effective 9-bit address is obtained

by concatenating the 8-bit FSR register and the IRP bit

(STATUS<7>), as shown in Figure 4-15. However, IRP

is not used in the PIC16C71X devices.

EXAMPLE 4-1: CALL OF A SUBROUTINE IN

PAGE 1 FROM PAGE 0

ORG 0x500

BSF

BCF

PCLATH,3 ;Select page 1 (800h-FFFh)

PCLATH,4 ;Only on >4K devices

CALL

SUB1_P1

;Call subroutine in

;page 1 (800h-FFFh)

:

ORG 0x900

SUB1_P1:

;called subroutine

;page 1 (800h-FFFh)

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 4-2.

:

RETURN

;return to Call subroutine

;in page 0 (000h-7FFh)

EXAMPLE 4-2: INDIRECT ADDRESSING

movlw 0x20

movwf FSR

;initialize pointer

;to RAM

incf

INDF

;clear INDF register

FSR,F ;inc pointer

btfss FSR,4 ;all done?

goto

CONTINUE

:

;yes continue

FIGURE 4-15: DIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

(1)

from opcode

7

RP1:RP0

6

0

IRP

FSR register

bank select

location select

bank select

location select

00

01

80h

10

100h

11

00h

180h

Not

Used

Data

Memory

7Fh

FFh

17Fh

1FFh

Bank 0

Bank 1 Bank 2

Bank 3

For register ﬁle map detail see Figure 4-4.

Note 1:

The RP1 and IRP bits are reserved, always maintain these bits clear.

DS30272A-page 24

1997 Microchip Technology Inc.

PIC16C71X

FIGURE 5-1: BLOCK DIAGRAM OF

5.0

I/O PORTS

RA3:RA0 PINS

Applicable Devices 710 71 711 715

Data

bus

Some pins for these I/O ports are multiplexed with an

alternate function for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

D

Q

VDD

P

WR

Port

CK

5.1

PORTA and TRISA Registers

Data Latch

PORTA is a 5-bit latch.

I/O pin⁽¹⁾

N

D

Q

The RA4/T0CKI pin is a Schmitt Trigger input and an

open drain output. All other RA port pins have TTL

input levels and full CMOS output drivers. All pins have

data direction bits (TRIS registers) which can conﬁgure

these pins as output or input.

WR

TRIS

VSS

Analog

Q

CK

input

mode

TRIS Latch

Setting aTRISA register bit puts the corresponding out-

put driver in a hi-impedance mode. Clearing a bit in the

TRISA register puts the contents of the output latch on

the selected pin(s).

TTL

input

buffer

RD TRIS

Reading the PORTA register reads the status of the

pins whereas writing to it will write to the port latch. All

write operations are read-modify-write operations.

Therefore a write to a port implies that the port pins are

read, this value is modiﬁed, and then written to the port

data latch.

Q

D

EN

RD PORT

Pin RA4 is multiplexed with the Timer0 module clock

input to become the RA4/T0CKI pin.

To A/D Converter

Other PORTA pins are multiplexed with analog inputs

and analog VREF input. The operation of each pin is

selected by clearing/setting the control bits in the

ADCON1 register (A/D Control Register1).

Note 1: I/O pins have protection diodes to VDD and

VSS.

FIGURE 5-2: BLOCK DIAGRAM OF RA4/

T0CKI PIN

Note: On a Power-on Reset, these pins are con-

ﬁgured as analog inputs and read as '0'.

Data

bus

The TRISA register controls the direction of the RA

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

D

Q

WR

PORT

CK

I/O pin⁽¹⁾

N

Data Latch

EXAMPLE 5-1: INITIALIZING PORTA

D

Q

VSS

BCF

CLRF

STATUS, RP0

PORTA

;

WR

TRIS

; Initialize PORTA by

; clearing output

; data latches

Schmitt

Trigger

input

Q

CK

TRIS Latch

buffer

BSF

STATUS, RP0 ; Select Bank 1

MOVLW 0xCF

; Value used to

; initialize data

; direction

RD TRIS

MOVWF TRISA

; Set RA<3:0> as inputs

; RA<4> as outputs

; TRISA<7:5> are always

; read as '0'.

Q

D

EN

RD PORT

TMR0 clock input

Note 1: I/O pin has protection diodes to VSS only.

1997 Microchip Technology Inc.

DS30272A-page 25

PIC16C71X

TABLE 5-1:

Name

PORTA FUNCTIONS

Bit#

Buffer Function

RA0/AN0

bit0

bit1

bit2

bit3

bit4

TTL

ST

Input/output or analog input

RA1/AN1

Input/output or analog input

Input/output or analog input/VREF

RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

Input/output or external clock input for Timer0

Output is open drain type

Legend: TTL = TTL input, ST = Schmitt Trigger input

TABLE 5-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on:

POR,

BOR

Value on all

other resets

Address Name

Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

05h

85h

9Fh

PORTA

TRISA

—

RA4

RA3

RA2

RA1

RA0

---x 0000 ---u 0000

---1 1111 ---1 1111

PORTA Data Direction Register

ADCON1

—

PCFG1 PCFG0 ---- --00 ---- --00

Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by PORTA.

DS30272A-page 26

1997 Microchip Technology Inc.

PIC16C71X

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins conﬁgured as inputs can

cause this interrupt to occur (i.e. any RB7:RB4 pin con-

ﬁgured as an output is excluded from the interrupt on

change comparison). The input pins (of RB7:RB4) are

compared with the old value latched on the last read of

PORTB. The “mismatch” outputs of RB7:RB4 are

OR’ed together to generate the RB Port Change Inter-

rupt with ﬂag bit RBIF (INTCON<0>).

5.2

PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The corre-

sponding data direction register is TRISB. Setting a bit

in the TRISB register puts the corresponding output

driver in a hi-impedance input mode. Clearing a bit in

the TRISB register puts the contents of the output latch

on the selected pin(s).

EXAMPLE 5-2: INITIALIZING PORTB

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the inter-

rupt in the following manner:

BCF

CLRF

STATUS, RP0

PORTB

;

; Initialize PORTB by

; clearing output

; data latches

a) Any read or write of PORTB. This will end the

mismatch condition.

BSF

MOVLW 0xCF

STATUS, RP0 ; Select Bank 1

; Value used to

; initialize data

; direction

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

b) Clear ﬂag bit RBIF.

A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and

allow ﬂag bit RBIF to be cleared.

MOVWF TRISB

This interrupt on mismatch feature, together with soft-

ware conﬁgurable pull-ups on these four pins allow

easy interface to a keypad and make it possible for

wake-up on key-depression. Refer to the Embedded

Control Handbook, "Implementing Wake-Up on Key

Stroke" (AN552).

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

performed by clearing bit RBPU (OPTION<7>). The

weak pull-up is automatically turned off when the port

pin is conﬁgured as an output. The pull-ups are dis-

abled on a Power-on Reset.

Note: For the PIC16C71

FIGURE 5-3: BLOCK DIAGRAM OF

if a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then interrupt ﬂag bit

RBIF may not get set.

RB3:RB0 PINS

VDD

RBPU⁽²⁾

weak

P

pull-up

Data Latch

Data bus

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

D

Q

I/O

pin⁽¹⁾

WR Port

CK

TRIS Latch

D

Q

TTL

Input

Buffer

WR TRIS

CK

RD TRIS

RD Port

Q

D

EN

RB0/INT

Schmitt Trigger

Buffer

RD Port

Note 1: I/O pins have diode protection to VDD and VSS.

2: TRISB = ’1’ enables weak pull-up if

RBPU = ’0’ (OPTION<7>).

1997 Microchip Technology Inc.

DS30272A-page 27

PIC16C71X

FIGURE 5-4: BLOCK DIAGRAM OF

RB7:RB4 PINS

FIGURE 5-5: BLOCK DIAGRAM OF

RB7:RB4 PINS

(PIC16C71)

(PIC16C710/711/715)

VDD

RBPU⁽²⁾

weak

P

pull-up

Data Latch

Data bus

WR Port

Data bus

WR Port

D

Q

D

Q

I/O

pin⁽¹⁾

I/O

pin⁽¹⁾

CK

TRIS Latch

CK

TRIS Latch

D

Q

D

Q

WR TRIS

TTL

Input

Buffer

TTL

Input

Buffer

CK

ST

Buffer

ST

Buffer

RD TRIS

RD Port

RD TRIS

RD Port

Latch

Q

D

Q

D

EN

Q1

Set RBIF

From other

RB7:RB4 pins

Q

D

From other

RB7:RB4 pins

RD Port

Q3

EN

RD Port

RB7:RB6 in serial programming mode

Note 1: I/O pins have diode protection to VDD and VSS.

2: TRISB = ’1’ enables weak pull-up if

RBPU = ’0’ (OPTION<7>).

Note 1: I/O pins have diode protection to VDD and VSS.

2: TRISB = ’1’ enables weak pull-up if

RBPU = ’0’ (OPTION<7>).

TABLE 5-3:

PORTB FUNCTIONS

Name

Bit#

Buffer

Function

(1)

RB0/INT

bit0

TTL/ST

Input/output pin or external interrupt input. Internal software

programmable weak pull-up.

RB1

RB2

RB3

RB4

bit1

bit2

bit3

bit4

TTL

Input/output pin. Internal software programmable weak pull-up.

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up.

RB5

RB6

RB7

bit5

bit6

bit7

TTL

TTL/ST

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up.

(2)

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming clock.

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

DS30272A-page 28

1997 Microchip Technology Inc.

PIC16C71X

TABLE 5-4:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on:

Value on all

POR,

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3 Bit 2 Bit 1 Bit 0

other resets

BOR

06h, 106h

86h, 186h

81h, 181h

PORTB

TRISB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

PS1

RB0

PS0

xxxx xxxx

1111 1111

uuuu uuuu

1111 1111

PORTB Data Direction Register

RBPU INTEDG T0CS T0SE PSA

OPTION

PS2

Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.

1997 Microchip Technology Inc.

DS30272A-page 29

PIC16C71X

5.3

I/O Programming Considerations

EXAMPLE 5-3: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O

PORT

5.3.1

BI-DIRECTIONAL I/O PORTS

;Initial PORT settings: PORTB<7:4> Inputs

Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF

instructions, for example, read the register into the

CPU, execute the bit operation and write the result

back to the register. Caution must be used when these

instructions are applied to a port with both inputs and

outputs deﬁned. For example, a BSFoperation on bit5

of PORTB will cause all eight bits of PORTB to be read

into the CPU. Then the BSF operation takes place on

bit5 and PORTB is written to the output latches. If

another bit of PORTB is used as a bi-directional I/O pin

(e.g., bit0) and it is deﬁned as an input at this time, the

input signal present on the pin itself would be read into

the CPU and rewritten to the data latch of this particular

pin, overwriting the previous content. As long as the pin

stays in the input mode, no problem occurs. However,

if bit0 is switched to an output, the content of the data

latch may now be unknown.

;

PORTB<3:0> Outputs

;PORTB<7:6> have external pull-ups and are

;not connected to other circuitry

;

PORT latch PORT pins

---------- ---------

BCF PORTB, 7

BCF PORTB, 6

BSF STATUS, RP0

BCF TRISB, 7

BCF TRISB, 6

; 01pp pppp

; 10pp pppp

;

11pp pppp

; 10pp pppp

11pp pppp

10pp pppp

;

;Note that the user may have expected the

;pin values to be 00pp ppp. The 2nd BCF

;caused RB7 to be latched as the pin value

;(high).

A pin actively outputting a Low or High should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wired-and”).

The resulting high output currents may damage the

chip.

Reading the port register, reads the values of the port

pins. Writing to the port register writes the value to the

port latch. When using read-modify-write instructions

(ex. BCF, BSF, etc.) on a port, the value of the port pins

is read, the desired operation is done to this value, and

this value is then written to the port latch.

5.3.2

SUCCESSIVE OPERATIONS ON I/O PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle

(Figure 5-6). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should be

such to allow the pin voltage to stabilize (load depen-

dent) before the next instruction which causes that ﬁle

to be read into the CPU is executed. Otherwise, the

previous state of that pin may be read into the CPU

rather than the new state. When in doubt, it is better to

separate these instructions with a NOP or another

instruction not accessing this I/O port.

Example 5-3 shows the effect of two sequential read-

modify-write instructions on an I/O port.

FIGURE 5-6: SUCCESSIVE I/O OPERATION

Q4

Q1 Q2

Q4

Q3

Q1 Q2

PC

Q1 Q2

Note:

This example shows a write to PORTB

followed by a read from PORTB.

PC + 3

NOP

PC

Instruction

fetched

PC + 1

PC + 2

NOP

MOVWF PORTB MOVF PORTB,W

write to

PORTB

Note that:

data setup time = (0.25TCY - TPD)

RB7:RB0

where TCY = instruction cycle

TPD = propagation delay

Port pin

sampled here

TPD

Therefore, at higher clock frequencies,

a write followed by a read may be

problematic.

Instruction

executed

NOP

MOVWF PORTB

write to

MOVF PORTB,W

PORTB

DS30272A-page 30

1997 Microchip Technology Inc.

PIC16C71X

bit T0SE selects the rising edge. Restrictions on the

external clock input are discussed in detail in

Section 6.2.

6.0

TIMER0 MODULE

Applicable Devices 710 71 711 715

The Timer0 module timer/counter has the following fea-

tures:

The prescaler is mutually exclusively shared between

the Timer0 module and the Watchdog Timer. The pres-

caler assignment is controlled in software by control bit

PSA (OPTION<3>). Clearing bit PSA will assign the

prescaler to the Timer0 module. The prescaler is not

readable or writable.When the prescaler is assigned to

the Timer0 module, prescale values of 1:2, 1:4, ...,

1:256 are selectable. Section 6.3 details the operation

of the prescaler.

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overﬂow from FFh to 00h

• Edge select for external clock

Figure 6-1 is a simpliﬁed block diagram of the Timer0

module.

6.1

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overﬂows from FFh to 00h. This overﬂow sets bit

T0IF (INTCON<2>). The interrupt can be masked by

clearing bit T0IE (INTCON<5>). Bit T0IF must be

cleared in software by the Timer0 module interrupt ser-

vice routine before re-enabling this interrupt. The

TMR0 interrupt cannot awaken the processor from

SLEEP since the timer is shut off during SLEEP. See

Figure 6-4 for Timer0 interrupt timing.

Timer mode is selected by clearing bit T0CS

(OPTION<5>). In timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

the TMR0 register is written, the increment is inhibited

for the following two instruction cycles (Figure 6-2 and

Figure 6-3). The user can work around this by writing

an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS

(OPTION<5>). In counter mode, Timer0 will increment

either on every rising or falling edge of pin RA4/T0CKI.

The incrementing edge is determined by the Timer0

Source Edge Select bit T0SE (OPTION<4>). Clearing

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

Data bus

FOSC/4

0

1

PSout

8

1

0

Sync with

Internal

clocks

TMR0

Programmable

Prescaler

RA4/T0CKI

PSout

(2 cycle delay)

T0SE

3

Set interrupt

ﬂag bit T0IF

on overﬂow

PS2, PS1, PS0

PSA

T0CS

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).

2: The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed block diagram).

FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

Instruction

Fetch

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

MOVWF TMR0

T0

T0+1

T0+2

NT0

NT0+1

NT0+2

T0

TMR0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

1997 Microchip Technology Inc.

DS30272A-page 31

PIC16C71X

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

MOVWF TMR0

Instruction

Fetch

T0

T0+1

NT0+1

PC+6

NT0

TMR0

Instruction

Execute

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

Write TMR0

executed

FIGURE 6-4: TIMER0 INTERRUPT TIMING

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

OSC1

CLKOUT(3)

Timer0

FEh

FFh

00h

01h

02h

1

T0IF bit

(INTCON<2>)

GIE bit

(INTCON<7>)

INSTRUCTION

FLOW

PC

PC +1

0004h

0005h

Instruction

fetched

Inst (PC)

Inst (PC+1)

Inst (0004h)

Inst (0005h)

Instruction

executed

Inst (PC-1)

Dummy cycle

Inst (0004h)

Inst (PC)

Note 1: Interrupt ﬂag bit T0IF is sampled here (every Q1).

2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.

3: CLKOUT is available only in RC oscillator mode.

DS30272A-page 32

1997 Microchip Technology Inc.

PIC16C71X

caler so that the prescaler output is symmetrical. For

the external clock to meet the sampling requirement,

the ripple-counter must be taken into account. There-

fore, it is necessary for T0CKI to have a period of at

least 4Tosc (and a small RC delay of 40 ns) divided by

the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the mini-

mum pulse width requirement of 10 ns. Refer to param-

eters 40, 41 and 42 in the electrical speciﬁcation of the

desired device.

6.2

Using Timer0 with an External Clock

When an external clock input is used for Timer0, it must

meet certain requirements. The requirements ensure

the external clock can be synchronized with the internal

phase clock (TOSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.2.1

EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 6-5).

Therefore, it is necessary for T0CKI to be high for at

least 2Tosc (and a small RC delay of 20 ns) and low for

at least 2Tosc (and a small RC delay of 20 ns). Refer to

the electrical speciﬁcation of the desired device.

6.2.2

TMR0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0 mod-

ule is actually incremented. Figure 6-5 shows the delay

from the external clock edge to the timer incrementing.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple-counter type pres-

FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

misses sampling

External Clock Input or

(2)

Prescaler output

(1)

(3)

External Clock/Prescaler

Output after sampling

Increment Timer0 (Q4)

Timer0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.

2: External clock if no prescaler selected, Prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

1997 Microchip Technology Inc.

DS30272A-page 33

PIC16C71X

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,

6.3

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer, respectively (Figure 6-6). For simplicity, this

counter is being referred to as “prescaler” throughout

this data sheet. Note that there is only one prescaler

available which is mutually exclusively shared between

the Timer0 module and the Watchdog Timer. Thus, a

prescaler assignment for the Timer0 module means

that there is no prescaler for the Watchdog Timer, and

vice-versa.

BSF

1,x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer. The pres-

caler is not readable or writable.

Note: Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler

count, but will not change the prescaler

assignment.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine

the prescaler assignment and prescale ratio.

FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

Data Bus

8

CLKOUT (=Fosc/4)

M

U

X

1

0

1

M

U

X

RA4/T0CKI

SYNC

2

Cycles

TMR0 reg

T0SE

T0CS

Set ﬂag bit T0IF

on Overﬂow

PSA

0

1

8-bit Prescaler

M

U

X

Watchdog

Timer

8

8 - to - 1MUX

PS2:PS0

PSA

1

0

WDT Enable bit

M U X

PSA

WDT

Time-out

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).

DS30272A-page 34

1997 Microchip Technology Inc.

PIC16C71X

6.3.1

SWITCHING PRESCALER ASSIGNMENT

Note: To avoid an unintended device RESET, the

following instruction sequence (shown in

Example 6-1) must be executed when

changing the prescaler assignment from

Timer0 to the WDT.This sequence must be

followed even if the WDT is disabled.

The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the ﬂy” during program

execution.

EXAMPLE 6-1: CHANGING PRESCALER (TIMER0→WDT)

BCF

STATUS, RP0 ;Bank 0

CLRF

BSF

TMR0

;Clear TMR0 & Prescaler

STATUS, RP0 ;Bank 1

CLRWDT

;Clears WDT

MOVLW b'xxxx1xxx' ;Selects new prescale value

MOVWF OPTION_REG ;and assigns the prescaler to the WDT

STATUS, RP0 ;Bank 0

BCF

To change prescaler from the WDT to the Timer0

module use the sequence shown in Example 6-2.

EXAMPLE 6-2: CHANGING PRESCALER (WDT→TIMER0)

CLRWDT

BSF

;Clear WDT and prescaler

STATUS, RP0 ;Bank 1

MOVLW

MOVWF

BCF

b'xxxx0xxx' ;Select TMR0, new prescale value and

OPTION_REG ;clock source

STATUS, RP0 ;Bank 0

TABLE 6-1:

REGISTERS ASSOCIATED WITH TIMER0

Value on:

POR,

BOR

Value on all

other resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h

TMR0

INTCON GIE

OPTION RBPU INTEDG

TRISA

Timer0 module’s register

xxxx xxxx uuuu uuuu

RBIF 0000 000x 0000 000u

0Bh,8Bh,

81h

ADIE

T0IE

T0CS

—

INTE

T0SE

RBIE

PSA

T0IF

PS2

INTF

PS1

PS0

1111 1111 1111 1111

---1 1111 ---1 1111

85h

—

PORTA Data Direction Register

Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.

1997 Microchip Technology Inc.

DS30272A-page 35

PIC16C71X

NOTES:

DS30272A-page 36

1997 Microchip Technology Inc.

PIC16C71X

The A/D converter has a unique feature of being able

to operate while the device is in SLEEP mode.To oper-

ate in sleep, the A/D conversion clock must be derived

from the A/D’s internal RC oscillator.

7.0

ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

Applicable Devices 710 71 711 715

The A/D module has three registers. These registers

are:

The analog-to-digital (A/D) converter module has four

analog inputs.

• A/D Result Register (ADRES)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

The A/D allows conversion of an analog input signal to

a corresponding 8-bit digital number (refer to Applica-

tion Note AN546 for use of A/D Converter). The output

of the sample and hold is the input into the converter,

which generates the result via successive approxima-

tion. The analog reference voltage is software select-

able to either the device’s positive supply voltage (VDD)

or the voltage level on the RA3/AN3/VREF pin.

The ADCON0 register, shown in Figure 7-1 and

Figure 7-2, controls the operation of the A/D module.

The ADCON1 register, shown in Figure 7-3 conﬁgures

the functions of the port pins.The port pins can be con-

ﬁgured as analog inputs (RA3 can also be a voltage ref-

erence) or as digital I/O.

FIGURE 7-1: ADCON0 REGISTER (ADDRESS 08h), PIC16C710/71/711

R/W-0 R/W-0

ADCS1 ADCS0

U-0

R/W-0

CHS1

R/W-0

ADIF

R/W-0

ADON

(1)

CHS0 GO/DONE

R =Readable bit

W = Writable bit

U =Unimplemented

bit, read as ‘0’

—

bit7

bit0

- n =Value at POR reset

bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits

00= FOSC/2

01= FOSC/8

10= FOSC/32

11= FRC (clock derived from an RC oscillation)

bit 5:

Unimplemented: Read as '0'.

bit 4-3: CHS1:CHS0: Analog Channel Select bits

00= channel 0, (RA0/AN0)

01= channel 1, (RA1/AN1)

10= channel 2, (RA2/AN2)

11= channel 3, (RA3/AN3)

bit 2:

GO/DONE: A/D Conversion Status bit

If ADON = 1:

1 = A/D conversion in progress (setting this bit starts the A/D conversion)

0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver-

sion is complete)

bit 1:

bit 0:

ADIF: A/D Conversion Complete Interrupt Flag bit

1 = conversion is complete (must be cleared in software)

0 = conversion is not complete

ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter module is shutoff and consumes no operating current

Note 1: Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is

unimplemented, read as '0'.

1997 Microchip Technology Inc.

DS30272A-page 37

PIC16C71X

FIGURE 7-2: ADCON0 REGISTER (ADDRESS 1Fh), PIC16C715

R/W-0 R/W-0 R/W-0

R/W-0

CHS1

R/W-0

U-0

—

R/W-0

ADON

ADCS1 ADCS0

bit7

—

CHS0 GO/DONE

R =Readable bit

W = Writable bit

U =Unimplemented bit,

read as ‘0’

bit0

- n = Value at POR reset

bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits

00= FOSC/2

01= FOSC/8

10= FOSC/32

11= FRC (clock derived from an RC oscillation)

bit 5:

Unused

bit 6-3: CHS1:CHS0: Analog Channel Select bits

000= channel 0, (RA0/AN0)

001= channel 1, (RA1/AN1)

010= channel 2, (RA2/AN2)

011= channel 3, (RA3/AN3)

100= channel 0, (RA0/AN0)

101= channel 1, (RA1/AN1)

110= channel 2, (RA2/AN2)

111= channel 3, (RA3/AN3)

bit 2:

GO/DONE: A/D Conversion Status bit

If ADON = 1

1 = A/D conversion in progress (setting this bit starts the A/D conversion)

0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver-

sion is complete)

bit 1:

bit 0:

Unimplemented: Read as '0'

ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter module is shutoff and consumes no operating current

FIGURE 7-3: ADCON1 REGISTER, PIC16C710/71/711 (ADDRESS 88h),

PIC16C715 (ADDRESS 9Fh)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

PCFG1

PCFG0

R =Readable bit

W = Writable bit

bit7

bit0

U =Unimplemented

bit, read as ‘0’

- n =Value at POR reset

bit 7-2: Unimplemented: Read as '0'

bit 1-0: PCFG1:PCFG0: A/D Port Conﬁguration Control bits

PCFG1:PCFG0 RA1 & RA0

RA2

RA3

VREF

00

01

10

11

A

D

A

D

A

VDD

RA3

VDD

VREF

D

A = Analog input

D = Digital I/O

DS30272A-page 38

1997 Microchip Technology Inc.

PIC16C71X

The ADRES register contains the result of the A/D con-

version. When the A/D conversion is complete, the

result is loaded into the ADRES register, the GO/DONE

bit (ADCON0<2>) is cleared, and A/D interrupt ﬂag bit

ADIF is set. The block diagram of the A/D module is

shown in Figure 7-4.

2. Conﬁgure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time.

4. Start conversion:

After the A/D module has been conﬁgured as desired,

the selected channel must be acquired before the con-

version is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 7.1.

After this acquisition time has elapsed the A/D conver-

sion can be started. The following steps should be fol-

lowed for doing an A/D conversion:

• Set GO/DONE bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

OR

• Waiting for the A/D interrupt

6. Read A/D Result register (ADRES), clear bit

ADIF if required.

1. Conﬁgure the A/D module:

7. For next conversion, go to step 1 or step 2 as

required. The A/D conversion time per bit is

deﬁned as TAD. A minimum wait of 2TAD is

required before next acquisition starts.

• Conﬁgure analog pins / voltage reference /

and digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

FIGURE 7-4: A/D BLOCK DIAGRAM

CHS1:CHS0

11

RA3/AN3/VREF

VIN

10

(Input voltage)

RA2/AN2

01

A/D

Converter

RA1/AN1

00

RA0/AN0

VDD

00or

10or

11

VREF

(Reference

voltage)

01

PCFG1:PCFG0

1997 Microchip Technology Inc.

DS30272A-page 39

PIC16C71X

7.1

A/D Acquisition Requirements

Note 1: The reference voltage (VREF) has no

effect on the equation, since it cancels

itself out.

For the A/D converter to meet its speciﬁed accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 7-5. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD),

Figure 7-5. The source impedance affects the offset

voltage at the analog input (due to pin leakage current).

The maximum recommended impedance for ana-

log sources is 10 kΩ. After the analog input channel is

selected (changed) this acquisition must be done

before the conversion can be started.

Note 2: The charge holding capacitor (CHOLD) is

not discharged after each conversion.

Note 3: The maximum recommended impedance

for analog sources is 10 kΩ. This is

required to meet the pin leakage speciﬁ-

cation.

Note 4: After a conversion has completed, a

2.0TAD delay must complete before acqui-

sition can begin again. During this time the

holding capacitor is not connected to the

selected A/D input channel.

To calculate the minimum acquisition time, Equation 7-

1 may be used.This equation calculates the acquisition

time to within 1/2 LSb error is used (512 steps for the

A/D). The 1/2 LSb error is the maximum error allowed

for the A/D to meet its speciﬁed accuracy.

EXAMPLE 7-1: CALCULATING THE

MINIMUM REQUIRED

AQUISITION TIME

TACQ = Ampliﬁer Settling Time +

Holding Capacitor Charging Time +

Temperature Coefﬁcient

EQUATION 7-1:

A/D MINIMUM CHARGING

TIME

(-TCAP/CHOLD(RIC + RSS + RS))

TACQ = 5 µs + TCAP + [(Temp - 25°C)(0.05 µs/°C)]

TCAP = -CHOLD (RIC + RSS + RS) ln(1/511)

-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)

-51.2 pF (18 kΩ) ln(0.0020)

VHOLD = (VREF - (VREF/512)) • (1 - e

)

Given: VHOLD = (VREF/512), for 1/2 LSb resolution

The above equation reduces to:

TCAP = -(51.2 pF)(1 kΩ + RSS + RS) ln(1/511)

Example 7-1 shows the calculation of the minimum

required acquisition time TACQ. This calculation is

based on the following system assumptions.

-0.921 µs (-6.2364)

5.747 µs

TACQ = 5 µs + 5.747 µs + [(50°C - 25°C)(0.05 µs/°C)]

10.747 µs + 1.25 µs

CHOLD = 51.2 pF

Rs = 10 kΩ

11.997 µs

1/2 LSb error

VDD = 5V → Rss = 7 kΩ

Temp (application system max.) = 50°C

VHOLD = 0 @ t = 0

FIGURE 7-5: ANALOG INPUT MODEL

VDD

Sampling

Switch

VT = 0.6V

ANx

SS

RIC ≤ 1k

RSS

Rs

CHOLD

= DAC capacitance

= 51.2 pF

CPIN

5 pF

VA

I leakage

± 500 nA

VT = 0.6V

VSS

Legend CPIN

VT

= input capacitance

= threshold voltage

6V

5V

I leakage = leakage current at the pin due to

various junctions

VDD 4V

3V

2V

RIC

SS

= interconnect resistance

= sampling switch

CHOLD

= sample/hold capacitance (from DAC)

5 6 7 8 9 10 11

Sampling Switch

( kΩ )

DS30272A-page 40

1997 Microchip Technology Inc.

PIC16C71X

7.2

Selecting the A/D Conversion Clock

7.3

Configuring Analog Port Pins

The A/D conversion time per bit is deﬁned as TAD. The

A/D conversion requires 9.5TAD per 8-bit conversion.

The source of the A/D conversion clock is software

selectable. The four possible options for TAD are:

The ADCON1 and TRISA registers control the opera-

tion of the A/D port pins. The port pins that are desired

as analog inputs must have their corresponding TRIS

bits set (input). If the TRIS bit is cleared (output), the

digital output level (VOH or VOL) will be converted.

• 2TOSC

The A/D operation is independent of the state of the

CHS2:CHS0 bits and the TRIS bits.

• 8TOSC

• 32TOSC

• Internal RC oscillator

Note 1: When reading the port register, all pins

conﬁgured as analog input channels will

read as cleared (a low level). Pins conﬁg-

ured as digital inputs, will convert an ana-

log input. Analog levels on a digitally

conﬁgured input will not affect the conver-

sion accuracy.

For correct A/D conversions, the A/D conversion clock

(TAD) must be selected to ensure a minimum TAD time

of:

2.0 µs for the PIC16C71

1.6 µs for all other PIC16C71X devices

Note 2: Analog levels on any pin that is deﬁned as

a digital input (including the AN7:AN0

pins), may cause the input buffer to con-

sume current that is out of the devices

speciﬁcation.

Table 7-1 and Table 7-2 and show the resultant TAD

times derived from the device operating frequencies

and the A/D clock source selected.

TABLE 7-1:

TAD vs. DEVICE OPERATING FREQUENCIES, PIC16C71

AD Clock Source (TAD)

Device Frequency

Operation

2TOSC

ADCS1:ADCS0

20 MHz

16 MHz

4 MHz

1 MHz

2.0 µs

8.0 µs

333.33 kHz

(2)

00

01

10

11

6 µs

100 ns

125 ns

500 ns

(2)

(3)

8TOSC

2.0 µs

400 ns

500 ns

24 µs

(2)

(3)

32TOSC

2.0 µs

8.0 µs

1.6 µs

32.0 µs

2 - 6 µs

96 µs

(5)

(1,4)

(1)

RC

2 - 6 µs

Legend: Shaded cells are outside of recommended range.

Note 1: The RC source has a typical TAD time of 4 µs.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for

sleep operation only.

5: For extended voltage devices (LC), please refer to Electrical Speciﬁcations section.

TABLE 7-2:

TAD vs. DEVICE OPERATING FREQUENCIES, PIC16C710/711, PIC16C715

Device Frequency

5 MHz 1.25 MHz

AD Clock Source (TAD)

Operation

2TOSC

ADCS1:ADCS0

20 MHz

333.33 kHz

(2)

00

01

10

11

1.6 µs

6.4 µs

6 µs

100 ns

400 ns

(2)

(3)

8TOSC

1.6 µs

400 ns

24 µs

(3)

32TOSC

1.6 µs

6.4 µs

25.6 µs

96 µs

(5)

(1,4)

(1)

RC

2 - 6 µs

Legend: Shaded cells are outside of recommended range.

Note 1: The RC source has a typical TAD time of 4 µs.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for

sleep operation only.

5: For extended voltage devices (LC), please refer to Electrical Speciﬁcations section.

1997 Microchip Technology Inc.

DS30272A-page 41

PIC16C71X

7.4

A/D Conversions

Note: The GO/DONE bit should NOT be set in

Example 7-2 shows how to perform an A/D conversion.

The RA pins are conﬁgured as analog inputs.The ana-

log reference (VREF) is the device VDD. The A/D inter-

rupt is enabled, and the A/D conversion clock is FRC.

The conversion is performed on the RA0 pin (channel

0).

the same instruction that turns on the A/D.

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The ADRES register will

NOT be updated with the partially completed A/D con-

version sample. That is, the ADRES register will con-

tinue to contain the value of the last completed

conversion (or the last value written to the ADRES reg-

ister). After the A/D conversion is aborted, a 2TAD wait

is required before the next acquisition is started. After

this 2TAD wait, an acquisition is automatically started

on the selected channel.

EXAMPLE 7-2: A/D CONVERSION

BSF

CLRF

BCF

MOVLW

MOVWF

BSF

STATUS, RP0

ADCON1

STATUS, RP0

0xC1

ADCON0

INTCON, ADIE

INTCON, GIE

; Select Bank 1

; Configure A/D inputs

; Select Bank 0

; RC Clock, A/D is on, Channel 0 is selected

;

; Enable A/D Interrupt

; Enable all interrupts

BSF

;

Ensure that the required sampling time for the selected input channel has elapsed.

Then the conversion may be started.

BSF

:

ADCON0, GO

; Start A/D Conversion

; The ADIF bit will be set and the GO/DONE bit

:

;

is cleared upon completion of the A/D Conversion.

DS30272A-page 42

1997 Microchip Technology Inc.

PIC16C71X

7.4.1

FASTER CONVERSION - LOWER

RESOLUTION TRADE-OFF

Since the TAD is based from the device oscillator, the

user must use some method (a timer, software loop,

etc.) to determine when the A/D oscillator may be

changed. Example 7-3 shows a comparison of time

required for a conversion with 4-bits of resolution, ver-

sus the 8-bit resolution conversion. The example is for

devices operating at 20 MHz and 16 MHz (The A/D

clock is programmed for 32TOSC), and assumes that

immediately after 6TAD, the A/D clock is programmed

for 2TOSC.

Not all applications require a result with 8-bits of reso-

lution, but may instead require a faster conversion time.

The A/D module allows users to make the trade-off of

conversion speed to resolution. Regardless of the res-

olution required, the acquisition time is the same. To

speed up the conversion, the clock source of the A/D

module may be switched so that the TAD time violates

the minimum speciﬁed time (see the applicable electri-

cal speciﬁcation). Once the TAD time violates the mini-

mum speciﬁed time, all the following A/D result bits are

not valid (see A/D Conversion Timing in the Electrical

Speciﬁcations section.) The clock sources may only be

switched between the three oscillator versions (cannot

be switched from/to RC). The equation to determine

the time before the oscillator can be switched is as

follows:

The 2TOSC violates the minimum TAD time since the

last 4-bits will not be converted to correct values.

Conversion time = 2TAD + N • TAD + (8 - N)(2TOSC)

Where: N = number of bits of resolution required.

EXAMPLE 7-3: 4-BIT vs. 8-BIT CONVERSION TIMES

Resolution

(1)

Freq. (MHz)

4-bit

8-bit

TAD

20

16

20

16

20

16

1.6 µs

2.0 µs

50 ns

1.6 µs

2.0 µs

50 ns

TOSC

62.5 ns

10 µs

62.5 ns

16 µs

2TAD + N • TAD + (8 - N)(2TOSC)

12.5 µs

20 µs

Note 1: The PIC16C71 has a minimum TAD time of 2.0 µs.

All other PIC16C71X devices have a minimum TAD time of 1.6 µs.

1997 Microchip Technology Inc.

DS30272A-page 43

PIC16C71X

full scale error is that full scale does not take offset error

into account. Gain error can be calibrated out in soft-

ware.

7.5

A/D Operation During Sleep

The A/D module can operate during SLEEP mode.This

requires that the A/D clock source be set to RC

(ADCS1:ADCS0 = 11). When the RC clock source is

selected, the A/D module waits one instruction cycle

before starting the conversion. This allows the SLEEP

instruction to be executed, which eliminates all digital

switching noise from the conversion. When the conver-

sion is completed the GO/DONE bit will be cleared, and

the result loaded into the ADRES register. If the A/D

interrupt is enabled, the device will wake-up from

SLEEP. If the A/D interrupt is not enabled, the A/D mod-

ule will then be turned off, although the ADON bit will

remain set.

Linearity error refers to the uniformity of the code

changes. Linearity errors cannot be calibrated out of

the system. Integral non-linearity error measures the

actual code transition versus the ideal code transition

adjusted by the gain error for each code.

Differential non-linearity measures the maximum

actual code width versus the ideal code width. This

measure is unadjusted.

In systems where the device frequency is low, use of

the A/D RC clock is preferred. At moderate to high fre-

quencies, TAD should be derived from the device oscil-

lator. TAD must not violate the minimum and should be

≤ 8 µs for preferred operation. This is because TAD,

when derived from TOSC, is kept away from on-chip

phase clock transitions.This reduces, to a large extent,

the effects of digital switching noise.This is not possible

with the RC derived clock. The loss of accuracy due to

digital switching noise can be signiﬁcant if many I/O

pins are active.

When the A/D clock source is another clock option (not

RC), a SLEEPinstruction will cause the present conver-

sion to be aborted and the A/D module to be turned off,

though the ADON bit will remain set.

Turning off the A/D places the A/D module in its lowest

current consumption state.

Note: For the A/D module to operate in SLEEP,

the A/D clock source must be set to RC

(ADCS1:ADCS0 = 11). To perform an A/D

conversion in SLEEP, ensure the SLEEP

instruction immediately follows the instruc-

tion that sets the GO/DONE bit.

In systems where the device will enter SLEEP mode

after the start of the A/D conversion, the RC clock

source selection is required. In this mode, the digital

noise from the modules in SLEEP are stopped. This

method gives high accuracy.

7.6

A/D Accuracy/Error

7.7

Effects of a RESET

The absolute accuracy speciﬁed for the A/D converter

includes the sum of all contributions for quantization

error, integral error, differential error, full scale error, off-

set error, and monotonicity. It is deﬁned as the maxi-

mum deviation from an actual transition versus an ideal

transition for any code. The absolute error of the A/D

converter is speciﬁed at < ±1 LSb for VDD = VREF (over

the device’s speciﬁed operating range). However, the

accuracy of the A/D converter will degrade as VDD

diverges from VREF.

A device reset forces all registers to their reset state.

This forces the A/D module to be turned off, and any

conversion is aborted.

The value that is in the ADRES register is not modiﬁed

for a Power-on Reset. The ADRES register will contain

unknown data after a Power-on Reset.

7.8

Connection Considerations

If the input voltage exceeds the rail values (VSS or VDD)

by greater than 0.2V, then the accuracy of the conver-

sion is out of speciﬁcation.

For a given range of analog inputs, the output digital

code will be the same.This is due to the quantization of

the analog input to a digital code. Quantization error is

typically ± 1/2 LSb and is inherent in the analog to dig-

ital conversion process.The only way to reduce quanti-

zation error is to increase the resolution of the A/D

converter.

Note: Care must be taken when using the RA0

pin in A/D conversions due to its proximity

to the OSC1 pin.

An external RC ﬁlter is sometimes added for anti-alias-

ing of the input signal. The R component should be

selected to ensure that the total source impedance is

kept under the 10 kΩ recommended speciﬁcation. Any

external components connected (via hi-impedance) to

an analog input pin (capacitor, zener diode, etc.) should

have very little leakage current at the pin.

Offset error measures the ﬁrst actual transition of a

code versus the ﬁrst ideal transition of a code. Offset

error shifts the entire transfer function. Offset error can

be calibrated out of a system or introduced into a sys-

tem through the interaction of the total leakage current

and source impedance at the analog input.

Gain error measures the maximum deviation of the last

actual transition and the last ideal transition adjusted

for offset error.This error appears as a change in slope

of the transfer function. The difference in gain error to

DS30272A-page 44

1997 Microchip Technology Inc.

PIC16C71X

7.9

Transfer Function

FIGURE 7-6: A/D TRANSFER FUNCTION

The ideal transfer function of the A/D converter is as fol-

lows: the ﬁrst transition occurs when the analog input

voltage (VAIN) is Analog VREF/256 (Figure 7-6).

7.10

References

FFh

FEh

A very good reference for understanding A/D convert-

ers is the "Analog-Digital Conversion Handbook" third

edition, published by Prentice Hall (ISBN 0-13-03-

2848-0).

04h

03h

02h

01h

00h

Analog input voltage

FIGURE 7-7: FLOWCHART OF A/D OPERATION

ADON = 0

Yes

ADON = 0?

No

Acquire

Selected Channel

Yes

GO = 0?

No

Yes

Start of A/D

Conversion Delayed

1 Instruction Cycle

Finish Conversion

SLEEP

Instruction?

A/D Clock

= RC?

GO = 0

ADIF = 1

No

Yes

Abort Conversion

GO = 0

Wake-up

From Sleep?

Finish Conversion

Device in

SLEEP?

Wait 2 TAD

GO = 0

ADIF = 1

ADIF = 0

No

SLEEP

Power-down A/D

Finish Conversion

Stay in Sleep

Power-down A/D

Wait 2 TAD

GO = 0

ADIF = 1

Wait 2 TAD

1997 Microchip Technology Inc.

DS30272A-page 45

PIC16C71X

TABLE 7-3:

REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C710/71/711

Value on:

POR,

BOR

Value on

all other

Resets

Address

Name

Bit 7

Bit 6 Bit 5 Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

ADRES

GIE

ADIE T0IE INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000u

xxxx xxxx uuuu uuuu

0Bh,8Bh

89h

A/D Result Register

ADCON0 ADCS1 ADCS0

—

CHS1 CHS0 GO/DONE ADIF

ADON 00-0 0000 00-0 0000

08h

ADCON1

—

PCFG1 PCFG0 ---- --00 ---- --00

88h

---x 0000 ---u 0000

---1 1111 ---1 1111

05h

PORTA

TRISA

—

RA4

RA3

RA2

RA1

RA0

85h

PORTA Data Direction Register

Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.

TABLE 7-4:

REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C715

Value on:

POR,

BOR

Value on

all other

Resets

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

—

PEIE

ADIF

ADIE

T0IE

—

INTE

—

RBIE

—

T0IF

—

INTF

—

RBIF 0000 000x 0000 000u

0Bh/8Bh

0Ch

PIR1

—

-0-- ---- -0-- ----

xxxx xxxx uuuu uuuu

PIE1

—

8Ch

ADRES

A/D Result Register

1Eh

ADCON

0

ADCS ADCS CHS2

CHS1

—

CHS0

—

GO/

DONE

—

ADON 0000 00-0 0000 00-0

1Fh

1

0

ADCON

1

—

PCFG1 PCFG0 ---- --00 ---- --00

9Fh

—

---x 0000 ---u 0000

---1 1111 ---1 1111

TRISA2 TRISA1 TRISA0

05h

85h

PORTA

TRISA

—

RA4

RA3

RA2

RA1

RA0

TRISA4

TRISA

3

Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.

DS30272A-page 46

1997 Microchip Technology Inc.

PIC16C71X

ﬁxed delay of 72 ms (nominal) on power-up only,

designed to keep the part in reset while the power sup-

ply stabilizes. With these two timers on-chip, most

applications need no external reset circuitry.

8.0

SPECIAL FEATURES OF THE

CPU

Applicable Devices 710 71 711 715

SLEEP mode is designed to offer a very low current

power-down mode.The user can wake-up from SLEEP

through external reset, Watchdog Timer Wake-up, or

through an interrupt. Several oscillator options are also

made available to allow the part to ﬁt the application.

The RC oscillator option saves system cost while the

LP crystal option saves power. A set of conﬁguration

bits are used to select various options.

What sets a microcontroller apart from other proces-

sors are special circuits to deal with the needs of real-

time applications. The PIC16CXX family has a host of

such features intended to maximize system reliability,

minimize cost through elimination of external compo-

nents, provide power saving operating modes and offer

code protection. These are:

• Oscillator selection

• Reset

8.1

Conﬁguration Bits

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

The conﬁguration bits can be programmed (read as '0')

or left unprogrammed (read as '1') to select various

device conﬁgurations. These bits are mapped in pro-

gram memory location 2007h.

- Brown-out Reset (BOR)

(PIC16C710/711/715)

The user will note that address 2007h is beyond the

user program memory space. In fact, it belongs to the

special test/conﬁguration memory space (2000h -

3FFFh), which can be accessed only during program-

ming.

- Parity Error Reset (PER) (PIC16C715)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-circuit serial programming

The PIC16CXX has a Watchdog Timer which can be

shut off only through conﬁguration bits. It runs off its

own RC oscillator for added reliability. There are two

timers that offer necessary delays on power-up. One is

the Oscillator Start-up Timer (OST), intended to keep

the chip in reset until the crystal oscillator is stable.The

other is the Power-up Timer (PWRT), which provides a

FIGURE 8-1: CONFIGURATION WORD FOR PIC16C71

—

CP0 PWRTE WDTE FOSC1 FOSC0

bit0

Register: CONFIG

Address 2007h

bit13

bit 13-5: Unimplemented: Read as '1'

bit 4:

bit 3:

bit 2:

CP0: Code protection bit

1 = Code protection off

0 = All memory is code protected, but 00h - 3Fh is writable

PWRTE: Power-up Timer Enable bit

1 = Power-up Timer enabled

0 = Power-up Timer disabled

WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection bits

11= RC oscillator

10= HS oscillator

01= XT oscillator

00= LP oscillator

1997 Microchip Technology Inc.

DS30272A-page 47

PIC16C71X

FIGURE 8-2: CONFIGURATION WORD, PIC16C710/711

CP0

CP0 CP0 CP0 CP0 CP0 CP0 BODEN CP0

CP0 PWRTE WDTE FOSC1 FOSC0

bit0

Register: CONFIG

Address 2007h

bit13

(2)

bit 13-7 CP0: Code protection bits

5-4: 1 = Code protection off

0 = All memory is code protected, but 00h - 3Fh is writable

(1)

bit 6:

bit 3:

bit 2:

BODEN: Brown-out Reset Enable bit

1 = BOR enabled

0 = BOR disabled

(1)

PWRTE: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection bits

11= RC oscillator

10= HS oscillator

01= XT oscillator

00= LP oscillator

Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.

Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.

2: All of the CP0 bits have to be given the same value to enable the code protection scheme listed.

FIGURE 8-3: CONFIGURATION WORD, PIC16C715

CP1 CP0 CP1 CP0 CP1 CP0 MPEEN BODEN CP1

bit13

CP0 PWRTE WDTE FOSC1 FOSC0

bit0

Register: CONFIG

Address 2007h

(2)

bit 13-8 CP1:CP0: Code Protection bits

5-4: 11= Code protection off

10= Upper half of program memory code protected

01= Upper 3/4th of program memory code protected

00= All memory is code protected

bit 7:

bit 6:

bit 3:

bit 2:

MPEEN: Memory Parity Error Enable

1 = Memory Parity Checking is enabled

0 = Memory Parity Checking is disabled

(1)

BODEN: Brown-out Reset Enable bit

1 = BOR enabled

0 = BOR disabled

(1)

PWRTE: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection bits

11= RC oscillator

10= HS oscillator

01= XT oscillator

00= LP oscillator

Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.

Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.

2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

DS30272A-page 48

1997 Microchip Technology Inc.

PIC16C71X

8.2

Oscillator Conﬁgurations

TABLE 8-1:

CERAMIC RESONATORS,

PIC16C71

8.2.1

OSCILLATOR TYPES

Ranges Tested:

The PIC16CXX can be operated in four different oscil-

lator modes. The user can program two conﬁguration

bits (FOSC1 and FOSC0) to select one of these four

modes:

Mode

XT

Freq

OSC1

OSC2

455 kHz

2.0 MHz

4.0 MHz

47 - 100 pF 47 - 100 pF

15 - 68 pF 15 - 68 pF

• LP

• XT

• HS

• RC

Low Power Crystal

Crystal/Resonator

HS

8.0 MHz

15 - 68 pF 15 - 68 pF

10 - 47 pF 10 - 47 pF

16.0 MHz

High Speed Crystal/Resonator

Resistor/Capacitor

These values are for design guidance only. See

notes at bottom of page.

8.2.2

CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

Resonators Used:

455 kHz

Panasonic EFO-A455K04B ± 0.3%

In XT, LP or HS modes a crystal or ceramic resonator

is connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 8-4). The

PIC16CXX Oscillator design requires the use of a par-

allel cut crystal. Use of a series cut crystal may give a

frequency out of the crystal manufacturers speciﬁca-

tions. When in XT, LP or HS modes, the device can

have an external clock source to drive the OSC1/

CLKIN pin (Figure 8-5).

2.0 MHz Murata Erie CSA2.00MG

4.0 MHz Murata Erie CSA4.00MG

8.0 MHz Murata Erie CSA8.00MT

± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

All resonators used did not have built-in capacitors.

TABLE 8-2:

CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR,

PIC16C71

FIGURE 8-4: CRYSTAL/CERAMIC

RESONATOR OPERATION

(HS, XT OR LP

Mode

Freq

OSC1

OSC2

LP

32 kHz

200 kHz

33 - 68 pF

15 - 47 pF

33 - 68 pF

15 - 47 pF

OSC CONFIGURATION)

XT

100 kHz

500 kHz

1 MHz

2 MHz

4 MHz

47 - 100 pF

20 - 68 pF

15 - 68 pF

15 - 47 pF

15 - 33 pF

47 - 100 pF

20 - 68 pF

15 - 68 pF

15 - 47 pF

15 - 33 pF

OSC1

C1

XTAL

OSC2

SLEEP

PIC16CXXX

RF

HS

8 MHz

20 MHz

15 - 47 pF

To internal

logic

RS

(2)

C2

Note1

These values are for design guidance only. See

notes at bottom of page.

See Table 8-1 and Table 8-1 for recommended values of

C1 and C2.

Note 1: A series resistor may be required for AT strip

cut crystals.

2: The buffer is on the OSC2 pin.

FIGURE 8-5: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP

OSC CONFIGURATION)

OSC1

OSC2

Clock from

ext. system

PIC16CXXX

Open

1997 Microchip Technology Inc.

DS30272A-page 49

PIC16C71X

TABLE 8-3:

CERAMIC RESONATORS,

PIC16C710/711/715

TABLE 8-4:

CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR,

PIC16C710/711/715

Ranges Tested:

Crystal

Freq

Cap. Range

C1

Cap. Range

C2

Osc Type

Mode

XT

Freq

455 kHz

2.0 MHz

4.0 MHz

OSC1

OSC2

68 - 100 pF

15 - 68 pF

68 - 100 pF

15 - 68 pF

LP

32 kHz

200 kHz

1 MHz

33 pF

15 pF

33 pF

15 pF

XT

HS

47-68 pF

15 pF

47-68 pF

15 pF

HS

8.0 MHz

16.0 MHz

10 - 68 pF

10 - 22 pF

10 - 68 pF

10 - 22 pF

4 MHz

15 pF

These values are for design guidance only. See

notes at bottom of page.

4 MHz

15 pF

8 MHz

15-33 pF

Resonators Used:

20 MHz

455 kHz Panasonic EFO-A455K04B ± 0.3%

These values are for design guidance only. See

notes at bottom of page.

2.0 MHz Murata Erie CSA2.00MG

4.0 MHz Murata Erie CSA4.00MG

8.0 MHz Murata Erie CSA8.00MT

16.0 MHz Murata Erie CSA16.00MX

± 0.5%

Crystals Used

32 kHz

200 kHz

1 MHz

Epson C-001R32.768K-A

STD XTL 200.000KHz

ECS ECS-10-13-1

± 20 PPM

± 50 PPM

± 30 PPM

All resonators used did not have built-in capacitors.

4 MHz

ECS ECS-40-20-1

8 MHz

EPSON CA-301 8.000M-C

EPSON CA-301 20.000M-C

20 MHz

Note 1: Recommended values of C1 and C2 are identical to the ranges tested table.

2: Higher capacitance increases the stability of oscillator but also increases the start-up time.

3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal man-

ufacturer for appropriate values of external components.

4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level speci-

ﬁcation.

DS30272A-page 50

1997 Microchip Technology Inc.

PIC16C71X

8.2.3

EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

8.2.4

RC OSCILLATOR

For timing insensitive applications the “RC” device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the resis-

tor (Rext) and capacitor (Cext) values, and the operat-

ing temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal pro-

cess parameter variation. Furthermore, the difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

Cext values. The user also needs to take into account

variation due to tolerance of external R and C compo-

nents used. Figure 8-8 shows how the R/C combina-

tion is connected to the PIC16CXX. For Rext values

below 2.2 kΩ, the oscillator operation may become

unstable, or stop completely. For very high Rext values

(e.g. 1 MΩ), the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend to keep

Rext between 3 kΩ and 100 kΩ.

Either a prepackaged oscillator can be used or a simple

oscillator circuit with TTL gates can be built. Prepack-

aged oscillators provide a wide operating range and

better stability. A well-designed crystal oscillator will

provide good performance with TTL gates.Two types of

crystal oscillator circuits can be used; one with series

resonance, or one with parallel resonance.

Figure 8-6 shows implementation of a parallel resonant

oscillator circuit. The circuit is designed to use the fun-

damental frequency of the crystal.The 74AS04 inverter

performs the 180-degree phase shift that a parallel

oscillator requires. The 4.7 kΩ resistor provides the

negative feedback for stability. The 10 kΩ potentiome-

ter biases the 74AS04 in the linear region. This could

be used for external oscillator designs.

FIGURE 8-6: EXTERNAL PARALLEL

RESONANT CRYSTAL

Although the oscillator will operate with no external

capacitor (Cext = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or pack-

age lead frame capacitance.

OSCILLATOR CIRCUIT

+5V

To Other

Devices

10k

74AS04

PIC16CXXX

4.7k

CLKIN

74AS04

See characterization data for desired device for RC fre-

quency variation from part to part due to normal pro-

cess variation.The variation is larger for larger R (since

leakage current variation will affect RC frequency more

for large R) and for smaller C (since variation of input

capacitance will affect RC frequency more).

10k

XTAL

10k

See characterization data for desired device for varia-

tion of oscillator frequency due to VDD for given Rext/

Cext values as well as frequency variation due to oper-

ating temperature for given R, C, and VDD values.

20 pF

Figure 8-7 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental fre-

quency of the crystal. The inverter performs a 180-

degree phase shift in a series resonant oscillator cir-

cuit. The 330 kΩ resistors provide the negative feed-

back to bias the inverters in their linear region.

The oscillator frequency, divided by 4, is available on

the OSC2/CLKOUT pin, and can be used for test pur-

poses or to synchronize other logic (see Figure 3-2 for

waveform).

FIGURE 8-8: RC OSCILLATOR MODE

FIGURE 8-7: EXTERNAL SERIES

RESONANT CRYSTAL

VDD

OSCILLATOR CIRCUIT

Rext

Internal

OSC1

To Other

clock

Devices

330 kΩ

Cext

74AS04

PIC16CXXX

VSS

CLKIN

0.1 µF

OSC2/CLKOUT

Fosc/4

XTAL

1997 Microchip Technology Inc.

DS30272A-page 51

PIC16C71X

WDT Reset, on MCLR reset during SLEEP, and Brown-

out Reset (BOR). They are not affected by a WDT

Wake-up, which is viewed as the resumption of normal

operation.The TO and PD bits are set or cleared differ-

ently in different reset situations as indicated in Table 8-

7, Table 8-8 and Table 8-9. These bits are used in soft-

ware to determine the nature of the reset. See Table 8-

10 and Table 8-11 for a full description of reset states

of all registers.

8.3

Reset

Applicable Devices 710 71 711 715

The PIC16CXX differentiates between various kinds of

reset:

• Power-on Reset (POR)

• MCLR reset during normal operation

• MCLR reset during SLEEP

A simpliﬁed block diagram of the on-chip reset circuit is

shown in Figure 8-9.

• WDT Reset (normal operation)

• Brown-out Reset (BOR) (PIC16C710/711/715)

• Parity Error Reset (PIC16C715)

The PIC16C710/711/715 have a MCLR noise ﬁlter in

the MCLR reset path. The ﬁlter will detect and ignore

small pulses.

Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in any

other reset. Most other registers are reset to a “reset

state” on Power-on Reset (POR), on the MCLR and

It should be noted that a WDT Reset does not drive

MCLR pin low.

FIGURE 8-9: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/VPP Pin

MPEEN

Program

Memory

Parity

(3)

WDT

Module

SLEEP

WDT Time-out

Power-on Reset

VDD rise

detect

VDD

Brown-out

(2)

S

R

Reset

BODEN

OST/PWRT

OST

10-bit Ripple-counter

Chip_Reset

Q

OSC1/

CLKIN

PWRT

10-bit Ripple-counter

(1)

On-chip

RC OSC

Enable PWRT

Enable OST

See Table 8-6 for time-out situations.

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

2: Brown-out Reset is implemented on the PIC16C710/711/715.

3: Parity Error Reset is implemented on the PIC16C715.

DS30272A-page 52

1997 Microchip Technology Inc.

PIC16C71X

The power-up time delay will vary from chip to chip due

to VDD, temperature, and process variation. See DC

parameters for details.

8.4

Power-on Reset (POR), Power-up

Timer (PWRT) and Oscillator Start-up

Timer (OST), and Brown-out Reset

(BOR)

8.4.3

OSCILLATOR START-UP TIMER (OST)

8.4.1

POWER-ON RESET (POR)

Applicable Devices 710 71 711 715

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over.This ensures that the crystal oscil-

lator or resonator has started and stabilized.

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.5V - 2.1V). To

take advantage of the POR, just tie the MCLR pin

directly (or through a resistor) to VDD.This will eliminate

external RC components usually needed to create a

Power-on Reset. A maximum rise time for VDD is spec-

iﬁed. See Electrical Speciﬁcations for details.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

8.4.4

BROWN-OUT RESET (BOR)

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature, ...) must be met to ensure

operation. If these conditions are not met, the device

must be held in reset until the operating conditions are

met. Brown-out Reset may be used to meet the startup

conditions.

Applicable Devices 710 71 711 715

A conﬁguration bit, BODEN, can disable (if clear/pro-

grammed) or enable (if set) the Brown-out Reset cir-

cuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for

greater than parameter #35, the brown-out situation will

reset the chip. A reset may not occur if VDD falls below

4.0V for less than parameter #35. The chip will remain

in Brown-out Reset until VDD rises above BVDD. The

Power-up Timer will now be invoked and will keep the

chip in RESET an additional 72 ms. If VDD drops below

BVDD while the Power-up Timer is running, the chip will

go back into a Brown-out Reset and the Power-up

Timer will be initialized. Once VDD rises above BVDD,

the Power-up Timer will execute a 72 ms time delay.

The Power-up Timer should always be enabled when

Brown-out Reset is enabled. Figure 8-10 shows typical

brown-out situations.

For additional information, refer to Application Note

AN607, "Power-up Trouble Shooting."

8.4.2

POWER-UP TIMER (PWRT)

Applicable Devices 710 71 711 715

The Power-up Timer provides a ﬁxed 72 ms nominal

time-out on power-up only, from the POR. The Power-

up Timer operates on an internal RC oscillator. The

chip is kept in reset as long as the PWRT is active.The

PWRT’s time delay allows VDD to rise to an acceptable

level. A conﬁguration bit is provided to enable/disable

the PWRT.

FIGURE 8-10: BROWN-OUT SITUATIONS

VDD

BVDD

Internal

Reset

72 ms

VDD

BVDD

Internal

Reset

<72 ms

72 ms

VDD

BVDD

Internal

Reset

72 ms

1997 Microchip Technology Inc.

DS30272A-page 53

PIC16C71X

8.4.5

TIME-OUT SEQUENCE

Bit1 is POR (Power-on Reset Status bit). It is cleared

on a Power-on Reset and unaffected otherwise. The

user must set this bit following a Power-on Reset.

Applicable Devices 710 71 711 715

For the PIC16C715, bit2 is PER (Parity Error Reset). It

is cleared on a Parity Error Reset and must be set by

user software. It will also be set on a Power-on Reset.

On power-up the time-out sequence is as follows: First

PWRT time-out is invoked after the POR time delay has

expired. Then OST is activated. The total time-out will

vary based on oscillator conﬁguration and the status of

the PWRT. For example, in RC mode with the PWRT

disabled, there will be no time-out at all. Figure 8-11,

Figure 8-12, and Figure 8-13 depict time-out

sequences on power-up.

For the PIC16C715, bit7 is MPEEN (Memory Parity

Error Enable).This bit reﬂects the status of the MPEEN

bit in conﬁguration word. It is unaffected by any reset of

interrupt.

8.4.7

PARITY ERROR RESET (PER)

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then

bringing MCLR high will begin execution immediately

(Figure 8-12). This is useful for testing purposes or to

synchronize more than one PIC16CXX device operat-

ing in parallel.

Applicable Devices 710 71 711 715

The PIC16C715 has on-chip parity bits that can be

used to verify the contents of program memory. Parity

bits may be useful in applications in order to increase

overall reliability of a system.

Table 8-10 and Table 8-11 show the reset conditions for

some special function registers, while Table 8-12 and

Table 8-13 show the reset conditions for all the

registers.

There are two parity bits for each word of Program

Memory. The parity bits are computed on alternating

bits of the program word. One computation is per-

formed using even parity, the other using odd parity. As

a program executes, the parity is veriﬁed.The even par-

ity bit is XOR’d with the even bits in the program mem-

ory word. The odd parity bit is negated and XOR’d with

the odd bits in the program memory word. When an

error is detected, a reset is generated and the PER ﬂag

bit 2 in the PCON register is cleared (logic‘0’).This indi-

cation can allow software to act on a failure. However,

there is no indication of the program memory location

of the failure in Program Memory. This ﬂag can only be

set (logic ‘1’) by software.

8.4.6

POWER CONTROL/STATUS REGISTER

(PCON)

Applicable Devices 710 71 711 715

The Power Control/Status Register, PCON has up to

two bits, depending upon the device.

Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is

unknown on a Power-on Reset. It must then be set by

the user and checked on subsequent resets to see if bit

BOR cleared, indicating a BOR occurred. The BOR bit

is a "Don’t Care" bit and is not necessarily predictable

if the Brown-out Reset circuitry is disabled (by clearing

bit BODEN in the Conﬁguration Word).

The parity array is user selectable during programming.

Bit 7 of the conﬁguration word located at address

2007h can be programmed (read as ‘0’) to disable par-

ity. If left unprogrammed (read as ‘1’), parity is enabled.

TABLE 8-5:

TIME-OUT IN VARIOUS SITUATIONS, PIC16C71

Oscillator Conﬁguration

Power-up

Wake-up from SLEEP

PWRTE = 1

72 ms + 1024TOSC

72 ms

PWRTE = 0

1024TOSC

—

XT, HS, LP

RC

1024 TOSC

—

TABLE 8-6:

TIME-OUT IN VARIOUS SITUATIONS, PIC16C710/711/715

Oscillator Conﬁguration

Power-up

PWRTE = 0

Wake-up from SLEEP

Brown-out

PWRTE = 1

1024TOSC

—

XT, HS, LP

RC

72 ms + 1024TOSC

72 ms

72 ms + 1024TOSC

72 ms

1024TOSC

—

DS30272A-page 54

1997 Microchip Technology Inc.

PIC16C71X

TABLE 8-7:

TO

STATUS BITS AND THEIR SIGNIFICANCE, PIC16C71

PD

1

0

x

0

u

1

x

0

1

0

u

0

Power-on Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

WDT Reset

WDT Wake-up

MCLR Reset during normal operation

MCLR Reset during SLEEP or interrupt wake-up from SLEEP

TABLE 8-8:

STATUS BITS AND THEIR SIGNIFICANCE, PIC16C710/711

POR

BOR

TO

PD

0

1

x

0

1

0

x

0

u

1

x

0

x

1

0

u

0

Power-on Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WDT Reset

WDT Wake-up

MCLR Reset during normal operation

MCLR Reset during SLEEP or interrupt wake-up from SLEEP

TABLE 8-9:

STATUS BITS AND THEIR SIGNIFICANCE, PIC16C715

PER

POR

BOR

TO

PD

1

x

1

0

1

0

x

0

1

x

0

1

0

x

0

u

1

x

1

x

0

x

1

0

u

0

1

x

Power-on Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WDT Reset

WDT Wake-up

MCLR Reset during normal operation

MCLR Reset during SLEEP or interrupt wake-up from SLEEP

Parity Error Reset

Illegal, PER is set on POR

Illegal, PER is set on BOR

1997 Microchip Technology Inc.

DS30272A-page 55

PIC16C71X

TABLE 8-10: RESET CONDITION FOR SPECIAL REGISTERS, PIC16C710/71/711

Program

Counter

STATUS

Register

PCON

Register

Condition

PIC16C710/711

Power-on Reset

000h

PC + 1

000h

0001 1xxx

000u uuuu

0001 0uuu

0000 1uuu

uuu0 0uuu

0001 1uuu

uuu1 0uuu

---- --0x

---- --uu

---- --u0

---- --uu

MCLR Reset during normal operation

MCLR Reset during SLEEP

WDT Reset

WDT Wake-up

Brown-out Reset (PIC16C710/711)

Interrupt wake-up from SLEEP

(1)

PC + 1

Legend: u= unchanged, x= unknown, -= unimplemented bit read as '0'.

Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded

with the interrupt vector (0004h).

TABLE 8-11: RESET CONDITION FOR SPECIAL REGISTERS, PIC16C715

Program

Counter

STATUS

Register

PCON

Register

Condition

Power-on Reset

000h

PC + 1

000h

0001 1xxx

000u uuuu

0001 0uuu

0000 1uuu

uuu0 0uuu

0001 1uuu

uuu1 0uuu

u--- -10x

u--- -uuu

u--- -uu0

u--- -0uu

u--- -uuu

MCLR Reset during normal operation

MCLR Reset during SLEEP

WDT Reset

WDT Wake-up

Brown-out Reset

Parity Error Reset

(1)

Interrupt wake-up from SLEEP

PC + 1

Legend: u= unchanged, x= unknown, -= unimplemented bit read as '0'.

Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

DS30272A-page 56

1997 Microchip Technology Inc.

PIC16C71X

TABLE 8-12: INITIALIZATION CONDITIONS FOR ALL REGISTERS, PIC16C710/71/711

Register

Power-on Reset,

MCLR Resets

WDT Reset

Wake-up via

WDT or

Interrupt

(5)

Brown-out Reset

W

xxxx xxxx

N/A

uuuu uuuu

N/A

uuuu uuuu

N/A

INDF

TMR0

PCL

xxxx xxxx

0000h

uuuu uuuu

0000h

uuuu uuuu

(2)

PC + 1

(3)

STATUS

0001 1xxx

000q quuu

uuuq quuu

FSR

xxxx xxxx

---x 0000

xxxx xxxx

---0 0000

0000 000x

uuuu uuuu

---u 0000

uuuu uuuu

---0 0000

0000 000u

uuuu uuuu

---u uuuu

uuuu uuuu

---u uuuu

PORTA

PORTB

PCLATH

INTCON

(1)

uuuu uuuu

ADRES

ADCON0

OPTION

TRISA

xxxx xxxx

00-0 0000

1111 1111

---1 1111

1111 1111

---- --0u

uuuu uuuu

00-0 0000

1111 1111

---1 1111

1111 1111

---- --uu

uuuu uuuu

uu-u uuuu

uuuu uuuu

---u uuuu

uuuu uuuu

---- --uu

TRISB

(4)

PCON

ADCON1

---- --00

---- --uu

Legend: u = unchanged, x = unknown, -= unimplemented bit, read as '0', q= value depends on condition

Note 1: One or more bits in INTCON will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: See Table 8-10 for reset value for speciﬁc condition.

4: The PCON register is not implemented on the PIC16C71.

5: Brown-out reset is not implemented on the PIC16C71.

1997 Microchip Technology Inc.

DS30272A-page 57

PIC16C71X

TABLE 8-13: INITIALIZATION CONDITIONS FOR ALL REGISTERS, PIC16C715

Register

Power-on Reset,

Brown-out Reset

Parity Error Reset

MCLR Resets

WDT Reset

Wake-up via

WDT or

Interrupt

W

xxxx xxxx

N/A

uuuu uuuu

N/A

uuuu uuuu

N/A

INDF

TMR0

PCL

xxxx xxxx

0000 0000

uuuu uuuu

0000 0000

uuuu uuuu

(2)

PC + 1

(3)

STATUS

0001 1xxx

000q quuu

uuuq quuu

FSR

xxxx xxxx

---x 0000

xxxx xxxx

---0 0000

0000 000x

uuuu uuuu

---u 0000

uuuu uuuu

---0 0000

0000 000u

uuuu uuuu

---u uuuu

uuuu uuuu

---u uuuu

PORTA

PORTB

PCLATH

INTCON

(1)

uuuu uuuu

(1)

-0-- ----

PIR1

-u-- ----

ADCON0

OPTION

TRISA

TRISB

PIE1

0000 00-0

1111 1111

---1 1111

1111 1111

-0-- ----

---- -qqq

---- --00

0000 00-0

1111 1111

---1 1111

1111 1111

-0-- ----

---- -1uu

---- --00

uuuu uu-u

uuuu uuuu

---u uuuu

uuuu uuuu

-u-- ----

---- -1uu

---- --uu

PCON

ADCON1

Legend: u = unchanged, x = unknown, -= unimplemented bit, read as '0', q= value depends on condition

Note 1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: See Table 8-11 for reset value for speciﬁc condition.

DS30272A-page 58

1997 Microchip Technology Inc.

PIC16C71X

FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

1997 Microchip Technology Inc.

DS30272A-page 59

PIC16C71X

FIGURE 8-14: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

FIGURE 8-15: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1

VDD

33k

VDD

10k

MCLR

D

R

R1

40k

PIC16CXX

MCLR

PIC16CXX

C

Note 1: This circuit will activate reset when VDD

goes below (Vz + 0.7V) where Vz = Zener

voltage.

Note 1: External Power-on Reset circuit is

required only if VDD power-up slope is too

slow. The diode D helps discharge the

capacitor quickly when VDD powers down.

2: Internal brown-out detection on the

PIC16C710/711/715 should be disabled

when using this circuit.

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not violate

the device’s electrical speciﬁcation.

3: Resistors should be adjusted for the char-

acteristics of the transistor.

3: R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR from external capacitor

C in the event of MCLR/VPP pin break-

down due to Electrostatic Discharge

(ESD) or Electrical Overstress (EOS).

FIGURE 8-16: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

VDD

R1

R2

Q1

MCLR

40k

PIC16CXX

Note 1: This brown-out circuit is less expensive,

albeit less accurate. Transistor Q1 turns

off when VDD is below a certain level

such that:

R1

= 0.7V

VDD •

R1 + R2

2: Internal brown-out detection on the

PIC16C710/711/715 should be disabled

when using this circuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

DS30272A-page 60

1997 Microchip Technology Inc.

PIC16C71X

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs (Figure 8-19).

The latency is the same for one or two cycle instruc-

tions. Individual interrupt ﬂag bits are set regardless of

the status of their corresponding mask bit or the GIE

bit.

8.5

Interrupts

Applicable Devices 710 71 711 715

The PIC16C71X family has 4 sources of interrupt.

Interrupt Sources

External interrupt RB0/INT

TMR0 overﬂow interrupt

PORTB change interrupts (pins RB7:RB4)

A/D Interrupt

Note: For the PIC16C71

If an interrupt occurs while the Global Inter-

rupt Enable (GIE) bit is being cleared, the

GIE bit may unintentionally be re-enabled

by the user’s Interrupt Service Routine (the

RETFIE instruction). The events that

would cause this to occur are:

The interrupt control register (INTCON) records indi-

vidual interrupt requests in ﬂag bits. It also has individ-

ual and global interrupt enable bits.

Note: Individual interrupt ﬂag bits are set regard-

less of the status of their corresponding

mask bit or the GIE bit.

1. An instruction clears the GIE bit while

an interrupt is acknowledged.

2. The program branches to the Interrupt

vector and executes the Interrupt Ser-

vice Routine.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. When bit GIE is enabled, and an

interrupt’s ﬂag bit and mask bit are set, the interrupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous registers. Individual interrupt bits are set

regardless of the status of the GIE bit. The GIE bit is

cleared on reset.

3. The Interrupt Service Routine com-

pletes with the execution of the RET-

FIE instruction. This causes the GIE

bit to be set (enables interrupts), and

the program returns to the instruction

after the one which was meant to dis-

able interrupts.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine as well as sets the GIE bit, which

re-enables interrupts.

Perform the following to ensure that inter-

rupts are globally disabled:

LOOP BCF

INTCON, GIE ; Disable global

interrupt bit

BTFSC INTCON, GIE ; Global interrupt

disabled?

; NO, try again

The RB0/INT pin interrupt, the RB port change inter-

rupt and the TMR0 overﬂow interrupt ﬂags are con-

tained in the INTCON register.

;

The peripheral interrupt ﬂags are contained in the spe-

cial function registers PIR1 and PIR2.The correspond-

ing interrupt enable bits are contained in special

function registers PIE1 and PIE2, and the peripheral

interrupt enable bit is contained in special function reg-

ister INTCON.

GOTO LOOP

:

;

Yes, continue

with program

flow

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

1997 Microchip Technology Inc.

DS30272A-page 61

PIC16C71X

FIGURE 8-17: INTERRUPT LOGIC, PIC16C710, 71, 711

Wakeup

(If in SLEEP mode)

T0IF

T0IE

INTF

INTE

Interrupt to CPU

RBIF

RBIE

ADIF

ADIE

GIE

FIGURE 8-18: INTERRUPT LOGIC, PIC16C715

Wakeup

(If in SLEEP mode)

T0IF

T0IE

INTF

INTE

Interrupt to CPU

RBIF

RBIE

ADIF

ADIE

GIE

DS30272A-page 62

1997 Microchip Technology Inc.

PIC16C71X

8.5.1

INT INTERRUPT

8.5.2

TMR0 INTERRUPT

External interrupt on RB0/INT pin is edge triggered:

either rising if bit INTEDG (OPTION<6>) is set, or fall-

ing, if the INTEDG bit is clear. When a valid edge

appears on the RB0/INT pin, ﬂag bit INTF

(INTCON<1>) is set. This interrupt can be disabled by

clearing enable bit INTE (INTCON<4>). Flag bit INTF

must be cleared in software in the interrupt service rou-

tine before re-enabling this interrupt. The INT interrupt

can wake-up the processor from SLEEP, if bit INTE was

set prior to going into SLEEP.The status of global inter-

rupt enable bit GIE decides whether or not the proces-

sor branches to the interrupt vector following wake-up.

See Section 8.8 for details on SLEEP mode.

An overﬂow (FFh → 00h) in the TMR0 register will set

ﬂag bit T0IF (INTCON<2>). The interrupt can be

enabled/disabled by setting/clearing enable bit T0IE

(INTCON<5>). (Section 6.0)

8.5.3

PORTB INTCON CHANGE

An input change on PORTB<7:4> sets ﬂag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit RBIE (INTCON<4>).

(Section 5.2)

Note: For the PIC16C71

if a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RBIF inter-

rupt ﬂag may not get set.

FIGURE 8-19: INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT

3

4

INT pin

1

Interrupt Latency

INTF ﬂag

(INTCON<1>)

5

2

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

PC

0004h

PC+1

—

0005h

PC

Instruction

fetched

Inst (PC)

Inst (PC+1)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

executed

Dummy Cycle

Inst (PC)

Inst (PC-1)

Note

1: INTF ﬂag is sampled here (every Q1).

2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

1997 Microchip Technology Inc.

DS30272A-page 63

PIC16C71X

8.6

Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack.Typically, users may wish to save key reg-

isters during an interrupt i.e., W register and STATUS

register. This will have to be implemented in software.

Example 8-1 stores and restores the STATUS and W

registers. The user register, STATUS_TEMP, must be

deﬁned in bank 0.

The example:

a) Stores the W register.

b) Stores the STATUS register in bank 0.

c) Executes the ISR code.

d) Restores the STATUS register (and bank select

bit).

e) Restores the W register.

EXAMPLE 8-1: SAVING STATUS AND W REGISTERS IN RAM

MOVWF

SWAPF

MOVWF

:

W_TEMP

STATUS,W

STATUS_TEMP

;Copy W to TEMP register, could be bank one or zero

;Swap status to be saved into W

;Save status to bank zero STATUS_TEMP register

:(ISR)

:

SWAPF

STATUS_TEMP,W

;Swap STATUS_TEMP register into W

;(sets bank to original state)

;Move W into STATUS register

;Swap W_TEMP

MOVWF

SWAPF

STATUS

W_TEMP,F

W_TEMP,W

;Swap W_TEMP into W

DS30272A-page 64

1997 Microchip Technology Inc.

PIC16C71X

assigned to the WDT under software control by writing

to the OPTION register. Thus, time-out periods up to

2.3 seconds can be realized.

8.7

Watchdog Timer (WDT)

Applicable Devices 710 71 711 715

The CLRWDTand SLEEPinstructions clear the WDT and

the postscaler, if assigned to the WDT, and prevent it

from timing out and generating a device RESET condi-

tion.

The Watchdog Timer is as a free running on-chip RC

oscillator which does not require any external compo-

nents.This RC oscillator is separate from the RC oscil-

lator of the OSC1/CLKIN pin.That means that the WDT

will run, even if the clock on the OSC1/CLKIN and

OSC2/CLKOUT pins of the device has been stopped,

for example, by execution of a SLEEPinstruction. Dur-

ing normal operation, a WDT time-out generates a

device RESET (Watchdog Timer Reset). If the device is

in SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation (Watch-

dog Timer Wake-up). The WDT can be permanently

disabled by clearing conﬁguration bit WDTE

(Section 8.1).

The TO bit in the STATUS register will be cleared upon

a Watchdog Timer time-out.

8.7.2

WDT PROGRAMMING CONSIDERATIONS

It should also be taken into account that under worst

case conditions (VDD = Min., Temperature = Max., and

max. WDT prescaler) it may take several seconds

before a WDT time-out occurs.

Note: When a CLRWDT instruction is executed

and the prescaler is assigned to the WDT,

the prescaler count will be cleared, but the

prescaler assignment is not changed.

8.7.1

WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). The time-out periods vary with tempera-

DD

ture, V and process variations from part to part (see

DC specs). If longer time-out periods are desired, a

prescaler with a division ratio of up to 1:128 can be

FIGURE 8-20: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source

(Figure 6-6)

0

Postscaler

8

M

1

U

WDT Timer

X

8 - to - 1 MUX

PS2:PS0

PSA

WDT

Enable Bit

To TMR0 (Figure 6-6)

0

1

MUX

PSA

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION register.

FIGURE 8-21: SUMMARY OF WATCHDOG TIMER REGISTERS

Address

2007h

Name

Bit 7

(1)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

WDTE

PS2

Bit 1

FOSC1

PS1

Bit 0

FOSC0

PS0

(1)

Conﬁg. bits

OPTION

CP1

CP0

BODEN

PWRTE

PSA

81h,181h

RBPU

INTEDG

T0CS T0SE

Legend: Shaded cells are not used by the Watchdog Timer.

Note 1: See Figure 8-1, Figure 8-2 and Figure 8-3 for operation of these bits.

1997 Microchip Technology Inc.

DS30272A-page 65

PIC16C71X

Other peripherals cannot generate interrupts since dur-

ing SLEEP, no on-chip Q clocks are present.

8.8

Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have a NOPafter the SLEEPinstruction.

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit (STATUS<3>) is cleared, the

TO (STATUS<4>) bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had,

before the SLEEP instruction was executed (driving

high, low, or hi-impedance).

For lowest current consumption in this mode, place all

I/O pins at either VDD, or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down

the A/D, disable external clocks. Pull all I/O pins, that

are hi-impedance inputs, high or low externally to avoid

switching currents caused by ﬂoating inputs. The

T0CKI input should also be at VDD or VSS for lowest

current consumption. The contribution from on-chip

pull-ups on PORTB should be considered.

8.8.2

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt ﬂag bit set, one of the following will occur:

The MCLR pin must be at a logic high level (VIHMC).

• If the interrupt occurs before the the execution of

a SLEEPinstruction, the SLEEPinstruction will

complete as a NOP.Therefore, the WDT and WDT

postscaler will not be cleared, the TO bit will not

be set and PD bits will not be cleared.

8.8.1

WAKE-UP FROM SLEEP

The device can wake up from SLEEP through one of

the following events:

1. External reset input on MCLR pin.

• If the interrupt occurs during or after the execu-

tion of a SLEEPinstruction, the device will immedi-

ately wake up from sleep . The SLEEPinstruction

will be completely executed before the wake-up.

Therefore, the WDT and WDT postscaler will be

cleared, the TO bit will be set and the PD bit will

be cleared.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. Interrupt from INT pin, RB port change, or some

Peripheral Interrupts.

External MCLR Reset will cause a device reset. All

other events are considered a continuation of program

execution and cause a "wake-up". The TO and PD bits

in the STATUS register can be used to determine the

cause of device reset. The PD bit, which is set on

power-up, is cleared when SLEEPis invoked.The TO bit

is cleared if a WDT time-out occurred (and caused

wake-up).

Even if the ﬂag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes.To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEPinstruction was

executed as a NOP.

To ensure that the WDT is cleared, a CLRWDTinstruc-

tion should be executed before a SLEEPinstruction.

The following peripheral interrupts can wake the device

from SLEEP:

1. TMR1 interrupt. Timer1 must be operating as

an asynchronous counter.

2. A/D conversion (when A/D clock source is RC).

DS30272A-page 66

1997 Microchip Technology Inc.

PIC16C71X

FIGURE 8-22: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

TOST(2)

INTF ﬂag

(INTCON<1>)

Interrupt Latency

(Note 2)

GIE bit

(INTCON<7>)

Processor in

SLEEP

INSTRUCTION FLOW

PC

PC+1

PC+2

PC + 2

0004h

0005h

Instruction

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = SLEEP

Inst(PC - 1)

fetched

Instruction

executed

Dummy cycle

SLEEP

Inst(PC + 1)

Inst(0004h)

Note 1: XT, HS or LP oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.

3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

The device is placed into a program/verify mode by

holding the RB6 and RB7 pins low while raising the

MCLR (VPP) pin from VIL to VIHH (see programming

speciﬁcation). RB6 becomes the programming clock

and RB7 becomes the programming data. Both RB6

and RB7 are Schmitt Trigger inputs in this mode.

8.9

Program Veriﬁcation/Code Protection

If the code protection bit(s) have not been pro-

grammed, the on-chip program memory can be read

out for veriﬁcation purposes.

Note: Microchip does not recommend code pro-

tecting windowed devices.

After reset, to place the device into programming/verify

mode, the program counter (PC) is at location 00h. A 6-

bit command is then supplied to the device. Depending

on the command, 14-bits of program data are then sup-

plied to or from the device, depending if the command

was a load or a read. For complete details of serial pro-

gramming, please refer to the PIC16C6X/7X Program-

ming Speciﬁcations (Literature #DS30228).

8.10

ID Locations

Four memory locations (2000h - 2003h) are designated

as ID locations where the user can store checksum or

other code-identiﬁcation numbers. These locations are

not accessible during normal execution but are read-

able and writable during program/verify. It is recom-

mended that only the 4 least signiﬁcant bits of the ID

location are used.

FIGURE 8-23: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING

8.11

In-Circuit Serial Programming

CONNECTION

PIC16CXX microcontrollers can be serially pro-

grammed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground, and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent ﬁrmware or a custom ﬁrm-

ware to be programmed.

To Normal

Connections

External

Connector

Signals

PIC16CXX

+5V

0V

VDD

VSS

VPP

MCLR/VPP

RB6

RB7

CLK

Data I/O

VDD

To Normal

Connections

1997 Microchip Technology Inc.

DS30272A-page 67

PIC16C71X

NOTES:

DS30272A-page 68

1997 Microchip Technology Inc.

PIC16C71X

• Byte-oriented operations

9.0

INSTRUCTION SET SUMMARY

• Bit-oriented operations

Each PIC16CXX instruction is a 14-bit word divided

into an OPCODE which speciﬁes the instruction type

and one or more operands which further specify the

operation of the instruction. The PIC16CXX instruction

set summary in Table 9-2 lists byte-oriented, bit-ori-

ented, and literal and control operations. Table 9-1

shows the opcode ﬁeld descriptions.

• Literal and control operations

All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the pro-

gram counter is changed as a result of an instruction.

In this case, the execution takes two instruction cycles

with the second cycle executed as a NOP. One instruc-

tion cycle consists of four oscillator periods. Thus, for

an oscillator frequency of 4 MHz, the normal instruction

execution time is 1 µs. If a conditional test is true or the

program counter is changed as a result of an instruc-

tion, the instruction execution time is 2 µs.

For byte-oriented instructions, 'f' represents a ﬁle reg-

ister designator and 'd' represents a destination desig-

nator. The ﬁle register designator speciﬁes which ﬁle

register is to be used by the instruction.

The destination designator speciﬁes where the result of

the operation is to be placed. If 'd' is zero, the result is

placed in the W register. If 'd' is one, the result is placed

in the ﬁle register speciﬁed in the instruction.

Table 9-2 lists the instructions recognized by the

MPASM assembler.

Figure 9-1 shows the general formats that the instruc-

tions can have.

For bit-oriented instructions, 'b' represents a bit ﬁeld

designator which selects the number of the bit affected

by the operation, while 'f' represents the number of the

ﬁle in which the bit is located.

Note: To maintain upward compatibility with

future PIC16CXX products, do not use the

OPTIONand TRISinstructions.

For literal and control operations, 'k' represents an

eight or eleven bit constant or literal value.

All examples use the following format to represent a

hexadecimal number:

TABLE 9-1:

OPCODE FIELD

DESCRIPTIONS

0xhh

where h signiﬁes a hexadecimal digit.

Field

Description

FIGURE 9-1: GENERAL FORMAT FOR

INSTRUCTIONS

f

W

b

k

x

Register ﬁle address (0x00 to 0x7F)

Working register (accumulator)

Byte-oriented ﬁle register operations

13

8

7

6

0

Bit address within an 8-bit ﬁle register

Literal ﬁeld, constant data or label

OPCODE

d

f (FILE #)

Don't care location (= 0 or 1)

d = 0 for destination W

d = 1 for destination f

f = 7-bit ﬁle register address

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

d

Destination select; d = 0: store result in W,

d = 1: store result in ﬁle register f.

Default is d = 1

Bit-oriented ﬁle register operations

13 10 9

b (BIT #)

7

6

OPCODE

f (FILE #)

label Label name

TOS Top of Stack

PC Program Counter

b = 3-bit bit address

f = 7-bit ﬁle register address

PCLATH

Program Counter High Latch

Literal and control operations

GIE Global Interrupt Enable bit

WDT Watchdog Timer/Counter

TO Time-out bit

General

13

8

7

0

PD Power-down bit

OPCODE

k (literal)

dest Destination either the W register or the speciﬁed

register ﬁle location

k = 8-bit immediate value

[ ] Options

Contents

( )

→

CALLand GOTOinstructions only

13 11 10

OPCODE

k = 11-bit immediate value

Assigned to

Register bit ﬁeld

In the set of

< >

k (literal)

User deﬁned term (font is courier)

italics

The instruction set is highly orthogonal and is grouped

into three basic categories:

1997 Microchip Technology Inc.

DS30272A-page 69

PIC16C71X

TABLE 9-2:

PIC16CXX INSTRUCTION SET

Mnemonic,

Operands

Description

Cycles

14-Bit Opcode

Status

Affected

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

1

1(2)

1

1(2)

1

00

0111 dfff ffff C,DC,Z

1,2

2

0101 dfff ffff

0001 lfff ffff

0001 0xxx xxxx

1001 dfff ffff

0011 dfff ffff

1011 dfff ffff

1010 dfff ffff

1111 dfff ffff

0100 dfff ffff

1000 dfff ffff

0000 lfff ffff

0000 0xx0 0000

1101 dfff ffff

1100 dfff ffff

Z

-

f, d

f

1,2

1,2,3

1,2

1,2,3

1,2

DECFSZ

INCF

Z

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

Z

1,2

Move W to f

No Operation

-

f, d

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

C

1,2

0010 dfff ffff C,DC,Z

1110 dfff ffff

0110 dfff ffff Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

01

00bb bfff ffff

01bb bfff ffff

10bb bfff ffff

11bb bfff ffff

1,2

3

1 (2) 01

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

-

k

-

k

-

k

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

1

2

1

2

1

2

1

11

10

00

10

11

00

11

00

11

111x kkkk kkkk C,DC,Z

1001 kkkk kkkk

0kkk kkkk kkkk

Z

0000 0110 0100 TO,PD

1kkk kkkk kkkk

Inclusive OR literal with W

Move literal to W

1000 kkkk kkkk

00xx kkkk kkkk

0000 0000 1001

01xx kkkk kkkk

0000 0000 1000

Z

Return from interrupt

Return with literal in W

Return from Subroutine

Go into standby mode

Subtract W from literal

Exclusive OR literal with W

0000 0110 0011 TO,PD

110x kkkk kkkk C,DC,Z

1010 kkkk kkkk

Z

Note 1: When an I/O register is modiﬁed as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven low by an external

device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

DS30272A-page 70

1997 Microchip Technology Inc.

PIC16C71X

9.1

Instruction Descriptions

Add Literal and W

ANDLW

AND Literal with W

ADDLW

Syntax:

[label] ANDLW

k

Syntax:

[label] ADDLW

0 ≤ k ≤ 255

k

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

Operands:

Operation:

Status Affected:

Encoding:

Description:

(W) .AND. (k) → (W)

(W) + k → (W)

C, DC, Z

Z

11

1001

kkkk

11

111x

kkkk

The contents of W register are

AND’ed with the eight bit literal 'k'.The

result is placed in the W register.

The contents of the W register are

added to the eight bit literal 'k' and the

result is placed in the W register.

Words:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal "k"

Process

data

Write to

W

Decode

Read

literal 'k'

Process

data

Write to

W

ANDLW

0x5F

ADDLW

0x15

Example

Example:

Before Instruction

W

=

0xA3

0x03

W

=

0x10

0x25

After Instruction

W

=

W

=

ADDWF

Syntax:

Add W and f

ANDWF

Syntax:

AND W with f

[label] ADDWF f,d

[label] ANDWF f,d

Operands:

0 ≤ f ≤ 127

Operands:

0 ≤ f ≤ 127

d

[0,1]

d

[0,1]

Operation:

(W) + (f) → (dest)

Operation:

(W) .AND. (f) → (dest)

Status Affected:

Encoding:

C, DC, Z

Status Affected:

Encoding:

Z

00

0111

dfff

ffff

00

0101

dfff

ffff

Add the contents of the W register

with register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'.

AND the W register with register 'f'. If

'd' is 0 the result is stored in the W

register. If 'd' is 1 the result is stored

back in register 'f'.

Description:

Words:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write to

Dest

Decode

Read

register

'f'

Process

data

Write to

Dest

ADDWF

FSR,

0

ANDWF

FSR, 1

Example

Before Instruction

W

FSR =

=

0x17

0xC2

W

FSR =

=

0x17

0xC2

After Instruction

W

FSR =

=

0xD9

0xC2

W

FSR =

=

0x17

0x02

1997 Microchip Technology Inc.

DS30272A-page 71

PIC16C71X

BCF

Bit Clear f

BTFSC

Bit Test, Skip if Clear

Syntax:

Operands:

[label] BCF f,b

Syntax:

[label] BTFSC f,b

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation:

Status Affected:

Encoding:

0 → (f<b>)

Operation:

skip if (f<b>) = 0

None

Status Affected:

Encoding:

01

00bb

bfff

ffff

01

10bb

bfff

ffff

If bit 'b' in register 'f' is '1' then the next

instruction is executed.

If bit 'b', in register 'f', is '0' then the next

instruction is discarded, and a NOP is

executed instead, making this a 2TCY

instruction.

Description:

Words:

Bit 'b' in register 'f' is cleared.

Description:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write

register 'f'

Words:

1

Cycles:

1(2)

Q Cycle Activity:

Q1

Q2

Q3

Q4

BCF

FLAG_REG, 7

Example

Decode

Read

register 'f'

Process

data

NOP

Before Instruction

FLAG_REG = 0xC7

If Skip:

(2nd Cycle)

Q1

After Instruction

FLAG_REG = 0x47

Q2

Q3

Q4

NOP

HERE

FALSE

TRUE

BTFSC FLAG,1

Example

GOTO

PROCESS_CODE

•

Before Instruction

PC

=

address HERE

After Instruction

if FLAG<1> = 0,

PC =

if FLAG<1>=1,

address TRUE

BSF

Bit Set f

Syntax:

Operands:

[label] BSF f,b

PC =

address FALSE

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation:

Status Affected:

Encoding:

1 → (f<b>)

None

01

01bb

bfff

ffff

Bit 'b' in register 'f' is set.

Description:

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write

register 'f'

BSF

FLAG_REG,

7

Example

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

DS30272A-page 72

1997 Microchip Technology Inc.

PIC16C71X

BTFSS

Bit Test f, Skip if Set

CALL

Call Subroutine

Syntax:

[label] BTFSS f,b

Syntax:

[ label ] CALL k

Operands:

0 ≤ f ≤ 127

0 ≤ b < 7

Operands:

Operation:

0 ≤ k ≤ 2047

(PC)+ 1→ TOS,

Operation:

skip if (f<b>) = 1

None

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected:

Encoding:

Status Affected:

Encoding:

None

01

11bb

bfff

ffff

10

0kkk

kkkk

If bit 'b' in register 'f' is '0' then the next

instruction is executed.

If bit 'b' is '1', then the next instruction is

discarded and a NOP is executed

instead, making this a 2TCY instruction.

Description:

Call Subroutine. First, return address

(PC+1) is pushed onto the stack. The

eleven bit immediate address is loaded

into PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALLis a two cycle instruction.

Description:

Words:

1

Cycles:

1(2)

Words:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Cycles:

Decode

Read

register 'f'

Process

data

NOP

Q Cycle Activity:

1st Cycle

Q1

Q2

Q3

Q4

Decode

Read

Process

data

Write to

PC

If Skip:

(2nd Cycle)

Q1

literal 'k',

Push PC

to Stack

Q2

Q3

Q4

NOP

2nd Cycle

Example

HERE

FALSE

TRUE

BTFSC FLAG,1

GOTO

Example

HERE

CALL THERE

PROCESS_CODE

Before Instruction

•

PC

= Address HERE

After Instruction

PC

= Address THERE

Before Instruction

TOS = Address HERE+1

PC

=

address HERE

After Instruction

if FLAG<1> = 0,

PC =

address FALSE

if FLAG<1> = 1,

PC =

address TRUE

1997 Microchip Technology Inc.

DS30272A-page 73

PIC16C71X

CLRF

Clear f

CLRW

Clear W

Syntax:

[label] CLRF

0 ≤ f ≤ 127

f

Syntax:

[ label ] CLRW

None

Operands:

Operation:

Operands:

Operation:

00h → (f)

1 → Z

00h → (W)

1 → Z

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

Z

00

0001

1fff

ffff

00

0001

0xxx

xxxx

The contents of register 'f' are cleared

and the Z bit is set.

Description:

W register is cleared. Zero bit (Z) is

set.

Description:

Words:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write

register 'f'

Decode

NOP

Process

data

Write to

W

CLRW

Example

CLRF

FLAG_REG

Example

Before Instruction

FLAG_REG

After Instruction

W

=

0x5A

=

0x5A

After Instruction

W

=

0x00

1

FLAG_REG

Z

=

0x00

1

Z

=

CLRWDT

Syntax:

Clear Watchdog Timer

[ label ] CLRWDT

None

Operands:

Operation:

00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

Status Affected:

Encoding:

TO, PD

00

0000

0110

0100

CLRWDTinstruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT. Status bits TO and PD

are set.

Description:

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

NOP

Process

data

Clear

WDT

Counter

CLRWDT

Example

Before Instruction

After Instruction

WDT counter

=

?

WDT counter

0x00

WDT prescaler=

0

1

TO

PD

=

DS30272A-page 74

1997 Microchip Technology Inc.

PIC16C71X

COMF

Complement f

[ label ] COMF f,d

0 ≤ f ≤ 127

DECFSZ

Syntax:

Decrement f, Skip if 0

[ label ] DECFSZ f,d

0 ≤ f ≤ 127

Syntax:

Operands:

d

[0,1]

d

[0,1]

Operation:

(f) → (dest)

Operation:

(f) - 1 → (dest); skip if result = 0

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

None

00

1001

dfff

ffff

00

1011

dfff

ffff

The contents of register 'f' are comple-

mented. If 'd' is 0 the result is stored in

W. If 'd' is 1 the result is stored back in

register 'f'.

Description:

The contents of register 'f' are decre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

If the result is 1, the next instruction, is

executed. If the result is 0, then a NOP is

executed instead making it a 2TCY

instruction.

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Words:

1

Decode

Read

register

'f'

Process

data

Write to

dest

Cycles:

1(2)

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write to

dest

COMF

REG1,0

Example

Before Instruction

REG1

After Instruction

REG1

=

0x13

If Skip:

(2nd Cycle)

Q1

Q2

Q3

Q4

=

0x13

0xEC

NOP

W

DECF

Decrement f

[label] DECF f,d

0 ≤ f ≤ 127

HERE

DECFSZ

GOTO

CNT, 1

LOOP

Example

Syntax:

Operands:

CONTINUE •

•

d

[0,1]

Before Instruction

Operation:

(f) - 1 → (dest)

PC

=

address HERE

Status Affected:

Encoding:

Z

After Instruction

CNT

if CNT =

PC

if CNT ≠

PC

=

CNT - 1

0,

address CONTINUE

0,

address HERE+1

00

0011

dfff

ffff

Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Description:

=

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write to

dest

DECF

CNT, 1

Example

Before Instruction

CNT

=

0x01

Z

=

0

After Instruction

CNT

Z

=

0x00

1

1997 Microchip Technology Inc.

DS30272A-page 75

PIC16C71X

INCF

Increment f

GOTO

Unconditional Branch

Syntax:

Operands:

[ label ] INCF f,d

Syntax:

[ label ] GOTO k

0 ≤ f ≤ 127

Operands:

Operation:

0 ≤ k ≤ 2047

d

[0,1]

k → PC<10:0>

PCLATH<4:3> → PC<12:11>

Operation:

(f) + 1 → (dest)

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

None

00

1010

dfff

ffff

10

1kkk

kkkk

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

GOTOis an unconditional branch. The

eleven bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTOis a two cycle instruction.

Description:

Words:

1

Words:

1

2

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

1st Cycle

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write to

dest

Decode

Read

literal 'k'

Process

data

Write to

PC

NOP

2nd Cycle

Example

INCF

CNT, 1

Example

GOTO THERE

Before Instruction

CNT

Z

=

0xFF

0

After Instruction

PC

=

Address THERE

After Instruction

CNT

Z

=

0x00

1

DS30272A-page 76

1997 Microchip Technology Inc.

PIC16C71X

INCFSZ

Syntax:

Increment f, Skip if 0

[ label ] INCFSZ f,d

0 ≤ f ≤ 127

IORLW

Inclusive OR Literal with W

[ label ] IORLW k

0 ≤ k ≤ 255

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

d

[0,1]

(W) .OR. k → (W)

Z

Operation:

(f) + 1 → (dest), skip if result = 0

Status Affected:

Encoding:

None

11

1000

kkkk

00

1111

dfff

ffff

The contents of the W register is

OR’ed with the eight bit literal 'k'. The

result is placed in the W register.

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 1, the next instruction is

executed. If the result is 0, a NOP is

executed instead making it a 2TCY

instruction.

Description:

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal 'k'

Process

data

Write to

W

Words:

1

Cycles:

1(2)

Q Cycle Activity:

Q1

Q2

Q3

Q4

IORLW

0x35

Example

Decode

Read

register

'f'

Process

data

Write to

dest

Before Instruction

W

=

0x9A

After Instruction

If Skip:

(2nd Cycle)

Q1

W

=

0xBF

1

Z

=

Q2

Q3

Q4

NOP

HERE

INCFSZ

GOTO

CNT, 1

LOOP

Example

CONTINUE •

•

Before Instruction

PC

=

address HERE

After Instruction

CNT

=

CNT + 1

if CNT=

0,

PC

if CNT≠

=

address CONTINUE

0,

PC

=

address HERE +1

1997 Microchip Technology Inc.

DS30272A-page 77

PIC16C71X

IORWF

Inclusive OR W with f

MOVLW

Move Literal to W

[ label ] MOVLW k

0 ≤ k ≤ 255

Syntax:

[ label ] IORWF f,d

Syntax:

Operands:

0 ≤ f ≤ 127

Operands:

Operation:

Status Affected:

Encoding:

Description:

d

[0,1]

k → (W)

Operation:

(W) .OR. (f) → (dest)

None

Status Affected:

Encoding:

Z

11

00xx

kkkk

00

0100

dfff

ffff

The eight bit literal 'k' is loaded into W

register.The don’t cares will assemble

as 0’s.

Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

Words:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal 'k'

Process

data

Write to

W

Decode

Read

register

'f'

Process

data

Write to

dest

MOVLW

0x5A

Example

After Instruction

IORWF

RESULT, 0

Example

W

=

0x5A

Before Instruction

RESULT =

0x13

0x91

W

=

After Instruction

RESULT =

0x13

0x93

1

W

Z

=

MOVWF

Move W to f

MOVF

Move f

Syntax:

[ label ] MOVWF

0 ≤ f ≤ 127

(W) → (f)

f

Syntax:

Operands:

[ label ] MOVF f,d

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ f ≤ 127

d

[0,1]

None

Operation:

(f) → (dest)

00

0000

1fff

ffff

Status Affected:

Encoding:

Z

Move data from W register to register

'f'.

00

1000

dfff

ffff

The contents of register f is moved to

a destination dependant upon the sta-

tus of d. If d = 0, destination is W reg-

ister. If d = 1, the destination is ﬁle

register f itself. d = 1 is useful to test a

ﬁle register since status ﬂag Z is

affected.

Description:

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write

register 'f'

Words:

1

Cycles:

MOVWF

OPTION_REG

Example

Q Cycle Activity:

Q1

Q2

Q3

Q4

Before Instruction

OPTION =

Decode

Read

register

'f'

Process

data

Write to

dest

0xFF

0x4F

W

=

After Instruction

OPTION =

0x4F

MOVF

FSR, 0

Example

W

=

After Instruction

W = value in FSR register

Z

= 1

DS30272A-page 78

1997 Microchip Technology Inc.

PIC16C71X

NOP

No Operation

[ label ] NOP

None

RETFIE

Return from Interrupt

[ label ] RETFIE

None

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Operands:

Operation:

No operation

None

TOS → PC,

1 → GIE

Status Affected:

Encoding:

None

00

0000

0xx0

0000

00

0000

1001

No operation.

Return from Interrupt. Stack is POPed

and Top of Stack (TOS) is loaded in

the PC. Interrupts are enabled by set-

ting Global Interrupt Enable bit, GIE

(INTCON<7>). This is a two cycle

instruction.

Description:

1

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

NOP

Words:

1

2

NOP

Example

Cycles:

Q Cycle Activity:

1st Cycle

Q1

Q2

Q3

Q4

Decode

NOP

Set the Pop from

GIE bit the Stack

NOP

2nd Cycle

Example

RETFIE

After Interrupt

PC

=

TOS

GIE =

1

OPTION

Syntax:

Load Option Register

[ label ] OPTION

None

Operands:

Operation:

(W) → OPTION

Status Affected: None

00

0000

0110

0010

Encoding:

The contents of the W register are

loaded in the OPTION register. This

instruction is supported for code com-

patibility with PIC16C5X products.

Since OPTION is a readable/writable

register, the user can directly address

it.

Description:

Words:

Cycles:

Example

1

To maintain upward compatibility

with future PIC16CXX products, do

not use this instruction.

1997 Microchip Technology Inc.

DS30272A-page 79

PIC16C71X

RETLW

Return with Literal in W

RETURN

Return from Subroutine

[ label ] RETURN

None

Syntax:

[ label ] RETLW k

Syntax:

Operands:

Operation:

0 ≤ k ≤ 255

Operands:

Operation:

Status Affected:

Encoding:

Description:

k → (W);

TOS → PC

None

Status Affected:

Encoding:

None

00

0000

1000

11

01xx

kkkk

Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.

This is a two cycle instruction.

The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Description:

Words:

1

2

Cycles:

Words:

1

2

Q Cycle Activity:

1st Cycle

Q1

Q2

Q3

Q4

Cycles:

Decode

NOP

Pop from

the Stack

Q Cycle Activity:

1st Cycle

Q1

Q2

Q3

Q4

Decode

Read

NOP

Write to

W, Pop

from the

Stack

NOP

2nd Cycle

Example

literal 'k'

RETURN

NOP

2nd Cycle

Example

After Interrupt

PC

=

TOS

CALL TABLE ;W contains table

;offset value

•

;W now has table value

•

TABLE

ADDWF PC

RETLW k1

RETLW k2

•

;W = offset

;Begin table

;

•

RETLW kn

; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

DS30272A-page 80

1997 Microchip Technology Inc.

PIC16C71X

RLF

Rotate Left f through Carry

RRF

Rotate Right f through Carry

[ label ] RRF f,d

0 ≤ f ≤ 127

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

Operands:

0 ≤ f ≤ 127

d

[0,1]

d

[0,1]

Operation:

See description below

C

Operation:

See description below

C

Status Affected:

Encoding:

Status Affected:

Encoding:

00

1101

dfff

ffff

00

1100

dfff

ffff

The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

stored back in register 'f'.

The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

C

Register f

C

Register f

Words:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write to

dest

Decode

Read

register

'f'

Process

data

Write to

dest

RLF

REG1,0

Example

RRF

REG1,0

Example

Before Instruction

REG1

C

=

1110 0110

0

REG1

C

=

1110 0110

0

After Instruction

REG1

W

C

=

1110 0110

1100 1100

1

REG1

W

C

=

1110 0110

0111 0011

0

1997 Microchip Technology Inc.

DS30272A-page 81

PIC16C71X

SLEEP

SUBLW

Subtract W from Literal

Syntax:

[ label ]

SUBLW k

Syntax:

[ label ] SLEEP

Operands:

Operation:

0 ≤ k ≤ 255

Operands:

Operation:

None

k - (W) → (W)

00h → WDT,

0 → WDT prescaler,

1 → TO,

Status Affected: C, DC, Z

Encoding:

11

110x

kkkk

0 → PD

The W register is subtracted (2’s comple-

ment method) from the eight bit literal 'k'.

The result is placed in the W register.

Description:

Status Affected:

Encoding:

TO, PD

00

0000

0110

0011

Words:

1

The power-down status bit, PD is

cleared. Time-out status bit, TO is

set. Watchdog Timer and its pres-

caler are cleared.

Description:

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

The processor is put into SLEEP

mode with the oscillator stopped.

See Section 8.8 for more details.

Decode

Read

literal 'k'

Process Write to W

data

Words:

1

Example 1:

SUBLW

0x02

Cycles:

Before Instruction

Q Cycle Activity:

Q1

Q2

Q3

Q4

W

C

Z

=

1

?

Decode

NOP

Go to

Sleep

After Instruction

Example:

SLEEP

W

C

Z

=

1

1; result is positive

0

Example 2:

Before Instruction

W

C

Z

=

2

?

After Instruction

W

C

Z

=

0

1; result is zero

1

Example 3:

Before Instruction

W

C

Z

=

3

?

After Instruction

W

C

=

0xFF

0; result is nega-

tive

Z

=

0

DS30272A-page 82

1997 Microchip Technology Inc.

PIC16C71X

SUBWF

Syntax:

Subtract W from f

SWAPF

Syntax:

Swap Nibbles in f

[ label ] SWAPF f,d

[ label ]

SUBWF f,d

Operands:

0 ≤ f ≤ 127

Operands:

0 ≤ f ≤ 127

d

[0,1]

d

[0,1]

Operation:

(f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3:0>)

Operation:

(f) - (W) → (dest)

Status Affected: C, DC, Z

Status Affected:

Encoding:

None

Encoding:

00

0010

dfff

ffff

00

1110

dfff

ffff

Subtract (2’s complement method) W reg-

ister from register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'.

Description:

The upper and lower nibbles of regis-

ter 'f' are exchanged. If 'd' is 0 the

result is placed in W register. If 'd' is 1

the result is placed in register 'f'.

Description:

Words:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register 'f'

Process

data

Write to

dest

Decode

Read

register 'f'

Process Write to

data dest

Example 1:

SUBWF

REG1,1

SWAPF REG,

0

Example

Before Instruction

REG1

=

3

2

?

W

C

Z

=

0xA5

After Instruction

REG1

W

=

0xA5

0x5A

After Instruction

REG1

=

1

2

W

C

Z

=

1; result is positive

0

Example 2:

Before Instruction

TRIS

Load TRIS Register

REG1

=

2

?

Syntax:

[label] TRIS

f

W

C

Z

Operands:

Operation:

5 ≤ f ≤ 7

(W) → TRIS register f;

Status Affected: None

After Instruction

00

Encoding:

0000 0110

0fff

REG1

=

0

W

C

Z

=

2

The instruction is supported for code

compatibility with the PIC16C5X prod-

ucts. Since TRIS registers are read-

able and writable, the user can directly

address them.

Description:

1; result is zero

1

Example 3:

Before Instruction

REG1

=

1

2

?

Words:

Cycles:

Example

1

W

C

Z

After Instruction

To maintain upward compatibility

with future PIC16CXX products, do

not use this instruction.

REG1

=

0xFF

2

0; result is negative

0

W

C

Z

=

1997 Microchip Technology Inc.

DS30272A-page 83

PIC16C71X

XORLW

Exclusive OR Literal with W

[label] XORLW k

XORWF

Syntax:

Exclusive OR W with f

[label] XORWF f,d

0 ≤ f ≤ 127

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

0 ≤ k ≤ 255

d

[0,1]

(W) .XOR. k → (W)

Operation:

(W) .XOR. (f) → (dest)

Z

Status Affected:

Encoding:

Z

11

1010 kkkk kkkk

00

0110

dfff

ffff

The contents of the W register are

XOR’ed with the eight bit literal 'k'.

The result is placed in the W regis-

ter.

Description:

Exclusive OR the contents of the W

register with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Description:

Words:

1

Cycles:

Words:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Cycles:

Decode

Read

literal 'k'

Process Write to

Q Cycle Activity:

Q1

Q2

Q3

Q4

data

W

Decode

Read

register

'f'

Process

data

Write to

dest

Example:

XORLW

0xAF

Before Instruction

REG

1

Example

XORWF

W

=

0xB5

0x1A

Before Instruction

After Instruction

REG

W

=

0xAF

0xB5

W

=

After Instruction

REG

W

=

0x1A

0xB5

DS30272A-page 84

1997 Microchip Technology Inc.

PIC16C71X

10.3

ICEPIC: Low-Cost PIC16CXXX

In-Circuit Emulator

10.0 DEVELOPMENT SUPPORT

10.1

Development Tools

ICEPIC is a low-cost in-circuit emulator solution for the

Microchip PIC16C5X and PIC16CXXX families of 8-bit

OTP microcontrollers.

The PICmicrο microcontrollers are supported with a

full range of hardware and software development tools:

• PICMASTER/PICMASTER CE Real-Time

In-Circuit Emulator

ICEPIC is designed to operate on PC-compatible

machines ranging from 286-AT through Pentium

based machines under Windows 3.x environment.

ICEPIC features real time, non-intrusive emulation.

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX

In-Circuit Emulator

• PRO MATE II Universal Programmer

10.4

PRO MATE II: Universal Programmer

• PICSTART Plus Entry-Level Prototype

Programmer

The PRO MATE II Universal Programmer is a full-fea-

tured programmer capable of operating in stand-alone

mode as well as PC-hosted mode.

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

The PRO MATE II has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to support various package types. In stand-

alone mode the PRO MATE II can read, verify or pro-

• MPLAB SIM Software Simulator

• MPLAB-C (C Compiler)

• Fuzzy Logic Development System

(fuzzyTECH −MP)

gram

PIC12CXXX,

PIC14C000,

PIC16C5X,

10.2

PICMASTER: High Performance

Universal In-Circuit Emulator with

MPLAB IDE

PIC16CXXX and PIC17CXX devices. It can also set

conﬁguration and code-protect bits in this mode.

10.5

PICSTART Plus Entry Level

Development System

The PICMASTER Universal In-Circuit Emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for all

microcontrollers in the PIC12CXXX, PIC14C000,

PIC16C5X, PIC16CXXX and PIC17CXX families.

PICMASTER is supplied with the MPLAB Integrated

Development Environment (IDE), which allows editing,

“make” and download, and source debugging from a

single environment.

The PICSTART programmer is an easy-to-use, low-

cost prototype programmer. It connects to the PC via

one of the COM (RS-232) ports. MPLAB Integrated

Development Environment software makes using the

programmer simple and efﬁcient. PICSTART Plus is

not recommended for production programming.

PICSTART Plus supports all PIC12CXXX, PIC14C000,

PIC16C5X, PIC16CXXX and PIC17CXX devices with

up to 40 pins. Larger pin count devices such as the

PIC16C923 and PIC16C924 may be supported with an

adapter socket.

Interchangeable target probes allow the system to be

easily reconﬁgured for emulation of different proces-

sors. The universal architecture of the PICMASTER

allows expansion to support all new Microchip micro-

controllers.

The PICMASTER Emulator System has been

designed as a real-time emulation system with

advanced features that are generally found on more

expensive development tools. The PC compatible 386

(and higher) machine platform and Microsoft Windows

3.x environment were chosen to best make these fea-

tures available to you, the end user.

A CE compliant version of PICMASTER is available for

European Union (EU) countries.

1997 Microchip Technology Inc.

DS30272A-page 85

PIC16C71X

an RS-232 interface, push-button switches, a potenti-

ometer for simulated analog input, a thermistor and

separate headers for connection to an external LCD

module and a keypad. Also provided on the PICDEM-3

board is an LCD panel, with 4 commons and 12 seg-

ments, that is capable of displaying time, temperature

and day of the week. The PICDEM-3 provides an addi-

tional RS-232 interface and Windows 3.1 software for

showing the demultiplexed LCD signals on a PC. A sim-

ple serial interface allows the user to construct a hard-

ware demultiplexer for the LCD signals.

10.6

PICDEM-1 Low-Cost PIC16/17

Demonstration Board

The PICDEM-1 is a simple board which demonstrates

the capabilities of several of Microchip’s microcontrol-

lers. The microcontrollers supported are: PIC16C5X

(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,

PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and

PIC17C44. All necessary hardware and software is

included to run basic demo programs. The users can

program the sample microcontrollers provided with

the PICDEM-1 board, on a PRO MATE II or

PICSTART-Plus programmer, and easily test ﬁrm-

ware. The user can also connect the PICDEM-1

board to the PICMASTER emulator and download

the ﬁrmware to the emulator for testing. Additional pro-

totype area is available for the user to build some addi-

tional hardware and connect it to the microcontroller

socket(s). Some of the features include an RS-232

interface, a potentiometer for simulated analog input,

push-button switches and eight LEDs connected to

PORTB.

10.9

MPLAB Integrated Development

Environment Software

The MPLAB IDE Software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. MPLAB is a windows based application

which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

10.7

PICDEM-2 Low-Cost PIC16CXX

Demonstration Board

The PICDEM-2 is a simple demonstration board that

supports the PIC16C62, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sample microcontrollers provided

with the PICDEM-2 board, on a PRO MATE II pro-

grammer or PICSTART-Plus, and easily test ﬁrmware.

The PICMASTER emulator may also be used with the

PICDEM-2 board to test ﬁrmware. Additional prototype

area has been provided to the user for adding addi-

tional hardware and connecting it to the microcontroller

socket(s). Some of the features include a RS-232 inter-

face, push-button switches, a potentiometer for simu-

lated analog input, a Serial EEPROM to demonstrate

MPLAB allows you to:

• Edit your source ﬁles (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PIC16/17 tools (automatically updates all

project information)

• Debug using:

- source ﬁles

- absolute listing ﬁle

• Transfer data dynamically via DDE (soon to be

replaced by OLE)

• Run up to four emulators on the same PC

The ability to use MPLAB with Microchip’s simulator

allows a consistent platform and the ability to easily

switch from the low cost simulator to the full featured

emulator with minimal retraining due to development

tools.

2

usage of the I C bus and separate headers for connec-

tion to an LCD module and a keypad.

10.8

PICDEM-3 Low-Cost PIC16CXXX

Demonstration Board

10.10 Assembler (MPASM)

The PICDEM-3 is a simple demonstration board that

supports the PIC16C923 and PIC16C924 in the PLCC

package. It will also support future 44-pin PLCC

microcontrollers with a LCD Module. All the neces-

sary hardware and software is included to run the

basic demonstration programs. The user can pro-

gram the sample microcontrollers provided with

the PICDEM-3 board, on a PRO MATE II program-

mer or PICSTART Plus with an adapter socket, and

easily test ﬁrmware. The PICMASTER emulator may

also be used with the PICDEM-3 board to test ﬁrm-

ware. Additional prototype area has been provided to

the user for adding hardware and connecting it to the

microcontroller socket(s). Some of the features include

The MPASM Universal Macro Assembler is a PC-

hosted symbolic assembler. It supports all microcon-

troller series including the PIC12C5XX, PIC14000,

PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, condi-

tional assembly, and several source and listing formats.

It generates various object code formats to support

Microchip's development tools as well as third party

programmers.

MPASM allows full symbolic debugging from

PICMASTER, Microchip’s Universal Emulator

System.

DS30272A-page 86

1997 Microchip Technology Inc.

PIC16C71X

MPASM has the following features to assist in develop-

ing software for speciﬁc use applications.

10.14 MP-DriveWay – Application Code

Generator

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

MP-DriveWay is an easy-to-use Windows-based Appli-

cation Code Generator. With MP-DriveWay you can

visually conﬁgure all the peripherals in a PIC16/17

device and, with a click of the mouse, generate all the

initialization and many functional code modules in C

language. The output is fully compatible with Micro-

chip’s MPLAB-C C compiler. The code produced is

highly modular and allows easy integration of your own

code. MP-DriveWay is intelligent enough to maintain

your code through subsequent code generation.

• Macro assembly capability.

• Produces all the ﬁles (Object, Listing, Symbol,

and special) required for symbolic debug with

Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source

and listing formats.

MPASM provides a rich directive language to support

programming of the PIC16/17. Directives are helpful in

making the development of your assemble source code

shorter and more maintainable.

10.15 SEEVAL Evaluation and

Programming System

10.11 Software Simulator (MPLAB-SIM)

The SEEVAL SEEPROM Designer’s Kit supports all

Microchip 2-wire and 3-wire Serial EEPROMs. The kit

includes everything necessary to read, write, erase or

program special features of any Microchip SEEPROM

product including Smart Serials and secure serials.

The Total Endurance Disk is included to aid in trade-

off analysis and reliability calculations. The total kit can

signiﬁcantly reduce time-to-market and result in an

optimized system.

The MPLAB-SIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PIC16/17 series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pins. The input/

output radix can be set by the user and the execution

can be performed in; single step, execute until break, or

in a trace mode.

10.16 KEELOQ Evaluation and

Programming Tools

MPLAB-SIM fully supports symbolic debugging using

MPLAB-C and MPASM. The Software Simulator offers

the low cost ﬂexibility to develop and debug code out-

side of the laboratory environment making it an excel-

lent multi-project software development tool.

KEELOQ evaluation and programming tools support

Microchips HCS Secure Data Products.The HCS eval-

uation kit includes an LCD display to show changing

codes, a decoder to decode transmissions, and a pro-

gramming interface to program test transmitters.

10.12 C Compiler (MPLAB-C)

The MPLAB-C Code Development System is a

complete ‘C’ compiler and integrated development

environment for Microchip’s PIC16/17 family of micro-

controllers. The compiler provides powerful integration

capabilities and ease of use not found with other

compilers.

For easier source level debugging, the compiler pro-

vides symbol information that is compatible with the

MPLAB IDE memory display.

10.13 Fuzzy Logic Development System

(fuzzyTECH-MP)

fuzzyTECH-MP fuzzy logic development tool is avail-

able in two versions - a low cost introductory version,

MP Explorer, for designers to gain a comprehensive

working knowledge of fuzzy logic system design; and a

full-featured version, fuzzyTECH-MP, edition for imple-

menting more complex systems.

Both versions include Microchip’s fuzzyLAB demon-

stration board for hands-on experience with fuzzy logic

systems implementation.

1997 Microchip Technology Inc.

DS30272A-page 87

PIC16C71X

TABLE 10-1: DEVELOPMENT TOOLS FROM MICROCHIP

ufzy

D e m o B o a r d s

E m u l a t o r P r o d u c t s

S o f t w a r e T o o l s

P r o g r a m m e r s

DS30272A-page 88

1997 Microchip Technology Inc.

PIC16C71X

Applicable Devices 710 71 711 715

11.0 ELECTRICAL CHARACTERISTICS FOR PIC16C710 AND PIC16C711

Absolute Maximum Ratings †

Ambient temperature under bias.................................................................................................................-55 to +125˚C

Storage temperature .............................................................................................................................. -65˚C to +150˚C

Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ........................................................................................................... -0.3 to +7.5V

Voltage on MCLR with respect to VSS................................................................................................................0 to +14V

Voltage on RA4 with respect to Vss ...................................................................................................................0 to +14V

Total power dissipation (Note 1)................................................................................................................................1.0W

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin ..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA

Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................± 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by PORTA ........................................................................................................................200 mA

Maximum current sourced by PORTA...................................................................................................................200 mA

Maximum current sunk by PORTB........................................................................................................................200 mA

Maximum current sourced by PORTB...................................................................................................................200 mA

Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device.This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

TABLE 11-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

PIC16C710-04

PIC16C711-04

PIC16C710-10

PIC16C711-10

PIC16C710-20

PIC16C711-20

PIC16LC710-04

PIC16LC711-04

PIC16C710/JW

PIC16C711/JW

OSC

VDD: 4.0V to 6.0V

VDD: 4.5V to 5.5V

VDD: 2.5V to 6.0V

VDD: 4.0V to 6.0V

IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA typ. at 3.0V IDD: 5 mA max. at 5.5V

RC

IPD: 21 µA max. at 4V IPD: 1.5 µA typ. at 4V

IPD: 1.5 µA typ. at 4V

IPD: 5.0 µA typ. at 3V

IPD: 21 µA max. at 4V

Freq:4 MHz max.

Freq: 4 MHz max.

Freq:4 MHz max.

VDD: 4.0V to 6.0V

VDD: 4.5V to 5.5V

VDD: 2.5V to 6.0V

VDD: 4.0V to 6.0V

IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA typ. at 3.0V IDD: 5 mA max. at 5.5V

XT

HS

IPD: 21 µA max. at 4V IPD: 1.5 µA typ. at 4V

IPD: 1.5 µA typ. at 4V

IPD: 5.0 µA typ. at 3V

IPD: 21 µA max. at 4V

Freq: 4 MHz max.

VDD: 4.5V to 5.5V

VDD:4.5V to 5.5V

VDD: 4.5V to 5.5V

IDD: 13.5 mA typ. at

5.5V

IDD: 30 mA max. at

5.5V

IDD: 30 mA max. at

5.5V

IDD: 30 mA max. at

5.5V

Not recommended for

use in HS mode

IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V

IPD: 1.5 µA typ. at 4.5V

Freq: 4 MHz max.

Freq: 10 MHz max.

Freq:20 MHz max.

Freq: 10 MHz max.

VDD: 4.0V to 6.0V

IDD: 52.5 µA typ. at

32 kHz, 4.0V

IPD: 0.9 µA typ. at 4.0V

Freq: 200 kHz max.

VDD: 2.5V to 6.0V

IDD: 48 µA max. at

32 kHz, 3.0V

IPD: 5.0 µA max. at 3.0V IPD: 5.0 µA max. at

Freq: 200 kHz max.

VDD: 2.5V to 6.0V

IDD: 48 µA max. at

32 kHz, 3.0V

Not recommended for

use in LP mode

Not recommended for

use in LP mode

LP

3.0V

Freq: 200 kHz max.

1997 Microchip Technology Inc.

DS30272A-page 89

PIC16C71X

Applicable Devices 710 71 711 715

11.1

DC Characteristics:

PIC16C710-04 (Commercial, Industrial, Extended)

PIC16C711-04 (Commercial, Industrial, Extended)

PIC16C710-10 (Commercial, Industrial, Extended)

PIC16C711-10 (Commercial, Industrial, Extended)

PIC16C710-20 (Commercial, Industrial, Extended)

PIC16C711-20 (Commercial, Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0˚C

-40˚C

≤ TA ≤ +70˚C (commercial)

≤ TA ≤ +85˚C (industrial)

≤ TA ≤ +125˚C (extended)

DC CHARACTERISTICS

Param.

No.

Characteristic

Sym Min Typ† Max Units

Conditions

D001

D001A

Supply Voltage

VDD

4.0

4.5

-

6.0

5.5

V

XT, RC and LP osc conﬁguration

HS osc conﬁguration

D002*

D003

RAM Data Retention

Voltage (Note 1)

VDR

-

1.5

-

V

VDD start voltage to

ensure internal Power-

on Reset signal

VPOR

-

VSS

-

V

See section on Power-on Reset for details

D004*

VDD rise rate to ensure

internal Power-on Reset

signal

SVDD 0.05

-

V/ms See section on Power-on Reset for details

D005

D010

Brown-out Reset Voltage BVDD 3.7 4.0 4.3

3.7 4.0 4.4

V

BODEN conﬁguration bit is enabled

Extended Range Only

Supply Current (Note 2)

IDD

-

2.7

5

mA XT, RC osc conﬁguration

FOSC = 4 MHz, VDD = 5.5V (Note 4)

D013

D015

-

13.5 30

mA HS osc conﬁguration

FOSC = 20 MHz, VDD = 5.5V

Brown-out Reset Current ∆IBOR

300* 500 µA BOR enabled VDD = 5.0V

(Note 5)

D020

D021

D021A

D021B

Power-down Current

(Note 3)

IPD

-

10.5 42 µA VDD = 4.0V, WDT enabled, -40°C to +85°C

1.5

21

24

30

µA VDD = 4.0V, WDT disabled, -0°C to +70°C

µA VDD = 4.0V, WDT disabled, -40°C to +85°C

µA VDD = 4.0V, WDT disabled, -40°C to +125°C

D023

Brown-out Reset Current ∆IBOR

-

300* 500 µA BOR enabled VDD = 5.0V

(Note 5)

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25˚C unless otherwise stated.These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as speciﬁed.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be esti-

mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

DS30272A-page 90

1997 Microchip Technology Inc.

PIC16C71X

Applicable Devices 710 71 711 715

11.2

DC Characteristics: PIC16LC710-04 (Commercial, Industrial, Extended)

PIC16LC711-04 (Commercial, Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0˚C

-40˚C

Sym Min Typ† Max Units

≤ TA ≤ +70˚C (commercial)

≤ TA ≤ +85˚C (industrial)

≤ TA ≤ +125˚C (extended)

DC CHARACTERISTICS

Param

No.

Characteristic

Conditions

D001

Supply Voltage

Commercial/Industrial

Extended

VDD

2.5

3.0

-

6.0

V

LP, XT, RC osc conﬁguration (DC - 4 MHz)

D002*

D003

RAM Data Retention

Voltage (Note 1)

VDR

-

1.5

-

V

VDD start voltage to

ensure internal Power-

on Reset signal

VPOR

-

VSS

-

V

See section on Power-on Reset for details

D004*

VDD rise rate to ensure SVDD 0.05

-

V/ms See section on Power-on Reset for details

internal Power-on

Reset

signal

D005

D010

Brown-out Reset

Voltage

BVDD

IDD

3.7

-

4.0

2.0

4.3

3.8

V

BODEN conﬁguration bit is enabled

Supply Current

(Note 2)

mA XT, RC osc conﬁguration

FOSC = 4 MHz, VDD = 3.0V (Note 4)

D010A

D015

-

22.5 48

300* 500

µA LP osc conﬁguration

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

µA BOR enabled VDD = 5.0V

Brown-out Reset

Current (Note 5)

∆IBOR

D020

D021

D021A

D021B

D023

Power-down Current

(Note 3)

IPD

-

7.5

0.9

30

5

µA VDD = 3.0V, WDT enabled, -40°C to +85°C

µA VDD = 3.0V, WDT disabled, 0°C to +70°C

µA VDD = 3.0V, WDT disabled, -40°C to +85°C

µA VDD = 3.0V, WDT disabled, -40°C to +125°C

µA BOR enabled VDD = 5.0V

10

Brown-out Reset

Current (Note 5)

∆IBOR

300* 500

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25˚C unless otherwise stated.These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as speciﬁed.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be esti-

mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

1997 Microchip Technology Inc.

DS30272A-page 91

PIC16C71X

Applicable Devices 710 71 711 715

11.3

DC Characteristics:

PIC16C710-04 (Commercial, Industrial, Extended)

PIC16C711-04 (Commercial, Industrial, Extended)

PIC16C710-10 (Commercial, Industrial, Extended)

PIC16C711-10 (Commercial, Industrial, Extended)

PIC16C710-20 (Commercial, Industrial, Extended)

PIC16C711-20 (Commercial, Industrial, Extended)

PIC16LC710-04 (Commercial, Industrial, Extended)

PIC16LC711-04 (Commercial, Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0˚C

-40˚C

≤ TA ≤ +70˚C (commercial)

≤ TA ≤ +85˚C (industrial)

≤ TA ≤ +125˚C (extended)

DC CHARACTERISTICS

Operating voltage VDD range as described in DC spec Section 11.1 and

Section 11.2.

Param

No.

Characteristic

Sym

Min Typ Max Units

†

Conditions

Input Low Voltage

I/O ports

VIL

D030

with TTL buffer

VSS

-

0.15VDD

0.8V

0.2VDD

V

For entire VDD range

4.5 ≤ VDD ≤ 5.5V

D030A

D031

D032

with Schmitt Trigger buffer

MCLR, OSC1

(in RC mode)

D033

OSC1 (in XT, HS and LP)

Input High Voltage

I/O ports

VSS

-

0.3VDD

V

Note1

VIH

-

D040

D040A

with TTL buffer

2.0

VDD

V

4.5 ≤ VDD ≤ 5.5V

For entire VDD range

0.25VDD

+ 0.8V

0.8VDD

0.7VDD

0.9VDD

50

D041

D042

with Schmitt Trigger buffer

MCLR, RB0/INT

-

VDD

V

For entire VDD range

Note1

D042A OSC1 (XT, HS and LP)

D043

D070

OSC1 (in RC mode)

PORTB weak pull-up current

Input Leakage Current (Notes 2, 3)

I/O ports

IPURB

IIL

250 400

µA VDD = 5V, VPIN = VSS

D060

-

±1

µA Vss ≤ VPIN ≤ VDD, Pin at hi-

impedance

D061

D063

MCLR, RA4/T0CKI

OSC1

-

±5

µA Vss ≤ VPIN ≤ VDD

µA Vss ≤ VPIN ≤ VDD, XT, HS and LP

osc conﬁguration

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In RC oscillator conﬁguration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C7X be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The speciﬁed levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as current sourced by the pin.

DS30272A-page 92

1997 Microchip Technology Inc.

PIC16C71X

Applicable Devices 710 71 711 715

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0˚C

-40˚C

≤ TA ≤ +70˚C (commercial)

≤ TA ≤ +85˚C (industrial)

≤ TA ≤ +125˚C (extended)

DC CHARACTERISTICS

Operating voltage VDD range as described in DC spec Section 11.1 and

Section 11.2.

Param

No.

Characteristic

Sym

Min Typ Max Units

†

Conditions

Output Low Voltage

D080

I/O ports

VOL

-

0.6

V

IOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

IOL = 7.0 mA, VDD = 4.5V,

-40°C to +125°C

IOL = 1.6 mA, VDD = 4.5V,

-40°C to +85°C

IOL = 1.2 mA, VDD = 4.5V,

-40°C to +125°C

D080A

D083

OSC2/CLKOUT (RC osc conﬁg)

D083A

Output High Voltage

D090

I/O ports (Note 3)

VOH VDD - 0.7 -

VDD - 0.7 -

-

V

IOH = -3.0 mA, VDD = 4.5V,

-40°C to +85°C

IOH = -2.5 mA, VDD = 4.5V,

-40°C to +125°C

IOH = -1.3 mA, VDD = 4.5V,

-40°C to +85°C

IOH = -1.0 mA, VDD = 4.5V,

-40°C to +125°C

D090A

D092

OSC2/CLKOUT (RC osc conﬁg)

VDD - 0.7 -

-

D092A

D130*

VDD - 0.7 -

-

Open-Drain High Voltage

Capacitive Loading Specs on

Output Pins

VOD

-

14

RA4 pin

D100

D101

OSC2 pin

COSC2

15

50

pF In XT, HS and LP modes when

external clock is used to drive

OSC1.

All I/O pins and OSC2 (in RC mode) CIO

pF

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In RC oscillator conﬁguration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C7X be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The speciﬁed levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as current sourced by the pin.

1997 Microchip Technology Inc.

DS30272A-page 93

PIC16C71X

Applicable Devices 710 71 711 715

11.4

Timing Parameter Symbology

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase letters (pp) and their meanings:

pp

cc

T

Time

CCP1

CLKOUT

CS

osc

rd

OSC1

RD

ck

cs

di

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O port

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (Hi-impedance)

Low

Valid

L

Hi-impedance

FIGURE 11-1: LOAD CONDITIONS

Load condition 1

Load condition 2

VDD/2

RL

CL

VSS

RL = 464Ω

CL = 50 pF for all pins except OSC2

15 pF for OSC2 output

DS30272A-page 94

1997 Microchip Technology Inc.

PIC16C71X

Applicable Devices 710 71 711 715

11.5

Timing Diagrams and Speciﬁcations

FIGURE 11-2: EXTERNAL CLOCK TIMING

Q4

Q1

1

Q2

Q3

Q4

4

Q1

OSC1

3

4

2

CLKOUT

TABLE 11-2: EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter Sym Characteristic

No.

Min

Typ†

Max

Units Conditions

Fosc External CLKIN Frequency

DC

0.1

—

4

MHz XT osc mode

(Note 1)

MHz HS osc mode (-04)

MHz HS osc mode (-10)

MHz HS osc mode (-20)

kHz LP osc mode

10

20

200

4

Oscillator Frequency

(Note 1)

MHz RC osc mode

4

MHz XT osc mode

4

5

—

20

200

MHz HS osc mode

kHz LP osc mode

1

Tosc External CLKIN Period

250

100

50

—

ns

µs

ns

XT osc mode

(Note 1)

HS osc mode (-04)

HS osc mode (-10)

HS osc mode (-20)

LP osc mode

—

5

—

Oscillator Period

(Note 1)

250

—

RC osc mode

10,000

250

XT osc mode

HS osc mode (-04)

100

50

—

250

ns

HS osc mode (-10)

HS osc mode (-20)

5

—

DC

—

µs

ns

µs

ns

LP osc mode

TCY = 4/FOSC

XT oscillator

LP oscillator

HS oscillator

XT oscillator

LP oscillator

HS oscillator

2

3

TCY

Instruction Cycle Time (Note 1) 200

TosL, External Clock in (OSC1) High

TosH or Low Time

50

2.5

10

—

4

TosR, External Clock in (OSC1) Rise

TosF or Fall Time

25

50

15

—

†

Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All speciﬁed values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or higher than expected current

consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.

When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected

(has no loading) for the PIC16C710/711.

1997 Microchip Technology Inc.

DS30272A-page 95

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 11-3: CLKOUT AND I/O TIMING

Q1

Q2

Q3

Q4

OSC1

11

10

CLKOUT

13

14

12

18

19

16

I/O Pin

(input)

15

17

I/O Pin

new value

old value

(output)

20, 21

Note: Refer to Figure 11-1 for load conditions.

TABLE 11-3: CLKOUT AND I/O TIMING REQUIREMENTS

Parameter Sym

No.

Characteristic

Min

Typ†

Max

Units Conditions

10*

11*

12*

13*

14*

15*

16*

17*

TosH2ckL OSC1↑ to CLKOUT↓

TosH2ckH OSC1↑ to CLKOUT↑

—

15

5

30

ns

Note 1

30

TckR

TckF

CLKOUT rise time

CLKOUT fall time

15

5

TckL2ioV CLKOUT ↓ to Port out valid

TioV2ckH Port in valid before CLKOUT ↑

—

0.5TCY + 20

—

0.25TCY + 25

TckH2ioI

Port in hold after CLKOUT ↑

0

—

TosH2ioV OSC1↑ (Q1 cycle) to

—

80 - 100

Port out valid

18*

TosH2ioI

OSC1↑ (Q2 cycle) to

TBD

—

ns

Port input invalid (I/O in hold time)

19*

20*

TioV2osH Port input valid to OSC1↑ (I/O in setup time)

TBD

—

10

—

10

—

25

60

25

60

—

ns

TioR

Port output rise time

Port output fall time

INT pin high or low time

PIC16C710/711

PIC16LC710/711

PIC16C710/711

PIC16LC710/711

—

21*

TioF

—

22††*

23††*

Tinp

Trbp

20

RB7:RB4 change INT high or low time

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

†† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

DS30272A-page 96

1997 Microchip Technology Inc.

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Time-out

Internal

RESET

Watchdog

Timer

RESET

31

34

I/O Pins

Note: Refer to Figure 11-1 for load conditions.

FIGURE 11-5: BROWN-OUT RESET TIMING

BVDD

VDD

35

TABLE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min

Typ†

Max Units

Conditions

30

31

TmcL MCLR Pulse Width (low)

1

—

µs VDD = 5V, -40˚C to +125˚C

Twdt

Watchdog Timer Time-out Period

7*

18

33*

ms VDD = 5V, -40˚C to +125˚C

(No Prescaler)

32

33

34

Tost

Oscillation Start-up Timer Period

—

28*

—

1024TOSC

—

132*

1.1

—

TOSC = OSC1 period

Tpwrt Power up Timer Period

72

—

ms VDD = 5V, -40˚C to +125˚C

TIOZ

I/O Hi-impedance from MCLR Low

µs

or Watchdog Timer Reset

35

TBOR

Brown-out Reset pulse width

100

—

µs 3.8V ≤ VDD ≤ 4.2V

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

1997 Microchip Technology Inc.

DS30272A-page 97

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 11-6: TIMER0 EXTERNAL CLOCK TIMINGS

RA4/T0CKI

41

40

42

TMR0

Note: Refer to Figure 11-1 for load conditions.

TABLE 11-5: TIMER0 EXTERNAL CLOCK REQUIREMENTS

Param

No.

Sym

Characteristic

Min

Typ† Max Units Conditions

40

Tt0H

T0CKI High Pulse Width

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5TCY + 20*

10*

—

ns Must also meet

parameter 42

ns

41

42

Tt0L

Tt0P

T0CKI Low Pulse Width

T0CKI Period

0.5TCY + 20*

10*

ns

Must also meet

parameter 42

Greater of:

20 ns or TCY + 40*

N

ns N = prescale value

(2, 4,..., 256)

48

Tcke2tmrI Delay from external clock edge to timer increment

These parameters are characterized but not tested.

2Tosc

—

7Tosc

—

*

†

Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

DS30272A-page 98

1997 Microchip Technology Inc.

PIC16C71X

Applicable Devices 710 71 711 715

TABLE 11-6: A/D CONVERTER CHARACTERISTICS:

PIC16C710/711-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)

PIC16C710/711-10 (COMMERCIAL, INDUSTRIAL, EXTENDED)

PIC16C710/711-20 (COMMERCIAL, INDUSTRIAL, EXTENDED)

PIC16LC710/711-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)

Param Sym Characteristic

No.

Min

Typ†

Max

Units

Conditions

A01

NR Resolution

—

8-bits

< ± 1

bit VREF = VDD, VSS ≤ AIN ≤ VREF

VREF = VDD, VSS ≤ AIN ≤ VREF

VSS ≤ VAIN ≤ VREF

A02 EABS Absolute error

LSb

A03

A04

A05

EIL Integral linearity error

—

EDL Differential linearity error

EFS Full scale error

A06 EOFF Offset error

A10 Monotonicity

A20 VREF Reference voltage

< ± 1

—

LSb

—

V

—

2.5V

guaranteed

—

VDD + 0.3

VREF + 0.3

10.0

A25

A30

VAIN Analog input voltage

VSS - 0.3

—

V

ZAIN Recommended impedance of

analog voltage source

kΩ

A40

A50

IAD A/D conversion current (VDD)

—

180

—

µA Average current consumption

when A/D is on. (Note 1)

IREF VREF input current (Note 2)

10

1000

µA During VAIN acquisition.

Based on differential of VHOLD to VAIN.

To charge CHOLD see Section 7.1.

µA During A/D Conversion cycle

—

10

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: When A/D is off, it will not consume any current other than minor leakage current.

The power-down current spec includes any such leakage from the A/D module.

2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.

1997 Microchip Technology Inc.

DS30272A-page 99

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 11-7: A/D CONVERSION TIMING

BSF ADCON0, GO

(TOSC/2) ⁽¹⁾

1 Tcy

131

130

Q4

132

A/D CLK

7

6

5

4

3

2

1

0

A/D DATA

NEW_DATA

DONE

OLD_DATA

ADRES

ADIF

GO

SAMPLING STOPPED

SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

TABLE 11-7: A/D CONVERSION REQUIREMENTS

Param Sym Characteristic

No.

Min

Typ†

Max Units

Conditions

130

TAD A/D clock period PIC16C710/711

1.6

2.0

2.0*

3.0*

—

µs TOSC based, VREF ≥ 3.0V

µs TOSC based, VREF full range

µs A/D RC mode

PIC16LC710/711

PIC16C710/711

PIC16LC710/711

4.0

6.0

9.5

6.0

9.0

—

µs A/D RC mode

131

132

TCNV Conversion time

(not including S/H time). (Note 1)

TACQ Acquisition time

TAD

Note 2

5*

20

—

µs

µs The minimum time is the ampliﬁer

settling time. This may be used if the

"new" input voltage has not changed

by more than 1 LSb (i.e., 19.5 mV @

5.12V) from the last sampled voltage

(as stated on CHOLD).

134

135

TGO Q4 to AD clock start

—

TOSC/2§

—

If the A/D clock source is selected as

RC, a time of TCY is added before the

A/D clock starts. This allows the

SLEEPinstruction to be executed.

TSWC Switching from convert → sample time 1.5§

TAD

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

§

This speciﬁcation ensured by design.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 7.1 for min conditions.

DS30272A-page 100

1997 Microchip Technology Inc.

PIC16C71X

Applicable Devices 710 71 711 715

12.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C710

AND PIC16C711

The graphs and tables provided in this section are for design guidance and are not tested or guaranteed.

In some graphs or tables the data presented are outside speciﬁed operating range (i.e., outside speciﬁed VDD

range). This is for information only and devices are guaranteed to operate properly only within the speciﬁed

range.

Note: The data presented in this section is a statistical summary of data collected on units from different lots over

a period of time and matrix samples. 'Typical' represents the mean of the distribution at, 25°C, while 'max'

or 'min' represents (mean +3σ) and (mean -3σ) respectively where σ is standard deviation.

FIGURE 12-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE)

35

30

25

20

15

10

5

0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD(Volts)

FIGURE 12-2: MAXIMUM IPD vs. VDD (WDT DISABLED, RC MODE)

10.000

85°C

70°C

1.000

0.100

25°C

0°C

-40°C

0.010

0.001

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD(Volts)

1997 Microchip Technology Inc.

DS30272A-page 101

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 12-3: TYPICAL IPD vs. VDD @ 25°C

FIGURE 12-5: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD

(WDT ENABLED, RC MODE)

Cext = 22 pF,T = 25°C

6.0

25

20

15

10

5

5.5

5.0

4.5

R = 5k

4.0

3.5

3.0

R = 10k

2.5

2.0

1.5

1.0

R = 100k

0

2.5

0.5

0.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD(Volts)

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD(Volts)

Shaded area is beyond recommended range.

FIGURE 12-4: MAXIMUM IPD vs. VDD (WDT

ENABLED, RC MODE)

FIGURE 12-6: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD

35

-40°C

Cext = 100 pF,T = 25°C

30

0°C

2.4

2.2

25

20

R = 3.3k

2.0

1.8

1.6

70°C

15

R = 5k

1.4

85°C

1.2

10

1.0

R = 10k

5

0

0.8

0.6

0.4

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

R = 100k

0.2

VDD(Volts)

0.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD(Volts)

FIGURE 12-7: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD

Cext = 300 pF,T = 25°C

1000

900

800

R = 3.3k

700

600

R = 5k

500

400

R = 10k

300

200

R = 100k

5.5 6.0

100

0

2.5

3.0

3.5

4.0

4.5

5.0

VDD(Volts)

DS30272A-page 102

1997 Microchip Technology Inc.

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 12-8: TYPICAL IPD vs. VDD BROWN-

OUT DETECT ENABLED (RC

MODE)

FIGURE 12-10: TYPICAL IPD vs.TIMER1

ENABLED (32 kHz, RC0/RC1 =

33 pF/33 pF, RC MODE)

1400

1200

1000

30

25

20

15

10

5

Device NOT in

Brown-out Reset

800

600

400

200

0

Device in

Brown-out

Reset

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD(Volts)

0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

The shaded region represents the built-in hysteresis of the

brown-out reset circuitry.

VDD(Volts)

FIGURE 12-9: MAXIMUM IPD vs. VDD

BROWN-OUT DETECT

ENABLED

FIGURE 12-11: MAXIMUM IPD vs.TIMER1

ENABLED

(32 kHz, RC0/RC1 = 33 pF/33

(85°C TO -40°C, RC MODE)

pF, 85°C TO -40°C, RC MODE)

1600

1400

1200

45

40

35

30

1000

Device NOT in

Brown-out Reset

800

600

400

200

0

Device in

Brown-out

Reset

25

20

15

10

5

4.3

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD(Volts)

0

The shaded region represents the built-in hysteresis of the

brown-out reset circuitry.

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD(Volts)

1997 Microchip Technology Inc.

DS30272A-page 103

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 12-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25°C)

2000

1800

1600

1400

1200

1000

800

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

600

400

200

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

Frequency(MHz)

Shaded area is

beyond recommended range

FIGURE 12-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40°C TO 85°C)

2000

6.0V

1800

1600

1400

1200

1000

800

600

400

200

0

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

Frequency(MHz)

Shaded area is

beyond recommended range

DS30272A-page 104

1997 Microchip Technology Inc.

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 12-14: TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25°C)

1600

1400

1200

1000

800

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

600

400

200

0

200

Shaded area is

beyond recommended range

400

600

800

1000

1200

1400

1600

1800

Frequency(kHz)

FIGURE 12-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40°C TO 85°C)

1600

6.0V

5.5V

1400

1200

1000

800

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

600

400

200

0

200

Shaded area is

beyond recommended range

400

600

800

1000

1200

1400

1600

1800

Frequency(kHz)

1997 Microchip Technology Inc.

DS30272A-page 105

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 12-16: TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25°C)

1200

6.0V

5.5V

1000

800

600

400

200

0

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

0

100

200

300

400

500

600

700

Frequency(kHz)

FIGURE 12-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40°C TO 85°C)

1200

6.0V

5.5V

1000

800

600

400

200

0

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

0

100

200

300

400

500

600

700

Frequency(kHz)

DS30272A-page 106

1997 Microchip Technology Inc.

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 12-18: TYPICAL IDD vs.

CAPACITANCE @ 500 kHz

FIGURE 12-19: TRANSCONDUCTANCE(gm)

OF HS OSCILLATOR vs. VDD

(RC MODE)

600

500

400

300

200

100

4.0

Max -40°C

5.0V

3.5

3.0

4.0V

3.0V

2.5

Typ 25°C

2.0

Min 85°C

1.5

1.0

0.5

0.0

0

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

20 pF

100 pF

300 pF

VDD(Volts)

Capacitance(pF)

Shaded area is

beyond recommended range

TABLE 12-1: RC OSCILLATOR

FREQUENCIES

FIGURE 12-20: TRANSCONDUCTANCE(gm)

OF LP OSCILLATOR vs. VDD

Average

110

Cext

Rext

100

Max -40°C

Fosc @ 5V, 25°C

90

80

70

22 pF

5k

10k

100k

3.3k

5k

4.12 MHz

2.35 MHz

268 kHz

1.80 MHz

1.27 MHz

688 kHz

77.2 kHz

707 kHz

501 kHz

269 kHz

28.3 kHz

± 1.4%

60

50

40

30

20

10

0

Typ 25°C

± 1.1%

± 1.0%

± 1.2%

± 1.0%

± 1.4%

± 1.2%

± 1.6%

± 1.1%

100 pF

300 pF

10k

100k

3.3k

5k

Min 85°C

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

VDD(Volts)

Shaded areas are

beyond recommended range

10k

100k

FIGURE 12-21: TRANSCONDUCTANCE(gm)

OF XT OSCILLATOR vs. VDD

The percentage variation indicated here is part to

part variation due to normal process distribution.The

variation indicated is ±3 standard deviation from

average value for VDD = 5V.

1000

900

Max -40°C

800

700

600

500

400

300

200

100

0

Typ 25°C

Min 85°C

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

VDD(Volts)

Shaded areas are

beyond recommended range

1997 Microchip Technology Inc.

DS30272A-page 107

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 12-22: TYPICAL XTAL STARTUP

FIGURE 12-24: TYPICAL XTAL STARTUP

TIME vs. VDD (LP MODE, 25°C)

TIME vs. VDD (XT MODE, 25°C)

3.5

3.0

2.5

70

60

50

2.0

40

200 kHz, 68 pF/68 pF

32 kHz, 33 pF/33 pF

1.5

30

200 kHz, 47 pF/47 pF

20

1.0

1 MHz, 15 pF/15 pF

10

4 MHz, 15 pF/15 pF

0.5

0.0

200 kHz, 15 pF/15 pF

0

2.5

3.0

3.5

4.0

VDD(Volts)

4.5

5.0

5.5

6.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD(Volts)

FIGURE 12-23: TYPICAL XTAL STARTUP

TIME vs. VDD (HS MODE,

25°C)

TABLE 12-2: CAPACITOR SELECTION

FOR CRYSTAL

OSCILLATORS

Crystal

Freq

Cap. Range

C1

Cap. Range

C2

7

6

Osc Type

LP

32 kHz

200 kHz

1 MHz

33 pF

15 pF

33 pF

15 pF

20 MHz, 33 pF/33 pF

5

XT

HS

47-68 pF

15 pF

47-68 pF

15 pF

4

8 MHz, 33 pF/33 pF

4 MHz

15 pF

3

20 MHz, 15 pF/15 pF

4 MHz

15 pF

8 MHz, 15 pF/15 pF

2

8 MHz

15-33 pF

20 MHz

1

4.0

4.5

5.0

5.5

6.0

VDD(Volts)

Crystals

Used

32 kHz

200 kHz

1 MHz

Epson C-001R32.768K-A

STD XTL 200.000KHz

ECS ECS-10-13-1

± 20 PPM

± 50 PPM

± 30 PPM

4 MHz

ECS ECS-40-20-1

8 MHz

EPSON CA-301 8.000M-C

EPSON CA-301 20.000M-C

20 MHz

DS30272A-page 108

1997 Microchip Technology Inc.

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 12-25: TYPICAL IDD vs. FREQUENCY

FIGURE 12-27: TYPICAL IDD vs. FREQUENCY

(LP MODE, 25°C)

(XT MODE, 25°C)

1800

1600

6.0V

120

100

80

5.5V

1400

5.0V

1200

4.5V

1000

800

600

4.0V

3.5V

60

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

40

20

0

3.0V

2.5V

3.0V

2.5V

400

200

0

50

100

150

200

Frequency(kHz)

0

0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

Frequency(MHz)

FIGURE 12-26: MAXIMUM IDD vs.

FREQUENCY

FIGURE 12-28: MAXIMUM IDD vs.

FREQUENCY

(LP MODE, 85°C TO -40°C)

(XT MODE, -40°C TO 85°C)

1800

1600

1400

1200

6.0V

5.5V

5.0V

4.5V

140

120

100

80

4.0V

1000

3.5V

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

60

800

600

3.0V

40

2.5V

20

400

200

3.0V

2.5V

0

50

100

150

200

0

Frequency(kHz)

0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

Frequency(MHz)

1997 Microchip Technology Inc.

DS30272A-page 109

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 12-29: TYPICAL IDD vs. FREQUENCY

FIGURE 12-30: MAXIMUM IDD vs.

FREQUENCY

(HS MODE, 25°C)

(HS MODE, -40°C TO 85°C)

7.0

6.0

5.0

4.0

3.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

6.0V

2.0

5.5V

5.0V

4.5V

4.0V

6.0V

5.5V

5.0V

4.5V

4.0V

1.0

0.0

1

2

4

6

8

10

12

14

16

18

20

1

2

4

6

8

10

12

14

16

18

20

Frequency(MHz)

DS30272A-page 110

1997 Microchip Technology Inc.

PIC16C71X

Applicable Devices 710 71 711 715

13.0 ELECTRICAL CHARACTERISTICS FOR PIC16C715

Absolute Maximum Ratings †

Ambient temperature under bias.................................................................................................................-55 to +125˚C

Storage temperature .............................................................................................................................. -65˚C to +150˚C

Voltage on any pin with respect to VSS (except VDD and MCLR)....................................................-0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V