PIC16F83A-10I/SO_技术文档

M

PIC16F8X

18-pin Flash/EEPROM 8-Bit Microcontrollers

Devices Included in this Data Sheet:

Pin Diagrams

• PIC16F83

• PIC16F84

PDIP, SOIC

•1

RA2

RA3

18

17

16

15

14

13

12

11

10

RA1

• PIC16CR83

• PIC16CR84

• Extended voltage range devices available

(PIC16LF8X, PIC16LCR8X)

2

3

4

5

6

7

8

9

RA0

RA4/T0CKI

MCLR

VSS

OSC1/CLKIN

OSC2/CLKOUT

VDD

High Performance RISC CPU Features:

RB0/INT

RB1

RB7

RB6

• Only 35 single word instructions to learn

RB2

RB5

• All instructions single cycle except for program

branches which are two-cycle

RB3

RB4

• Operating speed: DC - 10 MHz clock input

DC - 400 ns instruction cycle

Special Microcontroller Features:

Program

Memory

(words)

Data

RAM

(bytes) (bytes)

Data

EEPROM Freq

Max.

Device

• In-Circuit Serial Programming (ICSP™) - via two

pins (ROM devices support only Data EEPROM

programming)

(MHz)

PIC16F83

PIC16F84

512 Flash

1 K Flash

36

68

36

68

64

10

• Power-on Reset (POR)

PIC16CR83 512 ROM

PIC16CR84 1 K ROM

• Power-up Timer (PWRT)

• Oscillator Start-up Timer (OST)

• 14-bit wide instructions

• 8-bit wide data path

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Code-protection

• 15 special function hardware registers

• Eight-level deep hardware stack

• Power saving SLEEP mode

• Selectable oscillator options

• Direct, indirect and relative addressing modes

• Four interrupt sources:

CMOS Flash/EEPROM Technology:

- External RB0/INT pin

- TMR0 timer overﬂow

- PORTB<7:4> interrupt on change

- Data EEPROM write complete

• Low-power, high-speed technology

• Fully static design

• Wide operating voltage range:

- Commercial: 2.0V to 6.0V

• 1000 erase/write cycles Flash program memory

- Industrial:

2.0V to 6.0V

• 10,000,000 erase/write cycles EEPROM data mem-

ory

• Low power consumption:

- < 2 mA typical @ 5V, 4 MHz

- 15 µA typical @ 2V, 32 kHz

- < 1 µA typical standby current @ 2V

• EEPROM Data Retention > 40 years

Peripheral Features:

• 13 I/O pins with individual direction control

• High current sink/source for direct LED drive

- 25 mA sink max. per pin

- 20 mA source max. per pin

• TMR0: 8-bit timer/counter with 8-bit

programmable prescaler

1998 Microchip Technology Inc.

DS30430C-page 1

PIC16F8X

Table of Contents

1.0 General Description...................................................................................................................................................................... 3

2.0 PIC16F8X Device Varieties .......................................................................................................................................................... 5

3.0 Architectural Overview.................................................................................................................................................................. 7

4.0 Memory Organization ................................................................................................................................................................. 11

5.0 I/O Ports...................................................................................................................................................................................... 21

6.0 Timer0 Module and TMR0 Register............................................................................................................................................ 27

7.0 Data EEPROM Memory.............................................................................................................................................................. 33

8.0 Special Features of the CPU ...................................................................................................................................................... 37

9.0 Instruction Set Summary ............................................................................................................................................................ 53

10.0 Development Support................................................................................................................................................................. 69

11.0 Electrical Characteristics for PIC16F83 and PIC16F84.............................................................................................................. 73

12.0 Electrical Characteristics for PIC16CR83 and PIC16CR84........................................................................................................ 85

13.0 DC & AC Characteristics Graphs/Tables.................................................................................................................................... 97

14.0 Packaging Information.............................................................................................................................................................. 109

Appendix A: Feature Improvements - From PIC16C5X To PIC16F8X .......................................................................................... 113

Appendix B: Code Compatibility - from PIC16C5X to PIC16F8X.................................................................................................. 113

Appendix C: What’s New In This Data Sheet................................................................................................................................. 114

Appendix D: What’s Changed In This Data Sheet ......................................................................................................................... 114

Appendix E: Conversion Considerations - PIC16C84 to PIC16F83/F84 And PIC16CR83/CR84.................................................. 115

Index ................................................................................................................................................................................................. 117

On-Line Support................................................................................................................................................................................. 119

Reader Response .............................................................................................................................................................................. 120

PIC16F8X Product Identification System........................................................................................................................................... 121

Sales and Support.............................................................................................................................................................................. 121

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of

time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you

ﬁnd any information that is missing or appears in error, please use the reader response form in the back of this data

sheet to inform us. We appreciate your assistance in making this a better document.

DS30430C-page 2

1998 Microchip Technology Inc.

PIC16F8X

Table 1-1 lists the features of the PIC16F8X. A simpli-

ﬁed block diagram of the PIC16F8X is shown in

Figure 3-1.

1.0

GENERAL DESCRIPTION

The PIC16F8X is a group in the PIC16CXX family of

low-cost, high-performance, CMOS, fully-static, 8-bit

microcontrollers. This group contains the following

devices:

The PIC16F8X ﬁts perfectly in applications ranging

from high speed automotive and appliance motor

control to low-power remote sensors, electronic locks,

security devices and smart cards. The Flash/EEPROM

technology makes customization of application

programs (transmitter codes, motor speeds, receiver

frequencies, security codes, etc.) extremely fast and

convenient. The small footprint packages make this

microcontroller series perfect for all applications with

space limitations. Low-cost, low-power, high

performance, ease-of-use and I/O ﬂexibility make the

PIC16F8X very versatile even in areas where no

microcontroller use has been considered before

(e.g., timer functions; serial communication; capture,

compare and PWM functions; and co-processor

applications).

• PIC16F83

• PIC16F84

• PIC16CR83

• PIC16CR84

All PICmicro™ microcontrollers employ an advanced

RISC architecture. PIC16F8X devices have enhanced

core features, eight-level deep stack, and multiple

internal and external interrupt sources. The separate

instruction and data buses of the Harvard architecture

allow a 14-bit wide instruction word with a separate

8-bit wide data bus. The two stage instruction pipeline

allows all instructions to execute in a single cycle,

except for program branches (which require two

cycles). A total of 35 instructions (reduced instruction

set) are available. Additionally, a large register set is

used to achieve a very high performance level.

The serial in-system programming feature (via two

pins) offers ﬂexibility of customizing the product after

complete assembly and testing. This feature can be

used to serialize a product, store calibration data, or

program the device with the current ﬁrmware before

shipping.

PIC16F8X microcontrollers typically achieve a 2:1 code

compression and up to a 4:1 speed improvement (at 20

MHz) over other 8-bit microcontrollers in their class.

The PIC16F8X has up to 68 bytes of RAM, 64 bytes of

Data EEPROM memory, and 13 I/O pins. A timer/

counter is also available.

1.1

Family and Upward Compatibility

Those users familiar with the PIC16C5X family of

microcontrollers will realize that this is an enhanced

version of the PIC16C5X architecture. Please refer to

Appendix A for a detailed list of enhancements. Code

written for PIC16C5X devices can be easily ported to

PIC16F8X devices (Appendix B).

The PIC16CXX family has special features to reduce

external components, thus reducing cost, enhancing

system reliability and reducing power consumption.

There are four oscillator options, of which the single pin

RC oscillator provides a low-cost solution, the LP

oscillator minimizes power consumption, XT is

a

1.2

Development Support

standard crystal, and the HS is for High Speed crystals.

The SLEEP (power-down) mode offers power saving.

The user can wake the chip from sleep through several

external and internal interrupts and resets.

The PIC16CXX family is supported by a full-featured

macro assembler, a software simulator, an in-circuit

emulator, a low-cost development programmer and a

full-featured programmer. A “C” compiler and fuzzy

logic support tools are also available.

A highly reliable Watchdog Timer with its own on-chip

RC oscillator provides protection against software lock-

up.

The devices with Flash program memory allow the

same device package to be used for prototyping and

production. In-circuit reprogrammability allows the

code to be updated without the device being removed

from the end application. This is useful in the

development of many applications where the device

may not be easily accessible, but the prototypes may

require code updates. This is also useful for remote

applications where the code may need to be updated

(such as rate information).

1998 Microchip Technology Inc.

DS30430C-page 3

PIC16F8X

TABLE 1-1

PIC16F8X FAMILY OF DEVICES

PIC16F83

PIC16CR83

PIC16F84

PIC16CR84

Maximum Frequency

of Operation (MHz)

10

Clock

Flash Program Memory

EEPROM Program Memory

ROM Program Memory

Data Memory (bytes)

512

—

1K

—

68

64

—

1K

68

64

Memory

—

512

36

64

Data EEPROM (bytes)

64

Peripherals Timer Module(s)

Interrupt Sources

I/O Pins

TMR0

4

TMR0

4

TMR0

4

TMR0

4

13

Features

Voltage Range (Volts)

Packages

2.0-6.0

18-pin DIP,

SOIC

18-pin DIP,

SOIC

18-pin DIP,

SOIC

18-pin DIP,

SOIC

All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capa-

bility. All PIC16F8X Family devices use serial programming with clock pin RB6 and data pin RB7.

DS30430C-page 4

1998 Microchip Technology Inc.

PIC16F8X

2.3

Serialized Quick-Turnaround-

Production (SQTP^SM) Devices

2.0

PIC16F8X DEVICE VARIETIES

A variety of frequency ranges and packaging options

are available. Depending on application and production

requirements the proper device option can be selected

using the information in this section. When placing

orders, please use the “PIC16F8X Product

Identiﬁcation System” at the back of this data sheet to

specify the correct part number.

Microchip offers the unique programming service

where a few user-deﬁned locations in each device are

programmed with different serial numbers. The serial

numbers

or sequential.

may

be

random,

pseudo-random

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

There are four device “types” as indicated in the device

number.

1. F, as in PIC16F84. These devices have Flash

program memory and operate over the standard

voltage range.

For information on submitting a SQTP code, please

contact your Microchip Regional Sales Ofﬁce.

2.4

ROM Devices

2. LF, as in PIC16LF84.These devices have Flash

program memory and operate over an extended

voltage range.

Some of Microchip’s devices have a corresponding

device where the program memory is a ROM. These

devices give a cost savings over Microchip’s traditional

user programmed devices (EPROM, EEPROM).

3. CR, as in PIC16CR83. These devices have

ROM program memory and operate over the

standard voltage range.

ROM devices (PIC16CR8X) do not allow serialization

information in the program memory space. The user

may program this information into the Data EEPROM.

4. LCR, as in PIC16LCR84. These devices have

ROM program memory and operate over an

extended voltage range.

For information on submitting a ROM code, please

contact your Microchip Regional Sales Ofﬁce.

When discussing memory maps and other architectural

features, the use of F and CR also implies the LF and

LCR versions.

2.1

Flash Devices

These devices are offered in the lower cost plastic

package, even though the device can be erased and

reprogrammed.This allows the same device to be used

for prototype development and pilot programs as well

as production.

A further advantage of the electrically-erasable Flash

version is that it can be erased and reprogrammed in-

circuit, or by device programmers, such as Microchip's

®

PICSTART Plus or PRO MATE II programmers.

2.2

Quick-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who choose not to program a

medium to high quantity of units and whose code

patterns have stabilized. The devices have all Flash

locations and conﬁguration options already pro-

grammed by the factory. Certain code and prototype

veriﬁcation procedures do apply before production

shipments are available.

For information on submitting a QTP code, please

contact your Microchip Regional Sales Ofﬁce.

1998 Microchip Technology Inc.

DS30430C-page 5

PIC16F8X

NOTES:

DS30430C-page 6

1998 Microchip Technology Inc.

PIC16F8X

PIC16CXX devices contain an 8-bit ALU and working

register. The ALU is a general purpose arithmetic unit.

It performs arithmetic and Boolean functions between

data in the working register and any register ﬁle.

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC16CXX family can be

attributed to number of architectural features

a

commonly found in RISC microprocessors. To begin

with, the PIC16CXX uses a Harvard architecture. This

architecture has the program and data accessed from

separate memories. So the device has a program

memory bus and a data memory bus. This improves

bandwidth over traditional von Neumann architecture

where program and data are fetched from the same

memory (accesses over the same bus). Separating

program and data memory further allows instructions

to be sized differently than the 8-bit wide data word.

PIC16CXX opcodes are 14-bits wide, enabling single

word instructions.The full 14-bit wide program memory

bus fetches a 14-bit instruction in a single cycle. A two-

stage pipeline overlaps fetch and execution of instruc-

tions (Example 3-1). Consequently, all instructions exe-

cute in a single cycle except for program branches.

The ALU is 8-bits wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the working register

(W register), and the other operand is a ﬁle register or

an immediate constant. In single operand instructions,

the operand is either the W register or a ﬁle register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register.The C and DC bits

operate as

a borrow and digit borrow out bit,

respectively, in subtraction. See the SUBLWand SUBWF

The PIC16F83 and PIC16CR83 address 512 x 14 of

program memory, and the PIC16F84 and PIC16CR84

address 1K x 14 program memory. All program mem-

ory is internal.

instructions for examples.

A simpliﬁed block diagram for the PIC16F8X is shown

in Figure 3-1, its corresponding pin description is

shown in Table 3-1.

The PIC16CXX can directly or indirectly address its

register ﬁles or data memory. All special function

registers including the program counter are mapped in

the data memory. An orthogonal (symmetrical)

instruction set makes it possible to carry out any oper-

ation on any register using any addressing mode. This

symmetrical nature and lack of ‘special optimal

situations’ make programming with the PIC16CXX

simple yet efﬁcient. In addition, the learning curve is

reduced signiﬁcantly.

1998 Microchip Technology Inc.

DS30430C-page 7

PIC16F8X

FIGURE 3-1: PIC16F8X BLOCK DIAGRAM

Data Bus

13

8

Program Counter

Flash/ROM

Program

Memory

EEPROM Data Memory

PIC16F83/CR83

512 x 14

PIC16F84/CR84

1K x 14

RAM

EEPROM

File Registers

8 Level Stack

(13-bit)

EEDATA

Data Memory

64 x 8

PIC16F83/CR83

36 x 8

PIC16F84/CR84

68 x 8

Program

Bus

14

7

RAM Addr

EEADR

Addr Mux

Instruction reg

TMR0

7

Indirect

Addr

Direct Addr

5

FSR reg

RA4/T0CKI

STATUS reg

MUX

8

Power-up

Timer

I/O Ports

8

Instruction

Decode &

Control

Oscillator

Start-up Timer

ALU

Power-on

Reset

RA3:RA0

RB7:RB1

Watchdog

Timer

Timing

Generation

W reg

RB0/INT

MCLR

OSC2/CLKOUT

OSC1/CLKIN

VDD, VSS

DS30430C-page 8

1998 Microchip Technology Inc.

PIC16F8X

TABLE 3-1

PIC16F8X PINOUT DESCRIPTION

DIP

No.

SOIC

No.

I/O/P

Type

Buffer

Type

Pin Name

Description

(3)

OSC1/CLKIN

16

15

16

15

I

ST/CMOS

—

Oscillator crystal input/external clock source input.

OSC2/CLKOUT

O

Oscillator crystal output. Connects to crystal or resonator in crystal

oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which

has 1/4 the frequency of OSC1, and denotes the instruction cycle

rate.

MCLR

4

I/P

ST

Master clear (reset) input/programming voltage input. This pin is an

active low reset to the device.

PORTA is a bi-directional I/O port.

RA0

17

18

1

17

18

1

I/O

TTL

ST

RA1

RA2

RA3

2

RA4/T0CKI

3

Can also be selected to be the clock input to the TMR0

timer/counter. Output is open drain type.

PORTB is a bi-directional I/O port. PORTB can be software pro-

grammed for internal weak pull-up on all inputs.

(1)

RB0/INT

6

7

6

7

I/O

P

TTL/ST

TTL

RB0/INT can also be selected as an external interrupt pin.

RB1

RB2

8

TTL

RB3

9

TTL

RB4

10

11

12

13

5

10

11

12

13

5

TTL

Interrupt on change pin.

RB5

TTL

Interrupt on change pin.

(2)

RB6

TTL/ST

—

Interrupt on change pin. Serial programming clock.

Interrupt on change pin. Serial programming data.

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

(2)

RB7

VSS

VDD

14

P

—

Legend: I= input

O = output

— = Not used

I/O = Input/Output

TTL = TTL input

P = power

ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

3: This buffer is a Schmitt Trigger input when conﬁgured in RC oscillator mode and a CMOS input otherwise.

1998 Microchip Technology Inc.

DS30430C-page 9

PIC16F8X

3.1

Clocking Scheme/Instruction Cycle

3.2

Instruction Flow/Pipelining

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, the

program counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The

instruction is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution ﬂow is shown in Figure 3-2.

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO)

then two cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the Program Counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register” in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Q4

PC

Internal

phase

clock

PC

PC+1

PC+2

OSC2/CLKOUT

(RC mode)

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 55h

2. MOVWF PORTB

3. CALL SUB_1

Fetch 1

Execute 1

Fetch 2

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

PORTA, BIT3

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

DS30430C-page 10

1998 Microchip Technology Inc.

PIC16F8X

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK -

4.0

MEMORY ORGANIZATION

There are two memory blocks in the PIC16F8X. These

are the program memory and the data memory. Each

block has its own bus, so that access to each block can

occur during the same oscillator cycle.

PIC16F83/CR83

PC<12:0>

13

CALL, RETURN

RETFIE, RETLW

The data memory can further be broken down into the

general purpose RAM and the Special Function

Registers (SFRs). The operation of the SFRs that

control the “core” are described here. The SFRs used

to control the peripheral modules are described in the

section discussing each individual peripheral module.

Stack Level 1

•

Stack Level 8

Reset Vector

0000h

0004h

Peripheral Interrupt Vector

The data memory area also contains the data

EEPROM memory.This memory is not directly mapped

into the data memory, but is indirectly mapped. That is,

an indirect address pointer speciﬁes the address of the

data EEPROM memory to read/write. The 64 bytes of

data EEPROM memory have the address range

0h-3Fh. More details on the EEPROM memory can be

found in Section 7.0.

1FFh

4.1

Program Memory Organization

The PIC16FXX has a 13-bit program counter capable

of addressing an 8K x 14 program memory space. For

the PIC16F83 and PIC16CR83, the ﬁrst 512 x 14

1FFFh

(0000h-01FFh)

are

physically

implemented

(Figure 4-1). For the PIC16F84 and PIC16CR84, the

ﬁrst 1K x 14 (0000h-03FFh) are physically imple-

mented (Figure 4-2). Accessing a location above the

physically implemented address will cause a wrap-

around. For example, for the PIC16F84 locations 20h,

420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h

will be the same instruction.

FIGURE 4-2: PROGRAM MEMORY MAP

AND STACK -

PIC16F84/CR84

PC<12:0>

13

CALL, RETURN

RETFIE, RETLW

Stack Level 1

The reset vector is at 0000h and the interrupt vector is

at 0004h.

•

Stack Level 8

Reset Vector

0000h

0004h

Peripheral Interrupt Vector

3FFh

1FFFh

1998 Microchip Technology Inc.

DS30430C-page 11

PIC16F8X

4.2.1

GENERAL PURPOSE REGISTER FILE

4.2

Data Memory Organization

All devices have some amount of General Purpose

Register (GPR) area. Each GPR is 8 bits wide and is

accessed either directly or indirectly through the FSR

(Section 4.5).

The data memory is partitioned into two areas.The ﬁrst

is the Special Function Registers (SFR) area, while the

second is the General Purpose Registers (GPR) area.

The SFRs control the operation of the device.

The GPR addresses in bank

addresses in bank 0. As an example, addressing loca-

tion 0Ch or 8Ch will access the same GPR.

1 are mapped to

Portions of data memory are banked. This is for both

the SFR area and the GPR area. The GPR area is

banked to allow greater than 116 bytes of general

purpose RAM.The banked areas of the SFR are for the

registers that control the peripheral functions. Banking

requires the use of control bits for bank selection.

These control bits are located in the STATUS Register.

Figure 4-1 and Figure 4-2 show the data memory map

organization.

4.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (Figure 4-1, Figure 4-2

and Table 4-1) are used by the CPU and Peripheral

functions to control the device operation. These

registers are static RAM.

Instructions MOVWFand MOVFcan move values from the

W register to any location in the register ﬁle (“F”), and

vice-versa.

The special function registers can be classiﬁed into two

sets, core and peripheral. Those associated with the

core functions are described in this section. Those

related to the operation of the peripheral features are

described in the section for that speciﬁc feature.

The entire data memory can be accessed either

directly using the absolute address of each register ﬁle

or indirectly through the File Select Register (FSR)

(Section 4.5). Indirect addressing uses the present

value of the RP1:RP0 bits for access into the banked

areas of data memory.

Data memory is partitioned into two banks which

contain the general purpose registers and the special

function registers. Bank 0 is selected by clearing the

RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank

1. Each Bank extends up to 7Fh (128 bytes). The ﬁrst

twelve locations of each Bank are reserved for the

Special Function Registers. The remainder are Gen-

eral Purpose Registers implemented as static RAM.

DS30430C-page 12

1998 Microchip Technology Inc.

PIC16F8X

FIGURE 4-1: REGISTER FILE MAP -

PIC16F83/CR83

FIGURE 4-2: REGISTER FILE MAP -

PIC16F84/CR84

File Address

00h

File Address

00h

File Address

80h

File Address

80h

(1)

Indirect addr.

01h

02h

TMR0

PCL

OPTION

PCL

81h

82h

01h

02h

TMR0

PCL

OPTION

PCL

81h

82h

03h

04h

05h

06h

STATUS

FSR

STATUS

FSR

83h

84h

85h

86h

03h

04h

05h

06h

STATUS

FSR

STATUS

FSR

83h

84h

85h

86h

PORTA

PORTB

TRISA

TRISB

PORTA

PORTB

TRISA

TRISB

07h

08h

09h

87h

88h

89h

07h

08h

09h

87h

88h

89h

EEDATA

EEADR

EECON1

EEDATA

EEADR

EECON1

(1)

EECON2

PCLATH

INTCON

0Ah

PCLATH

INTCON

PCLATH

INTCON

8Ah

0Ah

PCLATH

INTCON

8Ah

0Bh

0Ch

8Bh

8Ch

0Bh

0Ch

8Bh

8Ch

36

General

Purpose

registers

(SRAM)

Mapped

(accesses)

in Bank 0

68

General

Purpose

registers

(SRAM)

Mapped

(accesses)

in Bank 0

2Fh

30h

AFh

B0h

4Fh

50h

CFh

D0h

7Fh

FFh

7Fh

FFh

Bank 0

Bank 1

Unimplemented data memory location; read as '0'.

Note 1: Not a physical register.

Unimplemented data memory location; read as '0'.

Note 1: Not a physical register.

1998 Microchip Technology Inc.

DS30430C-page 13

PIC16F8X

TABLE 4-1

REGISTER FILE SUMMARY

Value on

Power-on

Reset

Value on all

other resets

(Note3)

Address Name

Bank 0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00h

01h

02h

INDF

TMR0

PCL

Uses contents of FSR to address data memory (not a physical register)

8-bit real-time clock/counter

---- ----

xxxx xxxx

0000 0000

---- ----

uuuu uuuu

0000 0000

Low order 8 bits of the Program Counter (PC)

(2)

TO

Indirect data memory address pointer 0

03h

04h

05h

06h

07h

08h

09h

STATUS

FSR

IRP

RP1

RP0

PD

Z

DC

C

0001 1xxx

xxxx xxxx

---x xxxx

000q quuu

uuuu uuuu

---u uuuu

uuuu uuuu

---- ----

uuuu uuuu

PORTA

PORTB

—

RA4/T0CKI

RB4

RA3

RB3

RA2

RB2

RA1

RB1

RA0

RB7

RB6

RB5

RB0/INT xxxx xxxx

---- ----

Unimplemented location, read as '0'

EEPROM data register

EEDATA

EEADR

xxxx xxxx

EEPROM address register

xxxx xxxx

(1)

0Ah

0Bh

PCLATH

INTCON

—

Write buffer for upper 5 bits of the PC

INTE RBIE T0IF

---0 0000

0000 000u

GIE

EEIE

T0IE

INTF

RBIF

0000 000x

Bank 1

80h

INDF

Uses contents of FSR to address data memory (not a physical register)

---- ----

1111 1111

---- ----

1111 1111

OPTION_

REG

81h

82h

RBPU INTEDG

T0CS

T0SE

PSA

PS2

PS1

DC

PS0

C

PCL

Low order 8 bits of Program Counter (PC)

IRP RP1 RP0 TO

Indirect data memory address pointer 0

PORTA data direction register

0000 0000

(2)

83h

84h

85h

86h

STATUS

FSR

PD

Z

0001 1xxx

xxxx xxxx

---1 1111

1111 1111

---- ----

000q quuu

uuuu uuuu

---1 1111

1111 1111

---- ----

TRISA

TRISB

—

PORTB data direction register

Unimplemented location, read as '0'

87h

88h

EECON1

EECON2

—

EEIF

WRERR

WREN

WR

RD

---0 x000

---- ----

---0 q000

---- ----

89h

EEPROM control register 2 (not a physical register)

(1)

0Ah

0Bh

PCLATH

INTCON

—

Write buffer for upper 5 bits of the PC

INTE RBIE T0IF

---0 0000

0000 000x

---0 0000

0000 000u

GIE

EEIE

T0IE

INTF

RBIF

Legend: x= unknown, u= unchanged. -= unimplemented read as '0', q= value depends on condition.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents

of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never trans-

ferred to PCLATH.

2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.

3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

DS30430C-page 14

1998 Microchip Technology Inc.

PIC16F8X

4.2.2.1

STATUS REGISTER

Only the BCF, BSF, SWAPF and MOVWF instructions

should be used to alter the STATUS register (Table 9-2)

because these instructions do not affect any status bit.

The STATUS register contains the arithmetic status of

the ALU, the RESET status and the bank select bit for

data memory.

Note 1: The IRP and RP1 bits (STATUS<7:6>) are

not used by the PIC16F8X and should be

programmed as cleared. Use of these bits

as general purpose R/W bits is NOT

recommended, since this may affect

upward compatibility with future products.

As with any register, the STATUS register can be the

destination for any instruction. If the STATUS register is

the destination for an instruction that affects the Z, DC

or C bits, then the write to these three bits is disabled.

These bits are set or cleared according to device logic.

Furthermore, the TO and PD bits are not writable.

Therefore, the result of an instruction with the STATUS

register as destination may be different than intended.

Note 2: The C and DC bits operate as a borrow

and digit borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

For example, CLRF STATUSwill clear the upper-three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

Note 3: When the STATUS register is the

destination for an instruction that affects

the Z, DC or C bits, then the write to these

three bits is disabled. The speciﬁed bit(s)

will be updated according to device logic

FIGURE 4-1: STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0

IRP

R/W-0

RP1

R/W-0

RP0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

R = Readable bit

W = Writable bit

bit7

bit0

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

IRP: Register Bank Select bit (used for indirect addressing)

0 = Bank 0, 1 (00h - FFh)

1 = Bank 2, 3 (100h - 1FFh)

The IRP bit is not used by the PIC16F8X. IRP should be maintained clear.

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

00 = Bank 0 (00h - 7Fh)

01 = Bank 1 (80h - FFh)

10 = Bank 2 (100h - 17Fh)

11 = Bank 3 (180h - 1FFh)

Each bank is 128 bytes. Only bit RP0 is used by the PIC16F8X. RP1 should be maintained clear.

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

TO: Time-out bit

1 = After power-up, CLRWDTinstruction, or SLEEPinstruction

0 = A WDT time-out occurred

PD: Power-down bit

1 = After power-up or by the CLRWDTinstruction

0 = By execution of the SLEEPinstruction

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit (for ADDWFand ADDLWinstructions) (For borrow the polarity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

C: Carry/borrow bit (for ADDWFand ADDLWinstructions)

1 = A carry-out from the most signiﬁcant bit of the result occurred

0 = No carry-out from the most signiﬁcant bit of the result occurred

Note:For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of

the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low

order bit of the source register.

1998 Microchip Technology Inc.

DS30430C-page 15

PIC16F8X

4.2.2.2

OPTION_REG REGISTER

Note: When the prescaler is assigned to

the WDT (PSA = '1'), TMR0 has a 1:1

prescaler assignment.

The OPTION_REG register is a readable and writable

register which contains various control bits to conﬁgure

the TMR0/WDT prescaler, the external INT interrupt,

TMR0, and the weak pull-ups on PORTB.

FIGURE 4-1: OPTION_REG REGISTER (ADDRESS 81h)

R/W-1

RBPU

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

R

W

U

= Readable bit

= Writable bit

= Unimplemented bit,

read as ‘0’

bit7

bit0

- n = Value at POR reset

bit 7:

RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled (by individual port latch values)

bit 6:

bit 5:

bit 4:

bit 3:

INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

PSA: Prescaler Assignment bit

1 = Prescaler assigned to the WDT

0 = Prescaler assigned to TMR0

bit 2-0: PS2:PS0: Prescaler Rate Select bits

Bit Value

TMR0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

DS30430C-page 16

1998 Microchip Technology Inc.

PIC16F8X

4.2.2.3

INTCON REGISTER

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

The INTCON register is a readable and writable

register which contains the various enable bits for all

interrupt sources.

FIGURE 4-1:

INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0

GIE

R/W-0

EEIE

R/W-0

T0IE

R/W-0

INTE

R/W-0

RBIE

R/W-0

T0IF

R/W-0

INTF

R/W-x

RBIF

R

W

U

= Readable bit

= Writable bit

= Unimplemented bit,

read as ‘0’

bit7

bit0

- n = Value at POR reset

bit 7:

GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

Note: For the operation of the interrupt structure, please refer to Section 8.5.

bit 6:

bit 5:

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt

0 = Disables the EE write complete interrupt

T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

INTE: RB0/INT Interrupt Enable bit

1 = Enables the RB0/INT interrupt

0 = Disables the RB0/INT interrupt

RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

T0IF: TMR0 overﬂow interrupt ﬂag bit

1 = TMR0 has overﬂowed (must be cleared in software)

0 = TMR0 did not overﬂow

INTF: RB0/INT Interrupt Flag bit

1 = The RB0/INT interrupt occurred

0 = The RB0/INT interrupt did not occur

RBIF: RB Port Change Interrupt Flag bit

1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

1998 Microchip Technology Inc.

DS30430C-page 17

PIC16F8X

manipulation of the PCLATH<4:3> is not required for

the return instructions (which “pops” the PC from the

stack).

4.3

Program Counter: PCL and PCLATH

The Program Counter (PC) is 13-bits wide. The low

byte is the PCL register, which is a readable and

writable register.The high byte of the PC (PC<12:8>) is

not directly readable nor writable and comes from the

PCLATH register.The PCLATH (PC latch high) register

is a holding register for PC<12:8>. The contents of

PCLATH are transferred to the upper byte of the

program counter when the PC is loaded with a new

value. This occurs during a CALL, GOTOor a write to

PCL. The high bits of PC are loaded from PCLATH as

shown in Figure 4-1.

Note: The PIC16F8X ignores the PCLATH<4:3>

bits, which are used for program memory

pages 1, 2 and 3 (0800h - 1FFFh). The

use of PCLATH<4:3> as general purpose

R/W bits is not recommended since this

may affect upward compatibility with

future products.

4.4

Stack

The PIC16FXX has an 8 deep x 13-bit wide hardware

stack (Figure 4-1). The stack space is not part of either

program or data space and the stack pointer is not

readable or writable.

FIGURE 4-1: LOADING OF PC IN

DIFFERENT SITUATIONS

PCH

PCL

12

8

7

0

The entire 13-bit PC is “pushed” onto the stack when a

CALLinstruction is executed or an interrupt is acknowl-

edged.The stack is “popped” in the event of a RETURN,

RETLW or a RETFIE instruction execution. PCLATH is

not affected by a push or a pop operation.

INST with PCL

as dest

PC

8

PCLATH<4:0>

PCLATH

5

ALU result

Note: There are no instruction mnemonics

called push or pop.These are actions that

occur from the execution of the CALL,

RETURN, RETLW, and RETFIE instruc-

tions, or the vectoring to an interrupt

address.

PCH

12 11 10

PCL

8

7

0

GOTO, CALL

PC

11

PCLATH<4:3>

PCLATH

2

Opcode <10:0>

The stack operates as a circular buffer. That is, after the

stack has been pushed eight times, the ninth push over-

writes the value that was stored from the ﬁrst push. The

tenth push overwrites the second push (and so on).

4.3.1

COMPUTED GOTO

If the stack is effectively popped nine times, the PC

value is the same as the value from the ﬁrst pop.

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL).When doing a table

read using a computed GOTO method, care should be

exercised if the table location crosses a PCL memory

boundary (each 256 word block).Refer to the application

note “Implementing a Table Read” (AN556).

Note: There are no status bits to indicate stack

overﬂow or stack underﬂow conditions.

4.3.2

PROGRAM MEMORY PAGING

The PIC16F83 and PIC16CR83 have 512 words of pro-

gram memory. The PIC16F84 and PIC16CR84 have

1K of program memory. The CALL and GOTO instruc-

tions have an 11-bit address range.This 11-bit address

range allows a branch within a 2K program memory

page size. For future PIC16F8X program memory

expansion, there must be another two bits to specify

the program memory page. These paging bits come

from the PCLATH<4:3> bits (Figure 4-1).When doing a

CALLor a GOTOinstruction, the user must ensure that

these page bits (PCLATH<4:3>) are programmed to

the desired program memory page. If a CALL instruc-

tion (or interrupt) is executed, the entire 13-bit PC is

“pushed” onto the stack (see next section). Therefore,

DS30430C-page 18

1998 Microchip Technology Inc.

PIC16F8X

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 4-2.

4.5

Indirect Addressing; INDF and FSR

Registers

The INDF register is not a physical register. Address-

ing INDF actually addresses the register whose

address is contained in the FSR register (FSR is a

pointer). This is indirect addressing.

EXAMPLE 4-2: HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

movlw 0x20 ;initialize pointer

movwf FSR

clrf

incf

;

to RAM

INDF ;clear INDF register

FSR ;inc pointer

EXAMPLE 4-1: INDIRECT ADDRESSING

• Register ﬁle 05 contains the value 10h

• Register ﬁle 06 contains the value 0Ah

• Load the value 05 into the FSR register

• A read of the INDF register will return the value of

10h

• Increment the value of the FSR register by one

(FSR = 06)

• A read of the INDF register now will return the

value of 0Ah.

goto

NEXT ;NO, clear next

CONTINUE

:

;YES, continue

An effective 9-bit address is obtained by concatenating

the 8-bit FSR register and the IRP bit (STATUS<7>), as

shown in Figure 4-1. However, IRP is not used in the

PIC16F8X.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no-operation (although STATUS bits may be affected).

FIGURE 4-1: DIRECT/INDIRECT ADDRESSING

Indirect Addressing

Direct Addressing

RP1 RP0

6

0

IRP

7

(FSR)

0

from opcode

bank select

location select

bank select

00h

location select

00

01

10

11

00h

not used not used

0Bh

0Ch

Addresses

map back

to Bank 0

(1)

Data

Memory

2Fh

30h

(3)

(2)

4Fh

50h

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

Note 1: PIC16F83 and PIC16CR83 devices.

2: PIC16F84 and PIC16CR84 devices

3: For memory map detail see Figure 4-1.

1998 Microchip Technology Inc.

DS30430C-page 19

PIC16F8X

NOTES:

DS30430C-page 20

1998 Microchip Technology Inc.

PIC16F8X

EXAMPLE 5-1: INITIALIZING PORTA

5.0

I/O PORTS

CLRF

PORTA

; Initialize PORTA by

; setting output

; data latches

The PIC16F8X has two ports, PORTA and PORTB.

Some port pins are multiplexed with an alternate func-

tion for other features on the device.

BSF

STATUS, RP0 ; Select Bank 1

MOVLW 0x0F

; Value used to

; initialize data

; direction

5.1

PORTA and TRISA Registers

PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger

input and an open drain output. All other RA port pins

have TTL input levels and full CMOS output drivers. All

pins have data direction bits (TRIS registers) which can

conﬁgure these pins as output or input.

MOVWF TRISA

; Set RA<3:0> as inputs

; RA4 as outputs

; TRISA<7:5> are always

; read as '0'.

FIGURE 5-2: BLOCK DIAGRAM OF PIN RA4

Setting a TRISA bit (=1) will make the corresponding

PORTA pin an input, i.e., put the corresponding output

driver in a hi-impedance mode. Clearing a TRISA bit

(=0) will make the corresponding PORTA pin an output,

i.e., put the contents of the output latch on the selected

pin.

Data

bus

D

Q

WR

PORT

CK

RA4 pin

N

Reading the PORTA register reads the status of the pins

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. So a write

to a port implies that the port pins are ﬁrst read, then this

value is modiﬁed and written to the port data latch.

Data Latch

VSS

D

Q

WR

TRIS

CK

The RA4 pin is multiplexed with the TMR0 clock input.

Schmitt

Trigger

input

TRIS Latch

FIGURE 5-1: BLOCK DIAGRAM OF PINS

RA3:RA0

buffer

Data

bus

RD TRIS

D

Q

D

VDD

P

WR

Port

CK

EN

RD PORT

Data Latch

N

I/O pin

TMR0 clock input

Note: I/O pin has protection diodes to VSS only.

D

Q

WR

TRIS

VSS

CK

TRIS Latch

TTL

input

buffer

RD TRIS

Q

D

EN

RD PORT

Note: I/O pins have protection diodes to VDD and VSS.

1998 Microchip Technology Inc.

DS30430C-page 21

PIC16F8X

TABLE 5-1

PORTA FUNCTIONS

Name

Bit0

Buffer Type

Function

RA0

bit0

bit1

bit2

bit3

bit4

TTL

ST

Input/output

RA1

RA2

RA3

RA4/T0CKI

Input/output or external clock input for TMR0.

Output is open drain type.

Legend: TTL = TTL input, ST = Schmitt Trigger input

TABLE 5-2

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on

Power-on

Reset

Value on all

other resets

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

05h

85h

PORTA

TRISA

—

RA4/T0CKI

TRISA4

RA3

RA2

RA1

RA0

---x xxxx

---1 1111

---u uuuu

---1 1111

TRISA3

TRISA2 TRISA1 TRISA0

Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are unimplemented, read as '0'

DS30430C-page 22

1998 Microchip Technology Inc.

PIC16F8X

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the

interrupt in the following manner:

5.2

PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The

corresponding data direction register is TRISB. A '1' on

any bit in the TRISB register puts the corresponding

output driver in a hi-impedance mode. A '0' on any bit

in the TRISB register puts the contents of the output

latch on the selected pin(s).

a) Read (or write) PORTB. This will end the mis-

match condition.

b) Clear ﬂag bit RBIF.

A mismatch condition will continue to set the RBIF bit.

Reading PORTB will end the mismatch condition, and

allow the RBIF bit to be cleared.

Each of the PORTB pins have a weak internal pull-up.

A single control bit can turn on all the pull-ups. This is

done by clearing the RBPU (OPTION_REG<7>) bit.

The weak pull-up is automatically turned off when the

port pin is conﬁgured as an output. The pull-ups are

disabled on a Power-on Reset.

This interrupt on mismatch feature, together with

software conﬁgurable pull-ups on these four pins allow

easy interface to a key pad and make it possible for

wake-up on key-depression (see AN552 in the

Embedded Control Handbook).

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins conﬁgured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

conﬁgured as an output is excluded from the interrupt

on change comparison). The pins value in input mode

are compared with the old value latched on the last

read of PORTB.The “mismatch” outputs of the pins are

OR’ed together to generate the RB port

change interrupt.

Note 1: For

a change on the I/O pin to be

recognized, the pulse width must be at

least TCY (4/fOSC) wide.

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

FIGURE 5-3: BLOCK DIAGRAM OF PINS

RB7:RB4

FIGURE 5-4: BLOCK DIAGRAM OF PINS

RB3:RB0

VDD

RBPU⁽¹⁾

VDD

weak

P

RBPU⁽¹⁾

weak

P

pull-up

Data Latch

Data bus

pull-up

Data Latch

Data bus

D

Q

I/O

D

Q

pin⁽²⁾

WR Port

CK

TRIS Latch

I/O

pin⁽²⁾

WR Port

CK

TRIS Latch

D

Q

TTL

Input

Buffer

WR TRIS

D

Q

CK

WR TRIS

TTL

CK

Input

Buffer

RD TRIS

RD Port

Q

D

Latch

RD TRIS

RD Port

Q

D

EN

Set RBIF

RB0/INT

Schmitt Trigger

Buffer

RD Port

From other

RB7:RB4 pins

Q

D

Note 1: TRISB = '1' enables weak pull-up

(if RBPU = '0' in the OPTION_REG register).

EN

2: I/O pins have diode protection to VDD and VSS.

RD Port

Note 1: TRISB = '1' enables weak pull-up

(if RBPU = '0' in the OPTION_REG register).

2: I/O pins have diode protection to VDD and VSS.

1998 Microchip Technology Inc.

DS30430C-page 23

PIC16F8X

EXAMPLE 5-1: INITIALIZING PORTB

CLRF

PORTB

; Initialize PORTB by

; setting output

; data latches

BSF

STATUS, RP0 ; Select Bank 1

MOVLW 0xCF

; Value used to

; initialize data

; direction

MOVWF TRISB

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

TABLE 5-3

PORTB FUNCTIONS

Name

Bit

Buffer Type

I/O Consistency Function

(1)

RB0/INT

bit0

TTL/ST

Input/output pin or external interrupt input. Internal software

programmable weak pull-up.

RB1

RB2

RB3

RB4

bit1

bit2

bit3

bit4

TTL

Input/output pin. Internal software programmable weak pull-up.

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up.

RB5

RB6

RB7

bit5

bit6

bit7

TTL

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up.

(2)

TTL/ST

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming clock.

(2)

TTL/ST

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Trigger.

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

TABLE 5-4

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on

Power-on

Reset

Value on all

other resets

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

06h

86h

PORTB

TRISB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT xxxx xxxx

uuuu uuuu

1111 1111

TRISB7 TRISB6 TRISB5

TRISB4

TRISB3

TRISB2 TRISB1 TRISB0

1111 1111

OPTION_

REG

1111 1111

81h

RBPU INTEDG T0CS

T0SE

PSA

PS2 PS1 PS0

Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.

DS30430C-page 24

1998 Microchip Technology Inc.

PIC16F8X

5.3.2

SUCCESSIVE OPERATIONS ON I/O

PORTS

5.3

I/O Programming Considerations

5.3.1

BI-DIRECTIONAL I/O PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle

(Figure 5-5). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should be

such that the pin voltage stabilizes (load dependent)

before the next instruction which causes that ﬁle to be

read into the CPU is executed. Otherwise, the previous

state of that pin may be read into the CPU rather than

the new state. When in doubt, it is better to separate

these instructions with a NOPor another instruction not

accessing this I/O port.

Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF

instructions, for example, read the register into the

CPU, execute the bit operation and write the result back

to the register. Caution must be used when these

instructions are applied to a port with both inputs and

outputs deﬁned. For example, a BSFoperation on bit5

of PORTB will cause all eight bits of PORTB to be read

into the CPU. Then the BSF operation takes place on

bit5 and PORTB is written to the output latches. If

another bit of PORTB is used as a bi-directional I/O pin

(i.e., bit0) and it is deﬁned as an input at this time, the

input signal present on the pin itself would be read into

the CPU and rewritten to the data latch of this particular

pin, overwriting the previous content. As long as the pin

stays in the input mode, no problem occurs. However,

if bit0 is switched into output mode later on, the content

of the data latch is unknown.

Example 5-1 shows the effect of two sequential

read-modify-write instructions (e.g., BCF, BSF, etc.) on

an I/O port.

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN

Reading the port register, reads the values of the port

pins. Writing to the port register writes the value to the

port latch. When using read-modify-write instructions

(i.e., BCF, BSF, etc.) on a port, the value of the port pins

is read, the desired operation is done to this value, and

this value is then written to the port latch.

I/O PORT

;Initial PORT settings: PORTB<7:4> Inputs

;

PORTB<3:0> Outputs

;PORTB<7:6> have external pull-ups and are

;not connected to other circuitry

;

PORT latch PORT pins

---------- ---------

A pin actively outputting a Low or High should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wired-and”).

The resulting high output current may damage the chip.

BCF PORTB, 7

BCF PORTB, 6

BSF STATUS, RP0

BCF TRISB, 7

BCF TRISB, 6

; 01pp ppp

; 10pp ppp

;

11pp ppp

; 10pp ppp

11pp ppp

10pp ppp

;

;Note that the user may have expected the

;pin values to be 00pp ppp. The 2nd BCF

;caused RB7 to be latched as the pin value

;(high).

FIGURE 5-5: SUCCESSIVE I/O OPERATION

Q4

Q1 Q2

Q4

Q3

Q1 Q2

PC

Q1 Q2

Note:

This example shows a write to PORTB

followed by a read from PORTB.

PC + 3

NOP

PC

Instruction

fetched

PC + 1

PC + 2

NOP

MOVWF PORTB MOVF PORTB,W

write to

PORTB

Note that:

data setup time = (0.25TCY - TPD)

RB7:RB0

where TCY = instruction cycle

TPD = propagation delay

Port pin

sampled here

TPD

Therefore, at higher clock frequencies,

a write followed by a read may be

problematic.

Instruction

executed

NOP

MOVWF PORTB

write to

MOVF PORTB,W

PORTB

1998 Microchip Technology Inc.

DS30430C-page 25

PIC16F8X

NOTES:

DS30430C-page 26

1998 Microchip Technology Inc.

PIC16F8X

edge select bit, T0SE (OPTION_REG<4>). Clearing bit

T0SE selects the rising edge. Restrictions on the exter-

nal clock input are discussed in detail in Section 6.2.

6.0

TIMER0 MODULE AND TMR0

REGISTER

The Timer0 module timer/counter has the following

features:

The prescaler is shared between the Timer0 Module

and the Watchdog Timer. The prescaler assignment is

controlled, in software, by control bit PSA

(OPTION_REG<3>). Clearing bit PSA will assign the

prescaler to the Timer0 Module. The prescaler is not

readable or writable. When the prescaler (Section 6.3)

is assigned to the Timer0 Module, the prescale value

(1:2, 1:4, ..., 1:256) is software selectable.

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overﬂow from FFh to 00h

• Edge select for external clock

6.1

TMR0 Interrupt

Timer mode is selected by clearing the T0CS bit

(OPTION_REG<5>). In timer mode, the Timer0 mod-

ule (Figure 6-1) will increment every instruction cycle

(without prescaler). If the TMR0 register is written, the

increment is inhibited for the following two cycles

(Figure 6-2 and Figure 6-3). The user can work around

this by writing an adjusted value to the TMR0 register.

The TMR0 interrupt is generated when the TMR0

register overﬂows from FFh to 00h. This overﬂow sets

the T0IF bit (INTCON<2>). The interrupt can be

masked by clearing enable bit T0IE (INTCON<5>).The

T0IF bit must be cleared in software by the Timer0

Module interrupt service routine before re-enabling this

interrupt.The TMR0 interrupt (Figure 6-4) cannot wake

the processor from SLEEP since the timer is shut off

during SLEEP.

Counter mode is selected by setting the T0CS bit

(OPTION_REG<5>). In this mode TMR0 will increment

either on every rising or falling edge of pin RA4/T0CKI.

The incrementing edge is determined by the T0 source

FIGURE 6-1: TMR0 BLOCK DIAGRAM

Data bus

FOSC/4

0

1

PSout

8

1

0

Sync with

Internal

clocks

TMR0 register

RA4/T0CKI

Programmable

Prescaler

PSout

(2 cycle delay)

T0SE

3

Set bit T0IF

on Overﬂow

PS2, PS1, PS0

PSA

T0CS

Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION_REG register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-6)

FIGURE 6-2: TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC-1

PC

PC+1

PC+2

PC+4

PC

PC+3

PC+5

PC+6

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

MOVWF TMR0

Instruction

Fetch

MOVF TMR0,W

T0

TMR0

T0+1

T0+2

NT0

T0

NT0+1

NT0+2

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

1998 Microchip Technology Inc.

DS30430C-page 27

PIC16F8X

FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

PC

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

MOVWF TMR0

Instruction

Fetch

T0

T0+1

NT0+1

NT0

TMR0

Instruction

Execute

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

Write TMR0

executed

FIGURE 6-4: TMR0 INTERRUPT TIMING

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

OSC1

CLKOUT⁽³⁾

TMR0 timer

FEh

1

FFh

1

00h

01h

02h

4

T0IF bit

(INTCON<2>)

GIE bit

(INTCON<7>)

Interrupt Latency⁽²⁾

PC +1

INSTRUCTION FLOW

PC

PC +1

0004h

0005h

Instruction

fetched

Inst (PC)

Inst (PC+1)

Inst (0004h)

Dummy cycle

Inst (0005h)

Inst (0004h)

Instruction

executed

Inst (PC-1)

Dummy cycle

Inst (PC)

Note 1: T0IF interrupt ﬂag is sampled here (every Q1).

2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time.

3: CLKOUT is available only in RC oscillator mode.

4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit.

The TMR0 register will roll over 3 Tosc cycles later.

DS30430C-page 28

1998 Microchip Technology Inc.

PIC16F8X

6.2.2

TMR0 INCREMENT DELAY

6.2

Using TMR0 with External Clock

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

Module is actually incremented. Figure 6-5 shows the

delay from the external clock edge to the timer

incrementing.

When an external clock input is used for TMR0, it must

meet certain requirements. The external clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing

of

the

TMR0

register

after

synchronization.

6.3

Prescaler

6.2.1

EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of pin RA4/T0CKI with the internal phase clocks is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-5). Therefore, it is necessary for T0CKI to be

high for at least 2Tosc (plus a small RC delay) and low

for at least 2Tosc (plus a small RC delay). Refer to the

electrical speciﬁcation of the desired device.

An 8-bit counter is available as a prescaler for the

Timer0 Module, or as a postscaler for the Watchdog

Timer (Figure 6-6). For simplicity, this counter is being

referred to as “prescaler” throughout this data sheet.

Note that there is only one prescaler available which is

mutually exclusive between the Timer0 Module and the

Watchdog Timer. Thus, a prescaler assignment for the

Timer0 Module means that there is no prescaler for the

Watchdog Timer, and vice-versa.

When a prescaler is used, the external clock input is

divided by an asynchronous ripple counter type

prescaler so that the prescaler output is symmetrical.

For the external clock to meet the sampling

requirement, the ripple counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4Tosc (plus a small RC delay) divided

by the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the

minimum pulse width requirement of 10 ns. Refer to

parameters 40, 41 and 42 in the AC Electrical

Speciﬁcations of the desired device.

The PSA and PS2:PS0 bits (OPTION_REG<3:0>)

determine the prescaler assignment and prescale ratio.

When assigned to the Timer0 Module, all instructions

writing to the Timer0 Module (e.g., CLRF 1, MOVWF 1,

BSF 1,x ....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer. The

prescaler is not readable or writable.

1998 Microchip Technology Inc.

DS30430C-page 29

PIC16F8X

FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Ext. Clock Input or

Prescaler Out (Note 2)

(Note 3)

Ext. Clock/Prescaler

Output After Sampling

Increment TMR0 (Q4)

TMR0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on TMR0 input = ± 4Tosc max.

2: External clock if no prescaler selected, Prescaler output otherwise.

3: The arrows ↑ indicate where sampling occurs. A small clock pulse may be missed by sampling.

FIGURE 6-6: BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER

Data Bus

CLKOUT (= Fosc/4)

8

M

U

X

1

0

1

M

U

X

RA4/T0CKI

SYNC

2

Cycles

TMR0 register

T0SE

T0CS

Set bit T0IF

on overﬂow

PSA

0

1

8-bit Prescaler

M

U

X

Watchdog

Timer

8

8 - to - 1MUX

PS2:PS0

PSA

1

0

WDT Enable bit

M U X

PSA

WDT

time-out

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION_REG register.

DS30430C-page 30

1998 Microchip Technology Inc.

PIC16F8X

6.3.1

SWITCHING PRESCALER ASSIGNMENT

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0→WDT)

The prescaler assignment is fully under software

control (i.e., it can be changed “on the ﬂy” during

program execution).

BCF

CLRF

STATUS, RP0 ;Bank 0

TMR0 ;Clear TMR0

; and Prescaler

STATUS, RP0 ;Bank 1

;Clears WDT

b'xxxx1xxx' ;Select new

BSF

Note: To avoid an unintended device RESET, the

CLRWDT

MOVLW

MOVWF

BCF

following

instruction

sequence

(Example 6-1) must be executed when

changing the prescaler assignment from

Timer0 to the WDT. This sequence must

be taken even if the WDT is disabled. To

change prescaler from the WDT to the

Timer0 module use the sequence shown in

Example 6-2.

OPTION_REG

; prescale value

STATUS, RP0 ;Bank 0

EXAMPLE 6-2: CHANGING PRESCALER

(WDT→TIMER0)

CLRWDT

;Clear WDT and

; prescaler

BSF

STATUS, RP0 ;Bank 1

MOVLW

b'xxxx0xxx' ;Select TMR0, new

; prescale value

’ and clock source

MOVWF

BCF

OPTION_REG

STATUS, RP0 ;Bank 0

;

TABLE 6-1

REGISTERS ASSOCIATED WITH TIMER0

Value on

Power-on

Reset

Value on all

other resets

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h

0Bh

TMR0

Timer0 module’s register

xxxx xxxx

0000 000x

uuuu uuuu

0000 0000

INTCON

GIE

EEIE

T0IE

INTE

RBIE

T0IF

PS2

INTF

PS1

RBIF

PS0

OPTION_

REG

1111 1111

---1 1111

81h

85h

RBPU INTEDG

T0CS

—

T0SE

PSA

TRISA

—

TRISA4

TRISA3

TRISA2 TRISA1 TRISA0

---1 1111

Legend: x= unknown, u= unchanged. -= unimplemented read as '0'. Shaded cells are not associated with Timer0.

1998 Microchip Technology Inc.

DS30430C-page 31

PIC16F8X

NOTES:

DS30430C-page 32

1998 Microchip Technology Inc.

PIC16F8X

data memory is rated for high erase/write cycles. The

write time is controlled by an on-chip timer. The write-

time will vary with voltage and temperature as well as

from chip to chip. Please refer to AC speciﬁcations for

exact limits.

7.0

DATA EEPROM MEMORY

The EEPROM data memory is readable and writable

during normal operation (full VDD range). This memory

is not directly mapped in the register ﬁle space. Instead

it is indirectly addressed through the Special Function

Registers. There are four SFRs used to read and write

this memory. These registers are:

When the device is code protected, the CPU may

continue to read and write the data EEPROM memory.

The device programmer can no longer access

this memory.

• EECON1

• EECON2

• EEDATA

• EEADR

7.1

EEADR

The EEADR register can address up to a maximum of

256 bytes of data EEPROM. Only the ﬁrst 64 bytes of

data EEPROM are implemented.

EEDATA holds the 8-bit data for read/write, and EEADR

holds the address of the EEPROM location being

accessed. PIC16F8X devices have 64 bytes of data

EEPROM with an address range from 0h to 3Fh.

The upper two bits are address decoded. This means

that these two bits must always be '0' to ensure that the

address is in the 64 byte memory space.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the new data (erase before write).The EEPROM

FIGURE 7-1: EECON1 REGISTER (ADDRESS 88h)

U

—

U

R/W-0

EEIF

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-x

RD

—

WRERR

R

W

S

= Readable bit

= Writable bit

= Settable bit

bit7

bit0

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:5 Unimplemented: Read as '0'

bit 4

EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation is not complete or has not been started

bit 3

WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated

(any MCLR reset or any WDT reset during normal operation)

0 = The write operation completed

bit 2

bit 1

WREN: EEPROM Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the data EEPROM

WR: Write Control bit

1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only

be set (not cleared) in software.

0 = Write cycle to the data EEPROM is complete

bit 0

RD: Read Control bit

1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only

be set (not cleared) in software).

0 = Does not initiate an EEPROM read

1998 Microchip Technology Inc.

DS30430C-page 33

PIC16F8X

7.2

EECON1 and EECON2 Registers

7.4

Writing to the EEPROM Data Memory

EECON1 is the control register with ﬁve low order bits

physically implemented. The upper-three bits are non-

existent and read as '0's.

To write an EEPROM data location, the user must ﬁrst

write the address to the EEADR register and the data

to the EEDATA register. Then the user must follow a

speciﬁc sequence to initiate the write for each byte.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software.They are cleared in hardware at completion of

the read or write operation.The inability to clear the WR

bit in software prevents the accidental, premature ter-

mination of a write operation.

EXAMPLE 7-1: DATA EEPROM WRITE

BSF

STATUS, RP0 ; Bank 1

BCF

BSF

INTCON, GIE ; Disable INTs.

EECON1, WREN ; Enable Write

MOVLW

MOVWF

MOVLW

MOVWF

BSF

55h

EECON2

AAh

EECON2

EECON1,WR

;

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear.The WRERR bit is

set when a write operation is interrupted by a MCLR

reset or a WDT time-out reset during normal operation.

In these situations, following reset, the user can check

the WRERR bit and rewrite the location. The data and

address will be unchanged in the EEDATA and

EEADR registers.

; Write 55h

;

; Write AAh

; Set WR bit

;

begin write

BSF

INTCON, GIE ; Enable INTs.

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment.

Interrupt ﬂag bit EEIF is set when write is complete. It

must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all '0's. The EECON2 register is used

exclusively in the Data EEPROM write sequence.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware

7.3

Reading the EEPROM Data Memory

To read a data memory location, the user must write

the address to the EEADR register and then set control

bit RD (EECON1<0>).The data is available, in the very

next cycle, in the EEDATA register; therefore it can be

read in the next instruction. EEDATA will hold this value

until another read or until it is written to by the user

(during a write operation).

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle.The WR bit will

be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. EEIF must be

cleared by software.

EXAMPLE 7-1: DATA EEPROM READ

BCF

STATUS, RP0 ; Bank 0

MOVLW

MOVWF

BSF

BCF

CONFIG_ADDR

EEADR

STATUS, RP0 ; Bank 1

EECON1, RD ; EE Read

STATUS, RP0 ; Bank 0

EEDATA, W ; W = EEDATA

;

; Address to read

MOVF

DS30430C-page 34

1998 Microchip Technology Inc.

PIC16F8X

GOTO WRITE_ERR

:

; NO, Write error

; YES, Good write

; Continue program

7.5

Write Verify

Depending on the application, good programming

practice may dictate that the value written to the Data

EEPROM should be veriﬁed (Example 7-1) to the

desired value to be written. This should be used in

applications where an EEPROM bit will be stressed

near the speciﬁcation limit. The Total Endurance disk

will help determine your comfort level.

7.6

Protection Against Spurious Writes

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built in. On power-up, WREN is cleared. Also, the

Power-up Timer (72 ms duration) prevents

EEPROM write.

Generally the EEPROM write failure will be a bit which

was written as a '1', but reads back as a '0' (due to

leakage off the bit).

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch, or software malfunction.

EXAMPLE 7-1: WRITE VERIFY

BCF

:

STATUS, RP0 ; Bank 0

; Any code can go here

7.7

Data EEPROM Operation during Code

Protect

;

MOVF EEDATA, W

; Must be in Bank 0

When the device is code protected, the CPU is able to

read and write unscrambled data to the Data

EEPROM.

BSF

BCF

STATUS, RP0 ; Bank 1

READ

EECON1, RD ; YES, Read the

;

value written

For ROM devices, there are two code protection bits

(Section 8.1). One for the ROM program memory and

one for the Data EEPROM memory.

STATUS, RP0 ; Bank 0

;

; Is the value written (in W reg) and

;

read (in EEDATA) the same?

SUBWF EEDATA, W

BTFSS STATUS, Z

;

; Is difference 0?

TABLE 7-1

REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Value on

Power-on

Reset

Value on all

other resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

08h

09h

88h

89h

EEDATA EEPROM data register

xxxx xxxx

---0 x000

---- ----

uuuu uuuu

---0 q000

---- ----

EEADR

EEPROM address register

EECON1

—

EEIF

WRERR

WREN

WR

RD

EECON2 EEPROM control register 2

Legend: x= unknown, u= unchanged, -= unimplemented read as '0', q= value depends upon condition. Shaded cells are not

used by Data EEPROM.

1998 Microchip Technology Inc.

DS30430C-page 35

PIC16F8X

NOTES:

DS30430C-page 36

1998 Microchip Technology Inc.

PIC16F8X

8.1

Conﬁguration Bits

8.0

SPECIAL FEATURES OF THE

CPU

The conﬁguration bits can be programmed (read as '0')

or left unprogrammed (read as '1') to select various

device conﬁgurations. These bits are mapped in

program memory location 2007h.

What sets

a

microcontroller apart from other

processors are special circuits to deal with the needs of

real time applications. The PIC16F8X has a host of

such features intended to maximize system reliability,

minimize cost through elimination of external

components, provide power saving operating modes

and offer code protection. These features are:

Address 2007h is beyond the user program memory

space and it belongs to the special test/conﬁguration

memory space (2000h - 3FFFh). This space can only

be accessed during programming.

• OSC Selection

To ﬁnd out how to program the PIC16C84, refer to

PIC16C84 EEPROM Memory Programming Speciﬁca-

tion (DS30189).

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-circuit serial programming

The PIC16F8X has a Watchdog Timer which can be

shut off only through conﬁguration bits. It runs off its

own RC oscillator for added reliability. There are two

timers that offer necessary delays on power-up. One is

the Oscillator Start-up Timer (OST), intended to keep

the chip in reset until the crystal oscillator is stable.The

other is the Power-up Timer (PWRT), which provides a

ﬁxed delay of 72 ms (nominal) on power-up only. This

design keeps the device in reset while the power supply

stabilizes. With these two timers on-chip, most

applications need no external reset circuitry.

SLEEP mode offers a very low current power-down

mode. The user can wake-up from SLEEP through

external reset, Watchdog Timer time-out or through an

interrupt. Several oscillator options are provided to

allow the part to ﬁt the application. The RC oscillator

option saves system cost while the LP crystal option

saves power. A set of conﬁguration bits are used to

select the various options.

1998 Microchip Technology Inc.

DS30430C-page 37

PIC16F8X

FIGURE 8-1: CONFIGURATION WORD - PIC16CR83 AND PIC16CR84

R-u

CP

R-u

CP

R-u

CP

R-u

CP

R-u

CP

R-u R/P-u R-u

CP DP CP

R-u

CP

R-u

CP

R-u

PWRTE WDTE FOSC1 FOSC0

bit0

bit13

R

P

= Readable bit

= Programmable bit

- n = Value at POR reset

u = unchanged

bit 13:8 CP: Program Memory Code Protection bit

1 = Code protection off

0 = Program memory is code protected

bit 7

DP: Data Memory Code Protection bit

1 = Code protection off

0 = Data memory is code protected

bit 6:4 CP: Program Memory Code Protection bit

1 = Code protection off

0 = Program memory is code protected

bit 3

bit 2

PWRTE: Power-up Timer Enable bit

1 = Power-up timer is disabled

0 = Power-up timer is enabled

WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1:0 FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator

FIGURE 8-2: CONFIGURATION WORD - PIC16F83 AND PIC16F84

R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u

R/P-u

R/P-u R/P-u

R/P-u

CP

PWRTE WDTE FOSC1 FOSC0

bit0

bit13

R

P

= Readable bit

= Programmable bit

- n = Value at POR reset

u = unchanged

bit 13:4 CP: Code Protection bit

1 = Code protection off

0 = All memory is code protected

bit 3

bit 2

PWRTE: Power-up Timer Enable bit

1 = Power-up timer is disabled

0 = Power-up timer is enabled

WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1:0 FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator

DS30430C-page 38

1998 Microchip Technology Inc.

PIC16F8X

8.2

Oscillator Conﬁgurations

TABLE 8-1

CAPACITOR SELECTION

FOR CERAMIC RESONATORS

8.2.1

OSCILLATOR TYPES

Ranges Tested:

Mode

The PIC16F8X can be operated in four different

oscillator modes. The user can program two

conﬁguration bits (FOSC1 and FOSC0) to select one of

these four modes:

Freq

OSC1/C1

OSC2/C2

XT

455 kHz

2.0 MHz

4.0 MHz

47 - 100 pF 47 - 100 pF

15 - 33 pF 15 - 33 pF

• LP

• XT

• HS

• RC

Low Power Crystal

Crystal/Resonator

HS

8.0 MHz

15 - 33 pF 15 - 33 pF

10.0 MHz

High Speed Crystal/Resonator

Resistor/Capacitor

Note: Recommended values of C1 and C2 are identical to

the ranges tested table.

8.2.2

CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

Higher capacitance increases the stability of the

oscillator but also increases the start-up time.

These values are for design guidance only. Since

each resonator has its own characteristics, the user

should consult the resonator manufacturer for the

appropriate values of external components.

In XT, LP or HS modes a crystal or ceramic resonator

is connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 8-3).

Resonators Tested:

FIGURE 8-3: CRYSTAL/CERAMIC

RESONATOR OPERATION

(HS, XT OR LP OSC

455 kHz

2.0 MHz

4.0 MHz

8.0 MHz

10.0 MHz

Panasonic EFO-A455K04B ± 0.3%

Murata Erie CSA2.00MG

Murata Erie CSA4.00MG

Murata Erie CSA8.00MT

± 0.5%

CONFIGURATION)

(1)

C1

OSC1

Murata Erie CSA10.00MTZ ± 0.5%

None of the resonators had built-in capacitors.

To

internal

logic

TABLE 8-2

CAPACITOR SELECTION

XTAL

(3)

RF

FOR CRYSTAL OSCILLATOR

OSC2

SLEEP

PIC16FXX

(2)

RS

Mode

Freq

OSC1/C1

OSC2/C2

(1)

C2

LP

32 kHz

200 kHz

68 - 100 pF

15 - 33 pF

68 - 100 pF

15 - 33 pF

Note1: See Table 8-1 for recommended values of

C1 and C2.

XT

HS

100 kHz

2 MHz

4 MHz

100 - 150 pF 100 - 150 pF

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF varies with the crystal chosen.

15 - 33 pF

4 MHz

10 MHz

15 - 33 pF

The PIC16F8X oscillator design requires the use of a

parallel cut crystal. Use of a series cut crystal may give

Note: Higher capacitance increases the stability of

oscillator but also increases the start-up time.

These values are for design guidance only. Rs may

be required in HS mode as well as XT mode to

avoid overdriving crystals with low drive level spec-

iﬁcation. Since each crystal has its own characteris-

tics, the user should consult the crystal

a

frequency out of the crystal manufacturers

speciﬁcations.When in XT, LP or HS modes, the device

can have an external clock source to drive the

OSC1/CLKIN pin (Figure 8-4).

manufacturer for appropriate values of external

components.

FIGURE 8-4: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP

For VDD > 4.5V, C1 = C2 ≈ 30 pF is recommended.

Crystals Tested:

OSC CONFIGURATION)

32.768 kHz Epson C-001R32.768K-A ± 20 PPM

OSC1

OSC2

Clock from

ext. system

100 kHz

200 kHz

1.0 MHz

2.0 MHz

4.0 MHz

10.0 MHz

Epson C-2 100.00 KC-P ± 20 PPM

PIC16FXX

STD XTL 200.000 KHz

ECS ECS-10-13-2

ECS ECS-20-S-2

ECS ECS-40-S-4

ECS ECS-100-S-4

± 20 PPM

± 50 PPM

Open

1998 Microchip Technology Inc.

DS30430C-page 39

PIC16F8X

8.2.3

EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

8.2.4

RC OSCILLATOR

For timing insensitive applications the RC device option

offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the

resistor (Rext) values, capacitor (Cext) values, and the

operating temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal

process parameter variation. Furthermore, the

difference in lead frame capacitance between package

types also affects the oscillation frequency, especially

for low Cext values. The user needs to take into

account variation due to tolerance of the external

R and C components. Figure 8-7 shows how an R/C

combination is connected to the PIC16F8X. For Rext

values below 4 kΩ, the oscillator operation may

become unstable, or stop completely. For very high

Rext values (e.g., 1 MΩ), the oscillator becomes

sensitive to noise, humidity and leakage. Thus, we

recommend keeping Rext between 5 kΩ and 100 kΩ.

Either a prepackaged oscillator can be used or a simple

oscillator circuit with TTL gates can be built.

Prepackaged oscillators provide

a wide operating

range and better stability. A well-designed crystal

oscillator will provide good performance with TTL

gates. Two types of crystal oscillator circuits are

available; one with series resonance, and one with

parallel resonance.

Figure 8-5 shows a parallel resonant oscillator circuit.

The circuit is designed to use the fundamental

frequency of the crystal.The 74AS04 inverter performs

the 180-degree phase shift that a parallel oscillator

requires. The 4.7 kΩ resistor provides negative

feedback for stability. The 10 kΩ potentiometer biases

the 74AS04 in the linear region. This could be used for

external oscillator designs.

Although the oscillator will operate with no external

capacitor (Cext = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With little

or no external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package lead frame capacitance.

FIGURE 8-5: EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

+5V

To Other

Devices

PIC16FXX

10k

74AS04

4.7k

See the electrical speciﬁcation section for RC

frequency variation from part to part due to normal

process variation. The variation is larger for larger R

(since leakage current variation will affect RC

frequency more for large R) and for smaller C (since

variation of input capacitance has a greater affect on

RC frequency).

CLKIN

74AS04

10k

XTAL

10k

See the electrical speciﬁcation section for variation of

oscillator frequency due to VDD for given Rext/Cext

values as well as frequency variation due to

operating temperature.

20 pF

Figure 8-6 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a

180-degree phase shift. The 330 kΩ resistors provide

the negative feedback to bias the inverters in their

linear region.

The oscillator frequency, divided by 4, is available on

the OSC2/CLKOUT pin, and can be used for test

purposes or to synchronize other logic (see Figure 3-2

for waveform).

FIGURE 8-7: RC OSCILLATOR MODE

VDD

FIGURE 8-6: EXTERNAL SERIES

RESONANT CRYSTAL

Rext

Internal

OSC1

OSCILLATOR CIRCUIT

clock

Cext

VSS

PIC16FXX

To Other

Devices

330 kΩ

PIC16FXX

OSC2/CLKOUT

74AS04

Fosc/4

CLKIN

Recommended values: 5 kΩ ≤ Rext ≤ 100 kΩ

0.1 µF

Cext > 20pF

XTAL

Note: When the device oscillator is in RC mode,

do not drive the OSC1 pin with an external

clock or you may damage the device.

DS30430C-page 40

1998 Microchip Technology Inc.

PIC16F8X

Some registers are not affected in any reset condition;

their status is unknown on a POR reset and unchanged

in any other reset. Most other registers are reset to a

“reset state” on POR, MCLR or WDT reset during

normal operation and on MCLR reset during SLEEP.

They are not affected by a WDT reset during SLEEP,

since this reset is viewed as the resumption of normal

operation.

8.3

Reset

The PIC16F8X differentiates between various kinds

of reset:

• Power-on Reset (POR)

• MCLR reset during normal operation

• MCLR reset during SLEEP

• WDT Reset (during normal operation)

• WDT Wake-up (during SLEEP)

Table 8-3 gives a description of reset conditions for the

program counter (PC) and the STATUS register.

Table 8-4 gives a full description of reset states for all

registers.

Figure 8-8 shows a simpliﬁed block diagram of the

on-chip reset circuit. The MCLR reset path has a noise

ﬁlter to ignore small pulses. The electrical speciﬁca-

tions state the pulse width requirements for the MCLR

pin.

The TO and PD bits are set or cleared differently in dif-

ferent reset situations (Section 8.7). These bits are

used in software to determine the nature of the reset.

FIGURE 8-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR

SLEEP

WDT

Module

Time_Out

Reset

VDD rise

detect

S

R

Power_on_Reset

VDD

OST/PWRT

OST

Chip_Reset

Q

10-bit Ripple counter

OSC1/

CLKIN

PWRT

On-chip

(1)

RC OSC

Enable PWRT

Enable OST

See Table 8-5

Note 1: This is a separate oscillator from the

RC oscillator of the CLKIN pin.

1998 Microchip Technology Inc.

DS30430C-page 41

PIC16F8X

TABLE 8-3

RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER

Program Counter

STATUS Register

Condition

Power-on Reset

000h

PC + 1

0001 1xxx

000u uuuu

0001 0uuu

0000 1uuu

uuu0 0uuu

MCLR Reset during normal operation

MCLR Reset during SLEEP

WDT Reset (during normal operation)

WDT Wake-up

(1)

Interrupt wake-up from SLEEP

PC + 1

uuu1 0uuu

Legend: u= unchanged, x= unknown.

Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

TABLE 8-4

Register

RESET CONDITIONS FOR ALL REGISTERS

MCLR Reset during:

Wake-up from SLEEP:

– through interrupt

– through WDT Time-out

– normal operation

– SLEEP

Address

Power-on Reset

WDT Reset during nor-

mal operation

W

—

xxxx xxxx

---- ----

xxxx xxxx

0000h

uuuu uuuu

---- ----

uuuu uuuu

0000h

uuuu uuuu

---- ----

uuuu uuuu

INDF

00h

01h

02h

03h

04h

05h

06h

08h

09h

0Ah

0Bh

80h

81h

82h

83h

84h

85h

86h

88h

89h

8Ah

8Bh

TMR0

(2)

PCL

PC + 1

(3)

STATUS

FSR

0001 1xxx

xxxx xxxx

---x xxxx

xxxx xxxx

---0 0000

0000 000x

---- ----

1111 1111

0000h

000q quuu

uuuq quuu

uuuu uuuu

---u uuuu

uuuu uuuu

---0 0000

0000 000u

---- ----

1111 1111

0000h

uuuu uuuu

---u uuuu

uuuu uuuu

---u uuuu

PORTA

PORTB

EEDATA

EEADR

PCLATH

INTCON

INDF

(1)

uuuu uuuu

---- ----

uuuu uuuu

PC + 1

OPTION_REG

PCL

(3)

STATUS

FSR

0001 1xxx

xxxx xxxx

---1 1111

1111 1111

---0 x000

---- ----

---0 0000

0000 000x

000q quuu

uuuq quuu

uuuu uuuu

---1 1111

1111 1111

---0 q000

---- ----

---0 0000

0000 000u

uuuu uuuu

---u uuuu

uuuu uuuu

---0 uuuu

---- ----

---u uuuu

TRISA

TRISB

EECON1

EECON2

PCLATH

INTCON

(1)

uuuu uuuu

Legend: u = unchanged,

x = unknown, -= unimplemented bit read as '0',

q= value depends on condition.

Note 1: One or more bits in INTCON will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: Table 8-3 lists the reset value for each speciﬁc condition.

DS30430C-page 42

1998 Microchip Technology Inc.

PIC16F8X

8.4

Power-on Reset (POR)

FIGURE 8-9: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.2V - 1.7V). To

take advantage of the POR, just tie the MCLR pin

directly (or through a resistor) to VDD.This will eliminate

external RC components usually needed to create

Power-on Reset. A minimum rise time for VDD must be

met for this to operate properly. See Electrical Speciﬁ-

cations for details.

VDD

D

R

R1

MCLR

PIC16FXX

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature, ...) must be meet to ensure

operation. If these conditions are not met, the device

must be held in reset until the operating conditions

are met.

C

Note 1: External Power-on Reset circuit is required

only if VDD power-up rate is too slow. The

diode D helps discharge the capacitor

quickly when VDD powers down.

For additional information, refer to Application Note

AN607, "Power-up Trouble Shooting."

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not exceed

0.2V (max leakage current spec on MCLR

pin is 5 µA). A larger voltage drop will

degrade VIH level on the MCLR pin.

The POR circuit does not produce an internal reset

when VDD declines.

8.5

Power-up Timer (PWRT)

3: R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR from external

The Power-up Timer (PWRT) provides a ﬁxed 72 ms

nominal time-out (TPWRT) from POR (Figure 8-10,

Figure 8-11, Figure 8-12 and Figure 8-13). The

Power-up Timer operates on an internal RC oscillator.

The chip is kept in reset as long as the PWRT is active.

The PWRT delay allows the VDD to rise to an accept-

able level (Possible exception shown in Figure 8-13).

capacitor C in the event of an MCLR pin

breakdown due to ESD or EOS.

A conﬁguration bit, PWRTE, can enable/disable the

PWRT. See either Figure 8-1 or Figure 8-2 for the oper-

ation of the PWRTE bit for a particular device.

The power-up time delay TPWRT will vary from chip to

chip due to VDD, temperature, and process variation.

See DC parameters for details.

8.6

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle delay (from OSC1 input) after the

PWRT delay ends (Figure 8-10, Figure 8-11,

Figure 8-12 and Figure 8-13). This ensures the crystal

oscillator or resonator has started and stabilized.

The OST time-out (TOST) is invoked only for XT, LP and

HS modes and only on Power-on Reset or wake-up

from SLEEP.

When VDD rises very slowly, it is possible that the

TPWRT time-out and TOST time-out will expire before

VDD has reached its ﬁnal value. In this case

(Figure 8-13), an external power-on reset circuit may

be necessary (Figure 8-9).

1998 Microchip Technology Inc.

DS30430C-page 43

PIC16F8X

FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

DS30430C-page 44

1998 Microchip Technology Inc.

PIC16F8X

FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLRTIED TO VDD): SLOW VDD RISETIME

V1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD

has reached its ﬁnal value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

1998 Microchip Technology Inc.

DS30430C-page 45

PIC16F8X

8.7

Time-out Sequence and Power-down

Status Bits (TO/PD)

8.8

Reset on Brown-Out

A brown-out is a condition where device power (VDD)

dips below its minimum value, but not to zero, and then

recovers. The device should be reset in the event of a

brown-out.

On power-up (Figure 8-10, Figure 8-11, Figure 8-12

and Figure 8-13) the time-out sequence is as follows:

First PWRT time-out is invoked after a POR has

expired. Then the OST is activated. The total time-out

will vary based on oscillator conﬁguration and PWRTE

conﬁguration bit status. For example, in RC mode with

the PWRT disabled, there will be no time-out at all.

To reset a PIC16F8X device when a brown-out occurs,

external brown-out protection circuits may be built, as

shown in Figure 8-14 and Figure 8-15.

FIGURE 8-14: BROWN-OUT PROTECTION

CIRCUIT 1

TABLE 8-5

TIME-OUT IN VARIOUS

SITUATIONS

VDD

Oscillator

Power-up

Wake-up

Conﬁguration

from

SLEEP

PWRT

Enabled

PWRT

Disabled

VDD

33k

XT, HS, LP

RC

72 ms +

1024TOSC

—

1024TOSC

10k

MCLR

72 ms

—

40k

PIC16F8X

Since the time-outs occur from the POR reset pulse, if

MCLR is kept low long enough, the time-outs will

expire. Then bringing MCLR high, execution will begin

immediately (Figure 8-10). This is useful for testing

purposes or to synchronize more than one PIC16F8X

device when operating in parallel.

This circuit will activate reset when VDD goes below

(Vz + 0.7V) where Vz = Zener voltage.

Table 8-6 shows the signiﬁcance of the TO and PD bits.

Table 8-3 lists the reset conditions for some special

registers, while Table 8-4 lists the reset conditions for

all the registers.

FIGURE 8-15: BROWN-OUT PROTECTION

CIRCUIT 2

TABLE 8-6

STATUS BITS AND THEIR

SIGNIFICANCE

VDD

R1

TO

PD

Condition

Q1

1

0

x

0

1

x

0

1

0

1

0

Power-on Reset

MCLR

Illegal, TO is set on POR

R2

40k

PIC16F8X

Illegal, PD is set on POR

WDT Reset (during normal operation)

WDT Wake-up

MCLR Reset during normal operation

MCLR Reset during SLEEP or interrupt

wake-up from SLEEP

This brown-out circuit is less expensive, although less

accurate. Transistor Q1 turns off when VDD is below a

certain level such that:

R1

= 0.7V

VDD •

R1 + R2

DS30430C-page 46

1998 Microchip Technology Inc.

PIC16F8X

The RB0/INT pin interrupt, the RB port change inter-

rupt and the TMR0 overﬂow interrupt ﬂags are con-

tained in the INTCON register.

8.9

Interrupts

The PIC16F8X has 4 sources of interrupt:

• External interrupt RB0/INT pin

When an interrupt is responded to; the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. For external interrupt events, such as the

RB0/INT pin or PORTB change interrupt, the interrupt

latency will be three to four instruction cycles.The exact

latency depends when the interrupt event occurs

(Figure 8-17).The latency is the same for both one and

two cycle instructions. Once in the interrupt service

routine the source(s) of the interrupt can be determined

by polling the interrupt ﬂag bits. The interrupt ﬂag bit(s)

must be cleared in software before re-enabling

interrupts to avoid inﬁnite interrupt requests.

• TMR0 overﬂow interrupt

• PORTB change interrupts (pins RB7:RB4)

• Data EEPROM write complete interrupt

The interrupt control register (INTCON) records

individual interrupt requests in ﬂag bits. It also contains

the individual and global interrupt enable bits.

The global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. Bit GIE is cleared on reset.

The “return from interrupt” instruction, RETFIE, exits

interrupt routine as well as sets the GIE bit, which

re-enable interrupts.

Note 1: Individual interrupt ﬂag bits are set

regardless of the status of their

corresponding mask bit or the GIE bit.

FIGURE 8-16: INTERRUPT LOGIC

Wake-up

(If in SLEEP mode)

T0IF

T0IE

INTF

INTE

Interrupt to CPU

RBIF

RBIE

EEIF

EEIE

GIE

1998 Microchip Technology Inc.

DS30430C-page 47

PIC16F8X

FIGURE 8-17: INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT

3

4

INT pin

1

Interrupt Latency

INTF ﬂag

(INTCON<1>)

5

2

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

PC

0004h

PC+1

—

0005h

PC

Instruction

fetched

Inst (PC)

Inst (PC+1)

Inst (PC)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

executed

Dummy Cycle

Inst (PC-1)

Note

1: INTF ﬂag is sampled here (every Q1).

2: Interrupt latency = 3-4Tcy where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

8.9.1

INT INTERRUPT

8.9.3

PORT RB INTERRUPT

External interrupt on RB0/INT pin is edge triggered:

either rising if INTEDG bit (OPTION_REG<6>) is set,

or falling, if INTEDG bit is clear. When a valid edge

appears on the RB0/INT pin, the INTF bit

(INTCON<1>) is set. This interrupt can be disabled by

clearing control bit INTE (INTCON<4>). Flag bit INTF

must be cleared in software via the interrupt service

routine before re-enabling this interrupt. The INT

interrupt can wake the processor from SLEEP

(Section 8.12) only if the INTE bit was set prior to going

into SLEEP. The status of the GIE bit decides whether

the processor branches to the interrupt vector

following wake-up.

An input change on PORTB<7:4> sets ﬂag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit RBIE (INTCON<3>)

(Section 5.2).

Note 1: For

a change on the I/O pin to be

recognized, the pulse width must be at

least TCY wide.

8.9.2

TMR0 INTERRUPT

An overﬂow (FFh → 00h) in TMR0 will set ﬂag bit T0IF

(INTCON<2>). The interrupt can be enabled/disabled

by setting/clearing enable bit T0IE (INTCON<5>)

(Section 6.0).

DS30430C-page 48

1998 Microchip Technology Inc.

PIC16F8X

Example 8-1 does the following:

8.10

Context Saving During Interrupts

a) Stores the W register.

During an interrupt, only the return PC value is saved

on the stack. Typically, users wish to save key register

values during an interrupt (e.g., W register and STATUS

register). This is implemented in software.

b) Stores the STATUS register in STATUS_TEMP.

c) Executes the Interrupt Service Routine code.

d) Restores the STATUS (and bank select bit)

register.

Example 8-1 stores and restores the STATUS and W

register’s values.The User deﬁned registers, W_TEMP

and STATUS_TEMP are the temporary storage

locations for the W and STATUS registers values.

e) Restores the W register.

EXAMPLE 8-1: SAVING STATUS AND W REGISTERS IN RAM

PUSH

MOVWF

SWAPF

MOVWF

:

W_TEMP

STATUS, W

STATUS_TEMP

; Copy W to TEMP register,

; Swap status to be saved into W

; Save status to STATUS_TEMP register

:

ISR

:

; Interrupt Service Routine

:

;

should configure Bank as required

POP

SWAPF

STATUS_TEMP, W ; Swap nibbles in STATUS_TEMP register

; and place result into W

MOVWF

STATUS

; Move W into STATUS register

(sets bank to original state)

;

SWAPF

W_TEMP, F

W_TEMP, W

; Swap nibbles in W_TEMP and place result in W_TEMP

; Swap nibbles in W_TEMP and place result into W

1998 Microchip Technology Inc.

DS30430C-page 49

PIC16F8X

part (see DC specs). If longer time-out periods are

desired, a prescaler with a division ratio of up to 1:128

can be assigned to the WDT under software control by

writing to the OPTION_REG register. Thus, time-out

periods up to 2.3 seconds can be realized.

8.11

Watchdog Timer (WDT)

The Watchdog Timer is a free running on-chip RC

oscillator which does not require any external

components. This RC oscillator is separate from the

RC oscillator of the OSC1/CLKIN pin. That means that

the WDT will run even if the clock on the OSC1/CLKIN

and OSC2/CLKOUT pins of the device has been

The CLRWDTand SLEEPinstructions clear the WDT and

the postscaler (if assigned to the WDT) and prevent it

from timing out and generating

RESET condition.

a

device

stopped, for example, by execution of

a SLEEP

instruction. During normal operation a WDT time-out

generates a device RESET. If the device is in SLEEP

mode, a WDT Wake-up causes the device to wake-up

and continue with normal operation. The WDT can be

permanently disabled by programming conﬁguration bit

WDTE as a '0' (Section 8.1).

The TO bit in the STATUS register will be cleared upon

a WDT time-out.

8.11.2 WDT PROGRAMMING CONSIDERATIONS

It should also be taken into account that under worst

case conditions (VDD = Min., Temperature = Max., max.

WDT prescaler) it may take several seconds before a

WDT time-out occurs.

8.11.1 WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). The time-out periods vary with

temperature, VDD and process variations from part to

FIGURE 8-18: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source

(Figure 6-6)

0

M

U

X

Postscaler

8

1

WDT Timer

•

PS2:PS0

To TMR0 (Figure 6-6)

PSA

8 - to -1 MUX

PSA

WDT

Enable Bit

•

1

0

MUX

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION_REG register.

TABLE 8-7

SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Value on

Power-on

Reset

Value on all

other resets

Address Name

Bit 7

(2)

Bit 6

(2)

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

2007h

81h

Conﬁg. bits

(2)

PWRTE⁽¹⁾

PSA

WDTE

PS2

FOSC1

PS1

FOSC0

PS0

(2)

OPTION_

REG

1111 1111

RBPU INTEDG

T0CS

T0SE

Legend: x= unknown. Shaded cells are not used by the WDT.

Note 1: See Figure 8-1 and Figure 8-2 for operation of the PWRTE bit.

2: See Figure 8-1, Figure 8-2 and Section 8.13 for operation of the Code and Data protection bits.

DS30430C-page 50

1998 Microchip Technology Inc.

PIC16F8X

8.12.2 WAKE-UP FROM SLEEP

8.12

Power-down Mode (SLEEP)

The device can wake-up from SLEEP through one of

the following events:

A device may be powered down (SLEEP) and later

powered up (Wake-up from SLEEP).

1. External reset input on MCLR pin.

2. WDT Wake-up (if WDT was enabled).

8.12.1 SLEEP

The Power-down mode is entered by executing the

SLEEPinstruction.

3. Interrupt from RB0/INT pin, RB port change, or

data EEPROM write complete.

If enabled, the Watchdog Timer is cleared (but keeps

running), the PD bit (STATUS<3>) is cleared, the TO bit

(STATUS<4>) is set, and the oscillator driver is turned

off. The I/O ports maintain the status they had before

the SLEEPinstruction was executed (driving high, low,

or hi-impedance).

Peripherals cannot generate interrupts during SLEEP,

since no on-chip Q clocks are present.

The ﬁrst event (MCLR reset) will cause a device reset.

The two latter events are considered a continuation of

program execution.The TO and PD bits can be used to

determine the cause of a device reset. The PD bit,

which is set on power-up, is cleared when SLEEP is

invoked. The TO bit is cleared if a WDT time-out

occurred (and caused wake-up).

For the lowest current consumption in SLEEP mode,

place all I/O pins at either at VDD or VSS, with no

external circuitry drawing current from the I/O pins, and

disable external clocks. I/O pins that are hi-impedance

inputs should be pulled high or low externally to avoid

switching currents caused by ﬂoating inputs. The

T0CKI input should also be at VDD or VSS. The

contribution from on-chip pull-ups on PORTB should be

considered.

While the SLEEPinstruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up

occurs regardless of the state of the GIE bit. If the GIE

bit is clear (disabled), the device continues execution at

the instruction after the SLEEPinstruction. If the GIE bit

is set (enabled), the device executes the instruction

after the SLEEP instruction and then branches to the

interrupt address (0004h). In cases where the

execution of the instruction following SLEEP is not

desirable, the user should have a NOP after the

SLEEPinstruction.

The MCLR pin must be at a logic high level (VIHMC).

It should be noted that a RESET generated by a WDT

time-out does not drive the MCLR pin low.

FIGURE 8-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

TOST(2)

INTF ﬂag

(INTCON<1>)

Interrupt Latency

(Note 2)

GIE bit

(INTCON<7>)

Processor in

SLEEP

INSTRUCTION FLOW

PC

PC+1

PC+2

PC + 2

0004h

0005h

Instruction

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = SLEEP

Inst(PC - 1)

fetched

Instruction

executed

Dummy cycle

SLEEP

Inst(PC + 1)

Inst(0004h)

Note 1: XT, HS or LP oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.

3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

1998 Microchip Technology Inc.

DS30430C-page 51

PIC16F8X

8.12.3 WAKE-UP USING INTERRUPTS

8.15

In-Circuit Serial Programming

microcontrollers can be

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt ﬂag bit set, one of the following will occur:

PIC16F8X

serially

programmed while in the end application circuit.This is

simply done with two lines for clock and data, and three

other lines for power, ground, and the programming

voltage. Customers can manufacture boards with

unprogrammed devices, and then program the

microcontroller just before shipping the product,

allowing the most recent ﬁrmware or custom ﬁrmware

to be programmed.

• If the interrupt occurs before the execution of a

SLEEPinstruction, the SLEEPinstruction will com-

plete as a NOP. Therefore, the WDT and WDT

postscaler will not be cleared, the TO bit will not

be set and PD bits will not be cleared.

• If the interrupt occurs during or after the execu-

tion of a SLEEPinstruction, the device will immedi-

ately wake up from sleep. The SLEEPinstruction

will be completely executed before the wake-up.

Therefore, the WDT and WDT postscaler will be

cleared, the TO bit will be set and the PD bit will

be cleared.

The device is placed into a program/verify mode by

holding the RB6 and RB7 pins low, while raising the

MCLR pin from VIL to VIHH (see programming

speciﬁcation). RB6 becomes the programming clock

and RB7 becomes the programming data. Both RB6

and RB7 are Schmitt Trigger inputs in this mode.

After reset, to place the device into programming/verify

mode, the program counter (PC) points to location 00h.

A 6-bit command is then supplied to the device, 14-bits

of program data is then supplied to or from the device,

using load or read-type instructions. For complete

details of serial programming, please refer to the

PIC16CXX Programming Speciﬁcations (Literature

#DS30189).

Even if the ﬂag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes.To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEPinstruction was

executed as a NOP.

To ensure that the WDT is cleared, a CLRWDTinstruc-

tion should be executed before a SLEEPinstruction.

FIGURE 8-20: TYPICAL IN-SYSTEM SERIAL

PROGRAMMING

8.13

Program Veriﬁcation/Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out for veriﬁcation purposes.

CONNECTION

To Normal

Note: Microchip does not recommend code pro-

Connections

External

Connector

Signals

tecting widowed devices.

PIC16FXX

8.14

ID Locations

+5V

0V

VDD

VSS

Four memory locations (2000h - 2003h) are designated

as ID locations to store checksum or other code

identiﬁcation numbers. These locations are not

accessible during normal execution but are readable

and writable only during program/verify. Only the

4 least signiﬁcant bits of ID location are usable.

VPP

MCLR/VPP

RB6

RB7

CLK

Data I/O

For ROM devices, these values are submitted along

with the ROM code.

VDD

To Normal

Connections

For ROM devices, both the program memory and Data

EEPROM memory may be read, but only the Data

EEPROM memory may be programmed.

DS30430C-page 52

1998 Microchip Technology Inc.

PIC16F8X

The instruction set is highly orthogonal and is grouped

into three basic categories:

9.0

INSTRUCTION SET SUMMARY

Each PIC16CXX instruction is a 14-bit word divided

into an OPCODE which speciﬁes the instruction type

and one or more operands which further specify the

operation of the instruction. The PIC16CXX instruction

set summary in Table 9-2 lists byte-oriented, bit-ori-

ented, and literal and control operations. Table 9-1

shows the opcode ﬁeld descriptions.

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the pro-

gram counter is changed as a result of an instruction.

In this case, the execution takes two instruction cycles

with the second cycle executed as a NOP. One instruc-

tion cycle consists of four oscillator periods. Thus, for

an oscillator frequency of 4 MHz, the normal instruction

execution time is 1 µs. If a conditional test is true or the

program counter is changed as a result of an instruc-

tion, the instruction execution time is 2 µs.

For byte-oriented instructions, 'f' represents a ﬁle reg-

ister designator and 'd' represents a destination desig-

nator. The ﬁle register designator speciﬁes which ﬁle

register is to be used by the instruction.

The destination designator speciﬁes where the result of

the operation is to be placed. If 'd' is zero, the result is

placed in the W register. If 'd' is one, the result is placed

in the ﬁle register speciﬁed in the instruction.

Table 9-2 lists the instructions recognized by the

MPASM assembler.

For bit-oriented instructions, 'b' represents a bit ﬁeld

designator which selects the number of the bit affected

by the operation, while 'f' represents the number of the

ﬁle in which the bit is located.

Figure 9-1 shows the general formats that the instruc-

tions can have.

Note: To maintain upward compatibility with

future PIC16CXX products, do not use the

OPTIONand TRISinstructions.

For literal and control operations, 'k' represents an

eight or eleven bit constant or literal value.

TABLE 9-1

OPCODE FIELD

DESCRIPTIONS

All examples use the following format to represent a

hexadecimal number:

0xhh

Field

Description

where h signiﬁes a hexadecimal digit.

f

W

b

k

x

Register ﬁle address (0x00 to 0x7F)

Working register (accumulator)

Bit address within an 8-bit ﬁle register

Literal ﬁeld, constant data or label

Don't care location (= 0 or 1)

FIGURE 9-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented ﬁle register operations

13

8

7

6

0

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

OPCODE

d

f (FILE #)

d = 0 for destination W

d = 1 for destination f

f = 7-bit ﬁle register address

d

Destination select; d = 0: store result in W,

d = 1: store result in ﬁle register f.

Default is d = 1

label

TOS

Label name

Top of Stack

Bit-oriented ﬁle register operations

13 10 9

b (BIT #)

7

6

PC

Program Counter

OPCODE

f (FILE #)

PCLATH

Program Counter High Latch

Global Interrupt Enable bit

Watchdog Timer/Counter

Time-out bit

b = 3-bit bit address

f = 7-bit ﬁle register address

GIE

WDT

TO

Literal and control operations

PD

Power-down bit

dest

Destination either the W register or the speciﬁed

register ﬁle location

General

13

8

7

0

[ ]

( )

→

Options

Contents

OPCODE

k (literal)

k = 8-bit immediate value

Assigned to

Register bit ﬁeld

In the set of

< >

CALLand GOTOinstructions only

13 11 10

OPCODE

k = 11-bit immediate value

User deﬁned term (font is courier)

italics

k (literal)

1998 Microchip Technology Inc.

DS30430C-page 53

PIC16F8X

TABLE 9-2

PIC16FXX INSTRUCTION SET

Mnemonic,

Operands

Description

Cycles

14-Bit Opcode

Status

Affected

Notes

MSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

LSb

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

1

1(2)

1

1(2)

1

00

0111 dfff ffff C,DC,Z

1,2

2

0101 dfff ffff

0001 lfff ffff

0001 0xxx xxxx

1001 dfff ffff

0011 dfff ffff

1011 dfff ffff

1010 dfff ffff

1111 dfff ffff

0100 dfff ffff

1000 dfff ffff

0000 lfff ffff

0000 0xx0 0000

1101 dfff ffff

1100 dfff ffff

Z

-

f, d

f

1,2

1,2,3

1,2

1,2,3

1,2

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

DECFSZ

INCF

Z

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

Z

Move W to f

No Operation

-

f, d

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

C

1,2

0010 dfff ffff C,DC,Z

1110 dfff ffff

0110 dfff ffff

Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

1 (2)

01 00bb bfff ffff

01 01bb bfff ffff

01 10bb bfff ffff

01 11bb bfff ffff

1,2

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

-

k

-

k

-

k

Add literal and W

AND literal with W

Call subroutine

1

2

1

2

1

2

1

11 111x kkkk kkkk C,DC,Z

11 1001 kkkk kkkk

10 0kkk kkkk kkkk

Z

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into standby mode

Subtract W from literal

Exclusive OR literal with W

00 0000 0110 0100 TO,PD

10 1kkk kkkk kkkk

11 1000 kkkk kkkk

11 00xx kkkk kkkk

00 0000 0000 1001

11 01xx kkkk kkkk

00 0000 0000 1000

Z

00 0000 0110 0011 TO,PD

11 110x kkkk kkkk C,DC,Z

11 1010 kkkk kkkk

Z

Note 1: When an I/O register is modiﬁed as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven low by an external

device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

DS30430C-page 54

1998 Microchip Technology Inc.

PIC16F8X

9.1

Instruction Descriptions

Add Literal and W

ANDLW

AND Literal with W

ADDLW

Syntax:

[label] ANDLW

k

Syntax:

[label] ADDLW

0 ≤ k ≤ 255

k

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

Operands:

Operation:

Status Affected:

Encoding:

Description:

(W) .AND. (k) → (W)

(W) + k → (W)

C, DC, Z

Z

11

1001

kkkk

11

111x

kkkk

The contents of W register are

AND’ed with the eight bit literal 'k'.The

result is placed in the W register.

The contents of the W register are

added to the eight bit literal 'k' and the

result is placed in the W register.

Words:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal "k"

Process

data

Write to

W

Decode

Read

literal 'k'

Process

data

Write to

W

ANDLW

0x5F

ADDLW

0x15

Example

Example:

Before Instruction

W

=

0xA3

0x03

W

=

0x10

0x25

After Instruction

W

=

W

=

ADDWF

Syntax:

Add W and f

ANDWF

Syntax:

AND W with f

[label] ADDWF f,d

[label] ANDWF f,d

Operands:

0 ≤ f ≤ 127

Operands:

0 ≤ f ≤ 127

d

[0,1]

d

[0,1]

Operation:

(W) + (f) → (destination)

Operation:

(W) .AND. (f) → (destination)

Status Affected:

Encoding:

C, DC, Z

Status Affected:

Encoding:

Z

00

0111

dfff

ffff

00

0101

dfff

ffff

Add the contents of the W register with

register 'f'. If 'd' is 0 the result is stored

in the W register. If 'd' is 1 the result is

stored back in register 'f'.

AND the W register with register 'f'. If 'd'

is 0 the result is stored in the W regis-

ter. If 'd' is 1 the result is stored back in

register 'f'.

Description:

Words:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write to

destination

Decode

Read

register

'f'

Process

data

Write to

destination

ADDWF

FSR,

0

ANDWF

FSR, 1

Example

Before Instruction

W

FSR =

=

0x17

0xC2

W

FSR =

=

0x17

0xC2

After Instruction

W

FSR =

=

0xD9

0xC2

W

FSR =

=

0x17

0x02

1998 Microchip Technology Inc.

DS30430C-page 55

PIC16F8X

BCF

Bit Clear f

BTFSC

Bit Test, Skip if Clear

Syntax:

Operands:

[label] BCF f,b

Syntax:

[label] BTFSC f,b

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation:

Status Affected:

Encoding:

0 → (f<b>)

Operation:

skip if (f<b>) = 0

None

Status Affected:

Encoding:

01

00bb

bfff

ffff

01

10bb

bfff

ffff

If bit 'b' in register 'f' is '1' then the next

instruction is executed.

If bit 'b', in register 'f', is '0' then the next

instruction is discarded, and a NOP is

executed instead, making this a 2TCY

instruction.

Description:

Words:

Bit 'b' in register 'f' is cleared.

Description:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write

register 'f'

Words:

1

Cycles:

1(2)

Q Cycle Activity:

Q1

Q2

Q3

Q4

BCF

FLAG_REG, 7

Example

Decode

Read

Process No-Operat

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

register 'f'

data

ion

If Skip:

(2nd Cycle)

Q1

Q2

Q3

Q4

No-Operati No-Opera No-Operat

on tion ion

No-Operat

ion

HERE

FALSE

TRUE

BTFSC FLAG,1

Example

GOTO

PROCESS_CODE

•

Before Instruction

PC

=

address HERE

After Instruction

if FLAG<1> = 0,

BSF

Bit Set f

PC =

address TRUE

Syntax:

Operands:

[label] BSF f,b

if FLAG<1>=1,

PC =

address FALSE

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation:

Status Affected:

Encoding:

1 → (f<b>)

None

01

01bb

bfff

ffff

Bit 'b' in register 'f' is set.

Description:

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write

register 'f'

BSF

FLAG_REG,

7

Example

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

DS30430C-page 56

1998 Microchip Technology Inc.

PIC16F8X

BTFSS

Bit Test f, Skip if Set

CALL

Call Subroutine

Syntax:

[label] BTFSS f,b

Syntax:

[ label ] CALL k

Operands:

0 ≤ f ≤ 127

0 ≤ b < 7

Operands:

Operation:

0 ≤ k ≤ 2047

(PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Operation:

skip if (f<b>) = 1

None

Status Affected:

Encoding:

Status Affected:

Encoding:

None

01

11bb

bfff

ffff

10

0kkk

kkkk

If bit 'b' in register 'f' is '0' then the next

instruction is executed.

If bit 'b' is '1', then the next instruction is

discarded and a NOP is executed

instead, making this a 2TCY instruction.

Description:

Call Subroutine. First, return address

(PC+1) is pushed onto the stack. The

eleven bit immediate address is loaded

into PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH. CALL

is a two cycle instruction.

Description:

Words:

1

Cycles:

1(2)

Words:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Cycles:

Decode

Read

register 'f'

Process No-Operat

data

Q Cycle Activity:

1st Cycle

Q1

Q2

Q3

Q4

ion

Decode

Read

Process

data

Write to

PC

If Skip:

(2nd Cycle)

Q1

literal 'k',

Push PC

to Stack

Q2

Q3

Q4

No-Operati No-Opera No-Operat

on tion ion

No-Opera No-Opera No-Operat

2nd Cycle

Example

No-Operat

ion

No-Opera

tion

ion

HERE

FALSE

TRUE

BTFSC FLAG,1

Example

HERE

CALL

THERE

GOTO

PROCESS_CODE

Before Instruction

PC Address HERE

After Instruction

PC

•

=

Address THERE

Before Instruction

PC

TOS = Address HERE+1

=

address HERE

After Instruction

if FLAG<1> = 0,

PC =

address FALSE

if FLAG<1> = 1,

PC =

address TRUE

1998 Microchip Technology Inc.

DS30430C-page 57

PIC16F8X

CLRF

Clear f

CLRW

Clear W

Syntax:

[label] CLRF

0 ≤ f ≤ 127

f

Syntax:

[ label ] CLRW

None

Operands:

Operation:

Operands:

Operation:

00h → (f)

1 → Z

00h → (W)

1 → Z

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

Z

00

0001

1fff

ffff

00

0001

0xxx

xxxx

The contents of register 'f' are cleared

and the Z bit is set.

Description:

W register is cleared. Zero bit (Z) is

set.

Description:

Words:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write

register 'f'

Decode No-Opera Process

tion data

Write to

W

CLRW

Before Instruction

Example

CLRF

FLAG_REG

Example

Before Instruction

FLAG_REG

After Instruction

W

=

0x5A

=

0x5A

After Instruction

W

=

0x00

1

FLAG_REG

=

0x00

1

Z

=

Z

CLRWDT

Syntax:

Clear Watchdog Timer

[ label ] CLRWDT

None

Operands:

Operation:

00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

Status Affected:

Encoding:

TO, PD

00

0000

0110

0100

CLRWDTinstruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT. Status bits TO and PD are

set.

Description:

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode No-Opera Process

Clear

WDT

tion

data

Counter

CLRWDT

Before Instruction

Example

WDT counter

After Instruction

WDT counter

=

?

0x00

WDT prescaler=

0

1

TO

PD

=

DS30430C-page 58

1998 Microchip Technology Inc.

PIC16F8X

COMF

Complement f

[ label ] COMF f,d

0 ≤ f ≤ 127

DECFSZ

Syntax:

Decrement f, Skip if 0

Syntax:

Operands:

[ label ] DECFSZ f,d

Operands:

0 ≤ f ≤ 127

d

[0,1]

d

[0,1]

Operation:

(f) → (destination)

Operation:

(f) - 1 → (destination);

skip if result = 0

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

None

00

1001

dfff

ffff

00

1011

dfff

ffff

The contents of register 'f' are comple-

mented. If 'd' is 0 the result is stored in

W. If 'd' is 1 the result is stored back in

register 'f'.

Description:

The contents of register 'f' are decre-

mented. If 'd' is 0 the result is placed in the

W register. If 'd' is 1 the result is placed

back in register 'f'.

If the result is 1, the next instruction, is

executed. If the result is 0, then a NOP is

executed instead making it a 2TCY instruc-

tion.

Description:

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write to

destination

Words:

1

Cycles:

1(2)

Q Cycle Activity:

Q1

Q2

Q3

Q4

COMF

REG1,0

Example

Decode

Read

register 'f'

Process

data

Write to

destination

Before Instruction

REG1

After Instruction

REG1

=

0x13

If Skip:

(2nd Cycle)

Q1

Q2

Q3

Q4

=

0x13

0xEC

W

No-Opera No-Operat No-Operati

No-Operat

ion

tion

ion

on

DECF

Decrement f

[label] DECF f,d

0 ≤ f ≤ 127

Syntax:

Operands:

HERE

DECFSZ

GOTO

CNT, 1

LOOP

Example

CONTINUE •

d

[0,1]

•

Operation:

(f) - 1 → (destination)

Before Instruction

Status Affected:

Encoding:

Z

PC

=

address HERE

00

0011

dfff

ffff

After Instruction

CNT

if CNT =

PC

if CNT ≠

PC

=

CNT - 1

0,

address CONTINUE

0,

address HERE+1

Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

1 the result is stored back in register 'f'.

Description:

=

Words:

1

=

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write to

destination

DECF

CNT, 1

Example

Before Instruction

CNT

=

0x01

Z

=

0

After Instruction

CNT

Z

=

0x00

1

1998 Microchip Technology Inc.

DS30430C-page 59

PIC16F8X

INCF

Increment f

GOTO

Unconditional Branch

Syntax:

Operands:

[ label ] INCF f,d

Syntax:

[ label ] GOTO

0 ≤ k ≤ 2047

k

0 ≤ f ≤ 127

Operands:

Operation:

d

[0,1]

k → PC<10:0>

PCLATH<4:3> → PC<12:11>

Operation:

(f) + 1 → (destination)

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

None

00

1010

dfff

ffff

10

1kkk

kkkk

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

GOTOis an unconditional branch. The

eleven bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTOis a two cycle instruction.

Description:

Words:

1

Words:

1

2

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

1st Cycle

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write to

destination

Decode

Read

literal 'k'

Process

data

Write to

PC

No-Operat No-Opera No-Operat

ion tion ion

2nd Cycle

No-Operat

ion

INCF

CNT, 1

Example

Before Instruction

GOTO THERE

Example

CNT

=

0xFF

Z

=

0

After Instruction

PC

=

Address THERE

CNT

Z

=

0x00

1

DS30430C-page 60

1998 Microchip Technology Inc.

PIC16F8X

INCFSZ

Syntax:

Increment f, Skip if 0

[ label ] INCFSZ f,d

0 ≤ f ≤ 127

IORLW

Inclusive OR Literal with W

Syntax:

[ label ] IORLW

0 ≤ k ≤ 255

(W) .OR. k → (W)

Z

k

Operands:

Operation:

Status Affected:

Encoding:

Description:

d

[0,1]

Operation:

(f) + 1 → (destination),

skip if result = 0

11

1000

kkkk

Status Affected:

Encoding:

None

The contents of the W register is

OR’ed with the eight bit literal 'k'. The

result is placed in the W register.

00

1111

dfff

ffff

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 1, the next instruction is

executed. If the result is 0, a NOP is exe-

cuted instead making it a 2TCY instruc-

tion.

Description:

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal 'k'

Process

data

Write to

W

Words:

1

Cycles:

1(2)

IORLW

0x35

Example

Q Cycle Activity:

Q1

Q2

Q3

Q4

Before Instruction

Decode

Read

register 'f'

Process

data

Write to

destination

W

=

0x9A

After Instruction

W

Z

=

0xBF

1

If Skip:

(2nd Cycle)

Q1

Q2

Q3

Q4

No-Opera No-Opera No-Operati

No-Operat

ion

tion

on

HERE

INCFSZ

GOTO

CNT, 1

LOOP

Example

CONTINUE •

•

Before Instruction

PC

=

address HERE

After Instruction

CNT

=

CNT + 1

if CNT=

0,

PC

if CNT≠

=

address CONTINUE

0,

PC

=

address HERE +1

1998 Microchip Technology Inc.

DS30430C-page 61

PIC16F8X

IORWF

Inclusive OR W with f

MOVLW

Move Literal to W

[ label ] MOVLW

0 ≤ k ≤ 255

Syntax:

[ label ] IORWF f,d

Syntax:

k

Operands:

0 ≤ f ≤ 127

Operands:

Operation:

Status Affected:

Encoding:

Description:

d

[0,1]

k → (W)

Operation:

(W) .OR. (f) → (destination)

None

Status Affected:

Encoding:

Z

11

00xx

kkkk

00

0100

dfff

ffff

The eight bit literal 'k' is loaded into W

register.The don’t cares will assemble

as 0’s.

Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in the

W register. If 'd' is 1 the result is placed

back in register 'f'.

Description:

Words:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal 'k'

Process

data

Write to

W

Decode

Read

register

'f'

Process

data

Write to

destination

MOVLW

0x5A

Example

After Instruction

IORWF

RESULT, 0

Example

W

=

0x5A

Before Instruction

RESULT

W

=

0x13

0x91

After Instruction

RESULT

W

Z

=

0x13

0x93

1

MOVWF

Move W to f

MOVF

Move f

Syntax:

[ label ] MOVWF

0 ≤ f ≤ 127

(W) → (f)

f

Syntax:

Operands:

[ label ] MOVF f,d

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ f ≤ 127

d

[0,1]

None

Operation:

(f) → (destination)

00

0000

1fff

ffff

Status Affected:

Encoding:

Z

Move data from W register to register

'f'.

00

1000

dfff

ffff

The contents of register f is moved to a

destination dependant upon the status

of d. If d = 0, destination is W register. If

d = 1, the destination is ﬁle register f

itself. d = 1 is useful to test a ﬁle regis-

ter since status ﬂag Z is affected.

Description:

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write

register 'f'

Words:

1

Cycles:

MOVWF

OPTION_REG

Q Cycle Activity:

Q1

Q2

Q3

Q4

Example

Decode

Read

register

'f'

Process

data

Write to

destination

Before Instruction

OPTION

=

0xFF

0x4F

W

After Instruction

OPTION

MOVF

FSR, 0

Example

=

0x4F

W

After Instruction

W

= value in FSR register

Z

= 1

DS30430C-page 62

1998 Microchip Technology Inc.

PIC16F8X

NOP

No Operation

[ label ] NOP

None

RETFIE

Return from Interrupt

Syntax:

[ label ] RETFIE

None

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Operands:

Operation:

No operation

None

TOS → PC,

1 → GIE

Status Affected:

Encoding:

None

00

0000

0xx0

0000

00

0000

1001

No operation.

Return from Interrupt. Stack is POPed

and Top of Stack (TOS) is loaded in the

PC. Interrupts are enabled by setting

Global Interrupt Enable bit, GIE

(INTCON<7>). This is a two cycle

instruction.

Description:

1

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode No-Opera No-Opera No-Operat

tion

ion

Words:

1

2

Cycles:

NOP

Example

Q Cycle Activity:

1st Cycle

Q1

Q2

Q3

Q4

Decode No-Opera Set the

tion GIE bit

Pop from

the Stack

No-Opera No-Opera No-Operat

tion tion ion

2nd Cycle

No-Operat

ion

RETFIE

Example

After Interrupt

PC

=

TOS

GIE =

1

OPTION

Syntax:

Load Option Register

[ label ] OPTION

None

Operands:

Operation:

(W) → OPTION

Status Affected: None

00

0000

0110

0010

Encoding:

The contents of the W register are

loaded in the OPTION register. This

instruction is supported for code com-

patibility with PIC16C5X products.

Since OPTION is a readable/writable

register, the user can directly address

it.

Description:

Words:

Cycles:

Example

1

To maintain upward compatibility

with future PIC16CXX products,

do not use this instruction.

1998 Microchip Technology Inc.

DS30430C-page 63

PIC16F8X

RETLW

Return with Literal in W

RETURN

Return from Subroutine

[ label ] RETURN

None

Syntax:

[ label ] RETLW

k

Syntax:

Operands:

Operation:

0 ≤ k ≤ 255

Operands:

Operation:

Status Affected:

Encoding:

Description:

k → (W);

TOS → PC

None

Status Affected:

Encoding:

None

00

0000

1000

11

01xx

kkkk

Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.This

is a two cycle instruction.

The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Description:

Words:

1

2

Cycles:

Words:

1

2

Q Cycle Activity:

1st Cycle

Q1

Q2

Q3

Q4

Cycles:

Decode No-Opera No-Opera Pop from

tion tion the Stack

Q Cycle Activity:

1st Cycle

Q1

Q2

Q3

Q4

Decode

Read

No-Opera WritetoW,

No-Opera No-Opera No-Opera

tion tion tion

2nd Cycle

literal 'k'

tion

Pop from

the Stack

No-Operat

ion

No-Opera No-Opera No-Operat

tion tion ion

2nd Cycle

No-Operat

ion

RETURN

Example

After Interrupt

PC

=

TOS

CALL TABLE ;W contains table

;offset value

•

Example

;W now has table value

•

TABLE

ADDWF PC

RETLW k1

RETLW k2

•

;W = offset

;Begin table

;

•

RETLW kn

; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

DS30430C-page 64

1998 Microchip Technology Inc.

PIC16F8X

RLF

Rotate Left f through Carry

RRF

Rotate Right f through Carry

[ label ] RRF f,d

0 ≤ f ≤ 127

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

Operands:

0 ≤ f ≤ 127

d

[0,1]

d

[0,1]

Operation:

See description below

C

Operation:

See description below

C

Status Affected:

Encoding:

Status Affected:

Encoding:

00

1101

dfff

ffff

00

1100

dfff

ffff

The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in the

W register. If 'd' is 1 the result is stored

back in register 'f'.

The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in the

W register. If 'd' is 1 the result is placed

back in register 'f'.

Description:

C

Register f

C

Register f

Words:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register

'f'

Process

data

Write to

destination

Decode

Read

register

'f'

Process

data

Write to

destination

RLF

REG1,0

Example

RRF

REG1,0

Example

Before Instruction

REG1

C

=

1110 0110

0

REG1

C

=

1110 0110

0

After Instruction

REG1

W

C

=

1110 0110

1100 1100

1

REG1

W

C

=

1110 0110

0111 0011

0

1998 Microchip Technology Inc.

DS30430C-page 65

PIC16F8X

SLEEP

SUBLW

Subtract W from Literal

Syntax:

[ label ]

SUBLW k

Syntax:

[ label ] SLEEP

Operands:

Operation:

0 ≤ k ≤ 255

Operands:

Operation:

None

k - (W) → (W)

00h → WDT,

0 → WDT prescaler,

1 → TO,

Status Affected: C, DC, Z

Encoding:

11

110x

kkkk

0 → PD

The W register is subtracted (2’s comple-

ment method) from the eight bit literal 'k'.

The result is placed in the W register.

Description:

Status Affected:

Encoding:

TO, PD

00

0000

0110

0011

Words:

1

The power-down status bit, PD is

cleared. Time-out status bit, TO is

set.Watchdog Timer and its prescaler

are cleared.

Description:

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

The processor is put into SLEEP

mode with the oscillator stopped. See

Section 14.8 for more details.

Decode

Read

literal 'k'

Process Write to W

data

Words:

1

Example 1:

SUBLW

0x02

Cycles:

Before Instruction

Q Cycle Activity:

Q1

Q2

Q3

Q4

W

C

Z

=

1

?

Decode No-Opera No-Opera

tion tion

Go to

Sleep

After Instruction

Example:

SLEEP

W

C

Z

=

1

1; result is positive

0

Example 2:

Before Instruction

W

C

Z

=

2

?

After Instruction

W

C

Z

=

0

1; result is zero

1

Example 3:

Before Instruction

W

C

Z

=

3

?

After Instruction

W

C

=

0xFF

0; result is nega-

tive

Z

=

0

DS30430C-page 66

1998 Microchip Technology Inc.

PIC16F8X

SUBWF

Syntax:

Subtract W from f

SWAPF

Syntax:

Swap Nibbles in f

[ label ] SWAPF f,d

[ label ]

SUBWF f,d

Operands:

0 ≤ f ≤ 127

Operands:

0 ≤ f ≤ 127

d

[0,1]

d

[0,1]

Operation:

(f<3:0>) → (destination<7:4>),

(f<7:4>) → (destination<3:0>)

Operation:

(f) - (W) → (destination)

Status Affected: C, DC, Z

Status Affected:

Encoding:

None

Encoding:

00

0010

dfff

ffff

00

1110

dfff

ffff

Subtract (2’s complement method) W reg-

ister from register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'.

Description:

The upper and lower nibbles of register

'f' are exchanged. If 'd' is 0 the result is

placed in W register. If 'd' is 1 the result

is placed in register 'f'.

Description:

Words:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register 'f'

Process

data

Write to

destination

Decode

Read

register 'f'

Process

data

Write to

destination

Example 1:

SUBWF

REG1,1

SWAPF REG,

0

Example

Before Instruction

REG1

=

3

W

C

Z

2

?

=

0xA5

After Instruction

REG1

W

=

0xA5

0x5A

After Instruction

REG1

=

1

2

W

C

Z

=

1; result is positive

0

Example 2:

Before Instruction

TRIS

Load TRIS Register

REG1

=

2

?

Syntax:

[label] TRIS

f

W

C

Z

Operands:

Operation:

5 ≤ f ≤ 7

(W) → TRIS register f;

Status Affected: None

After Instruction

00

Encoding:

0000 0110

0fff

REG1

=

0

W

C

Z

=

2

The instruction is supported for code

compatibility with the PIC16C5X prod-

ucts. Since TRIS registers are read-

able and writable, the user can directly

address them.

Description:

1; result is zero

1

Example 3:

Before Instruction

REG1

=

1

2

?

Words:

Cycles:

Example

1

W

C

Z

After Instruction

To maintain upward compatibility

with future PIC16CXX products,

do not use this instruction.

REG1

=

0xFF

2

0; result is negative

0

W

C

Z

=

1998 Microchip Technology Inc.

DS30430C-page 67

PIC16F8X

XORLW

Exclusive OR Literal with W

[label] XORLW

XORWF

Syntax:

Exclusive OR W with f

[label] XORWF f,d

0 ≤ f ≤ 127

Syntax:

k

Operands:

Operation:

Status Affected:

Encoding:

0 ≤ k ≤ 255

d

[0,1]

(W) .XOR. k → (W)

Operation:

(W) .XOR. (f) → (destination)

Z

Status Affected:

Encoding:

Z

11

1010 kkkk kkkk

00

0110

dfff

ffff

The contents of the W register are

XOR’ed with the eight bit literal 'k'.

The result is placed in the W regis-

ter.

Description:

Exclusive OR the contents of the W

register with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

1 the result is stored back in register 'f'.

Description:

Words:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

Process Write to

literal 'k'

data

W

Decode

Read

register

'f'

Process

data

Write to

destination

Example:

XORLW

0xAF

Before Instruction

REG

1

Example

XORWF

W

=

0xB5

0x1A

Before Instruction

After Instruction

REG

W

=

0xAF

0xB5

W

=

After Instruction

REG

W

=

0x1A

0xB5

DS30430C-page 68

1998 Microchip Technology Inc.

PIC16F8X

10.3

ICEPIC: Low-Cost PICmicro™

In-Circuit Emulator

10.0 DEVELOPMENT SUPPORT

10.1

Development Tools

ICEPIC is a low-cost in-circuit emulator solution for the

Microchip PIC12CXXX, PIC16C5X and PIC16CXXX

families of 8-bit OTP microcontrollers.

The PICmicrο microcontrollers are supported with a

full range of hardware and software development tools:

• PICMASTER /PICMASTER CE Real-Time

In-Circuit Emulator

ICEPIC is designed to operate on PC-compatible

machines ranging from 286-AT through Pentium

based machines under Windows 3.x environment.

ICEPIC features real time, non-intrusive emulation.

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX

In-Circuit Emulator

• PRO MATE II Universal Programmer

10.4

PRO MATE II: Universal Programmer

• PICSTART Plus Entry-Level Prototype

Programmer

The PRO MATE II Universal Programmer is a full-fea-

tured programmer capable of operating in stand-alone

mode as well as PC-hosted mode. PRO MATE II is CE

compliant.

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

The PRO MATE II has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to support various package types. In stand-

alone mode the PRO MATE II can read, verify or pro-

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

• Fuzzy Logic Development System

(fuzzyTECH −MP)

10.2

PICMASTER: High Performance

Universal In-Circuit Emulator with

MPLAB IDE

gram

PIC12CXXX,

PIC14C000,

PIC16C5X,

PIC16CXXX and PIC17CXX devices. It can also set

conﬁguration and code-protect bits in this mode.

The PICMASTER Universal In-Circuit Emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for all

microcontrollers in the PIC14C000, PIC12CXXX,

PIC16C5X, PIC16CXXX and PIC17CXX families.

PICMASTER is supplied with the MPLAB Integrated

Development Environment (IDE), which allows editing,

“make” and download, and source debugging from a

single environment.

10.5

PICSTART Plus Entry Level

Development System

The PICSTART programmer is an easy-to-use,

low-cost prototype programmer. It connects to the PC

via one of the COM (RS-232) ports. MPLAB Integrated

Development Environment software makes using the

programmer simple and efﬁcient. PICSTART Plus is

not recommended for production programming.

Interchangeable target probes allow the system to be

easily reconﬁgured for emulation of different proces-

sors. The universal architecture of the PICMASTER

allows expansion to support all new Microchip micro-

controllers.

PICSTART Plus supports all PIC12CXXX, PIC14C000,

PIC16C5X, PIC16CXXX and PIC17CXX devices with

up to 40 pins. Larger pin count devices such as the

PIC16C923, PIC16C924 and PIC17C756 may be sup-

ported with an adapter socket. PICSTART Plus is CE

compliant.

The PICMASTER Emulator System has been

designed as

a real-time emulation system with

advanced features that are generally found on more

expensive development tools. The PC compatible 386

(and higher) machine platform and Microsoft Windows

3.x environment were chosen to best make these fea-

tures available to you, the end user.

A CE compliant version of PICMASTER is available for

European Union (EU) countries.

1998 Microchip Technology Inc.

DS30430C-page 69

PIC16F8X

an RS-232 interface, push-button switches, a potenti-

ometer for simulated analog input, a thermistor and

separate headers for connection to an external LCD

module and a keypad. Also provided on the PICDEM-3

board is an LCD panel, with 4 commons and 12 seg-

ments, that is capable of displaying time, temperature

and day of the week. The PICDEM-3 provides an addi-

tional RS-232 interface and Windows 3.1 software for

showing the demultiplexed LCD signals on a PC. A sim-

ple serial interface allows the user to construct a hard-

ware demultiplexer for the LCD signals.

10.6

PICDEM-1 Low-Cost PICmicro

Demonstration Board

The PICDEM-1 is a simple board which demonstrates

the capabilities of several of Microchip’s microcontrol-

lers. The microcontrollers supported are: PIC16C5X

(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,

PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and

PIC17C44. All necessary hardware and software is

included to run basic demo programs. The users can

program the sample microcontrollers provided with

the PICDEM-1 board, on

a PRO MATE II or

10.9

MPLAB™ Integrated Development

Environment Software

PICSTART-Plus programmer, and easily test ﬁrm-

ware. The user can also connect the PICDEM-1

board to the PICMASTER emulator and download

the ﬁrmware to the emulator for testing. Additional pro-

totype area is available for the user to build some addi-

tional hardware and connect it to the microcontroller

socket(s). Some of the features include an RS-232

interface, a potentiometer for simulated analog input,

push-button switches and eight LEDs connected to

PORTB.

The MPLAB IDE Software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. MPLAB is a windows based application

which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

10.7

PICDEM-2 Low-Cost PIC16CXX

Demonstration Board

The PICDEM-2 is a simple demonstration board that

supports the PIC16C62, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sample microcontrollers provided

with the PICDEM-2 board, on a PRO MATE II pro-

grammer or PICSTART-Plus, and easily test ﬁrmware.

The PICMASTER emulator may also be used with the

PICDEM-2 board to test ﬁrmware. Additional prototype

area has been provided to the user for adding addi-

tional hardware and connecting it to the microcontroller

socket(s). Some of the features include a RS-232 inter-

face, push-button switches, a potentiometer for simu-

lated analog input, a Serial EEPROM to demonstrate

MPLAB allows you to:

• Edit your source ﬁles (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro tools (automatically updates all

project information)

• Debug using:

- source ﬁles

- absolute listing ﬁle

• Transfer data dynamically via DDE (soon to be

replaced by OLE)

• Run up to four emulators on the same PC

The ability to use MPLAB with Microchip’s simulator

allows a consistent platform and the ability to easily

switch from the low cost simulator to the full featured

emulator with minimal retraining due to development

tools.

2

usage of the I C bus and separate headers for connec-

tion to an LCD module and a keypad.

10.8

PICDEM-3 Low-Cost PIC16CXXX

Demonstration Board

10.10 Assembler (MPASM)

The PICDEM-3 is a simple demonstration board that

supports the PIC16C923 and PIC16C924 in the PLCC

package. It will also support future 44-pin PLCC

microcontrollers with a LCD Module. All the neces-

sary hardware and software is included to run the

basic demonstration programs. The user can pro-

gram the sample microcontrollers provided with

the PICDEM-3 board, on a PRO MATE II program-

mer or PICSTART Plus with an adapter socket, and

easily test ﬁrmware. The PICMASTER emulator may

also be used with the PICDEM-3 board to test ﬁrm-

ware. Additional prototype area has been provided to

the user for adding hardware and connecting it to the

microcontroller socket(s). Some of the features include

The MPASM Universal Macro Assembler is

a

PC-hosted symbolic assembler. It supports all micro-

controller series including the PIC12C5XX, PIC14000,

PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, condi-

tional assembly, and several source and listing formats.

It generates various object code formats to support

Microchip's development tools as well as third party

programmers.

MPASM allows full symbolic debugging from

PICMASTER, Microchip’s Universal Emulator System.

DS30430C-page 70

1998 Microchip Technology Inc.

PIC16F8X

MPASM has the following features to assist in develop-

ing software for speciﬁc use applications.

10.14 MP-DriveWay – Application Code

Generator

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

MP-DriveWay is an easy-to-use Windows-based Appli-

cation Code Generator. With MP-DriveWay you can

visually conﬁgure all the peripherals in a PICmicro

device and, with a click of the mouse, generate all the

initialization and many functional code modules in C

language. The output is fully compatible with Micro-

chip’s MPLAB-C C compiler. The code produced is

highly modular and allows easy integration of your own

code. MP-DriveWay is intelligent enough to maintain

your code through subsequent code generation.

• Macro assembly capability.

• Produces all the ﬁles (Object, Listing, Symbol,

and special) required for symbolic debug with

Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source

and listing formats.

MPASM provides a rich directive language to support

programming of the PICmicro. Directives are helpful in

making the development of your assemble source code

shorter and more maintainable.

10.15 SEEVAL Evaluation and

Programming System

10.11 Software Simulator (MPLAB-SIM)

The SEEVAL SEEPROM Designer’s Kit supports all

Microchip 2-wire and 3-wire Serial EEPROMs. The kit

includes everything necessary to read, write, erase or

program special features of any Microchip SEEPROM

product including Smart Serials and secure serials.

The MPLAB-SIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PICmicro series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pins. The

input/output radix can be set by the user and the exe-

cution can be performed in; single step, execute until

break, or in a trace mode.

The Total Endurance

Disk is included to aid in

trade-off analysis and reliability calculations. The total

kit can signiﬁcantly reduce time-to-market and result in

an optimized system.

10.16 KEELOQ Evaluation and

Programming Tools

MPLAB-SIM fully supports symbolic debugging using

MPLAB-C and MPASM. The Software Simulator offers

the low cost ﬂexibility to develop and debug code out-

side of the laboratory environment making it an excel-

lent multi-project software development tool.

KEELOQ evaluation and programming tools support

Microchips HCS Secure Data Products.The HCS eval-

uation kit includes an LCD display to show changing

codes, a decoder to decode transmissions, and a pro-

gramming interface to program test transmitters.

10.12 C Compiler (MPLAB-C17)

The MPLAB-C Code Development System is

a

complete ‘C’ compiler and integrated development

environment for Microchip’s PIC17CXXX family of

microcontrollers. The compiler provides powerful inte-

gration capabilities and ease of use not found with

other compilers.

For easier source level debugging, the compiler pro-

vides symbol information that is compatible with the

MPLAB IDE memory display.

10.13 Fuzzy Logic Development System

(fuzzyTECH-MP)

fuzzyTECH-MP fuzzy logic development tool is avail-

able in two versions - a low cost introductory version,

MP Explorer, for designers to gain a comprehensive

working knowledge of fuzzy logic system design; and a

full-featured version, fuzzyTECH-MP, Edition for imple-

menting more complex systems.

Both versions include Microchip’s fuzzyLAB demon-

stration board for hands-on experience with fuzzy logic

systems implementation.

1998 Microchip Technology Inc.

DS30430C-page 71

PIC16F83/84

PIC16F8X

10.0 ELECTRICAL CHARACTERISTICS FOR PIC16F83 AND PIC16F84

Absolute Maximum Ratings †

Ambient temperature under bias.............................................................................................................-55°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on VDD with respect to VSS .......................................................................................................... -0.3 to +7.5V

(2)

Voltage on MCLR with respect to VSS ...................................................................................................... -0.3 to +14V

Voltage on any pin with respect to VSS (except VDD and MCLR)....................................................-0.6V to (VDD + 0.6V)

(1)

Total power dissipation .....................................................................................................................................800 mW

Maximum current out of VSS pin ...........................................................................................................................150 mA

Maximum current into VDD pin ..............................................................................................................................100 mA

Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA

Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................± 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................20 mA

Maximum current sunk by PORTA ..........................................................................................................................80 mA

Maximum current sourced by PORTA.....................................................................................................................50 mA

Maximum current sunk by PORTB........................................................................................................................150 mA

Maximum current sourced by PORTB...................................................................................................................100 mA

Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,

a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling

this pin directly to VSS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above

those indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions

for extended periods may affect device reliability.

1998 Microchip Technology Inc.

DS30430C-page 73

PIC16F8X

PIC16F83/84

TABLE 10-1

CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

PIC16F84-04

PIC16F83-04

PIC16F84-10

PIC16F83-10

PIC16LF84-04

PIC16LF83-04

OSC

RC

XT

HS

VDD: 4.0V to 6.0V

VDD: 4.5V to 5.5V

VDD: 2.0V to 6.0V

IDD:

IPD:

4.5 mA max. at 5.5V

14 µA max. at 4V WDT dis

IDD:

IPD:

1.8 mA typ. at 5.5V

1.0 µA typ. at 5.5V WDT dis

IDD:

IPD:

4.5 mA max. at 5.5V

7.0 µA max. at 2V WDT dis

Freq: 4.0 MHz max.

Freq: 4..0 MHz max.

Freq: 2.0 MHz max.

VDD: 4.0V to 6.0V

VDD: 4.5V to 5.5V

VDD: 2.0V to 6.0V

IDD:

IPD:

4.5 mA max. at 5.5V

14 µA max. at 4V WDT dis

IDD:

IPD:

1.8 mA typ. at 5.5V

1.0 µA typ. at 5.5V WDT dis

IDD:

IPD:

4.5 mA max. at 5.5V

7.0 µA max. at 2V WDT dis

Freq: 4.0 MHz max.

Freq: 2.0 MHz max.

Do not use in HS mode

VDD: 2.0V to 6.0V

VDD: 4.5V to 5.5V

IDD:

IPD:

4.5 mA typ. at 5.5V

1.0 µA typ. at 4.5V WDT dis

IDD:

IPD:

10 mA max. at 5.5V typ.

1.0 µA typ. at 4.5V WDT dis

Freq: 4.0 MHz max.

VDD: 4.0V to 6.0V

Freq: 10 MHz max.

LP

IDD:

IPD:

48 µA typ. at 32 kHz, 2.0V

0.6 µA typ. at 3.0V WDT dis

IDD:

IPD:

45 µA max. at 32 kHz, 2.0V

7 µA max. at 2.0V WDT dis

Do not use in LP mode

Freq: 200 kHz max.

The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX speciﬁca-

tions. It is recommended that the user select the device type that ensures the speciﬁcations required.

DS30430C-page 74

1998 Microchip Technology Inc.

PIC16F83/84

PIC16F8X

10.1

DC CHARACTERISTICS:

PIC16F84, PIC16F83 (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤ +70°C (commercial)

-40°C ≤ TA ≤ +85°C (industrial)

DC Characteristics

Power Supply Pins

Parameter

No.

Sym

Characteristic

Supply Voltage

Min Typ† Max Units

Conditions

D001

D001A

VDD

4.0

4.5

—

6.0

5.5

V

XT, RC and LP osc conﬁguration

HS osc conﬁguration

D002

D003

VDR

RAM Data Retention

Voltage

1.5*

—

V

Device in SLEEP mode

(1)

VPOR VDD start voltage to

ensure internal

—

VSS

—

V

See section on Power-on Reset for details

Power-on Reset signal

D004

SVDD VDD rise rate to ensure 0.05*

internal Power-on

—

V/ms See section on Power-on Reset for details

Reset signal

(2)

(4)

IDD

IPD

Supply Current

RC and XT osc conﬁguration

D010

D010A

—

1.8

7.3

4.5

10

mA

FOSC = 4.0 MHz, VDD = 5.5V

(During Flash programming)

HS osc conﬁguration (PIC16F84-10)

FOSC = 10 MHz, VDD = 5.5V

D013

—

5

10

mA

(3)

D020

D021

D021A

Power-down Current

—

7.0

1.0

28

14

16

µA VDD = 4.0V, WDT enabled, industrial

µA VDD = 4.0V, WDT disabled, commercial

µA VDD = 4.0V, WDT disabled, industrial

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5.0V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD,

MCLR = VDD; WDT enabled/disabled as speciﬁed.

3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be esti-

mated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.

1998 Microchip Technology Inc.

DS30430C-page 75

PIC16F8X

PIC16F83/84

10.2

DC CHARACTERISTICS:

PIC16LF84, PIC16LF83 (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤ +70°C (commercial)

-40°C ≤ TA ≤ +85°C (industrial)

DC Characteristics

Power Supply Pins

Parameter

No.

Sym

Characteristic

Supply Voltage

Min Typ† Max Units

Conditions

D001

D002

VDD

VDR

2.0

—

6.0

—

V

XT, RC, and LP osc conﬁguration

Device in SLEEP mode

RAM Data Retention

1.5*

(1)

Voltage

D003

D004

VPOR VDD start voltage to

ensure internal

—

VSS

—

V

See section on Power-on Reset for details

Power-on Reset signal

SVDD VDD rise rate to ensure 0.05*

internal Power-on

V/ms See section on Power-on Reset for details

Reset signal

(2)

(4)

IDD

Supply Current

RC and XT osc conﬁguration

D010

D010A

—

1

7.3

4

10

mA

FOSC = 2.0 MHz, VDD = 5.5V

(During Flash programming)

LP osc conﬁguration

D014

—

15

45

µA

FOSC = 32 kHz, VDD = 2.0V,

WDT disabled

(3)

D020

D021

D021A

IPD

Power-down Current

—

3.0

0.4

16

7.0

9.0

µA VDD = 2.0V, WDT enabled, industrial

µA VDD = 2.0V, WDT disabled, commercial

µA VDD = 2.0V, WDT disabled, industrial

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD,

MCLR = VDD; WDT enabled/disabled as speciﬁed.

3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be

estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.

DS30430C-page 76

1998 Microchip Technology Inc.

PIC16F83/84

PIC16F8X

10.3

DC CHARACTERISTICS:

PIC16F84, PIC16F83 (Commercial, Industrial)

PIC16LF84, PIC16LF83 (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤ +70°C (commercial)

-40°C ≤ TA ≤ +85°C (industrial)

DC Characteristics

All Pins Except

Power Supply Pins

Operating voltage VDD range as described in DC spec

Section 10.1 and Section 10.2.

Parame-

ter

Sym

Characteristic

Input Low Voltage

I/O ports

with TTL buffer

Min

Typ†

Max

Units

Conditions

No.

VIL

(4)

—

D030

VSS

Vss

0.8

V

4.5 V ≤ VDD ≤ 5.5 V

(4)

D030A

D031

D032

D033

D034

0.16VDD

0.2VDD

0.3VDD

0.1VDD

entire range

with Schmitt Trigger buffer

MCLR, RA4/T0CKI

OSC1 (XT, HS and LP modes)

OSC1 (RC mode)

entire range

(1)

Input High Voltage

I/O ports

—

VIH

(4)

—

D040

D040A

with TTL buffer

2.4

0.48VDD

VDD

V

4.5 V ≤ VDD ≤ 5.5V

entire range

(4)

—

D041

D042

with Schmitt Trigger buffer

0.45VDD

VDD

entire range

MCLR, RA4/T0CKI, OSC1

(RC mode)

0.85

VDD

V

(1)

—

D043

D050

OSC1 (XT, HS and LP modes)

0.7 VDD

TBD

VDD

—

V

VHYS Hysteresis of

Schmitt Trigger inputs

D070

D060

IPURB PORTB weak pull-up current

50*

—

250*

—

400*

µA VDD = 5.0V, VPIN = VSS

(2,3)

Input Leakage Current

IIL

I/O ports

±1

µA Vss ≤ VPIN ≤ VDD,

Pin at hi-impedance

—

D061

D063

MCLR, RA4/T0CKI

OSC1

±5

µA Vss ≤ VPIN ≤ VDD

µA Vss ≤ VPIN ≤ VDD, XT, HS

and LP osc conﬁguration

Output Low Voltage

I/O ports

—

D080

D083

VOL

VOH

0.6

V

IOL = 8.5 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V

OSC2/CLKOUT

Output High Voltage

(3)

—

D090

D092

I/O ports

VDD-0.7

V

IOH = -3.0 mA, VDD = 4.5V

IOH = -1.3 mA, VDD = 4.5V

OSC2/CLKOUT

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In RC oscillator conﬁguration, the OSC1 pin is a Schmitt Trigger input. Do not drive the PIC16F8X with an

external clock while the device is in RC mode, or chip damage may result.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The speciﬁed lev-

els represent normal operating conditions. Higher leakage current may be measured at different input volt-

ages.

3: Negative current is deﬁned as coming out of the pin.

4: The user may choose the better of the two specs.

1998 Microchip Technology Inc.

DS30430C-page 77

PIC16F8X

PIC16F83/84

10.4

DC CHARACTERISTICS: PIC16F84, PIC16F83 (Commercial, Industrial)

PIC16LF84, PIC16F83 (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤ +70°C (commercial)

-40°C ≤ TA ≤ +85°C (industrial)

DC Characteristics

All Pins Except

Power Supply Pins

Operating voltage VDD range as described in DC spec

Section 10.1 and Section 10.2.

Parameter

No.

Sym

Characteristic

Min

Typ†

Max Units

Conditions

Capacitive Loading Specs

on Output Pins

—

D100

D101

COSC2 OSC2 pin

—

15

50

pF In XT, HS and LP modes

when external clock is used to

drive OSC1.

CIO

All I/O pins and OSC2

pF

(RC mode)

Data EEPROM Memory

—

D120

D121

ED

Endurance

1M

10M

—

E/W 25°C at 5V

VDRW VDD for read/write

VMIN

6.0

V

VMIN = Minimum operating

voltage

D122

TDEW Erase/Write cycle time

—

10

20*

ms

Program Flash Memory

—

D130

D131

EP

Endurance

100

1000

—

E/W

V

VPR

VDD for read

VMIN

6.0

VMIN = Minimum operating

voltage

—

D132

D133

VPEW VDD for erase/write

4.5

—

5.5

—

V

TPEW Erase/Write cycle time

10

ms

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

DS30430C-page 78

1998 Microchip Technology Inc.

PIC16F83/84

PIC16F8X

TABLE 10-2

TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created fol-

lowing one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase symbols (pp) and their meanings:

pp

T

Time

2

to

os,osc

ost

OSC1

ck

CLKOUT

cycle time

I/O port

INT pin

MCLR

oscillator start-up timer

power-up timer

RBx pins

cy

io

pwrt

rbt

inp

mc

t0

T0CKI

wdt

watchdog timer

Uppercase symbols and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (Hi-impedance)

Low

Valid

L

High Impedance

FIGURE 10-1: PARAMETER MEASUREMENT INFORMATION

All timings are measure between high and low mea-

surement points as indicated in the ﬁgures below.

0.7 VDD XTAL

0.8 VDD RC

(High)

0.9 VDD (High)

0.1 VDD (Low)

0.3 VDD XTAL

0.15 VDD RC

(Low)

OSC1 Measurement Points

I/O Port Measurement Points

FIGURE 10-2: LOAD CONDITIONS

Load Condition 1

VDD/2

Load Condition 2

CL

RL

VSS

CL

VSS

RL =

CL =

464Ω

50 pF

15 pF

for all pins except OSC2.

for OSC2 output.

1998 Microchip Technology Inc.

DS30430C-page 79

PIC16F8X

PIC16F83/84

10.5

Timing Diagrams and Speciﬁcations

FIGURE 10-3: EXTERNAL CLOCK TIMING

Q4

Q3

Q4

Q1

Q2

OSC1

1

3

4

2

CLKOUT

TABLE 10-3

EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

(1)

FOSC External CLKIN Frequency

DC

—

2

4

MHz XT, RC osc PIC16LF8X-04

MHz XT, RC osc PIC16F8X-04

10

200

MHz HS osc

kHz LP osc

PIC16F8X-10

PIC16LF8X-04

(1)

Oscillator Frequency

DC

0.1

1.0

DC

—

2

4

MHz RC osc

MHz XT osc

MHz HS osc

kHz LP osc

PIC16LF8X-04

PIC16F8X-04

PIC16LF8X-04

PIC16F8X-04

PIC16F8X-10

PIC16LF8X-04

2

4

10

200

(1)

1

Tosc External CLKIN Period

500

250

100

5.0

—

ns

µs

XT, RC osc PIC16LF8X-04

XT, RC osc PIC16F8X-04

HS osc

LP osc

PIC16F8X-10

PIC16LF8X-04

(1)

Oscillator Period

500

250

500

250

100

5.0

—

ns

µs

RC osc

XT osc

HS osc

LP osc

PIC16LF8X-04

PIC16F8X-04

PIC16LF8X-04

PIC16F8X-04

PIC16F8X-10

PIC16LF8X-04

10,000

1,000

—

(1)

2

3

TCY

Instruction Cycle Time

0.4

60 *

50 *

2.0 *

35 *

4/Fosc

—

DC

—

µs

ns

µs

ns

TosL, Clock in (OSC1) High or Low

TosH Time

XT osc

LP osc

HS osc

XT osc

LP osc

HS osc

PIC16LF8X-04

PIC16F8X-04

PIC16LF8X-04

PIC16F8X-10

PIC16F8X-04

PIC16LF8X-04

PIC16F8X-10

—

4

TosR, Clock in (OSC1) Rise or Fall Time 25 *

—

TosF

50 *

15 *

—

*

These parameters are characterized but no tested.

†

Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All speciﬁed values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at "min." values with an

external clock applied to the OSC1 pin.

When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.

DS30430C-page 80

1998 Microchip Technology Inc.

PIC16F83/84

PIC16F8X

FIGURE 10-4: CLKOUT AND I/O TIMING

Q1

Q2

Q3

Q4

OSC1

11

10

22

23

CLKOUT

13

12

16

19

18

14

I/O Pin

(input)

15

17

I/O Pin

new value

old value

(output)

20, 21

Note: All tests must be done with speciﬁed capacitive loads (Figure 10-2) 50 pF on I/O pins and CLKOUT.

TABLE 10-4

CLKOUT AND I/O TIMING REQUIREMENTS

Parameter

No.

Sym

Characteristic

OSC1↑ to CLKOUT↓ PIC16F8X

Min

Typ†

Max

Units Conditions

10

TosH2ckL

—

15

30 *

ns

Note 1

10A

11

PIC16LF8X

PIC16F8X

PIC16LF8X

PIC16F8X

PIC16LF8X

PIC16F8X

PIC16LF8X

—

15

—

120 *

30 *

ns

Note 1

TosH2ckH OSC1↑ to CLKOUT↑

—

11A

12

—

120 *

30 *

TckR

TckF

CLKOUT rise time

CLKOUT fall time

—

12A

13

—

100 *

30 *

—

13A

14

—

100 *

0.5TCY +20 *

—

TckL2ioV

TioV2ckH

CLKOUT ↓ to Port out valid

—

15

Port in valid before

PIC16F8X

PIC16LF8X

0.30TCY + 30 *

CLKOUT ↑

0.30TCY + 80 *

—

16

17

TckH2ioI

TosH2ioV

Port in hold after CLKOUT ↑

0 *

—

OSC1↑ (Q1 cycle) to

PIC16F8X

125 *

250 *

—

Port out valid

PIC16LF8X

PIC16F8X

PIC16LF8X

—

18

19

TosH2ioI

OSC1↑ (Q2 cycle) to

Port input invalid

(I/O in hold time)

10 *

—

TioV2osH

Port input valid to

OSC1↑

PIC16F8X

-75 *

—

ns

PIC16LF8X

-175 *

(I/O in setup time)

20

20A

21

TioR

TioF

Tinp

Trbp

Port output rise time

Port output fall time

PIC16F8X

PIC16LF8X

PIC16F8X

PIC16LF8X

PIC16F8X

PIC16LF8X

—

10

—

35 *

70 *

35 *

70 *

—

ns

—

21A

22

—

INT pin high

or low time

20 *

55 *

TOSC §

22A

23

—

RB7:RB4 change INT PIC16F8X

high or low time PIC16LF8X

—

23A

—

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

By design

§

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

1998 Microchip Technology Inc.

DS30430C-page 81

PIC16F8X

PIC16F83/84

FIGURE 10-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Time-out

Internal

RESET

Watchdog

Timer

RESET

31

34

I/O Pins

TABLE 10-5

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min

Typ†

Max Units

Conditions

30

31

TmcL MCLR Pulse Width (low)

1000 *

7 *

—

ns 2.0V ≤ VDD ≤ 6.0V

Twdt

Tost

Watchdog Timer Time-out Period

(No Prescaler)

18

33 *

ms VDD = 5.0V

32

33

Oscillation Start-up Timer Period

1024TOSC

72

ms TOSC = OSC1 period

ms VDD = 5.0V

Tpwrt Power-up Timer Period

I/O Hi-impedance from MCLR Low

or reset

These parameters are characterized but not tested.

28 *

—

132 *

100 *

34

TIOZ

—

ns

*

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

DS30430C-page 82

1998 Microchip Technology Inc.

PIC16F83/84

PIC16F8X

FIGURE 10-6: TIMER0 CLOCK TIMINGS

RA4/T0CKI

40

41

42

TABLE 10-6

TIMER0 CLOCK REQUIREMENTS

Parameter Sym

No.

Characteristic

Min

Typ† Max Units

Conditions

40

Tt0H T0CKI High Pulse Width

Tt0L T0CKI Low Pulse Width

Tt0P T0CKI Period

No Prescaler

0.5TCY + 20 *

—

ns

With Prescaler

50 *

30 *

—

ns 2.0V ≤ VDD ≤ 3.0V

ns 3.0V ≤ VDD ≤ 6.0V

41

42

No Prescaler

0.5TCY + 20 *

—

ns

With Prescaler

50 *

20 *

—

ns 2.0V ≤ VDD ≤ 3.0V

ns 3.0V ≤ VDD ≤ 6.0V

TCY + 40 *

N

—

ns N = prescale value

(2, 4, ..., 256)

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

1998 Microchip Technology Inc.

DS30430C-page 83

PIC16F8X

PIC16F83/84

NOTES:

DS30430C-page 84

1998 Microchip Technology Inc.

PIC16CR83/84

PIC16F8X

11.0 ELECTRICAL CHARACTERISTICS FOR PIC16CR83 AND PIC16CR84