PIC16F707T-I/PT_技术文档

PIC16F707/PIC16LF707

Data Sheet

40/44-Pin, Flash Microcontrollers

with nanoWatt XLP and

mTouch™ Technology

 2010 Microchip Technology Inc.

Preliminary

DS41418A

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

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suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-60932-148-2

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS41418A-page 2

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

40/44-Pin, Flash Microcontrollers with

nanoWatt XLP and mTouch™ Technology

Devices included in this data sheet:

Extreme Low-Power Management

PIC16LF707 with nanoWatt XLP:

• PIC16F707

• PIC16LF707

• Sleep mode: 20 nA @ 1.8V, typical

• Watchdog Timer: 500 nA @ 1.8V, typical

• Timer1 Oscillator: 600 nA @ 1.8V, typical

@ 32 kHz

High-Performance RISC CPU:

• Only 35 Single-Word Instructions to Learn:

- All single-cycle instructions except branches

• Operating Speed:

- DC – 20 MHz clock input

- DC – 200 ns instruction cycle

• 8K x 14 Words of Flash Program Memory

• 363 Bytes of Data Memory (SRAM)

• Interrupt Capability

mTouch™ Technology Features:

• Up to 32 Channels

• Two Capacitive Sensing modules:

- Acquire 2 samples simultaneously

• Multiple Power modes:

- Operation during Sleep

- Proximity sensing with ultra low µA current

• Adjustable Waveform Min. and Max. for Optimal

Noise Performance

• 1.8V to 5.5V Operation (3.6V max. for

PIC16LF707)

• 8-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

• Processor Read Access to Program Memory

• Pinout Compatible to other 40-pin PIC16CXXX

and PIC16FXXX Microcontrollers

Analog Features:

Special Microcontroller Features:

• A/D Converter:

• Precision Internal Oscillator:

- 16 MHz or 500 kHz operation

- Factory calibrated to ±1%, typical

- Software selectable ÷1, ÷2, ÷4 or ÷8 divider

• 31 kHz Low-Power Internal Oscillator

• External Oscillator Block with:

- 3 crystal/resonator modes up to 20 MHz

- 3 external clock modes up to 20 MHz

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Oscillator Start-Up Timer (OST)

• Brown-out Reset (BOR):

- Selectable between two trip points

- Disabled in Sleep option

- 8-bit resolution and up to 14 channels

- Conversion available during Sleep

- Selectable 1.024V/2.048V/4.096V voltage

reference

• On-chip 3.2V Regulator (PIC16F707 device only)

Peripheral Highlights:

• Up to 35 I/O Pins and 1 Input-only Pin:

- High current source/sink for direct LED drive

- Interrupt-on-pin change

- Individually programmable weak pull-ups

• Timer0/A/B: 8-Bit Timer/Counter with 8-Bit

Prescaler

• Watchdog Timer (WDT)

• Enhanced Timer1/3:

• Programmable Code Protection

• In-Circuit Serial Programming™ (ICSP™) via two

pins

• In-Circuit Debug (ICD) via Two Pins

• Multiplexed Master Clear with Pull-up/Input Pin

• Industrial and Extended Temperature Range

• High-Endurance Flash Cell:

- 1,000 Write Flash Endurance (typical)

- Flash Retention: >40 years

- Power-Saving Sleep mode

- Dedicated low-power 32 kHz oscillator driver

- 16-bit timer/counter with prescaler

- External Gate Input mode with toggle and

single shot modes

- Interrupt-on-gate completion

• Timer2: 8-Bit Timer/Counter with 8-Bit Period

Register, Prescaler and Postscaler

• Two Capture, Compare, PWM modules (CCP):

- 16-bit Capture, max. resolution 12.5 ns

- 16-bit Compare, max. resolution 200 ns

- 10-bit PWM, max. frequency 20 kHz

• Addressable Universal Synchronous

Asynchronous Receiver Transmitter (AUSART)

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF707)

• 1.8V to 5.5V (PIC16F707)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 3

PIC16F707/PIC16LF707

• Synchronous Serial Port (SSP):

- SPI (Master/Slave)

- I²C™ (Slave) with Address Mask

• Voltage Reference module:

- Fixed voltage reference (FVR) with 1.024V,

2.048V and 4.096V output levels

- 5-bit rail-to-rail resistive DAC with positive

reference selection

Program

Memory Flash

(words)

Timers

8/16-bit

SRAM

(bytes)

Capacitive Touch 8-bit A/D

Device

I/Os

AUSART CCP

Channels

(ch)

PIC16F707

8192

363

36

32

14

Yes

2

4/2

PIC16LF707

Pin Diagrams

40-PIN PDIP

RB7/CPSB15/ICSPDAT

RB6/CPSB14/ICSPCLK

40

39

38

37

36

35

1

2

3

4

5

6

VPP/MCLR/RE3

(3)

(2)

VCAP /SS /AN0/RA0

CPSA0/AN1/RA1

RB5/AN13/CPSB13/T1G/T3CKI

RB4/AN11/CPSB12

DACOUT/CPSA1/AN2/RA2

CPSA2/VREF/AN3/RA3

TACKI/T0CKI/CPSA3/RA4

(1)

RB3/AN9/CPSB11/CCP2

RB2/AN8/CPSB10

RB1/AN10/CPSB9

RB0/AN12/CPSB8/INT

(3)

(2)

VCAP /SS /CPSA4/AN4/RA5

CPSA5/AN5/RE0

34

33

32

31

30

7

8

9

VDD

CPSA6/AN6/RE1

CPSA7/AN7/RE2

VDD

VSS

10

11

RD7/CPSA15

RD6/CPSA14

VSS

29

12

RD5/CPSA13

CLKIN/OSC1/CPSB0/RA7

28

27

26

25

13

14

15

16

(3)

RD4/CPSA12

VCAP /CLKOUT/OSC2/CPSB1/RA6

RC7/CPSA11/RX/DT

T1CKI/T1OSO/CPSB2/RC0

(1)

RC6/CPSA10/TX/CK

RC5/CPSA9/SDO

RC4/SDI/SDA

CCP2 /T1OSI/CPSB3/RC1

24

23

TBCKI/CCP1/CPSB4/RC2

SCL/SCK/RC3

17

18

RD3/CPSA8

T3G/CPSB5/RD0

CPSB6/RD1

22

21

19

20

RD2/CPSB7

Note 1: CCP2 pin location may be selected as RB3 or RC1.

2: SS pin location may be selected as RA5 or RA0.

3: PIC16F707 only.

DS41418A-page 4

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

Pin Diagrams

44-PIN QFN (8x8x0.9)

(3)

DT/RX/CPSA11/RC7

1

2

RA6/OSC2/CLKOUT/CPSB1/VCAP

RA7/OSC1/CLKIN/CPSB0

VSS

NC

VDD

33

32

31

30

29

28

27

26

CPSA12/RD4

CPSA13/RD5

CPSA14/RD6

CPSA15/RD7

VSS

3

4

5

PIC16F707

6

7

8

9

10

11

VDD

PIC16LF707

RE2/AN7/CPSA7

RE1/AN6/CPSA6

RE0/AN5/CPSA5

INT/CPSB8/AN12/RB0

CPSB9/AN10/RB1

CPSB10/AN8/RB2

25

24

23

(3)

RA5/AN4/CPSA4/SS⁽²⁾/VCAP

RA4/CPSA3/T0CKI/TACKI

Note 1: CCP2 pin location may be selected as RB3 or RC1.

2: SS pin location may be selected as RA5 or RA0.

3: PIC16F707 only.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 5

PIC16F707/PIC16LF707

Pin Diagrams

44-PIN TQFP

NC

1

2

3

4

33

32

31

30

29

28

27

DT/RX/CPSA11/RC7

CPSA12/RD4

RC0/T1OSO/T1CKI/CPSB2

RA6/OSC2/CLKOUT/CPSB1/VCAP

RA7/OSC1/CLKIN/CPSB0

VSS

(3)

CPSA13/RD5

CPSA14/RD6

CPSA15/RD7

VSS

5

PIC16F707

VDD

6

PIC16LF707

RE2/AN7/CPSA7

RE1/AN6/CPSA6

RE0/AN5/CPSA5

7

VDD

8

26

INT/CPSB8/AN12/RB0

CPSB9/AN10/RB1

CPSB10/AN8/RB2

CCP2⁽¹⁾/CPSB11/AN9/RB3

9

25

24

23

RA5/AN4/CPSA4/SS⁽²⁾/VCAP

(3)

10

11

RA4/CPSA3/T0CKI/TACKI

Note 1: CCP2 pin location may be selected as RB3 or RC1.

2: SS pin location may be selected as RA5 or RA0.

3: PIC16F707 only.

DS41418A-page 6

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 1:

40/44-PIN ALLOCATION TABLE FOR PIC16F707/PIC16LF707

(4)

SS⁽³⁾

—

RA0

2

19

Y

AN0

AN1

—

VCAP

RA1

RA2

RA3

3

4

5

20

21

22

20

21

22

Y

CPSA0

—

AN2 DACOUT CPSA1

—

AN3/

VREF

CPSA2

—

RA4

6

23

Y

—

CPSA3

T0CKI/

TACKI

—

SS⁽³⁾

—

VCAP

(4)

RA5

RA6

7

24

31

24

33

Y

AN4

—

CPSA4

CPSB1

—

14

OSC2/

CLKOUT/

(4)

VCAP

RA7

13

30

32

Y

—

CPSB0

—

OSC1/

CLKIN

RB0

RB1

RB2

RB3

RB4

RB5

33

34

35

36

37

38

8

9

Y

AN12

AN10

AN8

—

CPSB8

CPSB9

—

IOC/INT

IOC

Y

—

9

10

11

12

14

15

10

11

14

15

CPSB10

CPSB11

CPSB12

CPSB13

—

CCP2⁽²⁾

IOC

AN9

IOC

AN11

AN13

—

IOC

T1G/

—

IOC

T3CKI

RB6

RB7

RC0

39

40

15

16

17

32

16

17

34

Y

—

CPSB14

CPSB15

CPSB2

—

IOC

—

Y

ICSPCLK/

ICDCLK

—

ICSPDAT/

ICDDAT

T1OSO/

T1CKI

—

RC1

RC2

RC3

RC4

RC5

RC6

RC7

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

RE0

RE1

RE2

16

17

18

23

24

25

26

19

20

21

22

27

28

29

30

8

35

36

37

42

43

44

1

35

36

37

42

43

44

1

Y

—

Y

—

CPSB3

CPSB4

—

T1OSI

TBCKI

—

CCP2⁽²⁾

CCP1

—

SCK/SCL

—

SDI/SDA

SDO

—

CPSA9

CPSA10

CPSA11

CPSB5

CPSB6

CPSB7

CPSA8

CPSA12

CPSA13

CPSA14

CPSA15

CPSA5

CPSA6

CPSA7

—

TX/CK

RX/DT

—

38

39

40

41

2

38

39

40

41

2

—

T3G

—

3

—

4

—

5

—

25

26

27

25

26

27

AN5

AN6

AN7

—

9

—

10

—

RE3

1

18

—

Y⁽¹⁾

MCLR/

VPP

VDD

Vss

11, 32 7, 28

7,8,28

—

VDD

VSS

12, 31 6, 29 6, 30, 31

Note 1: Pull-up activated only with external MCLR configuration.

2: RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.

3: RA5 is the default pin location for SS. RA0 may be selected by changing the SSSEL bit in the APFCON register.

4: PIC16F707 only. VCAP functionality is selectable by the VCAPEN bits in Configuration Word 2.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 7

PIC16F707/PIC16LF707

Table of Contents

1.0 Device Overview ....................................................................................................................................................................... 11

2.0 Memory Organization................................................................................................................................................................ 17

3.0 Resets ....................................................................................................................................................................................... 29

4.0 Interrupts ................................................................................................................................................................................... 39

5.0 Low Dropout (LDO) Voltage Regulator ..................................................................................................................................... 49

6.0 I/O Ports .................................................................................................................................................................................... 51

7.0 Oscillator Module....................................................................................................................................................................... 69

8.0 Device Configuration ................................................................................................................................................................. 75

9.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 79

10.0 Fixed Voltage Reference........................................................................................................................................................... 89

11.0 Digital-to-Analog Converter (DAC) Module ............................................................................................................................... 91

12.0 Timer0 Module .......................................................................................................................................................................... 95

13.0 Timer1/3 Modules with Gate Control......................................................................................................................................... 99

14.0 TimerA/B Modules................................................................................................................................................................... 111

15.0 Timer2 Module ........................................................................................................................................................................ 115

16.0 Capacitive Sensing Module..................................................................................................................................................... 117

17.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................. 127

18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) .......................................................... 137

19.0 SSP Module Overview ............................................................................................................................................................ 157

20.0 Program Memory Read ........................................................................................................................................................... 179

21.0 Power-Down Mode (Sleep) ..................................................................................................................................................... 183

22.0 In-Circuit Serial Programming™ (ICSP™) .............................................................................................................................. 185

23.0 Instruction Set Summary......................................................................................................................................................... 187

24.0 Development Support.............................................................................................................................................................. 197

25.0 Electrical Specifications........................................................................................................................................................... 201

26.0 DC and AC Characteristics Graphs and Charts...................................................................................................................... 231

27.0 Packaging Information............................................................................................................................................................. 267

Appendix A: Data Sheet Revision History......................................................................................................................................... 273

Appendix B: Migrating From Other PIC® Devices ............................................................................................................................ 273

The Microchip Web Site.................................................................................................................................................................... 281

Customer Change Notification Service ............................................................................................................................................. 281

Customer Support ............................................................................................................................................................................. 281

Reader Response ............................................................................................................................................................................. 282

Product Identification System............................................................................................................................................................. 283

DS41418A-page 8

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Web site; http://www.microchip.com

Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 9

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 10

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

1.0

DEVICE OVERVIEW

The PIC16F707/PIC16LF707 devices are covered by

this data sheet. They are available in 40/44-pin

packages. Figure 1-1 shows a block diagram of the

PIC16F707/PIC16LF707 devices. Table 1-1 shows the

pinout descriptions.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 11

PIC16F707/PIC16LF707

FIGURE 1-1:

PIC16F707/PIC16LF707 BLOCK DIAGRAM

PORTA

Configuration

RA0

RA1

RA2

RA3

RA4

RA5

RA6

RA7

13

8

Data Bus

Program Counter

Flash

Program

Memory

8 Level Stack

(13-bit)

RAM

Program

Bus

PORTB

14

9

RAM Addr

RB0

RB1

RB2

Addr MUX

Instruction Reg

Instruction reg

RB3

RB4

RB5

RB6

RB7

Indirect

Addr

7

Direct Addr

8

FSR Reg

FSR reg

SSTTAATTUUSSRreegg

PORTC

8

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

3

MUX

Power-up

Timer

Oscillator

Start-up Timer

Instruction

DDeecocoddeea&nd

Control

ALU

Power-on

Reset

OSC1/CLKIN

OSC2/CLKOUT

PORTD

8

RD0

RD1

RD2

RD3

RD4

Timing

Generation

Watchdog

Timer

W Reg

Brown-out

Reset

LDO

Regulator

RD5

RD6

RD7

Internal

Oscillator

Block

CCP1

CCP2

PORTE

CCP1

RE0

RE1

MCLR VDD

VSS

RE2

RE3

CCP2

Timer1

32 kHz

T1OSI

T1OSO

Oscillator

SCK/

SDI/

SDO

SCL SS

SDA

TX/CK RX/DT

TBCKI

T0CKI

Timer0

T1G

T3G T3CKI TACKI

T1CKI

Synchronous

Serial Port

Timer1

Timer2

Timer3

TimerA TimerB

AUSART

VREF

Digital-To-Analog

Analog-To-Digital Converter

Converter

AN8 AN9 AN10 AN11

AN0 AN1

AN3 AN4

AN5 AN6 AN7

AN2

AN12 AN13

DACOUT

Capacitive Sensing Module A

CPSA0 CPSA1 CPSA2 CPSA3 CPSA4 CPSA5 CPSA6

CPSA7 CPSA8 CPSA9 CPSA10 CPSA11 CPSA12 CPSA13 CPSA14 CPSA15

Capacitive Sensing Module B

CPSB0 CPSB1 CPSB2 CPSB3 CPSB4 CPSB5 CPSB6

CPSB7 CPSB8 CPSB9 CPSB10 CPSB11 CPSB12 CPSB13 CPSB14 CPSB15

DS41418A-page 12

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 1-1:

PIC16F707/PIC16LF707 PINOUT DESCRIPTION

Input Output

Name

Function

Description

Type

RA0/AN0/SS/VCAP

RA0

AN0

TTL

AN

ST

CMOS General purpose I/O.

—

A/D Channel 0 input.

Slave Select input.

SS

VCAP

RA1

Power Power Filter capacitor for Voltage Regulator (PIC16F only).

RA1/AN1/CPSA0

TTL

AN

TTL

AN

—

CMOS General purpose I/O.

AN1

—

A/D Channel 1 input.

CPSA0

RA2

Capacitive sensing A input 0.

RA2/AN2/CPSA1/DACOUT

CMOS General purpose I/O.

AN2

—

A/D Channel 2 input.

CPSA1

DACOUT

RA3

Capacitive sensing A input 1.

Voltage Reference Output.

AN

RA3/AN3/VREF/CPSA2

TTL

AN

TTL

AN

ST

CMOS General purpose I/O.

AN3

—

A/D Channel 3 input.

VREF

A/D Voltage Reference input.

Capacitive sensing A input 2.

CPSA2

RA4

RA4/CPSA3/T0CKI/TACKI

RA5/AN4/CPSA4/SS/VCAP

CMOS General purpose I/O.

CPSA3

T0CKI

TACKI

RA5

—

Capacitive sensing A input 3.

Timer0 clock input.

TimerA clock input.

ST

TTL

AN

ST

CMOS General purpose I/O.

AN4

—

A/D Channel 4 input.

Capacitive sensing A input 4.

Slave Select input.

CPSA4

SS

VCAP

RA6

Power Power Filter capacitor for Voltage Regulator (PIC16F only).

RA6/OSC2/CLKOUT/VCAP/

CPSB1

TTL

—

CMOS General purpose I/O.

OSC2

CLKOUT

VCAP

CPSB1

RA7

XTAL Crystal/Resonator (LP, XT, HS modes).

CMOS FOSC/4 output.

—

Power Power Filter capacitor for Voltage Regulator (PIC16F only).

AN

TTL

—

Capacitive sensing B input 1.

RA7/OSC1/CLKIN/CPSB0

CMOS General purpose I/O.

OSC1

CLKIN

CPSB0

RB0

XTAL

CMOS

ST

—

Crystal/Resonator (LP, XT, HS modes).

External clock input (EC mode).

RC oscillator connection (RC mode).

Capacitive sensing B input 0.

AN

RB0/AN12/CPSB8/INT

RB1/AN10/CPSB9

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN12

CPSB8

INT

AN

ST

—

A/D Channel 12 input.

Capacitive sensing B input 8.

External interrupt.

RB1

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN10

AN

—

A/D Channel 10 input.

CPSB9

Capacitive sensing B input 9.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

HV = High Voltage

XTAL = Crystal levels

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 13

PIC16F707/PIC16LF707

TABLE 1-1:

PIC16F707/PIC16LF707 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

RB2/AN8/CPSB10

RB2

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN8

CPSB10

RB3

AN

—

A/D Channel 8 input.

Capacitive sensing B input 10.

RB3/AN9/CPSB11/CCP2

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN9

CPSB11

CCP2

RB4

AN

ST

—

A/D Channel 9 input.

Capacitive sensing B input 11.

CMOS Capture/Compare/PWM2.

RB4/AN11/CPSB12

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN11

CPSB12

RB5

AN

—

A/D Channel 11 input.

Capacitive sensing B input 12.

RB5/AN13/CPSB13/T1G/T3CKI

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN13

CPSB13

T1G

AN

ST

—

A/D Channel 13 input.

Capacitive sensing B input 13.

Timer1 gate input.

T3CKI

RB6

ST

Timer3 clock input.

RB6/ICSPCLK/ICDCLK/CPSB14

RB7/ICSPDAT/ICDDAT/CPSB15

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

ICSPCLK

ICDCLK

CPSB14

RB7

ST

—

Serial Programming Clock.

In-Circuit Debug Clock.

AN

TTL

Capacitive sensing B input 14.

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

ICSPDAT

ICDDAT

CPSB15

RC0

ST

CMOS ICSP™ Data I/O.

—

In-Circuit Data I/O.

AN

ST

Capacitive sensing B input 15.

RC0/T1OSO/T1CKI/CPSB2

RC1/T1OSI/CCP2/CPSB3

RC2/CCP1/CPSB4/TBCKI

RC3/SCK/SCL

CMOS General purpose I/O.

T1OSO

T1CKI

CPSB2

RC1

XTAL

ST

XTAL Timer1 oscillator connection.

—

Timer1 clock input.

AN

ST

Capacitive sensing B input 2.

CMOS General purpose I/O.

T1OSI

CCP2

CPSB3

RC2

XTAL

ST

XTAL Timer1 oscillator connection.

CMOS Capture/Compare/PWM2.

AN

ST

—

Capacitive sensing B input 3.

CMOS General purpose I/O.

CCP1

CPSB4

TBCKI

RC3

ST

CMOS Capture/Compare/PWM1.

AN

ST

—

Capacitive sensing B input 4.

TimerB clock input.

ST

CMOS General purpose I/O.

SCK

ST

CMOS SPI clock.

2

SCL

I C™

OD

I C™ clock.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

levels

XTAL = Crystal

DS41418A-page 14

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 1-1:

PIC16F707/PIC16LF707 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

RC4/SDI/SDA

RC4

SDI

ST

CMOS General purpose I/O.

—

SPI data input.

2

SDA

I C™

OD

I C™ data input/output.

RC5/SDO/CPSA9

RC6/TX/CK/CPSA10

RC5

ST

—

CMOS General purpose I/O.

CMOS SPI data output.

SDO

CPSA9

RC6

AN

ST

—

Capacitive sensing A input 9.

CMOS General purpose I/O.

TX

CMOS USART asynchronous transmit.

CMOS USART synchronous clock.

CK

ST

AN

ST

AN

ST

AN

ST

AN

ST

AN

ST

AN

ST

AN

ST

AN

ST

AN

ST

AN

ST

AN

ST

AN

ST

AN

TTL

ST

HV

Power

CPSA10

RC7

—

Capacitive sensing A input 10.

RC7/RX/DT/CPSA11

RD0/CPSB5/T3G

CMOS General purpose I/O.

RX

—

USART asynchronous input.

DT

CMOS USART synchronous data.

CPSA11

RD0

—

Capacitive sensing A input 11.

CMOS General purpose I/O.

CPSB5

T3G

—

Capacitive sensing B input 5.

Timer3 Gate input.

RD1/CPSB6

RD2/CPSB7

RD3/CPSA8

RD4/CPSA12

RD1

CMOS General purpose I/O.

CPSB6

RD2

—

Capacitive sensing B input 6.

CMOS General purpose I/O.

CPSB7

RD3

—

Capacitive sensing B input 7.

CMOS General purpose I/O.

CPSA8

RD4

—

Capacitive sensing A input 8.

General purpose I/O.

CMOS

—

CPSA12

RD5

Capacitive sensing A input 12.

General purpose I/O.

RD5/CPSA13

RD6/CPSA14

RD7/CPSA15

RE0/AN5/CPSA5

CMOS

—

CPSA13

RD6

Capacitive sensing A input 13.

General purpose I/O.

CMOS

—

CPSA14

RD7

Capacitive sensing A input 14.

General purpose I/O.

CMOS

—

CPSA15

RE0

Capacitive sensing A input 15.

CMOS General purpose I/O.

AN5

—

A/D Channel 5 input.

CPSA5

RE1

Capacitive sensing A input 5.

RE1/AN6/CPSA6

RE2/AN7/CPSA7

RE3/MCLR/VPP

VDD

CMOS General purpose I/O.

AN6

—

A/D Channel 6 input.

CPSA6

RE2

Capacitive sensing A input 6.

CMOS General purpose I/O.

AN7

—

A/D Channel 7 input.

CPSA7

RE3

Capacitive sensing A input 7.

General purpose input.

Master Clear with internal pull-up.

Programming voltage.

Positive supply.

MCLR

VPP

VDD

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

HV = High Voltage

XTAL = Crystal levels

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 15

PIC16F707/PIC16LF707

TABLE 1-1:

PIC16F707/PIC16LF707 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

VSS

Power

—

Ground reference.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note:

The PIC16F707 devices have an internal low dropout voltage regulator. An external capacitor must be

connected to one of the available VCAP pins to stabilize the regulator. For more information, see

Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16LF707 devices do not have the voltage

regulator and therefore no external capacitor is required.

DS41418A-page 16

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

2.2

Data Memory Organization

2.0

2.1

MEMORY ORGANIZATION

Program Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers (GPRs)

and the Special Function Registers (SFRs). Bits RP0

and RP1 are bank select bits.

The PIC16F707/PIC16LF707 has a 13-bit program

counter capable of addressing an 8K x 14 program

memory space. The Reset vector is at 0000h and the

interrupt vector is at 0004h.

RP1

0

RP0

0



Bank 0 is selected

Bank 1 is selected

Bank 2 is selected

Bank 3 is selected

0

1

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F707/PIC16LF707

1

0

1

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function

Registers are the General Purpose Registers,

implemented as static RAM. All implemented banks

contain Special Function Registers. Some frequently

used Special Function Registers from one bank are

mirrored in another bank for code reduction and

quicker access.

PC<12:0>

CALL, RETURN

RETFIE, RETLW

13

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

2.2.1

GENERAL PURPOSE REGISTER

FILE

0000h

The register file is organized as 363 x 8 bits. Each

register is accessed either directly or indirectly through

the File Select Register (FSR), (Refer to Section 2.5

“Indirect Addressing, INDF and FSR Registers”).

Interrupt Vector

Page 0

0004h

0005h

07FFh

0800h

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (refer to Table 2-2).

These registers are static RAM.

Page 1

On-chip

Program

Memory

0FFFh

1000h

Page 2

Page 3

The Special Function Registers can be classified into

two sets: core and peripheral. The Special Function

Registers associated with the “core” are described in

this section. Those related to the operation of the

peripheral features are described in the section of that

peripheral feature.

17FFh

1800h

1FFFh

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 17

PIC16F707/PIC16LF707

TABLE 2-1:

DATA MEMORY MAP FOR PIC16F707/PIC16LF707

File Address

(*)

Indirect addr.

00h

01h

02h

03h

04h

05h

06h

07h

Indirect addr.

OPTION

PCL

80h

81h

82h

83h

84h

85h

86h

87h

Indirect addr.

TMR0

100h

101h

102h

103h

104h

105h

106h

107h

Indirect addr.

OPTION

PCL

180h

181h

182h

183h

184h

185h

186h

187h

TMR0

PCL

STATUS

FSR

STATUS

FSR

STATUS

FSR

STATUS

FSR

ANSELA

ANSELB

PORTA

PORTB

PORTC

TRISA

TACON

CPSBCON0

CPSBCON1

CPSACON0

CPSACON1

TRISB

TRISC

ANSELC

ANSELD

PORTD

PORTE

PCLATH

INTCON

PIR1

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

TRISD

TRISE

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

1A0h

ANSELE

PCLATH

INTCON

PIE1

PCLATH

INTCON

PMDATL

PMADRL

PMDATH

PMADRH

TMRA

PCLATH

INTCON

PMCON1

Reserved

PIR2

PIE2

TMR1L

PCON

TMR1H

T1CON

TMR2

T1GCON

OSCCON

OSCTUNE

PR2

TBCON

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

TMRB

SSPADD/SSPMSK 93h

DACCON0

DACCON1

SSPSTAT

WPUB

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

IOCB

General

Purpose

Register

16 Bytes

T3CON

TXSTA

General

Purpose

Register

11 Bytes

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

SPBRG

TMR3L

TMR3H

APFCON

FVRCON

T3GCON

ADCON1

ADRES

ADCON0

General

Purpose

Register

80 Bytes

General

Purpose

Register

80 Bytes

General

Purpose

Register

80 Bytes

General

Purpose

Register

96 Bytes

EFh

F0h

16Fh

170h

1EFh

1F0h

Accesses

70h – 7Fh

Accesses

70h – 7Fh

Accesses

70h – 7Fh

FFh

17Fh

1FFh

7Fh

BANK 0

BANK 1

BANK 2

BANK 3

Legend:

= Unimplemented data memory locations, read as ‘0’,

*

= Not a physical register

DS41418A-page 18

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 2-2:

SPECIAL FUNCTION REGISTER SUMMARY

Value on all

other

resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 0

00h^{( 2)}

01h

02h^{( 2)}

03h^{( 2)}

04h^{( 2)}

05h

INDF

TMR0

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 Module Register

xxxx xxxx xxxx xxxx

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

---- xxxx ---- uuuu

---0 0000 ---0 0000

0000 000x 0000 000u

0000 0000 0000 0000

0000 ---0 0000 ---0

xxxx xxxx uuuu uuuu

PCL

Program Counter (PC) Least Significant Byte

STATUS

FSR

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

PORTA

PORTB

PORTC

PORTD

PORTE

PORTA Data Latch when written: PORTA pins when read

PORTB Data Latch when written: PORTB pins when read

PORTC Data Latch when written: PORTC pins when read

PORTD Data Latch when written: PORTD pins when read

06h

07h

08h

09h

—

RE3

RE2

RE1

RE0

0Ah^{( 1),( 2)}PCLATH

—

Write Buffer for the upper 5 bits of the Program Counter

0Bh^{( 2)}

0Ch

0Dh

0Eh

0Fh

10h

INTCON

PIR1

GIE

PEIE

ADIF

TMR3IF

TMR0IE

RCIF

INTE

TXIF

RBIE

SSPIF

—

TMR0IF

CCP1IF

—

INTF

TMR2IF

—

RBIF

TMR1GIF

TMR3GIF

TMR1IF

CCP2IF

PIR2

TMRBIF

TMRAIF

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TMR1H

T1CON

TMR2

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN

Timer2 Module Register

T1SYNC

—

TMR1ON 0000 00-0 uuuu uu-u

11h

0000 0000 0000 0000

12h

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0

TMR2ON

T2CKPS1 T2CKPS0 -000 0000 -000 0000

13h

Synchronous Serial Port Receive Buffer/Transmit Register

SSPEN CKP SSPM3 SSPM2

xxxx xxxx uuuu uuuu

14h

WCOL

SSPOV

SSPM1

SSPM0

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

15h

Capture/Compare/PWM Register 1 (LSB)

Capture/Compare/PWM Register 1 (MSB)

16h

17h

—

DC1B1

SREN

DC1B0

CREN

CCP1M3

ADDEN

CCP1M2

FERR

CCP1M1

OERR

CCP1M0 --00 0000 --00 0000

18h

SPEN

RX9

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

19h

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRES

ADCON0

USART Transmit Data Register

USART Receive Data Register

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

Legend:

Capture/Compare/PWM Register 2 (LSB)

Capture/Compare/PWM Register 2 (MSB)

—

DC2B1

DC2B0

A/D Result Register

CHS2 CHS1

CCP2M3

CCP2M2

CCP2M1

CCP2M0 --00 0000 --00 0000

xxxx xxxx uuuu uuuu

CHS3

CHS0

GO/DONE

ADON

--00 0000 --00 0000

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

upper byte of the program counter.

2: These registers can be addressed from any bank.

3: Accessible only when SSPM<3:0> = 1001.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 19

PIC16F707/PIC16LF707

TABLE 2-2:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 1

80h^{( 2)}

81h

82h^{( 2)}

83h^{( 2)}

84h^{( 2)}

85h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx xxxx xxxx

1111 1111 1111 1111

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

---- 1111 ---- 1111

---0 0000 ---0 0000

0000 000x 0000 000u

0000 0000 0000 0000

0000 ---0 0000 ---0

---- --qq ---- --uu

0000 0x00 uuuu uxuu

OPTION_REG

PCL

RBPU

INTEDG

TMR0CS TMR0SE

PSA

PS2

PS1

PS0

Program Counter (PC) Least Significant Byte

STATUS

FSR

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

PORTA Data Direction Register

PORTB Data Direction Register

PORTC Data Direction Register

PORTD Data Direction Register

TRISA

TRISB

TRISC

TRISD

TRISE

86h

87h

88h

89h

—

‘1’

TRISE2

TRISE1

TRISE0

8Ah^{( 1),( 2)}PCLATH

8Bh^{( 2)}

Write Buffer for the upper 5 bits of the Program Counter

INTCON

PIE1

GIE

PEIE

ADIE

TMR3IE

—

TMR0IE

RCIE

TMRBIE

—

INTE

TXIE

RBIE

SSPIE

—

TMR0IF

CCP1IE

—

INTF

TMR2IE

—

RBIF

TMR1IE

CCP2IE

BOR

8Ch

TMR1GIE

TMR3GIE

—

8Dh

PIE2

TMRAIE

—

8Eh

PCON

T1GCON

—

POR

8Fh

TMR1GE

T1GPOL

T1GTM

T1GSPM

T1GGO/

DONE

T1GVAL

T1GSS1

T1GSS0

90h

91h

92h

93h

93h⁽³⁾

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

OSCCON

OSCTUNE

PR2

—

IRCF1

TUN5

IRCF0

TUN4

ICSL

ICSS

—

--10 00-- --10 uu--

--00 0000 --00 0000

1111 1111 1111 1111

0000 0000 0000 0000

1111 1111 1111 1111

0000 0000 0000 0000

1111 1111 1111 1111

0000 0000 0000 0000

TUN3

TUN2

TUN1

TUN0

Timer2 Period Register

Synchronous Serial Port (I²C mode) Address Register

Synchronous Serial Port (I²C mode) Address Mask Register

SSPADD

SSPMSK

SSPSTAT

WPUB

SMP

WPUB7

IOCB7

CKE

D/A

P

S

WPUB3

IOCB3

—

R/W

WPUB2

IOCB2

T3SYNC

BRGH

BRG2

UA

WPUB1

IOCB1

—

BF

WPUB6

IOCB6

WPUB5

IOCB5

WPUB4

IOCB4

WPUB0

IOCB0

IOCB

T3CON

TXSTA

TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0

TMR3ON 0000 -0-0 uuuu -u-u

CSRC

BRG7

TX9

TXEN

BRG5

SYNC

BRG4

—

TRMT

BRG1

TX9D

BRG0

0000 -010 0000 -010

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

SPBRG

TMR3L

BRG6

BRG3

Holding Register for the Least Significant Byte of the 16-bit TMR3 Register

Holding Register for the Most Significant Byte of the 16-bit TMR3 Register

TMR3H

APFCON

FVRCON

T3GCON

—

SSSEL

ADFVR1

T3GSS1

CCP2SEL ---- --00 ---- --00

FVRRDY

TMR3GE

FVREN

T3GPOL

CDAFVR1

CDAFVR0

T3GVAL

ADFVR0

T3GSS0

x000 0000 x000 0000

0000 0x00 uuuu uxuu

T3GTM

T3GSPM

T3GGO/

DONE

9Fh

ADCON1

—

ADCS2

ADCS1

ADCS0

—

ADREF1

ADREF0 -000 --00 -000 --00

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

upper byte of the program counter.

2: These registers can be addressed from any bank.

3: Accessible only when SSPM<3:0> = 1001.

DS41418A-page 20

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 2-2:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 2

100h^{( 2)}

101h

102h^{( 2)}

103h^{( 2)}

104h^{( 2)}

105h

INDF

TMR0

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 Module Register

xxxx xxxx xxxx xxxx

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

0-00 0000 0-00 0000

00-- 0000 00-- 0000

PCL

Program Counter’s (PC) Least Significant Byte

STATUS

FSR

IRP

RP1

—

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

TACON

TMRAON

TACS

—

TASE

—

TAPSA

TAPS2

TAPS1

TAPS0

TBXCS

106h

CPSBCON0

CPSBCON1

CPSACON0

CPSACON1

CPSBON CPSBRM

CPSBRNG1 CPSBRNG0 CPSBOUT

CPSBCH3

CPSARNG1 CPSARNG0 CPSAOUT

CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000

107h

—

CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000

TAXCS 0--- 0000 0--- 0000

108h

CPSAON CPSARM

—

109h

—

10Ah^{( 1),(2)}PCLATH

—

Write Buffer for the upper 5 bits of the Program Counter

INTE RBIE TMR0IF INTF

---0 0000 ---0 0000

0000 000x 0000 000u

xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu

---x xxxx ---u uuuu

0000 0000 0000 0000

0-00 0000 0-00 0000

0000 0000 0000 0000

000- 00-- 000- 00--

---0 0000 ---0 0000

10Bh^{( 2)}

10Ch

10Dh

10Eh

10Fh

110h

INTCON

PMDATL

PMADRL

PMDATH

PMADRH

TMRA

GIE

PEIE

TMR0IE

RBIF

Program Memory Read Data Register Low Byte

Program Memory Read Address Register Low Byte

—

Program Memory Read Data Register High Byte

—

Program Memory Read Address Register High Byte

TimerA Module Register

111h

TBCON

TMRBON

—

TBCS

TBSE

TBPSA

TBPS2

TBPS1

TBPS0

112h

TMRB

TimerB Module Register

113h

DACCON0

DACCON1

DACEN

—

DACLPS

—

DACOE

—

DACPSS1

DACR3

DACPSS0

DACR2

—

114h

DACR4

DACR1

DACR0

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

upper byte of the program counter.

2: These registers can be addressed from any bank.

3: Accessible only when SSPM<3:0> = 1001.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 21

PIC16F707/PIC16LF707

TABLE 2-2:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 3

180h^{( 2)}

181h

182h^{( 2)}

183h^{( 2)}

184h^{( 2)}

185h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx xxxx xxxx

1111 1111 1111 1111

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

111- -111 111- -111

1111 1111 1111 1111

---- -111 ---- -111

---0 0000 ---0 0000

0000 000x 0000 000u

1--- ---0 1--- ---0

OPTION_REG

PCL

RBPU

INTEDG

TMR0CS TMR0SE

Program Counter (PC) Least Significant Byte

RP0 TO PD

Indirect Data Memory Address Pointer

PSA

PS2

PS1

PS0

STATUS

FSR

IRP

RP1

Z

DC

C

ANSELA

ANSELB

ANSELC

ANSELD

ANSELE

ANSA7

ANSB7

ANSC7

ANSD7

—

ANSA6

ANSB6

ANSC6

ANSD6

—

ANSA5

ANSB5

ANSC5

ANSD5

—

ANSA4

ANSB4

—

ANSA3

ANSB3

—

ANSA2

ANSB2

ANSC2

ANSD2

ANSE2

ANSA1

ANSB1

ANSC1

ANSD1

ANSE1

ANSA0

ANSB0

ANSC0

ANSD0

ANSE0

186h

187h

188h

ANSD4

—

ANSD3

—

189h

18Ah^{( 1),(2)}PCLATH

18Bh^{( 2)}

—

Write Buffer for the upper 5 bits of the Program Counter

INTCON

GIE

PEIE

—

TMR0IE

—

INTE

—

RBIE

—

TMR0IF

—

INTF

—

RBIF

RD

18Ch

PMCON1

—

18Dh

—

Reserved

—

18Eh

Reserved

18Fh

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

upper byte of the program counter.

2: These registers can be addressed from any bank.

3: Accessible only when SSPM<3:0> = 1001.

DS41418A-page 22

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u= unchanged).

2.2.2.1

STATUS Register

The STATUS register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section 23.0

“Instruction Set Summary”).

• the bank select bits for data memory (SRAM)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note 1: The C and DC bits operate as Borrow and

Digit Borrow out bits, respectively, in

subtraction.

REGISTER 2-1:

STATUS: STATUS REGISTER

R/W-0

IRP

R/W-0

RP1

R/W-0

RP0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC⁽¹⁾

R/W-x

C⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

IRP: Register Bank Select bit (used for indirect addressing)

1= Bank 2, 3 (100h-1FFh)

0= Bank 0, 1 (00h-FFh)

bit 6-5

RP<1:0>: Register Bank Select bits (used for direct addressing)

00= Bank 0 (00h-7Fh)

01= Bank 1 (80h-FFh)

10= Bank 2 (100h-17Fh)

11= Bank 3 (180h-1FFh)

bit 4

bit 3

bit 2

bit 1

bit 0

TO: Time-out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)⁽¹⁾

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

C: Carry/Borrow bit⁽¹⁾(ADDWF, ADDLW, SUBLW, SUBWF instructions)⁽¹⁾

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 23

PIC16F707/PIC16LF707

2.2.2.2

OPTION register

Note:

To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT by

setting PSA bit of the OPTION register to

‘1’. Refer to Section 13.3 “Timer1/3

Prescaler”.

The OPTION register, shown in Register 2-2, is a

readable and writable register, which contains various

control bits to configure:

• Timer0/WDT prescaler

• External RB0/INT interrupt

• Timer0

• Weak pull-ups on PORTB

REGISTER 2-2:

OPTION_REG: OPTION REGISTER

R/W-1

RBPU

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

TMR0CS

TMR0SE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RBPU: PORTB Pull-up Enable bit

1= PORTB pull-ups are disabled

0= PORTB pull-ups are enabled by individual bits in the WPUB register

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of RB0/INT pin

0= Interrupt on falling edge of RB0/INT pin

TMR0CS: Timer0 Clock Source Select bit

1= Transition on RA4/T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

TMR0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on RA4/T0CKI pin

0= Increment on low-to-high transition on RA4/T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

Bit Value

Timer0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

DS41418A-page 24

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

2.2.2.3

PCON Register

The Power Control (PCON) register contains flag bits

(refer to Table 3-4) to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

The PCON register bits are shown in Register 2-3.

REGISTER 2-3:

PCON: POWER CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-q

POR

R/W-q

BOR

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

q = Value depends on condition

bit 7-2

bit 1

Unimplemented: Read as ‘0’

POR: Power-on Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0

BOR: Brown-out Reset Status bit

1= No Brown-out Reset occurred

0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 25

PIC16F707/PIC16LF707

2.3

PCL and PCLATH

Note 1: There are no Status bits to indicate stack

The Program Counter (PC) is 13 bits wide. The low

byte comes from the PCL register, which is a readable

and writable register. The high byte (PC<12:8>) is not

directly readable or writable and comes from

PCLATH. On any Reset, the PC is cleared. Figure 2-2

shows the two situations for the loading of the PC. The

upper example in Figure 2-2 shows how the PC is

loaded on a write to PCL (PCLATH<4:0>  PCH).

The lower example in Figure 2-2 shows how the PC is

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL,

RETURN, RETLW and RETFIE instruc-

tions or the vectoring to an interrupt

address.

loaded during

(PCLATH<4:3>  PCH).

a

CALL or GOTO instruction

2.4

Program Memory Paging

All devices are capable of addressing a continuous 8K

word block of program memory. The CALL and GOTO

instructions provide only 11 bits of address to allow

branching within any 2K program memory page. When

doing a CALL or GOTO instruction, the upper 2 bits of

the address are provided by PCLATH<4:3>. When

doing a CALLor GOTOinstruction, the user must ensure

that the page select bits are programmed so that the

desired program memory page is addressed. If a return

from a CALL instruction (or interrupt) is executed, the

entire 13-bit PC is POPed off the stack. Therefore,

manipulation of the PCLATH<4:3> bits is not required

for the RETURNinstructions (which POPs the address

from the stack).

FIGURE 2-2:

LOADING OF PC IN

DIFFERENT SITUATIONS

PCH

PCL

Instruction with

12

8

7

0

PCL as

Destination

PC

8

PCLATH<4:0>

PCLATH

5

ALU Result

PCH

12 11 10

PC

PCL

8

7

0

GOTO, CALL

Note:

The contents of the PCLATH register are

unchanged after a RETURN or RETFIE

instruction is executed. The user must

rewrite the contents of the PCLATH regis-

ter for any subsequent subroutine calls or

GOTOinstructions.

PCLATH<4:3>

PCLATH

11

2

OPCODE<10:0>

2.3.1

A computed GOTOis accomplished by adding an offset

to the program counter (ADDWF PCL). When

COMPUTED GOTO

Example 2-1 shows the calling of a subroutine in

page 1 of the program memory. This example assumes

that PCLATH is saved and restored by the Interrupt

Service Routine (if interrupts are used).

performing a table read using a computed GOTO

method, care should be exercised if the table location

crosses a PCL memory boundary (each 256-byte

block). Refer to Application Note AN556,

“Implementing a Table Read” (DS00556).

EXAMPLE 2-1:

CALL OF A SUBROUTINE

IN PAGE 1 FROM PAGE 0

ORG 500h

PAGESELSUB_P1 ;Select page 1

;(800h-FFFh)

2.3.2

STACK

All devices have an 8-level x 13-bit wide hardware

stack (refer to Figure 2-1). The stack space is not part

of either program or data space and the Stack Pointer

is not readable or writable. The PC is PUSHed onto the

stack when a CALL instruction is executed or an

interrupt causes a branch. The stack is POPed in the

event of a RETURN, RETLW or a RETFIE instruction

execution. PCLATH is not affected by a PUSH or POP

operation.

CALL

:

SUB1_P1;Call subroutine in

;page 1 (800h-FFFh)

ORG

900h

;page 1 (800h-FFFh)

SUB1_P1

:

;called subroutine

;page 1 (800h-FFFh)

:

RETURN

;return to

;Call subroutine

;in page 0

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

PUSH overwrites the value that was stored from the

first PUSH. The tenth PUSH overwrites the second

PUSH (and so on).

;(000h-7FFh)

DS41418A-page 26

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

EXAMPLE 2-2:

INDIRECT ADDRESSING

2.5

Indirect Addressing, INDF and

FSR Registers

MOVLW

MOVWF

BANKISEL 020h

020h

FSR

;initialize pointer

;to RAM

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

NEXT CLRF

INDF

FSR

;clear INDF register

;inc pointer

INCF

BTFSS

GOTO

Indirect addressing is possible by using the INDF

register. Any instruction using the INDF register

actually accesses data pointed to by the File Select

Register (FSR). Reading INDF itself indirectly will

produce 00h. Writing to the INDF register indirectly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR register and the IRP bit of

the STATUS register, as shown in Figure 2-3.

FSR,4 ;all done?

NEXT ;no clear next

;yes continue

CONTINUE

A simple program to clear RAM location 020h-02Fh

using indirect addressing is shown in Example 2-2.

FIGURE 2-3:

DIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

From Opcode

7

RP1

RP0

6

0

IRP

File Select Register

Bank Select

180h

Location Select

Bank Select

Location Select

00h

00

01

10

11

Data

Memory

7Fh

1FFh

Bank 0

Bank 1

Bank 2

Bank 3

Note:

For memory map detail, refer to Table 2-2.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 27

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 28

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

Most registers are not affected by a WDT wake-up

since this is viewed as the resumption of normal

operation. TO and PD bits are set or cleared differently

in different Reset situations, as indicated in Table 3-3.

These bits are used in software to determine the nature

of the Reset.

3.0

RESETS

The PIC16F707/PIC16LF707 differentiates between

various kinds of Reset:

a) Power-on Reset (POR)

b) WDT Reset during normal operation

c) WDT Reset during Sleep

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 3-1.

d) MCLR Reset during normal operation

e) MCLR Reset during Sleep

f) Brown-out Reset (BOR)

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Section 25.0 “Electrical

Specifications” for pulse width specifications.

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on Reset (POR)

• MCLR Reset

• MCLR Reset during Sleep

• WDT Reset

• Brown-out Reset (BOR)

FIGURE 3-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

MCLRE

MCLR/VPP

Sleep

WDT

Module

Time-out

Reset

POR

Power-on Reset

VDD

Brown-out⁽¹⁾

Reset

BOREN

OST/PWRT

OST

10-bit Ripple Counter

Chip_Reset

OSC1/

CLKIN

PWRT

11-bit Ripple Counter

WDTOSC

Enable PWRT

Enable OST

Note 1: Refer to the Configuration Word Register 1 (Register 8-1).

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 29

PIC16F707/PIC16LF707

TABLE 3-1:

STATUS BITS AND THEIR SIGNIFICANCE

POR

BOR

TO

PD

Condition

0

1

x

0

1

0

x

1

0

u

1

x

0

1

0

u

0

Power-on Reset or LDO Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WDT Reset

WDT Wake-up

MCLR Reset during normal operation

MCLR Reset during Sleep or interrupt wake-up from Sleep

TABLE 3-2:

RESET CONDITION FOR SPECIAL REGISTERS⁽²⁾

Program

STATUS

Register

PCON

Register

Condition

Counter

Power-on Reset

0000h

0001 1xxx

000u uuuu

---- --0x

---- --uu

MCLR Reset during normal operation

0000h

MCLR Reset during Sleep

WDT Reset

0000h

0001 0uuu

0000 1uuu

uuu0 0uuu

0001 1uuu

uuu1 0uuu

---- --uu

---- --u0

---- --uu

WDT Wake-up

PC + 1

Brown-out Reset

0000h

PC + 1⁽¹⁾

Interrupt Wake-up from Sleep

Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and global enable bit (GIE) is set, the return address is pushed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

DS41418A-page 30

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

3.1

MCLR

3.3

Power-up Timer (PWRT)

The PIC16F707/PIC16LF707 has a noise filter in the

MCLR Reset path. The filter will detect and ignore

small pulses.

The Power-up Timer provides a fixed 64 ms (nominal)

time-out on power-up only, from POR or Brown-out

Reset. The Power-up Timer operates from the WDT

oscillator. For more information, see Section 7.3

“Internal Clock Modes”. The chip is kept in Reset as

long as PWRT is active. The PWRT delay allows the

VDD to rise to an acceptable level. A Configuration bit,

PWRTE, can disable (if set) or enable (if cleared or pro-

grammed) the Power-up Timer. The Power-up Timer

should be enabled when Brown-out Reset is enabled,

although it is not required.

It should be noted that a Reset does not drive the

MCLR pin low.

Voltages applied to the pin that exceed its specification

can result in both MCLR Resets and excessive current

beyond the device specification during the ESD event.

For this reason, Microchip recommends that the MCLR

pin no longer be tied directly to VDD. The use of an RC

network, as shown in Figure 3-2, is suggested.

The Power-up Timer delay will vary from chip-to-chip

and vary due to:

An internal MCLR option is enabled by clearing the

MCLRE bit in the Configuration Word register. When

MCLRE = 0, the Reset signal to the chip is generated

internally. When the MCLRE = 1, the RE3/MCLR pin

becomes an external Reset input. In this mode, the

RE3/MCLR pin has a weak pull-up to VDD. In-Circuit

Serial Programming is not affected by selecting the

internal MCLR option.

• VDD variation

• Temperature variation

• Process variation

See DC parameters for details (Section 25.0

“Electrical Specifications”).

Note:

The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word 1.

FIGURE 3-2:

RECOMMENDED MCLR

CIRCUIT

3.4

Watchdog Timer (WDT)

VDD

R1

PIC^®MCU

The WDT has the following features:

• Shares an 8-bit prescaler with Timer0

10 k

• Time-out period is from 17 ms to 2.2 seconds,

nominal

MCLR

• Enabled by a Configuration bit

WDT is cleared under certain conditions described in

Table 3-3.

C1

0.1 F

3.4.1

WDT OSCILLATOR

The WDT derives its time base from 31 kHz internal

oscillator.

3.2

Power-on Reset (POR)

Note:

When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,

because the WDT Ripple Counter is used

by the OST to perform the oscillator delay

count. When the OST count has expired,

the WDT will begin counting (if enabled).

The on-chip POR circuit holds the chip in Reset until VDD

has reached a high enough level for proper operation. A

maximum rise time for VDD is required. See

Section 25.0 “Electrical Specifications” for details. If

the BOR is enabled, the maximum rise time specification

does not apply. The BOR circuitry will keep the device in

Reset until VDD reaches VBOR (see Section 3.5

“Brown-Out Reset (BOR)”).

When the device starts normal operation (exits the

Reset condition), device operating parameters (i.e.,

voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 31

PIC16F707/PIC16LF707

3.4.2

WDT CONTROL

The WDTE bit is located in the Configuration Word

Register 1. When set, the WDT runs continuously.

The PSA and PS<2:0> bits of the OPTION register

control the WDT period. See Section 12.0 “Timer0

Module” for more information.

FIGURE 3-3:

WATCHDOG TIMER BLOCK DIAGRAM

TxGSS = 11

TMRxGE

From TMR0

Clock Source

WDTE

Low-Power

WDT OSC

0

1

Postscaler

8

Divide by

512

PS<2:0>

TO TMR0

0

1

PSA

WDT Reset

To TxG

WDTE

TABLE 3-3:

WDT STATUS

Conditions

WDT

Cleared

WDTE = 0

CLRWDTCommand

Exit Sleep + System Clock = EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

DS41418A-page 32

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

If VDD falls below VBOR for greater than parameter

(TBOR) (see Section 25.0 “Electrical Specifica-

tions”), the brown-out situation will reset the device.

This will occur regardless of VDD slew rate. A Reset is

not ensured to occur if VDD falls below VBOR for more

than parameter (TBOR).

3.5

Brown-Out Reset (BOR)

Brown-out Reset is enabled by programming the

BOREN<1:0> bits in the Configuration register. The

brown-out trip point is selectable from two trip points

via the BORV bit in the Configuration register.

Between the POR and BOR, complete voltage range

coverage for execution protection can be imple-

mented.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

Two bits are used to enable the BOR. When

BOREN = 11, the BOR is always enabled. When

BOREN = 10, the BOR is enabled, but disabled during

Sleep. When BOREN = 0X, the BOR is disabled.

Note:

When erasing Flash program memory, the

BOR is forced to enabled at the minimum

BOR setting to ensure that any code

protection circuitry is operating properly.

FIGURE 3-4:

BROWN-OUT SITUATIONS

VDD

VBOR

Internal

Reset

(1)

64 ms

VDD

VBOR

Internal

Reset

< 64 ms

(1)

64 ms

VDD

VBOR

Internal

Reset

(1)

64 ms

Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 33

PIC16F707/PIC16LF707

3.6

Time-out Sequence

3.7

Power Control (PCON) Register

On power-up, the time-out sequence is as follows: first,

PWRT time-out is invoked after POR has expired, then

OST is activated after the PWRT time-out has expired.

The total time-out will vary based on oscillator configu-

ration and PWRTE bit status. For example, in EC mode

with PWRTE bit = 1(PWRT disabled), there will be no

time-out at all. Figure 3-5, Figure 3-6 and Figure 3-7

depict time-out sequences.

The Power Control (PCON) register has two Status bits

to indicate what type of Reset that last occurred.

Bit 0 is BOR (Brown-out Reset). BOR is unknown on

Power-on Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0,

indicating that a brown-out has occurred. The BOR

Status bit is a “don’t care” and is not necessarily

predictable if the brown-out circuit is disabled

(BOREN<1:0> = 00in the Configuration Word register).

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then,

bringing MCLR high will begin execution immediately

(see Figure 3-6). This is useful for testing purposes or

to synchronize more than one PIC16F707/

PIC16LF707 device operating in parallel.

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset has occurred (i.e., VDD may have

gone too low).

Table 3-2 shows the Reset conditions for some special

registers.

For more information, see Section 3.5 “Brown-Out

Reset (BOR)”.

TABLE 3-4:

TIME-OUT IN VARIOUS SITUATIONS

Power-up

Brown-out Reset

Wake-up from

Oscillator Configuration

Sleep

PWRTE = 0

PWRTE = 1

PWRTE = 0

PWRTE = 1

TPWRT + 1024 •

TOSC

1024 • TOSC

TPWRT + 1024 •

TOSC

1024 • TOSC

—

XT, HS, LP

RC, EC, INTOSC

TPWRT

—

TPWRT

—

FIGURE 3-5:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

DS41418A-page 34

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 3-6:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 3-7:

TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 35

PIC16F707/PIC16LF707

TABLE 3-5:

Register

INITIALIZATION CONDITION FOR REGISTERS

Power-on Reset/

MCLR Reset/

WDT Reset

Wake-up from Sleep through

Interrupt/Time-out

Address

Brown-out Reset⁽¹⁾

W

—

xxxx xxxx

uuuu uuuu

xxxx xxxx

uuuu uuuu

INDF

00h/80h/

100h/180h

TMR0

PCL

01h/101h

xxxx xxxx

0000 0000

uuuu uuuu

0000 0000

uuuu uuuu

PC + 1⁽³⁾

02h/82h/

102h/182h

STATUS

FSR

03h/83h/

103h/183h

0001 1xxx

xxxx xxxx

000q quuu⁽⁴⁾

uuuu uuuu

uuuq quuu⁽⁴⁾

uuuu uuuu

04h/84h/

104h/184h

PORTA

PORTB

PORTC

PORTD

PORTE

PCLATH

05h

06h

07h

08h

09h

xxxx xxxx

---- xxxx

---0 0000

xxxx xxxx

---- xxxx

---0 0000

uuuu uuuu

---- uuuu

---u uuuu

0Ah/8Ah/

10Ah/18Ah

INTCON

0Bh/8Bh/

0000 000x

uuuu uuuu⁽²⁾

10Bh/18Bh

PIR1

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

0000 0000

0000 ---0

xxxx xxxx

0000 00-0

0000 0000

-000 0000

xxxx xxxx

0000 0000

xxxx xxxx

--00 0000

0000 000x

0000 0000

xxxx xxxx

--00 0000

xxxx xxxx

0000 0000

0000 ---0

uuuu uuuu

uuuu uu-u

0000 0000

-000 0000

xxxx xxxx

0000 0000

xxxx xxxx

--00 0000

0000 000x

0000 0000

xxxx xxxx

--00 0000

uuuu uuuu

uuuu uuuu⁽²⁾

uuuu ---u⁽²⁾

uuuu uuuu

uuuu uu-u

uuuu uuuu

-uuu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

PIR2

TMR1L

TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRES

Legend: u= unchanged, x= unknown, - = unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 3-2 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

DS41418A-page 36

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 3-5:

Register

INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

Power-on Reset/

MCLR Reset/

WDT Reset

Wake-up from Sleep through

Interrupt/Time-out

Address

Brown-out Reset⁽¹⁾

ADCON0

1Fh

--00 0000

1111 1111

---- 1111

0000 0000

0000 ---0

---- --qq

0000 0x00

--10 qq--

--00 0000

1111 1111

0000 0000

1111 1111

0000 0000

1111 1111

0000 0000

0000 -0-0

0000 -010

0000 0000

xxxx xxxx

---- --00

q000 0000

-000 --00

0-00 0000

00-- 0000

---- 0000

00-- 0000

---- 0000

xxxx xxxx

--xx xxxx

---x xxxx

0000 0000

--00 0000

1111 1111

---- 1111

0000 0000

0000 ---0

---- --uu^(1,5)

uuuu uxuu

--10 qq--

--uu uuuu

1111 1111

0000 0000

1111 1111

0000 0000

1111 1111

0000 0000

0000 -0-0

0000 -010

0000 0000

uuuu uuuu

---- --00

q000 0000

-000 --00

0-00 0000

00-- 0000

---- 0000

00-- 0000

---- 0000

xxxx xxxx

--xx xxxx

---x xxxx

0000 0000

--uu uuuu

uuuu uuuu

---- uuuu

uuuu uuuu

uuuu ---u

---- --uu

uuuu uxuu

--uu qq--

--uu uuuu

uuuu uuuu

uuuu -u-u

uuuu -uuu

uuuu uuuu

---- --uu

q000 0000

-uuu --uu

u-uu uuuu

uu-- uuuu

---- uuuu

uu-- uuuu

---- uuuu

uuuu uuuu

--uu uuuu

---u uuuu

uuuu uuuu

OPTION_REG 81h/181h

TRISA

85h

86h

TRISB

TRISC

87h

TRISD

88h

TRISE

89h

PIE1

8Ch

8Dh

8Eh

8Fh

90h

PIE2

PCON

T1GCON

OSCCON

OSCTUNE

PR2

91h

92h

SSPADD

SSPMSK

SSPSTAT

WPUB

93h

94h

95h

IOCB

96h

T3CON

TXSTA

97h

98h

SPBRG

TMR3L

99h

9Ah

9Bh

9Ch

9Dh

9Fh

105h

106h

107h

108h

109h

10Ch

10Dh

10Eh

10Fh

110h

TMR3H

APFCON

FVRCON

ADCON1

TACON

CPSBCON0

CPSBCON1

CPSACON0

CPSACON1

PMDATL

PMADRL

PMDATH

PMADRH

TMRA

Legend: u= unchanged, x= unknown, - = unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 3-2 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 37

PIC16F707/PIC16LF707

TABLE 3-5:

Register

INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

Power-on Reset/

MCLR Reset/

WDT Reset

Wake-up from Sleep through

Interrupt/Time-out

Address

Brown-out Reset⁽¹⁾

TBCON

111h

112h

113h

114h

185h

186h

187h

188h

189h

18Ch

0-00 0000

0000 0000

000- 00--

---0 0000

1111 1111

---- -111

1--- ---0

0-00 0000

0000 0000

000- 00--

---0 0000

1111 1111

---- -111

1--- ---0

u-uu uuuu

uuuu uuuu

uuu- uu--

---u uuuu

uuuu uuuu

---- -uuu

u--- ---u

TMRB

DACCON0

DACCON1

ANSELA

ANSELB

ANSELC

ANSELD

ANSELE

PMCON1

Legend: u= unchanged, x= unknown, - = unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 3-2 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

TABLE 3-6:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Value on

all other

Resets⁽¹⁾

Value on

POR, BOR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

STATUS

PCON

IRP

—

RP1

—

RP0

—

TO

—

PD

—

Z

DC

C

0001 1xxx 000q quuu

---- --qq ---- --uu

—

POR

BOR

Legend:

u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’, q= value depends on condition. Shaded cells are

not used by Resets.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

DS41418A-page 38

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

• AUSART Receive Interrupt

• AUSART Transmit Interrupt

• SSP Event Interrupt

4.0

INTERRUPTS

The PIC16F707/PIC16LF707 device family features an

interruptible core, allowing certain events to preempt

normal program flow. An Interrupt Service Routine

(ISR) is used to determine the source of the interrupt

and act accordingly. Some interrupts can be configured

to wake the MCU from Sleep mode.

• CCP1 Event Interrupt

• Timer2 Match with PR2 Interrupt

• Timer1 Overflow Interrupt

• CCP2 Event Interrupt

The PIC16F707 family has 16 interrupt sources,

differentiated by corresponding interrupt enable and

flag bits:

• TimerA Overflow Interrupt

• TimerB Overflow Interrupt

• Timer3 Overflow Interrupt

• Timer3 Gate Interrupt

• Timer0 Overflow Interrupt

• External Edge Detect on INT Pin Interrupt

• PORTB Change Interrupt

A block diagram of the interrupt logic is shown in

Figure 4-1.

• Timer1 Gate Interrupt

• A/D Conversion Complete Interrupt

FIGURE 4-1:

INTERRUPT LOGIC

IOC-RB0

IOCB0

IOC-RB1

IOCB1

SSPIF

SSPIE

IOC-RB2

IOCB2

TXIF

TXIE

IOC-RB3

IOCB3

RCIF

RCIE

(1)

Wake-up (If in Sleep mode)

IOC-RB4

IOCB4

TMR0IF

TMR0IE

TMR2IF

TMR2IE

Interrupt to CPU

IOC-RB5

IOCB5

INTF

INTE

RBIF

TMR1IF

TMR1IE

IOC-RB6

IOCB6

RBIE

ADIF

ADIE

PEIE

GIE

IOC-RB7

IOCB7

TMR1GIF

TMR1GIE

CCP1IF

CCP1IE

CCP2IF

CCP2IE

TMRAIF

TMRAIE

Note 1: Some peripherals depend upon the

system clock for operation. Since the

system clock is suspended during

Sleep, these peripherals will not wake

the part from Sleep. See Section 21.1

“Wake-up from Sleep”.

TMRBIF

TMRBIE

TMR3IF

TMR3IE

TMR3GIF

TMR3GIE

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 39

PIC16F707/PIC16LF707

interrupts. Because the GIE bit is cleared, any interrupt

that occurs while executing the ISR will be recorded

through its interrupt flag, but will not cause the

processor to redirect to the interrupt vector.

4.1

Operation

Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:

• GIE bit of the INTCON register

The RETFIE instruction exits the ISR by popping the

• Interrupt enable bit(s) for the specific interrupt

event(s)

previous address from the stack and setting the GIE bit.

For additional information on a specific interrupt’s

operation, refer to its peripheral chapter.

• PEIE bit of the INTCON register (if the interrupt

enable bit of the interrupt event is contained in the

PIE1 and PIE2 registers)

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other

enable bits.

The INTCON, PIR1 and PIR2 registers record individ-

ual interrupts via interrupt flag bits. Interrupt flag bits will

be set, regardless of the status of the GIE, PEIE and

individual Interrupt Enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring

while the GIE bit is clear will be serviced

when the GIE bit is set again.

The following events happen when an interrupt event

occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

4.2

Interrupt Latency

Interrupt latency is defined as the time from when the

interrupt event occurs to the time code execution at the

interrupt vector begins. The latency for synchronous

interrupts is 3 instruction cycles. For asynchronous

interrupts, the latency is 3 to 4 instruction cycles,

depending on when the interrupt occurs. See Figure 4-2

for timing details.

• Current Program Counter (PC) is pushed onto the

stack

• PC is loaded with the interrupt vector 0004h

The ISR determines the source of the interrupt by

polling the interrupt flag bits. The interrupt flag bits must

be cleared before exiting the ISR to avoid repeated

FIGURE 4-2:

INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(3)

CLKOUT

(4)

INT pin

(1)

(2)

(5)

Interrupt Latency

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

PC

PC + 1

—

0004h

0005h

PC

Inst (PC)

PC + 1

Instruction

Fetched

Inst (0004h)

Inst (PC + 1)

Inst (0005h)

Inst (0004h)

Instruction

Executed

Dummy Cycle

Inst (PC)

Inst (PC – 1)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTOSC and RC Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 25.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

DS41418A-page 40

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

following the ISR from using invalid data. Examples of

key registers include the W, STATUS, FSR and

PCLATH registers.

4.3

Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To

wake from Sleep, the peripheral must be able to

operate without the system clock. The interrupt source

must have the appropriate interrupt enable bit(s) set

prior to entering Sleep.

Note:

The microcontroller does not normally

require saving the PCLATH register.

However, if computed GOTO’s are used,

the PCLATH register must be saved at the

beginning of the ISR and restored when

the ISR is complete to ensure correct

program flow.

On waking from Sleep, if the GIE bit is also set, the

processor will branch to the interrupt vector. Otherwise,

the processor will continue executing instructions after

the SLEEPinstruction. The instruction directly after the

SLEEP instruction will always be executed before

branching to the ISR. Refer to Section 21.0 “Power-

Down Mode (Sleep)” for more details.

The code shown in Example 4-1 can be used to do the

following.

• Save the W register

• Save the STATUS register

• Save the PCLATH register

• Execute the ISR program

• Restore the PCLATH register

• Restore the STATUS register

• Restore the W register

4.4

INT Pin

The external interrupt, INT pin, causes an

asynchronous, edge-triggered interrupt. The INTEDG bit

of the OPTION register determines on which edge the

interrupt will occur. When the INTEDG bit is set, the

rising edge will cause the interrupt. When the INTEDG

bit is clear, the falling edge will cause the interrupt. The

INTF bit of the INTCON register will be set when a valid

edge appears on the INT pin. If the GIE and INTE bits

are also set, the processor will redirect program

execution to the interrupt vector. This interrupt is

disabled by clearing the INTE bit of the INTCON register.

Since most instructions modify the W register, it must

be saved immediately upon entering the ISR. The

SWAPF instruction is used when saving and restoring

the W and STATUS registers because it will not affect

any bits in the STATUS register. It is useful to place

W_TEMP in shared memory because the ISR cannot

predict which bank will be selected when the interrupt

occurs.

4.5

Context Saving

The processor will branch to the interrupt vector by

loading the PC with 0004h. The PCLATH register will

remain unchanged. This requires the ISR to ensure

that the PCLATH register is set properly before using

an instruction that causes PCLATH to be loaded into

the PC. See Section 2.3 “PCL and PCLATH” for

details on PC operation.

When an interrupt occurs, only the return PC value is

saved to the stack. If the ISR modifies or uses an

instruction that modifies key registers, their values

must be saved at the beginning of the ISR and restored

when the ISR completes. This prevents instructions

EXAMPLE 4-1:

SAVING W, STATUS AND PCLATH REGISTERS IN RAM

;Copy W to W_TEMP register

MOVWF

SWAPF

W_TEMP

STATUS,W

;Swap status to be saved into W

;Swaps are used because they do not affect the status bits

;Select regardless of current bank

BANKSEL STATUS_TEMP

MOVWF

MOVF

MOVWF

:

STATUS_TEMP

PCLATH,W

PCLATH_TEMP

;Copy status to bank zero STATUS_TEMP register

;Copy PCLATH to W register

;Copy W register to PCLATH_TEMP

:(ISR)

:

;Insert user code here

BANKSEL STATUS_TEMP

;Select regardless of current bank

;

;Restore PCLATH

;Swap STATUS_TEMP register into W

;(sets bank to original state)

;Move W into STATUS register

;Swap W_TEMP

MOVF

MOVWF

SWAPF

PCLATH_TEMP,W

PCLATH

STATUS_TEMP,W

MOVWF

SWAPF

STATUS

W_TEMP,F

W_TEMP,W

;Swap W_TEMP into W

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 41

PIC16F707/PIC16LF707

4.5.1

INTCON REGISTER

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User software should ensure the appropri-

ate interrupt flag bits are clear prior to

enabling an interrupt.

The INTCON register is a readable and writable

register, which contains the various enable and flag bits

for TMR0 register overflow, PORTB change and

external RB0/INT/SEG0 pin interrupts.

REGISTER 4-1:

INTCON: INTERRUPT CONTROL REGISTER

R/W-0

GIE

R/W-0

PEIE

R/W-0

INTE

R/W-0

RBIE⁽¹⁾

R/W-0

TMR0IF⁽²⁾

R/W-0

INTF

R/W-x

RBIF

TMR0IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

GIE: Global Interrupt Enable bit

1= Enables all unmasked interrupts

0= Disables all interrupts

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PEIE: Peripheral Interrupt Enable bit

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

TMR0IE: Timer0 Overflow Interrupt Enable bit

1= Enables the Timer0 interrupt

0= Disables the Timer0 interrupt

INTE: RB0/INT External Interrupt Enable bit

1= Enables the RB0/INT external interrupt

0= Disables the RB0/INT external interrupt

RBIE: PORTB Change Interrupt Enable bit⁽¹⁾

1= Enables the PORTB change interrupt

0= Disables the PORTB change interrupt

TMR0IF: Timer0 Overflow Interrupt Flag bit⁽²⁾

1= TMR0 register has overflowed (must be cleared in software)

0= TMR0 register did not overflow

INTF: RB0/INT External Interrupt Flag bit

1= The RB0/INT external interrupt occurred (must be cleared in software)

0= The RB0/INT external interrupt did not occur

RBIF: PORTB Change Interrupt Flag bit

1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in

software)

0= None of the PORTB general purpose I/O pins have changed state

Note 1: The appropriate bits in the IOCB register must also be set.

2: TMR0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before

clearing TMR0IF bit.

DS41418A-page 42

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

4.5.2

PIE1 REGISTER

The PIE1 register contains the interrupt enable bits, as

shown in Register 4-2.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 4-2:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

TMR1GIE

bit 7

R/W-0

ADIE

R/W-0

RCIE

R/W-0

TXIE

R/W-0

SSPIE

R/W-0

CCP1IE

TMR2IE

TMR1IE

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TMR1GIE: Timer1 Gate Interrupt Enable bit

1= Enable the Timer1 gate acquisition complete interrupt

0= Disable the Timer1 gate acquisition complete interrupt

ADIE: A/D Converter (ADC) Interrupt Enable bit

1= Enables the ADC interrupt

0= Disables the ADC interrupt

RCIE: USART Receive Interrupt Enable bit

1= Enables the USART receive interrupt

0= Disables the USART receive interrupt

TXIE: USART Transmit Interrupt Enable bit

1= Enables the USART transmit interrupt

0= Disables the USART transmit interrupt

SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit

1= Enables the SSP interrupt

0= Disables the SSP interrupt

CCP1IE: CCP1 Interrupt Enable bit

1= Enables the CCP1 interrupt

0= Disables the CCP1 interrupt

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1= Enables the Timer2 to PR2 match interrupt

0= Disables the Timer2 to PR2 match interrupt

TMR1IE: Timer1 Overflow Interrupt Enable bit

1= Enables the Timer1 overflow interrupt

0= Disables the Timer1 overflow interrupt

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 43

PIC16F707/PIC16LF707

4.5.3

PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as

shown in Register 4-3.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 4-3:

R/W-0

PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

TMR3GIE

bit 7

TMR3IE

TMRBIE

TMRAIE

CCP2IE

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other

Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

TMR3GIE: Timer3 Gate Interrupt Flag bit

1= Enable the Timer3 gate acquisition complete interrupt

0= Disable the Timer3 gate acquisition complete interrupt

TMR3IE: Timer3 Overflow Interrupt Enable bit

1= Enables the Timer3 overflow interrupt

0= Disables the Timer3 overflow interrupt

TMRBIE: TimerB Overflow Interrupt Enable bit

1= Enables the TimerB interrupt

0= Disables the TimerB interrupt

TMRAIE: TimerA Overflow Interrupt Enable bit

1= Enables the TimerA interrupt

0= Disables the TimerA interrupt

bit 3-1

bit 0

Unimplemented: Read as '0'

CCP2IE: CCP2 Interrupt Enable bit

1= Enables the CCP2 interrupt

0= Disables the CCP2 interrupt

DS41418A-page 44

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

4.5.4

PIR1 REGISTER

The PIR1 register contains the interrupt flag bits, as

shown in Register 4-4.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

REGISTER 4-4:

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0

TMR1GIF

bit 7

R/W-0

ADIF

R-0

R/W-0

SSPIF

R/W-0

RCIF

TXIF

CCP1IF

TMR2IF

TMR1IF

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

TMR1GIF: Timer1 Gate Interrupt Flag bit

1= Timer1 gate is inactive

0= Timer1 gate is active

ADIF: A/D Converter Interrupt Flag bit

1= A/D conversion complete (must be cleared in software)

0= A/D conversion has not completed or has not been started

RCIF: USART Receive Interrupt Flag bit

1= The USART receive buffer is full (cleared by reading RCREG)

0= The USART receive buffer is not full

TXIF: USART Transmit Interrupt Flag bit

1= The USART transmit buffer is empty (cleared by writing to TXREG)

0= The USART transmit buffer is full

SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit

1= The Transmission/Reception is complete (must be cleared in software)

0= Waiting to Transmit/Receive

CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1= A Timer1 register capture occurred (must be cleared in software)

0= No Timer1 register capture occurred

Compare mode:

1= A Timer1 register compare match occurred (must be cleared in software)

0= No Timer1 register compare match occurred

PWM mode:

Unused in this mode

bit 1

bit 0

TMR2IF: Timer2 to PR2 Interrupt Flag bit

1= A Timer2 to PR2 match occurred (must be cleared in software)

0= No Timer2 to PR2 match occurred

TMR1IF: Timer1 Overflow Interrupt Flag bit

1= The Timer1 register overflowed (must be cleared in software)

0= The Timer1 register did not overflow

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 45

PIC16F707/PIC16LF707

4.5.5

PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as

shown in Register 4-5.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

REGISTER 4-5:

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0

TMR3GIF

bit 7

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

TMR3IF

TMRBIF

TMRAIF

CCP2IF

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

TMR3GIF: Timer3 Gate Interrupt Flag bit

1= Timer3 gate is inactive

0= Timer3 gate is active

TMR3IF: Timer3 Overflow Interrupt Flag bit

1= Timer3 register overflowed (must be cleared in software)

0= Timer3 register did not overflow

TMRBIF: TimerB Overflow Interrupt Flag bit

1= TimerB register has overflowed (must be cleared in software)

0= TimerB register did not overflow

TMRAIF: TimerA Overflow Interrupt Flag bit

1= TimerA register has overflowed (must be cleared in software)

0= TimerA register did not overflow

bit 3-1

bit 0

Unimplemented: Read as ‘0’

CCP2IF: CCP2 Interrupt Flag bit

Capture Mode

1= A Timer1 register capture occurred (must be cleared in software)

0= No Timer1 register capture occurred

Compare Mode

1= A Timer1 register compare match occurred (must be cleared in software)

0= No Timer1 register compare match occurred

PWM Mode

Unused in this mode

DS41418A-page 46

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 4-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Value on

all other

Resets

Value on

POR, BOR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

PEIE

TMR0IE

INTE

RBIE

PSA

TMR0IF

PS2

INTF

PS1

RBIF

PS0

0000 000x

1111 1111

0000 0000

0000 ---0

0000 0000

0000 ---0

0000 000x

1111 1111

OPTION_REG

PIE1

RBPU

INTEDG TMR0CS TMR0SE

ADIE RCIE TXIE

TMR1GIE

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000

CCP2IE 0000 ---0

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000

CCP2IF 0000 ---0

PIE2

TMR3GIE TMR3IE TMRBIE TMRAIE

TMR1GIF ADIF RCIF TXIF

TMR3GIF TMR3IF TMRBIF TMRAIF

—

PIR1

PIR2

—

Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by interrupts.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 47

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 48

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

On power-up, the external capacitor will load the LDO

voltage regulator. To prevent erroneous operation, the

device is held in Reset while a constant current source

charges the external capacitor. After the cap is fully

charged, the device is released from Reset. For more

information on recommended capacitor values and the

constant current rate, refer to the LDO Regulator

Characteristics Table in Section 25.0 “Electrical

Specifications”.

5.0

LOW DROPOUT (LDO)

VOLTAGE REGULATOR

The PIC16F707 has an internal Low Dropout Regulator

(LDO) which provides operation above 3.6V. The LDO

regulates a voltage for the internal device logic while

permitting the VDD and I/O pins to operate at a higher

voltage. There is no user enable/disable control

available for the LDO, it is always active. The

PIC16LF707 operates at a maximum VDD of 3.6V and

does not incorporate an LDO.

A device I/O pin may be configured as the LDO voltage

output, identified as the VCAP pin. Although not

required, an external low-ESR capacitor may be

connected to the VCAP pin for additional regulator

stability.

The VCAPEN<1:0> bits of Configuration Word 2

determines which pin is assigned as the VCAP pin.

Refer to Table 5-1.

TABLE 5-1:

VCAPEN<1:0>

00

VCAPEN<1:0> SELECT BITS

RA0

RA5

01

10

11

RA6

No VCAP

TABLE 5-2:

SUMMARY OF CONFIGURATION WORD WITH LDO

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

CONFIG2

76

(1)

VCAPEN1

VCAPEN0

Legend:

— = unimplemented locations read as ‘0’. Shaded cells are not used by LDO.

Note 1: PIC16F707 only.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 49

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 50

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 6-1:

GENERIC I/O PORT

OPERATION

6.0

I/O PORTS

There are thirty-five general purpose I/O pins available.

Depending on which peripherals are enabled, some or

all of the pins may not be available as general purpose

I/O. In general, when a peripheral is enabled, the

associated pin may not be used as a general purpose

I/O pin.

TRISx

D

Q

Each port has two registers for its operation. These

registers are:

Write PORTx

Data Bus

CK

Data Register

VDD

• TRISx registers (data direction register)

• PORTx registers (port read/write register)

Ports with analog functions also have an ANSELx

register which can disable the digital input and save

power. A simplified model of a generic I/O port, without

the interfaces to other peripherals, is shown in

Figure 6-1.

I/O pin

Read PORTx

To peripherals

VSS

ANSELx

6.1

Alternate Pin Function

The Alternate Pin Function Control (APFCON) register

is used to steer specific peripheral input and output

functions between different pins. The APFCON register

is shown in Register 6-1. For this device family, the

following functions can be moved between different

pins.

• SS (Slave Select)

• CCP2

REGISTER 6-1:

APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SSSEL

CCP2SEL

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-2

bit 1

Unimplemented: Read as ‘0’.

SSSEL: SS Input Pin Selection bit

0= SS function is on RA5/AN4/CPS7/SS/VCAP

1= SS function is on RA0/AN0/SS/VCAP

bit 0

CCP2SEL: CCP2 Input/Output Pin Selection bit

0= CCP2 function is on RC1/T1OSI/CCP2

1= CCP2 function is on RB3/CCP2

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 51

PIC16F707/PIC16LF707

The TRISA register (Register 6-3) controls the PORTA

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISA register are maintained set when using them as

analog inputs. I/O pins configured as analog input

always read ‘0’.

6.2

PORTA and TRISA Registers

PORTA is

a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 6-3). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., disable the

output driver). Clearing a TRISA bit (= 0) will make the

corresponding PORTA pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). Example 6-1 shows how to

initialize PORTA.

Note:

The ANSELA register must be initialized to

configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’.

Reading the PORTA register (Register 6-2) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch.

EXAMPLE 6-1:

INITIALIZING PORTA

BANKSELPORTA

;

CLRF

BANKSELANSELA

CLRF ANSELA

BANKSELTRISA

PORTA

;Init PORTA

;

;digital I/O

;

;Set RA<3:2> as inputs

;and set RA<7:4,1:0>

;as outputs

MOVLW

MOVWF

0Ch

TRISA

REGISTER 6-2:

PORTA: PORTA REGISTER

R/W-x

RA7

R/W-x

RA6

R/W-x

RA5

R/W-x

RA4

R/W-x

RA3

R/W-x

RA2

R/W-x

RA1

R/W-x

RA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

RA<7:0>: PORTA I/O Pin bits

1= Port pin is > VIH

0= Port pin is < VIL

REGISTER 6-3:

TRISA: PORTA TRI-STATE REGISTER

R/W-1

TRISA7

bit 7

R/W-1

TRISA6

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

TRISA<7:0>: PORTA Tri-State Control bits

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

DS41418A-page 52

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

6.2.1

ANSELA REGISTER

The ANSELA register (Register 6-4) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELA bits has no affect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

REGISTER 6-4:

ANSELA: PORTA ANALOG SELECT REGISTER

R/W-1

ANSA7

bit 7

R/W-1

ANSA6

ANSA5

ANSA4

ANSA3

ANSA2

ANSA1

ANSA0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

ANSA<7:0>: Analog Select between Analog or Digital Function on pins RA<7:0>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital Input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

6.2.2

PIN DESCRIPTIONS

6.2.2.2

RA1/AN1/CPSA0

Each PORTA pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the A/D Converter (ADC), refer to the

appropriate section in this data sheet.

The RA1 pin is configurable to function as one of the

following:

• General purpose I/O

• Analog input for the A/D

• Capacitive sensing input

6.2.2.1

RA0/AN0/VCAP

6.2.2.3

RA2/AN2/CPSA1/DACOUT

The RA0 pin is configurable to function as one of the

following:

The RA2 pin is configurable to function as one of the

following:

• General purpose I/O

• Analog input for the A/D

• Capacitive sensing input

• DAC Output

• Analog input for the A/D

• Slave Select input for the SSP⁽¹⁾

• Voltage Regulator Capacitor pin (PIC16F707

only)

Note 1: SS pin location may be selected as RA5

or RA0.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 53

PIC16F707/PIC16LF707

6.2.2.4

RA3/AN3/VREF+/CPSA2

6.2.2.7

RA6/CPSB1/OSC2/CLKOUT/VCAP

The RA3 pin is configurable to function as one of the

following:

The RA6 pin is configurable to function as one of the

following:

• General purpose I/O

• Crystal/resonator connection

• Clock Output

• Analog input for the A/D

• Voltage Reference input for the A/D

• Capacitive sensing input

• Voltage Regulator Capacitor pin (PIC16F707

only)

6.2.2.5

RA4/CPSA3/T0CKI/TACKI

• Capacitive sensing input

The RA4 pin is configurable to function as one of the

following:

6.2.2.8

RA7/CPSB0/OSC1/CLKIN

The RA7 pin is configurable to function as one of the

following:

• General purpose I/O

• Capacitive sensing input

• Clock input for Timer0

• Clock input for TimerA

• General purpose I/O

• Crystal/resonator connection

• Clock Input

The Timer0 clock input function works independently

of any TRIS register setting. Effectively, if TRISA4 = 0,

the PORTA4 register bit will output to the pad and

clock Timer0 at the same time.

• Capacitive sensing input.

6.2.2.6

RA5/AN4/CPSA4/SS/VCAP

The RA5 pin is configurable to function as one of the

following:

• General purpose I/O

• Capacitive sensing input

• Analog input for the A/D

• Slave Select input for the SSP⁽¹⁾

• Voltage Regulator Capacitor pin (PIC16F707

only)

Note 1: SS pin location may be selected as RA5

or RA0.

TABLE 6-1:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

ADCON0

—

ADCS2

ANSA6

—

CHS3

ADCS1

ANSA5

—

CHS2

ADCS0

ANSA4

—

CHS1

—

CHS0

—

ADON

ADREF0

ANSA0

--00 0000

-000 --00

1111 1111

--00 0000

-000 --00

1111 1111

---- --00

00-- 0000

---- 0000

00-- 0000

---- 0000

—

GO/DONE

ADREF1

ANSA1

ADCON1

ANSELA

ANSA7

—

ANSA3

—

ANSA2

—

APFCON

SSSEL

CCP2SEL ---- --00

TAXCS 00-- 0000

CPSACH1 CPSACH0 ---- 0000

CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000

CPSACON0

CPSACON1

CPSBCON0

CPSBCON1

CONFIG2⁽¹⁾

CPSAON

—

CPSARM

—

CPSARNG1 CPSARNG0 CPSAOUT

CPSACH3 CPSACH2

—

CPSBON

—

CPSBRM

—

CPSBCH3

CPSBCH2

CPSBCH1 CPSBCH0 ---- 0000

VCAPEN1 VCAPEN0

—

PSA

—

PS2

—

PS1

—

PS0

OPTION_REG

PORTA

RBPU

INTEDG TMR0CS TMR0SE

1111 1111

xxxx xxxx

0000 0000

1111 1111

0-00 0000

000- 00--

1111 1111

xxxx xxxx

0000 0000

1111 1111

0-00 0000

000- 00--

RA7

RA6

SSPOV

TRISA6

—

RA5

RA4

CKP

RA3

RA2

RA1

RA0

SSPCON

TRISA

WCOL

TRISA7

TMRAON

DACEN

SSPEN

TRISA5

TACS

SSPM3

TRISA3

TAPSA

DACPSS1

SSPM2

TRISA2

TAPS2

DACPSS0

SSPM1

TRISA1

TAPS1

—

SSPM0

TRISA0

TAPS0

—

TRISA4

TASE

—

TACON

DACCON0

DACLPS

DACOE

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Note 1:

PIC16F707 only.

DS41418A-page 54

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

6.3.1

ANSELB REGISTER

6.3

PORTB and TRISB Registers

The ANSELB register (Register 6-9) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELB bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

PORTB is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISB

(Register 6-6). Setting a TRISB bit (= 1) will make the

corresponding PORTB pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISB bit (= 0) will make the corresponding

PORTB pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 6-2 shows how to initialize PORTB.

The state of the ANSELB bits has no affect on digital

output functions. A pin with TRIS clear and ANSELB

set will still operate as a digital output, but the Input

mode will be analog. This can cause unexpected

behavior

instructions on the affected port.

when

executing

read-modify-write

Reading the PORTB register (Register 6-5) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch.

6.3.2

WEAK PULL-UPS

Each of the PORTB pins has an individually configurable

internal weak pull-up. Control bits WPUB<7:0> enable or

disable each pull-up (see Register 6-7). Each weak pull-

up is automatically turned off when the port pin is

configured as an output. All pull-ups are disabled on a

Power-on Reset by the RBPU bit of the OPTION register.

The TRISB register (Register 6-6) controls the PORTB

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISB register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’. Example 6-2 shows how to initialize PORTB.

6.3.3

INTERRUPT-ON-CHANGE

All of the PORTB pins are individually configurable as an

interrupt-on-change pin. Control bits IOCB<7:0> enable

or disable the interrupt function for each pin. Refer to

Register 6-8. The interrupt-on-change feature is

disabled on a Power-on Reset.

EXAMPLE 6-2:

INITIALIZING PORTB

BANKSEL PORTB

;

CLRF

BANKSEL ANSELB

CLRF ANSELB

BANKSEL TRISB

PORTB

;Init PORTB

For enabled interrupt-on-change pins, the present value

is compared with the old value latched on the last read

of PORTB to determine which bits have changed or

mismatched the old value. The ‘mismatch’ outputs of

the last read are OR’d together to set the PORTB

Change Interrupt Flag bit (RBIF) in the INTCON

register.

;Make RB<7:0> digital

;

MOVLW

B’11110000’ ;Set RB<7:4> as inputs

;and RB<3:0> as outputs

;

MOVWF

TRISB

This interrupt can wake the device from Sleep. The user,

in the Interrupt Service Routine, clears the interrupt by:

Note:

The ANSELB register must be initialized to

configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’.

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear the flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading or writing PORTB will end the mismatch

condition and allow flag bit RBIF to be cleared. The latch

holding the last read value is not affected by a MCLR nor

Brown-out Reset. After these Resets, the RBIF flag will

continue to be set if a mismatch is present.

Note:

When a pin change occurs at the same

time as a read operation on PORTB, the

RBIF flag will always be set. If multiple

PORTB pins are configured for the

interrupt-on-change, the user may not be

able to identify which pin changed state.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 55

PIC16F707/PIC16LF707

REGISTER 6-5:

PORTB: PORTB REGISTER

R/W-x

RB7

R/W-x

RB6

R/W-x

RB5

R/W-x

RB4

R/W-x

RB3

R/W-x

RB2

R/W-x

RB1

R/W-x

RB0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

RB<7:0>: PORTB I/O Pin bit

1= Port pin is > VIH

0= Port pin is < VIL

REGISTER 6-6:

TRISB: PORTB TRI-STATE REGISTER

R/W-1

TRISB7

bit 7

R/W-1

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1

TRISB0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

TRISB<7:0>: PORTB Tri-State Control bit

1= PORTB pin configured as an input (tri-stated)

0= PORTB pin configured as an output

REGISTER 6-7:

WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1

WPUB7

bit 7

R/W-1

WPUB6

WPUB5

WPUB4

WPUB3

WPUB2

WPUB1

WPUB0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

WPUB<7:0>: Weak Pull-up Register bits

1= Pull-up enabled

0= Pull-up disabled

Note 1: Global RBPU bit of the OPTION register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in configured as an output.

DS41418A-page 56

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 6-8:

IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER

R/W-0

IOCB7

bit 7

R/W-0

IOCB6

R/W-0

IOCB5

R/W-0

IOCB4

R/W-0

IOCB3

R/W-0

IOCB2

R/W-0

IOCB1

R/W-0

IOCB0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

IOCB<7:0>: Interrupt-on-Change PORTB Control bits

1= Interrupt-on-change enabled

0= Interrupt-on-change disabled

REGISTER 6-9:

ANSELB: PORTB ANALOG SELECT REGISTER

R/W-1

ANSB7

bit 7

R/W-1

ANSB6

ANSB5

ANSB4

ANSB3

ANSB2

ANSB1

ANSB0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

ANSB<7:0>: Analog Select between Analog or Digital Function on Pins RB<7:0>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

6.3.4

PIN DESCRIPTIONS

6.3.4.2

RB1/AN10/CPSB9

Each PORTB pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the SSP, I²C or interrupts, refer to the appropriate

section in this data sheet.

These pins are configurable to function as one of the

following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

6.3.4.1

RB0/AN12/CPSB8/INT

6.3.4.3

RB2/AN8/CPSB10

These pins are configurable to function as one of the

following:

These pins are configurable to function as one of the

following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

• External edge triggered interrupt

• Analog input for the ADC

• Capacitive sensing input

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 57

PIC16F707/PIC16LF707

6.3.4.4

RB3/AN9/CPSB11/CCP2

6.3.4.6

RB5/AN13/CPSB13/T1G/T3CKI

These pins are configurable to function as one of the

following:

These pins are configurable to function as one of the

following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

• Timer1 gate input

• Analog input for the ADC

• Capacitive sensing input

• Capture 2 input, Compare 2 output, and PWM2

output

• Timer3 clock input

Note:

CCP2 pin location may be selected as

RB3 or RC1.

6.3.4.7

RB6/ICSPCLK/CPSB14

These pins are configurable to function as one of the

following:

6.3.4.5

RB4/AN11/CPSB12

These pins are configurable to function as one of the

following:

• General purpose I/O

• In-Circuit Serial Programming clock

• Capacitive sensing input

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

6.3.4.8

RB7/ICSPDAT/CPSB15

These pins are configurable to function as one of the

following:

• General purpose I/O

• In-Circuit Serial Programming data

• Capacitive sensing input

TABLE 6-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on all

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

other

POR, BOR

Resets

ADCON0

ANSELB

APFCON

CCP2CON

CPSBCON0

CPSBCON1

INTCON

—

ANSB7

—

ANSB6

—

CHS3

ANSB5

—

CHS2

ANSB4

—

CHS1

ANSB3

—

CHS0

ANSB2

—

GO/DONE

ANSB1

ADON

--00 0000 --00 0000

1111 1111 1111 1111

ANSB0

SSSEL

CCP2SEL ---- --00 ---- --00

CCP2M0 --00 0000 --00 0000

—

DC2B1

—

DC2B0

—

CCP2M3

CCP2M2

CCP2M1

CPSBON CPSBRM

CPSBRNG1 CPSBRNG0 CPSBOUT

TBXCS

00-- 0000 00-- 0000

—

CPSBCH3

RBIE

CPSBCH2

TMR0IF

IOCB2

CPSBCH1 CPSBCH0 ---- 0000 ---- 0000

GIE

PEIE

IOCB6

TMR0IE

IOCB5

INTE

IOCB4

INTF

RBIF

0000 000x 0000 000X

0000 0000 0000 0000

IOCB

IOCB7

IOCB3

IOCB1

IOCB0

OPTION_REG

PORTB

RBPU

RB7

INTEDG

RB6

TMR0CS

RB5

TMR0SE

RB4

PSA

RB3

—

PS2

RB2

PS1

RB1

PS0

RB0

1111 1111 1111 1111

xxxx xxxx xxxx xxxx

T3CON

TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0

T3SYNC

T1GVAL

—

TMR3ON 0000 -0-0 0000 -0-0

T1GCON

TMR1GE

T1GPOL

T1GTM

T1GSPM

T1GGO/

DONE

T1GSS1

T1GSS0

0000 0x00 uuuu uxuu

TRISB

TRISB7

WPUB7

TRISB6

WPUB6

TRISB5

WPUB5

TRISB4

WPUB4

TRISB3

WPUB3

TRISB2

WPUB2

TRISB1

WPUB1

TRISB0

WPUB0

1111 1111 1111 1111

WPUB

Legend:

x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.

DS41418A-page 58

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

EXAMPLE 6-3:

INITIALIZING PORTC

6.4

PORTC and TRISC Registers

BANKSELPORTC

;

PORTC is

a 8-bit wide, bidirectional port. The

CLRF

PORTC

;Init PORTC

;

corresponding data direction register is TRISC

(Register 6-11). Setting a TRISC bit (= 1) will make the

corresponding PORTC pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISC bit (= 0) will make the corresponding

PORTC pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 6-3 shows how to initialize PORTC.

BANKSELTRISC

MOVLW

MOVWF

B‘00001100’ ;Set RC<3:2> as inputs

TRISC

;and set RC<7:4,1:0>

;as outputs

The location of the CCP2 function is controlled by the

CCP2SEL bit in the APFCON register (see Register 6-1).

Reading the PORTC register (Register 6-10) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch.

The TRISC register (Register 6-11) controls the PORTC

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISC register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

REGISTER 6-10: PORTC: PORTC REGISTER

R/W-x

RC7

R/W-x

RC6

R/W-x

RC5

R/W-x

RC4

R/W-x

RC3

R/W-x

RC2

R/W-x

RC1

R/W-x

RC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

RC<7:0>: PORTC General Purpose I/O Pin bits

1= Port pin is > VIH

0= Port pin is < VIL

REGISTER 6-11: TRISC: PORTC TRI-STATE REGISTER

R/W-1

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

TRISC<7:0>: PORTC Tri-State Control bits

1= PORTC pin configured as an input (tri-stated)

0= PORTC pin configured as an output

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 59

PIC16F707/PIC16LF707

6.4.1

ANSELC REGISTER

The ANSELC register (Register 6-12) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELC bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELC bits has no affect on digital

output functions. A pin with TRIS clear and ANSELC

set will still operate as a digital output, but the Input

mode will be analog. This can cause unexpected

behavior when executing read-modify-write instruc-

tions on the affected port.

Note:

The ANSELC register must be initialized

to configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’.

REGISTER 6-12: ANSELC: PORTC ANALOG SELECT REGISTER

R/W-1

U-0

—

U-0

—

R/W-1

ANSC7

ANSC6

ANSC5

ANSC2

ANSC1

ANSC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

ANSC<7:5>: Analog Select between Analog or Digital Function on Pins RC<7:5>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

bit 4-3

bit 2-0

Unimplemented: Read as ‘0’

ANSC<2:0>: Analog Select between Analog or Digital Function on Pins RC<2:0>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

6.4.2

PIN DESCRIPTIONS

6.4.2.2

RC1/T1OSi/CCP2/CPSB3

Each PORTC pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the SSP, I²C or interrupts, refer to the appropriate

section in this data sheet.

These pins are configurable to function as one of the

following:

• General purpose I/O

• Timer1 oscillator input

• Capture 2 input, Compare 2 output, and PWM2

output

6.4.2.1

RC0/T1OSO/T1CKI/CPSB2

• Capacitive sensing input

These pins are configurable to function as one of the

following:

Note:

CCP2 pin location may be selected as

RB3 or RC1.

• General purpose I/O

• Timer1 oscillator output

• Timer1 clock input

• Capacitive sensing input

DS41418A-page 60

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

6.4.2.3

RC2/CCP1/CPSB4/TBCKI

6.4.2.6

RC5/SDO/CPSA9

These pins are configurable to function as one of the

following:

These pins are configurable to function as one of the

following:

• General purpose I/O

• SPI data output

• Capture 1 input, Compare 1 output, and PWM1

output

• Capacitive sensing input

• TimerB Clock input

6.4.2.7

RC6/TX/CK/CPSA10

These pins are configurable to function as one of the

following:

6.4.2.4

RC3/SCK/SCL

These pins are configurable to function as one of the

following:

• General purpose I/O

• Asynchronous serial output

• Synchronous clock I/O

• Capacitive sensing input

• General purpose I/O

• SPI clock

• I²C™ clock

6.4.2.8

RC7/RX/DT/CPSA11

6.4.2.5

RC4/SDI/SDA

These pins are configurable to function as one of the

following:

These pins are configurable to function as one of the

following:

• General purpose I/O

• SPI data input

• I²C data I/O

• Asynchronous serial input

• Synchronous serial data I/O

• Capacitive sensing input

TABLE 6-3:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on all

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

other

POR, BOR

Resets

ANSELC

ANSC7

—

ANSC6

—

ANSC5

—

ANSC2

—

ANSC1

SSSEL

ANSC0

111- -111 111- -111

APFCON

—

CCP2SEL ---- --00 ---- --00

CCP1M0 --00 0000 --00 0000

CCP2M0 --00 0000 --00 0000

CCP1CON

CCP2CON

CPSACON0

CPSACON1

CPSBCON0

CPSBCON1

PORTC

—

DC1B1

DC2B1

—

DC1B0

DC2B0

—

CCP1M3

CCP2M3

CCP1M2

CCP2M2

CCP1M1

CCP2M1

—

CPSAON

—

CPSARM

—

CPSARNG1 CPSARNG0 CPSAOUT

CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000

CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000

CPSBCH1 CPSBCH0 ---- 0000 ---- 0000

TAXCS

00-- 0000 00-- 0000

—

CPSBON

—

CPSBRM

—

CPSBCH3

RC3

CPSBCH2

RC2

RC7

RC6

RC5

SREN

SSPEN

D/A

RC4

CREN

CKP

P

RC1

OERR

SSPM1

UA

RC0

RX9D

SSPM0

BF

xxxx xxxx xxxx xxxx

0000 000x 0000 000x

0000 0000 0000 0000

RCSTA

SPEN

WCOL

SMP

RX9

ADDEN

SSPM3

S

FERR

SSPM2

R/W

SSPCON

SSPSTAT

SSPOV

CKE

—

T1CON

TBCON

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN

T1SYNC

TBPS2

TMR1ON 0000 00-0 uuuu uu-u

TMRBON

—

TBCS

TBSE

TBPSA

TBPS1

TBPS0

0-00 0000 0-00 0000

TXSTA

TRISC

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010 0000 -010

1111 1111 1111 1111

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

Legend:

x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 61

PIC16F707/PIC16LF707

EXAMPLE 6-4:

INITIALIZING PORTD

6.5

PORTD and TRISD Registers

BANKSELPORTD

;

PORTD is

a 8-bit wide, bidirectional port. The

CLRF

BANKSELANSELD

CLRF ANSELD

BANKSELTRISD

PORTD

;Init PORTD

corresponding data direction register is TRISD

(Register 6-14). Setting a TRISD bit (= 1) will make the

corresponding PORTD pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISD bit (= 0) will make the corresponding

PORTD pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 6-4 shows how to initialize PORTD.

;Make PORTD digital

;

MOVLW

MOVWF

B‘00001100’ ;Set RD<3:2> as inputs

TRISD

;and set RD<7:4,1:0>

;as outputs

6.5.1

ANSELD REGISTER

Reading the PORTD register (Register 6-13) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch.

The ANSELD register (Register 6-15) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELD bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELD bits has no affect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

The TRISD register (Register 6-14) controls the

PORTD pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits

in the TRISD register are maintained set when using

them as analog inputs. I/O pins configured as analog

input always read ‘0’.

Note:

The ANSELD register must be initialized

to configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’.

REGISTER 6-13: PORTD: PORTD REGISTER

R/W-x

RD7

R/W-x

RD6

R/W-x

RD5

R/W-x

RD4

R/W-x

RD3

R/W-x

RD2

R/W-x

RD1

R/W-x

RD0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

RD<7:0>: PORTD General Purpose I/O Pin bits

1= Port pin is > VIH

0= Port pin is < VIL

DS41418A-page 62

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 6-14: TRISD: PORTD TRI-STATE REGISTER

R/W-1

TRISD7

TRISD6

TRISD5

TRISD4

TRISD3

TRISD2

TRISD1

TRISD0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

TRISD<7:0>: PORTD Tri-State Control bits

1= PORTD pin configured as an input (tri-stated)

0= PORTD pin configured as an output

REGISTER 6-15: ANSELD: PORTD ANALOG SELECT REGISTER

R/W-1

ANSD7

ANSD6

ANSD5

ANSD4

ANSD3

ANSD2

ANSD1

ANSD0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

ANSD<7:0>: Analog Select between Analog or Digital Function on Pins RD<7:0>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

6.5.2

PIN DESCRIPTIONS

6.5.2.3

RD2/CPSB7

Each PORTD pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the SSP, I²C or interrupts, refer to the appropriate

section in this data sheet.

These pins are configurable to function as one of the

following:

• General purpose I/O

• Capacitive sensing input

6.5.2.4

RD3/CPSA8

6.5.2.1

RD0/CPSB5/T3G

These pins are configurable to function as one of the

following:

These pins are configurable to function as one of the

following:

• General purpose I/O

• Capacitive sensing input

• Timer3 Gate input

• Capacitive sensing input

6.5.2.5

RD4/CPSA12

These pins are configurable to function as one of the

following:

6.5.2.2

RD1/CPSB6

These pins are configurable to function as one of the

following:

• General purpose I/O

• Capacitive sensing input

• General purpose I/O

• Capacitive sensing input

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 63

PIC16F707/PIC16LF707

6.5.2.6

RD5/CPSA13

6.5.2.8

RD7/CPSA15

These pins are configurable to function as one of the

following:

These pins are configurable to function as one of the

following:

• General purpose I/O

• Capacitive sensing input

6.5.2.7

RD6/CPSA14

These pins are configurable to function as one of the

following:

• General purpose I/O

• Capacitive sensing input

TABLE 6-4:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

ANSELD

ANSD7

ANSD6

ANSD5

—

ANSD4

—

ANSD3

ANSD2

ANSD1

ANSD0

TAXCS

1111 1111

00-- 0000

1111 1111

00-- 0000

---- 0000

00-- 0000

---- 0000

uuuu uxuu

CPSACON0 CPSAON CPSARM

CPSACON1

CPSBCON0 CPSBON CPSBRM

CPSARNG1 CPSARNG0 CPSAOUT

CPSACH3 CPSACH2

CPSBRNG1 CPSBRNG0 CPSBOUT

—

CPSACH1 CPSACH0 ---- 0000

TBXCS 00-- 0000

CPSBCH1 CPSBCH0 ---- 0000

—

CPSBCON1

T3GCON

—

CPSBCH3

CPSBCH2

T3GVAL

TMR3GE T3GPOL T3GTM T3GSPM

T3GGO/

DONE

T3GSS1

T3GSS0

0000 0x00

PORTD

TRISD

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

xxxx xxxx

1111 1111

xxxx xxxx

1111 1111

TRISD7

TRISD6

TRISD5 TRISD4

TRISD3

TRISD2

TRISD1

TRISD0

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.

DS41418A-page 64

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

EXAMPLE 6-5:

INITIALIZING PORTE

6.6

PORTE and TRISE Registers

BANKSELPORTE

;

PORTE is

a 4-bit wide, bidirectional port. The

CLRF

BANKSELANSELE

CLRF ANSELE

BANKSELTRISE

PORTE

;Init PORTE

;

;digital I/O

;

corresponding data direction register is TRISE. Setting a

TRISE bit (= 1) will make the corresponding PORTE pin

an input (i.e., put the corresponding output driver in a

High-Impedance mode). Clearing a TRISE bit (= 0) will

make the corresponding PORTE pin an output (i.e.,

enable the output driver and put the contents of the

output latch on the selected pin). The exception is RE3,

which is input only and its TRIS bit will always read as

‘1’. Example 6-5 shows how to initialize PORTE.

MOVLW

MOVWF

B‘00001100’ ;Set RE<2> as an input

TRISE

;and set RE<1:0>

;as outputs

6.6.1

ANSELE REGISTER

The ANSELE register (Register 6-18) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELE bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

Reading the PORTE register (Register 6-16) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch. RE3 reads ‘0’ when

MCLRE = 1.

The state of the ANSELE bits has no affect on digital

output functions. A pin with TRIS clear and ANSELE

set will still operate as a digital output, but the Input

mode will be analog. This can cause unexpected

The TRISE register (Register 6-17) controls the PORTE

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISE register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

behavior

when

executing

read-modify-write

instructions on the affected port.

Note:

The ANSELE register must be initialized to

configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’.

REGISTER 6-16: PORTE: PORTE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R-x

R/W-x

RE2

R/W-x

RE1

R/W-x

RE0

RE3

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

RE<3:0>: PORTE I/O Pin bits

1= Port pin is > VIH

0= Port pin is < VIL

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 65

PIC16F707/PIC16LF707

REGISTER 6-17: TRISE: PORTE TRI-STATE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R-1

R/W-1

TRISE3

TRISE2

TRISE1

TRISE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3

Unimplemented: Read as ‘0’

TRISE3: RE3 Port Tri-state Control bit

This bit is always ‘1’ as RE3 is an input only

bit 2-0

TRISE<2:0>: RE<2:0> Tri-State Control bits⁽¹⁾

1= PORTE pin configured as an input (tri-stated)

0= PORTE pin configured as an output

REGISTER 6-18: ANSELE: PORTE ANALOG SELECT REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

ANSE2

ANSE1

ANSE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

ANSE<2:0>: Analog Select between Analog or Digital Function on Pins RE<2:0>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

6.6.2

PIN DESCRIPTIONS

6.6.2.2

RE1/AN6/CPSA6

Each PORTE pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the SSP, I²C or interrupts, refer to the appropriate

section in this data sheet.

These pins are configurable to function as one of the

following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

6.6.2.1

RE0/AN5/CPSA5

6.6.2.3

RE2/AN7/CPSA7

These pins are configurable to function as one of the

following:

These pins are configurable to function as one of the

following:

• General purpose I/O

• Analog input for the ADC

• Capacitive sensing input

• Analog input for the ADC

• Capacitive sensing input

DS41418A-page 66

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

6.6.2.4

RE3/MCLR/VPP

These pins are configurable to function as one of the

following:

• General purpose input

• Master Clear Reset with weak pull-up

• Programming voltage reference input

TABLE 6-5:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

ADCON0

ANSELE

—

CHS3

—

CHS2

—

CHS1

—

CHS0

GO/DONE

ANSE1

ADON

ANSE0

--00 0000

---- -111

00-- 0000

---- 0000

---- xxxx

---- 1111

--00 0000

---- -111

00-- 0000

---- 0000

---- xxxx

---- 1111

ANSE2

CPSACON0 CPSAON CPSARM

—

CPSARNG1 CPSARNG0 CPSAOUT

TAXCS

CPSACON1

—

CPSACH3

CPSACH2

CPSACH1

CPSACH0

PORTE

TRISE

—

RE3

RE2

RE1

RE0

TRISE3⁽¹⁾

TRISE2

TRISE1

TRISE0

Legend:

Note 1:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.

This bit is always ‘1’ as RE3 is input only.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 67

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 68

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

Clock source modes are configured by the FOSC bits

in Configuration Word 1 (CONFIG1). The oscillator

module can be configured for one of eight modes of

operation.

7.0

7.1

OSCILLATOR MODULE

Overview

The oscillator module has a wide variety of clock sources

and selection features that allow it to be used in a wide

range of applications while maximizing performance and

minimizing power consumption. Figure 7-1 illustrates a

block diagram of the oscillator module.

1. RC – External Resistor-Capacitor (RC) with

FOSC/4 output on OSC2/CLKOUT.

2. RCIO – External Resistor-Capacitor (RC) with

I/O on OSC2/CLKOUT.

3. INTOSC – Internal oscillator with FOSC/4 output

on OSC2 and I/O on OSC1/CLKIN.

Clock sources can be configured from external

oscillators, quartz crystal resonators, ceramic resonators

and Resistor-Capacitor (RC) circuits. In addition, the

system can be configured to use an internal calibrated

high-frequency oscillator as clock source, with a choice

of selectable speeds via software.

4. INTOSCIO – Internal oscillator with I/O on

OSC1/CLKIN and OSC2/CLKOUT.

5. EC – External clock with I/O on OSC2/CLKOUT.

6. HS – High Gain Crystal or Ceramic Resonator

mode.

7. XT

– Medium Gain Crystal or Ceramic

Resonator Oscillator mode.

8. LP – Low-Power Crystal mode.

FIGURE 7-1:

SIMPLIFIED PIC^®MCU CLOCK SOURCE BLOCK DIAGRAM

FOSC<2:0>

(Configuration Word 1)

External Oscillator

OSC2

OSC1

Sleep

LP, XT, HS, RC, EC

System Clock

(CPU and Peripherals)

Internal Oscillator

500 kHz

IRCF<1:0>

(OSCCON Register)

INTOSC

0

1

16 MHz/500 kHz

11

10

01

00

32x

PLL

8 MHz/250 kHz

4 MHz/125 kHz

2 MHz/62.5 kHz

PLLEN

(Configuration Word 1)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 69

PIC16F707/PIC16LF707

7.3.2

FREQUENCY SELECT BITS (IRCF)

7.2

Clock Source Modes

The output of the 500 kHz INTOSC and 16 MHz

INTOSC, with Phase Locked Loop enabled, connect to

a postscaler and multiplexer (see Figure 7-1). The

Internal Oscillator Frequency Select bits (IRCF) of the

OSCCON register select the frequency output of the

internal oscillator. Depending upon the PLLEN bit, one

of four frequencies of two frequency sets can be

selected via software:

Clock source modes can be classified as external or

internal.

• Internal clock source (INTOSC) is contained

within the oscillator module and derived from a

500 kHz high precision oscillator. The oscillator

module has eight selectable output frequencies,

with a maximum internal frequency of 16 MHz.

• External clock modes rely on external circuitry for

the clock source. Examples are: oscillator mod-

ules (EC mode), quartz crystal resonators or

ceramic resonators (LP, XT and HS modes) and

Resistor-Capacitor (RC) mode circuits.

If PLLEN = 1, frequency selection is as follows:

• 16 MHz

• 8 MHz (Default after Reset)

• 4 MHz

The system clock can be selected between external or

internal clock sources via the FOSC bits of the

Configuration Word 1.

• 2 MHz

If PLLEN = 0, frequency selection is as follows:

• 500 kHz

• 250 kHz (Default after Reset)

• 125 kHz

7.3

Internal Clock Modes

The oscillator module has eight output frequencies

derived from a 500 kHz high precision oscillator. The

IRCF bits of the OSCCON register select the

postscaler applied to the clock source dividing the

frequency by 1, 2, 4 or 8. Setting the PLLEN bit of the

Configuration Word 1 locks the internal clock source to

16 MHz before the postscaler is selected by the IRCF

bits. The PLLEN bit must be set or cleared at the time

of programming; therefore, only the upper or low four

clock source frequencies are selectable in software.

• 62.5 kHz

Note:

Following any Reset, the IRCF<1:0> bits of

the OSCCON register are set to ‘10’ and

the frequency selection is set to 8 MHz or

250 kHz. The user can modify the IRCF

bits to select a different frequency.

There is no start-up delay before a new frequency

selected in the IRCF bits takes effect. This is because

the old and new frequencies are derived from INTOSC

via the postscaler and multiplexer.

7.3.1

INTOSC AND INTOSCIO MODES

Start-up delay specifications are located in the

The INTOSC and INTOSCIO modes configure the

internal oscillators as the system clock source when

the device is programmed using the oscillator selection

or the FOSC<2:0> bits in the CONFIG1 register. See

Section 8.0 “Device Configuration” for more

information.

Table 25-4

in

Section 25.0

“Electrical

Specifications”.

In INTOSC mode, OSC1/CLKIN is available for general

purpose I/O. OSC2/CLKOUT outputs the selected

internal oscillator frequency divided by 4. The CLKOUT

signal may be used to provide a clock for external

circuitry, synchronization, calibration, test or other

application requirements.

In INTOSCIO mode, OSC1/CLKIN and OSC2/

CLKOUT are available for general purpose I/O.

DS41418A-page 70

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

7.4

Oscillator Control

The Oscillator Control (OSCCON) register (Figure 7-1)

displays the status and allows frequency selection of the

internal oscillator (INTOSC) system clock. The

OSCCON register contains the following bits:

• Frequency selection bits (IRCF)

• Status Locked bits (ICSL)

• Status Stable bits (ICSS)

REGISTER 7-1:

OSCCON: OSCILLATOR CONTROL REGISTER

U-0

—

U-0

—

R/W-1

IRCF1

R/W-0

IRCF0

R-q

U-0

—

U-0

—

ICSL

ICSS

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

q = Value depends on condition

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

IRCF<1:0>: Internal Oscillator Frequency Select bits

When PLLEN = 1 (16 MHz INTOSC)

11= 16 MHz

10= 8 MHz (POR value)

01= 4 MHz

00= 2 MHz

When PLLEN = 0 (500 kHz INTOSC)

11= 500 kHz

10= 250 kHz (POR value)

01= 125 kHz

00= 62.5 kHz

bit 3

ICSL: Internal Clock Oscillator Status Locked bit (2% Stable)

1= 16 MHz/500 kHz Internal Oscillator (HFIOSC) is in lock.

0= 16 MHz/500 kHz Internal Oscillator (HFIOSC) has not yet locked.

bit 2

ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable)

1= 16 MHz/500 kHz Internal Oscillator (HFIOSC) has stabilized to its maximum accuracy

0= 16 MHz/500 kHz Internal Oscillator (HFIOSC) has not yet reached its maximum accuracy

bit 1-0

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 71

PIC16F707/PIC16LF707

When the OSCTUNE register is modified, the INTOSC

frequency will begin shifting to the new frequency. Code

execution continues during this shift. There is no

indication that the shift has occurred.

7.5

Oscillator Tuning

The INTOSC is factory calibrated but can be adjusted

in software by writing to the OSCTUNE register

(Register 7-2).

The default value of the OSCTUNE register is ‘0’. The

value is a 6-bit two’s complement number.

REGISTER 7-2:

OSCTUNE: OSCILLATOR TUNING REGISTER

U-0

—

U-0

—

R/W-0

TUN5

R/W-0

TUN4

R/W-0

TUN3

R/W-0

TUN2

R/W-0

TUN1

R/W-0

TUN0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

TUN<5:0>: Frequency Tuning bits

01 1111= Maximum frequency

01 1110=

•

00 0001=

00 0000= Oscillator module is running at the factory-calibrated frequency.

11 1111=

•

10 0000= Minimum frequency

DS41418A-page 72

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current consumption is the medium of the three modes.

This mode is best suited to drive resonators with a

medium drive level specification.

7.6

External Clock Modes

7.6.1 OSCILLATOR START-UP TIMER

(OST)

If the oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations on the OSC1 pin before the device is

released from Reset. This occurs following a Power-on

Reset (POR) and when the Power-up Timer (PWRT)

has expired (if configured), or a wake-up from Sleep.

During this time, the program counter does not

increment and program execution is suspended. The

OST ensures that the oscillator circuit, using a quartz

crystal resonator or ceramic resonator, has started and

is providing a stable system clock to the oscillator

module.

HS Oscillator mode selects the highest gain setting of the

internal inverter-amplifier. HS mode current consumption

is the highest of the three modes. This mode is best

suited for resonators that require a high drive setting.

Figure 7-3 and Figure 7-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

FIGURE 7-3:

QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

PIC^®MCU

7.6.2

EC MODE

The External Clock (EC) mode allows an externally

generated logic level as the system clock source. When

operating in this mode, an external clock source is

connected to the OSC1 input and the OSC2 is available

for general purpose I/O. Figure 7-2 shows the pin

connections for EC mode.

OSC1/CLKIN

C1

To Internal

Logic

Quartz

Crystal

(2)

Sleep

RF

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC^®MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

OSC2/CLKOUT

(1)

C2

RS

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of RF varies with the Oscillator mode

selected.

Note 1: Quartz crystal characteristics vary according

to type, package and manufacturer. The

user should consult the manufacturer data

sheets for specifications and recommended

application.

FIGURE 7-2:

EXTERNAL CLOCK (EC)

MODE OPERATION

OSC1/CLKIN

Clock from

Ext. System

PIC^®MCU

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

(1)

I/O

OSC2/CLKOUT

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

Note 1: Alternate pin functions are described in

Section 6.1 “Alternate Pin Function”.

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and PIC^®

Devices” (DS00826)

7.6.3

LP, XT, HS MODES

• AN849, “Basic PIC^®Oscillator Design”

(DS00849)

• AN943, “Practical PIC^®Oscillator

Analysis and Design” (DS00943)

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 and OSC2 (Figure 7-3). The mode selects a low,

medium or high gain setting of the internal inverter-

amplifier to support various resonator types and speed.

• AN949, “Making Your Oscillator Work”

(DS00949)

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier. LP mode current consumption

is the least of the three modes. This mode is best suited

to drive resonators with a low drive level specification, for

example, tuning fork type crystals.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 73

PIC16F707/PIC16LF707

FIGURE 7-4:

CERAMIC RESONATOR

OPERATION

FIGURE 7-5:

EXTERNAL RC MODES

(XT OR HS MODE)

VDD

PIC^®MCU

REXT

OSC1/CLKIN

Internal

Clock

OSC1/CLKIN

CEXT

VSS

C1

To Internal

Logic

(3)

(2)

RP

RF

Sleep

(1)

FOSC/4 or

I/O

OSC2/CLKOUT

(2)

OSC2/CLKOUT

(1)

C2

RS

Ceramic

Resonator

Recommended values: 10 k  REXT  100 k, <3V

3 k  REXT  100 k, 3-5V

CEXT > 20 pF, 2-5V

Note 1: A series resistor (RS) may be required for

Note 1: Alternate pin functions are described in

Section 6.1 “Alternate Pin Function”.

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator mode

2: Output depends upon RC or RCIO clock mode.

selected.

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

In RCIO mode, the RC circuit is connected to OSC1.

OSC2 becomes an additional general purpose I/O pin.

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting

the oscillator frequency are:

7.6.4

EXTERNAL RC MODES

The external Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required. There are two modes: RC and RCIO.

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The user also needs to take into account variation due

to tolerance of external RC components used.

In RC mode, the RC circuit connects to OSC1. OSC2/

CLKOUT outputs the RC oscillator frequency divided

by 4. This signal may be used to provide a clock for

external circuitry, synchronization, calibration, test or

other application requirements. Figure 7-5 shows the

external RC mode connections.

TABLE 7-1:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

POR, BOR

(1)

Resets

(1)

CONFIG1

—

CP

—

MCLRE PWRTE

WDTE

ICSL

FOSC2

ICSS

FOSC1

—

FOSC0

—

OSCCON

IRCF1

TUN5

IRCF0

TUN4

--10 qq-- --10 qq--

--00 0000 --uu uuuu

OSCTUNE

—

TUN3

TUN2

TUN1

TUN0

Legend:

x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.

Note 1: See Configuration Word 1 (Register 8-1) for operation of all bits.

DS41418A-page 74

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

8.1

Configuration Words

8.0

DEVICE CONFIGURATION

There are several Configuration Word bits that allow

different oscillator and memory protection options.

These are implemented as Configuration Word 1

register at 2007h and Configuration Word 2 register at

2008h. These registers are only accessible during

programming.

Device Configuration consists of Configuration Word 1

and Configuration Word 2 registers, Code Protection

and Device ID.

REGISTER 8-1:

CONFIG1: CONFIGURATION WORD REGISTER 1

(4)

R/P-1

U-1

—

R/P-1

—

DEBUG

PLLEN

BORV

BOREN1

BOREN0

bit 15

bit 8

(4)

U-1

R/P-1

CP

R/P-1

—

MCLRE

PWRTE

WDTE

FOSC2

FOSC1

FOSC0

bit 7

bit 0

Legend:

P = Programmable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 13

bit 12

DEBUG: In-Circuit Debugger Mode bit

1= In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins

0= In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger

PLLEN: INTOSC PLL Enable bit

0= INTOSC Frequency is 500 kHz

1= INTOSC Frequency is 16 MHz (32x)

bit 11

bit 10

Unimplemented: Read as ‘1’

BORV: Brown-out Reset Voltage Selection bit

0= Brown-out Reset Voltage (VBOR) set to 2.5 V nominal

1= Brown-out Reset Voltage (VBOR) set to 1.9 V nominal

(1)

bit 9-8

BOREN<1:0>: Brown-out Reset Selection bits

0x= BOR disabled (Preconditioned State)

10= BOR enabled during operation and disabled in Sleep

11= BOR enabled

bit 7

bit 6

Unimplemented: Read as ‘1’

(2)

CP: Code Protection bit

1= Program memory code protection is disabled

0= Program memory code protection is enabled

(3)

bit 5

bit 4

bit 3

MCLRE: RE3/MCLR Pin Function Select bit

1= RE3/MCLR pin function is MCLR

0= RE3/MCLR pin function is digital input, MCLR internally tied to VDD

PWRTE: Power-up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire program memory will be erased when the code protection is turned off.

3: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

®

4: MPLAB IDE masks unimplemented Configuration bits to ‘0’.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 75

PIC16F707/PIC16LF707

REGISTER 8-1:

CONFIG1: CONFIGURATION WORD REGISTER 1 (CONTINUED)

bit 2-0

FOSC<2:0>: Oscillator Selection bits

111= RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN

110= RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN

101= INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN

100= INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN

011= EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN

010= HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

001= XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

000= LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire program memory will be erased when the code protection is turned off.

3: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

®

4: MPLAB IDE masks unimplemented Configuration bits to ‘0’.

REGISTER 8-2:

CONFIG2: CONFIGURATION WORD REGISTER 2

U-1⁽¹⁾

—

U-1⁽¹⁾

—

U-1⁽¹⁾

—

U-1⁽¹⁾

—

U-1⁽¹⁾

—

U-1⁽¹⁾

—

U-1⁽¹⁾

—

U-1⁽¹⁾

—

bit 15

bit 8

U-1⁽¹⁾

—

U-1⁽¹⁾

—

R/P-1

U-1⁽¹⁾

—

U-1⁽¹⁾

—

U-1⁽¹⁾

—

U-1⁽¹⁾

—

VCAPEN1

VCAPEN0

bit 7

bit 0

Legend:

P = Programmable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-6

bit 5-4

Unimplemented: Read as ‘1’

VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits

For the PIC16LF707:

These bits are ignored. All VCAP pin functions are disabled.

For the PIC16F707:

00= VCAP functionality is enabled on RA0

01= VCAP functionality is enabled on RA5

10= VCAP functionality is enabled on RA6

11= All VCAP functions are disabled (not recommended)

bit 3-0

Unimplemented: Read as ‘1’

Note 1: MPLAB^®IDE masks unimplemented Configuration bits to ‘0’.

DS41418A-page 76

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

8.2

Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out using ICSP™ for verification purposes.

Note:

The entire Flash program memory will be

erased when the code protection is turned

off. See the “PIC16F707/PIC16LF707

Memory Programming Specification”

(DS41332) for more information.

8.3

User ID

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution, but are read-

able and writable during Program/Verify mode. Only

the Least Significant 7 bits of the ID locations are

reported when using MPLAB IDE. See the

“PIC16F707/PIC16LF707

Memory

Programming

Specification” (DS41332) for more information.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 77

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 78

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

9.0

ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 8-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates

a 8-bit binary result via successive

approximation and stores the conversion result into the

ADC result register (ADRES). Figure 9-1 shows the

block diagram of the ADC.

The ADC voltage reference is software selectable to be

either internally generated or externally supplied.

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

FIGURE 9-1:

ADC BLOCK DIAGRAM

AVDD

ADREF = 0x

ADREF = 11

ADREF = 10

VREF+

0000

AN0

AN1

0001

0010

0011

0100

0101

AN2

AN3

AN4

AN5

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

AN6

AN7

ADC

AN8

8

GO/DONE

ADON

AN9

AN10

AN11

AN12

AN13

Reserved

FVREF

ADRES

VSS

CHS<3:0>

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 79

PIC16F707/PIC16LF707

9.1.3

ADC VOLTAGE REFERENCE

9.1

ADC Configuration

The ADREF bits of the ADCON1 register provides

control of the positive voltage reference. The positive

voltage reference can be either VDD, an external

voltage source or the internal Fixed Voltage Reference.

The negative voltage reference is always connected to

the ground reference. See Section 10.0 “Fixed

Voltage Reference” for more details on the Fixed

Voltage Reference.

When configuring and using the ADC the following

functions must be considered:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• Results formatting

9.1.4

CONVERSION CLOCK

The source of the conversion clock is software select-

able via the ADCS bits of the ADCON1 register. There

are seven possible clock options:

9.1.1

PORT CONFIGURATION

The ADC can be used to convert both analog and

digital signals. When converting analog signals, the I/O

pin should be configured for analog by setting the

associated TRIS and ANSEL bits. Refer to Section 6.0

“I/O Ports” for more information.

• FOSC/2

• FOSC/4

• FOSC/8

• FOSC/16

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

• FOSC/32

• FOSC/64

• FRC (dedicated internal oscillator)

9.1.2

CHANNEL SELECTION

The time to complete one bit conversion is defined as

TAD. One full 8-bit conversion requires 10 TAD periods

as shown in Figure 9-2.

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 9.2

“ADC Operation” for more information.

For correct conversion, the appropriate TAD

specification must be met. Refer to the A/D conversion

requirements

in

Section 25.0

“Electrical

Specifications” for more information. Table 9-1 gives

examples of appropriate ADC clock selections.

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

TABLE 9-1:

ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

ADC Clock Period (TAD)

Device Frequency (FOSC)

ADC

Clock Source

ADCS<2:0>

20 MHz

16 MHz

8 MHz

4 MHz

1 MHz

Fosc/2

Fosc/4

Fosc/8

Fosc/16

Fosc/32

Fosc/64

FRC

000

100

001

101

010

110

x11

100 ns⁽²⁾

200 ns⁽²⁾

400 ns⁽²⁾

800 ns

125 ns⁽²⁾

250 ns⁽²⁾

0.5 s⁽²⁾

1.0 s

250 ns⁽²⁾

500 ns⁽²⁾

1.0 s

500 ns⁽²⁾

1.0 s

2.0 s

4.0 s

8.0 s⁽³⁾

16.0 s⁽³⁾

32.0 s⁽³⁾

64.0 s⁽³⁾

2.0 s

4.0 s

1.6 s

2.0 s

4.0 s

8.0 s⁽³⁾

16.0 s⁽³⁾

3.2 s

4.0 s

1.0-6.0 s^(1,4)1.0-6.0 s^(1,4)1.0-6.0 s^(1,4)1.0-6.0 s^(1,4)1.0-6.0 s^(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the

conversion will be performed during Sleep.

DS41418A-page 80

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 9-2:

ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

Tcy to TAD

TAD0

TAD1

TAD2

b7

TAD3

b6

TAD4

TAD5

b4

TAD6

b3

TAD7

TAD8

TAD9

b5

b2

b1

b0

Conversion Starts

Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO/DONE bit

ADRES register is loaded,

GO/DONE bit is cleared,

ADIF bit is set,

Holding capacitor is connected to analog input

9.1.5

INTERRUPTS

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC interrupt flag is the ADIF bit in the

PIR1 register. The ADC Interrupt Enable is the ADIE bit

in the PIE1 register. The ADIF bit must be cleared in

software.

Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

2: The ADC operates during Sleep only

when the FRC oscillator is selected.

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEPinstruc-

tion is always executed. If the user is attempting to

wake-up from Sleep and resume in-line code execu-

tion, the GIE and PEIE bits of the INTCON register

must be disabled. If the GIE and PEIE bits of the

INTCON register are enabled, execution will switch to

the Interrupt Service Routine.

Please refer to Section 9.1.5 “Interrupts” for more

information.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 81

PIC16F707/PIC16LF707

9.2.5

SPECIAL EVENT TRIGGER

9.2

ADC Operation

The Special Event Trigger of the CCP module allows

periodic ADC measurements without software inter-

vention. When this trigger occurs, the GO/DONE bit is

set by hardware and the Timer1 counter resets to zero.

9.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 register to a ‘1’ will start the

Analog-to-Digital conversion.

Using the Special Event Trigger does not assure proper

ADC timing. It is the user’s responsibility to ensure that

the ADC timing requirements are met.

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the ADC.

Refer to Section 9.2.6 “A/D Conversion

Procedure”.

Refer to Section 17.0 “Capture/Compare/PWM

(CCP) Module” for more information.

9.2.6

A/D CONVERSION PROCEDURE

9.2.2

COMPLETION OF A CONVERSION

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

1. Configure Port:

• Set the ADIF interrupt flag bit

• Disable pin output driver (Refer to the TRIS

register)

• Update the ADRES register with new conversion

result

• Configure pin as analog (Refer to the ANSEL

register)

9.2.3

TERMINATING A CONVERSION

2. Configure the ADC module:

• Select ADC conversion clock

• Configure voltage reference

• Select ADC input channel

• Turn on ADC module

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The

ADRES register will be updated with the partially com-

plete Analog-to-Digital conversion sample. Incomplete

bits will match the last bit converted.

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt⁽¹⁾

4. Wait the required acquisition time⁽²⁾

.

9.2.4

ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC waits one additional instruction before starting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

5. Start conversion by setting the GO/DONE bit.

6. Wait for ADC conversion to complete by one of

the following:

• Polling the GO/DONE bit

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result.

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present conver-

sion to be aborted and the ADC module is turned off,

although the ADON bit remains set.

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: Refer to Section 9.3 “A/D Acquisition

Requirements”.

DS41418A-page 82

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

EXAMPLE 9-1:

A/D CONVERSION

;This code block configures the ADC

;for polling, Vdd reference, Frc clock

;and AN0 input.

;

;Conversion start & polling for completion

; are included.

;

BANKSEL

MOVLW

ADCON1

;

B’01110000’;ADC Frc clock,

;VDD reference

MOVWF

BANKSEL

BSF

BANKSEL

BSF

BANKSEL

MOVLW

MOVWF

CALL

BSF

BTFSC

GOTO

BANKSEL

MOVF

MOVWF

ADCON1

TRISA

TRISA,0

ANSELA

ANSELA,0

ADCON0

B’00000001’;AN0, On

ADCON0

SampleTime ;Acquisiton delay

ADCON0,GO ;Start conversion

ADCON0,GO ;Is conversion done?

;

;Set RA0 to input

;

;Set RA0 to analog

;

$-1

;No, test again

;

;Read result

;store in GPR space

ADRES

ADRES,W

RESULT

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 83

PIC16F707/PIC16LF707

9.2.7

ADC REGISTER DEFINITIONS

The following registers are used to control the

operation of the ADC.

REGISTER 9-1:

ADCON0: A/D CONTROL REGISTER 0

U-0

—

U-0

—

R/W-0

CHS3

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0

R/W-0

ADON

GO/DONE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-2

Unimplemented: Read as ‘0’

CHS<3:0>: Analog Channel Select bits

0000= AN0

0001= AN1

0010= AN2

0011= AN3

0100= AN4

0101= AN5

0110= AN6

0111= AN7

1000= AN8

1001= AN9

1010= AN10

1011= AN11

1100= AN12

1101= AN13

1110= Reserved

1111= Fixed Voltage Reference (FVREF)

bit 1

bit 0

GO/DONE: A/D Conversion Status bit

1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0= A/D conversion completed/not in progress

ADON: ADC Enable bit

1= ADC is enabled

0= ADC is disabled and consumes no operating current

DS41418A-page 84

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 9-2:

ADCON1: A/D CONTROL REGISTER 1

U-0

—

R/W-0

ADCS2

R/W-0

ADCS1

R/W-0

ADCS0

U-0

—

U-0

—

R/W-0

ADREF1

ADREF0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6-4

ADCS<2:0>: A/D Conversion Clock Select bits

000= FOSC/2

001= FOSC/8

010= FOSC/32

011= FRC (clock supplied from a dedicated RC oscillator)

100= FOSC/4

101= FOSC/16

110= FOSC/64

111= FRC (clock supplied from a dedicated RC oscillator)

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

ADREF<1:0>: Voltage Reference Configuration bits

0x= VREF is connected to VDD

10= VREF is connected to external VREF (RA3/AN3)

11= VREF is connected to internal Fixed Voltage Reference

REGISTER 9-3:

R/W-x

ADRES: ADC RESULT REGISTER

R/W-x

ADRES7

bit 7

ADRES6

ADRES5

ADRES4

ADRES3

ADRES2

ADRES1

ADRES0

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-0

ADRES<7:0>: ADC Result Register bits

8-bit conversion result.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 85

PIC16F707/PIC16LF707

source impedance is decreased, the acquisition time

may be decreased. After the analog input channel is

selected (or changed), an A/D acquisition must be

done before the conversion can be started. To calculate

the minimum acquisition time, Equation 9-1 may be

used. This equation assumes that 1/2 LSb error is used

(256 steps for the ADC). The 1/2 LSb error is the

maximum error allowed for the ADC to meet its

specified resolution.

9.3

A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The analog

input model is shown in Figure 9-3. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), refer

to Figure 9-3. The maximum recommended

impedance for analog sources is 10 k. As the

EQUATION 9-1:

ACQUISITION TIME EXAMPLE

Temperature = 50°C and external impedance of 10k 5.0V VDD

Assumptions:

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

= 2µs + TC + Temperature - 25°C0.05µs/°C

The value for TC can be approximated with the following equations:

1





;[1] VCHOLD charged to within 1/2 lsb

^VAPPLIED^{1 – -------------------------- = VCHOLD}



2^{n + 1} – 1

–TC

---------





RC

VAPPLIED 1 – e

= V^CHOLD







;[2] VCHOLD charge response to VAPPLIED

;combining [1] and [2]



–Tc

--------









RC

1







^{= VAPPLIED}^{1 – --------------------------}

2^{n + 1} – 1

VAPPLIED 1 – e





Note: Where n = number of bits of the ADC.

Solving for TC:

TC = –CHOLDRIC + RSS + RS ln(1/511)

= –10pF1k + 7k + 10k ln(0.001957)

= 1.12µs

Therefore:

TACQ = 2µs + 1.12µs + 50°C- 25°C0.05µs/°C

= 4.42µs

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

DS41418A-page 86

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 9-3:

ANALOG INPUT MODEL

VDD

Sampling

Switch

VT  0.6V

ANx

SS

RIC  1k

Rss

Rs

(1)

CPIN

5 pF

VA

I LEAKAGE

CHOLD = 10 pF

VSS/VREF-

VT  0.6V

6V

5V

RSS

VDD 4V

3V

Legend:

CHOLD

CPIN

= Sample/Hold Capacitance

= Input Capacitance

2V

I LEAKAGE = Leakage current at the pin due to

various junctions

5 6 7 8 9 1011

Sampling Switch

RIC

RSS

SS

VT

= Interconnect Resistance

= Resistance of Sampling Switch

= Sampling Switch

(k)

= Threshold Voltage

Note 1: Refer to Section 25.0 “Electrical Specifications”.

FIGURE 9-4:

ADC TRANSFER FUNCTION

Full-Scale Range

FFh

FEh

FDh

FCh

FBh

1 LSB ideal

Full-Scale

Transition

04h

03h

02h

01h

00h

Analog Input Voltage

1 LSB ideal

Zero-Scale

Transition

VREF

VSS

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 87

PIC16F707/PIC16LF707

TABLE 9-2:

SUMMARY OF ASSOCIATED ADC REGISTERS

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADCON0

ADCON1

ANSELA

ANSELB

ANSELE

ADRES

—

CHS3

ADCS1

ANSA5

ANSB5

—

CHS2

ADCS0

ANSA4

ANSB4

—

CHS1

—

CHS0

—

GO/DONE

ADREF1

ANSA1

ADON

ADREF0

ANSA0

ANSB0

ANSE0

--00 0000

-000 --00

1111 1111

---- -111

xxxx xxxx

--00 0000

q000 0000

0000 000x

0000 0000

1111 1111

---- 1111

--00 0000

-000 --00

1111 1111

---- -111

uuuu uuuu

--00 0000

q000 0000

0000 000x

0000 0000

1111 1111

---- 1111

ADCS2

ANSA6

ANSB6

—

ANSA7

ANSB7

—

ANSA3

ANSB3

—

ANSA2

ANSB2

ANSE2

ANSB1

ANSE1

A/D Result Register Byte

CCP2CON

—

DC2B1

—

DC2B0

—

CCP2M3

CCP2M2

CCP2M1

ADFVR1

INTF

CCP2M0

ADFVR0

RBIF

FVRCON

INTCON

PIE1

FVRRDY

GIE

FVREN

PEIE

CDAFVR1 CDAFVR0

TMR0IE

RCIE

RCIF

INTE

TXIE

TXIF

TRISA4

TRISB4

—

RBIE

TMR0IF

CCP1IE

CCP1IF

TRISA2

TRISB2

TRISE2

TMR1GIE

TMR1GIF

TRISA7

TRISB7

—

ADIE

ADIF

SSPIE

SSPIF

TMR2IE

TMR2IF

TRISA1

TRISB1

TRISE1

TMR1IE

TMR1IF

TRISA0

TRISB0

TRISE0

PIR1

TRISA

TRISB

TRISE

Legend:

TRISA6

TRISB6

—

TRISA5

TRISB5

—

TRISA3

TRISB3

TRISE3

x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends on condition. Shaded cells are not used for ADC

module.

DS41418A-page 88

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

10.1 Independent Gain Amplifiers

10.0 FIXED VOLTAGE REFERENCE

The output of the FVR supplied to the ADC and

CSM/DAC modules is routed through the two

independent programmable gain amplifiers. Each

amplifier can be configured to amplify the reference

voltage by 1x, 2x or 4x.

The Fixed Voltage Reference, or FVR, is a stable

voltage reference independent of VDD with 1.024V,

2.048V or 4.096V selectable output levels. The output

of the FVR can be configured to supply a reference

voltage to the following:

The ADFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the ADC module. Refer-

ence Section 9.0 “Analog-to-Digital Converter

(ADC) Module” for additional information on selecting

the appropriate input channel.

• ADC input channel

• ADC positive reference

• Digital-to-Analog Converter (DAC)

• Capacitive Sensing Modules (CSM)

The FVR can be enabled by setting the FVREN bit of

the FVRCON register.

The CDAFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the capacitive sensing and

digital-to-analog converter modules. Reference

Section 16.0 “Capacitive Sensing Module” and

Section 11.0 “Digital-to-Analog Converter (DAC)

Module” for additional information.

10.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it

requires time for the reference and amplifier circuits to

stabilize. Once the circuits stabilize and are ready for

use, the FVRRDY bit of the FVRCON register will be set.

See Section 25.0 “Electrical Specifications” for the

minimum delay requirement.

FIGURE 10-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

ADFVR<1:0>

2

X1

X2

X4

FVR BUFFER1

(To ADC Module)

CDAFVR<1:0>

2

X1

X2

X4

FVR BUFFER2

(To Cap Sense, DAC)

+

_

FVREN

FVRRDY

1.024V Fixed

Reference

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 89

PIC16F707/PIC16LF707

REGISTER 10-1: FVRCON: FIXED VOLTAGE REFERENCE REGISTER

R-q

FVRRDY⁽¹⁾

R/W-0/0

FVREN

R/W-0/0

—

R/W-0/0

—

R/W-0/0

CDAFVR1⁽²⁾CDAFVR0⁽²⁾ADFVR1⁽²⁾ADFVR0⁽²⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

q = Value depends on condition

bit 7

bit 6

FVRRDY: Fixed Voltage Reference Ready Flag bit⁽¹⁾

0= Fixed Voltage Reference output is not active or stable

1= Fixed Voltage Reference output is ready for use

FVREN: Fixed Voltage Reference Enable bit

0= Fixed Voltage Reference is disabled

1= Fixed Voltage Reference is enabled

bit 5-4

bit 3-2

Reserved: Read as ‘0’. Maintain these bits clear

CDAFVR<1:0>: Cap Sense and D/A Converter Fixed Voltage Reference Selection bit⁽²⁾

00= CSM and D/A Converter Fixed Voltage Reference Peripheral output is off.

01= CSM and D/A Converter Fixed Voltage Reference Peripheral output is 1x (1.024V)

10= CSM and D/A Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)

11= CSM and D/A Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)

bit 1-0

ADFVR<1:0>: A/D Converter Fixed Voltage Reference Selection bit⁽²⁾

00= A/D Converter Fixed Voltage Reference Peripheral output is off.

01= A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V)

10= A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)

11= A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)

Note 1: FVRRDY is always ‘1’ on PIC16F707 devices.

2: Fixed Voltage Reference output cannot exceed VDD.

TABLE 10-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FVRCON FVRRDY FVREN Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 q000 0000 q000 0000

Legend: Shaded cells are not used by the voltage reference module.

DS41418A-page 90

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

11.1 Output Voltage Selection

11.0 DIGITAL-TO-ANALOG

CONVERTER (DAC) MODULE

The DAC has 32 voltage level ranges. The 32 levels

are set with the DACR<4:0> bits of the DACCON1

register.

The Digital-to-Analog Converter supplies a variable

voltage reference, ratiometric with VDD, with 32

selectable output levels. The output of the DAC can be

configured to supply a reference voltage to the

following:

The DAC output voltage is determined by the following

equation:

• DACOUT device pin

• Capacitive sensing modules

The Digital-to-Analog Converter (DAC) can be enabled

by setting the DACEN bit of the DACCON0 register.

EQUATION 11-1:

IF DACEN = 1





DACR[4:0]

-

+

VOUT = VSOURCE – VSOURCE  x ----------------------------- + VSOURCE





5





2

IF DACEN = 0 & DACLPS = 1 & DACR[4:0] = 11111

+

VOUT = VSOURCE

IF DACEN = 0 & DACLPS = 0 & DACR[4:0] = 00000

-

VOUT = VSOURCE

VSOURCE+ = VDD, VREF, or FVR BUFFER 2

VSOURCE- = VSS

Due to the limited current drive capability, a buffer must

be used on the voltage reference output for external

connections to DACOUT. Example 11-1 shows an

example buffering technique.

11.2 Output Clamped to VSS

The DAC output voltage can be set to VSS with no

power consumption by setting the DACEN bit of the

DACCON0 register to ‘0’.

11.5 Operation During Sleep

11.3 Output Ratiometric to VDD

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the DACCON0 register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

The DAC is VDD derived and therefore, the DAC output

changes with fluctuations in VDD. The tested absolute

accuracy of the DAC can be found in Section 25.0

“Electrical Specifications”.

11.4 Voltage Reference Output

11.6 Effects of a Reset

The DAC can be output to the device DACOUT pin by

setting the DACOE bit of the DACCON0 register to ‘1’.

Selecting the reference voltage for output on the

DACOUT pin automatically overrides the digital output

buffer and digital input threshold detector functions of

that pin. Reading the DACOUT pin when it has been

configured for reference voltage output will always

return a ‘0’.

A device Reset affects the following:

• Voltage reference is disabled

• Fixed voltage reference is disabled

• DAC is removed from the DACOUT pin

• The DACR<4:0> range select bits are cleared

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 91

PIC16F707/PIC16LF707

FIGURE 11-1:

DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

DACEN

DACLPS

DACPSS[1:0] = 00

VDD

DACPSS[1:0] = 01

DACPSS[1:0] = 10

VREF

DACR<4:0>

FVR

R

BUFFER 2

R

(To Capacitive

Sensing Module)

DAC

32 Steps

DACOE

R

DACOUT pin

DACEN

DACLPS

EXAMPLE 11-1:

VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

PIC16F707/

PIC16LF707

DAC

Module

R

+

–

Buffered DAC Output

DACOUT

Voltage

Reference

Output

Impedance

DS41418A-page 92

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 11-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0/0

DACEN

R/W-0/0

DACLPS

R/W-0/0

DACOE

U-0

R/W-0/0

U-0

—

DACPSS1

DACPSS0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

bit 5

DACEN: Digital-to-Analog Converter Enable bit

0= Digital-to-Analog Converter is disabled

1= Digital-to-Analog Converter is enabled

DACLPS: DAC Low-Power Voltage State Select bit

0= VDAC = DAC negative reference source selected

1= VDAC = DAC positive reference source selected

DACOE: DAC Voltage Output Enable bit

0= DAC voltage level is output on the DACOUT pin

1= DAC voltage level is disconnected from the DACOUT pin

bit 4

Unimplemented: Read as ‘0’

bit 3-2

DACPSS<1:0>: DAC Positive Source Select bits

00= VDD

01= VREF

10= FVR Buffer 2 output

11= Reserved, do not use

bit 1-0

Unimplemented: Read as ‘0’

REGISTER 11-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1

U-0

R/W-0/0

DACR4

R/W-0/0

DACR3

R/W-0/0

DACR2

R/W-0/0

DACR1

R/W-0/0

DACR0

—

bit 7

bit 0

Legend:

R = Readable bit

u = bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

DACR<4:0>: DAC Voltage Output Select bits

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 93

PIC16F707/PIC16LF707

TABLE 11-1: REGISTERS ASSOCIATED WITH THE DIGITAL-TO-ANALOG CONVERTER

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FVRCON

FVRRDY

FVREN

DACLPS

—

Reserved

DACOE

—

Reserved

—

CDAFVR1

DACPSS1

DACR3

CDAFVR0

DACPSS0

DACR2

ADFVR1

—

ADFVR0

—

q000 0000 q000 0000

000- 00-- 000- 00--

---0 0000 ---0 0000

DACCON0 DACEN

DACCON1

—

DACR4

DACR1

DACR0

Legend:

— = Unimplemented locations, read as ‘0’. Shaded cells are not used by the DAC module.

DS41418A-page 94

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

12.0 TIMER0 MODULE

The Timer0 module is an 8-bit timer/counter with the

following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (shared with Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

Figure 12-1 is a block diagram of the Timer0 module.

FIGURE 12-1:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

FOSC/4

Data Bus

0

1

T0CKI

8

1

Sync

TMR0

2 TCY

0

1

TMR0SE

Set Flag bit TMR0IF

8-bit

TMR0CS

on Overflow

Prescaler

PSA

T1GSS = 11

TMR1GE

PSA

8

WDTE

PS<2:0>

1

0

WDT

Time-out

Divide by

512

PSA

Note 1: TMR0SE, TMR0CS, PSA, PS<2:0> are bits in the OPTION register.

2: WDTE bit is in Configuration Word 1.

3: T1GSS and TMR1GE are in the T1GCON register.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 95

PIC16F707/PIC16LF707

12.1.4

TIMER0 INTERRUPT

12.1 Timer0 Operation

Timer0 will generate an interrupt when the TMR0

register overflows from FFh to 00h. The TMR0IF

interrupt flag bit of the INTCON register is set every

time the TMR0 register overflows, regardless of

whether or not the Timer0 interrupt is enabled. The

TMR0IF bit can only be cleared in software. The

Timer0 interrupt enable is the TMR0IE bit of the

INTCON register.

The Timer0 module can be used as either an 8-bit timer

or an 8-bit counter.

12.1.1

8-BIT TIMER MODE

The Timer0 module will increment every instruction

cycle, if used without a prescaler. 8-bit Timer mode is

selected by clearing the TMR0CS bit of the OPTION

register.

Note:

The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

Note:

The value written to the TMR0 register can

be adjusted, in order to account for the two

instruction cycle delay when TMR0 is

written.

12.1.5

USING TIMER0 WITH AN

EXTERNAL CLOCK

When Timer0 is in Counter mode, the synchronization

of the T0CKI input and the Timer0 register is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks.

Therefore, the high and low periods of the external

clock source must meet the timing requirements as

shown in Section 25.0 “Electrical Specifications”.

12.1.2

8-BIT COUNTER MODE

In 8-bit Counter mode, the Timer0 module will increment

on every rising or falling edge of the T0CKI pin. 8-bit

Counter mode using the T0CKI pin is selected by setting

the TMR0CS bit of the OPTION register to ‘1’.

The rising or falling transition of the incrementing edge

for either input source is determined by the TMR0SE bit

in the OPTION register.

12.1.6

TIMER ENABLE

Operation of Timer0 is always enabled and the module

will operate according to the settings of the OPTION

register.

12.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

12.1.7

OPERATION DURING SLEEP

A single software programmable prescaler is available

for use with either Timer0 or the Watchdog Timer

(WDT), but not both simultaneously. The prescaler

assignment is controlled by the PSA bit of the OPTION

register. To assign the prescaler to Timer0, the PSA bit

must be cleared to a ‘0’.

Timer0 cannot operate while the processor is in Sleep

mode. The contents of the TMR0 register will remain

unchanged while the processor is in Sleep mode.

There are 8 prescaler options for the Timer0 module

ranging from 1:2 to 1:256. The prescale values are

selectable via the PS<2:0> bits of the OPTION register.

In order to have a 1:1 prescaler value for the Timer0

module, the prescaler must be assigned to the WDT

module.

The prescaler is not readable or writable. When the

prescaler is enabled or assigned to the Timer0 module,

all instructions writing to the TMR0 register will clear the

prescaler.

Note:

When the prescaler is assigned to WDT, a

CLRWDTinstruction will clear the prescaler

along with the WDT.

DS41418A-page 96

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 12-1: OPTION_REG: OPTION REGISTER

R/W-1

RBPU

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

TMR0CS

TMR0SE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RBPU: PORTB Pull-up Enable bit

1= PORTB pull-ups are disabled

0= PORTB pull-ups are enabled by individual PORT latch values

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of INT pin

0= Interrupt on falling edge of INT pin

TMR0CS: TMR0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

TMR0SE: TMR0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

BIT VALUE TMR0 RATE

WDT RATE

000

001

010

011

100

101

110

111

1 : 2

1 : 1

1 : 4

1 : 2

1 : 8

1 : 4

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

PEIE

TMR0IE

INTE

RBIE

PSA

TMR0IF

PS2

INTF

PS1

RBIF

PS0

0000 000x 0000 000x

OPTION_REG

TMR0

RBPU

INTEDG

TMR0CS

TMR0SE

1111 1111 1111 1111

xxxx xxxx uuuu uuuu

Timer0 Module Register

TRISA4 TRISA3

TRISA

TRISA7

TRISA6

TRISA5

TRISA2

TRISA1

TRISA0 1111 1111 1111 1111

Legend:

– = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 97

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 98

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

13.0 TIMER1/3 MODULES WITH

GATE CONTROL

The Timer1 and Timer3 modules are 16-bit timers/

counters with the following features:

• 16-bit timer/counter register pair (TMRxH:TMRxL)

• Programmable internal or external clock source

• 3-bit prescaler

• Dedicated LP oscillator circuit (Timer1 only)

• Synchronous or asynchronous operation

• Multiple Timer1/3 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function

(Timer1 only)

• Special Event Trigger with CCP (Timer1 only)

• Selectable Gate Source Polarity

• Gate Toggle mode

• Gate Single-pulse mode

• Gate Value Status

• Gate Event Interrupt

Figure 13-1 is a block diagram of the Timer1/3

modules.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 99

PIC16F707/PIC16LF707

FIGURE 13-1:

TIMER1/TIMER3 BLOCK DIAGRAM

TxGSS<1:0>

TxGSPM

00

TxG

0

1

01

10

11

From TimerA/B

(4)

TxG_IN

D

Data Bus

Overflow

TxGVAL

Q1

0

1

D

Q

From Timer2

Match PR2

RD

TXGCON

Single Pulse

Acq. Control

EN

Q

From WDT

Overflow

Interrupt

det

Set

TMRxGIF

TxGGO/DONE

CK

R

TxGPOL

TMRxGE

TxGTM

Set flag bit

TMRxIF on

Overflow

TMRxON

(2)

TMRx

TMRxH

EN

Synchronized

clock input

0

TxCLK

TMRxL

Q

D

1

TMRxCS<1:0>

TxSYNC

(5)

Cap. Sense

(3)

11

Synchronize

det

Prescaler

1, 2, 4, 8

Oscillator A/B

1

0

T1OSO/T1CKI

OUT

10

00

(6)

T1OSC

2

TxCKPS<1:0>

FOSC

Internal

Clock

T1OSI

EN

FOSC/2

Internal

Clock

Sleep input

FOSC/4

Internal

Clock

00

T1OSCEN

TxCKI

(1)

Note 1: ST Buffer is high speed type when using TxCKI.

2: Timer1/3 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

4: Timer1 gate source is TimerA. Timer3 gate source is TimerB. Refer to Table 13-1.

5: Timer1 clock source is CPSAOSC. Timer3 clock source is CPSBOSC. Refer to Table 13-1.

6: Timer3 does not have a T3OSC circuit. There is no T3OSCEN bit. Timer3 can operate from T1OSC.

TABLE 13-1: CPSOSC/TIMER

ASSOCIATION

Period

Measurement

Cap Sense

Oscillator

Divider Timer

(Gate Source)

Timer1

Timer3

CPS A

CPS B

TimerA

TimerB

DS41418A-page 100

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

13.1 Timer1/3 Operation

13.2 Clock Source Selection

The Timer1 and Timer3 modules are 16-bit increment-

ing counters which are accessed through the

TMRxH:TMRxL register pair. Writes to TMRxH or

TMRxL directly update the counter.

The TMRxCS<1:0> bits of the TxCON register and the

T1OSCEN bit of the T1CON register are used to select

the clock source for Timer1/3. Table 13-3 displays the

clock source selections.

When used with an internal clock source, the module is

a timer and increments on every instruction cycle.

When used with an external clock source, the module

can be used as either a timer or counter and incre-

ments on every selected edge of the external source.

13.2.1

INTERNAL CLOCK SOURCE

When the internal clock source is selected, the

TMRxH:TMRxL register pair will increment on multiples

of FOSC as determined by the Timer1/3 prescaler.

Timer1/3 is enabled by configuring the TMRxON and

TMRxGE bits in the TxCON and TxGCON registers,

respectively. Table 13-2 displays the Timer1/3 enable

selections.

13.2.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the

Timer1/3 modules may work as a timer or a counter.

When enabled to count, Timer1/3 is incremented on the

rising edge of the external clock input TxCKI or a

capacitive sensing oscillator signal. Either of these

external clock sources can be synchronized to the

microcontroller system clock or they can be run

asynchronously. If set for the capacitive sensing

oscillator signal, Timer1 will use the CPS A signal and

Timer3 will use the CPS B signal (see Table 13-1).

TABLE 13-2: TIMER1/3 ENABLE

SELECTIONS

Timer1/3

TMRxON

TMRxGE

Operation

0

1

0

1

0

1

Off

When used as a timer with a clock oscillator, an

external 32.768 kHz crystal can be used in conjunction

with the dedicated internal oscillator circuit. Only one

dedicated internal oscillator circuit is available. See

Section 13.4 “Timer1/3 Oscillator” for more

information.

Always On

Count Enabled

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after any one or

more of the following conditions:

• Timer1/3 enabled after POR reset

• Write to TMRxH or TMRxL

• Timer1/3 is disabled

• Timer1/3 is disabled (TMRxON = 0)

when TxCKI is high, then Timer1/3 is

enabled (TMRxON=1) when TxCKI is

low.

TABLE 13-3: CLOCK SOURCE SELECTIONS

TMRxCS1

TMRxCS0

T1OSCEN

Timer1 Clock Source

System Clock (FOSC)

Instruction Clock (FOSC/4)

Timer3 Clock Source

0

1

0

1

0

x

0

1

System Clock (FOSC)

Instruction Clock (FOSC/4)

Capacitive Sensing A Oscillator

External Clocking on T1CKI Pin

Capacitive Sensing B Oscillator

External Clocking on T3CKI Pin

Oscillator Circuit on T1OSI/

T1OSO Pins

Oscillator Circuit on T1OSI/

T1OSO Pins

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 101

PIC16F707/PIC16LF707

13.5.1

READING AND WRITING TIMER1/3

IN ASYNCHRONOUS COUNTER

MODE

13.3 Timer1/3 Prescaler

Timer1 and Timer3 have four prescaler options allowing

1, 2, 4 or 8 divisions of the clock input. The TxCKPS bits

of the TxCON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMRxH or TMRxL.

Reading TMRxH or TMRxL while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself poses certain problems, since the

timer may overflow between the reads.

13.4 Timer1/3 Oscillator

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMRxH:TMRxL register pair.

A dedicated low-power 32.768 kHz oscillator circuit is

built-in between pins T1OSI (input) and T1OSO

(amplifier output). This internal circuit is to be used in

conjunction with an external 32.768 kHz crystal.

The oscillator circuit is enabled by setting the

T1OSCEN bit of the T1CON register. The oscillator can

provide a clock source to Timer1 and/or Timer3. The

oscillator will continue to run during Sleep.

13.6 Timer1/3 Gate

Timer1/3 can be configured to count freely or the count

can be enabled and disabled using Timer1/3 gate

circuitry. This is also referred to as Timer1/3 gate count

enable.

Note:

The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to enabling Timer1/3.

Timer1/3 gate can also be driven by multiple selectable

sources.

13.5 Timer1/3 Operation in

Asynchronous Counter Mode

13.6.1

TIMER1/3 GATE COUNT ENABLE

The Timer1/3 gate is enabled by setting the TMRxGE bit

of the TxGCON register. The polarity of the Timer1/3

gate is configured using the TxGPOL bit of the TxGCON

register.

If control bit TxSYNC of the TxCON register is set, the

external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If external clock source is selected, then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 13.5.1 “Reading and Writing Timer1/3 in

Asynchronous Counter Mode”).

When Timer1/3 gate (TxG) input is active, Timer1/3 will

increment on the rising edge of the Timer1/3 clock

source. When Timer1/3 gate input is inactive, no incre-

menting will occur and Timer1/3 will hold the current

count. See Figure 13-3 for timing details.

TABLE 13-4: TIMER1/3 GATE ENABLE

SELECTIONS

TxCLK TxGPOL TxG

Timer1/3 Operation



0

1

0

1

0

1

Counts

Holds Count

Counts

13.6.2

TIMER1/3 GATE SOURCE

SELECTION

The Timer1/3 gate source can be selected from one of

four different sources. Source selection is controlled by

the TxGSS bits of the TxGCON register. The polarity

for each available source is also selectable. Polarity

selection is controlled by the TxGPOL bit of the

TxGCON register.

DS41418A-page 102

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 13-5: TIMER1/3 GATE SOURCES

TxGSS

Timer1 Gate Source

Timer1 Gate Pin

Timer3 Gate Source

00

01

Timer3 Gate Pin

Overflow of TimerA

Overflow of TimerB

(TMRA increments from FFh to 00h)

(TMRB increments from FFh to 00h)

10

11

Timer2 match PR2

(TMR2 increments to match PR2)

Timer2 match PR2

(TMR2 increments to match PR2)

Count Enabled by WDT Overflow

(Watchdog Time-out interval expired)

13.6.3

TxG PIN GATE OPERATION

13.6.6

WATCHDOG OVERFLOW GATE

OPERATION

The TxG pin is one source for Timer1/3 gate control.

It can be used to supply an external source to the

Timer1/3 gate circuitry. Timer1 gate can be configured

for the T1G pin and Timer3 gate can be configured for

the T3G pin.

The Watchdog Timer oscillator, prescaler and counter

will be automatically turned on when TMRxGE = 1and

TxGSS selects the WDT as a gate source for Timer1/3

(TxGSS = 11). TMRxON does not factor into the oscil-

lator, prescaler and counter enable. See Table 13-6.

Both Timer1 gate and Timer3 gate can be configured

for Watchdog overflow.

13.6.4

TIMERA/B OVERFLOW GATE

OPERATION

When TimerA/B increments from FFh to 00h a low-to-

high pulse will automatically be generated and

internally supplied to the Timer1/3 gate circuitry. Timer1

gate can be configured for TimerA overflow and Timer3

gate can be configured for TimerB overflow.

The PSA and PS bits of the OPTION register still

control what time-out interval is selected. Changing the

prescaler during operation may result in a spurious

capture.

Enabling the Watchdog Timer oscillator does not

automatically enable a Watchdog Reset or wake-up

from Sleep upon counter overflow.

13.6.5

TIMER2 MATCH GATE OPERATION

The TMR2 register will increment until it matches the

value in the PR2 register. On the very next increment

cycle, TMR2 will be reset to 00h. When this Reset

occurs, a low-to-high pulse will automatically be gener-

ated and internally supplied to the Timer1/3 gate cir-

cuitry. Both Timer1 gate and Timer3 gate can be

configured for the Timer2 match.

Note:

When using the WDT as a gate source for

Timer1/3, operations that clear the

Watchdog Timer (CLRWDT, SLEEP

instructions) will affect the time interval

being measured for capacitive sensing.

This includes waking from Sleep. All other

interrupts that might wake the device from

Sleep should be disabled to prevent them

from disturbing the measurement period.

As the gate signal coming from the WDT counter will

generate different pulse widths, depending on if the

WDT is enabled, when the CLRWDTinstruction is exe-

cuted, and so on, Toggle mode must be used. A spe-

cific sequence is required to put the device into the

correct state to capture the next WDT counter interval.

TABLE 13-6: WDT/TIMER1/3 GATE INTERRACTION

TMRxGE = 1 and

TxGSS = 11

WDT Oscillator

Enable

WDT Available for

WDTE

WDT Reset

Wake-up

TxG Source

1

0

N

Y

N

Y

N

Y

N

Y

N

Y

N

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 103

PIC16F707/PIC16LF707

Clearing the TxGSPM bit of the TxGCON register will

also clear the TxGGO/DONE bit. See Figure 13-5 for

timing details.

13.6.7

TIMER1/3 GATE TOGGLE MODE

When Timer1/3 Gate Toggle mode is enabled, it is

possible to measure the full-cycle length of a Timer1/3

gate signal, as opposed to the duration of a single level

pulse.

Enabling the Toggle mode and the Single-Pulse mode

simultaneously will permit both sections to work

together. This allows the cycle times on the Timer1/3

gate source to be measured. See Figure 13-6 for timing

details.

The Timer1/3 gate source is routed through a flip-flop

that changes state on every incrementing edge of the

signal. See Figure 13-4 for timing details.

Timer1/3 Gate Toggle mode is enabled by setting the

TxGTM bit of the TxGCON register. When the TxGTM

bit is cleared, the flip-flop is cleared and held clear. This

is necessary in order to control which edge is

measured.

13.6.9

TIMER1/3 GATE VALUE STATUS

When Timer1/3 gate value status is utilized, it is

possible to read the most current level of the gate

control value. The value is stored in the TxGVAL bit in

the TxGCON register. The TxGVAL bit is valid even

when the Timer1/3 gate is not enabled (TMRxGE bit is

cleared).

Note:

Enabling Toggle mode at the same time

as changing the gate polarity may result in

indeterminate operation.

13.6.10 TIMER1/3 GATE EVENT

INTERRUPT

When Timer1/3 gate event interrupt is enabled, it is

possible to generate an interrupt upon the completion

of a gate event. When the falling edge of TxGVAL

occurs, the TMRxGIF flag bit in the PIRx register will be

set. If the TMRxGIE bit in the PIEx register is set, then

an interrupt will be recognized. See Table 13-7 for

interrupt bit locations.

13.6.8

TIMER1/3 GATE SINGLE-PULSE

MODE

When Timer1/3 Gate Single-Pulse mode is enabled, it

is possible to capture a single pulse gate event.

Timer1/3 Gate Single-Pulse mode is first enabled by

setting the TxGSPM bit in the TxGCON register. Next,

the TxGGO/DONE bit in the TxGCON register must be

set. The Timer1/3 will be fully enabled on the next

incrementing edge. On the next trailing edge of the

pulse, the TxGGO/DONE bit will automatically be

cleared. No other gate events will be allowed to incre-

ment Timer1/3 until the TxGGO/DONE bit is once

again set in software.

The TMRxGIF flag bit operates even when the

Timer1/3 gate is not enabled (TMRxGE bit is cleared).

TABLE 13-7: TIMER1/3 INTERRUPT BIT LOCATIONS

Timer1

Timer3

Interrupt Flag

TMR1IF bit in PIR1 register

TMR1IE bit in PIE1 register

TMR3IF bit in PIR2 register

TMR3IE bit in PIE2 register

Interrupt Enable

Gate Interrupt Flag

Gate Interrupt Enable

TMR1GIF bit in PIR1 register

TMR1GIE bit in PIE1 register

TMR3GIF bit in PIR2 register

TMR3GIE bit in PIE2 register

13.7 Timer1/3 Interrupt

Note:

The TMRxH:TMRxL register pair and the

TMRxIF bit should be cleared before

enabling interrupts.

The Timer1/3 register pair (TMRxH:TMRxL)

increments to FFFFh and rolls over to 0000h. When

Timer1/3 rolls over, the Timer1/3 interrupt flag bit of the

PIRx register is set. See Table 13-7 for interrupt bit

locations.

To enable the interrupt on rollover, you must set these

bits:

• TMRxON bit of the TxCON register

• TMRxIE bit of the PIEx register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt is cleared by clearing the TMRxIF bit in

the Interrupt Service Routine.

DS41418A-page 104

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

In Capture mode, the value in the TMR1H:TMR1L

register pair is copied into the CCPR1H:CCPR1L

register pair on a configured event.

13.8 Timer1/3 Operation During Sleep

Timer1/3 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

In Compare mode, an event is triggered when the value

CCPR1H:CCPR1L register pair matches the value in

the TMR1H:TMR1L register pair. This event can be a

Special Event Trigger.

• TMRxON bit of the TxCON register must be set

• TMRxIE bit of the PIEx register must be set

• PEIE bit of the INTCON register must be set

• TxSYNC bit of the TxCON register must be set

For more information, see Section 17.0 “Capture/

Compare/PWM (CCP) Module”.

• TMRxCS bits of the TxCON register must be

configured

13.10 CCP Special Event Trigger

(Timer1 only)

• T1OSCEN bit of the T1CON register must be

configured

When the CCP is configured to trigger a special event,

the trigger will clear the TMR1H:TMR1L register pair.

This special event does not cause a Timer1 interrupt.

The CCP module may still be configured to generate a

CCP interrupt.

• TMRxGIE bit of the TxGCON register must be

configured

The device will wake-up on an overflow and execute

the next instructions. If the GIE bit of the INTCON

register is set, the device will call the Interrupt Service

Routine (0004h).

In this mode of operation, the CCPR1H:CCPR1L

register pair becomes the period register for Timer1.

Timer1 should be synchronized to the FOSC/4 to utilize

the Special Event Trigger. Asynchronous operation of

Timer1 can cause a Special Event Trigger to be

missed.

13.9 CCP Capture/Compare Time Base

(Timer1 Only)

The CCP module uses the TMR1H:TMR1L register

pair as the time base when operating in Capture or

Compare mode.

In the event that a write to TMR1H or TMR1L coincides

with a Special Event Trigger from the CCP, the write will

take precedence.

For more information, see Section 17.2.4 “Special

Event Trigger”.

FIGURE 13-2:

TIMER1/TIMER3 INCREMENTING EDGE

TxCKI = 1

when TMR1/3

Enabled

TxCKI = 0

when TMR1/3

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 105

PIC16F707/PIC16LF707

FIGURE 13-3:

TIMER1/TIMER3 GATE COUNT ENABLE MODE

TMRxGE

TxGPOL

TxG_IN

TxCKI

TxGVAL

Timer1/3

N

N + 1

N + 2

N + 3

N + 4

FIGURE 13-4:

TIMER1/TIMER3 GATE TOGGLE MODE

TMRxGE

TxGPOL

TxGTM

TxG_IN

TxCKI

TxGVAL

TIMER1/3

N

N + 1 N + 2 N + 3 N + 4

N + 5 N + 6 N + 7 N + 8

DS41418A-page 106

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 13-5:

TIMER1/TIMER3 GATE SINGLE-PULSE MODE

TMRxGE

TxGPOL

TxGSPM

Cleared by hardware on

falling edge of TxGVAL

TxGGO/

DONE

Set by software

Counting enabled on

rising edge of TxG

TxG_IN

TxCKI

TxGVAL

TIMER1/3

TMRxGIF

N

N + 1

N + 2

Cleared by

software

Set by hardware on

falling edge of TxGVAL

Cleared by software

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 107

PIC16F707/PIC16LF707

FIGURE 13-6:

TMRxGE

TxGPOL

TIMER1/TIMER3 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

TxGSPM

TxGTM

Cleared by hardware on

falling edge of TxGVAL

TxGGO/

DONE

Set by software

Counting enabled on

rising edge of TxG

TxG_IN

TxCKI

TxGVAL

TIMER1/3

TMRxGIF

N + 4

N + 2 N + 3

N

N + 1

Set by hardware on

falling edge of TxGVAL

Cleared by

software

Cleared by software

DS41418A-page 108

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

13.11 Timer1/3 Control Register

The Timer1/3 Control register (TxCON), shown in

Register 13-1, is used to control Timer1/3 and select

the various features of the Timer1/3 module.

REGISTER 13-1: TxCON: TIMER1/TIMER3 CONTROL REGISTER

R/W-0/0

TxSYNC

U-0

—

R/W-0/0

TMRxCS1

TMRxCS0

TxCKPS1

TxCKPS0 T1OSCEN⁽¹⁾

TMRxON

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-6

TMRxCS<1:0>: Timerx Clock Source Select bits

11=Timerx clock source is Capacitive Sensing Oscillator (CPSxOSC)

10=Timerx clock source is pin or oscillator:

If T1OSCEN = 0:

External clock from TxCKI pin (on the rising edge)

If T1OSCEN = 1:

Crystal oscillator on T1OSI/T1OSO pins

01=Timerx clock source is system clock (FOSC)

00=Timerx clock source is instruction clock (FOSC/4)

bit 5-4

TxCKPS<1:0>: Timerx Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3

bit 2

T1OSCEN: LP Oscillator Enable Control bit⁽¹⁾

1= Dedicated Timer1/3 oscillator circuit enabled

0= Dedicated Timer1/3 oscillator circuit disabled

TxSYNC: Timerx External Clock Input Synchronization Control bit

If TMRxCS<1:0> = 1X

1= Do not synchronize external clock input

0= Synchronize external clock input with system clock (FOSC)

If TMRxCS<1:0> = 0X

This bit is ignored. Timerx uses the internal clock when TMR1CS<1:0> = 0X.

bit 1

bit 0

Unimplemented: Read as ‘0’

TMRxON: Timerx on bit

1= Enables Timerx

0= Stops Timerx

Clears Timerx gate flip-flop

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 109

PIC16F707/PIC16LF707

REGISTER 13-2: TxGCON: TIMER1/TIMER3 GATE CONTROL REGISTER

R/W-0/0

TxGPOL

R/W-0/0

TxGTM

R/W-0/0

R-0/0

R/W-0/0

TxGSS1

R/W-0/0

TxGSS0

TMRxGE

TxGSPM

TxGGO/

DONE

TxGVAL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7

TMRxGE: Timerx Gate Enable bit

If TMRxON = 0:

This bit is ignored.

If TMRxON = 1:

1= Timerx counting is controlled by the Timerx gate function

0= Timerx counts regardless of Timerx gate function

bit 6

bit 5

TxGPOL: Timerx Gate Polarity bit

1= Timerx gate is active-high (Timerx counts when gate is high)

0= Timerx gate is active-low (Timerx counts when gate is low)

TxGTM: Timerx Gate Toggle Mode bit

1= Timerx Gate Toggle mode is enabled

0= Timerx Gate Toggle mode is disabled and toggle flip-flop is cleared

Timerx gate flip-flop toggles on every rising edge.

bit 4

bit 3

TxGSPM: Timerx Gate Single-Pulse Mode bit

1= Timerx gate Single-Pulse mode is enabled and is controlling Timerx gate

0= Timerx gate Single-Pulse mode is disabled

TxGGO/DONE: Timerx Gate Single-Pulse Acquisition Status bit

1= Timerx gate single-pulse acquisition is ready, waiting for an edge

0= Timerx gate single-pulse acquisition has completed or has not been started

This bit is automatically cleared when T1GSPM is cleared.

bit 2

TxGVAL: Timerx Gate Current State bit

Indicates the current state of the Timerx gate that could be provided to TMRxH:TMRxL.

Unaffected by Timerx Gate Enable (TMRxGE).

bit 1-0

TxGSS<1:0>: Timerx Gate Source Select bits

00= Timerx gate pin

01= TimerA/B overflow output

10= TMR2 Match PR2 output

11= Watchdog Timer scaler overflow

Watchdog Timer oscillator is turned on if TMRxGE = 1, regardless of the state of TMR1ON.

DS41418A-page 110

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

14.0 TIMERA/B MODULES

TimerA and TimerB are two more Timer0-type

modules. Timers A and B are available as general-

purpose timers/counters, and are closely integrated

with the capacitive sensing modules.

The TimerA/B modules incorporate the following

features:

• 8-bit timer/counter register (TMRx)

• 8-bit prescaler

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

• TMRA can be used to gate Timer1

• TMRB can be used to gate Timer3

Figure 14-1 is a block diagram of the TimerA/TimerB

modules.

FIGURE 14-1:

BLOCK DIAGRAM OF THE TIMERA/TIMERB PRESCALER

FOSC/4

Data Bus

TxCKI

0

1

8

0

1

Sync

TMRx

2 Tcy

From

CPSxOSC

0

Set Flag bit TMRxIF

on Overflow

TMRxCS

TMRxSE

TxXCS

8-bit

Prescaler

TMRxPSA

Overflow to Timer1/3

8

TMRxPS<2:0>

Note 1: TxXCS is in the CPSxCON0 register.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 111

PIC16F707/PIC16LF707

14.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

14.1 TimerA/B Operation

The TimerA/B modules can be used as either 8-bit tim-

ers or 8-bit counters. Additionally, the modules can also

be used to set Timer1’s/Timer3’s period of measure-

ment for the capacitive sensing modules via Timer1’s

or Timer3’s gate feature.

For TimerA/B modules, the software programmable

prescaler is exclusive to the Timer. The prescaler is

enabled by clearing the TMRxPSA bit of the TxCON

register.

There are 8 prescaler options for TimerA/B modules

ranging from 1:2 to 1:256. The prescale values are

selectable via the TMRxPS<2:0> bits of the TxCON

register for TimerA/B. In order to have a 1:1 prescaler

value for the TimerA/B modules, the prescaler must be

disabled.

TABLE 14-1: CPSOSC/TIMER

ASSOCIATION

Cap Sense

Oscillator

Divider

Timer

Period

Measurement

The prescaler is not readable or writable. When the

prescaler is enabled or assigned to the Timer module, all

instructions writing to the TMRx register will clear the

prescaler. Enabling the TimerA/B modules also clears

the prescaler.

CPS A

CPS B

TimerA

TimerB

Timer1

Timer3

14.1.1

8-BIT TIMER MODE

The TimerA/B modules will increment every instruction

cycle, if used without a prescaler. 8-bit Timer mode is

selected by clearing the TMRxCS bit of the TxCON

registers.

14.1.4

TIMERA/B INTERRUPT

TimerA/B will generate an interrupt when the

corresponding TMR register overflows from FFh to

00h. The TMRxIF interrupt flag bit of the PIR2 register

is set every time the TMRx register overflows. These

interrupt flag bits are set regardless of whether or not

the relative Timer interrupt is enabled. The interrupt

flag bits can only be cleared in software. The TimerA/B

interrupt enable bits are the TMRxIE in the PIE2

register.

When TMRx is written, the increment is inhibited for

two instruction cycles immediately following the write.

Note:

The value written to the TMRx register can

be adjusted, in order to account for the two

instruction cycle delay when TMRx is

written.

14.1.2

8-BIT COUNTER MODE

Note:

TimerA/B interrupts cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

In 8-bit Counter mode, the TimerA/B modules will

increment on every rising or falling edge of the TxCKI

pin or the Capacitive Sensing Oscillator (CPSxOSC)

signal. 8-bit Counter mode using the TxCKI pin is

selected by setting the TMRxCS bit of the TxCON

register to ‘1’ and resetting the TxXCS bit in the

CPSxCON0 register to ‘0’. 8-bit Counter mode using the

Capacitive Sensing Oscillator (CPSxOSC) signal is

selected by setting the TMRxCS bit in the TxCON

register to ‘1’ and setting the TxXCS bit in the

CPSxCON0 register to ‘1’.

14.1.5

USING TIMERA/B WITH AN

EXTERNAL CLOCK

When TimerA/B is in Counter mode, the

synchronization of the TxCKI input and the TMRx

register is accomplished by sampling the prescaler

output on the Q2 and Q4 cycles of the internal phase

clocks. Therefore, the high and low periods of the

external clock source must meet the timing

requirements as shown in Section 25.0 “Electrical

Specifications”.

The rising or falling transition of the incrementing edge

for either input source is determined by the TMRxSE bit

in the TxCON register.

14.1.6

TIMER ENABLE

Operation of TimerA/B is enabled by setting the

TMRxON bit of the TxCON register. When the module

is disabled, the value in the TMRx register is

maintained. Enabling the TMRx module will reset the

prescaler used by the counter.

14.1.7

OPERATION DURING SLEEP

TimerA and TimerB cannot operate while the processor

is in Sleep mode. The contents of the TMRx registers

will remain unchanged while the processor is in Sleep

mode.

DS41418A-page 112

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 14-1: TxCON: TIMERA/TIMERB CONTROL REGISTER

R/W-0/0

U-0

—

R/W-0/0

TMRxSE

R/W-0/0

TMRxON

TMRxCS

TMRxPSA

TMRxPS2

TMRxPS1

TMRxPS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

TMRxON: TimerA/TimerB On/Off Control bit

1= Timerx is enabled

0= Timerx is disabled

bit 6

bit 5

Unimplemented: Read as ‘0’

TMRxCS: TMRx Clock Source Select bit

1= Transition on TxCKI pin or CPSxOSC signal

0= Internal instruction cycle clock (FOSC/4)

bit 4

TMRxSE: TMRx Source Edge Select bit

1= Increment on high-to-low transition on TxCKI pin

0= Increment on low-to-high transition on TxCKI pin

bit 3

TMRxPSA: Prescaler Assignment bit

1= Prescaler is disabled. Timer clock input bypasses prescaler.

0= Prescaler is enabled. Timer clock input comes from the prescaler output.

bit 2-0

TMRxPS<2:0>: Prescaler Rate Select bits

BIT VALUE TMRx RATE

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH TIMERA/B

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CPSACON0 CPSAON

CPSBCON0 CPSBON

CPSARM

CPSBRM

TMR3IE

TMR3IF

—

CPSARNG1 CPSARNG0 CPSAOUT

CPSBRNG1 CPSBRNG0 CPSBOUT

TAXCS

TBXCS

CCP2IE

CCP2IF

TAPS0

TBPS0

00-- 0000 00-- 0000

0000 ---0 0000 ---0

0-00 0000 0-00 0000

0000 0000 0000 0000

1111 1111 1111 1111

—

PIE2

TMR3GIE

TMR3GIF

TMRAON

TMRBON

TMRBIE

TMRBIF

TACS

TBCS

TMRAIE

TMRAIF

TASE

TBSE

—

PIR2

—

TACON

TBCON

TMRA

TMRB

TRISA

TRISC

Legend:

TAPSA

TBPSA

TAPS2

TBPS2

TAPS1

TBPS1

—

TimerA Module Register

TimerB Module Register

TRISA7

TRISC7

TRISA6

TRISC6

TRISA5

TRISC5

TRISA4

TRISC4

TRISA3

TRISC3

TRISA2

TRISC2

TRISA1

TRISC1

TRISA0

TRISC0

– = Unimplemented locations, read as ‘0’. Shaded cells are not used by the TimerA/B modules.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 113

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 114

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

The TMR2 and PR2 registers are both fully readable

and writable. On any Reset, the TMR2 register is set to

00h and the PR2 register is set to FFh.

15.0 TIMER2 MODULE

The Timer2 module is an 8-bit timer with the following

features:

Timer2 is turned on by setting the TMR2ON bit in the

T2CON register to a ‘1’. Timer2 is turned off by clearing

the TMR2ON bit to a ‘0’.

• 8-bit timer register (TMR2)

• 8-bit period register (PR2)

• Interrupt on TMR2 match with PR2

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

The Timer2 prescaler is controlled by the T2CKPS bits

in the T2CON register. The Timer2 postscaler is

controlled by the TOUTPS bits in the T2CON register.

The prescaler and postscaler counters are cleared

when:

See Figure 15-1 for a block diagram of Timer2.

• A write to TMR2 occurs.

• A write to T2CON occurs.

15.1 Timer2 Operation

The clock input to the Timer2 module is the system

instruction clock (FOSC/4). The clock is fed into the

Timer2 prescaler, which has prescale options of 1:1,

1:4 or 1:16. The output of the prescaler is then used to

increment the TMR2 register.

• Any device Reset occurs (Power-on Reset, MCLR

Reset, Watchdog Timer Reset, or Brown-out

Reset).

Note:

TMR2 is not cleared when T2CON is

written.

The values of TMR2 and PR2 are constantly compared

to determine when they match. TMR2 will increment

from 00h until it matches the value in PR2. When a

match occurs, two things happen:

• TMR2 is reset to 00h on the next increment cycle.

• The Timer2 postscaler is incremented.

The match output of the Timer2/PR2 comparator is

then fed into the Timer2 postscaler. The postscaler has

postscale options of 1:1 to 1:16 inclusive. The output of

the Timer2 postscaler is used to set the TMR2IF

interrupt flag bit in the PIR1 register.

FIGURE 15-1:

TIMER2 BLOCK DIAGRAM

Sets Flag

bit TMR2IF

TMR2

Output

Prescaler

Reset

EQ

TMR2

FOSC/4

1:1, 1:4, 1:16

Postscaler

1:1 to 1:16

2

Comparator

PR2

T2CKPS<1:0>

4

TOUTPS<3:0>

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 115

PIC16F707/PIC16LF707

REGISTER 15-1: T2CON: TIMER2 CONTROL REGISTER

U-0

—

R/W-0

TOUTPS3

TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

Unimplemented: Read as ‘0’

bit 6-3

TOUTPS<3:0>: Timer2 Output Postscaler Select bits

0000= 1:1 Postscaler

0001= 1:2 Postscaler

0010= 1:3 Postscaler

0011= 1:4 Postscaler

0100= 1:5 Postscaler

0101= 1:6 Postscaler

0110= 1:7 Postscaler

0111= 1:8 Postscaler

1000= 1:9 Postscaler

1001= 1:10 Postscaler

1010= 1:11 Postscaler

1011= 1:12 Postscaler

1100= 1:13 Postscaler

1101= 1:14 Postscaler

1110= 1:15 Postscaler

1111= 1:16 Postscaler

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0

T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

PEIE

ADIE

ADIF

TMR0IE

RCIE

INTE

TXIE

TXIF

RBIE

SSPIE

SSPIF

TMR0IF

CCP1IE

CCP1IF

INTF

RBIF

0000 000x

0000 0000

0000 000x

0000 0000

TMR1GIE

TMR1GIF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

0000 0000

1111 1111

0000 0000

-000 0000

0000 0000

1111 1111

0000 0000

-000 0000

RCIF

PR2

Timer2 Module Period Register

Holding Register for the 8-bit TMR2 Register

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON

TMR2

T2CON

Legend:

—

T2CKPS1

T2CKPS0

x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.

DS41418A-page 116

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

• Software control

16.0 CAPACITIVE SENSING

MODULE

• Operation during sleep

• Acquire two samples simultaneously (when using

both CSM modules)

The capacitive sensing modules (CSM) allow for an

interaction with an end user without a mechanical

interface. In a typical application, the capacitive

sensing module is attached to a pad on a Printed

Circuit Board (PCB), which is electrically isolated from

the end user. When the end user places their finger

over the PCB pad, a capacitive load is added, causing

a frequency shift in the capacitive sensing module. The

capacitive sensing module requires software and at

least one timer resource to determine the change in

frequency. Key features of this module include:

Two identical capacitive sensing modules are

implemented on the PIC16F707/PIC16LF707. The

modules are named CPSA and CPSB. The timer

module integration for both capacitive sensing modules

is shown in Table 16-1. A block diagram of the

capacitive sensing module is shown in Figure 16-1 and

Figure 16-2.

• Analog MUX for monitoring multiple inputs

• Capacitive sensing oscillator

• Multiple Power modes

• High power range with variable voltage

references

• Multiple timer resources

TABLE 16-1: CPSOSC TIMER USAGE

Cap Sense Oscillator

Mode

Frequency Measurement

Duration Control

TimerA/Software

Timer1/Software

Timer1/TimerA

TimerB/Software

Timer3/Software

Timer3/TimerB

TimerA

Timer1

TimerB

Timer3

Software

TimerA

Cap Sense Oscillator A

Software

TimerB

Cap Sense Oscillator B

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 117

PIC16F707/PIC16LF707

FIGURE 16-1:

CAPACITIVE SENSING BLOCK DIAGRAM

TimerA/B Module

TMRxCS

Set

TMRxIF

CPSxCH<3:0>

TxXCS

CPSxON⁽¹⁾

FOSC/4

0

1

Overflow

CPSx0

CPSx1

CPSx2

CPSx3

CPSx4

CPSx5

CPSx6

CPSx7

CPSx8

CPSx9

CPSx10

CPSx11

CPSx12

CPSx13

CPSx14

CPSx15

TxCKI

0

1

TMRx

CPSxRNG<1:0>

CPSxON

Capacitive

Sensing

Oscillator

Timer1/3 Module

TMRxCS<1:0>

CPSxOSC

FOSC

FOSC/4

CPSxCLK

CPSxOUT

0

1

Int.

Ref.

TMRxH:TMRxL

EN

Ref-

T1OSC/

TxCKI

DAC

0

TxGSS<1:0>

TxG

Ref+

1

FVR

Timer1/3 Gate

Control Logic

CPSxRM

Watchdog Timer Module

Timer2 Module

Postscaler

WDT

Event

Overflow

Set

TMR2IF

TMR2

LP WDT

OSC

Overflow

WDT

Scaler

PS<2:0>

Note 1: If CPSxON = 0, disabling capacitive sensing, no channel is selected.

DS41418A-page 118

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 16-2:

CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM

Oscillator Module

VDD

(1)

(2)

+

-

S

R

Q

CPSxCLK

CPSx

(1)

Analog Pin

-

+

Internal

References

0

1

0

Ref-

Ref+

(3)

FVR

1

DAC

CPSxRM

Note 1: Module Enable and Power mode selections are not shown.

2: Comparators remain active in Noise Detection mode.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 119

PIC16F707/PIC16LF707

16.1 Analog MUX

16.3 Voltage References

Each capacitive sensing module can monitor up to 16

inputs, providing 32 capacitive sensing inputs in total.

The capacitive sensing inputs are defined as

CPSA<15:0> for capacitive sensing module A, and

CPSB<15:0> for capacitive sensing module B. To

determine if a frequency change has occurred the use

must:

The capacitive sensing oscillator uses voltage

references to provide two voltage thresholds for

oscillation. The upper voltage threshold is referred to

as Ref+ and the lower voltage threshold is referred to

as Ref-.

The user can elect to use fixed voltage references,

which are internal to the capacitive sensing oscillator,

or variable voltage references, which are supplied by

the Fixed Voltage Reference (FVR) module and the

Digital-to-Analog Converter (DAC) module.

• Select the appropriate CPS pin by setting the

CPSxCH<3:0> bits of the CPSxCON1 register.

• Set the corresponding ANSEL bit.

• Set the corresponding TRIS bit.

• Run the software algorithm.

When the fixed voltage references are used, the VSS

voltage determines the lower threshold level (Ref-) and

the VDD voltage determines the upper threshold level

(Ref+).

Selection of the CPSx pin while the module is enabled

will cause the capacitive sensing oscillator to be on the

CPSx pin. Failure to set the corresponding ANSEL and

TRIS bits can cause the capacitive sensing oscillator to

stop, leading to false frequency readings.

When the variable voltage references are used, the

DAC voltage determines the lower threshold level

(Ref-) and the FVR voltage determines the upper

threshold level (Ref+). An advantage of using these ref-

erence sources is that oscillation frequency remains

constant with changes in VDD.

16.2 Capacitive Sensing Oscillator

The capacitive sensing oscillator consists of a constant

current source and a constant current sink, to produce

Different oscillation frequencies can be obtained

through the use of these variable voltage references.

The more the upper voltage reference level is lowered

and the more the lower voltage reference level is

raised, the higher the capacitive sensing oscillator

frequency becomes.

a

triangle waveform. The CPSxOUT bit of the

CPSxCON0 register shows the status of the capacitive

sensing oscillator, whether it is sinking or sourcing

current. The oscillator is designed to drive a capacitive

load (single PCB pad) and at the same time, be a clock

source to either TimerA/B or Timer1/3. The oscillator

has three different current settings as defined by

CPSxRNG<1:0> of the CPSxCON0 register. The

different current settings for the oscillator serve two

purposes:

Selection between the voltage references is controlled

by the CPSxRM bit of the CPSxCON0 register. Setting

this bit selects the variable voltage references and

clearing this bit selects the fixed voltage references.

Please see Section 10.0 “Fixed Voltage Reference”

and Section 11.0 “Digital-to-Analog Converter

(DAC) Module” for more information on configuring

the variable voltage levels.

• Maximize the number of counts in a timer for a

fixed time base.

• Maximize the count differential in the timer during

a change in frequency.

DS41418A-page 120

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

The remaining mode is a Noise Detection mode that

resides within the high range. The Noise Detection

mode is unique in that it disables the sinking and sourc-

ing of current on the analog pin but leaves the rest of

the oscillator circuitry active. This reduces the oscilla-

tion frequency on the analog pin to zero and also

greatly reduces the current consumed by the oscillator

module.

16.4 Power Modes

The capacitive sensing oscillator can operate in one of

seven different power modes. The power modes are

separated into two ranges; the low range and the high

range.

When the oscillator's low range is selected, the fixed

internal voltage references of the capacitive sensing

oscillator are being used. When the oscillator's high

range is selected, the variable voltage references

supplied by the FVR and DAC modules are being used.

Selection between the voltage references is controlled

by the CPSxRM bit of the CPSxCON0 register. See

Section 16.3 “Voltage References” for more

information.

When noise is introduced onto the pin, the oscillator is

driven at the frequency determined by the noise. This

produces a detectable signal at the comparator output,

indicating the presence of activity on the pin.

Figure 16-2 shows a more detailed drawing of the

current sources and comparators associated with the

oscillator.

Within each range there are three distinct power

modes; Low, Medium and High. Current consumption

is dependent upon the range and mode selected.

Selecting power modes within each range is accom-

plished by configuring the CPSxRNG <1:0> bits in the

CPSxCON0 register. See Table 16-2 for proper power

mode selection.

TABLE 16-2: POWER MODE SELECTION

CPSxRM

Range

CPSxRNG<1:0>

Mode

Nominal Current ⁽¹⁾

00

01

10

11

00

01

10

11

Off

Low

0.0 µA

0.1 µA

1.2 µA

18 µA

0.0 µA

9 µA

0

Low

Medium

High

Noise Detection

Low

1

High

Medium

High

30 µA

100 µA

Note:

See Section 25.0 “Electrical Specifications” for more information.

16.5

Timer Resources

16.6 Fixed Time Base

To measure the change in frequency of the capacitive

sensing oscillator, a fixed time base is required. For the

period of the fixed time base, the capacitive sensing

oscillator is used to clock either TimerA/B or Timer1/3

(for CPSA/B, respectively). The frequency of the

capacitive sensing oscillator is equal to the number of

counts in the timer divided by the period of the fixed

time base.

To measure the frequency of the capacitive sensing

oscillator, a fixed time base is required. Any timer

resource or software loop can be used to establish the

fixed time base. It is up to the end user to determine the

method in which the fixed time base is generated.

Note:

The fixed time base can not be generated

by the timer resource that the capacitive

sensing oscillator is clocking.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 121

PIC16F707/PIC16LF707

16.6.1

TIMERA/B

16.7 Software Control

To select TimerA/B as the timer resource for the

capacitive sensing module:

The software portion of the capacitive sensing module

is required to determine the change in frequency of the

capacitive sensing oscillator. This is accomplished by

the following:

• Set the TAXCS/TBXCS bit of the CPSACON0/

CPSBCON0 register.

• Clear the TMRACS/TMRBCS bit of the TACON/

TBCON register.

• Setting a fixed time base to acquire counts on

TimerA/B or Timer1/3.

• Establishing the nominal frequency for the

capacitive sensing oscillator.

When TimerA/B is chosen as the timer resource, the

capacitive sensing oscillator will be the clock source for

TimerA/B. Refer to Section 14.0 “TimerA/B Mod-

ules” for additional information.

• Establishing the reduced frequency for the

capacitive sensing oscillator due to an additional

capacitive load.

16.6.2

TIMER1/3

• Set the frequency threshold.

To select Timer1/3 as the timer resource for the

capacitive sensing module, set the TMRxCS<1:0> of

the TxCON register to ‘11’. When Timer1/3 is chosen

as the timer resource, the capacitive sensing oscilla-

tor will be the clock source for Timer1/3. Because the

Timer1/3 module has a gate control, developing a

time base for the frequency measurement can be

simplified by using the TimerA/B overflow flag.

16.7.1

NOMINAL FREQUENCY (NO

CAPACITIVE LOAD)

To determine the nominal frequency of the capacitive

sensing oscillator:

• Remove any extra capacitive load on the selected

CPSx pin.

• At the start of the fixed time base, clear the timer

resource.

It is recommend that the TimerA/B overflow flag, in

conjunction with the Toggle mode of the Timer1/3 gate,

be used to develop the fixed time base required by the

software portion of the capacitive sensing module.

Refer to Section 13.11 “Timer1/3 Control Register ”

for additional information.

• At the end of the fixed time base, save the value

in the timer resource.

The value of the timer resource is the number of

oscillations of the capacitive sensing oscillator for the

given time base. The frequency of the capacitive

sensing oscillator is equal to the number of counts on

the timer divided by the period of the fixed time base.

TABLE 16-3: TIMER1/3 ENABLE FUNCTION

TMRxON

TMRxGE

Timerx Operation

16.7.2

REDUCED FREQUENCY

(ADDITIONAL CAPACITIVE LOAD)

0

1

0

1

0

1

Off

On

The extra capacitive load will cause the frequency of

the capacitive sensing oscillator to decrease. To

determine the reduced frequency of the capacitive

sensing oscillator:

Count Enabled by Input

• Add a typical capacitive load on the selected

CPSx pin.

• Use the same fixed time base as the nominal

frequency measurement.

• At the start of the fixed time base, clear the timer

resource.

• At the end of the fixed time base, save the value

in the timer resource.

The value of the timer resource is the number of

oscillations of the capacitive sensing oscillator with an

additional capacitive load. The frequency of the

capacitive sensing oscillator is equal to the number of

counts on the timer divided by the period of the fixed

time base. This frequency should be less than the

value obtained during the nominal frequency

measurement.

DS41418A-page 122

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

16.7.3

FREQUENCY THRESHOLD

16.8 Operation during Sleep

The frequency threshold should be placed midway

between the value of nominal frequency and the

reduced frequency of the capacitive sensing oscillator.

Refer to Application Note AN1103, “Software Handling

for Capacitive Sensing” (DS01103) for more detailed

information on the software required for capacitive

sensing module.

The capacitive sensing oscillator will continue to run as

long as the module is enabled, independent of the part

being in Sleep. In order for the software to determine if

a frequency change has occurred, the part must be

awake. However, the part does not have to be awake

when the timer resource is acquiring counts.

Note:

TimerA/B does not operate when in Sleep,

and therefore cannot be used for

capacitive sense measurements in Sleep.

Note:

For more information on general

capacitive sensing refer to Application

Notes:

•

AN1101, “Introduction to Capacitive

Sensing” (DS01101)

• AN1102, “Layout and Physical

Design Guidelines for Capacitive

Sensing” (DS01102).

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 123

PIC16F707/PIC16LF707

REGISTER 16-1: CPSxCON0: CAPACITIVE SENSING CONTROL REGISTER 0

R/W-0/0

U-0

—

U-0

—

R/W-0/0

R-0/0

R/W-0/0

TxXCS

CPSxON

CPSxRM

CPSxRNG1 CPSxRNG0

CPSxOUT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

CPSxON: Capacitive Sensing Module Enable bit

1= Capacitive sensing module is enabled

0= Capacitive sensing module is disabled

CPSxRM: Capacitive Sensing Reference Mode bit

1= Capacitive sensing module is in high range. DAC and FVR provide oscillator voltage references.

0= Capacitive sensing module is in low range. Internal oscillator voltage references are used.

bit 5-4

bit 3-2

Unimplemented: Read as ‘0’

CPSxRNG<1:0>: Capacitive Sensing Current Range bits

If CPSxRM = 0(low range):

11= Oscillator is in high range: Charge/discharge current is nominally 18 µA.

10= Oscillator is in medium range. Charge/discharge current is nominally 1.2 µA.

01= Oscillator is in low range. Charge/discharge current is nominally 0.1 µA.

00= Oscillator is off.

If CPSxRM = 1(high range):

11= Oscillator is in high range: Charge/discharge current is nominally 100 µA.

10= Oscillator is in medium range. Charge/discharge current is nominally 30 µA.

01= Oscillator is in low range. Charge/discharge current is nominally 9 µA.

00=Oscillator is on; Noise Detection mode; No charge/discharge current is supplied.

bit 1

bit 0

CPSxOUT: Capacitive Sensing Oscillator Status bit

1= Oscillator is sourcing current (Current flowing out of the pin)

0= Oscillator is sinking current (Current flowing into the pin)

TxXCS: TimerA/B External Clock Source Select bit

If TMRxCS = 1:

The TxXCS bit controls which clock external to the core/TimerA/B module supplies TimerA/B:

1= TimerA/B clock source is the capacitive sensing oscillator

0= TimerA/B clock source is the TxCKI pin

If TMRxCS = 0:

TimerA/B clock source is controlled by the core/TimerA/B module and is FOSC/4.

DS41418A-page 124

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 16-2: CPSxCON1: CAPACITIVE SENSING CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

CPSxCH3

CPSxCH2

CPSxCH1

CPSxCH0

bit 7

bit 0

Legend:

R = Readable bit

u = bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

CPSxCH<3:0>: Capacitive Sensing Channel Select bits

If CPSxON = 0:

These bits are ignored. No channel is selected.

If CPSxON = 1:

0000= channel 0, (CPSx0)

0001= channel 1, (CPSx1)

0010= channel 2, (CPSx2)

0011= channel 3, (CPSx3)

0100= channel 4, (CPSx4)

0101= channel 5, (CPSx5)

0110= channel 6, (CPSx6)

0111= channel 7, (CPSx7)

1000= channel 8, (CPSx8)

1001= channel 9, (CPSx9)

1010= channel 10, (CPSx10)

1011= channel 11, (CPSx11)

1100= channel 12, (CPSx12)

1101= channel 13, (CPSx13)

1110= channel 14, (CPSx14)

1111= channel 15, (CPSx15)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 125

PIC16F707/PIC16LF707

TABLE 16-4: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

ANSELB

ANSELC

ANSELD

ANSELE

CPSACON0

CPSACON1

CPSBCON0

CPSBCON1

TACON

ANSA7

ANSB7

ANSC7

ANSD7

—

ANSA6

ANSB6

ANSC6

ANSD6

—

ANSA5

ANSB5

ANSC5

ANSD5

—

ANSA4

ANSB4

—

ANSA3

ANSB3

—

ANSA2

ANSB2

ANSC2

ANSD2

ANSE2

ANSA1

ANSB1

ANSC1

ANSD1

ANSE1

ANSA0

ANSB0

ANSC0

ANSD0

ANSE0

TAXCS

1111 1111 1111 1111

111- -111 111- -111

1111 1111 1111 1111

---- -111 ---- -111

00-- 0000 00-- 0000

ANSD4

—

ANSD3

—

CPSAON

—

CPSARM

—

CPSARNG1 CPSARNG0 CPSAOUT

CPSACH3 CPSACH2

CPSBRNG1 CPSBRNG0 CPSBOUT

—

CPSACH1 CPSACH0 ---- 0000 ---- 0000

TBXCS 00-- 0000 00-- 0000

CPSBCH1 CPSBCH0 ---- 0000 ---- 0000

CPSBON

—

CPSBRM

—

CPSBCH3

TAPSA

CPSBCH2

TAPS2

TMRAON

TMRBON

—

TACS

TBCS

TASE

TBSE

TAPS1

TBPS1

—

TAPS0

TBPS0

0-00 0000 0-00 0000

TBCON

—

TBPSA

TBPS2

T1CON

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN

T1SYNC

T3SYNC

TRISA2

TRISB2

TRISC2

TRISD2

TRISE2

TMR1ON 0000 00-0 0000 00-0

TMR3ON 0000 -0-0 0000 -0-0

T3CON

TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0

—

TRISA

TRISA7

TRISB7

TRISC7

TRISD7

—

TRISA6

TRISB6

TRISC6

TRISD6

—

TRISA5

TRISB5

TRISC5

TRISD5

—

TRISA4

TRISB4

TRISC4

TRISD4

—

TRISA3

TRISB3

TRISC3

TRISD3

TRISE3

TRISA1

TRISB1

TRISC1

TRISD1

TRISE1

TRISA0

TRISB0

TRISC0

TRISD0

TRISE0

1111 1111 1111 1111

---- 1111 ---- 1111

TRISB

TRISC

TRISD

TRISE

Legend:

— = Unimplemented locations, read as ‘0’. Shaded cells are not used by the capacitive sensing modules.

DS41418A-page 126

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

17.0 CAPTURE/COMPARE/PWM

(CCP) MODULE

TABLE 17-1: CCP MODE – TIMER

RESOURCES REQUIRED

The Capture/Compare/PWM module is a peripheral

which allows the user to time and control different

events. In Capture mode, the peripheral allows the

timing of the duration of an event. The Compare mode

allows the user to trigger an external event when a

predetermined amount of time has expired. The PWM

mode can generate a pulse-width modulated signal of

varying frequency and duty cycle.

CCP Mode

Capture

Timer Resource

Timer1

Timer2

Compare

PWM

Note:

Timer3 has no connection to either CCP.

The timer resources used by the module are shown in

Table 17-2.

Additional information on CCP modules is available in

Application Note AN594, “Using the CCP Modules”

(DS00594).

TABLE 17-2: INTERACTION OF TWO CCP MODULES

CCP1 Mode CCP2 Mode

Capture Capture

Interaction

Same TMR1 time base

Capture

Compare

PWM

Compare

PWM

Same TMR1 time base^{(1, 2)}

The PWMs will have the same frequency and update rate (TMR2 interrupt).

The rising edges will be aligned.

PWM

Capture

None

Compare

Note 1: If CCP2 is configured as a Special Event Trigger, CCP1 will clear Timer1, affecting the value captured on

the CCP2 pin.

2: If CCP1 is in Capture mode and CCP2 is configured as a Special Event Trigger, CCP2 will clear Timer1,

affecting the value captured on the CCP1 pin.

Note:

CCPRx and CCPx throughout this

document refer to CCPR1 or CCPR2 and

CCP1 or CCP2, respectively.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 127

PIC16F707/PIC16LF707

REGISTER 17-1: CCPxCON: CCPx CONTROL REGISTER

U-0

—

U-0

—

R/W-0

DCxB1

DCxB0

CCPxM3

CCPxM2

CCPxM1

CCPxM0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

DCxB<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0

CCPxM<3:0>: CCP Mode Select bits

0000= Capture/Compare/PWM off (resets CCP module)

0001= Unused (reserved)

0010= Compare mode, toggle output on match (CCPxIF bit of the PIRx register is set)

0011= Unused (reserved)

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode, set output on match (CCPxIF bit of the PIRx register is set)

1001= Compare mode, clear output on match (CCPxIF bit of the PIRx register is set)

1010= Compare mode, generate software interrupt on match (CCPxIF bit is set of the PIRx register,

CCPx pin is unaffected)

1011= Compare mode, trigger special event (CCPxIF bit of the PIRx register is set, TMR1 is reset

and A/D conversion⁽¹⁾is started if the ADC module is enabled. CCPx pin is unaffected.)

11xx= PWM mode.

Note 1: A/D conversion start feature is available only on CCP2.

DS41418A-page 128

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

17.1.3

SOFTWARE INTERRUPT

17.1 Capture Mode

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCPxIE interrupt enable bit of the PIEx register clear to

avoid false interrupts. Additionally, the user should

clear the CCPxIF interrupt flag bit of the PIRx register

following any change in operating mode.

In Capture mode, CCPRxH:CCPRxL captures the

16-bit value of the TMR1 register when an event occurs

on pin CCPx. An event is defined as one of the

following and is configured by the CCPxM<3:0> bits of

the CCPxCON register:

• Every falling edge

• Every rising edge

Note:

Clocking Timer1 from the system clock

(FOSC) should not be used in Capture

mode. In order for Capture mode to

recognize the trigger event on the CCPx

pin, Timer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

• Every 4th rising edge

• Every 16th rising edge

When a capture is made, the interrupt request flag bit

CCPxIF of the PIRx register is set. The interrupt flag

must be cleared in software. If another capture occurs

before the value in the CCPRxH, CCPRxL register pair

is read, the old captured value is overwritten by the new

captured value (refer to Figure 17-1).

17.1.4

CCP PRESCALER

There are four prescaler settings specified by the

CCPxM<3:0> bits of the CCPxCON register. Whenever

the CCP module is turned off, or the CCP module is not

in Capture mode, the prescaler counter is cleared. Any

Reset will clear the prescaler counter.

17.1.1

CCPx PIN CONFIGURATION

In Capture mode, the CCPx pin should be configured

as an input by setting the associated TRIS control bit.

Either RC1 or RB3 can be selected as the CCP2 pin.

Refer to Section 6.1 “Alternate Pin Function” for

more information.

Switching from one capture prescaler to another does not

clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by

clearing the CCPxCON register before changing the

prescaler (refer to Example 17-1).

Note:

If the CCPx pin is configured as an output,

a write to the port can cause a capture

condition.

EXAMPLE 17-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

FIGURE 17-1:

CAPTURE MODE

OPERATION BLOCK

DIAGRAM

BANKSELCCP1CON

;Set Bank bits to point

;to CCP1CON

;Turn CCP module off

CLRF

CCP1CON

Set Flag bit CCPxIF

(PIRx register)

MOVLW

NEW_CAPT_PS;Load the W reg with

; the new prescaler

Prescaler

 1, 4, 16

; move value and CCP ON

MOVWF

CCP1CON

;Load CCP1CON with this

; value

CCPx

CCPRxH

CCPRxL

Capture

Enable

and

Edge Detect

17.1.5

CAPTURE DURING SLEEP

TMR1H

TMR1L

Capture mode depends upon the Timer1 module for

proper operation. There are two options for driving the

Timer1 module in Capture mode. It can be driven by

the instruction clock (FOSC/4), or by an external clock

source.

CCPxCON<3:0>

System Clock (FOSC)

17.1.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchronized

Counter mode for the CCP module to use the capture

feature. In Asynchronous Counter mode or when

Timer1 is clocked at FOSC, the capture operation may

not work.

If Timer1 is clocked by FOSC/4, then Timer1 will not

increment during Sleep. When the device wakes from

Sleep, Timer1 will continue from its previous state.

If Timer1 is clocked by an external clock source, then

Capture mode will operate as defined in Section 17.1

“Capture Mode”.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 129

PIC16F707/PIC16LF707

TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELB

ANSELC

APFCON

CCP1CON

CCP2CON

CCPRxL

CCPRxH

INTCON

ANSB7

ANSC7

—

ANSB6

ANSC6

—

ANSB5

ANSC5

—

ANSB4

—

ANSB3

—

ANSB2

ANSC2

—

ANSB1

ANSC1

SSSEL

ANSB0

ANSC0

1111 1111

111- -111

1111 1111

111- -111

---- --00

--00 0000

uuuu uuuu

—

CCP2SEL ---- --00

—

DC1B1

DC2B1

DC1B0

DC2B0

CCP1M3

CCP2M3

CCP1M2

CCP2M2

CCP1M1

CCP2M1

CCP1M0

CCP2M0

--00 0000

xxxx xxxx

—

Capture/Compare/PWM Register X Low Byte

Capture/Compare/PWM Register X High Byte

GIE

PEIE

TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

0000 000x

0000 0000

0000 ---0

0000 0000

0000 ---0

0000 000x

0000 0000

0000 ---0

0000 0000

0000 ---0

PIE1

PIE2

PIR1

PIR2

TMR1GIE

TMR3GIE

ADIE

RCIE

TXIE

SSPIE

—

CCP1IE

—

TMR2IE

—

TMR1IE

TMR3IE

TMRBIE

TMRAIE

CCP2IE

TMR1IF

CCP2IF

TMR1ON

TMR1GIF

TMR3GIF

ADIF

RCIF

TXIF

SSPIF

—

CCP1IF

—

TMR2IF

TMR3IF

TMRBIF

TMRAIF

—

TMR1CS1 TMR1CS0 T1CKPS1

T1CKPS0 T1OSCEN

T1SYNC

T1CON

0000 00-0

0000 0x00

uuuu uu-u

0000 0x00

T1GCON

TMR1GE

T1GPOL

T1GTM

T1GSPM

T1GGO/

DONE

T1GVAL

T1GSS1

T1GSS0

TMR1L

TMR1H

TRISB

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx

1111 1111

uuuu uuuu

1111 1111

TRISB7

TRISC7

TRISB6

TRISC6

TRISB5

TRISC5

TRISB4

TRISC4

TRISB3

TRISC3

TRISB2

TRISC2

TRISB1

TRISC1

TRISB0

TRISC0

TRISC

1111 1111

Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Capture.

DS41418A-page 130

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

17.2.2

TIMER1 MODE SELECTION

17.2 Compare Mode

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

In Compare mode, the 16-bit CCPRx register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the CCPx module may:

• Toggle the CCPx output

• Set the CCPx output

Note:

Clocking Timer1 from the system clock

(FOSC) should not be used in Compare

mode. For the Compare operation of the

TMR1 register to the CCPRx register to

occur, Timer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

• Clear the CCPx output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCPxM<3:0> control bits of the CCPxCON register.

All Compare modes can generate an interrupt.

17.2.3

SOFTWARE INTERRUPT MODE

When Software Interrupt mode is chosen

(CCPxM<3:0> = 1010), the CCPxIF bit in the PIRx

register is set and the CCPx module does not assert

control of the CCPx pin (refer to the CCPxCON

register).

FIGURE 17-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

CCPxCON<3:0>

Mode Select

17.2.4

SPECIAL EVENT TRIGGER

Set CCPxIF Interrupt Flag

(PIRx)

When Special Event Trigger mode is chosen

(CCPxM<3:0> = 1011), the CCPx module does the

following:

4

CCPRxH CCPRxL

Comparator

CCPx

Q

S

R

Output

Logic

• Resets Timer1

Match

• Starts an ADC conversion if ADC is enabled

(CCP2 only)

TMR1H TMR1L

TRIS

Output Enable

The CCPx module does not assert control of the CCPx

pin in this mode (refer to the CCPxCON register).

Special Event Trigger

Special Event Trigger will:

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPRxH, CCPRxL

register pair. The TMR1H, TMR1L register pair is not

reset until the next rising edge of the Timer1 clock. This

allows the CCPRxH, CCPRxL register pair to

effectively provide a 16-bit programmable period

register for Timer1.

•

Clear TMR1H and TMR1L registers.

NOT set interrupt flag bit TMR1IF of the PIR1 register.

Set the GO/DONE bit to start the ADC conversion

(CCP2 only).

17.2.1

CCPx PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the associated TRIS bit.

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMR1IF of the PIR1 register.

Either RC1 or RB3 can be selected as the CCP2 pin.

Refer to Section 6.1 “Alternate Pin Function” for

more information.

2: Removing the match condition by

changing the contents of the CCPRxH

and CCPRxL register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates the Timer1 Reset, will preclude

the Reset from occurring.

Note:

Clearing the CCPxCON register will force

the CCPx compare output latch to the

default low level. This is not the PORT I/O

data latch.

17.2.5

COMPARE DURING SLEEP

The Compare mode is dependent upon the system

clock (FOSC) for proper operation. Since FOSC is shut

down during Sleep mode, the Compare mode will not

function properly during Sleep.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 131

PIC16F707/PIC16LF707

TABLE 17-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADCON0

ANSELB

ANSELC

APFCON

CCP1CON

CCP2CON

CCPRxL

CCPRxH

INTCON

—

ANSB7

ANSC7

—

ANSB6

ANSC6

—

CHS3

ANSB5

ANSC5

—

CHS2

ANSB4

—

CHS1

ANSB3

—

CHS0

ANSB2

ANSC2

—

GO/DONE

ANSB1

ADON

ANSB0

ANSC0

--00 0000

1111 1111

111- -111

--00 0000

1111 1111

111- -111

---- --00

--00 0000

uuuu uuuu

0000 000x

ANSC1

—

SSSEL

CCP2SEL ---- --00

—

DC1B1

DC2B1

DC1B0

DC2B0

CCP1M3

CCP2M3

CCP1M2

CCP2M2

CCP1M1

CCP2M1

CCP1M0

CCP2M0

--00 0000

xxxx xxxx

0000 000x

—

Capture/Compare/PWM Register X Low Byte

Capture/Compare/PWM Register X High Byte

GIE

PEIE

TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

PIE1

PIE2

TMR1GIE

TMR3GIE

ADIE

RCIE

TXIE

SSPIE

—

CCP1IE

—

TMR2IE

—

TMR1IE

CCP2IE

0000 0000

0000 ---0

0000 0000

0000 ---0

TMR3IE

TMRBIE

TMRAIE

PIR1

TMR1GIF

TMR3GIF

ADIF

RCIF

TXIF

SSPIF

—

CCP1IF

—

TMR2IF

—

TMR1IF

CCP2IF

TMR1ON

T1GSS0

0000 0000

0000 ---0

0000 00-0

0000 0x00

0000 0000

0000 ---0

uuuu uu-u

0000 0x00

TMR3IF

TMRBIF

TMRAIF

PIR2

TMR1CS1 TMR1CS0 T1CKPS1

T1CKPS0 T1OSCEN

T1SYNC

T1GVAL

—

T1CON

T1GCON

TMR1GE

T1GPOL

T1GTM

T1GSPM

T1GGO/

DONE

T1GSS1

TMR1L

TMR1H

TRISB

TRISC

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx

1111 1111

uuuu uuuu

1111 1111

TRISB7

TRISC7

TRISB6

TRISC6

TRISB5

TRISC5

TRISB4

TRISC4

TRISB3

TRISC3

TRISB2

TRISC2

TRISB1

TRISC1

TRISB0

TRISC0

Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Compare.

DS41418A-page 132

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

The PWM output (Figure 17-4) has a time base

(period) and a time that the output stays high (duty

cycle).

17.3 PWM Mode

The PWM mode generates a pulse-width modulated

signal on the CCPx pin. The duty cycle, period and

resolution are determined by the following registers:

FIGURE 17-4:

CCP PWM OUTPUT

• PR2

Period

• T2CON

• CCPRxL

• CCPxCON

Pulse Width

TMR2 = PR2

TMR2 = CCPRxL:CCPxCON<5:4>

In Pulse-Width Modulation (PWM) mode, the CCP

module produces up to a 10-bit resolution PWM output

on the CCPx pin.

TMR2 = 0

Figure 17-3 shows a simplified block diagram of PWM

operation.

17.3.1

CCPX PIN CONFIGURATION

In PWM mode, the CCPx pin is multiplexed with the

PORT data latch. The user must configure the CCPx

pin as an output by clearing the associated TRIS bit.

Figure 17-4 shows a typical waveform of the PWM

signal.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, refer to Section 17.3.8

“Setup for PWM Operation”.

Either RC1 or RB3 can be selected as the CCP2 pin.

Refer to Section 6.1 “Alternate Pin Function” for

more information.

FIGURE 17-3:

SIMPLIFIED PWM BLOCK

DIAGRAM

Note:

Clearing the CCPxCON register will

relinquish CCPx control of the CCPx pin.

CCPxCON<5:4>

Duty Cycle Registers

CCPRxL

CCPRxH⁽²⁾(Slave)

CCPx

R

S

Q

Comparator

(1)

TMR2

TRIS

Comparator

PR2

Clear Timer2,

toggle CCPx pin and

latch duty cycle

Note 1: The 8-bit timer TMR2 register is concatenated

with the 2-bit internal system clock (FOSC), or

2 bits of the prescaler, to create the 10-bit time

base.

2: In PWM mode, CCPRxH is a read-only register.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 133

PIC16F707/PIC16LF707

17.3.2

PWM PERIOD

EQUATION 17-2: PULSE WIDTH

The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the

formula of Equation 17-1.

Pulse Width = CCPRxL:CCPxCON<5:4> 

TOSC  (TMR2 Prescale Value)

EQUATION 17-1: PWM PERIOD

Note: TOSC = 1/FOSC

PWM Period = PR2 + 1  4  TOSC 

EQUATION 17-3: DUTY CYCLE RATIO

(TMR2 Prescale Value)

CCPRxL:CCPxCON<5:4>

Duty Cycle Ratio = ----------------------------------------------------------------------

4PR2 + 1

Note:

TOSC = 1/FOSC

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

The CCPRxH register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

• TMR2 is cleared

• The CCPx pin is set. (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

The 8-bit timer TMR2 register is concatenated with

either the 2-bit internal system clock (FOSC), or 2 bits of

the prescaler, to create the 10-bit time base. The system

clock is used if the Timer2 prescaler is set to 1:1.

• The PWM duty cycle is latched from CCPRxL into

CCPRxH.

When the 10-bit time base matches the CCPRxH and

2-bit latch, then the CCPx pin is cleared (refer to

Figure 17-3).

Note:

The

Timer2

postscaler

(refer

to

Section 15.1 “Timer2 Operation”) is not

used in the determination of the PWM

frequency.

17.3.3

PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit value

to multiple registers: CCPRxL register and DCxB<1:0>

bits of the CCPxCON register. The CCPRxL contains

the eight MSbs and the DCxB<1:0> bits of the

CCPxCON register contain the two LSbs. CCPRxL and

DCxB<1:0> bits of the CCPxCON register can be written

to at any time. The duty cycle value is not latched into

CCPRxH until after the period completes (i.e., a match

between PR2 and TMR2 registers occurs). While using

the PWM, the CCPRxH register is read-only.

Equation 17-2 is used to calculate the PWM pulse

width.

Equation 17-3 is used to calculate the PWM duty cycle

ratio.

DS41418A-page 134

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

17.3.4

PWM RESOLUTION

EQUATION 17-4: PWM RESOLUTION

The resolution determines the number of available duty

cycles for a given period. For example, a 10-bit resolution

will result in 1024 discrete duty cycles, whereas an 8-bit

resolution will result in 256 discrete duty cycles.

log4PR2 + 1

Resolution = ----------------------------------------- bits

log2

The maximum PWM resolution is 10 bits when PR2 is

255. The resolution is a function of the PR2 register

value as shown by Equation 17-4.

Note:

If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

TABLE 17-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency

1.22 kHz

4.88 kHz

19.53 kHz

78.12 kHz

156.3 kHz

208.3 kHz

Timer Prescale (1, 4, 16)

PR2 Value

16

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

TABLE 17-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency

1.22 kHz

4.90 kHz

19.61 kHz

76.92 kHz

153.85 kHz 200.0 kHz

Timer Prescale (1, 4, 16)

PR2 Value

16

0x65

8

4

0x65

8

1

0x65

8

1

0x19

6

1

0x0C

5

1

0x09

5

Maximum Resolution (bits)

17.3.5

OPERATION IN SLEEP MODE

17.3.8

SETUP FOR PWM OPERATION

In Sleep mode, the TMR2 register will not increment

and the state of the module will not change. If the CCPx

pin is driving a value, it will continue to drive that value.

When the device wakes up, TMR2 will continue from its

previous state.

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Disable the PWM pin (CCPx) output driver(s) by

setting the associated TRIS bit(s).

2. Load the PR2 register with the PWM period value.

3. Configure the CCP module for the PWM mode

by loading the CCPxCON register with the

appropriate values.

17.3.6

CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency (FOSC). Any changes in the system clock fre-

quency will result in changes to the PWM frequency.

Refer to Section 7.0 “Oscillator Module” for

additional details.

4. Load the CCPRxL register and the DCxBx bits of

the CCPxCON register, with the PWM duty cycle

value.

5. Configure and start Timer2:

•

Clear the TMR2IF interrupt flag bit of the PIR1

register. See Note below.

17.3.7

EFFECTS OF RESET

Configure the T2CKPS bits of the T2CON

register with the Timer2 prescale value.

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

Enable Timer2 by setting the TMR2ON bit of

the T2CON register.

6. Enable PWM output pin:

•

Wait until Timer2 overflows, TMR2IF bit of the

PIR1 register is set. See Note below.

•

Enable the PWM pin (CCPx) output driver(s) by

clearing the associated TRIS bit(s).

Note:

In order to send a complete duty cycle and

period on the first PWM output, the above

steps must be included in the setup

sequence. If it is not critical to start with a

complete PWM signal on the first output,

then step 6 may be ignored.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 135

PIC16F707/PIC16LF707

TABLE 17-7: SUMMARY OF REGISTERS ASSOCIATED WITH PWM

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELB

ANSELC

APFCON

CCP1CON

CCP2CON

CCPRxL

CCPRxH

ANSB7

ANSC7

—

ANSB6

ANSC6

—

ANSB5

ANSC5

—

ANSB4

—

ANSB3

—

ANSB2

ANSC2

—

ANSB1

ANSC1

SSSEL

ANSB0

ANSC0

1111 1111

111- -111

1111 1111

111- -111

---- --00

--00 0000

uuuu uuuu

—

CCP2SEL ---- --00

—

DC1B1

DC2B1

DC1B0

DC2B0

CCP1M3

CCP2M3

CCP1M2

CCP2M2

CCP1M1

CCP2M1

CCP1M0

CCP2M0

--00 0000

xxxx xxxx

1111 1111

—

Capture/Compare/PWM Register X Low Byte

Capture/Compare/PWM Register X High Byte

Timer2 Period Register

PR2

1111 1111

-000 0000

0000 0000

1111 1111

-000 0000

0000 0000

1111 1111

T2CON

TMR2

TRISB

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

Timer2 Module Register

TRISB7

TRISC7

TRISB6

TRISC6

TRISB5

TRISC5

TRISB4

TRISC4

TRISB3

TRISC3

TRISB2

TRISC2

TRISB1

TRISC1

TRISB0

TRISC0

TRISC

1111 1111

Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the PWM.

DS41418A-page 136

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

The AUSART module includes the following capabilities:

18.0 ADDRESSABLE UNIVERSAL

SYNCHRONOUS

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

ASYNCHRONOUS RECEIVER

TRANSMITTER (AUSART)

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Sleep operation

The

Addressable

Universal

Synchronous

Asynchronous Receiver Transmitter (AUSART)

module is a serial I/O communications peripheral. It

contains all the clock generators, shift registers and

data buffers necessary to perform an input or output

serial data transfer independent of device program

execution. The AUSART, also known as a Serial

Communications Interface (SCI), can be configured as

a full-duplex asynchronous system or half-duplex

synchronous system. Full-Duplex mode is useful for

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These devices typically do not have internal clocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

Block diagrams of the AUSART transmitter and

receiver are shown in Figure 18-1 and Figure 18-2.

FIGURE 18-1:

AUSART TRANSMIT BLOCK DIAGRAM

Data Bus

TXIE

Interrupt

TXIF

TXREG Register

8

TX/CK

MSb

(8)

LSb

0

Pin Buffer

and Control

• • •

Transmit Shift Register (TSR)

TXEN

TRMT

SPEN

Baud Rate Generator

FOSC

÷ n

TX9

n

+ 1

Multiplier x4 x16 x64

TX9D

SYNC

BRGH

1

x

0

1

0

SPBRG

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 137

PIC16F707/PIC16LF707

FIGURE 18-2:

AUSART RECEIVE BLOCK DIAGRAM

SPEN

CREN

OERR

RX/DT

RSR Register

MSb

Stop (8)

LSb

Pin Buffer

and Control

Data

Recovery

7

1

0

START

• • •

Baud Rate Generator

FOSC

RX9

÷ n

n

+ 1

Multiplier x4 x16 x64

SYNC

BRGH

1

x

0

1

0

FIFO

SPBRG

RX9D

FERR

RCREG Register

8

Data Bus

RCIF

RCIE

Interrupt

The operation of the AUSART module is controlled

through two registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

These registers are detailed in Register 18-1 and

Register 18-2, respectively.

DS41418A-page 138

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

18.1 AUSART Asynchronous Mode

Note 1: When the SPEN bit is set, the RX/DT I/O

pin is automatically configured as an input,

regardless of the state of the corresponding

TRIS bit and whether or not the AUSART

receiver is enabled. The RX/DT pin data

can be read via a normal PORT read but

PORT latch data output is precluded.

The AUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH mark state which

represents a ‘1’ data bit, and a VOL space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output level of that bit without returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the mark state. Each character

transmission consists of one Start bit followed by eight

or nine data bits and is always terminated by one or

more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is 8 bits. Each transmitted bit persists for a period

of 1/(Baud Rate). An on-chip dedicated 8-bit Baud Rate

Generator is used to derive standard baud rate

frequencies from the system oscillator. Refer to

Table 18-5 for examples of baud rate configurations.

2: The corresponding ANSEL bit must be

cleared for the RX/DT port pin to ensure

proper AUSART functionality.

3: The TXIF transmitter interrupt flag is set

when the TXEN enable bit is set.

18.1.1.2

Transmitting Data

A transmission is initiated by writing a character to the

TXREG register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately

transferred to the TSR register. If the TSR still contains

all or part of a previous character, the new character

data is held in the TXREG until the Stop bit of the

previous character has been transmitted. The pending

character in the TXREG is then transferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the Start bit, data bits

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TXREG.

The AUSART transmits and receives the LSb first. The

AUSART’s transmitter and receiver are functionally

independent, but share the same data format and baud

rate. Parity is not supported by the hardware, but can

be implemented in software and stored as the ninth

data bit.

18.1.1

AUSART ASYNCHRONOUS

TRANSMITTER

The AUSART transmitter block diagram is shown in

Figure 18-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXREG register.

18.1.1.3

Transmit Interrupt Flag

The TXIF interrupt flag bit of the PIR1 register is set

whenever the AUSART transmitter is enabled and no

character is being held for transmission in the TXREG.

In other words, the TXIF bit is only clear when the TSR

is busy with a character and a new character has been

queued for transmission in the TXREG. The TXIF flag

bit is not cleared immediately upon writing TXREG.

TXIF becomes valid in the second instruction cycle

following the write execution. Polling TXIF immediately

following the TXREG write will return invalid results. The

TXIF bit is read-only, it cannot be set or cleared by

software.

18.1.1.1

Enabling the Transmitter

The AUSART transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

• TXEN = 1

• SYNC = 0

• SPEN = 1

All other AUSART control bits are assumed to be in

their default state.

The TXIF interrupt can be enabled by setting the TXIE

interrupt enable bit of the PIE1 register. However, the

TXIF flag bit will be set whenever the TXREG is empty,

regardless of the state of TXIE enable bit.

Setting the TXEN bit of the TXSTA register enables the

transmitter circuitry of the AUSART. Clearing the SYNC

bit of the TXSTA register configures the AUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the AUSART and

automatically configures the TX/CK I/O pin as an output.

To use interrupts when transmitting data, set the TXIE

bit only when there is more data to send. Clear the

TXIE interrupt enable bit upon writing the last character

of the transmission to the TXREG.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 139

PIC16F707/PIC16LF707

18.1.1.4

TSR Status

18.1.1.6

Asynchronous Transmission Set-up:

The TRMT bit of the TXSTA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

register from the TXREG. The TRMT bit remains clear

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user has to

poll this bit to determine the TSR status.

1. Initialize the SPBRG register and the BRGH bit to

achieve the desired baud rate (Refer to

Section 18.2 “AUSART Baud Rate Generator

(BRG)”).

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If 9-bit transmission is desired, set the TX9 con-

trol bit. A set ninth data bit will indicate that the 8

Least Significant data bits are an address when

the receiver is set for address detection.

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

4. Enable the transmission by setting the TXEN

control bit. This will cause the TXIF interrupt bit

to be set.

18.1.1.5

Transmitting 9-Bit Characters

The AUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTA register is set the

AUSART will shift 9 bits out for each character transmit-

ted. The TX9D bit of the TXSTA register is the ninth,

and Most Significant, data bit. When transmitting 9-bit

data, the TX9D data bit must be written before writing

the 8 Least Significant bits into the TXREG. All nine bits

of data will be transferred to the TSR shift register

immediately after the TXREG is written.

5. If interrupts are desired, set the TXIE interrupt

enable bit of the PIE1 register. An interrupt will

occur immediately provided that the GIE and

PEIE bits of the INTCON register are also set.

6. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

7. Load 8-bit data into the TXREG register. This

will start the transmission.

A special 9-bit Address mode is available for use with

multiple receivers. Refer to Section 18.1.2.7 “Address

Detection” for more information on the Address mode.

FIGURE 18-3:

ASYNCHRONOUS TRANSMISSION

Write to TXREG

Word 1

BRG Output

(Shift Clock)

TX/CK pin

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXIF bit

(Transmit Buffer

Empty Flag)

1 TCY

Word 1

Transmit Shift Reg

TRMT bit

(Transmit Shift

Reg. Empty Flag)

FIGURE 18-4:

ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Write to TXREG

Word 2

Start bit

Word 1

BRG Output

(Shift Clock)

TX/CK pin

Start bit

Word 2

bit 0

bit 1

bit 7/8

bit 0

Stop bit

TXIF bit

(Transmit Buffer

Empty Flag)

1 TCY

Word 1

1 TCY

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Transmit Shift Reg.

Word 2

Transmit Shift Reg.

Note:

This timing diagram shows two consecutive transmissions.

DS41418A-page 140

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 18-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

PEIE

ADIE

ADIF

RX9

TMR0IE

RCIE

INTE

TXIE

RBIE

SSPIE

SSPIF

ADDEN

BRG3

TMR0IF

INTF

RBIF

0000 000x 0000 000x

TMR1GIE

TMR1GIF

SPEN

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIR1

RCIF

TXIF

RCSTA

SPBRG

TRISC

TXREG

TXSTA

Legend:

SREN

BRG5

CREN

BRG4

FERR

BRG2

OERR

BRG1

RX9D

BRG0

0000 000x 0000 000x

0000 0000 0000 0000

BRG7

BRG6

TRISC7

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

AUSART Transmit Data Register

TXEN SYNC BRGH

0000 0000 0000 0000

0000 -010 0000 -010

CSRC

TX9

—

TRMT

TX9D

x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for asynchronous transmission.

18.1.2

AUSART ASYNCHRONOUS

RECEIVER

18.1.2.1

Enabling the Receiver

The AUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:

The Asynchronous mode is typically used in RS-232

systems. The receiver block diagram is shown in

Figure 18-2. The data is received on the RX/DT pin and

drives the data recovery block. The data recovery block

is actually a high-speed shifter operating at 16 times

the baud rate, whereas the serial Receive Shift

Register (RSR) operates at the bit rate. When all 8 or 9

bits of the character have been shifted in, they are

immediately transferred to a two character First-In

First-Out (FIFO) memory. The FIFO buffering allows

reception of two complete characters and the start of a

third character before software must start servicing the

AUSART receiver. The FIFO and RSR registers are not

directly accessible by software. Access to the received

data is via the RCREG register.

• CREN = 1

• SYNC = 0

• SPEN = 1

All other AUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCSTA register enables the

receiver circuitry of the AUSART. Clearing the SYNC bit

of the TXSTA register configures the AUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the AUSART and

automatically configures the RX/DT I/O pin as an input.

Note 1: When the SPEN bit is set, the TX/CK I/O

pin is automatically configured as an out-

put, regardless of the state of the corre-

sponding TRIS bit and whether or not the

AUSART transmitter is enabled. The

PORT latch is disconnected from the out-

put driver so it is not possible to use the

TX/CK pin as a general purpose output.

2: The corresponding ANSEL bit must be

cleared for the RX/DT port pin to ensure

proper AUSART functionality.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 141

PIC16F707/PIC16LF707

18.1.2.2

Receiving Data

18.1.2.4

Receive Framing Error

The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,

also known as the Start bit, is always a zero. The data

recovery circuit counts one-half bit time to the center of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit counts a full bit time to the center of the

next bit. The bit is then sampled by a majority detect

circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.

This repeats until all data bits have been sampled and

shifted into the RSR. One final bit time is measured and

the level sampled. This is the Stop bit, which is always

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

character, otherwise the framing error is cleared for this

character. Refer to Section 18.1.2.4 “Receive

Framing Error” for more information on framing

errors.

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indicates that a Stop bit was not seen at the expected

time. The framing error status is accessed via the

FERR bit of the RCSTA register. The FERR bit

represents the status of the top unread character in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RCREG.

The FERR bit is read-only and only applies to the top

unread character in the receive FIFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCSTA register which resets the AUSART.

Clearing the CREN bit of the RCSTA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

Note:

If all receive characters in the receive

FIFO have framing errors, repeated reads

of the RCREG will not clear the FERR bit.

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the AUSART receive FIFO and the RCIF interrupt

flag bit of the PIR1 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RCREG register.

18.1.2.5

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before the FIFO is accessed. When

this happens the OERR bit of the RCSTA register is

set. The characters already in the FIFO buffer can be

read but no additional characters will be received until

the error is cleared. The error must be cleared by either

clearing the CREN bit of the RCSTA register or by

setting the AUSART by clearing the SPEN bit of the

RCSTA register.

Note:

If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition

is

cleared.

Refer

to

Section 18.1.2.5

“Receive

Overrun

Error” for more information on overrun

errors.

18.1.2.3

Receive Interrupts

The RCIF interrupt flag bit of the PIR1 register is set

whenever the AUSART receiver is enabled and there is

an unread character in the receive FIFO. The RCIF

interrupt flag bit is read-only, it cannot be set or cleared

by software.

18.1.2.6

Receiving 9-bit Characters

The AUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set the AUSART

will shift 9 bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth and Most Significant data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the 8 Least Significant bits from

the RCREG.

RCIF interrupts are enabled by setting all of the

following bits:

• RCIE, Receive Interrupt Enable bit of the PIE1

register

• PEIE, Peripheral Interrupt Enable bit of the

INTCON register

• GIE, Global Interrupt Enable bit of the INTCON

register

The RCIF interrupt flag bit of the PIR1 register will be

set when there is an unread character in the FIFO,

regardless of the state of interrupt enable bits.

DS41418A-page 142

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

18.1.2.7

Address Detection

18.1.2.9

9-bit Address Detection Mode Set-

up

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCSTA

register.

This mode would typically be used in RS-485 systems.

To set up an asynchronous reception with address

detect enable:

1. Initialize the SPBRG register and the BRGH bit

to achieve the desired baud rate (refer to

Section 18.2 “AUSART Baud Rate Generator

(BRG)”).

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffer, thereby setting the RCIF interrupt

bit of the PIR1 register. All other characters will be

ignored.

2. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

3. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

4. Enable 9-bit reception by setting the RX9 bit.

5. Enable address detection by setting the ADDEN

bit.

6. Enable reception by setting the CREN bit.

7. The RCIF interrupt flag bit of the PIR1 register

will be set when a character with the ninth bit set

is transferred from the RSR to the receive buffer.

An interrupt will be generated if the RCIE inter-

rupt enable bit of the PIE1 register was also set.

18.1.2.8

Asynchronous Reception Set-up:

1. Initialize the SPBRG register and the BRGH bit

to achieve the desired baud rate (refer to

Section 18.2 “AUSART Baud Rate Generator

(BRG)”).

8. Read the RCSTA register to get the error flags.

The ninth data bit will always be set.

2. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

9. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

register. Software determines if this is the

device’s address.

3. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

4. If 9-bit reception is desired, set the RX9 bit.

5. Enable reception by setting the CREN bit.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

6. The RCIF interrupt flag bit of the PIR1 register

will be set when a character is transferred from

the RSR to the receive buffer. An interrupt will be

generated if the RCIE bit of the PIE1 register

was also set.

7. Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

8. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

register.

9. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 143

PIC16F707/PIC16LF707

FIGURE 18-5:

ASYNCHRONOUS RECEPTION

Start

bit

Start

bit

Start

bit

RX/DT pin

bit 7/8

bit 0 bit 1

Stop

bit

Stop

bit

Stop

bit

bit 0

bit 7/8

Rcv Shift

Reg

Rcv Buffer Reg

Word 2

RCREG

Word 1

RCREG

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note:

This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

TABLE 18-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELC

INTCON

PIE1

ANSC7

GIE

ANSC6

PEIE

ANSC5

TMR0IE

RCIE

—

ANSC2

TMR0IF

ANSC1

INTF

ANSC0 111- -111 111- -111

RBIF 0000 000x 0000 000x

INTE

TXIE

TXIF

RBIE

SSPIE

SSPIF

TMR1GIE

TMR1GIF

ADIE

ADIF

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIR1

RCIF

RCREG

RCSTA

SPBRG

TRISC

TXSTA

Legend:

AUSART Receive Data Register

0000 0000 0000 0000

0000 000x 0000 000x

0000 0000 0000 0000

SPEN

BRG7

RX9

SREN

BRG5

CREN

BRG4

ADDEN

BRG3

FERR

BRG2

OERR

BRG1

RX9D

BRG0

BRG6

TRISC7

CSRC

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010

—

x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for asynchronous reception.

DS41418A-page 144

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0

CSRC

R/W-0

TX9

R/W-0

TXEN⁽¹⁾

R/W-0

SYNC

U-0

—

R/W-0

BRGH

R-1

R/W-0

TX9D

TRMT

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

bit 4

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

TXEN: Transmit Enable bit⁽¹⁾

1= Transmit enabled

0= Transmit disabled

SYNC: AUSART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

bit 3

bit 2

Unimplemented: Read as ‘0’

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Synchronous mode.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 145

PIC16F707/PIC16LF707

REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0

SPEN

R/W-0

RX9

R/W-0

SREN

R/W-0

CREN

R/W-0

R-0

R-x

ADDEN

FERR

OERR

RX9D

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit⁽¹⁾

1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0= Serial port disabled (held in Reset)

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave:

Don’t care

bit 4

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables receiver

0= Disables receiver

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

0= Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Don’t care

Synchronous mode:

Must be set to ‘0’

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receive next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

Note 1: The AUSART module automatically changes the pin from tri-state to drive as needed. Configure

TRISx = 1.

DS41418A-page 146

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

EXAMPLE 18-1:

CALCULATING BAUD

RATE ERROR

18.2 AUSART Baud Rate Generator

(BRG)

For a device with FOSC of 16 MHz, desired baud rate of

9600, and Asynchronous mode with SYNC = 0and BRGH

= 0(as seen in Table 18-5):

The Baud Rate Generator (BRG) is an 8-bit timer that

is dedicated to the support of both the asynchronous

and synchronous AUSART operation.

FOSC

Desired Baud Rate = ---------------------------------------

64SPBRG + 1

The SPBRG register determines the period of the free

running baud rate timer. In Asynchronous mode the

multiplier of the baud rate period is determined by the

BRGH bit of the TXSTA register. In Synchronous mode,

the BRGH bit is ignored.

Solving for SPBRG:

FOSC









--------------------------------------------------------

SPBRG =

=

– 1

Table 18-3 contains the formulas for determining the

baud rate. Example 18-1 provides a sample calculation

for determining the baud rate and baud rate error.

64Desired Baud Rate

16000000

649600







------------------------

– 1



Typical baud rates and error values for various

Asynchronous modes have been computed for your

convenience and are shown in Table 18-5. It may be

advantageous to use the high baud rate (BRGH = 1), to

reduce the baud rate error.

= 25.042 = 25

16000000

Actual Baud Rate = --------------------------

6425 + 1

= 9615

Writing a new value to the SPBRG register causes the

BRG timer to be reset (or cleared). This ensures that

the BRG does not wait for a timer overflow before

outputting the new baud rate.

Actual Baud Rate – Desired Baud Rate





% Error = ------------------------------------------------------------------------------------------------- 100





Desired Baud Rate

9615 – 9600







-----------------------------

=

100 = 0.16%



9600

TABLE 18-3: BAUD RATE FORMULAS

Configuration Bits

Baud Rate Formula

AUSART Mode

SYNC

BRGH

0

1

0

1

x

Asynchronous

Synchronous

FOSC/[64 (n+1)]

FOSC/[16 (n+1)]

FOSC/[4 (n+1)]

Legend: x= Don’t care, n = value of SPBRG register

TABLE 18-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RCSTA

SPBRG

TXSTA

SPEN

BRG7

CSRC

RX9

BRG6

TX9

SREN

BRG5

TXEN

CREN

BRG4

SYNC

ADDEN

BRG3

—

FERR

BRG2

BRGH

OERR

BRG1

TRMT

RX9D

BRG0

TX9D

0000 000x 0000 000x

0000 0000 0000 0000

0000 -010 0000 -010

Legend:

x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 147

PIC16F707/PIC16LF707

TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0

FOSC = 20.000 MHz

FOSC = 18.432 MHz

FOSC = 16.0000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

—

1201

2403

9615

10416

19.23k

—

0.08

0.16

-0.01

0.16

—

207

103

25

300

1200

—

255

129

32

—

239

119

29

—

143

71

17

16

8

1221

2404

9470

10417

19.53k

1.73

0.16

-1.36

0.00

1.73

1200

2400

9600

10286

19.20k

0.00

-1.26

0.00

—

1200

2400

9600

10165

19.20k

0.00

-2.42

0.00

—

2400

9600

10417

19.2k

57.6k

115.2k

29

27

23

15

14

12

—

2

—

57.60k

—

7

57.60k

—

SYNC = 0, BRGH = 0

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

0.00

—

300

1200

—

1202

2404

9615

10417

—

0.16

0.00

—

103

51

12

11

300

1202

2404

—

0.16

—

207

51

25

—

5

300

1200

2400

9600

—

191

47

23

5

300

1202

—

0.16

—

51

12

—

2400

9600

—

10417

19.2k

57.6k

115.2k

10417

—

0.00

—

2

—

19.20k

0.00

—

0

—

57.60k

—

SYNC = 0, BRGH = 1

FOSC = 18.432 MHz FOSC = 16.0000 MHz

FOSC = 20.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

—

300

1200

2400

9600

10417

19.2k

57.6k

—

71

65

35

11

5

9615

10417

19.23k

56.82k

0.16

0.00

0.16

-1.36

129

119

64

9600

10378

19.20k

57.60k

115.2k

0.00

-0.37

0.00

119

110

59

19

9

9615

10417

19.23k

58.8k

—

0.16

0.00

0.16

2.12

—

103

95

51

16

—

9600

0.00

0.53

0.00

10473

19.20k

57.60k

115.2k

21

115.2k 113.64k -1.36

10

DS41418A-page 148

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

—

300

1200

—

1202

2404

9615

10417

19.23k

—

207

103

25

—

191

95

23

21

11

3

300

1202

2404

—

0.16

—

207

51

25

—

5

0.16

0.00

0.16

—

1200

0.00

0.53

0.00

2400

2404

9615

10417

19231

55556

—

0.16

0.00

0.16

-3.55

—

207

51

47

25

8

2400

9600

10417

19.2k

57.6k

115.2k

23

10473

19.2k

57.60k

115.2k

10417

—

0.00

—

12

—

1

—

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 149

PIC16F707/PIC16LF707

18.3.1.2

Synchronous Master Transmission

18.3 AUSART Synchronous Mode

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are

automatically enabled when the AUSART is configured

for synchronous master transmit operation.

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary cir-

cuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the

internal clock generation circuitry.

A transmission is initiated by writing a character to the

TXREG register. If the TSR still contains all or part of a

previous character, the new character data is held in

the TXREG until the last bit of the previous character

has been transmitted. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately trans-

ferred to the TSR. The transmission of the character

commences immediately following the transfer of the

data to the TSR from the TXREG.

There are two signal lines in Synchronous mode: a

bidirectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and trans-

mit shift registers. Since the data line is bidirectional,

synchronous operation is half-duplex only. Half-duplex

refers to the fact that master and slave devices can

receive and transmit data but not both simultaneously.

The AUSART can operate as either a master or slave

device.

Each data bit changes on the leading edge of the

master clock and remains valid until the subsequent

leading clock edge.

Start and Stop bits are not used in synchronous

transmissions.

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

18.3.1

SYNCHRONOUS MASTER MODE

18.3.1.3

Synchronous Master Transmission

Set-up:

The following bits are used to configure the AUSART

for Synchronous Master operation:

1. Initialize the SPBRG register and the BRGH bit

to achieve the desired baud rate (refer to

Section 18.2 “AUSART Baud Rate Generator

(BRG)”).

• SYNC = 1

• CSRC = 1

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

3. Disable Receive mode by clearing bits SREN

and CREN.

Setting the SYNC bit of the TXSTA register configures

the device for synchronous operation. Setting the CSRC

bit of the TXSTA register configures the device as a

master. Clearing the SREN and CREN bits of the RCSTA

register ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

AUSART.

4. Enable Transmit mode by setting the TXEN bit.

5. If 9-bit transmission is desired, set the TX9 bit.

6. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

18.3.1.1

Master Clock

8. Start transmission by loading data to the

TXREG register.

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device config-

ured as a master transmits the clock on the TX/CK line.

The TX/CK pin output driver is automatically enabled

when the AUSART is configured for synchronous

transmit or receive operation. Serial data bits change

on the leading edge to ensure they are valid at the trail-

ing edge of each clock. One clock cycle is generated

for each data bit. Only as many clock cycles are

generated as there are data bits.

DS41418A-page 150

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 18-6:

SYNCHRONOUS TRANSMISSION

RX/DT

bit 0

bit 1

bit 2

bit 7

bit 0

bit 1

Word 2

bit 7

Word 1

TX/CK pin

Write to

TXREG Reg

Write Word 1

Write Word 2

TXIF bit

(Interrupt Flag)

TRMT bit

‘1’

TXEN bit

Note:

Synchronous Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

FIGURE 18-7:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin

bit 0

bit 2

bit 1

bit 6

bit 7

TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

TXEN bit

TABLE 18-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

PEIE

ADIE

ADIF

RX9

TMR0IE

RCIE

INTE

TXIE

RBIE

SSPIE

SSPIF

ADDEN

BRG3

TMR0IF

INTF

RBIF

0000 000x 0000 000x

TMR1GIE

TMR1GIF

SPEN

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIR1

RCIF

TXIF

RCSTA

SPBRG

TRISC

TXREG

TXSTA

Legend:

SREN

BRG5

CREN

BRG4

FERR

BRG2

OERR

BRG1

RX9D

BRG0

0000 000x 0000 000x

0000 0000 0000 0000

BRG7

BRG6

TRISC7

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

AUSART Transmit Data Register

TXEN SYNC BRGH

0000 0000 0000 0000

0000 -010 0000 -010

CSRC

TX9

—

TRMT

TX9D

x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for synchronous master transmission.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 151

PIC16F707/PIC16LF707

18.3.1.4

Synchronous Master Reception

18.3.1.7

Receiving 9-bit Characters

Data is received at the RX/DT pin. The RX/DT pin

output driver is automatically disabled when the

AUSART is configured for synchronous master receive

operation.

The AUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set, the AUSART

will shift 9-bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth, and Most Significant, data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the 8 Least Significant bits from

the RCREG.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCSTA register) or the Continuous Receive Enable bit

(CREN of the RCSTA register).

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the completion of one character. When CREN is set,

clocks are continuously generated until CREN is

cleared. If CREN is cleared in the middle of a character

the CK clock stops immediately and the partial charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cleared at the completion of the first character

and CREN takes precedence.

Address detection in Synchronous modes is not

supported, therefore the ADDEN bit of the RCSTA

register must be cleared.

18.3.1.8

Synchronous Master Reception

Set-up:

1. Initialize the SPBRG register for the appropriate

baud rate. Set or clear the BRGH bit, as

required, to achieve the desired baud rate.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

3. Ensure bits CREN and SREN are clear.

Register (RSR). When

a complete character is

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

received into the RSR, the RCIF bit of the PIR1 register

is set and the character is automatically transferred to

the two character receive FIFO. The Least Significant

eight bits of the top character in the receive FIFO are

available in RCREG. The RCIF bit remains set as long

as there are un-read characters in the receive FIFO.

5. If 9-bit reception is desired, set bit RX9.

6. Verify address detection is disabled by clearing

the ADDEN bit of the RCSTA register.

7. Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

18.3.1.5

Synchronous data transfers use a separate clock line,

which is synchronous with the data. device

Slave Clock

8. Interrupt flag bit RCIF of the PIR1 register will be

set when reception of a character is complete.

An interrupt will be generated if the RCIE inter-

rupt enable bit of the PIE1 register was set.

A

configured as a slave receives the clock on the TX/CK

line. The TX/CK pin output driver is automatically

disabled when the device is configured for

synchronous slave transmit or receive operation. Serial

data bits change on the leading edge to ensure they are

valid at the trailing edge of each clock. One data bit is

transferred for each clock cycle. Only as many clock

cycles should be received as there are data bits.

9. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RCREG register.

11. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit, which

resets the AUSART.

18.3.1.6

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before RCREG is read to access

the FIFO. When this happens the OERR bit of the

RCSTA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

will be received until the error is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RCREG. If the overrun occurred when the CREN bit is

set then the error condition is cleared by either clearing

the CREN bit of the RCSTA register.

DS41418A-page 152

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 18-8:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

TX/CK pin

Write to

bit SREN

SREN bit

‘0’

CREN bit

RCIF bit

(Interrupt)

Read

RCREG

Note:

Timing diagram demonstrates Synchronous Master mode with bit SREN = 1and bit BRGH = 0.

TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELC

INTCON

PIE1

ANSC7

GIE

ANSC6

PEIE

ANSC5

TMR0IE

RCIE

—

ANSC2

TMR0IF

ANSC1

INTF

ANSC0 111- -111 111- -111

RBIF 0000 000x 0000 000x

INTE

TXIE

TXIF

RBIE

SSPIE

SSPIF

TMR1GIE

TMR1GIF

ADIE

ADIF

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIR1

RCIF

RCREG

RCSTA

TRISC

TXSTA

Legend:

AUSART Receive Data Register

SREN CREN ADDEN FERR

0000 0000 0000 0000

0000 000X 0000 000X

SPEN

TRISC7

CSRC

RX9

OERR

RX9D

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010

—

x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for synchronous master reception.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 153

PIC16F707/PIC16LF707

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

18.3.2

SYNCHRONOUS SLAVE MODE

The following bits are used to configure the AUSART

for synchronous slave operation:

1. The first character will immediately transfer to

the TSR register and transmit.

• SYNC = 1

2. The second word will remain in TXREG register.

3. The TXIF bit will not be set.

• CSRC = 0

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

4. After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

Setting the SYNC bit of the TXSTA register configures

the device for synchronous operation. Clearing the

CSRC bit of the TXSTA register configures the device as

a slave. Clearing the SREN and CREN bits of the RCSTA

register ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

AUSART.

5. If the PEIE and TXIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

18.3.2.2

Synchronous Slave Transmission

Set-up:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

18.3.2.1

AUSART Synchronous Slave

Transmit

2. Clear the CREN and SREN bits.

The operation of the Synchronous Master and Slave

modes are identical (refer to Section 18.3.1.2

“Synchronous Master Transmission”), except in the

case of the Sleep mode.

3. If using interrupts, ensure that the GIE and PEIE

bits of the INTCON register are set and set the

TXIE bit.

4. If 9-bit transmission is desired, set the TX9 bit.

5. Enable transmission by setting the TXEN bit.

6. Verify address detection is disabled by clearing

the ADDEN bit of the RCSTA register.

7. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

8. Start transmission by writing the Least

Significant 8 bits to the TXREG register.

TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELC

INTCON

PIE1

ANSC7

GIE

ANSC6

PEIE

ADIE

ADIF

RX9

ANSC5

TMR0IE

RCIE

—

ANSC2

TMR0IF

ANSC1

INTF

ANSC0 111- -111 111- -111

RBIF 0000 000x 0000 000x

INTE

TXIE

TXIF

CREN

RBIE

TMR1GIE

TMR1GIF

SPEN

SSPIE

SSPIF

ADDEN

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIR1

RCIF

RCSTA

TRISC

TXREG

TXSTA

Legend:

SREN

FERR

OERR

RX9D

0000 000X 0000 000X

TRISC7

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

AUSART Transmit Data Register

TXEN SYNC BRGH

0000 0000 0000 0000

0000 -010 0000 -010

CSRC

TX9

—

TRMT

TX9D

x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for synchronous slave transmission.

DS41418A-page 154

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

18.3.2.3

AUSART Synchronous Slave

Reception

18.3.2.4

Synchronous Slave Reception Set-

up:

The operation of the Synchronous Master and Slave

modes is identical (Section 18.3.1.4 “Synchronous

Master Reception”), with the following exceptions:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

• Sleep

• CREN bit is always set, therefore the receiver is

never Idle

3. If 9-bit reception is desired, set the RX9 bit.

4. Verify address detection is disabled by clearing

the ADDEN bit of the RCSTA register.

• SREN bit, which is a “don’t care” in Slave mode

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCREG register. If the RCIE interrupt enable bit

of the PIE1 register is set, the interrupt generated will

wake the device from Sleep and execute the next

instruction. If the GIE bit is also set, the program will

branch to the interrupt vector.

5. Set the CREN bit to enable reception.

6. The RCIF bit of the PIR1 register will be set

when reception is complete. An interrupt will be

generated if the RCIE bit of the PIE1 register

was set.

7. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

register.

8. Retrieve the 8 Least Significant bits from the

receive FIFO by reading the RCREG register.

9. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register.

TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELC

INTCON

PIE1

ANSC7

GIE

ANSC6

PEIE

ANSC5

TMR0IE

RCIE

—

ANSC2

TMR0IF

ANSC1

INTF

ANSC0 111- -111 111- -111

RBIF 0000 000x 0000 000x

INTE

TXIE

TXIF

RBIE

SSPIE

SSPIF

TMR1GIE

TMR1GIF

ADIE

ADIF

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIR1

RCIF

RCREG

RCSTA

TRISC

TXSTA

Legend:

AUSART Receive Data Register

SREN CREN ADDEN FERR

0000 0000 0000 0000

0000 000X 0000 000X

SPEN

TRISC7

CSRC

RX9

OERR

RX9D

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 0000 -010

—

x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 155

PIC16F707/PIC16LF707

18.4.2

SYNCHRONOUS TRANSMIT

DURING SLEEP

18.4 AUSART Operation During Sleep

The AUSART will remain active during Sleep only in the

Synchronous Slave mode. All other modes require the

system clock and therefore cannot generate the

necessary signals to run the transmit or receive shift

registers during Sleep.

To transmit during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA control registers must be

configured for synchronous slave transmission

(refer to Section 18.3.2.2 “Synchronous Slave

Transmission Set-up:”).

Synchronous Slave mode uses an externally generated

clock to run the transmit and receive shift registers.

• The TXIF interrupt flag must be cleared by writing

the output data to the TXREG, thereby filling the

TSR and transmit buffer.

18.4.1

SYNCHRONOUS RECEIVE DURING

SLEEP

• If interrupts are desired, set the TXIE bit of the

PIE1 register and the PEIE bit of the INTCON

register.

To receive during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA control registers must be

configured for synchronous slave reception (refer

to Section 18.3.2.4 “Synchronous Slave

Reception Set-up:”).

Upon entering Sleep mode, the device will be ready to

accept clocks on TX/CK pin and transmit data on the

RX/DT pin. When the data word in the TSR has been

completely clocked out by the external device, the

pending byte in the TXREG will transfer to the TSR and

the TXIF flag will be set. Thereby, waking the processor

from Sleep. At this point, the TXREG is available to

accept another character for transmission, which will

clear the TXIF flag.

• If interrupts are desired, set the RCIE bit of the

PIE1 register and the PEIE bit of the INTCON

register.

• The RCIF interrupt flag must be cleared by read-

ing RCREG to unload any pending characters in

the receive buffer.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit is also set then the Interrupt

Service Routine at address 0004h will be called.

Upon entering Sleep mode, the device will be ready to

accept data and clocks on the RX/DT and TX/CK pins,

respectively. When the data word has been completely

clocked in by the external device, the RCIF interrupt

flag bit of the PIR1 register will be set. Thereby, waking

the processor from Sleep.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit of the INTCON register is

also set, then the Interrupt Service Routine at address

0004h will be called.

DS41418A-page 156

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

A typical SPI connection between microcontroller

devices is shown in Figure 19-1. Addressing of more

than one slave device is accomplished via multiple

hardware slave select lines. External hardware and

additional I/O pins must be used to support multiple

slave select addressing. This prevents extra overhead

in software for communication.

19.0 SSP MODULE OVERVIEW

The Synchronous Serial Port (SSP) module is a serial

interface useful for communicating with other peripher-

als or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers, dis-

play drivers, A/D converters, etc. The SSP module can

operate in one of two modes:

For SPI communication, typically three pins are used:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C™)

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Serial Clock (SCK)

19.1 SPI Mode

Additionally, a fourth pin may be used when in a Slave

mode of operation:

The SPI mode allows 8 bits of data to be synchronously

transmitted and received, simultaneously. The SSP

module can be operated in one of two SPI modes:

• Slave Select (SS)

• Master mode

• Slave mode

SPI is a full-duplex protocol, with all communication

being bidirectional and initiated by a master device. All

clocking is provided by the master device and all bits

are transmitted, MSb first. Care must be taken to

ensure that all devices on the SPI bus are setup to

allow all controllers to send and receive data at the

same time.

FIGURE 19-1:

TYPICAL SPI MASTER/SLAVE CONNECTION

SPI Master SSPM<3:0> = 00xx

SPI Slave SSPM<3:0> = 010x

SDO

SDI

Serial Input Buffer

(SSPBUF)

Serial Input Buffer

(SSPBUF)

SDI

SDO

Shift Register

(SSPSR)

Shift Register

(SSPSR)

LSb

MSb

LSb

Serial Clock

SCK

SS

Slave Select

(optional)

General I/O

Processor 2

Processor 1

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 157

PIC16F707/PIC16LF707

FIGURE 19-2:

SPI MODE BLOCK

DIAGRAM

19.1.1

MASTER MODE

In Master mode, data transfer can be initiated at any

time because the master controls the SCK line. Master

mode determines when the slave (Figure 19-1,

Processor 2) transmits data via control of the SCK line.

Internal

Data Bus

Read

Write

19.1.1.1

Master Mode Operation

SSPBUF Reg

SSPSR Reg

The SSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

register shifts the data in and out of the device, MSb

first. The SSPBUF register holds the data that is written

out of the master until the received data is ready. Once

the eight bits of data have been received, the byte is

moved to the SSPBUF register. The Buffer Full Status

bit, BF of the SSPSTAT register, and the SSP Interrupt

Flag bit, SSPIF of the PIR1 register, are then set.

SDI

bit 0

bit 7

Shift

Clock

SDO

Any write to the SSPBUF register during transmission/

reception of data will be ignored and the Write Collision

Detect bit, WCOL of the SSPCON register, will be set.

User software must clear the WCOL bit so that it can be

determined if the following write(s) to the SSPBUF

register completed successfully.

SS

Control

Enable

RA5/SS

RA0/SS

SSSEL

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data is written to the SSPBUF. The BF bit of the

SSPSTAT register is set when SSPBUF has been

loaded with the received data (transmission is

complete). When the SSPBUF is read, the BF bit is

cleared. This data may be irrelevant if the SPI is only a

transmitter. The SSP interrupt may be used to

determine when the transmission/reception is

complete and the SSPBUF must be read and/or

written. If interrupts are not used, then software polling

can be done to ensure that a write collision does not

occur. Example 19-1 shows the loading of the SSPBUF

(SSPSR) for data transmission.

2

Clock Select

Edge

Select

TMR2

2

Output

Edge

Select

FOSC

Prescaler

4, 16, 64

SCK

4

TRISx

Note:

The SSPSR is not directly readable or

writable and can only be accessed by

addressing the SSPBUF register.

SSPM<3:0>

19.1.1.2

Enabling Master I/O

To enable the serial port, the SSPEN bit of the

SSPCON register, must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, re-initialize the

SSPCON register and then set the SSPEN bit. If a

Master mode of operation is selected in the SSPM bits

of the SSPCON register, the SDI, SDO and SCK pins

will be assigned as serial port pins.

For these pins to function as serial port pins, they must

have their corresponding data direction bits set or

cleared in the associated TRIS register as follows:

• SDI configured as input

• SDO configured as output

• SCK configured as output

DS41418A-page 158

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

19.1.1.3

Master Mode Setup

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is loaded with a byte

value. If the master is only going to receive, SDO output

could be disabled (programmed and used as an input).

The SSPSR register will continue to shift in the signal

present on the SDI pin at the programmed clock rate.

When initializing SPI Master mode operation, several

options need to be specified. This is accomplished by

programming the appropriate control bits in the

SSPCON and SSPSTAT registers. These control bits

allow the following to be specified:

• SCK as clock output

• Idle state of SCK (CKP bit)

• Data input sample phase (SMP bit)

• Output data on rising/falling edge of SCK (CKE bit)

• Clock bit rate

In Master mode, the SPI clock rate (bit rate) is user

selectable to be one of the following:

• FOSC/4 (or TCY)

• FOSC/16 (or 4  TCY)

• FOSC/64 (or 16  TCY)

• (Timer2 output)/2

This allows

a maximum data rate of 5 Mbps

(at FOSC = 20 MHz).

Figure 19-3 shows the waveforms for Master mode.

The clock polarity is selected by appropriately program-

ming the CKP bit of the SSPCON register. When the

CKE bit is set, the SDO data is valid before there is a

clock edge on SCK. The sample time of the input data

is shown based on the state of the SMP bit and can

occur at the middle or end of the data output time. The

time when the SSPBUF is loaded with the received

data is shown.

19.1.1.4

Sleep in Master Mode

In Master mode, all module clocks are halted and the

transmission/reception will remain in their current state,

paused, until the device wakes from Sleep. After the

device wakes up from Sleep, the module will continue

to transmit/receive data.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 159

PIC16F707/PIC16LF707

FIGURE 19-3:

SPI MASTER MODE WAVEFORM

Write to

SSPBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 Clock

Modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

SDO

(CKE = 0)

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

bit 7

bit 3

SDO

(CKE = 1)

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit 0

bit 7

Input

Sample

(SMP = 1)

SSPIF

SSPSR to

SSPBUF

EXAMPLE 19-1:

LOADING THE SSPBUF (SSPSR) REGISTER

BANKSEL

SSPSTAT

;

LOOP

BTFSS

GOTO

SSPSTAT, BF ;Has data been received(transmit complete)?

LOOP

;No

BANKSEL

MOVF

MOVWF

MOVF

SSPBUF

SSPBUF, W

RXDATA

TXDATA, W

SSPBUF

;

;WREG reg = contents of SSPBUF

;Save in user RAM, if data is meaningful

;W reg = contents of TXDATA

;New data to xmit

MOVWF

DS41418A-page 160

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

19.1.2

SLAVE MODE

19.1.2.2

Enabling Slave I/O

For any SPI device acting as a slave, the data is

transmitted and received as external clock pulses

appear on the SCK pin. This external clock must meet

the minimum high and low times as specified in the

electrical specifications.

To enable the serial port, the SSPEN bit of the

SSPCON register must be set. If a Slave mode of

operation is selected in the SSPM bits of the SSPCON

register, the SDI, SDO and SCK pins will be assigned

as serial port pins.

For these pins to function as serial port pins, they must

have their corresponding data direction bits set or

cleared in the associated TRIS register as follows:

19.1.2.1

Slave Mode Operation

The SSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready.

• SDI configured as input

• SDO configured as output

• SCK configured as input

Optionally, a fourth pin, Slave Select (SS) may be used

in Slave mode. Slave Select may be configured to

operate on one of the following pins via the SSSEL bit in

the APFCON register.

The slave has no control as to when data will be

clocked in or out of the device. All data that is to be

transmitted, to a master or another slave, must be

loaded into the SSPBUF register before the first clock

pulse is received.

• RA5/AN4/SS

• RA0/AN0/SS

Once eight bits of data have been received:

• Received byte is moved to the SSPBUF register

• BF bit of the SSPSTAT register is set

• SSPIF bit of the PIR1 register is set

Upon selection of a Slave Select pin, the appropriate

bits must be set in the ANSELA and TRISA registers.

Slave Select must be set as an input by setting the

corresponding bit in TRISA, and digital I/O must be

enabled on the SS pin by clearing the corresponding bit

of the ANSELA register.

Any write to the SSPBUF register during transmission/

reception of data will be ignored and the Write Collision

Detect bit, WCOL of the SSPCON register, will be set.

User software must clear the WCOL bit so that it can be

determined if the following write(s) to the SSPBUF

register completed successfully.

19.1.2.3

Slave Mode Setup

When initializing the SSP module to SPI Slave mode,

compatibility must be ensured with the master device.

This is done by programming the appropriate control

bits of the SSPCON and SSPSTAT registers. These

control bits allow the following to be specified:

The user’s firmware must read SSPBUF, clearing the

BF flag, or the SSPOV bit of the SSPCON register will

be set with the reception of the next byte and

communication will be disabled.

• SCK as clock input

A SPI module transmits and receives at the same time,

occasionally causing dummy data to be transmitted/

received. It is up to the user to determine which data is

to be used and what can be discarded.

• Idle state of SCK (CKP bit)

• Data input sample phase (SMP bit)

• Output data on rising/falling edge of SCK (CKE bit)

Figure 19-4 and Figure 19-5 show example waveforms

of Slave mode operation.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 161

PIC16F707/PIC16LF707

FIGURE 19-4:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS

Optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

bit 3

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

SSPSR to

SSPBUF

FIGURE 19-5:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS

Not Optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPBUF

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

bit 3

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

SSPSR to

SSPBUF

DS41418A-page 162

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

When the SPI module resets, the bit counter is cleared

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit. Figure 19-6

shows the timing waveform for such a synchronization

event.

19.1.2.4

Slave Select Operation

The SS pin allows Synchronous Slave mode operation.

The SPI must be in Slave mode with SS pin control

enabled (SSPM<3:0> = 0100). The associated TRIS bit

for the SS pin must be set, making SS an input.

Note:

SSPSR must be reinitialized by writing to

the SSPBUF register before the data can

be clocked out of the slave again.

In Slave Select mode, when:

• SS = 0, The device operates as specified in

Section 19.1.2 “Slave Mode”.

• SS = 1, The SPI module is held in Reset and the

SDO pin will be tri-stated.

19.1.2.5

Sleep in Slave Mode

While in Sleep mode, the slave can transmit/receive

data. The SPI Transmit/Receive Shift register operates

asynchronously to the device on the externally supplied

clock source. This allows the device to be placed in

Sleep mode and data to be shifted into the SPI Trans-

mit/Receive Shift register. When all 8 bits have been

received, the SSP interrupt flag bit will be set and if

enabled, will wake the device from Sleep.

Note 1: When the SPI is in Slave mode with SS pin

control enabled (SSPM<3:0> = 0100), the

SPI module will reset if the SS pin is driven

high.

2: If the SPI is used in Slave mode with CKE

set, the SS pin control must be enabled.

FIGURE 19-6:

SLAVE SELECT SYNCHRONIZATION WAVEFORM

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

SSPSR must be reinitialized by writing to

the SSPBUF register before the data can

be clocked out of the slave again.

bit 6

bit 7

bit 0

SDO

bit 7

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

SSPSR to

SSPBUF

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 163

PIC16F707/PIC16LF707

REGISTER 19-1: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

WCOL: Write Collision Detect bit

1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in

software)

0= No collision

bit 6

SSPOV: Receive Overflow Indicator bit

1= A new byte is received while the SSPBUF register is still holding the previous data. In case of

overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read

the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the over-

flow bit is not set since each new reception (and transmission) is initiated by writing to the

SSPBUF register.

0= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit

1= Enables serial port and configures SCK, SDO and SDI as serial port pins⁽¹⁾

0= Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level

0= Idle state for clock is a low level

bit 3-0

SSPM<3:0>: Synchronous Serial Port Mode Select bits

0000= SPI Master mode, clock = FOSC/4

0001= SPI Master mode, clock = FOSC/16

0010= SPI Master mode, clock = FOSC/64

0011= SPI Master mode, clock = TMR2 output/2

0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.

0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.

Note 1: When enabled, these pins must be properly configured as input or output.

DS41418A-page 164

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 19-2: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (SPI MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

SMP: SPI Data Input Sample Phase bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

CKE: SPI Clock Edge Select bit

SPI mode, CKP = 0:

1= Data stable on rising edge of SCK

0= Data stable on falling edge of SCK

SPI mode, CKP = 1:

1= Data stable on falling edge of SCK

0= Data stable on rising edge of SCK

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

D/A: Data/Address bit

Used in I²C mode only.

P: Stop bit

Used in I²C mode only.

S: Start bit

Used in I²C mode only.

R/W: Read/Write Information bit

Used in I²C mode only.

UA: Update Address bit

Used in I²C mode only.

BF: Buffer Full Status bit

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 165

PIC16F707/PIC16LF707

TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Value on

POR, BOR

Value on all

other Resets

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

APFCON

INTCON

PIE1

ANSA7

—

ANSA6

—

ANSA5

—

ANSA4

—

ANSA3

—

ANSA2

—

ANSA1

SSSEL

INTF

ANSA0

CCP2SEL

RBIF

1111 1111

---- --00

0000 000x

0000 0000

1111 1111

---- --00

0000 000x

0000 0000

GIE

PEIE

ADIE

TMR0IE

RCIE

INTE

TXIE

RBIE

SSPIE

TMR0IF

CCP1IE

TMR1GIE

TMR2IE

TMR1IE

PIR1

TMR1GIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

PR2

Timer2 Period Register

Synchronous Serial Port Receive Buffer/Transmit Register

1111 1111

xxxx xxxx

0000 0000

1111 1111

-000 0000

1111 1111

uuuu uuuu

0000 0000

1111 1111

-000 0000

SSPBUF

SSPCON

SSPSTAT

TRISA

WCOL

SMP

SSPOV

CKE

SSPEN

D/A

CKP

P

SSPM3

S

SSPM2

R/W

SSPM1

UA

SSPM0

BF

TRISA7

TRISC7

—

TRISA6

TRISC6

TRISA5

TRISC5

TRISA4

TRISC4

TRISA3

TRISC3

TRISA2

TRISC2

TRISA1

TRISC1

TRISA0

TRISC0

TRISC

T2CON

Legend:

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

x= unknown, u= unchanged, –= unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.

DS41418A-page 166

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

2

FIGURE 19-8:

TYPICAL I²C™

CONNECTIONS

19.2 I C Mode

The SSP module, in I²C mode, implements all slave

functions, except general call support. It provides

interrupts on Start and Stop bits in hardware to facilitate

firmware implementations of the master functions. The

SSP module implements the I²C Standard mode

specifications:

VDD VDD

Slave 1

Master

SDA

• I²C Slave mode (7-bit address)

• I²C Slave mode (10-bit address)

SDA

SCL

• Start and Stop bit interrupts enabled to support

firmware Master mode

Slave 2

• Address masking

SDA

Two pins are used for data transfer; the SCL pin (clock

line) and the SDA pin (data line). The user must

configure the two pin’s data direction bits as inputs in

the appropriate TRIS register. Upon enabling I²C

mode, the I²C slew rate limiters in the I/O pads are

controlled by the SMP bit of the SSPSTAT register. The

SSP module functions are enabled by setting the

SSPEN bit of the SSPCON register.

SCL

(optional)

The SSP module has six registers for I²C operation.

They are:

• SSP Control (SSPCON) register

Data is sampled on the rising edge and shifted out on

the falling edge of the clock. This ensures that the SDA

signal is valid during the SCL high time. The SCL clock

input must have minimum high and low times for proper

operation. Refer to Section 25.0 “Electrical

Specifications”.

• SSP Status (SSPSTAT) register

• Serial Receive/Transmit Buffer (SSPBUF) register

• SSP Shift Register (SSPSR), not directly

accessible

• SSP Address (SSPADD) register

• SSP Address Mask (SSPMSK) register

FIGURE 19-7:

I²C™ MODE BLOCK

DIAGRAM

19.2.1

HARDWARE SETUP

Selection of I²C mode, with the SSPEN bit of the

SSPCON register set, forces the SCL and SDA pins to

be open drain, provided these pins are programmed as

inputs by setting the appropriate TRISC bits. The SSP

module will override the input state with the output

data, when required, such as for Acknowledge and

slave-transmitter sequences.

Internal

Data Bus

Read

Write

SSPBUF Reg

SCL

SDA

Shift

Clock

Note:

Pull-up resistors must be provided

externally to the SCL and SDA pins for

proper operation of the I²C module.

SSPSR Reg

MSb

LSb

SSPMSK Reg

Match Detect

SSPADD Reg

Addr Match

Start and

Stop bit Detect

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 167

PIC16F707/PIC16LF707

Figure 19-9 shows the Start and Stop conditions. A

master device generates these conditions for starting

and terminating data transfer. Due to the definition of

the Start and Stop conditions, when data is being trans-

mitted, the SDA line can only change state when the

SCL line is low.

19.2.2

START AND STOP CONDITIONS

During times of no data transfer (Idle time), both the

clock line (SCL) and the data line (SDA) are pulled high

through external pull-up resistors. The Start and Stop

conditions determine the start and stop of data trans-

mission. The Start condition is defined as a high-to-low

transition of the SDA line while SCL is high. The Stop

condition is defined as a low-to-high transition of the

SDA line while SCL is high.

FIGURE 19-9:

START AND STOP CONDITIONS

SDA

SCL

S

P

Change of

Data Allowed

Start

Data Allowed

Stop

Condition

In such a case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF of the PIR1 register is

set. Table 19-2 shows the results of when a data

transfer byte is received, given the status of bits BF and

SSPOV. Flag bit BF is cleared by reading the SSPBUF

register, while bit SSPOV is cleared through software.

19.2.3

ACKNOWLEDGE

After the valid reception of an address or data byte, the

hardware automatically will generate the Acknowledge

(ACK) pulse and load the SSPBUF register with the

received value currently in the SSPSR register. There

are certain conditions that will cause the SSP module

not to generate this ACK pulse. They include any or all

of the following:

• The Buffer Full bit, BF of the SSPSTAT register,

was set before the transfer was received.

• The SSP Overflow bit, SSPOV of the SSPCON

register, was set before the transfer was received.

• The SSP Module is being operated in Firmware

Master mode.

TABLE 19-2: DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

Generate ACK

Transfer is Received

SSPSR  SSPBUF

Pulse

BF

SSPOV

0

1

Yes

No

Yes

No

Yes

1

0

Note:

Shaded cells show the conditions where the user software did not properly clear the overflow condition.

DS41418A-page 168

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

The sequence of events for 10-bit address is as follows

for reception:

19.2.4

ADDRESSING

Once the SSP module has been enabled, it waits for a

Start condition to occur. Following the Start condition,

the 8 bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock line (SCL).

1. Load SSPADD register with high byte of address.

2. Receive first (high) byte of address (bits SSPIF,

BF and UA of the SSPSTAT register are set).

3. Read the SSPBUF register (clears bit BF).

4. Clear the SSPIF flag bit.

19.2.4.1

7-bit Addressing

5. Update the SSPADD register with second (low)

byte of address (clears UA bit and releases the

SCL line).

In 7-bit Addressing mode (Figure 19-10), the value of

register SSPSR<7:1> is compared to the value of

register SSPADD<7:1>. The address is compared on

the falling edge of the eighth clock (SCL) pulse. If the

addresses match, and the BF and SSPOV bits are

clear, the following events occur:

6. Receive low byte of address (bits SSPIF, BF and

UA are set).

7. Update the SSPADD register with the high byte

of address. If match releases SCL line, this will

clear bit UA.

• The SSPSR register value is loaded into the

SSPBUF register.

8. Read the SSPBUF register (clears bit BF).

9. Clear flag bit SSPIF.

• The BF bit is set.

• An ACK pulse is generated.

If data is requested by the master, once the slave has

been addressed:

• SSP interrupt flag bit, SSPIF of the PIR1 register,

is set (interrupt is generated if enabled) on the

falling edge of the ninth SCL pulse.

1. Receive repeated Start condition.

2. Receive repeat of high byte address with R/W = 1,

19.2.4.2

10-bit Addressing

indicating a read.

In 10-bit Address mode, two address bytes need to be

received by the slave (Figure 19-11). The five Most Sig-

nificant bits (MSbs) of the first address byte specify if it

is a 10-bit address. The R/W bit of the SSPSTAT regis-

ter must specify a write so the slave device will receive

the second address byte. For a 10-bit address, the first

byte would equal ‘1111 0 A9 A8 0’, where A9 and

A8 are the two MSbs of the address.

3. BF bit is set and the CKP bit is cleared, stopping

SCL and indicating a read request.

4. SSPBUF is written, setting BF, with the data to

send to the master device.

5. CKP is set in software, releasing the SCL line.

19.2.4.3

Address Masking

The Address Masking register (SSPMSK) is only

accessible while the SSPM bits of the SSPCON

register are set to ‘1001’. In this register, the user can

select which bits of a received address the hardware

will compare when determining an address match. Any

bit that is set to a zero in the SSPMSK register, the

corresponding bit in the received address byte and

SSPADD register are ignored when determining an

address match. By default, the register is set to all

ones, requiring a complete match of a 7-bit address or

the lower eight bits of a 10-bit address.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 169

PIC16F707/PIC16LF707

19.2.5

RECEPTION

When the R/W bit of the received address byte is clear,

the master will write data to the slave. If an address

match occurs, the received address is loaded into the

SSPBUF register. An address byte overflow will occur

if that loaded address is not read from the SSPBUF

before the next complete byte is received.

An SSP interrupt is generated for each data transfer byte.

The BF, R/W and D/A bits of the SSPSTAT register are

used to determine the status of the last received byte.

FIGURE 19-10:

I²C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

R/W = 0

ACK

Receiving Address

A7 A6 A5 A4 A3 A2

Receiving Data

ACK

9

ACK

9

SDA

A1

7

D2 D1 D0

D4

D3

D7 D6 D5 D4 D3 D2 D1 D0

D7

1

D6 D5

1

2

3

4

5

6

8

9

1

2

3

4

5

6

7

8

2

3

4

5

6

7

8

P

SCL

S

SSPIF

Cleared in software

Bus Master

sends Stop

condition

BF

SSPBUF register is read

SSPOV

Bit SSPOV is set because the SSPBUF register is still full.

ACK is not sent.

DS41418A-page 170

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 19-11:

I²C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 171

PIC16F707/PIC16LF707

Following the 8th falling clock edge, control of the SDA

line is released back to the master so that the master

can acknowledge or not acknowledge the response. If

the master sends a not acknowledge, the slave’s

transmission is complete and the slave must monitor for

the next Start condition. If the master acknowledges,

control of the bus is returned to the slave to transmit

another byte of data. Just as with the previous byte, the

clock is stretched by the slave, data must be loaded into

the SSPBUF and CKP must be set to release the clock

line (SCL).

19.2.6

TRANSMISSION

When the R/W bit of the received address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set and the slave will respond to

the master by reading out data. After the address match,

an ACK pulse is generated by the slave hardware and

the SCL pin is held low (clock is automatically stretched)

until the slave is ready to respond. See Section 19.2.7

“Clock Stretching”. The data the slave will transmit

must be loaded into the SSPBUF register, which sets

the BF bit. The SCL line is released by setting the CKP

bit of the SSPCON register.

An SSP interrupt is generated for each transferred data

byte. The SSPIF flag bit of the PIR1 register initiates an

SSP interrupt, and must be cleared by software before

the next byte is transmitted. The BF bit of the SSPSTAT

register is cleared on the falling edge of the 8th

received clock pulse. The SSPIF flag bit is set on the

falling edge of the ninth clock pulse.

FIGURE 19-12:

I²C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

Receiving Address

A7 A6 A5 A4 A3 A2 A1

R/W

Transmitting Data

ACK

9

SDA

SCL

ACK

D7 D6 D5 D4 D3 D2 D1 D0

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

S

P

SCL held low

while CPU

responds to SSPIF

Data in

sampled

Cleared in software

SSPIF

BF

Dummy read of SSPBUF

to clear BF flag

From SSP Interrupt

Service Routine

SSPBUF is written in software

CKP

Set bit after writing to SSPBUF

(the SSPBUF must be written to

before the CKP bit can be set)

DS41418A-page 172

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

2

FIGURE 19-13:

I C™ SLAVE MODE TIMING (TRANSMISSION 10-BIT ADDRESS)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 173

PIC16F707/PIC16LF707

Refer to Application Note AN554, “Software

Implementation of I²C™ Bus Master” (DS00554) for more

information.

19.2.7

CLOCK STRETCHING

During any SCL low phase, any device on the I²C bus

may hold the SCL line low and delay, or pause, the

transmission of data. This “stretching” of a transmission

allows devices to slow down communication on the

bus. The SCL line must be constantly sampled by the

master to ensure that all devices on the bus have

released SCL for more data.

19.2.9

MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allow the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the SSP

module is disabled. The Stop (P) and Start (S) bits will

toggle based on the Start and Stop conditions. Control

of the I²C bus may be taken when the P bit of the

SSPSTAT register is set or when the bus is Idle, and

both the S and P bits are clear. When the bus is busy,

enabling the SSP interrupt will generate the interrupt

when the Stop condition occurs.

Stretching usually occurs after an ACK bit of a

transmission, delaying the first bit of the next byte. The

SSP module hardware automatically stretches for two

conditions:

• After a 10-bit address byte is received (update

SSPADD register)

• Anytime the CKP bit of the SSPCON register is

cleared by hardware

In Multi-Master operation, the SDA line must be moni-

tored to see if the signal level is the expected output

level. This check only needs to be done when a high

level is output. If a high level is expected and a low level

is present, the device needs to release the SDA and

SCL lines (set TRIS bits). There are two stages where

this arbitration of the bus can be lost. They are the

Address Transfer and Data Transfer stages.

The module will hold SCL low until the CKP bit is set.

This allows the user slave software to update SSPBUF

with data that may not be readily available. In 10-bit

addressing modes, the SSPADD register must be

updated after receiving the first and second address

bytes. The SSP module will hold the SCL line low until

the SSPADD has a byte written to it. The UA bit of the

SSPSTAT register will be set, along with SSPIF,

indicating an address update is needed.

When the slave logic is enabled, the slave continues to

receive. If arbitration was lost during the address

transfer stage, communication to the device may be in

progress. If addressed, an ACK pulse will be

generated. If arbitration was lost during the data

transfer stage, the device will need to re-transfer the

data at a later time.

19.2.8

FIRMWARE MASTER MODE

Master mode of operation is supported in firmware

using interrupt generation on the detection of the Start

and Stop conditions. The Stop (P) and Start (S) bits of

the SSPSTAT register are cleared from a Reset or

when the SSP module is disabled (SSPEN cleared).

The Stop (P) and Start (S) bits will toggle based on the

Start and Stop conditions. Control of the I²C bus may

be taken when the P bit is set or the bus is Idle and both

the S and P bits are clear.

Refer to Application Note AN578, “Use of the SSP

Module in the I²C™ Multi-Master Environment”

(DS00578) for more information.

In Firmware Master mode, the SCL and SDA lines are

manipulated by setting/clearing the corresponding TRIS

bit(s). The output level is always low, irrespective of the

value(s) in the corresponding PORT register bit(s).

When transmitting a ‘1’, the TRIS bit must be set (input)

and a ‘0’, the TRIS bit must be clear (output).

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP Interrupt will occur if

enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

Firmware Master mode of operation can be done with

either the Slave mode Idle (SSPM<3:0> = 1011), or

with either of the Slave modes in which interrupts are

enabled. When both master and slave functionality is

enabled, the software needs to differentiate the

source(s) of the interrupt.

DS41418A-page 174

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

19.2.10 CLOCK SYNCHRONIZATION

19.2.11 SLEEP OPERATION

When the CKP bit is cleared, the SCL output is held

low once it is sampled low. Therefore, the CKP bit will

not stretch the SCL line until an external I²C master

device has already asserted the SCL line low. The

SCL output will remain low until the CKP bit is set and

all other devices on the I²C bus have released SCL.

This ensures that a write to the CKP bit will not violate

the minimum high time requirement for SCL

(Figure 19-14).

While in Sleep mode, the I²C module can receive

addresses of data, and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if SSP interrupt is enabled).

FIGURE 19-14:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX-1

Master device

asserts clock

CKP

Master device

deasserts clock

WR

SSPCON

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 175

PIC16F707/PIC16LF707

REGISTER 19-3: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I²C MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

WCOL: Write Collision Detect bit

1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in

software)

0= No collision

bit 6

SSPOV: Receive Overflow Indicator bit

1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t

care” in Transmit mode. SSPOV must be cleared in software in either mode.

0= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit

1= Enables the serial port and configures the SDA and SCL pins as serial port pins⁽²⁾

0= Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

1= Release control of SCL

0= Holds clock low (clock stretch). (Used to ensure data setup time.)

bit 3-0

SSPM<3:0>: Synchronous Serial Port Mode Select bits

0110= I²C Slave mode, 7-bit address

0111= I²C Slave mode, 10-bit address

1000= Reserved

1001= Load SSPMSK register at SSPADD SFR Address⁽¹⁾

1010= Reserved

1011= I²C Firmware Controlled Master mode (Slave Idle)

1100= Reserved

1101= Reserved

1110= I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1111= I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

Note 1: When this mode is selected, any reads or writes to the SSPADD SFR address accesses the SSPMSK register.

2: When enabled, these pins must be properly configured as input or output using the associated TRIS bit.

DS41418A-page 176

Preliminary

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PIC16F707/PIC16LF707

REGISTER 19-4: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (I²C MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

SMP: SPI Data Input Sample Phase bit

1= Slew Rate Control (limiting) disabled. Operating in I²C Standard mode (100 kHz and 1 MHz).

0= Slew Rate Control (limiting) enabled. Operating in I²C Fast mode (400 kHz).

bit 6

bit 5

CKE: SPI Clock Edge Select bit

This bit must be maintained clear. Used in SPI mode only.

D/A: DATA/ADDRESS bit (I²C mode only)

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

bit 4

bit 3

bit 2

P: Stop bit

This bit is cleared when the SSP module is disabled, or when the Start bit is detected last.

1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)

0= Stop bit was not detected last

S: Start bit

This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.

1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)

0= Start bit was not detected last

R/W: READ/WRITE bit Information

This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next Start bit, Stop bit or ACK bit.

1= Read

0= Write

bit 1

bit 0

UA: Update Address bit (10-bit I²C mode only)

1= Indicates that the user needs to update the address in the SSPADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

Receive:

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

Transmit:

1= Transmit in progress, SSPBUF is full

0= Transmit complete, SSPBUF is empty

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 177

PIC16F707/PIC16LF707

REGISTER 19-5: SSPMSK: SSP MASK REGISTER

R/W-1

MSK7

R/W-1

MSK6

R/W-1

MSK5

R/W-1

MSK4

R/W-1

MSK3

R/W-1

MSK2

R/W-1

MSK1

R/W-1

MSK0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-1

bit 0

MSK<7:1>: Mask bits

1= The received address bit n is compared to SSPADD<n> to detect I²C address match

0= The received address bit n is not used to detect I²C address match

MSK<0>: Mask bit for I²C Slave Mode, 10-bit Address

I²C Slave Mode, 10-bit Address (SSPM<3:0> = 0111):

1= The received address bit ‘0’ is compared to SSPADD<0> to detect I²C address match

0= The received address bit ‘0’ is not used to detect I²C address match

All other SSP modes: this bit has no effect.

REGISTER 19-6: SSPADD: SSP I²C™ ADDRESS REGISTER

R/W-0

ADD7

R/W-0

ADD6

R/W-0

ADD5

R/W-0

ADD4

R/W-0

ADD3

R/W-0

ADD2

R/W-0

ADD1

R/W-0

ADD0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

ADD<7:0>: Address bits

Received address

TABLE 19-3: REGISTERS ASSOCIATED WITH I²C™ OPERATION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE

PEIE

ADIF

ADIE

TMR0IE

RCIF

INTE

TXIF

TXIE

RBIE

TMR0IF

INTF

RBIF

0000 000x 0000 000u

TMR1GIF

TMR1GIE

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIE1

RCIE

SSPBUF

SSPADD

SSPCON

SSPMSK

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

2

Synchronous Serial Port (I C mode) Address Register

WCOL

SSPOV SSPEN

CKP

SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

(2)

2

Synchronous Serial Port (I C mode) Address Mask Register

1111 1111 1111 1111

0000 0000 0000 0000

(1)

SSPSTAT

TRISC

SMP

CKE

D/A

P

S

R/W

UA

BF

TRISC7

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend:

x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in

2

I C mode.

2

Note 1: Maintain these bits clear in I C mode.

2: Accessible only when SSPM<3:0> = 1001.

DS41418A-page 178

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

The value written to the PMADRH:PMADRL register

pair determines which program memory location is

read. The read operation will be initiated by setting the

RD bit of the PMCON1 register. The program memory

flash controller takes two instructions to complete the

read. As a consequence, after the RD bit has been set,

the next two instructions will be ignored. To avoid

conflict with program execution, it is recommended that

the two instructions following the setting of the RD bit

are NOP. When the read completes, the result is placed

in the PMDATLH:PMDATL register pair. Refer to

Example 20-1 for sample code.

20.0 PROGRAM MEMORY READ

The Flash program memory is readable during normal

operation over the full VDD range of the device. To read

data from Program Memory, five Special Function

Registers (SFRs) are used:

• PMCON1

• PMDATL

• PMDATH

• PMADRL

• PMADRH

Note:

Code-protect does not effect the CPU

from performing a read operation on the

program memory. For more information,

refer to Section 8.2 “Code Protection”

EXAMPLE 20-1:

PROGRAM MEMORY READ

BANKSEL PMADRL

;

MOVF

MS_PROG_ADDR, W;

MOVWF

MOVF

MOVWF

PMADRH

LS_PROG_ADDR, W;

PMADRL ;LS Byte of Program Address to read

;MS Byte of Program Address to read

BANKSEL PMCON1

;

BSF

NOP

PMCON1, RD

;Initiate Read

;Any instructions here are ignored as program

;memory is read in second cycle after BSF

BANKSEL PMDATL

;

MOVF

PMDATL, W

;W = LS Byte of Program Memory Read

MOVWF

MOVF

MOVWF

LOWPMBYTE

PMDATH, W

HIGHPMBYTE

;

;W = MS Byte of Program Memory Read

;

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 179

PIC16F707/PIC16LF707

REGISTER 20-1: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

U-1

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/S-0

RD

bit 7

bit 0

Legend:

S = Setable bit, cleared in hardware

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented: Read as ‘1’

Unimplemented: Read as ‘0’

RD: Read Control bit

bit 6-1

bit 0

1= Initiates a program memory read (The RD is cleared in hardware; the RD bit can only be set (not

cleared) in software).

0= Does not initiate a program memory read

REGISTER 20-2: PMDATH: PROGRAM MEMORY DATA HIGH REGISTER

U-0

—

U-0

—

R/W-x

PMD9

R/W-x

PMD8

PMD13

PMD12

PMD11

PMD10

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL after a

program memory read command.

REGISTER 20-3: PMDATL: PROGRAM MEMORY DATA LOW REGISTER

R/W-x

PMD7

R/W-x

PMD6

R/W-x

PMD5

R/W-x

PMD4

R/W-x

PMD3

R/W-x

PMD2

R/W-x

PMD1

R/W-x

PMD0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

PMD<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after a

program memory read command.

DS41418A-page 180

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

REGISTER 20-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH REGISTER

U-0

—

U-0

—

U-0

—

R/W-x

PMA9

R/W-x

PMA8

PMA12

PMA11

PMA10

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

PMA<12:8>: Program Memory Read Address bits

REGISTER 20-5: PMADRL: PROGRAM MEMORY ADDRESS LOW REGISTER

R/W-x

PMA7

R/W-x

PMA6

R/W-x

PMA5

R/W-x

PMA4

R/W-x

PMA3

R/W-x

PMA2

R/W-x

PMA1

R/W-x

PMA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

PMA<7:0>: Program Memory Read Address bits

TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY READ

Value on

POR, BOR

Value on all

other Resets

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PMCON1

PMADRH

PMADRL

PMDATH

PMDATL

Legend:

—

RD

1--- ---0

---x xxxx

xxxx xxxx

--xx xxxx

xxxx xxxx

Program Memory Read Address Register High Byte ---x xxxx

Program Memory Read Address Register Low Byte

xxxx xxxx

--xx xxxx

xxxx xxxx

—

Program Memory Read Data Register High Byte

Program Memory Read Data Register Low Byte

x= unknown, u= unchanged, –= unimplemented, read as ‘0’. Shaded cells are not used by the program memory read.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 181

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 182

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

21.1 Wake-up from Sleep

21.0 POWER-DOWN MODE (SLEEP)

The device can wake-up from Sleep through one of the

following events:

The Power-down mode is entered by executing a

SLEEPinstruction.

1. External Reset input on MCLR pin, if enabled

2. BOR Reset, if enabled

Upon entering Sleep mode, the following conditions

exist:

3. POR Reset

1. WDT will be cleared but keeps running, if

enabled.

4. Watchdog Timer, if enabled

5. Any external interrupt

2. PD bit of the STATUS register is cleared.

3. TO bit of the STATUS register is set.

4. CPU clock is disabled.

6. Interrupts by peripherals capable of running

during Sleep (see individual peripheral for more

information)

5. 31 kHz LFINTOSC is unaffected and peripherals

that operate from it may continue operation in

Sleep.

The first three events will cause a device Reset. The

last three events are considered a continuation of

program execution.

6. Timer1/3 oscillator is unaffected and peripherals

that operate from it may continue operation in

Sleep.

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be enabled. Wake-up will

occur regardless of the state of the GIE bit. If the GIE

bit is disabled, the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

enabled, the device executes the instruction after the

SLEEP instruction, the device will call the Interrupt

Service Routine. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOPafter the SLEEPinstruction.

7. ADC is unaffected, if the dedicated FRC clock is

selected.

8. Capacitive Sensing oscillators are unaffected.

9. I/O ports maintain the status they had before

SLEEPwas executed (driving high, low or high-

impedance).

10. Resets other than WDT are not affected by

Sleep mode.

Refer to individual chapters for more details on

peripheral operation during Sleep.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

To minimize current consumption, the following

conditions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• Modules using Timer1/3 oscillator

I/O pins that are high-impedance inputs should be

pulled to VDD or VSS externally to avoid switching cur-

rents caused by floating inputs.

Examples of internal circuitry that might be sourcing

current include modules such as the DAC and FVR

modules. See Section 11.0 “Digital-to-Analog Con-

verter (DAC) Module” and Section 10.0 “Fixed Volt-

age Reference” for more information on these

modules.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 183

PIC16F707/PIC16LF707

• If the interrupt occurs during or after the execu-

tion of a SLEEPinstruction

21.1.1

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

- SLEEPinstruction will be completely exe-

cuted

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

- TO bit of the STATUS register will be set

- PD bit of the STATUS register will be cleared.

• If the interrupt occurs before the execution of a

SLEEPinstruction

- SLEEPinstruction will execute as a NOP.

- WDT and WDT prescaler will not be cleared

- TO bit of the STATUS register will not be set

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes.

To determine whether a SLEEP instruction executed,

test the PD bit. If the PD bit is set, the SLEEPinstruction

was executed as a NOP.

- PD bit of the STATUS register will not be

cleared.

FIGURE 21-1:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1⁽¹⁾

(3)

CLKOUT⁽²⁾

TOST

Interrupt Latency⁽⁴⁾

Interrupt flag

GIE bit

(INTCON reg.)

Processor in

Sleep

Instruction Flow

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Fetched

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Instruction

Executed

Dummy Cycle

Sleep

Inst(PC + 1)

Inst(PC - 1)

Inst(0004h)

Note 1:

XT, HS or LP Oscillator mode assumed.

CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.

TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.

GIE = 1assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

2:

3:

4:

TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Value on all

other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

IOCBF

PIE1

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

0000 000x

0000 0000

0000 ---0

0000 0000

0000 ---0

0001 1xxx

0000 000x

0000 0000

0000 ---0

0000 0000

0000 ---0

000q quuu

IOCBF7

TMR1GIE

IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0

ADIE

RCIE

TXIE

SSPIE

—

CCP1IE TMR2IE TMR1IE

CCP2IE

CCP1IF TMR2IF TMR1IF

PIE2

TMR3GIE TMR3IE TMRBIE TMRAIE

TMR1GIF ADIF RCIF TXIF

TMR3GIF TMR3IF TMRBIF TMRAIF

IRP RP1 RP0 TO

—

SSPIF

PIR1

PIR2

—

Z

—

CCP2IF

C

STATUS

Legend:

PD

DC

— = unimplemented location, read as ‘0’. Shaded cells are not used in Power-down mode.

DS41418A-page 184

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

The device is placed into Program/Verify mode by

holding the ICSPCLK and ICSPDAT pins low then

raising the voltage on MCLR/VPP from 0v to VPP. In

Program/Verify mode the program memory, user IDs and

the Configuration Words are programmed through serial

communications. The ICSPDAT pin is a bidirectional I/O

used for transferring the serial data and the ISCPCLK pin

is the clock input. For more information on ICSP™ refer

22.0 IN-CIRCUIT SERIAL

PROGRAMMING™ (ICSP™)

ICSP™ programming allows customers to manufacture

circuit boards with unprogrammed devices. Programming

can be done after the assembly process allowing the

device to be programmed with the most recent firmware

or a custom firmware. Five pins are needed for ICSP™

programming:

to

the

“PIC16F707/PIC16LF707

Programming

Specification” (DS41405A).

• ICSPCLK

• ICSPDAT

• MCLR/VPP

• VDD

Note:

The ICD 2 produces a VPP voltage greater

than the maximum VPP specification of the

PIC16F707/PIC16LF707. When using this

programmer, an external circuit, such as

the AC164112 MPLAB^®ICD 2 VPP volt-

age limiter, is required to keep the VPP

voltage within the device specifications.

• VSS

FIGURE 22-1:

TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

External

Programming

Signals

Device to be

Programmed

VDD

10k

VPP

MCLR/VPP

VSS

GND

Data

ICSPDAT

ICSPCLK

Clock

*

To Normal Connections

Isolation devices (as required).

*

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 185

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 186

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 23-1: OPCODE FIELD

DESCRIPTIONS

23.0 INSTRUCTION SET SUMMARY

The PIC16F707/PIC16LF707 instruction set is highly

orthogonal and is comprised of three basic categories:

Field

Description

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

Bit address within an 8-bit file register

Literal field, constant data or label

k

Each PIC16 instruction is a 14-bit word divided into an

opcode, which specifies the instruction type and one or

more operands, which further specify the operation of

the instruction. The formats for each of the categories

is presented in Figure 23-1, while the various opcode

fields are summarized in Table 23-1.

x

Don’t care location (= 0or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

Table 23-2 lists the instructions recognized by the

MPASM^TMassembler.

For byte-oriented instructions, ‘f’ represents a file

register designator and ‘d’ represents a destination

designator. The file register designator specifies which

file register is to be used by the instruction.

PC

TO

C

Program Counter

Time-out bit

Carry bit

DC

Z

Digit carry bit

Zero bit

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W register. If ‘d’ is one, the result is placed

in the file register specified in the instruction.

PD

Power-down bit

FIGURE 23-1:

GENERAL FORMAT FOR

INSTRUCTIONS

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operation, while ‘f’ represents the address of the file in

which the bit is located.

Byte-oriented file register operations

13

8

7

6

0

For literal and control operations, ‘k’ represents an

8-bit or 11-bit constant, or literal value.

OPCODE

d

f (FILE #)

d = 0for destination W

d = 1for destination f

f = 7-bit file register address

One instruction cycle consists of four oscillator periods;

for an oscillator frequency of 4 MHz, this gives a

nominal instruction execution time of 1 s. All

instructions are executed within a single instruction

cycle, unless a conditional test is true, or the program

counter is changed as a result of an instruction. When

this occurs, the execution takes two instruction cycles,

with the second cycle executed as a NOP.

Bit-oriented file register operations

13 10 9

b (BIT #)

7

6

0

OPCODE

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

Literal and control operations

General

13

8

7

0

23.1 Read-Modify-Write Operations

OPCODE

k (literal)

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

k = 8-bit immediate value

CALLand GOTOinstructions only

13 11 10

OPCODE

k = 11-bit immediate value

k (literal)

For example, a CLRF PORTB instruction will read

PORTB, clear all the data bits, then write the result

back to PORTB. This example would have the unin-

tended consequence of clearing the condition that set

the RBIF flag.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 187

PIC16F707/PIC16LF707

TABLE 23-2: PIC16F707/PIC16LF707 INSTRUCTION SET

14-Bit Opcode

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

1

1(2)

1

1(2)

1

00 0111 dfff ffff C, DC, Z

1, 2

2

00 0101 dfff ffff

00 0001 lfff ffff

00 0001 0xxx xxxx

00 1001 dfff ffff

00 0011 dfff ffff

00 1011 dfff ffff

00 1010 dfff ffff

00 1111 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 lfff ffff

00 0000 0xx0 0000

00 1101 dfff ffff

00 1100 dfff ffff

Z

–

f, d

f

1, 2

1, 2, 3

1, 2

1, 2, 3

1, 2

Z

Move W to f

No Operation

–

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

C

1, 2

00 0010 dfff ffff C, DC, Z

00 1110 dfff ffff

00 0110 dfff ffff

Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

1 (2)

01 00bb bfff ffff

1, 2

3

01 01bb bfff ffff

01 10bb bfff ffff

01 11bb bfff ffff

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

–

k

–

k

–

k

Add literal and W

AND literal with W

Call Subroutine

Clear Watchdog Timer

Go to address

1

2

1

2

1

2

1

11 111x kkkk kkkk C, DC, Z

11 1001 kkkk kkkk

10 0kkk kkkk kkkk

Z

00 0000 0110 0100 TO, PD

10 1kkk kkkk kkkk

Inclusive OR literal with W

Move literal to W

11 1000 kkkk kkkk

11 00xx kkkk kkkk

00 0000 0000 1001

11 01xx kkkk kkkk

00 0000 0000 1000

Z

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

00 0000 0110 0011 TO, PD

11 110x kkkk kkkk C, DC, Z

11 1010 kkkk kkkk

Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

DS41418A-page 188

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

23.2 Instruction Descriptions

BCF

Bit Clear f

ADDLW

Add literal and W

Syntax:

[ label ] BCF f,b

Syntax:

[ label ] ADDLW

0  k  255

k

Operands:

0  f  127

0  b  7

Operands:

Operation:

Status Affected:

Description:

(W) + k  (W)

C, DC, Z

Operation:

0 (f<b>)

Status Affected:

Description:

None

The contents of the W register

are added to the eight-bit literal ‘k’

and the result is placed in the

W register.

Bit ‘b’ in register ‘f’ is cleared.

BSF

Bit Set f

ADDWF

Add W and f

Syntax:

[ label ] BSF f,b

Syntax:

[ label ] ADDWF f,d

Operands:

0  f  127

0  b  7

Operands:

0  f  127

d 0,1

Operation:

1 (f<b>)

Operation:

(W) + (f)  (destination)

Status Affected:

Description:

None

Status Affected: C, DC, Z

Bit ‘b’ in register ‘f’ is set.

Description:

Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back

in register ‘f’.

BTFSC

Bit Test f, Skip if Clear

ANDLW

AND literal with W

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] ANDLW

0  k  255

k

Operands:

0  f  127

0  b  7

Operands:

Operation:

Status Affected:

Description:

(W) .AND. (k)  (W)

Operation:

skip if (f<b>) = 0

Z

Status Affected: None

The contents of W register are

AND’ed with the eight-bit literal

‘k’. The result is placed in the W

register.

Description: If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

If bit ‘b’, in register ‘f’, is ‘0’, the

next instruction is discarded, and

a NOPis executed instead, making

this a 2-cycle instruction.

ANDWF

AND W with f

Syntax:

[ label ] ANDWF f,d

Operands:

0  f  127

d 0,1

Operation:

(W) .AND. (f)  (destination)

Status Affected:

Description:

Z

AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored in

the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 189

PIC16F707/PIC16LF707

CLRWDT

Clear Watchdog Timer

BTFSS

Bit Test f, Skip if Set

Syntax:

[ label ] CLRWDT

Syntax:

[ label ] BTFSS f,b

Operands:

Operation:

None

Operands:

0  f  127

0  b < 7

00h  WDT

0 WDT prescaler,

1 TO

Operation:

skip if (f<b>) = 1

Status Affected: None

1 PD

Description:

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

Status Affected: TO, PD

Description:

CLRWDTinstruction resets the

Watchdog Timer. It also resets the

prescaler of the WDT.

If bit ‘b’ is ‘1’, then the next

instruction is discarded and a NOP

is executed instead, making this a

2-cycle instruction.

Status bits TO and PD are set.

CALL

Call Subroutine

COMF

Complement f

Syntax:

[ label ] CALL k

0  k  2047

Syntax:

[ label ] COMF f,d

Operands:

Operation:

Operands:

0  f  127

d  [0,1]

(PC)+ 1 TOS,

k  PC<10:0>,

(PCLATH<4:3>)  PC<12:11>

Operation:

(f)  (destination)

Status Affected:

Description:

Z

Status Affected: None

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in

register ‘f’.

Description:

Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The eleven-bit

immediate address is loaded into

PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALLis a two-cycle instruction.

CLRF

Clear f

DECF

Decrement f

Syntax:

[ label ] CLRF

0  f  127

f

Syntax:

[ label ] DECF f,d

Operands:

Operation:

Operands:

0  f  127

d  [0,1]

00h  (f)

1 Z

Operation:

(f) - 1  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are

cleared and the Z bit is set.

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

Operation:

None

00h  (W)

1 Z

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z)

is set.

DS41418A-page 190

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

DECFSZ

Decrement f, Skip if 0

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Syntax:

[ label ] INCFSZ f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) - 1  (destination);

skip if result = 0

Operation:

(f) + 1  (destination),

skip if result = 0

Status Affected: None

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, then a NOPis

executed instead, making it a

2-cycle instruction.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, a NOPis executed

instead, making it a 2-cycle

instruction.

GOTO

Unconditional Branch

IORLW

Inclusive OR literal with W

Syntax:

[ label ] GOTO

0  k  2047

k

Syntax:

[ label ] IORLW k

0  k  255

Operands:

Operation:

Status Affected:

Description:

Operation:

k  PC<10:0>

PCLATH<4:3>  PC<12:11>

(W) .OR. k  (W)

Z

Status Affected: None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the

W register.

Description:

GOTOis an unconditional branch.

The eleven-bit immediate value is

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTOis a

two-cycle instruction.

IORWF

Inclusive OR W with f

INCF

Increment f

Syntax:

[ label ] IORWF f,d

Syntax:

[ label ] INCF f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(W) .OR. (f)  (destination)

Operation:

(f) + 1  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Inclusive OR the W register with

register ‘f’. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 191

PIC16F707/PIC16LF707

MOVWF

Move W to f

[ label ] MOVWF

0  f  127

(W)  (f)

MOVF

Move f

Syntax:

f

Syntax:

Operands:

[ label ] MOVF f,d

Operands:

Operation:

Status Affected:

Description:

0  f  127

d  [0,1]

Operation:

(f)  (dest)

None

Status Affected:

Description:

Z

Move data from W register to

register ‘f’.

The contents of register f is

moved to a destination dependent

upon the status of d. If d = 0,

destination is W register. If d = 1,

the destination is file register f

itself. d = 1is useful to test a file

register since status flag Z is

affected.

Words:

1

Cycles:

Example:

MOVW

F

OPTION

Before Instruction

OPTION = 0xFF

Words:

1

W

=

0x4F

After Instruction

Cycles:

Example:

OPTION = 0x4F

W

MOVF

FSR, 0

=

0x4F

After Instruction

W

=

value in FSR

register

Z

=

1

MOVLW

Syntax:

Move literal to W

NOP

No Operation

[ label ] MOVLW k

0  k  255

Syntax:

[ label ] NOP

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

Words:

None

k  (W)

No operation

Status Affected: None

None

Description:

The eight-bit literal ‘k’ is loaded into

W register. The “don’t cares” will

assemble as ‘0’s.

No operation.

1

Cycles:

1

Words:

1

NOP

Example:

Cycles:

Example:

MOVLW

0x5A

After Instruction

W

=

0x5A

DS41418A-page 192

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

RETFIE

Return from Interrupt

[ label ] RETFIE

None

RETLW

Return with literal in W

[ label ] RETLW k

0  k  255

Syntax:

Operands:

Operation:

Operands:

Operation:

TOS  PC,

1 GIE

k  (W);

TOS  PC

Status Affected:

Description:

None

Status Affected:

Description:

None

Return from Interrupt. Stack is

POPed and Top-of-Stack (TOS) is

loaded in the PC. Interrupts are

enabled by setting Global

Interrupt Enable bit, GIE

The W register is loaded with the

eight bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

(INTCON<7>). This is a two-cycle

instruction.

Words:

1

2

Cycles:

Example:

Words:

1

CALL TABLE;W contains

table

Cycles:

Example:

2

RETFIE

;offset value

•

;W now has table value

TABLE

After Interrupt

PC = TOS

GIE =

1

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2

;

•

RETLW kn ; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

RETURN

Return from Subroutine

Syntax:

[ label ] RETURN

None

Operands:

Operation:

TOS  PC

Status Affected: None

Description: Return from subroutine. The stack

is POPed and the top of the stack

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 193

PIC16F707/PIC16LF707

RLF

Rotate Left f through Carry

SLEEP

Enter Sleep mode

[ label ] SLEEP

None

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

0  f  127

d  [0,1]

Operands:

Operation:

00h  WDT,

0 WDT prescaler,

1 TO,

Operation:

See description below

C

Status Affected:

Description:

0 PD

The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

Status Affected:

Description:

TO, PD

The power-down Status bit, PD is

cleared. Time-out Status bit, TO

is set. Watchdog Timer and its

prescaler are cleared.

The processor is put into Sleep

mode with the oscillator stopped.

C

Register f

Words:

1

Cycles:

Example:

RLF

REG1,0

Before Instruction

REG1

C

=

1110 0110

0

After Instruction

REG1

W

C

=

1110 0110

1100 1100

1

SUBLW

Subtract W from literal

RRF

Rotate Right f through Carry

Syntax:

[ label ] SUBLW k

0 k 255

Syntax:

[ label ] RRF f,d

Operands:

Operation:

Operands:

0  f  127

d  [0,1]

k - (W) W)

Operation:

See description below

C

Status Affected: C, DC, Z

Status Affected:

Description:

Description: The W register is subtracted (2’s

complement method) from the

eight-bit literal ‘k’. The result is

placed in the W register.

The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is placed

back in register ‘f’.

C = 0

W  k

C = 1

W  k

DC = 0

DC = 1

W<3:0>  k<3:0>

W<3:0>  k<3:0>

C

Register f

DS41418A-page 194

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

SUBWF

Subtract W from f

XORLW

Exclusive OR literal with W

Syntax:

[ label ] SUBWF f,d

Syntax:

[ label ] XORLW k

0 k 255

Operands:

0 f 127

d  [0,1]

Operands:

Operation:

Status Affected:

Description:

(W) .XOR. k W)

Z

Operation:

(f) - (W) destination)

Status Affected: C, DC, Z

The contents of the W register

are XOR’ed with the eight-bit

literal ‘k’. The result is placed in

the W register.

Description:

Subtract (2’s complement method)

W register from register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f.

C = 0

W  f

C = 1

W  f

DC = 0

DC = 1

W<3:0>  f<3:0>

W<3:0>  f<3:0>

SWAPF

Swap Nibbles in f

XORWF

Exclusive OR W with f

Syntax:

[ label ] SWAPF f,d

Syntax:

[ label ] XORWF f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

Operation:

(W) .XOR. (f) destination)

Status Affected:

Description:

Z

Status Affected: None

Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Description: The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in the W

register. If ‘d’ is ‘1’, the result is

placed in register ‘f’.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 195

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 196

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

24.1 MPLAB Integrated Development

Environment Software

24.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers and dsPIC^®digital signal

controllers are supported with a full range of software

and hardware development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• A single graphical interface to all debugging tools

- Simulator

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- Programmer (sold separately)

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- HI-TECH C for Various Device Families

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Customizable data windows with direct edit of

contents

• Simulators

• High-level source code debugging

• Mouse over variable inspection

- MPLAB SIM Software Simulator

• Emulators

• Drag and drop variables from source to watch

windows

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 197

PIC16F707/PIC16LF707

24.2 MPLAB C Compilers for Various

Device Families

24.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

24.3 HI-TECH C for Various Device

Families

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

24.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor, and one-step driver, and can run on multiple

platforms.

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

24.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• MPLAB IDE compatibility

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

DS41418A-page 198

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

24.7 MPLAB SIM Software Simulator

24.9 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC^®Flash microcon-

trollers and dsPIC^®DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer's PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

24.10 PICkit 3 In-Circuit Debugger/

Programmer and

24.8 MPLAB REAL ICE In-Circuit

Emulator System

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC^®and dsPIC^®Flash microcontrollers at a

most affordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer's PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial Pro-

gramming™.

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC^®Flash MCUs and dsPIC^®Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers signifi-

cant advantages over competitive emulators including

low-cost, full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, a rugge-

dized probe interface and long (up to three meters) inter-

connection cables.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 199

PIC16F707/PIC16LF707

24.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

24.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use inter-

face for programming and debugging Microchip’s Flash

families of microcontrollers. The full featured

Windows^®programming interface supports baseline

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

(PIC10F,

PIC12F5xx,

PIC16F5xx),

midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

Development Environment (IDE) the PICkit™

2

enables in-circuit debugging on most PIC^®microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the application. When halted at a break-

point, the file registers can be examined and modified.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

24.12 MPLAB PM3 Device Programmer

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS41418A-page 200

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

25.0 ELECTRICAL SPECIFICATIONS

(†)

Absolute Maximum Ratings

Ambient temperature under bias....................................................................................................... -40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on VDD with respect to VSS, PIC16F707 ............................................................................... -0.3V to +6.5V

Voltage on VCAP pin with respect to VSS, PIC16F707 ....................................................................... -0.3V to +4.0V

Voltage on VDD with respect to VSS, PIC16LF707 ............................................................................. -0.3V to +4.0V

Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V

Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾...............................................................................................................................800 mW

Maximum current out of VSS pin ...................................................................................................................... 95 mA

Maximum current into VDD pin ......................................................................................................................... 70 mA

Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA

Maximum output current sunk by any I/O pin....................................................................................................25 mA

Maximum output current sourced by any I/O pin .............................................................................................. 25 mA

Maximum current sunk by all ports⁽²⁾, -40°C  TA  +85°C for industrial ........................................................ 200 mA

Maximum current sunk by all ports⁽²⁾, -40°C  TA  +125°C for extended........................................................ 90 mA

Maximum current sourced by all ports⁽²⁾, 40°C  TA  +85°C for industrial ................................................... 140 mA

Maximum current sourced by all ports⁽²⁾, -40°C  TA  +125°C for extended................................................... 65 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for

extended periods may affect device reliability.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 201

PIC16F707/PIC16LF707

25.1 DC Characteristics: PIC16F707/PIC16LF707-I/E (Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

PIC16LF707

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F707

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param.

No.

Sym.

Characteristic

Supply Voltage

Min.

Typ† Max. Units

Conditions

D001

VDD

PIC16LF707

1.8

2.3

2.5

—

3.6

V

FOSC  16 MHz: HFINTOSC, EC

FOSC  4 MHz

FOSC  20 MHz, EC

FOSC  20 MHz, HS

V

D001

PIC16F707

1.8

2.3

2.5

—

5.5

V

FOSC  16 MHz: HFINTOSC, EC

FOSC  4 MHz

FOSC  20 MHz, EC

FOSC  20 MHz, HS

(1)

D002*

VDR

RAM Data Retention Voltage

PIC16LF707

1.5

1.7

—

V

Device in Sleep mode

PIC16F707

VPOR*

Power-on Reset Release Voltage

1.6

VPORR* Power-on Reset Rearm Voltage

PIC16LF707

—

0.8

1.7

—

V

Device in Sleep mode

PIC16F707

D003

VFVR

Fixed Voltage Reference Voltage,

Initial Accuracy

-5.5

—

5.5

%

VFVR = 1.024V, VDD  2.5V

VFVR = 2.048V, VDD  2.5V

VFVR = 4.096V, VDD 4.75V;

-40 TA85°C

-6

—

6

%

VFVR = 1.024V, VDD  2.5V

VFVR = 2.048V, VDD  2.5V

VFVR = 4.096V, VDD 4.75V;

-40 TA125°C

D004*

SVDD

VDD Rise Rate to ensure internal

Power-on Reset signal

0.05

—

V/ms See Section 3.2 “Power-on Reset

(POR)” for details.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

DS41418A-page 202

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 25-1:

POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR

VPORR

VSS

NPOR

POR REARM

VSS

(3)

(2)

TPOR

TVLOW

Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.

3: TVLOW 2.7 s typical.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 203

PIC16F707/PIC16LF707

25.2 DC Characteristics: PIC16F707/PIC16LF707-I/E (Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

PIC16LF707

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F707

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Param

No.

Device

Characteristics

Min.

Typ†

Max.

Units

VDD

Note

(1, 2)

Supply Current (IDD)

LDO Regulator

D009

—

350

—

A

—

HS, EC OR INTOSC/INTOSCIO (8-16 MHZ)

Clock modes with all VCAP pins disabled

—

50

30

5

—

A

—

All VCAP pins disabled

VCAP enabled on RA0, RA5 or RA6

LP Clock mode and Sleep (requires FVR and

BOR to be disabled)

D010

—

7.0

9.0

12

14

A

1.8

3.0

FOSC = 32 kHz

LP Oscillator mode (Note 4),

-40°C  TA  +85°C

—

11

14

20

22

24

12

18

A

1.8

3.0

5.0

1.8

3.0

FOSC = 32 kHz

LP Oscillator mode (Note 4),

-40°C  TA  +85°C

15

D011

7.0

9.0

FOSC = 32 kHz

LP Oscillator mode

-40°C  TA  +125°C

—

11

21

A

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

FOSC = 32 kHz

LP Oscillator mode (Note 4)

-40°C  TA  +125°C

14

25

15

27

D011

110

150

120

180

240

230

400

250

420

500

125

230

150

225

250

150

215

175

250

300

600

350

650

750

180

270

205

320

410

FOSC = 1 MHz

XT Oscillator mode

FOSC = 1 MHz

XT Oscillator mode (Note 5)

D012

FOSC = 4 MHz

XT Oscillator mode

FOSC = 4 MHz

XT Oscillator mode (Note 5)

D013

FOSC = 1 MHz

EC Oscillator mode

FOSC = 1 MHz

EC Oscillator mode (Note 5)

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in k

4: FVR and BOR are disabled.

5: 0.1 F capacitor on VCAP (RA0).

DS41418A-page 204

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

25.2 DC Characteristics: PIC16F707/PIC16LF707-I/E (Industrial, Extended) (Continued)

Standard Operating Conditions (unless otherwise stated)

PIC16LF707

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F707

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Param

No.

Device

Characteristics

Min.

Typ†

Max.

Units

VDD

Note

(1, 2)

Supply Current (IDD)

D014

—

290

460

300

450

500

100

120

115

135

150

650

1000

625

1000

1100

1.0

330

500

430

655

730

130

150

195

200

220

800

1200

850

1200

1500

1.2

A

mA

A

mA

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

3.0

3.6

3.0

5.0

FOSC = 4 MHz

EC Oscillator mode

FOSC = 4 MHz

EC Oscillator mode (Note 5)

D015

FOSC = 500 kHz

MFINTOSC mode

FOSC = 500 kHz

MFINTOSC mode (Note 5)

D016

FOSC = 8 MHz

HFINTOSC mode

FOSC = 8 MHz

HFINTOSC mode (Note 5)

D017

FOSC = 16 MHz

HFINTOSC mode

1.5

1.85

1.2

1

FOSC = 16 MHz

HFINTOSC mode (Note 5)

1.5

1.7

2.1

D018

210

340

225

360

410

1.6

240

380

320

445

650

1.9

FOSC = 4 MHz

EXTRC mode (Note 3, Note 5)

FOSC = 4 MHz

EXTRC mode (Note 3, Note 5)

D019

FOSC = 20 MHz

HS Oscillator mode

2.0

2.8

1.6

2

FOSC = 20 MHz

HS Oscillator mode (Note 5)

1.9

3.2

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in k

4: FVR and BOR are disabled.

5: 0.1 F capacitor on VCAP (RA0).

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 205

PIC16F707/PIC16LF707

25.3 DC Characteristics: PIC16F707/PIC16LF707-I/E (Power-Down)

Standard Operating Conditions (unless otherwise stated)

PIC16LF707

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F707

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Param

No.

Max.

+85°C +125°C

Max.

Device Characteristics

Min.

Typ†

Units

VDD

Note

(2)

Power-down Base Current (IPD)

D020

—

0.02

0.08

4.3

5

0.7

1.0

10.2

10.5

11.8

1.7

2.5

13.5

14.5

16

3.9

4.3

17

A

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

WDT, BOR, FVR, and T1OSC

disabled, all Peripherals Inactive

—

WDT, BOR, FVR, and T1OSC

disabled, all Peripherals Inactive

18

5.5

0.5

0.8

6

21

D021

4.1

4.8

16.4

16.8

18.7

22

LPWDT Current (Note 1)

6.5

7.5

8.5

23

25

26

—

D021A

18

FVR current (Note 1, Note 3)

18

22

44

48

FVR current (Note 1, Note 3,

Note 5)

45

55

60

70

D022

—

BOR Current (Note 1, Note 3)

7.5

—

12

22

—

BOR Current (Note 1, Note 3,

Note 5)

23

25

0.6

1.8

4.5

6

42

49

46

50

D026

3

7

T1OSC Current (Note 1)

6

8.75

—

11.1

12.5

13.5

—

7

—

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.

4: A/D oscillator source is FRC.

5: 0.1 F capacitor on VCAP (RA0).

6: Includes FVR IPD and DAC IPD.

DS41418A-page 206

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

25.3 DC Characteristics: PIC16F707/PIC16LF707-I/E (Power-Down) (Continued)

Standard Operating Conditions (unless otherwise stated)

PIC16LF707

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F707

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Param

No.

Max.

+85°C +125°C

Max.

Device Characteristics

Min.

Typ†

Units

VDD

Note

(2)

Power-down Base Current (IPD)

D027

—

0.06

0.08

6

0.7

1.0

10.7

10.6

11.9

400

430

3.2

4.4

13

5.0

5.5

18

20

22

—

A

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

A/D Current (Note 1, Note 4), no

conversion in progress

—

A/D Current (Note 1, Note 4), no

conversion in progress

7

7.2

250

280

2.2

3.3

6.5

8

D027A

A/D Current (Note 1, Note 4),

conversion in progress

—

A/D Current (Note 1, Note 4,

Note 5), conversion in progress

—

D028

14.4

15.6

21

23

25

17

18

23

24

27

25

44

31

50

58

—

Cap Sense Low Range

Low Power

Cap Sense Low Range

Low Power

14

8

14

D028A

4.2

6

Cap Sense Low Range

Medium Power

7

8.5

11

15.5

17

Cap Sense Low Range

Medium Power

11

18

D028B

12

14

Cap Sense Low Range

High Power

32

35

16

20

Cap Sense Low Range

High Power

36

41

42

49

D028C

115

120

135

140

150

125

130

—

Cap Sense HighRange

Low Power (Note 6)

—

Cap Sense High Range

Low Power (Note 6)

—

D028D

—

Cap Sense HighRange

Medium Power (Note 6)

—

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.

4: A/D oscillator source is FRC.

5: 0.1 F capacitor on VCAP (RA0).

6: Includes FVR IPD and DAC IPD.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 207

PIC16F707/PIC16LF707

25.3 DC Characteristics: PIC16F707/PIC16LF707-I/E (Power-Down) (Continued)

Standard Operating Conditions (unless otherwise stated)

PIC16LF707

PIC16F707

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Param

No.

Max.

+85°C +125°C

Max.

Device Characteristics

Min.

Typ†

Units

VDD

Note

D028D

—

145

150

160

150

170

180

190

200

—

A

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

Cap Sense High Range

Medium Power (Note 6)

D028E

Cap Sense HighRange

High Power (Note 6)

Cap Sense High Range

High Power (Note 6)

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.

4: A/D oscillator source is FRC.

5: 0.1 F capacitor on VCAP (RA0).

6: Includes FVR IPD and DAC IPD.

DS41418A-page 208

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

25.4 DC Characteristics: PIC16F707/PIC16LF707-I/E

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

DC CHARACTERISTICS

Param

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

VIL

Input Low Voltage

I/O PORT:

D030

D030A

D031

with TTL buffer

—

0.8

V

4.5V  VDD  5.5V

0.15 VDD

0.2 VDD

0.3 VDD

0.2 VDD

0.3 VDD

1.8V  VDD  4.5V

2.0V  VDD  5.5V

with Schmitt Trigger buffer

2

with I C™ levels

(1)

D032

MCLR, OSC1 (RC mode)

D033A

OSC1 (HS mode)

Input High Voltage

I/O ports:

VIH

—

D040

with TTL buffer

2.0

V

4.5V  VDD 5.5V

1.8V  VDD  4.5V

D040A

0.25 VDD +

0.8

D041

with Schmitt Trigger buffer

0.8 VDD

0.7 VDD

0.8 VDD

0.7 VDD

0.9 VDD

—

V

2.0V  VDD  5.5V

2

with I C™ levels

D042

MCLR

D043A

D043B

OSC1 (HS mode)

OSC1 (RC mode)

(Note 1)

(2)

IIL

Input Leakage Current

D060

I/O ports

—

± 5

± 125

nA

VSS  VPIN  VDD, Pin at high-

impedance, 85°C

± 5

± 1000

± 200

nA 125°C

(3)

D061

MCLR

± 50

nA

A

V

VSS  VPIN  VDD, 85°C

IPUR

VOL

PORTB Weak Pull-up Current

D070*

25

100

140

200

300

VDD = 3.3V, VPIN = VSS

VDD = 5.0V, VPIN = VSS

(4)

Output Low Voltage

D080

D090

D101*

I/O ports

IOL = 8mA, VDD = 5V

IOL = 6mA, VDD = 3.3V

IOL = 1.8mA, VDD = 1.8V

—

0.6

—

(4)

VOH

Output High Voltage

I/O ports

IOH = 3.5mA, VDD = 5V

IOH = 3mA, VDD = 3.3V

IOH = 1mA, VDD = 1.8V

VDD - 0.7

V

Capacitive Loading Specs on Output Pins

COSC2 OSC2 pin

—

15

50

pF

In XT, HS and LP modes when

external clock is used to drive

OSC1

D101A* CIO

All I/O pins

—

Program Flash Memory

Legend:

TBD = To Be Determined

These parameters are characterized but not tested.

*

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: Including OSC2 in CLKOUT mode.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 209

PIC16F707/PIC16LF707

25.4 DC Characteristics: PIC16F707/PIC16LF707-I/E (Continued)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

DC CHARACTERISTICS

Param

No.

Sym.

EP

Characteristic

Min.

Typ†

Max.

Units

Conditions

D130

Cell Endurance

100

1k

—

E/W Temperature during programming:

10°C  TA  40°C

D131

VDD for Read

VMIN

8.0

—

V

Temperature during programming:

10°C  TA  40°C

Voltage on MCLR/VPP during

Erase/Program

9.0

V

VDD for Bulk Erase

2.7

3

—

Temperature during programming:

10°C  TA  40°C

D132

VPEW

VDD for Write or Row Erase

—

VMIN = Minimum operating voltage

VMAX = Maximum operating

voltage

Temperature during programming:

10°C  TA  40°C

IPPPGM Current on MCLR/VPP during

Erase/Write

—

40

—

5.0

mA

IDDPGM Current on VDD during Erase/

Write

Temperature during programming:

10°C  TA  40°C

5.0

2.8

D133

D134

TPEW

Erase/Write cycle time

ms Temperature during programming:

10°C  TA  40°C

TRETD

Characteristic Retention

—

Year Provided no other specifications

are violated

VCAP Capacitor Charging

D135

Charging current

—

200

0.0

—

A

mA

D135A

Source/sink capability when

charging complete

Legend:

TBD = To Be Determined

These parameters are characterized but not tested.

*

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: Including OSC2 in CLKOUT mode.

DS41418A-page 210

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

25.5 Thermal Considerations

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No.

Sym.

Characteristic

Typ.

Units

Conditions

28-pin SPDIP package

TH01

^JA

Thermal Resistance Junction to Ambient

60

80

C/W

C

28-pin SOIC package

90

28-pin SSOP package

27.5

47.2

46

28-pin UQFN 4x4mm package

28-pin QFN 6x6mm package

40-pin PDIP package

44-pin TQFP package

24.4

31.4

24

44-pin QFN 8x8mm package

28-pin SPDIP package

28-pin SOIC package

TH02

^JC

Thermal Resistance Junction to Case

24

28-pin SSOP package

24

28-pin UQFN 4x4mm package

28-pin QFN 6x6mm package

40-pin PDIP package

24

24.7

14.5

20

44-pin TQFP package

44-pin QFN 8x8mm package

TH03

TH04

TH05

TH06

TH07

TJMAX

PD

Maximum Junction Temperature

Power Dissipation

150

—

W

PD = PINTERNAL + PI/O

(1)

PINTERNAL Internal Power Dissipation

—

W

PINTERNAL = IDD x VDD

PI/O

I/O Power Dissipation

Derated Power

—

W

PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))

(2)

PDER

—

W

PDER = PDMAX (TJ - TA)/JA

Note 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature

3: TJ = Junction Temperature

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 211

PIC16F707/PIC16LF707

25.6

Timing Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase letters (pp) and their meanings:

pp

cc

T

Time

CCP1

CLKOUT

CS

osc

rd

OSC1

RD

ck

cs

di

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O PORT

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (High-impedance)

Low

Valid

L

High-impedance

FIGURE 25-2:

LOAD CONDITIONS

Load Condition

CL

VSS

Legend: CL = 50 pF for all pins, 15 pF for

OSC2 output

DS41418A-page 212

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

25.7 AC Characteristics: PIC16F707-I/E

FIGURE 25-3:

CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

OSC1/CLKIN

OS02

OS04

OS03

OSC2/CLKOUT

(LP,XT,HS Modes)

OSC2/CLKOUT

(CLKOUT Mode)

FIGURE 25-4:

PIC16F707 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C

5.5

3.6

2.5

2.3

2.0

1.8

0

4

10

16

20

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 213

PIC16F707/PIC16LF707

FIGURE 25-5:

PIC16LF707 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C

3.6

2.5

2.3

2.0

1.8

0

4

10

16

20

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies.

FIGURE 25-6:

HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE

+ 5%

125

85

± 3%

± 2%

60

25

0

-20

+ 5%

-40

1.8

2.0

2.5

3.3⁽²⁾3.5

4.0

VDD (V)

4.5

5.0

5.5

3.0

Note 1: This chart covers both regulator enabled and regulator disabled states.

2: Regulator Nominal voltage.

DS41418A-page 214

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 25-1: CLOCK OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C  TA  +125°C

Param

Sym.

No.

Characteristic

Min.

Typ†

Max.

Units

Conditions

LP Oscillator mode

(1)

OS01

FOSC

TOSC

TCY

External CLKIN Frequency

DC

—

37

4

kHz

MHz XT Oscillator mode

MHz HS Oscillator mode

MHz EC Oscillator mode

—

20

—

(1)

Oscillator Frequency

32.768

—

kHz

LP Oscillator mode

0.1

1

4

MHz XT Oscillator mode

—

4

MHz

HS Oscillator mode, VDD 2.7V

HS Oscillator mode, VDD 2.7V

1

—

20

4

DC

27

250

50

—

MHz RC Oscillator mode

(1)

OS02

External CLKIN Period

—



s

ns

s

ns

s

ns

LP Oscillator mode

XT Oscillator mode

HS Oscillator mode

EC Oscillator mode

LP Oscillator mode

XT Oscillator mode

HS Oscillator mode, VDD 2.7V

HS Oscillator mode, VDD 2.7V

RC Oscillator mode

TCY = 4/FOSC

—



—



—



(1)

Oscillator Period

30.5

—

250

50

250

200

2

10,000

1,000

—

(1)

OS03

Instruction Cycle Time

TCY

—

DC

—

OS04*

TosH,

TosL

External CLKIN High,

External CLKIN Low

LP oscillator

100

20

0

—

XT oscillator

—

HS oscillator

OS05*

TosR,

TosF

External CLKIN Rise,

External CLKIN Fall

—



LP oscillator

0

—



XT oscillator

0

—



HS oscillator

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current

consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an

external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 215

PIC16F707/PIC16LF707

TABLE 25-2: OSCILLATOR PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C TA +125°C

Param

Sym.

No.

Freq.

Tolerance

Characteristic

Min. Typ† Max. Units

Conditions

OS08

HFOSC

Internal Calibrated HFINTOSC

Frequency

2%

—

16.0

—

MHz 0°C  TA  +85°C,

VDD V

(2)

5%

2%

—

16.0

500

—

MHz -40°C  TA  +125°C

OS08A MFOSC

OS10* TIOSC ST

Internal Calibrated MFINTOSC

Frequency

kHz 0°C  TA  +85°C

VDD V

(2)

5%

—

500

5

10

8

kHz -40°C  TA  +125°C

s

—

HFINTOSC Wake-up from Sleep

Start-up Time

MFINTOSC

—

20

30

s

Wake-up from Sleep

Start-up Time

These parameters are characterized but not tested.

*

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current

consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an

external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

3: By design.

FIGURE 25-7:

CLKOUT AND I/O TIMING

Cycle

Write

Q4

Fetch

Q1

Read

Q2

Execute

Q3

FOSC

OS12

OS11

OS20

OS21

CLKOUT

OS19

OS13

OS18

OS16

OS17

I/O pin

(Input)

OS14

OS15

I/O pin

(Output)

New Value

Old Value

OS18, OS19

DS41418A-page 216

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 25-3: CLKOUT AND I/O TIMING PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No.

Sym.

Characteristic

Min.

Typ† Max. Units

Conditions

OS11 TosH2ckL Fosc to CLKOUT ⁽¹⁾

OS12 TosH2ckH Fosc to CLKOUT ⁽¹⁾

OS13 TckL2ioV CLKOUT to Port out valid⁽¹⁾

—

70

72

20

ns VDD = 3.3-5.0V

ns

OS14 TioV2ckH Port input valid before CLKOUT⁽¹⁾

OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid

TOSC + 200 ns

—

50

—

70*

—

ns

—

ns VDD = 3.3-5.0V

OS16 TosH2ioI

Fosc (Q2 cycle) to Port input invalid

50

(I/O in hold time)

OS17 TioV2osH Port input valid to Fosc(Q2 cycle)

20

—

ns

(I/O in setup time)

OS18 TioR

OS19 TioF

Port output rise time⁽²⁾

—

40

15

72

32

ns

VDD = 2.0V

VDD = 3.3-5.0V

Port output fall time⁽²⁾

—

28

15

55

30

VDD = 2.0V

VDD = 3.3-5.0V

OS20* Tinp

OS21* Trbp

INT pin input high or low time

25

—

ns

PORTB interrupt-on-change new input

level time

TCY

*

†

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25C unless otherwise stated.

Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

2: Includes OSC2 in CLKOUT mode.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 217

PIC16F707/PIC16LF707

FIGURE 25-8:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Start-Up Time

(1)

Internal Reset

Watchdog Timer

(1)

Reset

31

34

I/O pins

Note 1: Asserted low.

FIGURE 25-9:

BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

VBOR and VHYST

VBOR

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

37

Reset

(1)

33

(due to BOR)

Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2 ms

delay if PWRTE = 0and VREGEN = 1.

DS41418A-page 218

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 25-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No.

Sym.

Characteristic

Min. Typ† Max. Units

Conditions

30

TMCL

MCLR Pulse Width (low)

2

5

—

s VDD = 3.3-5V, -40°C to +85°C

s VDD = 3.3-5V

31

TWDTLP Low Power Watchdog Timer Time-

out Period (No Prescaler)

10

—

40

—

18

1024

65

27

ms VDD = 3.3V-5V

32

TOST

Oscillator Start-up Timer Period^(1),

—

Tosc (Note 3)

(2)

33*

34*

35

TPWRT Power-up Timer Period,

140

2.0

ms

PWRTE = 0

TIOZ

I/O high-impedance from MCLR

—

s

Low or Watchdog Timer Reset

VBOR

Brown-out Reset Voltage

2.38

1.80

2.5

1.9

2.73

2.11

V

BORV=2.5V

BORV=1.9V

36*

37*

VHYST

Brown-out Reset Hysteresis

0

1

25

3

50

mV

-40°C to +85°C

TBORDC Brown-out Reset DC Response

Time

5

10

s VDD  VBOR, -40°C to +85°C

VDD  VBOR

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at “min” values with an external

clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no

clock) for all devices.

2: By design.

3: Period of the slower clock.

4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 219

PIC16F707/PIC16LF707

FIGURE 25-10:

TIMER0/A/B AND TIMER1/3 EXTERNAL CLOCK TIMINGS

T0CKI/TACKI/TBCKI

40

41

42

T1CKI/T3CKI

45

46

49

47

TMRx

TABLE 25-5: TIMER0/A/B AND TIMER1/3 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No.

Sym.

TT0H

Characteristic

Min.

Typ†

Max.

Units

Conditions

40*

T0CKI/TACKI/TBCKI High No Prescaler

0.5 TCY + 20

10

—

ns

Pulse Width

With Pres-

caler

41*

TT0L

T0CKI/TACKI/TBCKI Low

Pulse Width

No Prescaler

0.5 TCY + 20

10

—

ns

With Pres-

caler

42*

45*

TT0P

TT1H

T0CKI/TACKI/TBCKI Period

Greater of:

20 or TCY + 40

N

—

ns

N = prescale value

(2, 4, ..., 256)

T1CKI/

T3CKI High

Time

Synchronous, No Prescaler

Synchronous, with Prescaler

Asynchronous

0.5 TCY + 20

—

ns

15

30

46*

47*

TT1L

TT1P

T1CKI/

T3CKI Low

Time

Synchronous, No Prescaler

Synchronous, with Prescaler

Asynchronous

0.5 TCY + 20

15

30

T1CKI/

Synchronous

Greater of:

30 or TCY + 40

N

N = prescale value

(1, 2, 4, 8)

T3CKIInput

Period

Asynchronous

60

—

ns

48

FT1

Timer1 Oscillator Input Frequency Range

(oscillator enabled by setting bit

T1OSCEN)

32.4

32.76

8

33.1

kHz

49*

TCKEZTMR Delay from External Clock Edge to Timer

2 TOSC

—

7 TOSC

—

Timers in Sync

mode

1

Increment

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

DS41418A-page 220

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 25-11:

CAPTURE/COMPARE/PWM TIMINGS (CCP)

CCPx

(Capture mode)

CC01

CC02

CC03

Note: Refer to Figure 25-2 for load conditions.

TABLE 25-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C  TA  +125°C

Param

No.

Sym.

Characteristic

Min.

Typ† Max. Units

Conditions

CC01* TccL CCPx Input Low Time

CC02* TccH CCPx Input High Time

CC03* TccP CCPx Input Period

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5TCY + 20

—

ns

20

0.5TCY + 20

20

3TCY + 40

N

N = prescale value (1, 4 or 16)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

TABLE 25-7: PIC16F707 A/D CONVERTER (ADC) CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No.

Sym.

Characteristic

Min.

Typ†

Max. Units

Conditions

AD01

AD02

AD03

NR

Resolution

—

8

bit

EIL

EDL

Integral Error

±1.7

±1

LSb VREF = 3.0V

Differential Error

LSb No missing codes

VREF = 3.0V

AD04 EOFF Offset Error

—

±2.2

±1.5

VDD

VREF

50

LSb VREF = 3.0V

AD05 EGN Gain Error

LSb VREF = 3.0V

(3)

AD06 VREF Reference Voltage

AD07 VAIN Full-Scale Range

1.8

VSS

—

V

AD08 ZAIN Recommended Impedance of

Analog Voltage Source

k Can go higher if external 0.01F capacitor is

present on input pin.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Total Absolute Error includes integral, differential, offset and gain errors.

2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

3: When ADC is off, it will not consume any current other than leakage current. The power-down current specification

includes any such leakage from the ADC module.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 221

PIC16F707/PIC16LF707

TABLE 25-8: PIC16F707 A/D CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C  TA  +125°C

Param

Sym.

No.

Characteristic

Min.

Typ†

Max. Units

Conditions

AD130* TAD

A/D Clock Period

1.0

—

9.0

6.0

s

TOSC-based

ADCS<1:0> = 11(ADRC mode)

A/D Internal RC Oscillator

Period

2.0

AD131 TCNV Conversion Time (not including

—

10.5

1.0

—

TAD Set GO/DONE bit to conversion

complete

(1)

Acquisition Time)

AD132* TACQ Acquisition Time

s

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The ADRES register may be read on the following TCY cycle.

FIGURE 25-12:

PIC16F707 A/D CONVERSION TIMING (NORMAL MODE)

BSF ADCON0, GO

1 TCY

(1)

(TOSC/2

AD134

Q4

)

AD131

AD130

A/D CLK

7

6

5

4

3

2

1

0

A/D Data

ADRES

NEW_DATA

1 TCY

OLD_DATA

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

DS41418A-page 222

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 25-13:

PIC16F707 A/D CONVERSION TIMING (SLEEP MODE)

BSF ADCON0, GO

AD134

(1)

(TOSC/2 + TCY

1 TCY

)

AD131

Q4

AD130

A/D CLK

A/D Data

7

6

5

3

2

1

0

4

NEW_DATA

1 TCY

OLD_DATA

ADRES

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

FIGURE 25-14:

USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

CK

DT

US121

US122

US120

Refer to Figure 25-2 for load conditions.

Note:

TABLE 25-9: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C TA +125°C

Param.

Symbol

No.

Characteristic

Min.

Max.

Units Conditions

US120 TCKH2DTV SYNC XMIT (Master and Slave)

Clock high to data-out valid

3.0-5.5V

1.8-5.5V

3.0-5.5V

1.8-5.5V

3.0-5.5V

1.8-5.5V

—

80

100

45

ns

US121 TCKRF

Clock out rise time and fall time

(Master mode)

50

US122 TDTRF

Data-out rise time and fall time

45

50

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 223

PIC16F707/PIC16LF707

FIGURE 25-15:

USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

CK

DT

US125

US126

Note: Refer to Figure 25-2 for load conditions.

TABLE 25-10: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C TA +125°C

Param.

Symbol

No.

Characteristic

Min.

Max.

Units

Conditions

US125 TDTV2CKL SYNC RCV (Master and Slave)

Data-hold before CK  (DT hold time)

10

15

—

ns

US126 TCKL2DTL Data-hold after CK  (DT hold time)

FIGURE 25-16:

SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

SS

SP70

SCK

(CKP = 0)

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP80

bit 6 - - - - - -1

MSb

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

LSb In

SP74

SP73

Note: Refer to Figure 25-2 for load conditions.

DS41418A-page 224

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 25-17:

SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SS

SP81

SCK

(CKP = 0)

SP71

SP73

SP72

SP79

SP78

SCK

(CKP = 1)

SP80

bit 6 - - - - - -1

LSb

MSb

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

SP74

Note: Refer to Figure 25-2 for load conditions.

LSb In

FIGURE 25-18:

SPI SLAVE MODE TIMING (CKE = 0)

SS

SP70

SCK

(CKP = 0)

SP83

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP79

SP80

MSb

SDO

SDI

bit 6 - - - - - -1

SP77

SP75, SP76

MSb In

SP74

SP73

bit 6 - - - -1

LSb In

Note: Refer to Figure 25-2 for load conditions.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 225

PIC16F707/PIC16LF707

FIGURE 25-19:

SPI SLAVE MODE TIMING (CKE = 1)

SP82

SP70

SS

SP83

SCK

(CKP = 0)

SP72

SP71

SCK

(CKP = 1)

SP80

MSb

bit 6 - - - - - -1

LSb

SDO

SDI

SP77

SP75, SP76

bit 6 - - - -1

MSb In

SP74

LSb In

Note: Refer to Figure 25-2 for load conditions.

DS41418A-page 226

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 25-11: SPI MODE REQUIREMENTS

Param

Symbol

Characteristic

Min.

Typ† Max. Units Conditions

No.

SP70* TSSL2SCH, SS to SCK or SCK input

TCY

—

ns

TSSL2SCL

SP71* TSCH

SP72* TSCL

SCK input high time (Slave mode)

SCK input low time (Slave mode)

TCY + 20

100

—

ns

SP73* TDIV2SCH, Setup time of SDI data input to SCK edge

TDIV2SCL

SP74* TSCH2DIL, Hold time of SDI data input to SCK edge

TSCL2DIL

100

—

ns

SP75* TDOR

SDO data output rise time

3.0-5.5V

1.8-5.5V

—

10

—

Tcy

10

25

10

—

10

25

10

—

25

50

25

50

25

50

25

50

145

—

ns

SP76* TDOF

SDO data output fall time

SP77* TSSH2DOZ SS to SDO output high-impedance

SP78* TSCR

SCK output rise time

(Master mode)

3.0-5.5V

1.8-5.5V

SP79* TSCF

SCK output fall time (Master mode)

SP80* TSCH2DOV, SDO data output valid after

TSCL2DOV SCK edge

3.0-5.5V

1.8-5.5V

SP81* TDOV2SCH SDO data output setup to SCK edge

,

TDOV2SCL

SP82* TSSL2DOV SDO data output valid after SS edge

—

50

—

ns

SP83* TSCH2SSH, SS after SCK edge

1.5TCY +

40

TSCL2SSH

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

FIGURE 25-20:

I²C™ BUS START/STOP BITS TIMING

SCL

SP93

SP91

SP90

SP92

SDA

Stop

Condition

Start

Condition

Note: Refer to Figure 25-2 for load conditions.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 227

PIC16F707/PIC16LF707

TABLE 25-12: I²C™ BUS START/STOP BITS REQUIREMENTS

Param

Symbol

Characteristic

Min. Typ Max. Units

Conditions

No.

SP90* TSU:STA Start condition

Setup time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4700

600

—

ns Only relevant for Repeated

Start condition

SP91* THD:STA Start condition

Hold time

4000

600

ns After this period, the first

clock pulse is generated

SP92* TSU:STO Stop condition

Setup time

4700

600

ns

SP93 THD:STO Stop condition

Hold time

4000

600

ns

*

These parameters are characterized but not tested.

FIGURE 25-21:

I²C™ BUS DATA TIMING

SP100

SP103

SP102

SP101

SCL

SP90

SP106

SP107

SP92

SP91

SDA

In

SP110

SP109

SDA

Out

Note: Refer to Figure 25-2 for load conditions.

DS41418A-page 228

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

TABLE 25-13: I²C™ BUS DATA REQUIREMENTS

Param.

Symbol

Characteristic

Min.

Max. Units

Conditions

No.

SP100* THIGH

Clock high time

100 kHz mode

4.0

—

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

Device must operate at a

minimum of 10 MHz

SSP Module

1.5TCY

4.7

—

SP101* TLOW

Clock low time

100 kHz mode

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

SSP Module

1.3

—

Device must operate at a

minimum of 10 MHz

1.5TCY

—

SP102* TR

SP103* TF

SDA and SCL rise 100 kHz mode

time

1000

300

ns

400 kHz mode

20 +

0.1CB

CB is specified to be from

10-400 pF

SDA and SCL fall

time

100 kHz mode

400 kHz mode

—

250

ns

20 +

0.1CB

CB is specified to be from

10-400 pF

SP106* THD:DAT Data input hold

time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

0

—

0.9

—

ns

s

ns

s

0

SP107* TSU:DAT Data input setup

time

250

100

—

(Note 2)

(Note 1)

—

SP109* TAA

Output valid from

clock

3500

—

SP110* TBUF

Bus free time

4.7

1.3

—

Time the bus must be free

before a new transmis-

sion can start

—

SP111 CB

Bus capacitive loading

—

400

pF

*

These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (400 kHz) I²C™ bus device can be used in a Standard mode (100 kHz) I²C bus system, but

the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does

not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal,

it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to

the Standard mode I²C bus specification), before the SCL line is released.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 229

PIC16F707/PIC16LF707

TABLE 25-14: CAP SENSE OSCILLATOR SPECIFICATIONS

Param.

Symbol

Characteristic

Min.

Typ†

Max. Units

Conditions

No.

CS01

ISRC

Current Source

High

—

-6

-3.2

-0.9

6

A

mV

-5.8

-1.1

-0.2

6.6

-40, -85°C

Medium

Low

CS02

CS03

ISNK

Current Sink

High

-40, -85°C

Medium

Low

1.3

3.2

0.9

—

0.24

525

375

280

VCHYST

Cap Hysteresis

High

VCTH-VCTL

Medium

Low

—

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

FIGURE 25-22:

CAP SENSE OSCILLATOR

VCTH

VCTL

ISRC

Enabled

ISNK

Enabled

DS41418A-page 230

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

26.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are

not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

“Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean + 3) or

(mean - 3) respectively, where  is a standard deviation, over the whole temperature range.

FIGURE 26-1:

PIC16F707 MAXIMUM IDD vs. FOSC OVER VDD, EC MODE, VCAP = 0.1µF

2,200.00

2,000.00

1,800.00

1,600.00

1,400.00

1,200.00

1,000.00

800.00

5V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

3.6V

3V

2.5V

1.8V

600.00

400.00

200.00

0.00

1 MHz

4 MHz

8 MHz

12 MHz

16 MHz

20 MHz

VDD (V)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 231

PIC16F707/PIC16LF707

FIGURE 26-2:

PIC16LF707 MAXIMUM IDD vs. FOSC OVER VDD, EC MODE

2,400

2,200

2,000

1,800

1,600

1,400

1,200

1,000

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

3.6V

3.3V

3V

2.5V

2V

1.8V

600

400

200

0

1 MHz

4 MHz

8 MHz

12 MHz

16 MHz

20 MHz

FOSC

FIGURE 26-3:

PIC16F707 TYPICAL IDD vs. FOSC OVER VDD, EC MODE, VCAP = 0.1µF

2,000

1,800

1,600

1,400

1,200

1,000

800

5V

3.6V

3V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

2.5V

1.8V

600

400

200

0

1 MHz

4 MHz

8 MHz

12 MHz

16 MHz

20 MHz

FOSC

DS41418A-page 232

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-4:

PIC16LF707 TYPICAL IDD vs. FOSC OVER VDD, EC MODE

2,200

2,000

1,800

1,600

1,400

1,200

1,000

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

3.6V

3.3V

3V

2.5V

2V

1.8V

600

400

200

0

1 MHz

4 MHz

8 MHz

12 MHz

16 MHz

20 MHz

FOSC

FIGURE 26-5:

PIC16F707 MAXIMUM IDD vs. VDD OVER FOSC, EXTRC MODE, VCAP = 0.1µF

600

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

4 MHz

(-40°C to 125°C)

500

400

300

200

100

0

1 MHz

1.8

2

2.5

3

3.3

3.6

4.2

4.5

5

VDD (V)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 233

PIC16F707/PIC16LF707

FIGURE 26-6:

PIC16LF707 MAXIMUM IDD vs. VDD OVER FOSC, EXTRC MODE

500

4 MHz

Typical: Statistical Mean @25°C

450

400

350

300

250

200

150

100

50

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

1 MHz

0

1.8

2

2.5

3

3.3

3.6

VDD (V)

FIGURE 26-7:

PIC16F707 TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE, VCAP = 0.1µF

450

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

4 MHz

400

350

300

250

200

150

100

50

1 MHz

0

1.8

2

2.5

3

3.3

3.6

4.2

4.5

5

VDD (V)

DS41418A-page 234

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-8:

PIC16LF707 TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE

450

Typical: Statistical Mean @25°C

4 MHz

Maximum: Mean (Worst-Case Temp) + 3

400

350

300

250

200

150

100

50

(-40°C to 125°C)

1 MHz

0

1.8

2

2.5

3

3.3

3.6

VDD (V)

FIGURE 26-9:

PIC16F707 MAXIMUM IDD vs. FOSC OVER VDD, HS MODE, VCAP = 0.1µF

2.4

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

2.2

2

5V

4.5V

3.6V

3V

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

4 MHz

6 MHz

8 MHz

10 MHz

13 MHz

16 MHz

20 MHz

Fosc

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 235

PIC16F707/PIC16LF707

FIGURE 26-10:

PIC16LF707 MAXIMUM IDD vs. FOSC OVER VDD, HS MODE

2.50

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

3.6V

3.3V

2.00

1.50

1.00

0.50

0.00

3V

2.5V

4 MHz

6 MHz

8 MHz

10 MHz

13 MHz

16 MHz

20 MHz

Fosc

FIGURE 26-11:

PIC16F707 TYPICAL IDD vs. FOSC OVER VDD, HS MODE, VCAP = 0.1µF

Typical: Statistical Mean @25°C

2.00

1.50

1.00

0.50

0.00

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

5V

4.5V

3.6V

3V

4 MHz

6 MHz

8 MHz

10 MHz

13 MHz

16 MHz

20 MHz

Fosc

DS41418A-page 236

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-12:

PIC16LF707 TYPICAL IDD vs. FOSC OVER VDD, HS MODE

2.50

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

2.00

1.50

1.00

0.50

0.00

3.6V

3.3V

3V

2.5V

4 MHz

6 MHz

8 MHz

10 MHz

13 MHz

16 MHz

20 MHz

Fosc

FIGURE 26-13:

PIC16F707 MAXIMUM IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.1µF

600

Typical: Statistical Mean @25°C

4 MHz

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

500

400

300

200

100

0

1 MHz

1.8

2

2.5

3

3.3

3.6

4.2

4.5

5

VDD (V)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 237

PIC16F707/PIC16LF707

FIGURE 26-14:

PIC16LF707 MAXIMUM IDD vs. VDD OVER FOSC, XT MODE

600

Typical: Statistical Mean @25°C

4 MHz

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

500

400

300

200

100

0

1 MHz

1.8

2

2.5

3

3.3

3.6

VDD (V)

FIGURE 26-15:

PIC16F707 TYPICAL IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.1µF

600

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

500

400

300

200

100

0

4 MHz

1 MHz

1.8

2

2.5

3

3.3

3.6

4.2

4.5

5

VDD (V)

DS41418A-page 238

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-16:

PIC16LF707 TYPICAL IDD vs. VDD OVER FOSC, XT MODE

600

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

500

400

300

200

100

0

4 MHz

1 MHz

1.8

2

2.5

3

3.3

3.6

VDD (V)

FIGURE 26-17:

PIC16F707 IDD vs. VDD, LP MODE, VCAP = 0.1µF

20.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

17.5

15.0

12.5

10.0

32 kHz Maximum

VDD (V)

32 kHz Typical

1.8

3

5

VDD (V)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 239

PIC16F707/PIC16LF707

FIGURE 26-18:

PIC16LF707 IDD vs. VDD, LP MODE

30

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

25

20

15

10

5

32 kHz Maximum

32 kHz Typical

1.8

3

3.3

3.6

VDD (V)

FIGURE 26-19:

PIC16F707 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF

210

Typical: Statistical Mean @25°C

200

190

180

170

160

150

140

130

120

110

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

5V

3.6V

2.5V

1.8V

62.5 kHz

125 kHz

250 kHz

500 kHz

FOSC

DS41418A-page 240

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-20:

PIC16LF707 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE

170

Typical: Statistical Mean @25°C

3.6V

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

160

150

140

130

120

110

100

3V

2.5V

1.8V

62.5 kHz

125 kHz

250 kHz

500 kHz

FOSC

FIGURE 26-21:

PIC16F707 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF

2,000

5V

Typical: Statistical Mean @25°C

1,800

1,600

1,400

1,200

1,000

800

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

3.6V

2.5V

1.8V

600

400

200

0

2 MHz

4 MHz

8 MHz

16 MHz

FOSC

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 241

PIC16F707/PIC16LF707

FIGURE 26-22:

PIC16LF707 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE

2,250

s

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

3.6V

2,000

1,750

1,500

1,250

1,000

750

3V

2.5V

1.8V

500

250

0

2 MHz

4 MHz

8 MHz

16 MHz

FOSC

FIGURE 26-23:

PIC16F707 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF

160

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

150

140

130

120

110

100

90

5V

3.6V

2.5V

1.8V

80

62.5 kHz

125 kHz

250 kHz

500 kHz

FOSC

DS41418A-page 242

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-24:

PIC16LF707 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE

140

3.6V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

130

120

110

100

90

3V

2.5V

1.8V

80

70

62.5 kHz

125 kHz

250 kHz

500 kHz

FOSC

FIGURE 26-25:

PIC16F707 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF

2,000

Typical: Statistical Mean @25°C

1,800

1,600

1,400

1,200

1,000

800

5V

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

3.6V

2.5V

1.8V

600

400

200

0

2 MHz

4 MHz

8 MHz

16 MHz

FOSC

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 243

PIC16F707/PIC16LF707

FIGURE 26-26:

PIC16LF707 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE

2,000

3.6V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

1,800

1,600

1,400

1,200

1,000

800

3V

2.5V

1.8V

600

400

200

0

2 MHz

4 MHz

8 MHz

16 MHz

VDD (V)

FIGURE 26-27:

PIC16F707 MAXIMUM BASE IPD vs. VDD, VCAP = 0.1µF

25

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

20

15

10

5

125°C

85°C

0

1.8V

2V

3V

3.6V

4V

5V

5.5V

VDD (V)

DS41418A-page 244

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-28:

PIC16LF707 MAXIMUM BASE IPD vs. VDD

7

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

6

5

4

3

2

1

0

125°C

85°C

1.8V

2V

2.5V

3V

3.6V

VDD (V)

FIGURE 26-29:

PIC16F707 TYPICAL BASE IPD vs. VDD, VCAP = 0.1µF

8

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

7

6

5

4

3

2

25°C

1.8V

2V

3V

3.6V

4V

5V

5.5V

VDD (V)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 245

PIC16F707/PIC16LF707

FIGURE 26-30:

PIC16LF707 TYPICAL BASE IPD vs. VDD

250

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

200

150

100

50

25°C

0

1.8V

2V

2.5V

3V

3.6V

VDD (V)

FIGURE 26-31:

PIC16F707 FIXED VOLTAGE REFERENCE IPD vs. VDD, VCAP = 0.1µF

70

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

Max. 125°C

60

50

40

30

20

10

0

(-40°C to 125°C)

Max. 85°C

Typ. 25°C

1.8V

2V

3V

3.6V

5V

5.5V

VDD (V)

DS41418A-page 246

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-32:

PIC16LF707 FIXED VOLTAGE REFERENCE IPD vs. VDD

25

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

Max. 125°C

20

15

10

5

Max. 85°C

Typ. 25°C

0

1.8V

2V

2.5V

3V

3.6V

VDD (V)

FIGURE 26-33:

PIC16F707 BOR IPD vs. VDD, VCAP = 0.1µF

70

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

60

50

40

30

20

10

0

Max. 125°C

Max. 85°C

Typ. 25°C

2V

3V

3.6V

5V

5.5V

VDD (V)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 247

PIC16F707/PIC16LF707

FIGURE 26-34:

PIC16LF707 BOR IPD vs. VDD

30

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

25

20

15

10

5

Max. 125°C

Max. 85°C

Typ. 25°C

0

2V

2.5V

3V

3.6V

VDD (V)

FIGURE 26-35:

PIC16F707 CAP SENSE HIGH POWER IPD vs. VDD, VCAP = 0.1µF

70

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

Max. 125°C

60

50

40

30

20

10

0

Max. 85°C

Typ. 25°C

1.8V

2V

3V

3.6V

5V

5.5V

VDD (V)

DS41418A-page 248

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-36:

PIC16LF707 CAP SENSE HIGH POWER IPD vs. VDD

60

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

50

40

30

20

10

0

Max. 125°C

Max. 85°C

Typ. 25°C

1.8V

2V

2.5V

3V

3.6V

VDD (V)

FIGURE 26-37:

PIC16F707 CAP SENSE MEDIUM POWER IPD vs. VDD, VCAP = 0.1µF

30

Max. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

25

20

15

10

5

Max. 85°C

Typ. 25°C

0

1.8V

2V

3V

3.6V

5V

5.5V

VDD (V)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 249

PIC16F707/PIC16LF707

FIGURE 26-38:

PIC16LF707 CAP SENSE MEDIUM POWER IPD vs. VDD

20

Typical: Statistical Mean @25°C

Max. 125°C

Maximum: Mean (Worst-Case Temp) + 3

18

16

14

12

10

8

(-40°C to 125°C)

Max. 85°C

Typ. 25°C

6

4

2

0

1.8V

2V

2.5V

3V

3.6V

VDD (V)

FIGURE 26-39:

PIC16F707 CAP SENSE LOW POWER IPD vs. VDD, VCAP = 0.1µF

30

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

Max. 125°C

25

20

15

10

5

Max. 85°C

Typ. 25°C

0

1.8V

2V

3V

3.6V

5V

5.5V

VDD (V)

DS41418A-page 250

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-40:

PIC16LF707 CAP SENSE LOW POWER IPD vs. VDD

18

Typical: Statistical Mean @25°C

Max. 125°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

16

14

12

10

8

6

Max. 85°C

Typ. 25°C

4

2

0

1.8V

2V

2.5V

3V

3.6V

VDD (V)

FIGURE 26-41:

PIC16F707 T1OSC 32 kHz IPD vs. VDD, VCAP = 0.1µF

16

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

Max. 85°C

14

12

10

8

Typ. 25° C

6

4

2

0

1.8V

2V

3V

3.6V

5V

5.5V

VDD (V)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 251

PIC16F707/PIC16LF707

FIGURE 26-42:

PIC16LF707 T1OSC 32 kHz IPD vs. VDD

4.0

Max. 85°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Typ.

1.8V

2V

2.5V

3V

3.6V

VDD (V)

FIGURE 26-43:

PIC16F707 TYPICAL ADC IPD vs. VDD, VCAP = 0.1µF

7.5

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

Typ. 25°C

7.0

6.5

6.0

5.5

5.0

1.8V

2V

3V

3.6V

5V

5.5V

VDD (V)

DS41418A-page 252

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-44:

PIC16LF707 TYPICAL ADC IPD vs. VDD

250

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

Typ. 25°C

200

150

100

50

0

1.8V

2V

2.5V

3V

3.6V

VDD (V)

FIGURE 26-45:

PIC16F707 ADC IPD vs. VDD, VCAP = 0.1µF

25

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

Max. 125°C

20

15

10

5

Max. 85°C

1.8V

2V

3V

3.6V

5V

5.5V

VDD (V)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 253

PIC16F707/PIC16LF707

FIGURE 26-46:

PIC16LF707 ADC IPD vs. VDD

8

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

7

6

5

4

3

2

1

0

Max. 125°C

Max. 85°C

1.8V

2V

2.5V

3V

3.6V

VDD (V)

FIGURE 26-47:

PIC16F707 WDT IPD vs. VDD, VCAP = 0.1µF

18

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

Max. 85°C

16

14

12

10

8

Typ. 25°C

6

4

2

0

1.8V

2V

3V

3.6V

5V

5.5V

VDD (V)

DS41418A-page 254

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-48:

PIC16LF707 WDT IPD vs. VDD

3.5

Typical: Statistical Mean @25°C

Max. 85°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Typ. 25°C

1.8V

2V

2.5V

3V

3.6V

VDD (V)

FIGURE 26-49:

TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

1.8

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

1.6

1.4

1.2

1

Minimum: Mean - 3 (-40°C to 125°C)

Max. -40°

Typ. 25°

Min. 125°

0.8

0.6

0.4

1.8

3.6

5.5

VDD (V)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 255

PIC16F707/PIC16LF707

FIGURE 26-50:

SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

3.5

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Minimum: Mean - 3 (-40°C to 125°C)

VIHMax. -40°C

VIHMin. 125°C

1.8

3.6

5.5

VDD (V)

FIGURE 26-51:

SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

3.0

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

Minimum: Mean - 3 (-40°C to 125°C)

2.5

2.0

1.5

1.0

0.5

0.0

VIL Max. -40°C

VIL Min. 125°C

1.8

3.6

5.5

VDD (V)

DS41418A-page 256

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-52:

VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V

5.6

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

5.5

5.4

5.3

5.2

5.1

5

Minimum: Mean - 3 (-40°C to 125°C)

Max. -40°

Typ. 25°

Min. 125°

-0.2

-1.0

-1.8

-2.6

-3.4

-4.2

-5.0

IOH (mA)

FIGURE 26-53:

VOH vs. IOH OVER TEMPERATURE, VDD = 3.6V

3.8

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

Minimum: Mean - 3 (-40°C to 125°C)

3.6

3.4

3.2

3

Max. -40°

Typ. 25°

Min. 125°

2.8

2.6

-0.2

-1.0

-1.8

-2.6

-3.4

-4.2

-5.0

IOH (mA)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 257

PIC16F707/PIC16LF707

FIGURE 26-54:

VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V

2

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

1.8

1.6

1.4

1.2

1

Minimum: Mean - 3 (-40°C to 125°C)

Max. -40°

Typ. 25°

0.8

0.6

0.4

0.2

Min. 125°

0

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

-1.6

-1.8

-2.0

IOH (mA)

FIGURE 26-55:

VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V

0.5

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

0.45

0.4

Minimum: Mean - 3 (-40°C to 125°C)

0.35

0.3

Max. 125°

0.25

0.2

Typ. 25°

0.15

0.1

Min. -40°

0.05

0

5.0

6.0

7.0

8.0

9.0

10.0

IOL (mA)

DS41418A-page 258

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-56:

VOL vs. IOL OVER TEMPERATURE, VDD = 3.6

0.9

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Minimum: Mean - 3 (-40°C to 125°C)

Max. 125°

Typ. 25°

Min. -40°

4.0

5.0

6.0

7.0

8.0

9.0

10.0

IOL (mA)

FIGURE 26-57:

VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V

1.2

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

Minimum: Mean - 3 (-40°C to 125°C)

1

0.8

0.6

0.4

0.2

0

Max. 125°

Min. -40°

0.0

0.4

0.8

1.2

1.6

IOL (mA)

2.0

2.4

2.8

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 259

PIC16F707/PIC16LF707

FIGURE 26-58:

PIC16F707 PWRT PERIOD

105

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

95

85

75

65

55

45

Max. -40°C

Typ. 25°C

Min. 125°C

1.8V

2V

2.2V

2.4V

3V

3.6V

4V

4.5V

5V

5.5V

VDD

FIGURE 26-59:

PIC16F707 WDT TIME-OUT PERIOD

24.00

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

22.00

20.00

18.00

16.00

14.00

12.00

10.00

Max. -40°C

Typ. 25°C

Min. 125°C

1.8V

2V

2.2V

2.4V

3V

3.6V

4V

4.5V

5V

VDD

DS41418A-page 260

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-60:

PIC16F707 HFINTOSC WAKE-UP FROM SLEEP START-UP TIME

6.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

Max.

Typ.

1.8V

2V

3V

3.6V

4V

4.5V

5V

5.5V

VDD

FIGURE 26-61:

PIC16F707 A/D INTERNAL RC OSCILLATOR PERIOD

6.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

5.0

4.0

3.0

2.0

1.0

0.0

Max.

Min.

1.8V

3.6V

5.5V

VDD(V)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 261

PIC16F707/PIC16LF707

FIGURE 26-62:

PIC16F707 CAP SENSE OUTPUT CURRENT, POWER MODE = HIGH

20000

Min. Sink -40°C

Typ. Sink 25°C

15000

10000

5000

Max. Sink 85°C

0

Min. Source 85°C

Typ. Source 25°C

-5000

-10000

-15000

Max. Source -40°C

1.8

2

2.5

3

3.2

3.6

4

4.5

5

5.5

VDD(V)

FIGURE 26-63:

PIC16F707 CAP SENSE OUTPUT CURRENT, POWER MODE = MEDIUM

3000

Max. Sink -40°C

2000

1000

0

Typ. Sink 25°C

Min. Sink 85°C

Min. Source 85°C

Typ. Source 25°C

-1000

-2000

-3000

Max. Source -40°C

1.8

2

2.5

3

3.2

3.6

4

4.5

5

5.5

VDD(V)

DS41418A-page 262

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-64:

PIC16F707 CAP SENSE OUTPUT CURRENT, POWER MODE = LOW

600

Max. Sink 85°C

Typ. Sink 25°C

400

200

0

Min. Sink -40°C

Min. Source 85°C

Typ. Source 25°C

-200

-400

-600

-800

Max. Source -40°C

1.8

2

2.5

3

3.2

3.6

4

4.5

5

5.5

VDD(V)

FIGURE 26-65:

PIC16F707 CAP SENSOR HYSTERESIS, POWER MODE = HIGH

700

Max. 125°C

Max. 85°C

600

500

400

Typ. 25°C

Min. 0°C

Min. -40°C

300

1.8

2.0

2.5

3.0

3.2

3.6

4.0

4.5

5.0

5.5

VDD(V)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 263

PIC16F707/PIC16LF707

FIGURE 26-66:

PIC16F707 CAP SENSOR HYSTERESIS, POWER MODE = MEDIUM

550

500

450

400

350

300

Max. 125°C

Max. 85°C

Typ. 25°C

Min. 0°C

Min. -40°C

250

1.8

2.0

2.5

3.0

3.2

3.6

4.0

4.5

5.0

5.5

VDD(V)

FIGURE 26-67:

PIC16F707 CAP SENSOR HYSTERESIS, POWER MODE = LOW

450

Max. 125°C

Max. 85°C

400

350

300

250

200

150

Typ. 25°C

Min. 0°C

Min -40°C

1.8

2.0

2.5

3.0

3.2

3.6

4.0

4.5

5.0

5.5

VDD(V)

DS41418A-page 264

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

FIGURE 26-68:

TYPICAL FVR (X1 AND X2) VS. SUPPLY VOLTAGE (V) NORMALIZED AT 3.0V

1.5

1

0.5

0

-0.5

-1

-1.5

1.8

2.5

3

3.6

4.2

5.5

Voltage

FIGURE 26-69:

TYPICAL FVR CHANGE VS. TEMPERATURE NORMALIZED AT 25°C

1.5

1

0.5

0

-0.5

-1

-1.5

-2

-2.5

-3

-40

0

45

85

125

Temperature (°C)

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 265

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 266

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

27.0 PACKAGING INFORMATION

27.1 Package Marking Information

40-Lead PDIP

Example

XXXXXXXXXXXXXXXXXX

PIC16F707

e

3

-I/P

10033K1

YYWWNNN

44-Lead QFN

Example

XXXXXXXXXX

YYWWNNN

PIC16F707

-I/ML

10033K1

e

3

44-Lead TQFP

Example

XXXXXXXXXXX

YYWWNNN

PIC16F707

e

3

-I/PT

10033K1

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*

Standard PICmicro^®device marking consists of Microchip part number, year code, week code and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 267

PIC16F707/PIC16LF707

27.2 Package Details

The following sections give the technical details of the packages.

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ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ

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ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁ1ꢔꢁ

2ꢐ,3 2ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢘꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢀꢛ2

DS41418A-page 268

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

ꢀꢀꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ ꢏꢅꢆꢇ!ꢉꢅꢋ"ꢇꢛꢗꢇꢃꢄꢅꢆꢇꢈꢅꢍ#ꢅ$ꢄꢇꢒ%ꢃꢓꢇMꢇ&'&ꢇꢕꢕꢇꢖꢗꢆꢘꢇꢙ !ꢛꢚ

ꢛꢗꢋꢄꢜ 4ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ5ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ5ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ

ꢍ&&ꢓ366***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'6ꢓꢆꢌ5ꢆꢑꢃꢄꢑ

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ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ

ꢎꢁ ꢂꢆꢌ5ꢆꢑꢈꢅꢃ!ꢅ!ꢆ*ꢅ!ꢃꢄꢑ"ꢇꢆ&ꢈ#ꢁ

-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁ1ꢔꢁ

2ꢐ,3 2ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

ꢝ.43 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢘꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀꢕ-2

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 269

PIC16F707/PIC16LF707

ꢀꢀꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ ꢏꢅꢆꢇ!ꢉꢅꢋ"ꢇꢛꢗꢇꢃꢄꢅꢆꢇꢈꢅꢍ#ꢅ$ꢄꢇꢒ%ꢃꢓꢇMꢇ&'&ꢇꢕꢕꢇꢖꢗꢆꢘꢇꢙ !ꢛꢚ

ꢛꢗꢋꢄꢜ 4ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ5ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ5ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ

ꢍ&&ꢓ366***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'6ꢓꢆꢌ5ꢆꢑꢃꢄꢑ

DS41418A-page 270

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

ꢀꢀꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ()ꢌꢑꢇ ꢏꢅꢆꢇ!ꢉꢅꢋ*ꢅꢍ#ꢇꢒꢈ(ꢓꢇMꢇ+ꢁ'+ꢁ'+ꢇꢕꢕꢇꢖꢗꢆꢘ"ꢇ,-ꢁꢁꢇꢕꢕꢇꢙ( !ꢈꢚ

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ꢍ&&ꢓ366***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'6ꢓꢆꢌ5ꢆꢑꢃꢄꢑ

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ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ

ꢎꢁ ,ꢍꢆ'%ꢈꢉ!ꢅꢆ&ꢅꢌꢋꢉꢄꢈꢉ!ꢅꢆꢉꢈꢅꢋꢓ&ꢃꢋꢄꢆꢇAꢅ!ꢃBꢈꢅ'ꢆꢊꢅ ꢆꢉꢊꢁ

-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢀꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢎ1ꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ

ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁ1ꢔꢁ

2ꢐ,3 2ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

ꢝ.43 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢘꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢜꢛ2

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 271

PIC16F707/PIC16LF707

ꢀꢀꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ()ꢌꢑꢇ ꢏꢅꢆꢇ!ꢉꢅꢋ*ꢅꢍ#ꢇꢒꢈ(ꢓꢇMꢇ+ꢁ'+ꢁ'+ꢇꢕꢕꢇꢖꢗꢆꢘ"ꢇ,-ꢁꢁꢇꢕꢕꢇꢙ( !ꢈꢚ

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DS41418A-page 272

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

APPENDIX A: DATA SHEET

REVISION HISTORY

APPENDIX B: MIGRATING FROM

OTHER PIC^®

DEVICES

Revision A (April 2010)

This discusses some of the issues in migrating from

other PIC^®devices to the PIC16F707 family of devices.

Original release of this data sheet.

Note:

This device has been designed to perform

to the parameters of its data sheet. It has

been tested to an electrical specification

designed to determine its conformance

with these parameters. Due to process

differences in the manufacture of this

device, this device may have different

performance characteristics than its ealier

version. These differences may cause this

device to perform differently in your

application than the earlier version of this

device.

Note:

The user should verify that the device

oscillator starts and performs as expected.

Adjusting the loading capacitor values

and/or the oscillator mode may be

required.

B.1

PIC16F77 to PIC16F707

TABLE B-1:

Feature

FEATURE COMPARISON

PIC16F77

PIC16F707

Max. Operating Speed

20 MHz

8K

20 MHz

8K

Max. Program

Memory (Words)

Max. SRAM (Bytes)

A/D Resolution

Timers (8/16-bit)

Oscillator Modes

Brown-out Reset

Internal Pull-ups

Interrupt-on-change

Comparator

368

363

8-bit

2/1

4/2

4

8

Y

RB<7:0>

RB<7:4>

RB<7:0>

0

Y

N

0

Y

N

USART

Extended WDT

Software Control

Option of WDT/BOR

INTOSC Frequencies

Clock Switching

None

N

500 kHz -

16 MHz

N

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 273

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 274

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

INDEX

Receive .................................................... 155

Transmit ................................................... 154

Reception ......................................................... 155

Transmission .................................................... 154

A

A/D

Specifications.................................................... 220, 221

Absolute Maximum Ratings .............................................. 201

AC Characteristics

B

Industrial and Extended ............................................ 212

Load Conditions........................................................ 211

ADC .................................................................................... 79

Acquisition Requirements ........................................... 86

Associated registers.................................................... 88

Block Diagram............................................................. 79

Calculating Acquisition Time....................................... 86

Channel Selection....................................................... 80

Configuration............................................................... 80

Configuring Interrupt ................................................... 82

Conversion Clock........................................................ 80

Conversion Procedure ................................................ 82

Internal Sampling Switch (RSS) IMPEDANCE ................ 86

Interrupts..................................................................... 81

Operation .................................................................... 82

Operation During Sleep .............................................. 82

Port Configuration....................................................... 80

Reference Voltage (VREF)........................................... 80

Source Impedance...................................................... 86

Special Event Trigger.................................................. 82

ADCON0 Register......................................................... 19, 84

ADCON1 Register......................................................... 20, 85

Addressable Universal Synchronous Asynchronous

Receiver Transmitter (AUSART)............................... 137

ADRES Register ................................................................. 85

ADRESH Register............................................................... 19

Alternate Pin Function......................................................... 51

Analog-to-Digital Converter. See ADC

BF bit ........................................................................ 165, 177

Block Diagrams

(CCP) Capture Mode Operation............................... 129

ADC............................................................................ 79

ADC Transfer Function............................................... 87

Analog Input Model..................................................... 87

AUSART Receive..................................................... 138

AUSART Transmit.................................................... 137

CCP PWM ................................................................ 133

Clock Source .............................................................. 69

Compare................................................................... 131

Crystal Operation........................................................ 73

Digital-to-Analog Converter (DAC) ............................. 92

External RC Mode ...................................................... 74

Interrupt Logic............................................................. 39

MCLR Circuit .............................................................. 31

On-Chip Reset Circuit................................................. 29

Resonator Operation .................................................. 74

SPI Mode.................................................................. 158

2

SSP (I C Mode)........................................................ 167

Timer1 ...................................................................... 100

Timer2 ...................................................................... 115

TMR0/WDT Prescaler ........................................ 95, 111

Voltage Reference...................................................... 92

Voltage Reference Output Buffer Example ................ 92

Brown-out Reset (BOR)...................................................... 33

Specifications ........................................................... 218

Timing and Characteristics....................................... 217

ANSELA Register ............................................................... 53

ANSELB Register ......................................................... 57, 60

ANSELD Register ............................................................... 63

ANSELE Register ............................................................... 66

APFCON Register............................................................... 51

Assembler

MPASM Assembler................................................... 198

AUSART ........................................................................... 137

Associated Registers

C

C Compilers

MPLAB C18.............................................................. 198

Capacitive Sensing........................................................... 117

Capture Module. See Capture/Compare/PWM (CCP)

Capture/Compare/PWM (CCP) ........................................ 127

Associated registers w/ Capture............................... 130

Associated registers w/ Compare............................. 132

Associated registers w/ PWM................................... 136

Capture Mode........................................................... 129

CCPx Pin Configuration............................................ 129

Compare Mode......................................................... 131

CCPx Pin Configuration.................................... 131

Software Interrupt Mode........................... 129, 131

Special Event Trigger....................................... 131

Timer1 Mode Selection............................. 129, 131

Interaction of Two CCP Modules (table)................... 127

Prescaler .................................................................. 129

PWM Mode............................................................... 133

Duty Cycle ........................................................ 134

Effects of Reset................................................ 135

Example PWM Frequencies and

Baud Rate Generator........................................ 147

Asynchronous Mode ................................................. 139

Associated Registers

Receive..................................................... 144

Transmit.................................................... 141

Baud Rate Generator (BRG) ............................ 147

Receiver............................................................ 141

Setting up 9-bit Mode with Address Detect....... 143

Transmitter........................................................ 139

Baud Rate Generator (BRG)

Baud Rate Error, Calculating ............................ 147

Formulas........................................................... 147

High Baud Rate Select (BRGH Bit) .................. 147

Synchronous Master Mode............................... 150, 154

Associated Registers

Receive..................................................... 153

Transmit.................................................... 151

Reception.......................................................... 152

Transmission .................................................... 150

Synchronous Slave Mode

Resolutions, 20 MHZ................................ 135

Example PWM Frequencies and

Resolutions, 8 MHz .................................. 135

Operation in Sleep Mode.................................. 135

Setup for Operation .......................................... 135

System Clock Frequency Changes .................. 135

PWM Period ............................................................. 134

Associated Registers

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 275

PIC16F707/PIC16LF707

Setup for PWM Operation.........................................135

Timer Resources.......................................................127

CCP. See Capture/Compare/PWM (CCP)

Electrical Specifications.................................................... 201

Enhanced Capture/Compare/PWM (ECCP)

Specifications ........................................................... 220

Errata.................................................................................... 9

CCP1CON Register ............................................................19

CCP2CON Register ............................................................19

CCPR1H Register...............................................................19

CCPR1L Register................................................................19

CCPR2H Register...............................................................19

CCPR2L Register................................................................19

CCPxCON Register ..........................................................128

CKE bit...................................................................... 165, 177

CKP bit...................................................................... 164, 176

Clock Sources

External Modes...........................................................73

EC.......................................................................73

HS.......................................................................73

LP........................................................................73

OST.....................................................................73

RC.......................................................................74

XT .......................................................................73

Code Examples

F

Firmware Instructions ....................................................... 187

Fixed Voltage Reference. See FVR

FSR Register ................................................................ 19, 20

Fuses. See Configuration Bits

FVR..................................................................................... 89

FVRCON Register .............................................................. 90

G

General Purpose Register File ........................................... 17

I

2

I C Mode

Associated Registers................................................ 178

INDF Register............................................................... 19, 20

Indirect Addressing, INDF and FSR Registers ................... 27

Instruction Format............................................................. 187

Instruction Set................................................................... 187

ADDLW..................................................................... 189

ADDWF..................................................................... 189

ANDLW..................................................................... 189

ANDWF..................................................................... 189

MOVF ....................................................................... 192

BCF .......................................................................... 189

BSF........................................................................... 189

BTFSC...................................................................... 189

BTFSS ...................................................................... 190

CALL......................................................................... 190

CLRF ........................................................................ 190

CLRW ....................................................................... 190

CLRWDT .................................................................. 190

COMF ....................................................................... 190

DECF........................................................................ 190

DECFSZ ................................................................... 191

GOTO ....................................................................... 191

INCF ......................................................................... 191

INCFSZ..................................................................... 191

IORLW...................................................................... 191

IORWF...................................................................... 191

MOVLW .................................................................... 192

MOVWF.................................................................... 192

NOP.......................................................................... 192

RETFIE..................................................................... 193

RETLW ..................................................................... 193

RETURN................................................................... 193

RLF........................................................................... 194

RRF .......................................................................... 194

SLEEP ...................................................................... 194

SUBLW..................................................................... 194

SUBWF..................................................................... 195

SWAPF..................................................................... 195

XORLW .................................................................... 195

XORWF .................................................................... 195

Summary Table ........................................................ 188

INTCON Register................................................................ 42

Internal Oscillator Block

A/D Conversion...........................................................83

Call of a Subroutine in Page 1 from Page 0................26

Changing Between Capture Prescalers....................129

Indirect Addressing .....................................................27

Initializing PORTA.......................................................52

Initializing PORTB.......................................................55

Initializing PORTC.......................................................59

Initializing PORTD.......................................................62

Initializing PORTE.......................................................65

Loading the SSPBUF (SSPSR) Register..................160

Saving W, STATUS and PCLATH Registers

in RAM ...............................................................41

Compare Module. See Capture/Compare/PWM (CCP)

CONFIG1 Register........................................................ 75, 76

Customer Change Notification Service .............................281

Customer Notification Service...........................................281

Customer Support.............................................................281

D

D/A bit ...............................................................................177

DACCON0 (Digital-to-Analog Converter Control 0)

Register.......................................................................93

DACCON1 (Digital-to-Analog Converter Control 1)

Register.......................................................................93

Data Memory.......................................................................17

Data/Address bit (D/A) ......................................................177

DC and AC Characteristics ...............................................231

DC Characteristics

Extended and Industrial ............................................208

Industrial and Extended ............................................202

Development Support .......................................................197

Device Configuration...........................................................75

Code Protection ..........................................................77

Configuration Word .....................................................75

User ID........................................................................77

Device Overview .................................................................11

Digital-to-Analog Converter (DAC)......................................91

Associated Registers ..................................................94

Effects of a Reset........................................................91

Operation During Sleep ..............................................91

INTOSC

E

Specifications ................................................... 215

Internal Sampling Switch (RSS) IMPEDANCE ........................ 86

Internet Address ............................................................... 281

Interrupts............................................................................. 39

EECON1 Register...............................................................22

Effects of Reset

PWM mode ...............................................................135

DS41418A-page 276

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

ADC ............................................................................ 82

Associated registers w/ Interrupts............................... 47

Configuration Word w/ LDO........................................ 49

Interrupt-on-Change.................................................... 55

Synchronous Serial Port Interrupt............................... 46

INTOSC Specifications ..................................................... 215

IOCB Register..................................................................... 57

PMADRH Register............................................................ 181

PMADRL Register ............................................................ 181

PMCON1 Register.................................................... 180, 181

PMDATH Register............................................................ 180

PMDATL Register............................................................. 180

PORTA ............................................................................... 52

ANSELA Register....................................................... 53

Associated Registers.................................................. 54

Pin Descriptions and Diagrams .................................. 53

PORTA Register......................................................... 19

RA0............................................................................. 53

RA3............................................................................. 54

RA4............................................................................. 54

RA5............................................................................. 54

RA6............................................................................. 54

RA7............................................................................. 54

Specifications ........................................................... 216

PORTA Register................................................................. 52

PORTB ............................................................................... 55

Additional Pin Functions

L

Load Conditions................................................................ 211

M

MCLR.................................................................................. 31

Internal........................................................................ 31

Memory Organization.......................................................... 17

Data ............................................................................ 17

Program ...................................................................... 17

Microchip Internet Web Site.............................................. 281

Migrating from other PIC Microcontroller Devices............. 273

MPLAB ASM30 Assembler, Linker, Librarian ................... 198

MPLAB Integrated Development Environment Software .. 197

MPLAB PM3 Device Programmer .................................... 200

MPLAB REAL ICE In-Circuit Emulator System................. 199

MPLINK Object Linker/MPLIB Object Librarian ................ 198

ANSELB Register................................... 55, 60, 65

Weak Pull-up ...................................................... 55

Associated Registers.................................................. 58

Interrupt-on-Change ................................................... 55

P1B/P1C/P1D.See Enhanced Capture/Compare/

O

PWM+ (ECCP+) ................................................. 55

Pin Descriptions and Diagrams .................................. 57

PORTB Register......................................................... 19

RB0............................................................................. 57

RB1............................................................................. 57

RB2............................................................................. 57

RB3............................................................................. 58

RB4............................................................................. 58

RB5............................................................................. 58

RB6............................................................................. 58

RB7............................................................................. 58

PORTB Register................................................................. 56

PORTC ............................................................................... 59

Associated Registers.................................................. 61

P1A.See Enhanced Capture/Compare/PWM+

(ECCP+)............................................................. 59

PORTC Register......................................................... 19

RC0 ............................................................................ 60

RC2 ............................................................................ 61

RC3 ............................................................................ 61

RC4 ............................................................................ 61

RC5 ............................................................................ 61

RC6 ............................................................................ 61

RC7 ............................................................................ 61

Specifications ........................................................... 216

PORTC Register................................................................. 59

PORTD ............................................................................... 62

Additional Pin Functions

OPCODE Field Descriptions............................................. 187

OPTION Register................................................................ 24

OPTION_REG Register ...................................................... 97

OSCCON Register.............................................................. 71

Oscillator

Associated registers............................................ 74, 115

Oscillator Module

EC............................................................................... 69

HS............................................................................... 69

INTOSC ...................................................................... 69

INTOSCIO................................................................... 69

LP................................................................................ 69

Oscillator Tuning......................................................... 72

RC............................................................................... 69

RCIO........................................................................... 69

XT ............................................................................... 69

Oscillator Parameters ....................................................... 215

Oscillator Specifications.................................................... 214

Oscillator Start-up Timer (OST)

Specifications............................................................ 218

OSCTUNE Register ............................................................ 72

P

P (Stop) bit........................................................................ 177

Packaging ......................................................................... 267

Marking ..................................................................... 267

PDIP Details.............................................................. 268

Paging, Program Memory................................................... 26

PCL and PCLATH............................................................... 26

Computed GOTO........................................................ 26

Stack........................................................................... 26

PCL Register................................................................. 19, 20

PCLATH Register ......................................................... 19, 20

PCON Register ....................................................... 20, 25, 34

PIE1 Register................................................................ 20, 43

PIE2 Register...................................................................... 20

Pinout Descriptions

ANSELD Register............................................... 62

Associated Registers.................................................. 64

P1B/P1C/P1D.See Enhanced Capture/Compare/

PWM+ (ECCP+) ................................................. 62

PORTD Register......................................................... 19

RD6 ...................................................................... 63, 64

PORTD Register................................................................. 62

PORTE ............................................................................... 65

Associated Registers.................................................. 67

PORTE Register......................................................... 19

RE0............................................................................. 66

RE1............................................................................. 66

PIC16F707/PIC16LF707............................................. 13

PIR1 Register................................................................ 19, 45

PIR2 Register................................................................ 19, 46

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 277

PIC16F707/PIC16LF707

RE2 .............................................................................66

RE3 .............................................................................67

PORTE Register .................................................................65

Power-Down Mode (Sleep)...............................................183

Associated Registers ................................................184

Power-on Reset ..................................................................31

Power-up Timer (PWRT).....................................................31

Specifications............................................................218

PR2 Register............................................................... 20, 166

Precision Internal Oscillator Parameters...........................215

Prescaler

Shared WDT/Timer0 ...........................................96, 112

Product Identification System............................................283

Program ..............................................................................17

Program Memory ................................................................17

Map and Stack (PIC16F707/PIC16LF707) .................17

Paging.........................................................................26

Program Memory Read (PMR) .........................................179

Associated Registers ................................................181

Programming, Device Instructions ....................................187

Reset Values (Special Registers)............................... 38

SSPCON (Sync Serial Port Control) Register .. 164, 176

SSPSTAT (Sync Serial Port Status) Register... 165, 177

STATUS ..................................................................... 23

T2CON ..................................................................... 116

TRISA (Tri-State PORTA)........................................... 52

TRISB (Tri-State PORTB)........................................... 56

TRISC (Tri-State PORTC) .......................................... 59

TRISD (Tri-State PORTD) .......................................... 63

TRISE (Tri-State PORTE)........................................... 66

TXSTA (Transmit Status and Control)...................... 145

WPUB (Weak Pull-up PORTB)................................... 56

Reset .................................................................................. 29

Resets

Associated Registers.................................................. 38

Revision History................................................................ 273

S

S (Start) bit........................................................................ 177

SMP bit ..................................................................... 165, 177

Software Simulator (MPLAB SIM) .................................... 199

SPBRG ............................................................................. 147

SPBRG Register................................................................. 20

Special Event Trigger ......................................................... 82

Special Function Registers................................................. 17

SPI Mode.......................................................................... 163

Associated Registers................................................ 166

Typical Master/Slave Connection ............................. 157

SSP................................................................................... 157

R

R/W bit ..............................................................................177

RCREG .............................................................................143

RCREG Register.................................................................19

RCSTA Register.......................................................... 19, 146

Reader Response .............................................................282

Read-Modify-Write Operations..........................................187

Receive Overflow Indicator bit (SSPOV)................... 164, 176

Registers

2

I C Mode .................................................................. 167

ADCON0 (ADC Control 0) ..........................................84

ADCON1 (ADC Control 1) ..........................................85

ADRES (ADC Result) .................................................85

ANSELA (PORTA Analog Select)...............................53

ANSELB (PORTB Analog Select)......................... 57, 60

ANSELD (PORTD Analog Select) ..............................63

ANSELE (PORTE Analog Select)...............................66

APFCON (Alternate Pin Function Control)..................51

CCPxCON (CCP Operation).....................................128

CONFIG1 (Configuration Word Register 1) .......... 75, 76

DACCON0 ..................................................................93

DACCON1 ..................................................................93

FVRCON (Fixed Voltage Reference Register) ...........90

INTCON (Interrupt Control).........................................42

IOCB (Interrupt-on-Change PORTB) ..........................57

OPTION_REG (OPTION) ...........................................24

OPTION_REG (Option) ..............................................97

OSCCON (Oscillator Control) .....................................71

OSCTUNE (Oscillator Tuning)....................................72

PCON (Power Control Register).................................25

PCON (Power Control) ...............................................34

PIE1 (Peripheral Interrupt Enable 1)...........................43

PIR1 (Peripheral Interrupt Register 1) ........................45

PIR2 (Peripheral Interrupt Request 2) ........................46

PMADRH (Program Memory Address High).............181

PMADRL (Program Memory Address Low) ..............181

PMCON1 (Program Memory Control 1)....................180

PMDATH (Program Memory Data High)...................180

PMDATL (Program Memory Data Low) ....................180

PORTA........................................................................52

PORTB........................................................................56

PORTC .......................................................................59

PORTD .......................................................................62

PORTE........................................................................65

RCSTA (Receive Status and Control).......................146

Reset Values...............................................................36

Acknowledge .................................................... 168

Addressing........................................................ 169

Clock Stretching ............................................... 174

Clock Synchronization...................................... 175

Firmware Master Mode..................................... 174

Hardware Setup................................................ 167

Multi-Master Mode............................................ 174

Reception ......................................................... 170

Sleep Operation................................................ 175

Start/Stop Conditions........................................ 168

Transmission .................................................... 172

Master Mode............................................................. 158

SPI Mode.................................................................. 157

Slave Mode....................................................... 161

Typical SPI Master/Slave Connection ...................... 157

SSPADD Register............................................................... 20

SSPBUF Register............................................................... 19

SSPCON Register .............................................. 19, 164, 176

SSPEN bit................................................................. 164, 176

SSPIF ................................................................................. 46

SSPM bits................................................................. 164, 176

SSPOV bit................................................................. 164, 176

SSPSTAT Register............................................. 20, 165, 177

STATUS Register ............................................................... 23

Synchronous Serial Port Enable bit (SSPEN) .......... 164, 176

Synchronous Serial Port Interrupt....................................... 46

Synchronous Serial Port Mode Select bits (SSPM).. 164, 176

T

T1CON Register ........................................................... 19, 20

T2CON Register ................................................. 19, 116, 166

Thermal Considerations.................................................... 210

Time-out Sequence ............................................................ 34

Timer0................................................................................. 95

Associated Registers.......................................... 97, 113

Interrupt ...................................................................... 97

DS41418A-page 278

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

Operation .................................................... 96, 101, 112

Specifications............................................................ 219

Timer1................................................................................. 99

Asynchronous Counter Mode ................................... 102

Reading and Writing ......................................... 102

Modes of Operation .................................................. 101

Oscillator................................................................... 102

Prescaler................................................................... 102

Specifications............................................................ 219

TMR1H Register ......................................................... 99

TMR1L Register.......................................................... 99

Timer2

TRISA Register............................................................. 20, 52

TRISB ................................................................................. 55

TRISB Register............................................................. 20, 56

TRISC................................................................................. 59

TRISC Register............................................................. 20, 59

TRISD................................................................................. 62

TRISD Register............................................................. 20, 63

TRISE ................................................................................. 65

TRISE Register............................................................. 20, 66

TXREG ............................................................................. 139

TXREG Register................................................................. 19

TXSTA Register.......................................................... 20, 145

BRGH Bit.................................................................. 147

Associated registers.................................................. 116

Timers

U

Timer2

UA..................................................................................... 177

Update Address bit, UA.................................................... 177

USART

T2CON.............................................................. 116

Timing Diagrams

A/D Conversion......................................................... 221

A/D Conversion (Sleep Mode) .................................. 222

Asynchronous Reception.......................................... 144

Asynchronous Transmission..................................... 140

Asynchronous Transmission (Back-to-Back)............ 140

Brown-out Reset (BOR)............................................ 217

Brown-out Reset Situations ........................................ 33

CLKOUT and I/O....................................................... 215

Clock Synchronization .............................................. 175

Clock Timing ............................................................. 212

Enhanced Capture/Compare/PWM (ECCP)............. 220

Synchronous Master Mode

Requirements, Synchronous Receive .............. 223

Requirements, Synchronous Transmission...... 222

Timing Diagram, Synchronous Receive ........... 223

Timing Diagram, Synchronous Transmission... 222

V

VREF. SEE ADC Reference Voltage

W

2

Wake-up Using Interrupts................................................. 184

Watchdog Timer (WDT)...................................................... 31

Clock Source .............................................................. 31

Modes......................................................................... 32

Period ......................................................................... 31

Specifications ........................................................... 218

WCOL bit .................................................................. 164, 176

WPUB Register................................................................... 56

Write Collision Detect bit (WCOL) ............................ 164, 176

WWW Address ................................................................. 281

WWW, On-Line Support ....................................................... 9

I C Bus Data............................................................. 227

2

I C Bus Start/Stop Bits.............................................. 226

2

I C Reception (7-bit Address)................................... 170

2

I C Slave Mode with SEN = 0 (Reception,

10-bit Address) ................................................. 171

I C Transmission (7-bit Address).............................. 172

2

INT Pin Interrupt.......................................................... 40

Reset, WDT, OST and Power-up Timer ................... 217

Slave Select Synchronization ................................... 163

SPI Master Mode ...................................................... 160

SPI Master Mode (CKE = 1, SMP = 1) ..................... 224

SPI Mode (Slave Mode with CKE = 0)...................... 162

SPI Mode (Slave Mode with CKE = 1)...................... 162

SPI Slave Mode (CKE = 0) ....................................... 224

SPI Slave Mode (CKE = 1) ....................................... 225

Synchronous Reception (Master Mode, SREN) ....... 153

Synchronous Transmission....................................... 151

Synchronous Transmission (Through TXEN) ........... 151

Time-out Sequence

Case 1 ................................................................ 34

Case 2 ................................................................ 35

Case 3 ................................................................ 35

Timer0 and Timer1 External Clock ........................... 219

USART Synchronous Receive (Master/Slave) ......... 223

USART Synchronous Transmission (Master/Slave). 222

Wake-up from Interrupt............................................. 184

Timing Parameter Symbology........................................... 211

Timing Requirements

2

I C Bus Data............................................................. 228

I2C Bus Start/Stop Bits ............................................. 227

SPI Mode .................................................................. 226

TMR0 Register.................................................................... 19

TMR1H Register ........................................................... 19, 20

TMR1L Register............................................................ 19, 20

TMR2 Register.................................................................... 19

TMRO Register ................................................................... 21

TRISA ................................................................................. 52

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 279

PIC16F707/PIC16LF707

NOTES:

DS41418A-page 280

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

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Users of Microchip products can receive assistance

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• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 281

PIC16F707/PIC16LF707

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

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Reader Response

Total Pages Sent ________

RE:

From:

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Company

Address

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Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

PIC16F707/PIC16LF707

DS41418A

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS41418A-page 282

Preliminary

 2010 Microchip Technology Inc.

PIC16F707/PIC16LF707

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature

Range

Package

Pattern

a)

PIC16F707-E/P 301 = Extended Temp., PDIP

package, QTP pattern #301

b)

PIC16F707-I/ML

package

= Industrial Temp., QFN

Device:

PIC16F707, PIC16LF707, PIC16F707T, PIC16LF707T⁽¹⁾

Temperature

Range:

I

E

=

-40C to +85C

-40C to +125C

Package:

MV

ML

P

=

Micro Lead Frame (UQFN)

Micro Lead Frame (QFN)

Plastic DIP

PT

TQFP (Thin Quad Flatpack)

Pattern:

3-Digit Pattern Code for QTP (blank otherwise)

Note 1:

T

= In tape and reel.

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 283

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

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Fax: 61-2-9868-6755

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Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

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Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

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Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

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Tel: 86-23-8980-9588

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Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

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Tel: 630-285-0071

Fax: 630-285-0075

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Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

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Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Cleveland

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

01/05/10

DS41418A-page 284

Preliminary

 2010 Microchip Technology Inc.


型号：	PIC16F707T-I/PT
厂家：	MICROCHIP
描述：	40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouchâ¢ Technology 微控制器
文件：	总284页 (文件大小：3135K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16F707T-I/PT [MICROCHIP]

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