PIC16F506-E/PQTP [MICROCHIP]
8/14-Pin, 8-Bit Flash Microcontroller; 8月14日引脚, 8位闪存微控制器型号: | PIC16F506-E/PQTP |
厂家: | MICROCHIP |
描述: | 8/14-Pin, 8-Bit Flash Microcontroller |
文件: | 总114页 (文件大小:1604K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC12F510/16F506
Data Sheet
8/14-Pin, 8-Bit Flash Microcontroller
*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
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RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
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Microchip disclaims all liability arising from this information and
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use. No licenses are conveyed, implicitly or otherwise, under
any Microchip intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and Zena are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41268B-page ii
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
8/14-Pin, 8-Bit Flash Microcontroller
• Selectable oscillator options:
Devices Included In This Data Sheet:
- INTOSC: 4/8 MHz precision Internal
oscillator
• PIC16F506
• PIC12F510
- EXTRC: External low-cost RC oscillator
- XT: Standard crystal/resonator
- LP: Power-saving, low-frequency crystal
- HS: High-speed crystal/resonator
(PIC16F506 only)
High-Performance RISC CPU:
• Only 33 single-word instructions to learn
• All single-cycle instructions except for program
branches, which are two-cycle
- EC: High-speed external clock input
(PIC16F506 only)
• 12-bit wide instructions
• Analog-to-Digital (A/D) Converter:
• 2-level deep hardware stack
- 8-bit resolution
• Direct, Indirect and Relative Addressing modes
for data and instructions
- 4-input channels (1 channel is dedicated to
conversion of the internal 0.6V absolute
voltage reference)
• 8-bit wide data path
• High current sink/source for direct LED drive
• 10 Special Function Hardware registers
(PIC12F510)
• 8-bit real-time clock/counter (TMR0) with 8-bit
programmable prescaler
• 13 Special Function Hardware registers
(PIC16F506)
Low-Power Features/CMOS Technology:
• Operating speed:
- DC – 8 MHz Crystal Oscillator (PIC12F510)
- DC – 500 ns instruction cycle (PIC12F510)
- DC – 20 MHz Crystal Oscillator (PIC16F506)
- DC – 200 ns instruction cycle (PIC16F506)
• Operating Current:
- < 170 μA @ 2V, 4 MHz
• Standby Current:
- 100 nA @ 2V, typical
• Low-power, high-speed Flash technology:
Special Microcontroller Features:
- 100,000 cycle Flash endurance
- > 40-year retention
• 4 or 8 MHz selectable precision internal oscillator:
- Factory calibrated to ±1%
• Fully static design
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Debugging (ICD) support
• Power-on Reset (POR)
• Wide operating voltage range: 2.0V to 5.5V
• Wide temperature range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
• Device Reset Timer (DRT):
- Short DRT (1.125 ms, typical) for INTOSC,
EXTRC and EC
Peripheral Features (PIC12F510):
- DRT (18 ms, typical) for HS, XT and LP
• 6 I/O pins:
• Watchdog Timer (WDT) with dedicated on-chip
RC oscillator for reliable operation
- 5 I/O pins with individual direction control
- 1 input only pin
• Programmable code protection
• 1 Analog Comparator with absolute reference
• Multiplexed MCLR input pin
• Selectable internal weak pull-ups on I/O pins
• Power-Saving Sleep mode
Peripheral Features (PIC16F506):
• 12 I/O pins:
• Wake-up from Sleep on pin change
• Wake-up from Sleep on comparator change
- 11 I/O pins with individual direction control
- 1 input only pin
• 2 Analog Comparators with absolute reference
and programmable reference
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 1
PIC12F510/16F506
Program Memory
Data Memory
SRAM (bytes)
Timers
8-bit
Device
I/O
Flash (words)
PIC16F506
PIC12F510
1024
1024
67
38
12
6
1
1
Pin Diagrams
PDIP, SOIC and TSSOP
VSS
14
VDD
1
2
3
4
5
6
7
RB0/AN0/C1IN+/ICSPDAT
RB1/AN1/C1IN-/ICSPCLK
RB2/AN2/C1OUT
RC0/C2IN+
RB5/OSC1/CLKIN
RB4/OSC2/CLKOUT
RB3/MCLR/VPP
RC5/T0CKI
13
12
11
10
9
RC1/C2IN-
RC4/C2OUT
8
RC2/CVREF
RC3
PDIP, SOIC, MSOP
VSS
VDD
GP5/OSC1/CLKIN
GP4/OSC2
1
2
3
4
8
7
6
5
GP0/AN0/C1IN+/ICSPDAT
GP1/AN1/C1IN-/ICSPCLK
GP2/AN2/T0CKI/C1OUT
GP3/MCLR/VPP
DS41268B-page 2
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC12F510/16F506 Device Varieties .......................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization................................................................................................................................................................. 15
5.0 I/O Port....................................................................................................................................................................................... 27
6.0 TMR0 Module and TMR0 Register............................................................................................................................................. 39
7.0 Comparator(s) ............................................................................................................................................................................ 43
8.0 Comparator Voltage Reference Module (PIC16F506 only)........................................................................................................ 49
9.0 Analog-to-Digital (A/D) Converter............................................................................................................................................... 51
10.0 Special Features Of The CPU.................................................................................................................................................... 55
11.0 Instruction Set Summary............................................................................................................................................................ 71
12.0 Development Support................................................................................................................................................................. 79
13.0 Electrical Characteristics............................................................................................................................................................ 83
14.0 DC and AC Characteristics Graphs and Charts......................................................................................................................... 96
15.0 Packaging................................................................................................................................................................................... 98
Index .................................................................................................................................................................................................. 107
The Microchip Web Site..................................................................................................................................................................... 109
Customer Change Notification Service .............................................................................................................................................. 109
Customer Support.............................................................................................................................................................................. 109
Reader Response.............................................................................................................................................................................. 110
Product Identification System ............................................................................................................................................................ 111
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 3
PIC12F510/16F506
NOTES:
DS41268B-page 4
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
1.1
Applications
1.0
GENERAL DESCRIPTION
The PIC12F510/16F506 devices fit in applications
ranging from personal care appliances and security
systems to low-power remote transmitters/receivers.
The Flash technology makes customizing application
programs (transmitter codes, appliance settings,
receiver frequencies, etc.) extremely fast and conve-
nient. The small footprint packages, for through hole or
surface mounting, make these microcontrollers perfect
for applications with space limitations. Low-cost, low-
power, high-performance, ease-of-use and I/O flexibil-
ity make the PIC12F510/16F506 devices very versa-
tile, even in areas where no microcontroller use has
been considered before (e.g., timer functions, logic and
PLDs in larger systems and coprocessor applications).
The PIC12F510/16F506 devices from Microchip
Technology are low-cost, high-performance, 8-bit, fully-
static, Flash-based CMOS microcontrollers. They
employ a RISC architecture with only 33 single-word/
single-cycle instructions. All instructions are single-
cycle except for program branches, which take two
cycles. The PIC12F510/16F506 devices deliver
performance in an order of magnitude higher than their
competitors in the same price category. The 12-bit wide
instructions are highly symmetrical, resulting in a
typical 2:1 code compression over other 8-bit
microcontrollers in its class. The easy-to-use and easy-
to-remember instruction set reduces development time
significantly.
The PIC12F510/16F506 products are equipped with
special features that reduce system cost and power
requirements. The Power-on Reset (POR) and Device
Reset Timer (DRT) eliminate the need for external
Reset circuitry. There are four oscillator configurations
to choose from (six on the PIC16F506), including
INTOSC Internal Oscillator mode and the power-saving
LP (Low-power) Oscillator mode. Power-saving Sleep
mode, Watchdog Timer and code protection features
improve system cost, power and reliability.
The PIC12F510/16F506 devices allow the customer to
take full advantage of Microchip’s price leadership in
Flash programmable microcontrollers, while benefiting
from the Flash programmable flexibility.
The PIC12F510/16F506 products are supported by a
full-featured macro assembler, a software simulator, an
in-circuit emulator,
a
‘C’ compiler,
a
low-cost
development programmer and a full featured program-
mer. All the tools are supported on IBM® PC and
compatible machines.
TABLE 1-1:
PIC12F510/16F506 DEVICES
PIC16F506
PIC12F510
Clock
Maximum Frequency of Operation (MHz)
Flash Program Memory
Data Memory (bytes)
Timer Module(s)
20
1024
67
8
Memory
1024
38
Peripherals
Features
TMR0
Yes
11
TMR0
Wake-up from Sleep on Pin Change
I/O Pins
Yes
5
Input Only Pin
1
1
Internal Pull-ups
Yes
Yes
33
Yes
In-Circuit Serial Programming
Number of Instructions
Packages
Yes
33
14-pin PDIP, SOIC,
TSSOP
8-pin PDIP, SOIC, MSOP
The PIC12F510/16F506 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current
capability and precision internal oscillator.
The PIC12F510/16F506 device uses serial programming with data pin RB0/GP0 and clock pin RB1/GP1.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 5
PIC12F510/16F506
NOTES:
DS41268B-page 6
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
2.2
Serialized Quick Turn
ProgrammingSM (SQTPSM) Devices
2.0
PIC12F510/16F506 DEVICE
VARIETIES
Microchip offers a unique programming service, where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
A variety of packaging options are available. Depend-
ing on application and production requirements, the
proper device option can be selected using the
information in this section. When placing orders, please
use the PIC12F510/16F506 Product Identification
System at the back of this data sheet to specify the
correct part number.
Serial programming allows each device to have a
unique number, which can serve as an entry code,
password or ID number.
2.1
Quick Turn Programming (QTP)
Devices
Microchip offers a QTP programming service for
factory production orders. This service is made
available for users who choose not to program
medium-to-high quantity units and whose code
patterns have stabilized. The devices are identical to
the Flash devices, but with all Flash locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please
contact your local Microchip Technology sales office for
more details.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 7
PIC12F510/16F506
NOTES:
DS41268B-page 8
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
The ALU is 8 bits wide and capable of addition, subtrac-
tion, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two’s comple-
ment in nature. In two-operand instructions, one
operand is typically the W (working) register. The other
operand is either a file register or an immediate
constant. In single-operand instructions, the operand is
either the W register or a file register.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC12F510/16F506
devices can be attributed to a number of architectural
features commonly found in RISC microprocessors.
The PIC12F510/16F506 devices use a Harvard archi-
tecture in which program and data are accessed on
separate buses. This improves bandwidth over tradi-
tional von Neumann architectures where program and
data are fetched on the same bus. Separating program
and data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12 bits wide, making it possible to have all
single-word instructions. A 12-bit wide program mem-
ory access bus fetches a 12-bit instruction in a single
cycle. A two-stage pipeline overlaps fetch and execu-
tion of instructions. Consequently, all instructions (33)
execute in a single cycle (200 ns @ 20 MHz, 1 μs @
4 MHz) except for program branches.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC) and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit, respec-
tively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1 for
PIC12F510 with the corresponding device pins
described in Table 3-2. A simplified block diagram for
PIC16F506 is shown in Figure 3-2 with the
corresponding device pins described in Table 3-3.
Table 3-1 lists program memory (Flash) and data
memory (RAM) for the PIC12F510/16F506 devices.
TABLE 3-1:
Device
PIC12F510/16F506 MEMORY
Memory
Program
Data
PIC12F510
PIC16F506
1024 x 12
1024 x 12
38 x 8
67 x 8
The PIC12F510/16F506 devices can directly or indi-
rectly address its register files and data memory. All
Special Function Registers (SFR), including the PC,
are mapped in the data memory. The PIC12F510/
16F506 devices have a highly orthogonal (symmetri-
cal) instruction set that makes it possible to carry out
any operation, on any register, using any addressing
mode. This symmetrical nature and lack of “special
optimal situations” make programming with the
PIC12F510/16F506 devices simple, yet efficient. In
addition, the learning curve is reduced significantly.
The PIC12F510/16F506 devices contain an 8-bit ALU
and working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 9
PIC12F510/16F506
FIGURE 3-1:
PIC12F510 SERIES BLOCK DIAGRAM
10-11
8
GPIO
Data Bus
Program Counter
Flash
1K x 12
GP0/ICSPDAT
GP1/ICSPCLK
GP2
GP3
GP4
RAM
STACK 1
STACK 2
Program
Memory
38 bytes
File
Registers
GP5
Program
Bus
12
RAM Addr
9
Addr MUX
Instruction Reg
Indirect
Addr
5
Direct Addr
5-7
FSR Reg
STATUS Reg
8
3
MUX
Device Reset
Timer
C1IN+
Instruction
Decode &
Control
Power-on
Reset
Comparator
C1IN-
ALU
C1OUT
8
Watchdog
Timer
Timing
Generation
W Reg
OSC1/CLKIN
OSC2
Internal RC
Clock
VREF
AN0
AN1
AN2
Timer0
8-bit ADC
VDD, VSS
MCLR
T0CKI
DS41268B-page 10
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
TABLE 3-2:
Name
PIN DESCRIPTIONS – PIC12F510
I/O/P Type Input Type
Output
Type
Description
GP0/AN0/C1IN+/ICSPDAT
GP0
TTL
CMOS Bidirectional I/O port. Can be software pro-
grammed for internal weak pull-up and wake-up
from Sleep on pin change.
AN0
C1IN+
ICSPDAT
GP1
AN
AN
ST
—
—
ADC channel input.
Comparator input.
CMOS In-Circuit Serial Programming data pin.
GP1/AN1/C1IN-/ICSPCLK
TTL
CMOS Bidirectional I/O port. Can be software pro-
grammed for internal weak pull-up and wake-up
from Sleep on pin change.
AN1
C1IN-
ICSPCLK
GP2
AN
AN
ST
—
—
—
ADC channel input.
Comparator input.
In-Circuit Serial Programming clock pin.
GP2/AN2/T0CKI/C1OUT
GP3/MCLR/VPP
TTL
AN
ST
CMOS Bidirectional I/O port.
AN2
—
—
ADC channel input.
Timer0 clock input.
T0CKI
C1OUT
GP3
—
CMOS Comparator output.
TTL
—
Standard TTL input. Can be software pro-
grammed for internal weak pull-up and wake-up
from Sleep on pin change.
MCLR
ST
—
—
MCLR input – weak pull-up always enabled in
this mode.
VPP
GP4
High Voltage
Programming Voltage input.
GP4/OSC2
TTL
—
CMOS Bidirectional I/O port.
XTAL XTAL oscillator output pin.
CMOS Bidirectional I/O port.
OSC2
GP5
GP5/OSC1/CLKIN
TTL
XTAL
ST
OSC1
CLKIN
VDD
—
—
—
—
XTAL oscillator input pin.
EXTRC Schmitt Trigger input.
VDD
VSS
P
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
VSS
P
Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger
input, AN = Analog Voltage
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 11
PIC12F510/16F506
FIGURE 3-2:
PIC16F506 SERIES BLOCK DIAGRAM
10
8
PORTB
Data Bus
Program Counter
RB0/ICSPDAT
RB1/ICSPCLK
RB2
RB3
RB4
Flash
1K x 12
Program
Memory
RAM
67 bytes
File
Registers
STACK 1
STACK 2
RB5
Program
Bus
10
RAM Addr
9
PORTC
Addr MUX
Instruction Reg
RC0
RC1
RC2
RC3
RC4
RC5
Indirect
Addr
5
Direct Addr
5-7
FSR Reg
STATUS Reg
8
C1IN+
Comparator 1
C1IN-
C1OUT
3
MUX
Device Reset
Timer
VREF
Instruction
Decode &
Control
Power-on
Reset
C2IN+
C2IN-
ALU
Comparator 2
8
Watchdog
Timer
C2OUT
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
W Reg
Internal RC
Clock
CVREF
CVREF
CVREF
Timer0
AN0
AN1
AN2
VDD, VSS
MCLR
8-bit ADC
VREF
T0CKI
DS41268B-page 12
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
TABLE 3-3:
Name
PIN DESCRIPTIONS – PIC16F506
Output
Type
Function Input Type
Description
RB0/AN0/C1IN+/ICSPDAT
RB0
TTL
CMOS Bidirectional I/O port. Can be software pro-
grammed for internal weak pull-up and wake-up
from Sleep on pin change.
AN0
C1IN+
ICSPDAT
RB1
AN
AN
ST
—
—
ADC channel input.
Comparator 1 input.
CMOS In-Circuit Serial Programming data pin.
RB1/AN1/C1IN-/ICSPCLK
TTL
CMOS Bidirectional I/O port. Can be software pro-
grammed for internal weak pull-up and wake-up
from Sleep on pin change.
AN1
C1IN-
ICSPCLK
RB2
AN
AN
ST
—
—
—
ADC channel input.
Comparator 1 input.
In-Circuit Serial Programming clock pin.
RB2/AN2/C1OUT
RB3/MCLR/VPP
TTL
AN
—
CMOS Bidirectional I/O port.
ADC channel input.
CMOS Comparator 1 output.
AN2
—
C1OUT
RB3
TTL
—
Standard TTL input. Can be software programmed
for internal weak pull-up and wake-up from Sleep
on pin change.
MCLR
ST
—
—
MCLR input – weak pull-up always enabled in this
mode.
VPP
High Voltage
TTL
Programming voltage input.
RB4/OSC2/CLKOUT
RB5/OSC1/CLKIN
RB4
CMOS Bidirectional I/O port. Can be software pro-
grammed for internal weak pull-up and wake-up
from Sleep on pin change.
OSC2
CLKOUT
RB5
—
—
XTAL XTAL oscillator output pin.
CMOS EXTRC/INTOSC CLKOUT pin (FOSC/4).
CMOS Bidirectional I/O port.
TTL
XTAL
ST
OSC1
CLKIN
RC0
—
—
XTAL oscillator input pin.
EXTRC/EC Schmitt Trigger input.
RC0/C2IN+
RC1/C2IN-
RC2/CVREF
TTL
AN
TTL
AN
TTL
—
CMOS Bidirectional I/O port.
Comparator 2 input.
CMOS Bidirectional I/O port.
Comparator 2 input.
CMOS Bidirectional I/O port.
C2IN+
RC1
—
C2IN-
RC2
—
CVREF
RC3
AN
Programmable Voltage Reference output.
RC3
TTL
TTL
—
CMOS Bidirectional I/O port.
CMOS Bidirectional I/O port.
CMOS Comparator 2 output.
CMOS Bidirectional I/O port.
RC4/C2OUT
RC4
C2OUT
RC5
RC5/T0CKI
TTL
ST
T0CKI
VDD
—
—
—
Timer0 clock input.
VDD
VSS
P
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
VSS
P
Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger
input, AN = Analog Voltage
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 13
PIC12F510/16F506
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO), then two cycles
are required to complete the instruction (Example 3-1).
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC
is incremented every Q1 and the instruction is fetched
from program memory and latched into the instruction
register in Q4. It is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-3 and Example 3-1.
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-3:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
PC
Internal
Phase
Clock
PC
PC + 1
PC + 2
Fetch INST (PC)
Execute INST (PC – 1)
Fetch INST (PC + 1)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 1)
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
1. MOVLW 03H
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
4. BSF PORTB, BIT1
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
DS41268B-page 14
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F510/16F506
4.0
MEMORY ORGANIZATION
The PIC12F510/16F506 memories are organized into
program memory and data memory. For devices with
more than 512 bytes of program memory, a paging
scheme is used. Program memory pages are accessed
using STATUS register bit PA0. For the PIC12F510 and
PIC16F506, with data memory register files of more
than 32 registers, a banking scheme is used. Data
memory banks are accessed using the File Select
Register (FSR).
PC<11:0>
10
CALL, RETLW
Stack Level 1
Stack Level 2
(1)
Reset Vector
0000h
4.1
Program Memory Organization for
the PIC12F510/16F506
On-chip Program
Memory
The PIC12F510/16F506 devices have
a
10-bit
Program Counter (PC) capable of addressing a 2K x 12
program memory space.
512 Word
01FFh
0200h
Only the first 1K x 12 (0000h-03FFh) are physically
implemented (see Figure 4-1). Accessing a location
above these boundaries will cause a wraparound
within the 1K x 12 space. The effective Reset vector
is a 0000h (see Figure 4-1). Location 03FFh contains
the internal clock oscillator calibration value. This
value should never be overwritten.
On-chip Program
Memory
1024 Word
03FFh
0400h
7FFh
Note 1: Address 0000h becomes the effective
Reset vector. Location 03FFh contains
the MOVLW XXinternal oscillator
calibration value.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 15
PIC12F510/16F506
FIGURE 4-2:
PIC12F510 REGISTER
FILE MAP
4.2
Data Memory Organization
Data memory is composed of registers or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: Special Function Registers (SFR)
and General Purpose Registers (GPR).
FSR<5>
File Address
00h
0
1
INDF(1)
TMR0
20h
01h
02h
03h
04h
05h
06h
The Special Function Registers include the TMR0
register, the Program Counter (PCL), the STATUS
register, the I/O registers (ports) and the File Select
Register (FSR). In addition, Special Function Registers
are used to control the I/O port configuration and
prescaler options.
PCL
Addresses
map back to
addresses in
Bank 0.
STATUS
FSR
OSCCAL
GPIO
The General Purpose Registers are used for data and
control information under command of the instructions.
CM1CON0
07h
08h
ADCON0
ADRES
For the PIC12F510, the register file is composed of 10
Special Function Registers,
Registers and 32 General Purpose Registers accessed
by banking (see Figure 4-2).
09h
0Ah
6 General Purpose
General
Purpose
Registers
0Fh
10h
2Fh
30h
For the PIC16F506, the register file is composed of 13
Special Function Registers,
3 General Purpose
General
Purpose
Registers
General
Purpose
Registers
Registers and 64 General Purpose Registers accessed
by banking (see Figure 4-3).
4.2.1
GENERAL PURPOSE REGISTER
FILE
1Fh
3Fh
The General Purpose Register file is accessed either
directly or indirectly through the File Select Register
(FSR). See Section 4.8 “Indirect Data Addressing:
INDF and FSR Registers”.
Bank 0
Bank 1
Note 1: Not a physical register.
FIGURE 4-3:
PIC16F506 REGISTER FILE MAP
FSR<6:5>
File Address
00h
00
01
10
11
INDF(1)
TMR0
20h
40h
60h
01h
02h
PCL
03h
04h
STATUS
FSR
OSCCAL
05h
06h
07h
Addresses map back to
addresses in Bank 0.
PORTB
PORTC
CM1CON0
ADCON0
ADRES
08h
09h
0Ah
CM2CON0
VRCON
0Bh
0Ch
0Dh
General
Purpose
Registers
0Fh
10h
2Fh
30h
4Fh
50h
6Fh
70h
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
5Fh
7Fh
1Fh
3Fh
Bank 0
Bank 1
Bank 2
Bank 3
Note 1: Not a physical register.
DS41268B-page 16
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control the
operation of the device (see Table 4-1).
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY – PIC12F510
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-on
Reset
N/A
N/A
00h
01h
02h
TRIS
I/O Control Registers (TRISGPIO)
--11 1111
1111 1111
xxxx xxxx
xxxx xxxx
1111 1111
OPTION
INDF
Contains control bits to configure Timer0 and Timer0/WDT Prescaler
Uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
TMR0
PCL
(1)
Low Order 8 bits of PC
03h
STATUS
GPWUF
CWUF
PA0
TO
PD
Z
DC
C
0001 1xxx
100x xxxx
04h
05h
06h
FSR
Indirect Data Memory Address Pointer
OSCCAL
GPIO
CAL6
—
CAL5
—
CAL4
GP5
CAL3
GP4
CAL2
GP3
CAL1
GP2
CAL0
GP1
—
1111 111-
--xx xxxx
GP0
07h
CM1CON0
C1OUT
ANS1
C1OUTEN C1POL
ANS0 ADCS1
C1T0CS
ADCS0
C1ON
CHS1
C1NREF
CHS0
C1PREF
C1WU
ADON
1111 1111
08h
09h
ADCON0
ADRES
GO/DONE
1111 1100
xxxx xxxx
ADC Conversion Result
Legend:
Note 1:
x= unknown, u= unchanged, – = unimplemented, read as ‘0’ (if applicable). Shaded cells = unimplemented or unused.
The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of
how to access these bits.
TABLE 4-2:
SPECIAL FUNCTION REGISTER SUMMARY – PIC16F506
Value on
Power-on
Reset
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N/A
N/A
00h
01h
02h
TRIS
I/O Control Registers (TRISB, TRISC)
--11 1111
1111 1111
xxxx xxxx
xxxx xxxx
1111 1111
OPTION
INDF
Contains control bits to configure Timer0 and Timer0/WDT Prescaler
Uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
TMR0
PCL
(1)
Low Order 8 bits of PC
03h
04h
05h
06h
07h
STATUS
FSR
RBWUF
CWUF
PA0
TO
PD
Z
DC
C
0001 1xxx
100x xxxx
1111 111-
--xx xxxx
--xx xxxx
Indirect Data Memory Address Pointer
OSCCAL
PORTB
PORTC
CAL6
—
CAL5
—
CAL4
RB5
CAL3
RB4
CAL2
RB3
CAL1
RB2
CAL0
RB1
—
RB0
RC0
—
—
RC5
RC4
RC3
RC2
RC1
08h
09h
CM1CON0
C1OUT
ANS1
C1OUTEN
ANS0
C1POL
ADCS1
C1T0CS
ADCS0
C1ON
CHS1
C1NREF
CHS0
C1PREF
C1WU
ADON
1111 1111
ADCON0
ADRES
GO/DONE
1111 1100
xxxx xxxx
0Ah
ADC Conversion Result
0Bh
0Ch
CM2CON0
VRCON
C2OUT
VREN
C2OUTEN
VROE
C2POL
VRR
C2PREF2
—
C2ON
VR3
C2NREF
VR2
C2PREF1
VR1
C2WU
VR0
1111 1111
001- 1111
Legend:
Note 1:
x= unknown, u= unchanged, – = unimplemented, read as ‘0’ (if applicable). Shaded cells = unimplemented or unused.
The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of
how to access these bits.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 17
PIC12F510/16F506
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
4.3
STATUS Register
This register contains the arithmetic status of the ALU,
the Reset status and the page preselect bit.
Therefore, it is recommended that only BCF, BSFand
MOVWFinstructions be used to alter the STATUS regis-
ter. These instructions do not affect the Z, DC or C bits
from the STATUS register. For other instructions which
do affect Status bits, see Section 11.0 “Instruction
Set Summary”.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 4-1:
STATUS REGISTER (ADDRESS: 03h) (PIC12F510)
R/W-0
R/W-0
CWUF
R/W-0
PA0
R-1
TO
R-1
PD
R/W-X
Z
R/W-X
DC
R/W-X
C
GPWUF
bit 7
bit 0
bit 7
bit 6
bit 5
GPWUF: GPIO Reset bit
1= Reset due to wake-up from Sleep on pin change
0= After power-up or other Reset
CWUF: Comparator Reset bit
1= Reset due to wake-up from Sleep on comparator change
0= After power-up or other Reset
PA0: Program Page Preselect bit
1= Page 1 (200h-3FFh)
0= Page 0 (000h-1FFh)
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page
preselect is not recommended, since this may affect upward compatibility with future products.
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)
ADDWF:
1= A carry from the 4th low-order bit of the result occurred
0= A carry from the 4th low-order bit of the result did not occur
SUBWF:
1= A borrow from the 4th low-order bit of the result did not occur
0= A borrow from the 4th low-order bit of the result occurred
bit 0
C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)
ADDWF:
SUBWF:
RRF or RLF:
1= A carry occurred
0= A carry did not occur
1= A borrow did not occur
0= A borrow occurred
Load bit with LSb or MSb, respectively
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DS41268B-page 18
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
REGISTER 4-2:
STATUS REGISTER (ADDRESS: 03h) (PIC16F506)
R/W-0
R/W-0
CWUF
R/W-0
PA0
R-1
TO
R-1
PD
R/W-X
Z
R/W-X
DC
R/W-X
C
RBWUF
bit 7
bit 0
bit 7
bit 6
bit 5
RBWUF: PORTB Reset bit
1= Reset due to wake-up from Sleep on pin change
0= After power-up or other Reset
CWUF: Comparator Reset bit
1= Reset due to wake-up from Sleep on comparator change
0= After power-up or other Reset
PA0: Program Page Preselect bits
1= Page 1 (200h-3FFh)
0= Page 0 (000h-1FFh)
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page pre-
select is not recommended, since this may affect upward compatibility with future products.
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)
ADDWF:
1= A carry from the 4th low-order bit of the result occurred
0= A carry from the 4th low-order bit of the result did not occur
SUBWF:
1= A borrow from the 4th low-order bit of the result did not occur
0= A borrow from the 4th low-order bit of the result occurred
bit 0
C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)
ADDWF:
SUBWF:
RRF or RLF:
1= A carry occurred
0= A carry did not occur
1= A borrow did not occur
0= A borrow occurred
Load bit with LSb or MSb, respectively
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 19
PIC12F510/16F506
4.4
OPTION Register
The OPTION register is a 8-bit wide, write-only register,
that contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A Reset sets the OPTION<7:0> bits.
Note 1: If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are
disabled for that pin (i.e., note that TRIS
overrides Option control of GPPU/RBPU
and GPWU/RBWU).
2: If the T0CS bit is set to ‘1’, it will override
the TRIS function on the T0CKI pin.
REGISTER 4-3:
OPTION REGISTER (PIC12F510)
W-1
W-1
W-1
W-1
W-1
W-1
PS2
W-1
PS1
W-1
PS0
GPWU
GPPU
T0CS
T0SE
PSA
bit 7
bit 0
bit 7
bit 6
GPWU: Enable Wake-up On Pin Change bit (GP0, GP1, GP3)
1= Disabled
0= Enabled
GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3)
1= Disabled
0= Enabled
bit 5
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1= Prescaler assigned to the WDT
0= Prescaler assigned to Timer0
bit 2-0
PS<2:0>: Prescaler Rate Select bits
Bit Value
Timer0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41268B-page 20
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
REGISTER 4-4:
OPTION REGISTER (PIC16F506)
W-1
W-1
W-1
W-1
W-1
W-1
PS2
W-1
PS1
W-1
PS0
RBWU
RBPU
T0CS
T0SE
PSA
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBWU: Enable Wake-up On Pin Change bit (RB0, RB1, RB3, RB4)
1= Disabled
0= Enabled
RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4)
1= Disabled
0= Enabled
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler assigned to the WDT
0= Prescaler assigned to Timer0
PS<2:0>: Prescaler Rate Select bits
Bit Value
Timer0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 21
PIC12F510/16F506
4.5
OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to
calibrate the internal precision 4/8 MHz oscillator. It
contains seven bits for calibration.
Note:
Erasing the device will also erase the pre-
programmed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
After you move in the calibration constant, do not change
the value. See Section 10.2.5 “Internal 4/8 MHz RC
Oscillator”.
REGISTER 4-5:
OSCCAL REGISTER (ADDRESS: 05h)
R/W-1
CAL6
R/W-1
CAL5
R/W-1
CAL4
R/W-1
CAL3
R/W-1
CAL2
R/W-1
CAL1
R/W-1
CAL0
U-0
—
bit 7
bit 0
bit 7-1
CAL<6:0>: Oscillator Calibration bits
0111111= Maximum frequency
•
•
•
0000001
0000000= Center frequency
1111111
•
•
•
1000000= Minimum frequency
bit 0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41268B-page 22
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
4.6.1
EFFECTS OF RESET
4.6
Program Counter
The PC is set upon a Reset, which means that the PC
addresses the last location in the last page (i.e., the
oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 00h and
begin executing user code.
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
The STATUS register page preselect bits are cleared
upon a Reset, which means that page 0 is preselected.
For a GOTOinstruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The Program Counter
(PCL) is mapped to PC<7:0>. Bit 5 of the STATUS
register provides page information to bit 9 of the PC
(Figure 4-4).
Therefore, upon a Reset, a GOTO instruction will
automatically cause the program to jump to page 0 until
the value of the page bits is altered.
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-4).
4.7
Stack
The PIC12F510/16F506 devices have a 2-deep, 12-bit
wide hardware PUSH/POP stack.
A CALLinstruction will PUSH the current value of Stack
1 into Stack 2 and then PUSH the current PC value,
incremented by one, into Stack Level 1. If more than
two sequential CALLs are executed, only the most
recent two return addresses are stored.
Instructions where the PCL is the destination or modify
PCL instructions include MOVWF PC, ADDWF PCand
BSF PC, 5.
Note:
Because PC<8> is cleared in the CALL
instruction or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any
program memory page (512 words long).
A RETLW instruction will POP the contents of Stack
Level 1 into the PC and then copy Stack Level 2
contents into Stack Level 1. If more than two sequential
RETLWs are executed, the stack will be filled with the
address previously stored in Stack Level 2.
FIGURE 4-4:
LOADING OF PC
Note 1: The W register will be loaded with the lit-
eral value specified in the instruction. This
is particularly useful for the implementa-
tion of data look-up tables within the
program memory.
BRANCH INSTRUCTIONS
GOTOInstruction
9 8 7
0
PC
PCL
2: There are no Status bits to indicate stack
overflows or stack underflow conditions.
Instruction Word
3: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLWinstructions.
PA0
0
7
STATUS
CALLor Modify PCL Instruction
9 8 7
0
PC
PCL
Instruction Word
Reset to ‘0’
PA0
7
0
STATUS
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 23
PIC12F510/16F506
EXAMPLE 4-1:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
4.8
Indirect Data Addressing: INDF
and FSR Registers
The INDF register is not a physical register. Addressing
INDF actually addresses the register whose address is
contained in the FSR register (FSR is a pointer). This is
indirect addressing.
MOVLW
MOVWF
0x10
;initialize pointer
;to RAM
FSR
NEXT
CLRF
INCF
BTFSC
GOTO
INDF
FSR,F
FSR,4
NEXT
;clear INDF register
;inc pointer
;all done?
4.8.1
INDIRECT ADDRESSING EXAMPLE
;NO, clear next
CONTINUE
• Register file 07 contains the value 10h
• Register file 08 contains the value 0Ah
• Load the value 07 into the FSR register
:
:
;YES, continue
• A read of the INDF register will return the value
of 10h
The FSR is a 5-bit wide register. It is used in conjunc-
tion with the INDF register to indirectly address the data
memory area.
• Increment the value of the FSR register by one
(FSR = 08)
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
• A read of the INDR register now will return the
value of 0Ah.
PIC16F506 – Uses FSR<6:5>. Selects from Bank 0 to
Bank 3. FSR<7> is unimplemented, read as ‘1’.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no operation (although Status bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-1.
PIC12F510 – Uses FSR<5>. Selects from Bank 0 to
Bank 1. FSR<7:6> are unimplemented, read as ‘11’.
FIGURE 4-5:
DIRECT/INDIRECT ADDRESSING (PIC12F510)
Direct Addressing
(opcode)
Indirect Addressing
(FSR)
(FSR)
4
3
2
1
0
5
3
2
1
0
6
4
5
6
bank select
bank
select
location select
location select
00
01
00h
Addresses map back to
addresses in Bank 0.
Data
Memory
0Fh
10h
(1)
1Fh
3Fh
Bank 1
Bank 0
Note 1: For register map detail, see Figure 4-2.
DS41268B-page 24
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 4-6:
DIRECT/INDIRECT ADDRESSING (PIC16F506)
Direct Addressing
(opcode)
Indirect Addressing
(FSR)
(FSR)
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Bank Select
Location Select
00h
Bank
Location Select
00
01
10
11
Addresses
map back to
addresses
in Bank 0.
0Fh
10h
Data
Memory
(1)
1Fh
3Fh
5Fh
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Note 1: For register map detail, see Figure 4-3.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 25
PIC12F510/16F506
NOTES:
DS41268B-page 26
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
5.4
I/O Interfacing
5.0
I/O PORT
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except RB3/GP3 which is
input only, may be used for both input and output oper-
ations. For input operations, these ports are non-latch-
ing. Any input must be present until read by an input
instruction (e.g., MOVF PORTB, W). The outputs are
latched and remain unchanged until the output latch is
rewritten. To use a port pin as output, the correspond-
ing direction control bit in TRIS must be cleared (= 0).
For use as an input, the corresponding TRIS bit must
be set. Any I/O pin (except RB3/GP3) can be
programmed individually as input or output.
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB, W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
Note:
On the PIC12F510, I/O PORTB is refer-
enced as GPIO. On the PIC16F506, I/O
PORTB is referenced as PORTB.
5.1
PORTB/GPIO
FIGURE 5-1:
PIC12F510/16F506
EQUIVALENT CIRCUIT
FOR PIN DRIVE(2)
PORTB/GPIO is an 8-bit I/O register. Only the low-
order 6 bits are used (RB/GP<5:0>). Bits 7 and 6 are
unimplemented and read as ‘0’s. Please note that RB3/
GP3 is an input only pin. The Configuration Word can
set several I/O’s to alternate functions. When acting as
alternate functions, the pins will read as ‘0’ during a port
read. Pins RB0/GP0, RB1/GP1, RB3/GP3 and RB4
(PIC16F506 only) can be configured with weak pull-up
and also for wake-up on change. The wake-up on
change and weak pull-up functions are not pin select-
able. If RB3/GP3/MCLR is configured as MCLR, weak
pull-up is always on and wake-up on change for this pin
is not enabled.
Data
Bus
Data
Bus
Interface
VDD
P
VDD
(1)
N
I/O
pin
VSS VSS
5.2
PORTC (PIC16F506 Only)
PORTC is an 8-bit I/O register. Only the low-order 6 bits
are used (RC<5:0>). Bits 7 and 6 are unimplemented
and read as ‘0’s.
Reset
Note 1: GP3/RB3 has protection diode to VSS only.
5.3
TRIS Registers
2: For pin specific information, see Figure 5-2
The Output Driver Control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A ‘1’ from a TRIS register bit puts the corre-
sponding output driver in a High-Impedance mode. A
‘0’ puts the contents of the output data latch on the
selected pins, enabling the output buffer. The exception
is RB3/GP3, which are input only, and the T0CKI pin,
which may be controlled by the OPTION register. See
Register 4-3.
through Figure 5-13.
Note:
A read of the port reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
Note:
The TRIS registers are “write-only” and
are set (output drivers disabled) upon
Reset.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 27
PIC12F510/16F506
FIGURE 5-2:
BLOCK DIAGRAM OF
GP0/RB0 AND GP1/RB1
FIGURE 5-3:
BLOCK DIAGRAM OF
GP3/RB3 (With Weak
Pull-up And Wake-up On
Change)
GPPU
RBPU
GPPU
RBPU
Data
MCLRE
Bus
D
Q
Q
Data
Latch
(1)
I/O Pin
WR
Port
CK
Reset
W
Reg
(1)
I/O Pin
D
Q
Q
TRIS
Latch
TRIS ‘f’
CK
Data Bus
RD Port
Q
Reset
ADC pin Ebl
D
COMP pin Ebl
CK
RD Port
Mis-match
Q
D
CK
Mis-Match
ADC
COMP
Note 1: I/O pins have protection diodes to VDD and
Note 1: GP3/MCLR pin has a protection diode to VSS
VSS.
only.
DS41268B-page 28
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 5-4:
BLOCK DIAGRAM OF GP2
FIGURE 5-5:
BLOCK DIAGRAM OF RB2
C1OUT
C1OUT
0
1
0
1
(1)
(1)
I/O Pin
I/O Pin
Data
Bus
D
Data
Bus
Q
Q
D
Q
Data
Latch
Data
Latch
WR
WR
Port
Port
Q
CK
CK
C1OUTEN
Q
TRIS
Latch
C1OUTEN
W
Reg
W
Reg
D
D
Q
TRIS
Latch
TRIS ‘f’
TRIS ‘f’
Q
Q
CK
CK
Reset
Reset
T0CS
ADC Pin Enable
C1T0CS
ADC Pin Enable
RD Port
T0CKI
RD Port
ADC
ADC
Note 1: I/O pins have protection diodes to VDD and
Note 1: I/O pins have protection diodes to VDD and
VSS.
VSS.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 29
PIC12F510/16F506
FIGURE 5-6:
BLOCK DIAGRAM OF RB4
FIGURE 5-7:
BLOCK DIAGRAM OF GP4
RBPU
Data
Bus
D
Q
Q
Data
Latch
I/O
pin(1)
WR
Port
Data
Bus
D
CK
0
1
Q
Q
Data
Latch
WR
Port
CK
W
Reg
I/O
pin
(1)
D
Q
Q
TRIS
Latch
FOSC/4
Q
W
TRIS ‘f’
Reg
CK
D
TRIS
Latch
TRIS ‘f’
Reset
INTOSC/RC
Q
CK
Reset
INTOSC/RC/EC
CLKOUT Enable
(Note 2)
RD Port
Oscillator
Circuit
OSC1
RD Port
Oscillator
Circuit
OSC1
Note 1: I/O pins have protection diodes to VDD and
Note 1: I/O pins have protection diodes to VDD and VSS.
VSS.
2: Input mode is disabled when pin is used for
oscillator.
DS41268B-page 30
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 5-8:
BLOCK DIAGRAM OF
RB5/GP5
FIGURE 5-9:
BLOCK DIAGRAM OF
RC0/RC1
Data
Bus
D
Data
Bus
Q
Q
Data
Latch
D
Q
Q
I/O
pin(1)
WR
Data
Latch
Port
I/O
pin(1)
WR
Port
CK
CK
W
Reg
W
Reg
D
Q
Q
TRIS
Latch
D
Q
Q
TRIS
Latch
TRIS ‘f’
CK
TRIS ‘f’
CK
Reset
Reset
Comp Pin Enable
(Note 2)
RD Port
Oscillator
Circuit
OSC2
RD Port
COMP2
Note 1: I/O pins have protection diodes to VDD and
VSS.
Note 1: I/O pins have protection diodes to VDD and
2: Input mode is disabled when pin is used for
VSS.
oscillator.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 31
PIC12F510/16F506
FIGURE 5-10:
BLOCK DIAGRAM OF RC2
FIGURE 5-11:
BLOCK DIAGRAM OF RC3
VROE
(1)
I/O Pin
Data
Bus
D
Q
Q
Data
Latch
CVREF
WR
Port
1
0
(1)
I/O PIN
CK
Data
Bus
D
Q
Q
Data
Latch
W
WR
Port
Reg
D
Q
Q
CK
TRIS
Latch
TRIS ‘f’
CK
W
Reg
D
Q
Q
Reset
TRIS
Latch
TRIS ‘f’
CK
Reset
RD Port
RD Port
COMP2
Note 1: I/O pins have protection diodes to VDD and
Note 1: I/O pins have protection diodes to VDD and
VSS.
VSS.
DS41268B-page 32
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 5-12:
BLOCK DIAGRAM OF RC4
FIGURE 5-13:
BLOCK DIAGRAM OF RC5
(1)
C2OUT
0
I/O Pin
(1)
I/O Pin
Data
Bus
Data
Bus
1
D
Q
Q
D
Q
Q
Data
Latch
Data
Latch
WR
Port
WR
Port
CK
CK
C2OUTEN
Q
TRIS
Latch
W
Reg
W
Reg
D
D
Q
Q
TRIS
Latch
TRIS ‘f’
TRIS ‘f’
Q
CK
CK
T0CS
Reset
Reset
RD Port
RD Port
T0CKI
Note 1: I/O pins have protection diodes to VDD and
Note 1: I/O pins have protection diodes to VDD and
VSS.
VSS.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 33
PIC12F510/16F506
TABLE 5-1:
SUMMARY OF PORT REGISTERS
Value on
Power-On
Reset
Value on
All Other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
(1)
N/A
TRISGPIO
—
—
—
—
I/O Control Register
I/O Control Register
I/O Control Register
--11 1111
--11 1111
--11 1111
1111 1111
1111 1111
--11 1111
--11 1111
--11 1111
1111 1111
1111 1111
(2)
N/A
TRISB
(2)
N/A
TRISC
—
—
(1)
N/A
OPTION
GPWU
RBWU
GPPU
RBPU
T0CS
T0CS
PA0
TOSE
TOSE
TO
PSA
PSA
PD
PS2
PS2
Z
PS1
PS1
DC
PS0
PS0
C
(2)
N/A
OPTION
(1)
(3)
03h
STATUS
GPWUF CWUF
RBWUF CWUF
0001 1xxx qq0q quuu
0001 1xxx qq0q quuu
(2)
(3)
03h
STATUS
PA0
TO
PD
Z
DC
C
(1)
06h
GPIO
—
—
—
—
—
—
GP5
RB5
RC5
GP4
RB4
RC4
GP3
RB3
RC3
GP2
RB2
RC2
GP1
RB1
RC1
GP0
RB0
RC0
--xx xxxx
--xx xxxx
--xx xxxx
--uu uuuu
(2)
06h
PORTB
--uu uuuu
--uu uuuu
(2)
07h
PORTC
Legend:
– = unimplemented read as ‘0’, x= unknown, u= unchanged, q= depends on condition.
Note 1: PIC12F510 only.
2: PIC16F506 only.
3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
TABLE 5-2:
I/O PIN FUNCTION ORDER OF PRECEDENCE (PIC16F506)
Priority
RB0
AN0/C1IN+
TRISB
—
RB1
AN1/C1IN-
TRISB
—
RB2
C1OUT
AN2
RB3
RB4
RB5
OSC1/CLKIN
TRISB
1
2
3
Input/MCLR OSC2/CLKOUT
—
—
TRISB
—
TRISB
—
TABLE 5-3:
Priority
I/O PIN FUNCTION ORDER OF PRECEDENCE (PIC16F506)
RC0
RC1
RC2
RC3
RC4
RC5
1
2
C2IN+
TRISC
C2IN-
CVREF
TRISC
TRISC
—
C2OUT
TRISC
T0CKI
TRISC
TRISC
TABLE 5-4:
Priority
I/O PIN FUNCTION ORDER OF PRECEDENCE (PIC12F510)
GP0
AN0/C1IN+
TRISIO
—
GP1
AN1/C1IN-
TRISIO
—
GP2
C1OUT
AN2
GP3
GP4
OSC2
TRISIO
—
GP5
OSC1/CLKIN
TRISIO
—
1
2
3
4
Input/MCLR
—
—
—
T0CKI
TRISIO
—
—
—
—
DS41268B-page 34
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
TABLE 5-5:
REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC12F510)
GP0
GP0
GP1
GP1
GP2
GP2
GP3
GP4
GP5
CM1CON0
C1ON
0
1
0
0
1
1
0
0
1
—
—
—
—
—
—
—
—
—
C1PREF
C1NREF
—
—
—
—
—
—
—
—
—
C1T0CS
—
—
—
—
—
—
—
—
—
—
1
1
—
—
—
—
—
—
C1OUTEN
CM2CON0
C2ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C2PREF1
C2PREF2
C2NREF
C2OUTEN
VRCON0
VROE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VREN
OPTION
T0CS
—
—
—
—
—
0
—
—
—
—
—
—
ADCON0
ANS<1:0>
CONFIG
MCLRE
INTOSC
LP
00, 01
00, 01 00, 01, 10 00, 01, 10
00
00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Disabled Disabled
Disabled
Disabled Disabled
EXTRC
XT
—
Note 1: Multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for
the pin.
2: Shaded cells indicate the bit status does not affect the pins digital functionality.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 35
PIC12F510/16F506
TABLE 5-6:
REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC16F506 PORTB)(1), (2)
RB0
RB0
RB0
RB1
RB1
RB2 RB2 RB3
RB4
RB5
CM1CON0
C1ON
—
—
—
0
1
0
0
1
—
0
0
1
—
—
—
—
—
—
—
—
—
C1PREF
C1NREF
—
—
—
—
—
—
—
—
—
C1T0CS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1OUTEN
CM2CON0
C2ON
1
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C2PREF1
C2PREF2
C2NREF
1
—
C2OUTEN
OPTION
T0CS
—
—
—
—
—
—
—
—
00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCON0
ANS<1:0>
CONFIG
MCLRE
INTOSC
LP
00, 01 00, 01 00, 01 00, 01, 10 00, 01, 10 00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
Disabled Disabled
Disabled
Disabled Disabled
Disabled
EXTRC
—
XT
EC
—
HS
Disabled Disabled
Disabled Disabled
Disabled Disabled
INTOSC CLKOUT
EXTRC CLOCKOUT
Note 1: Multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for
the pin.
2: Shaded cells indicate the bit status does not affect the pins digital functionality.
TABLE 5-7:
REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC16F506 PORTC)(1), (2)
RC0
RC0
RC1
RC1
RC2
RC3
RC4
RC4
RC5
RC5
CM2CON0
C2ON
0
1
0
0
1
—
—
0
—
—
—
—
—
—
—
—
0
1
—
—
—
—
—
—
—
—
C2PREF1
C2PREF2
C2NREF
—
—
—
—
—
—
—
—
—
—
—
—
0
—
C2OUTEN
VRCON0
VROE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
—
—
0
—
—
—
0
—
—
OPTION
T0CS
—
Note 1: Multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for
the pin.
2: Shaded cells indicate the bit status does not affect the pins digital functionality.
DS41268B-page 36
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT(e.g., PIC16F506)
5.5
I/O Programming Considerations
5.5.1
BIDIRECTIONAL I/O PORTS
Some instructions operate internally as read followed
by write operations. For example, the BCF and BSF
instructions read the entire port into the CPU, execute
the bit operation and re-write the result. Caution must
be used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSFoperation on bit 5 of PORTB/GPIO will
cause all eight bits of PORTB/GPIO to be read into the
CPU, bit 5 to be set and the PORTB/GPIO value to be
written to the output latches. If another bit of PORTB/
GPIO is used as a bidirectional I/O pin (say bit ‘0’) and
it is defined as an input at this time, the input signal
present on the pin itself would be read into the CPU and
rewritten to the data latch of this particular pin, overwrit-
ing the previous content. As long as the pin stays in the
Input mode, no problem occurs. However, if bit ‘0’ is
switched into Output mode later on, the content of the
data latch may now be unknown.
;Initial PORTB Settings
;PORTB<5:3> Inputs
;PORTB<2:0> Outputs
;
;
;
PORTB latch PORTB pins
----------
PORTB, 5 ;--01 -ppp
PORTB, 4 ;--10 -ppp
----------
--11 pppp
--11 pppp
BCF
BCF
MOVLW 007h;
TRIS
PORTB
;--10 -ppp
--11 pppp
;
Note:
The user may have expected the pin values to
be ‘--00 pppp’. The 2nd BCFcaused RB5 to
be latched as the pin value (High).
5.5.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle. Whereas for reading, the data must
be valid at the beginning of the instruction cycle
(Figure 5-14). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction causes the file to be read
into the CPU. Otherwise, the previous state of that pin
may be read into the CPU rather than the new state.
When in doubt, it is better to separate these
instructions with a NOP or another instruction not
accessing this I/O port.
Example 5-1 shows the effect of two sequential
Read-Modify-Write instructions (e.g., BCF, BSF, etc.)
on an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired OR”, “wired
AND”). The resulting high output currents may damage
the chip.
FIGURE 5-14:
SUCCESSIVE I/O OPERATION (PIC16F506)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC + 3
PC
MOVWF PORTB
PC + 1
PC + 2
This example shows a write to PORTB followed by a
read from PORTB.
Instruction
Fetched
MOVF PORTB, W
NOP
NOP
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle
TPD = propagation delay
RB<5:0>
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
Port pin
written here
Port pin
sampled here
Instruction
Executed
MOVWF PORTB
MOVF PORTB,W
NOP
(Write to PORTB)
(Read PORTB)
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 37
PIC12F510/16F506
NOTES:
DS41268B-page 38
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
The second Counter mode uses the output of the com-
parator to increment Timer0. It can be entered in two
different ways. The first way is selected by setting the
T0CS bit (OPTION<5>), and clearing the C1T0CS bit
(CM1CON0<4>) (C1OUTEN [CM1CON0<6>] does not
affect this mode of operation). This enables an internal
connection between the comparator and the Timer0.
6.0
TMR0 MODULE AND TMR0
REGISTER
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select:
- Edge select for external clock
The second way is selected by setting the T0CS bit
(OPTION<5>), setting the C1T0CS bit (CM1CON0)
and clearing the C1OUTEN bit (CM1CON0<6>). This
allows the output of the comparator onto the T0CKI pin,
while keeping the T0CKI input active. Therefore, any
comparator change on the COUT pin is fed back into
the T0CKI input. The T0SE bit (OPTION<4>) deter-
mines the source edge. Clearing the T0SE bit selects
the rising edge. Restrictions on the external clock input
as discussed in Section 6.1 “Using Timer0 With An
External Clock”.
- External clock from either the T0CKI pin or
from the output of the comparator
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit will
assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 6.2 “Prescaler” details
the operation of the prescaler.
There are two types of Counter mode. The first Counter
mode uses the T0CKI pin to increment Timer0. It is
selected by setting the T0CKI bit (OPTION<5>), setting
the C1T0CS bit (CM1CON0<4>) and setting the
C1OUTEN bit (CM1CON0<6>). In this mode, Timer0
will increment either on every rising or falling edge of
pin T0CKI. The T0SE bit (OPTION<4>) determines the
source edge. Clearing the T0SE bit selects the rising
edge. Restrictions on the external clock input are
discussed in detail in Section 6.1 “Using Timer0 With
An External Clock”.
A summary of registers associated with the Timer0
module is found in Table 6-1.
FIGURE 6-1:
TIMER0 BLOCK DIAGRAM
T0CKI
Pin
Data Bus
FOSC/4
0
1
PSOUT
8
1
0
1
0
Internal
Comparator
Output
Sync with
Internal
Clocks
TMR0 Reg
Programmable
PSOUT
Sync
(2)
Prescaler
(1)
(2 TCY delay)
T0SE
3
(3)
(1)
(1)
C1T0CS
PS2, PS1, PS0
PSA
(1)
T0CS
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
3: Bit C1T0CS is located in the CM1CON0 register, CM1CON0<4>.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 39
PIC12F510/16F506
FIGURE 6-2:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC - 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
Instruction
Fetch
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
NT0 + 1
T0
T0 + 1
T0 + 2
NT0
NT0 + 2
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
FIGURE 6-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC - 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Instruction
Fetch
T0
T0 + 1
NT0
NT0 + 1
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Bit 0 Power-On
Reset
Value on
All Other
Resets
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
01h
07h
TMR0
Timer0 – 8-bit Real-Time Clock/Counter
C1OUT C1OUTEN C1POL C1T0CS
C1OUT C1OUTEN C1POL C1T0CS
xxxx xxxx uuuu uuuu
1111 1111 uuuu uuuu
C1NREF C1PREF C1WU
(2)
(3)
CM1CON0
CM1CON0
OPTION
C1ON
C1ON
PSA
08h
N/A
N/A
C1NREF C1PREF C1WU 1111 1111 uuuu uuuu
GPWU
—
GPPU
—
T0CS
T0SE
PS2
PS1
PS0 1111 1111 1111 1111
(1)
TRISGPIO
I/O Control Register
---- 1111 --11 1111
Legend:
Shaded cells not used by Timer0, – = unimplemented, x = unknown, u= unchanged.
Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1.
2: For PIC12F510.
3: For PIC16F506.
DS41268B-page 40
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling require-
ment, the ripple counter must be taken into account.
Therefore, it is necessary for T0CKI or the comparator
output to have a period of at least 4TOSC (and a small
RC delay of 4Tt0H) divided by the prescaler value. The
only requirement on T0CKI or the comparator output
high and low time is that they do not violate the
minimum pulse width requirement of Tt0H. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
6.1
Using Timer0 With An External
Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock require-
ment is due to internal phase clock (TOSC) synchroniza-
tion. Also, there is a delay in the actual incrementing of
Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of an external clock with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-4). Therefore, it is necessary for T0CKI or the
comparator output to be high for at least 2TOSC (and a
small RC delay of 2Tt0H) and low for at least 2TOSC
(and a small RC delay of 2Tt0H). Refer to the electrical
specification of the desired device.
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
FIGURE 6-4:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
misses sampling
External Clock Input or
(2)
Prescaler Output
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4TOSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
6.2
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (see Figure 10-12). For sim-
plicity, this counter is being referred to as “prescaler”
throughout this data sheet.
MOVWF 1, BSF 1, x, etc.) will clear the prescaler.
When assigned to WDT, a CLRWDTinstruction will clear
the prescaler along with the WDT. The prescaler is
neither readable nor writable. On a Reset, the
prescaler contains all ‘0’s.
Note:
The prescaler may be used by either the
Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the WDT and vice-versa.
The PSA and PS<2:0> bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 41
PIC12F510/16F506
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before
switching the prescaler.
6.2.1
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during pro-
gram execution). To avoid an unintended device Reset,
the following instruction sequence (Example 6-1) must
be executed when changing the prescaler assignment
from Timer0 to the WDT.
EXAMPLE 6-2:
CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
;Clear WDT and
;prescaler
EXAMPLE 6-1:
CHANGING PRESCALER
(TIMER0 → WDT)
;Clear WDT
MOVLW ‘xxxx0xxx’ ;Select TMR0, new
;prescale value and
;clock source
CLRWDT
CLRF
TMR0
;Clear TMR0 & Prescaler
OPTION
MOVLW ‘00xx1111’b ;These 3 lines (5, 6, 7)
OPTION
;are required only if
;desired
CLRWDT
;PS<2:0> are 000 or 001
MOVLW ‘00xx1xxx’b ;Set Postscaler to
OPTION
;desired WDT rate
FIGURE 6-5:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
(2)
T0CKI
Pin
TCY (= FOSC/4)
Data Bus
8
0
M
U
X
1
1
0
M
U
X
Comparator
Output
Sync
2
Cycles
1
TMR0 Reg
0
(1)
(1)
T0SE
T0CS
(1)
PSA
(3)
C1T0CS
0
1
8-bit Prescaler
M
U
X
8
Watchdog
Timer
(1)
8-to-1 MUX
PS<2:0>
(1)
PSA
1
0
WDT Enable bit
(1)
MUX
PSA
WDT
Time-Out
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
2: T0CKI is shared with pin GP2 on the PIC12F510 and shared with RC5 on the PIC16F506.
3: Bit C1T0CS is located in the CM1CON0 register.
DS41268B-page 42
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
7.0
COMPARATOR(S)
The PIC12F510 contains one analog comparator
module. The PIC16F506 contains two comparators
and a comparator voltage reference.
REGISTER 7-1:
CM1CON0 REGISTER (ADDRESS: 07h) (PIC12F510)
R-1
R/W-1
R/W-1
R/W-1
R/W-1
C1ON
R/W-1
R/W-1
R/W-1
C1WU
C1OUT C1OUTEN C1POL
bit 7
C1T0CS
C1NREF C1PREF
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
C1OUT: Comparator Output bit
1= VIN+ > VIN-
0= VIN+ < VIN-
C1OUTEN: Comparator Output Enable bit(1), (2)
1= Output of comparator is NOT placed on the C1OUT pin
0= Output of comparator is placed in the C1OUT pin
C1POL: Comparator Output Polarity bit(2)
1= Output of comparator is not inverted
0= Output of comparator is inverted
C1T0CS: Comparator TMR0 Clock Source bit(2)
1= TMR0 clock source selected by T0CS control bit
0= Comparator output used as TMR0 clock source
C1ON: Comparator Enable bit
1= Comparator is on
0= Comparator is off
C1NREF: Comparator Negative Reference Select bit(2)
1= C1IN pin
0= VREF
C1PREF: Comparator Positive Reference Select bit(2)
1= C1IN+ pin
0= C1IN- pin
C1WU: Comparator Wake-up On Change Enable bit(2)
1= Wake-up On Comparator Change is disabled
0= Wake-up On Comparator Change is enabled
Note 1: Overrides T0CS bit for TRIS control of GP2.
2: When comparator is turned on, these control bits assert themselves.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 43
PIC12F510/16F506
REGISTER 7-2:
CM1CON0 REGISTER (ADDRESS: 08h) (PIC16F506)
R-1
R/W-1
R/W-1
R/W-1
R/W-1
C1ON
R/W-1
R/W-1
R/W-1
C1WU
C1OUT C1OUTEN C1POL
bit 7
C1T0CS
C1NREF C1PREF
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
C1OUT: Comparator Output bit
1= VIN+ > VIN-
0= VIN+ < VIN-
C1OUTEN: Comparator Output Enable bit(1), (2)
1= Output of comparator is NOT placed on the C1OUT pin
0= Output of comparator is placed in the C1OUT pin
C1POL: Comparator Output Polarity bit(2)
1= Output of comparator not inverted
0= Output of comparator inverted
C1T0CS: Comparator TMR0 Clock Source bit(2)
1= TMR0 clock source selected by TOCS control bit
0= Comparator output used as TMR0 clock source
C1ON: Comparator Enable bit
1= Comparator is on
0= Comparator is off
C1NREF: Comparator Negative Reference Select bit(2)
1= C1IN- pin
0= VREF
C1PREF: Comparator Positive Reference Select bit(2)
1= C1IN+ pin
0= C1IN- pin
C1WU: Comparator Wake-up On Change Enable bit(2)
1= Wake-up On Comparator Change is disabled
0= Wake-up On Comparator Change is enabled.
Note 1: Overrides T0CS bit for TRIS control of RC5.
2: When comparator is turned on, these control bits assert themselves. Otherwise, the
other registers have precedence.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41268B-page 44
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
REGISTER 7-3:
CM2CON0 REGISTER (ADDRESS: 0Bh) (PIC16F506)
R-1
C2OUT C2OUTEN C2POL C2PREF2
bit 7
R/W-1
R/W-1
R/W-1
R/W-1
C2ON
R/W-1
C2NREF C2PREF1 C2WU
bit 0
R/W-1
R/W-1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
C2OUT: Comparator Output bit
1= VIN+ > VIN-
0= VIN+ < VIN-
C2OUTEN: Comparator Output Enable bit(1), (2)
1= Output of comparator is NOT placed on the C2OUT pin
0= Output of comparator is placed in the C2OUT pin
C2POL: Comparator Output Polarity bit(2)
1= Output of comparator not inverted
0= Output of comparator inverted
C2PREF2: Comparator Positive Reference Select bit(2)
1= C1IN+ pin
0= C2IN- pin
C2ON: Comparator Enable bit
1= Comparator is on
0= Comparator is off
C2NREF: Comparator Negative Reference Select bit(2)
1= C2IN- pin
0= VREF
C2PREF1: Comparator Positive Reference Select bit(2)
1= C2IN+ pin
0= C2PREF2 controls analog input selection
C2WU: Comparator Wake-up on Change Enable bit(2)
1= Wake-up on Comparator change is disabled
0= Wake-up on Comparator change is enabled.
Note 1: Overrides TOCS bit for TRIS control of RC4.
2: When comparator is turned on, these control bits assert themselves. Otherwise, the
other registers have precedence.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 45
PIC12F510/16F506
FIGURE 7-1:
COMPARATOR 1 BLOCK DIAGRAM FOR PIC12F510/16F506
C1PREF
To
Data Bus
C1IN-
0
1
RD_CM1CON0
C1IN+
C1WUF
D
Q
Q3 * RD_CM1CON0
EN
CL
C1WU
NRESET
(1)
C1NREF
C1ON
C1
C1 Output Enable
C1OUT
+
-
1
0
C1IN-
C1OUT
0.6 VREF
C1POL
Note 1: When C1ON = 0, the comparator, C1, will produce a ‘0’ output to the XOR Gate.
FIGURE 7-2:
COMPARATOR 2 BLOCK DIAGRAM (PIC16F506 ONLY)
To
Data Bus
RD_CM2CON0
C2WUF
D
Q
C2PREF1
C2WU
Q3 * RD_CM2CON0
NRESET
C2OUT
EN
CL
C2PREF2
C2ON(1)
1
C2IN+
1
0
C1IN+
C2IN-
+
-
C2
0
C2 Output Enable
C2POL
C2NREF
1
C2OUT
C2IN-
CVREF
0
Note 1:
When C2ON = 0, the comparator, C2, will produce a ‘0’ output to the XOR Gate.
DS41268B-page 46
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
7.1
Comparator Operation
Note:
Analog levels on any pin that is defined as
a digital input may cause the input buffer
to consume more current than is specified.
A single comparator is shown in Figure 7-3 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. The shaded area of the output of
the comparator in Figure 7-3 represent the uncertainty
due to input offsets and response time. See Table 13-1
for Common Mode Voltage.
7.5
Comparator Wake-up Flag
The Comparator Wake-up Flag is set whenever all of
the following conditions are met:
• C1WU = 0(CM1CON0<0>) or
C2WU = 0(CM2CON0<0>)
FIGURE 7-3:
SINGLE COMPARATOR
• CM1CON0 or CM2CON0 has been read to latch
the last known state of the C1OUT and C2OUT bit
(MOVF CM1CON0, W)
VIN+
VIN-
+
Result
• Device is in Sleep
–
• The output of a comparator has changed state
The wake-up flag may be cleared in software or by
another device Reset.
7.6
Comparator Operation During
Sleep
VIN-
VIN+
When the comparator is enabled it is active. To mini-
mize power consumption while in Sleep mode, turn off
the comparator before entering Sleep.
Result
7.7
Effects of Reset
A Power-on Reset (POR) forces the CM2CON0
register to its Reset state. This forces the Comparator
input pins to analog Reset mode. Device current is
minimized when analog inputs are present at Reset
time.
7.2
Comparator Reference
An internal reference signal may be used depending on
the comparator operating mode. The analog signal that
is present at VIN- is compared to the signal at VIN+, and
the digital output of the comparator is adjusted accord-
ingly (Figure 7-3). Please see Section 8.0 “Compara-
tor Voltage Reference Module (PIC16F506 only)” for
internal reference specifications.
7.8
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 7-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum source impedance of 10 kΩ is recom-
mended for the analog sources. Any external compo-
nent connected to an analog input pin, such as a
capacitor or a Zener diode, should have very little
leakage current.
7.3
Comparator Response Time
Response time is the minimum time after selecting a
new reference voltage or input source before the com-
parator output is to have a valid level. If the comparator
inputs are changed, a delay must be used to allow the
comparator to settle to its new state. Please see
Table 13-1
specifications.
for
comparator
response
time
7.4
Comparator Output
The comparator output is read through the CM1CON0
or CM2CON0 register. This bit is read-only. The
comparator output may also be used externally, see
Figure 7-3.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 47
PIC12F510/16F506
FIGURE 7-4:
ANALOG INPUT MODE
VDD
VT = 0.6V
RIC
RS < 10 K
AIN
ILEAKAGE
±500 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend:
CPIN
VT
= Input Capacitance
= Threshold Voltage
ILEAKAGE = Leakage Current at the Pin
RIC
RS
VA
= Interconnect Resistance
= Source Impedance
= Analog Voltage
TABLE 7-1:
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
All Other
Resets
Value on
POR
Add
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
03h
STATUS
GPWUF
C1OUT
C1OUT
CWUF
PA0
TO
PD
Z
DC
C
0001 1xxx qq0q quuu
1111 1111 uuuu uuuu
1111 1111 uuuu uuuu
07h
08h
CM1CON0(1)
CM1CON0(2)
C1OUTEN C1POL
C1OUTEN C1POL
C1T0CS
C1T0CS
C1ON
C1ON
C1NREF
C1NREF
C1PREF
C1PREF
C1WU
C1WU
C2WU
0Bh
N/A
N/A
N/A
CM2CON0(2)
TRISB(2)
TRISC(2)
C2OUT
C2OUTEN C2POL C2PREF2 C2ON
C2NREF C2PREF1
1111 1111 uuuu uuuu
--11 1111 --11 1111
--11 1111 --11 1111
--11 1111 --11 1111
—
—
—
—
—
—
I/O Control Register
I/O Control Register
I/O Control Register
TRISGPIO(1)
Legend:
Note 1:
2:
x= Unknown, u= Unchanged, – = Unimplemented, read as ‘0’, q= Depends on condition.
PIC12F510 only.
PIC16F506 only.
DS41268B-page 48
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
8.2
Voltage Reference Accuracy/Error
8.0
COMPARATOR VOLTAGE
REFERENCE MODULE
(PIC16F506 ONLY)
The full range of VSS to VDD cannot be realized due to
construction of the module. The transistors on the top
and bottom of the resistor ladder network (Figure 8-1)
keep CVREF from approaching VSS or VDD. The excep-
tion is when the module is disabled by clearing the
VREN bit (VRCON<7>). When disabled, the reference
voltage is VSS when VR<3:0> is ‘0000’ and the VRR
(VRCON<5>) bit is set. This allows the comparator to
detect a zero-crossing and not consume the CVREF
module current.
The Comparator Voltage Reference module also
allows the selection of an internally generated voltage
reference for one of the C2 comparator inputs. The
VRCON register (Register 8-1) controls the Voltage
Reference module shown in Figure 8-1.
8.1
Configuring The Voltage
Reference
The voltage reference is VDD derived and, therefore,
the CVREF output changes with fluctuations in VDD. The
tested absolute accuracy of the comparator voltage ref-
erence can be found in Section 13.2 “DC Character-
istics: PIC12F510/16F506 (Extended)”.
The voltage reference can output 32 voltage levels; 16
in a high range and 16 in a low range.
Equation 8-1 determines the output voltages:
EQUATION 8-1:
VRR = 1 (low range): CVREF = (VR3:VR0/24) x VDD
VRR = 0 (high range):
CVREF = (VDD/4) + (VR3:VR0 x VDD/32)
REGISTER 8-1:
VRCON: PIC16F506 ONLY (ADDRESS: 0Ch)
R/W-0
VREN
R/W-0
VROE
R/W-1
VRR
U-0
—
R/W-1
VR3
R/W-1
VR2
R/W-1
VR1
R/W-1
VR0
bit 7
bit 0
bit 7
bit 6
bit 5
VREN: CVREF Enable bit
1= CVREF is powered on
0= CVREF is powered down, no current is drawn
VROE: CVREF Output Enable bit(1)
1= VREF output is enabled
0= VREF output is disabled
VRR: CVREF Range Selection bit
1= Low range
0= High range
bit 4
Unimplemented: Read as ‘0’
bit 3-0
VR<3:0> CVREF Value Selection bit
When VRR = 1: CVREF= (VR<3:0>/24)*VDD
When VRR = 0: CVREF= VDD/4+(VR<3:0>/32)*VDD
Note 1: When this bit is set, the TRIS for the VREF pin is overridden and the analog voltage
is placed on the VREF pin.
2: VREF controls for ratio metric reference applies to Comparator 2 on the PIC12F506
only.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 49
PIC12F510/16F506
FIGURE 8-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R
R
R
R
R
VDD
8R
VRR
16-1 Analog
MUX
VREN
CVREF to
Comparator 2
Input
VR3:VR0
RC2/VREF
VREN
VR3:VR0 = ‘0000’
VRR
VROE
TABLE 8-1:
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Value on
POR
Value on all
other Resets
Add
0Ch
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
001- 1111
1111 1111
1111 1111
001- 1111
uuuu uuuu
uuuu uuuu
08h
0Bh
CM1CON0(1) C1OUT C1OUTEN C1POL
C1T0CS
C1ON
C2ON
C1NREF
C1PREF
C1WU
CM2CON0(1) C2OUT C2OUTEN C2POL C2PREF2
C2NREF C2PREF1 C2WU
Legend:
x= unknown, u= unchanged, – = unimplemented, read as ‘0’.
Note 1:
PIC16F506 only.
DS41268B-page 50
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
9.0
ANALOG-TO-DIGITAL (A/D)
CONVERTER
Note:
It is the users responsibility to ensure that
use of the ADC and comparator simulta-
neously on the same pin, does not
adversely affect the signal being
monitored or adversely effect device
operation.
The A/D Converter allows conversion of an analog
signal into an 8-bit digital signal.
9.1
Clock Divisors
The ADC has 4 clock source settings ADCS<1:0>.
There are 3 divisor values 32, 16 and 8. The fourth set-
ting is INTOSC with a divisor of 4. These settings will
allow a proper conversion when using an external
oscillator at speeds from 20 MHz to 350 kHz. Using an
external oscillator at a frequency below 350 kHz
requires the ADC oscillator setting to be INTOSC/8 for
valid ADC results.
When the CHS<1:0> bits are changed during an ADC
conversion, the new channel will not be selected until
the current conversion is completed. This allows the
current conversion to complete with valid results. All
channel selection information will be lost when the
device enters Sleep.
TABLE 9-1:
CHANNEL SELECT (ADCS)
BITS AFTER AN EVENT
The ADC requires 13 TAD periods to complete a
conversion. The divisor values do not affect the number
of TAD periods required to perform a conversion. The
divisor values determine the length of the TAD period.
Event
ADCS<1:0>
MCLR
11
CS<1:0>
CS<1:0>
11
When the ADCS<1:0> bits are changed while an ADC
conversion is in process, the new ADC clock source will
not be selected until the next conversion is started. This
clock source selection will be lost when the device
enters Sleep.
Conversion completed
Conversion terminated
Power-on
Wake from Sleep
11
Note:
The ADC clock is derived from the instruc-
tion clock. The ADCS divisors are then
applied to create the ADC clock
9.1.4
THE GO/DONE BIT
The GO/DONE bit is used to determine the status of a
conversion, to start a conversion and to manually halt a
conversion in process. Setting the GO/DONE bit starts
a conversion. When the conversion is complete, the
ADC module clears the GO/DONE bit. A conversion
can be terminated by manually clearing the GO/DONE
bit while a conversion is in process. Manual termination
of a conversion may result in a partially converted
result in ADRES.
9.1.1
VOLTAGE REFERENCE
There is no external voltage reference for the ADC. The
ADC reference voltage will always be VDD.
9.1.2
ANALOG MODE SELECTION
The ANS<1:0> bits are used to configure pins for
analog input. Upon any Reset, ANS<1:0> defaults to
11. This configures pins AN0, AN1 and AN2 as analog
inputs. The comparator output, C1OUT, will override
AN2 as an input if the comparator output is enabled.
Pins configured as analog inputs are not available for
digital output. Users should not change the ANS bits
while a conversion is in process. ANS bits are active
regardless of the condition of ADON.
The GO/DONE bit is cleared when the device enters
Sleep, stopping the current conversion. The ADC does
not have a dedicated oscillator, it runs off of the instruc-
tion clock. Therefore, no conversion can occur in sleep.
The GO/DONE bit cannot be set when ADON is clear.
9.1.3
ADC CHANNEL SELECTION
The CHS bits are used to select the analog channel to
be sampled by the ADC. The CHS<1:0> bits can be
changed at any time without adversely effecting a con-
version. To acquire an analog signal the CHS<1:0>
selection must match one of the pin(s) selected by the
ANS<1:0> bits. When the ADC is on (ADON = 1) and a
channel is selected that is also being used by the
comparator, then both the comparator and the ADC will
see the analog voltage on the pin.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 51
PIC12F510/16F506
9.1.5
SLEEP
This ADC does not have a dedicated ADC clock, and
therefore, no conversion in Sleep is possible. If a
conversion is underway and a Sleep command is
executed, the GO/DONE and ADON bit will be cleared.
This will stop any conversion in process and power-
down the ADC module to conserve power. Due to the
nature of the conversion process, the ADRES may con-
tain a partial conversion. At least 1 bit must have been
converted prior to Sleep to have partial conversion data
in ADRES. The ADCS and CHS bits are reset to their
default condition; ANS<1:0> = 11and CHS<1:0> = 11.
• For accurate conversions, TAD must meet the
following:
• 500 ns < TAD < 50 μs
• TAD = 1/(FOSC/divisor)
Shaded areas indicate TAD out of range for accurate
conversions. If analog input is desired at these
frequencies, use INTOSC/8 for the ADC clock source.
TABLE 9-2:
TAD FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS
ADCS
<1:0>
20
MHz
16
MHz
500
kHz
350
kHz
200
kHz
100
kHz
Source
Divisor
8 MHz 4 MHz 1 MHz
32 kHz
INTOSC
FOSC
FOSC
FOSC
11
10
01
00
8
8
—
—
.5 μs
1 μs
1 μs
2 μs
4 μs
—
—
—
—
—
—
.2 μs .25 μs .5 μs
.4 μs
.8 μs
4 μs
8 μs
8 μs
11 μs 20 μs 40 μs 125 μs
16
32
.5 μs
1 μs
1 μs
2 μs
16 μs 23 μs 40 μs 80 μs 250 μs
16 μs 32 μs 46 μs 80 μs 160 μs 500 μs
TABLE 9-3:
EFFECTS OF SLEEP ON ADCON0
ANS1
ANS0
ADCS1
ADCS0
CHS1
CHS0
GO/DONE
ADON
Entering
Sleep
Unchanged Unchanged
1
1
1
1
0
0
Wake or
Reset
1
1
1
1
1
1
0
0
DS41268B-page 52
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
If the GO/DONE bit is cleared in software during a con-
version, the conversion stops. The data in ADRES is
the partial conversion result. This data is valid for the bit
weights that have been converted. The position of the
‘leading one’ determines the number of bits that have
been converted. The bits that were not converted
before the GO/DONE was cleared are unrecoverable.
9.1.6
ANALOG CONVERSION RESULT
REGISTER
The ADRES register contains the results of the last
conversion. These results are present during the sam-
pling period of the next analog conversion process.
After the sampling period is over, ADRES is cleared
(= 0). A ‘leading one’ is then right shifted into the
ADRES to serve as an internal conversion complete
bit. As each bit weight, starting with the MSB, is con-
verted, the leading one is shifted right and the con-
verted bit is stuffed into ADRES. After a total of 9 right
shifts of the ‘leading one’ have taken place, the conver-
sion is complete; the ‘leading one’ has been shifted out
and the GO/DONE bit is cleared.
REGISTER 9-1:
ADCON0 REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CHS1
R/W-1
CHS0
R/W-0
R/W-0
ADON
ANS1
ANS0
ADCS1
ADCS0
GO/DONE
bit 7
bit 0
(1), (2), (3), (6)
bit 7-6
bit 5-4
bit 3-2
bit 1
ANS<1:0>: ADC Analog Input Pin Select bits
00= No pins configured for analog input
01= GP2/AN2 configured as an analog input
10= GP2/AN2 and GP0/AN0 configured as analog inputs
11= GP2/AN2, GP1/AN1 and GP0/AN0 configured as analog inputs
ADCS<1:0>: ADC Conversion Clock Select bits
00= FOSC/32
01= FOSC/16
10= FOSC/8
11= INTOSC/8
(4), (6)
CHS<1:0>: ADC Channel Select bits for PIC16F506
00= Channel 00 (GP0/AN0)
01= Channel 01 (GP1/AN1)
10= Channel 02 (GP2/AN2)
11= 0.6V absolute voltage reference
(5)
GO/DONE: ADC Conversion Status bit
1= ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically
cleared by hardware when the ADC is done converting.
0= ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in process
terminates the current conversion.
bit 0
ADON: ADC Enable bit
1= ADC module is operating
0= ADC module is shut-off and consumes no power
Note 1: On the PIC16F506, the term is RBx, on PIC12F510, the term is GPx.
2: When the ANS bits are set, the channels selected will automatically be forced into Analog
mode, regardless of the pin function previously defined. The only exception to this is the com-
parator, where the analog input to the comparator and the ADC will be active at the same
time. It is the users responsibility to ensure that the ADC loading on the comparator input does
not affect their application.
3: The ANS<1:0> bits are active regardless of the condition of ADON.
4: CHS<1:0> bits default to 11after any Reset.
5: If the ADON bit is clear, the GO/DONE bit cannot be set.
6: C1OUT, when enabled, overrides AN2.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 53
PIC12F510/16F506
REGISTER 9-2:
ADRES REGISTER
R-X R-X
R-X
R-X
R-X
R-X
R-X
R-X
ADRES7 ADRES6 ADRES5 ADRES4
bit 7
ADRES3 ADRES2 ADRES1 ADRES0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
EXAMPLE 9-1:
PERFORMING AN
ANALOG-TO-DIGITAL
CONVERSION
EXAMPLE 9-2:
CHANNEL SELECTION
CHANGE DURING
CONVERSION
MOVLW 0xF1
MOVWF ADCON0
;configure A/D
;Sample code operates out of BANK0
MOVLW 0xF1
;configure A/D
BSF ADCON0, 1 ;start conversion
BSF ADCON0, 2 ;setup for read of
;channel 1
BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop0
MOVWF ADCON0
BSF ADCON0, 1 ;start conversion
BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop0
MOVF ADRES, W ;read result
MOVWF result0 ;save result
loop0
loop1
loop2
loop0
MOVF ADRES, W ;read result
MOVWF result0 ;save result
BSF ADCON0, 2 ;setup for read of
;channel 1
BSF ADCON0, 1 ;start conversion
BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop1
BSF ADCON0, 1 ;start conversion
BSF ADCON0, 3 ;setup for read of
BCF ADCON0, 2 ;channel 2
BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop1
loop1
loop2
MOVF ADRES, W ;read result
MOVWF result1 ;save result
MOVF ADRES, W ;read result
MOVWF result1 ;save result
BSF ADCON0, 3 ;setup for read of
BCF ADCON0, 2 ;channel 2
BSF ADCON0, 1 ;start conversion
BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop2
BSF ADCON0, 1 ;start conversion
BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop2
MOVF ADRES, W ;read result
MOVWF result2 ;save result
CLRF ADCON0
;pins to Digital mode and turns off
;the ADC module
MOVF ADRES, W ;read result
MOVWF result2 ;save result
;optional: returns
DS41268B-page 54
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
10.1 Configuration Bits
10.0 SPECIAL FEATURES OF THE
CPU
The PIC12F510/16F506 Configuration Words consist
of 12 bits. Configuration bits can be programmed to
select various device configurations. Three bits are for
the selection of the oscillator type; (two bits on the
PIC12F510), one bit is the Watchdog Timer enable bit,
one bit is the MCLR enable bit and one bit is for code
protection (Register 10-1, Register 10-2).
What sets a microcontroller apart from other proces-
sors are special circuits that deal with the needs of real-
time
applications.
The
PIC12F510/16F506
microcontrollers have a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power-
saving operating modes and offer code protection.
These features are:
• Oscillator Selection
• Reset:
- Power-on Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from Sleep on Pin Change
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming™ (ICSP™)
• Clock Out
The PIC12F510/16F506 devices have a Watchdog
Timer, which can be shut off only through Configuration
bit WDTE. It runs off of its own RC oscillator for added
reliability. If using HS (PIC16F506), XT or LP selectable
oscillator options, there is always a delay, provided by
the Device Reset Timer (DRT), intended to keep the
chip in Reset until the crystal oscillator is stable. If using
INTOSC, EXTRC or EC there is an 1.125 ms (nominal)
delay only on VDD power-up. With this timer on-chip,
most applications need no external Reset circuitry.
The Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
through a change-on-input pin or through a Watchdog
Timer time-out. Several oscillator options are also
made available to allow the part to fit the application,
including an internal 4/8 MHz oscillator. The EXTRC
oscillator option saves system cost while the LP crystal
option saves power. A set of Configuration bits are
used to select various options.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 55
PIC12F510/16F506
REGISTER 10-1: CONFIGURATION WORD – PIC12F510
—
—
—
—
—
—
IOSCFS MCLRE
CP
WDTE FOSC1 FOSC0
bit 0
bit 11
bit 11-6: Unimplemented: Read as ‘1’
bit 5
IOSCFS: Internal Oscillator Frequency Select bit
1= 8 MHz INTOSC speed
0= 4 MHz INTOSC speed
bit 4:
bit 3:
bit 2:
MCLRE: Master Clear Enable bit
1= GP3/MCLR pin functions as MCLR
0= GP3/MCLR pin functions as GP3, MCLR internally tied to VDD
CP: Code Protection bit
1= Code protection off
0= Code protection on
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
00= LP oscillator with 18 ms DRT
01= XT oscillator with 18 ms DRT
10= INTOSC with 1.125 ms DRT(1), (2)
11= EXTRC with 1.125 ms DRT(1), (2)
Note 1: Refer to the “PIC12F510 Memory Programming Specification”, DS41257 to determine how to
access the Configuration Word.
2: It is the responsibility of the application designer to ensure the use of the 1.125 ms (nominal)
DRT will result in acceptable operation. Refer to Electrical Specifications for VDD rise time and
stability requirements for this mode of operation.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = bit is cleared x = bit is unknown
DS41268B-page 56
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
REGISTER 10-2: CONFIGURATION WORD – PIC16F506
—
—
—
—
—
IOSCFS MCLRE
CP
WDTE FOSC2 FOSC1 FOSC0
bit 0
bit 11
bit 11-7: Unimplemented: Read as ‘1’
bit 6:
bit 5:
bit 4:
bit 3:
IOSCFS: Internal Oscillator Frequency Select bit
1= 8 MHz INTOSC speed
0= 4 MHz INTOSC speed
MCLRE: Master Clear Enable bit
1= RB3/MCLR pin functions as MCLR
0= RB3/MCLR pin functions as RB3, MCLR tied internally to VDD
CP: Code Protection bit
1= Code protection off
0= Code protection on
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 2-0: FOSC2:FOSC0: Oscillator Selection bits
000= LP oscillator and 18 ms DRT
001= XT oscillator and 18 ms DRT
010= HS oscillator and 18 ms DRT
011= EC oscillator with RB4 function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2)
100= INTOSC with RB4 function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2)
101= INTOSC with CLKOUT function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2)
110= EXTRC with RB4 function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2)
111= EXTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2)
Note 1: Refer to the “PIC16F506 Memory Programming Specification”, DS41258, to determine how to
access the Configuration Word.
2: It is the responsibility of the application designer to ensure the use of the 1.125 ms (nominal)
DRT will result in acceptable operation. Refer to Electrical Specifications for VDD rise time and
stability requirements for this mode of operation.
Legend:
R = Readable bit
-n = bLANK
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = bit is cleared x = bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 57
PIC12F510/16F506
FIGURE 10-1:
CRYSTAL OPERATION
(OR CERAMIC
RESONATOR)
10.2 Oscillator Configurations
10.2.1
OSCILLATOR TYPES
(HS, XT OR LP OSC
CONFIGURATION)
The PIC12F510/16F506 devices can be operated in up
to six different oscillator modes. The user can program
up to three Configuration bits (FOSC<1:0>
[PIC12F510], FOSC<2:0> [PIC16F506]). To select one
of these modes:
(1)
C1
PIC12F510
PIC16F506
OSC1
OSC2
Sleep
•LP:
•XT:
•HS:
Low-Power Crystal
Crystal/Resonator
XTAL
(3)
RF
To internal
logic
High-Speed Crystal/Resonator
(PIC16F506 only)
(2)
RS
(1)
C2
•INTOSC: Internal 4/8 MHz Oscillator
•EXTRC: External Resistor/Capacitor
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
•EC:
External High-Speed Clock Input
(PIC16F506 only)
3: RF approx. value = 10 MΩ.
10.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In HS (PIC16F506), XT or LP modes, a crystal or
ceramic resonator is connected to the (GP5/RB5)/
OSC1/(CLKIN) and (GP4/RB4)/OSC2/(CLKOUT) pins
to establish oscillation (Figure 10-1). The PIC12F510/
16F506 oscillator designs require the use of a parallel
cut crystal. Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers specifications.
When in HS (PIC16F506), XT or LP modes, the device
can have an external clock source drive the (GP5/
RB5)/OSC1/CLKIN pin (Figure 10-2).
FIGURE 10-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
OSC1
Clock from
ext. system
PIC12F510
PIC16F506
Open
OSC2
Note 1: This device has been designed to per-
form to the parameters of its data sheet.
It has been tested to an electrical
specification designed to determine its
conformance with these parameters.
Due to process differences in the
manufacture of this device, this device
may have different performance charac-
teristics than its earlier version. These
differences may cause this device to
perform differently in your application
than the earlier version of this device.
TABLE 10-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS –
PIC12F510/16F506(1)
Osc.
Type
Resonator Cap. Range Cap. Range
Freq.
C1
C2
XT
HS(2)
4.0 MHz
16 MHz
30 pF
30 pF
10-47 pF
10-47 pF
Note 1: These values are for design guidance
only. Since each resonator has its own
characteristics, the user should consult
the resonator manufacturer for
appropriate values of external
2: The user should verify that the device
oscillator starts and performs as
expected. Adjusting the loading capacitor
values and/or the Oscillator mode may
be required.
components.
2: PIC16F506 only.
DS41268B-page 58
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
TABLE 10-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR –
FIGURE 10-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
PIC12F510/16F506(2)
+5V
Osc.
Type
Resonator Cap.Range Cap. Range
To Other
Devices
Freq.
C1
C2
10k
32 kHz(1)
15 pF
15 pF
4.7k
74AS04
LP
XT
200 kHz
1 MHz
4 MHz
47-68 pF
15 pF
15 pF
47-68 pF
15 pF
15 pF
CLKIN
74AS04
PIC12F510
PIC16F506
(3)
10k
HS
20 MHz
15-47 pF
15-47 pF
XTAL
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
10k
2: These values are for design guidance
only. Rs may be required to avoid over-
driving crystals beyond the drive level
specification. Since each crystal has its
own characteristics, the user should con-
sult the crystal manufacturer for appropri-
ate values of external components.
20 pF
20 pF
Figure 10-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180-
degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
3: PIC16F506 only.
10.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
FIGURE 10-4:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good perfor-
mance with TTL gates. Two types of crystal oscillator
circuits can be used: one with parallel resonance or one
with series resonance.
To Other
Devices
330
330
74AS04
74AS04
74AS04
CLKIN
0.1 mF
XTAL
PIC12F510
PIC16F506
Figure 10-3 shows implementation of a parallel reso-
nant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a
parallel oscillator requires. The 4.7 kΩ resistor provides
the negative feedback for stability. The 10 kΩ potenti-
ometers bias the 74AS04 in the linear region. This
circuit could be used for external oscillator designs.
10.2.4
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the EXTRC device
option offers additional cost savings. The EXTRC oscil-
lator frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit-to-unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C
components used.
Figure 10-5 shows how the R/C combination is
connected to the PIC12F510/16F506 devices. For
REXT values below 5.0 kΩ, the oscillator operation may
become unstable or stop completely. For very high
REXT values (e.g., 1 MΩ), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, we
recommend keeping REXT between 5.0 kΩ and
100 kΩ.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 59
PIC12F510/16F506
Although the oscillator will operate with no external
capacitor (CEXT = 0pF), we recommend using values
above 20 pF for noise and stability reasons. With no
capacitance or small external capacitance, the oscilla-
tion frequency can vary dramatically due to changes in
external capacitances, such as PCB trace capacitance
or package lead frame capacitance.
FIGURE 10-6:
EXTERNAL CLOCK INPUT
OPERATION
PIC16F506: EC, HS, XT, LP
Clock From
ext. system
RB5/OSC1/CLKIN
(1)
Section 13.0 “Electrical Characteristics”, shows RC
frequency variation from part-to-part due to normal
process variation. The variation is larger for larger val-
ues of R (since leakage current variation will affect RC
frequency more for large R) and for smaller values of C
(since variation of input capacitance will affect RC
frequency more).
OSC2/CLKOUT/RB4
OSC2/CLKOUT/RB4
PIC12F510: XT, LP
Clock From
ext. system
GP5/OSC1/CLKIN
GP4/OSC2
OSC2
Also, see the Electrical Specifications section for
variation of oscillator frequency due to VDD for given
REXT/CEXT values, as well as frequency variation due
to operating temperature for given R, C and VDD
values.
Note 1: RB4 is available in EC mode only.
In addition, a calibration instruction is programmed into
the last address of memory, which contains the calibra-
tion value for the internal RC oscillator. This location is
always uncode protected, regardless of the code-pro-
tect settings. This value is programmed as a MOVLW XX
instruction where XX is the calibration value, and is
placed at the Reset vector. This will load the W register
with the calibration value upon Reset and the PC will
then roll over to the users program at address 0x000.
The user then has the option of writing the value to the
OSCCAL Register (05h) or ignoring it.
FIGURE 10-5:
EXTERNAL RC
OSCILLATOR MODE
VDD
REXT
Internal
clock
OSC1
N
CEXT
VSS
PIC12F510
PIC16F506
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency.
OSC2/CLKOUT
FOSC/4
Note:
Erasing the device will also erase the pre-
programmed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
10.2.5
INTERNAL 4/8 MHz RC
OSCILLATOR
The internal RC oscillator provides a fixed 4/8 MHz
(nominal) system clock (see Section 13.0 “Electrical
Characteristics” for information on variation over
voltage and temperature).
For the PIC12F510/16F506 devices, only bits <7:1> of
OSCCAL are implemented. Bits CAL6-CAL0 are used
for calibration. Adjusting CAL6-CAL0 from ‘0000000’
to ‘1111111’ changes the clock speed. See
Register 4-3 for more information.
10.2.6
EXTERNAL CLOCK IN
For applications where a clock is already available
elsewhere, users may directly drive the PIC12F510/
16F506 devices provided that this external clock
source meets the AC/DC timing requirements listed in
Section 10.6 “Watchdog Timer (WDT)”. Figure 10-6
below shows how an external clock circuit should be
configured.
Note:
The 0 bit of OSCCAL is unimplemented
and should be written as ‘0’ when modify-
ing OSCCAL for compatibility with future
devices.
DS41268B-page 60
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
10.3 Reset
The device differentiates between various kinds of
Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during Sleep
• WDT Time-out Reset during normal operation
• WDT Time-out Reset during Sleep
• Wake-up from Sleep Reset on pin change
• Wake-up from Sleep Reset on comparator
change
Some registers are not reset in any way, they are
unknown on POR and unchanged in any other Reset.
Most other registers are reset to “Reset state” on
Power-on Reset (POR), MCLR, WDT or Wake-up from
Sleep Reset on pin change or wake-up from Sleep
Reset on comparator change. The exceptions are TO,
PD, CWUF and RBWUF/GPWUF bits. They are set or
cleared differently in different Reset situations. These
bits are used in software to determine the nature of
Reset. See Table 10-4 for a full description of Reset
states of all registers.
TABLE 10-3: RESET CONDITIONS FOR REGISTERS – PIC12F510
MCLR Reset, WDT Time-out,
Register
Address
Power-on Reset
Wake-up On Pin Change, Wake-up on
Comparator Change
W
—
qqqq qqqu(1)
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
110x xxxx
1111 111-
--xx xxxx
qqqq qqqu(1)
uuuu uuuu
uuuu uuuu
1111 1111
qq0q quuu(2)
11uu uuuu
uuuu uuu-
--uu uuuu
INDF
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
—
TMR0
PCL
STATUS
FSR
OSCCAL
GPIO
CM1CON0
ADCON0
ADRES
OPTION
TRISIO
1111 1111
1111 1100
xxxx xxxx
1111 1111
--11 1111
uuuu uuuu
uu11 1100
uuuu uuuu
1111 1111
—
--11 1111
Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.
Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of
memory.
2: See Table 10-5 for Reset value for specific conditions.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 61
PIC12F510/16F506
TABLE 10-4: RESET CONDITIONS FOR REGISTERS – PIC16F506
MCLR Reset, WDT Time-out,
Register
Address
Power-on Reset
Wake-up On Pin Change, Wake-up on
Comparator Change
W
—
qqqq qqqu(1)
xxxx xxxx
xxxx xxxx
1111 1111
qqqq qqqu(1)
uuuu uuuu
uuuu uuuu
1111 1111
INDF
00h
01h
02h
TMR0
PCL
STATUS
FSR
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
—
0001 1xxx
110x xxxx
1111 111-
--xx xxxx
--xx xxxx
1111 1111
1111 1100
xxxx xxxx
1111 1111
001- 1111
1111 1111
--11 1111
--11 1111
qq0q quuu(2)
11uu uuuu
uuuu uuu-
--uu uuuu
--uu uuuu
uuuu uuuu
uu11 1100
uuuu uuuu
OSCCAL
PORTB
PORTC
CM1CON0
ADCON0
ADRES
CM2CON0
VRCON
OPTION
TRISB
1111 1111
--11 1111
--11 1111
—
TRISC
—
Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.
Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of
memory.
2: See Table 10-5 for Reset value for specific conditions.
TABLE 10-5: RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
PCL Addr: 02h
Power-on Reset
0001 1xxx
000u uuuu
0001 0uuu
0000 0uuu
0000 uuuu
1001 0uuu
0101 0uuu
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset during Sleep
WDT Reset normal operation
Wake-up from Sleep Reset on pin change
Wake from Sleep Reset on Comparator
Change
Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’.
DS41268B-page 62
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 10-8.
10.3.1
MCLR ENABLE
This Configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD and the pin is assigned to be a I/O. See
Figure 10-7.
The Power-on Reset circuit and the Device Reset
Timer (see Section 10.5 “Device Reset Timer
(DRT)”) circuit are closely related. On power-up, the
Reset latch is set and the DRT is reset. The DRT timer
begins counting once it detects MCLR, internal or
external, to be high. After the time-out period, it will
reset the Reset latch and thus end the on-chip Reset
signal.
FIGURE 10-7:
MCLR SELECT
GPWU/RBWU
A power-up example where MCLR is held low is shown
in Figure 10-9. VDD is allowed to rise and stabilize
before bringing MCLR high. The chip will actually come
out of Reset TDRT msec after MCLR goes high.
(GP3/RB3)/MCLR/VPP
Internal MCLR
MCLRE
In Figure 10-10, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together or the pin
is programmed to be (GP3/RB3). The VDD is stable
before the Start-up timer times out and there is no prob-
lem in getting a proper Reset. However, Figure 10-11
depicts a problem situation where VDD rises too slowly.
The time between when the DRT senses that MCLR is
high and when MCLR and VDD actually reach their full
value, is too long. In this situation, when the start-up
timer times out, VDD has not reached the VDD (min)
value and the chip may not function correctly. For such
situations, we recommend that external RC circuits be
used to achieve longer POR delay times (Figure 10-10).
10.4 Power-on Reset (POR)
The PIC12F510/16F506 devices incorporate an on-
chip Power-on Reset (POR) circuitry, which provides
an internal chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper oper-
ation. The POR is active regardless of the state of the
MCLR enable bit. An internal weak pull-up resistor is
implemented using a transistor (refer to Table 13-4 for
the pull-up resistor ranges). This will eliminate external
RC components usually needed to create an external
Power-on Reset. A maximum rise time for VDD is spec-
ified. See Section 13.0 “Electrical Characteristics”
for details.
Note:
When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency,
temperature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
When the devices start normal operation (exit the
Reset condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
For additional information, refer to Application Notes
AN522, “Power-Up Considerations” (DS00522) and
AN607, “Power-up Trouble Shooting” (DS00607).
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 63
PIC12F510/16F506
FIGURE 10-8:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
VDD
Power-up
Detect
POR (Power-on Reset)
MCLR Reset
(GP3/RB3)/MCLR/VPP
S
R
Q
Q
MCLRE
WDT Reset
Start-up Timer
WDT Time-out
CHIP Reset
(10 ms, 1.125 ms
or 18 ms)
Pin Change
Sleep
Wake-up on pin Change Reset
Comparator Change
Wake-up on
Comparator Change
FIGURE 10-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
FIGURE 10-10:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
DS41268B-page 64
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 10-11:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
V1
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
Note:
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 65
PIC12F510/16F506
TABLE 10-6: TYPICAL DRT PERIODS
10.5 Device Reset Timer (DRT)
Oscillator
Configuration
Subsequent
On the PIC12F510/16F506 devices, the DRT runs any
time the device is powered up. DRT runs from Reset
and varies based on oscillator selection and Reset type
(see Table 10-6).
POR Reset
Resets
LP
18 ms
18 ms
18 ms
18 ms
18 ms
10 μs
10 μs
10 μs
XT
The DRT operates from a free running on-chip oscilla-
tor that is separate from INTOSC. The processor is
kept in Reset as long as the DRT is active. The DRT
delay allows VDD to rise above VDD minimum and for
the oscillator to stabilize.
HS(1)
18 ms
EC(1)
1.125 ms
1.125 ms
1.125 ms
INTOSC
EXTRC
Oscillator circuits, based on crystals or ceramic resona-
tors, require a certain time after power-up to establish
a stable oscillation. The on-chip DRT keeps the devices
in a Reset for a set period, as stated in Table 10-6, after
MCLR has reached a logic high (VIH MCLR) level.
Programming (GP3/RB3)/MCLR/VPP as MCLR and
using an external RC network connected to the MCLR
input is not required in most cases. This allows savings
in cost-sensitive and/or space restricted applications,
as well as allowing the use of the (GP3/RB3)/MCLR/
VPP pin as a general purpose input.
Note 1: PIC16F506 only
Note:
It is the responsibility of the application
designer to ensure the use of the
1.125 ms nominal DRT will result in
acceptable operation. Refer to Electrical
Specifications for VDD rise time and
stability requirements for this mode of
operation.
The DRT delays will vary from chip-to-chip due to VDD,
temperature and process variation. See AC
parameters for details.
10.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms (with
no prescaler). If a longer time-out period is desired, a
prescaler with a divisor ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These
periods vary with temperature, VDD and part-to-part
process variations (see DC specs).
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out, Wake-
up on Pin Change and Wake-up on Comparator
Change. See Section 10.9.2 “Wake-up from Sleep
Reset”, Notes 1, 2 and 3.
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
10.6 Watchdog Timer (WDT)
10.6.2
WDT PROGRAMMING
CONSIDERATIONS
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator that does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the (GP5/RB5)/OSC1/CLKIN
pin and the internal 4/8 MHz oscillator. This means that
the WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset generates a device Reset.
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by program-
ming the configuration WDTE as
a
‘0’ (see
Section 10.1 “Configuration Bits”). Refer to the
PIC12F510/16F506 Programming Specifications to
determine how to access the Configuration Word.
DS41268B-page 66
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 10-12:
WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 6-5)
0
M
U
X
Postscaler
1
Watchdog
Timer
8-to-1 MUX
PS<2:0>
PSA
WDTE
(Figure 6-4)
To Timer0
0
1
MUX
PSA
WDT Time-out
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
TABLE 10-7: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Value on
All Other
Resets
Address
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On
Reset
N/A
N/A
OPTION(1) GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
OPTION(2) RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer. – = unimplemented, read as ‘0’, u= unchanged.
Note 1: PIC12F510 only.
2: PIC16F506 only.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 67
PIC12F510/16F506
FIGURE 10-14:
BROWN-OUT
PROTECTION CIRCUIT 2
10.7 Time-out Sequence, Power-down
and Wake-up from Sleep Status
Bits (TO, PD, GPWUF/RBWUF)
VDD
VDD
The TO, PD and (GPWUF/RBWUF) bits in the STATUS
register can be tested to determine if a Reset condition
has been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) Reset.
R1
R2
PIC12F510
PIC16F506
Q1
(2)
MCLR
(1)
40k
TABLE 10-8: TO/PD/(GPWUF/RBWUF)
STATUS AFTER RESET
GPWUF/
RBWUF
CWUF
TO PD
Reset Caused By
Note 1: This brown-out circuit is less expensive,
although less accurate. Transistor Q1 turns
off when VDD is below a certain level such
that:
0
0
0
0
1
0
u
0
WDT wake-up from
Sleep
0
0
0
0
WDT time-out (not
from Sleep)
R1
= 0.7V
VDD •
R1 + R2
MCLR wake-up from
Sleep
2: Pin must be configured as MCLR.
0
0
0
0
1
u
1
u
Power-up
FIGURE 10-15:
BROWN-OUT
PROTECTION CIRCUIT 3
MCLR not during
Sleep
VDD
0
1
1
0
1
1
0
0
Wake-up from Sleep
on pin change
MCP809
VDD
Bypass
Capacitor
Wake-up from Sleep
on comparator
change
VSS
VDD
RST
MCLR
Legend: u= unchanged
PIC12F510
PIC16F506
10.8 Reset on Brown-out
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.
Note:
This brown-out protection circuit employs
Microchip Technology’s MCP809 microcon-
troller supervisor. There are 7 different trip
point selections to accommodate 5V to 3V
systems.
To reset PIC12F510/16F506 devices when a brown-
out occurs, external brown-out protection circuits may
be built, as shown in Figure 10-13 and Figure 10-14.
FIGURE 10-13:
BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
33k
PIC12F510
PIC16F506
Q1
(2)
MCLR
10k
(1)
40k
Note 1: This circuit will activate Reset when VDD goes
below Vz + 0.7V (where Vz = Zener voltage).
2: Pin must be configured as MCLR.
DS41268B-page 68
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
10.9 Power-Down Mode (Sleep)
Note 1: Caution: Right before entering Sleep,
read the comparator Configuration
register(s) CM1CON0 and CM2CON0.
When in Sleep, wake-up occurs when the
comparator output bit C1OUT and
C2OUT change from the state they were
in at the last reading. If a wake-up on
comparator change occurs and the pins
are not read before re-entering Sleep, a
wake-up will occur immediately, even if
no pins change while in Sleep mode.
A device may be powered down (Sleep) and later
powered up (wake-up from Sleep Reset).
10.9.1
SLEEP
The Power-Down mode is entered by executing a
SLEEPinstruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or high-impedance).
2: For 16F506 only.
The WDT is cleared when the device wakes from
Sleep, regardless of the wake-up source.
Note:
A device Reset generated by a WDT
time-will not drive the MCLR pin low.
For lowest current consumption while powered down,
all input pins should be at VDD or VSS and (GP3/RB3)/
MCLR/VPP pin must be at a logic high level if MCLR is
enabled.
10.10 Program Verification/Code
Protection
If the code protection bit has not been programmed, the
on-chip program memory can be read out for
verification purposes.
10.9.2
WAKE-UP FROM SLEEP RESET
The device can wake-up from Sleep through one of the
following events:
The first 64 locations and the last location (OSCCAL)
can be read, regardless of the code protection bit
setting.
1. An external Reset input on (GP3/RB3)/MCLR/
VPP pin when configured as MCLR.
The last memory location can be read regardless of the
code protection bit setting on the PIC12F510/16F506
devices.
2. A Watchdog Timer Time-out Reset (if WDT was
enabled).
3. A change-on-input pin GP0/RB0, GP1/RB1,
GP3/RB3 or RB4 when wake-up on change is
enabled.
10.11 ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other code
identification numbers. These locations are not
accessible during normal execution, but are readable
and writable during Program/Verify.
4. A change in the comparator ouput bits, C1OUT
and C2OUT (if comparator wake-up is enabled).
These events cause a device Reset. The TO, PD,
CWUF and GPWUF/RBWUF bits can be used to deter-
mine the cause of device Reset. The TO bit is cleared
if a WDT time-out occurred (and caused wake-up). The
PD bit, which is set on power-up, is cleared when
SLEEPis invoked. The CWUF bit indicates a change in
comparator output state while the device was in Sleep.
The GPWUF/RBWUF bit indicates a change in state
while in Sleep at pins GP0/RB0, GP1/RB1, GP3/RB3
or RB4 (since the last file or bit operation on GP/RB
port).
Use only the lower 4 bits of the ID locations and always
set the upper 4 bits as ‘1’s. The upper 4 bits are
unimplemented.
These locations can be read regardless of the code
protect setting.
Note:
Caution: Right before entering Sleep,
read the input pins. When in Sleep, wake-
up occurs when the values at the pins
change from the state they were in at the
last reading. If a wake-up on change
occurs and the pins are not read before
reentering Sleep, a wake-up will occur
immediately even if no pins change while
in Sleep mode.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 69
PIC12F510/16F506
FIGURE 10-16:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
10.12 In-Circuit Serial Programming™
(ICSP™)
The PIC12F510/16F506 microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock and data,
and three other lines for power, ground and the
programming voltage. This allows customers to manu-
facture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware, or
a custom firmware, to be programmed.
To Normal
Connections
PIC12F510
PIC16F506
External
Connector
Signals
+5V
0V
VDD
VSS
VPP
MCLR/VPP
The devices are placed into a Program/Verify mode by
holding the GP1/RB1 and GP0/RB0 pins low while rais-
ing the MCLR (VPP) pin from VIL to VIHH (see program-
GP1/RB1
GP0/RB0
CLK
Data I/O
ming
specification).
GP1/RB1
becomes
the
programming clock and GP0/RB0 becomes the
programming data. Both GP1/RB1 and GP0/RB0 are
Schmitt Trigger inputs in this mode.
VDD
To Normal
Connections
After Reset, a 6-bit command is supplied to the device.
Depending on the command and if the command was a
Load or a Read, 14 bits of program data are then sup-
plied to or from the device. For complete details of serial
programming, please refer to the PIC12F510/16F506
Programming Specifications.
A typical In-Circuit Serial Programming connection is
shown in Figure 10-16.
DS41268B-page 70
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 μs.
11.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC16 instruction is a 12-bit word divided into an
opcode, which specifies the instruction type, and one
or more operands which further specify the operation
of the instruction. The formats for each of the catego-
ries is presented in Figure 11-1, while the various
opcode fields are summarized in Table 11-1.
Figure 11-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal
number:
0xhhh
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
where ‘h’ signifies a hexadecimal digit.
FIGURE 11-1:
GENERAL FORMAT FOR
INSTRUCTIONS
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the result is placed
in the file register specified in the instruction.
Byte-oriented file register operations
11
6
5
d
4
0
OPCODE
f (FILE #)
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bits
affected by the operation, while ‘f’ represents the
number of the file in which the bit is located.
d = 0for destination W
d = 1for destination f
f = 5-bit file register address
Bit-oriented file register operations
11 8 7
b (BIT #)
For literal and control operations, ‘k’ represents an
8 or 9-bit constant or literal value.
5
4
0
OPCODE
f (FILE #)
b = 3-bit bit address
f = 5-bit file register address
TABLE 11-1: OPCODE FIELD
DESCRIPTIONS
Literal and control operations (except GOTO)
11
Field
Description
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
8
7
0
OPCODE
k (literal)
Bit address within an 8-bit file register
Literal field, constant data or label
k = 8-bit immediate value
Don’t care location (= 0or 1)
Literal and control operations – GOTOinstruction
11
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
9
8
0
OPCODE
k (literal)
d
Destination select;
d= 0(store result in W)
d= 1(store result in file register ‘f’)
Default is d= 1
k = 9-bit immediate value
label
TOS
PC
Label name
Top-of-Stack
Program Counter
Watchdog Timer counter
WDT
TO
Time-out bit
PD
Power-down bit
dest
Destination, either the W register or the specified
register file location
[
(
]
)
Options
Contents
→
Assigned to
Register bit field
In the set of
< >
∈
italics User defined term (font is courier)
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 71
PIC12F510/16F506
TABLE 11-2: INSTRUCTION SET SUMMARY
12-Bit Opcode
MSb LSb
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
1
1
1
1
1
0001 11df ffff C, DC, Z 1, 2, 4
0001 01df ffff
0000 011f ffff
0000 0100 0000
0010 01df ffff
0000 11df ffff
0010 11df ffff
0010 10df ffff
0011 11df ffff
0001 00df ffff
0010 00df ffff
0000 001f ffff
0000 0000 0000
0011 01df ffff
0011 00df ffff
Z
Z
Z
Z
Z
None
Z
None
Z
2, 4
4
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1
2, 4
2, 4
2, 4
2, 4
2, 4
2, 4
1, 4
DECFSZ
INCF
1(2)
1
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
1(2)
1
1
1
1
1
1
1
1
1
Z
None
None
C
–
f, d
f, d
f, d
f, d
f, d
2, 4
2, 4
C
0000 10df ffff C, DC, Z 1, 2, 4
0011 10df ffff
0001 10df ffff
None
Z
2, 4
2, 4
Exclusive OR W with f
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
0100 bbbf ffff
None
None
None
None
2, 4
2, 4
0101 bbbf ffff
0110 bbbf ffff
0111 bbbf ffff
1(2)
1(2)
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
k
k
–
k
k
k
–
k
–
f
AND literal with W
Call Subroutine
1
2
1
2
1
1
1
2
1
1
1
1110 kkkk kkkk
1001 kkkk kkkk
0000 0000 0100 TO, PD
101k kkkk kkkk
1101 kkkk kkkk
1100 kkkk kkkk
0000 0000 0010
1000 kkkk kkkk
Z
None
1
3
Clear Watchdog Timer
Unconditional branch
Inclusive OR literal with W
Move literal to W
Load OPTION register
Return, place literal in W
Go into Standby mode
Load TRIS register
None
Z
None
None
None
0000 0000 0011 TO, PD
0000 0000 0fff
1111 kkkk kkkk
None
Z
XORLW
k
Exclusive OR literal to W
Note 1: The 9th bit of the Program Counter will be forced to a ‘0’ by any instruction that writes to the PC except for
GOTO. See Section 4.6 “Program Counter”.
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state
latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
DS41268B-page 72
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
ADDWF
Add W and f
BCF
Bit Clear f
Syntax:
[ label ] ADDWF f,d
Syntax:
[ label ] BCF f,b
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Operation:
(W) + (f) → (dest)
Operation:
0 → (f<b>)
Status
C, DC, Z
Status Affected: None
Affected:
Description:
Bit ‘b’ in register ‘f’ is cleared.
Description:
Add the contents of the W register
and register ‘f’. If ‘d’ is ‘0’, the result
is stored in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
ANDLW
AND literal with W
BSF
Bit Set f
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] BSF f,b
Operands:
Operation:
Status Affected:
Description:
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
(W).AND. (k) → (W)
Operation:
1 → (f<b>)
Z
Status Affected: None
The contents of the W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
Description:
Bit ‘b’ in register ‘f’ is set.
ANDWF
AND W with f
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] ANDWF f,d
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Operation:
(W) .AND. (f) → (dest)
Operation:
skip if (f<b>) = 0
Status Affected: Z
Status Affected: None
Description: The contents of the W register are
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W regis-
ter. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next instruc-
tion fetched during the current
instruction execution is discarded,
and a NOPis executed instead,
making this a two-cycle instruction.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 73
PIC12F510/16F506
BTFSS
Bit Test f, Skip if Set
CLRW
Clear W
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRW
Operands:
0 ≤ f ≤ 31
0 ≤ b < 7
Operands:
Operation:
None
00h → (W);
1 → Z
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected:
Description:
Z
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the
The W register is cleared. Zero bit
(Z) is set.
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOPis executed instead,
making this a two-cycle instruction.
CALL
Subroutine Call
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
0 ≤ k ≤ 255
Syntax:
[ label ] CLRWDT
Operands:
Operation:
Operands:
Operation:
None
(PC) + 1→ Top-of-Stack;
k → PC<7:0>;
00h → WDT;
0 → WDT prescaler (if assigned);
(STATUS <6:5>) → PC<10:9>;
0 → PC<8>
1 → TO;
1 → PD
Status Affected: None
Status Affected: TO, PD
Description:
Subroutine call. First, return
Description:
The CLRWDTinstruction resets the
address (PC + 1) is PUSHed onto
the stack. The eight-bit immediate
address is loaded into PC
WDT. It also resets the prescaler,
if the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
bits <7:0>. The upper bits
PC<10:9> are loaded from
STATUS <6:5>, PC<8> is cleared.
CALLis a two-cycle instruction.
CLRF
Clear f
COMF
Complement f
Syntax:
[ label ] CLRF
0 ≤ f ≤ 31
f
Syntax:
[ label ] COMF f,d
Operands:
Operation:
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
00h → (f);
1 → Z
Operation:
(f) → (dest)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ‘f’ are
cleared and the Z bit is set.
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
DS41268B-page 74
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
DECF
Decrement f
INCF
Increment f
Syntax:
[ label ] DECF f,d
Syntax:
[ label ] INCF f,d
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) – 1 → (dest)
Operation:
(f) + 1 → (dest)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) – 1 → d; skip if result = 0
Operation:
(f) + 1 → (dest), skip if result = 0
Status Affected: None
Status Affected: None
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOPis executed
instead making it a two-cycle
instruction.
If the result is ‘0’, then the next
instruction, which is already
fetched, is discarded and a NOPis
executed instead making it a
two-cycle instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ] GOTO k
0 ≤ k ≤ 511
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k → PC<8:0>;
STATUS <6:5> → PC<10:9>
(W) .OR. (k) → (W)
Z
Status Affected: None
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W register.
Description: GOTOis an unconditional branch.
The 9-bit immediate value is
loaded into PC bits <8:0>. The
upper bits of PC are loaded from
STATUS <6:5>. GOTOis a two-
cycle instruction.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 75
PIC12F510/16F506
IORWF
Inclusive OR W with f
MOVWF
Move W to f
Syntax:
[ label ] IORWF f,d
Syntax:
[ label ] MOVWF
0 ≤ f ≤ 31
f
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
Operation:
(W) → (f)
Operation:
(W).OR. (f) → (dest)
Status Affected: None
Status Affected:
Description:
Z
Description:
Move data from the W register to
register ‘f’.
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is placed back in register
‘f’.
MOVF
Move f
NOP
No Operation
Syntax:
[ label ] MOVF f,d
Syntax:
[ label ] NOP
None
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
Operation:
No operation
Operation:
(f) → (dest)
Status Affected: None
Status Affected:
Description:
Z
Description:
No operation.
The contents of register ‘f’ are
moved to destination ‘d’. If ‘d’ is ‘0’,
destination is the W register. If ‘d’
is ‘1’, the destination is file
register ‘f’. ‘d’ = 1is useful as a
test of a file register, since Status
flag Z is affected.
MOVLW
Move Literal to W
OPTION
Load OPTION Register
Syntax:
[ label ] Option
None
Syntax:
[ label ] MOVLW k
0 ≤ k ≤ 255
Operands:
Operation:
Operands:
Operation:
(W) → Option
k → (W)
Status Affected: None
Status Affected: None
Description: The content of the W register is
Description:
The eight-bit literal ‘k’ is loaded
into the W register. The “don’t
loaded into the OPTION register.
cares” will be assembled as ‘0’s.
DS41268B-page 76
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
RETLW
Return with Literal in W
SLEEP
Enter SLEEP Mode
Syntax:
[ label ] RETLW k
0 ≤ k ≤ 255
Syntax:
[label ] SLEEP
Operands:
Operation:
Operands:
Operation:
None
k → (W);
TOS → PC
00h → WDT;
0 → WDT prescaler;
1 → TO;
Status Affected: None
0 → PD
Description:
The W register is loaded with the
Status Affected: TO, PD, RBWUF
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
Description:
Time-out Status bit (TO) is set.
The Power-down Status bit (PD) is
cleared.
RBWUF is unaffected.
The WDT and its prescaler are
cleared.
The processor is put into Sleep
mode with the oscillator stopped.
See Section 10.9 “Power-Down
Mode (Sleep)” on Sleep for more
details.
RLF
Rotate Left f through Carry
SUBWF
Syntax:
Subtract W from f
Syntax:
[ label ] RLF f,d
[label ] SUBWF f,d
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
See description below
C
Operation:
(f) – (W) → (dest)
Status Affected:
Description:
Status Affected: C, DC, Z
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
Description:
Subtract (2’s complement method)
the W register from register ‘f’. If ‘d’
is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
register ‘f’
C
RRF
Rotate Right f through Carry
SWAPF
Swap Nibbles in f
Syntax:
[ label ] RRF f,d
Syntax:
[ label ] SWAPF f,d
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
See description below
C
Operation:
(f<3:0>) → (dest<7:4>);
(f<7:4>) → (dest<3:0>)
Status Affected:
Description:
Status Affected: None
The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
register ‘f’
C
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 77
PIC12F510/16F506
TRIS
Load TRIS Register
XORWF
Exclusive OR W with f
Syntax:
[ label ] TRIS
f
Syntax:
[ label ] XORWF f,d
Operands:
Operation:
f = 6
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
(W) → TRIS register f
Status Affected: None
Operation:
(W) .XOR. (f) → (dest)
Description:
TRIS register ‘f’ (f = 6 or 7) is
loaded with the contents of the W
register
Status Affected:
Description:
Z
Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
XORLW
Exclusive OR literal with W
Syntax:
[label ] XORLW k
0 ≤ k ≤ 255
Operands:
Operation:
Status Affected:
Description:
(W) .XOR. k → (W)
Z
The contents of the W register are
XOR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
DS41268B-page 78
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
12.1 MPLAB Integrated Development
Environment Software
12.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
- PICSTART® Plus Development Programmer
• Drag and drop variables from source to watch
windows
- MPLAB PM3 Device Programmer
• Extensive on-line help
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PICmicro MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 79
PIC12F510/16F506
12.2 MPASM Assembler
12.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
12.6 MPLAB SIM Software Simulator
12.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PICmicro MCUs and dsPIC® DSCs on an
instruction level. On any given instruction, the data
areas can be examined or modified and stimuli can be
applied from a comprehensive stimulus controller.
Registers can be logged to files for further run-time
analysis. The trace buffer and logic analyzer display
extend the power of the simulator to record and track
program execution, actions on I/O, as well as internal
registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 family of microcontrollers and
dsPIC30F family of digital signal controllers. These
compilers provide powerful integration capabilities,
superior code optimization and ease of use not found
with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the laboratory environment, making it an excellent,
economical software development tool.
12.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS41268B-page 80
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
12.7 MPLAB ICE 2000
High-Performance
12.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PICmicro
MCUs and can be used to develop for these and other
PICmicro MCUs and dsPIC DSCs. The MPLAB ICD 2
utilizes the in-circuit debugging capability built into
the Flash devices. This feature, along with Microchip’s
In-Circuit Serial ProgrammingTM (ICSPTM) protocol,
offers cost-effective, in-circuit Flash debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by setting breakpoints,
single stepping and watching variables, and CPU
status and peripheral registers. Running at full speed
enables testing hardware and applications in real
time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
12.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PICmicro devices without a PC connection. It can also
set code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
12.8 MPLAB ICE 4000
High-Performance
In-Circuit Emulator
The MPLAB ICE 4000 In-Circuit Emulator is intended to
provide the product development engineer with a
complete microcontroller design tool set for high-end
PICmicro MCUs and dsPIC DSCs. Software control of
the MPLAB ICE 4000 In-Circuit Emulator is provided by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICE 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, and up to 2 Mb of emulation memory.
The MPLAB ICE 4000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 81
PIC12F510/16F506
12.11 PICSTART Plus Development
Programmer
12.12 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PICmicro devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PICmicro MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) for
the complete list of demonstration, development and
evaluation kits.
DS41268B-page 82
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
13.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Ambient temperature under bias..........................................................................................................-40°C to +125°C
Storage temperature ............................................................................................................................-65°C to +150°C
Voltage on VDD with respect to VSS ...............................................................................................................0 to +7.0V
Voltage on MCLR with respect to VSS.............................................................................................................0 to +14V
Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ..................................................................................................................................700 mW
Max. current out of VSS pin ................................................................................................................................200 mA
Max. current into VDD pin...................................................................................................................................150 mA
Input clamp current, IIK (VI < 0 or VI > VDD)................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ........................................................................................................... 20 mA
Max. output current sunk by any I/O pin ..............................................................................................................25 mA
Max. output current sourced by any I/O pin.........................................................................................................25 mA
Max. output current sourced by I/O port ............................................................................................................100 mA
Max. output current sunk by I/O port .................................................................................................................100 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 83
PIC12F510/16F506
VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C (PIC12F510)
FIGURE 13-1:
6.0
5.5
5.0
4.5
4.0
3.5
VDD
(Volts)
3.0
2.5
2.0
0
4
8
10
20
25
Frequency (MHz)
MAXIMUM OSCILLATOR FREQUENCY TABLE (PIC12F510)
FIGURE 13-2:
LP
XT
EXTRC
INTOSC
0
200 kHz
4 MHz
8 MHz
20 MHz
Frequency (MHz)
DS41268B-page 84
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
VOLTAGE FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C (PIC16F506)
FIGURE 13-3:
6.0
5.5
5.0
4.5
4.0
3.5
VDD
(Volts)
3.0
2.5
2.0
0
4
8
10
20
25
Frequency (MHz)
MAXIMUM OSCILLATOR FREQUENCY TABLE (PIC16F506)
FIGURE 13-4:
LP
XT
EXTRC
INTOSC
EC
HS
0
200 kHz
4 MHz
8 MHz
20 MHz
Frequency (MHz)
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 85
PIC12F510/16F506
DC Characteristics: PIC12F510/16F506 (Industrial)
13.1
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (Industrial)
DC CHARACTERISTICS
Parm
Sym
Characteristic
Min Typ(1) Max Units
Conditions
No.
D001
D002
VDD
VDR
Supply Voltage
2.0
—
—
5.5
—
V
V
See Figure 13-1
RAM Data Retention
Voltage(2)
1.5*
Device in Sleep mode
D003
D004
D010
VPOR VDD Start Voltage to
—
Vss
—
—
—
V
See Section 10.4 “Power-on Reset
(POR)”
ensure Power-on Reset
SVDD VDD Rise Rate to ensure 0.05*
V/ms See Section 10.4 “Power-on Reset
(POR)” for details
Power-on Reset
IDD
Supply Current(3)
—
—
—
—
170 TBD
μA FOSC = 4 MHz, VDD = 2.0V(4)
0.4
1.7
15
TBD mA FOSC = 8 MHz, VDD = 3.0V
TBD mA FOSC = 20 MHz, VDD = 5.0V
TBD
μA FOSC = 32 kHz, VDD = 2.0V, WDT
disabled
D020
D022
D023
D024
D025
IPD
Power-Down Current(5)
—
—
—
—
—
0.1
1.0
15
TBD
TBD
TBD
μA VDD = 2.0V
μA VDD = 2.0V
μA VDD = 2.0V
μA VDD = 2.0V
μA VDD = 2.0V
ΔIWDT WDT Current(5)
ΔICMP Comparator Current
ΔIADC ADC Current
100 TBD
ΔIVREF Internal Reference
80
TBD
Current
D026
ΔCVREF Comparator Voltage
—
58
TBD
μA VDD = 2.0V
Reference Current
Legend: TBD = To be determined.
These parameters are characterized but not tested.
*
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD,
MCLR = VDD;
WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in Sleep
mode.
4: Does not include current through REXT (in EXTRC mode only). The current through the resistor can be
estimated by the formula:
I = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS.
DS41268B-page 86
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
13.2 DC Characteristics: PIC12F510/16F506 (Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +125°C (Extended)
DC CHARACTERISTICS
Parm
Sym
Characteristic
Min Typ(1) Max Units
Conditions
No.
D001
D002
VDD
VDR
Supply Voltage
2.0
—
—
5.5
—
V
V
See Figure 13-1
RAM Data Retention
Voltage(2)
1.5*
Device in Sleep mode
D003
D004
D010
VPOR VDD Start Voltage to
—
Vss
—
—
—
V
See Section 10.4 “Power-on Reset
(POR)”
ensure Power-on Reset
SVDD VDD Rise Rate to ensure 0.05*
V/ms See Section 10.4 “Power-on Reset
(POR)” for details
Power-on Reset
IDD
Supply Current(3)
—
—
—
—
—
385 TBD
170 TBD
μA FOSC = 4 MHz, VDD = 5.0V
μA FOSC = 4 MHz, VDD = 2.0V(4)
0.4
1.7
15
TBD mA FOSC = 8 MHz, VDD = 3.0V
TBD mA FOSC = 20 MHz, VDD = 5.0V
TBD
μA FOSC = 32 kHz, VDD = 2.0V, WDT
disabled
D020
D022
D023
D024
D025
IPD
Power-Down Current(5)
—
—
—
—
—
0.1
1.0
15
TBD
TBD
TBD
μA VDD = 2.0V
μA VDD = 2.0V
μA VDD = 2.0V
μA VDD = 2.0V
μA VDD = 2.0V
ΔIWDT WDT Current(5)
ΔICMP Comparator Current
ΔIADC ADC Current
100 TBD
ΔIVREF Internal Reference
80
TBD
Current
D026 ΔCVREF Comparator Voltage
—
58
TBD
μA VDD = 2.0V
Reference Current
Legend: TBD = To be determined.
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD,
MCLR = VDD;
WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in Sleep
mode.
4: Does not include current through REXT (in EXTRC mode only). The current through the resistor can be
estimated by the formula:
I = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 87
PIC12F510/16F506
13.3 DC Characteristics: PIC12F510/16F506 (Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
DC CHARACTERISTICS
Operating Temperature
-40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports
D030
D030A
D031
D032
D033
D033
D033
with TTL buffer
VSS
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
—
0.8V
V
V
V
V
V
V
V
For 4.5 ≤ VDD ≤ 5.5V
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
0.3 VDD
otherwise
with Schmitt Trigger buffer
MCLR, T0CKI
OSC1 (in EXTRC), EC(1)
OSC1 (in HS)
OSC1 (in XT and LP)
Input High Voltage
I/O ports
VIH
—
—
—
D040
with TTL buffer
2.0
VDD
VDD
V
V
4.5 ≤ VDD ≤ 5.5V
D040A
0.25 VDD
+ 0.8V
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
1.6
Otherwise
D041
D042
D043
D043
D043
D070
with Schmitt Trigger buffer
MCLR, T0CKI
OSC1 (in EXTRC), EC(1)
—
—
VDD
VDD
VDD
VDD
VDD
TBD
V
V
For entire VDD range
—
V
OSC1 (in HS)
—
V
OSC1 (in XT and LP)
—
V
IPUR
IIL
GPIO/PORTB Weak Pull-up Current
Input Leakage Current(2), (3)
GPIO Weak Pull-up Current (GP3)
TBD
250
μA
VDD = 5V, VPIN = VSS
D070
TBD
225
TBD
μA
VDD = 5V
VPIN = 0V
D060
D061A
D063
I/O ports
GP3/RB3/MCLR(4)
—
—
—
—
—
—
±1
±5
±5
μA
μA
μA
Vss ≤ VPIN ≤ VDD, Pin at high-impedance
Vss ≤ VPIN ≤ VDD
OSC1
Vss ≤ VPIN ≤ VDD, XT, HS and LP oscillator
configuration
Output Low Voltage
D080
VOL
I/O ports/CLKOUT
—
—
—
—
—
—
—
—
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V, –40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V, –40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V, –40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V, –40°C to +125°C
D080A
D083
OSC2
D083A
Output High Voltage
D090
VOH
I/O ports/CLKOUT(3)
VDD – 0.7
VDD – 0.7
VDD – 0.7
VDD – 0.7
—
—
—
—
—
—
—
—
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V, –40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V, –40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V, –40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V, –40°C to +125°C
D090A
D092
OSC2
D092A
Capacitive Loading Specs on Output Pins
COSC2 OSC2 pin
D100
—
—
—
—
15
50
pF
pF
In XT, HS and LP modes when external
clock is used to drive OSC1.
D101
CIO
All I/O pins
Legend:
TBD = To be determined.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1:
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F510/16F506 be
driven with external clock in RC mode.
2:
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating
conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
This specification applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is
higher than the standard I/O logic.
3:
4:
DS41268B-page 88
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
TABLE 13-1: COMPARATOR SPECIFICATIONS
Sym
Characteristics
Input Offset Voltage
Min
Typ
Max
Units
Comments
VOS
VCM
—
0
±3
—
±10
VDD – 1.5
—
mV
V
Input Common Mode Voltage
Common Mode Rejection Ratio
Response Time(1)
CMRR
TRT
+55*
—
—
dB
ns
V
150
0.6
400*
Internal
VIVRF
Internal Voltage Reference
0.550
0.650
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD – 1.5V.
TABLE 13-2: COMPARATOR VOLTAGE REFERENCE (VREF) SPECIFICATIONS
Sym
Characteristics
Min
Typ
Max
Units
Comments
CVRES Resolution
—
—
VDD/24*
VDD/32
—
—
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
Absolute Accuracy
—
—
—
—
±1/4*
±1/2*
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
Unit Resistor Value (R)
Settling Time(1)
—
—
2K*
—
Ω
—
—
10*
μs
*
These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1and VR<3:0> transitions from 0000to 1111.
TABLE 13-3: A/D CONVERTER CHARACTERISTICS (PIC12F510/16F506)
Param
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
No.
A01
NR
Resolution
—
—
—
—
—
—
8 bits
± 1
bit
A03
A04
EIL
Integral Error
LSb VDD = 5.0V
EDL
Differential Error
-1 < EDL ≤ 1 LSb No missing codes to 8
bits VDD = 5.0V
A05
A06
A07
A10
A25
A30
EFS
EOFF
EGN
—
Full-scale Range
Offset Error
2
—
—
5.5*
± 1
± 1
—
V
VDD
—
LSb VDD = 5.0V
LSb VDD = 5.0V
Gain Error
—
—
Monotonicity
—
guaranteed(2)
—
V
VSS ≤ VAIN ≤ VDD
VAIN
ZAIN
Analog Input Voltage
VSS
—
—
—
VDD
10
RecommendedImpedance
of Analog Voltage Source
kΩ
*
These parameters are characterized but not tested.
†
Data in the “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only are not tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
3: VREF current is from external VREF or VDD pin, whichever is selected as reference input.
4: When A/D is off, it will not consume any current other than leakage current. The power-down current
specification includes any such leakage from the A/D module.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 89
PIC12F510/16F506
TABLE 13-4: A/D CONVERTER CHARACTERISTICS (PIC12F510)
Param
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
No.
A01
NR
Resolution
—
—
—
—
—
—
8 bits
± 1
bit
A03
A04
EIL
Integral Error
LSb VDD = 5.0V
EDL
Differential Error
-1 < EDL ≤ 1 LSb No missing codes to 8
bits VDD = 5.0V
A05
A06
A07
A10
A25
A30
EFS
EOFF
EGN
—
Full-scale Range
Offset Error
2
—
—
5.5*
± 1
± 1
—
V
VDD
—
LSb VDD = 5.0V
LSb VDD = 5.0V
Gain Error
—
—
Monotonicity
—
guaranteed(2)
—
V
VSS ≤ VAIN ≤ VDD
VAIN
ZAIN
Analog Input Voltage
VSS
—
—
—
VDD
10
RecommendedImpedance
of Analog Voltage Source
kΩ
*
These parameters are characterized but not tested.
†
Data in the “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only are not tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
3: VREF current is from external VREF or VDD pin, whichever is selected as reference input.
4: When A/D is off, it will not consume any current other than leakage current. The power-down current
specification includes any such leakage from the A/D module.
DS41268B-page 90
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
13.4 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T Time
Lowercase (pp) and their meanings:
pp
2
To
mc
osc
os
MCLR
ck
cy
drt
io
CLKOUT
Cycle Time
Device Reset Timer
I/O port
Oscillator
OSC1
t0
T0CKI
wdt
Watchdog Timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (High-impedance)
Low
Valid
L
High-impedance
FIGURE 13-5:
LOAD CONDITIONS
Legend:
CL = 50 pF for all pins except OSC2
Pin
Cl
15 pF for OSC2 in XT, HS or LP
modes when external clock
is used to drive OSC1
VSS
FIGURE 13-6:
EXTERNAL CLOCK TIMING
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 91
PIC12F510/16F506
TABLE 13-5: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
AC CHARACTERISTICS
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),
-40°C ≤ TA ≤ +125°C (extended)
Para
Sym
No.
Characteristic
Min Typ(1)
Max Units
Conditions
1A
FOSC
TOSC
TCY
External CLKIN Frequency(2) DC
DC
—
—
4
MHz XT Oscillator mode
20
MHz HS/EC Oscillator mode
(PIC16F506 only)
DC
—
—
—
—
200
4
kHz LP Oscillator mode
MHz EXTRC Oscillator mode
MHz XT Oscillator mode
Oscillator Frequency(2)
—
0.1
4
4
20
MHz HS/EC Oscillator mode
(PIC16F506 only)
—
250
50
—
—
—
200
—
kHz LP Oscillator mode
ns XT Oscillator mode
1
External CLKIN Period(2)
Oscillator Period(2)
—
ns HS/EC Oscillator mode
(PIC16F506 only)
5
—
—
—
—
—
—
μs LP Oscillator mode
250
250
50
ns EXTRC Oscillator mode
10,000 ns XT Oscillator mode
250
ns HS/EC Oscillator mode
(PIC16F506 only)
5
—
—
—
—
—
—
μs LP Oscillator mode
ns
2
3
Instruction Cycle Time
200 4/FOSC
TosL,
TosH
Clock in (OSC1) Low or High 50*
—
—
—
ns XT Oscillator
μs LP Oscillator
ns HS/EC Oscillator
(PIC16F506 only)
Time
2*
10
4
TosR,
TosF
Clock in (OSC1) Rise or Fall
Time
—
—
—
—
—
—
25*
50*
15
ns XT Oscillator
ns LP Oscillator
ns HS/EC Oscillator
(PIC16F506 only)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for
design guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
DS41268B-page 92
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
TABLE 13-6: CALIBRATED INTERNAL RC FREQUENCIES
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),
-40°C ≤ TA ≤ +125°C (extended)
AC CHARACTERISTICS
Param
Freq.
Tolerance
Sym
Characteristic
Min Typ(1) Max* Units
Conditions
No.
F10
FOSC Internal Calibrated INTOSC
Frequency(1)
±1%
±2%
7.92 8.00 8.08 MHz VDD = 3.5V TA = 25°C
7.84 8.00 8.16 MHz 2.5V ≤ VDD ≤ 5.5V
0°C ≤ TA ≤ +85°C
7.60 8.00 8.40 MHz 2.0V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (Ind.)
±5%
-40°C ≤ TA ≤ +125°C (Ext.)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for
design guidance only and are not tested.
FIGURE 13-7:
I/O TIMING
Q1
Q2
Q3
Q4
OSC1
I/O Pin
(input)
17
18
19
I/O Pin
(output)
New Value
Old Value
20, 21
Note:
All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 93
PIC12F510/16F506
TABLE 13-7: TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
17
18
TOSH2IOV
TOSH2IOI
OSC1↑ (Q1 cycle) to Port out valid(2), (3)
—
—
—
100*
—
ns
ns
OSC1↑ (Q2 cycle) to Port input invalid
TBD
(I/O in hold time)(2)
19
20
21
TIOV2OSH
TIOR
Port input valid to OSC1↑ (I/O in setup time)
Port output rise time(2), (3)
Port output fall time(2), (3)
TBD
—
—
10
10
—
ns
ns
ns
25**
25**
TIOF
—
*
These parameters are characterized but not tested.
** These parameters are design targets and are not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for
design guidance only and are not tested.
2: Measurements are taken in EXTRC mode.
3: See Figure 13-5 for loading conditions.
FIGURE 13-8:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
VDD
MCLR
30
Internal
POR
32
32
32
DRT
(2)
Timeout
Internal
Reset
Watchdog
Timer Reset
31
34
34
(1)
I/O pin
Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.
2: Runs in MCLR or WDT Reset only in XT, LP and HS modes.
DS41268B-page 94
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
TABLE 13-8: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
AC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min Typ(1) Max
Units
Conditions
30
31
TMCL MCLR Pulse Width (low)
2000*
—
—
ns
VDD = 5.0V
TWDT Watchdog Timer Time-out Period
(No Prescaler)
9*
9*
18*
18*
30*
40*
ms
ms
VDD = 5.0V (Commercial)
VDD = 5.0V (Extended)
32
34
TDRT Device Reset Timer Period
Standard
9*
9*
18*
18*
30*
40*
ms
ms
VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
Short
0.5* 1.125*
0.5* 1.125* 2.5*
2*
ms
ms
VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
TIOZ I/O high-impedance from MCLR low
—
—
2000*
ns
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
FIGURE 13-9:
TIMER0 CLOCK TIMINGS
T0CKI
40
41
42
TABLE 13-9: TIMER0 CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
AC CHARACTERISTICS
Parm
Sym
No.
(1)
Characteristic
Min
Typ
Max Units
Conditions
40
41
42
Tt0H
Tt0L
Tt0P
T0CKI High Pulse Width No Prescaler
With Prescaler
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
T0CKI Low Pulse Width No Prescaler
With Prescaler
0.5 TCY + 20*
10*
T0CKI Period
20 or TCY + 40* N
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 95
PIC12F510/16F506
14.0 DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Graphs and charts are not available at this time.
DS41268B-page 96
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
NOTES:
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 97
PIC12F510/16F506
15.0 PACKAGING
15.1 Package Marking Information
8-Lead PDIP
Example
12F510/P
XXXXXXXX
XXXXXNNN
YYWW
017
0410
14-Lead PDIP
Example
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
PIC16F506-I/P
0410017
YYWWNNN
8-Lead SOIC (.150”)
Example
XXXXXXXX
XXXXYYWW
PIC12F510-I
/SN0410
NNN
017
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code and traceability code.
For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales
Office. For QTP devices, any special marking adders are included in QTP price.
DS41268B-page 98
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
15.2 Package Marking Information (Cont’d)
14-Lead SOIC (.150”)
Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
PIC16F506
-I/SL
0410017
8-Lead MSOP
Example
XXXXXX
YWWNNN
602/MS
310017
14-Lead TSSOP
Example
XXXXXXXX
YYWW
16F506/ST
0410
NNN
017
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 99
PIC12F510/16F506
8-Lead Plastic Dual In-Line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
8
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.100
2.54
Top to Seating Plane
A
.140
.155
.130
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS41268B-page 100
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
14-Lead Plastic Dual In-Line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
B1
β
eB
p
B
Units
INCHES*
NOM
14
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
.100
2.54
Top to Seating Plane
A
.140
.155
.130
.170
3.56
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
5
.145
2.92
0.38
7.62
6.10
18.80
3.18
0.20
1.14
0.36
7.87
5
3.68
.313
.250
.750
.130
.012
.058
.018
.370
10
.325
.260
.760
.135
.015
.070
.022
.430
15
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 101
PIC12F510/16F506
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
8
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.050
1.27
Overall Height
A
.053
.061
.056
.007
.237
.154
.193
.015
.025
4
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
0
12
15
0
12
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS41268B-page 102
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
1
B
n
α
h
45°
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
14
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
1.27
Overall Height
A
.053
.052
.004
.228
.150
.337
.010
.016
0
.069
1.35
1.32
1.55
1.42
0.18
5.99
3.90
8.69
0.38
0.84
4
1.75
Molded Package Thickness
A2
A1
E
.061
.010
.244
.157
.347
.020
.050
8
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
Standoff
§
0.10
5.79
3.81
8.56
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
0
12
15
0
12
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 103
PIC12F510/16F506
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
n
1
B
α
c
φ
A2
A
L
F
A1
β
Units
INCHES
NOM
MILLIMETERS
*
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.026 BSC
0.65 BSC
Overall Height
A
A2
A1
E
-
-
.043
-
-
1.10
0.95
0.15
Molded Package Thickness
Standoff
.030
.033
.037
.006
0.75
0.85
.000
-
0.00
-
Overall Width
.193 BSC
4.90 BSC
Molded Package Width
Overall Length
E1
D
.118 BSC
.118 BSC
3.00 BSC
3.00 BSC
Foot Length
L
.016
.024
.037 REF
.031
0.40
0.60
0.95 REF
0.80
Footprint (Reference)
Foot Angle
F
φ
0°
-
8°
0°
-
-
-
-
-
8°
c
Lead Thickness
Lead Width
.003
.009
.006
.012
.009
.016
0.08
0.22
0.23
0.40
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
5°
5°
-
15°
15°
5°
5°
15°
15°
β
-
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-187
Drawing No. C04-111
Revised 07-21-05
DS41268B-page 104
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
β
L
A1
A2
Units
INCHES
NOM
MILLIMETERS
NOM
14
*
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
14
.026 BSC
.041
0.65 BSC
1.05
Overall Height
A
A2
A1
E
.039
.033
.002
.246
.169
.193
.020
.043
1.00
1.10
Molded Package Thickness
Standoff
.035
.004
.251
.173
.197
.024
.037
.006
.256
.177
.201
.028
0.85
0.05
6.25
4.30
4.90
0.50
0.90
0.95
0.15
6.50
4.50
5.10
0.70
0.10
Overall Width
6.38
Molded Package Width
Molded Package Length
Foot Length
E1
D
4.40
5.00
L
0.60
φ
Foot Angle
0°
4°
8°
0°
4°
0.15
0.25
12° REF
12° REF
8°
c
Lead Thickness
.004
.007
.006
.010
.008
.012
0.09
0.19
0.20
0.30
Lead Width
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
12° REF
12° REF
β
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-153 AB-1
Drawing No. C04-087
Revised: 08-17-05
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 105
PIC12F510/16F506
APPENDIX A: REVISION HISTORY
Revision A
Original release.
Revision B
Page 3 – Special Microcontroller Features and Low-
Power Features sections.
PIC12F510 Pin Diagram.
Section 3.0 – Figure 3-1, Figure 3-2, Table 3-2,
Table 3-3.
Section 4.0 – First paragraph, Section 4.2 - Figure
references, Tables 4-1 and 4-2 (Note 1).
Section 5.0 – Table 5-2, Table 5-6 Title.
Section 6.0
Section 7.0 – First paragraph, Section 7.7, Register
7-1, Register 7-2, Register 7-3, Figure 7-1, Figure 7-2,
Sections 7.4 through 7.7, Table 7-1.
Section 8.0 – Sections 8.0 through 8.2, Figure 8-1,
Table 8-1.
Section 9.0 – Table 9-2, Register 9-1, Register 9-2,
Table 9-3.
Section 10.0 – Registers 10-1 and 10-2 (Note 1), Table
10-2 (Note 2), Section 10.2.5, Section 10.3,
Table 10-3, Table 10-4, Table 10-5, Section 10.4,
Section 10.5, Section 10.6.1, Section 10.9, 10.9.1,
10.9.2, Section 10.11.
Section 13.0 – 13.1 DC Characteristics, 13.2 DC
Characteristics, Table 13-1, Table 13-3, Table 13-4.
DS41268B-page 106
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
INDEX
Microchip Internet Web Site.............................................. 108
MPLAB ASM30 Assembler, Linker, Librarian..................... 80
MPLAB ICD 2 In-Circuit Debugger ..................................... 81
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator...................................................... 81
MPLAB ICE 4000 High-Performance Universal
A
ALU ....................................................................................... 9
Assembler
MPASM Assembler..................................................... 80
B
In-Circuit Emulator...................................................... 81
MPLAB Integrated Development Environment Software.... 79
MPLAB PM3 Device Programmer ...................................... 81
MPLINK Object Linker/MPLIB Object Librarian.................. 80
Block Diagram
Comparator for the PIC12F510................................... 46
Comparator for the PIC16F506................................... 46
On-Chip Reset Circuit................................................. 64
Timer0......................................................................... 39
TMR0/WDT Prescaler................................................. 42
Watchdog Timer.......................................................... 67
Brown-Out Protection Circuit .............................................. 68
O
OPTION Register................................................................ 20
OSC Selection .................................................................... 55
OSCCAL Register............................................................... 22
Oscillator Configurations..................................................... 58
Oscillator Types
C
C Compilers
HS............................................................................... 58
LP ............................................................................... 58
RC .............................................................................. 58
XT............................................................................... 58
MPLAB C18 ................................................................ 80
MPLAB C30 ................................................................ 80
Carry ..................................................................................... 9
Clocking Scheme ................................................................ 14
Code Protection ............................................................ 55, 69
Configuration Bits................................................................ 55
Configuration Word (PIC12F510) ....................................... 56
Configuration Word (PIC16F506) ....................................... 57
Customer Change Notification Service ............................. 108
Customer Notification Service........................................... 108
Customer Support............................................................. 108
P
PIC12F510/16F506 Device Varieties ................................... 7
PICSTART Plus Development Programmer....................... 82
POR
Device Reset Timer (DRT) ................................... 55, 66
PD............................................................................... 68
Power-on Reset (POR)............................................... 55
TO............................................................................... 68
PORTB ............................................................................... 27
Power-down Mode.............................................................. 69
Prescaler ............................................................................ 41
Program Counter................................................................ 23
D
DC....................................................................................... 88
DC Characteristics (Extended) ........................................... 87
DC Characteristics (Industrial)............................................ 86
DC Characteristics (Industrial, Extended)........................... 88
Development Support ......................................................... 79
Digit Carry............................................................................. 9
Q
Q cycles.............................................................................. 14
E
R
Errata .................................................................................... 3
RC Oscillator....................................................................... 59
Reader Response............................................................. 109
Read-Modify-Write.............................................................. 37
Register File Map
PIC12F510 ................................................................. 16
PIC16F506 ................................................................. 16
Registers
F
Family of Devices
PIC12F510/16F506....................................................... 5
FSR..................................................................................... 24
I
Special Function......................................................... 17
Reset .................................................................................. 55
Reset on Brown-Out ........................................................... 68
I/O Interfacing ..................................................................... 27
I/O Ports.............................................................................. 27
I/O Programming Considerations........................................ 37
ID Locations.................................................................. 55, 69
INDF.................................................................................... 24
Indirect Data Addressing..................................................... 24
Instruction Cycle ................................................................. 14
Instruction Flow/Pipelining .................................................. 14
Instruction Set Summary..................................................... 72
Internet Address................................................................ 108
S
Sleep ............................................................................ 55, 69
Software Simulator (MPLAB SIM) ...................................... 80
Special Features of the CPU .............................................. 55
Special Function Registers................................................. 17
Stack................................................................................... 23
STATUS Register ..................................................... 9, 18, 51
L
T
Loading of PC ..................................................................... 23
Timer0
M
Timer0 ........................................................................ 39
Timer0 (TMR0) Module .............................................. 39
TMR0 with External Clock .......................................... 41
Timing Diagrams and Specifications .................................. 91
Memory Organization.......................................................... 15
Data Memory .............................................................. 16
Program Memory (PIC12F510/16F506) ..................... 15
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 107
PIC12F510/16F506
Timing Parameter Symbology and Load Conditions...........91
TRIS Registers....................................................................27
W
Wake-up from Sleep ...........................................................69
Watchdog Timer (WDT) ................................................ 55, 66
Period..........................................................................66
Programming Considerations .....................................66
WWW Address..................................................................108
WWW, On-Line Support........................................................3
Z
Zero bit..................................................................................9
DS41268B-page 108
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 109
PIC12F510/16F506
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
PIC12F510/16F506
DS41268B
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41268B-page 110
Preliminary
© 2006 Microchip Technology Inc.
PIC12F510/16F506
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
PIC18LF258 - I/L 301 = Industrial temp., PLCC
package, Extended VDD limits, QTP pattern
#301.
b)
c)
PIC18LF458 - I/PT = Industrial temp., TQFP
package, Extended VDD limits.
Device:
PIC18F248/258(1), PIC18F448/458(1), PIC18F248/258T(2)
PIC18F448/458T(2)
VDD range 4.2V to 5.5V
PIC18LF248/258(1), PIC18LF448/458(1), PIC18LF248/258T(2)
PIC18LF448/458T(2)
VDD range 2.0V to 5.5V
,
PIC18F258 - E/L = Extended temp., PLCC
package, normal VDD limits.
;
,
;
Temperature
Range:
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
Package:
PT
L
SO
SP
P
=
=
=
=
=
TQFP (Thin Quad Flatpack)
PLCC
Note 1:
2:
F
LF
T
=
=
=
Standard Voltage Range
Wide Voltage Range
in tape and reel PLCC, and TQFP
packages only.
SOIC
Skinny Plastic DIP
PDIP
Pattern:
QTP, SQTP, Code or Special Requirements
(blank otherwise)
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 111
WORLDWIDE SALES AND SERVICE
AMERICAS
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02/16/06
DS41268B-page 112
© 2006 Microchip Technology Inc.
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