PIC16C84-04I/PXXX [MICROCHIP]
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,18PIN,PLASTIC;
| 型号： | PIC16C84-04I/PXXX |
| 厂家： | 
MICROCHIP |
| 描述： | IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,18PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 微控制器 光电二极管 外围集成电路 |
| 文件： | 总110页 (文件大小：960K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M
PIC16C84
8-bit CMOS EERPOM Microcontroller
High Performance RISC CPU Features:
Pin Diagram
• Only 35 single word instructions to learn
PDIP, SOIC
• All instructions single cycle (400 ns @ 10 MHz)
except for program branches which are two-cycle
• Operating speed: DC - 10 MHz clock input
DC - 400 ns instruction cycle
RA2
RA3
•1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
RA1
RA0
RA4/T0CKI
MCLR
VSS
OSC1/CLKIN
OSC2/CLKOUT
VDD
• 14-bit wide instructions
• 8-bit wide data path
• 1K x 14 EEPROM program memory
• 36 x 8 general purpose registers (SRAM)
• 64 x 8 on-chip EEPROM data memory
• 15 special function hardware registers
• Eight-level deep hardware stack
• Direct, indirect and relative addressing modes
• Four interrupt sources:
RB0/INT
RB1
RB7
RB6
RB2
RB5
RB3
RB4
- External RB0/INT pin
CMOS Technology:
- TMR0 timer overflow
• Low-power, high-speed CMOS EEPROM
technology
- PORTB<7:4> interrupt on change
- Data EEPROM write complete
• Fully static design
• 1,000,000 data memory EEPROM
ERASE/WRITE cycles
• Wide operating voltage range:
- Commercial: 2.0V to 6.0V
• EEPROM Data Retention > 40 years
- Industrial:
2.0V to 6.0V
Peripheral Features:
• Low power consumption:
- < 2 mA typical @ 5V, 4 MHz
- 60 µA typical @ 2V, 32 kHz
- 26 µA typical standby current @ 2V
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
- 25 mA sink max. per pin
- 20 mA source max. per pin
• TMR0: 8-bit timer/counter with 8-bit
programmable prescaler
Special Microcontroller Features:
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Serial In-System Programming - via two pins
1997 Microchip Technology Inc.
DS30445C-page 1
PIC16C84
Table of Contents
1.0 General Description ....................................................................................................................................................................... 3
2.0 PIC16C84 Device Varieties ........................................................................................................................................................... 5
3.0 Architectural Overview................................................................................................................................................................... 7
4.0 Memory Organization................................................................................................................................................................... 11
5.0 I/O Ports....................................................................................................................................................................................... 19
6.0 Timer0 Module and TMR0 Register............................................................................................................................................. 25
7.0 Data EEPROM Memory............................................................................................................................................................... 31
8.0 Special Features of the CPU ....................................................................................................................................................... 35
9.0 Instruction Set Summary.............................................................................................................................................................. 51
10.0 Development Support .................................................................................................................................................................. 67
11.0 Electrical Characteristics for PIC16C84....................................................................................................................................... 71
12.0 DC & AC Characteristics Graphs/Tables for PIC16C84 .............................................................................................................. 83
13.0 Packaging Information ................................................................................................................................................................. 97
Appendix A: Feature Improvements - From PIC16C5X To PIC16C84 ............................................................................................ 99
Appendix B: Code Compatibility - from PIC16C5X to PIC16C84.................................................................................................... 99
Appendix C: What’s New In This Data Sheet................................................................................................................................. 100
Appendix D: What’s Changed In This Data Sheet ......................................................................................................................... 100
Appendix E: Conversion Considerations - PIC16C84 to PIC16F83/F84 And PIC16CR83/CR84.................................................. 101
Index .................................................................................................................................................................................................. 103
On-Line Support................................................................................................................................................................................. 105
PIC16C84 Product Identification System........................................................................................................................................... 107
Sales and Support.............................................................................................................................................................................. 107
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of
time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you
find any information that is missing or appears in error, please use the reader response form in the back of this data
sheet to inform us. We appreciate your assistance in making this a better document.
DS30445C-page 2
1997 Microchip Technology Inc.
PIC16C84
The PIC16C84 fits perfectly in applications ranging
from high speed automotive and appliance motor
control to low-power remote sensors, electronic locks,
security devices and smart cards. The EEPROM
technology makes customization of application
programs (transmitter codes, motor speeds, receiver
frequencies, security codes, etc.) extremely fast and
convenient. The small footprint packages make this
microcontroller series perfect for all applications with
space limitations. Low cost, low power, high
performance, ease of use and I/O flexibility make the
PIC16C84 very versatile even in areas where no
microcontroller use has been considered before
(e.g., timer functions, serial communication, capture
and compare, PWM functions and co-processor
applications).
1.0
GENERAL DESCRIPTION
The PIC16C84 is a low-cost, high-performance,
CMOS, fully-static, 8-bit microcontroller.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. PIC16CXX devices have enhanced
core features, eight-level deep stack, and multiple inter-
nal and external interrupt sources. The separate
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with a separate
8-bit wide data bus. The two stage instruction pipeline
allows all instructions to execute in a single cycle,
except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set is
used to achieve a very high performance level.
PIC16CXX microcontrollers typically achieve a 2:1
code compression and up to a 2:1 speed improvement
(at 10 MHz) over other 8-bit microcontrollers in their
class.
The serial in-system programming feature (via two
pins) offers flexibility of customizing the product after
complete assembly and testing. This feature can be
used to serialize a product, store calibration data, or
program the device with the current firmware before
shipping.
The PIC16C84 has 36 bytes of RAM, 64 bytes of Data
EEPROM memory, and 13 I/O pins. A timer/counter is
also available.
1.1
Family and Upward Compatibility
The PIC16CXX family has special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LP
oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power savings.
The user can wake the chip from sleep through several
external and internal interrupts and resets.
Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for PIC16C5X can be easily ported to the
PIC16C84 (Appendix B).
1.2
Development Support
The PIC16CXX family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. A “C” compiler and fuzzy
logic support tools are also available.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lock-
up.
The PIC16C84 EEPROM program memory allows the
same device package to be used for prototyping and
production. In-circuit reprogrammability allows the
code to be updated without the device being removed
from the end application. This is useful in the
development of many applications where the device
may not be easily accessible, but the prototypes may
require code updates. This is also useful for remote
applications where the code may need to be updated
(such as rate information).
Table 1-1 lists the features of the PIC16C84. A simpli-
fied block diagram of the PIC16C84 is shown in
Figure 3-1.
1997 Microchip Technology Inc.
DS30445C-page 3
PIC16C84
TABLE 1-1
PIC16C8X FAMILY OF DEVICES
PIC16F83
PIC16CR83
PIC16F84
PIC16CR84
Maximum Frequency
of Operation (MHz)
10
10
10
10
Clock
Flash Program Memory
EEPROM Program Memory
ROM Program Memory
Data Memory (bytes)
512
—
—
—
1K
—
—
68
64
—
—
1K
68
64
Memory
—
512
36
36
64
Data EEPROM (bytes)
64
Peripherals Timer Module(s)
Interrupt Sources
I/O Pins
TMR0
4
TMR0
4
TMR0
4
TMR0
4
13
13
13
13
Features
Voltage Range (Volts)
Packages
2.0-6.0
2.0-6.0
2.0-6.0
2.0-6.0
18-pin DIP,
SOIC
18-pin DIP,
SOIC
18-pin DIP,
SOIC
18-pin DIP,
SOIC
All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capa-
bility. All PIC16C8X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30445C-page 4
1997 Microchip Technology Inc.
PIC16C84
2.0
PIC16C84 DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements the proper device option can be selected
using the information in this section. When placing
orders, please use the “PIC16C84 Product
Identification System” at the back of this data sheet to
specify the correct part number.
There are two device “types” as indicated in the device
number.
1. C, as in PIC16C84. These devices have
EEPROM program memory and operate over
the standard voltage range.
2. LC, as in PIC16LC84. These devices have
EEPROM program memory and operate over an
extended voltage range.
When discussing memory maps and other architectural
features, the use of C also implies the LC versions.
2.1
Electrically Erasable Devices
These devices are offered in the lower cost plastic
package, even though the device can be erased and
reprogrammed.This allows the same device to be used
for prototype development and pilot programs as well
as production.
A further advantage of the electrically erasable version
is that they can be erased and reprogrammed in-circuit,
or by device programmers, such as Microchip's
PICSTART Plus or PRO MATE II programmers.
1997 Microchip Technology Inc.
DS30445C-page 5
PIC16C84
NOTES:
DS30445C-page 6
1997 Microchip Technology Inc.
PIC16C84
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
data in the working register and any register file.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16CXX uses a Harvard architecture. This
architecture has the program and data accessed from
separate memories. So the device has a program
memory bus and a data memory bus. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory (accesses over the same bus). Separating
program and data memory further allows instructions
to be sized differently than the 8-bit wide data word.
PIC16CXX opcodes are 14-bits wide, enabling single
word instructions.The full 14-bit wide program memory
bus fetches a 14-bit instruction in a single cycle. A two-
stage pipeline overlaps fetch and execution of instruc-
tions (Example 3-1). Consequently, all instructions exe-
cute in a single cycle (400 ns @ 10 MHz) except for
program branches.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register), and the other operand is a file register or
an immediate constant. In single operand instructions,
the operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register.The C and DC bits
operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the SUBLWand SUBWF
instructions for examples.
The PIC16C84 addresses 1K x 14 program memory.
All program memory is internal.
A simplified block diagram for the PIC16C84 is shown
in Figure 3-1, its corresponding pin description is
shown in Table 3-1.
PIC16CXX devices can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. An orthogonal (symmetrical)
instruction set that makes it possible to carry out any
operation on any register using any addressing mode.
This symmetrical nature and lack of ‘special optimal
situations’ make programming with the PIC16CXX
simple yet efficient. In addition, the learning curve is
reduced significantly.
The PIC16C84 has 36 x 8 SRAM and 64 x 8 EEPROM
data memory.
1997 Microchip Technology Inc.
DS30445C-page 7
PIC16C84
FIGURE 3-1: PIC16C84 BLOCK DIAGRAM
13
Data Bus 8
Program Counter
EEPROM Data Memory
EEPROM
Program
Memory
RAM
EEPROM
Data Memory
64 x 8
1K x 14
File Registers
8 Level Stack
EEDATA
(13-bit)
36 x 8
Program
Bus 14
7
RAM Addr
EEADR
Addr Mux
Instruction reg
TMR0
7
Indirect
Addr
5
Direct Addr
FSR reg
RA4/T0CKI
STATUS reg
MUX
8
Power-up
Timer
I/O Ports
Instruction
Decode &
Control
Oscillator
Start-up Timer
ALU
Power-on
Reset
RA3:RA0
RB7:RB1
Watchdog
Timer
Timing
Generation
W reg
RB0/INT
MCLR
OSC2/CLKOUT
OSC1/CLKIN
VDD, VSS
DS30445C-page 8
1997 Microchip Technology Inc.
PIC16C84
TABLE 3-1
PIC16C8X PINOUT DESCRIPTION
DIP
No.
SOIC
No.
I/O/P
Type
Buffer
Type
Pin Name
Description
(1)
OSC1/CLKIN
16
15
16
15
I
ST/CMOS
—
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
O
Oscillator crystal output. Connects to crystal or resonator in crys-
tal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1, and denotes the instruction cycle
rate.
MCLR
4
4
I/P
ST
Master clear (reset) input/programming voltage input. This pin is an
active low reset to the device.
PORTA is a bi-directional I/O port.
RA0
17
18
1
17
18
1
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
RA1
RA2
RA3
2
2
RA4/T0CKI
3
3
Can also be selected to be the clock input to the TMR0 timer/
counter. Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be software pro-
grammed for internal weak pull-up on all inputs.
RB0/INT
6
7
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
TTL
TTL
TTL
TTL
TTL
TTL
RB0/INT can also be selected as an external interrupt pin.
RB1
RB2
8
8
RB3
9
9
RB4
10
11
12
13
5
10
11
12
13
5
Interrupt on change pin.
RB5
Interrupt on change pin.
(2)
RB6
TTL/ST
TTL/ST
—
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
(2)
RB7
VSS
VDD
14
14
P
—
Legend: I= input
O = output
— = Not used
I/O = Input/Output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
1997 Microchip Technology Inc.
DS30445C-page 9
PIC16C84
3.1
Clocking Scheme/Instruction Cycle
3.2
Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
PC
Internal
phase
clock
PC
PC+1
PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30445C-page 10
1997 Microchip Technology Inc.
PIC16C84
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK
4.0
MEMORY ORGANIZATION
There are two memory blocks in the PIC16C84. These
are the program memory and the data memory. Each
block has its own bus, so that access to each block can
occur during the same oscillator cycle.
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
The data memory can further be broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
•
•
•
Stack Level 8
Reset Vector
0000h
0004h
Peripheral Interrupt Vector
The data memory area also contains the data
EEPROM memory.This memory is not directly mapped
into the data memory, but is indirectly mapped. That is
an indirect address pointer specifies the address of the
data EEPROM memory to read/write. The 64 bytes of
data EEPROM memory have the address range
0h-3Fh. More details on the EEPROM memory can be
found in Section 7.0.
4.1
Program Memory Organization
The PIC16CXX has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. For
the PIC16C84, only the first 1K x 14 (0000h-03FFh) are
physically implemented (Figure 4-1). Accessing a loca-
tion above the physically implemented address will
cause a wraparound. For example, locations 20h,
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h
will be the same instruction.
3FFh
1FFFh
The reset vector is at 0000h and the interrupt vector is
at 0004h.
1997 Microchip Technology Inc.
DS30445C-page 11
PIC16C84
4.2
Data Memory Organization
FIGURE 4-2: REGISTER FILE MAP
File Address
The data memory is partitioned into two areas.The first
is the Special Function Registers (SFR) area, while the
second is the General Purpose Registers (GPR) area.
The SFRs control the operation of the device.
File Address
80h
(1)
(1)
00h
Indirect addr.
Indirect addr.
01h
02h
TMR0
PCL
OPTION
PCL
81h
82h
Portions of data memory are banked. This is for both
the SFR area and the GPR area. The GPR area is
banked to allow greater than 116 bytes of general
purpose RAM.The banked areas of the SFR are for the
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection.
These control bits are located in the STATUS Register.
Figure 4-2 shows the data memory map organization.
03h
04h
05h
06h
STATUS
FSR
STATUS
FSR
83h
84h
85h
86h
PORTA
PORTB
TRISA
TRISB
07h
08h
09h
87h
88h
89h
EEDATA
EEADR
EECON1
(1)
Instructions MOVWFand MOVFcan move values from the
W register to any location in the register file (“F”), and
vice-versa.
EECON2
0Ah
PCLATH
INTCON
PCLATH
INTCON
8Ah
0Bh
0Ch
8Bh
8Ch
The entire data memory can be accessed either
directly using the absolute address of each register file
or indirectly through the File Select Register (FSR)
(Section 4.5). Indirect addressing uses the present
value of the RP1:RP0 bits for access into the banked
areas of data memory.
36
General
Purpose
registers
(SRAM)
Mapped
(accesses)
in Bank 0
2Fh
30h
AFh
B0h
Data memory is partitioned into two banks which
contain the general purpose registers and the special
function registers. Bank 0 is selected by clearing the
RP0 bit (STATUS<5>). Setting the RP0 bit selects
Bank 1. Each Bank extends up to 7Fh (128 bytes). The
first twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are Gen-
eral Purpose Registers implemented as static RAM.
4.2.1
GENERAL PURPOSE REGISTER FILE
All devices have some amount of General Purpose
Register (GPR) area. Each GPR is 8 bits wide and is
accessed either directly or indirectly through the FSR
(Section 4.5).
7Fh
FFh
Bank 0
Bank 1
The GPR addresses in bank 1 are mapped to
addresses in bank 0. As an example, addressing loca-
tion 0Ch or 8Ch will access the same GPR.
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (Figure 4-2 and
Table 4-1) are used by the CPU and Peripheral
functions to control the device operation. These
registers are static RAM.
The special function registers can be classified into two
sets, core and peripheral. Those associated with the
core functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for that specific feature.
DS30445C-page 12
1997 Microchip Technology Inc.
PIC16C84
TABLE 4-1
REGISTER FILE SUMMARY
Value on
Power-on
Reset
Value on all
other resets
(Note3)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
00h
01h
02h
INDF
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
---- ----
xxxx xxxx
0000 0000
---- ----
uuuu uuuu
0000 0000
TMR0
PCL
Low order 8 bits of the Program Counter (PC)
(2)
TO
Indirect data memory address pointer 0
03h
04h
05h
06h
07h
08h
09h
STATUS
FSR
IRP
RP1
RP0
PD
Z
DC
C
0001 1xxx
xxxx xxxx
---x xxxx
000q quuu
uuuu uuuu
---u uuuu
uuuu uuuu
---- ----
uuuu uuuu
uuuu uuuu
PORTA
PORTB
—
—
—
RA4/T0CKI
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB7
RB6
RB5
RB0/INT xxxx xxxx
---- ----
Unimplemented location, read as '0'
EEDATA
EEADR
EEPROM data register
xxxx xxxx
EEPROM address register
xxxx xxxx
(1)
0Ah
0Bh
PCLATH
INTCON
—
—
—
Write buffer for upper 5 bits of the PC
INTE RBIE T0IF INTF
Bank 1
Uses contents of FSR to address data memory (not a physical register)
---0 0000
---0 0000
0000 000u
GIE
EEIE
T0IE
RBIF
0000 000x
80h
INDF
---- ----
1111 1111
---- ----
1111 1111
OPTION_
REG
81h
82h
RBPU INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
C
PCL
Low order 8 bits of Program Counter (PC)
RP0 TO PD
Indirect data memory address pointer 0
0000 0000
0000 0000
(2)
83h
84h
85h
86h
STATUS
FSR
IRP
—
RP1
—
Z
DC
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
---- ----
000q quuu
uuuu uuuu
---1 1111
1111 1111
---- ----
TRISA
TRISB
—
PORTA data direction register
PORTB data direction register
Unimplemented location, read as '0'
87h
88h
EECON1
EECON2
—
—
—
EEIF
WRERR
WREN
WR
RD
---0 x000
---- ----
---0 q000
---- ----
89h
EEPROM control register 2 (not a physical register)
(1)
0Ah
0Bh
PCLATH
INTCON
—
—
—
Write buffer for upper 5 bits of the PC
INTE RBIE T0IF INTF
---0 0000
0000 000x
---0 0000
0000 000u
GIE
EEIE
T0IE
RBIF
Legend: x= unknown, u= unchanged. -= unimplemented read as '0', q= value depends on condition.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never transferred
to PCLATH.
2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1997 Microchip Technology Inc.
DS30445C-page 13
PIC16C84
4.2.2.1
STATUS REGISTER
Only the BCF, BSF, SWAPF and MOVWF instructions
should be used to alter the STATUS register (Table 9-2)
because these instructions do not affect any status bit.
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bit for
data memory.
Note 1: The IRP and RP1 bits (STATUS<7:6>) are
not used by the PIC16C84 and should be
programmed as cleared. Use of these bits
as general purpose R/W bits is NOT
recommended, since this may affect
upward compatibility with future products.
As with any register, the STATUS register can be the
destination for any instruction. If the STATUS register is
the destination for an instruction that affects the Z, DC
or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to device logic.
Furthermore, the TO and PD bits are not writable.
Therefore, the result of an instruction with the STATUS
register as destination may be different than intended.
Note 2: The C and DC bits operate as a borrow
and digit borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
Note 3: When the STATUS register is the
destination for an instruction that affects
the Z, DC or C bits, then the write to these
three bits is disabled. The specified bit(s)
will be updated according to device logic
FIGURE 4-3: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing)
0 = Bank 0, 1 (00h - FFh)
1 = Bank 2, 3 (100h - 1FFh)
The IRP bit is not used by the PIC16C8X. IRP should be maintained clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
Each bank is 128 bytes. Only bit RP0 is used by the PIC16C8X. RP1 should be maintained clear.
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
TO: Time-out bit
1 = After power-up, CLRWDTinstruction, or SLEEPinstruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDTinstruction
0 = By execution of the SLEEPinstruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (for ADDWFand ADDLWinstructions) (For borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (for ADDWFand ADDLWinstructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of
the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or
low order bit of the source register.
DS30445C-page 14
1997 Microchip Technology Inc.
PIC16C84
4.2.2.2
OPTION_REG REGISTER
Note: When the prescaler is assigned to
the WDT (PSA = '1'), TMR0 has a 1:1
prescaler assignment.
The OPTION_REG register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external INT interrupt,
TMR0, and the weak pull-ups on PORTB.
FIGURE 4-4: OPTION_REG REGISTER (ADDRESS 81h)
R/W-1
RBPU
bit7
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
R
= Readable bit
W = Writable bit
U
bit0
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled (by individual port latch values)
bit 6:
bit 5:
bit 4:
bit 3:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to TMR0
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1997 Microchip Technology Inc.
DS30445C-page 15
PIC16C84
4.2.2.3
INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
The INTCON register is a readable and writable
register which contains the various enable bits for all
interrupt sources.
FIGURE 4-5:
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
GIE
R/W-0
EEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
Note: For the operation of the interrupt structure, please refer to Section 8.5.
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
INTE: RB0/INT Interrupt Enable bit
1 = Enables the RB0/INT interrupt
0 = Disables the RB0/INT interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
T0IF: TMR0 overflow interrupt flag bit
1 = TMR0 has overflowed (must be cleared in software)
0 = TMR0 did not overflow
INTF: RB0/INT Interrupt Flag bit
1 = The RB0/INT interrupt occurred
0 = The RB0/INT interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
DS30445C-page 16
1997 Microchip Technology Inc.
PIC16C84
4.3
Program Counter: PCL and PCLATH
Note: The PIC16C84 ignores the PCLATH<4:3>
bits, which are used for program memory
pages 1, 2 and 3 (0800h - 1FFFh).The use
of PCLATH<4:3> as general purpose R/W
bits is not recommended since this may
affect upward compatibility with future
products.
The Program Counter (PC) is 13-bits wide. The low
byte is the PCL register, which is a readable and
writable register.The high byte of the PC (PC<12:8>) is
not directly readable nor writable and comes from the
PCLATH register.The PCLATH (PC latch high) register
is a holding register for PC<12:8>. The contents of
PCLATH are transferred to the upper byte of the
program counter when the PC is loaded with a new
value. This occurs during a CALL, GOTOor a write to
PCL. The high bits of PC are loaded from PCLATH as
shown in Figure 4-6.
4.4
Stack
The PIC16C84 has an 8 deep x 13-bit wide hardware
stack (Figure 4-1). The stack space is not part of either
program or data space and the stack pointer is not
readable or writable.
FIGURE 4-6: LOADING OF PC IN
DIFFERENT SITUATIONS
The entire 13-bit PC is “pushed” onto the stack when a
CALLinstruction is executed or an interrupt is acknowl-
edged.The stack is “popped” in the event of a RETURN,
RETLW or a RETFIE instruction execution. PCLATH is
not affected by a push or a pop operation.
PCH
PCL
12
8
7
0
INST with PCL
as dest
PC
8
PCLATH<4:0>
PCLATH
5
ALU result
Note: There are no instruction mnemonics called
push or pop. These are actions that occur
from the execution of the CALL, RETURN,
RETLW, and RETFIE instructions, or the
vectoring to an interrupt address.
PCH
12 11 10
PCL
8
7
0
The stack operates as a circular buffer. That is, after the
stack has been pushed eight times, the ninth push over-
writes the value that was stored from the first push. The
tenth push overwrites the second push (and so on).
GOTO, CALL
PC
11
PCLATH<4:3>
PCLATH
2
Opcode <10:0>
If the stack is effectively popped nine times, the PC
value is the same as the value from the first pop.
4.3.1
COMPUTED GOTO
Note: There are no status bits to indicate stack
overflow or stack underflow conditions.
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 word block). Refer to the
application note “Implementing a Table Read” (AN556).
4.3.2
PROGRAM MEMORY PAGING
The PIC16C84 has 1K of program memory. The CALL
and GOTO instructions have an 11-bit address range.
This 11-bit address range allows a branch within a 2K
program memory page size. For future PIC16CXX
program memory expansion, there must be another
two bits to specify the program memory page. These
paging bits come from the PCLATH<4:3> bits
(Figure 4-6). When doing a CALLor a GOTOinstruction,
the user must ensure that these page bits
(PCLATH<4:3>) are programmed to the desired
program memory page. If a CALL instruction (or
interrupt) is executed, the entire 13-bit PC is “pushed”
onto the stack (see next section). Therefore, manipula-
tion of the PCLATH<4:3> is not required for the return
instructions (which “pops” the PC from the stack).
1997 Microchip Technology Inc.
DS30445C-page 17
PIC16C84
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
4.5
Indirect Addressing; INDF and FSR
Registers
The INDF register is not a physical register. Address-
ing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer). This is indirect addressing.
EXAMPLE 4-2: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR
clrf
incf
;
to RAM
INDF ;clear INDF register
FSR ;inc pointer
EXAMPLE 4-1: INDIRECT ADDRESSING
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
• A read of the INDF register will return the value of
10h
NEXT
btfss FSR,4 ;all done?
goto
NEXT ;NO, clear next
CONTINUE
:
;YES, continue
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDF register now will return the
value of 0Ah.
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-7. However, IRP is not used in the
PIC16C84.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
FIGURE 4-7: DIRECT/INDIRECT ADDRESSING
Indirect Addressing
Direct Addressing
RP1 RP0
6
0
IRP
7
(FSR)
0
from opcode
bank select
location select
bank select
00h
location select
00
01
10
11
00h
not used not used
0Bh
0Ch
Addresses
map back
to Bank 0
Data
Memory
2Fh
30h
7Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
DS30445C-page 18
1997 Microchip Technology Inc.
PIC16C84
EXAMPLE 5-1: INITIALIZING PORTA
5.0
I/O PORTS
CLRF
PORTA
; Initialize PORTA by
; setting output
; data latches
The PIC16C84 has two ports, PORTA and PORTB.
Some port pins are multiplexed with an alternate func-
tion for other features on the device.
BSF
STATUS, RP0 ; Select Bank 1
MOVLW 0x0F
; Value used to
; initialize data
; direction
5.1
PORTA and TRISA Registers
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. All other RA port pins
have TTL input levels and full CMOS output drivers. All
pins have data direction bits (TRIS registers) which can
configure these pins as output or input.
MOVWF TRISA
; Set RA<3:0> as inputs
; RA4 as outputs
; TRISA<7:5> are always
; read as '0'.
FIGURE 5-2: BLOCK DIAGRAM OF PIN RA4
Setting a TRISA bit (=1) will make the corresponding
PORTA pin an input, i.e., put the corresponding output
driver in a hi-impedance mode. Clearing a TRISA bit
(=0) will make the corresponding PORTA pin an output,
i.e., put the contents of the output latch on the selected
pin.
Data
bus
D
Q
Q
WR
PORT
CK
RA4 pin
N
Reading the PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
Data Latch
VSS
D
Q
Q
WR
TRIS
CK
The RA4 pin is multiplexed with the TMR0 clock input.
Schmitt
Trigger
input
TRIS Latch
FIGURE 5-1: BLOCK DIAGRAM OF PINS
RA3:RA0
buffer
Data
bus
RD TRIS
D
Q
Q
Q
D
VDD
P
WR
Port
CK
EN
RD PORT
Data Latch
Q
N
I/O pin
TMR0 clock input
D
Note: I/O pin has protection diodes to VSS only.
WR
TRIS
VSS
Q
CK
TRIS Latch
Note: For crystal oscillator configurations
operating below 500 kHz, the device may
generate a spurious internal Q-clock when
PORTA<0> switches state. This does not
occur with an external clock in RC mode.
To avoid this, the RA0 pin should be kept
static, i.e. in input/output mode, pin RA0
should not be toggled.
TTL
input
buffer
RD TRIS
Q
D
EN
RD PORT
Note: I/O pins have protection diodes to VDD and VSS.
1997 Microchip Technology Inc.
DS30445C-page 19
PIC16C84
TABLE 5-1
Name
PORTA FUNCTIONS
Bit0
Buffer Type
Function
RA0
bit0
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
ST
Input/output
Input/output
Input/output
Input/output
RA1
RA2
RA3
RA4/T0CKI
Input/output or external clock input for TMR0.
Output is open drain type.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 5-2
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
Power-on
Reset
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h
85h
PORTA
TRISA
—
—
—
—
—
—
RA4/T0CKI
TRISA4
RA3
RA2
RA1
RA0
---x xxxx
---1 1111
---u uuuu
---1 1111
TRISA3
TRISA2 TRISA1 TRISA0
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are unimplemented, read as '0'
DS30445C-page 20
1997 Microchip Technology Inc.
PIC16C84
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' on
any bit in the TRISB register puts the corresponding
output driver in a hi-impedance mode. A '0' on any bit
in the TRISB register puts the contents of the output
latch on the selected pin(s).
a) Read (or write) PORTB. This will end the mis-
match condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set the RBIF bit.
Reading PORTB will end the mismatch condition, and
allow the RBIF bit to be cleared.
Each of the PORTB pins have a weak internal pull-up.
A single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (OPTION_REG<7>) bit.
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression (see AN552 in the
Embedded Control Handbook).
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The pins value in input mode
are compared with the old value latched on the last
read of PORTB.The “mismatch” outputs of the pins are
OR’ed together to generate the RB port
change interrupt.
Note 1: If a change on the I/O pin should occur
when a read operation of PORTB is being
executed (start of the Q2 cycle), the RBIF
interrupt flag bit may not be set.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-3: BLOCK DIAGRAM OF PINS
RB7:RB4
FIGURE 5-4: BLOCK DIAGRAM OF PINS
RB3:RB0
VDD
VDD
RBPU(1)
RBPU(1)
weak
P
weak
pull-up
P
pull-up
Data Latch
Data bus
Data Latch
Data bus
D
Q
D
Q
I/O
pin(2)
I/O
WR Port
CK
TRIS Latch
pin(2)
WR Port
CK
TRIS Latch
D
Q
D
Q
WR TRIS
TTL
WR TRIS
TTL
CK
CK
Input
Input
Buffer
Buffer
Latch
RD TRIS
RD Port
RD TRIS
RD Port
Q
D
Q
D
EN
EN
Set RBIF
RB0/INT
From other
RB7:RB4 pins
Q
D
RD Port
EN
Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
RD Port
2: I/O pins have diode protection to VDD and VSS.
Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.
1997 Microchip Technology Inc.
DS30445C-page 21
PIC16C84
EXAMPLE 5-1: INITIALIZING PORTB
CLRF
PORTB
; Initialize PORTB by
; setting output
; data latches
BSF
STATUS, RP0 ; Select Bank 1
MOVLW 0xCF
; Value used to
; initialize data
; direction
MOVWF TRISB
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
TABLE 5-3
PORTB FUNCTIONS
Name
Bit
Buffer Type
I/O Consistency Function
RB0/INT
bit0
TTL
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
RB2
RB3
RB4
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up.
RB5
RB6
RB7
bit5
bit6
bit7
TTL
Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up.
(1)
TTL/ST
Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up. Serial programming clock.
(1)
TTL/ST
Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger.
Note 1: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
Power-on
Reset
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
06h
86h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
TRISB
TRISB7 TRISB6 TRISB5
RBPU INTEDG T0CS
TRISB4
TRISB3
TRISB2 TRISB1 TRISB0
PS2 PS1 PS0
1111 1111
1111 1111
OPTION_
REG
81h
T0SE
PSA
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS30445C-page 22
1997 Microchip Technology Inc.
PIC16C84
5.3.2
SUCCESSIVE OPERATIONS ON I/O PORTS
5.3
I/O Programming Considerations
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 5-
5).Therefore, care must be exercised if a write followed
by a read operation is carried out on the same I/O port.
The sequence of instructions should be such that the
pin voltage stabilizes (load dependent) before the next
instruction which causes that file to be read into the
CPU is executed. Otherwise, the previous state of that
pin may be read into the CPU rather than the new state.
When in doubt, it is better to separate these instruc-
tions with a NOP or another instruction not accessing
this I/O port.
5.3.1
BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSFoperation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(i.e., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However,
if bit0 is switched into output mode later on, the content
of the data latch is unknown.
Example 5-1 shows the effect of two sequential read-
modify-write instructions (e.g., BCF, BSF, etc.) on an
I/O port.
EXAMPLE 5-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(i.e., BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
;Initial PORT settings: PORTB<7:4> Inputs
;
PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
;
;
PORT latch PORT pins
---------- ---------
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output current may damage the chip.
BCF PORTB, 7
BCF PORTB, 6
BSF STATUS, RP0
BCF TRISB, 7
BCF TRISB, 6
; 01pp ppp
; 10pp ppp
;
; 10pp ppp
; 10pp ppp
11pp ppp
11pp ppp
11pp ppp
10pp ppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
FIGURE 5-5: SUCCESSIVE I/O OPERATION
Q4
Q4
Q4
Q1 Q2
Q4
Q3
Q3
Q3
Q3
Q1 Q2
PC
Q1 Q2
Q1 Q2
Note:
This example shows a write to PORTB
followed by a read from PORTB.
PC + 3
NOP
PC
Instruction
fetched
PC + 1
PC + 2
NOP
MOVWF PORTB MOVF PORTB,W
write to
PORTB
Note that:
data setup time = (0.25TCY - TPD)
RB7:RB0
where TCY = instruction cycle
TPD = propagation delay
Port pin
sampled here
TPD
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
Instruction
executed
NOP
MOVWF PORTB
write to
MOVF PORTB,W
PORTB
1997 Microchip Technology Inc.
DS30445C-page 23
PIC16C84
NOTES:
DS30445C-page 24
1997 Microchip Technology Inc.
PIC16C84
edge select bit, T0SE (OPTION<4>). Clearing bit T0SE
selects the rising edge. Restrictions on the external
clock input are discussed in detail in Section 6.2.
6.0
TIMER0 MODULE AND TMR0
REGISTER
The Timer0 module timer/counter has the following
features:
The prescaler is shared between the Timer0 Module
and the Watchdog Timer. The prescaler assignment is
controlled, in software, by control bit PSA
(OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 Module. The prescaler is not
readable or writable. When the prescaler (Section 6.3)
is assigned to the Timer0 Module, the prescale value
(1:2, 1:4, ..., 1:256) is software selectable.
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
6.1
TMR0 Interrupt
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module
(Figure 6-1) will increment every instruction cycle
(without prescaler). If the TMR0 register is written, the
increment is inhibited for the following two cycles
(Figure 6-2 and Figure 6-3). The user can work around
this by writing an adjusted value to the TMR0 register.
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
the T0IF bit (INTCON<2>). The interrupt can be
masked by clearing enable bit T0IE (INTCON<5>).The
T0IF bit must be cleared in software by the Timer0
Module interrupt service routine before re-enabling this
interrupt.The TMR0 interrupt (Figure 6-4) cannot wake
the processor from SLEEP since the timer is shut off
during SLEEP.
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode TMR0 will increment either
on every rising or falling edge of pin RA4/T0CKI. The
incrementing edge is determined by the T0 source
FIGURE 6-1: TMR0 BLOCK DIAGRAM
Data bus
FOSC/4
0
1
PSout
8
1
0
Sync with
Internal
clocks
TMR0 register
RA4/T0CKI
pin
Programmable
Prescaler
PSout
(2 cycle delay)
T0SE
3
Set bit T0IF
on Overflow
PS2, PS1, PS0
PSA
T0CS
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
FIGURE 6-2: TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
PC
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
TMR0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
1997 Microchip Technology Inc.
DS30445C-page 25
PIC16C84
FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
PC
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
NT0
TMR0
Instruction
Execute
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
FIGURE 6-4: TMR0 INTERRUPT TIMING
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
OSC1
CLKOUT(3)
TMR0 timer
FEh
1
FFh
1
00h
01h
02h
4
T0IF bit
(INTCON<2>)
GIE bit
(INTCON<7>)
Interrupt Latency(2)
PC +1
INSTRUCTION FLOW
PC
PC
PC +1
0004h
0005h
Instruction
fetched
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Instruction
executed
Inst (PC-1)
Dummy cycle
Dummy cycle
Inst (0004h)
Inst (PC)
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit.
The TMR0 register will roll over 3 Tosc cycles later.
DS30445C-page 26
1997 Microchip Technology Inc.
PIC16C84
6.2.2
TMR0 INCREMENT DELAY
6.2
Using TMR0 with External Clock
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
Module is actually incremented. Figure 6-5 shows the
delay from the external clock edge to the timer
incrementing.
When an external clock input is used for TMR0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing
of
the
TMR0
register
after
synchronization.
6.3
Prescaler
6.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of pin RA4/T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2Tosc (plus a small RC delay) and low
for at least 2Tosc (plus a small RC delay). Refer to the
electrical specification of the desired device.
An 8-bit counter is available as a prescaler for the
Timer0 Module, or as a postscaler for the Watchdog
Timer (Figure 6-6). For simplicity, this counter is being
referred to as “prescaler” throughout this data sheet.
Note that there is only one prescaler available which is
mutually exclusive between the Timer0 Module and the
Watchdog Timer. Thus, a prescaler assignment for the
Timer0 Module means that there is no prescaler for the
Watchdog Timer, and vice-versa.
When a prescaler is used, the external clock input is
divided by an asynchronous ripple counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4Tosc (plus a small RC delay) divided
by the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the
minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the AC Electrical
Specifications of the desired device.
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
When assigned to the Timer0 Module, all instructions
writing to the Timer0 Module (e.g., CLRF 1, MOVWF 1,
BSF 1,x ....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Ext. Clock Input or
Prescaler Out (Note 2)
(Note 3)
Ext. Clock/Prescaler
Output After Sampling
Increment TMR0 (Q4)
TMR0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on TMR0 input = ± 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows ↑ indicate where sampling occurs. A small clock pulse may be missed by sampling.
1997 Microchip Technology Inc.
DS30445C-page 27
PIC16C84
FIGURE 6-6: BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER
Data Bus
CLKOUT (= Fosc/4)
8
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
pin
SYNC
2
Cycles
TMR0 register
T0SE
T0CS
Set bit T0IF
on overflow
PSA
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
DS30445C-page 28
1997 Microchip Technology Inc.
PIC16C84
6.3.1
SWITCHING PRESCALER ASSIGNMENT
EXAMPLE 6-1: CHANGING PRESCALER
(TIMER0→WDT)
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution).
BCF
CLRF
STATUS, RP0 ;Bank 0
TMR0 ;Clear TMR0
; and Prescaler
STATUS, RP0 ;Bank 1
;Clears WDT
b'xxxx1xxx' ;Select new
BSF
Note: To avoid an unintended device RESET, the
CLRWDT
MOVLW
MOVWF
BCF
following
instruction
sequence
(Example 6-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT.This sequence must be
taken even if the WDT is disabled. To
change prescaler from the WDT to the
Timer0 module use the sequence shown in
Example 6-2.
OPTION
; prescale value
STATUS, RP0 ;Bank 0
EXAMPLE 6-2: CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
;Clear WDT and
; prescaler
BSF
STATUS, RP0 ;Bank 1
MOVLW
b'xxxx0xxx' ;Select TMR0, new
; prescale value
’ and clock source
MOVWF
BCF
OPTION
STATUS, RP0 ;Bank 0
;
TABLE 6-1
REGISTERS ASSOCIATED WITH TIMER0
Value on
Power-on
Reset
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
0Bh
TMR0
Timer0 module’s register
xxxx xxxx
0000 000x
uuuu uuuu
0000 0000
INTCON
GIE
EEIE
T0IE
INTE
RBIE
T0IF
PS2
INTF
PS1
RBIF
PS0
81h
85h
OPTION
TRISA
RBPU INTEDG
T0CS
—
T0SE
PSA
1111 1111
---1 1111
1111 1111
---1 1111
—
—
TRISA4
TRISA3
TRISA2 TRISA1 TRISA0
Legend: x= unknown, u= unchanged. -= unimplemented read as '0'. Shaded cells are not associated with Timer0.
1997 Microchip Technology Inc.
DS30445C-page 29
PIC16C84
NOTES:
DS30445C-page 30
1997 Microchip Technology Inc.
PIC16C84
When the device is code protected, the CPU may
continue to read and write the data EEPROM memory.
The device programmer can no longer access
this memory.
7.0
DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers. There are four SFRs used to read and write
this memory. These registers are:
7.1
EEADR
The EEADR register can address up to a maximum of
256 bytes of data EEPROM. Only the first 64 bytes of
data EEPROM are implemented.
• EECON1
• EECON2
• EEDATA
• EEADR
The upper two bits are address decoded. This means
that these two bits must always be '0' to ensure that the
address is in the 64 byte memory space.
EEDATA holds the 8-bit data for read/write, and EEADR
holds the address of the EEPROM location being
accessed. PIC16C84 devices have 64 bytes of data
EEPROM with an address range from 0h to 3Fh.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write).The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write-
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC specifications for
exact limits.
FIGURE 7-1: EECON1 REGISTER (ADDRESS 88h)
U
—
U
U
R/W-0
EEIF
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-x
RD
—
—
WRERR
R
= Readable bit
W = Writable bit
bit7
bit0
S
U
= Settable bit
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:5 Unimplemented: Read as '0'
bit 4
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0 = The write operation completed
bit 2
bit 1
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only
be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software).
0 = Does not initiate an EEPROM read
1997 Microchip Technology Inc.
DS30445C-page 31
PIC16C84
7.2
EECON1 and EECON2 Registers
7.4
Writing to the EEPROM Data Memory
EECON1 is the control register with five low order bits
physically implemented. The upper-three bits are non-
existent and read as '0's.
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software.They are cleared in hardware at completion of
the read or write operation.The inability to clear the WR
bit in software prevents the accidental, premature ter-
mination of a write operation.
EXAMPLE 7-1: DATA EEPROM WRITE
BSF
STATUS, RP0 ; Bank 1
BCF
BSF
INTCON, GIE ; Disable INTs.
EECON1, WREN ; Enable Write
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
EECON2
AAh
EECON2
EECON1,WR
;
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.The WRERR bit is
set when a write operation is interrupted by a MCLR
reset or a WDT time-out reset during normal operation.
In these situations, following reset, the user can check
the WRERR bit and rewrite the location. The data and
address will be unchanged in the EEDATA and
EEADR registers.
; Write 55h
;
; Write AAh
; Set WR bit
;
begin write
BSF
INTCON, GIE ; Enable INTs.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment.
Interrupt flag bit EEIF is set when write is complete. It
must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the Data EEPROM write sequence.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
7.3
Reading the EEPROM Data Memory
To read a data memory location, the user must write
the address to the EEADR register and then set control
bit RD (EECON1<0>).The data is available, in the very
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle.The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
EXAMPLE 7-1: DATA EEPROM READ
BCF
STATUS, RP0 ; Bank 0
MOVLW
MOVWF
BSF
BSF
BCF
CONFIG_ADDR
EEADR
STATUS, RP0 ; Bank 1
EECON1, RD ; EE Read
STATUS, RP0 ; Bank 0
EEDATA, W ; W = EEDATA
;
; Address to read
Note: The data EEPROM memory E/W cycle
time may occasionally exceed the 10 ms
specification (typical). To ensure that the
write cycle is complete, use the EE
interrupt or poll the WR bit (EECON1<1>).
Both these events signify the completion of
the write cycle.
MOVF
DS30445C-page 32
1997 Microchip Technology Inc.
PIC16C84
7.5
Write Verify
7.6
Protection Against Spurious Writes
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 7-1) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit. The Total Endurance disk
will help determine your comfort level.
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
Generally the EEPROM write failure will be a bit which
was written as a '1', but reads back as a '0' (due to
leakage off the bit).
7.7
Data EEPROM Operation during Code
Protect
EXAMPLE 7-1: WRITE VERIFY
When the device is code protected, the CPU is able to
read and write unscrambled data to the Data
EEPROM.
BCF
:
:
STATUS, RP0 ; Bank 0
; Any code can go here
;
MOVF EEDATA, W
; Must be in Bank 0
For ROM devices, there are two code protection bits
(Section 8.1). One for the ROM program memory and
one for the Data EEPROM memory.
BSF
BSF
BCF
STATUS, RP0 ; Bank 1
READ
EECON1, RD ; YES, Read the
;
value written
7.8
Power Consumption Considerations
STATUS, RP0 ; Bank 0
;
Note: It is recommended that the EEADR<7:6>
bits be cleared.When either of these bits is
set, the maximum IDD for the device is
higher than when both are cleared. The
specification is 400 µA. With EEADR<7:6>
cleared, the maximum is approximately
150 µA.
; Is the value written (in W reg) and
;
;
read (in EEDATA) the same?
SUBWF EEDATA, W
;
BTFSS STATUS, Z
GOTO WRITE_ERR
:
:
; Is difference 0?
; NO, Write error
; YES, Good write
; Continue program
TABLE 7-1
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Value on
Power-on
Reset
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
09h
88h
89h
EEDATA EEPROM data register
xxxx xxxx
xxxx xxxx
---0 x000
---- ----
uuuu uuuu
uuuu uuuu
---0 q000
---- ----
EEADR
EEPROM address register
EECON1
—
—
—
EEIF
WRERR
WREN
WR
RD
EECON2 EEPROM control register 2
Legend: x= unknown, u= unchanged, -= unimplemented read as '0', q= value depends upon condition. Shaded cells are not
used by Data EEPROM.
1997 Microchip Technology Inc.
DS30445C-page 33
PIC16C84
NOTES:
DS30445C-page 34
1997 Microchip Technology Inc.
PIC16C84
the chip in reset until the crystal oscillator is stable.The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only. This
design keeps the device in reset while the power supply
stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
8.0
SPECIAL FEATURES OF THE
CPU
What sets
a
microcontroller apart from other
processors are special circuits to deal with the needs of
real time applications. The PIC16C84 has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection. These features are:
SLEEP mode offers a very low current power-down
mode. The user can wake-up from SLEEP through
external reset, Watchdog Timer time-out or through an
interrupt. Several oscillator options are provided to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits are used to
select the various options.
• OSC selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
8.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in
program memory location 2007h.
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
Address 2007h is beyond the user program memory
space and it belongs to the special test/configuration
memory space (2000h - 3FFFh). This space can only
be accessed during programming.
• In-circuit serial programming
The PIC16C84 has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
To find out how to program the PIC16C84, refer to
PIC16C84 EEPROM Memory Programming Specifica-
tion (DS30189).
FIGURE 8-1: CONFIGURATION WORD
U-1
—
U-1
—
U-1
—
U-1
—
U-1 U-1 U-1
U-1 U-1 R/P-u
CP
R/P-u
R/P-u R/P-u
R/P-u
—
—
—
—
—
PWRTE WDTE FOSC1 FOSC0
bit0
bit13
R
P
U
= Readable bit
= Programmable bit
= Unimplemented bit,
read as ‘1’
- n = Value at POR reset
u = unchanged
bit 13:5 Unimplemented: Read as '1'
bit 4
bit 3
bit 2
CP: Code Protection bit
1 = Code protection off
0 = All memory is code protected
PWRTE: Power-up Timer Enable bit
1 = Power-up timer is enabled
0 = Power-up timer is disabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1:0 FOSC1:FOSC0: Oscillator Selection bits
11 =RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
1997 Microchip Technology Inc.
DS30445C-page 35
PIC16C84
8.2
Oscillator Configurations
TABLE 8-1
CAPACITOR SELECTION
FORCERAMICRESONATORS
8.2.1
OSCILLATOR TYPES
The PIC16C84 can be operated in four different
oscillator modes. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
Ranges Tested:
Mode
Freq
OSC1/C1
OSC2/C2
XT
455 kHz
2.0 MHz
4.0 MHz
47 - 100 pF 47 - 100 pF
15 - 33 pF 15 - 33 pF
15 - 33 pF 15 - 33 pF
• LP
• XT
• HS
• RC
Low Power Crystal
Crystal/Resonator
HS
8.0 MHz
15 - 33 pF 15 - 33 pF
15 - 33 pF 15 - 33 pF
High Speed Crystal/Resonator
Resistor/Capacitor
10.0 MHz
Note: Recommended values of C1 and C2 are identical to
the ranges tested table.
8.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
Higher capacitance increases the stability of the
oscillator but also increases the start-up time.
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for the
appropriate values of external components.
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 8-2).
FIGURE 8-2: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP OSC
Resonators Tested:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
CONFIGURATION)
(1)
C1
OSC1
10.0 MHz Murata Erie CSA10.00MTZ
To
internal
logic
None of the resonators had built-in capacitors.
XTAL
(3)
RF
TABLE 8-2
CAPACITOR SELECTION
OSC2
SLEEP
PIC16CXX
FOR CRYSTAL OSCILLATOR
(2)
RS
(1)
C2
Mode
Freq
OSC1/C1
OSC2/C2
Note1: See Table 8-1 and Table 8-2 for recom-
mended values of C1 and C2.
LP
32 kHz
200 kHz
68 - 100 pF
15 - 33 pF
68 - 100 pF
15 - 33 pF
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the crystal chosen.
XT
HS
100 kHz
2 MHz
4 MHz
100 - 150 pF 100 - 150 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
4 MHz
10 MHz
15 - 33 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
The PIC16C84 oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
Note: Higher capacitance increases the stability of
oscillator but also increases the start-up time.
These values are for design guidance only. Rs may
be required in HS mode as well as XT mode to
avoid overdriving crystals with low drive level spec-
ification. Since each crystal has its own
a
frequency out of the crystal manufacturers
specifications.When in XT, LP or HS modes, the device
can have an external clock source to drive the OSC1/
CLKIN pin (Figure 8-3).
FIGURE 8-3: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
characteristics, the user should consult the crystal
manufacturer for appropriate values of external
components.
OSC CONFIGURATION)
For VDD > 4.5V, C1 = C2 ≈ 30 pF is recommended.
Crystals Tested:
OSC1
OSC2
Clock from
ext. system
PIC16CXX
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
Open
100 kHz
200 kHz
1.0 MHz
2.0 MHz
4.0 MHz
10.0 MHz
Epson C-2 100.00 KC-P ± 20 PPM
STD XTL 200.000 KHz
ECS ECS-10-13-2
ECS ECS-20-S-2
ECS ECS-40-S-4
ECS ECS-100-S-4
± 20 PPM
± 50 PPM
± 50 PPM
± 50 PPM
± 50 PPM
DS30445C-page 36
1997 Microchip Technology Inc.
PIC16C84
8.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
8.2.4
RC OSCILLATOR
For timing insensitive applications the RC device option
offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) values, capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types also affects the oscillation frequency, especially
for low Cext values. The user needs to take into
account variation due to tolerance of the external
R and C components. Figure 8-6 shows how an R/C
combination is connected to the PIC16C84. For Rext
values below 2.2 kΩ, the oscillator operation may
become unstable, or stop completely. For very high
Rext values (e.g., 1 MΩ), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, we
recommend keeping Rext between 3 kΩ and 100 kΩ.
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits are
available; one with series resonance, and one with
parallel resonance.
Figure 8-4 shows a parallel resonant oscillator circuit.
The circuit is designed to use the fundamental
frequency of the crystal.The 74AS04 inverter performs
the 180-degree phase shift that a parallel oscillator
requires. The 4.7 kΩ resistor provides negative
feedback for stability. The 10 kΩ potentiometer biases
the 74AS04 in the linear region. This could be used for
external oscillator designs.
FIGURE 8-4: EXTERNAL PARALLEL
RESONANT CRYSTAL
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With little
or no external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
OSCILLATOR CIRCUIT
+5V
To Other
Devices
PIC16CXX
10k
74AS04
4.7k
See the electrical specification section for RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger R
(since leakage current variation will affect RC
frequency more for large R) and for smaller C (since
variation of input capacitance has a greater affect on
RC frequency).
CLKIN
74AS04
10k
XTAL
10k
See the electrical specification section for variation of
oscillator frequency due to VDD for given Rext/Cext
values as well as frequency variation due to
operating temperature.
20 pF
20 pF
Figure 8-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180-
degree phase shift. The 330 kΩ resistors provide the
negative feedback to bias the inverters in their linear
region.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test
purposes or to synchronize other logic (see Figure 3-2
for waveform).
FIGURE 8-6: RC OSCILLATOR MODE
FIGURE 8-5: EXTERNAL SERIES
RESONANT CRYSTAL
VDD
OSCILLATOR CIRCUIT
Rext
Internal
OSC1
clock
To Other
Devices
Cext
330 kΩ
330 kΩ
PIC16CXX
PIC16CXX
VSS
74AS04
74AS04
74AS04
OSC2/CLKOUT
Fosc/4
CLKIN
0.1 µF
Recommended values: 3 kΩ ≤ Rext ≤ 100 kΩ
XTAL
Cext > 20pF
Note: When the device oscillator is in RC mode,
do not drive the OSC1 pin with an external
clock or you may damage the device.
1997 Microchip Technology Inc.
DS30445C-page 37
PIC16C84
Some registers are not affected in any reset condition;
their status is unknown on a POR reset and unchanged
in any other reset. Most other registers are reset to a
“reset state” on POR, MCLR or WDT reset during
normal operation and on MCLR reset during SLEEP.
They are not affected by a WDT reset during SLEEP,
since this reset is viewed as the resumption of normal
operation.
8.3
Reset
The PIC16C84 differentiates between various kinds
of reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
Table 8-3 gives a description of reset conditions for the
program counter (PC) and the STATUS register.
Table 8-4 gives a full description of reset states for all
registers.
Figure 8-7 shows a simplified block diagram of the on-
chip reset circuit. The electrical specifications state the
pulse width requirements for the MCLR pin.
The TO and PD bits are set or cleared differently in dif-
ferent reset situations (Section 8.7). These bits are
used in software to determine the nature of the reset.
FIGURE 8-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT
WDT
Module
Time_Out
Reset
VDD rise
detect
S
R
Power_on_Reset
VDD
OST/PWRT
OST
Chip_Reset
Q
10-bit Ripple counter
10-bit Ripple counter
OSC1/
CLKIN
PWRT
On-chip
(1)
RC OSC
Enable PWRT
Enable OST
See Table 8-5
Note 1: This is a separate oscillator from the
RC oscillator of the CLKIN pin.
DS30445C-page 38
1997 Microchip Technology Inc.
PIC16C84
TABLE 8-3
RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
Program Counter
STATUS Register
Condition
Power-on Reset
000h
000h
000h
000h
PC + 1
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset (during normal operation)
WDT Wake-up
(1)
Interrupt wake-up from SLEEP
PC + 1
uuu1 0uuu
Legend: u= unchanged, x= unknown.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
TABLE 8-4
Register
RESET CONDITIONS FOR ALL REGISTERS
MCLR Reset during:
Wake-up from SLEEP:
– through interrupt
– through WDT time-out
– normal operation
– SLEEP
Address
Power-on Reset
WDT Reset during nor-
mal operation
W
—
xxxx xxxx
---- ----
xxxx xxxx
0000h
uuuu uuuu
---- ----
uuuu uuuu
0000h
uuuu uuuu
---- ----
uuuu uuuu
INDF
00h
01h
02h
03h
04h
05h
06h
08h
09h
0Ah
0Bh
80h
81h
82h
83h
84h
85h
86h
88h
89h
8Ah
8Bh
TMR0
(2)
PCL
PC + 1
(3)
(3)
STATUS
FSR
0001 1xxx
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---0 0000
0000 000x
---- ----
1111 1111
0000h
000q quuu
uuuq quuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---0 0000
0000 000u
---- ----
1111 1111
0000h
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
PORTA
PORTB
EEDATA
EEADR
PCLATH
INTCON
INDF
(1)
uuuu uuuu
---- ----
uuuu uuuu
PC + 1
OPTION_REG
PCL
(3)
(3)
STATUS
FSR
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
---0 x000
---- ----
---0 0000
0000 000x
000q quuu
uuuq quuu
uuuu uuuu
---1 1111
1111 1111
---0 q000
---- ----
---0 0000
0000 000u
uuuu uuuu
---u uuuu
uuuu uuuu
---0 uuuu
---- ----
---u uuuu
TRISA
TRISB
EECON1
EECON2
PCLATH
INTCON
(1)
uuuu uuuu
Legend: u = unchanged, x = unknown, -= unimplemented bit read as '0',
q= value depends on condition.
Note 1: One or more bits in INTCON will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: Table 8-3 lists the reset value for each specific condition.
1997 Microchip Technology Inc.
DS30445C-page 39
PIC16C84
8.4
Power-on Reset (POR)
FIGURE 8-8: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD.This will eliminate
external RC components usually needed to create
Power-on Reset. A minimum rise time for VDD must be
met for this to operate properly. See Electrical Specifi-
cations for details.
VDD
VDD
D
R
R1
MCLR
PIC16CXX
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be meet to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions
are met.
C
Note 1: External Power-on Reset circuit is required
only if VDD power-up rate is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
For additional information, refer to Application Note
AN607, Power-up Trouble Shooting.
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
pin is 5 µA). A larger voltage drop will
degrade VIH level on the MCLR pin.
The POR circuit does not produce an internal reset
when VDD declines.
8.5
Power-up Timer (PWRT)
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external
The Power-up Timer (PWRT) provides a fixed 72 ms
nominal time-out (TPWRT) from POR (Figure 8-9,
Figure 8-10, Figure 8-11 and Figure 8-12). The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active.The
PWRT delay allows the VDD to rise to an acceptable
level (Possible exception shown in Figure 8-12).
capacitor C in the event of an MCLR pin
breakdown due to ESD or EOS.
A configuration bit, PWRTE, can enable/disable the
PWRT (Figure 8-1).
The power-up time delay TPWRT will vary from chip to
chip due to VDD, temperature, and process variation.
See DC parameters for details.
8.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT delay ends (Figure 8-9, Figure 8-10, Figure 8-
11 and Figure 8-12). This ensures the crystal oscillator
or resonator has started and stabilized.
The OST time-out (TOST) is invoked only for XT, LP and
HS modes and only on Power-on Reset or wake-up
from SLEEP.
When VDD rises very slowly, it is possible that the
TPWRT time-out and TOST time-out will expire before
VDD has reached its final value. In this case (Figure 8-
12), an external power-on reset circuit may be neces-
sary (Figure 8-8).
DS30445C-page 40
1997 Microchip Technology Inc.
PIC16C84
FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
1997 Microchip Technology Inc.
DS30445C-page 41
PIC16C84
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLRTIED TO VDD): SLOW VDD RISETIME
V1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
DS30445C-page 42
1997 Microchip Technology Inc.
PIC16C84
8.7
Time-out Sequence and Power Down
Status Bits (TO/PD)
8.8
Reset on Brown-Out
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.
On power-up (Figure 8-9, Figure 8-10, Figure 8-11 and
Figure 8-12) the time-out sequence is as follows: First
PWRT time-out is invoked after a POR has expired.
Then the OST is activated. The total time-out will vary
based on oscillator configuration and PWRTE
configuration bit status. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
To reset PIC16C84 devices when a brown-out occurs,
external brown-out protection circuits may be built, as
shown in Figure 8-13 and Figure 8-14.
FIGURE 8-13: BROWN-OUT PROTECTION
CIRCUIT 1
TABLE 8-5
TIME-OUT IN VARIOUS
SITUATIONS
VDD
Oscillator
Power-up
Wake-up
VDD
Configuration
from
SLEEP
PWRT
Enabled
PWRT
Disabled
33k
XT, HS, LP
RC
72 ms +
1024TOSC
1024TOSC
—
1024TOSC
10k
MCLR
72 ms
—
40k
PIC16CXX
Since the time-outs occur from the POR reset pulse, if
MCLR is kept low long enough, the time-outs will
expire. Then bringing MCLR high, execution will begin
immediately (Figure 8-9). This is useful for testing
purposes or to synchronize more than one PIC16CXX
device when operating in parallel.
This circuit will activate reset when VDD goes below
(Vz + 0.7V) where Vz = Zener voltage.
Table 8-6 shows the significance of the TO and PD bits.
Table 8-3 lists the reset conditions for some special
registers, while Table 8-4 lists the reset conditions for
all the registers.
FIGURE 8-14: BROWN-OUT PROTECTION
CIRCUIT 2
TABLE 8-6
STATUS BITS AND THEIR
SIGNIFICANCE
VDD
VDD
TO
PD
Condition
R1
1
0
x
0
0
1
1
1
x
0
1
0
1
0
Power-on Reset
Q1
Illegal, TO is set on POR
MCLR
R2
Illegal, PD is set on POR
40k
PIC16CXX
WDT Reset (during normal operation)
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt
wake-up from SLEEP
This brown-out circuit is less expensive, although less
accurate. Transistor Q1 turns off when VDD is below a
certain level such that:
R1
= 0.7V
VDD •
R1 + R2
1997 Microchip Technology Inc.
DS30445C-page 43
PIC16C84
When an interrupt is responded to; the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. For external interrupt events, such as the
RB0/INT pin or PORTB change interrupt, the interrupt
latency will be three to four instruction cycles.The exact
latency depends when the interrupt event occurs
(Figure 8-16).The latency is the same for both one and
two cycle instructions. Once in the interrupt service
routine the source(s) of the interrupt can be determined
by polling the interrupt flag bits. The interrupt flag bit(s)
must be cleared in software before re-enabling
interrupts to avoid infinite interrupt requests.
8.9
Interrupts
The PIC16C84 has 4 sources of interrupt:
• External interrupt RB0/INT pin
• TMR0 overflow interrupt
• PORTB change interrupts (pins RB7:RB4)
• EEPROM write complete interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also contains
the individual and global interrupt enable bits.
The global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. Bit GIE is cleared on reset.
Note 1: Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which re-
enable interrupts.
Note 2: If an interrupt occurs while the Global
Interrupt Enable (GIE) bit is being cleared,
the GIE bit may unintentionally be
re-enabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
The RB0/INT pin interrupt, the RB port change inter-
rupt and the TMR0 overflow interrupt flags are con-
tained in the INTCON register.
1. An instruction clears the GIE bit while
an interrupt is acknowledged
2. The program branches to the
Interrupt vector and executes the
Interrupt Service Routine.
3. The Interrupt Service Routine
completes with the execution of the
RETFIE instruction. This causes the
GIE bit to be set (enables interrupts),
and the program returns to the
instruction after the one which was
meant to disable interrupts.
The method to ensure that interrupts are
globally disabled is:
1. Ensure that the GIE bit is cleared by
the instruction, as shown in the
following code:
LOOP BCF
INTCON,GIE ;Disable All
Interrupts
BTFSC INTCON,GIE ;All Interrupts
Disabled?
;NO, try again
;
;
GOTO LOOP
;
;
;
Yes, continue
with program
flow
DS30445C-page 44
1997 Microchip Technology Inc.
PIC16C84
FIGURE 8-15: INTERRUPT LOGIC
Wake-up
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt to CPU
RBIF
RBIE
EEIF
EEIE
GIE
FIGURE 8-16: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
3
4
INT pin
1
1
Interrupt Latency
INTF flag
(INTCON<1>)
5
2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
0004h
PC+1
PC+1
—
0005h
PC
Instruction
fetched
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC-1)
Note
1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
1997 Microchip Technology Inc.
DS30445C-page 45
PIC16C84
8.9.1
INT INTERRUPT
8.10
Context Saving During Interrupts
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION_REG<6>) is set,
or falling, if INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software via the interrupt service
routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 8.12) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
During an interrupt, only the return PC value is saved
on the stack. Typically, users wish to save key register
values during an interrupt (e.g., W register and STATUS
register). This is implemented in software.
Example 8-1 stores and restores the STATUS and W
register’s values.The User defined registers, W_TEMP
and STATUS_TEMP are the temporary storage
locations for the W and STATUS registers values.
Example 8-1 does the following:
a) Stores the W register.
b) Stores the STATUS register in STATUS_TEMP.
c) Executes the Interrupt Service Routine code.
8.9.2
TMR0 INTERRUPT
d) Restores the STATUS (and bank select bit)
register.
An overflow (FFh → 00h) in TMR0 will set flag bit T0IF
(INTCON<2>). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON<5>)
(Section 6.0).
e) Restores the W register.
8.9.3
PORT RB INTERRUPT
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>)
(Section 5.2).
Note 1: If a change on an I/O pin should occur
when a read operation of PORTB is being
executed (start of the Q2 cycle), the RBIF
interrupt flag bit may not get set.
EXAMPLE 8-1: SAVING STATUS AND W REGISTERS IN RAM
PUSH
MOVWF
SWAPF
MOVWF
:
W_TEMP
STATUS, W
STATUS_TEMP
; Copy W to TEMP register,
; Swap status to be saved into W
; Save status to STATUS_TEMP register
:
ISR
:
; Interrupt Service Routine
:
:
;
;
should configure Bank as required
POP
SWAPF
STATUS_TEMP, W ; Swap nibbles in STATUS_TEMP register
; and place result into W
MOVWF
STATUS
; Move W into STATUS register
(sets bank to original state)
;
SWAPF
SWAPF
W_TEMP, F
W_TEMP, W
; Swap nibbles in W_TEMP and place result in W_TEMP
; Swap nibbles in W_TEMP and place result into W
DS30445C-page 46
1997 Microchip Technology Inc.
PIC16C84
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION_REG register. Thus, time-out
periods up to 2.3 seconds can be realized.
8.11
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC
oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins of the device has been
stopped, for example, by execution of a SLEEP
instruction. During normal operation a WDT time-out
generates a device RESET. If the device is in SLEEP
mode, a WDT Wake-up causes the device to wake-up
and continue with normal operation. The WDT can be
permanently disabled by programming configuration bit
WDTE as a '0' (Section 8.1).
The CLRWDTand SLEEPinstructions clear the WDT and
the postscaler (if assigned to the WDT) and prevent it
from timing out and generating
RESET condition.
a
device
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
8.11.2 WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
8.11.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
FIGURE 8-17: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-6)
0
M
U
X
Postscaler
8
1
WDT Timer
•
PS2:PS0
To TMR0 (Figure 6-6)
PSA
8 - to -1 MUX
PSA
WDT
Enable Bit
•
1
0
MUX
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 8-7
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Power-on
Reset
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
81h
Config. bits
—
—
—
CP
PWRTE
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
OPTION_
REG
1111 1111
1111 1111
RBPU
INTEDG
T0CS
T0SE
Legend: x= unknown. Shaded cells are not used by the WDT.
1997 Microchip Technology Inc.
DS30445C-page 47
PIC16C84
8.12.2 WAKE-UP FROM SLEEP
8.12
Power-down Mode (SLEEP)
The device can wake-up from SLEEP through one of
the following events:
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
1. External reset input on MCLR pin.
2. WDT Wake-up (if WDT was enabled).
8.12.1 SLEEP
The Power-down mode is entered by executing the
SLEEPinstruction.
3. Interrupt from RB0/INT pin, RB port change, or
data EEPROM write complete.
If enabled, the Watchdog Timer is cleared (but keeps
running), the PD bit (STATUS<3>) is cleared, the TO bit
(STATUS<4>) is set, and the oscillator driver is turned
off. The I/O ports maintain the status they had before
the SLEEPinstruction was executed (driving high, low,
or hi-impedance).
Peripherals cannot generate interrupts during SLEEP,
since no on-chip Q clocks are present.
The first event (MCLR reset) will cause a device reset.
The two latter events are considered a continuation of
program execution.The TO and PD bits can be used to
determine the cause of a device reset. The PD bit,
which is set on power-up, is cleared when SLEEP is
invoked. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up).
For the lowest current consumption in SLEEP mode,
place all I/O pins at either at VDD or VSS, with no
external circuitry drawing current from the I/O pins, and
disable external clocks. I/O pins that are hi-impedance
inputs should be pulled high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS. The
contribution from on-chip pull-ups on PORTB should be
considered.
While the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEPinstruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the
SLEEPinstruction.
The MCLR pin must be at a logic high level (VIHMC).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.
FIGURE 8-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
TOST(2)
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Inst(PC - 1)
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
DS30445C-page 48
1997 Microchip Technology Inc.
PIC16C84
8.12.3 WAKE-UP USING INTERRUPTS
8.15
In-Circuit Serial Programming
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
PIC16C84
microcontrollers
can
be
serially
programmed while in the end application circuit.This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. Customers can manufacture boards with
unprogrammed devices, and then program the
microcontroller just before shipping the product,
allowing the most recent firmware or custom firmware
to be programmed.
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP.Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, the device will imme-
diately wake up from sleep . The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR pin from VIL to VIHH (see PIC16C84 EEPROM
Memory Programming Specification (DS30189)). RB6
becomes the programming clock and RB7 becomes
the programming data. Both RB6 and RB7 are Schmitt
Trigger inputs in this mode.
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes.
To determine whether a SLEEP instruction executed,
test the PD bit. If the PD bit is set, the SLEEP instruc-
tion was executed as a NOP.
After reset, to place the device into programming/verify
mode, the program counter (PC) points to location 00h.
A 6-bit command is then supplied to the device, 14-bits
of program data is then supplied to or from the device,
using load or read-type instructions. For complete
details of serial programming, please refer to the In-Cir-
cuit Serial Programming Guide (DS30277).
To ensure that the WDT is cleared, a CLRWDT instruc-
tion should be executed before a SLEEP instruction.
For ROM devices, both the program memory and Data
EEPROM memory may be read, but only the Data
EEPROM memory may be programmed.
8.13
Program Verification/Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
FIGURE 8-19: TYPICAL IN-SYSTEM SERIAL
PROGRAMMING
CONNECTION
Note: Microchip does not recommend code pro-
tecting windowed devices..
To Normal
Connections
8.14
ID Locations
External
Connector
Signals
PIC16CXX
Four memory locations (2000h - 2003h) are designated
as ID locations to store checksum or other code
identification numbers. These locations are not
accessible during normal execution but are readable
and writable only during program/verify. Only the
4 least significant bits of ID location are usable.
+5V
0V
VDD
VSS
VPP
MCLR/VPP
RB6
RB7
CLK
For ROM devices, these values are submitted along
with the ROM code.
Data I/O
VDD
To Normal
Connections
1997 Microchip Technology Inc.
DS30445C-page 49
PIC16C84
NOTES:
DS30445C-page 50
1997 Microchip Technology Inc.
PIC16C84
The instruction set is highly orthogonal and is grouped
into three basic categories:
9.0
INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 9-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 9-1
shows the opcode field descriptions.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
For byte-oriented instructions, 'f' represents a file reg-
ister designator and 'd' represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
Table 9-2 lists the instructions recognized by the
MPASM assembler.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
Figure 9-1 shows the general formats that the instruc-
tions can have.
Note: To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTIONand TRISinstructions.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 9-1
OPCODE FIELD
DESCRIPTIONS
All examples use the following format to represent a
hexadecimal number:
0xhh
Field
Description
where h signifies a hexadecimal digit.
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Don't care location (= 0 or 1)
FIGURE 9-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
7
6
0
0
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
OPCODE
d
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
label
TOS
Label name
Top of Stack
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
PC
Program Counter
OPCODE
f (FILE #)
PCLATH
Program Counter High Latch
Global Interrupt Enable bit
Watchdog Timer/Counter
Time-out bit
b = 3-bit bit address
f = 7-bit file register address
GIE
WDT
TO
Literal and control operations
PD
Power-down bit
dest
Destination either the W register or the specified
register file location
General
13
8
7
0
0
[ ]
( )
→
Options
Contents
OPCODE
k (literal)
k = 8-bit immediate value
Assigned to
Register bit field
In the set of
< >
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
User defined term (font is courier)
italics
k (literal)
1998 Microchip Technology Inc.
DS30445C-page 51
PIC16C84
TABLE 9-2
PIC16CXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
LSb
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0xxx xxxx
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
DECFSZ
INCF
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
Move W to f
No Operation
-
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
Z
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
00 0000 0110 0100 TO,PD
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
Z
00 0000 0110 0011 TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS30445C-page 52
1998 Microchip Technology Inc.
PIC16C84
9.1
Instruction Descriptions
Add Literal and W
ANDLW
AND Literal with W
ADDLW
Syntax:
[label] ANDLW
k
Syntax:
[label] ADDLW
0 ≤ k ≤ 255
k
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
Operation:
Status Affected:
Encoding:
Description:
(W) .AND. (k) → (W)
(W) + k → (W)
C, DC, Z
Z
11
1001
kkkk
kkkk
11
111x
kkkk
kkkk
The contents of W register are
AND’ed with the eight bit literal 'k'.The
result is placed in the W register.
The contents of the W register are
added to the eight bit literal 'k' and the
result is placed in the W register.
Words:
1
1
Words:
1
1
Cycles:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal "k"
Process
data
Write to
W
Decode
Read
literal 'k'
Process
data
Write to
W
ANDLW
0x5F
ADDLW
0x15
Example
Example:
Before Instruction
Before Instruction
W
=
0xA3
0x03
W
=
0x10
0x25
After Instruction
After Instruction
W
=
W
=
ADDWF
Syntax:
Add W and f
ANDWF
Syntax:
AND W with f
[label] ADDWF f,d
[label] ANDWF f,d
Operands:
0 ≤ f ≤ 127
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) + (f) → (destination)
Operation:
(W) .AND. (f) → (destination)
Status Affected:
Encoding:
C, DC, Z
Status Affected:
Encoding:
Z
00
0111
dfff
ffff
00
0101
dfff
ffff
Add the contents of the W register with
register 'f'. If 'd' is 0 the result is stored
in the W register. If 'd' is 1 the result is
stored back in register 'f'.
AND the W register with register 'f'. If 'd'
is 0 the result is stored in the W regis-
ter. If 'd' is 1 the result is stored back in
register 'f'.
Description:
Description:
Words:
1
1
Words:
1
1
Cycles:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
Decode
Read
register
'f'
Process
data
Write to
destination
ADDWF
FSR,
0
ANDWF
FSR, 1
Example
Example
Before Instruction
Before Instruction
W
FSR =
=
0x17
0xC2
W
FSR =
=
0x17
0xC2
After Instruction
After Instruction
W
FSR =
=
0xD9
0xC2
W
FSR =
=
0x17
0x02
1998 Microchip Technology Inc.
DS30445C-page 53
PIC16C84
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
Operands:
[label] BCF f,b
Syntax:
[label] BTFSC f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
None
None
Status Affected:
Encoding:
01
00bb
bfff
ffff
01
10bb
bfff
ffff
If bit 'b' in register 'f' is '1' then the next
instruction is executed.
If bit 'b', in register 'f', is '0' then the next
instruction is discarded, and a NOP is
executed instead, making this a 2TCY
instruction.
Description:
Words:
Bit 'b' in register 'f' is cleared.
Description:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
Words:
1
Cycles:
1(2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
BCF
FLAG_REG, 7
Example
Decode
Read
register 'f'
Process No-Operat
data
Before Instruction
ion
FLAG_REG = 0xC7
If Skip:
(2nd Cycle)
Q1
After Instruction
FLAG_REG = 0x47
Q2
Q3
Q4
No-Operati No-Opera No-Operat
on tion ion
No-Operat
ion
HERE
FALSE
TRUE
BTFSC FLAG,1
Example
GOTO
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
BSF
Bit Set f
PC =
address TRUE
Syntax:
Operands:
[label] BSF f,b
if FLAG<1>=1,
PC =
address FALSE
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
1 → (f<b>)
None
01
01bb
bfff
ffff
Bit 'b' in register 'f' is set.
Description:
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
BSF
FLAG_REG,
7
Example
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS30445C-page 54
1998 Microchip Technology Inc.
PIC16C84
BTFSS
Bit Test f, Skip if Set
CALL
Call Subroutine
Syntax:
[label] BTFSS f,b
Syntax:
[ label ] CALL k
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
0 ≤ k ≤ 2047
(PC)+ 1→ TOS,
Operation:
skip if (f<b>) = 1
None
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected:
Encoding:
Status Affected:
Encoding:
None
01
11bb
bfff
ffff
10
0kkk
kkkk
kkkk
If bit 'b' in register 'f' is '0' then the next
instruction is executed.
If bit 'b' is '1', then the next instruction is
discarded and a NOP is executed
instead, making this a 2TCY instruction.
Description:
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH. CALL
is a two cycle instruction.
Description:
Words:
1
Cycles:
1(2)
Words:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Cycles:
Decode
Read
register 'f'
Process No-Operat
data
Q Cycle Activity:
1st Cycle
Q1
Q2
Q3
Q4
ion
Decode
Read
Process
data
Write to
PC
If Skip:
(2nd Cycle)
Q1
literal 'k',
Push PC
to Stack
Q2
Q3
Q4
No-Operati No-Opera No-Operat
on tion ion
No-Opera No-Opera No-Operat
2nd Cycle
Example
No-Operat
ion
No-Opera
tion
tion
tion
ion
HERE
FALSE
TRUE
BTFSC FLAG,1
Example
HERE
CALL
THERE
GOTO
PROCESS_CODE
Before Instruction
•
•
•
PC
= Address HERE
After Instruction
PC
= Address THERE
Before Instruction
TOS = Address HERE+1
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
1998 Microchip Technology Inc.
DS30445C-page 55
PIC16C84
CLRF
Clear f
CLRW
Clear W
Syntax:
[label] CLRF
0 ≤ f ≤ 127
f
Syntax:
[ label ] CLRW
None
Operands:
Operation:
Operands:
Operation:
00h → (f)
1 → Z
00h → (W)
1 → Z
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
0001
1fff
ffff
00
0001
0xxx
xxxx
The contents of register 'f' are cleared
and the Z bit is set.
Description:
W register is cleared. Zero bit (Z) is
set.
Description:
Words:
1
1
Words:
1
1
Cycles:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
Decode No-Opera Process
tion data
Write to
W
CLRW
Example
CLRF
FLAG_REG
Example
Before Instruction
Before Instruction
FLAG_REG
After Instruction
W
=
0x5A
=
0x5A
After Instruction
W
=
0x00
1
FLAG_REG
Z
=
=
0x00
1
Z
=
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
Operands:
Operation:
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected:
Encoding:
TO, PD
00
0000
0110
0100
CLRWDTinstruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD are
set.
Description:
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode No-Opera Process
Clear
WDT
tion
data
Counter
CLRWDT
Example
Before Instruction
WDT counter
After Instruction
=
=
?
WDT counter
0x00
WDT prescaler=
0
1
1
TO
PD
=
=
DS30445C-page 56
1998 Microchip Technology Inc.
PIC16C84
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 127
DECFSZ
Syntax:
Decrement f, Skip if 0
Syntax:
Operands:
[ label ] DECFSZ f,d
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(f) → (destination)
Operation:
(f) - 1 → (destination);
skip if result = 0
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
1001
dfff
ffff
00
1011
dfff
ffff
The contents of register 'f' are comple-
mented. If 'd' is 0 the result is stored in
W. If 'd' is 1 the result is stored back in
register 'f'.
Description:
The contents of register 'f' are decre-
mented. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
If the result is 1, the next instruction, is
executed. If the result is 0, then a NOP is
executed instead making it a 2TCY instruc-
tion.
Description:
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
Words:
1
Cycles:
1(2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
COMF
REG1,0
Example
Decode
Read
register 'f'
Process
data
Write to
destination
Before Instruction
REG1
After Instruction
REG1
=
0x13
If Skip:
(2nd Cycle)
Q1
Q2
Q3
Q4
=
=
0x13
0xEC
No-Opera No-Operat No-Operati
W
No-Operat
ion
tion
ion
on
DECF
Decrement f
[label] DECF f,d
0 ≤ f ≤ 127
Syntax:
Operands:
HERE
DECFSZ
GOTO
CNT, 1
LOOP
Example
CONTINUE •
d
[0,1]
•
•
Operation:
(f) - 1 → (destination)
Before Instruction
Status Affected:
Encoding:
Z
PC
=
address HERE
00
0011
dfff
ffff
After Instruction
CNT
if CNT =
PC
if CNT ≠
PC
=
CNT - 1
0,
address CONTINUE
0,
address HERE+1
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Description:
=
Words:
1
1
=
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
DECF
CNT, 1
Example
Before Instruction
CNT
=
0x01
Z
=
0
After Instruction
CNT
Z
=
=
0x00
1
1998 Microchip Technology Inc.
DS30445C-page 57
PIC16C84
INCF
Increment f
GOTO
Unconditional Branch
Syntax:
Operands:
[ label ] INCF f,d
Syntax:
[ label ] GOTO k
0 ≤ f ≤ 127
Operands:
Operation:
0 ≤ k ≤ 2047
d
[0,1]
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(f) + 1 → (destination)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
1010
dfff
ffff
10
1kkk
kkkk
kkkk
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
GOTOis an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTOis a two cycle instruction.
Description:
Words:
1
1
Words:
1
2
Cycles:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
1st Cycle
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
Decode
Read
literal 'k'
Process
data
Write to
PC
No-Operat No-Opera No-Operat
ion tion ion
2nd Cycle
No-Operat
ion
INCF
CNT, 1
Example
Before Instruction
GOTO THERE
Example
CNT
=
0xFF
Z
=
0
After Instruction
After Instruction
PC
=
Address THERE
CNT
Z
=
=
0x00
1
DS30445C-page 58
1998 Microchip Technology Inc.
PIC16C84
INCFSZ
Syntax:
Increment f, Skip if 0
[ label ] INCFSZ f,d
0 ≤ f ≤ 127
IORLW
Inclusive OR Literal with W
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
Operands:
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
(W) .OR. k → (W)
Z
Operation:
(f) + 1 → (destination),
skip if result = 0
11
1000
kkkk
kkkk
Status Affected:
Encoding:
None
The contents of the W register is
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
00
1111
dfff
ffff
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 1, the next instruction is
executed. If the result is 0, a NOP is exe-
cuted instead making it a 2TCY instruc-
tion.
Description:
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
W
Words:
1
Cycles:
1(2)
IORLW
0x35
Example
Q Cycle Activity:
Q1
Q2
Q3
Q4
Before Instruction
Decode
Read
register 'f'
Process
data
Write to
destination
W
=
0x9A
After Instruction
W
Z
=
=
0xBF
1
If Skip:
(2nd Cycle)
Q1
Q2
Q3
Q4
No-Opera No-Opera No-Operati
No-Operat
ion
tion
tion
on
HERE
INCFSZ
GOTO
CNT, 1
LOOP
Example
CONTINUE •
•
•
Before Instruction
PC
=
address HERE
After Instruction
CNT
=
CNT + 1
if CNT=
0,
PC
if CNT≠
=
address CONTINUE
0,
PC
=
address HERE +1
1998 Microchip Technology Inc.
DS30445C-page 59
PIC16C84
IORWF
Inclusive OR W with f
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
Syntax:
[ label ] IORWF f,d
Syntax:
Operands:
0 ≤ f ≤ 127
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
k → (W)
Operation:
(W) .OR. (f) → (destination)
None
Status Affected:
Encoding:
Z
11
00xx
kkkk
kkkk
00
0100
dfff
ffff
The eight bit literal 'k' is loaded into W
register.The don’t cares will assemble
as 0’s.
Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
Description:
Words:
1
1
Words:
1
1
Cycles:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
W
Decode
Read
register
'f'
Process
data
Write to
destination
MOVLW
0x5A
Example
After Instruction
IORWF
RESULT, 0
Example
W
=
0x5A
Before Instruction
RESULT =
0x13
0x91
W
=
After Instruction
RESULT =
0x13
0x93
1
W
Z
=
=
MOVWF
Move W to f
MOVF
Move f
Syntax:
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
f
Syntax:
Operands:
[ label ] MOVF f,d
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ f ≤ 127
d
[0,1]
None
Operation:
(f) → (destination)
00
0000
1fff
ffff
Status Affected:
Encoding:
Z
Move data from W register to register
'f'.
00
1000
dfff
ffff
The contents of register f is moved to a
destination dependant upon the status
of d. If d = 0, destination is W register. If
d = 1, the destination is file register f
itself. d = 1 is useful to test a file regis-
ter since status flag Z is affected.
Description:
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
Words:
1
1
Cycles:
MOVWF
OPTION_REG
Q Cycle Activity:
Q1
Q2
Q3
Q4
Example
Decode
Read
register
'f'
Process
data
Write to
destination
Before Instruction
OPTION =
0xFF
0x4F
W
=
After Instruction
MOVF
FSR, 0
Example
OPTION =
0x4F
0x4F
W
=
After Instruction
W = value in FSR register
Z
= 1
DS30445C-page 60
1998 Microchip Technology Inc.
PIC16C84
NOP
No Operation
[ label ] NOP
None
RETFIE
Return from Interrupt
Syntax:
Syntax:
[ label ] RETFIE
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Operands:
Operation:
No operation
None
TOS → PC,
1 → GIE
Status Affected:
Encoding:
None
00
0000
0xx0
0000
00
0000
0000
1001
No operation.
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in the
PC. Interrupts are enabled by setting
Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode No-Opera No-Opera No-Operat
tion
tion
ion
Words:
1
2
Cycles:
NOP
Example
Q Cycle Activity:
1st Cycle
Q1
Q2
Q3
Q4
Decode No-Opera Set the
tion GIE bit
Pop from
the Stack
No-Opera No-Opera No-Operat
tion tion ion
2nd Cycle
No-Operat
ion
RETFIE
Example
After Interrupt
PC
=
TOS
GIE =
1
OPTION
Syntax:
Load Option Register
[ label ] OPTION
None
Operands:
Operation:
(W) → OPTION
Status Affected: None
00
0000
0110
0010
Encoding:
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code com-
patibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Description:
Words:
Cycles:
Example
1
1
To maintain upward compatibility
with future PIC16CXX products,
do not use this instruction.
1998 Microchip Technology Inc.
DS30445C-page 61
PIC16C84
RETLW
Return with Literal in W
RETURN
Return from Subroutine
[ label ] RETURN
None
Syntax:
[ label ] RETLW k
Syntax:
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
Operation:
Status Affected:
Encoding:
Description:
k → (W);
TOS → PC
TOS → PC
None
Status Affected:
Encoding:
None
00
0000
0000
1000
11
01xx
kkkk
kkkk
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.This
is a two cycle instruction.
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
Description:
Words:
1
2
Cycles:
Words:
1
2
Q Cycle Activity:
1st Cycle
Q1
Q2
Q3
Q4
Cycles:
Decode No-Opera No-Opera Pop from
tion tion the Stack
Q Cycle Activity:
1st Cycle
Q1
Q2
Q3
Q4
Decode
Read
No-Opera WritetoW,
No-Opera No-Opera No-Opera
tion tion tion
2nd Cycle
literal 'k'
tion
Pop from
the Stack
No-Operat
ion
No-Opera No-Opera No-Operat
tion tion ion
2nd Cycle
No-Operat
ion
RETURN
Example
After Interrupt
PC
=
TOS
CALL TABLE ;W contains table
;offset value
•
•
Example
;W now has table value
•
TABLE
ADDWF PC
RETLW k1
RETLW k2
•
;W = offset
;Begin table
;
•
•
RETLW kn
; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
DS30445C-page 62
1998 Microchip Technology Inc.
PIC16C84
RLF
Rotate Left f through Carry
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 127
Syntax:
Operands:
[ label ]
RLF f,d
Syntax:
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
See description below
C
Operation:
See description below
C
Status Affected:
Encoding:
Status Affected:
Encoding:
00
1101
dfff
ffff
00
1100
dfff
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is stored
back in register 'f'.
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
Description:
Description:
C
Register f
C
Register f
Words:
1
1
Words:
1
1
Cycles:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
Decode
Read
register
'f'
Process
data
Write to
destination
RLF
REG1,0
Example
RRF
REG1,0
Example
Before Instruction
Before Instruction
REG1
C
=
=
1110 0110
0
REG1
C
=
=
1110 0110
0
After Instruction
After Instruction
REG1
W
C
=
=
=
1110 0110
1100 1100
1
REG1
W
C
=
=
=
1110 0110
0111 0011
0
1998 Microchip Technology Inc.
DS30445C-page 63
PIC16C84
SLEEP
SUBLW
Subtract W from Literal
Syntax:
[ label ]
SUBLW k
Syntax:
[ label ] SLEEP
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
Operation:
None
k - (W) → (W)
00h → WDT,
0 → WDT prescaler,
1 → TO,
Status Affected: C, DC, Z
Encoding:
11
110x
kkkk
kkkk
0 → PD
The W register is subtracted (2’s comple-
ment method) from the eight bit literal 'k'.
The result is placed in the W register.
Description:
Status Affected:
Encoding:
TO, PD
00
0000
0110
0011
Words:
1
1
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set.Watchdog Timer and its prescaler
are cleared.
Description:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
The processor is put into SLEEP
mode with the oscillator stopped. See
Section 14.8 for more details.
Decode
Read
literal 'k'
Process Write to W
data
Words:
1
1
Example 1:
SUBLW
0x02
Cycles:
Before Instruction
Q Cycle Activity:
Q1
Q2
Q3
Q4
W
C
Z
=
=
=
1
?
?
Decode No-Opera No-Opera
tion tion
Go to
Sleep
After Instruction
Example:
SLEEP
W
C
Z
=
=
=
1
1; result is positive
0
Example 2:
Before Instruction
W
C
Z
=
=
=
2
?
?
After Instruction
W
C
Z
=
=
=
0
1; result is zero
1
Example 3:
Before Instruction
W
C
Z
=
=
=
3
?
?
After Instruction
W
C
=
=
0xFF
0; result is nega-
tive
Z
=
0
DS30445C-page 64
1998 Microchip Technology Inc.
PIC16C84
SUBWF
Syntax:
Subtract W from f
SWAPF
Syntax:
Swap Nibbles in f
[ label ] SWAPF f,d
[ label ]
SUBWF f,d
Operands:
0 ≤ f ≤ 127
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Operation:
(f) - (W) → (destination)
Status Affected: C, DC, Z
Status Affected:
Encoding:
None
Encoding:
00
0010
dfff
ffff
00
1110
dfff
ffff
Subtract (2’s complement method) W reg-
ister from register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Description:
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in W register. If 'd' is 1 the result
is placed in register 'f'.
Description:
Words:
1
1
Words:
1
1
Cycles:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
Write to
destination
Decode
Read
register 'f'
Process
data
Write to
destination
Example 1:
SUBWF
REG1,1
SWAPF REG,
0
Example
Before Instruction
Before Instruction
REG1
REG1
=
=
=
=
3
W
C
Z
2
?
?
=
0xA5
After Instruction
REG1
W
=
=
0xA5
0x5A
After Instruction
REG1
=
1
2
W
C
Z
=
=
=
1; result is positive
0
Example 2:
Before Instruction
TRIS
Load TRIS Register
REG1
=
=
=
=
2
2
?
?
Syntax:
[label] TRIS
f
W
C
Z
Operands:
Operation:
5 ≤ f ≤ 7
(W) → TRIS register f;
Status Affected: None
After Instruction
00
Encoding:
0000 0110
0fff
REG1
=
0
W
C
Z
=
=
=
2
The instruction is supported for code
compatibility with the PIC16C5X prod-
ucts. Since TRIS registers are read-
able and writable, the user can directly
address them.
Description:
1; result is zero
1
Example 3:
Before Instruction
REG1
=
=
=
=
1
2
?
?
Words:
Cycles:
Example
1
1
W
C
Z
After Instruction
To maintain upward compatibility
with future PIC16CXX products,
do not use this instruction.
REG1
=
0xFF
2
0; result is negative
0
W
C
Z
=
=
=
1998 Microchip Technology Inc.
DS30445C-page 65
PIC16C84
XORLW
Exclusive OR Literal with W
[label] XORLW k
XORWF
Syntax:
Exclusive OR W with f
[label] XORWF f,d
0 ≤ f ≤ 127
Syntax:
Operands:
Operands:
Operation:
Status Affected:
Encoding:
0 ≤ k ≤ 255
d
[0,1]
(W) .XOR. k → (W)
Operation:
(W) .XOR. (f) → (destination)
Z
Status Affected:
Encoding:
Z
11
1010 kkkk kkkk
00
0110
dfff
ffff
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W regis-
ter.
Description:
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Description:
Words:
1
1
Words:
1
1
Cycles:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
Process Write to
literal 'k'
data
W
Decode
Read
register
'f'
Process
data
Write to
destination
Example:
XORLW
0xAF
Before Instruction
REG
1
Example
XORWF
W
=
0xB5
0x1A
Before Instruction
After Instruction
REG
W
=
=
0xAF
0xB5
W
=
After Instruction
REG
W
=
=
0x1A
0xB5
DS30445C-page 66
1998 Microchip Technology Inc.
PIC16C84
10.3
ICEPIC: Low-Cost PICmicro™
In-Circuit Emulator
10.0 DEVELOPMENT SUPPORT
10.1
Development Tools
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
families of 8-bit OTP microcontrollers.
The PICmicrο microcontrollers are supported with a
full range of hardware and software development tools:
• PICMASTER /PICMASTER CE Real-Time
In-Circuit Emulator
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
10.4
PRO MATE II: Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode.
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
• MPLAB SIM Software Simulator
• MPLAB-C (C Compiler)
• Fuzzy Logic Development System
(fuzzyTECH −MP)
gram
PIC12CXXX,
PIC14C000,
PIC16C5X,
10.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
10.5
PICSTART Plus Entry Level
Development System
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the SX, PIC14C000, PIC16C5X,
PIC16CXXX and PIC17CXX families. PICMASTER is
supplied with the MPLAB Integrated Development
Environment (IDE), which allows editing, “make” and
download, and source debugging from a single envi-
ronment.
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923 and PIC16C924 may be supported with an
adapter socket.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different proces-
sors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip micro-
controllers.
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these fea-
tures available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1997 Microchip Technology Inc.
DS30445A - page 67
PIC16C84
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
10.6
PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional pro-
totype area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
10.9
MPLAB™ Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
10.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
2
usage of the I C bus and separate headers for connec-
tion to an LCD module and a keypad.
10.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
10.10 Assembler (MPASM)
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
The MPASM Universal Macro Assembler is a PC-
hosted symbolic assembler. It supports all microcon-
troller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, condi-
tional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
MPASM allows full symbolic debugging from
PICMASTER, Microchip’s Universal Emulator System.
DS30445A - page 68
1997 Microchip Technology Inc.
PIC16C84
MPASM has the following features to assist in develop-
ing software for specific use applications.
10.14 MP-DriveWay – Application Code
Generator
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
MP-DriveWay is an easy-to-use Windows-based Appli-
cation Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PICmicro
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Micro-
chip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PICmicro. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
10.15 SEEVAL Evaluation and
Programming System
10.11 Software Simulator (MPLAB-SIM)
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PICmicro series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break, or
in a trace mode.
10.16 KEELOQ Evaluation and
Programming Tools
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code out-
side of the laboratory environment making it an excel-
lent multi-project software development tool.
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products.The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
10.12 C Compiler (MPLAB-C)
The MPLAB-C Code Development System is a
complete ‘C’ compiler and integrated development
environment for Microchip’s PICmicro™ family of
microcontrollers. The compiler provides powerful inte-
gration capabilities and ease of use not found with
other compilers.
For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
MPLAB IDE memory display.
10.13 Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, edition for imple-
menting more complex systems.
Both versions include Microchip’s fuzzyLAB demon-
stration board for hands-on experience with fuzzy logic
systems implementation.
1997 Microchip Technology Inc.
DS30445A - page 69
PIC16C84
TABLE 10-1: DEVELOPMENT TOOLS FROM MICROCHIP
ufzy
D e m o B o a r d s
E m u l a t o r P r o d u c t s
S o f t w a r e T o o l s
P r o g r a m m e r s
DS30445A - page 70
1997 Microchip Technology Inc.
PIC16C84
11.0 ELECTRICAL CHARACTERISTICS FOR PIC16C84
Absolute Maximum Ratings †
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
(2)
Voltage on MCLR with respect to VSS ...................................................................................................... -0.3 to +14V
Voltage on all other pins with respect to VSS ..................................................................................-0.6V to (VDD + 0.6V)
(1)
Total power dissipation .....................................................................................................................................800 mW
Maximum current out of VSS pin ...........................................................................................................................150 mA
Maximum current into VDD pin ..............................................................................................................................100 mA
Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA
Output clamp current, IOK (VO < 0 or VO >VDD)..............................................................................................................± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................20 mA
Maximum current sunk by PORTA ..........................................................................................................................80 mA
Maximum current sourced by PORTA.....................................................................................................................50 mA
Maximum current sunk by PORTB........................................................................................................................150 mA
Maximum current sourced by PORTB...................................................................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1997 Microchip Technology Inc.
DS30445C-page 71
PIC16C84
TABLE 11-1
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
OSC
PIC16C84-04
PIC16C84-10
VDD: 4.5V to 5.5V
IDD: 1.8 mA typ. at 5.5V
PIC16LC84-04
VDD: 2.0V to 6.0V
IDD: 4.5 mA max. at 5.5V
IPD: 100 µA max. at 4V WDT dis
Freq: 2.0 MHz max.
RC
XT
HS
VDD: 4.0V to 6.0V
IDD: 4.5 mA max. at 5.5V
IPD: 100 µA max. at 4.0V WDT dis IPD: 40.0 µA typ. at 4.5V WDT dis
Freq: 4.0 MHz max.
Freq: 4.0 MHz max.
VDD: 4.0V to 6.0V
IDD: 4.5 mA max. at 5.5V
IPD: 100 µA max. at 4.0V WDT dis IPD: 40.0 µA typ. at 4.5V WDT dis
Freq: 4.0 MHz max.
VDD: 4.5V to 5.5V
IDD: 1.8 mA typ. at 5.5V
VDD: 2.0V to 6.0V
IDD: 4.5 mA max. at 5.5V
IPD: 100 µA max. at 4V WDT dis
Freq: 2.0 MHz max.
Freq: 4.0 MHz max.
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
Do not use in HS mode
IDD: 4.5 mA typ. at 5.5V
IPD: 40.0 µA typ. at 4.5V WDT dis
Freq: 4.0 MHz max.
IDD: 10 mA max. at 5.5V typ.
IPD: 40.0 µA typ. at 4.5V WDT dis
Freq: 10 MHz max.
LP
VDD: 4.0V to 6.0V
Do not use in LP mode
VDD: 2.0V to 6.0V
IDD: 60 µA typ. at 32 kHz, 2.0V
IPD: 26 µA typ. at 2.0V WDT dis
Freq: 200 kHz max.
IDD: 400 µA max. at 32 kHz, 2.0V
IPD: 100 µA max. at 4.0V WDT dis
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is
recommended that the user select the device type that ensures the specifications required.
DS30445C-page 72
1997 Microchip Technology Inc.
PIC16C84
11.1
DC CHARACTERISTICS: PIC16C84-04 (Commercial, Industrial)
PIC16C84-10 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C (commercial)
-40°C ≤ TA ≤ +85°C (industrial)
DC Characteristics
Power Supply Pins
Parame-
ter No.
Sym
Characteristic
Min Typ† Max Units
Conditions
D001
D001A
VDD Supply Voltage
4.0
4.5
—
—
6.0
5.5
V
V
XT, RC and LP osc configuration
HS osc configuration
D002
D003
VDR RAM Data Retention
1.5*
—
—
V
Device in SLEEP mode
(1)
Voltage
VPOR VDD start voltage to
ensure internal
—
VSS
—
V
See section on Power-on Reset for details
Power-on Reset signal
D004
SVDD VDD rise rate to ensure 0.05*
internal Power-on
—
—
V/ms See section on Power-on Reset for details
Reset signal
(2)
(4)
IDD
IPD
Supply Current
RC and XT osc configuration
D010
D010A
—
—
1.8 4.5 mA
FOSC = 4 MHz, VDD = 5.5V
FOSC = 4 MHz, VDD = 5.5V
(During EEPROM programming)
HS osc configuration (PIC16C84-10)
FOSC = 10 MHz, VDD = 5.5V
7.3
10
mA
D013
—
5.0
10
mA
(3)
D020
D021
D021A
Power-down Current
—
—
—
40 100 µA VDD = 4.0V, WDT enabled, industrial
38 100 µA VDD = 4.0V, WDT disabled, commercial
38 100 µA VDD = 4.0V, WDT disabled, industrial
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
1997 Microchip Technology Inc.
DS30445C-page 73
PIC16C84
11.2
DC CHARACTERISTICS PIC16LC84-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
DC Characteristics
Power Supply Pins
Operating temperature
0°C ≤ TA ≤ +70°C (commercial)
-40°C ≤ TA ≤ +85°C (industrial)
Parameter Sym
No.
Characteristic
Min Typ† Max Units
Conditions
D001
D002
VDD Supply Voltage
2.0
—
—
6.0
—
V
V
XT, RC, and LP osc configuration
Device in SLEEP mode
VDR RAM Data Retention
1.5 *
(1)
Voltage
D003
D004
VPOR VDD start voltage to
ensure internal
—
VSS
—
—
—
V
See section on Power-on Reset for details
Power-on Reset signal
SVDD VDD rise rate to ensure 0.05*
internal Power-on
V/ms See section on Power-on Reset for details
Reset signal
(2)
(4)
IDD
Supply Current
RC and XT osc configuration
D010
D010A
—
—
1
7.3
4
10
mA
mA
FOSC = 2 MHz, VDD = 5.5V
FOSC = 2 MHz, VDD = 5.5V
(During EEPROM programming)
LP osc configuration
D014
—
60 400
µA
FOSC = 32 kHz, VDD = 2.0V,
WDT disabled
(3)
D020
D021
D021A
IPD
Power-down Current
—
—
—
26 100
26 100
26 100
µA VDD = 2.0V, WDT enabled, industrial
µA VDD = 2.0V, WDT disabled, commercial
µA VDD = 2.0V, WDT disabled, industrial
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
DS30445C-page 74
1997 Microchip Technology Inc.
PIC16C84
11.3
DC CHARACTERISTICS: PIC16C84-04 (Commercial, Industrial)
PIC16C84-10 (Commercial, Industrial)
PIC16LC84-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C (commercial)
-40°C ≤ TA ≤ +85°C (industrial)
DC Characteristics
All Pins Except
Power Supply Pins
Operating voltage VDD range as described in DC spec
Section 11-1 and Section 11.2.
Parameter
Sym
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
Min Typ† Max Units
Conditions
No.
VIL
D030
VSS
VSS
VSS
Vss
—
0.8
V
V
V
V
4.5 ≤ VDD ≤ 5.5V
(4)
D030A
D031
D032
— 0.16VDD
—
—
entire range
entire range
with Schmitt Trigger buffer
MCLR, RA4/T0CKI, OSC1
(RC mode)
OSC1 (XT, HS and LP modes)
Input High Voltage
I/O ports
0.2VDD
0.2VDD
(1)
D033
Vss
—
0.3VDD
V
VIH
D040
D040A
D041
D042
with TTL buffer
0.36VDD
0.48VDD
0.45VDD
0.85VDD
—
VDD
V
4.5 ≤ VDD ≤ 5.5V
entire range
entire range
(4)
with Schmitt Trigger buffer
MCLR, RA4/T0CKI, OSC1
(RC mode)
—
—
VDD
VDD
V
V
(1)
D043
D070
OSC1 (XT, HS and LP modes)
0.7VDD
50*
—
VDD
IPURB PORTB weak pull-up current
250* 400*
µA VDD = 5V, VPIN = VSS
(2,3)
Input Leakage Current
D060
IIL
I/O ports
—
—
±1
µA Vss ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061
D063
MCLR, RA4/T0CKI
OSC1/CLKIN
—
—
—
—
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
Output Low Voltage
I/O ports
OSC2/CLKOUT
(RC osc configuration)
D080
D083
VOL
—
—
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V
Output High Voltage
(3)
D090
D093
VOH I/O ports
VDD - 0.7 —
VDD - 0.7 —
—
—
V
V
IOH = -3.0 mA, VDD = 4.5V
IOH = -1.3 mA, VDD = 4.5V
OSC2/CLKOUT
(RC osc configuration)
These parameters are characterized but not tested.
*
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C84 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: The user may use better of the two specs.
1997 Microchip Technology Inc.
DS30445C-page 75
PIC16C84
11.4
DC CHARACTERISTICS: PIC16C84-04 (Commercial, Industrial)
PIC16C84-10 (Commercial, Industrial)
PIC16LC84-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C (commercial)
-40°C ≤ TA ≤ +85°C (industrial)
DC Characteristics
All Pins Except
Power Supply Pins
Operating voltage VDD range as described in DC spec Section 11-1
and Section 11.2.
Parameter Sym
No.
Characteristic
Min
Typ†
Max Units
Conditions
Capacitive Loading Specs
on Output Pins
D100
D101
COSC2 OSC2/CLKOUT pin
—
—
—
—
15
50
pF In XT, HS and LP modes when
external clock is used to drive
OSC1.
CIO
All I/O pins and OSC2
(RC mode)
pF
Data EEPROM Memory
—
D120
D121
ED
Endurance
1M
VMIN
10M
—
E/W 25°C at 5V
VDRW VDD for read/write
6.0
V
VMIN = Minimum operating
voltage
(1)
D122
TDEW Erase/Write cycle time
—
10
20*
ms
Program EEPROM Memory
Endurance
VDD for read
D130
D131
EP
VPR
100
VMIN
1000
—
—
6.0
E/W
V
VMIN = Minimum operating
voltage
D132
D133
VPEW VDD for erase/write
TPEW Erase/Write cycle time
4.5
—
—
10
5.5
—
V
ms
(1)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: The user should use interrupts or poll the EEIF or WR bits to ensure the write cycle has completed.
DS30445C-page 76
1997 Microchip Technology Inc.
PIC16C84
TABLE 11-2
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase symbols (pp) and their meanings:
pp
T
Time
2
to
os,osc
ost
OSC1
ck
CLKOUT
cycle time
I/O port
INT pin
MCLR
oscillator start-up timer
power-up timer
RBx pins
cy
io
pwrt
rbt
inp
mc
t0
T0CKI
wdt
watchdog timer
Uppercase symbols and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 11-1: PARAMETER MEASUREMENT INFORMATION
0.7 VDD XTAL
0.8 VDD RC
(High)
2.0 VDD (High)
0.2 VDD (Low)
0.3 VDD XTAL
0.15 VDD RC
(Low)
OSC1 Measurement Points
I/O Port Measurement Points
All timings are measured between high and low measurement points as indicated in the figure.
FIGURE 11-2: LOAD CONDITIONS
Load Condition 1
VDD/2
Load Condition 2
CL
RL
CL
Pin
VSS
Pin
VSS
RL =
CL =
464Ω
50 pF
15 pF
for all pins except OSC2.
for OSC2 output.
1997 Microchip Technology Inc.
DS30445C-page 77
PIC16C84
11.5
Timing Diagrams and Specifications
FIGURE 11-3: EXTERNAL CLOCK TIMING
Q4
Q3
Q4
Q1
Q1
Q2
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 11-3
EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units Conditions
(1)
FOSC External CLKIN Frequency
DC
DC
DC
DC
—
—
—
—
2
4
MHz XT, RC osc PIC16LC84-04
MHz XT, RC osc PIC16C84-04
10
200
MHz HS osc
kHz LP osc
PIC16C84-10
PIC16LC84-04
(1)
Oscillator Frequency
DC
DC
0.1
0.1
1
—
—
—
—
—
—
2
4
MHz RC osc
MHz RC osc
MHz XT osc
MHz XT osc
MHz HS osc
kHz LP osc
PIC16LC84-04
PIC16C84-04
PIC16LC84-04
PIC16C84-04
PIC16C84-10
PIC16LC84-04
2
4
10
200
DC
(1)
1
Tosc External CLKIN Period
500
250
100
5
—
—
—
—
—
—
—
—
ns
ns
ns
µs
XT, RC osc PIC16LC84-04
XT, RC osc PIC16C84-04
HS osc
LP osc
PIC16C84-10
PIC16LC84-04
(1)
Oscillator Period
500
250
—
—
—
—
ns
ns
RC osc
RC osc
PIC16LC84-04
PIC16C84-04
500
250
100
5
—
—
—
—
10,000
10,000
1,000
—
ns
ns
ns
µs
XT osc
XT osc
HS osc
LP osc
PIC16LC84-04
PIC16C84-04
PIC16C84-10
PIC16LC84-04
(1)
2
3
TCY
Instruction Cycle Time
0.4
60 *
50 *
2 *
4/Fosc
—
DC
—
—
—
—
—
—
—
µs
ns
ns
µs
ns
ns
ns
ns
TosL, Clock in (OSC1) High or Low
TosH Time
XT osc
XT osc
LP osc
HS osc
XT osc
LP osc
HS osc
PIC16LC84-04
PIC16C84-04
PIC16LC84-04
PIC16C84-10
PIC16C84-04
PIC16LC84-04
PIC16C84-10
—
—
35 *
—
4
TosR, Clock in (OSC1) Rise or Fall Time 25 *
—
TosF
50 *
15 *
—
—
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5.0V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30445C-page 78
1997 Microchip Technology Inc.
PIC16C84
FIGURE 11-4: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
22
23
CLKOUT
12
16
13
18
14
19
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: All tests must be done with specified capacitive loads (Figure 11-2) 50 pF on I/O pins and CLKOUT.
TABLE 11-4
CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
10
TosH2ckL
OSC1↑ to CLKOUT↓
PIC16C84
—
15
30 *
ns
Note 1
10A
11
PIC16LC84
PIC16C84
PIC16LC84
PIC16C84
PIC16LC84
PIC16C84
PIC16LC84
—
15
15
15
15
15
15
15
—
—
—
—
—
—
—
120 *
30 *
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
TosH2ckH OSC1↑ to CLKOUT↑
—
11A
12
—
120 *
30 *
TckR
TckF
CLKOUT rise time
CLKOUT fall time
—
12A
13
—
100 *
30 *
—
13A
14
—
100 *
0.5TCY +20 *
—
TckL2ioV
TioV2ckH
CLKOUT ↓ to Port out valid
—
15
Port in valid before
PIC16C84
PIC16LC84
0.30TCY + 30 *
CLKOUT ↑
0.30TCY + 80 *
—
16
17
TckH2ioI
TosH2ioV
Port in hold after CLKOUT ↑
0 *
—
—
OSC1↑ (Q1 cycle) to
PIC16C84
PIC16LC84
125 *
250 *
—
Port out valid
—
18
19
TosH2ioI
TioV2osH
TioR
OSC1↑ (Q2 cycle) to Port input invalid
TBD
(I/O in hold time)
Port input valid to OSC1↑
TBD
—
—
ns
(I/O in setup time)
20
20A
21
Port output rise time
Port output fall time
PIC16C84
PIC16LC84
PIC16C84
PIC16LC84
PIC16C84
PIC16LC84
—
—
10
10
10
10
—
—
—
—
25 *
60 *
25 *
60 *
—
ns
ns
ns
ns
ns
ns
ns
ns
TioF
Tinp
Trbp
—
21A
22
—
INT pin high
or low time
20 *
55 *
20 *
55 *
22A
23
—
RB7:RB4 change INT PIC16C84
high or low time PIC16LC84
—
23A
—
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5.0V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
1997 Microchip Technology Inc.
DS30445C-page 79
PIC16C84
FIGURE 11-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
TABLE 11-5
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
350 *
150 *
—
—
—
—
ns 2.0V ≤ VDD ≤ 3.0V
ns 3.0V ≤ VDD ≤ 6.0V
Twdt
Tost
Watchdog Timer Time-out Period
(No Prescaler)
7 *
18
33 *
ms VDD = 5V
32
33
Oscillation Start-up Timer Period
—
1024TOSC
72
—
ms TOSC = OSC1 period
ms VDD = 5.0V
Tpwrt Power-up Timer Period
I/O Hi-impedance from MCLR Low
or reset
These parameters are characterized but not tested.
28 *
132 *
34
TIOZ
—
—
100 *
ns
*
†
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30445C-page 80
1997 Microchip Technology Inc.
PIC16C84
FIGURE 11-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
40
41
42
TABLE 11-6
TIMER0 CLOCK REQUIREMENTS
Parameter Sym Characteristic
No.
Min
Typ† Max Units Conditions
40
Tt0H T0CKI High Pulse Width
Tt0L T0CKI Low Pulse Width
Tt0P T0CKI Period
No Prescaler
0.5TCY + 20 *
—
—
ns
With Prescaler
50 *
30 *
—
—
—
—
ns 2.0V ≤ VDD ≤ 3.0V
ns 3.0V ≤ VDD ≤ 6.0V
41
42
No Prescaler
0.5TCY + 20 *
—
—
ns
With Prescaler
50 *
20 *
—
—
—
—
ns 2.0V ≤ VDD ≤ 3.0V
ns 3.0V ≤ VDD ≤ 6.0V
TCY + 40 *
N
—
—
ns N = prescale value
(2, 4, ..., 256)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1997 Microchip Technology Inc.
DS30445C-page 81
PIC16C84
NOTES:
DS30445C-page 82
1997 Microchip Technology Inc.
PIC16C84
12.0 DC & AC CHARACTERISTICS GRAPHS/TABLES FOR PIC16C84
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are guaranteed to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. 'Typical' represents the mean of the distribution at 25°C, while 'max' or 'min' represents
(mean + 3σ) and (mean - 3σ) respectively, where σ is standard deviation.
FIGURE 12-1: TYPICAL RC OSCILLATOR FREQUENCY vs.TEMPERATURE
FOSC
Frequency Normalized To +25°C
FOSC (25°C)
1.10
Rext ≥ 10 kΩ
Cext = 100 pF
1.08
1.06
1.04
1.02
1.00
VDD = 5.5V
0.98
0.96
0.94
VDD = 3.5V
0.92
0.90
0.88
0
10
20
25
30
40
50
60
70
T(°C)
TABLE 12-1
RC OSCILLATOR FREQUENCIES *
Rext
Average
Fosc @ 5V, 25°C
Cext
20 pF
3.3k
5.1k
10k
4.68 MHz
3.94 MHz
2.34 MHz
250.16 kHz
1.49 MHz
1.12 MHz
620.31 kHz
90.25 kHz
524.24 kHz
415.52 kHz
270.33 kHz
25.37 kHz
± 27%
± 25%
± 29%
± 33%
± 25%
± 25%
± 30%
± 26%
± 28%
± 30%
± 26%
± 25%
100k
3.3k
5.1k
10k
100 pF
300 pF
100k
3.3k
5.1k
10k
100k
*Measured in PDIP Packages.The percentage variation indicated here is part to part variation due to normal process
distribution. The variation indicated is ±3 standard deviation from average value.
1997 Microchip Technology Inc.
DS30445C-page 83
PIC16C84
FIGURE 12-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD (Cext = 20 pF)
5.5
5.0
Rext = 3.3k
4.5
4.0
Rext = 5k
3.5
3.0
T = 25°C
2.5
2.0
Rext = 10k
1.5
1.0
Rext = 100k
0.5
0.0
2.0
2.5
3.0
3.5 4.0
4.5
5.0
5.5 6.0
VDD (Volts)
DS30445C-page 84
1997 Microchip Technology Inc.
PIC16C84
FIGURE 12-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD (Cext = 100 pF)
2.2
2.0
1.8
1.6
Rext = 3.3k
Rext = 5k
1.4
1.2
1.0
0.8
0.6
0.4
Rext = 10k
T = 25°C
Rext = 100k
0.2
0.0
2.0
2.5
3.0
3.5 4.0
VDD (Volts)
4.5
5.0
5.5 6.0
FIGURE 12-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD (Cext = 300 pF)
1.1
1.0
0.9
0.8
T = 25°C
0.7
Rext = 3.3k
0.6
0.5
Rext = 5k
0.4
0.3
Rext = 10k
0.2
0.1
Rext = 100k
0.0
2.0
2.5
3.0
3.5 4.0
4.5
5.0
5.5 6.0
VDD (Volts)
1997 Microchip Technology Inc.
DS30445C-page 85
PIC16C84
FIGURE 12-5: TYPICAL IPD vs. VDD WATCHDOG DISABLED (25˚C)
60
50
40
30
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 12-6: TYPICAL IPD vs. VDD WATCHDOG ENABLED (25˚C)
60
50
40
30
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30445C-page 86
1997 Microchip Technology Inc.
PIC16C84
FIGURE 12-7: MAXIMUM IPD vs. VDD WATCHDOG DISABLED
120
100
80
60
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 12-8: MAXIMUM IPD vs. VDD WATCHDOG ENABLED*
120
100
80
60
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
* IPD, with Watchdog Timer enabled, has two components:The leakage current which increases with higher temperature
and the operating current of the Watchdog Timer logic which increases with lower temperature. At -40°C, the latter
dominates explaining the apparently anomalous behavior.
1997 Microchip Technology Inc.
DS30445C-page 87
PIC16C84
FIGURE 12-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD
2.0
1.8
Max (-40°C to +85°C)
1.6
Typ @ 25°C
1.4
1.2
1.0
Min (-40°C to +85°C)
0.8
0.6
2.5
3.0
3.5
4.0
VDD (Volts)
4.5
5.0
5.5
6.0
FIGURE 12-10: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES)
vs. VDD
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30445C-page 88
1997 Microchip Technology Inc.
PIC16C84
FIGURE 12-11: VIH, VIL OF MCLR,T0CKI and OSC1 (IN RC MODE) vs. VDD
5.0
VIH, max (-40°C to +85°C)
4.5
VIH, typ (25°C)
4.0
VIH, min (-40°C to +85°C)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIL, max (-40°C to +85°C)
VIL, typ (25°C)
VIL, min (-40°C to +85°C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
1997 Microchip Technology Inc.
DS30445C-page 89
PIC16C84
FIGURE 12-12: TYPICAL IDD vs. FREQ (EXT CLOCK, 25˚C)
10,000
1,000
100 6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
10
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
FIGURE 12-13: MAXIMUM IDD vs. FREQ (EXT CLOCK, -40˚ TO +85˚C)
10,000
1,000
6.0V
5.5V
5.0V
4.5V
4.0V
100
3.5V
3.0V
2.5V
2.0V
10
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
DS30445C-page 90
1997 Microchip Technology Inc.
PIC16C84
FIGURE 12-14: WDT TIME-OUT PERIOD vs. VDD
70
60
Max. 85°C
50
Max. 70°C
40
Typ. 25°C
30
Min. 0°C
20
10
0
Min. -40°C
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 12-15: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR vs. VDD
10000
9000
8000
7000
6000
5000
Max @ -40°C
4000
3000
Typ @ 25°C
Min @ 85°C
2000
1000
0
2.0
3.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
1997 Microchip Technology Inc.
DS30445C-page 91
PIC16C84
FIGURE 12-16: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR vs. VDD
250
225
200
175
Typ @ 25°C
Max @ -40°C
150
125
100
75
Min @ 85°C
50
25
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
FIGURE 12-17: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD
2000
1800
1600
Max @ -40°C
1400
1200
1000
800
Typ @ 25°C
Min @ 85°C
600
400
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
DS30445C-page 92
1997 Microchip Technology Inc.
PIC16C84
FIGURE 12-18: IOH vs. VOH, VDD = 3V
0
-2
-4
-6
Min @ 85°C
-8
-10
-12
Typ @ 25°C
-14
-16
Max @ -40°C
-18
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOH (Volts)
FIGURE 12-19: IOH vs. VOH, VDD = 5V
0
-5
-10
-15
-20
Min @ 85°C
Max @ -40°C
-25
Typ @ 25°C
-30
-35
-40
-45
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOH (Volts)
1997 Microchip Technology Inc.
DS30445C-page 93
PIC16C84
FIGURE 12-20: IOL vs. VOL, VDD = 3V
35
Max. -40°C
30
25
20
Typ. 25°C
Min. +85°C
15
10
5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
FIGURE 12-21: IOL vs. VOL, VDD = 5V
90
80
70
60
50
40
30
Max @ -40°C
Typ @ 25°C
Min @ +85°C
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
DS30445C-page 94
1997 Microchip Technology Inc.
PIC16C84
FIGURE 12-22: MAXIMUM DATA MEMORY ERASE/WRITE CYCLE TIME VS. VDD
20
18
16
14
12
10
8
6
4
2
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
Shaded areas are beyond recommended range.
TABLE 12-2
INPUT CAPACITANCE*
Typical Capacitance (pF)
Pin Name
18L PDIP
18L SOIC
PORTA
PORTB
5.0
5.0
4.3
4.3
MCLR
17.0
4.0
4.3
3.2
17.0
3.5
3.5
2.8
OSC1/CLKIN
OSC2/CLKOUT
T0CKI
* All capacitance values are typical at 25°C. A part to part variation of ±25% (three standard deviations) should
be taken into account.
1997 Microchip Technology Inc.
DS30445C-page 95
PIC16C84
NOTES:
DS30445C-page 96
1997 Microchip Technology Inc.
PIC16C84
13.0 PACKAGING INFORMATION
13.1
K04-007 18-Lead Plastic Dual In-line (P) – 300 mil
E
D
2
α
n
1
E1
A1
L
A
R
c
A2
B1
β
p
B
eB
Units
INCHES*
NOM
0.300
18
MILLIMETERS
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
MIN
MAX
MIN
NOM
7.62
18
MAX
n
p
B
B1
R
c
0.100
0.018
0.060
0.005
0.010
0.155
0.095
0.020
0.130
0.895
0.255
0.250
0.349
10
2.54
0.013
0.023
0.33
1.40
0.46
1.52
0.13
0.25
3.94
2.41
0.51
3.30
22.73
6.48
6.35
8.85
10
0.58
†
0.055
0.000
0.005
0.110
0.075
0.000
0.125
0.890
0.245
0.230
0.310
5
0.065
0.010
0.015
0.155
0.115
0.020
0.135
0.900
0.265
0.270
0.387
15
1.65
0.25
0.38
3.94
2.92
0.51
3.43
22.86
6.73
6.86
9.83
15
0.00
0.13
2.79
1.91
0.00
3.18
22.61
6.22
5.84
7.87
5
Top to Seating Plane
Top of Lead to Seating Plane A1
A
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
A2
L
‡
D
‡
E
E1
eB
α
β
5
10
15
5
10
15
* Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed
0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall
not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
1997 Microchip Technology Inc.
DS30445C-page 97
PIC16C84
13.2
K04-051 18-Lead Plastic Small Outline (SO) – Wide, 300 mil
E1
E
p
D
2
1
B
n
X
α
45°
L
R2
c
A
A1
R1
φ
β
L1
A2
Units
Dimension Limits
Pitch
INCHES*
NOM
0.050
18
MILLIMETERS
MIN
MAX
MIN
NOM
1.27
18
MAX
p
n
A
A1
A2
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Chamfer Distance
Shoulder Radius
Gull Wing Radius
Foot Length
0.093
0.099
0.058
0.008
0.456
0.296
0.407
0.020
0.005
0.005
0.016
4
0.104
2.36
1.22
2.50
1.47
0.19
11.58
7.51
10.33
0.50
0.13
0.13
0.41
4
2.64
1.73
0.28
11.73
7.59
10.64
0.74
0.25
0.25
0.53
8
0.048
0.004
0.450
0.292
0.394
0.010
0.005
0.005
0.011
0
0.068
0.011
0.462
0.299
0.419
0.029
0.010
0.010
0.021
8
0.10
11.43
7.42
10.01
0.25
0.13
0.13
0.28
0
‡
D
E
‡
E1
X
R1
R2
L
Foot Angle
φ
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
*
L1
c
B
α
β
0.010
0.009
0.014
0
0.015
0.011
0.017
12
0.020
0.012
0.019
15
0.25
0.23
0.36
0
0.38
0.27
0.42
12
0.51
0.30
0.48
15
†
0
12
15
0
12
15
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS30445C-page 98
1997 Microchip Technology Inc.
PIC16C84
APPENDIX A: FEATURE
IMPROVEMENTS -
FROM PIC16C5X TO
PIC16C84
The following is the list of feature improvements over
the PIC16C5X microcontroller family:
APPENDIX B: CODE COMPATIBILITY
- FROM PIC16C5X TO
PIC16C84
To convert code written for PIC16C5X to PIC16C84,
the user should take the following steps:
1. Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
1. Instruction word length is increased to 14 bits.
This allows larger page sizes both in program
memory (2K now as opposed to 512 before) and
the register file (128 bytes now versus 32 bytes
before).
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
3. Eliminate any data memory page switching.
Redefine data variables for reallocation.
2. A PC latch register (PCLATH) is added to handle
program memory paging. PA2, PA1 and PA0 bits
are removed from the status register and placed
in the option register.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
5. Change reset vector to 0000h.
3. Data memory paging is redefined slightly. The
STATUS register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW. Two
instructions, TRIS and OPTION, are being
phased out although they are kept for
compatibility with PIC16C5X.
5. OPTION and TRIS registers are made
addressable.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. Reset vector is changed to 0000h.
9. Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized.
Registers are reset differently.
10. Wake up from SLEEP through interrupt is
added.
11. Two separate timers, the Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT), are
included for more reliable power-up. These
timers are invoked selectively to avoid
unnecessary delays on power-up and wake-up.
12. PORTB has weak pull-ups and interrupt on
change features.
13. T0CKI pin is also a port pin (RA4/T0CKI).
14. FSR is a full 8-bit register.
15. "In system programming" is made possible. The
user can program PIC16CXX devices using only
five pins: VDD, VSS, VPP, RB6 (clock) and RB7
(data in/out).
1997 Microchip Technology Inc.
DS30445C-page 99
PIC16C84
APPENDIX C: WHAT’S NEW IN THIS
DATA SHEET
APPENDIX D: WHAT’S CHANGED IN
THIS DATA SHEET
No new information has been added to this data sheet.
Here’s what’s changed in this data sheet:
For information on upgrade devices from the
PIC16C84, please refer to the PIC16F8X data sheet.
1. Some sections have been rearranged for clarity
and consistency.
2. Errata information has been included.
DS30445C-page 100
1997 Microchip Technology Inc.
PIC16C84
APPENDIX E: CONVERSION CONSIDERATIONS - PIC16C84 TO PIC16F83/F84 AND
PIC16CR83/CR84
Considerations for converting from the PIC16C84 to
the PIC16F84 are listed in the table below. These con-
siderations apply to converting from the PIC16C84 to
the PIC16F83 (same as PIC16F84 except for program
and data RAM memory sizes) and the PIC16CR84 and
PIC16CR83 (ROM versions of Flash devices). Devel-
opment Systems support is available for all of the
PIC16X8X devices.
Difference
PIC16C84
PIC16F84
The polarity of the PWRTE bit has
been reversed. Ensure that the pro-
grammer has this bit correctly set
before programming.
PWRTE
PWRTE
The PIC16F84 (and PIC16CR84)
have larger RAM sizes. Ensure that
this does not cause an issue with
your program.
RAM = 36 bytes
RAM = 68 bytes
The MCLR pin now has an on-chip
filter. The input signal on the MCLR
pin will require a longer low pulse to
generate an interrupt.
MCLR pulse width (low)
= 350ns; 2.0V ≤ VDD ≤ 3.0V
= 150ns; 3.0V ≤ VDD ≤ 6.0V
MCLR pulse width (low)
= 1000ns; 2.0V ≤ VDD ≤ 6.0V
Some electrical specifications have
been improved (see IPD example).
Compare the electrical specifica-
tions of the two devices to ensure
that this will not cause a compatibil-
ity issue.
IPD (typ @ 2V) = 26µA
IPD (typ @ 2V) < 1µA
IPD (max @ 4V, WDT disabled)
=100µA (PIC16C84)
=100µA (PIC16LC84)
IPD (max @ 4V, WDT disabled)
=14µA (PIC16F84)
=7µA (PIC16LF84)
PORTA and crystal oscillator values
less than 500kHz
For crystal oscillator configurations
operating below 500kHz, the device
may generate a spurious internal Q-
clock when PORTA<0> switches
state.
N/A
RB0/INT pin
TTL
TTL/ST*
(* This buffer is a Schmitt Trigger
input when configured as the exter-
nal interrupt.)
EEADR<7:6> and IDD
It is recommended that the
N/A
EEADR<7:6> bits be cleared.
When either of these bits is set, the
maximum IDD for the device is
higher than when both are cleared.
Code Protect
1 CP bit
9 CP bits
Recommended value of REXT for
RC oscillator circuits
REXT = 3kΩ - 100kΩ
REXT = 5kΩ - 100kΩ
GIE bit unintentional enable
If an interrupt occurs while the Glo-
bal Interrupt Enable (GIE) bit is
being cleared, the GIE bit may unin-
tentionally be re-enabled by the
user’s Interrupt Service Routine (the
RETFIEinstruction).
N/A
1997 Microchip Technology Inc.
DS30445C-page 101
PIC16C84
NOTES:
DS30445C-page 102
1997 Microchip Technology Inc.
PIC16C84
CLRWDT ................................................................... 56
COMF ........................................................................ 57
DECF ......................................................................... 57
DECFSZ .................................................................... 57
GOTO ........................................................................ 58
INCF .......................................................................... 58
INCFSZ ...................................................................... 59
IORLW ....................................................................... 59
IORWF ....................................................................... 60
MOVF ........................................................................ 60
MOVLW ..................................................................... 60
MOVWF ..................................................................... 60
NOP ........................................................................... 61
OPTION ..................................................................... 61
RETFIE ...................................................................... 61
RETLW ...................................................................... 62
RETURN .................................................................... 62
RLF ............................................................................ 63
RRF ........................................................................... 63
SLEEP ....................................................................... 64
SUBLW ...................................................................... 64
SUBWF ...................................................................... 65
SWAPF ...................................................................... 65
TRIS .......................................................................... 65
XORLW ..................................................................... 66
XORWF ..................................................................... 66
Section ....................................................................... 51
Summary Table ......................................................... 52
INT Interrupt ...................................................................... 46
INTCON ........................................................... 16, 39, 44, 46
INTEDG ............................................................................. 46
Interrupts
INDEX
A
Absolute Maximum Ratings ............................................... 71
ALU ...................................................................................... 7
Architectural Overview ......................................................... 7
Assembler
MPASM Assembler .................................................... 68
B
Block Diagram
Interrupt Logic ............................................................ 45
On-Chip Reset Circuit ................................................ 38
RA3:RA0 and RA5 Port Pins ..................................... 19
RA4 Pin ...................................................................... 19
RB3:RB0 Port Pins .................................................... 21
RB7:RB4 Port Pins .................................................... 21
TMR0/WDT Prescaler ................................................ 28
Watchdog Timer ......................................................... 47
Brown-out Protection Circuit .............................................. 43
C
Carry .................................................................................... 7
CLKIN .................................................................................. 9
CLKOUT .............................................................................. 9
Code Protection ........................................................... 35, 49
Compatibility, upward ........................................................... 3
Computed GOTO ............................................................... 17
Configuration Bits ............................................................... 35
D
DC Characteristics ........................................... 73, 74, 75, 76
Development Support ........................................................ 67
Development Tools ............................................................ 67
Digit Carry ............................................................................ 7
Flag ............................................................................ 44
Interrupt on Change Feature ..................................... 21
Interrupts ............................................................. 35, 44
E
K
External Power-on Reset Circuit ........................................ 40
KeeLoq Evaluation and Programming Tools .................. 69
F
L
Family of Devices
Loading of PC .................................................................... 17
PIC16C8X .................................................................... 4
FSR .............................................................................. 18, 39
Fuzzy Logic Dev. System (fuzzyTECH -MP) ................... 69
M
MCLR ...................................................................... 9, 38, 39
Memory Organization
G
Data Memory ............................................................. 12
Memory Organization ................................................ 11
Program Memory ....................................................... 11
MP-DriveWay™ - Application Code Generator ................. 69
MPLAB C ........................................................................... 69
MPLAB Integrated Development Environment Software ... 68
GIE ..................................................................................... 44
I
I/O Ports ............................................................................. 19
I/O Programming Considerations ....................................... 23
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 67
In-Circuit Serial Programming ...................................... 35, 49
INDF ................................................................................... 39
Instruction Format .............................................................. 51
Instruction Set
O
OPCODE ........................................................................... 51
OPTION_REG ....................................................... 15, 39, 46
OSC selection .................................................................... 35
OSC1 ....................................................................................9
OSC2 ....................................................................................9
Oscillator
HS ........................................................................ 36, 43
LP ........................................................................ 36, 43
RC ....................................................................... 36, 37
XT ........................................................................ 36, 43
Oscillator Configurations ................................................... 36
ADDLW ...................................................................... 53
ADDWF ...................................................................... 53
ANDLW ...................................................................... 53
ANDWF ...................................................................... 53
BCF ............................................................................ 54
BSF ............................................................................ 54
BTFSC ....................................................................... 54
BTFSS ....................................................................... 55
CALL .......................................................................... 55
CLRF .......................................................................... 56
CLRW ........................................................................ 56
P
Paging, Program Memory .................................................. 17
1997 Microchip Technology Inc.
DS30445C-page 103
PIC16C84
PCL ..............................................................................17, 39
PCLATH .......................................................................17, 39
PD ..........................................................................14, 38, 43
PICDEM-1 Low-Cost PICmicro Demo Board .....................68
PICDEM-2 Low-Cost PIC16CXX Demo Board ..................68
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................68
PICMASTER In-Circuit Emulator .....................................67
PICSTART Plus Entry Level Development System ........67
Pinout Descriptions ..............................................................9
POR ...................................................................................40
Oscillator Start-up Timer (OST) ...........................35, 40
Power-on Reset (POR) ..................................35, 39, 40
Power-up Timer (PWRT) .....................................35, 40
Time-out Sequence ....................................................43
Time-out Sequence on Power-up ..............................41
TO ..................................................................14, 38, 43
Port RB Interrupt ................................................................46
PORTA .....................................................................9, 19, 39
PORTB .....................................................................9, 21, 39
Power-down Mode (SLEEP) ..............................................48
Prescaler ............................................................................27
PRO MATE II Universal Programmer ..............................67
Product Identification System ...........................................107
Z
Zero bit ................................................................................. 7
R
RBIF bit ........................................................................21, 46
RC Oscillator ......................................................................43
Read-Modify-Write .............................................................23
Register File .......................................................................12
Reset ............................................................................35, 38
Reset on Brown-Out ...........................................................43
S
Saving W Register and STATUS in RAM ..........................46
SEEVAL Evaluation and Programming System ..............69
SLEEP ....................................................................35, 38, 48
Software Simulator (MPLAB-SIM) ......................................69
Special Features of the CPU ..............................................35
Special Function Registers ................................................12
Stack ..................................................................................17
Overflows ...................................................................17
Underflows .................................................................17
STATUS ...................................................................7, 14, 39
T
time-out ..............................................................................39
Timer0
Switching Prescaler Assignment ................................29
T0IF ............................................................................46
Timer0 Module ...........................................................25
TMR0 Interrupt ...........................................................46
TMR0 with External Clock ..........................................27
Timing Diagrams
Time-out Sequence ....................................................41
Timing Diagrams and Specifications ..................................78
TRISA .................................................................................19
TRISB ...........................................................................21, 39
W
W ........................................................................................39
Wake-up from SLEEP ..................................................39, 48
Watchdog Timer (WDT) ...................................35, 38, 39, 47
WDT ...................................................................................39
Period .........................................................................47
Programming Considerations ....................................47
Time-out .....................................................................39
DS30445C-page 104
1997 Microchip Technology Inc.
PIC16C84
The procedure to connect will vary slightly from country
to country. Please check with your local CompuServe
agent for details if you have a problem. CompuServe
service allow multiple users various baud rates
depending on the local point of access.
ON-LINE SUPPORT
Microchip provides two methods of on-line support.
These are the Microchip BBS and the Microchip World
Wide Web (WWW) site.
Use Microchip's Bulletin Board Service (BBS) to get
current information and help about Microchip products.
Microchip provides the BBS communication channel
for you to use in extending your technical staff with
microcontroller and memory experts.
The following connect procedure applies in most loca-
tions.
1. Set your modem to 8-bit, No parity, and One stop
(8N1). This is not the normal CompuServe setting
which is 7E1.
To provide you with the most responsive service possible,
the Microchip systems team monitors the BBS, posts
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provides technical help and embedded systems
insights, and discusses how Microchip products pro-
vide project solutions.
2. Dial your local CompuServe access number.
3. Depress the <Enter> key and a garbage string will
appear because CompuServe is expecting a 7E1
setting.
4. Type +, depress the <Enter> key and “Host Name:”
will appear.
The web site, like the BBS, is used by Microchip as a
means to make files and information easily available to
customers.To view the site, the user must have access
to the Internet and a web browser, such as Netscape or
Microsoft Explorer. Files are also available for FTP
download from our FTP site.
5. Type MCHIPBBS, depress the <Enter> key and you
will be connected to the Microchip BBS.
In the United States, to find the CompuServe phone
number closest to you, set your modem to 7E1 and dial
(800) 848-4480 for 300-2400 baud or (800) 331-7166
for 9600-14400 baud connection. After the system
responds with “Host Name:”, type NETWORK, depress
the <Enter> key and follow CompuServe's directions.
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
For voice information (or calling from overseas), you
may call (614) 723-1550 for your local CompuServe
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The file transfer site is available by using an FTP ser-
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Microchip regularly uses the Microchip BBS to distribute
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ftp.mchip.com/biz/mchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
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ety of Microchip specific business information is also
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The Systems Information and Upgrade Line provides
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Plus, this line provides information on how customers
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1-800-755-2345 for U.S. and most of Canada, and
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Connecting to the Microchip BBS
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER, PRO MATE and are registered trademarks
of Microchip Technology Incorporated in the U.S.A. and
other countries. PICmicro, FlexROM, MPLAB, and fuzzy-
LAB, are trademarks and SQTP is a service mark of
Microchip in the U.S.A.
Connect worldwide to the Microchip BBS using either
the Internet or the CompuServe communications net-
work.
Internet:
You can telnet or ftp to the Microchip BBS at the
address:
fuzzyTECH is a registered trademark of Inform Software
Corporation. IBM, IBM PC-AT are registered trademarks of
International Business Machines Corp. Pentium is a trade-
mark of Intel Corporation. Windows is a trademark and
MS-DOS, Microsoft Windows are registered trademarks
of Microsoft Corporation. CompuServe is a registered
trademark of CompuServe Incorporated.
mchipbbs.microchip.com
CompuServe Communications Network:
When using the BBS via the Compuserve Network,
in most cases, a local call is your only expense. The
Microchip BBS connection does not use CompuServe
membership services, therefore you do not need
CompuServe membership to join Microchip's BBS.
There is no charge for connecting to the Microchip BBS.
All other trademarks mentioned herein are the property of
their respective companies.
1997 Microchip Technology Inc.
Preliminary
DS30445C-page 105
PIC16C84
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product.
If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can
better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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RE:
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Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
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Device:
PIC16C84
Literature Number:
DS30445C
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
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7. How would you improve this document?
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DS30445C-page 106
Preliminary
1997 Microchip Technology Inc.
PIC16C84
PIC16C84 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
-XX
Examples:
Frequency Temperature Package
Range Range
Pattern
a) PIC16C84 -04/P 301 = Commercial
temp., PDIP package, 4MHz, normalVDD
limitis, QTP pattern #301.
(2)
(3)
Device
PIC16C84 , PIC16C84T
PIC16LC84 , PIC16LC84T
b) PIC16LC84 - 04I/SO = Industrial temp.,
SOIC package, 200kHz, Extended VDD
limits.
(2)
(3)
Frequency
Range
04
10
= 4 MHz
= 10 MHz
(1)
Temperature
Range
b
I
=
0°C to +70°C (Commercial)
= -40°C to +85°C (Industrial)
Note 1: b = blank
2:
C
= Standard VDD range
Package
P
SO
= PDIP
LC = Extended VDD range
= SOIC (Gull Wing, 300 mil body)
3: T = in tape and reel - SOIC, SSOP
packages only.
Pattern
3-digit Pattern Code for QTP, ROM (blank otherwise)
SALES AND SUPPORT
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see last page)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Development Tools
For the latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
The latest version of Development Tools software can be downloaded from either our Bulletin Board or Worldwide Web Site. (Infor-
mation on how to connect to our BBS or WWW site can be found in the On-Line Support section of this data sheet.)
1997 Microchip Technology Inc.
DS30445C-page 107
PIC16C84
DS30445C-page 108
1997 Microchip Technology Inc.
®
Note the following details of the code protection feature on PICmicro MCUs.
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
M
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2002 Microchip Technology Inc.
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