PIC12F509T [MICROCHIP]
8/14-Pin, 8-Bit Flash Microcontrollers; 8月14日引脚， 8位闪存微控制器
| 型号： | PIC12F509T |
| 厂家： | 
MICROCHIP |
| 描述： | 8/14-Pin, 8-Bit Flash Microcontrollers |
| 文件： | 总98页 (文件大小：1227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC12F508/509/16F505
Data Sheet
8/14-Pin, 8-Bit Flash Microcontrollers
*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U. S. and
foreign patents and applications may be issued or pending.
2004 Microchip Technology Inc.
Preliminary
DS41236A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41236A-page ii
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
8/14-Pin, 8-Bit Flash Microcontroller
- LP:
- EC:
Power-saving, low-frequency crystal
Devices Included In This Data Sheet:
High-speed external clock input
(PIC16F505 only)
• PIC12F508
• PIC12F509
• PIC16F505
Low-Power Features/CMOS Technology:
• Operating Current:
High-Performance RISC CPU:
- < 350 µA @ 2V, 4 MHz
• Standby Current:
• Only 33 single-word instructions to learn
• All single-cycle instructions except for program
branches, which are two-cycle
- 100 nA @ 2V, typical
• Low-power, high-speed Flash technology:
- 100,000 Flash endurance
- > 40 year retention
• 12-bit wide instructions
• 2-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
for data and instructions
• Fully static design
• Wide operating voltage range: 2.0V to 5.5V
• Wide temperature range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
• 8-bit wide data path
• 8 Special Function Hardware registers
• Operating speed:
- DC – 20 MHz clock input (PIC16F505 only)
- DC – 200 ns instruction cycle (PIC16F505
only)
Peripheral Features (PIC12F508/509):
- DC – 4 MHz clock input
• 6 I/O pins:
- DC – 1000 ns instruction cycle
- 5 I/O pins with individual direction control
- 1 input only pin
Special Microcontroller Features:
- High current sink/source for direct LED drive
- Wake-on-change
• 4 MHz precision internal oscillator:
- Factory calibrated to ±1%
- Weak pull-ups
• 8-bit real-time clock/counter (TMR0) with 8-bit
programmable prescaler
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Debugging (ICD) support
• Power-on Reset (POR)
Peripheral Features (PIC16F505):
• Device Reset Timer (DRT)
• 12 I/O pins:
• Watchdog Timer (WDT) with dedicated on-chip
RC oscillator for reliable operation
- 11 I/O pins with individual direction control
- 1 input only pin
• Programmable code protection
• Multiplexed MCLR input pin
- High current sink/source for direct LED drive
- Wake-on-change
• Internal weak pull-ups on I/O pins
• Power-saving Sleep mode
- Weak pull-ups
• Wake-up from Sleep on pin change
• Selectable oscillator options:
• 8-bit real-time clock/counter (TMR0) with 8-bit
programmable prescaler
- INTRC: 4 MHz precision Internal oscillator
- EXTRC: External low-cost RC oscillator
- XT:
- HS:
Standard crystal/resonator
High-speed crystal/resonator
(PIC16F505 only)
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 1
PIC12F508/509/16F505
Pin Diagrams
PDIP, SOIC, TSSOP
PDIP, SOIC, MSOP
14
13
12
VDD
RB5/OSC1/CLKIN
RB4/OSC2/CLKOUT
VSS
1
2
3
8
7
6
5
VDD
GP5/OSC1/CLKIN
GP4/OSC2
VSS
1
2
3
4
RB0/ICSPDAT
RB1/ISCPCLK
GP0/ICSPDAT
GP1/ICSPCLK
GP2/T0CKI
RB3/MCLR/VPP
RC5/T0CKI
4
5
11
10
RB2
RC0
GP3/MCLR/VPP
6
7
9
8
RC4
RC3
RC1
RC2
Program Memory
Flash (words)
Data Memory
SRAM (bytes)
Timers
8-bit
Device
I/O
PIC12F508
PIC12F509
PIC16F505
512
1024
1024
25
41
72
6
6
1
1
1
12
DS41236A-page 2
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC12F508/509/16F505 Device Varieties ................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization................................................................................................................................................................. 15
5.0 I/O Port....................................................................................................................................................................................... 29
6.0 Timer0 Module and TMR0 Register ........................................................................................................................................... 33
7.0 Special Features Of The CPU.................................................................................................................................................... 39
8.0 Instruction Set Summary............................................................................................................................................................ 55
9.0 Development Support................................................................................................................................................................. 63
10.0 Electrical Characteristics............................................................................................................................................................ 69
11.0 DC and AC Characteristics Graphs and Charts......................................................................................................................... 81
12.0 Packaging Information................................................................................................................................................................ 83
Index .................................................................................................................................................................................................... 91
On-Line Support................................................................................................................................................................................... 93
Systems Information and Upgrade Hot Line ........................................................................................................................................ 93
Reader Response................................................................................................................................................................................ 94
Product Identification System .............................................................................................................................................................. 95
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Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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Microchip’s Worldwide Web site; http://www.microchip.com
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When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-
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2004 Microchip Technology Inc.
Preliminary
DS41236A-page 3
PIC12F508/509/16F505
NOTES:
DS41236A-page 4
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
1.1
Applications
1.0
GENERAL DESCRIPTION
The PIC12F508/509/16F505 devices fit in applications
ranging from personal care appliances and security
systems to low-power remote transmitters/receivers.
The Flash technology makes customizing application
programs (transmitter codes, appliance settings,
receiver frequencies, etc.) extremely fast and conve-
nient. The small footprint packages, for through hole or
surface mounting, make these microcontrollers perfect
for applications with space limitations. Low cost, low
power, high performance, ease of use and I/O flexibility
make the PIC12F508/509/16F505 devices very versa-
tile even in areas where no microcontroller use has
been considered before (e.g., timer functions, logic and
PLDs in larger systems and coprocessor applications).
The PIC12F508/509/16F505 devices from Microchip
Technology are low-cost, high-performance, 8-bit, fully-
static, Flash-based CMOS microcontrollers. They
employ a RISC architecture with only 33 single word/
single cycle instructions. All instructions are single
cycle (200 µs) except for program branches, which
take two cycles. The PIC12F508/509/16F505 devices
deliver performance an order of magnitude higher than
their competitors in the same price category. The 12-bit
wide instructions are highly symmetrical, resulting in a
typical 2:1 code compression over other 8-bit
microcontrollers in its class. The easy to use and easy
to remember instruction set reduces development time
significantly.
The PIC12F508/509/16F505 products are equipped
with special features that reduce system cost and
power requirements. The Power-on Reset (POR) and
Device Reset Timer (DRT) eliminate the need for
external Reset circuitry. There are four oscillator config-
urations to choose from (six on the PIC16F505), includ-
ing INTRC Internal Oscillator mode and the power-
saving LP (Low-power) Oscillator mode. Power-saving
Sleep mode, Watchdog Timer and code protection
features improve system cost, power and reliability.
The PIC12F508/509/16F505 devices are available in
the cost-effective Flash programmable version, which
is suitable for production in any volume. The customer
can take full advantage of Microchip’s price leadership
in Flash programmable microcontrollers, while
benefiting from the Flash programmable flexibility.
The PIC12F508/509/16F505 products are supported
by a full-featured macro assembler, a software simula-
tor, an in-circuit emulator, a ‘C’ compiler, a low-cost
development programmer and a full featured program-
mer. All the tools are supported on IBM® PC and
compatible machines.
TABLE 1-1:
PIC12F508/509/16F505 DEVICES
PIC12F508
PIC12F509
PIC16F505
Clock
Maximum Frequency of Operation (MHz)
Flash Program Memory
Data Memory (bytes)
Timer Module(s)
4
512
25
4
1024
41
20
1024
72
Memory
Peripherals
Features
TMR0
Yes
5
TMR0
Yes
5
TMR0
Yes
11
Wake-up from Sleep on Pin Change
I/O Pins
Input Pins
1
1
1
Internal Pull-ups
Yes
Yes
33
Yes
Yes
33
Yes
Yes
33
In-Circuit Serial Programming
Number of Instructions
Packages
8-pin PDIP, SOIC,
MSOP
8-pin PDIP, SOIC,
MSOP
14-pin PDIP, SOIC,
TSSOP
The PIC12F508/509/16F505 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current
capability and precision internal oscillator.
The PIC12F508/509/16F505 device uses serial programming with data pin RB0/GP0 and clock pin RB1/GP1.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 5
PIC12F508/509/16F505
NOTES:
DS41236A-page 6
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
2.2
Serialized Quick Turn
ProgrammingSM (SQTPSM) Devices
2.0
PIC12F508/509/16F505 DEVICE
VARIETIES
Microchip offers a unique programming service, where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
A variety of packaging options are available. Depend-
ing on application and production requirements, the
proper device option can be selected using the
information in this section. When placing orders, please
use the PIC12F508/509/16F505 Product Identification
System at the back of this data sheet to specify the
correct part number.
Serial programming allows each device to have a
unique number, which can serve as an entry code,
password or ID number.
2.1
Quick Turn Programming (QTP)
Devices
Microchip offers a QTP programming service for
factory production orders. This service is made
available for users who choose not to program
medium-to-high quantity units and whose code
patterns have stabilized. The devices are identical to
the Flash devices but with all Flash locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please
contact your local Microchip Technology sales office for
more details.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 7
PIC12F508/509/16F505
NOTES:
DS41236A-page 8
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
The PIC12F508/509/16F505 devices contain an 8-bit
ALU and working register. The ALU is a general
purpose arithmetic unit. It performs arithmetic and
Boolean functions between data in the working register
and any register file.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC12F508/509/16F505
devices can be attributed to a number of architectural
features commonly found in RISC microprocessors.
To begin with, the PIC12F508/509/16F505 devices
use a Harvard architecture in which program and data
are accessed on separate buses. This improves
bandwidth over traditional von Neumann architec-
tures where program and data are fetched on the
same bus. Separating program and data memory fur-
ther allows instructions to be sized differently than the
8-bit wide data word. Instruction opcodes are 12 bits
wide, making it possible to have all single-word
instructions. A 12-bit wide program memory access
bus fetches a 12-bit instruction in a single cycle. A
two-stage pipeline overlaps fetch and execution of
instructions. Consequently, all instructions (33)
execute in a single cycle (200 ns @ 20 MHz, 1 µs @
4 MHz) except for program branches.
The ALU is 8 bits wide and capable of addition, subtrac-
tion, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two’s comple-
ment in nature. In two-operand instructions, one
operand is typically the W (working) register. The other
operand is either a file register or an immediate
constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC) and
Zero (Z) bits in the Status register. The C and DC bits
operate as a borrow and digit borrow out bit, respec-
tively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
The Table below lists program memory (Flash) and
data memory (RAM) for the PIC12F508/509/16F505
devices.
A simplified block diagram is shown in Figure 3-2, with
the corresponding device pins described in Table 3-3.
TABLE 3-1:
PIC12F508/509/16F505
MEMORY
Memory
Device
Program
Data
PIC12F508
PIC12F509
PIC16F505
512 x 12
1024 x 12
1024 x 12
25 x 8
41 x 8
72 x 8
The PIC12F508/509/16F505 devices can directly or
indirectly address its register files and data memory. All
Special Function Registers (SFR), including the PC,
are mapped in the data memory. The PIC12F508/509/
16F505 devices have a highly orthogonal (symmetri-
cal) instruction set that makes it possible to carry out
any operation, on any register, using any addressing
mode. This symmetrical nature and lack of “special
optimal situations” make programming with the
PIC12F508/509/16F505 devices simple, yet efficient.
In addition, the learning curve is reduced significantly.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 9
PIC12F508/509/16F505
FIGURE 3-1:
PIC12F508/509 BLOCK DIAGRAM
12
8
GPIO
Data Bus
Program Counter
Flash
GP0/ISCPDAT
GP1/ISCPCLK
GP2/T0CKI
GP3/MCLR/VPP
GP4/OSC2
512 x 12 or
1024 x 12
RAM
Program
Memory
25 x 8 or
Stack 1
Stack 2
File
Registers
GP5/OSC1/CLKIN
Program
Bus
12
RAM Addr
9
Addr MUX
Instruction reg
Indirect
Addr
5
Direct Addr
5-7
FSR reg
Status reg
8
3
MUX
Device Reset
Timer
Instruction
Decode &
Control
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
OSC1/CLKIN
OSC2
W reg
Internal RC
OSC
Timer0
MCLR
VDD, VSS
DS41236A-page 10
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
TABLE 3-2:
Name
PIC12F508/509 PINOUT DESCRIPTION
Input Output
Function
Description
Type
Type
GP0/ICSPDAT
GP0
TTL
CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
ICSPDAT
GP1
ST
CMOS In-Circuit Serial Programming™ data pin.
GP1\ICSPCLK
TTL
CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
ICSPCLK
GP2
ST
TTL
ST
CMOS In-Circuit Serial Programming clock pin.
CMOS Bidirectional I/O pin.
GP2/T0CKI
T0CKI
GP3
—
—
Clock input to TMR0.
GP3/MCLR/VPP
TTL
Input pin. Can be software programmed for internal weak
pull-up and wake-up from Sleep on pin change.
MCLR
ST
—
Master Clear (Reset). When configured as MCLR, this pin is
an active-low Reset to the device. Voltage on MCLR/VPP must
not exceed VDD during normal device operation or the device
will enter Programming mode. Weak pull-up always on if
configured as MCLR.
VPP
GP4
HV
TTL
—
—
Programming voltage input.
GP4/OSC2
CMOS Bidirectional I/O pin.
OSC2
XTAL Oscillator crystal output. Connections to crystal or resonator in
Crystal Oscillator mode (XT and LP modes only, GPIO in other
modes).
GP5/OSC1/CLKIN
GP5
OSC1
CLKIN
VDD
TTL
XTAL
ST
CMOS Bidirectional I/O pin.
—
—
P
Oscillator crystal input.
External clock source input .
VDD
VSS
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
VSS
—
P
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,
ST = Schmitt Trigger input
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 11
PIC12F508/509/16F505
FIGURE 3-2:
PIC16F505 BLOCK DIAGRAM
12
8
PORTB
Data Bus
RAM
Program Counter
Flash
RB0/ICSPCLK
RB1/ICSPDAT
RB2
1K x 12
Program
Stack 1
Memory
RB3/MCLR/VPP
RB4/OSC2/CLKOUT
RB5/OSC1/CLKIN
File
Stack 2
Registers
Program
Bus
12
RAM Addr
9
PORTC
Addr MUX
Instruction reg
RC0
RC1
RC2
Indirect
Addr
5
Direct Addr
5-7
RC3
RC4
FSR reg
RC5/T0CKI
Status reg
8
3
MUX
Device Reset
Timer
Power-on
Reset
ALU
Instruction
Decode &
Control
8
Watchdog
Timer
W reg
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Internal RC
OSC
Timer0
MCLR
VDD, VSS
DS41236A-page 12
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
TABLE 3-3:
Name
PIC16F505 PINOUT DESCRIPTION
Input Output
Function
Description
Type
Type
RB0/ICSPDAT
RB0
TTL
CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
ICSPDAT
RB1
ST
CMOS In-Circuit Serial Programming™ data pin.
RB1/ICSPCLK
TTL
CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
ICSPCLK
RB2
ST
CMOS In-Circuit Serial Programming clock pin.
CMOS Bidirectional I/O pin.
RB2
TTL
TTL
RB3/MCLR/VPP
RB3
—
Input port. Can be software programmed for internal weak
pull-up and wake-up from Sleep on pin change.
MCLR
ST
—
Master Clear (Reset). When configured as MCLR, this pin is
an active-low Reset to the device. Voltage on MCLR/VPP must
not exceed VDD during normal device operation or the device
will enter Programming mode. Weak pull-up always on if
configured as MCLR.
VPP
—
—
Programming voltage input.
RB4/OSC2/CLKOUT
RB4
TTL
CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
OSC2
—
—
XTAL Oscillator crystal output. Connections to crystal or resonator in
Crystal Oscillator mode (XT, HS and LP modes only).
CLKOUT
CMOS In EXTRC and INTRC modes, the pin output can be
configured for CLKOUT, which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate.
RB5/OSC1/CLKIN
RB5
OSC1
CLKIN
RC0
TTL
XTAL
ST
CMOS Bidirectional I/O pin.
—
—
Crystal input.
External clock source input.
RC0
TTL
TTL
TTL
TTL
TTL
TTL
ST
CMOS Bidirectional I/O pin.
CMOS Bidirectional I/O pin.
CMOS Bidirectional I/O pin.
CMOS Bidirectional I/O pin.
CMOS Bidirectional I/O pin.
CMOS Bidirectional I/O pin.
RC1
RC1
RC2
RC2
RC3
RC3
RC4
RC4
RC5/T0CKI
RC5
T0CKI
VDD
—
P
Clock input to TMR0.
VDD
VSS
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
VSS
—
P
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,
ST = Schmitt Trigger input
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 13
PIC12F508/509/16F505
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO), then two cycles
are required to complete the instruction (Example 3-1).
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC
is incremented every Q1 and the instruction is fetched
from program memory and latched into the instruction
register in Q4. It is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-3 and Example 3-1.
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-3:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
PC
Internal
phase
clock
PC
PC+1
PC+2
Fetch INST (PC)
Execute INST (PC – 1)
Fetch INST (PC + 1)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 1)
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
1. MOVLW 03H
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTB, BIT1
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
DS41236A-page 14
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F508/509
4.0
MEMORY ORGANIZATION
The PIC12F508/509/16F505 memories are organized
into program memory and data memory. For devices
with more than 512 bytes of program memory, a paging
scheme is used. Program memory pages are accessed
using one Status register bit. For the PIC12F509 and
PIC16F505, with data memory register files of more
than 32 registers, a banking scheme is used. Data
memory banks are accessed using the File Select
Register (FSR).
PC<11:0>
12
CALL, RETLW
Stack Level 1
Stack Level 2
(1)
Reset Vector
0000h
4.1
Program Memory Organization for
the PIC12F508/509
On-chip Program
Memory
The PIC12F508 device has a 10-bit Program Counter
(PC) and PIC12F509 has a 11-bit Program Counter
(PC) capable of addressing a 2K x 12 program memory
space.
512 Word
01FFh
0200h
Only the first 512 x 12 (0000h-01FFh) for the
PIC12F508, and 1K x 12 (0000h-03FFh) for the
PIC12F509 are physically implemented (see
On-chip Program
Memory
Figure 4-1). Accessing
a location above these
boundaries will cause a wraparound within the first
512 x 12 space (PIC12F508) or 1K x 12 space
(PIC12F509). The effective Reset vector is a 0000h
(see Figure 4-1). Location 01FFh (PIC12F508) and
location 03FFh (PIC12F509) contain the internal
clock oscillator calibration value. This value should
never be overwritten.
1024 Word
03FFh
0400h
7FFh
Note 1: Address 0000h becomes the
effective Reset vector. Location
01FFh, 03FFh (PIC12F508,
PIC12F509) contains the MOVLW XX
internal oscillator calibration value.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 15
PIC12F508/509/16F505
4.2
Program Memory Organization
For The PIC16F505
4.3
Data Memory Organization
Data memory is composed of registers or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: Special Function Registers (SFR)
and General Purpose Registers (GPR).
The PIC16F505 device has a 11-bit Program Counter
(PC) capable of addressing a 2K x 12 program memory
space.
The 1K x 12 (0000h-03FFh) for the PIC16F505 are
physically implemented. Refer to Figure 4-2. Access-
ing a location above this boundary will cause a wrap-
around within the first 1K x 12 space. The effective
Reset vector is at 0000h (see Figure 4-2). Location
03FFh contains the internal oscillator calibration value.
This value should never be overwritten.
The Special Function Registers include the TMR0 reg-
ister, the Program Counter (PCL), the Status register,
the I/O registers (ports) and the File Select Register
(FSR). In addition, Special Function Registers are used
to control the I/O port configuration and prescaler
options.
The General Purpose Registers are used for data and
control information under command of the instructions.
FIGURE 4-2:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F505
For the PIC12F508/509, the register file is composed of
7 Special Function Registers, 9 General Purpose
Registers and 16 or 32 General Purpose Registers
accessed by banking (see Figure 4-3 and Figure 4-4).
PC<11:0>
12
CALL, RETLW
For the PIC16F505, the register file is composed of 8
Stack Level 1
Stack Level 2
Special Function Registers,
8 General Purpose
Registers and 64 General Purpose Registers accessed
by banking (Figure 4-5).
(1)
Reset Vector
0000h
4.3.1
GENERAL PURPOSE REGISTER
FILE
The General Purpose Register file is accessed, either
directly or indirectly, through the File Select Register
(FSR). See Section 4.9 “Indirect Data Addressing:
INDF and FSR Registers”.
01FFh
0200h
On-chip Program
Memory
1024 Words
03FFh
0400h
7FFh
Note 1: Address 0000h becomes the
effective Reset vector. Location
03FFh contains the MOVLW XX
internal oscillator calibration value.
DS41236A-page 16
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
FIGURE 4-3:
PIC12F508 REGISTER
FILE MAP
FIGURE 4-4:
PIC12F509 REGISTER
FILE MAP
FSR<6:5>
File Address
00h
00
01
File Address
(1)
INDF
00h
01h
02h
03h
04h
05h
06h
07h
(1)
20h
INDF
TMR0
PCL
TMR0
PCL
01h
02h
03h
04h
05h
STATUS
FSR
Addresses map
back to
addresses
in Bank 0.
STATUS
FSR
OSCCAL
GPIO
OSCCAL
GPIO
06h
07h
General
Purpose
Registers
General
Purpose
Registers
2Fh
0Fh
10h
30h
General
Purpose
Registers
General
Purpose
Registers
1Fh
1Fh
3Fh
Bank 0
Bank 1
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and FSR
Registers”.
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and
FSR Registers”.
FIGURE 4-5:
PIC16F505 REGISTER FILE MAP
FSR<6:5>
00
01
10
11
File Address
00h
(1)
20h
40h
60h
INDF
01h
02h
03h
04h
05h
06h
TMR0
PCL
Addresses map back to
addresses in Bank 0.
STATUS
FSR
OSCCAL
PORTB
PORTC
07h
08h
General
Purpose
Registers
2Fh
30h
4Fh
50h
6Fh
0Fh
70h
10h
1Fh
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
3Fh
5Fh
7Fh
Bank 1
Bank 2
Bank 3
Bank 0
Note 1: Not a physical register. See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers”.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 17
PIC12F508/509/16F505
4.3.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control the
operation of the device (Table 4-1).
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC12F508/509)
Value on
Name
INDF
TMR0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
Power-On Page #
Reset(2)
00h
Uses Contents of FSR to Address Data Memory (not a physical
register)
xxxx xxxx
26
01h
8-bit Real-Time Clock/Counter
xxxx xxxx
1111 1111
0-01 1xxx(3)
111x xxxx
110x xxxx
1111 111-
--xx xxxx
--11 1111
1111 1111
33
25
20
26
26
24
29
29
22
02h(1)
PCL
Low-order 8 bits of PC
03h
STATUS
FSR
GPWUF
—
PA0(5)
TO
PD
Z
DC
C
04h
Indirect Data Memory Address Pointer
Indirect Data Memory Address Pointer
04h(4)
FSR
05h
OSCCAL
GPIO
CAL6
—
CAL5 CAL4 CAL3
CAL2
GP3
CAL1 CAL0
—
06h
—
—
GP5
GP4
GP2
GP1 GP0
N/A
TRISGPIO
OPTION
—
I/O Control Register
PSA
N/A
GPWU GPPU TOCS TOSE
PS2
PS1 PS0
Legend: — = unimplemented, read as ‘0’, x= unknown, u= unchanged, q= value depends on condition.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.7 “Program Counter” for
an explanation of how to access these bits.
2: Other (non Power-up) Resets include external Reset through MCLR, Watchdog Timer and wake-up on pin
change Reset.
3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
4: PIC12F509 only.
5: This bit is used on the PIC12F509. For code compatibility do not use this bit on the PIC12F508.
DS41236A-page 18
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
TABLE 4-2:
Address
SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC16F505)
Value on
Bit 1 Bit 0 Power-On
Reset(2)
Name
INDF
TMR0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Page #
00h
Uses Contents of FSR to Address Data Memory (not a physical
register)
xxxx xxxx
26
01h
02h(1)
03h
04h
05h
06h
07h
N/A
N/A
N/A
8-bit Real-Time Clock/Counter
Low-order 8 bits of PC
xxxx xxxx
1111 1111
0-01 1xxx
110x xxxx
1111 111-
--xx xxxx
--xx xxxx
--11 1111
--11 1111
1111 1111
33
25
20
26
24
29
29
29
29
23
PCL
STATUS
FSR
RBWUF
—
PA0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
OSCCAL
PORTB
PORTC
TRISB
TRISC
OPTION
CAL6
—
CAL5 CAL4 CAL3
CAL2
RB3
CAL1 CAL0
—
—
—
—
—
RB5
RC5
RB4
RC4
RB2
RC2
RB1 RB0
RC1 RC0
—
RC3
—
I/O Control Register
I/O Control Register
—
RBWU RBPU TOCS TOSE
PSA
PS2
PS1 PS0
Legend: — = unimplemented, read as ‘0’, x= unknown, u= unchanged, q= value depends on condition.
Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
2: Other (non Power-up) Resets include external reset through MCLR, Watchdog Timer and wake-up on pin
change Reset.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 19
PIC12F508/509/16F505
For example, CLRF STATUS,will clear the upper three
bits and set the Z bit. This leaves the Status register as
000u u1uu(where u= unchanged).
4.4
Status Register
This register contains the arithmetic status of the ALU,
the Reset status and the page preselect bit.
Therefore, it is recommended that only BCF, BSFand
MOVWFinstructions be used to alter the Status register.
These instructions do not affect the Z, DC or C bits from
the Status register. For other instructions which do
affect Status bits, see Section 8.0 “Instruction Set
Summary”.
The Status register can be the destination for any
instruction, as with any other register. If the Status
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
Status register as destination may be different than
intended.
REGISTER 4-1:
STATUS REGISTER (ADDRESS: 03h) (PIC12F508/509)
R/W-0
R/W-0
—
R/W-0
PA0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
GPWUF
bit 7
bit 0
bit 7
GPWUF: GPIO Reset bit
1= Reset due to wake-up from Sleep on pin change
0= After power-up or other Reset
bit 6
bit 5
Reserved: Do not use
(1)
PA0: Program Page Preselect bits
1= Page 1 (200h-3FFh)
0= Page 0 (000h-1FFh)
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page
preselect is not recommended, since this may affect upward compatibility with future products.
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)
ADDWF:
1= A carry from the 4th low-order bit of the result occurred
0= A carry from the 4th low-order bit of the result did not occur
SUBWF:
1= A borrow from the 4th low-order bit of the result did not occur
0= A borrow from the 4th low-order bit of the result occurred
bit 0
C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)
ADDWF:
SUBWF:
RRFor RLF:
1= A carry occurred
0= A carry did not occur
1= A borrow did not occur
0= A borrow occurred
Load bit with LSb or MSb, respectively
Note 1: This bit is used on the PIC12F509. For code compatibility do not use this bit on the
PIC12F508.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41236A-page 20
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
REGISTER 4-2:
STATUS REGISTER (ADDRESS: 03h) (PIC16F505)
R/W-0
RBWUF
bit 7
R/W-0
—
R/W-0
PA0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 0
bit 7
RBWUF: PORTB Reset bit
1= Reset due to wake-up from Sleep on pin change
0= After power-up or other Reset
bit 6
bit 5
Reserved: Do not use
PA0: Program Page Preselect bits
1= Page 1 (200h-3FFh)
0= Page 0 (000h-1FFh)
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program
page preselect is not recommended, since this may affect upward compatibility with future
products.
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)
ADDWF:
1= A carry from the 4th low-order bit of the result occurred
0= A carry from the 4th low-order bit of the result did not occur
SUBWF:
1= A borrow from the 4th low-order bit of the result did not occur
0= A borrow from the 4th low-order bit of the result occurred
bit 0
C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)
ADDWF:
SUBWF:
RRFor RLF:
1= A carry occurred
1= A borrow did not occur Load bit with LSb or MSb, respectively
0= A carry did not occur 0= A borrow occurred
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 21
PIC12F508/509/16F505
4.5
Option Register
Note:
Note:
If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are disabled
for that pin (i.e., note that TRIS overrides
Option control of GPPU/RBPU and
GPWU/RBWU).
The Option register is a 8-bit wide, write-only register,
which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W register will be transferred to the Option register.
A Reset sets the Option<7:0> bits.
If the T0CS bit is set to ‘1’, it will override
the TRIS function on the T0CKI pin.
REGISTER 4-3:
OPTION REGISTER (PIC12F508/509)
W-1
W-1
W-1
W-1
T0SE
W-1
W-1
PS2
W-1
PS1
W-1
GPWU
bit 7
GPPU
T0CS
PSA
PS0
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
GPWU: Enable Wake-up on Pin Change bit (GP0, GP1, GP3)
1= Disabled
0= Enabled
GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3)
1= Disabled
0= Enabled
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin (overrides TRIS on the T0CKI pin)
0= Transition on internal instruction cycle clock, FOSC/4
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on the T0CKI pin
0= Increment on low-to-high transition on the T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler assigned to the WDT
0= Prescaler assigned to Timer0
PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41236A-page 22
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
REGISTER 4-4:
OPTION REGISTER (PIC16F505)
W-1
W-1
W-1
W-1
W-1
W-1
PS2
W-1
PS1
W-1
RBWU
bit 7
RBPU
T0CS
T0SE
PSA
PS0
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBWU: Enable Wake-up on Pin Change bit (RB0, RB1, RB3, RB4)
1= Disabled
0= Enabled
RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4)
1= Disabled
0= Enabled
T0CS: Timer0 clock Source Select bit
1= Transition on T0CKI pin (overrides TRIS on the T0CKI pin)
0= Transition on internal instruction cycle clock, FOSC/4
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on the T0CKI pin
0= Increment on low-to-high transition on the T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler assigned to the WDT
0= Prescaler assigned to Timer0
PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 23
PIC12F508/509/16F505
4.6
OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to
calibrate the internal precision 4 MHz oscillator. It
contains seven bits for calibration.
Note:
Erasing the device will also erase the pre-
programmed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
After you move in the calibration constant, do not
change the value. See Section 7.2.5 “Internal 4 MHz
RC Oscillator”.
REGISTER 4-5:
OSCCAL REGISTER (ADDRESS: 05h)
R/W-1
CAL6
R/W-1
CAL5
R/W-1
CAL4
R/W-1
CAL3
R/W-1
CAL2
R/W-1
CAL1
R/W-1
CAL0
R/W-0
—
bit 7
bit 0
bit 7-1
CAL<6:0>: Oscillator Calibration bits
0111111= Maximum frequency
•
•
•
0000001
0000000= Center frequency
1111111
•
•
•
1000000= Minimum frequency
bit 0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41236A-page 24
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
4.7.1
EFFECTS OF RESET
4.7
Program Counter
The PC is set upon a Reset, which means that the PC
addresses the last location in the last page (i.e., the
oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 00h and
begin executing user code.
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
The Status register page preselect bits are cleared upon
a Reset, which means that page 0 is pre-selected.
For a GOTOinstruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The Program Counter
(PCL) is mapped to PC<7:0>. Bit 5 of the Status
register provides page information to bit 9 of the PC
(Figure 4-6).
Therefore, upon a Reset, a GOTO instruction will
automatically cause the program to jump to page 0 until
the value of the page bits is altered.
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-6).
4.8
Stack
The PIC12F508/509/16F505 devices have a 2-deep,
12-bit wide hardware PUSH/POP stack.
A CALLinstruction will PUSH the current value of Stack 1
into Stack 2 and then PUSH the current PC value, incre-
mented by one, into Stack Level 1. If more than two
sequential CALLs are executed, only the most recent two
return addresses are stored.
Instructions where the PCL is the destination, or modify
PCL instructions, include MOVWF PC, ADDWF PCand
BSF PC,5.
Note:
Because PC<8> is cleared in the CALL
instruction or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any
program memory page (512 words long).
A RETLW instruction will POP the contents of Stack
Level 1 into the PC and then copy Stack Level 2
contents into Stack Level 1. If more than two sequential
RETLWs are executed, the stack will be filled with the
address previously stored in Stack Level 2. Note that
the W register will be loaded with the literal value
specified in the instruction. This is particularly useful for
the implementation of data look-up tables within the
program memory.
FIGURE 4-6:
LOADING OF PC
BRANCH INSTRUCTIONS
GOTOInstruction
11 10 9 8 7
0
Note 1: There are no Status bits to indicate stack
PC
PCL
overflows or stack underflow conditions.
2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLWinstructions.
Instruction Word
0
PA0
7
Status
CALLor Modify PCL Instruction
11 10 9 8 7
0
PC
PCL
Instruction Word
Reset to ‘0’
PA0
7
0
Status
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 25
PIC12F508/509/16F505
EXAMPLE 4-1:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
4.9
Indirect Data Addressing: INDF
and FSR Registers
The INDF register is not
a physical register.
MOVLW
MOVWF
0x10
;initialize pointer
;to RAM
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a pointer). This is indirect addressing.
FSR
NEXT
CLRF
INDF
;clear INDF
;register
INCF
BTFSC
GOTO
FSR,F
FSR,4
NEXT
;inc pointer
;all done?
;NO, clear next
4.9.1
INDIRECT ADDRESSING
• Register file 07 contains the value 10h
• Register file 08 contains the value 0Ah
• Load the value 07 into the FSR register
CONTINUE
:
:
;YES, continue
• A read of the INDF register will return the value
of 10h
The FSR is a 5-bit wide register. It is used in conjunction
with the INDF register to indirectly address the data
memory area.
• Increment the value of the FSR register by one
(FSR = 08)
• A read of the INDR register now will return the
value of 0Ah.
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no operation (although Status bits may be affected).
PIC12F508 – Does not use banking. FSR <7:5> are
unimplemented and read as ‘1’s.
PIC12F509 – Uses FSR<5>. Selects between bank 0
and bank 1. FSR<7:6> is unimplemented, read as ‘1’.
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-1.
PIC16F505 – Uses FSR<6:5>. Selects from bank 0 to
bank 3. FSR<7> is unimplemented, read as ‘1’.
FIGURE 4-7:
DIRECT/INDIRECT ADDRESSING (PIC12F508/509)
Direct Addressing
Indirect Addressing
(FSR)
4
(opcode)
0
5
(FSR)
0
6
4
5
6
Location Select
Bank Select
Location Select
Bank
00
01
00h
Addresses
map back to
addresses
in Bank 0.
Data
Memory
0Fh
10h
(1)
1Fh
Bank 0
3Fh
Bank 1
(2)
Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.
2: PIC12F509.
DS41236A-page 26
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
FIGURE 4-8:
DIRECT/INDIRECT ADDRESSING (PIC16F505)
Direct Addressing
Indirect Addressing
(FSR) 0
(FSR)
6
5
4
(opcode)
0
6
5
4
Bank Select
Location Select
00h
Bank
Location Select
00
01
10
11
Addresses
map back to
addresses
in Bank 0.
0Fh
10h
Data
Memory
(1)
1Fh
3Fh
Bank 1
5Fh
Bank 2
7Fh
Bank 0
Bank 3
Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 27
PIC12F508/509/16F505
NOTES:
DS41236A-page 28
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
5.4
I/O Interfacing
5.0
I/O PORT
The equivalent circuit for an I/O port pin is shown in
Figure 5-2. All port pins, except RB3/GP3 which is
input only, may be used for both input and output oper-
ations. For input operations, these ports are non-latch-
ing. Any input must be present until read by an input
instruction (e.g., MOVF PORTB, W). The outputs are
latched and remain unchanged until the output latch is
rewritten. To use a port pin as output, the correspond-
ing direction control bit in TRIS must be cleared (= 0).
For use as an input, the corresponding TRIS bit must
be set. Any I/O pin (except RB3/GP3) can be
programmed individually as input or output.
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s input/output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
Note:
On the PIC12F508/509, I/O PORTB is ref-
erenced as GPIO. On the PIC16F505, I/O
PORTB is referenced as PORTB.
FIGURE 5-1:
PIC12F508/509/16F505
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
5.1
PORTB/GPIO
PORTB/GPIO is an 8-bit I/O register. Only the low-
order 6 bits are used (RB/GP<5:0>). Bits 7 and 6 are
unimplemented and read as ‘0’s. Please note that RB3/
GP3 is an input only pin. The Configuration Word can
set several I/O’s to alternate functions. When acting as
alternate functions, the pins will read as ‘0’ during a port
read. Pins RB0/GP0, RB1/GP1, RB3/GP3 and RB4
can be configured with weak pull-ups and also for
wake-up on change. The wake-up on change and weak
pull-up functions are not pin selectable. If RB3/GP3/
MCLR is configured as MCLR, weak pull-up is always
on and wake-up on change for this pin is not enabled.
Data
Bus
D
Q
Q
Data
Latch
VDD
P
VDD
WR
Port
CK
N
I/O
pin
W
Reg
D
Q
Q
TRIS
Latch
VSS VSS
TRIS ‘f’
5.2
PORTC (PIC16F505 Only)
CK
PORTC is an 8-bit I/O register. Only the low-order 6 bits
are used (RC<5:0>). Bits 7 and 6 are unimplemented
and read as ‘0’s.
Reset
(1)
5.3
TRIS Registers
The Output Driver Control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A ‘1’ from a TRIS register bit puts the corre-
sponding output driver in a High-Impedance mode. A
‘0’ puts the contents of the output data latch on the
selected pins, enabling the output buffer. The excep-
tions are RB3/GP3, which is input only and the T0CKI
pin, which may be controlled by the Option register.
See Register 4-3 and Register 4-4.
RD Port
Note 1: See Table 3-3 for buffer type.
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon Reset.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 29
PIC12F508/509/16F505
TABLE 5-1:
SUMMARY OF PORT REGISTERS
Value on
Power-On
Reset
Value on
All Other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
(1)
N/A
TRISGPIO
—
—
—
—
I/O Control Register
I/O Control Register
I/O Control Register
--11 1111
--11 1111
--11 1111
1111 1111
1111 1111
--11 1111
--11 1111
--11 1111
1111 1111
1111 1111
(2)
N/A
TRISB
(2)
N/A
TRISC
—
—
(1)
N/A
OPTION
GPWU
RBWU
GPWUF
RBWUF
—
GPPU
RBPU
—
TOCS
TOCS
PAO
PAO
GP5
TOSE
TOSE
TO
PSA
PSA
PD
PS2
PS2
Z
PS1
PS1
DC
PS0
PS0
C
(2)
N/A
OPTION
(1)
(3)
03h
STATUS
0-01 1xxx q00q quuu
0-01 1xxx q00q quuu
(2)
(3)
03h
STATUS
—
TO
PD
Z
DC
C
(1)
06h
GPIO
—
GP4
RB4
RC4
GP3
RB3
RC3
GP2
RB2
RC2
GP1
RB1
RC1
GP0
RB0
RC0
--xxxxxx
--xxxxxx
--xx xxxx
--uu uuuu
(2)
06h
PORTB
—
—
RB5
--uu uuuu
--uu uuuu
(2)
07h
PORTC
—
—
RC5
Legend:
Shaded cells are not used by Port registers, read as ‘0’. — = unimplemented, read as ‘0’, x= unknown, u= unchanged,
q= depends on condition.
Note 1: PIC12F508/509 only.
2: PIC16F505 only.
3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
DS41236A-page 30
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT(e.g. PIC16F505)
5.5
I/O Programming Considerations
5.5.1
BIDIRECTIONAL I/O PORTS
Some instructions operate internally as read followed
by write operations. The BCFand BSFinstructions, for
example, read the entire port into the CPU, execute the
bit operation and re-write the result. Caution must be
used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSFoperation on bit 5 of PORTB/GPIO will
cause all eight bits of PORTB/GPIO to be read into the
CPU, bit 5 to be set and the PORTB/GPIO value to be
written to the output latches. If another bit of PORTB/
GPIO is used as a bidirectional I/O pin (say bit 0) and it
is defined as an input at this time, the input signal
present on the pin itself would be read into the CPU and
rewritten to the data latch of this particular pin, overwrit-
ing the previous content. As long as the pin stays in the
Input mode, no problem occurs. However, if bit 0 is
switched into Output mode later on, the content of the
data latch may now be unknown.
;Initial PORTB Settings
;PORTB<5:3> Inputs
;PORTB<2:0> Outputs
;
;
;
PORTB latch PORTB pins
----------
PORTB, 5 ;--01 -ppp
PORTB, 4 ;--10 -ppp
----------
--11 pppp
--11 pppp
BCF
BCF
MOVLW 007h;
TRIS PORTB
;--10 -ppp
--11 pppp
;
Note 1: The user may have expected the pin values to
be ‘--00 pppp’. The 2nd BCFcaused RB5 to
be latched as the pin value (High).
5.5.2
SUCCESSIVE OPERATIONS ON
I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 5-2).
Therefore, care must be exercised if a write followed by
a read operation is carried out on the same I/O port. The
sequence of instructions should allow the pin voltage to
stabilize (load dependent) before the next instruction
causes that file to be read into the CPU. Otherwise, the
previous state of that pin may be read into the CPU rather
than the new state. When in doubt, it is better to separate
these instructions with a NOPor another instruction not
accessing this I/O port.
Example 5-1 shows the effect of two sequential
Read-Modify-Write instructions (e.g., BCF, BSF, etc.)
on an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired OR”, “wired
AND”). The resulting high output currents may damage
the chip.
FIGURE 5-2:
SUCCESSIVE I/O OPERATION (PIC16F505 Shown)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC + 3
PC
MOVWFPORTB
PC + 1
PC + 2
This example shows a write to PORTB
followed by a read from PORTB.
Instruction
Fetched
MOVFPORTB, W
NOP
NOP
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle.
TPD = propagation delay
RB<5:0>
Port pin
written here
Port pin
sampled here
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
Instruction
Executed
MOVWF PORTB
(Write to PORTB)
MOVF PORTB,W
(Read PORTB)
NOP
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 31
PIC12F508/509/16F505
NOTES:
DS41236A-page 32
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
Counter mode is selected by setting the T0CS bit
(Option<5>). In this mode, Timer0 will increment either
on every rising or falling edge of pin T0CKI. The T0SE
bit (Option<4>) determines the source edge. Clearing
the T0SE bit selects the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 6.1 “Using Timer0 with an External Clock”.
6.0
TIMER0 MODULE AND TMR0
REGISTER
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select:
- Edge select for external clock
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit, PSA (Option<3>). Clearing the PSA bit will
assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 6.2 “Prescaler” details
the operation of the prescaler.
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(Option<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
A summary of registers associated with the Timer0
module is found in Table 6-1.
FIGURE 6-1:
TIMER0 BLOCK DIAGRAM
Data Bus
(GP2/RC5)/T0CKI FOSC/4
0
1
PSOUT
8
Pin
1
0
Sync with
Internal
Clocks
TMR0 reg
Programmable
PSOUT
Sync
(2)
Prescaler
(2 TCY delay)
T0SE
3
(1)
(1)
PS2, PS1, PS0
PSA
(1)
T0CS
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the Option register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
FIGURE 6-2:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Instruction
Fetch
T0
NT0 + 1
T0 + 1
T0 + 2
NT0
NT0 + 2
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 33
PIC12F508/509/16F505
FIGURE 6-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Instruction
Fetch
T0
T0 + 1
NT0
NT0 + 1
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Power-On
Reset
Value on
All Other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
Timer0 – 8-bit real-time clock/counter
GPWU GPPU T0CS T0SE
xxxx xxxx
1111 1111
1111 1111
--11 1111
--11 1111
uuuu uuuu
1111 1111
1111 1111
--11 1111
--11 1111
(1)
(2)
N/A
OPTION
OPTION
PSA
PSA
PS2
PS2
PS1
PS1
PS0
PS0
N/A
RBWU
—
RBPU
—
T0CS T0SE
(1), (3)
N/A
TRISGPIO
I/O Control Register
RC5 RC4 RC3
(2), (3)
N/A
TRISC
—
—
RC2
RC1
RC0
Legend:
Shaded cells are not used by Timer0. — = unimplemented, x = unknown, u= unchanged.
Note 1: PIC12F508/509 only.
2: PIC16F505 only.
3: The TRIS of the T0CKI pin is overridden when T0CS = 1.
DS41236A-page 34
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling require-
ment, the ripple counter must be taken into account.
Therefore, it is necessary for T0CKI to have a period of
at least 4 TOSC (and a small RC delay of 4 Tt0H) divided
by the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the
minimum pulse width requirement of Tt0H. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
6.1
Using Timer0 with an External
Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock require-
ment is due to internal phase clock (TOSC) synchroniza-
tion. Also, there is a delay in the actual incrementing of
Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 6-4).
Therefore, it is necessary for T0CKI to be high for at
least 2 TOSC (and a small RC delay of 2 Tt0H) and low
for at least 2 TOSC (and a small RC delay of 2 Tt0H).
Refer to the electrical specification of the desired
device.
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
FIGURE 6-4:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
misses sampling
External Clock Input or
(2)
Prescaler Output
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4 TOSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 35
PIC12F508/509/16F505
EXAMPLE 6-1:
CHANGING PRESCALER
(TIMER0 → WDT)
;Clear WDT
;Clear TMR0 & Prescaler
6.2
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (see Section 7.6 “Watch-
dog Timer (WDT)”). For simplicity, this counter is
being referred to as “prescaler” throughout this data
sheet.
CLRWDT
CLRF
TMR0
MOVLW ‘00xx1111’b;These 3 lines (5, 6, 7)
OPTION
;are required only if
;desired
;PS<2:0> are 000 or 001
CLRWDT
MOVLW ‘00xx1xxx’b;Set Postscaler to
OPTION ;desired WDT rate
Note:
The prescaler may be used by either the
Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the WDT and vice versa.
To change the prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before
switching the prescaler.
The PSA and PS<2:0> bits (Option<3:0>) determine
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x, etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT. The prescaler is neither readable
nor writable. On a Reset, the prescaler contains all ‘0’s.
EXAMPLE 6-2:
CHANGING PRESCALER
(WDT → TIMER0)
CLRWDT
;Clear WDT and
;prescaler
MOVLW ‘xxxx0xxx’ ;Select TMR0, new
;prescale value and
;clock source
6.2.1
SWITCHING PRESCALER
ASSIGNMENT
OPTION
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during pro-
gram execution). To avoid an unintended device Reset,
the following instruction sequence (Example 6-1) must
be executed when changing the prescaler assignment
from Timer0 to the WDT.
DS41236A-page 36
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
FIGURE 6-5:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER(1), (2)
TCY (= FOSC/4)
Data Bus
8
0
1
(GP2/RC5)/T0CKI
pin
M
U
X
1
0
M
U
X
Sync
2
Cycles
TMR0 reg
T0SE
T0CS
PSA
0
1
8-bit Prescaler
M
U
X
8
Watchdog
Timer
8-to-1 MUX
PS<2:0>
PSA
1
0
WDT Enable bit
MUX
PSA
WDT
Time-out
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the Option register.
2: T0CKI is shared with pin RC5 on the PIC16F505 and pin GP2 on the PIC12F508/509.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 37
PIC12F508/509/16F505
NOTES:
DS41236A-page 38
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
The PIC12F508/509/16F505 devices have a Watchdog
Timer, which can be shut off only through configuration
bit WDTE. It runs off of its own RC oscillator for added
reliability. If using HS (PIC16F505), XT or LP selectable
oscillator options, there is always an 18 ms (nominal)
delay provided by the Device Reset Timer (DRT),
intended to keep the chip in Reset until the crystal
oscillator is stable. If using INTRC or EXTRC, there is
an 18 ms delay only on VDD power-up. With this timer
on-chip, most applications need no external Reset
circuitry.
7.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits that deal with the needs of real-
time applications. The PIC12F508/509/16F505
microcontrollers have a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power-
saving operating modes and offer code protection.
These features are:
The Sleep mode is designed to offer a very low current
Power-down mode. The user can wake-up from Sleep
through a change on input pins or through a Watchdog
Timer time-out. Several oscillator options are also
made available to allow the part to fit the application,
including an internal 4 MHz oscillator. The EXTRC
oscillator option saves system cost while the LP crystal
option saves power. A set of configuration bits are used
to select various options.
• Oscillator Selection
• Reset:
- Power-on Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from Sleep on Pin Change
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
7.1
Configuration Bits
• In-Circuit Serial Programming™
• Clock Out
The PIC12F508/509/16F505 Configuration Words
consist of 12 bits. Configuration bits can be
programmed to select various device configurations.
Three bits are for the selection of the oscillator type;
(two bits on the PIC12F508/509), one bit is the
Watchdog Timer enable bit, one bit is the MCLR enable
bit and one bit is for code protection (Register 7-1,
Register 7-2).
REGISTER 7-1:
CONFIGURATION WORD FOR PIC12F508/509(1)
—
—
—
—
—
—
—
MCLRE
CP
WDTE
FOSC1
FOSC0
bit 0
bit 11
bit 11-5
bit 4
Unimplemented: Read as ‘0’
MCLRE: GP3/MCLR Pin Function Select bit
1= GP3/MCLR pin function is MCLR
0= GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD
bit 3
CP: Code Protection bit
1= Code protection off
0= Code protection on
bit 2
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0
FOSC<1:0>: Oscillator Selection bits
11= EXTRC = external selection bits
10= INTRC = internal RC oscillator
01= XT oscillator
00= LP oscillator
Note 1: Refer to the “PIC12F508/509 Memory Programming Specifications” (DS41227) to determine how to access
the Configuration Word. The Configuration Word is not user addressable during device operation.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = bit is cleared x = bit is unknown
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 39
PIC12F508/509/16F505
REGISTER 7-2:
CONFIGURATION WORD FOR PIC16F505(1)
—
—
—
—
—
—
MCLRE CP
WDTE FOSC2 FOSC1 FOSC0
bit 0
bit 11
bit 11-6 Unimplemented: Read as ‘0’
bit 5
bit 4
bit 3
MCLRE: RB3/MCLR Pin Function Select bit
1= RB3/MCLR pin function is MCLR
0= RB3/MCLR pin function is digital I/O, MCLR internally tied to VDD
CP: Code Protection bit
1= Code protection off
0= Code protection on
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 2-0 FOSC<1:0>: Oscillator Selection bits
111= External RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin
110= External RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin
101= Internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin
100= Internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin
011= EC oscillator/RB4 function on RB4/OSC2/CLKOUT pin
010= HS oscillator
001= XT oscillator
000= LP oscillator
Note 1: Refer to the “PIC16F505 Memory Programming Specifications” (DS41226) to determine how to
access the Configuration Word. The Configuration Word is not user addressable during device
operation.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = bit is cleared x = bit is unknown
DS41236A-page 40
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
FIGURE 7-1:
CRYSTAL OPERATION
(OR CERAMIC
RESONATOR)
7.2
Oscillator Configurations
7.2.1
OSCILLATOR TYPES
(HS, XT OR LP OSC
CONFIGURATION)
The PIC12F508/509/16F505 devices can be operated
in up to six different oscillator modes. The user can
program up to three configuration bits (FOSC<1:0>
[PIC12F508/509], FOSC<2:0> [PIC16F505]). To select
one of these modes:
(1)
C1
PIC12F508/509
PIC16F505
OSC1
OSC2
Sleep
• LP:
• XT:
• HS:
Low-Power Crystal
Crystal/Resonator
XTAL
(3)
RF
To internal
logic
High-Speed Crystal/Resonator
(PIC16F505 only)
(2)
RS
(1)
C2
• INTRC: Internal 4 MHz Oscillator
• EXTRC: External Resistor/Capacitor
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
• EC:
External High-Speed Clock Input
(PIC16F505 only)
3: RF approx. value = 10 MΩ.
7.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In HS (PIC16F505), XT or LP modes, a crystal or
ceramic resonator is connected to the (GP5/RB5)/
OSC1/(CLKIN) and (GP4/RB4)/OSC2/(CLKOUT) pins
to establish oscillation (Figure 7-1). The PIC12F508/
509/16F505 oscillator designs require the use of a
parallel cut crystal. Use of a series cut crystal may give
FIGURE 7-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
a
frequency out of the crystal manufacturers
OSC1
Clock from
ext. system
specifications. When in HS (PIC16F505), XT or LP
modes, the device can have an external clock source
drive the (GP5/RB5)/OSC1/CLKIN pin (Figure 7-2).
PIC12F508/509
PIC16F505
OSC2
Open
Note 1: This device has been designed to per-
form to the parameters of its data sheet.
It has been tested to an electrical
specification designed to determine its
conformance with these parameters.
Due to process differences in the
manufacture of this device, this device
may have different performance charac-
teristics than its earlier version. These
differences may cause this device to
perform differently in your application
than the earlier version of this device.
TABLE 7-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS –
PIC12F508/509/16F505(1)
Osc
Resonator Cap. Range Cap. Range
Type
Freq
C1
C2
XT
HS(2)
4.0 MHz
16 MHz
30 pF
30 pF
10-47 pF
10-47 pF
Note 1: These values are for design guidance
only. Since each resonator has its own
characteristics, the user should consult
the resonator manufacturer for
appropriate values of external
2: The user should verify that the device
oscillator starts and performs as
expected. Adjusting the loading capacitor
values and/or the Oscillator mode may
be required.
components.
2: PIC16F505 only.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 41
PIC12F508/509/16F505
TABLE 7-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR –
PIC12F508/509/16F505(2)
FIGURE 7-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
Osc
Type
Resonator Cap.Range Cap. Range
To Other
Devices
Freq
C1
C2
10k
32 kHz(1)
15 pF
15 pF
4.7k
74AS04
LP
XT
200 kHz
1 MHz
4 MHz
47-68 pF
15 pF
15 pF
47-68 pF
15 pF
15 pF
CLKIN
74AS04
PIC16F505
PIC12F508
PIC12F509
(3)
10k
HS
20 MHz
15-47 pF
15-47 pF
XTAL
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
10k
2: These values are for design guidance
only. Rs may be required to avoid over-
driving crystals with low drive level specifi-
cation. Since each crystal has its own
characteristics, the user should consult
the crystal manufacturer for appropriate
values of external components.
20 pF
20 pF
Figure 7-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180-
degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
3: PIC16F505 only.
7.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
FIGURE 7-4:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good perfor-
mance with TTL gates. Two types of crystal oscillator
circuits can be used: one with parallel resonance, or
one with series resonance.
To Other
Devices
330
330
74AS04
74AS04
74AS04
CLKIN
0.1 mF
XTAL
PIC16F505
PIC12F508
PIC12F509
Figure 7-3 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the fun-
damental frequency of the crystal. The 74AS04 inverter
performs the 180-degree phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ potentiome-
ters bias the 74AS04 in the linear region. This circuit
could be used for external oscillator designs.
7.2.4
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C
components used.
Figure 7-5 shows how the R/C combination is con-
nected to the PIC12F508/509/16F505 devices. For
REXT values below 3.0 kΩ, the oscillator operation may
become unstable, or stop completely. For very high
REXT values (e.g., 1 MΩ), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, we
recommend keeping REXT between 5.0 kΩ and
100 kΩ.
DS41236A-page 42
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
Although the oscillator will operate with no external
capacitor (CEXT = 0pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
In addition, a calibration instruction is programmed into
the last address of memory, which contains the calibra-
tion value for the internal RC oscillator. This location is
always uncode protected, regardless of the code-pro-
tect settings. This value is programmed as a MOVLW XX
instruction where XX is the calibration value, and is
placed at the Reset vector. This will load the W register
with the calibration value upon Reset and the PC will
then roll over to the users program at address 0x000.
The user then has the option of writing the value to the
OSCCAL Register (05h) or ignoring it.
Section 10.0 “Electrical Characteristics”, shows RC
frequency variation from part-to-part due to normal
process variation. The variation is larger for larger val-
ues of R (since leakage current variation will affect RC
frequency more for large R) and for smaller values of C
(since variation of input capacitance will affect RC
frequency more).
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency.
Also, see the Electrical Specifications section for
variation of oscillator frequency due to VDD for given
REXT/CEXT values, as well as frequency variation due
to operating temperature for given R, C and VDD
values.
Note:
Erasing the device will also erase the pre-
programmed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
FIGURE 7-5:
EXTERNAL RC
OSCILLATOR MODE
For the PIC12F508/509/16F505 devices, only bits
<7:1> of OSCCAL are implemented. Bits CAL6-CAL0
are used for calibration. Adjusting CAL6-CAL0 from
‘0000000’ to ‘1111111’ changes the clock speed. See
Register 4-5 for more information.
VDD
REXT
Internal
clock
OSC1
N
Note:
The 0 bit of OSCCAL is unimplemented
and should be written as 0 when modifying
OSCCAL for compatibility with future
devices.
CEXT
VSS
PIC16F505
PIC12F508
PIC12F509
OSC2/CLKOUT
FOSC/4
7.2.5
INTERNAL 4 MHz RC OSCILLATOR
The internal RC oscillator provides a fixed 4 MHz (nom-
inal) system clock at VDD = 5V and 25°C, (see
Section 10.0 “Electrical Characteristics” for
information on variation over voltage and temperature).
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 43
PIC12F508/509/16F505
7.3.1
EXTERNAL CLOCK IN
7.3
Reset
For applications where a clock is already available
elsewhere, users may directly drive the PIC12F508/
509/16F505 devices provided that this external clock
source meets the AC/DC timing requirements listed in
Section 7.6 “Watchdog Timer (WDT)”. Figure 7-6
below shows how an external clock circuit should be
configured.
The device differentiates between various kinds of
Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during Sleep
• WDT time-out Reset during normal operation
• WDT time-out Reset during Sleep
• Wake-up from Sleep on pin change
FIGURE 7-6:
EXTERNAL CLOCK INPUT
OPERATION
Some registers are not reset in any way, they are
unknown on POR and unchanged in any other Reset.
Most other registers are reset to “Reset state” on
Power-on Reset (POR), MCLR, WDT or Wake-up on
pin change Reset during normal operation. They are
not affected by a WDT Reset during Sleep or MCLR
Reset during Sleep, since these Resets are viewed as
resumption of normal operation. The exceptions to this
are TO, PD and RBWUF/GPWUF bits. They are set or
cleared differently in different Reset situations. These
bits are used in software to determine the nature of
Reset. See Table 7-4 for a full description of Reset
states of all registers.
PIC16F505: EC, HS, XT, LP
Clock From
ext. system
RB5/OSC1/CLKIN
PIC16F505
(1)
OSC2/CLKOUT/RB4
OSC2/CLKOUT/RB4
PIC12F508/509: XT, LP
Clock From
ext. system
GP5/OSC1/CLKIN
PIC12F508
PIC12F509
GP4/OSC2
OSC2
Note 1: RB4 is available in EC mode only.
TABLE 7-3:
Register
RESET CONDITIONS FOR REGISTERS – PIC12F508/509
MCLR Reset, WDT Time-out,
Wake-up On Pin Change
Address
Power-on Reset
W
—
qqqq qqqu(1)
xxxx xxxx
xxxx xxxx
1111 1111
qqqq qqqu(1)
uuuu uuuu
uuuu uuuu
1111 1111
INDF
TMR0
PC
00h
01h
02h
STATUS
FSR(4)
03h
04h
0001 1xxx
110x xxxx
q00q quuu(2), (3)
11uu uuuu
FSR(5)
OSCCAL
GPIO
04h
05h
06h
—
111x xxxx
1111 111-
--xx xxxx
1111 1111
--11 1111
111u uuuu
uuuu uuu-
--uu uuuu
1111 1111
--11 1111
OPTION
TRIS
—
Legend: u= unchanged, x= unknown, — = unimplemented bit, read as ‘0’, q= value depends on condition.
Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of memory.
2: See Table 7-8 for Reset value for specific conditions.
3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
4: PIC12F509 only.
5: PIC12F508 only.
DS41236A-page 44
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
TABLE 7-4:
Register
RESET CONDITIONS FOR REGISTERS – PIC16F505
MCLR Reset, WDT Time-out,
Wake-up On Pin Change
Address
Power-on Reset
W
—
qqqq qqqu(1)
xxxx xxxx
xxxx xxxx
1111 1111
qqqq qqqu(1)
uuuu uuuu
uuuu uuuu
1111 1111
INDF
TMR0
PC
00h
01h
02h
STATUS
FSR
03h
04h
05h
06h
07h
—
0001 1xxx
110x xxxx
1111 111-
--xx xxxx
--xx xxxx
1111 1111
--11 1111
--11 1111
q00q quuu(2), (3)
11uu uuuu
uuuu uuu-
--uu uuuu
--uu uuuu
1111 1111
--11 1111
--11 1111
OSCCAL
PORTB
PORTC
OPTION
TRISB
—
TRISC
—
Legend: u= unchanged, x= unknown, — = unimplemented bit, read as ‘0’, q= value depends on condition.
Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of memory.
2: See Table 7-8 for Reset value for specific conditions.
3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
TABLE 7-5:
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
PCL Addr: 02h
Power-on Reset
0001 1xxx
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
MCLR Reset during normal operation
MCLR Reset during Sleep
000u uuuu
0001 0uuu
0000 0uuu
0000 uuuu
1001 0uuu
WDT Reset during Sleep
WDT Reset normal operation
Wake-up from Sleep on pin change
Legend: u= unchanged, x= unknown, — = unimplemented bit, read as ‘0’.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 45
PIC12F508/509/16F505
The Power-on Reset circuit and the Device Reset
Timer (see Section 7.5 “Device Reset Timer (DRT)”)
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 18 ms, it will reset the
Reset latch and thus end the on-chip Reset signal.
7.3.2
MCLR ENABLE
This configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD and the pin is assigned to be a I/O. See Figure 7-7.
FIGURE 7-7:
MCLR SELECT
A power-up example where MCLR is held low is shown
in Figure 7-9. VDD is allowed to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset TDRT msec after MCLR goes high.
GPWU/RBWU
(GP3/RB3)/MCLR/VPP
In Figure 7-10, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together or the pin
is programmed to be (GP3/RB3). The VDD is stable
before the Start-up timer times out and there is no prob-
lem in getting a proper Reset. However, Figure 7-11
depicts a problem situation where VDD rises too slowly.
The time between when the DRT senses that MCLR is
high and when MCLR and VDD actually reach their full
value, is too long. In this situation, when the start-up
timer times out, VDD has not reached the VDD (min)
value and the chip may not function correctly. For such
situations, we recommend that external RC circuits be
used to achieve longer POR delay times (Figure 7-10).
Internal MCLR
MCLRE
7.4
Power-on Reset (POR)
The PIC12F508/509/16F505 devices incorporate an
on-chip Power-on Reset (POR) circuitry, which
provides an internal chip Reset for most power-up
situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper oper-
ation. To take advantage of the internal POR, program
the (GP3/RB3)/MCLR/VPP pin as MCLR and tie
through a resistor to VDD, or program the pin as (GP3/
RB3). An internal weak pull-up resistor is implemented
using a transistor (refer to Table 10-2 for the pull-up
resistor ranges). This will eliminate external RC compo-
nents usually needed to create a Power-on Reset. A
maximum rise time for VDD is specified. See
Section 10.0 “Electrical Characteristics” for details.
Note:
When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
For additional information, refer to Application Notes
AN522 “Power-Up Considerations” (DS00522) and
AN607 “Power-up Trouble Shooting” (DS00607).
When the devices start normal operation (exit the
Reset condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 7-8.
DS41236A-page 46
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
FIGURE 7-8:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
VDD
Power-up
Detect
POR (Power-on Reset)
MCLR Reset
(GP3/RB3)/MCLR/VPP
S
R
Q
Q
MCLRE
WDT Reset
WDT Time-out
Start-up Timer
CHIP Reset
(10 µs or 18 ms)
Pin Change
Sleep
Wake-up on pin Change Reset
FIGURE 7-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
FIGURE 7-10:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 47
PIC12F508/509/16F505
FIGURE 7-11:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
V1
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
Note:
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
DS41236A-page 48
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
TABLE 7-6:
DRT (DEVICE RESET TIMER
PERIOD)
7.5
Device Reset Timer (DRT)
On the PIC12F508/509/16F505 devices, the DRT runs
any time the device is powered up. DRT runs from
Reset and varies based on oscillator selection and
Reset type (see Table 7-6).
Oscillator
Configuration
Subsequent
POR Reset
Resets
INTOSC, EXTRC 18 ms (typical) 10 µs (typical)
The DRT operates on an internal RC oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows VDD to rise above VDD min. and
for the oscillator to stabilize.
HS(1), XT, LP
EC(1)
18 ms (typical) 18 ms (typical)
18 ms (typical) 10 µs (typical)
Note 1: PIC16F505 only.
Oscillator circuits based on crystals or ceramic resona-
tors require a certain time after power-up to establish a
stable oscillation. The on-chip DRT keeps the devices in
a Reset condition for approximately 18 ms after MCLR
7.6.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the Option register. Thus, a time-out period of
a nominal 2.3 seconds can be realized. These periods
vary with temperature, VDD and part-to-part process
variations (see DC specs).
has reached
a
logic high (VIH MCLR) level.
Programming (GP3/RB3)/MCLR/VPP as MCLR and
using an external RC network connected to the MCLR
input is not required in most cases. This allows savings
in cost-sensitive and/or space restricted applications, as
well as allowing the use of the (GP3/RB3)/MCLR/VPP
pin as a general purpose input.
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
The Device Reset Time delays will vary from chip-to-
chip due to VDD, temperature and process variation.
See AC parameters for details.
7.6.2
WDT PROGRAMMING
CONSIDERATIONS
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 7.9.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
7.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the (GP5/RB5)/OSC1/CLKIN
pin and the internal 4 MHz oscillator. This means that
the WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset, generates a device Reset.
The TO bit (Status<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by program-
ming the configuration WDTE as a ‘0’ (see Section 7.1
“Configuration Bits”). Refer to the PIC12F508/509/
16F505 Programming Specifications to determine how
to access the configuration word.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 49
PIC12F508/509/16F505
FIGURE 7-12:
WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 6-5)
0
M
U
X
Postscaler
1
Watchdog
Time
8-to-1 MUX
PS<2:0>
PSA
WDT Enable
Configuration
(Figure 6-4)
To Timer0
Bit
0
1
MUX
PSA
WDT Time-out
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the Option register.
TABLE 7-7:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Value on
All Other
Resets
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On
Reset
N/A
N/A
OPTION(1) GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
OPTION(2) RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer. — = unimplemented, read as ‘0’, u= unchanged.
Note 1: PIC12F508/509 only.
2: PIC16F505 only.
DS41236A-page 50
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
FIGURE 7-14:
BROWN-OUT
PROTECTION CIRCUIT 2
7.7
Time-out Sequence, Power-down
and Wake-up from Sleep Status
Bits (TO, PD, GPWUF/RBWUF)
VDD
VDD
The TO, PD and (GPWUF/RBWUF) bits in the Status
register can be tested to determine if a Reset condition
has been caused by a Power-up condition, a MCLR or
Watchdog Timer (WDT) Reset.
R1
R2
PIC16F505
PIC12F508
PIC12F509
Q1
(2)
MCLR
(1)
40k
TABLE 7-8:
TO/PD/(GPWUF/RBWUF)
STATUS AFTER RESET
GPWUF/
RBWUF
TO PD
Reset Caused By
Note 1: This brown-out circuit is less expensive,
although less accurate. Transistor Q1 turns
off when VDD is below a certain level such
that:
0
0
0
0
0
u
WDT wake-up from Sleep
WDT time-out (not from
Sleep)
R1
= 0.7V
VDD •
0
0
0
1
1
1
u
1
0
1
u
0
MCLR wake-up from Sleep
Power-up
R1 + R2
2: Pin must be confirmed as MCLR.
MCLR not during Sleep
Wake-up from Sleep on pin
change
FIGURE 7-15:
BROWN-OUT
PROTECTION CIRCUIT 3
Legend: u= unchanged
VDD
Note 1: The TO, PD and GPWUF/RBWUF bits
maintain their status (u) until a Reset
occurs. A low-pulse on the MCLR input
does not change the TO, PD and
MCP809
VDD
Bypass
Capacitor
VSS
VDD
GPWUF/RBWUF status bits.
RST
MCLR
7.8
Reset on Brown-out
PIC16F505
PIC12F508
PIC12F509
A Brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
Brown-out.
Note:
This Brown-out Protection circuit employs
Microchip Technology’s MCP809 micro-
controller supervisor. There are 7 different
trip point selections to accommodate 5V to
3V systems.
To reset PIC12F508/509/16F505 devices when a
Brown-out occurs, external Brown-out protection
circuits may be built, as shown in Figure 7-13 and
Figure 7-14.
FIGURE 7-13:
BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
33k
PIC16F505
PIC12F508
PIC12F509
Q1
(2)
MCLR
10k
(1)
40k
Note 1: This circuit will activate Reset when VDD goes
below Vz + 0.7V (where Vz = Zener voltage).
2: Pin must be confirmed as MCLR.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 51
PIC12F508/509/16F505
7.9
Power-down Mode (Sleep)
7.10 Program Verification/Code
Protection
A device may be powered down (Sleep) and later
powered up (wake-up from Sleep).
If the code protection bit has not been programmed, the
on-chip program memory can be read out for
verification purposes.
7.9.1
SLEEP
The Power-down mode is entered by executing a
SLEEPinstruction.
The first 64 locations and the last location (OSCCAL)
can be read, regardless of the code protection bit
setting.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (Status<4>) is set, the PD bit
(Status<3>) is cleared and the oscillator driver is turned
off. The I/O ports maintain the status they had before
the SLEEP instruction was executed (driving high,
driving low or high-impedance).
The last memory location can be read regardless of the
code protection bit setting on the PIC12F508/509/
16F505 devices.
7.11 ID Locations
Note:
A Reset generated by a WDT time-out
does not drive the MCLR pin low.
Four memory locations are designated as ID locations
where the user can store checksum or other code
identification numbers. These locations are not
accessible during normal execution, but are readable
and writable during program/verify.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
(GP3/RB3)/MCLR/VPP pin must be at a logic high
level if MCLR is enabled.
Use only the lower 4 bits of the ID locations and always
program the upper 8 bits as ‘0’s.
7.9.2
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of
the following events:
7.12 In-Circuit Serial Programming™
The PIC12F508/509/16F505 microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock and data,
and three other lines for power, ground and the
programming voltage. This allows customers to manu-
facture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware, or
a custom firmware, to be programmed.
1. An external reset input on (GP3/RB3)/MCLR/VPP
pin, when configured as MCLR.
2. A Watchdog Timer time-out Reset (if WDT was
enabled).
3. A change on input pin GP0/RB0, GP1/RB1,
GP3/RB3 or RB4 when wake-up on change is
enabled.
These events cause a device Reset. The TO, PD and
GPWUF/RBWUF bits can be used to determine the
cause of device Reset. The TO bit is cleared if a WDT
time-out occurred (and caused wake-up). The PD bit,
which is set on power-up, is cleared when SLEEP is
invoked. The GPWUF/RBWUF bit indicates a change
in state while in Sleep at pins GP0/RB0, GP1/RB1,
GP3/RB3 or RB4 (since the last file or bit operation on
GP/RB port).
The devices are placed into a Program/Verify mode by
holding the GP1/RB1 and GP0/RB0 pins low while rais-
ing the MCLR (VPP) pin from VIL to VIHH (see program-
ming
specification).
GP1/RB1
becomes
the
programming clock and GP0/RB0 becomes the
programming data. Both GP1/RB1 and GP0/RB0 are
Schmitt Trigger inputs in this mode.
After Reset, a 6-bit command is then supplied to the
device. Depending on the command, 14 bits of program
data are then supplied to or from the device, depending
if the command was a Load or a Read. For complete
details of serial programming, please refer to the
PIC12F508/509/16F505 Programming Specifications.
Note:
Caution: Right before entering Sleep,
read the input pins. When in Sleep, wake
up occurs when the values at the pins
change from the state they were in at the
last reading. If a wake-up on change
occurs and the pins are not read before re-
entering Sleep, a wake-up will occur
immediately even if no pins change while
in Sleep mode.
A typical In-Circuit Serial Programming connection is
shown in Figure 7-16.
The WDT is cleared when the device wakes from
Sleep, regardless of the wake-up source.
DS41236A-page 52
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
FIGURE 7-16:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
PIC16F505
PIC12F508
PIC12F509
External
Connector
Signals
+5V
0V
VDD
VSS
VPP
MCLR/VPP
GP1/RB1
GP0/RB0
CLK
Data I/O
VDD
To Normal
Connections
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 53
PIC12F508/509/16F505
NOTES:
DS41236A-page 54
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 µs.
8.0
INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC16 instruction is a 12-bit word divided into an
opcode, which specifies the instruction type, and one
or more operands which further specify the operation
of the instruction. The formats for each of the catego-
ries is presented in Figure 8-1, while the various
opcode fields are summarized in Table 8-1.
Figure 8-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal
number:
0xhhh
For byte-oriented instructions, ‘f’ represents a file reg-
ister designator and ‘d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
where ‘h’ signifies a hexadecimal digit.
FIGURE 8-1:
GENERAL FORMAT FOR
INSTRUCTIONS
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the result is placed
in the file register specified in the instruction.
Byte-oriented file register operations
11
6
5
d
4
0
OPCODE
f (FILE #)
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ‘f’ represents the number of the
file in which the bit is located.
d = 0for destination W
d = 1for destination f
f = 5-bit file register address
Bit-oriented file register operations
11 8 7
b (BIT #)
For literal and control operations, ‘k’ represents an
8 or 9-bit constant or literal value.
5
4
0
OPCODE
f (FILE #)
b = 3-bit bit address
f = 5-bit file register address
TABLE 8-1:
OPCODE FIELD
DESCRIPTIONS
Literal and control operations (except GOTO)
11
Field
Description
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
8
7
0
OPCODE
k (literal)
Bit address within an 8-bit file register
Literal field, constant data or label
k = 8-bit immediate value
Don’t care location (= 0or 1)
Literal and control operations – GOTOinstruction
11
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
9
8
0
OPCODE
k (literal)
d
Destination select;
d= 0(store result in W)
d= 1(store result in file register ‘f’)
Default is d= 1
k = 9-bit immediate value
label
TOS
PC
Label name
Top-of-Stack
Program Counter
Watchdog Timer counter
Time-out bit
WDT
TO
PD
Power-down bit
dest
Destination, either the W register or the specified
register file location
[
(
]
)
Options
Contents
→
Assigned to
Register bit field
In the set of
< >
italics User defined term (font is courier)
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 55
PIC12F508/509/16F505
TABLE 8-2:
INSTRUCTION SET SUMMARY
Description
12-Bit Opcode
MSb LSb
Mnemonic,
Operands
Status
Affected
Cycles
Notes
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
1
1
1
1
1
0001 11df ffff C, DC, Z 1, 2, 4
0001 01df ffff
0000 011f ffff
0000 0100 0000
0010 01df ffff
0000 11df ffff
0010 11df ffff
0010 10df ffff
0011 11df ffff
0001 00df ffff
0010 00df ffff
0000 001f ffff
0000 0000 0000
0011 01df ffff
0011 00df ffff
Z
Z
Z
Z
Z
None
Z
None
Z
2, 4
4
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1
2, 4
2, 4
2, 4
2, 4
2, 4
2, 4
1, 4
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
Z
None
None
C
–
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
2, 4
2, 4
C
0000 10df ffff C, DC, Z 1, 2, 4
0011 10df ffff
0001 10df ffff
None
Z
2, 4
2, 4
Exclusive OR W with f
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
0100 bbbf ffff
None
None
None
None
2, 4
2, 4
0101 bbbf ffff
0110 bbbf ffff
0111 bbbf ffff
1(2)
1(2)
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
k
k
–
k
k
k
–
k
–
f
AND literal with W
Call Subroutine
1
2
1
2
1
1
1
2
1
1
1
1110 kkkk kkkk
1001 kkkk kkkk
0000 0000 0100 TO, PD
101k kkkk kkkk
1101 kkkk kkkk
1100 kkkk kkkk
0000 0000 0010
1000 kkkk kkkk
Z
None
1
3
Clear Watchdog Timer
Unconditional branch
Inclusive OR literal with W
Move literal to W
Load Option register
Return, place literal in W
Go into Standby mode
Load TRIS register
None
Z
None
None
None
0000 0000 0011 TO, PD
0000 0000 0fff
1111 kkkk kkkk
None
Z
XORLW
k
Exclusive OR literal to W
Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for
GOTO. See Section 4.7 “Program Counter”.
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state
latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
DS41236A-page 56
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
ADDWF
Add W and f
BCF
Bit Clear f
Syntax:
[ label ] ADDWF f,d
0 ≤ f ≤ 31
Syntax:
[ label ] BCF f,b
Operands:
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
d
[0,1]
Operation:
(W) + (f) → (dest)
Operation:
0 → (f<b>)
Status Affected: C, DC, Z
Status Affected: None
Description:
Add the contents of the W register
Description:
Bit ‘b’ in register ‘f’ is cleared.
and register ‘f’. If ‘d’ is’0’, the result
is stored in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
ANDLW
AND literal with W
BSF
Bit Set f
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] BSF f,b
Operands:
Operation:
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
(W).AND. (k) → (W)
Operation:
1 → (f<b>)
Status Affected: Z
Status Affected: None
Description:
The contents of the W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC
Bit Test f, Skip if Clear
ANDWF
AND W with f
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] ANDWF f,d
0 ≤ f ≤ 31
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Operands:
d
[0,1]
Operation:
skip if (f<b>) = 0
Operation:
(W) .AND. (f) → (dest)
Status Affected: None
Status Affected: Z
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the
Description: The contents of the W register are
next instruction is skipped.
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
If bit ‘b’ is ‘0’, then the next instruc-
tion fetched during the current
instruction execution is discarded,
and a NOPis executed instead,
making this a 2-cycle instruction.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 57
PIC12F508/509/16F505
CLRW
Clear W
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] CLRW
None
Syntax:
[ label ] BTFSS f,b
Operands:
Operation:
Operands:
0 ≤ f ≤ 31
0 ≤ b < 7
00h → (W);
1 → Z
Operation:
skip if (f<b>) = 1
Status Affected:
Description:
Z
Status Affected: None
The W register is cleared. Zero bit
(Z) is set.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOPis executed instead,
making this a 2-cycle instruction.
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
CALL
Subroutine Call
[ label ] CALL k
0 ≤ k ≤ 255
Syntax:
Operands:
Operation:
Operands:
Operation:
00h → WDT;
0 → WDT prescaler (if assigned);
(PC) + 1→ Top-of-Stack;
k → PC<7:0>;
1 → TO;
1 → PD
(Status<6:5>) → PC<10:9>;
0 → PC<8>
Status Affected: TO, PD
Status Affected: None
Description:
The CLRWDTinstruction resets the
Description:
Subroutine call. First, return
WDT. It also resets the prescaler, if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
address (PC + 1) is pushed onto
the stack. The eight-bit immediate
address is loaded into PC
bits <7:0>. The upper bits
PC<10:9> are loaded from
Status<6:5>, PC<8> is cleared.
CALLis a two-cycle instruction.
CLRF
Clear f
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 31
Syntax:
[ label ] CLRF
0 ≤ f ≤ 31
f
Syntax:
Operands:
Operands:
Operation:
d
[0,1]
00h → (f);
1 → Z
Operation:
(f) → (dest)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ‘f’ are
cleared and the Z bit is set.
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
DS41236A-page 58
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
DECF
Decrement f
[ label ] DECF f,d
0 ≤ f ≤ 31
INCF
Increment f
Syntax:
Operands:
Syntax:
Operands:
[ label ] INCF f,d
0 ≤ f ≤ 31
d
[0,1]
d
[0,1]
Operation:
(f) – 1 → (dest)
Operation:
(f) + 1 → (dest)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
INCFSZ
Syntax:
Increment f, Skip if 0
[ label ] INCFSZ f,d
0 ≤ f ≤ 31
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 31
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) + 1 → (dest), skip if result = 0
Operation:
(f) – 1 → d; skip if result = 0
Status Affected: None
Status Affected: None
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, then the next
instruction, which is already
fetched, is discarded and a NOPis
executed instead making it a
two-cycle instruction.
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOPis executed
instead making it a two-cycle
instruction.
IORLW
Inclusive OR literal with W
[ label ] IORLW k
0 ≤ k ≤ 255
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 511
Syntax:
Syntax:
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
(W) .OR. (k) → (W)
Z
k → PC<8:0>;
Status<6:5> → PC<10:9>
Status Affected: None
The contents of the W register are
OR’ed with the eight bit literal ‘k’.
The result is placed in the
W register.
Description: GOTOis an unconditional branch.
The 9-bit immediate value is
loaded into PC bits <8:0>. The
upper bits of PC are loaded from
Status<6:5>. GOTOis a two-cycle
instruction.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 59
PIC12F508/509/16F505
IORWF
Inclusive OR W with f
[ label ] IORWF f,d
0 ≤ f ≤ 31
MOVWF
Syntax:
Move W to f
[ label ] MOVWF
0 ≤ f ≤ 31
Syntax:
f
Operands:
Operands:
Operation:
d
[0,1]
(W) → (f)
Operation:
(W).OR. (f) → (dest)
Status Affected: None
Status Affected:
Description:
Z
Description:
Move data from the W register to
register ‘f’.
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is placed back in register
‘f’.
MOVF
Move f
NOP
No Operation
[ label ] NOP
None
Syntax:
Operands:
[ label ] MOVF f,d
Syntax:
0 ≤ f ≤ 31
Operands:
Operation:
d
[0,1]
No operation
Operation:
(f) → (dest)
Status Affected: None
Status Affected:
Description:
Z
Description:
No operation.
The contents of register ‘f’ are
moved to destination ‘d’. If ‘d’ is ‘0’,
destination is the W register. If ‘d’
is ‘1’, the destination is file
register ‘f’. ‘d’ = 1is useful as a
test of a file register, since status
flag Z is affected.
MOVLW
Syntax:
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
OPTION
Syntax:
Load Option Register
[ label ] Option
None
Operands:
Operation:
Operands:
Operation:
(W) → Option
k → (W)
Status Affected: None
Description: The content of the W register is
Status Affected: None
Description:
The eight-bit literal ‘k’ is loaded
loaded into the Option register.
into the W register. The don’t cares
will assembled as ‘0’s.
DS41236A-page 60
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
RETLW
Return with Literal in W
[ label ] RETLW k
0 ≤ k ≤ 255
SLEEP
Enter SLEEP Mode
Syntax:
Syntax:
[label ]
SLEEP
Operands:
Operation:
Operands:
Operation:
None
k → (W);
TOS → PC
00h → WDT;
0 → WDT prescaler;
1 → TO;
Status Affected: None
0 → PD
Description:
The W register is loaded with the
Status Affected: TO, PD, RBWUF
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address). This
is a two-cycle instruction.
Description:
Time-out Status bit (TO) is set. The
Power-down Status bit (PD) is
cleared.
RBWUF is unaffected.
The WDT and its prescaler are
cleared.
The processor is put into Sleep
mode with the oscillator stopped.
See Section 7.9 “Power-down
Mode (Sleep)” on Sleep for more
details.
RLF
Rotate Left f through Carry
SUBWF
Subtract W from f
Syntax:
Operands:
[ label ]
RLF f,d
Syntax:
[label ] SUBWF f,d
0 ≤ f ≤ 31
0 ≤ f ≤ 31
d
[0,1]
Operands:
d
[0,1]
Operation:
See description below
C
Operation:
(f) – (W) → (dest)
Status Affected:
Description:
Status Affected: C, DC, Z
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is stored back in reg-
ister ‘f’.
Description:
Subtract (2’s complement method)
the W register from register ‘f’. If ‘d’
is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
register ‘f’
C
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 31
SWAPF
Syntax:
Swap Nibbles in f
[ label ] SWAPF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
d
[0,1]
Operands:
d
[0,1]
Operation:
See description below
C
Operation:
(f<3:0>) → (dest<7:4>);
(f<7:4>) → (dest<3:0>)
Status Affected:
Description:
The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
register ‘f’
C
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 61
PIC12F508/509/16F505
TRIS
Load TRIS Register
XORWF
Syntax:
Exclusive OR W with f
[ label ] XORWF f,d
0 ≤ f ≤ 31
Syntax:
[ label ] TRIS
f
Operands:
Operation:
f = 6
Operands:
d
[0,1]
(W) → TRIS register f
Status Affected: None
Operation:
(W) .XOR. (f) → (dest)
Description:
TRIS register ‘f’ (f = 6 or 7) is
loaded with the contents of the W
register
Status Affected:
Description:
Z
Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
XORLW
Exclusive OR literal with W
Syntax:
[label ] XORLW k
0 ≤ k ≤ 255
Operands:
Operation:
(W) .XOR. k → (W)
Z
Status Affected:
Description:
The contents of the W register are
XOR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
DS41236A-page 62
Preliminary
2004 Microchip Technology Inc.
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9.1
MPLAB Integrated Development
Environment Software
9.0
DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• An interface to debugging tools
- simulator
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
- programmer (sold separately)
- emulator (sold separately)
MPLIBTM Object Librarian
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
• Customizable data windows with direct edit of
contents
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
• Emulators
• High level source code debugging
• Mouse over variable inspection
• Extensive on-line help
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
- MPLAB ICD 2
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Development Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM Demonstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
• Debug using:
- source files (assembly or C)
- absolute listing file (mixed assembly and C)
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increasing flexibility
and power.
9.2
MPASM Assembler
®
- KEELOQ
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
- PICDEM MSC
- microID®
- CAN
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol ref-
erence, absolute LST files that contain source lines and
generated machine code and COFF files for
debugging.
- PowerSmart®
- Analog
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User defined macros to streamline assembly code
• Conditional assembly for multi-purpose source
files
• Directives that allow complete control over the
assembly process
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 63
PIC12F508/509/16F505
9.3
MPLAB C17 and MPLAB C18
C Compilers
9.6
MPLAB ASM30 Assembler, Linker,
and Librarian
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
C
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
9.4
MPLINK Object Linker/
MPLIB Object Librarian
• Rich directive set
• Flexible macro language
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from pre-compiled libraries, using
directives from a linker script.
• MPLAB IDE compatibility
9.7
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The execu-
tion can be performed in Single-Step, Execute Until
Break, or Trace mode.
The MPLIB object librarian manages the creation and
modification of library files of pre-compiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
9.5
MPLAB C30 C Compiler
9.8
MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command-
line options and language extensions to take full
advantage of the dsPIC30F device hardware capabili-
ties, and afford fine control of the compiler code
generator.
The MPLAB SIM30 software simulator allows code
development in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been vali-
dated and conform to the ANSI C library standard. The
library includes functions for string manipulation,
dynamic memory allocation, data conversion, time-
keeping, and math functions (trigonometric, exponen-
tial and hyperbolic). The compiler provides symbolic
information for high level source debugging with the
MPLAB IDE.
DS41236A-page 64
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
9.9
MPLAB ICE 2000
9.11 MPLAB ICD 2 In-Circuit Debugger
High Performance Universal
In-Circuit Emulator
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low cost, run-time development tool,
connecting to the host PC via an RS-232 or high speed
USB interface. This tool is based on the FLASH
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the FLASH devices. This feature, along with
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM
)
protocol, offers cost effective in-circuit FLASH debug-
ging from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
9.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify, and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
9.10 MPLAB ICE 4000
High Performance Universal
In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for high-
end PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
9.13 PICSTART Plus Development
Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, up to 2 Mb of emulation memory, and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were cho-
sen to best make these features available in a simple,
unified application.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 65
PIC12F508/509/16F505
9.14 PICDEM 1 PICmicro
Demonstration Board
9.17 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 1 demonstration board demonstrates the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provided with the PICDEM 1 demonstration board can
be programmed with a PRO MATE II device program-
mer, or a PICSTART Plus development programmer.
The PICDEM 1 demonstration board can be connected
to the MPLAB ICE in-circuit emulator for testing. A pro-
totype area extends the circuitry for additional applica-
tion components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
9.18 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capa-
bilities of the 8-, 14-, and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320 fam-
ily of microcontrollers. PICDEM 4 is intended to show-
case the many features of these low pin count parts,
including LIN and Motor Control using ECCP. Special
provisions are made for low power operation with the
supercapacitor circuit, and jumpers allow on-board
hardware to be disabled to eliminate current draw in
this mode. Included on the demo board are provisions
for Crystal, RC or Canned Oscillator modes, a five volt
regulator for use with a nine volt wall adapter or battery,
DB-9 RS-232 interface, ICD connector for program-
ming via ICSP and development with MPLAB ICD 2,
2x16 liquid crystal display, PCB footprints for H-Bridge
motor driver, LIN transceiver and EEPROM. Also
included are: header for expansion, eight LEDs, four
potentiometers, three push buttons and a prototyping
area. Included with the kit is a PIC16F627A and a
PIC18F1320. Tutorial firmware is included along with
the User’s Guide.
9.15 PICDEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface con-
nector, an Ethernet interface, RS-232 interface, and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jeremy Bentham.
9.19 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A pro-
grammed sample is included. The PRO MATE II device
programmer, or the PICSTART Plus development pro-
grammer, can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board FLASH memory. A
generous prototype area is available for user hardware
expansion.
9.16 PICDEM 2 Plus
Demonstration Board
The PICDEM 2 Plus demonstration board supports
many 18-, 28-, and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the neces-
sary hardware and software is included to run the dem-
onstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device program-
mer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display, a piezo speaker, an on-board temperature
sensor, four LEDs, and sample PIC18F452 and
PIC16F877 FLASH microcontrollers.
DS41236A-page 66
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
9.20 PICDEM 18R PIC18C601/801
Demonstration Board
9.23 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/De-multiplexed and 16-bit
Memory modes. The board includes 2 Mb external
FLASH memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
The PICDEM USB Demonstration Board shows off the
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
9.24 Evaluation and
Programming Tools
In addition to the PICDEM series of circuits, Microchip
has a line of evaluation kits and demonstration software
for these products.
9.21 PICDEM LIN PIC16C43X
Demonstration Board
• KEELOQ evaluation and programming tools for
Microchip’s HCS Secure Data Products
The powerful LIN hardware and software kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 FLASH
microcontroller serves as the master. All three micro-
controllers are programmed with firmware to provide
LIN bus communication.
• CAN developers kit for automotive network
applications
• Analog design boards and filter design software
• PowerSmart battery charging evaluation/
calibration kits
• IrDA® development kit
• microID development and rfLabTM development
software
• SEEVAL® designer kit for memory evaluation and
endurance calculations
9.22 PICkitTM 1 Flash Starter Kit
A complete “development system in a box”, the PICkit
FLASH Starter Kit includes a convenient multi-section
board for programming, evaluation, and development
of 8/14-pin FLASH PIC® microcontrollers. Powered via
USB, the board operates under a simple Windows GUI.
The PICkit 1 Starter Kit includes the user’s guide (on
CD ROM), PICkit 1 tutorial software and code for vari-
ous applications. Also included are MPLAB® IDE (Inte-
grated Development Environment) software, software
and hardware “Tips ‘n Tricks for 8-pin FLASH PIC®
Microcontrollers” Handbook and a USB Interface
Cable. Supports all current 8/14-pin FLASH PIC
microcontrollers, as well as many future planned
devices.
• PICDEM MSC demo boards for Switching mode
power supply, high power IR driver, delta sigma
ADC, and flow rate sensor
Check the Microchip web page and the latest Product
Line Card for the complete list of demonstration and
evaluation kits.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 67
PIC12F508/509/16F505
NOTES:
DS41236A-page 68
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
10.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias..........................................................................................................-40°C to +125°C
Storage temperature ............................................................................................................................-65°C to +150°C
Voltage on VDD with respect to VSS ...............................................................................................................0 to +6.5V
Voltage on MCLR with respect to VSS..........................................................................................................0 to +13.5V
Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ..................................................................................................................................800 mW
Max. current out of VSS pin ................................................................................................................................200 mA
Max. current into VDD pin...................................................................................................................................150 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...........................................................................................................±20 mA
Max. output current sunk by any I/O pin ..............................................................................................................25 mA
Max. output current sourced by any I/O pin.........................................................................................................25 mA
Max. output current sourced by I/O port ..............................................................................................................75 mA
Max. output current sunk by I/O port ...................................................................................................................75 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 69
PIC12F508/509/16F505
FIGURE 10-1:
PIC12F508/509/16F505 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
6.0
5.5
5.0
4.5
4.0
3.5
VDD
(Volts)
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
FIGURE 10-2:
MAXIMUM OSCILLATOR FREQUENCY TABLE
LP
XT
INTOSC
XTRC
EC
HS
0
200 kHz
4 MHz
20 MHz
Frequency (MHz)
DS41236A-page 70
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
10.1 DC Characteristics: PIC12F508/509/16F505 (Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min Typ(1) Max Units
Conditions
See Figure 10-1
D001
D002
VDD
VDR
Supply Voltage
RAM Data Retention Voltage(2)
2.0
—
5.5
—
V
V
V
1.5*
Vss
Device in Sleep mode
D003 VPOR VDD Start Voltage to ensure
—
—
See Section 7.4 "DC Characteris-
tics" for details
Power-on Reset
D004 SVDD VDD Rise Rate to ensure
0.05
*
—
—
V/ms See Section 7.4 "DC Characteris-
tics" for details
Power-on Reset
D010
IDD
Supply Current(3)
—
—
—
—
170
0.4
1.7
15
TBD
TBD
TBD
TBD
µA
mA
mA
µA
FOSC = 4 MHz, VDD = 2.0V(4)
FOSC = 10 MHz, VDD = 3.0V
FOSC = 20 MHz, VDD = 5.0V
FOSC = 32 kHz, VDD = 2.0V, WDT
disabled
D020
IPD
Power-down Current(5)
—
—
0.1
1.0
TBD
TBD
µA
µA
VDD = 2.0V
VDD = 2.0V
D022 ∆IWDT WDT Current(5)
Legend: TBD = To Be Determined.
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in Sleep
mode.
4: Does not include current through REXT (in EXTRC mode only). The current through the resistor can be
estimated by the formula:
I = VDD/2REXT (mA) with REXT in kΩ.
5: The Power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 71
PIC12F508/509/16F505
10.2 DC Characteristics: PIC12F508/509/16F505 (Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +125°C (Extended)
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min Typ(1) Max Units
Conditions
See Figure 10-1
D001
D002
VDD
VDR
Supply Voltage
RAM Data Retention Voltage(2)
2.0
—
5.5
—
V
V
V
1.5*
Vss
Device in Sleep mode
D003 VPOR VDD Start Voltage to ensure
—
—
See Section 7.4 "DC Character-
istics" for details
Power-on Reset
D004 SVDD VDD Rise Rate to ensure
0.05*
—
—
V/ms See Section 7.4 "DC Character-
istics" for details
Power-on Reset
D010
IDD
Supply Current(3)
—
—
—
—
170
0.4
1.7
15
TBD
TBD
TBD
TBD
µA
FOSC = 4 MHz, VDD = 2.0V(4)
mA FOSC = 10 MHz, VDD = 3.0V
mA FOSC = 20 MHz, VDD = 5.0V
µA
FOSC = 32 kHz, VDD = 2.0V, WDT
disabled
D020
IPD
Power-down Current(5)
—
—
0.1
1.0
TBD
TBD
µA
µA
VDD = 2.0V
VDD = 2.0V
D022 ∆IWDT WDT Current(5)
Legend: TBD = To Be Determined.
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD,
MCLR = VDD;
WDT enabled/disabled as specified.
a) For standby current measurements, the conditions are the same, except that the device is in Sleep
mode.
4: Does not include current through REXT (in EXTRC mode only). The current through the resistor can be
estimated by the formula:
I = VDD/2REXT (mA) with REXT in kΩ.
5: The Power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS.
DS41236A-page 72
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
TABLE 10-1: DC CHARACTERISTICS: PIC12F508/509/16F505 (Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
Operating temperature -40°C ≤ TA ≤ +85°C (industrial)
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C (extended)
Operating voltage VDD range as described in DC specification
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
VIL Input Low Voltage
I/O ports:
D030
D030A
D031
D032
D033
D033
D033
with TTL buffer
Vss
Vss
Vss
Vss
Vss
Vss
Vss
—
—
—
—
—
—
—
0.8V
V
V
V
V
V
V
V
For all 4.5 ≤ VDD ≤ 5.5V
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
0.3
Otherwise
with Schmitt Trigger buffer
MCLR, T0CKI
OSC1 (in EXTRC)
OSC1 (in HS)
(Note1)
(Note1)
(Note1)
OSC1 (in XT and LP)
VIH Input High Voltage
I/O ports:
—
—
—
D040
with TTL buffer
2.0
VDD
VDD
V
V
4.5 ≤ VDD ≤ 5.5V
D040A
0.25 VDD
+ 0.8 VDD
Otherwise
D041
D042
D043
D043
D043
D070
with Schmitt Trigger buffer
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
1.6
—
—
VDD
VDD
VDD
VDD
VDD
TBD
V
V
For entire VDD range
MCLR, T0CKI
OSC1 (in EXTRC)
—
V
(Note1)
(Note1)
OSC1 (in HS)
—
V
OSC1 (in XT and LP)
IPUR GPIO weak pull-up current(4)
—
V
TBD
250
µA
VDD = 5V, VPIN = VSS
IIL
Input Leakage Current(2), (3)
D060
D061
D061A
D063
I/O ports
—
—
—
—
—
—
—
—
± 1
± 30
± 5
µA
µA
µA
µA
Vss ≤ VPIN ≤ VDD, Pin at high-impedance
Vss ≤ VPIN ≤ VDD
GP3/RB3/MCLRI(5)
GP3/RB3/MCLRI(6)
OSC1
Vss ≤ VPIN ≤ VDD
± 5
Vss ≤ VPIN ≤ VDD, XT, HS and LP oscillator
configuration
Output Low Voltage
D080
I/O ports/CLKOUT
—
—
—
—
—
—
—
—
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V, -40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V, -40°C to +125°C
D080A
D083
OSC2
D083A
Output High Voltage
D090
I/O ports/CLKOUT(3)
VDD – 0.7
VDD – 0.7
VDD – 0.7
VDD – 0.7
—
—
—
—
—
—
—
—
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V, -40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V, -40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V, -40°C to +125°C
D090A
D092
OSC2
D092A
Capacitive Loading Specs on
Output Pins
D100
OSC2 pin
—
—
—
—
15
50
pF
pF
In XT, HS and LP modes when external clock is
used to drive OSC1.
D101
All I/O pins and OSC2
Legend:
TBD = To Be Determined.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F508/509/
16F505 be driven with external clock in RC mode.
Note 1:
2:
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating
conditions. Higher leakage current may be measured at different input voltages.
3:
4:
5:
Negative current is defined as coming out of the pin.
Does not include GP3/RB3. For GP3/RB3 see parameters D061 and D061A.
This specification applies to GP3/RB3/MCLR configured as external MCLR and GP3/RB3/MCLR configured as input with internal pull-up
enabled.
6:
This specification applies when GP3/RB3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit
is higher than the standard I/O logic.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 73
PIC12F508/509/16F505
TABLE 10-2: PULL-UP RESISTOR RANGES – PIC12F508/509/16F505
VDD (Volts)
Temperature (°C)
Min
Typ
Max
Units
RB0/RB1/RB4
2.0
-40
25
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
85
125
-40
25
5.5
85
125
RB3
2.0
-40
25
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
85
125
-40
25
5.5
85
125
Legend: TBD = To Be determined.
These parameters are characterized but not tested.
*
DS41236A-page 74
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
10.3 Timing Parameter Symbology and Load Conditions – PIC12F508/509/16F505
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T Time
Lowercase subscripts (pp) and their meanings:
pp
2
to
mc
osc
os
MCLR
ck
cy
drt
io
CLKOUT
Cycle time
Device Reset Timer
I/O port
Oscillator
OSC1
t0
T0CKI
wdt
Watchdog Timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (high-impedance)
Low
Valid
L
High-impedance
FIGURE 10-3:
LOAD CONDITIONS – PIC12F508/509/16F505
Legend:
CL
CL = 50 pF for all pins except OSC2
pin
15 pF for OSC2 in XT, HS or LP
modes when external clock
is used to drive OSC1
VSS
FIGURE 10-4:
EXTERNAL CLOCK TIMING – PIC12F508/509/16F505
Q4
Q3
Q4
Q1
Q1
Q2
OSC1
1
3
3
4
4
2
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 75
PIC12F508/509/16F505
TABLE 10-3: EXTERNAL CLOCK TIMING REQUIREMENTS – PIC12F508/509/16F505
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1 "DC
Characteristics"
Param
Sym
Characteristic
Min Typ(1)
Max Units
Conditions
No.
1A
FOSC External CLKIN Frequency(2) DC
DC
—
—
4
MHz XT Oscillator mode
20
MHz HS Oscillator mode (PIC16F505
only)
DC
—
—
—
—
200
4
kHz LP Oscillator mode
MHz EXTRC Oscillator mode
MHz XT Oscillator mode
Oscillator Frequency(2)
—
0.1
4
4
20
MHz HS Oscillator mode (PIC16F505
only)
—
250
50
—
—
—
200
—
kHz LP Oscillator mode
ns XT Oscillator mode
1
TOSC
External CLKIN Period(2)
Oscillator Period(2)
—
ns HS Oscillator mode (PIC16F505
only)
5
—
—
—
—
—
µs LP Oscillator mode
250
250
ns EXTRC Oscillator mode
10,000 ns XT Oscillator mode
50
5
—
—
250
ns HS Oscillator mode (PIC16F505
only)
—
—
µs LP Oscillator mode
ns
2
3
TCY
Instruction Cycle Time
200 4/FOSC
TosL, Clock in (OSC1) Low or High 50*
TosH Time
—
—
—
—
—
—
—
ns XT Oscillator
2*
—
µs LP Oscillator
10*
—
ns HS Oscillator (PIC16F505 only)
ns XT Oscillator
4
TosR, Clock in (OSC1) Rise or Fall
TosF Time
—
—
—
25*
50*
15*
ns LP Oscillator
ns HS Oscillator (PIC16F505 only)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption. When an external clock
input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
DS41236A-page 76
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
TABLE 10-4: CALIBRATED INTERNAL RC FREQUENCIES – PIC12F508/509/16F505
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),
-40°C ≤ TA ≤ +125°C (extended)
AC CHARACTERISTICS
Operating Voltage VDD range is described in
Section 10.1 "DC Characteristics"
Param
Freq
Tolerance
Sym
Characteristic
Min Typ†
Max Units
Conditions
No.
F10
FOSC
Internal Calibrated
± 1%
TBD 4.00
TBD MHz VDD and Temperature
TBD
INTOSC Frequency(1)
± 2%
± 5%
TBD 4.00
TBD 4.00
TBD MHz 2.5V ≤ VDD ≤ 5.5V
0°C ≤ TA ≤ +85°C
TBD MHz 2.0V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (Ind.)
-40°C ≤ TA ≤ +125°C (Ext.)
Legend: TBD = To Be Determined.
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.
FIGURE 10-5:
I/O TIMING – PIC12F508/509/16F505
Q1
Q4
Q2
Q3
OSC1
I/O Pin
(input)
17
18
19
I/O Pin
(output)
New Value
Old Value
20, 21
Note:
All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 77
PIC12F508/509/16F505
TABLE 10-5: TIMING REQUIREMENTS – PIC12F508/509/16F505
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1 "DC Characteristics"
AC
CHARACTERISTIC
S
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
17
TOSH2IOV OSC1↑ (Q1 cycle) to Port Out Valid(2), (3)
TOSH2IOI OSC1↑ (Q2 cycle) to Port Input Invalid (I/O in hold time)(2) TBD
—
—
—
—
10
10
100*
—
ns
ns
ns
ns
ns
18
19
20
21
TIOV2OSH Port Input Valid to OSC1↑ (I/O in setup time)
TBD
—
—
TIOR
TIOF
Port Output Rise Time(3)
Port Output Fall Time(3)
25**
25**
—
Legend: TBD = To Be Determined.
*
These parameters are characterized but not tested.
** These parameters are design targets and are not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: Measurements are taken in EXTRC mode.
3: See Figure 10-3 for loading conditions.
FIGURE 10-6:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING –
PIC12F508/509/16F505
VDD
MCLR
30
Internal
POR
32
32
32
DRT
(2)
Timeout
Internal
Reset
Watchdog
Timer
Reset
31
34
34
(1)
I/O pin
Note 1: I/O pins must be taken out of High-impedance mode by enabling the output drivers in software.
2: Runs in MCLR or WDT Reset only in XT, LP and HS (PIC16F505) modes.
DS41236A-page 78
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
TABLE 10-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC12F508/509/16F505
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in
Section 10.1 "DC Characteristics"
Param
Sym
No.
Characteristic
Min Typ(1) Max Units
Conditions
VDD = 5.0V
30
31
TMCL MCLR Pulse Width (low)
2000*
—
—
ns
TWDT Watchdog Timer Time-out Period
(no prescaler)
9*
9*
18*
18*
30*
40*
ms
ms
VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
32
34
TDRT
Device Reset Timer Period(2)
9*
9*
18*
18*
30*
40*
ms
ms
VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
TIOZ
I/O High-impedance from MCLR
low
—
—
2000*
ns
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 79
PIC12F508/509/16F505
FIGURE 10-7:
TIMER0 CLOCK TIMINGS – PIC12F508/509/16F505
T0CKI
40
41
42
TABLE 10-7: TIMER0 CLOCK REQUIREMENTS – PIC12F508/509/16F505
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
AC CHARACTERISTICS
Operating Voltage VDD range is described in
Section 10.1 "DC Characteristics"
Param
Sym
No.
Characteristic
No Prescaler
Min
Typ(1) Max Units
Conditions
40
41
42
Tt0H T0CKI High Pulse
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Width
With Prescaler
No Prescaler
With Prescaler
Tt0L T0CKI Low Pulse
Width
0.5 TCY + 20*
10*
Tt0P T0CKI Period
20 or TCY + 40* N
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS41236A-page 80
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
11.0 DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Graphs and charts are not available at this time.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 81
PIC12F508/509/16F505
NOTES:
DS41236A-page 82
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
12.0 PACKAGING INFORMATION
12.1 Package Marking Information
8-Lead PDIP
Example
12F508-I
/P017
XXXXXXXX
XXXXXNNN
YYWW
0410
8-Lead SOIC (.150”)
Example
XXXXXXXX
XXXXYYWW
12F509-I
/SN0410
NNN
017
8-Lead MSOP
Example
12F509
0431017
XXXXXX
YWWNNN
Legend: XX...X Customer specific information*
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 83
PIC12F508/509/16F505
12.1 Package Marking Information (Cont’d)
14-Lead PDIP (300 mil)
Example
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
PIC16F505-I/PG
0215
0410017
YYWWNNN
Example
14-Lead SOIC (150 mil)
PIC16F505-E
/SLG0125
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
0431017
Example
16F505-I
14-Lead TSSOP (150 mil)
XXXXXXXX
YYWW
0431
017
NNN
DS41236A-page 84
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 85
PIC12F508/509/16F505
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS41236A-page 86
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
1
B
n
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
INCHES
NOM
MILLIMETERS*
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.026 BSC
0.65 BSC
Overall Height
A
A2
A1
E
-
-
.043
-
-
0.85
-
1.10
Molded Package Thickness
Standoff
.030
.000
.033
-
.037
.006
0.75
0.95
0.15
0.00
Overall Width
.193 TYP.
4.90 BSC
Molded Package Width
Overall Length
E1
D
.118 BSC
.118 BSC
3.00 BSC
3.00 BSC
Foot Length
L
.016
.024
.037 REF
.031
0.40
0.60
0.95 REF
0.80
Footprint (Reference)
Foot Angle
F
φ
c
0°
.003
.009
5°
-
8°
.009
.016
15°
0°
0.08
0.22
5°
-
-
-
-
-
8°
0.23
0.40
15°
Lead Thickness
Lead Width
.006
B
α
β
.012
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
-
-
5°
15°
5°
15°
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-187
Drawing No. C04-111
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 87
PIC12F508/509/16F505
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
B1
β
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
0.38
7.62
6.10
18.80
3.18
0.20
1.14
0.36
7.87
5
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
5
.145
3.68
.313
.250
.750
.130
.012
.058
.018
.370
10
.325
.260
.760
.135
.015
.070
.022
.430
15
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS41236A-page 88
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
1
B
n
α
h
45°
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
1.27
Overall Height
A
.053
.052
.004
.228
.150
.337
.010
.016
0
.069
1.35
1.32
1.55
1.42
0.18
5.99
3.90
8.69
0.38
0.84
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.061
.010
.244
.157
.347
.020
.050
8
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
§
0.10
5.79
3.81
8.56
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 89
PIC12F508/509/16F505
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
A1
A2
β
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.026
0.65
Overall Height
A
.043
1.10
0.95
0.15
6.50
4.50
5.10
0.70
8
Molded Package Thickness
Standoff
A2
A1
E
.033
.002
.246
.169
.193
.020
0
.035
.004
.251
.173
.197
.024
4
.037
.006
.256
.177
.201
.028
8
0.85
0.05
0.90
0.10
6.38
4.40
5.00
0.60
4
§
Overall Width
6.25
4.30
4.90
0.50
0
Molded Package Width
Molded Package Length
Foot Length
E1
D
L
φ
Foot Angle
c
Lead Thickness
.004
.007
0
.006
.010
5
.008
.012
10
0.09
0.19
0
0.15
0.25
5
0.20
0.30
10
Lead Width
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
DS41236A-page 90
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
INDEX
Data Memory.............................................................. 16
Program Memory (PIC12F508/509) ........................... 15
Program Memory (PIC16F505) .................................. 16
MPLAB ASM30 Assembler, Linker, Librarian..................... 64
MPLAB ICD 2 In-Circuit Debugger ..................................... 65
MPLAB ICE 2000 High Performance Universal
In-Circuit Emulator..................................................... 65
MPLAB ICE 4000 High Performance Universal
In-Circuit Emulator..................................................... 65
MPLAB Integrated Development Environment Software.... 63
MPLINK Object Linker/MPLIB Object Librarian.................. 64
A
ALU ....................................................................................... 9
Assembler
MPASM Assembler..................................................... 63
B
Block Diagram
On-Chip Reset Circuit................................................. 47
Timer0......................................................................... 33
TMR0/WDT Prescaler................................................. 37
Watchdog Timer.......................................................... 50
Brown-Out Protection Circuit .............................................. 51
O
Option Register................................................................... 22
OSC selection..................................................................... 39
OSCCAL Register............................................................... 24
Oscillator Configurations..................................................... 41
Oscillator Types
C
C Compilers
MPLAB C17 ................................................................ 64
MPLAB C18 ................................................................ 64
MPLAB C30 ................................................................ 64
Carry ..................................................................................... 9
Clocking Scheme ................................................................ 14
Code Protection ............................................................ 39, 52
Configuration Bits................................................................ 39
Configuration Word ............................................................. 40
HS............................................................................... 41
LP ............................................................................... 41
RC .............................................................................. 41
XT............................................................................... 41
P
PIC12F508/509/16F505 Device Varieties ............................ 7
PICkit 1 FLASH Starter Kit.................................................. 67
PICSTART Plus Development Programmer....................... 65
POR
Device Reset Timer (DRT) ................................... 39, 49
PD............................................................................... 51
Power-on Reset (POR)............................................... 39
TO............................................................................... 51
PORTB ............................................................................... 29
Power-down Mode.............................................................. 52
Prescaler ............................................................................ 36
PRO MATE II Universal Device Programmer..................... 65
Program Counter................................................................ 25
D
DC and AC Characteristics................................................. 81
Demonstration Boards
PICDEM 1................................................................... 66
PICDEM 17................................................................. 66
PICDEM 18R PIC18C601/801.................................... 67
PICDEM 2 Plus........................................................... 66
PICDEM 3 PIC16C92X............................................... 66
PICDEM 4................................................................... 66
PICDEM LIN PIC16C43X ........................................... 67
PICDEM USB PIC16C7X5.......................................... 67
PICDEM.net Internet/Ethernet .................................... 66
Development Support ......................................................... 63
Digit Carry............................................................................. 9
Q
Q cycles.............................................................................. 14
E
Errata .................................................................................... 3
Evaluation and Programming Tools.................................... 67
R
RC Oscillator....................................................................... 42
Read-Modify-Write.............................................................. 31
Register File Map
F
Family of Devices
PIC12F508 ................................................................. 17
PIC12F509 ................................................................. 17
PIC16F505 ................................................................. 17
Registers
PIC16F505.................................................................... 5
FSR..................................................................................... 26
I
Special Function......................................................... 18
Reset .................................................................................. 39
Reset on Brown-Out ........................................................... 51
I/O Interfacing ..................................................................... 29
I/O Ports.............................................................................. 29
I/O Programming Considerations........................................ 31
ID Locations.................................................................. 39, 52
INDF.................................................................................... 26
Indirect Data Addressing..................................................... 26
Instruction Cycle ................................................................. 14
Instruction Flow/Pipelining .................................................. 14
Instruction Set Summary..................................................... 56
S
Sleep ............................................................................ 39, 52
Software Simulator (MPLAB SIM) ...................................... 64
Software Simulator (MPLAB SIM30) .................................. 64
Special Features of the CPU .............................................. 39
Special Function Registers................................................. 18
Stack................................................................................... 25
Status Register ............................................................... 9, 20
L
Loading of PC ..................................................................... 25
M
Memory Organization.......................................................... 15
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 91
PIC12F508/509/16F505
T
Timer0
Timer0.........................................................................33
Timer0 (TMR0) Module...............................................33
TMR0 with External Clock...........................................35
Timing Diagrams and Specifications...................................75
Timing Parameter Symbology and Load Conditions...........75
TRIS Registers....................................................................29
W
Wake-up from Sleep ...........................................................52
Watchdog Timer (WDT) ................................................ 39, 49
Period..........................................................................49
Programming Considerations .....................................49
WWW, On-Line Support........................................................3
Z
Zero bit..................................................................................9
DS41236A-page 92
Preliminary
2004 Microchip Technology Inc.
PIC12F508/509/16F505
ON-LINE SUPPORT
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
Microchip provides on-line support on the Microchip
World Wide Web site.
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits. The Hot Line
Numbers are:
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet
Web Site
042003
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2003 Microchip Technology Inc.
Preliminary
DS41236A-page 93
PIC12F508/509/16F505
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
Reader Response
Total Pages Sent ________
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
PIC12F508/509/16F505
DS41236A
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41236A-page 94
Preliminary
2003 Microchip Technology Inc.
PIC12F508/509/16F505
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
b)
c)
d)
e)
f)
PIC16F505-I/PG
package (Pb-free)
PIC16F505T-I/SLG = Industrial temp., SOIC
package (Pb-free), Tape and Reel
PIC16F505T-I/SLG = Industrial temp., SOIC
package (Pb-free), Tape and Reel
PIC12F508T-I/SNG = Industrial temp., 150 mil
SOIC package (Pb-free), Tape and Reel
PIC12F508T-E/MSG = Extended temp., MSOP
package (Pb-free), Tape and Reel
PIC12F509-E/PG
package (Pb-free)
= Industrial temp., PDIP
Device
PIC16F505
PIC12F508
PIC12F509
PIC16F505T (Tape & Reel)
PIC12F508T (Tape & Reel)
PIC12F509T (Tape & Reel)
= Extended temp., PDIP
g)
PIC12F509-I/SMG = Industrial temp., 208 mil
SOIC package (Pb-free)
Temperature Range
Package
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
PG
=
300 mil PDIP (Pb-free)
150 mil SOIC, 14-LD (Pb-free)
150 mil SOIC, 8-LD (Pb-free)
MSOP (Pb-free)
SLG
SNG
MSG
STG
=
=
=
=
TSSOP (Pb-free)
Pattern
Special Requirements
Note:
Tape and Reel available for only the following packages: SOIC, MSOP
and TSSOP.
2004 Microchip Technology Inc.
Preliminary
DS41236A-page 95
WORLDWIDE SALES AND SERVICE
China - Beijing
Korea
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: www.microchip.com
Unit 706B
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Wan Tai Bei Hai Bldg.
No. 6 Chaoyangmen Bei Str.
Beijing, 100027, China
Tel: 86-10-85282100
Fax: 86-10-85282104
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Singapore
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
China - Chengdu
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-86766200
Atlanta
3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: 770-640-0034
Fax: 770-640-0307
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Fax: 86-28-86766599
Boston
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Fuzhou
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506
Fax: 86-591-7503521
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848
Fax: 978-692-3821
Taiwan
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071
Fax: 630-285-0075
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Dallas
EUROPE
Austria
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Regus Business Centre
Lautrup hoj 1-3
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423
Fax: 972-818-2924
China - Shanghai
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250
Tel: 86-21-6275-5700
Fax: 86-21-6275-5060
China - Shenzhen
Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: 86-755-82901380
Fax: 86-755-8295-1393
China - Shunde
Fax: 248-538-2260
Ballerup DK-2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
Kokomo
France
2767 S. Albright Road
Kokomo, IN 46902
Tel: 765-864-8360
Fax: 765-864-8387
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Room 401, Hongjian Building, No. 2
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888
Fax: 949-263-1338
Fengxiangnan Road, Ronggui Town, Shunde
District, Foshan City, Guangdong 528303, China
Tel: 86-757-28395507 Fax: 86-757-28395571
Germany
China - Qingdao
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
San Jose
1300 Terra Bella Avenue
Mountain View, CA 94043
Tel: 650-215-1444
Italy
India
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-22290061 Fax: 91-80-22290062
Japan
Fax: 650-961-0286
Toronto
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
Waegenburghtplein 4
NL-5152 JR, Drunen, Netherlands
Tel: 31-416-690399
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Fax: 905-673-6509
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
ASIA/PACIFIC
Australia
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Fax: 31-416-690340
United Kingdom
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
05/28/04
DS41236A-page 96
Preliminary
2004 Microchip Technology Inc.
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