PD70210AL_技术文档

PD70211

PD Controller with Switching Regulator for AF/AT/UPOE/

HDBaseT/4-pair PoE Applications

Product Overview

Microchip's PD70211 is an advanced PD interface IC with integrated switching Pulse-Width Modulation (PWM)

regulator control for powered devices in PoE applications. It supports IEEE^®802.3af, IEEE 802at, HDBase-T, and

general 2/4-pair configurations.

The PD70211 front-end includes an advanced classification block that supports 2, 3, 4, and 6 event classification.

Using the SUPP_Sx pins, it also identifies the four pairs of cable that actually receive power and generate

appropriate flags.

The IC features an internal bleeder for discharging the input capacitor of the DC/DC converter rapidly to ensure fast

re-detection and port power-up, in case of a sudden removal and re-insertion of the Ethernet cable into the RJ-45.

The advanced PWM current-mode section supports synchronous Flyback and Active Clamp Forward topologies, as

well as Buck, Boost, and so on.

Features

The PD70211 device has the following key features.

•

Supports IEEE 802.3af/at, HDBaseT, and other 2-pair/4-pair configurations

Wall adapter support (Rear Aux method)

PD detection and programmable classification

2, 3, 4, and 6 event classification

Integrated 0.3Ω isolating (series-pass) FET

Inrush current limiting

Less than 10 µA offset current during detection

Advanced PWM section

Lead-free QFN-36 (6 mm × 6 mm) package

DS00003672A-page 1

Datasheet

PD70211

The following table lists the Microchip PD products offerings.

Table 1.ꢀMicrochip Powered Device Products Offerings

Part

Type

Package

IEEE

HDBase UPoE

802.3af 802.3at T (PoH)

PD70100

PD70101

PD70200

PD70201

PD70210

PD70210A

Front end

3 mm × 4 mm 12L DFN

5 mm × 5 mm 32L QFN

3 mm × 4 mm 12L DFN

5 mm × 5 mm 32L QFN

5 mm × 5 mm 16L DFN

4 mm × 5 mm 16L DFN

5 mm × 7 mm 38L QFN

6 mm × 6 mm 36L QFN

6 mm x 8 mm 40L QFN

x

—

x

—

x

—

x

Front end + PWM

Front end

Front end + PWM

Front end

x

Front end

x

PD70210AL Front end

x

PD70211

PD70224

Front end + PWM

Ideal Diode Bridge

x

Applications

The following are the applications of the PD70211 device.

•

HDBaseT up to 95W

IEEE 802.3af and IEEE 802at

Power forwarding

Indoor and outdoor PoE

DS00003672A-page 2

Datasheet

PD70211

The following figure shows a basic PD block diagram using PD70211.

Figure 1.ꢀBasic PD Block Diagram

Microchip offers complete reference design packages and Evaluation Boards (EVBs). For access to these design

packages, device datasheets, or application notes, consult your local Microchip Client Engagement Manager or visit

our website at www.microchip.com/poe. For technical support, consult your local consult your local Embedded

Solutions Engineers or go to microchipsupport.force.com/s/. For help in designing the dc/dc portion of your circuit,

see our MPLAB Analog Designer (MAD) tool at www.microchip.com/mad-poe.

DS00003672A-page 3

Datasheet

PD70211

Table of Contents

Product Overview...........................................................................................................................................1

1.

2.

Features....................................................................................................................................... 1

Applications..................................................................................................................................2

1. Functional Descriptions...........................................................................................................................5

2. Electrical Specifications.......................................................................................................................... 7

2.1. Absolute Maximum Ratings..........................................................................................................7

2.2. Operating Ratings........................................................................................................................ 8

2.3. Thermal Properties.......................................................................................................................8

2.4. Electrical Characteristics..............................................................................................................9

3. Pin Configuration...................................................................................................................................16

4. Package Specifications.........................................................................................................................22

4.1. Recommended PCB Layout.......................................................................................................23

5. Applications Information........................................................................................................................24

5.1. Peripheral Devices..................................................................................................................... 24

5.2. Setting Switching Frequency......................................................................................................24

5.3. Setting Soft-Start........................................................................................................................24

5.4. Setting Pulse-skip Mode Threshold............................................................................................25

5.5. Setting UVLO/Hysteresis Thresholds.........................................................................................25

5.6. Setting the Voltage Divider for Output Rails...............................................................................26

5.7. Selecting the Sense Resistor..................................................................................................... 26

5.8. Operation with an External DC Source...................................................................................... 27

6. Ordering Information............................................................................................................................. 30

7. Reference Documents.......................................................................................................................... 31

8. Revision History.................................................................................................................................... 32

The Microchip Website.................................................................................................................................33

Product Change Notification Service............................................................................................................33

Customer Support........................................................................................................................................ 33

Microchip Devices Code Protection Feature................................................................................................33

Legal Notice................................................................................................................................................. 34

Trademarks.................................................................................................................................................. 34

Quality Management System....................................................................................................................... 35

Worldwide Sales and Service.......................................................................................................................36

DS00003672A-page 4

Datasheet

PD70211

Functional Descriptions

1.

Functional Descriptions

The following figures show the functional blocks of the PD70211 device.

Figure 1-1.ꢀPD70211 Block Diagram (Front-End Section)

DS00003672A-page 5

Datasheet

PD70211

Functional Descriptions

Figure 1-2.ꢀPD70211 Block Diagram (PWM Section)

DS00003672A-page 6

Datasheet

PD70211

Electrical Specifications

2.

Electrical Specifications

The following sections describe the electrical specifications of the PD70211 device.

2.1

Absolute Maximum Ratings

Performance is not necessarily guaranteed over this entire range. These are maximum stress ratings only. Exceeding

these ratings, even momentarily, can cause immediate damage or negatively impact long-term operating reliability.

Voltages are with respect to IC ground (VPN_IN).

Table 2-1.ꢀAbsolute Maximum Ratings

Parameter

Min

–0.3

0

Max

Units

VPP, VPN_OUT, RDET

AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG

SUPP_S1, SUPP_S2

RREF, RCLS, WA_EN

VAUX_VCC

74

V

20

V_VPP+ 1.5

–0.3

0.3

5

20

6

PG, SG

VL

VH (with respect to VAUX_VCC)

ENABLE

–6

All other pins

–0.3

–40

—

VL + 0.3

150

V

Junction temperature

Lead soldering temperature (40 s, reflow)

Storage temperature, MSL3

°C

kV

V

260

–65

—

150

ESD rating

HBM

MM

±1.5¹

±50

—

CDM

—

±500

V

Note:ꢀ

1. The VPP, VAUX/VCC, and RREF pins pass ±1 kV HBM only.

DS00003672A-page 7

Datasheet

PD70211

Electrical Specifications

2.2

Operating Ratings

Performance is generally guaranteed over this range, as detailed in the 2.4.1 Electrical Characteristics of Front-End

Section. Voltages are with respect to IC ground (VPN_IN).

Table 2-2.ꢀOperating Ratings of Front-End Section

Parameter

Min

0

Max

57

Units

V

VPP

Ambient temperature¹

Detection range

Mark event range

Class event range

–40

1.1

4.9

13.7

85

°C

V

10.1

20.9

V

Note:ꢀ

1. The corresponding maximum operating junction temperature is 125 °C.

Performance is generally guaranteed over the range, as detailed in the 2.4.2 Electrical Characteristics of PWM

Section. Voltages are with respect to IC ground.

Table 2-3.ꢀOperating Ratings of PWM Section

Parameter

Min

7.8

100

—

Max

20

Units

V

VCC

F_SW(Adjustable Frequency Range)

Maximum duty cycle

500

44.5

1000

kHz

%

f_{sw_synch}(Synchronization Frequency Range)

200

kHz

2.3

Thermal Properties

The following table lists the thermal specifications of the PD70211 device.

Table 2-4.ꢀThermal Properties

Thermal Resistance

Min

—

Typ

22.3

3

Max

—

Units

θ_JA

θ_JP

θ_JC

°C/W

—

°C/W

—

4

—

Note:ꢀ The θJx numbers assume no forced airflow. Junction temperature is calculated using T_J= T_A+ (P_Dx q_jA). In

particular, θ_JAis a function of the PCB construction. Published thermal resistance is for a four-layer board in

accordance with the JESD-51 (JEDEC) standards.

DS00003672A-page 8

Datasheet

PD70211

Electrical Specifications

2.4

Electrical Characteristics

This section describes the electrical characteristics of the front-end and PWM sections, thermal protection

mechanism against excessive internal temperature, and wall adapter mode functionality.

2.4.1

Electrical Characteristics of Front-End Section

Unless otherwise specified under conditions, the minimum and maximum ratings stated in the following table apply

over the entire specified operating ratings of the PD70211 device. Typical values are determined either by design or

by production testing at 25 °C ambient temperature. Voltages are with respect to IC ground (VPN_IN).

Table 2-5.ꢀTypical Electrical Performance

Symbol

Input Voltage

I_IN

Parameter

Conditions

Min

Typ

Max

Units

IC input current with I_CLASSoff VPP = 55V

—

1

3

mA

Detection Phase

V_DET

Detection range

R_DETdisconnect threshold

—

1.1

10.1

—

10.1

12.8

50

V

Ω

R_{DET_TH}

R_{DS_DET_ON}ON-Resistance of internal

FET during detection

R_{DS_DET_OFF}OFF-Resistance of internal

FET after detection

—

2

—

5

MΩ

μA

I_{OFFSET_DET}Input offset current

1.1V ≤ VPP ≤ 10.1V,

T_J≤ 85 °C

—

V_{R_DET_ON}

Threshold when VPP goes

low

—

2.8

3.0

4.85

V

Classification Phase

V_{CLS_ON}

Classification sink turn-ON

threshold

—

11.4

20.9

—

1

13.7

23.9

—

V

V_{CLS_OFF}

Classification sink turn-OFF

threshold

V

V_{HYS_CLS_ON}Hysteresis of VCLS_ON

threshold

V

V_{MARK_TH}

Mark detection threshold

(VPP falling)

10.1

0.25

50

—

68

11.4

4

V

I_MARK

Current sink in the mark event —

region

mA

I_{CLASS_CLIM}

Current limit of class current

—

80

DS00003672A-page 9

Datasheet

PD70211

Electrical Specifications

...........continued

Symbol

Parameter

Conditions

Min

—

Typ

—

Max

3

Units

mA

I_CLASS

Classification current sink

R_CLASS= not present (class 0)

R_CLASS= 133Ω (class 1)

R_CLASS= 69.8Ω (class 2)

R_CLASS= 45.3Ω (class 3)

R_CLASS= 30.9Ω (class 4)

9.5

10.5

18.5

28.0

40.0

11.5

19.5

29.5

42.0

mA

17.5

26.5

38.0

mA

Isolation FET

R_DSON

ON resistence

Total resistance between VPN_IN

to VPN_OUT;

—

0.3

Ω

I_LOAD< 600 mA, –40 ^oC < T_A< 85

^oC

I_{CLIM_INRUSH}Inrush current limit

—

105

2.2

—

240

—

325

—

2

mA

A

OCP

Overcurrent protection

ILOAD

Continuous operation load

—

A

Undervoltage Lockout

UVLO_ON

Threshold that marks start of

inrush phase

—

36

—

42

V

UVLO_OFF

Threshold where pass- FET

turns OFF as VPP collapses

30.5

34.5

DC-DC Input Cap Discharger

I_{CAP_DIS}

t_dis

Discharge current

Discharge time

7V ≤ VPP ≤ 30V

22.8

—

60

mA

ms

C_{DC_DC}≤ 264 μF

500

(by design, not tested)

timer_dis

Discharge timer

Time for which discharge circuit is 430

activated

—

ms

References, Rails, and Logic

V_AUX

I_AUX

Auxiliary voltage

0 mA < I_AUX< 4 mA

—

9.8

4

10.5

—

12.0

—

V

Maximum continuous current

from V_AUX

mA

I_AUX

Auxiliary current limit

Bandgap reference voltage

Low level flag

—

10

—

32

mA

V

V_REF

1.17

—

1.2

—

1.23

0.4

t_{FLAG_LO}

For AT_FLAG, HD_FLAG,

4P_AT_FLAG, 4P_HD_FLAG,

I_FLAG= 3 mA

V

I_FLAG

Flag current driving capability For AT_FLAG, HD_FLAG,

4P_AT_FLAG, 4P_HD_FLAG

5

—

mA

DS00003672A-page 10

Datasheet

PD70211

Electrical Specifications

...........continued

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t_FLAG

Delay timer between start of

inrush and flags declared

For AT_FLAG, HD_FLAG,

4P_AT_FLAG, 4P_HD_FLAG

80

—

ms

V_{SUPP_HI}

SUPP_Sx high voltage

threshold

For SUPP_S1 and SUPP_S2

25

—

35

V

Wall Adapter

V_IH

V_IL

Input high logic

Input low logic

—

2.4

—

V

0.8

Table 2-6.ꢀTruth Table for Status of Flags

Number of Fingers “N”

SUPP_S1

SUPP_S2 AT_FLAG HD_FLAG 4P_AT_FLAG 4P_HD_FLAG

(N-Event classification)

1

X

H

L

X

L

Hi-Z

0V

Hi-Z

0V

Hi-Z

0V

Hi-Z

2

3

4

5

6

H

L

H

L

Hi Z

0V

H

X

0V

H

X

0V

Reserved for future

X

0V

DS00003672A-page 11

Datasheet

PD70211

Electrical Specifications

2.4.2

Electrical Characteristics of PWM Section

Unless otherwise specified under conditions, the minimum and maximum ratings listed in the following table apply

over the entire specified operating ratings of the PD70211 device. Typical values stated, are determined either by

design or by production testing at 25 °C ambient. Voltages are with respect to IC ground (VPN_IN).

Table 2-7.ꢀTypical Electrical Performance

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Input Voltage Current

V_{CC_UVLO_UP}

V_{CC_UVLO_DN}

I_{VCC_SD}

UVLO threshold with

input rising

V_CCrise time ≥ 0.5 ms

8.85

7

9.15

7.3

1

9.5

V

UVLO threshold with

input falling

7.6

V

IC input current (no

switching)

V_ENABLE= Low, or

—

2000

µA

V_VCC< V_{CC_UVLO_UP}

I_{VCC_Q}

IC input current

V_ENABLE= High, and

—

3

mA

(switching, no load on

SG, PG, VDD)

V_VCC> V_{CC_UVLO_UP}

f_SW= 500 kHz

,

Input UVLO/PFW

V_{INS_TH}

Threshold on VINS pin

Rising or falling

1.171

2.8

1.200

—

1.229

—

V

V_{HYST_HIGH}

Hysteresis pin high

voltage

I_{HYST_SOURCING}= 1 mA

V_{HYST_LOW}

Hysteresis pin low

voltage

I_{HYST_SINKING}= 3 mA

—

0.4

V

LDOs

VL

—

I_{VDD_EXT}< 5 mA (current out 4.75

of pin)

5

5.25

—

V

VH

VH rail (with respect to

—

–5

V_CC

)

Soft Start

I_{SS_CH}

Current out of SS pin

during charging phase

RFREQ = 33.3k, V_SS= 0.5V 32

36

10

40

—

µA

I_{SS_DISCH}

Current into SS pin

during discharging phase

RFREQ = 33.3k,

V_SS= 0.5V

—

% of

I_{SS_CH}

V_{SS_CH}

Soft start charge

completed threshold

By design only

90

—

50

95

—

% of

VREF

V_{SS_DISCH}

Soft start discharge

completed threshold

—

mV

Ω

R_{SS_DISCH}

Soft-start pin discharge

FET resistance

DS00003672A-page 12

Datasheet

PD70211

Electrical Specifications

...........continued

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t_DISCH

Soft-start discharge FET

on-time

—

32

—

Switch

cycles

Switching Frequency and Synchronization

f_{sw_range}

Switching frequency

accuracy

RFREQ = 33.2k

285

1

315

—

345

—

kHz

f_{sync_max}

Maximum

—

MHz

synchronization

frequency

V_{SYNC_HI}

V_{SYNC_LO}

t_sync

SYNC pin high threshold

SYNC pin low threshold

—

2.4

—

V

0.8

—

V

Minimum pulse width of

SYNC pulse

100

ns

D_{sync_max}

Maximum SYNC pulse

duty cycle

—

90

%

Error Amplifier

VREF

Reference voltage

DC open-loop gain

Unity gain bandwidth

—

1.171

70

1.200

100

5

1.229

—

V

Gain_{DC_OPL}

AV_UGBW

Rload = 100k

dB

MHz

Cload = 10 pF (By design

only)

2

—

I_{COMP_OUT}

I_{COMP_IN}

Output sourcing current

Output sinking current

0.2V ≤ V_COMP≤ 1.3V

—

110

145

2

—

620

495

—

µA

V

V_{EA_CMR_MAX}Maximum of input

common-mode range

V_CLAMP

PWM Comparator

V_OFFSETInserted offset in inverted

COMP pin high clamp

—

1.8

2.1

2.6

V

—

200

0

—

300

1

mV

V

input

V_RCLP

Voltage set on RCLP pin

by external resistor to

GND

Current Sense Amplifier

Gain_CSA

I_AUX

DC Gain

0 mA < I_AUX< 4 mA

—

4.75

4

5

5.25

—

V

Maximum continuous

current from V_AUX

—

mA

V_{CSA_CMR_MAX}Maximum input common-

mode range

—

2

—

V

DS00003672A-page 13

Datasheet

PD70211

Electrical Specifications

...........continued

Symbol

Parameter

Conditions

Min

50

Typ

—

Max

100

1.3

Units

ns

t_BLANK

V_ILIM

Blanking time

—

Current limit threshold on Where PWM pulses start to

1.1

1.2

V

output of current sense

amplifier

get truncated

V_ILIMHICCUP

Current limit threshold on Where PWM pulses start to

1.7

1.8

1.9

V

output of current sense

amplifier capability

get omitted in hiccup mode

Differential Voltage Amplifier

Gain_DA

DC gain of differential

voltage amplifier

—

6.68

—

7.0

5

7.14

—

V

A_{VUGBW_DA}

Unity gain bandwidth of

differential voltage

amplifier

MHz

V_{DA_CMR_MAX}Maximum of input

common-mode range

—

3.5

—

V

Drivers

R_{PG_HI}

Drive resistance when

PG is high

—

10

5

—

Ω

R_{PG_LO}

Drive resistance when

PG is low

t_{PG_MIN}

D_MAX

Minimum on-time of PG

PG maximum duty cycle

—

10

120

50

ns

%

Ω

44.5

—

R_{SG_HI}

Drive resistance when

SG is high

—

R_{SG_LO}

Drive resistance when

SG is low

—

10

—

Ω

t_DEAD

Deadtime

60

110

190

ns

Logic Levels on VINS and ENABLE

V_HI

Input high threshold

Input low threshold

—

2

—

V

V_LO

—

0.8

Thermal Protection

T_SD

Thermal shutdown

(rising)

—

157

15

—

°C

T_HYST

Thermal shutdown

hysteresis

30

DS00003672A-page 14

Datasheet

PD70211

Electrical Specifications

2.4.3

Thermal Protection

The PD70211 device is protected from the excessive internal temperatures that might occur during various operating

procedures. The following two temperature sensors are located on the chip monitor temperatures.

•

Isolating switch (pass-FET)

Classification current sink

Each of the given temperature sensors activates a protection mechanism that disconnects the Isolation (pass) FET or

the classification circuit, respectively. This action protects the device from being permanently damaged or even from

long-term degradation.

2.4.4

Wall Adapter Mode

The PD70211 device supports wall adapter functionality. That is, by setting WA_EN pin high, it gives priority to the

wall adapter jack to supply the load.

The WA_EN pin is used while connecting a wall adapter voltage between VPP and VPN_OUT by means of an OR-

ing diode.

While WA_EN, the wall adapter enable pin, is held low (referenced to VPN_IN), the front-end works as a normal PD.

When WA_EN pin is raised high (referenced to VPN_IN), the following three internal operations are forced:

•

The Isolation FET is turned OFF.

All output flags, like AT_FLAG, HD_FLAG, 4P_AT_FLAG, and 4P_HD_FLAG are activated (low state).

V_AUXoutput voltage is turned ON.

While activating the WA_EN pin, the wall adapter supplies the input voltage for the DC-DC converter. Having WA_EN

pin at high state does not disable detection and classification modes.

DS00003672A-page 15

Datasheet

PD70211

Pin Configuration

3.

Pin Configuration

The following figure shows the device pin diagram from the top-view.

Figure 3-1.ꢀPD70211 Pinout

The following table lists the pin descriptions of the PD70211 device.

Table 3-1.ꢀPin Descriptions

Designator

Description

Number

1

SUPP_S1

Input pin for sensing the voltage on the diode bridge connected to the data pairs.

This pin along with the SUPP_S2 pin can be used to distinguish between 2-pair and

4-pair operation. (For PSEs that operate in 4 pairs but generates the classification

procedure on only one pair and not on both pairs). Signal is referenced to VPN_IN.

Place a 10k resistor in the input of this pin.

2

SUPP_S2

Input pin for sensing the voltage on the diode bridge connected to the data pairs.

This pin along with the SUPP_S1 pin can be used to distinguish between 2-pair and

4-pair operation. (For PSEs that operate in 4 pairs but generates the classification

procedure on only one pair and not on both pairs). Signal is referenced to VPN_IN.

Place a 10k resistor in the input of this pin.

DS00003672A-page 16

Datasheet

PD70211

Pin Configuration

...........continued

Designator

Description

Number

3

4P_AT_FLAG

Open drain output. The pin gets actively pulled low when a 4-pair version of a (non-

standard) Type 2 PD-PSE mutually identify each other via classification. There is a

minimum 80 ms delay from the moment when the input capacitor is fully charged to

this signal activity. Signal is referenced to VPN_OUT.

4

5

RREF

Bias current resistor. A 60.4k, 1% resistor is connected between RREF and IC

ground (VPN_IN).

RCLASS

Sets the Class of the PD. Connect RCLASS (programming resistor) between this

pin and IC ground (VPN_IN). Allowed values are 133Ω, 69.8Ω, 45.3Ω, and 30.9Ω

for Class 1, 2, 3, and 4 respectively. If RCLASS is not present, the PD draws up to 3

mA during classification, therefore, indicating Class 0 (default Type 1) to the PSE.

Signal is referenced to VPN_IN.

6

7

HD_FLAG

AT_FLAG

Open drain output. The pin gets actively pulled low when a 2-pair HDBaseT PD-

PSE mutually identify each other through classification. There is a minimum of 80

ms delay from the moment when the input capacitor is fully charged to this signal

activity. Signal is referenced to VPN_OUT.

Open drain output. This pin gets actively pulled low when a Type 2 PD-PSE

mutually identifies each other through classification. There is a minimum of 80 ms

delay from the moment when the input capacitor is fully charged to this signal

activity. Signal is referenced to VPN_OUT.

8, 9

VPN_IN

Lower rail of the incoming PSE voltage rail—from the negative terminal of the two

OR-ed bridge rectifiers (the corresponding upper PoE rail is VPP).

10, 11

VPN_OUT

This is in effect, the switched ground for establishing continuity to the PWM section

after successful detection, classification, and power-up. It is connected to the power

ground and PWM controller IC’s ground plane of the DC-DC converter section.

12

ENABLE

A logic-level input to enable the converter. It can be pulled up constantly, for

example, with a 100k resistor to VDD, to forcibly enable the converter, provided the

input supply has exceeded any applicable UVLO thresholds as set on the VINS pin

or on the VCC pin. Internally, the ENABLE pin goes to the input of an OR-gate, the

other input terminal of which is tied to “POK”—a signal provided by the front-end. If

the ENABLE pin is forced high, the output of the OR-gate goes high and the

converter is allowed to start (provided all UVLO’s are past). If the ENABLE pin is

held low, the internal node “POK” goes active/high when the PD’s front-end

conducts (power OK), so the OR-gate goes high once again. In this case, the

switching converter turns ON as required by the PoE standard. However, for

supporting wall adapters, injecting power after the front-end (at the input of the

converter), the converter can be turned ON forcefully, without the front-end signaling

“PGOOD”, by not tying the ENABLE pin low, but by tying it high (to VDD). That turns

ON the converter irrespective of the state of the front-end (conducting or not), and

whether there is any incoming PoE power or not.

13

VINS

The VINS pin is a programmable UVLO pin. The converter turns ON provided the

voltage on the VINS pin is above 1.2V (and VCC is not in UVLO, and ENABLE pin

is also high—connected to VDD, for example). The converter stops switching (turns

OFF) when the voltage on the VINS pin falls below 1.2V (or if ENABLE is taken low,

or if VCC falls outside its operating range). Thus, by connecting a voltage divider

between input rail and IC ground, the UVLO threshold to enable switching can be

set. However, to have a smooth startup, it is advisable to have some hysteresis too,

by means of a resistor between VINS and HYST as explained in pin-14.

DS00003672A-page 17

Datasheet

PD70211

Pin Configuration

...........continued

Designator

Description

Number

14

HYST

This is the output of the UVLO comparator as shown in the Figure 1-2. “hysteresis

resistor” from HYST pin must be connected to VINS pin to create positive feedback

(and hysteresis). Initially, as the input voltage is rising, the VINS pin voltage is below

1.2V and so the output of the UVLO comparator is low, leading the hysteresis

resistor to fall in parallel to the lower resistor of the UVLO divider placed at the VINS

pin, assisting it to pull down the VINS pin voltage further. As soon as the rising

UVLO threshold is exceeded (VINS > 1.2V), the output of the UVLO comparator

suddenly goes high (up to VDD) and the hysteresis resistor, effectively comes

partially across the upper resistor of the UVLO divider, assisting it in to pull up the

voltage on the VINS pin. This feedback, therefore, increases the voltage on the

VINS pin. Now, the input rail has to fall to a much lower level to allow the VINS pin

voltage to fall below 1.2V. That is how hysteresis is created by positive feedback

action through the hysteresis resistor. The exact math is shown in the 5.

Applications Information section. Note that the HYST pin always toggles between

high or low depending on whether the voltage on the VINS pin is above or below

1.2V, respectively. This can always be used to indicate when the input rail is above

the programmed rising threshold and when it falls below the programmed falling

threshold.

15

16

SYNC

Synchronizes the LX7309 to a frequency higher than its default value as set on

R_FREQpin. The synchronizing clock must be 2x the desired sync frequency, with a

maximum synchronizing clock frequency of 1 MHz (for 500 kHz PWM frequency).

The PG pin’s rising edge occurs at the same instant as the rising edge of the clock

being applied on the SYNC pin.

RFREQ

Connect a programming resistor from this pin to IC ground (pin GND) to set the

switching frequency. A typical value of the programming resistor is 49.9k, and this

value provides a frequency of 215 kHz. Halving it roughly doubles the frequency,

whereas doubling it halves the frequency. Note that the converter is designed to

operate from 100 kHz to 500 kHz based on this pin.

Switching frequency equation:

where Freq is [Hz] and R_FREQis in [Ω]

For more information, see the 5.2 Setting Switching Frequency section.

17

SS

This is the soft-start pin. Typically, a 0.1 µF capacitor, the “soft-start capacitor”, is

connected between this pin and IC ground (pin GND). The capacitor gets charged

up to 1.2V by an internal resistor, and the voltage on the capacitor, in effect, forms

the input voltage reference V_REFof the error amplifier. But, note that this capacitor

serves other functions too; for example, it controls the rate of hiccupping under

overcurrent fault conditions. Therefore, even if the internal reference is not being

used (as in isolated topologies with a TL431 on the secondary side), the soft-start

capacitor is recommended to be in place always. The actual capacitor used is

determined by the application. For more information, see the 5.3 Setting Soft-Start

section.

18

RCLP

Low power clamp resistor. A resistor can be connected from this pin to IC ground

(pin GND) to set the exact level at which pulse-skipping mode is entered at light

loads. However, the usual default is to connect this pin directly to IC ground, in

which case pulse-skipping mode is disabled. The method to select the threshold

(and RCLP resistor value) is described in the 5. Applications Information section.

DS00003672A-page 18

Datasheet

PD70211

Pin Configuration

...........continued

Designator

Description

Number

19

VSN

The negative input of the internal differential-sense voltage amplifier. Note that the

common-mode range of the differential voltage amplifier is 3.5V and its gain is 7.

This differential amplifier can be used for implementing topologies where the

“system (output) ground” is different from the IC ground. Both output rails (output

rail and its return) can then be step-downed, by equal amounts, using identical

voltage dividers, to bring the voltage below 3.5V. Then, differential sensing can be

used, and finally the output of the differential voltage amplifier (pin DAO) can be

connected to the FB pin.

20

21

VSP

The positive input of the internal differential-sense voltage amplifier. Note that it

must always be connected in such a way that VSP is at a higher voltage than VSN.

Also, keep in mind that since the differential voltage amplifier has a gain of 7 and

the output of that amplifier is connected to the feedback pin, which compares that

against a 1.2V reference, in effect, the difference between VSP and VSN stabilizes

to 1.2V/7 = 0.171V in steady state. That is how the (identical) voltage dividers

present on VSP and VSN are designed.

COMP

This is the output of the internal error amplifier, and the input of the PWM

comparator. It is brought out to support isolated topologies because in such cases,

there is an error amplifier already present on the secondary side (for example, a

TL431 or equivalent). Therefore, the error amplifier of the converter section can be

passed. On the other hand, in non-isolated topologies, the error amplifier of the

converter can be used directly or through the differential voltage amplifier stage.

22

23

24

DAO

FB

This is the output of the internal differential voltage amplifier (gain = 7). When this

amplifier is used, DAO is connected to the feedback pin (FB). Part of the

compensation network is between the two pins, and this network is typical of any

Type 3 error amplifier input, with or without a differential amplifier.

This is the feedback pin of the IC. It is internally compared to a 1.2V reference. If

the internal error amplifier is not used and the COMP pin is being used to inject the

error signal (as in isolated topologies), the FB pin can be either tied high (to VDD),

or connected to COMP.

GND

This is the IC ground or the analog (quiet) ground of the IC. Pin 20 is the Power

Ground (PGND). Typically, the analog ground and PGND can be connected on a

copper island on the component side, and then connect that through several vias

very close to the chip on to a large ground plane which extends up to the lower side

of the current sense resistor. All chip decoupling can then be very simple with

respect to the copper island on the component side.

25

VL

This is created by an internal LDO and basically provides a housekeeping rail for

the IC itself, which is 5V with respect to the IC ground. A 1 µF ceramic cap placed

close to this pin, connected to IC ground is recommended for proper decoupling.

This pin can also provide up to 5 mA for external circuitry if required, thermal

aspects (IC dissipation) being considered.

DS00003672A-page 19

Datasheet

PD70211

Pin Configuration

...........continued

Designator

Description

Number

26

SG

Secondary gate driver. It drives a synchronous FET or an active clamp FET. It is

derived from VCC (~ 12 V), and has a 10Ω limiting resistor. Therefore, it can be

used to drive a gate-drive transformer directly. It is usually complementary to the

primary gate driver pin (PG). But, there is a typical 110 ns blanking time between

the two to prevent cross-conduction. SG is held firmly low in pulse-skip mode (if

allowed). It is also low during soft-start. It allows forced PWM (continuous

conduction) mode by allowing negative inductor currents. It does not support diode-

emulation mode (discontinuous conduction mode). However, in pulse-skip mode, as

the SG stays OFF, the converter automatically lapses into discontinuous conduction

mode through the body-diode of the synchronous FET. This pin can be left floating,

if unused.

27

28

PGND

CSN

Power ground (for internal SG and PG drivers). This is ideal for VCC decoupling

and the Primary-side current sense resistor’s lower terminal. GND and PGND can

be combined into a single large ground plane. Note that the power ground plane is

firmly connected to VPN_OUT, which is the drain side of the PD’s low-side pass-

FET (it stands for Negative Port Voltage Out).

The negative input of the internal current-sense voltage amplifier. Note that the

common-mode range of the differential current-sense amplifier is 2V and its gain is

5. This is used for high-side current sensing up to 2V. It is then placed on the

(steady) output side of a Buck inductor, and the maximum output voltage is 1.8V for

using this type of sensing. Ensure that CSN is at a lower voltage compared to the

positive input of the current-sense amplifier (CSP). Current sensing can also be

implemented in a more basic fashion for “low-side” sensing, with a resistor in the

return (ground) of the Buck. In that case, CSN is shown connected to IC ground.

However, to avoid noise from ground bounce, it is best to route this on the PCB in

Kelvin manner to the lower end of the sense resistor. This is important because the

peak operating voltage on the sense resistor is only 200 mV and PCB-related noise

can cause jitter in the switching waveform in current-mode control.

29

30

CSP

PG

The positive input of the internal current-sense voltage amplifier. See description of

pin 28 (CSN). Note that the output of the current-sense amplifier is amplified five

times. Therefore, a 0.2V current-sense voltage translates to a 1V swing at the input

of the PWM comparator. Higher voltages lead to hiccup mode protection.

This stands for primary gate driver. It drives the main FET, and has a 5Ω or 10Ω

limiting drive resistor switched between a voltage close to VCC rail and the IC

ground. For guaranteeing proper shutdown during OFF time, it is necessary to add

a 470k resistor from PG to VINS, as shown in Figure 1.

31

32

VH

Internal rail of –5V with respect to VCC, brought out only for decoupling purposes.

Connect a 0.1 µF ceramic cap very close, from this pin to VAUX_VCC pin.

VAUX_VCC

Auxiliary voltage rail from front-end to the VCC (supply) input of the PWM section.

The front-end provides a few mA of startup current for the PWM controller (at

typically 10.5V). Signal is referenced to VPN_OUT and is activated once front-end

power up sequence ends. After initial startup of PWM section, a bias winding can be

connected to this pin through a diode, to sustain the PWM section.

33

WA_EN

While this input is low (referenced to VPN_IN) the chip work according to internal

flow diagram. When this input is high, it enable wall adapter feature. Place 100 nF

to 1 uF/10V capacitor from WA_EN to VPN_IN pins, locate it close to device. When

WA_EN is no tused, connect it to VPN_IN. For further information, see the

Operation with an External DC Source section.

DS00003672A-page 20

Datasheet

PD70211

Pin Configuration

...........continued

Designator

Description

Number

34

4P_HD_FLAG

Open drain output. The pin gets actively pulled low when a 4-pair HDBaseT PD-

PSE mutually identify each other via classification. There is a minimum 80 ms delay

from the moment that the input capacitor is fully charged to this signal activity.

Signal is referenced to VPN_OUT.

35

36

37

VPP

Upper rail of the incoming PSE voltage rail—from the positive terminal of the two

OR-ed bridge rectifiers (the corresponding lower PoE rail is VPN_IN).

RDET

EPAD

Internally connects to VPN_IN during detection phase and disengages after it is

over. A 25 KΩ (or 24.9K), 1% resistor is connected between this pin and VPP.

Connected on PCB plane to VPN_IN.

DS00003672A-page 21

Datasheet

PD70211

Package Specifications

4.

Package Specifications

The following figure shows a 6 mm × 6 mm, 36-pin QFN PD70211 package.

Figure 4-1.ꢀQFN Package

Note:ꢀ Dimensions do not include protrusions; they must not exceed 0.155 mm (0.006″) on any side. Lead dimension

does not include solder coverage.

Table 4-1.ꢀPackage Dimensions

Millimeters

Min

Inches

Min

Dimension

Max

1.00

0.05

Max

A

0.80

0.031

0.039

0.002

A1

A3

e

0.00

0

0.20 REF

0.50 BSC

0.45

0.008 REF

0.019 BSC

0.018

L

0.65

0.30

0.026

0.011

b

0.18

0.007

D2

E2

D

4.00

4.25

0.157

0.167

4.00

0.157

6.00 BSC

0.25

0.236 BSC

0.0098

E

K

—

DS00003672A-page 22

Datasheet

PD70211

Package Specifications

4.1

Recommended PCB Layout

The following figures show the recommended PCB layout pattern for the PD70211 device.

Figure 4-2.ꢀTop Layer Copper Recommended PCB Layout (mm)

Figure 4-3.ꢀTop Layer Solder Mask, Solder Paste and Vias Recommended PCB Layout (mm)

Figure 4-4.ꢀBottom Layer Copper and Solder Paste Recommended PCB Layout for Thermal Pad Array (mm)

DS00003672A-page 23

Datasheet

PD70211

Applications Information

5.

Applications Information

The following sections describe the PD70211 application.

5.1

Peripheral Devices

An 82 nF to 100 nF/100 V capacitor must be placed between device VPP and VPN_IN pins, and located as close as

possible to the device.

A 58V TVS must be placed between device VPP and VPN_IN pins for protection against voltage transients. For

complete surge protection, see www.microchip.com/DS00003410B.

A 10 KΩ resistor must be placed on SUPP_S1 and SUPP_S2 lines between diode bridge and PD70211 device.

When WA_EN is used, a 100 nF to 1 uF/10V capacitor must be placed between WA_EN and VPN_IN pins close to

PD70211 device. Consult Microchip Technology for optimized recommendation.

When not used, WA_EN must be connected to VPN_IN pin.

5.2

Setting Switching Frequency

The R_FREQresistor is connected from R_FREQpin to IC ground. Based on that, the following frequency is obtained:

where, Freq is [Hz] and R_FREQis Ω.

For example, by setting R_FREQ= 49900Ω:

Any frequency between 100 kHz to 500 kHz can be set.

Note:ꢀ When synchronizing, the default frequency (as set by R_FREQ) must be lower than the synchronization clock. If

the synchronization breaks, the converter lapses back to the default value. When synchronizing, the frequency can

be increased to 1 MHz.

5.3

Setting Soft-Start

A capacitor is connected between SS pin and IC ground. The current charging of the capacitor is:

For example, if R_FREQ= 49.9k, then:

Therefore, charging a 0.1 µF ceramic cap on the SS pin from 0V to 1.2V takes:

This is the soft-start time in this case.

DS00003672A-page 24

Datasheet

PD70211

Applications Information

5.4

Setting Pulse-skip Mode Threshold

If an RCLP programming resistor is placed between RCLP pin and IC ground, the clamping voltage level is given by:

For example, if RCLP = R_FREQ, assuming that both are 49.9k, then the converter enters pulse skipping when the

output of the current sense amplifier drops to 0.3V.

Note:ꢀ The gain with this current amplifier is 5.

Therefore, in terms of the voltage on the sense resistor (input of the current amplifier), 0.3V/5 = 0.06V. As the

converter is usually designed in such a way that its peak is around 0.2V (the peak of Rsense voltage before it starts

to current limit), ratio of 0.06V/0.2V = 0.3 is obtained. In other words, the converter enters pulse-skipping when the

output current is 30% of the maximum designed output current.

5.5

Setting UVLO/Hysteresis Thresholds

Note: A 470k resistor from PG pin to VINS pin is required for guaranteeing proper termination of gate drive pulse

during UVLO.

For example, a divider is connected to input at the VINS pin, and resistors are called R_UPPERand R_LOWER. RHYST, a

hysteresis resistor from the output of the UVLO comparator, which provides positive feedback on to the VINS pin, is

also present, as explained in the 3. Pin Configuration section. When the input voltage is rising, in effect, the

hysteresis resistor is in parallel to the lower resistor R_LOWER. When the voltage on the VINS pin rises above 1.2V, the

UVLO comparator flips and the hysteresis resistor appears connected to 5V (output of the UVLO comparator). The

equivalent configurations are shown in Figure 5-1. After solving the equations, the following example indicates the set

thresholds. The values are as used in Figure 1-2.

Therefore, with the selected resistors, a rising threshold of 39.8V and a falling threshold of 34.8V is achieved.

DS00003672A-page 25

Datasheet

PD70211

Applications Information

Figure 5-1.ꢀEquivalent Diagrams for UVLO and Hysteresis

5.6

Setting the Voltage Divider for Output Rails

Generically, the equation is stated as:

Where, R_UPis the name given to the upper resistor (connected to output rail) and R_LOWis the name given to the

resistor connected to lower rail (usually IC ground). However, with so many topologies, in effect the following three

cases in all the typical schematics presented so far are present.

•

Non-isolated topologies with simple divider connected directly to FB pin. For this, V_X= 1.2V is used.

Isolated topologies with divider to another reference (such as TL431 with an internal reference of 2.5V). For this,

V_X= 2.5V is used.

•

Non-isolated topologies with a differential divider connected to differential voltage amplifier of the LX7309. The

same preceeding divider equation is used, but with V_X= 0.171V (that is, 1.2V divided by the gain of the

differential amplifier 7). Two identical dividers are required.

5.7

Selecting the Sense Resistor

In a Buck topology, the center of the switch current ramp equals the output current. To that, about 30% for the “I_PEAK

₊” peak current must be added because of the rising ramp caused by the inductor. That is a factor of 1.3. Some

headroom for proper transient response at maximum load must also be included. As the peak voltage on the sense

resistor is 0.2V, to leave headroom, it must be planned in such a way that the switch current peak stays at around

0.18V at the most, at maximum load. This means the following:

An adjust resistor must be placed in parallel (for example, the 22Ω placeholder).

For a Forward converter (Buck with a transformer), instead of the I_ORload current as shown in the preceeding

equation, the reflected load current of I_O/ncan be used, where n is the turns ratio (number of primary-side turns

divided by number of secondary-side turns). The sense resistance must also be lowered further (by means of the

adjust resistor), to account for the magnetization current component on the switch side.

DS00003672A-page 26

Datasheet

PD70211

Applications Information

Therefore, roughly:

For a Boost or Buck-Boost, account for the fact must be made that the peak current is not just 1.3 times of maximum

load current, but it is actually:

Therefore, the following equation for sense resistor must be used.

For example, if the maximum load current is 5A, the sense resistor value to use is:

This is roughly half of the Buck (same load current).

For a Flyback topology (Buck-Boost with a transformer), the reflected output current is used:

5.8

Operation with an External DC Source

PD applications utilizing PD70211 IC might be operated with an external power source (DC wall adaptor). Figure 5-2

and Figure 5-3 show the two cases of providing power with an external source.

•

External source connected to application’s low voltage supply rails. External source voltage level is dependent

on DC-DC output characteristics. See Figure 5-2 for more details.

•

External source connected to PD device output connection towards the application (VPP to VPNOUT). External

source voltage level is dependent on DC-DC input requirements. See Figure 5-3 for more details.

DS00003672A-page 27

Datasheet

PD70211

Applications Information

Figure 5-2.ꢀExternal Power Input Connected to Application Supply Rails

Figure 5-3.ꢀExternal Power Input Connected to PD70211 Output

The PD70211 WA_EN pin disables the Isolation switch and the PSE input power, when an external adapter is

connected.

The WA_EN resistors divider depends on the V_INHthreshold of the PD70211.

Figure 5-4 shows the resistors that must be selected in external adapter connection.

DS00003672A-page 28

Datasheet

PD70211

Applications Information

Figure 5-4.ꢀExternal Power Input Resistors Dividers

R1 and R2 set a rough threshold for PFET Q1 enable, to detect whether the external adapter exists or not. It must be

set at a lower threshold than the PD70211 disable levels.

R3 and R4 set the PD70211 disable threshold.

Therefore, in case of 36V–57V external adapter, the disable setting can be selected as follows:

PFET enable threshold = 30V.

R1 and R2 setting must be such that the value of Q1 VGS is less than 20V at maximum voltage condition of the

external adapter.

While external adapter voltage is more than 30 V, Q1 is above its VGS_thvalue.

R1 is selected as 2 kΩ.

Using R1 = 2 kΩ, Vext_adapter = 30V, and VGS = maximum VGS_th= 3.5V, the R2 value is obtained:

R3 and R4 are set to the range of few kΩ (10’s of kΩ) using the following equation:

Using R3 = 15 kΩ, Vext_adapter = 33.7V, and from this data sheet PD70211_WA_EN = 2.4V as the turn OFF

minimum threshold.

Solving the equation, the valid resistor's values for an adapter of 36V and above are achieved.

For complete information and details of various connection methods, see www.microchip.com/DS00003472A.

DS00003672A-page 29

Datasheet

PD70211

Ordering Information

6.

Ordering Information

The following table lists the ordering information of the PD70211 device.

Table 6-1.ꢀOrdering Information

Ambient

Type

Part Marking Ordering P/N

Package

Temperature

–40 °C to 85 °C

RoHS

MSCC Logo PD70211ILQ-TR QFN-36

compliant,

70211

(6 mm × 6 mm, 0.5 mm pitch)

Pb-free

Z Z e4¹

YYWWNNN²

Notes:ꢀ

1. ZZ e4: ZZ = Random character with no meaning, e4 = Second level interconnect.

2. YY = Year, WW = Week, NNN = Trace code.

DS00003672A-page 30

Datasheet

PD70211

Reference Documents

7.

Reference Documents

1. AN3533 PD70210(A) PD70211 System Layout Guidelines.

2. AN3471 Designing a Type 1/2 802.3 or HDBaseT Type 3 Powered Device Using PD702x1 and PD701x1 ICs.

3. AN3472 Implementing Auxiliary Power in PoE.

DS00003672A-page 31

Datasheet

PD70211

Revision History

8.

Revision History

Revision

Date

Description

A

10/2020

Following is the summary of changes:

•

The document was updated as per the Microchip standards.

Document ID PD-000390461 was changed to DS00003672A.

Added Table 1 to the Features section.

Added new Figure 1 and note in the 2 Applications section.

Updated units column of Table 2-5.

Updated units column of Table 2-7.

Edited the note in the 2.3 Thermal Properties section.

Updated Figure 3-1 and Table 3-1 in the Pin Configuration section.

Added K dimension values in Table 4-1 in the Package Specifications section.

Changed Figure 4-4 in the Recommended PCB Layout section.

Updated the 5.1 Peripheral Devices section.

Edited the 5.7 Selecting the Sense Resistor section.

Added the 7. Reference Documents section.

Updated package specifications in Table 6-1 and notes in the 6. Ordering

Information section.

2.0

09/2019

Following is the summary of changes:

•

Re-drew the QFN package diagram.

Corrected a typo in pin name in the Applications Information section.

Removed the column 'note' was from the Ordering Information table.

Converted the document to Microsemi formatting standards.

1.4

07/2017

07/2016

Updated the marking and MSL3 information

Following is the summary of changes:

1.31

•

Removed 'PD' in IC marking description

Removed name of the front-end die (PD70210A) in functional block diagram

Updated revision number and date in the footer

1.3

10/2015

Following is the summary of changes:

•

Fixed Vaux pin description

Added UVLO_ON missing information

PD70224 was changed to PD70211 in figures 9, 10, and 11.

1.2

1.1

1.0

0.6

0.3

0.2

0.1

Updated a typo in part marking definition.

Added a PCB footprint recommendation.

Added frequency setting information.

01/2015

08/2014

07/2014

03/2013

03/2012

02/2012

Flags maximum voltage was reduced and WA_EN information was added.

General updates were made.

Minor edits were made to the class values.

It was the first publication of this document.

DS00003672A-page 32

Datasheet

PD70211

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DS00003672A-page 33

Datasheet

PD70211

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The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,

BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,

KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST,

MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer,

QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,

TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control,

HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus,

ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider,

Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom,

CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,

dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP,

INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,

MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,

PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad

I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense,

ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A.

and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of

Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

©

ISBN: 978-1-5224-6923-0

DS00003672A-page 34

Datasheet

PD70211

Quality Management System

For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

DS00003672A-page 35

Datasheet

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

www.microchip.com/support

Web Address:

Australia - Sydney

Tel: 61-2-9868-6733

China - Beijing

India - Bangalore

Tel: 91-80-3090-4444

India - New Delhi

Tel: 91-11-4160-8631

India - Pune

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4485-5910

Tel: 86-10-8569-7000

China - Chengdu

Tel: 86-28-8665-5511

China - Chongqing

Tel: 86-23-8980-9588

China - Dongguan

Tel: 86-769-8702-9880

China - Guangzhou

Tel: 86-20-8755-8029

China - Hangzhou

Tel: 86-571-8792-8115

China - Hong Kong SAR

Tel: 852-2943-5100

China - Nanjing

Tel: 91-20-4121-0141

Japan - Osaka

Fax: 45-4485-2829

Finland - Espoo

Tel: 81-6-6152-7160

Japan - Tokyo

Tel: 358-9-4520-820

France - Paris

www.microchip.com

Atlanta

Tel: 81-3-6880- 3770

Korea - Daegu

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Garching

Tel: 49-8931-9700

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Austin, TX

Tel: 82-53-744-4301

Korea - Seoul

Tel: 82-2-554-7200

Malaysia - Kuala Lumpur

Tel: 60-3-7651-7906

Malaysia - Penang

Tel: 60-4-227-8870

Philippines - Manila

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Singapore

Germany - Haan

Tel: 512-257-3370

Boston

Tel: 49-2129-3766400

Germany - Heilbronn

Tel: 49-7131-72400

Germany - Karlsruhe

Tel: 49-721-625370

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Germany - Rosenheim

Tel: 49-8031-354-560

Israel - Ra’anana

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Tel: 86-25-8473-2460

China - Qingdao

Tel: 86-532-8502-7355

China - Shanghai

Tel: 86-21-3326-8000

China - Shenyang

Tel: 86-24-2334-2829

China - Shenzhen

Tel: 86-755-8864-2200

China - Suzhou

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Dallas

Tel: 65-6334-8870

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Taiwan - Taipei

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Tel: 972-9-744-7705

Italy - Milan

Tel: 86-186-6233-1526

China - Wuhan

Tel: 886-2-2508-8600

Thailand - Bangkok

Tel: 66-2-694-1351

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Tel: 39-0331-742611

Fax: 39-0331-466781

Italy - Padova

Novi, MI

Tel: 248-848-4000

Houston, TX

Tel: 86-27-5980-5300

China - Xian

Tel: 39-049-7625286

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Norway - Trondheim

Tel: 47-72884388

Tel: 281-894-5983

Indianapolis

Tel: 86-29-8833-7252

China - Xiamen

Noblesville, IN

Tel: 86-592-2388138

China - Zhuhai

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

Los Angeles

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Raleigh, NC

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Sweden - Gothenberg

Tel: 46-31-704-60-40

Sweden - Stockholm

Tel: 46-8-5090-4654

UK - Wokingham

Tel: 919-844-7510

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

Tel: 44-118-921-5800

Fax: 44-118-921-5820

DS00003672A-page 36

Datasheet


型号：	PD70210AL
厂家：	MICROCHIP
描述：	PD Controller with Switching Regulator for AF/AT/UPOE/ HDBaseT/4-pair PoE Applications 光电二极管
文件：	总36页 (文件大小：810K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PD70210AL [MICROCHIP]

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