MCP6V36UT-E/OT [MICROCHIP]
23 μA, 300 kHz Zero-Drift Op Amps;型号: | MCP6V36UT-E/OT |
厂家: | MICROCHIP |
描述: | 23 μA, 300 kHz Zero-Drift Op Amps |
文件: | 总50页 (文件大小:3270K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MCP6V36/6U/7/9
23 µA, 300 kHz Zero-Drift Op Amps
Features
Description
• High DC Precision:
The Microchip Technology Inc. MCP6V36/6U/7/9
family of operational amplifiers provides input offset
voltage correction for very low offset and offset drift.
These are low-power devices, with a gain bandwidth
product of 300 kHz (typical). They are unity gain stable,
have virtually no 1/f noise, and have good Power
Supply Rejection Ratio (PSRR) and Common Mode
Rejection Ratio (CMRR). These products operate with
a single supply voltage as low as 1.8V, while drawing
23 µA/amplifier (typical) of quiescent current.
- VOS Drift: ±150 nV/°C (maximum)
- VOS: ±25 µV (maximum)
- AOL: 110 dB (minimum, VDD = 5.5V)
- PSRR: 110 dB (minimum, VDD = 5.5V)
- CMRR: 110 dB (minimum, VDD = 5.5V)
- Eni: 1.0 µVP-P (typical), f = 0.1 Hz to 10 Hz
- Eni: 0.33 µVP-P (typical), f = 0.01 Hz to 1 Hz
• Low Power and Supply Voltages:
- IQ: 23 µA/amplifier (typical)
The Microchip Technology Inc. MCP6V36/6U/7/9 op
amps are offered in single (MCP6V36 and
MCP6V36U), dual (MCP6V37) and quad (MCP6V39)
packages. They were designed using an advanced
CMOS process.
- Wide Supply Voltage Range: 1.8V to 5.5V
• Small Packages:
- Singles in SC70, SOT-23
- Duals in MSOP-8, 2×3 TDFN
- Quads in TSSOP-14
Package Types
• Easy to Use:
MCP6V36
SOT-23
MCP6V37
MSOP
- Rail-to-Rail Input/Output
- Gain Bandwidth Product: 300 kHz (typical)
- Unity Gain Stable
VDD
1
VDD VOUTA
8
7
6
5
VOUT
VSS
1
5
4
VOUTB
2
3
4
VINA
VINA
–
+
2
3
• Extended Temperature Range: -40°C to +125°C
VINB
VINB
–
+
VIN+
VIN–
VSS
Typical Applications
• Portable Instrumentation
• Sensor Conditioning
MCP6V36U
SC70, SOT-23
MCP6V37
2×3 TDFN *
• Temperature Measurement
• DC Offset Correction
VOUTA
VDD
1
8
VIN+
VSS
VDD
1
2
3
5
VINA–
VOUTB
2
3
4
7
6
5
EP
9
• Medical Instrumentation
VINA+
VINB
VINB
–
+
VIN–
VOUT
4
VSS
Design Aids
MCP6V39
• SPICE Macro Models
TSSOP
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
V
V
V
V
1
14
13
12
11
10
9
VOUTA
OUTD
–
2
3
4
5
6
7
VINA
VINA
VDD
VINB
VINB
–
IND
+
+
IND
Related Parts
SS
V
+
+
INC
• MCP6V01/2/3: Auto-Zeroed, Spread Clock
• MCP6V06/7/8: Auto-Zeroed
VINC
VOUTC
–
–
VOUTB
8
• MCP6V26/7/8: Auto-Zeroed, Low Noise
• MCP6V11/1U/2/4: Zero-Drift, Low Power
• MCP6V31/1U/2/4: Zero-Drift, Low Power
* Includes Exposed Thermal Pad (EP); see
Table 3-1.
2019 Microchip Technology Inc.
DS20006209A-page 1
MCP6V36/6U/7/9
Typical Application Circuit
R1
R2
R3
VIN
VOUT
R4
R5
C2
U1
MCP6XXX
VDD/2
R2
VDD/2
U2
MCP6V36
Offset Voltage Correction for Power Driver
DS20006209A-page 2
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS .................................................................................................................................................................6.5V
Current at Input Pins ..............................................................................................................................................±2 mA
Analog Inputs (VIN+ and VIN–) (Note 1) .....................................................................................VSS – 1.0V to VDD+1.0V
All other Inputs and Outputs .......................................................................................................VSS – 0.3V to VDD+0.3V
Difference Input voltage .................................................................................................................................|VDD – VSS
|
Output Short Circuit Current ...........................................................................................................................Continuous
Current at Output and Supply Pins ......................................................................................................................±30 mA
Storage Temperature .............................................................................................................................-65°C to +150°C
Maximum Junction Temperature .......................................................................................................................... +150°C
ESD protection on all pins (HBM, CDM, MM) 2 kV, 1.5 kV, 400V
Note 1: See Section 4.2.1, Rail-to-Rail Inputs.
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1.2
Specifications
DC ELECTRICAL SPECIFICATIONS
TABLE 1-1:
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND,
VCM = VDD/3,VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Input Offset
Input Offset Voltage
VOS
TC1
-25
—
—
+25
µV
TA = +25°C
Input Offset Voltage Drift with
Temperature (Linear Temp. Co.)
-150
+150
nV/°C TA = -40 to +125°C
(Note 1)
Input Offset Voltage Quadratic
Temp. Co.
TC2
—
±0.08
135
—
—
nV/°C2 TA = -40 to +125°C
Power Supply Rejection Ratio
Input Bias Current and Impedance
Input Bias Current
PSRR
110
dB
IB
IB
—
—
0
+5
+20
—
—
+5
—
—
+1
—
—
pA
Input Bias Current across Temperature
pA
nA
TA = +85°C
IB
+2.9
TA = +125°C
Input Offset Current
IOS
IOS
IOS
ZCM
ZDIFF
—
—
-1
—
—
±130
±140
±0.4
1013||6
1013||6
pA
Input Offset Current across Temperature
pA
TA = +85°C
nA
TA = +125°C
Common-Mode Input Impedance
Differential Input Impedance
Ω||pF
Ω||pF
Note 1: For Design Guidance only; not tested.
2: Figure 2-15 shows how VCML and VCMH changed across temperature for the first production lot.
2019 Microchip Technology Inc.
DS20006209A-page 3
MCP6V36/6U/7/9
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND,
VCM = VDD/3,VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5).
Parameters
Common-Mode
Sym.
Min.
Typ.
Max.
Units
Conditions
Common-Mode
Input Voltage Range Low
VCML
—
—
—
VSS 0.15
V
V
(Note 2)
Common-Mode
Input Voltage Range High
VCMH VDD + 0.2
—
—
(Note 2)
Common-Mode Rejection Ratio
CMRR
CMRR
100
110
125
dB
VDD = 1.8V,
VCM = -0.15V to 2.0V
(Note 2)
135
—
dB
VDD = 5.5V,
VCM = -0.15V to 5.7V
(Note 2)
Open-Loop Gain
DC Open-Loop Gain (large signal)
AOL
AOL
93
125
135
—
—
dB
dB
VDD = 1.8V,
VOUT = 0.3V to 1.6V
110
VDD = 5.5V,
VOUT = 0.3V to 5.3V
Output
Minimum Output Voltage Swing
VOL
VOL
VOH
VOH
VSS
—
VSS + 14 VSS + 45
mV RL = 10 kΩ, G = +2,
0.5V input overdrive
VSS + 1.4
—
VDD
—
mV RL = 100 kΩ, G = +2,
0.5V input overdrive
Maximum Output Voltage Swing
Output Short Circuit Current
VDD – 45 VDD – 14
mV RL = 10 kΩ, G = +2,
0.5V input overdrive
—
VDD – 1.4
mV RL = 100 kΩ, G = +2,
0.5V input overdrive
ISC
ISC
—
—
±6
—
—
mA VDD = 1.8V
mA VDD = 5.5V
±21
Power Supply
Supply Voltage
VDD
IQ
1.8
12
—
23
21
—
5.5
34
V
Quiescent Current per amplifier
µA
IO = 0, MCP6V36/6U
IO = 0, MCP6V37/9
10
34
POR Trip Voltage
VPOR
0.9
1.6
V
Note 1: For Design Guidance only; not tested.
2: Figure 2-15 shows how VCML and VCMH changed across temperature for the first production lot.
DS20006209A-page 4
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5).
Parameters
Sym. Min. Typ. Max. Units
Conditions
Amplifier AC Response
Gain Bandwidth Product
Slew Rate
GBWP
SR
—
—
—
300
0.13
70
—
—
—
kHz
V/µs
°
Phase Margin
PM
G = +1
Amplifier Noise Response
Input Noise Voltage
Eni
Eni
eni
ini
—
—
—
—
0.33
1.0
50
—
—
—
—
µVP-P f = 0.01 Hz to 1 Hz
µVP-P f = 0.1 Hz to 10 Hz
nV/√Hz f < 2 kHz
Input Noise Voltage Density
Input Noise Current Density
Amplifier Distortion (Note 1)
Intermodulation Distortion (AC)
Amplifier Step Response
Start Up Time
5
fA/√Hz
IMD
—
52
—
µVPK VCM tone = 50 mVPK at 100 Hz, GN = 1
tSTR
tSTL
—
—
2
—
—
ms
µs
G = +1, 0.1% VOUT settling (Note 2)
Offset Correction Settling Time
100
G = +1, VIN step of 2V,
VOS within 100 µV of its final value
Output Overdrive Recovery Time tODR
—
120
—
µs
G = -10, ±0.5V input overdrive to VDD/2,
VIN 50% point to VOUT 90% point (Note 3)
Note 1: These parameters were characterized using the circuit in Figure 1-6. In Figure 2-33 and Figure 2-34,
there is an IMD tone at DC, a residual tone at 100 Hz and other IMD tones and clock tones.
2: High gains behave differently; see Section 4.3.3, Offset at Power Up.
3:
t
ODR includes some uncertainty due to clock edge timing.
TABLE 1-3:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V,
VSS = GND.
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
(Note 1)
Thermal Package Resistances
Thermal Resistance, 5L-SC-70
JA
JA
θJA
θJA
θJA
—
—
—
—
—
209
201
53
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 8L-2×3 TDFN
Thermal Resistance, 8L-MSOP
Thermal Resistance, 14L-TSSOP
211
100
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).
2019 Microchip Technology Inc.
DS20006209A-page 5
MCP6V36/6U/7/9
1.3
Timing Diagrams
1.4
Test Circuits
The circuits used for most DC and AC tests are shown
in Figure 1-4 and Figure 1-5. Lay the bypass capacitors
out as discussed in Section 4.3.10 “Supply
Bypassing and Filtering”. RN is equal to the parallel
combination of RF and RG to minimize bias current
effects.
1.8V to 5.5V
1.8V
0V
VDD
tSTR
1.001(VDD/3)
0.999(VDD/3)
VOUT
VDD
1 µF
FIGURE 1-1:
Amplifier Start Up.
RN
VIN
RISO
CL
VOUT
MCP6V3X
VIN
RL
100 nF
RF
tSTL
VDD/3
VOS + 100 µV
OS – 100 µV
VOS
VL
RG
V
FIGURE 1-4:
AC and DC Test Circuit for
FIGURE 1-2:
Offset Correction Settling
Most Noninverting Gain Conditions.
Time.
VDD
1 µF
VIN
RN
VDD/3
RISO
CL
VOUT
tODR
MCP6V3X
RL
100 nF
RF
VDD
VIN
tODR
VL
RG
VOUT
VDD/2
FIGURE 1-5:
Most Inverting Gain Conditions.
AC and DC Test Circuit for
VSS
FIGURE 1-3:
Output Overdrive Recovery.
The circuit in Figure 1-6 tests the input’s dynamic
behavior (i.e., IMD, tSTR, tSTL and tODR). The
potentiometer balances the resistor network (VOUT
should equal VREF at DC). The op amp’s Common-
mode input voltage is VCM = VIN/2. The error at the
input (VERR) appears at VOUT with a noise gain of
10 V/V.
11.0 kΩ 100 kΩ 500 Ω
0.1%
0.1% 25 turn
VREF = VDD/3
VDD
RISO
0 Ω
1 µF
VOUT
VIN
100 nF
CL
20 pF
RL
open
MCP6V3X
VL
11.0 kΩ
100 kΩ 249 Ω
1%
0.1%
0.1%
FIGURE 1-6:
Test Circuit for Dynamic
Input Behavior.
DS20006209A-page 6
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
2.1
DC Input Precision
55%
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
8
6
VCM = VCML
56 Samples
Representative Part
TA = +25°C
VDD = 1.6V and 5.5V
4
2
0
+125°C
+85°C
+25°C
-40°C
-2
-4
-6
-8
0%
-8
-6
-4
-2
0
2
4
6
8
Input Offset Voltage (µV)
Power Supply Voltage (V)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage vs.
Power Supply Voltage with VCM = VCML
.
35%
8
VCM = VCMH
56 Samples
DD = 1.6V and 5.5V
Representative Part
V
6
4
30%
25%
20%
15%
10%
5%
2
0
+125°C
+85°C
+25°C
-40°C
-2
-4
-6
-8
0%
-20 -16 -12 -8 -4
0
4
8
12 16 20
Input Offset Voltage Drift; TC1 (nV/°C)
Power Supply Voltage (V)
FIGURE 2-2:
Input Offset Voltage Drift.
FIGURE 2-5:
Input Offset Voltage vs.
Power Supply Voltage with VCM = VCMH
.
30%
8
Representative Part
56 Samples
DD = 1.6V and 5.5V
V
6
4
25%
20%
15%
10%
5%
2
VDD = 1.8V
0
VDD = 5.5V
-2
-4
-6
0%
-100 -80 -60 -40 -20
0
20 40 60 80 100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage's Quadratic Temp Co;
TC2 (pV/°C2)
FIGURE 2-3:
Input Offset Voltage
FIGURE 2-6:
Input Offset Voltage vs.
Quadratic Temp. Co.
Output Voltage.
2019 Microchip Technology Inc.
DS20006209A-page 7
MCP6V36/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
160
155
150
140
135
130
125
120
115
110
8
6
VDD = 1.8V
Representative Part
4
VDD = 5.5V
VDD = 1.8V
2
0
-2
-4
-6
-8
+125°C
+85°C
-40°C
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
-50
-25
0
25
50
75
100
125
Input Common Mode Voltage (V)
Ambient Temperature (°C)
FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
DC Open-Loop Gain vs.
Common-Mode Voltage with VDD = 1.8V.
Ambient Temperature.
8
200
TA = +85°C
VDD = 5.5V
VDD = 5.5V
150
6
4
2
100
50
IB
0
0
-2
-50
-100
-150
-200
+125°C
-4
+85°C
IOS
-40°C
-6
-8
Input Common Mode Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-11:
Input Bias and Offset
FIGURE 2-8:
Input Offset Voltage vs.
Currents vs. Common-Mode Input Voltage with
TA = +85°C.
Common-Mode Voltage with VDD = 5.5V.
160
155
150
5000
TA = +125°C
DD
4000
PSRR
3000
140
135
130
125
120
115
110
2000
IB
1000
0
IOS
VDD = 5.5V
VDD = 1.8V
CMRR
-1000
-2000
-50
-25
0
25
50
75
100
125
Common Mode Input Voltage (V)
Ambient Temperature (°C)
FIGURE 2-9:
CMRR and PSRR vs.
FIGURE 2-12:
Input Bias and Offset
Ambient Temperature.
Currents vs. Common-Mode Input Voltage with
TA = +125°C.
DS20006209A-page 8
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
1000
1n
VDD = 5.5V
100
1n
IOS
100
100p
IB
10p
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
FIGURE 2-13:
Currents vs. Ambient Temperature with
DD = +5.5V.
Input Bias and Offset
V
1.E-02
10m
1.E-04
100µ
1.E-05
10µ
1.E-06
1µ
1.E-07
100n
+125°C
+85°C
+25°C
-40°C
1.E-08
10n
1.E-09
1n
1.E-10
100p
1.E-11
10p
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-14:
Input Bias Current vs. Input
Voltage (below VSS).
2019 Microchip Technology Inc.
DS20006209A-page 9
MCP6V36/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
2.2
Other DC Voltages and Currents
40
30
0.4
1 Wafer Lot
-40°C
+25°C
+85°C
+125°C
0.3
0.2
Upper ( VCMH – VDD
)
20
10
0.1
0
0.0
-10
-20
-30
-40
-0.1
-0.2
-0.3
-0.4
Lower (VCML – VSS
)
+125°C
+85°C
+25°C
-40°C
-50
-25
0
25
50
75
100 125
Ambient Temperature (°C)
Power Supply Voltage (V)
FIGURE 2-15:
Input Common-Mode
FIGURE 2-18:
Output Short Circuit Current
Voltage Headroom (Range) vs. Ambient
Temperature.
vs. Power Supply Voltage.
1000
35
Representative Part
30
25
20
15
VDD – VOH
100
VOL – VSS
VDD = 5.5V
VDD = 1.8V
10
1
+125°C
+85°C
+25°C
-40°C
10
5
0
0.1
1
10
Output Current Magnitude (mA)
Power Supply Voltage (V)
FIGURE 2-16:
Output Voltage Headroom
FIGURE 2-19:
Supply Current vs. Power
vs. Output Current.
Supply Voltage.
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
12
11
10
9
8
RL = 25 kȍ
7
VDD = 5.5V
6
5
4
3
VDD – VOH
VOL – VSS
2
VDD = 1.8V
1
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-17:
Output Voltage Headroom
FIGURE 2-20:
Power-on Reset Voltage vs.
vs. Ambient Temperature.
Ambient Temperature.
DS20006209A-page 10
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
2.3
Frequency Response
110
100
90
80
70
60
50
40
30
20
10
700
600
500
400
300
200
100
0
100
90
80
70
60
50
40
30
PM
VDD = 5.5V
VDD = 1.8V
GBWP
0
PSRR
10
1.E+01
1k
10k
1.E+04
100k
1.E+05
100
-50
-25
25
50
75
100 125
1.E+02
1.E+03
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-21:
CMRR and PSRR vs.
FIGURE 2-24:
Gain Bandwidth Product
Frequency.
and Phase Margin vs. Ambient Temperature.
70
60
50
40
30
20
10
0
0
700
600
500
400
300
200
100
0
100
90
80
70
60
50
40
30
VDD = 1.8V
RF = 1 Mȍ
C
L = 20 pF
-30
PM
-60
VDD = 5.5V
AOL
-90
-120
-150
-180
-210
-240
-270
VDD = 1.8V
GBWP
| AOL
|
-10
-20
1.E+03
1k
10k
100k
1.E+05
1M
1.E+06
1.E+04
Frequency (Hz)
Common Mode Input Voltage (V)
FIGURE 2-22:
Open-Loop Gain vs.
FIGURE 2-25:
Gain Bandwidth Product
Frequency with VDD = 1.8V.
and Phase Margin vs. Common-Mode Input
Voltage.
70
60
50
40
30
20
10
0
0
700
600
500
400
300
200
100
0
100
90
80
70
60
50
40
30
VDD = 5.5V
CL = 20 pF
VDD = 5.5V
-30
PM
-60
AOL
-90
-120
-150
-180
-210
-240
-270
| AOL
|
GBWP
VDD = 1.8V
-10
-20
1.E+03
1k
10k
1.E+04
100k
1.E+05
1M
1.E+06
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Frequency (Hz)
FIGURE 2-23:
Open-Loop Gain vs.
FIGURE 2-26:
Gain Bandwidth Product
Frequency with VDD = 5.5V.
and Phase Margin vs. Output Voltage.
2019 Microchip Technology Inc.
DS20006209A-page 11
MCP6V36/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
140
120
100
80
1.E+05
100k
VDD = 1.8V
1.E+04
10k
MCP6V3ꢀꢁ
MCP6V3ꢂ
1.E+03
1k
60
1.E+02
100
40
1.E+01
10
G = 1 V/V
G = 11 V/V
G = 101 V/V
20
1.E+00
1
1k
10k
14
100k
15
1M
1.6
1.03
100
1k
1.E+03
10k
100k
1.E+05
1M
1.E+06
1.E+02
1.E+04
Frequency (Hz)
Frequency (Hz)
FIGURE 2-27:
Closed-Loop Output
FIGURE 2-29:
Channel-to-Channel
Impedance vs. Frequency with VDD = 1.8V.
Separation vs. Frequency.
10
1.E+05
100k
VDD = 5.5V
VDD = 5.5V
1.E+04
10k
1.E+03
1k
VDD = 1.8V
1
1.E+02
100
1.E+01
10
G = 1 V/V
G = 11 V/V
G = 101 V/V
1.E+00
10
1.E+03
100
1k
1.E+03
10k
100k
1.E+05
1M
1.E+06
1k
10k
1.E+04
100k
1.E+05
1M
1.E+02
1.E+04
1.E+06
Frequency (Hz)
Frequency (Hz)
FIGURE 2-28:
Closed-Loop Output
FIGURE 2-30:
Maximum Output Voltage
Impedance vs. Frequency with VDD = 5.5V.
Swing vs. Frequency.
DS20006209A-page 12
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
2.4
Input Noise and Distortion
1000
100
10
1000
1000
100
10
GDM = 1 V/V
VDD tone = 50 mVPK
,
f = 100 Hz
eni
100
10
1
IMD tone at DC
100 Hz tone
VDD = 5.5V
VDD = 1.8V
1
VDD = 1.8V
VDD = 5.5V
Eni(0 Hz to f)
1
100k
1
10
100
1k
10k
100k
1
10
100
1k
10k
1.E+00 1.E+01 1.E+ 2 1.E+03 1.E+04 1.E+05
Frequency (Hz)
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
FIGURE 2-31:
Input Noise Voltage Density
FIGURE 2-34:
Intermodulation Distortion
and Integrated Input Noise Voltage vs.
Frequency.
vs. Frequency with VDD Disturbance
(see Figure 1-6).
80
VDD = 1.8V
f < 2 kHz
VDD = 1.8V
60
50
40
VDD = 5.5V
30
20
10
0
NPBW = 10 Hz
NPBW = 1 Hz
0
10 20 30 40 50 60 70 80 90 100
Time (s)
Common Mode Input Voltage (V)
FIGURE 2-32:
Input Noise Voltage Density
FIGURE 2-35:
Input Noise vs. Time with
vs. Input Common-Mode Voltage.
1 Hz and 10 Hz Filters and VDD = 1.8V.
1000
1.4
GDM = 1 V/V
VCM tone = 50 mVPK, f = 100 Hz
VDD = 5.5V
1.2
1.0
0.8
0.6
0.4
0.2
100
10
1
residual 100 Hz tone
0.0
NPBW = 10 Hz
-0.2
-0.4
VDD = 1.8V
VDD = 5.5V
-0.6
NPBW = 1 Hz
-0.8
1
10
100
1k
10k
100k
0
10 20 30 40 50 60 70 80 90 100
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
Time (s)
FIGURE 2-33:
Intermodulation Distortion
vs. Frequency with VCM Disturbance (see
Figure 1-6).
FIGURE 2-36:
1 Hz and 10 Hz Filters and VDD = 5.5V.
Input Noise vs. Time with
2019 Microchip Technology Inc.
DS20006209A-page 13
MCP6V36/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
2.5
Time Response
6
5
6
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
G = 1
VDD = 5.5V
G = 1
5
VDD
4
4
POR Trip Point
3
3
2
2
1
1
0
0
VOS
-1
-2
-3
-4
-1
-2
-3
-4
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Time (ms)
0
50
100 150 200 250 300 350 400
Time (µs)
FIGURE 2-37:
Input Offset Voltage vs.
FIGURE 2-40:
Noninverting Large Signal
Time at Power Up.
Step Response.
90
80
70
60
50
40
30
20
10
0
7
6
VDD = 5.5V
G = 1
VIN
VDD = 5.5V
G = -1
5
VOUT
4
3
2
1
0
-1
-10
0
1
2
3
4
5
6
7
8
9
10
0
10 20 30 40 50 60 70 80 90 100
Time (µs)
Time (ms)
FIGURE 2-38:
The MCP6V36/6U/7/9
FIGURE 2-41:
Inverting Small Signal Step
Family Shows No Input Phase Reversal with
Overdrive.
Response.
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
80
VDD = 5.5V
G = -1
VDD = 5.5V
G = 1
70
60
50
40
30
20
10
0
0
10 20 30 40 50 60 70 80 90 100
Time (µs)
0
50
100 150 200 250 300 350 400
Time (µs)
FIGURE 2-42:
Response.
Inverting Large Signal Step
FIGURE 2-39:
Step Response.
Noninverting Small Signal
DS20006209A-page 14
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
0.30
VDD = 5.5V
0.25
Falling Edge
0.20
0.15
0.10
VDD = 1.8V
0.05
Rising Edge
0.00
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-43:
Slew Rate vs. Ambient
Temperature.
7
6
5
7
6
5
4
3
2
1
0
-1
VOUT
G VIN
4
3
2
VDD = 5.5V
G = -10 V/V
0.5V Overdrive
1
G VIN
VOUT
0
-1
0
100 200 300 400 500 600 700 800 900 10001100
Time (100 µs/div)
FIGURE 2-44:
Output Overdrive Recovery
vs. Time with G = -10 V/V.
1.E
10m
0.5V Input Overdrive
VDD = 1.8V
1.E-
1m
tODR, high
VDD = 5.5V
1.E-04
100µ
tODR, low
1.E
10µ
1
10
100
1000
Inverting Gain Magnitude (V/V)
FIGURE 2-45:
Output Overdrive Recovery
Time vs. Inverting Gain.
2019 Microchip Technology Inc.
DS20006209A-page 15
MCP6V36/6U/7/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
MCP6V36 MCP6V36U
MCP6V37
MCP6V39
Symbol
Description
SOT-23,
SOT-23
2×3 TDFN MSOP
TSSOP
SC-70
1
4
1
2
1
2
1
2
VOUT, VOUTA Output (Op Amp A)
4
3
VIN–, VINA
–
Inverting Input (Op Amp A)
Noninverting Input (Op Amp A)
Positive Power Supply
3
1
3
3
3
VIN+, VINA
VDD
+
5
5
8
8
4
—
—
—
—
—
—
2
—
—
—
—
—
—
2
5
5
5
VINB
+
–
Noninverting Input (Op Amp B)
Inverting Input (Op Amp B)
Output (Op Amp B)
6
6
6
VINB
7
7
7
VOUTB
VOUTC
—
—
—
4
—
—
—
4
8
Output (Op Amp C)
9
VINC
–
+
Inverting Input (Op Amp C)
Noninverting Input (Op Amp C)
Negative Power Supply
10
11
12
13
14
—
VINC
VSS
—
—
—
—
—
—
—
—
—
—
—
9
—
—
—
—
VIND
+
Noninverting Input (Op Amp D)
Inverting Input (Op Amp D)
Output (Op Amp D)
VIND
–
VOUTD
EP
Exposed Thermal Pad (EP); must be
connected to VSS
3.1
Analog Outputs
3.4
Exposed Thermal Pad (EP)
The analog output pins (VOUT) are low-impedance
voltage sources.
There is an internal connection between the exposed
thermal pad (EP) and the VSS pin; they must be
connected to the same potential on the printed circuit
board (PCB).
3.2
Analog Inputs
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (θJA).
The noninverting and inverting inputs (VIN+, VIN–, …)
are high-impedance CMOS inputs with low bias
currents.
3.3
Power Supply Pins
The positive power supply (VDD) is 1.8V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
DS20006209A-page 16
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
NOTES:
2019 Microchip Technology Inc.
DS20006209A-page 17
MCP6V36/6U/7/9
The Low-Pass Filter reduces high-frequency content,
including harmonics of the Chopping Clock.
4.0
APPLICATIONS
The MCP6V36/6U/7/9 family of zero-drift op amps is
manufactured using Microchip’s state of the art CMOS
process. It is designed for applications with
requirements for small packages and low power. Its low
supply voltage and low quiescent current make the
MCP6V36/6U/7/9 devices ideal for battery-powered
applications.
The Output Buffer drives external loads at the VOUT pin
(VREF is an internal reference voltage).
The Oscillator runs at fOSC1 = 200 kHz. Its output is
divided by two, to produce the Chopping Clock rate of
fCHOP = 100 kHz.
The internal POR part starts the part in a known good
state, protecting against power supply brown-outs.
4.1
Overview of Zero-Drift Operation
The Digital Control block controls switching and POR
events.
Figure 4-1 shows
a
simplified diagram of the
MCP6V36/6U/7/9 zero-drift op amps. This diagram will
be used to explain how slow voltage errors are reduced
in this architecture (much better VOS, ∆VOS/∆TA (TC1),
CMRR, PSRR, AOL and 1/f noise).
4.1.2
CHOPPING ACTION
Figure 4-2 shows the amplifier connections for the first
phase of the Chopping Clock and Figure 4-3 shows
them for the second phase. Its slow voltage errors
alternate in polarity, making the average error small.
VREF
Output
VOUT
VIN+
Buffer
VIN+
Main
VIN–
Amp.
NC
Main
VIN–
Amp.
NC
Low-Pass
Filter
Low-Pass
Filter
Aux.
Amp.
Chopper
Input
Switches
Chopper
Output
Switches
Aux.
Amp.
FIGURE 4-2:
First Chopping Clock Phase;
Equivalent Amplifier Diagram.
VIN+
Oscillator
Digital Control
POR
Main
VIN–
FIGURE 4-1:
Amp Functional Diagram.
Simplified Zero-Drift Op
Amp.
NC
4.1.1
BUILDING BLOCKS
Low-Pass
Filter
The Main Amplifier is designed for high gain and
bandwidth, with a differential topology. Its main input
pair (+ and - pins at the top left) is used for the higher
frequency portion of the input signal. Its auxiliary input
pair (+ and - pins at the bottom left) is used for the low-
frequency portion of the input signal and corrects the
op amp’s input offset voltage. Both inputs are added
together internally.
Aux.
Amp.
The Auxiliary Amplifier, Chopper Input Switches and
Chopper Output Switches provide a high DC gain to the
input signal. DC errors are modulated to higher
frequencies, while white noise is modulated to low
frequency.
FIGURE 4-3:
Phase; Equivalent Amplifier Diagram.
Second Chopping Clock
DS20006209A-page 18
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
4.1.3
INTERMODULATION DISTORTION
(IMD)
Bond
Pad
VDD
VIN+
VSS
These op amps will show intermodulation distortion
(IMD) products when an AC signal is present.
The signal and clock can be decomposed into sine
wave tones (Fourier series components). These tones
interact with the zero-drift circuitry’s nonlinear response
to produce IMD tones at sum and difference frequen-
cies. Each of the square wave clock’s harmonics has a
series of IMD tones centered on it. See Figure 2-33 and
Figure 2-34.
Bond
Pad
Bond
Pad
Input
Stage
VIN–
Bond
Pad
4.2
Other Functional Blocks
FIGURE 4-4:
Simplified Analog Input ESD
Structures.
4.2.1
RAIL-TO-RAIL INPUTS
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages well above VDD; their breakdown
voltage is high enough to allow normal operation, but
not low enough to protect against slow overvoltage
(beyond VDD) events. Very fast ESD events (that meet
the spec) are limited so that damage does not occur.
The input stage of the MCP6V36/6U/7/9 op amps uses
two differential CMOS input stages in parallel. One
operates at low Common-mode input voltage (VCM
,
which is approximately equal to VIN+ and VIN– in
normal operation) and the other at high VCM. With this
topology, the input operates with VCM up to VDD + 0.2V,
and down to VSS – 0.15V, at +25°C (see Figure 2-15).
The input offset voltage (VOS) is measured at
VCM = VSS – 0.15V and VDD + 0.2V to ensure proper
operation.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-5 shows one approach to protecting these
inputs. D1 and D2 may be small signal silicon diodes,
Schottky diodes for lower clamping voltages or diode
connected FETs for low leakage.
The transition between the input stages occurs when
VCM ≈ VDD – 0.9V (see Figure 2-7 and Figure 2-8). For
the best distortion and gain linearity, with noninverting
gains, avoid this region of operation.
VDD
4.2.1.1
Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-38 shows an input voltage
exceeding both supplies with no phase inversion.
U1
D1
MCP6V3X
V1
D2
VOUT
V2
4.2.1.2
Input Voltage Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 “Absolute Maximum
Ratings †”). This requirement is independent of the
current limits discussed later on.
FIGURE 4-5:
Against High Voltages.
Protecting the Analog Inputs
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
overvoltage conditions, and to minimize input bias
current (IB).
2019 Microchip Technology Inc.
DS20006209A-page 19
MCP6V36/6U/7/9
4.2.1.3
Input Current Limits
4.3
Application Tips
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1 “Absolute
Maximum Ratings †”). This requirement is
independent of the voltage limits discussed previously.
4.3.1
INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Table 1-1 gives both the linear and quadratic
temperature coefficients (TC1 and TC2) of input offset
voltage. The input offset voltage, at any temperature in
the specified range, can be calculated as follows:
Figure 4-6 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
current in or out of the input pins (and into D1 and D2).
EQUATION 4-1:
The diode currents will dump onto VDD
.
VOSTA = VOS + TC1T + TC2T2
VDD
Where:
∆T
VOS(TA)
VOS
=
=
=
=
=
TA – 25°C
U1
D1
R1
R2
input offset voltage at TA
input offset voltage at +25°C
linear temperature coefficient
quadratic temperature coefficient
MCP6V3X
V1
V2
D2
VOUT
TC1
TC2
4.3.2
Figures 2-9 to 2-11 are histograms of the reciprocals
(in units of µV/V) of CMRR, PSRR and AOL
respectively. They represent the change in input offset
voltage (VOS) with a change in Common-mode input
voltage (VCM), power supply voltage (VDD) and output
voltage (VOUT).
DC GAIN PLOTS
VSS – min(V1, V2)
2 mA
max(V1, V2) – VDD
2 mA
min(R1, R2) >
min(R1, R2) >
,
FIGURE 4-6:
Against High Currents.
Protecting the Analog Inputs
The 1/AOL histogram is centered near 0 µV/V because
the measurements are dominated by the op amp’s
input noise. The negative values shown represent
noise and tester limitations, not unstable behavior.
Production tests make multiple VOS measurements,
which validates an op amp's stability; an unstable part
would show greater VOS variability, or the output would
stick at one of the supply rails.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Common-
mode voltage (VCM) is below ground (VSS); see
Figure 2-14.
4.3.3
OFFSET AT POWER UP
When these parts power up, the input offset (VOS
)
starts at its uncorrected value (usually less than
±5 mV). Circuits with high DC gain can cause the
output to reach one of the two rails. In this case, the
time to a valid output is delayed by an output overdrive
time (like tODR), in addition to the start-up time (like
tSTR).
4.2.2
The output voltage range of the MCP6V36/6U/7/9 zero-
drift op amps is DD – 20 mV (minimum) and
VSS + 20 mV (maximum) when RL = 10 kΩ is
connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-
16 and Figure 2-17 for more information.
RAIL-TO-RAIL OUTPUT
V
It can be simple to avoid this extra start-up time.
Reducing the gain is one method. Adding a capacitor
across the feedback resistor (RF) is another method.
This op amp is designed to drive light loads; use
another amplifier to buffer the output from heavy loads.
DS20006209A-page 20
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
GN is the circuit’s noise gain. For noninverting gains,
GN and the Signal Gain are equal. For inverting gains,
GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
4.3.4
SOURCE RESISTANCES
The input bias currents have two significant
components; switching glitches that dominate at room
temperature and below, and input ESD diode leakage
currents that dominate at +85°C and above.
1.E
10k
RL||(RF + RG) 100 k
Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.
1.E+
1k
The inputs should see a resistance on the order of 10 Ω
to 1 kΩ at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
GN = 1
GN = 10
GN = 100
1.E
100
10p
100p
1n
10n
100n
1µ
1.1 10 1.09 18 17 1.E06
Capacitive Load (F)
Small input resistances may be needed for high gains.
Without them, parasitic capacitances might cause
positive feedback and instability.
FIGURE 4-8:
for Capacitive Loads.
Recommended RISO values
4.3.5
SOURCE CAPACITANCE
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation is helpful.
The capacitances seen by the two inputs should be
small. Large input capacitances and source
resistances, together with high gain, can lead to
positive feedback and instability.
4.3.7
STABILIZING OUTPUT LOADS
4.3.6
CAPACITIVE LOADS
This family of zero-drift op amps has an output
impedance (Figure 2-27 and Figure 2-28) that has a
double zero when the gain is low. This can cause a
large phase shift in feedback networks that have low-
impedance near the part’s bandwidth. This large phase
shift can cause stability problems.
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These zero-drift op amps have a different
output impedance than most op amps, due to their
unique topology.
Figure 4-9 shows that the load on the output is
(RL + RISO)||(RF + RG), where RISO is before the load
(like Figure 4-7). This load needs to be large enough to
maintain stability; it should be at least 10 kΩ.
When driving a capacitive load with these op amps, a
series resistor at the output (RISO in Figure 4-7)
improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
RG
RF
VOUT
RL
CL
U1
MCP6V3X
Output Load.
RISO
VOUT
FIGURE 4-9:
CL
U1
MCP6V3X
FIGURE 4-7:
Output Resistor, RISO,
Stabilizes Capacitive Loads.
Figure 4-8 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
load capacitance (CL). The y-axis is the resistance
(RISO).
2019 Microchip Technology Inc.
DS20006209A-page 21
MCP6V36/6U/7/9
4.3.8
GAIN PEAKING
4.3.9
REDUCING UNDESIRED NOISE
AND SIGNALS
Figure 4-10 shows an op amp circuit that represents
noninverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s Common-mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel. The capacitance CFP represents the
parasitic capacitance coupling the output and
noninverting input pins.
Reduce undesired noise and signals with:
• Low bandwidth signal filters:
- Minimizes random analog noise
- Reduces interfering signals
• Good PCB layout techniques:
- Minimizes crosstalk
- Minimizes parasitic capacitances and
inductances that interact with fast switching
edges
• Good power supply design:
- Isolation from other parts
CN
CFP
RN
- Filtering of interference on supply line(s)
VP
4.3.10
SUPPLY BYPASSING AND
FILTERING
U1
MCP6V3X
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
of the pin for good high-frequency performance.
VM
VOUT
RG
RF
CG
These parts also need a bulk capacitor (i.e., 1 µF or
larger) within 100 mm to provide large, slow currents.
This bulk capacitor can be shared with other low noise,
analog parts.
FIGURE 4-10:
Capacitance.
Amplifier with Parasitic
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF||RG.
In some cases, high-frequency power supply noise
(e.g., switched mode power supplies) may cause
undue intermodulation distortion, with a DC offset shift;
this noise needs to be filtered. Adding a resistor into the
supply connection can be helpful.
CN and RN form a low-pass filter that affects the signal
4.3.11
PCB DESIGN FOR DC PRECISION
at VP. This filter has a single real pole at 1/(2πRNCN).
The largest value of RF that should be used depends
on noise gain (see GN in Section 4.3.6 “Capacitive
Loads”), CG and the open-loop gain’s phase shift. An
approximate limit for RF is:
In order to achieve DC precision on the order of ±1 µV,
many physical errors need to be minimized. The design
of the Printed Circuit Board (PCB), the wiring, and the
thermal environment have a strong impact on the
precision achieved. A poor PCB design can easily be
more than 100 times worse than the MCP6V36/6U/7/9
op amps’ minimum and maximum specifications.
EQUATION 4-2:
RF 10 k ------------- G2N
12 pF
CG
4.3.11.1
PCB Layout
Any time two dissimilar metals are joined together, a
temperature dependent voltage appears across the
junction (the Seebeck or thermojunction effect). This
effect is used in thermocouples to measure
temperature. The following are examples of
thermojunctions on a PCB:
Some applications may modify these values to reduce
either output loading or gain peaking (step response
overshoot).
At high gains, RN needs to be small, in order to prevent
positive feedback and oscillations. Large CN values
can also help.
• Components (resistors, op amps, …) soldered to
a copper pad
• Wires mechanically attached to the PCB
• Jumpers
• Solder joints
• PCB vias
DS20006209A-page 22
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
Typical thermojunctions have temperature to voltage
conversion coefficients of 1 to 100 µV/°C (sometimes
higher).
4.4
Typical Applications
4.4.1
WHEATSTONE BRIDGE
Microchip’s AN1258 (“Op Amp Precision Design: PCB
Layout Techniques”) contains in-depth information on
PCB layout techniques that minimize thermojunction
effects. It also discusses other effects, such as
crosstalk, impedances, mechanical stresses and
humidity.
Many sensors are configured as Wheatstone bridges.
Strain gauges and pressure sensors are two common
examples. These signals can be small and the
Common-mode noise large. Amplifier designs with
high differential gain are desirable.
Figure 4-11 shows how to interface to a Wheatstone
bridge with a minimum of components. Because the
circuit is not symmetric, the ADC input is single ended,
and there is a minimum of filtering; the CMRR is good
enough for moderate Common-mode noise.
4.3.11.2
Crosstalk
DC crosstalk causes offsets that appear as a larger
input offset voltage. Common causes include:
• Common-mode noise (remote sensors)
• Ground loops (current return paths)
• Power supply coupling
0.01C
100R
VDD
1 kΩ
VDD
R
R
ADC
Interference from the mains (usually 50 Hz or 60 Hz),
and other AC sources, can also affect the DC
performance. Nonlinear distortion can convert these
signals to multiple tones, including a DC shift in voltage.
When the signal is sampled by an ADC, these AC
signals can also be aliased to DC, causing an apparent
shift in offset.
0.2R
0.2R
U1
MCP6V36
R
R
FIGURE 4-11:
Simple Design.
To reduce interference:
4.4.2 RTD SENSOR
- Keep traces and wires as short as possible
- Use shielding
The ratiometric circuit in Figure 4-12 conditions a two-
wire RTD, for applications with a limited temperature
range. U1 acts a difference amplifier, with a low-
frequency pole. The sensor’s wiring resistance (RW) is
corrected in firmware. Failure (open) of the RTD is
detected by an out-of-range voltage.
- Use ground plane (at least a star ground)
- Place the input signal source near to the DUT
- Use good PCB layout techniques
- Use a separate power supply filter (bypass
capacitors) for these zero-drift op amps
VDD
4.3.11.3
Miscellaneous Effects
RT
34.8 kΩ
RN
10.0 kΩ
Keep the resistances seen by the input pins as small
and as near to equal as possible, to minimize bias-
current-related offsets.
10 nF
RF
2.00 MΩ
RW
Make the (trace) capacitances seen by the input pins
small and equal. This is helpful in minimizing switching
glitch-induced offset voltages.
U1
RRTD
100Ω
MCP6V36
Bending a coax cable with a radius that is too small
causes a small voltage drop to appear on the center
conductor (the triboelectric effect). Make sure the
bending radius is large enough to keep the conductors
and insulation in full contact.
1.00 kΩ
RG
RF
RW
10.0 kΩ 2.00 MΩ
100 nF
VDD
RB
4.99 kΩ
10 nF
1.0 µF
Mechanical stresses can make some capacitor types
(such as some ceramics) output small voltages. Use
more appropriate capacitor types in the signal path and
minimize mechanical stresses and vibration.
ADC
FIGURE 4-12:
RTD Sensor.
Humidity can cause electrochemical potential voltages
to appear in a circuit. Proper PCB cleaning helps, as
does the use of encapsulants.
2019 Microchip Technology Inc.
DS20006209A-page 23
MCP6V36/6U/7/9
4.4.3
OFFSET VOLTAGE CORRECTION
Figure 4-13 shows MCP6V36 (U2) correcting the input
offset voltage of another op amp (U1). R2 and C2
integrate the offset error seen at U1’s input; the
integration needs to be slow enough to be stable (with
the feedback provided by R1 and R3). R4 and R5
attenuate the integrator’s output; this shifts the
integrator pole down in frequency.
R1
R2
R3
VIN
VOUT
R4
R5
C2
U1
MCP6XXX
VDD/2
R2
VDD/2
U2
MCP6V36
FIGURE 4-13:
Offset Correction.
4.4.4 PRECISION COMPARATOR
Use high gain before a comparator to improve the
latter’s performance. Do not use MCP6V36/6U/7/9 as
a comparator by itself; the VOS correction circuitry does
not operate properly without a feedback loop.
U1
VIN
MCP6V36
R1
R2
R3
R4
R5
VOUT
VDD/2
U2
MCP6541
FIGURE 4-14:
Precision Comparator.
DS20006209A-page 24
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
NOTES:
2019 Microchip Technology Inc.
DS20006209A-page 25
MCP6V36/6U/7/9
5.4
Application Notes
5.0
DESIGN AIDS
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/sitesearch/Search/all and are recommended as
supplemental reference resources.
Microchip provides the basic design aids needed for
the MCP6V36/6U/7/9 family of op amps.
5.1
SPICE Macro Model
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
The latest SPICE macro model for the
MCP6V36/6U/7/9 op amps is available on the Micro-
chip web site at www.microchip.com. This model is
intended to be an initial design tool that works well in
the op amp’s linear region of operation over the
temperature range. See the model file for information
on its capabilities.
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
5.2
Microchip Advanced Part Selector
(MAPS)
AN1228: “Op Amp Precision Design: Random Noise”,
DS01228
AN1258: “Op Amp Precision Design: PCB Layout
Techniques”, DS01258
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design require-
ment. Available at no cost from the Microchip web site
at www.microchip.com/maps, MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool, a customer can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for Data Sheets, Purchase and Sampling of
Microchip parts.
These Application Notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
5.3
Analog Demonstration and
Evaluation Boards
Microchip offers
a
broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help customers achieve faster time to
market. For a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at
www.microchip.com/treelinktool.
Some boards that are especially useful are:
• MCP6V01 Thermocouple Auto-Zeroed Reference
Design (P/N MCP6V01RD-TCPL)
• MCP6XXX Amplifier Evaluation Board 2 (P/N
DS51668)
• MCP6XXX Amplifier Evaluation Board 3 (P/N
DS51673)
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board
(P/N SOIC8EV)
• 14-Pin SOIC/TSSOP/DIP Evaluation Board (P/N
SOIC14EV)
DS20006209A-page 26
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
NOTES:
2019 Microchip Technology Inc.
DS20006209A-page 27
MCP6V36/6U/7/9
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SC70 (MCP6V36U)
Example:
FS25
Device
MCP6V36UT-E/LTY
Code
FSNN
Note:
Applies to 5-Lead SC-70.
5-Lead SOT-23 (MCP6V36, MCP6V36U)
Example:
Device
MCP6V36T-E/OT
Code
RBDF
WWNNN
RBDF
10256
MCP6V36UT-E/OT
RBDG
WWNNN
Note:
Applies to 5-Lead SOT-23.
8-Lead MSOP (3 x 3 mm) (MCP6V37)
Example
6V37E
410256
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20006209A-page 28
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
8-Lead TDFN (2 x 3 x 0.8 mm) (MCP6V37)
Example
Device
Code
MCP6V37-E/MNY
MCP6V37T-E/MNY
DM2
DM2
DM2
410
25
Note:
Applies to 8-Lead 2x3 TDFN.
14-Lead TSSOP (4.4 mm) (MCP6V39)
Example
XXXXXXXX
YYWW
6V39E/ST
1410
256
NNN
2019 Microchip Technology Inc.
DS20006209A-page 29
MCP6V36/6U/7/9
5-Lead Plastic Small Outline Transistor (LT) [SC70]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
e
e
B
E
3
1
E1
2X
0.15 C
4
N
5X TIPS
0.30 C
NOTE 1
2X
0.15 C
5X b
0.10
C A B
TOP VIEW
c
A2
A
C
SEATING
PLANE
A1
L
SIDE VIEW
END VIEW
Microchip Technology Drawing C04-061D Sheet 1 of 2
DS20006209A-page 30
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
5-Lead Plastic Small Outline Transistor (LT) [SC70]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
5
0.65 BSC
Overall Height
Standoff
Molded Package Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
A
A1
A2
D
D2
E
E1
b
L
c
0.80
0.00
0.80
-
-
1.10
0.10
1.00
-
2.00 BSC
2.60
2.10 BSC
1.25 BSC
-
2.50
2.70
0.15
0.10
0.08
0.40
0.46
0.26
Terminal Length
Lead Thickness
0.20
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-061D Sheet 2 of 2
2019 Microchip Technology Inc.
DS20006209A-page 31
MCP6V36/6U/7/9
5-Lead Plastic Small Outline Transistor (LT) [SC70]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
Gx
SILK SCREEN
3
4
2
1
5
C
G
Y
X
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.65 BSC
2.20
MAX
Contact Pitch
E
C
Contact Pad Spacing
Contact Pad Width
Contact Pad Length
Distance Between Pads
Distance Between Pads
X
Y
G
Gx
0.45
0.95
1.25
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2061B
DS20006209A-page 32
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A2
A1
A
0.20 C
SEATING PLANE
A
SEE SHEET 2
C
SIDE VIEW
Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2
2019 Microchip Technology Inc.
DS20006209A-page 33
MCP6V36/6U/7/9
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
5
0.95 BSC
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
e1
A
A2
A1
E
E1
D
L
1.90 BSC
0.90
0.89
-
-
-
-
1.45
1.30
0.15
2.80 BSC
1.60 BSC
2.90 BSC
0.30
-
0.60
Footprint
Foot Angle
Lead Thickness
Lead Width
L1
0.60 REF
I
0°
0.08
0.20
-
-
-
10°
0.26
0.51
c
b
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2
DS20006209A-page 34
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.95 BSC
2.80
MAX
Contact Pitch
E
C
Contact Pad Spacing
Contact Pad Width (X5)
Contact Pad Length (X5)
Distance Between Pads
Distance Between Pads
Overall Width
X
Y
G
GX
Z
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091B [OT]
2019 Microchip Technology Inc.
DS20006209A-page 35
MCP6V36/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006209A-page 36
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006209A-page 37
MCP6V36/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006209A-page 38
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E
N
(DATUM A)
(DATUM B)
NOTE 1
2X
0.15 C
2X
1
2
0.15 C
TOP VIEW
0.10 C
(A3)
C
A
SEATING
PLANE
8X
A1
L
0.08 C
C A B
SIDE VIEW
0.10
D2
1
2
0.10
C A B
NOTE 1
E2
K
N
8X b
0.10
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing No. C04-129-MN Rev E Sheet 1 of 2
2019 Microchip Technology Inc.
DS20006209A-page 39
MCP6V36/6U/7/9
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Length
Overall Width
Exposed Pad Length
Exposed Pad Width
Contact Width
Contact Length
N
8
e
0.50 BSC
0.75
A
A1
A3
D
0.70
0.00
0.80
0.05
0.02
0.20 REF
2.00 BSC
3.00 BSC
1.40
E
D2
E2
b
L
K
1.35
1.25
0.20
0.25
0.20
1.45
1.35
0.30
0.45
-
1.30
0.25
0.30
-
Contact-to-Exposed Pad
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04-129-MN Rev E Sheet 2 of 2
DS20006209A-page 40
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X2
EV
8
ØV
C
Y2
EV
Y1
1
2
SILK SCREEN
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C
1.60
1.50
2.90
Contact Pad Width (X8)
Contact Pad Length (X8)
Thermal Via Diameter
Thermal Via Pitch
X1
Y1
V
0.25
0.85
0.30
1.00
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing No. C04-129-MN Rev. B
2019 Microchip Technology Inc.
DS20006209A-page 41
MCP6V36/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006209A-page 42
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006209A-page 43
MCP6V36/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006209A-page 44
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
APPENDIX A: REVISION HISTORY
Revision A (July 2019)
• Initial release of this document.
2019 Microchip Technology Inc.
DS20006209A-page 45
MCP6V36/6U/7/9
NOTES:
DS20006209A-page 46
2019 Microchip Technology Inc.
MCP6V36/6U/7/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
[X]
Examples:
PART NO.
–X
/XX
a)
MCP6V36T-E/OT:
Tape and Reel,
Extended temperature,
5LD SOT-23 package
Device Tape and Reel
Temperature
Range
Package
a)
b)
MCP6V36UT-E/LTY: Tape and Reel
Device:
MCP6V36T: Single Op Amp (Tape and Reel) (SOT-23)
MCP6V36UT: Single Op Amp (Tape and Reel)
(SC-70, SOT-23)
Extended temperature,
5LD SC70 package
MCP6V36UT-E/OT: Tape and Reel,
MCP6V37:
Dual Op Amp (MSOP, 2x3 TDFN)
Extended temperature,
5LD SOT-23 package
MCP6V37T: Dual Op Amp (Tape and Reel) (MSOP,
2x3 TDFN)
MCP6V39:
Quad Op Amp (TSSOP)
a)
b)
MCP6V37-E/MS:
Extended temperature,
8LD MSOP package
MCP6V39T: Quad Op Amp (Tape and Reel) (TSSOP)
MCP6V37T-E/MS: Tape and Reel,
Extended temperature,
8LD MSOP package
MCP6V37T-E/MNY: Tape and Reel,
Temperature Range:
Package:
E
= -40°C to +125°C (Extended)
c)
Extended temperature,
8LD 2x3 TDFN package
LTY*
OT
=
Plastic Small Outline Transistor, 5-lead
= Plastic Small Outline Transistor, 5-lead
MNY* = Plastic Dual Flat, No-Lead - 2×3×0.8 mm Body,
8-lead
a)
b)
MCP6V39-E/ST:
MCP6V39T-E/ST:
Extended temperature,
14LD TSSOP package
MS
ST
= Plastic Micro Small Outline, 8-lead
= Plastic Thin Shrink Small Outline - 4.4 mm
Body, 14-lead
Tape and Reel
Extended temperature,
14LD TSSOP package
* Y = Nickel palladium gold manufacturing designator. Only
available on the TDFN and SC-70 packages.
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
2019 Microchip Technology Inc.
DS20006209A-page 47
MCP6V36/6U/7/9
NOTES:
DS20006209A-page 48
2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4576-0
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2019 Microchip Technology Inc.
DS20006209A-page 49
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
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Technical Support:
http://www.microchip.com/
support
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Tel: 86-10-8569-7000
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Tel: 91-11-4160-8631
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
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Tel: 86-28-8665-5511
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Tel: 358-9-4520-820
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Tel: 49-89-627-144-0
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Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20006209A-page 50
2019 Microchip Technology Inc.
05/14/19
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