MCP6V16UT-EOT_技术文档

MCP6V16/6U/7/9

7.5 µA, 80 kHz Zero-Drift Op Amps

Features

Description

• High DC Precision:

The Microchip Technology Inc. MCP6V16/6U/7/9

family of operational amplifiers provides input offset

voltage correction for very low offset and offset drift.

These are low-power devices, with a gain bandwidth

product of 80 kHz (typical). They are unity gain stable,

have virtually no 1/f noise, and have good Power

Supply Rejection Ratio (PSRR) and Common-Mode

Rejection Ratio (CMRR). These products operate with

a single supply voltage as low as 1.6V, while drawing

7.5 µA/amplifier (typical) of quiescent current.

- V_OSDrift: ±150 nV/°C (maximum)

- V_OS: ±25 µV (maximum)

- A_OL: 102 dB (minimum, V_DD= 5.5V)

- PSRR: 108 dB (minimum, V_DD= 5.5V)

- CMRR: 109 dB (minimum, V_DD= 5.5V)

- E_ni: 2.1 µV_P-P(typical), f = 0.1 Hz to 10 Hz

- E_ni: 0.67 µV_P-P(typical), f = 0.01 Hz to 1 Hz

• Low Power and Supply Voltages:

- I_Q: 7.5 µA/amplifier (typical)

The Microchip Technology Inc. MCP6V16/6U/7/9 op

amps are offered in single (MCP6V16 and

MCP6V16U), dual (MCP6V17) and quad (MCP6V19)

packages. They were designed using an advanced

CMOS process.

- Wide Supply Voltage Range: 1.6V to 5.5V

• Small Packages:

- Singles in SC70, SOT-23

- Duals in MSOP-8, 2×3 TDFN

- Quads in TSSOP-14

Package Types

• Easy to Use:

MCP6V16

SOT-23

MCP6V17

MSOP

- Rail-to-Rail Input/Output

- Gain Bandwidth Product: 80 kHz (typical)

- Unity Gain Stable

V_DD

8

1

2

3

4

V_OUT

V_SS

V_DDV_OUTA

1

5

4

V_OUTB

7

6

5

V_INA

–

+

2

3

• Extended Temperature Range: -40°C to +125°C

V_INB

–

+

V_IN+

V_IN–

V_INB

V_SS

Typical Applications

MCP6V16U

SC70, SOT-23

• Portable Instrumentation

• Sensor Conditioning

MCP6V17

2×3 TDFN*

• Temperature Measurement

• DC Offset Correction

V_OUTA

V_DD

1

8

V_IN+

V_SS

V_DD

1

2

3

5

V_INA

–

+

V_OUTB

2

3

4

7

6

5

EP

9

• Medical Instrumentation

V_INA

V_INB

–

+

V_IN–

V_OUT

4

V_SS

Design Aids

• SPICE Macro Models

MCP6V19

TSSOP

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

V

1

14

13

12

11

10

9

V_OUTA

OUTD

V

–

+

2

3

4

5

6

7

V_INA

–

+

IND

SS

Related Parts

V_DD

V

+

–

V_INB

+

–

INC

• MCP6V01/2/3: Auto-Zeroed, Spread Clock

• MCP6V06/7/8: Auto-Zeroed

V_INC

V_OUTC

V_OUTB

8

• MCP6V11/1U/2/4: Zero-Drift, Low Power

• MCP6V26/7/8: Auto-Zeroed, Low Noise

• MCP6V31/1U/2/4: Zero-Drift, Low Power

* Includes Exposed Thermal Pad (EP); see

Table 3-1.

 2019 Microchip Technology Inc.

DS20006204A-page 1

MCP6V16/6U/7/9

Typical Application Circuit

R₁

R₃

V_IN

V_OUT

R₂

R₄

R₅

C₂

U₁

MCP6XXX

V_DD/2

R₂

V_DD/2

U₂

MCP6V16

Offset Voltage Correction for Power Driver

DS20006204A-page 2

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

1.0

1.1

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

V_DD– V_SS.................................................................................................................................................................6.5V

Current at Input Pins ..............................................................................................................................................±2 mA

Analog Inputs (V_IN+ and V_IN–) (Note 1) .....................................................................................V_SS– 1.0V to V_DD+1.0V

All other Inputs and Outputs .......................................................................................................V_SS– 0.3V to V_DD+0.3V

Difference Input voltage .................................................................................................................................|V_DD– V_SS

|

Output Short Circuit Current ...........................................................................................................................Continuous

Current at Output and Supply Pins ......................................................................................................................±30 mA

Storage Temperature .............................................................................................................................-65°C to +150°C

Maximum Junction Temperature .......................................................................................................................... +150°C

ESD protection on all pins (HBM, CDM, MM)   2 kV, 1.5 kV, 400V

Note 1: See Section 4.2.1, Rail-to-Rail Inputs.

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

1.2

Specifications

DC ELECTRICAL SPECIFICATIONS

TABLE 1-1:

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +1.6V to +5.5V, V_SS= GND,

V_CM= V_DD/3,V_OUT= V_DD/2, V_L= V_DD/2, R_L= 100 kΩ to V_Land C_L= 20 pF (refer to Figure 1-4 and Figure 1-5).

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Input Offset

Input Offset Voltage

V_OS

TC₁

-25

—

+25

µV

T_A= +25°C

Input Offset Voltage Drift with

Temperature (Linear Temp. Co.)

-150

+150

nV/°C T_A= -40 to +125°C

(Note 1)

Input Offset Voltage Quadratic

Temp. Co.

TC₂

—

±0.08

135

—

nV/°C²T_A= -40 to +125°C

Power Supply Rejection Ratio

Input Bias Current and Impedance

Input Bias Current

PSRR

108

dB

I_B

—

0

+5

+17

—

+5

—

+1

—

pA

Input Bias Current across Temperature

pA

nA

T_A= +85°C

I_B

+2.9

±50

T_A= +125°C

Input Offset Current

I_OS

Z_CM

Z_DIFF

—

-1

—

pA

Input Offset Current across Temperature

±80

pA

T_A= +85°C

±0.4

nA

T_A= +125°C

Common-Mode Input Impedance

Differential Input Impedance

10¹³||6

Ω||pF

Note 1: For Design Guidance only; not tested.

2: Figure 2-15 shows how V_CMLand V_CMHchanged across temperature for the first production lot.

 2019 Microchip Technology Inc.

DS20006204A-page 3

MCP6V16/6U/7/9

TABLE 1-1:

DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +1.6V to +5.5V, V_SS= GND,

V_CM= V_DD/3,V_OUT= V_DD/2, V_L= V_DD/2, R_L= 100 kΩ to V_Land C_L= 20 pF (refer to Figure 1-4 and Figure 1-5).

Parameters

Common-Mode

Sym.

Min.

Typ.

Max.

Units

Conditions

Common-Mode

Input Voltage Range Low

V_CML

—

V_SS 0.15

V

(Note 2)

Common-Mode

Input Voltage Range High

V_CMHV_DD+ 0.2

—

(Note 2)

Common-Mode Rejection Ratio

CMRR

98

125

dB

V_DD= 1.6V,

V_CM= -0.15V to 1.8V

(Note 2)

109

135

—

dB

V_DD= 5.5V,

V_CM= -0.15V to 5.7V

(Note 2)

Open-Loop Gain

DC Open-Loop Gain (large signal)

A_OL

90

120

135

—

dB

V_DD= 1.6V,

V_OUT= 0.3V to 1.4V

102

V_DD= 5.5V,

V_OUT= 0.3V to 5.3V

Output

Minimum Output Voltage Swing

V_OL

V_OH

V_SS

—

V_SS+ 14 V_SS+ 45

mV R_L= 10 kΩ, G = +2,

0.5V input overdrive

V_SS+ 1.4

—

V_DD

—

mV R_L= 100 kΩ, G = +2,

0.5V input overdrive

Maximum Output Voltage Swing

Output Short Circuit Current

V_DD– 45 V_DD– 14

mV R_L= 10 kΩ, G = +2,

0.5V input overdrive

—

V_DD– 1.4

mV R_L= 100 kΩ, G = +2,

0.5V input overdrive

I_SC

—

±5

—

mA V_DD= 1.6V

mA V_DD= 5.5V

±17

Power Supply

Supply Voltage

V_DD

I_Q

1.6

4

—

7.5

6.5

—

5.5

11

V

Quiescent Current per Amplifier

µA

I_O= 0, MCP6V16/6U

I_O= 0, MCP6V17/19

3

11

POR Trip Voltage

V_POR

0.9

1.5

V

Note 1: For Design Guidance only; not tested.

2: Figure 2-15 shows how V_CMLand V_CMHchanged across temperature for the first production lot.

DS20006204A-page 4

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

TABLE 1-2:

AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +1.6V to +5.5V, V_SS= GND,

V_CM= V_DD/3, V_OUT= V_DD/2, V_L= V_DD/2, R_L= 100 kΩ to V_Land C_L= 20 pF (refer to Figure 1-4 and Figure 1-5).

Parameters

Sym. Min. Typ. Max. Units

Conditions

Amplifier AC Response

Gain Bandwidth Product

Slew Rate

GBWP

SR

—

80

0.03

70

—

kHz

V/µs

°

Phase Margin

PM

G = +1

Amplifier Noise Response

Input Noise Voltage

E_ni

e_ni

i_ni

—

0.67

2.1

102

4

—

µV_P-Pf = 0.01 Hz to 1 Hz

µV_P-Pf = 0.1 Hz to 10 Hz

nV/√Hz f < 500 Hz

fA/√Hz

Input Noise Voltage Density

Input Noise Current Density

Amplifier Distortion (Note 1)

Intermodulation Distortion (AC)

Amplifier Step Response

Start Up Time

IMD

—

50

—

µV_PKV_CMtone = 50 mV_PKat 100 Hz, G_N= 1

t_STR

t_STL

—

2

—

ms

µs

G = +1, 0.1% V_OUTsettling (Note 2)

Offset Correction Settling Time

300

G = +1, V_INstep of 2V,

V_OSwithin 100 µV of its final value

Output Overdrive Recovery Time t_ODR

—

450

—

µs

G = -10, ±0.5V input overdrive to V_DD/2,

V_IN50% point to V_OUT90% point (Note 3)

Note 1: These parameters were characterized using the circuit in Figure 1-6. In Figure 2-33 and Figure 2-34,

there is an IMD tone at DC, a residual tone at1 kHz and other IMD tones and clock tones.

2: High gains behave differently; see Section 4.3.3, Offset at Power Up.

3:

t

_ODRincludes some uncertainty due to clock edge timing.

TABLE 1-3:

TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: V_DD= +1.6V to +5.5V,

V_SS= GND.

Parameters

Temperature Ranges

Sym.

Min.

Typ.

Max.

Units

Conditions

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

T_A

-40

-65

—

+125

+150

°C

(Note 1)

Thermal Package Resistances

Thermal Resistance, 5L-SC-70

_JA

θ_JA

—

209

201

53

—

°C/W

Thermal Resistance, 5L-SOT-23

Thermal Resistance, 8L-2×3 TDFN

Thermal Resistance, 8L-MSOP

Thermal Resistance, 14L-TSSOP

211

100

Note 1: Operation must not cause T_Jto exceed Maximum Junction Temperature specification (+150°C).

 2019 Microchip Technology Inc.

DS20006204A-page 5

MCP6V16/6U/7/9

1.3

Timing Diagrams

1.4

Test Circuits

The circuits used for most DC and AC tests are shown

in Figure 1-4 and Figure 1-5. Lay the bypass capacitors

out as discussed in Section 4.3.10, Supply Bypassing

and Filtering. R_Nis equal to the parallel combination of

R_Fand R_Gto minimize bias current effects.

1.6V to 5.5V

1.6V

0V

V_DD

t_STR

1.001(V_DD/3)

0.999(V_DD/3)

V_OUT

V_DD

1 µF

R_N

MCP6V1X

V_DD/3

V_IN

FIGURE 1-1:

Amplifier Start Up.

R_ISO

C_L

V_OUT

V_IN

R_L

100 nF

R_F

t_STL

V_OS+ 100 µV

_OS– 100 µV

V_L

R_G

V_OS

V

FIGURE 1-4:

AC and DC Test Circuit for

Most Noninverting Gain Conditions.

FIGURE 1-2:

Offset Correction Settling

Time.

V_DD

1 µF

R_N

V_DD/3

V_IN

R_ISO

C_L

V_OUT

MCP6V1X

t_ODR

R_L

100 nF

R_F

V_IN

V_DD

V_L

R_G

t_ODR

V_OUT

V_DD/2

FIGURE 1-5:

AC and DC Test Circuit for

Most Inverting Gain Conditions.

V_SS

The circuit in Figure 1-6 tests the input’s dynamic

FIGURE 1-3:

Output Overdrive Recovery.

behavior (i.e., IMD, t_STR, t_STLand t_ODR). The

potentiometer balances the resistor network (V_OUT

should equal V_REFat DC). The op amp’s Common-

mode input voltage is V_CM= V_IN/2. The error at the

input (V_ERR) appears at V_OUTwith a noise gain of

10 V/V.

11.0 kΩ 100 kΩ 500Ω

0.1%

0.1% 25 turn

V_REF= V_DD/3

V_DD

R_ISO

0Ω

1 µF

V_OUT

V_IN

100 nF

C_L

20 pF

R_L

open

MCP6V1X

V_L

11.0 kΩ

100 kΩ 249Ω

1%

0.1%

FIGURE 1-6:

Test Circuit for Dynamic

Input Behavior.

DS20006204A-page 6

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.6V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 100 kΩ to V_Land C_L= 20 pF.

2.1

DC Input Precision

8

6

40%

35%

30%

25%

20%

15%

10%

5%

V_CM= V_CML

52 Samples

Representative Part

T_A= +25°C

V_DD= 1.6V and 5.5V

4

2

-40°C

+25°C

+85°C

+125°C

0

-2

-4

-6

-8

0%

-8

-6

-4

-2

0

2

4

6

8

Input Offset Voltage (µV)

Power Supply Voltage (V)

FIGURE 2-1:

Input Offset Voltage.

FIGURE 2-4:

Input Offset Voltage vs.

Power Supply Voltage with V_CM= V_CML

.

8

55%

V_CM= V_CMH

Representative Part

+125°C

+85°C

+25°C

-40°C

52 Samples

V_DD= 1.6V and 5.5V

6

4

50%

45%

40%

35%

30%

25%

20%

15%

10%

5%

2

0

-2

-4

-6

-8

0%

-40

-30

-20

-10

0

10

20

30

40

Input Offset Voltage Drift; TC₁(nV/°C)

Power Supply Voltage (V)

FIGURE 2-2:

Input Offset Voltage Drift.

FIGURE 2-5:

Input Offset Voltage vs.

Power Supply Voltage with V_CM= V_CMH

.

8

50%

Representative Part

52 Samples

V_DD= 1.6V and 5.5V

6

4

45%

40%

35%

30%

25%

20%

15%

10%

5%

2

V_DD= 5.5V

0

V_DD= 1.6V

-2

-4

-6

-8

0%

-160 -120 -80

-40

0

40

80

120 160

Input Offset Voltage's Quadratic Temp Co;

TC_2ꢀ(pV/°C²)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

FIGURE 2-3:

Input Offset Voltage

FIGURE 2-6:

Input Offset Voltage vs.

Quadratic Temp. Co.

Output Voltage.

 2019 Microchip Technology Inc.

DS20006204A-page 7

MCP6V16/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.6V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 100 kΩ to V_Land C_L= 20 pF.

160

155

150

145

140

135

130

125

120

115

110

8

6

V_DD= 1.6V

Representative Part

4

V_DD= 5.5V

V_DD= 1.6V

2

0

-2

-4

-6

-8

-40°C

+25°C

+85°C

+125°C

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

-50

-25

0

25

50

75

100

125

Input Common Mode Voltage (V)

Ambient Temperature (°C)

FIGURE 2-7:

Input Offset Voltage vs.

FIGURE 2-10:

DC Open-Loop Gain vs.

Common-Mode Voltage with V_DD= 1.6V.

Ambient Temperature.

8

200

T_A= +85°C

V_DD= 5.5V

150

Representative Part

6

4

2

0

100

50

I_B

0

-2

-50

-100

-150

-200

-40°C

+25°C

-4

+85°C

+125°C

I_OS

-6

-8

Input Common Mode Voltage (V)

Common Mode Input Voltage (V)

FIGURE 2-8:

Input Offset Voltage vs.

FIGURE 2-11:

Input Bias and Offset

Common-Mode Voltage with V_DD= 5.5V.

Currents vs. Common-Mode Input Voltage with

T_A= +85°C.

160

155

5000

T_A= +125°C

V

_DD

= 5.5V

4000

150

PSRR

3000

2000

145

140

135

130

125

120

I_B

1000

0

I_OS

CMRR

-1000

-2000

V_DD= 5.5V

V_DD= 1.6V

115

110

-50

-25

0

25

50

75

100

125

Ambient Temperature (°C)

Common Mode Input Voltage (V)

FIGURE 2-9:

CMRR and PSRR vs.

FIGURE 2-12:

Input Bias and Offset

Ambient Temperature.

Currents vs. Common-Mode Input Voltage with

T_A= +125°C.

DS20006204A-page 8

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.6V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 100 kΩ to V_Land C_L= 20 pF.

10000

10n

V_DD= 5.5V

1000

1n

100

100p

I_OS

10

10p

I_B

1

1p

25 35 45 55 65 75 85 95 105 115 125

Ambient Temperature (°C)

FIGURE 2-13:

Currents vs. Ambient Temperature with

_DD= +5.5V.

Input Bias and Offset

V

1.E-02

10m

1.E-03

1m

1.E-04

100µ

1.E-05

10µ

1.E-06

1µ

1.E- 7

100n

+125°C

+85°C

+25°C

-40°C

1.E-08

10n

1.E-09

1n

1.E-10

100p

1.E-11

10p

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

FIGURE 2-14:

Input Bias Current vs. Input

Voltage (below V_SS).

 2019 Microchip Technology Inc.

DS20006204A-page 9

MCP6V16/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.6V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 100 kΩ to V_Land C_L= 20 pF.

2.2

Other DC Voltages and Currents

40

30

0.4

1 Wafer Lot

-40°C

+25°C

+85°C

+125°C

0.3

0.2

Upper ( V_CMH– V_DD

)

20

10

0.1

0

0.0

-10

-20

-30

-40

-0.1

-0.2

-0.3

-0.4

Lower (V_CML– V_SS

)

+125°C

+85°C

+25°C

-40°C

-50

-25

0

25

50

75

100 125

Ambient Temperature (°C)

Power Supply Voltage (V)

FIGURE 2-15:

Input Common-Mode

FIGURE 2-18:

Output Short Circuit Current

Voltage Headroom (Range) vs. Ambient

Temperature.

vs. Power Supply Voltage.

1000

11

10

9

Representative Part

8

7

6

V_DD– V_OH

V_OL– V_SS

100

V_DD= 5.5V

V_DD= 1.6V

5

4

3

2

1

0

10

1

+125°C

+85°C

+25°C

-40°C

0.1

1

10

Output Current Magnitude (mA)

Power Supply Voltage (V)

FIGURE 2-16:

Output Voltage Headroom

FIGURE 2-19:

Supply Current vs. Power

vs. Output Current.

Supply Voltage.

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

12

11

10

9

8

R_L= 25 kȍ

7

V_DD= 5.5V

6

5

4

3

V_DD– V_OH

2

V_OL– V_SS

V_DD= 1.6V

1

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Ambient Temperature (°C)

FIGURE 2-17:

Output Voltage Headroom

FIGURE 2-20:

Power-on Reset Voltage vs.

vs. Ambient Temperature.

Ambient Temperature.

DS20006204A-page 10

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.6V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 100 kΩ to V_Land C_L= 20 pF.

2.3

Frequency Response

100

90

80

70

60

50

40

30

20

10

0

140

120

100

80

100

90

80

70

60

50

40

30

PM

V_DD= 5.5V

CMRR

60

40

V_DD= 1.6V

GBWP

PSRR

20

0

10

1.E+01

1k

10k

1.E+04

100k

1.E+05

-50

-25

0

25

50

75

100 125

100

1.E+02

1.E+03

Ambient Temperature (°C)

Frequency (Hz)

FIGURE 2-21:

CMRR and PSRR vs.

FIGURE 2-24:

Gain Bandwidth Product

Frequency.

and Phase Margin vs. Ambient Temperature.

70

60

50

40

30

20

10

0

140

120

100

80

100

90

80

70

60

50

40

30

V_DD= 1.6V

R_F= 1 M

PM

GBWP

C

_L= 20 pF

-30

-60

-90

-120

-150

-180

-210

-240

-270

A_OL

60

V_DD= 5.5V

40

| A_OL

|

V_DD= 1.6V

20

-10

0

-20

1.E+02

100

1k

10k

1.E+04

100k

1.E+05

1M

1.E+06

1.E+03

Frequency (Hz)

Common Mode Input Voltage (V)

FIGURE 2-22:

Open-Loop Gain vs.

FIGURE 2-25:

Gain Bandwidth Product

Frequency with V_DD= 1.6V.

and Phase Margin vs. Common-Mode Input

Voltage.

70

60

50

40

30

20

10

0

140

120

100

80

100

90

80

70

60

50

40

30

V_DD= 5.5V

C_L= 20 pF

V_DD= 5.5V

-30

GBWP

-60

-90

-120

-150

-180

-210

-240

-270

PM

A_OL

60

40

| A_OL

|

V_DD= 1.6V

20

-10

-20

0

100

1.E+02

1k

1.E+03

10k

1.E+04

100k

1.E+05

1M

1.E+06

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Frequency (Hz)

FIGURE 2-23:

Open-Loop Gain vs.

FIGURE 2-26:

Gain Bandwidth Product

Frequency with V_DD= 5.5V.

and Phase Margin vs. Output Voltage.

 2019 Microchip Technology Inc.

DS20006204A-page 11

MCP6V16/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.6V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 100 kΩ to V_Land C_L= 20 pF.

1.E+05

100k

140

120

100

80

V_DD= 1.6V

1.E+04

10k

1.E+03

1k

MCP6V17

MCP6V19

60

1.E+02

100

40

1.E+01

10

G = 1 V/V

G = 11 V/V

G = 101 V/V

20

1.E+00

1

0

100

1k

1.E+03

10k

100k

1.E+05

1M

1.E+06

1k

10k

1.E+04

100k

1.E+05

1M

1.E+0

1.E+03

1.E+02

1.E+04

Frequency (Hz)

FIGURE 2-27:

Closed-Loop Output

FIGURE 2-29:

Channel-to-Channel

Impedance vs. Frequency with V_DD= 1.6V.

Separation vs. Frequency.

10

1.E+05

100k

V_DD= 5.5V

1.E+04

10k

1.E+03

1k

V_DD= 1.6V

1

1.E+02

1.E+03

1.E+04

10k

1.E+05

100k

1.E+02

100

1.E+01

10

G = 1 V/V

G = 11 V/V

G = 101 V/V

1.E+00

0.1

1

100

1k

1.E+03

10k

100k

1.E+05

1M

1.E+06

100

1k

1.E+02

1.E+04

Frequency (Hz)

FIGURE 2-28:

Closed-Loop Output

FIGURE 2-30:

Maximum Output Voltage

Impedance vs. Frequency with V_DD= 5.5V.

Swing vs. Frequency.

DS20006204A-page 12

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.6V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 100 kΩ to V_Land C_L= 20 pF.

2.4

Input Noise and Distortion

1000

100

10

1000

100

10

G_DM= 1 V/V

V_DDtone = 50 mV_PK, f = 100 Hz

e_ni

100

10

1

IMD tone at DC

100 Hz tone

V_DD= 5.5V

V_DD= 1.6V

V_DD= 5.5V

_DD= 1.6V

V

E_ni(0 Hz to f)

1

100k

1

10

100

1k

10k

1

10

100

1k

10k

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

Frequency (Hz)

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

Frequency (Hz)

FIGURE 2-31:

Input Noise Voltage Density

FIGURE 2-34:

Intermodulation Distortion

and Integrated Input Noise Voltage vs.

Frequency.

vs. Frequency with V_DDDisturbance

(see Figure 1-6).

160

140

V_DD= 1.6V

f < 500 Hz

V_DD= 1.6V

120

100

V_DD= 5.5V

80

60

40

20

0

NPBW = 10 Hz

NPBW = 1 Hz

0

10 20 30 40 50 60 70 80 90 100

Time (s)

Common Mode Input Voltage (V)

FIGURE 2-32:

Input Noise Voltage Density

FIGURE 2-35:

Input Noise vs. Time with

vs. Input Common-Mode Voltage.

1 Hz and 10 Hz Filters and V_DD=1.6V.

1000

3.0

G_DM= 1 V/V

V_CMtone = 50 mV_PK, f = 100 Hz

V_DD= 5.5V

2.5

2.0

1.5

1.0

0.5

100

10

1

residual 100 Hz tone

IMD tone at DC

V_DD= 1.6V

V_DD= 5.5V

0.0

NPBW = 10 Hz

-0.5

-1.0

-1.5

NPBW = 1 Hz

-2.0

1

10

100

1k

10k

100k

0

10 20 30 40 50 60 70 80 90 100

Time (s)

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

Frequency (Hz)

FIGURE 2-33:

Intermodulation Distortion

vs. Frequency with V_CMDisturbance (see

Figure 1-6).

FIGURE 2-36:

1 Hz and 10 Hz Filters and V_DD=5.5V.

Input Noise vs. Time with

 2019 Microchip Technology Inc.

DS20006204A-page 13

MCP6V16/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.6V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 100 kΩ to V_Land C_L= 20 pF.

2.5

Time Response

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

8

7

6

V_DD= 5.5V

G = 1

5

V_DD

6

4

5

3

POR Trip Point

4

2

3

1

2

0

1

-1

-2

-3

-4

0

V_OS

-1

-2

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Time (ms)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Time (ms)

FIGURE 2-40:

Step Response.

Noninverting Large Signal

FIGURE 2-37:

Time at Power Up.

Input Offset Voltage vs.

80

70

60

50

40

30

20

10

0

7

6

V_DD= 5.5V

G = 1

V_DD= 5.5V

G = -1

V_IN

5

V_OUT

4

3

2

1

0

-1

0

20 40 60 80 100 120 140 160 180 200

Time (µs)

0

2

4

6

8

10 12 14 16 18 20

Time (ms)

FIGURE 2-38:

The MCP6V16/6U/7/9

FIGURE 2-41:

Inverting Small Signal Step

Family Shows No Input Phase Reversal with

Overdrive.

Response.

80

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_DD= 5.5V

G = -1

G = 1

70

60

50

40

30

20

10

0

20 40 60 80 100 120 140 160 180 200

Time (µs)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Time (ms)

FIGURE 2-39:

Step Response.

Noninverting Small Signal

FIGURE 2-42:

Response.

Inverting Large Signal Step

DS20006204A-page 14

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.6V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 100 kΩ to V_Land C_L= 20 pF.

0.08

V_DD= 5.5V

0.07

Falling Edge

0.06

0.05

0.04

0.03

0.02

V_DD= 1.6V

0.01

Rising Edge

0.00

-50

-25

0

25

50

75

100

125

Ambient Temperature (°C)

FIGURE 2-43:

Slew Rate vs. Ambient

Temperature.

7

6

5

7

6

5

4

3

2

1

0

-1

V_OUT

G V_IN

4

3

2

V_DD= 5.5V

G = -10 V/V

0.5V Overdrive

1

G V_IN

V_OUT

0

-1

0

1

2

3

4

5

6

Time (500 µs/div)

FIGURE 2-44:

Output Overdrive Recovery

vs. Time with G = -10 V/V.

1.E- 2

10m

0.5V Input Overdrive

V_DD= 1.6V

t_ODR, low

1.E-03

1m

V

_DD

= 5.5V

t_ODR, high

1.E-04

100µ

1

10

100

1000

Inverting Gain Magnitude (V/V)

FIGURE 2-45:

Output Overdrive Recovery

Time vs. Inverting Gain.

 2019 Microchip Technology Inc.

DS20006204A-page 15

MCP6V16/6U/7/9

NOTES:

DS20006204A-page 16

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

3.0

PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP6V16 MCP6V16U

MCP6V17

MCP6V19

Symbol

Description

SOT-23,

SOT-23

2×3 TDFN MSOP

TSSOP

SC-70

1

4

1

2

1

2

1

2

V_OUT, V_OUTAOutput (Op Amp A)

4

3

V_IN–, V_INA

–

+

Inverting Input (Op Amp A)

Noninverting Input (Op Amp A)

Positive Power Supply

3

1

3

V_IN+, V_INA

V_DD

5

8

4

—

2

—

2

5

V_INB

+

–

Noninverting Input (Op Amp B)

Inverting Input (Op Amp B)

Output (Op Amp B)

6

V_INB

7

V_OUTB

V_OUTC

—

4

—

4

8

Output (Op Amp C)

9

V_INC

–

+

Inverting Input (Op Amp C)

Noninverting Input (Op Amp C)

Negative Power Supply

Noninverting Input (Op Amp D)

Inverting Input (Op Amp D)

Output (Op Amp D)

10

11

12

13

14

—

V_INC

V_SS

—

9

—

V_IND

+

V_IND

–

V_OUTD

EP

Exposed Thermal Pad (EP); must be

connected to V_SS

3.1

Analog Outputs

3.4

Exposed Thermal Pad (EP)

The analog output pins (V_OUT) are low-impedance

voltage sources.

There is an internal connection between the exposed

thermal pad (EP) and the V_SSpin; they must be

connected to the same potential on the printed circuit

board (PCB).

3.2

Analog Inputs

This pad can be connected to a PCB ground plane to

provide a larger heat sink. This improves the package

thermal resistance (θ_JA).

The noninverting and inverting inputs (V_IN+, V_IN–, …)

are high-impedance CMOS inputs with low bias

currents.

3.3

Power Supply Pins

The positive power supply (V_DD) is 1.6V to 5.5V higher

than the negative power supply (V_SS). For normal

operation, the other pins are between V_SSand V_DD

.

Typically, these parts are used in a single (positive)

supply configuration. In this case, V_SSis connected to

ground and V_DDis connected to the supply. V_DDwill

need bypass capacitors.

 2019 Microchip Technology Inc.

DS20006204A-page 17

MCP6V16/6U/7/9

NOTES:

DS20006204A-page 18

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

The Low-Pass Filter reduces high-frequency content,

including harmonics of the Chopping Clock.

4.0

APPLICATIONS

The MCP6V16/6U/7/9 family of zero-drift op amps is

manufactured using Microchip’s state of the art CMOS

process. It is designed for applications with

requirements for small packages and low power. Its low

supply voltage and low quiescent current make the

MCP6V16/6U/7/9 devices ideal for battery-powered

applications.

The Output Buffer drives external loads at the V_OUTpin

(V_REFis an internal reference voltage).

The Oscillator runs at f_OSC1= 50 kHz. Its output is

divided by two, to produce the Chopping Clock rate of

f_CHOP= 25 kHz.

The internal POR part starts the part in a known good

state, protecting against power supply brown-outs.

4.1

Overview of Zero-Drift Operation

The Digital Control block controls switching and POR

events.

Figure 4-1 shows

a

simplified diagram of the

MCP6V16/6U/7/9 zero-drift op amps. This diagram will

be used to explain how slow voltage errors are reduced

in this architecture (much better V_OS, ∆V_OS/∆T_A(TC₁),

CMRR, PSRR, A_OLand 1/f noise).

4.1.2

CHOPPING ACTION

Figure 4-2 shows the amplifier connections for the first

phase of the Chopping Clock and Figure 4-3 shows

them for the second phase. Its slow voltage errors

alternate in polarity, making the average error small.

V_REF

Output

V_OUT

V_IN+

Buffer

V_IN+

Main

V_IN–

Amp.

NC

Main

V_IN–

Amp.

NC

Low-Pass

Filter

Low-Pass

Filter

Aux.

Amp.

Chopper

Input

Switches

Chopper

Output

Switches

Aux.

Amp.

FIGURE 4-2:

First Chopping Clock Phase;

Equivalent Amplifier Diagram.

V_IN+

Oscillator

Digital Control

POR

Main

V_IN–

FIGURE 4-1:

Amp Functional Diagram.

Simplified Zero-Drift Op

Amp.

NC

4.1.1

BUILDING BLOCKS

Low-Pass

Filter

The Main Amplifier is designed for high gain and

bandwidth, with a differential topology. Its main input

pair (+ and - pins at the top left) is used for the higher

frequency portion of the input signal. Its auxiliary input

pair (+ and - pins at the bottom left) is used for the low-

frequency portion of the input signal and corrects the

op amp’s input offset voltage. Both inputs are added

together internally.

Aux.

Amp.

The Auxiliary Amplifier, Chopper Input Switches and

Chopper Output Switches provide a high DC gain to the

input signal. DC errors are modulated to higher

frequencies, while white noise is modulated to low

frequency.

FIGURE 4-3:

Phase; Equivalent Amplifier Diagram.

Second Chopping Clock

 2019 Microchip Technology Inc.

DS20006204A-page 19

MCP6V16/6U/7/9

4.1.3

INTERMODULATION DISTORTION

(IMD)

Bond

Pad

V_DD

V_IN+

V_SS

These op amps will show intermodulation distortion

(IMD) products when an AC signal is present.

The signal and clock can be decomposed into sine

wave tones (Fourier series components). These tones

interact with the zero-drift circuitry’s nonlinear response

to produce IMD tones at sum and difference frequen-

cies. Each of the square wave clock’s harmonics has a

series of IMD tones centered on it. See Figure 2-33 and

Figure 2-34.

Bond

Pad

Bond

Pad

Input

Stage

V_IN–

Bond

Pad

4.2

Other Functional Blocks

FIGURE 4-4:

Simplified Analog Input ESD

Structures.

4.2.1

RAIL-TO-RAIL INPUTS

The input ESD diodes clamp the inputs when they try

to go more than one diode drop below V_SS. They also

clamp any voltages well above V_DD; their breakdown

voltage is high enough to allow normal operation, but

not low enough to protect against slow overvoltage

(beyond V_DD) events. Very fast ESD events (that meet

the spec) are limited so that damage does not occur.

The input stage of the MCP6V16/6U/7/9 op amps uses

two differential CMOS input stages in parallel. One

operates at low Common-mode input voltage (V_CM

,

which is approximately equal to V_IN+ and V_IN– in

normal operation) and the other at high V_CM. With this

topology, the input operates with V_CMup to V_DD+ 0.2V,

and down to V_SS– 0.15V, at +25°C (see Figure 2-15).

The input offset voltage (V_OS) is measured at

V_CM= V_SS– 0.15V and V_DD+ 0.2V to ensure proper

operation.

In some applications, it may be necessary to prevent

excessive voltages from reaching the op amp inputs;

Figure 4-5 shows one approach to protecting these

inputs. D₁and D₂may be small signal silicon diodes,

Schottky diodes for lower clamping voltages or diode

connected FETs for low leakage.

The transition between the input stages occurs when

V_CM≈ V_DD– 0.9V (see Figure 2-7 and Figure 2-8). For

the best distortion and gain linearity, with noninverting

gains, avoid this region of operation.

V_DD

4.2.1.1

Phase Reversal

The input devices are designed to not exhibit phase

inversion when the input pins exceed the supply

voltages. Figure 2-38 shows an input voltage

exceeding both supplies with no phase inversion.

U₁

D₁

MCP6V1X

V₁

D₂

V_OUT

V₂

4.2.1.2

Input Voltage Limits

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the voltages at

the input pins (see Section 1.1 “Absolute Maximum

Ratings †”). This requirement is independent of the

current limits discussed later on.

FIGURE 4-5:

Against High Voltages.

Protecting the Analog Inputs

The ESD protection on the inputs can be depicted as

shown in Figure 4-4. This structure was chosen to

protect the input transistors against many (but not all)

overvoltage conditions, and to minimize input bias

current (I_B).

DS20006204A-page 20

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

4.2.1.3

Input Current Limits

4.3

Application Tips

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

into the input pins (see Section 1.1 “Absolute

Maximum Ratings †”). This requirement is

independent of the voltage limits discussed previously.

4.3.1

INPUT OFFSET VOLTAGE OVER

TEMPERATURE

Table 1-1 gives both the linear and quadratic

temperature coefficients (TC₁and TC₂) of input offset

voltage. The input offset voltage, at any temperature in

the specified range, can be calculated as follows:

Figure 4-6 shows one approach to protecting these

inputs. The resistors R₁and R₂limit the possible

current in or out of the input pins (and into D₁and D₂).

EQUATION 4-1:

The diode currents will dump onto V_DD

.

V_OST_A = V_OS+ TC₁T + TC₂T²

V_DD

Where:

∆T

V_OS(T_A)

V_OS

=

T_A– 25°C

U₁

D₁

R₁

R₂

input offset voltage at T_A

input offset voltage at +25°C

linear temperature coefficient

quadratic temperature coefficient

MCP6V1X

V₁

V₂

D₂

V_OUT

TC₁

TC₂

4.3.2

Figures 2-9 to 2-11 are histograms of the reciprocals

(in units of µV/V) of CMRR, PSRR and A_OL

respectively. They represent the change in input offset

voltage (V_OS) with a change in Common-mode input

voltage (V_CM), power supply voltage (V_DD) and output

voltage (V_OUT).

DC GAIN PLOTS

V_SS– min(V₁, V₂)

2 mA

max(V₁, V₂) – V_DD

2 mA

min(R₁, R₂) >

,

FIGURE 4-6:

Against High Currents.

Protecting the Analog Inputs

The 1/A_OLhistogram is centered near 0 µV/V because

the measurements are dominated by the op amp’s

input noise. The negative values shown represent

noise and tester limitations, not unstable behavior.

Production tests make multiple V_OSmeasurements,

which validates an op amp's stability; an unstable part

would show greater V_OSvariability, or the output would

stick at one of the supply rails.

It is also possible to connect the diodes to the left of

resistors R₁and R₂. In this case, the currents through

the diodes D₁and D₂need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (V_IN+ and

V_IN–) should be very small.

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the Common-

mode voltage (V_CM) is below ground (V_SS); see

Figure 2-14.

4.3.3

OFFSET AT POWER UP

When these parts power up, the input offset (V_OS

)

starts at its uncorrected value (usually less than

±5 mV). Circuits with high DC gain can cause the

output to reach one of the two rails. In this case, the

time to a valid output is delayed by an output overdrive

time (like t_ODR), in addition to the start-up time (like

t_STR).

4.2.2

RAIL-TO-RAIL OUTPUT

The output voltage range of the MCP6V16/6U/7/9

zero-drift op amps is V_DD– 20 mV (minimum) and

V_SS+ 20 mV (maximum) when R_L= 10 kΩ is

connected to V_DD/2 and V_DD= 5.5V. Refer to

Figure 2-16 and Figure 2-17 for more information.

It can be simple to avoid this extra start-up time.

Reducing the gain is one method. Adding a capacitor

across the feedback resistor (R_F) is another method.

This op amp is designed to drive light loads; use

another amplifier to buffer the output from heavy loads.

 2019 Microchip Technology Inc.

DS20006204A-page 21

MCP6V16/6U/7/9

G_Nis the circuit’s noise gain. For noninverting gains,

G_Nand the Signal Gain are equal. For inverting gains,

G_Nis 1+|Signal Gain| (e.g., -1 V/V gives G_N= +2 V/V).

4.3.4

SOURCE RESISTANCES

The input bias currents have two significant

components; switching glitches that dominate at room

temperature and below, and input ESD diode leakage

currents that dominate at +85°C and above.

1.E+ 5

100k

R_L||(R_F+ R_G) 100 k

Make the resistances seen by the inputs small and

equal. This minimizes the output offset caused by the

input bias currents.

1.E+ 4

10k

The inputs should see a resistance on the order of 10 Ω

to 1 kΩ at high frequencies (i.e., above 1 MHz). This

helps minimize the impact of switching glitches, which

are very fast, on overall performance. In some cases, it

may be necessary to add resistors in series with the

inputs to achieve this improvement in performance.

1.E+03

1k

G_N= 1

G_N= 10

G_N= 100

1.E+ 2

100

10p

100p

1n

10n

100n

1µ

1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06

Capacitive Load (F)

Small input resistances may be needed for high gains.

Without them, parasitic capacitances might cause

positive feedback and instability.

FIGURE 4-8:

for Capacitive Loads.

Recommended R_ISOValues

4.3.5

SOURCE CAPACITANCE

After selecting R_ISOfor your circuit, double check the

resulting frequency response peaking and step

response overshoot. Modify R_ISO's value until the

response is reasonable. Bench evaluation is helpful.

The capacitances seen by the two inputs should be

small. Large input capacitances and source

resistances, together with high gain, can lead to

positive feedback and instability.

4.3.7

STABILIZING OUTPUT LOADS

4.3.6

CAPACITIVE LOADS

This family of zero-drift op amps has an output

impedance (Figure 2-27 and Figure 2-28) that has a

double zero when the gain is low. This can cause a

large phase shift in feedback networks that have low-

impedance near the part’s bandwidth. This large phase

shift can cause stability problems.

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. These zero-drift op amps have a different

output impedance than most op amps, due to their

unique topology.

Figure 4-9 shows that the load on the output is

(R_L+ R_ISO)||(R_F+ R_G), where R_ISOis before the load

(like Figure 4-7). This load needs to be large enough to

maintain stability; it should be at least 10 kΩ.

When driving a capacitive load with these op amps, a

series resistor at the output (R_ISOin Figure 4-7)

improves the feedback loop’s phase margin (stability)

by making the output load resistive at higher

frequencies. The bandwidth will be generally lower

than the bandwidth with no capacitive load.

R_G

R_F

V_OUT

R_L

C_L

U₁

MCP6V1X

R_ISO

V_OUT

FIGURE 4-9:

Output Load.

C_L

U₁

MCP6V1X

FIGURE 4-7:

Output Resistor, R_ISO,

Stabilizes Capacitive Loads.

Figure 4-8 gives recommended R_ISOvalues for

different capacitive loads and gains. The x-axis is the

load capacitance (C_L). The y-axis is the resistance

(R_ISO).

DS20006204A-page 22

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

4.3.8

GAIN PEAKING

4.3.9

REDUCING UNDESIRED NOISE

AND SIGNALS

Figure 4-10 shows an op amp circuit that represents

noninverting amplifiers (V_Mis a DC voltage and V_Pis

the input) or inverting amplifiers (V_Pis a DC voltage

and V_Mis the input). The capacitances C_Nand C_G

represent the total capacitance at the input pins; they

include the op amp’s Common-mode input capacitance

(C_CM), board parasitic capacitance and any capacitor

placed in parallel. The capacitance C_FPrepresents the

parasitic capacitance coupling the output and

noninverting input pins.

Reduce undesired noise and signals with:

• Low bandwidth signal filters:

- Minimizes random analog noise

- Reduces interfering signals

• Good PCB layout techniques:

- Minimizes crosstalk

- Minimizes parasitic capacitances and

inductances that interact with fast switching

edges

• Good power supply design:

- Isolation from other parts

C_N

C_FP

R_N

- Filtering of interference on supply line(s)

V_P

4.3.10

SUPPLY BYPASSING AND

FILTERING

U₁

MCP6V1X

With this family of operational amplifiers, the power

supply pin (V_DDfor single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

of the pin for good high-frequency performance.

V_M

V_OUT

R_G

R_F

C_G

These parts also need a bulk capacitor (i.e., 1 µF or

larger) within 100 mm to provide large, slow currents.

This bulk capacitor can be shared with other low noise,

analog parts.

FIGURE 4-10:

Capacitance.

Amplifier with Parasitic

C_Gacts in parallel with R_G(except for a gain of +1 V/V),

which causes an increase in gain at high frequencies.

C_Galso reduces the phase margin of the feedback

loop, which becomes less stable. This effect can be

reduced by either reducing C_Gor R_F||R_G.

In some cases, high-frequency power supply noise

(e.g., switched mode power supplies) may cause

undue intermodulation distortion, with a DC offset shift;

this noise needs to be filtered. Adding a resistor into the

supply connection can be helpful.

C_Nand R_Nform a low-pass filter that affects the signal

4.3.11

PCB DESIGN FOR DC PRECISION

at V_P. This filter has a single real pole at 1/(2πR_NC_N).

The largest value of R_Fthat should be used depends

on noise gain (see G_Nin Section 4.3.6, Capacitive

Loads), C_Gand the open-loop gain’s phase shift. An

approximate limit for R_Fis:

In order to achieve DC precision on the order of ±1 µV,

many physical errors need to be minimized. The design

of the Printed Circuit Board (PCB), the wiring, and the

thermal environment have a strong impact on the

precision achieved. A poor PCB design can easily be

more than 100 times worse than the MCP6V16/6U/7/9

op amps’ minimum and maximum specifications.

EQUATION 4-2:

R_F 40 k  -------------  G²_N

12 pF

C_G

4.3.11.1

PCB Layout

Any time two dissimilar metals are joined together, a

temperature dependent voltage appears across the

junction (the Seebeck or thermojunction effect). This

effect is used in thermocouples to measure

temperature. The following are examples of

thermojunctions on a PCB:

Some applications may modify these values to reduce

either output loading or gain peaking (step response

overshoot).

At high gains, R_Nneeds to be small, in order to prevent

positive feedback and oscillations. Large C_Nvalues

can also help.

• Components (resistors, op amps, …) soldered to

a copper pad

• Wires mechanically attached to the PCB

• Jumpers

• Solder joints

• PCB vias

 2019 Microchip Technology Inc.

DS20006204A-page 23

MCP6V16/6U/7/9

Typical thermojunctions have temperature to voltage

conversion coefficients of 1 to 100 µV/°C (sometimes

higher).

4.4

Typical Applications

4.4.1

WHEATSTONE BRIDGE

Microchip’s AN1258 (“Op Amp Precision Design: PCB

Layout Techniques”) contains in-depth information on

PCB layout techniques that minimize thermojunction

effects. It also discusses other effects, such as

crosstalk, impedances, mechanical stresses and

humidity.

Many sensors are configured as Wheatstone bridges.

Strain gauges and pressure sensors are two common

examples. These signals can be small and the

Common-mode noise large. Amplifier designs with

high differential gain are desirable.

Figure 4-11 shows how to interface to a Wheatstone

bridge with a minimum of components. Because the

circuit is not symmetric, the ADC input is single ended,

and there is a minimum of filtering; the CMRR is good

enough for moderate Common-mode noise.

4.3.11.2

Crosstalk

DC crosstalk causes offsets that appear as a larger

input offset voltage. Common causes include:

• Common-mode noise (remote sensors)

• Ground loops (current return paths)

• Power supply coupling

0.01C

100R

V_DD

1 kΩ

V_DD

R

ADC

Interference from the mains (usually 50 Hz or 60 Hz),

and other AC sources, can also affect the DC

performance. Nonlinear distortion can convert these

signals to multiple tones, including a DC shift in voltage.

When the signal is sampled by an ADC, these AC

signals can also be aliased to DC, causing an apparent

shift in offset.

0.2R

U₁

MCP6V16

R

FIGURE 4-11:

Simple Design.

To reduce interference:

4.4.2 RTD SENSOR

- Keep traces and wires as short as possible

- Use shielding

The ratiometric circuit in Figure 4-12 conditions a two-

wire RTD (Resistance Temperature Detector), for

applications with a limited temperature range. U₁acts

as a difference amplifier, with a low frequency pole. The

sensor’s wiring resistance (R_W) is corrected in

firmware. Failure (open) of the RTD is detected by an

out-of-range voltage.

- Use ground plane (at least a star ground)

- Place the input signal source near to the DUT

- Use good PCB layout techniques

- Use a separate power supply filter (bypass

capacitors) for these zero-drift op amps

4.3.11.3

Miscellaneous Effects

V_DD

Keep the resistances seen by the input pins as small

and as near to equal as possible, to minimize bias-

current-related offsets.

R_T

34.8 kΩ

R_N

10.0 kΩ

10 nF

Make the (trace) capacitances seen by the input pins

small and equal. This is helpful in minimizing switching

glitch-induced offset voltages.

R_F

2.00 MΩ

R_W

U₁

R_RTD

100Ω

Bending a coax cable with a radius that is too small

causes a small voltage drop to appear on the center

conductor (the triboelectric effect). Make sure the

bending radius is large enough to keep the conductors

and insulation in full contact.

MCP6V16

1.00 kΩ

R_G

R_F

R_W

10.0 kΩ 2.00 MΩ

100 nF

V_DD

R_B

4.99 kΩ

10 nF

Mechanical stresses can make some capacitor types

(such as some ceramics) output small voltages. Use

more appropriate capacitor types in the signal path and

minimize mechanical stresses and vibration.

1.0 µF

ADC

Humidity can cause electrochemical potential voltages

to appear in a circuit. Proper PCB cleaning helps, as

does the use of encapsulants.

FIGURE 4-12:

RTD Sensor.

DS20006204A-page 24

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

4.4.3

OFFSET VOLTAGE CORRECTION

Figure 4-13 shows MCP6V16 (U₂) correcting the input

offset voltage of another op amp (U₁). R₂and C₂

integrate the offset error seen at U₁’s input; the

integration needs to be slow enough to be stable (with

the feedback provided by R₁and R₃). R₄and R₅

attenuate the integrator’s output; this shifts the

integrator pole down in frequency.

R₁

R₂

R₃

V_IN

V_OUT

R₄

R₅

C₂

U₁

MCP6XXX

V_DD/2

R₂

V_DD/2

U₂

MCP6V16

FIGURE 4-13:

Offset Correction.

4.4.4 PRECISION COMPARATOR

Use high gain before a comparator to improve the

latter’s performance. Do not use MCP6V16/6U/7/9 as

a comparator by itself; the V_OScorrection circuitry does

not operate properly without a feedback loop.

U₁

V_IN

MCP6V16

R₁

R₂

R₃

R₄

R₅

V_OUT

V_DD/2

U₂

MCP6541

FIGURE 4-14:

Precision Comparator.

 2019 Microchip Technology Inc.

DS20006204A-page 25

MCP6V16/6U/7/9

NOTES:

DS20006204A-page 26

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

5.4

Application Notes

5.0

DESIGN AIDS

The following Microchip Application Notes are

available on the Microchip web site at www.microchip.

com/sitesearch/Search/all and are recommended as

supplemental reference resources.

Microchip provides the basic design aids needed for

the MCP6V16/6U/7/9 family of op amps.

5.1

SPICE Macro Model

ADN003: “Select the Right Operational Amplifier for

your Filtering Circuits”, DS21821

The latest SPICE macro model for the

MCP6V16/6U/7/9 op amps is available on the

Microchip web site at www.microchip.com. This model

is intended to be an initial design tool that works well in

the op amp’s linear region of operation over the

temperature range. See the model file for information

on its capabilities.

AN722: “Operational Amplifier Topologies and DC

Specifications”, DS00722

AN723: “Operational Amplifier AC Specifications and

Applications”, DS00723

AN884: “Driving Capacitive Loads With Op Amps”,

Bench testing is a very important part of any design and

cannot be replaced with simulations. Also, simulation

results using this macro model need to be validated by

comparing them to the data sheet specifications and

characteristic curves.

DS00884

AN990: “Analog Sensor Conditioning Circuits – An

Overview”, DS00990

AN1177: “Op Amp Precision Design: DC Errors”,

DS01177

5.2

Microchip Advanced Part Selector

(MAPS)

AN1228: “Op Amp Precision Design: Random Noise”,

DS01228

AN1258: “Op Amp Precision Design: PCB Layout

Techniques”, DS01258

MAPS is a software tool that helps efficiently identify

Microchip devices that fit a particular design require-

ment. Available at no cost from the Microchip web site

at www.microchip.com/maps, MAPS is an overall

selection tool for Microchip’s product portfolio that

includes Analog, Memory, MCUs and DSCs. Using this

tool, a customer can define a filter to sort features for a

parametric search of devices and export side-by-side

technical comparison reports. Helpful links are also

provided for Data Sheets, Purchase and Sampling of

Microchip parts.

These Application Notes and others are listed in the

design guide:

“Signal Chain Design Guide”, DS21825

5.3

Analog Demonstration and

Evaluation Boards

Microchip offers

a

broad spectrum of Analog

Demonstration and Evaluation Boards that are

designed to help customers achieve faster time to

market. For a complete listing of these boards and their

corresponding user’s guides and technical information,

visit the Microchip web site at

www.microchip.com/treelinktool.

Some boards that are especially useful are:

• MCP6V01 Thermocouple Auto-Zeroed Reference

Design (P/N MCP6V01RD-TCPL)

• MCP6XXX Amplifier Evaluation Board 2 (P/N

DS51668)

• MCP6XXX Amplifier Evaluation Board 3 (P/N

DS51673)

• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board

(P/N SOIC8EV)

• 14-Pin SOIC/TSSOP/DIP Evaluation Board (P/N

SOIC14EV)

 2019 Microchip Technology Inc.

DS20006204A-page 27

MCP6V16/6U/7/9

NOTES:

DS20006204A-page 28

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

6.0

6.1

PACKAGING INFORMATION

Package Marking Information

5-Lead SC70 (MCP6V16U)

Example:

FR25

Device

MCP6V16UT-E/LTY

Code

FRNN

Note:

Applies to 5-Lead SC-70.

5-Lead SOT-23 (MCP6V16/6U)

Example:

RBDD

Device

Code

MCP6V16T-E/OT

RBDD

WWNNN

19256

MCP6V16UT-E/OT

RBDE

WWNNN

Note:

Applies to 5-Lead SOT-23.

8-Lead MSOP (3x3 mm) (MCP6V17)

Example

6V17E

919256

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC^®designator for Matte Tin (Sn)

e

3

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2019 Microchip Technology Inc.

DS20006204A-page 29

MCP6V16/6U/7/9

8-Lead TDFN (2x3x0.8 mm)(MCP6V17)

Example

Device

Code

MCP6V17-E/MNY

MCP6V17T-E/MNY

DM1

919

25

Note:

Applies to 8-Lead 2x3 TDFN.

14-Lead TSSOP (4.4 mm)(MCP6V19)

Example

XXXXXXXX

YYWW

6V19E/ST

1919

256

NNN

DS20006204A-page 30

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

5-Lead Plastic Small Outline Transistor (LT) [SC70]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

e

B

E

3

1

E1

2X

0.15 C

4

N

5X TIPS

0.30 C

NOTE 1

2X

0.15 C

5X b

0.10

C A B

TOP VIEW

c

A2

A

C

SEATING

PLANE

A1

L

SIDE VIEW

END VIEW

Microchip Technology Drawing C04-061D Sheet 1 of 2

 2019 Microchip Technology Inc.

DS20006204A-page 31

MCP6V16/6U/7/9

5-Lead Plastic Small Outline Transistor (LT) [SC70]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

5

0.65 BSC

Overall Height

Standoff

Molded Package Thickness

Overall Length

Exposed Pad Length

Overall Width

Exposed Pad Width

Terminal Width

A

A1

A2

D

D2

E

E1

b

L

c

0.80

0.00

0.80

-

1.10

0.10

1.00

-

2.00 BSC

2.60

2.10 BSC

1.25 BSC

-

2.50

2.70

0.15

0.10

0.08

0.40

0.46

0.26

Terminal Length

Lead Thickness

0.20

-

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

protrusions shall not exceed 0.15mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-061D Sheet 2 of 2

DS20006204A-page 32

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

5-Lead Plastic Small Outline Transistor (LT) [SC70]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

Gx

SILK SCREEN

3

4

2

1

5

C

G

Y

X

RECOMMENDED LAND PATTERN

Units

MILLIMETERS

Dimension Limits

MIN

NOM

0.65 BSC

2.20

MAX

Contact Pitch

E

C

Contact Pad Spacing

Contact Pad Width

Contact Pad Length

Distance Between Pads

X

Y

G

Gx

0.45

0.95

1.25

0.20

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2061B

 2019 Microchip Technology Inc.

DS20006204A-page 33

MCP6V16/6U/7/9

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

0.20 C 2X

D

e1

A

D

N

E/2

E1/2

E1

E

(DATUM D)

(DATUM A-B)

0.15 C D

2X

NOTE 1

1

2

e

B

NX b

0.20

C A-B D

TOP VIEW

A

A2

A1

A

0.20 C

SEATING PLANE

A

SEE SHEET 2

C

SIDE VIEW

Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2

DS20006204A-page 34

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

c

T

L

L1

VIEW A-A

SHEET 1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

5

0.95 BSC

Outside lead pitch

Overall Height

Molded Package Thickness

Standoff

Overall Width

Molded Package Width

Overall Length

Foot Length

e1

A

A2

A1

E

E1

D

L

1.90 BSC

0.90

0.89

-

1.45

1.30

0.15

2.80 BSC

1.60 BSC

2.90 BSC

0.30

-

0.60

Footprint

Foot Angle

Lead Thickness

Lead Width

L1

0.60 REF

I

0°

0.08

0.20

-

10°

0.26

0.51

c

b

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

protrusions shall not exceed 0.25mm per side.

2. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2

 2019 Microchip Technology Inc.

DS20006204A-page 35

MCP6V16/6U/7/9

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

X

SILK SCREEN

5

Y

Z

C

G

1

2

E

GX

RECOMMENDED LAND PATTERN

Units

MILLIMETERS

Dimension Limits

MIN

NOM

0.95 BSC

2.80

MAX

Contact Pitch

E

C

Contact Pad Spacing

Contact Pad Width (X5)

Contact Pad Length (X5)

Distance Between Pads

Overall Width

X

Y

G

GX

Z

0.60

1.10

1.70

0.35

3.90

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2091B [OT]

DS20006204A-page 36

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2019 Microchip Technology Inc.

DS20006204A-page 37

MCP6V16/6U/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20006204A-page 38

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2019 Microchip Technology Inc.

DS20006204A-page 39

MCP6V16/6U/7/9

8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]

With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

N

(DATUM A)

(DATUM B)

NOTE 1

2X

0.15 C

2X

1

2

0.15 C

TOP VIEW

0.10 C

(A3)

C

A

SEATING

PLANE

8X

A1

L

0.08 C

C A B

SIDE VIEW

0.10

D2

1

2

0.10

C A B

NOTE 1

E2

K

N

8X b

0.10

0.05

C A B

C

e

BOTTOM VIEW

Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 1 of 2

DS20006204A-page 40

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]

With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Pins

Pitch

Overall Height

Standoff

Contact Thickness

Overall Length

Overall Width

Exposed Pad Length

Exposed Pad Width

Contact Width

Contact Length

N

8

e

0.50 BSC

0.75

A

A1

A3

D

0.70

0.00

0.80

0.05

0.02

0.20 REF

2.00 BSC

3.00 BSC

1.40

E

D2

E2

b

L

K

1.35

1.25

0.20

0.25

0.20

1.45

1.35

0.30

0.45

-

1.30

0.25

0.30

-

Contact-to-Exposed Pad

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package may have one or more exposed tie bars at ends.

3. Package is saw singulated

4. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 2 of 2

 2019 Microchip Technology Inc.

DS20006204A-page 41

MCP6V16/6U/7/9

8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]

With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

X2

EV

8

ØV

C

Y2

EV

Y1

1

2

SILK SCREEN

X1

E

RECOMMENDED LAND PATTERN

Units

Dimension Limits

E

MILLIMETERS

NOM

0.50 BSC

MIN

MAX

Contact Pitch

Optional Center Pad Width

Optional Center Pad Length

Contact Pad Spacing

X2

Y2

C

1.60

1.50

2.90

Contact Pad Width (X8)

Contact Pad Length (X8)

Thermal Via Diameter

Thermal Via Pitch

X1

Y1

V

0.25

0.85

0.30

1.00

EV

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during

reflow process

Microchip Technology Drawing No. C04-129-MNY Rev. B

DS20006204A-page 42

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2019 Microchip Technology Inc.

DS20006204A-page 43

MCP6V16/6U/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20006204A-page 44

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2019 Microchip Technology Inc.

DS20006204A-page 45

MCP6V16/6U/7/9

NOTES:

DS20006204A-page 46

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

APPENDIX A: REVISION HISTORY

Revision A (July 2019)

• Initial release of this document.

 2019 Microchip Technology Inc.

DS20006204A-page 47

MCP6V16/6U/7/9

NOTES:

DS20006204A-page 48

 2019 Microchip Technology Inc.

MCP6V16/6U/7/9

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

(1)

Examples:

[X]

PART NO.

–X

/XX

a)

MCP6V16T-E/OT:

Tape and Reel,

Extended temperature,

5LD SOT-23 package

Device Tape and Reel

Temperature

Range

Package

a)

b)

MCP6V16UT-E/LTY: Tape and Reel,

Extended temperature,

5LD SC70 package

Device:

MCP6V16T: Single Op Amp (Tape and Reel) (SOT-23)

MCP6V16UT: Single Op Amp (Tape and Reel)

(SC-70, SOT-23)

MCP6V16UT-E/OT: Tape and Reel,

Extended temperature,

5LD SOT-23 package

MCP6V17:

Dual Op Amp (MSOP, 2x3 TDFN)

MCP6V17T: Dual Op Amp (Tape and Reel) (MSOP,

2x3 TDFN)

MCP6V19:

a)

b)

MCP6V17-E/MS:

MCP6V17T-E/MS:

Extended temperature,

8LD MSOP package

Quad Op Amp (TSSOP)

MCP6V19T: Quad Op Amp (Tape and Reel) (TSSOP)

Tape and Reel,

Extended temperature,

8LD MSOP package

Temperature Range:

Package:

E

= -40°C to +125°C (Extended)

c)

MCP6V17T-E/MNY: Tape and Reel,

Extended temperature,

LTY*

OT

=

Plastic Small Outline Transistor, 5-lead

8LD 2x3 TDFN package

= Plastic Small Outline Transistor, 5-lead

a)

b)

MCP6V19-E/ST:

MCP6V19T-E/ST:

Extended temperature,

14LD TSSOP package

MNY* = Plastic Dual Flat, No-Lead - 2×3×0.8 mm Body,

8-lead

MS

ST

= Plastic Micro Small Outline, 8-lead

= Plastic Thin Shrink Small Outline - 4.4 mm

Body, 14-lead

Tape and Reel,

Extended temperature,

14LD TSSOP package

* Y = Nickel palladium gold manufacturing designator. Only

available on the TDFN and SC70 packages.

Note 1:

Tape and Reel identifier only appears in the

catalog part number description. This

identifier is used for ordering purposes and

is not printed on the device package. Check

with your Microchip Sales Office for package

availability with the Tape and Reel option.

 2019 Microchip Technology Inc.

DS20006204A-page 49

MCP6V16/6U/7/9

NOTES:

DS20006204A-page 50

 2019 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, Adaptec,

AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,

chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,

flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,

LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,

Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,

PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,

Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,

SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,

TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA

are registered trademarks of Microchip Technology Incorporated in

the U.S.A. and other countries.

APT, ClockWorks, The Embedded Control Solutions Company,

EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,

IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision

Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,

SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,

TimePictra, TimeProvider, Vite, WinPath, and ZL are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,

CryptoAuthentication, CryptoAutomotive, CryptoCompanion,

CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average

Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,

KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,

MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple

Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,

SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,

USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and

ZENA are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage

Technology, and Symmcom are registered trademarks of Microchip

Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany

II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in

other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-4575-3

For information regarding Microchip’s Quality Management Systems,

please visit www.microchip.com/quality.

 2019 Microchip Technology Inc.

DS20006204A-page 51

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Australia - Sydney

Tel: 61-2-9868-6733

India - Bangalore

Tel: 91-80-3090-4444

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

China - Beijing

Tel: 86-10-8569-7000

India - New Delhi

Tel: 91-11-4160-8631

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

China - Chengdu

Tel: 86-28-8665-5511

India - Pune

Tel: 91-20-4121-0141

Finland - Espoo

Tel: 358-9-4520-820

China - Chongqing

Tel: 86-23-8980-9588

Japan - Osaka

Tel: 81-6-6152-7160

Web Address:

www.microchip.com

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

China - Dongguan

Tel: 86-769-8702-9880

Japan - Tokyo

Tel: 81-3-6880- 3770

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Guangzhou

Tel: 86-20-8755-8029

Korea - Daegu

Tel: 82-53-744-4301

Germany - Garching

Tel: 49-8931-9700

China - Hangzhou

Tel: 86-571-8792-8115

Korea - Seoul

Tel: 82-2-554-7200

Germany - Haan

Tel: 49-2129-3766400

Austin, TX

Tel: 512-257-3370

China - Hong Kong SAR

Tel: 852-2943-5100

Malaysia - Kuala Lumpur

Tel: 60-3-7651-7906

Germany - Heilbronn

Tel: 49-7131-72400

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

China - Nanjing

Tel: 86-25-8473-2460

Malaysia - Penang

Tel: 60-4-227-8870

Germany - Karlsruhe

Tel: 49-721-625370

China - Qingdao

Philippines - Manila

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Tel: 86-532-8502-7355

Tel: 63-2-634-9065

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

China - Shanghai

Tel: 86-21-3326-8000

Singapore

Tel: 65-6334-8870

Germany - Rosenheim

Tel: 49-8031-354-560

China - Shenyang

Tel: 86-24-2334-2829

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Israel - Ra’anana

Tel: 972-9-744-7705

China - Shenzhen

Tel: 86-755-8864-2200

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Suzhou

Tel: 86-186-6233-1526

Taiwan - Taipei

Tel: 886-2-2508-8600

Detroit

Novi, MI

Tel: 248-848-4000

China - Wuhan

Tel: 86-27-5980-5300

Thailand - Bangkok

Tel: 66-2-694-1351

Italy - Padova

Tel: 39-049-7625286

Houston, TX

Tel: 281-894-5983

China - Xian

Tel: 86-29-8833-7252

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

China - Xiamen

Tel: 86-592-2388138

Norway - Trondheim

Tel: 47-7288-4388

China - Zhuhai

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Raleigh, NC

Tel: 919-844-7510

Sweden - Gothenberg

Tel: 46-31-704-60-40

New York, NY

Tel: 631-435-6000

Sweden - Stockholm

Tel: 46-8-5090-4654

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

DS20006204A-page 52

 2019 Microchip Technology Inc.

05/14/19


型号：	MCP6V16UT-EOT
厂家：	MICROCHIP
描述：	7.5 Î¼A, 80 kHz Zero-Drift Op Amps
文件：	总52页 (文件大小：3439K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP6V16UT-EOT [MICROCHIP]

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