MCP6G02T-E/OT [MICROCHIP]
110 レA Selectable Gain Amplifier; 110 μA可选增益放大器
| 型号： | MCP6G02T-E/OT |
| 厂家： | 
MICROCHIP |
| 描述： | 110 レA Selectable Gain Amplifier |
| 文件： | 总38页 (文件大小：1284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6G01/1R/1U/2/3/4
110 µA Selectable Gain Amplifier
Description
Features
• 3 Gain Selections:
The Microchip Technology Inc. MCP6G01/1R/1U/2/3/4
are analog Selectable Gain Amplifiers (SGA). They can
- +1, +10, +50 V/V
• One Gain Select Input per Amplifier
• Rail-to-Rail Input and Output
be configured for gains of +1 V/V, +10 V/V, and
+50 V/V through the Gain Select input pin(s). The Chip
Select pin on the MCP6G03 can put it into shutdown to
conserve power. These SGAs are optimized for single
supply applications requiring reasonable quiescent
current and speed.
• Low Gain Error: ±1% (max.)
• High Bandwidth: 250 kHz to 900 kHz (typ.)
• Low Supply Current: 110 µA (typ.)
• Single Supply: 1.8V to 5.5V
The single amplifiers MCP6G01, MCP6G01R,
MCP6G01U, and MCP6G03, are available in 5-pin
SOT-23 package and the dual amplifier MCP6G02, are
available in 8-pin SOIC and MSOP packages. The
quad amplifier MCP6G04 is available in 14-pin SOIC
and TSSOP packages. All parts are fully specified from
-40°C to +125°C.
• Extended Temperature Range: -40°C to +125°C
Typical Applications
• A/D Converter Driver
• Industrial Instrumentation
• Bar Code Readers
• Metering
Package Types
• Digital Cameras
MCP6G01
SOIC, MSOP
MCP6G03
SOIC, MSOP
Block Diagram
NC
NC
1
1
NC
CS
8
7
8
7
VDD
VDD
VDD
GSEL 2
GSEL 2
VIN
VIN
3
4
3
4
6 VOUT
5 NC
6 VOUT
5 NC
VIN
VSS
VSS
VOUT
Gain
Switches
MCP6G01
SOT-23-5
MCP6G02
SOIC, MSOP
RF
3
VOUTA
1
2
3
4
VDD
8
7
VOUT
VSS
VIN
1
5 VDD
VOUTB
GSELA
VINA
RG
Gain Select
Logic
2
3
GSEL
CS
6 GSELB
GSEL
4
VSS
5 MΩ
5
VINB
MCP6G01R
SOT-23-5
MCP6G04
SOIC, TSSOP
(MCP6G03
only)
VOUT
VDD
VIN
1
2
3
5 VSS
VOUTA
1
14 VOUTD
13 GSELD
12 VIND
VSS
GSELA 2
4 GSEL
VINA
VDD
VINB
3
4
5
Gain
(V/V)
GSEL Voltage (Typ.)
(V)
11 VSS
MCP6G01U
SOT-23-5
10 VINC
1
V
DD/2 (or open)
VIN
1
2
5 VDD GSELB 6
VOUTB
9 GSELC
8 VOUTC
10
50
0
7
VSS
VDD
GSEL 3
4 VOUT
Note:
VSS is assumed to be 0V
© 2006 Microchip Technology Inc.
DS22004B-page 1
MCP6G01/1R/1U/2/3/4
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
Current at Analog Input Pin (VIN)......................................±2 mA
Analog Input (VIN) †† ..................... VSS – 1.0V to VDD + 1.0V
All other Inputs and Outputs........... VSS – 0.3V to VDD + 0.3V
Output Short Circuit Current...................................continuous
Current at Output and Supply Pins................................ ±30 mA
Storage Temperature.....................................-65°C to +150°C
Junction Temperature..................................................+150°C
ESD protection on all pins (HBM; MM) ................ ≥ 4 kV; 200V
†† See Section 4.1.4 “Input Voltage and Current Limits”.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V,
IN = (0.3V)/G, RL = 100 kΩ to VDD/2, GSEL = VDD/2, and CS is tied low.
V
Parameters
Sym
Min
Typ
Max
Units
Conditions
Amplifier Inputs (VIN
)
Input Offset Voltage
VOS
–4.5
—
±1.0
±1.0
±2
+4.5
—
mV
mV
G = +1
G = +10, +50
Input Offset Voltage Drift
Power Supply Rejection Ratio
Input Bias Current
Input Bias Current at
Temperature
ΔVOS/ΔTA
—
—
µV/°C
dB
G = +1, TA = -40°C to +125°C
G = +1 (Note 1)
PSRR
IB
65
—
80
—
1
—
pA
IB
—
30
—
pA
TA = +85°C
IB
—
1000
1013||6
5000
—
pA
TA = +125°C
Input Impedance
ZIN
—
Ω||pF
Amplifier Gain
Nominal Gains
G
gE
—
–0.3
–1.0
—
1 to 50
—
—
+0.3
+1.0
—
V/V
%
+1, +10 or +50
DC Gain Error G = +1
G ≥ +10
VOUT ≈ 0.3V to VDD − 0.3V
VOUT ≈ 0.3V to VDD − 0.3V
gE
—
%
DC Gain Drift G = +1
G ≥ +10
ΔG/ΔTA
ΔG/ΔTA
±1
ppm/°C TA = -40°C to +125°C
ppm/°C TA = -40°C to +125°C
—
±4
—
Ladder Resistance (Note 1)
Ladder Resistance
RLAD
200
—
350
500
—
kΩ
Ladder Resistance
across Temperature
ΔRLAD/ΔTA
–1800
ppm/°C TA = -40°C to +125°C
Amplifier Output
DC Output Non-linearity G = +1
VONL
VONL
VONL
–0.2
–0.1
—
—
+0.2
+0.1
% of FSR VOUT = 0.3V to VDD – 0.3V,
V
DD = 1.8V
% of FSR VOUT = 0.3V to VDD – 0.3V,
DD = 5.5V
+0.05 % of FSR VOUT = 0.3V to VDD – 0.3V
V
DC Output Non-linearity, G = +10, +50
Maximum Output Voltage Swing
–0.05
—
—
VOH, VOL VSS+10
VOH, VOL VSS+10
VDD–10
VDD–10
—
mV
mV
mA
mA
G = +1; 0.3V output overdrive
G ≥ +10; 0.5V output overdrive
VDD = 1.8V
—
Short Circuit Current
ISC
ISC
—
—
±7
±20
—
VDD = 5.5V
Note 1: RLAD (RF+RG in Figure 4-1) connects VSS, VOUT, and the inverting input of the internal amplifier. Thus, VSS is coupled
to the internal amplifier and the PSRR spec describes PSRR+ only. It is recommended that the VSS pin be tied directly
to ground to avoid noise problems.
2:
IQ includes current in RLAD (typically 0.6 µA at VOUT = 0.3V), and excludes digital switching currents.
DS22004B-page 2
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V,
IN = (0.3V)/G, RL = 100 kΩ to VDD/2, GSEL = VDD/2, and CS is tied low.
V
Parameters
Sym
Min
Typ
Max
Units
Conditions
Power Supply
Supply Voltage
VDD
IQ
1.8
60
—
5.5
V
Quiescent Current per Amplifier
110
170
µA
IO = 0 (Note 2)
Note 1: RLAD (RF+RG in Figure 4-1) connects VSS, VOUT, and the inverting input of the internal amplifier. Thus, VSS is coupled
to the internal amplifier and the PSRR spec describes PSRR+ only. It is recommended that the VSS pin be tied directly
to ground to avoid noise problems.
2:
IQ includes current in RLAD (typically 0.6 µA at VOUT = 0.3V), and excludes digital switching currents.
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V,
V
IN = (0.3V)/G, RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Parameters
Sym
Min
Typ
Max Units
Conditions
Frequency Response
-3dB Bandwidth
BW
BW
—
—
—
—
—
—
900
350
250
0.3
0
—
—
—
—
—
—
kHz
kHz
kHz
dB
G = +1, VOUT < 100 mVP-P (Note 1)
G = +10, VOUT < 100 mVP-P (Note 1)
G = +50, VOUT < 100 mVP-P (Note 1)
G = +1; VOUT < 100 mVP-P
BW
Gain Peaking
GPK
GPK
GPK
dB
G = +10, VOUT < 100 mVP-P
0.7
dB
G = +50; VOUT < 100 mVP-P
Total Harmonic Distortion plus Noise
f = 1 kHz, G = +1 V/V
THD+N
THD+N
THD+N
—
—
—
0.0029
0.18
1.3
—
—
—
%
%
%
VOUT = 1.75V ± 1.4VPK, VDD = 5.0V,
BW = 80 kHz
f = 1 kHz, G = +10 V/V
f = 1 kHz, G = +50 V/V
VOUT = 2.5V ± 1.4VPK, VDD = 5.0V,
BW = 80 kHz
VOUT = 2.5V ± 1.4VPK, VDD = 5.0V,
BW = 80 kHz
Step Response
Slew Rate
SR
SR
SR
—
—
—
0.50
2.3
—
—
—
V/µs G = 1
V/µs G = 10
V/µs G = 50
4.5
Noise
Input Noise Voltage
Eni
Eni
eni
eni
eni
ini
—
—
—
—
—
—
9
—
—
—
—
—
—
µVP-P f = 0.1 Hz to 10 Hz (Note 2)
µVP-P f = 0.1 Hz to 30 kHz (Note 2)
nV/√Hz G = +1 V/V, f = 10 kHz (Note 2)
nV/√Hz G = +10 V/V, f = 10 kHz (Note 2)
nV/√Hz G = +50 V/V, f = 10 kHz (Note 2)
fA/√Hz f = 10 kHz
50
38
46
41
4
Input Noise Voltage Density
Input Noise Current Density
Note 1: See Table 4-1 for a list of typical numbers and Figure 2-31 for the frequency response versus gain.
2: ni and eni include ladder resistance thermal noise.
E
© 2006 Microchip Technology Inc.
DS22004B-page 3
MCP6G01/1R/1U/2/3/4
DIGITAL ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = 25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Low Specifications
CS Logic Threshold, Low
CS Input Current, Low
VCSL
ICSL
0
—
0.2VDD
—
V
CS = 0V
CS = 0V
—
30
pA
CS High Specifications
CS Logic Threshold, High
CS Input Current, High
VCSH
ICSH
0.8VDD
—
—
0.8
120
VDD
—
V
CS = VDD
µA
pA
CS = VDD = 5.5V
Quiescent Current per Amplifier,
IDD_SHDN
—
—
CS = VDD, MCP6G03
Shutdown Mode (IDD
)
Quiescent Current per Amplifier,
Shutdown Mode (ISS) (Note 3)
ISS_SHDN
ISS_SHDN
—
—
–2.4
–7.2
—
—
µA
µA
CS = VDD = 1.8V, MCP6G03
CS = VDD = 5.5V, MCP6G03
CS Dynamic Specifications
Input Capacitance
CCS
—
10
—
2
pF
Input Rise/Fall Times
tCSRF
tCSON
—
—
—
µs
µs
(Note 2)
CS Low to Amplifier Output High
Turn-on Time
40
—
G = +1 V/V, VDD = 1.8V, VIN = 0.9VDD
CS = 0.2VDD to VOUT = 0.8VDD
tCSON
—
—
7
—
µs
µs
G = +1 V/V, VDD = 5.5V, VIN = 0.9VDD
CS = 0.2VDD to VOUT = 0.8VDD
CS High to Amplifier Output High-Z
Turn-off Time
30
G = +1 V/V, VIN = VDD/2,
CS = 0.8VDD to VOUT = 0.1VDD/2
tCSOFF
—
Hysteresis
VCSHY
VCSHY
—
—
0.40
0.55
—
—
V
V
VDD = 1.8V
VDD = 5.5V
GSEL Specifications (Note 1)
GSEL Logic Threshold, Low
VGSL
VGSH
0.15VDD
0.65VDD
—
—
0.35VDD
0.85VDD
V
V
Gain changes between 1 and 10,
I
GSEL = 0
Gain changes between 1 and 50,
GSEL = 0
GSEL Logic Threshold, High
I
GSEL Input Current, Low
GSEL Input Current, High
IGSL
IGSH
–10
—
—
–1.5
+10
µA
µA
GSEL voltage = 0.3VDD
GSEL voltage = 0.7VDD
+1.5
GSEL Dynamic Specifications (Note 1)
Input Capacitance
CGSEL
—
8
—
pF
10
Input Rise/Fall Times
Hysteresis
tGSRF
VGSHY
VGSHY
tGSL1
—
—
—
—
45
95
10
µs
(Note 2)
—
—
mV
mV
VDD = 1.8V
VDD = 5.5V
GSEL Low to Valid Output Time,
G = +1 to +10 Select
VIN = 150 mV,
GSEL = 0.25VDD to VOUT = 1.37V
—
—
—
—
—
—
—
—
µs
µs
µs
µs
GSEL Middle to Valid Output Time,
G = +10 to +1 Select
tGSM10
tGSH1
12
9
VIN = 150 mV,
GSEL = 0.25VDD to VOUT = 0.28V
GSEL High to Valid Output Time,
G = +1 to +50 Select
VIN = 30 mV,
GSEL = 0.75VDD to VOUT = 1.35V
GSEL Middle to Valid Output Time,
G = +50 to +1 Select
tGSM50
8
VIN = 30 mV,
GSEL = 0.75VDD to VOUT = 0.18V
Note 1: GSEL is a tri-level input pin. The gain is 10 when its voltage is low, 1 when it is at mid-suppy, and 50 when it is high.
2: Not tested in production. Set by design and characterization.
3: ISS_SHDN includes the current through the CS pin, RL and RLAD, and excludes digital switching currents. The block dia-
gram on the from page shows these current paths (through VSS).
DS22004B-page 4
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
DIGITAL ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA = 25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
Conditions
GSEL High to Valid Output Time,
G = +10 to +50 Select
tGSH10
12
VIN = 30 mV,
GSEL = 0.75VDD to VOUT = 1.38V
—
—
µs
GSEL Low to Valid Output Time,
G = +50 to +10 Select
tGSL50
9
VIN = 30 mV,
GSEL = 0.25VDD to VOUT = 0.42V
—
—
µs
Note 1: GSEL is a tri-level input pin. The gain is 10 when its voltage is low, 1 when it is at mid-suppy, and 50 when it is high.
2: Not tested in production. Set by design and characterization.
3: ISS_SHDN includes the current through the CS pin, RL and RLAD, and excludes digital switching currents. The block dia-
gram on the from page shows these current paths (through VSS).
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.8V to +5.5V, and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
TA
TA
TA
–40
–40
–65
—
—
—
+125
+125
+150
°C
°C
°C
(Note 1)
θJA
θJA
θJA
θJA
θJA
—
—
—
—
—
256
163
206
120
100
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
Note 1: The MCP6G01/1R/1U/2/3/4 family of SGAs operates over this temperature range, but operation must not cause TJ to
exceed Maximum Junction Temperature (+150°C).
VIN
0.150V
0.030V
GSEL
tGSL1
tGSM10
tGSH1
tGSM50
tGSH10
tGSL50
1.50V
1.50V
1.50V
VOUT
0.30V
0.30V
0.15V
0.15V
0.03V
0.03V
FIGURE 1-1:
Gain Select Timing Diagram.
© 2006 Microchip Technology Inc.
DS22004B-page 5
MCP6G01/1R/1U/2/3/4
CS
tCSON
tCSOFF
0.9VDD
High-Z
VOUT
High-Z
110 µA (typ.)
IDD
120 pA (typ.)
–VDD / 7 MΩ (typ.)
ISS
–110 µA (typ.)
30 pA (typ.)
VDD / 7 MΩ (typ.)
ICS
FIGURE 1-2:
SGA Chip Select Timing Diagram.
DS22004B-page 6
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
The DC Gain Drift (ΔG/ΔTA) can be calculated from the
change in gE across temperature. This is shown in the
following equation:
1.1
DC Output Voltage Specs / Model
1.1.1
IDEAL MODEL
The ideal SGA output voltage (VOUT) is (see Figure 1-3):
EQUATION 1-4:
EQUATION 1-1:
ΔgE
in units of V/V/°C
in units of %/°C
,
---------
ΔG ⁄ ΔTA = G ⋅
,
ΔTA
VO_ID = GVIN
ΔgE
---------
ΔTA
Where:
ΔG ⁄ ΔTA = 100% ⋅
G is the nominal gain
VREF = VSS = 0V
VOUT (V)
This equation holds when there are no gain or offset
errors.
VDD
DD-0.3
V2
1.1.2
LINEAR MODEL
V
The SGA’s linear region of operation is modeled by the
line VO_LIN shown in Figure 1-3. VO_LIN includes offset
and gain errors, but does not include non-linear effects.
V1
VIN (V)
EQUATION 1-2:
0.3
0
0.3V
VO_LIN = G(1 + gE) VIN – ----------- + VOS + 0.3V
⎛
⎞
⎝
⎠
G
0.3
G
VDD-0.3 VDD
0
Where:
G
G
G is the nominal gain
gE is the gain error
FIGURE 1-3:
Output Voltage Model.
1.1.3 OUTPUT NON-LINEARITY
VOS is the input offset voltage
Figure 1-4 shows the Integral Non-Linearity (INL) of the
output voltage. INL is the output non-linearity error not
VREF = VSS = 0V
explained by VO_LIN
:
This line’s endpoints are 0.3V from the supply rails
(VO_ID = 0.3V and VDD – 0.3V). The gain error and
input offset voltage specifications (in the electrical
specifications) relate to Figure 1-3 as follows:
EQUATION 1-5:
INL = VOUT – VO_LIN
The output non-linearity specification (in the Electrical
Specifications, with units of % of FSR) is related to
Figure 1-4 by:
EQUATION 1-3:
V2 – V1
----------------------------
gE = 100% ⋅
V
DD – 0.6V
EQUATION 1-6:
V1
------------------------
VOS
Where:
=
,
G = +1
max(V3, V4)
G(1 + gE)
------------------------------
VONL = 100% ⋅
V
DD – 0.6V
Where:
V1 = VOUT – VO_ID
V2 = VOUT – VO_ID
,
,
VO_ID = 0.3V
VO_ID = VDD – 0.3V
V3 = max(–INL)
V4 = max(INL)
The input offset specification describes VOS at
G = +1 V/V.
Note that the Full Scale Range (FSR) is VDD – 0.6V
(0.3V to VDD – 0.3V).
© 2006 Microchip Technology Inc.
DS22004B-page 7
MCP6G01/1R/1U/2/3/4
INL (V)
V4
0
V3
VIN (V)
0.3
G
VDD-0.3 VDD
0
G
G
FIGURE 1-4:
Output Voltage INL.
DS22004B-page 8
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
18%
16%
14%
12%
10%
8%
30%
25%
20%
15%
10%
5%
2459 Samples
G = +1
2460 Samples
G = +1
T
A = -40 to +125°C
6%
4%
2%
0%
0%
DC Gain Error (%)
DC Gain Drift (ppm/°C)
FIGURE 2-1:
DC Gain Error, G = +1.
FIGURE 2-4:
DC Gain Drift, G = +1.
14%
14%
12%
10%
8%
4916 Samples
G ≥ +10
4912 Samples
G ≥ +10
TA = -40 to +125°C
12%
10%
8%
6%
6%
4%
4%
2%
2%
0%
0%
DC Gain Error (%)
DC Gain Drift (ppm/°C)
FIGURE 2-2:
DC Gain Error, G ≥ +10.
FIGURE 2-5:
DC Gain Drift, G ≥ +10.
20%
22%
1612 Samples
G = +1, +10, +50
TA = -40 to +125°C
2460 Samples
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
G = +50
G = +10
G = +1
Input Offset Voltage (mV)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-3:
Input Offset Voltage.
FIGURE 2-6:
Input Offset Voltage Drift.
© 2006 Microchip Technology Inc.
DS22004B-page 9
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
0
-10
-20
-30
-40
6
VDD = 5.0V
G = 50 V/V
VIN
RS = 1 MΩ
S = 100 kΩ
VDD = 5.0V
G = +1 V/V
5
4
R
VOUT
R
S = 10 kΩ
-50
-60
3
-70
-80
2
-90
1
RS = 0 Ω
-100
-110
-120
0
-1
1k
10k
100k
1.E+05
0.0E+00
1.0E-03
2.0E-03
3.0E-03
4.0E-03
5.0E-03
6.0E-03
7.0E-03
8.0E-03
9.0E-03
1.0E-02
1.E+03
1.E+04
Time (1 ms/div)
Frequency (Hz)
FIGURE 2-7:
The MCP6G01/1R/1U/2/3/4
FIGURE 2-10:
Crosstalk vs. Frequency,
family shows no phase reversal under overdrive.
with G = 50 (circuit in Figure 4-7).
90
120
110
100
90
Input Referred
VDD = 5.5V
G = 50
80
70
60
50
G = 10
40
30
20
80
VDD = 1.8V
G = 1
70
100
100
1k
1000
10k
10000
100k
100000
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Frequency (Hz)
FIGURE 2-8:
PSRR vs. Temperature.
FIGURE 2-11:
PSRR vs. Frequency.
10000
160
TA = +125°C
TA +85°C
140
120
100
80
=
G = +1
= +10
= +50
1000
100
10
60
TA
TA
=
=
+25°C
–40°C
40
20
0
0.1
1
10
100
1k
Frequency (Hz)
10k 100k
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
0.1
1
10
100 1000 10000 10000
0
FIGURE 2-9:
Input Noise Voltage Density
FIGURE 2-12:
Quiescent Current vs.
vs. Frequency.
Supply Voltage.
DS22004B-page 10
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
0
-1
-2
-3
-4
-5
-6
-7
-8
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
In Shutdown Mode
In Shutdown Mode
VIN = VDD/2
VIN = VDD/2
CS = VDD
VDD = 1.8V
VDD = 5.5V
ISS_SHDN
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-13:
Quiescent Current (I ) in
FIGURE 2-16:
Quiescent Current (I ) in
SS
SS
Shutdown Mode vs. Supply Voltage.
Shutdown Mode vs. Temperature.
1,000
1.E- 2
10m
1.E-03
1m
1.E-04
100µ
VDD = 5.5V
VIN = VDD
1.E-1005µ
1.E-016µ
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
100
10
1
+125°C
+85°C
+25°C
-40°C
55
65
75
85
95
105 115 125
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Ambient Temperature (°C)
FIGURE 2-14:
Input Bias Current vs.
FIGURE 2-17:
Input Bias Current vs. Input
Temperature.
Voltage.
10,000
30
25
20
15
10
5
VDD = 5.5V
TA
TA
TA
=
=
=
–40°C
+25°C
+85°C
1,000
100
10
TA = +125°C
TA = +85°C
TA = +125°C
0
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
FIGURE 2-15:
Voltage.
Input Bias Current vs. Input
FIGURE 2-18:
vs. Supply Voltage.
Output Short Circuit Current
© 2006 Microchip Technology Inc.
DS22004B-page 11
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
3
2
3
2
VDD = +5.5V
Representative Part
VDD = +1.8V
Representative Part
1
1
G = +1
0
0
G = +1
G = +10
G = +50
-1
-2
-3
-1
-2
-3
G = +10
G = +50
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Ideal Output Voltage; GVIN (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Ideal Output Voltage; GVIN (V)
FIGURE 2-19:
Output Voltage Error vs.
FIGURE 2-22:
Output Voltage Error vs.
Ideal Output Voltage, with V = 1.8V.
Ideal Output Voltage, with V = 5.5V.
DD
DD
4.0
1000
VDD = 5.5V: VDD–VOH
3.5
VOL–VSS
3.0
VDD = +1.8V
100
2.5
2.0
1.5
VDD – VOH
VDD = +5.5V
VOL – VSS
10
1.0
VDD = 1.8V: VOL–VSS
0.5
0.0
VDD–VOH
1
-50
-25
0
25
50
75
100 125
0.01
0.1
1
10
Output Current Magnitude (mA)
Ambient Temperature (°C)
FIGURE 2-20:
Output Voltage Headroom
FIGURE 2-23:
Output Voltage Headroom
vs. Output plus Ladder Current (circuit in
Figure 4-4).
vs. Temperature.
100k
1.E+05
14%
12%
10%
8%
G = 50
= 10
1228 Samples
T
A = -40 to +125°C
=
1
10k
1.E+04
6%
4%
1k
1.E+03
2%
0%
100
1.E+02
10k
1.E+04
100k
1.E+05
1M
1.E+06
10M
1.E+07
Ladder Resistance Drift (ppm/°C)
Frequency (Hz)
FIGURE 2-21:
Output Impedance vs.
FIGURE 2-24:
Ladder Resistance Drift.
Frequency.
DS22004B-page 12
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
0.7
0.6
10
G = +1 V/V
VDD = 5.5V
VDD = 5.5V
0.5
0.4
0.3
0.2
0.1
0.0
Falling Edge
Rising Edge
VDD = 1.8V
1
VDD = 1.8V
G = +1
G = +10
G = +50
0.1
1.E+03
1k
1.E+04
10k
1.E+05
100k
1.E+06
1M
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Frequency (Hz)
FIGURE 2-25:
Slew Rate vs. Temperature,
FIGURE 2-28:
Output Voltage Swing vs.
with G = +1.
Frequency.
3.0
4.0
G = +10 V/V
G = +50 V/V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.5V
VDD = 5.5V
2.5
2.0
1.5
1.0
0.5
0.0
Falling Edge
Falling Edge
Rising Edge
Rising Edge
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-26:
Slew Rate vs. Temperature,
FIGURE 2-29:
Slew Rate vs. Temperature,
with G = +10.
with G = +50.
1M
1.E+06
1.E+016M
G = +1
G = +1
G = +10
G = +50
G = +10
G = +50
100k
1.E+05
100k
1.E+05
10k
1.E+04
100
1k
1.E+03
10k
1.E+04
100k
1.E+05
10
100
1000
1.E+02
Resistive Load (ȍ)
Capacitive Load (pF)
FIGURE 2-27:
Bandwidth vs. Resistive
FIGURE 2-30:
Bandwidth vs. Capacitive
Load.
Load.
© 2006 Microchip Technology Inc.
DS22004B-page 13
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
40
30
7
6
5
4
3
2
1
0
G = +50
G = +10
G = +1
G = +10
G = +50
20
10
0
G = +1
-10
-20
-30
-40
10k
100k
1.E+05
1M
1.E+06
Frequency (Hz)
10M
10
100
Capacitive Load (pF)
1000
1.E+04
1.E+07
FIGURE 2-31:
Gain vs. Frequency.
FIGURE 2-34:
Gain Peaking vs. Capacitive
Load.
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
VDD = +5.0V
VDD = +5.0V
GVI
VOUT
G = +50
G = +10
G = +1
VOUT
G = +1
G = +10
G = +50
GVIN
0
0.00
5.00
10.00
15.00
20.00
25.00
35.00
40.00
45.00
50.00
Time (5 µs/3d0.0i0v)
Time (5 µs/3d0.0i0v)
0.00
5.00
10.00
15.00
20.00
25.00
35.00
40.00
45.00
50.00
FIGURE 2-32:
Small Signal Pulse
FIGURE 2-35:
Large Signal Pulse
Response.
Response.
10
10
G = +50
G = +10
G = +50
G = +10
1
0.1
1
0.1
G = +1
VOUT = 2.8VP-P
VDD = 5.0V
Measurement BW = 80 kHz
VOUT = 4 VP-P
VDD = 5.0V
0.01
0.001
0.01
0.001
G = +1
Measurement BW = 80 kHz
100
1k
1.E+03
10k
1.E+04
100k
1.E+05
100
1k
1.E+03
10k
1.E+04
100k
1.E+02
1.E+02
1.E+05
Frequency (Hz)
Frequency (Hz)
FIGURE 2-33:
THD plus Noise vs.
= 2.8 V
FIGURE 2-36:
THD plus Noise vs.
= 4.0 V
Frequency, V
.
Frequency, V
.
P-P
OUT
P-P
OUT
DS22004B-page 14
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
10
1
10
1
G = +50
G = +10
G = +50
G = +10
0.1
0.1
G = +1
G = +1
VOUT = 0.8VDD
f = 1 kHz
f = 1 kHz
VDD = 5.0V
0.01
0.001
0.01
Measurement BW = 80 kHz
Measurement BW = 80 kHz
0.001
1k
1.E+03
10k
1.E+04
Load Resistance (Ω)
100k
1.E+05
1M
1.E+06
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-37:
THD plus Noise vs. Supply
FIGURE 2-40:
THD plus Noise vs. Load
Voltage.
Resistance.
10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
10
1
5
5
G = +50
G = +10
0
GSEL
0
VDD = 5.0V
-5
VIN = 0.030V
-10
-15
-20
-25
-30
-35
-40
0.1
0.01
G = +1
VOUT
VDD = 5.0V
f = 1 kHz
(G = +50)
Measurement BW = 80 kHz
0.001
1
0.5
0.0
(G = +1)
(G = +1)
10
0
10
20
30
40
50
60
70
80
90
100
Output Swing (VP-P
)
Time (10 µs/div)
FIGURE 2-38:
THD plus Noise vs. Output
FIGURE 2-41:
Gain Select Timing, with
Swing.
Gain = 1 and 50.
10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
10
5
5
5
GSEL
5
0
0
0
0
GSEL
-5
-5
VDD = 5.0V
VDD = 5.0V
IN = 0.15V
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
VIN = 0.030V
V
VOUT
(G = +10)
(G = +10)
VOUT
1.5
1.0
0.5
0.0
(G = +50)
(G = +10)
(G = +1)
0.5
(G = +10)
0.0
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
Time (10 µs/div)
Time (10 µs/div)
FIGURE 2-39:
Gain = 1 and 10.
Gain Select Timing, with
FIGURE 2-42:
Gain = 1 and 10.
Gain Select Timing, with
© 2006 Microchip Technology Inc.
DS22004B-page 15
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
VOUT is "ON"
VDD = 1.8V
IN = 0.9VDD
VOUT is "ON"
VDD = 5.0V
V
VIN = 0.9VDD
Shutdown
Shutdown
G = 1
G = 10
G = 50
G = 1
G = 10
G = 50
1.8
0
5
0
CS
CS
Time (20 µs/div)
Time (20 µs/div)
FIGURE 2-43:
Output Voltage vs. Chip
FIGURE 2-46:
Output Voltage vs. Chip
Select, with V = 1.8V.
Select, with V = 5.0V.
DD
DD
10
10
VDD = 1.8V
VDD = 5.5V
8
8
6
4
6
4
TA
=
=
+25°C
+85°C
TA
=
=
+25°C
+85°C
2
0
2
0
TA = +125°C
TA = +125°C
=
=
+85°C
+25°C
= +125°C
=
=
+85°C
+25°C
= +125°C
-2
-2
-4
-4
-6
-6
-8
-8
-10
-10
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
GSEL Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
GSEL Voltage (V)
FIGURE 2-44:
GSEL Pin Current vs. GSEL
FIGURE 2-47:
GSEL Pin Current vs. GSEL
Voltage, with V = 1.8V.
Voltage, with V = 5.5V.
DD
DD
22%
20%
1228 Samples
18%
1228 Samples
GSEL = 0.3VDD
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
GSEL = 0.7VDD
16%
14%
12%
VDD = 5.5V
VDD = 1.8V
VDD = 1.8V
VDD = 5.5V
10%
8%
6%
4%
2%
0%
GSEL Current (µA)
GSEL Current (µA)
FIGURE 2-45:
GSEL Current, with GSEL
FIGURE 2-48:
GSEL Current, with GSEL
Voltage of 0.3V
.
Voltage of 0.7V
.
DD
DD
DS22004B-page 16
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL = 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
1228 Samples
G = +1 to +50
1227 Samples
G = +1 to +10
VDD = 5.5V
VDD = 1.8V
VDD = 1.8V
VDD = 5.5V
Normalized GSEL Trip Point; VGSEL/VDD
Normalized GSEL Trip Point; VGSEL/VDD
FIGURE 2-49:
GSEL Trip Point between
FIGURE 2-50:
GSEL Trip Point between
G = +1 and G = +10.
G = +1 and G = +50.
© 2006 Microchip Technology Inc.
DS22004B-page 17
MCP6G01/1R/1U/2/3/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6G01
(SOIC,
MSOP)
MCP6G01
(SOT-23-5)
MCP6G01R MCP6G01U
MCP6G03
Symbol
Description
(SOT-23-5)
(SOT-23-5)
6
2
1
4
1
4
4
3
6
2
VOUT
GSEL
VIN
Analog Output
Gain Select Input
Analog Input
3
3
3
1
3
7
5
2
5
7
VDD
VSS
CS
Positive Power Supply
Negative Power Supply
Chip Select
4
2
5
2
4
—
1,5,8
—
—
—
—
—
—
8
1,5
NC
No Internal Connection
TABLE 3-2:
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6G02
MCP6G04
Symbol
Description
1
2
1
2
VOUTA
GSELA
VINA
Analog Output A
Gain Select Input (SGA A)
Analog Input A
3
3
8
4
VDD
Positive Power Supply
Analog Input B
5
5
VINB
6
6
GSELB
VOUTB
VOUTC
GSELC
VINC
Gain Select Input (SGA B)
Analog Output B
7
7
—
—
—
4
8
Analog Output C
9
Gain Select Input (SGA C)
Analog Input C
10
11
12
13
14
VSS
Negative Power Supply
Analog Input D
—
—
—
VIND
GSELD
VOUTD
Gain Select Input (SGA D)
Analog Output D
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground, and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts need
to use a bulk capacitor (typically 1.0 µF to 10 µF) within
100 mm of the VDD pin; it can be shared with nearby
analog parts.
3.1
Analog Output
The output pin (VOUT) is a low impedance voltage
source. The selected gain (G) and input voltage (VIN)
determine its value.
3.2
Analog Input
The analog inputs (VIN) are high impedance CMOS
inputs with low bias currents. Only three fixed, non-
inverting gains are available through these inputs.
3.4
Digital Inputs
The Chip Select (CS) input is a Schmitt-triggered,
CMOS logic input.
3.3
Power Supply (VSS and VDD)
The Gain Select (GSEL) inputs are tri-level digital
inputs. They function similar to normal logic inputs at
low (G = +10) and high voltages (G = +50). The pin can
also be set to mid-supply (G = +1) by a low impedance
source, or by leaving this pin open.
The Positive Power Supply Pin (VDD) is 1.8V to 5.5V
higher than the Negative Power Supply Pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD
.
DS22004B-page 18
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
TABLE 4-1:
GAIN VS. INTERNAL
COMPENSATION
CAPACITOR
4.0
APPLICATIONS INFORMATION
The MCP6G01/1R/1U/2/3/4 family of Selectable Gain
Amplifiers (SGA) is based on simple analog building
blocks (see Figure 4-1). Each of these blocks will be
explained in more detail in the following subsections.
x
Internal
G
BW
SR
FPBW
BW
Gain
(V/V)
Comp.
Cap.
(MHz) (V/µs) (kHz) (kHz)
Typ.
Typ.
Typ.
Typ.
1
Large
Medium
Small
0.90
3.5
0.50
2.3
29
900
350
250
VDD
10
50
133
260
VIN
12.5
4.5
VOUT
Note 1: Changing the compensation capacitor does not
Gain
Switches
change the DC performance (e.g., VOS).
RF
x
2:
G
BW is approximately the Gain Bandwidth
3
Product of the internal op amp.
3: FPBW is the Full Power Bandwidth at
VDD = 5.5V, which is based on slew rate (SR).
4: BW is the closed-loop, small signal –3 dB
bandwidth.
RG
Gain Select
Logic
GSEL
CS
5 MΩ
(MCP6G03
only)
4.1.2
RAIL-TO-RAIL INPUTS
The input stage of the internal op amp uses two
differential input stages in parallel; one operates at low
VIN (input voltage), while the other operates at high VIN.
With this topology, the internal inputs can operate to
0.3V past either supply rail, although the output will clip
the signal before that happens.
VSS
Gain
(V/V)
GSEL Voltage (Typ.)
(V)
1
VDD/2 (or open)
The inputs need to be kept within a smaller range to
prevent output clipping. The input offset voltage also
reduces the range; most designs will need the following
for normal operation:
10
50
0
VDD
Note:
VSS is assumed to be 0V
EQUATION 4-1:
FIGURE 4-1:
SGA Block Diagram.
VOL
VOH
--------- + VOS < VIN < ---------- – VOS
4.1
Internal Op Amp
G
G
The internal op amp gives the right combination of
bandwidth, accuracy, and flexibility.
The transition between the two input stage occurs
when VIN ≈ VDD – 1.1V (see Figure 2-19 and Figure 2-
22). For the best distortion and gain linearity, avoid this
region of operation.
4.1.1
COMPENSATION CAPACITORS
The internal op amp has three compensation
capacitors (comp. caps.) connected to a switching
network. They are selected to give good small signal
bandwidth at high gains, and good slew rate (full power
bandwidth) at low gains. The change in bandwidth as
gain changes is between 250 and 900 kHz. Refer to
Table 4-1 for more information.
4.1.3
PHASE REVERSAL
The MCP6G01/1R/1U/2/3/4 amplifier family is
designed with CMOS input devices. It is designed to
not exhibit phase inversion when the input pins exceed
the supply voltages. Figure 2-7 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
© 2006 Microchip Technology Inc.
DS22004B-page 19
MCP6G01/1R/1U/2/3/4
current into the input pin (VIN) should be very small.
4.1.4
INPUT VOLTAGE AND CURRENT
LIMITS
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-17. Applications that are
high impedance may need to limit the useable voltage
range.
The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
4.1.5
RAIL-TO-RAIL OUTPUT
The maximum output voltage swing is the maximum
swing possible under a particular amplifier load current.
The amplifier load current is the sum of the external
load current (IOUT) and the current through the ladder
resistance (ILAD); see Figure 4-4.
Bond
VDD
Pad
EQUATION 4-2:
Amplifier Load Current = IOUT + ILAD
Bond
Pad
Input
Stage
to the rest of
the amplifier
VIN
Where:
(VOUT – VSS
)
ILAD = ---------------------------------
RLAD
Bond
Pad
VSS
FIGURE 4-2:
Simplified Analog Input ESD
IOUT
Structures.
VIN
VOUT
MCP6G0X
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN pins (see Section
“Absolute Maximum Ratings †” at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN) from going too far below ground, and the resistor
R1 limits the possible current drawn out of the input pin.
Diode D1 prevents the input pin (VIN) from going too far
above VDD. When implemented as shown, resistor R1
also limits the current through D1.
ILAD
RLAD
VSS
Amplifier Load Current.
FIGURE 4-4:
See Figure 2-20 for the typical output headroom
(VDD – VOH or VOL – VSS) as a function of amplifier
load current.The specification table states the output
can reach within 10 mV of either supply rail when
RL = 100 kΩ.
VDD
4.2
Resistor Ladder
The
resistor
ladder
shown
in
Figure 4-1
D1
(RLAD = RF + RG) sets the gain. Placing the gain
switches in series with the inverting input reduces the
parasitic capacitance, distortion, and gain mismatch.
V1
VOUT
MCP6G0X
VIN
R1
RLAD is an additional load on the output of the SGA and
causes additional current draw from the supplies.
VSS – (minimum expected V1)
2 mA
R1 ≥
When CS is high, the SGA is shut down (low power).
RLAD is still attached to the VOUT and VSS pins. Thus,
these pins and the internal amplifier’s inverting input
are all connected through RLAD and the output is not
high-Z (unlike the internal op amp).
FIGURE 4-3:
Inputs.
Protecting the Analog
It is also possible to connect the diode to the left of the
resistor R1. In this case, the current through the diode
D1 needs to be limited by some other mechanism. The
resistor then serves as in-rush current limiter; the DC
RLAD contributes to the output noise; see Figure 2-9.
DS22004B-page 20
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
RLAD is intended to be driven at the VSS pin by a low
impedance voltage source. The power supply driving
the VSS pin should have an output impedance less than
0.1Ω to maintain reasonable gain accuracy.
TABLE 4-3:
HARD WIRED GAIN
SELECTION
Selected Gain
Possible GSEL Drivers
+1 V/V
Open Circuit (Note 1)
Low impedance source at VDD/2
Tied to GND (0V)
4.3
MCP6G03 Chip Select (CS)
+10 V/V
+50 V/V
The MCP6G03 is a single amplifier with chip select
(CS). When CS is high, the internal op amp is shut
down and its output placed in a high-Z state. The
resistive ladder is always connected between VSS and
VOUT; even in shutdown. This means that the output
resistance will be 350 kΩ (typ.), with a path for output
signals to appear at the input. The supply current at
VSS includes the current through the load resistor and
ladder resistors; it also includes current from the CS pin
to VSS. When CS is low, the amplifier is enabled. If CS
is left floating, the amplifier may not operate properly.
Tied to VDD
Note 1: The GSEL pin floats to mid-supply
(VDD/2); a bypass capacitor may be
needed.
4.5
Capacitive Load and Stability
Large capacitive loads can cause stability problems
and reduced bandwidth for the MCP6G01/1R/1U/2/3/4
family of SGAs (Figure 2-30 and Figure 2-34). As the
load capacitance increases, there is a corresponding
increase in frequency response peaking and step
response overshoot and ringing. This happens
because a large load capacitance decreases the
internal amplifier’s phase margin and bandwidth.
Figure 1-2 and Figure 2-43 show how the output
voltage and supply current response to a CS pulse.
4.4
Gain Select (GSEL)
The amplifier can be set to the gains +1 V/V, +10 V/V,
and +50 V/V using one input pin (GSEL). At the same
time, different compensation capacitors are selected to
optimize the bandwidth vs. slew rate trade-off (see
Table 4-1). Table 4-2 shows how to change the gain
using a GPIO pin on a microcontroller and Table 4-3
shows how to hard wire the gain (i.e., using PCB
wiring).
When driving large capacitive loads with these SGAs
(i.e., > 60 pF), a small series resistor at the output
(RISO in Figure 4-5) improves the internal amplifier’s
stability by making the load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
RISO
TABLE 4-2:
MCU DRIVEN GAIN
SELECTION
VOUT
CL
VIN
MCP6G0X
Gain
MCU Pin’s State
+1 V/V
Output PIC’s VREF at VDD/2
Digital Output High-Z (Notes 1)
Output VDD/2 PWM signal (Notes 2)
FIGURE 4-5:
Capacitive Loads.
SGA Circuit for Large
+10 V/V Digital Output driven Low
+50 V/V Digital Output driven High
Figure 4-6 gives recommended RISO values for
different capacitive loads. After selecting RISO for your
circuit, double check the resulting frequency response
peaking and step response overshoot on the bench.
Modify RISO’s value until the response is reasonable at
all gains.
Note 1: See Section 4.8.1 “Driving the Gain
Select Pin with a Microcontroller GPIO
Pin”.
2: See Section 4.8.2 “Driving the Gain
Select Pin with a PWM Signal”
© 2006 Microchip Technology Inc.
DS22004B-page 21
MCP6G01/1R/1U/2/3/4
4.6.3
INPUT SOURCE IMPEDANCE
1,000
The sources driving the inputs of the SGAs need to
have reasonably low source impedance at higher
frequencies. Figure 4-7 shows how the external source
resistance (RS), SGA package pin capacitance (CP1),
and SGA package pin-to-pin capacitance (CP2) form a
positive feedback voltage divider network. Feedback
may cause frequency response peaking and step
response overshoot and ringing.
100
For all gains
10
10p
CP2
100p
100
1n
1,000
Load Capacitance (F)
10n
10,000
100n
100,000
10
FIGURE 4-6:
Recommended R
.
ISO
RS
VS
VOUT
MCP6G0X
4.6
Layout Considerations
CP1
Good PC board layout techniques will help achieve the
performance shown in Section 1.0 “Electrical
Characteristics”
and
Section 2.0
“Typical
Performance Curves”. It will also help minimize
Electromagnetic Compatibility (EMC) issues.
FIGURE 4-7:
Positive Feedback Path.
Figure 2-10 shows the crosstalk (referred to input) that
results when a hostile signal is connected to the other
inputs (e.g., VINB through VIND), and the input of
interest (e.g., VINA) has RS connected to GND. A gain
of +50 was chosen for this plot because it
demonstrates the worst-case behavior. Increasing RS
increases the crosstalk as expected. At a source
impedance of 10 MΩ, there is noticeable change in
behavior.
Because the MCP6G01/1R/1U/2/3/4 SGAs’ frequency
response reaches unity gain at 10 MHz when G = 50, it
is important to use good PCB layout techniques. Any
parasitic coupling at high frequency might cause
undesired peaking. Filtering high frequency signals
(i.e., fast edge rates) can help.
4.6.1
COMPONENT PLACEMENT
Separate different circuit functions: digital from analog,
low speed from high speed, and low power from high
power. This will reduce crosstalk.
Most designs should use a source resistance (RS) no
larger than 10 MΩ. Careful attention to layout parasitics
and proper component selection will help minimize this
effect. When a source impedance larger than 10 MΩ
must be used, place a capacitor in parallel to CP1 to
reduce the positive feedback. This capacitor needs to
be large enough to overcome gain (or crosstalk)
peaking, yet small enough to allow a reasonable signal
bandwidth.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high frequency (low rise time)
signals.
4.6.2
SUPPLY BYPASS
Use a local bypass capacitor (0.01 µF to 0.1 µF) within
2 mm of the VDD pin for good, high frequency
performance. It must connect directly to ground.
4.6.4
SIGNAL COUPLING
The input pins of the MCP6G01/1R/1U/2/3/4 family of
SGAs are high impedance. This makes them especially
susceptible to capacitively coupled noise. Using a
ground plane helps reduce this problem.
Use a bulk bypass capacitor (i.e., 1.0 µF to 10 µF)
within 100 mm of the VDD pin. It needs to connect to
ground, and provides large, slow currents. This
capacitor may be shared with other nearby analog
parts.
When noise is capacitively coupled, the ground plane
provides additional shunt capacitance to ground. When
noise is magnetically coupled, the ground plane
reduces the mutual inductance between traces.
Increasing the separation between traces makes a
significant difference.
Ground plane is important, and power plane(s) can
also be of great help. High frequency (e.g., multi-layer
ceramic capacitors), surface mount components
improve the supply’s performance.
Changing the direction of one of the traces can also
reduce magnetic coupling. It may help to locate guard
traces next to the victim trace. They should be on both
sides of, and as close as possible to, the victim trace.
Connect the guard traces to the ground plane at both
ends. Also connect long guard traces to the ground
plane in the middle.
DS22004B-page 22
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
4.8.2
DRIVING THE GAIN SELECT PIN
WITH A PWM SIGNAL
4.7
Unused Amplifiers
An unused amplifier in a quad package (MCP6G04)
should be configured as shown in Figure 4-8. This
circuit prevents the output from toggling and causing
crosstalk. Because the VIN pin looks like an open
circuit, the GSEL voltage is automatically set at VDD/2,
and the gain is 1 V/V. The output pin provides a
buffered VDD/2 voltage and minimizes the supply
current draw of the unused amplifier.
The circuit in Figure 4-10 uses a PWM output on a PIC
microcontroller (100 kHz clock rate) to drive the Gain
Select input (GSEL). Setting the PWM duty cycle to
0%, 50% or 100% gives a GSEL voltage of 0V, VDD/2
or VDD, respectively (G = 10, 1 or 50).
VDD
¼ MCP6G04
VIN
MCP6G0X
VOUT
VDD
GSEL
VDD
VIN
MCP6G0X
VOUT
PIC MCU
GSEL
10 kΩ
10 kΩ
4.7 nF
PWM
Output
4.7 nF
FIGURE 4-8:
Unused Amplifiers.
4.8
Typical Applications
FIGURE 4-10:
Driving the GSEL Pin.
The PWM clock rate needs to be fast so it is easily
filtered and does not interfere with the desired signal,
and it needs to be slow enough for good accuracy and
low crosstalk. This filter reduces the ripple at the GSEL
pin to about 7 mVP-P at VDD = 5.0V. The 10% settling
time is about 200 µs; the filter limits how quickly the
gain can be changed. Scale the resistors and/or
capacitors for other clock rates, or for different ripple.
4.8.1
DRIVING THE GAIN SELECT PIN
WITH A MICROCONTROLLER GPIO
PIN
The circuit in Figure 4-9 uses a microcontroller GPIO
pin to drive the Gain Select input (GSEL). Setting the
GPIO pin to logic low, high-Z or logic high gives a GSEL
voltage of 0V, VDD/2 or VDD, respectively (G = 10, 1 or
50).
4.8.3
GAIN RANGING
VDD
Figure 4-11 shows a circuit that measures the current
IX. The circuit’s performance benefits from changing
the gain on the SGA. Just as a hand-held multimeter
uses different measurement ranges to obtain the best
results, this circuit makes it easy to set a high gain for
small signals and a low gain for large signals. As a
result, the required dynamic range at the SGA’s output
is less than at its input (by up to 34 dB).
VDD
VIN
MCP6G0X
VOUT
GSEL
MCU
GPIO
Pin
VOUT
MCP6G0X
FIGURE 4-9:
Driving the GSEL Pin.
IX
The microcontroller’s GPIO pin cannot produce a
leakage current of more than ±1 µA for this circuit to
function properly. In noisy environments, a capacitor
may need to be added to the GPIO pin.
RS
FIGURE 4-11:
Wide Dynamic Range
Current Measurement Circuit.
© 2006 Microchip Technology Inc.
DS22004B-page 23
MCP6G01/1R/1U/2/3/4
4.8.4
SHIFTED GAIN RANGE SGA
4.8.5
ADC DRIVER
Figure 4-12 shows a circuit using a MCP6271 at a gain
of +10 in front of a MCP6G01. This shifts the overall
gain range to +10 V/V to +500 V/V (from +1 V/V to
+50 V/V).
This family of SGAs is well suited for driving Analog-to-
Digital Converters (ADC). The gains (1, 10, and 50)
effectively increase the ADC’s input resolution by a
factor of as large as 50 (i.e., by 5.6 bits). This works
well for applications needing relative accuracy more
than absolute accuracy (e.g., power monitoring); see
Figure 4-14.
VIN
VOUT
MCP6271
MCP6G01
Low-pass
Filter
MCP3001
3
VIN
MCP6G01
10-bit
ADC
OUT
10.0 kΩ
1.11 kΩ
FIGURE 4-14:
SGA as an ADC Driver.
The low-pass filter in the block diagram reduces the
integrated noise at the MCP6G01’s output and serves
as an anti-aliasing filter. This filter may be designed
using Microchip’s FilterLab® software, available at
www.microchip.com.
FIGURE 4-12:
Range.
SGA with Higher Gain
It is also easy to shift the gain range to lower gains (see
Figure 4-13). The MCP6001 acts as a unity gain buffer,
and the resistive voltage divider shifts the gain range
down to +0.1 V/V to +5.0 V/V (from +1 V/V to +50 V/V).
VIN
MCP6001
10.0 kΩ
VOUT
MCP6G01
1.11 kΩ
FIGURE 4-13:
SGA with Lower Gain
Range.
DS22004B-page 24
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
5.0
5.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SOT-23 (MCP6G01, MCP6G01R, MCP6G01U)
Device
Code
MCP6G01
CKNN
CLNN
CMNN
XXNN
CK25
MCP6G01R
MCP6G01U
Note: Applies to 5-Lead SOT-23
8-Lead SOIC (150 mil) (MCP6G01, MCP6G02, MCP6G03)
Example:
XXXXXXXX
XXXXYYWW
MCP6G01E
SN^
e
3
0634
NNN
256
Example:
8-Lead MSOP (MCP6G01, MCP6G02, MCP6G03)
6G01E
XXXXXX
YWWNNN
634256
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006 Microchip Technology Inc.
DS22004B-page 25
MCP6G01/1R/1U/2/3/4
Package Marking Information (Continued)
14-Lead SOIC (150 mil) (MCP6S24)
Example:
MCP6G04
E/SL^
XXXXXXXXXXX
XXXXXXXXXXX
e
3
YYWWNNN
0609256
14-Lead TSSOP (4.4mm) (MCP6S24)
Example:
XXXXXXXX
YYWW
6G04E/ST
0609
256
NNN
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS22004B-page 26
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
B
p1
D
n
1
α
c
A
A2
φ
L
A1
β
Units
INCHES
NOM
*
MILLIMETERS
NOM
5
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
5
.038
0.95
p1
A
Outside lead pitch (basic)
Overall Height
.075
.046
.043
.003
.110
.064
.116
.018
1.90
.035
.057
0.90
1.18
1.45
1.30
0.15
3.00
1.75
3.10
0.55
Molded Package Thickness
Standoff
A2
A1
E
.035
.000
.102
.059
.110
.014
.051
.006
.118
.069
.122
.022
10
0.90
0.00
2.60
1.50
2.80
0.35
1.10
0.08
Overall Width
2.80
Molded Package Width
Overall Length
E1
D
1.63
2.95
Foot Length
L
f
0.45
Foot Angle
0
5
0
5
10
c
Lead Thickness
Lead Width
.004
.014
.006
.017
.008
.020
10
0.09
0.35
0.15
0.43
0.20
0.50
B
a
Mold Draft Angle Top
Mold Draft Angle Bottom
0
0
5
5
0
5
5
10
10
b
10
0
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
EIAJ Equivalent: SC-74A
Revised 09-12-05
Drawing No. C04-091
© 2006 Microchip Technology Inc.
DS22004B-page 27
MCP6G01/1R/1U/2/3/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
2
b
1
e
c
ϕ
A2
A
L1
L
A1
Units
MILLIMETERS
Dimension Limits
NOM
8
MAX
MIN
Number of Pins
Pitch
N
e
0.65 BSC
—
—
Overall Height
A
1.10
0.95
0.15
0.75
0.00
0.85
Molded Package Thickness
Standoff
A2
A1
E
—
4.90 BSC
3.00 BSC
3.00 BSC
0.60
Overall Width
Molded Package Width
Overall Length
Foot Length
E1
D
0.40
L
0.80
0.95 REF
—
Footprint
L1
0°
Foot Angle
ϕ
8°
0.08
0.22
—
Lead Thickness
Lead Width
c
0.23
0.40
—
b
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–111, Sept. 8, 2006
DS22004B-page 28
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
© 2006 Microchip Technology Inc.
DS22004B-page 29
MCP6G01/1R/1U/2/3/4
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
14
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
5.99
3.90
8.69
0.38
0.84
4
1.75
Molded Package Thickness
A2
A1
E
.052
.004
.228
.150
.337
.010
.016
0
.061
.010
.244
.157
.347
.020
.050
8
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
Standoff
§
0.10
5.79
3.81
8.56
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
0
12
15
0
12
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
Revised 7-20-06
DS22004B-page 30
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
1
n
B
α
A
c
φ
β
L
A1
A2
Units
INCHES
NOM
MILLIMETERS
NOM
14
*
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
14
.026 BSC
.041
0.65 BSC
1.05
Overall Height
A
A2
A1
E
.039
.033
.002
.246
.169
.193
.020
.043
1.00
1.10
Molded Package Thickness
Standoff
.035
.004
.251
.173
.197
.024
.037
.006
.256
.177
.201
.028
0.85
0.05
6.25
4.30
4.90
0.50
0.90
0.95
0.15
6.50
4.50
5.10
0.70
0.10
Overall Width
6.38
Molded Package Width
Molded Package Length
Foot Length
E1
D
4.40
5.00
L
0.60
φ
Foot Angle
0°
4°
8°
0°
4°
0.15
0.25
12° REF
12° REF
8°
c
Lead Thickness
.004
.007
.006
.010
.008
.012
0.09
0.19
0.20
0.30
Lead Width
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
12° REF
12° REF
β
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tole rance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-153 AB-1
Drawing No. C04-087
Revised: 08-17-05
© 2006 Microchip Technology Inc.
DS22004B-page 31
MCP6G01/1R/1U/2/3/4
NOTES:
DS22004B-page 32
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
APPENDIX A: REVISION HISTORY
Revision B (December 2006)
The following is the list of modifications:
• Added SOT-23-5 package option for the single
gain blocks MCP6G01, MCP6G01R, and
MCP6G01U.
• Added a discussion on VIN range vs. G.
Revision A (September 2006)
• Original Release of this Document.
© 2006 Microchip Technology Inc.
DS22004B-page 33
MCP6G01/1R/1U/2/3/4
NOTES:
DS22004B-page 34
© 2006 Microchip Technology Inc.
MCP6G01/1R/1U/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
–X
/XX
a)
MCP6G01-E/MS: Extended Temperature,
Temperature Package
Range
8LD MSOP.
b)
MCP6G01T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC.
Device:
MCP6G01:
MCP6G01T:
Single SGA
Single SGA
(Tape and Reel for MSOP and SOIC)
c)
d)
e)
MCP6G01T-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23-5.
MCP6G01RT: Single SGA
(Tape and Reel for SOT-23-5)
MCP6G01UT: Single SGA
(Tape and Reel for SOT-23-5)
Dual SGA
MCP6G01RT-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23-5.
MCP6G02:
MCP6G02T:
Dual SGA
(Tape and Reel for MSOP and SOIC)
Single SGA
MCP6G01UT-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23-5.
MCP6G03:
MCP6G03T:
Single SGA
(Tape and Reel for MSOP and SOIC)
Quad SGA
Quad SGA
a)
b)
MCP6G02-E/MS: Extended Temperature,
8LD MSOP.
MCP6G04:
MCP6G04T:
(Tape and Reel for SOIC and TSSOP)
MCP6G02T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC.
Temperature Range:
Package:
E
=
-40°C to +125°C
a)
b)
MCP6G03-E/MS: Extended Temperature,
8LD MSOP.
MS
OT
SN
SL
=
=
=
=
=
Plastic MSOP, 8-lead
Plastic Small Outline Transistor (SOT-23-5), 5-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead (MCP6G04)
Plastic TSSOP (4.4mm Body), 14-lead (MCP6G04)
MCP6G03T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC.
ST
c)
a)
MCP6G03-E/SN: Extended Temperature,
8LD SOIC.
MCP6G04T-E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC.
b)
c)
MCP6G04T-E/ST: Tape and Reel,
Extended Temperature,
14LD TSSOP.
MCP6G04-E/ST:
Extended Temperature,
14LD TSSOP.
© 2006 Microchip Technology Inc.
DS22004B-page 35
MCP6G01/1R/1U/2/3/4
NOTES:
DS22004B-page 36
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs,
microperipherals, nonvolatile memory and analog products. In addition,
Microchip’s quality system for the design and manufacture of
development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS22004B-page 37
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Habour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
10/19/06
DS22004B-page 38
© 2006 Microchip Technology Inc.
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