MCP633-E/MF [MICROCHIP]
24 MHz, 2.5 mA Op Amps; 24兆赫， 2.5毫安运算放大器
| 型号： | MCP633-E/MF |
| 厂家： | 
MICROCHIP |
| 描述： | 24 MHz, 2.5 mA Op Amps |
| 文件： | 总42页 (文件大小：789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP631/2/3/5
24 MHz, 2.5 mA Op Amps
Features
Description
• Gain Bandwidth Product: 24 MHz (typical)
• Short Circuit Current: 70 mA (typical)
• Noise: 10 nV/√Hz (typical, at 1 MHz)
• Rail-to-Rail Output
The Microchip Technology, Inc. MCP631/2/3/5 family of
operational amplifiers features high gain bandwidth
product (24 MHz, typical) and high output short circuit
current (70 mA, typical). Some also provide a Chip
Select pin (CS) that supports a low power mode of
operation. These amplifiers are optimized for high
speed, low noise and distortion, single-supply
operation with rail-to-rail output and an input that
includes the negative rail.
• Slew Rate: 10 V/µs (typical)
• Supply Current: 2.5 mA (typical)
• Power Supply: 2.5V to 5.5V
• Extended Temperature Range: -40°C to +125°C
This family is offered in single (MCP631), single with
CS pin (MCP633), dual (MCP632) and dual with
two CS pins (MCP635). All devices are fully specified
from -40°C to +125°C.
Typical Applications
• Driving A/D Converters
• Power Amplifier Control Loops
• Barcode Scanners
Typical Application Circuit
• Optical Detector Amplifier
R1
R2
VDD/2
VOUT
RL
Design Aids
R3
• SPICE Macro Models
• FilterLab® Software
VIN
MCP63X
• Mindi™ Circuit Designer & Simulator
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
Power Driver with High Gain
Package Types
MCP633
MCP631
MCP632
MCP635
SOIC
SOIC
SOIC
MSOP
VDD
V
DD
VOUTA
1
8
7
6
5
1
8
7
6
5
1
8
7
6
5
VOUTA
1
2
3
10
9
NC
CS
NC
NC
VOUTB
VINA
–
+
VOUTB
2
3
4
2
3
4
2
3
4
VINA
–
+
VIN
–
+
VDD
VOUT
NC
VIN
–
+
VDD
VOUT
NC
VINA
VINB
VINB
–
+
VINA
VINB
VINB
–
+
8
VIN
VIN
VSS 4
VSS
7
VSS
VSS
CSA
5
CSB
6
MCP632
3x3 DFN *
MCP635
3x3 DFN *
1
2
3
4
5
10
VDD
VOUTA
VDD
VOUTA
1
8
7
6
5
VINA
VINA
–
+
VOUTB
9
8
7
6
VINA
VINA
VSS
–
VOUTB
2
3
4
VINB
VINB
–
+
+
VINB
VINB
–
+
VSS
CSA
CSB
* Includes Exposed Thermal Pad (EP); see Table 3-1.
© 2009 Microchip Technology Inc.
DS22197A-page 1
MCP631/2/3/5
NOTES:
DS22197A-page 2
© 2009 Microchip Technology Inc.
MCP631/2/3/5
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS .......................................................................6.5V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD + 1.0V
All other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3V
Output Short Circuit Current ................................Continuous
Current at Output and Supply Pins ..........................±150 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................+150°C
ESD protection on all pins (HBM, MM) ................≥ 1 kV, 200V
†† See Section 4.1.2 “Input Voltage and Current Limits”.
1.2
Specifications
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3,
VOUT ≈ VDD/2, VL = VDD/2, RL = 2 kΩ to VL and CS = VSS (refer to Figure 1-2).
Conditions
Parameters
Sym
Min
Typ
Max
Units
Input Offset
Input Offset Voltage
VOS
-8
—
61
±1.8
±2.0
76
+8
—
—
mV
Input Offset Voltage Drift
Power Supply Rejection Ratio
Input Current and Impedance
Input Bias Current
ΔVOS/ΔTA
PSRR
µV/°C TA= -40°C to +125°C
dB
IB
IB
—
—
—
—
—
—
4
—
—
pA
Across Temperature
100
pA
pA
TA= +85°C
Across Temperature
IB
1500
5,000
—
TA= +125°C
Input Offset Current
IOS
ZCM
ZDIFF
±2
pA
Common Mode Input Impedance
Differential Input Impedance
Common Mode
1013||9
1013||2
—
Ω||pF
Ω||pF
—
Common-Mode Input Voltage Range
Common-Mode Rejection Ratio
VCMR
CMRR
CMRR
VSS − 0.3
—
78
81
VDD − 1.3
V
(Note 1)
63
66
—
—
dB
dB
VDD = 2.5V, VCM = -0.3 to 1.2V
VDD = 5.5V, VCM = -0.3 to 4.2V
Open Loop Gain
DC Open Loop Gain (large signal)
AOL
AOL
88
94
115
124
—
—
dB
dB
VDD = 2.5V, VOUT = 0.3V to 2.2V
VDD = 5.5V, VOUT = 0.3V to 5.2V
Output
Maximum Output Voltage Swing
VOL, VOH VSS + 20
OL, VOH VSS + 40
—
—
VDD − 20
VDD − 40
mV
mV
VDD = 2.5V, G = +2,
0.5V Input Overdrive
V
VDD = 5.5V, G = +2,
0.5V Input Overdrive
Output Short Circuit Current
ISC
ISC
±40
±35
±85
±70
±130
±110
mA
mA
VDD = 2.5V (Note 2)
VDD = 5.5V (Note 2)
Power Supply
Supply Voltage
VDD
IQ
2.5
1.2
—
5.5
3.6
V
Quiescent Current per Amplifier
2.5
mA
No Load Current
Note 1: See Figure 2-5 for temperature effects.
2: The ISC specifications are for design guidance only; they are not tested.
© 2009 Microchip Technology Inc.
DS22197A-page 3
MCP631/2/3/5
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS (refer to Figure 1-2).
Parameters
Sym
Min
Typ
Max Units
Conditions
AC Response
Gain Bandwidth Product
Phase Margin
GBWP
PM
—
—
—
24
65
20
—
—
—
MHz
°
G = +1
Open Loop Output Impedance
AC Distortion
ROUT
Ω
Total Harmonic Distortion plus Noise
THD+N
—
0.0015
—
%
G = +1, VOUT = 2VP-P, f = 1 kHz,
DD = 5.5V, BW = 80 kHz
V
Step Response
Rise Time, 10% to 90%
Slew Rate
tr
—
—
20
10
—
—
ns
G = +1, VOUT = 100 mVP-P
SR
V/µs G = +1
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Eni
eni
ini
—
—
16
10
4
—
—
—
µVP-P f = 0.1 Hz to 10 Hz
nV/√Hz f = 1 MHz
fA/√Hz f = 1 kHz
TABLE 1-3:
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS (refer to Figure 1-1 and Figure 1-2).
Parameters
Sym
Min
Typ
Max Units
Conditions
CS Low Specifications
CS Logic Threshold, Low
CS Input Current, Low
CS High Specifications
CS Logic Threshold, High
CS Input Current, High
GND Current
VIL
VSS
—
—
0.2VDD
—
V
ICSL
0.1
nA
CS = 0V
VIH
ICSH
0.8VDD
VDD
—
V
—
-2
0.7
-1
µA
µA
MΩ
nA
CS = VDD
ISS
—
CS Internal Pull Down Resistor
Amplifier Output Leakage
CS Dynamic Specifications
CS Input Hysteresis
RPD
—
—
5
—
IO(LEAK)
50
—
CS = VDD, TA = +125°C
—
—
—
—
VHYST
tOFF
0.25
200
V
CS High to Amplifier Off Time
(output goes High-Z)
ns
G = +1 V/V, VL = VSS
CS = 0.8VDD to VOUT = 0.1(VDD/2)
G = +1 V/V, VL = VSS
CS = 0.2VDD to VOUT = 0.9(VDD/2)
,
CS Low to Amplifier On Time
tON
—
2
10
µs
DS22197A-page 4
© 2009 Microchip Technology Inc.
MCP631/2/3/5
TABLE 1-4:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND.
Parameters
Temperature Ranges
Sym
Min
Typ
Max Units
Conditions
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
(Note 1)
Thermal Package Resistances
Thermal Resistance, 8L-3x3 DFN
Thermal Resistance, 8L-SOIC
θJA
θJA
θJA
θJA
—
—
—
—
60
149.5
57
—
—
—
—
°C/W (Note 2)
°C/W
Thermal Resistance, 10L-3x3 DFN
Thermal Resistance, 10L-MSOP
°C/W (Note 2)
°C/W
202
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).
2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.
EQUATION 1-1:
1.3
Timing Diagram
GDM = RF ⁄ RG
GN = 1 + GDM
0.1 nA
(typical)
0.7 µA
(typical)
0.7 µA
(typical)
ICS
CS
VCM = VP(1 – 1 ⁄ GN) + VREF(1 ⁄ GN)
VOST = VIN– – VIN+
VIH
VIL
VOUT = VREF + (VP – VM)GDM + VOSTGN
Where:
tON
tOFF
GDM = Differential Mode Gain
GN = Noise Gain
(V/V)
(V/V)
(V)
VOUT
High-Z
High-Z
On
VCM = Op Amp’s Common Mode
-2.5 mA
(typical)
Input Voltage
-1 µA
(typical)
-1 µA
(typical)
ISS
VOST = Op Amp’s Total Input Offset
(mV)
Voltage
FIGURE 1-1:
Timing Diagram.
1.4
Test Circuits
CF
6.8 pF
The circuit used for most DC and AC tests is shown in
Figure 1-2. It independently sets VCM and VOUT; see
Equation 1-1. The circuit’s common mode voltage is
(VP + VM)/2, not VCM. VOST includes VOS plus the
RG
RF
10 kΩ
10 kΩ
VREF = VDD/2
VDD
effects of temperature, CMRR, PSRR and AOL
.
VP
VIN+
CB1
CB2
100 nF
2.2 µF
MCP63X
VIN–
VOUT
VM
RL
CL
RG
RF
2 kΩ
50 pF
10 kΩ
10 kΩ
CF
6.8 pF
VL
FIGURE 1-2:
AC and DC Test Circuit for
Most Specifications.
© 2009 Microchip Technology Inc.
DS22197A-page 5
MCP631/2/3/5
NOTES:
DS22197A-page 6
© 2009 Microchip Technology Inc.
MCP631/2/3/5
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS
.
2.1
DC Signal Inputs
14%
12%
10%
8%
-1.0
-1.2
-1.4
-1.6
-1.8
-2.0
-2.2
-2.4
-2.6
-2.8
-3.0
396 Samples
TA = +25°C
VDD = 2.5V and 5.5V
Representative Part
VDD = 2.5V
VDD = 5.5V
6%
4%
2%
0%
-6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage (mV)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage vs.
Output Voltage.
16%
0.0
398 Samples
1 Lot
VDD = 2.5V and 5.5V
TA = -40°C to +125°C
14%
12%
10%
8%
Low (VCMR_L – VSS
)
-0.1
-0.2
-0.3
-0.4
-0.5
6%
VDD = 2.5V and 5.5V
4%
2%
0%
-8 -7 -6 -5 -4 -3 -2 -1
0 1 2 3 4 5 6 7 8
-50
-25
0
25
50
75
100 125
Input Offset Voltage Drift (µV/°C)
Ambient Temperature (°C)
FIGURE 2-2:
Input Offset Voltage Drift.
FIGURE 2-5:
Low Input Common Mode
Voltage Headroom vs. Ambient Temperature.
-2.0
-2.2
-2.4
-2.6
-2.8
-3.0
-3.2
-3.4
-3.6
-3.8
-4.0
1.3
Representative Part
VCM = VSS
1 Lot
High (VDD – VCMR_H
)
1.2
1.1
1.0
0.9
VDD = 2.5V
+125°C
+85°C
+25°C
-40°C
VDD = 5.5V
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-3:
Power Supply Voltage with V
Input Offset Voltage vs.
= 0V.
FIGURE 2-6:
Voltage Headroom vs. Ambient Temperature.
High Input Common Mode
CM
© 2009 Microchip Technology Inc.
DS22197A-page 7
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS
.
2.0
130
125
120
115
110
105
100
VDD = 2.5V
1.5 Representative Part
+125°C
+85°C
+25°C
-40°C
1.0
VDD = 5.5V
VDD = 2.5V
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Input Common Mode Voltage (V)
FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
DC Open-Loop Gain vs.
Common Mode Voltage with V = 2.5V.
Ambient Temperature.
DD
2.0
130
VDD = 5.5V
VDD = 5.5V
Representative Part
1.5
125
120
115
110
105
100
95
1.0
+125°C
+85°C
+25°C
-40°C
0.5
0.0
VDD = 2.5V
-0.5
-1.0
-1.5
-2.0
100
1k
1.E+03
10k
1.E+04
100k
1.E+05
1.E+02
Load Resistance (Ω)
Input Common Mode Voltage (V)
FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
DC Open-Loop Gain vs.
Common Mode Voltage with V = 5.5V.
Load Resistance.
DD
110
105
100
1.E1-008n
VDD = 5.5V
VCM = VCMR_H
1n
1.E-09
95
CMRR, VDD = 2.5V
90
85
80
75
70
65
60
CMRR, VDD = 5.5V
IB
100p
1.E-10
10p
1.E-11
PSRR
| IOS
|
1p
1.E-12
-50
-25
0
25
50
75
100
125
25
45
65
85
105
125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-9:
CMRR and PSRR vs.
FIGURE 2-12:
Input Bias and Offset
Ambient Temperature.
Currents vs. Ambient Temperature with
= +5.5V.
V
DD
DS22197A-page 8
© 2009 Microchip Technology Inc.
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS
.
2000
1500
1000
500
1.E-10m3
1.E10-004µ
IB
10µ
1.E-05
1µ
1.E-06
100n
1.E-07
IOS
10n
1.E- 8
0
1n
1.E-09
+125°C
+85°C
+25°C
-40°C
-500
-1000
-1500
Representative Part
A = +125°C
VDD = 5.5V
100p
1.E-10
T
10p
1.E-11
1p
1.E-12
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-13:
Input Bias Current vs. Input
FIGURE 2-15:
Input Bias and Offset
Voltage (below V ).
Currents vs. Common Mode Input Voltage with
T = +125°C.
SS
A
200
150
100
50
IB
0
IOS
-50
-100
-150
-200
Representative Part
A = +85°C
VDD = 5.5V
T
Common Mode Input Voltage (V)
FIGURE 2-14:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
T = +85°C.
A
© 2009 Microchip Technology Inc.
DS22197A-page 9
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS
.
2.2
Other DC Voltages and Currents
1000
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.5V
100
10
1
+125°C
+85°C
+25°C
-40°C
VDD = 2.5V
VOL – VSS
VDD – VOH
0.1
1
10
100
Output Current Magnitude (mA)
Power Supply Voltage (V)
FIGURE 2-16:
Output Voltage Headroom
FIGURE 2-19:
Supply Current vs. Power
vs. Output Current.
Supply Voltage.
20
3.5
3.0
2.5
2.0
RL = 2 kΩ
18
VDD = 5.5V
16
14
12
VOL – VSS
VDD = 2.5V
VDD = 5.5V
10
1.5
1.0
0.5
0.0
8
6
4
2
0
VDD = 2.5V
VDD – VOH
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Common Mode Input Voltage (V)
FIGURE 2-17:
Output Voltage Headroom
FIGURE 2-20:
Supply Current vs. Common
vs. Ambient Temperature.
Mode Input Voltage.
100
80
60
+125°C
+85°C
+25°C
-40°C
40
20
0
-20
-40
-60
-80
-100
Power Supply Voltage (V)
FIGURE 2-18:
Output Short Circuit Current
vs. Power Supply Voltage.
DS22197A-page 10
© 2009 Microchip Technology Inc.
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS
.
2.3
Frequency Response
100
90
80
70
60
50
40
30
20
10
36
34
32
30
28
26
24
22
20
80
75
70
65
60
55
50
45
40
PM
VDD = 5.5V
VDD = 2.5V
CMRR
PSRR+
PSRR-
GBWP
100
11.Ek+3
10k
100k
1M
10M
1.E+7
1.E+2
1.E+4
1.E+5
1.E+6
Frequency (Hz)
Common Mode Input Voltage (V)
FIGURE 2-21:
CMRR and PSRR vs.
FIGURE 2-24:
Gain Bandwidth Product
Frequency.
and Phase Margin vs. Common Mode Input
Voltage.
140
120
100
80
0
36
34
32
30
28
26
24
22
20
80
-30
75
70
65
60
55
50
45
40
PM
-60
-90
∠AOL
VDD = 5.5V
VDD = 2.5V
60
-120
-150
-180
-210
-240
40
| AOL
|
20
0
GBWP
-20
1
10 100 1k 10k 100k 11.EM+6 10M 100M
1.E+7 1.E+8
1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Frequency (Hz)
FIGURE 2-22:
Open-Loop Gain vs.
FIGURE 2-25:
Gain Bandwidth Product
Frequency.
and Phase Margin vs. Output Voltage.
36
34
32
30
80
75
70
65
60
55
50
45
40
100
PM
G = 101 V/V
G = 11 V/V
G = 1 V/V
10
VDD = 5.5V
VDD = 2.5V
28
26
24
22
20
1
GBWP
0.1
10k
100k
1.0E+05
1M
10M
1.0E+07
100M
-50 -25
0
25
50
75 100 125
1.0E+04
1.0E+06
1.0E+08
Ambient Temperature (°C)
Frequency (Hz)
FIGURE 2-23:
Gain Bandwidth Product
FIGURE 2-26:
Closed-Loop Output
and Phase Margin vs. Ambient Temperature.
Impedance vs. Frequency.
© 2009 Microchip Technology Inc.
DS22197A-page 11
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS
.
10
9
150
140
130
120
110
100
90
RS = 0Ω
R
R
S = 100Ω
S = 1 kΩ
8
GN = 1 V/V
GN = 2 V/V
7
GN ≥ 4 V/V
6
5
4
3
2
1
0
VCM = VDD/2
G = +1 V/V
80
70
RS = 10 kΩ
S = 100 kΩ
60
R
50
1k
10k
1.E+04
100k
1.E+05
1M
1.E+06
10M
1.E+07
10p
1.0E-11
100p
1.0E-10
1n
1.0E-09
1.E+03
Normalized Capacitive Load; CL/GN (F)
Frequency (Hz)
FIGURE 2-27:
Gain Peaking vs.
FIGURE 2-28:
Channel-to-Channel
Normalized Capacitive Load.
Separation vs. Frequency.
DS22197A-page 12
© 2009 Microchip Technology Inc.
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS
.
2.4
Noise and Distortion
1.E+4
10µ
20
15
10
5
Representative Part
1.E+3
1µ
0
110.E0+n2
11.E0+n1
-5
-10
-15
-20
Analog NPBW = 0.1 Hz
Sample Rate = 2 SPS
VOS = -3150 µV
1n
1.E+0
0
5 10 15 20 25 30 35 40 45 50 55 60 65
0.1
1
10 100 1k 10k 100k 11.EM+6 10M
1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+7
Frequency (Hz)
Time (min)
FIGURE 2-29:
Input Noise Voltage Density
FIGURE 2-32:
Input Noise vs. Time with
vs. Frequency.
0.1 Hz Filter.
200
180
1
VDD = 2.5V
160
140
120
100
80
0.1
G = 1 V/V
G = 11 V/V
BW = 22 Hz to > 500 kHz
VDD = 5.5V
0.01
0.001
60
40
BW = 22 Hz to 80 kHz
VDD = 5.0V
20
f = 100 Hz
VOUT = 2 VP-P
0
0.0001
100
1.E+2
1k
1.E+3
10k
1.E+4
100k
1.E+5
Frequency (Hz)
Common Mode Input Voltage (V)
FIGURE 2-30:
Input Noise Voltage Density
FIGURE 2-33:
THD+N vs. Frequency.
vs. Input Common Mode Voltage with f = 100 Hz.
20
18
16
VDD = 2.5V
14
12
VDD = 5.5V
10
8
6
4
2
f = 1 MHz
0
Common Mode Input Voltage (V)
FIGURE 2-31:
Input Noise Voltage Density
vs. Input Common Mode Voltage with f = 1 MHz.
© 2009 Microchip Technology Inc.
DS22197A-page 13
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS
.
2.5
Time Response
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.5V
G = 1
VDD = 5.5V
G = -1
R
F = 1 kΩ
VIN
VIN
VOUT
VOUT
0.0
0.1
0.2
0.3
0.4
Time (µs)
0.5
0.6
0.7
0.8
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Time (µs)
FIGURE 2-34:
Non-inverting Small Signal
FIGURE 2-37:
Inverting Large Signal Step
Step Response.
Response.
5.5
5.0
4.5
4.0
3.5
3.0
7
6
VDD = 5.5V
G = 2
VDD = 5.5V
G = 1
VOUT
5
VIN
4
3
2.5
VIN
VOUT
2
2.0
1.5
1.0
0.5
0.0
1
0
-1
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Time (µs)
0
1
2
3
4
5
6
7
8
9
10
Time (ms)
FIGURE 2-35:
Step Response.
Non-inverting Large Signal
FIGURE 2-38:
shows no input phase reversal with overdrive.
The MCP631/2/3/5 family
24
22
Falling Edge
VIN
20
18
VDD = 5.5V
16
14
12
10
8
VDD = 5.5V
G = -1
RF = 1 kΩ
VDD = 2.5V
6
4
2
0
Rising Edge
VOUT
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
-50
-25
0
25
50
75
100
125
Time (µs)
Ambient Temperature (°C)
FIGURE 2-36:
Inverting Small Signal Step
FIGURE 2-39:
Slew Rate vs. Ambient
Response.
Temperature.
DS22197A-page 14
© 2009 Microchip Technology Inc.
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS
.
10
VDD = 5.5V
VDD = 2.5V
1
0.1
100k
1M
1.E+06
10M
1.E+07
100M
1.E+08
1.E+05
Frequency (Hz)
FIGURE 2-40:
Maximum Output Voltage
Swing vs. Frequency.
© 2009 Microchip Technology Inc.
DS22197A-page 15
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS
.
2.6
Chip Select Response
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
CS = VDD
VDD = 5.5V
VDD = 2.5V
-50
-25
0
25
50
75
100
125
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Ambient Temperature (°C)
FIGURE 2-41:
CS Current vs. Power
FIGURE 2-44:
CS Hysteresis vs. Ambient
Supply Voltage.
Temperature.
3.0
5
4
3
2
1
0
VDD = 2.5V
G = 1
VL = 0V
2.5
CS
2.0
1.5
1.0
0.5
VDD = 2.5V
VOUT
On
VDD = 5.5V
0.0
Off
Off
-0.5
-50
-25
0
25
50
75
100
125
0
2
4
6
8
10 12 14 16 18 20
Time (µs)
Ambient Temperature (°C)
FIGURE 2-42:
CS and Output Voltages vs.
FIGURE 2-45:
CS Turn On Time vs.
Time with V = 2.5V.
Ambient Temperature.
DD
6
8
VDD = 5.5V
G = 1
VL = 0V
Representative Part
CS
7
6
5
4
3
2
1
0
5
4
3
VOUT
2
On
1
0
Off
Off
-1
-50
-25
0
25
50
75
100
125
0
2
4
6
8
10 12 14 16 18 20
Time (µs)
Ambient Temperature (°C)
FIGURE 2-43:
CS and Output Voltages vs.
FIGURE 2-46:
CS’s Pull-down Resistor
Time with V = 5.5V.
(R ) vs. Ambient Temperature.
DD
PD
DS22197A-page 16
© 2009 Microchip Technology Inc.
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS
.
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
1.E-016µ
1.E10-007n
CS = VDD
CS = VDD = 5.5V
+125°C
+85°C
10n
1.E-08
-1.2
-1.4
-40°C
+25°C
1n
1.E-09
-1.6
-1.8
-2.0
-2.2
+85°C
+125°C
100p
1.E-10
+25°C
10p
1.E-11
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Voltage (V)
Power Supply Voltage (V)
FIGURE 2-47:
Quiescent Current in
FIGURE 2-48:
Output Leakage Current vs.
Shutdown vs. Power Supply Voltage.
Output Voltage.
© 2009 Microchip Technology Inc.
DS22197A-page 17
MCP631/2/3/5
NOTES:
DS22197A-page 18
© 2009 Microchip Technology Inc.
MCP631/2/3/5
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP631
PIN FUNCTION TABLE
MCP632
SOIC DFN
MCP633
MCP635
MSOP DFN
Symbol
Description
SOIC
SOIC
6
2
3
4
1
2
3
4
1
2
3
4
6
2
3
4
1
2
3
4
1
2
3
4
VOUT, VOUTA Output (op amp A)
VIN–, VINA
VIN+, VINA
VSS
–
Inverting Input (op amp A)
Non-inverting Input (op amp A)
Negative Power Supply
+
—
—
—
8
5
5
CS, CSA
CSB
Chip Select Digital Input (op amp A)
—
—
—
5
—
5
—
—
—
—
7
6
7
6
7
Chip Select Digital Input (op amp B)
Non-inverting Input (op amp B)
Inverting Input (op amp B)
Output (op amp B)
VINB
+
–
—
6
6
8
8
VINB
—
7
7
9
9
VOUTB
VDD
NC
7
8
8
10
—
—
10
—
11
Positive Power Supply
1,5,8
—
—
—
—
9
1,5
—
No Internal Connection
EP
Exposed Thermal Pad (EP);
must be connected to VSS
3.1
Analog Outputs
3.4
Chip Select Digital Input (CS)
The analog output pins (VOUT) are low-impedance
voltage sources.
This input (CS) is a CMOS, Schmitt-triggered input that
places the part into a low power mode of operation.
3.2
Analog Inputs
3.5
Exposed Thermal Pad (EP)
The non-inverting and inverting inputs (VIN+, VIN–, …)
are high-impedance CMOS inputs with low bias
currents.
There is an internal connection between the Exposed
Thermal Pad (EP) and the VSS pin; they must be
connected to the same potential on the Printed Circuit
Board (PCB).
3.3
Power Supply Pins
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (θJA).
The positive power supply (VDD) is 2.5V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
© 2009 Microchip Technology Inc.
DS22197A-page 19
MCP631/2/3/5
NOTES:
DS22197A-page 20
© 2009 Microchip Technology Inc.
MCP631/2/3/5
4.0
APPLICATIONS
VDD
The MCP631/2/3/5 family op amps is manufactured
using Microchip’s state of the art CMOS process. It is
designed for low cost, low power and high speed
applications. Its low supply voltage, low quiescent
current and wide bandwidth make the MCP631/2/3/5
ideal for battery-powered applications.
D1
R1
D2
MCP63X
V1
V2
VOUT
R2
4.1
Input
VSS – (minimum expected V1)
R1 >
R2 >
4.1.1
PHASE REVERSAL
2 mA
VSS – (minimum expected V2)
2 mA
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-38 shows an input voltage
exceeding both supplies with no phase inversion.
FIGURE 4-2:
Protecting the Analog
Inputs.
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush
current limiters; the DC current into the input pins
(VIN+ and VIN–) should be very small.
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-13. Applications that are high impedance may
need to limit the usable voltage range.
4.1.3
NORMAL OPERATION
Bond
VDD
The input stage of the MCP631/2/3/5 op amps uses a
differential PMOS input stage. It operates at
low common mode input voltages (VCM), with VCM
between VSS – 0.3V and VDD – 1.3V. To ensure proper
operation, the input offset voltage (VOS) is measured
Pad
Bond
Pad
Bond
Pad
Input
Stage
VIN+
VIN–
at both
VCM = VSS – 0.3V
and
VDD – 1.3V.
See Figure 2-5 and Figure 2-6 for temperature effects.
When operating at very low non-inverting gains, the
output voltage is limited at the top by the VCM range
(< VDD – 1.3V); see Figure 4-3.
Bond
Pad
VSS
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
VDD
MCP63X
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”). Figure 4-2 shows
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
VIN
VOUT
VSS < VIN, VOUT ≤ VDD – 1.3V
FIGURE 4-3:
Unity Gain Voltage
Limitations for Linear Operation.
© 2009 Microchip Technology Inc.
DS22197A-page 21
MCP631/2/3/5
4.2
Rail-to-Rail Output
VDD
VOUT
4.2.1
MAXIMUM OUTPUT VOLTAGE
IDD
The Maximum Output Voltage (see Figure 2-16 and
Figure 2-17) describes the output range for a given
load. For instance, the output voltage swings to within
50 mV of the negative rail with a 1 kΩ load tied to
VDD/2.
IOUT
RSER
VL
MCP63X
IL
RL
ISS
VLG
4.2.2
OUTPUT CURRENT
VSS
Figure 4-4 shows the possible combinations of output
voltage (VOUT) and output current (IOUT), when
VDD = 5.5V. IOUT is positive when it flows out of the op
amp into the external circuit.
FIGURE 4-5:
Calculations.
Diagram for Power
The instantaneous op amp power (POA(t)), RSER power
(PRSER(t)) and load power (PL(t)) are:
6.0
VOH Limited
5.5
(VDD = 5.5V)
EQUATION 4-2:
5.0
4.5
RL = 1 kΩ
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
RL = 100Ω
RL = 10Ω
POA(t) = IDD (VDD – VOUT) + ISS (VSS – VOUT
)
2
P
RSER(t) = IOUT RSER
PL(t) = IL2RL
The maximum op amp power, for resistive loads,
occurs when VOUT is halfway between VDD and VLG or
VOL Limited
halfway between VSS and VLG
:
IOUT (mA)
EQUATION 4-3:
FIGURE 4-4:
Output Current.
2
max (V – V , V – V )
DD
LG
LG
SS
4.2.3 POWER DISSIPATION
P
≤
OAmax
4(R
+ R )
L
SER
Since the output short circuit current (ISC) is specified
at ±70 mA (typical), these op amps are capable of both
delivering and dissipating significant power.
The maximum ambient to junction temperature rise
(ΔTJA) and junction temperature (TJ) can be calculated
using POAmax, ambient temperature (TA), the package
thermal resistance (θJA) found in Table 1-4, and the
number of op amps in the package (assuming equal
power dissipations):
Figure 4-5 show the quantities used in the following
power calculations for a single op amp. RSER is 0 Ω in
most applications; it can be used to limit IOUT. VOUT is
the op amp’s output voltage, VL is the voltage at the
load, and VLG is the load’s ground point. VSS is usually
ground (0V). The input currents are assumed to be
negligible. The currents shown are approximately:
EQUATION 4-4:
ΔT = P (t) θ ≤ n P
θ
JA
OA
JA
OAmax JA
EQUATION 4-1:
T = T + ΔT
J
A
JA
Where:
n
VOUT – VLG
IOUT = IL =
R
SER + RL
=
number of op amps in package (1, 2)
IDD ≈ IQ + max(0, IOUT
)
ISS ≈ –IQ + min(0, IOUT
)
Where:
IQ
=
quiescent supply current
DS22197A-page 22
© 2009 Microchip Technology Inc.
MCP631/2/3/5
The power de-rating across temperature for an op amp
in a particular package can be easily calculated
(assuming equal power dissipations):
Figure 4-7 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
EQUATION 4-5:
T
– T
A
Jmax
n θ
P
≤
OAmax
JA
1,000
Where:
TJmax
=
absolute maximum junction temperature
Several techniques are available to reduce ΔTJA for a
100
given POAmax
:
• Lower θJA
GN = +1
- Use another package
- PCB layout (ground plane, etc.)
- Heat sinks and air flow
• Reduce POAmax
GN ≥ +2
10
10p
100p
1n
1.E-09
10n
1.E-12
1.E-11
1.E-10
1.E-08
Normalized Capacitance; CL/GN (F)
FIGURE 4-7:
Recommended R
Values
- Increase RL
ISO
for Capacitive Loads.
- Limit IOUT (using RSER
- Decrease VDD
)
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP631/2/3/5 SPICE macro
model are helpful.
4.3
Improving Stability
4.3.1
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
4.3.2
GAIN PEAKING
Figure 4-8 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s common mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel.
When driving large capacitive loads with these op
amps (e.g., > 20 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-6) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
CN
RN
MCP63X
VP
VOUT
VM
RISO
CL
RG
RF
RG
RF
CG
VOUT
FIGURE 4-8:
Capacitance.
Amplifier with Parasitic
MCP63X
RN
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF.
FIGURE 4-6:
stabilizes large capacitive loads.
Output Resistor, R
ISO
© 2009 Microchip Technology Inc.
DS22197A-page 23
MCP631/2/3/5
CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2πRNCN).
4.4
MCP633 and MCP635 Chip Select
The MCP633 is a single amplifier with Chip Select
(CS). When CS is pulled high, the supply current drops
to 1 µA (typical) and flows through the CS pin to VSS
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. The CS pin has an internal 5 MΩ (typical)
pulldown resistor connected to VSS, so it will go low if
the CS pin is left floating. Figure 1-1, Figure 2-42 and
Figure 2-43 show the output voltage and supply current
response to a CS pulse.
The largest value of RF that should be used depends
on noise gain (see GN in Section 4.3.1 “Capacitive
Loads”), CG and the open-loop gain’s phase shift.
Figure 4-9 shows the maximum recommended RF for
several CG values. Some applications may modify
these values to reduce either output loading or gain
peaking (step response overshoot).
.
1.E+05
100k
CG = 10 pF
CG = 32 pF
CG = 100 pF
CG = 320 pF
CG = 1 nF
The MCP635 is a dual amplifier with two CS pins; CSA
controls op amp A and CSB controls op amp B. These
op amps are controlled independently, with an enabled
quiescent current (IQ) of 2.5 mA/amplifier (typical) and
a disabled IQ of 1 µA/amplifier (typical). The IQ seen at
the supply pins is the sum of the two op amps’ IQ; the
typical value for the MCP635’s IQ will be 2 µA, 2.5 mA
or 5 mA when there are 0, 1 or 2 amplifiers enabled,
respectively.
1.E+1004k
1k
1.E+03
GN > +1 V/V
100
1.E+02
1
10
100
Noise Gain; GN (V/V)
4.5
Power Supply
FIGURE 4-9:
R vs. Gain.
Maximum Recommended
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high frequency performance. Surface mount,
multilayer ceramic capacitors, or their equivalent,
should be used.
F
Figure 2-34 and Figure 2-35 show the small signal and
large signal step responses at G = +1 V/V. The unity
gain buffer usually has RF = 0Ω and RG open.
Figure 2-36 and Figure 2-37 show the small signal and
large signal step responses at G = -1 V/V. Since the
noise gain is 2 V/V and CG ≈ 10 pF, the resistors were
chosen to be RF = RG = 1 kΩ and RN = 500Ω.
These op amps require a bulk capacitor (i.e., 2.2 µF or
larger) within 50 mm to provide large, slow currents.
Tantalum capacitors, or their equivalent, may be a good
choice. This bulk capacitor can be shared with other
nearby analog parts as long as crosstalk through the
supplies does not prove to be a problem.
It is also possible to add a capacitor (CF) in parallel with
RF to compensate for the de-stabilizing effect of CG.
This makes it possible to use larger values of RF. The
conditions for stability are summarized in Equation 4-6.
4.6
High Speed PCB Layout
EQUATION 4-6:
These op amps are fast enough that a little extra care
in the PCB (Printed Circuit Board) layout can make a
significant difference in performance. Good PC board
layout techniques will help you achieve the
performance shown in the specifications and Typical
Performance Curves; it will also help you minimize
EMC (Electro-Magnetic Compatibility) issues.
Given:
GN1 = 1 + RF ⁄ RG
GN2 = 1 + CG ⁄ CF
fF = 1 ⁄ (2πRFCF)
fZ = fF(GN1 ⁄ GN2
We need:
)
Use a solid ground plane. Connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
fF ≤ fGBWP ⁄ (2GN2), GN1 < GN2
fF ≤ fGBWP ⁄ (4GN1), GN1 > GN2
Separate digital from analog, low speed from high
speed, and low power from high power. This will reduce
interference.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high frequency (low rise time)
signals.
DS22197A-page 24
© 2009 Microchip Technology Inc.
MCP631/2/3/5
Sometimes, it helps to place guard traces next to victim
traces. They should be on both sides of the victim
trace, and as close as possible. Connect guard traces
to ground plane at both ends, and in the middle for long
traces.
4.7.3
H-BRIDGE DRIVER
Figure 4-12 shows the MCP632 dual op amp used as
a H-bridge driver. The load could be a speaker or a DC
motor.
Use coax cables, or low inductance wiring, to route
signal and power to and from the PCB. Mutual and self
inductance of power wires is often a cause of crosstalk
and unusual behavior.
½ MCP632
VIN
VOT
RF
RF
RF
4.7
Typical Applications
RL
4.7.1
POWER DRIVER WITH HIGH GAIN
RGT
RGB
Figure 4-10 shows a power driver with high gain
(1 + R2/R1). The MCP631/2/3/5 op amp’s short circuit
current makes it possible to drive significant loads. The
calibrated input offset voltage supports accurate
response at high gains. R3 should be small, and equal
to R1||R2, in order to minimize the bias current induced
offset.
VOB
VDD/2
½ MCP632
H-Bridge Driver.
FIGURE 4-12:
This circuit automatically makes the noise gains (GN)
equal, when the gains are set properly, so that the
frequency responses match well (in magnitude and in
phase). Equation 4-7 shows how to calculate RGT and
RGB so that both op amps have the same DC gains;
GDM needs to be selected first.
R1
R3
R2
VDD/2
VOUT
RL
MCP63X
VIN
FIGURE 4-10:
Power Driver.
EQUATION 4-7:
VOT – VOB
4.7.2 OPTICAL DETECTOR AMPLIFIER
--------------------------------
≥ 1 V/V
GDM
≡
V
IN – VDD ⁄ 2
Figure 4-11 shows a transimpedance amplifier, using
the MCP63X op amp, in a photo detector circuit. The
RF
RGT = --------------------------------
photo detector is
a capacitive current source.
(GDM ⁄ 2) – 1
RF provides enough gain to produce 10 mV at VOUT
.
RF
RGB = ------------------
GDM ⁄ 2
CF stabilizes the gain and limits the transimpedance
bandwidth to about 1.1 MHz. RF’s parasitic
capacitance (e.g., 0.2 pF for a 0805 SMD) acts in
parallel with CF.
Equation 4-8 gives the resulting common mode and
differential mode output voltages.
CF
1.5 pF
EQUATION 4-8:
VOT + VOB
--------------------------- = ----------
VDD
Photo
Detector
RF
2
2
100 kΩ
VDD
⎛
⎞
⎠
VOUT
VOT – VOB = GDM VIN – ----------
⎝
2
ID
CD
100 nA
30pF
MCP63X
VDD/2
FIGURE 4-11:
Transimpedance Amplifier
for an Optical Detector.
© 2009 Microchip Technology Inc.
DS22197A-page 25
MCP631/2/3/5
NOTES:
DS22197A-page 26
© 2009 Microchip Technology Inc.
MCP631/2/3/5
5.5
Analog Demonstration and
Evaluation Boards
5.0
DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP631/2/3/5 family of op amps.
Microchip offers
a
broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help customers achieve faster time
to market. For a complete listing of these boards
and their corresponding user’s guides and technical
information, visit the Microchip web site at
www.microchip.com/analog tools.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP631/2/3/5
op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range.
See the model file for information on its capabilities.
Some boards that are especially useful are:
• MCP6XXX Amplifier Evaluation Board 1
• MCP6XXX Amplifier Evaluation Board 2
• MCP6XXX Amplifier Evaluation Board 3
• MCP6XXX Amplifier Evaluation Board 4
• Active Filter Demo Board Kit
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter
(using op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
Filter-Lab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.6
Application Notes
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
5.3
Mindi™ Circuit Designer &
Simulator
• AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams,
and simulate circuits. Circuits developed using the
Mindi Circuit Designer & Simulator can be downloaded
to a personal computer or workstation.
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
• AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
Some of these application notes, and others, are listed
in the design guide:
• “Signal Chain Design Guide”, DS21825
5.4
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit particular design
a
requirement. Available at no cost from the Microchip
website at www.microchip.com/maps, the MAPS is an
overall selection tool for Microchip’s product portfolio
that includes Analog, Memory, MCUs and DSCs. Using
this tool, a customer can define a filter to sort features
for a parametric search of devices and export
side-by-side technical comparison reports. Helpful links
are also provided for Data sheets, Purchase and
Sampling of Microchip parts.
© 2009 Microchip Technology Inc.
DS22197A-page 27
MCP631/2/3/5
NOTES:
DS22197A-page 28
© 2009 Microchip Technology Inc.
MCP631/2/3/5
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
8-Lead DFN (3×3) (MCP632)
Example
Device
Code
XXXX
YYWW
NNN
DABM
0931
256
MCP632
DABM
Note:
Applies to 8-Lead 3x3 DFN
8-Lead SOIC (150 mil) (MCP631, MCP632, MCP633)
Example:
XXXXXXXX
MCP631E
e
3
XXXXYYWW
SN 0931
NNN
256
10-Lead DFN (3×3) (MCP635)
Example
XXXX
BAFB
0931
256
Device
Code
YYWW
NNN
MCP635
BAFB
Note:
Applies to 10-Lead 3x3 DFN
10-Lead MSOP (MCP635)
Example:
XXXXXX
YWWNNN
635EUN
931256
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e
3
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
DS22197A-page 29
MCP631/2/3/5
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DS22197A-page 30
© 2009 Microchip Technology Inc.
MCP631/2/3/5
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© 2009 Microchip Technology Inc.
DS22197A-page 31
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ꢀꢁꢚꢒꢅꢘ,2
ꢚꢟ
ꢚꢁꢀꢞ
ꢚꢁ+ꢀ
.ꢟ
M
M
M
M
M
9ꢟ
ꢍ
(
ꢁ
ꢚꢁꢏ.
ꢚꢁ.ꢀ
ꢀ.ꢟ
ꢂ
.ꢟ
ꢀ.ꢟ
ꢑꢒꢊꢃꢉ%
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ
ꢏꢁ ꢝꢅꢕꢃꢐꢄꢃ$ꢃꢍꢇꢄ%ꢅ0ꢎꢇꢊꢇꢍ%ꢉꢊꢃ %ꢃꢍꢁ
+ꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄ ꢅꢓꢅꢇꢄ"ꢅ,ꢀꢅ"ꢌꢅꢄꢌ%ꢅꢃꢄꢍꢈ!"ꢉꢅ&ꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢁꢅꢖꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢅ ꢎꢇꢈꢈꢅꢄꢌ%ꢅꢉ#ꢍꢉꢉ"ꢅꢚꢁꢀ.ꢅ&&ꢅꢑꢉꢊꢅ ꢃ"ꢉꢁ
ꢒꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ
/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ
ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ
ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚ.ꢞ/
DS22197A-page 32
© 2009 Microchip Technology Inc.
MCP631/2/3/5
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ& ꢄꢈꢈꢆ'ꢎꢊꢈꢋ(ꢃꢆꢕ&ꢑꢗꢆMꢆꢑꢄ))ꢒ*ꢐꢆꢘꢛꢜꢚꢆ ꢆ!ꢒꢅ"ꢆ#&'+,$
ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ
ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ
© 2009 Microchip Technology Inc.
DS22197A-page 33
MCP631/2/3/5
-ꢚꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆMꢆꢘꢙꢘꢙꢚꢛꢜꢆ ꢆ!ꢒꢅ"ꢆ#ꢍꢏꢑ$
ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ
ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ
D
e
b
N
N
L
K
E
E2
EXPOSED
PAD
NOTE 1
NOTE 1
2
1
1
2
D2
BOTTOM VIEW
TOP VIEW
A
A1
A3
NOTE 2
4ꢄꢃ%
ꢖꢙ55ꢙꢖ,ꢗ,ꢘꢕ
ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%
ꢖꢙ6
67ꢖ
ꢀꢚ
ꢚꢁ.ꢚꢅ/ꢕ0
ꢚꢁꢛꢚ
ꢖꢔ8
6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ
ꢂꢃ%ꢍꢎ
7ꢆꢉꢊꢇꢈꢈꢅ;ꢉꢃꢐꢎ%
ꢕ%ꢇꢄ"ꢌ$$ꢅ
0ꢌꢄ%ꢇꢍ%ꢅꢗꢎꢃꢍ*ꢄꢉ
7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢐ%ꢎ
,#ꢑꢌ ꢉ"ꢅꢂꢇ"ꢅ5ꢉꢄꢐ%ꢎ
7ꢆꢉꢊꢇꢈꢈꢅ<ꢃ"%ꢎ
6
ꢉ
ꢔ
ꢔꢀ
ꢔ+
ꢓ
ꢓꢏ
,
ꢚꢁ9ꢚ
ꢚꢁꢚꢚ
ꢀꢁꢚꢚ
ꢚꢁꢚ.
ꢚꢁꢚꢏ
ꢚꢁꢏꢚꢅꢘ,2
+ꢁꢚꢚꢅ/ꢕ0
ꢏꢁ+.
+ꢁꢚꢚꢅ/ꢕ0
ꢀꢁ.9
ꢚꢁꢏ.
ꢚꢁꢒꢚ
M
ꢏꢁꢏꢚ
ꢏꢁꢒ9
,#ꢑꢌ ꢉ"ꢅꢂꢇ"ꢅ<ꢃ"%ꢎ
0ꢌꢄ%ꢇꢍ%ꢅ<ꢃ"%ꢎ
0ꢌꢄ%ꢇꢍ%ꢅ5ꢉꢄꢐ%ꢎ
0ꢌꢄ%ꢇꢍ%ꢜ%ꢌꢜ,#ꢑꢌ ꢉ"ꢅꢂꢇ"
,ꢏ
(
5
ꢀꢁꢒꢚ
ꢚꢁꢀ9
ꢚꢁ+ꢚ
ꢚꢁꢏꢚ
ꢀꢁꢞ.
ꢚꢁ+ꢚ
ꢚꢁ.ꢚ
M
>
ꢑꢒꢊꢃꢉ%
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ
ꢏꢁ ꢂꢇꢍ*ꢇꢐꢉꢅ&ꢇꢋꢅꢎꢇꢆꢉꢅꢌꢄꢉꢅꢌꢊꢅ&ꢌꢊꢉꢅꢉ#ꢑꢌ ꢉ"ꢅ%ꢃꢉꢅ(ꢇꢊ ꢅꢇ%ꢅꢉꢄ" ꢁ
+ꢁ ꢂꢇꢍ*ꢇꢐꢉꢅꢃ ꢅ ꢇ)ꢅ ꢃꢄꢐ!ꢈꢇ%ꢉ"ꢁ
ꢒꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ
/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ
ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ
ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚ:+/
DS22197A-page 34
© 2009 Microchip Technology Inc.
MCP631/2/3/5
-ꢚꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆMꢆꢘꢙꢘꢙꢚꢛꢜꢆ ꢆ!ꢒꢅ"ꢆ#ꢍꢏꢑ$
ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ
ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ
© 2009 Microchip Technology Inc.
DS22197A-page 35
MCP631/2/3/5
-ꢚꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢖꢋꢌ)ꢒꢆ& ꢄꢈꢈꢆ'ꢎꢊꢈꢋ(ꢃꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕ.ꢑꢗꢆ#ꢖ&'ꢇ$
ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ
ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ
D
N
E
E1
NOTE 1
1
2
b
e
c
A
A2
φ
L
A1
L1
4ꢄꢃ%
ꢖꢙ55ꢙꢖ,ꢗ,ꢘꢕ
ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%
ꢖꢙ6
67ꢖ
ꢖꢔ8
6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ
ꢂꢃ%ꢍꢎ
6
ꢉ
ꢀꢚ
ꢚꢁ.ꢚꢅ/ꢕ0
7ꢆꢉꢊꢇꢈꢈꢅ;ꢉꢃꢐꢎ%
ꢖꢌꢈ"ꢉ"ꢅꢂꢇꢍ*ꢇꢐꢉꢅꢗꢎꢃꢍ*ꢄꢉ
ꢕ%ꢇꢄ"ꢌ$$ꢅ
7ꢆꢉꢊꢇꢈꢈꢅ<ꢃ"%ꢎ
ꢖꢌꢈ"ꢉ"ꢅꢂꢇꢍ*ꢇꢐꢉꢅ<ꢃ"%ꢎ
7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢐ%ꢎ
2ꢌꢌ%ꢅ5ꢉꢄꢐ%ꢎ
ꢔ
M
ꢚꢁꢞ.
ꢚꢁꢚꢚ
M
ꢚꢁ9.
ꢀꢁꢀꢚ
ꢚꢁꢛ.
ꢚꢁꢀ.
ꢔꢏ
ꢔꢀ
,
,ꢀ
ꢓ
M
ꢒꢁꢛꢚꢅ/ꢕ0
+ꢁꢚꢚꢅ/ꢕ0
+ꢁꢚꢚꢅ/ꢕ0
ꢚꢁ:ꢚ
5
ꢚꢁꢒꢚ
ꢚꢁ9ꢚ
2ꢌꢌ%ꢑꢊꢃꢄ%
2ꢌꢌ%ꢅꢔꢄꢐꢈꢉ
5ꢀ
ꢀ
ꢚꢁꢛ.ꢅꢘ,2
M
ꢚꢟ
9ꢟ
5ꢉꢇ"ꢅꢗꢎꢃꢍ*ꢄꢉ
5ꢉꢇ"ꢅ<ꢃ"%ꢎ
ꢍ
(
ꢚꢁꢚ9
ꢚꢁꢀ.
M
M
ꢚꢁꢏ+
ꢚꢁ++
ꢑꢒꢊꢃꢉ%
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ
ꢏꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄ ꢅꢓꢅꢇꢄ"ꢅ,ꢀꢅ"ꢌꢅꢄꢌ%ꢅꢃꢄꢍꢈ!"ꢉꢅ&ꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢁꢅꢖꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢅ ꢎꢇꢈꢈꢅꢄꢌ%ꢅꢉ#ꢍꢉꢉ"ꢅꢚꢁꢀ.ꢅ&&ꢅꢑꢉꢊꢅ ꢃ"ꢉꢁ
+ꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ
/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ
ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ
ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚꢏꢀ/
DS22197A-page 36
© 2009 Microchip Technology Inc.
MCP631/2/3/5
APPENDIX A: REVISION HISTORY
Revision A (August 2009)
• Original Release of this Document.
© 2009 Microchip Technology Inc.
DS22197A-page 37
MCP631/2/3/5
NOTES:
DS22197A-page 38
© 2009 Microchip Technology Inc.
MCP631/2/3/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
-X
/XX
Examples:
a)
MCP631T-E/SN: Tape and Reel
Temperature
Range
Package
Extended temperature,
8LD SOIC package
a)
b)
MCP632T-E/MF: Tape and Reel
Device:
MCP631
MCP631T
Single Op Amp
Single Op Amp (Tape and Reel)
(SOIC)
Dual Op Amp
Dual Op Amp (Tape and Reel)
(DFN and SOIC)
Extended temperature,
8LD DFN package
MCP632T-E/SN: Tape and Reel
MCP632
MCP632T
Extended temperature,
8LD SOIC package
MCP633
MCP633T
Single Op Amp with CS
Single Op Amp with CS (Tape and Reel)
(SOIC)
Dual Op Amp with CS
Dual Op Amp with CS (Tape and Reel)
(DFN and MSOP)
a)
MCP633T-E/SN: Tape and Reel
Extended temperature,
8LD SOIC package
MCP635
MCP635T
a)
b)
MCP635T-E/MF: Tape and Reel
Extended temperature,
10LD DFN package
MCP635T-E/UN: Tape and Reel
Temperature Range:
Package:
E
=
=
-40°C to +125°C
Extended temperature,
10LD MSOP package
MF
Plastic Dual Flat, No Lead (3×3 DFN),
8-lead, 10-lead
SN
UN
=
=
Plastic Small Outline (3.90 mm), 8-lead
Plastic Micro Small Outline (MSOP), 10-lead
© 2009 Microchip Technology Inc.
DS22197A-page 39
MCP631/2/3/5
NOTES:
DS22197A-page 40
© 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc.
DS22197A-page 41
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
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Tel: 91-20-2566-1512
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Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
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Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
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Tel: 34-91-708-08-90
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Kokomo
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Fax: 765-864-8387
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
03/26/09
DS22197A-page 42
© 2009 Microchip Technology Inc.
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