MCP6283 [MICROCHIP]
450 UA, 5 MHz Rail-to-Rail Op Amp; 450 UA ， 5 MHz的轨至轨运算放大器
| 型号： | MCP6283 |
| 厂家： | 
MICROCHIP |
| 描述： | 450 UA, 5 MHz Rail-to-Rail Op Amp |
| 文件： | 总32页 (文件大小：563K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6281/2/3/4/5
450 µA, 5 MHz Rail-to-Rail Op Amp
Features
Description
• Gain Bandwidth Product: 5 MHz (typ.)
• Supply Current: IQ = 450 µA (typ.)
• Supply Voltage: 2.2V to 5.5V
The Microchip Technology Inc. MCP6281/2/3/4/5
family of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 5 MHz
Gain Bandwidth Product (GBWP) and a 65° phase
margin. This family also operates from a single supply
voltage as low as 2.2V, while drawing 450 µA (typ.)
quiescent current. Additionally, the MCP6281/2/3/4/5
supports rail-to-rail input and output swing, with a
common mode input voltage range of VDD + 300 mV to
• Rail-to-Rail Input/Output
• Extended Temperature Range: -40°C to +125°C
• Available in Single, Dual and Quad Packages
• Single with Chip Select (CS) (MCP6283)
• Dual with Chip Select (CS) (MCP6285)
VSS – 300 mV. This family of operational amplifiers is
designed with Microchip’s advanced CMOS process.
Applications
The MCP6285 has a Chip Select (CS) input for dual op
amps in an 8-pin package. This device is manufactured
by cascading the two op amps (the output of op amp A
connected to the non-inverting input of op amp B). The
CS input puts the device in Low-power mode.
• Automotive
• Portable Equipment
• Photodiode Amplifier
• Analog Filters
• Notebooks and PDAs
• Battery-Powered Systems
The MCP6281/2/3/4/5 family operates over the
Extended Temperature Range of -40°C to +125°C. It
also has a power supply range of 2.2V to 5.5V.
Available Tools
• SPICE Macro Model (at www.microchip.com)
• FilterLab® Software (at www.microchip.com)
Package Types
MCP6281
MCP6281
MCP6281R
MCP6282
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP
SOT-23-5
SOT-23-5
V
1
2
3
4
8
7
6
5
NC
V
OUTA
1
8
7
6
5
NC
DD
V
V
V
V
SS
1
2
3
5
4
1
OUT
5
4
DD
OUT
_
_
V
-
V
V
2
-
+
V
IN
DD
INA
OUTB
V
V
DD
2
3
+
SS
-
+
-
V
+
_
V
V
+ 3
4
IN
+
-
OUT
V
V
INA
INB
V
+
V
–
V
+
V –
IN
IN
IN
IN
V
V
NC
SS
+
SS
INB
MCP6283
PDIP, SOIC, MSOP
MCP6283
MCP6284
PDIP, SOIC, TSSOP
MCP6285
PDIP, SOIC, MSOP
SOT-23-6
NC
1
2
3
4
8 CS
V
V
14
1
OUTA
OUTD
V
/V
+
V
V
V
8
7
6
5
1
2
3
4
V
V
1
2
3
6
5
4
OUTA INB
DD
_
DD
OUT
_
_
V
V
7
-
V
IN
DD
2
+ - 13 V
- +
INA
IND
_
V
V
-
+
CS
SS
OUTB
INA
+
-
V
+
V
6
5
IN
12
V
V
+ 3
4
OUT
+
INA
_
_
IND
V
V
+
+
-
V
+
INB
IN
INA
IN
V
11
V
SS
NC
V
DD
SS
V
CS
SS
10
9
5
6
7
V
V
+
_
V
V
+
INC
INB
_
-
+ +
-
INB
INC
V
8 V
OUTB
OUTC
2004 Microchip Technology Inc.
DS21811D-page 1
MCP6281/2/3/4/5
† Notice: Stresses above those listed under “Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
V
– V ........................................................................7.0V
SS
DD
All Inputs and Outputs ................... V – 0.3V to V + 0.3V
SS
DD
Difference Input Voltage ...................................... |V – V
|
DD
SS
Output Short Circuit Current .................................Continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature.....................................-65°C to +150°C
Junction Temperature (T ) ..........................................+150°C
J
ESD Protection On All Pins (HBM;MM) ................ ≥ 4 kV;400V
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.2V to +5.5V, V = GND,
A
DD
SS
V
= V /2, R = 10 kΩ to V /2 and V
≈ V /2.
CM
DD
L
DD
OUT
DD
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset
Input Offset Voltage
V
V
-3.0
-5.0
—
—
+3.0
+5.0
mV
V
= V (Note 1)
CM SS
OS
OS
Input Offset Voltage
mV T = -40°C to +125°C,
A
(Extended Temperature)
V
= V (Note 1)
CM SS
Input Offset Temperature Drift
∆V /∆T
—
±1.7
90
—
—
µV/°C T = -40°C to +125°C,
A
OS
A
V
= V (Note 1)
CM
SS
Power Supply Rejection Ratio
PSRR
70
dB
V
= V (Note 1)
SS
CM
Input Bias, Input Offset Current and Impedance
Input Bias Current
I
I
I
—
—
—
—
—
—
±1.0
50
—
200
5
pA
pA
nA
pA
Note 2
T = +85°C (Note 2)
B
B
B
At Temperature
A
At Temperature
2
T = +125°C (Note 2)
A
Input Offset Current
I
±1.0
—
—
—
Note 3
OS
13
Common Mode Input Impedance
Differential Input Impedance
Common Mode (Note 4)
Common Mode Input Range
Common Mode Rejection Ratio
Common Mode Rejection Ratio
Open-Loop Gain
Z
10 ||6
Ω||pF Note 3
Ω||pF Note 3
CM
13
Z
10 ||3
DIFF
V
V
− 0.3
—
85
80
V
+ 0.3
DD
V
CMR
SS
CMRR
CMRR
70
—
—
dB
dB
V
V
= -0.3V to 2.5V, V = 5V
DD
CM
CM
65
90
= -0.3V to 5.3V, V = 5V
DD
DC Open-Loop Gain (Large Signal)
A
110
—
dB
V
V
= 0.2V to V – 0.2V,
OUT DD
OL
= V (Note 1)
CM
SS
Output
Maximum Output Voltage Swing
Output Short Circuit Current
Power Supply
V
, V
V
+ 15
—
V – 15
DD
mV
mA
OL
OH
SS
I
—
±25
—
SC
Supply Voltage
V
2.2
—
5.5
V
DD
Quiescent Current per Amplifier
I
300
450
570
µA
I = 0
O
Q
Note 1: The MCP6285’s V
for op amp B (pins V
/V + and V –) is V + 100 mV.
OUTA INB INB SS
CM
2: The current at the MCP6285’s V – pin is specified by I only.
INB
B
3: This specification does not apply to the MCP6285’s V
/V + pin.
OUTA INB
4: The MCP6285’s V – pin (op amp B) has a common mode range (V
) of V + 100 mV to V – 100 mV.
SS DD
INB
CMR
The MCP6285’s V
/V + pin (op amp B) has a voltage range specified by V
and V
.
OUTA INB
OH
OL
DS21811D-page 2
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.2V to +5.5V, V = GND,
A
DD
SS
V
= V /2, V
≈ V /2, R = 10 kΩ to V /2 and C = 60 pF.
CM
DD
OUT DD L DD L
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
Phase Margin at Unity-Gain
Slew Rate
GBWP
PM
—
—
—
5.0
65
—
—
—
MHz
°
SR
2.5
V/µs
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
E
—
—
—
3.5
16
3
—
—
—
µV
f = 0.1 Hz to 10 Hz
ni
P-P
e
nV/√Hz f = 1 kHz
fA/√Hz f = 1 kHz
ni
i
ni
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, V = +2.2V to +5.5V and V = GND.
DD
SS
Parameters
Temperature Ranges
Sym
Min
Typ
Max
Units
Conditions
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 6L-SOT-23
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
T
-40
-65
—
—
+125
+150
°C
°C
Note
A
T
A
θ
θ
θ
θ
θ
θ
θ
θ
—
—
—
—
—
—
—
—
256
230
85
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JA
JA
JA
163
206
70
120
100
JA
JA
Note:
The Junction Temperature (T ) must not exceed the Absolute Maximum specification of +150°C.
J
2004 Microchip Technology Inc.
DS21811D-page 3
MCP6281/2/3/4/5
MCP6283/MCP6285 CHIP SELECT (CS) SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.2V to +5.5V, V = GND,
A
DD
SS
V
= V /2, V
≈ V /2, R = 10 kΩ to V /2 and C = 60 pF.
CM
DD
OUT
DD
L
DD
L
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Low Specifications
CS Logic Threshold, Low
V
V
—
0.2 V
DD
V
IL
SS
CS Input Current, Low
I
—
0.01
—
µA
CS = V
SS
CSL
CS High Specifications
CS Logic Threshold, High
V
0.8 V
—
—
V
DD
V
IH
DD
CS Input Current, High
GND Current per Amplifier
Amplifier Output Leakage
I
0.7
2
µA
µA
µA
CS = V
CS = V
CS = V
CSH
DD
DD
DD
I
—
-0.7
0.01
—
—
SS
—
—
Dynamic Specifications (Note 1)
CS Low to Valid Amplifier
Output, Turn-on Time
t
—
4
10
µs
CS Low ≤ 0.2 V , G = +1 V/V,
DD
ON
V
V
= V /2, V
= 0.9 V /2,
IN
DD
OUT DD
= 5.0V
DD
CS High to Amplifier Output High-Z
Hysteresis
t
—
—
0.01
0.6
—
—
µs
V
CS High ≥ 0.8 V , G = +1 V/V,
DD
OFF
V
= V /2, V
= 0.1 V /2
IN
DD
OUT DD
V
V
= 5V
HYST
DD
Note 1: The input condition (V ) specified applies to both op amp A and B of the MCP6285. The dynamic specification is tested
IN
at the output of op amp B (V
).
OUTB
CS
VIL
VIH
tOFF
tON
Hi-Z
Hi-Z
VOUT
-0.7 µA (typ.)
0.7 µA (typ.)
-0.7 µA (typ.)
0.7 µA (typ.)
ISS
ICS
-450 µA (typ.)
10 nA (typ.)
FIGURE 1-1:
Timing Diagram for the
Chip Select (CS) pin on the MCP6283 and
MCP6285.
DS21811D-page 4
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
14%
12%
10%
8%
30%
25%
20%
15%
10%
5%
832 Samples
VCM = VSS
832 Samples
VCM = VSS
TA = -40°C to +125°C
6%
4%
2%
0%
0%
-10 -8
-6
-4
-2
0
2
4
6
8
10
Input Offset Voltage (mV)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage Drift.
35%
25%
210 Samples
TA = +125°C
210 Samples
TA = +85°C
30%
25%
20%
15%
10%
5%
20%
15%
10%
5%
0%
0%
0
10
20
30
40
50
60
70
80
90 100
Input Bias Current (pA)
Input Bias Current (pA)
FIGURE 2-2:
Input Bias Current at
FIGURE 2-5:
Input Bias Current at
TA = +85 °C.
TA = +125 °C.
300
300
VDD = 5.5V
VDD = 2.2V
250
200
150
100
50
250
200
150
100
50
TA = +125°C
TA = +125°C
0
0
TA
TA
TA
=
=
=
+85°C
+25°C
-40°C
TA
TA
TA
=
=
=
+85°C
+25°C
-40°C
-50
-100
-50
-100
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-3:
Input Offset Voltage vs.
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 2.2V.
Common Mode Input Voltage at VDD = 5.5V.
2004 Microchip Technology Inc.
DS21811D-page 5
MCP6281/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
300
10,000
VCM = VSS
Representative Part
VCM = VDD
VDD = 5.5V
250
200
150
100
50
1,000
100
10
Input Bias Current
Input Offset Current
0
VDD = 5.5V
VDD = 2.2V
-50
-100
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
Input Bias, Input Offset
Output Voltage.
Currents vs. Ambient Temperature.
120
110
110
PSRR-
100
CMRR
90
80
70
60
50
40
30
PSRR+
CMRR
100
90
PSRR
VCM = VSS
80
70
60
20 1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
-50
-25
0
25
50
75
100
125
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-8:
CMRR, PSRR vs.
FIGURE 2-11:
CMRR, PSRR vs. Ambient
Frequency.
Temperature.
55
45
35
25
15
5
2.5
TA = +125°C
VDD = 5.5V
2.0
1.5
Input Bias Current
Input Offset Current
Input Bias Current
Input Offset Current
1.0
0.5
0.0
-5
TA = +85°C
DD = 5.5V
-0.5
-1.0
-15
-25
V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-9:
Input Bias, Offset Currents
FIGURE 2-12:
Input Bias, Offset Currents
vs. Common Mode Input Voltage at TA = +85°C.
vs. Common Mode Input Voltage at TA = +125°C.
DS21811D-page 6
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
600
1000
500
400
100
300
TA = +125°C
200
10
1
TA = +85°C
TA = +25°C
TA = -40°C
VOL - VSS
100
0
VDD - VOH
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
0.01
0.1
1
10
Output Current Magnitude (mA)
FIGURE 2-13:
Quiescent Current vs.
FIGURE 2-16:
Output Voltage Headroom
Power Supply Voltage.
vs. Output Current Magnitude.
120
100
80
0
6
5
90
85
80
75
70
65
60
VDD = 5.5V
-30
Gain
VDD = 2.2V
-60
Gain Bandwidth Product
4
3
2
1
0
60
-90
Phase
VDD = 5.5V
40
20
0
-120
-150
-180
-210
VDD = 2.2V
Phase Margin
-20
-50
-25
0
25
50
75
100
125
0.1
1
10 100 1k 10k 100k 1M 10M 100M
Ambient Temperature (°C)
Frequency (Hz)
FIGURE 2-14:
Open-Loop Gain, Phase vs.
FIGURE 2-17:
Gain Bandwidth Product,
Frequency.
Phase Margin vs. Ambient Temperature.
10
4.5
Falling Edge, VDD = 2.2V
4.0
VDD = 5.5V
VDD = 2.2V
Falling Edge, VDD = 5.5V
3.5
3.0
2.5
2.0
1
1.5
1.0
0.5
0.0
Rising Edge, VDD = 5.5V
Rising Edge, VDD = 2.2V
0.1
-50
-25
0
25
50
75
100
125
1k
10k
100k
1M
10M
Ambient Temperature (°C)
Frequency (Hz)
FIGURE 2-15:
Maximum Output Voltage
FIGURE 2-18:
Slew Rate vs. Ambient
Swing vs. Frequency.
Temperature.
2004 Microchip Technology Inc.
DS21811D-page 7
MCP6281/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
1,000
30
25
20
15
10
5
f = 1 kHz
VDD = 5.0V
100
0
10 1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
0.1
1
10
100
1k
10k
100k
1M
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Input Voltage (V)
Frequency (Hz)
FIGURE 2-19:
Input Noise Voltage Density
FIGURE 2-22:
Input Noise Voltage Density
vs. Frequency.
vs. Common Mode Input Voltage at 1 kHz.
35
30
25
20
15
10
5
140
130
120
110
100
TA = +125°C
TA
TA
TA
=
=
=
+85°C
+25°C
-40°C
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
1
10
100
Frequency (kHz)
FIGURE 2-20:
Output Short Circuit Current
FIGURE 2-23:
Channel-to-Channel
vs. Power Supply Voltage.
Separation vs. Frequency (MCP6282 and
MCP6284 only).
1000
500
450
400
350
300
250
200
150
100
50
VDD = 5.5V
Op-Amp shuts off here
900
Op-Amp turns on here
800
Hysteresis
700
CS swept
low to high
600
500
400
300
200
100
0
Hysteresis
CS swept
high to low
CS swept
low to high
VDD = 2.2V
Op Amp toggles On/Off here
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
Chip Select Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
FIGURE 2-21:
Quiescent Current vs.
FIGURE 2-24:
Quiescent Current vs.
Chip Select (CS) Voltage at VDD = 2.2V
(MCP6283 and MCP6285 only).
Chip Select (CS) Voltage at VDD = 5.5V
(MCP6283 and MCP6285 only).
DS21811D-page 8
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0 0.E+00
G = +1V/V
G = -1V/V
VDD = 5.0V
VDD = 5.0V
2.E-06
4.E-06
6.E-06
8.E-06
1.E-05
1.E-05
1.E-05
2.E-05
2.E-05
2.E-05
0.0 0.E+0
0
2.E-06
4.E
-06
6.E-06
8.E-06
1.E-05
1.E-05
1.E-05
2.E-05
2.E-05
2.E-05
Time (2 µs/div)
Time (2 µs/div)
FIGURE 2-28:
Pulse Response.
Large-Signal, Inverting
FIGURE 2-25:
Pulse Response.
Large-Signal, Non-inverting
G = +1V/V
G = -1V/V
Time (500 ns/div)
Time (500 ns/div)
FIGURE 2-29:
Pulse Response.
Small-Signal, Inverting
FIGURE 2-26:
Pulse Response.
Small-Signal, Non-inverting
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
2.5
2.0
1.5
1.0
0.5
VDD = 5.5V
VDD = 2.2V
G = +1V/V
VIN = VSS
G = +1V/V
CS Voltage
V
IN = VSS
CS Voltage
VOUT
VOUT
Output On
Output High-Z
Output On
Output High-Z
0.0 0.E+00
5.E-06
1.E-05
2.E-05
2.E-05
3.E-05
3.E-05
4.E-05
4.E-05
5.E-05
5.E-05
0.0 0.0E+00
5.0E-06
1.0E-05
1.5E-05
2.0E-05
2.5E-05
3.0E-05
3.5E-05
4.0E-05
4.5E-05
5.0E-05
Time (5 µs/div)
Time (5 µs/div)
FIGURE 2-30:
Amplifier Output Response Time at VDD = 5.5V
(MCP6283 and MCP6285 only).
Chip Select (CS) to
FIGURE 2-27:
Amplifier Output Response Time at VDD = 2.2V
(MCP6283 and MCP6285 only).
Chip Select (CS) to
2004 Microchip Technology Inc.
DS21811D-page 9
MCP6281/2/3/4/5
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6283
MCP6281
(PDIP, SOIC,
MSOP)
MCP6281 MCP6271R
MCP6283
(PDIP, SOIC,
MSOP)
Symbol
Description
(SOT-23-5) (SOT-23-5)
(SOT-23-6)
6
2
1
4
1
4
6
2
1
4
VOUT Analog Output
VIN–
VIN+
VDD
VSS
CS
Inverting Input
3
3
3
3
3
Non-inverting Input
Positive Power Supply
Negative Power Supply
Chip Select
7
5
2
7
6
4
2
5
4
2
—
1,5,8
—
—
—
—
8
5
1,5
—
NC
No Internal Connection
TABLE 3-2:
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6282 MCP6284 MCP6285
Symbol
Description
Analog Output (op amp A)
1
2
1
2
—
2
VOUTA
VINA
–
+
Inverting Input (op amp A)
Non-inverting Input (op amp A)
Positive Power Supply
3
3
3
VINA
8
4
8
VDD
5
5
—
6
VINB
+
Non-inverting Input (op amp B)
Inverting Input (op amp B)
Analog Output (op amp B)
Analog Output (op amp C)
Inverting Input (op amp C)
Non-inverting Input (op amp C)
Negative Power Supply
6
6
VINB
–
7
7
7
VOUTB
VOUTC
—
—
—
4
8
—
—
—
4
9
VINC
–
+
10
11
12
13
14
—
—
VINC
VSS
—
—
—
—
—
—
—
—
1
VIND
+
Non-inverting Input (op amp D)
Inverting Input (op amp D)
Analog Output (op amp D)
Analog Output (op amp A)/Non-inverting Input (op amp B)
Chip Select
VIND
–
VOUTD
VOUTA/VINB
CS
+
5
3.1
Analog Outputs
3.4
CS Digital Input
The output pins are low-impedance voltage sources.
This is a CMOS, Schmitt-triggered input that places the
part into a low-power mode of operation.
3.2
Analog Inputs
3.5
Power Supply (V and V
)
DD
SS
The non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
The positive power supply (VDD) is 2.2V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
3.3
MCP6285’s V
/V + Pin
OUTA INB
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts need
to use a bulk capacitor (within 100 mm), which can be
shared with nearby analog parts.
For the MCP6285 only, the output of op amp A is
connected directly to the non-inverting input of
op amp B; this is the VOUTA/VINB+ pin. This connection
makes it possible to provide a Chip Select pin for duals
in 8-pin packages.
DS21811D-page 10
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
4.0
APPLICATION INFORMATION
The MCP6281/2/3/4/5 family of op amps is manufac-
tured using Microchip's state-of-the-art CMOS
process. This family is specifically designed for low-
cost, low-power and general purpose applications.
The low supply voltage, low quiescent current and
wide bandwidth makes the MCP6281/2/3/4/5 ideal for
battery-powered applications.
–
VOUT
RIN
MCP628X
+
VIN
(Maximum expected V ) – V
IN
---------------------------------------------------------------------------------
≥
DD
R
IN
2 mA
– (Minimum expected V
4.1
Rail-to-Rail Inputs
V
)
SS
IN
------------------------------------------------------------------------------
R
≥
The MCP6281/2/3/4/5 op amp is designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 4-1 shows the input voltage exceeding
the supply voltage without any phase reversal.
IN
2 mA
FIGURE 4-2:
Input Current Limiting
Resistor (RIN).
6
4.2
Rail-to-Rail Output
VDD = 5.0V
G = +2 V/V
5
The output voltage range of the MCP6281/2/3/4/5 op
amp is VDD – 15 mV (min.) and VSS + 15 mV (max.)
when RL = 10 kΩ is connected to VDD/2 and
4
VOUT
VIN
3
2
1
0
VDD = 5.5V. Refer to Figure 2-16 for more information.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
-1 -15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
Time (1 ms/div)
FIGURE 4-1:
No Phase Reversal.
The MCP6281/2/3/4/5 Show
The input stage of the MCP6281/2/3/4/5 op amps use
two differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM),
while the other operates at high VCM. With this
topology, the device operates with VCM up to 0.3V
above VDD and 0.3V below VSS. The Input Offset Volt-
age (VOS) is measured at VCM = VSS – 0.3V and
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will generally be lower than the bandwidth
with no capacitive load.
V
DD + 0.3V to ensure proper operation.
Input voltages that exceed the absolute maximum
voltage (VSS – 0.3V to VDD + 0.3V) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 4-2.
–
RISO
MCP628X
+
VOUT
VIN
CL
FIGURE 4-3:
Output Resistor, RISO
stabilizes large capacitive loads.
Figure 4-4 gives recommended RISO values for differ-
ent capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
2004 Microchip Technology Inc.
DS21811D-page 11
MCP6281/2/3/4/5
V
–
V
/V
+
INB
1,000
OUTA INB
1
6
2
3
7
V
V
–
INA
V
B
OUTB
100
A
+
INA
GN = 1 V/V
GN = 2 V/V
MCP6285
GN ≥ 4 V/V
10
5
10
100
1,000
10,000
CS
Normalized Load Capacitance; CL/GN (pF)
FIGURE 4-5:
Cascaded Gain Amplifier.
FIGURE 4-4:
for Capacitive Loads.
Recommended RISO Values
The output of op amp A is loaded by the input imped-
ance of op amp B, which is typically 1013Ω 6 pF, as
||
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and simula-
tions with the MCP6281/2/3/4/5 SPICE macro model
are helpful.
specified in the DC specification table (Refer to
Section 4.3 “Capacitive Loads” for further details
regarding capacitive loads).
The common mode input range of these op amps is
specified in the data sheet as VSS – 300 mV and
VDD + 300 mV. However, since the output of op amp A
is limited to VOL and VOH (20 mV from the rails with a
10 kΩ load), the non-inverting input range of op amp B
is limited to the common mode input range of
VSS + 20 mV and VDD – 20 mV.
4.4
MCP628X Chip Select (CS)
The MCP6283 and MCP6285 are single and dual op
amps with Chip Select (CS), respectively. When CS is
pulled high, the supply current drops to 0.7 µA (typ) and
flows through the CS pin to VSS. When this happens,
the amplifier output is put into a high-impedance state.
By pulling CS low, the amplifier is enabled. If the CS pin
is left floating, the amplifier may not operate properly.
Figure 1-1 shows the output voltage and supply current
response to a CS pulse.
4.6
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single-supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with other analog parts.
4.5
Cascaded Dual Op Amps
(MCP6285)
4.7
PCB Surface Leakage
The MCP6285 is a dual op amp with Chip Select (CS).
The Chip Select input is available on what would be the
non-inverting input of a standard dual op amp (pin 5).
This pin is available because the output of op amp A
connects to the non-inverting input of op amp B, as
shown in Figure 4-5. The Chip Select input, which can
be connected to a microcontroller I/O line, puts the
device in Low-power mode. Refer to Section 4.4
“MCP6283/5 Chip Select (CS)”.
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6281/2/3/4/5 family’s bias current at 25°C (1 pA,
typ.).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-6.
DS21811D-page 12
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
4.8
Application Circuits
VIN–
VIN+
VSS
4.8.1
SALLEN-KEY HIGH-PASS FILTER
The MCP6281/2/3/4/5 op amps can be used in active-
filter applications. Figure 4-7 shows a second-order
Sallen-Key high-pass filter with a gain of 1. The output
bias voltage is set by the VDD/2 reference, which can
be changed to any voltage within the output voltage
range.
Guard Ring
Example Guard Ring Layout
FIGURE 4-6:
for Inverting Gain.
R1
1. For Inverting Gain and Transimpedance
Amplifiers (convert current to voltage, such as
photo detectors):
VIN
+
C1
C2
R2
VOUT
MCP6281
–
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
VDD/2
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
FIGURE 4-7:
Sallen-Key High-Pass Filter.
This filter, and others, can be designed using
Microchip’s FilterLab® software, which is available on
our web site (www.microchip.com).
2. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
4.8.2
INVERTING MILLER INTEGRATOR
b. Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
Analog integrators are used in filters, control loops and
measurement circuits. Figure 4-8 shows the most
common implementation, the inverting Miller integrator.
The non-inverting input is at VDD/2 so that the op amp
properly biases up. The switch (SW) is used to zero the
output in some applications. Other applications use a
feedback loop to keep the output within its linear range
of operation.
SW
R
C
VOUT
VIN
+
MCP6281
VDD/2
–
VOUT
VIN
1
sRC
=
FIGURE 4-8:
Miller Integrator.
2004 Microchip Technology Inc.
DS21811D-page 13
MCP6281/2/3/4/5
4.8.3
CASCADED OP AMP
APPLICATIONS
R4
R3
R2
R1
The MCP6285 provides the flexibility of Low-power
mode for dual op amps in an 8-pin package. The
MCP6285 eliminates the added cost and space in
battery-powered applications by using two single op
amps with Chip Select lines or a 10-pin device with one
Chip Select line for both op amps. Since the two op
amps are internally cascaded, this device cannot be
used in circuits that require active or passive elements
between the two op amps. However, there are several
applications where this op amp configuration with
Chip Select line becomes suitable. The circuits below
show possible applications for this device.
VOUT
B
A
VIN
MCP6285
CS
FIGURE 4-10:
Cascaded Gain Circuit
Configuration.
4.8.3.1
Load Isolation
4.8.3.3
Difference Amplifier
With the cascaded op amp configuration, op amp B can
be used to isolate the load from op amp A. In applica-
tions where op amp A is driving capacitive or low resis-
tance loads in the feedback loop (such as an integrator
circuit or filter circuit), the op amp may not have
sufficient source current to drive the load. In this case,
op amp B can be used as a buffer.
Figure 4-11 shows op amp A configured as a difference
amplifier with Chip Select. In this configuration, it is
recommended to use well-matched resistors (e.g.,
0.1%) to increase the Common Mode Rejection Ratio
(CMRR). Op amp B can be used to provide additional
gain and isolate the load from the difference amplifier.
R4
R3
B
R2
R2
R1
A
VOUTB
Load
B
VIN2
A
VOUT
MCP6285
VIN1
MCP6285
R1
CS
FIGURE 4-9:
Buffer.
Isolating the Load with a
CS
FIGURE 4-11:
Difference Amplifier Circuit.
4.8.3.2
Cascaded Gain
Figure 4-10 shows a cascaded gain circuit configura-
tion with Chip Select. Op amps A and B are configured
in a non-inverting amplifier configuration. In this
configuration, it is important to note that the input offset
voltage of op amp A is amplified by the gain of
op amp A and B, as shown below:
VOUT = VINGAGB + VOSAGAGB + VOSBGB
Where:
GA = op amp A gain
GB = op amp B gain
VOSA = op amp A input offset voltage
VOSB = op amp B input offset voltage
Therefore, it is recommended to set most of the gain
with op amp A and use op amp B with relatively small
gain (e.g., a unity-gain buffer).
DS21811D-page 14
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
4.8.3.4
Buffered Non-inverting Integrator
4.8.3.6
Second-Order MFB Low-Pass Filter
with an Extra Pole-Zero Pair
Figure 4-12 shows a lossy non-inverting integrator that
is buffered and has a Chip Select input. Op amp A is
configured as a non-inverting integrator. In this config-
uration, matching the impedance at each input is
recommended. RF is used to provide a feedback loop
at frequencies << 1/(2πR1C1) and makes this a lossy
integrator (it has a finite gain at DC). Op amp B is used
to isolate the load from the integrator.
Figure 4-14 is a second-order multiple feedback low-
pass filter with Chip Select. Use the FilterLab® software
from Microchip to determine the R and C values for the
op amp A’s second-order filter. Op amp B can be used
to add a pole-zero pair using C3, R6 and R7.
R
C
6
3
R
1
R
C
2
C
2
1
R
7
R
R
2
3
R
V
F
IN
V
OUT
B
V
B
OUT
A
R
R
A
5
4
1
C
2
V
MCP6285
IN
R
MCP6285
C
1
CS
CS
||
R1C1 = (R2 RF)C2
FIGURE 4-14:
Second-Order Multiple
Feedback Low-Pass Filter with an Extra
Pole-Zero Pair.
FIGURE 4-12:
Buffered Non-inverting
Integrator with Chip Select.
4.8.3.7
Second-Order Sallen-Key Low-Pass
Filter with an Extra Pole-Zero Pair
4.8.3.5 Inverting Integrator with Active
Compensation and Chip Select
Figure 4-15 is a second-order Sallen-Key low-pass
filter with Chip Select. Use the FilterLab® software from
Microchip to determine the R and C values for the op
amp A’s second-order filter. Op amp B can be used to
add a pole-zero pair using C3, R5 and R6.
Figure 4-13 uses an active compensator (op amp B) to
compensate for the non-ideal op amp characteristics
introduced at higher frequencies. This circuit uses
op amp B as a unity-gain buffer to isolate the integration
capacitor C1 from op amp A and drives the capacitor
with low-impedance source. Since both op amps are
matched very well, they provide a higher quality
integrator.
C
3
R
R
R
5
2
1
R
6
V
B
OUT
R
R
3
4
A
R1
C1
V
IN
VIN
MCP6285
C
1
B
C
2
CS
VOUT
A
FIGURE 4-15:
Low-Pass Filter with an Extra Pole-Zero Pair and
Chip Select.
Second-Order Sallen-Key
MCP6285
CS
Integrator Circuit with Active
FIGURE 4-13:
Compensation.
2004 Microchip Technology Inc.
DS21811D-page 15
MCP6281/2/3/4/5
4.8.3.8
Capacitorless Second-Order
Low-Pass filter with Chip Select
5.0
DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6281/2/3/4/5 family of op amps.
The low-pass filter shown in Figure 4-16 does not
require external capacitors and uses only three exter-
nal resistors; the op amp's GBWP sets the corner
frequency. R1 and R2 are used to set the circuit gain
and R3 is used to set the Q. To avoid gain peaking in
the frequency response, Q needs to be low (lower
values need to be selected for R3). Note that the ampli-
fier bandwidth varies greatly over temperature and
process. However, this configuration provides a low-
cost solution for applications with high bandwidth
requirements.
5.1
SPICE Macro Model
The latest SPICE macro model for the
MCP6281/2/3/4/5 op amps is available on our web site
at www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. See the
macro model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
R2
R1
VIN
R3
®
5.2
FilterLab Software
A
VOUT
B
Microchip’s FilterLab software is an innovative tool that
simplifies analog active-filter (using op amps) design.
Available at no cost from our web site at
www.microchip.com, the FilterLab design tool provides
full schematic diagrams of the filter circuit with compo-
nent values. It also outputs the filter circuit in SPICE
format, which can be used with the macro model to
simulate actual filter performance.
VREF
MCP6285
CS
FIGURE 4-16:
Low-Pass Filter with Chip Select.
Capacitorless Second-Order
DS21811D-page 16
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
Example:
5-Lead SOT-23 (MCP6281 and MCP6281R)
Device
Code
MCP6281
CHNN
EUNN
XXNN
CH25
MCP6281R
Note: Applies to 5-Lead SOT-23.
Example:
6-Lead SOT-23 (MCP6283)
XXNN
CL25
8-Lead MSOP
Example:
XXXXXX
YWWNNN
6281E
437256
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
MCP6281
E/P256
YYWW
0437
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
XXXXYYWW
MCP6281
E/SN0437
NNN
256
Legend: XX...X Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
2004 Microchip Technology Inc.
DS21811D-page 17
MCP6281/2/3/4/5
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6284)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
MCP6284-E/P
0437256
YYWWNNN
14-Lead SOIC (150 mil) (MCP6284)
Example:
XXXXXXXXXX
XXXXXXXXXX
MCP6284ESL
0437256
YYWWNNN
Example:
14-Lead TSSOP (MCP6284)
XXXXXX
YYWW
6284EST
0437
NNN
256
DS21811D-page 18
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
E
E1
p
B
p1
D
n
1
α
c
A
A2
φ
A1
L
β
Units
Dimension Limits
INCHES*
NOM
5
MILLIMETERS
MIN
MAX
MIN
NOM
5
MAX
n
p
Number of Pins
Pitch
.038
0.95
p1
Outside lead pitch (basic)
Overall Height
.075
.046
.043
.003
.110
.064
.116
.018
5
1.90
1.18
1.10
0.08
2.80
1.63
2.95
0.45
5
A
A2
A1
E
.035
.035
.000
.102
.059
.110
.014
0
.057
0.90
1.45
Molded Package Thickness
Standoff
.051
.006
.118
.069
.122
.022
10
0.90
0.00
2.60
1.50
2.80
0.35
0
1.30
0.15
3.00
1.75
3.10
0.55
10
Overall Width
Molded Package Width
Overall Length
Foot Length
E1
D
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.004
.014
0
.006
.017
5
.008
.020
10
0.09
0.35
0
0.15
0.43
5
0.20
0.50
10
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
0
5
10
0
5
10
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
EIAJ Equivalent: SC-74A
Drawing No. C04-091
2004 Microchip Technology Inc.
DS21811D-page 19
MCP6281/2/3/4/5
6-Lead Plastic Small Outline Transistor (CH) (SOT-23)
E
E1
B
p1
D
n
1
α
c
A
A2
φ
A1
L
β
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
6
MAX
MIN
NOM
6
MAX
n
p
Number of Pins
Pitch
.038
0.95
1.90
p1
Outside lead pitch (basic)
Overall Height
.075
.046
.043
.003
.110
.064
.116
.018
5
A
A2
A1
E
.035
.057
0.90
0.90
1.18
1.10
0.08
2.80
1.63
2.95
0.45
5
1.45
1.30
0.15
3.00
1.75
3.10
0.55
10
Molded Package Thickness
Standoff
.035
.000
.102
.059
.110
.014
0
.051
.006
.118
.069
.122
.022
10
0.00
2.60
1.50
2.80
0.35
0
Overall Width
Molded Package Width
Overall Length
Foot Length
E1
D
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.004
.014
0
.006
.017
5
.008
.020
10
0.09
0.35
0
0.15
0.43
5
0.20
0.50
10
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
0
5
10
0
5
10
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
DS21811D-page 20
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
INCHES
NOM
MILLIMETERS*
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.026 BSC
0.65 BSC
Overall Height
A
A2
A1
E
-
-
.043
-
-
1.10
Molded Package Thickness
Standoff
.030
.000
.033
-
.037
.006
0.75
0.00
0.85
-
0.95
0.15
Overall Width
.193 TYP.
4.90 BSC
Molded Package Width
Overall Length
Foot Length
E1
D
.118 BSC
.118 BSC
3.00 BSC
3.00 BSC
L
.016
.024
.037 REF
.031
0.40
0.60
0.95 REF
0.80
Footprint (Reference)
Foot Angle
F
φ
c
0°
.003
.009
-
8°
.009
.016
15°
0°
0.08
0.22
5°
-
-
-
-
-
8°
0.23
0.40
15°
Lead Thickness
Lead Width
.006
.012
-
B
α
β
5°
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
5°
5°
5°
-
-
-
15°
5°
15°
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-187
Drawing No. C04-111
2004 Microchip Technology Inc.
DS21811D-page 21
MCP6281/2/3/4/5
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21811D-page 22
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
Overall Height
A
.053
.069
1.35
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.32
0.10
5.79
3.71
4.80
0.25
0.48
0
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
2004 Microchip Technology Inc.
DS21811D-page 23
MCP6281/2/3/4/5
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
B1
β
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
0.38
7.62
6.10
18.80
3.18
0.20
1.14
0.36
7.87
5
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
5
.145
3.68
.313
.250
.750
.130
.012
.058
.018
.370
10
.325
.260
.760
.135
.015
.070
.022
.430
15
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS21811D-page 24
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
1
B
n
α
h
45°
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
1.27
Overall Height
A
.053
.052
.004
.228
.150
.337
.010
.016
0
.069
1.35
1.32
1.55
1.42
0.18
5.99
3.90
8.69
0.38
0.84
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.061
.010
.244
.157
.347
.020
.050
8
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
§
0.10
5.79
3.81
8.56
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
2004 Microchip Technology Inc.
DS21811D-page 25
MCP6281/2/3/4/5
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
A1
A2
β
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.026
0.65
Overall Height
A
.043
1.10
0.95
0.15
6.50
4.50
5.10
0.70
8
Molded Package Thickness
Standoff
A2
A1
E
.033
.002
.246
.169
.193
.020
0
.035
.004
.251
.173
.197
.024
4
.037
.006
.256
.177
.201
.028
8
0.85
0.05
0.90
0.10
6.38
4.40
5.00
0.60
4
§
Overall Width
6.25
4.30
4.90
0.50
0
Molded Package Width
Molded Package Length
Foot Length
E1
D
L
φ
Foot Angle
c
Lead Thickness
.004
.007
0
.006
.010
5
.008
.012
10
0.09
0.19
0
0.15
0.25
5
0.20
0.30
10
Lead Width
B1
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
DS21811D-page 26
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
APPENDIX A: REVISION HISTORY
Revision A (June 2003)
Original data sheet release.
Revision B (October 2003)
Revision C (June 2004)
Revision D (December 2004)
The following is the list of modifications:
1. Added SOT-23-5 packages for the MCP6281
and MCP6281R single op amps.
2. Added SOT-23-6 package for the MCP6283
single op amp.
3. Added Section 3.0 “Pin Descriptions”.
4. Corrected application circuits
(Section 4.8 “Application Circuits”).
5. Added SOT-23-5 and SOT-23-6 packages and
corrected
package
marking
information
(Section 6.0 “Packaging Information”).
6. Added Appendix A: Revision History.
2004 Microchip Technology Inc.
DS21811D-page 27
MCP6281/2/3/4/5
NOTES:
DS21811D-page 28
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
/XX
–
a)
b)
c)
d)
MCP6281-E/SN:
Extended Temperature,
8LD SOIC package.
Temperature
Range
Package
MCP6281-E/MS: Extended Temperature,
8LD MSOP package.
MCP6281-E/P:
Extended Temperature,
8LD PDIP package.
Device:
MCP6281:
MCP6281T:
Single Op Amp
Single Op Amp
(Tape and Reel)
(SOIC, MSOP, SOT-23-5)
Single Op Amp
(Tape and Reel) (SOT-23-5)
Dual Op Amp
Dual Op Amp
(Tape and Reel) (SOIC, MSOP)
Single Op Amp with Chip Select
Single Op Amp with Chip Select
(Tape and Reel)
(SOIC, MSOP, SOT-23-6)
Quad Op Amp
MCP6281T-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
MCP6281RT:
a)
b)
c)
d)
MCP6282-E/SN:
Extended Temperature,
8LD SOIC package.
MCP6282:
MCP6282T:
MCP6282-E/MS: Extended Temperature,
8LD MSOP package.
MCP6282-E/P:
Extended Temperature,
8LD PDIP package.
MCP6283:
MCP6283T:
MCP6282T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
MCP6284:
MCP6284T:
a)
b)
c)
d)
MCP6283-E/SN:
Extended Temperature,
8LD SOIC package.
Quad Op Amp
(Tape and Reel) (SOIC, TSSOP)
Dual Op Amp with Chip Select
Dual Op Amp with Chip Select
(Tape and Reel) (SOIC, MSOP)
MCP6283-E/MS: Extended Temperature,
8LD MSOP package.
MCP6283-E/P:
MCP6285:
MCP6285T:
Extended Temperature,
8LD PDIP package.
MCP6283T-E/CH: Tape and Reel,
Extended Temperature,
Temperature Range:
Package:
E
=
-40°C to +125°C
6LD SOT-23 package.
a)
b)
MCP6284-E/P:
Extended Temperature,
14LD PDIP package.
OT
CH
=
=
Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6281, MCP6281R only)
Plastic Small Outline Transistor (SOT-23), 6-lead
(MCP6283 only)
MCP6284T-E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC package.
Extended Temperature,
14LD SOIC package.
Extended Temperature,
14LD TSSOP package.
MS
P
SN
SL
ST
=
=
=
=
=
Plastic MSOP, 8-lead
c)
d)
MCP6284-E/SL:
MCP6284-E/ST:
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC, (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead
Plastic TSSOP (4.4mm Body), 14-lead
a)
b)
c)
d)
MCP6285-E/SN:
Extended Temperature,
8LD SOIC package.
MCP6285-E/MS: Extended Temperature,
8LD MSOP package.
MCP6285-E/P:
Extended Temperature,
8LD PDIP package.
MCP6285T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com) to receive the most current information on our products.
2004 Microchip Technology Inc.
DS21811D-page 29
MCP6281/2/3/4/5
NOTES:
DS21811D-page 30
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS21811D-page 31
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
Austria - Weis
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
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10/20/04
DS21811D-page 32
2004 Microchip Technology Inc.
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