MCP6241-E/ST [MICROCHIP]
50 μA, 550 kHz Rail-to-Rail Op Amp; 50 μA ， 550 kHz的轨至轨运算放大器
| 型号： | MCP6241-E/ST |
| 厂家： | 
MICROCHIP |
| 描述： | 50 μA, 550 kHz Rail-to-Rail Op Amp |
| 文件： | 总38页 (文件大小：666K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6241/1R/1U/2/4
50 µA, 550 kHz Rail-to-Rail Op Amp
Description
Features
• Gain Bandwidth Product: 550 kHz (typical)
• Supply Current: IQ = 50 µA (typical)
• Supply Voltage: 1.8V to 5.5V
The Microchip Technology Inc. MCP6241/1R/1U/2/4
operational amplifiers (op amps) provide wide
bandwidth for the quiescent current. The MCP6241/1R/
1U/2/4 has a 550 kHz gain bandwidth product and 68°
(typical) phase margin. This family operates from a
single supply voltage as low as 1.8V, while drawing
50 µA (typical) quiescent current. In addition, the
MCP6241/1R/1U/2/4 family supports rail-to-rail input
and output swing, with a common mode input voltage
range of VDD + 300 mV to VSS – 300 mV. These op
amps are designed in one of Microchip’s advanced
CMOS processes.
• Rail-to-Rail Input/Output
• Extended Temperature Range: -40°C to +125°C
• Available in 5-pin SC-70 and SOT-23 packages
Applications
• Automotive
• Portable Equipment
• Photodiode (Transimpedance) Amplifier
• Analog Filters
Package Types
MCP6241
MCP6241
PDIP, SOIC, MSOP
• Notebooks and PDAs
• Battery-Powered Systems
SOT-23-5
1
2
3
4
8
7
6
5
NC
NC
V
V
V
1
2
3
5
4
DD
OUT
Design Aids
V
–
+
–
+
DD
IN
V
SS
+
–
V
V
OUT
IN
• SPICE Macro Models
V
V
–
IN
IN
V
NC
SS
• Mindi™ Circuit Designer & Simulator
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
MCP6241R
MCP6242
PDIP, SOIC, MSOP
SOT-23-5
VOUTA
V
V
VDD
1
5
4
1
2
8
7
6
5
SS
OUT
_
V
2
3
VINA
DD
-
VOUTB
+
–
Typical Application
_
V
+
V –
IN
VINA+ 3
VSS
IN
+
-
VINB
4
VINB
+
RG2
VIN2
VIN1
RG1
MCP6241U
SC-70-5, SOT-23-5
MCP6244
PDIP, SOIC, TSSOP
RF
V
V
+
VOUTA
14 VOUTD
1
2
3
4
1
2
3
5
DD
IN
VDD
+
–
V
- + + 13 VIND
-
–
+
VINA
–
+
SS
–
–
RX
RY
VOUT
MCP6241
+
VINA
12 VIND
V
V
OUT
4
IN
VDD
V
SS
11
RZ
MCP6241
2x3 DFN*
VINB
+
–
10 VINC
-
9 VINC
+
–
5
6
7
- +
+
VINB
VOUTB
8 VOUTC
NC
NC
1
8
VIN
VIN
VSS
–
VDD
2
7
6
5
EP
9
Summing Amplifier Circuit
+
VOUT
NC
3
4
* Includes Exposed Thermal Pad (EP); see Table 3-1.
© 2008 Microchip Technology Inc.
DS21882D-page 1
MCP6241/1R/1U/2/4
NOTES:
DS21882D-page 2
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
Current at Analog Input Pins (VIN+, VIN–).....................±2 mA
Analog Inputs (VIN+, VIN–) ††........ VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Difference Input Voltage ...................................... |VDD – VSS
|
Output Short Circuit Current ................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ..................................–65° C to +150°C
Maximum Junction Temperature (TJ)..........................+150°C
ESD Protection On All Pins (HBM; MM) .............. ≥ 4 kV; 300V
DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND,
VCM = VDD/2, RL = 100 kΩ to VDD/2 and VOUT ≈ VDD/2.
Parameters
Input Offset
Sym
Min
Typ
Max
Units
Conditions
Input Offset Voltage
VOS
VOS
-5.0
-7.0
—
—
+5.0
+7.0
mV VCM = VSS
Extended Temperature
mV TA= -40°C to +125°C,
VCM = VSS (Note 1)
Input Offset Drift with
Temperature
ΔVOS/ΔTA
—
—
±3.0
83
—
—
µV/°C TA= -40°C to +125°C,
VCM = VSS
Power Supply Rejection
PSRR
dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current:
IB
IB
—
—
—
—
—
—
±1.0
20
—
—
—
—
—
—
pA
At Temperature
pA TA = +85°C
At Temperature
IB
1100
pA TA = +125°C
Input Offset Current
IOS
ZCM
ZDIFF
±1.0
pA
Common Mode Input Impedance
Differential Input Impedance
Common Mode
1013||6
1013||3
Ω||pF
Ω||pF
Common Mode Input Range
Common Mode Rejection Ratio
Open-Loop Gain
VCMR
VSS – 0.3
60
—
VDD + 0.3
—
V
CMRR
75
dB
VCM = -0.3V to 5.3V, VDD = 5V
DC Open-Loop Gain
(large signal)
AOL
90
110
—
—
dB VOUT = 0.3V to VDD – 0.3V,
VCM = VSS
Output
Maximum Output Voltage Swing
V
OL, VOH VSS + 35
VDD – 35 mV RL = 10 kΩ, 0.5V Input
Overdrive
Output Short-Circuit Current
ISC
ISC
—
—
±6
—
—
mA VDD = 1.8V
mA VDD = 5.5V
±23
Power Supply
Supply Voltage
VDD
IQ
1.8
30
—
5.5
70
V
Quiescent Current per Amplifier
50
µA IO = 0, VCM = VDD – 0.5V
Note 1: The SC-70 package is only tested at +25°C.
© 2008 Microchip Technology Inc.
DS21882D-page 3
MCP6241/1R/1U/2/4
AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
Phase Margin
GBWP
PM
—
—
—
550
68
—
—
—
kHz
°
G = +1 V/V
Slew Rate
SR
0.30
V/µs
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Eni
eni
ini
—
—
—
10
45
—
—
—
µVP-P f = 0.1 Hz to 10 Hz
nV/√Hz f = 1 kHz
0.6
fA/√Hz f = 1 kHz
TEMPERATURE CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.
Parameters
Temperature Ranges
Sym
Min
Typ
Max
Units
Conditions
Extended Temperature Range
Operating Temperature Range
Storage Temperature Range
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
(Note)
Thermal Package Resistances
Thermal Resistance, 5L-SC70
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 8L-DFN (2x3)
Thermal Resistance, 8L-MSOP
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
θJA
θJA
θJA
θJA
θJA
θJA
θJA
θJA
θJA
331
256
84.5
206
85
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
163
70
120
100
Note:
The internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
1.1
Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-1 and Figure 1-2. The bypass
capacitors are laid out according to the rules discussed
in Section 4.6 “PCB Surface Leakage”.
VDD
1 µF
0.1 µF
VDD/2
VOUT
RL
RN
RG
MCP624X
VDD
1 µF
CL
0.1 µF
VIN
RF
VIN
VOUT
RL
RN
RG
VL
MCP624X
CL
FIGURE 1-2:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
RF
VDD/2
VL
FIGURE 1-1:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
DS21882D-page 4
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
20%
18%
16%
14%
12%
10%
8%
90
85
80
75
70
630 Samples
VCM = VSS
PSRR (VCM = VSS
)
6%
4%
CMRR (VCM = -0.3V to +5.3V,
2%
V
DD = 5.0V)
0%
-50
-25
0
25
50
75
100
125
Input Offset Voltage (mV)
Ambient Temperature (°C)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
CMRR, PSRR vs. Ambient
Temperature.
110
100
90
120
100
80
0
RL = 10.0 kΩ
-30
VCM = VDD/2
PSRR-
Gain
-60
CMRR
80
60
-90
70
PSRR+
Phase
60
40
20
0
-120
-150
-180
-210
50
40
30
-20
20
0.1
1
10 100 1k 10k 100k 1M 10M
10
100
1.E+02
1k
10k
1.E+04
100k
1.E+05
1.E- 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+
1.E+01
1.E+03
Frequency (Hz)
Frequency (Hz)
01 00 01 02 03 04 05 06 07
FIGURE 2-2:
PSRR, CMRR vs.
FIGURE 2-5:
Open-Loop Gain, Phase vs.
Frequency.
Frequency.
25%
30%
180 Samples
VCM = VDD/2
180 Samples
VCM = VDD/2
TA = +125°C
25%
20%
15%
10%
5%
20%
15%
10%
5%
TA = +85°C
0%
0%
Input Bias Current (pA)
Input Bias Current (nA)
FIGURE 2-3:
Input Bias Current at +85°C.
FIGURE 2-6:
Input Bias Current at
+125°C.
© 2008 Microchip Technology Inc.
DS21882D-page 5
MCP6241/1R/1U/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
10,000
20%
628 Samples
18%
VCM = VSS
16%
14%
TA = -40°C to +125°C
1,000
12%
10%
8%
6%
4%
2%
0%
100
10
0.1
1
10
100
1k
10k 100k
1.E-01 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0
Frequency (Hz)
Input Offset Voltage Drift (µV/°C)
0
1
2
3
4
5
FIGURE 2-7:
Input Noise Voltage Density
FIGURE 2-10:
Input Offset Voltage Drift.
vs. Frequency.
700
650
600
550
500
450
300
200
100
0
VCM = VSS
VDD = 1.8V
VDD = 5.5V
TA = -40°C
TA = +25°C
-100
-200
-300
VDD = 1.8V
400
350
300
TA = +85°C
TA = +125°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-11:
Input Offset Voltage vs.
FIGURE 2-8:
Input Offset Voltage vs.
Output Voltage.
Common Mode Input Voltage at V = 1.8V.
DD
35
30
25
20
15
10
5
400
+ISC
VDD = 5.5V
300
200
TA = +125°C
T
A = +85°C
TA = +25°C
A = -40°C
0
100
-5
TA = -40°C
-10
-15
-20
-25
-30
-35
T
0
TA = +25°C
TA = +85°C
-100
TA = +125°C
-200
-ISC
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-12:
Output Short-Circuit Current
FIGURE 2-9:
Input Offset Voltage vs.
vs. Ambient Temperature.
Common Mode Input Voltage at V = 5.5V.
DD
DS21882D-page 6
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
0.50
G = +1 V/V
VDD = 5.5V
RL = 10 kΩ
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
Falling Edge
VDD = 1.8V
Rising Edge
-50
-25
0
25
50
75
100 125
Time (1 µs/div)
Ambient Temperature (°C)
FIGURE 2-13:
Slew Rate vs. Ambient
FIGURE 2-16:
Small-Signal, Non-Inverting
Temperature.
Pulse Response.
1,000
100
10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.0V
G = +1 V/V
VDD – VOH
VOL – VSS
1
10µ
100µ
1.E-01
1m
1.E+00
10m
1.E+01
1.E-02
Time (10 µs/div)
Output Current Magnitude (A)
FIGURE 2-14:
Output Voltage Headroom
FIGURE 2-17:
Large-Signal, Non-Inverting
vs. Output Current Magnitude.
Pulse Response.
80
10
VCM = 0.9VDD
70
60
50
40
30
20
10
0
VDD = 5.5V
VDD = 1.8V
1
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
1k
10k
1.E+04
Frequency (Hz)
100k
1M
1.E+06
1.E+03
1.E+05
FIGURE 2-15:
Maximum Output Voltage
FIGURE 2-18:
Quiescent Current vs.
Swing vs. Frequency.
Power Supply Voltage.
© 2008 Microchip Technology Inc.
DS21882D-page 7
MCP6241/1R/1U/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
1.E-02
10m
1.E-03
1m
1.E- 4
100µ
1.E1-05µ
1.E-016µ
100n
1.E- 7
10n
1.E- 8
1n
1.E-09
100p
1.E-10
10p
1.E-11
+125°C
+85°C
+25°C
-40°C
1p
1.E-12
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-19:
Measured Input Current vs.
Input Voltage (below V ).
SS
DS21882D-page 8
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6241
MCP6241R
MCP6241U
Symbol
Description
MSOP, PDIP,
SOIC
SOT-23-5,
SC-70
DFN
SOT-23-5
SOT-23-5
6
6
1
4
1
4
4
3
VOUT
VIN–
VIN+
VDD
VSS
NC
Analog Output
2
2
Inverting Input
3
3
7
3
3
1
Non-inverting Input
7
5
2
5
Positive Power Supply
Negative Power Supply
No Internal Connection
Exposed Thermal Pad (EP);
4
1, 5, 8
9
4
2
5
2
1, 5, 8
—
—
—
—
—
—
—
EP
must be connected to VSS
.
TABLE 3-2:
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6242
MCP6244
Symbol
Description
MSOP, PDIP, SOIC PDIP, SOIC, TSSOP
1
2
1
2
VOUTA
Analog Output (op amp A)
VINA
–
+
Inverting Input (op amp A)
Non-inverting Input (op amp A)
Positive Power Supply
3
3
VINA
8
4
VDD
5
5
VINB
+
Non-inverting Input (op amp B)
Inverting Input (op amp B)
Analog Output (op amp B)
Analog Output (op amp C)
Inverting Input (op amp C)
Non-inverting Input (op amp C)
Negative Power Supply
6
6
VINB
–
7
7
VOUTB
VOUTC
—
—
—
4
8
9
VINC
–
+
10
11
12
13
14
VINC
VSS
—
—
—
VIND
+
Non-inverting Input (op amp D)
Inverting Input (op amp D)
Analog Output (op amp D)
VIND
–
VOUTD
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
3.1
Analog Outputs
The output pins are low-impedance voltage sources.
3.2
Analog Inputs
3.4
Exposed Thermal Pad (EP)
The non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
3.3
Power Supply (VSS and VDD)
The positive power supply (VDD) is 1.8V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
© 2008 Microchip Technology Inc.
DS21882D-page 9
MCP6241/1R/1U/2/4
NOTES:
DS21882D-page 10
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
4.0
APPLICATION INFORMATION
Bond
VDD
The MCP6241/1R/1U/2/4 family of op amps is manu-
factured using Microchip’s state-of-the-art CMOS
process and is specifically designed for low-power and
general-purpose applications. The low supply voltage,
low quiescent current and wide bandwidth makes the
MCP6241/1R/1U/2/4 ideal for battery-powered
applications.
Pad
Bond
Pad
Bond
Pad
Input
Stage
VIN+
VIN–
4.1
Rail-to-Rail Inputs
Bond
Pad
VSS
4.1.1
PHASE REVERSAL
The MCP6241/1R/1U/2/4 op amp is designed to
prevent phase reversal when the input pins exceed the
supply voltages. Figure 4-1 shows the input voltage
exceeding the supply voltage without any phase
reversal.
FIGURE 4-2:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
6
VDD = 5.0V
G = +2 V/V
VOUT
5
4
VIN
3
2
1
0
-1
Time (1 ms/div)
VDD
FIGURE 4-1:
The MCP6241/1R/1U/2/4
Show No Phase Reversal.
D1 D2
4.1.2 INPUT VOLTAGE AND CURRENT
V1
LIMITS
R1
MCP624X
The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
V2
R2
R3
VSS – (minimum expected V1)
R1 >
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
FIGURE 4-3:
Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, current through the
diodes D1 and D2 needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
© 2008 Microchip Technology Inc.
DS21882D-page 11
MCP6241/1R/1U/2/4
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-19. Applications that are
high impedance may need to limit the useable voltage
range.
1.E+04
10k
1.E+03
1k
4.1.3
NORMAL OPERATION
The input stage of the MCP6241/1R/1U/2/4 op amps
use two differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM),
while the other operates at high VCM. WIth this topol-
ogy, the device operates with VCM up to 0.3V above
GN = +1 V/V
≥
GN +2 V/V
1.E+10020
10p
100p
1.E+02
1n
10n
1.E+01
1.E+03
1.E+04
Normalized Load Capacitance; CL/GN (F)
VDD and 0.3V below VSS
.
FIGURE 4-5:
for Capacitive Loads.
Recommended R
Values
ISO
4.2
Rail-to-Rail Output
The output voltage range of the MCP6241/1R/1U/2/4
op amps is VDD – 35 mV (maximum) and VSS + 35 mV
(minimum) when RL = 10 kΩ is connected to VDD/2 and
VDD = 5.5V. Refer to Figure 2-14 for more information.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Evaluation on the bench and
simulations with the MCP6241/1R/1U/2/4 SPICE
macro model are very helpful. Modify RISO’s value until
the response is reasonable.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage-feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, but all gains show the
same general behavior.
4.4
Supply Bypass
With this op amp, the power supply pin (VDD for
single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-
frequency performance. It can use a bulk capacitor
(i.e., 1 µF or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
other nearby analog parts.
When driving large capacitive loads with these op
amps (e.g., > 70 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
4.5
Unused Op Amps
An unused op amp in a quad package (MCP6244)
should be configured as shown in Figure 4-6. Both
circuits prevent the output from toggling and causing
crosstalk. Circuit A can use any reference voltage
between the supplies, provides a buffered DC voltage,
and minimizes the supply current draw of the unused
op amp. Circuit
B
minimizes the number of
–
components, but may draw a little more supply current
for the unused op amp.
RISO
VOUT
MCP624X
+
VIN
CL
¼ MCP6244 (A)
VDD
¼ MCP6244 (B)
VDD
FIGURE 4-4:
stabilizes large capacitive loads.
Output Resistor, R
ISO
VDD
R1
R2
Figure 4-5 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
signal gain are equal. For inverting gains, GN is
1 + |Signal Gain| (e.g., –1 V/V gives GN = +2 V/V).
VREF
R2
------------------
⋅
VREF = VDD
R1 + R2
FIGURE 4-6:
Unused Op Amps.
DS21882D-page 12
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
4.6
PCB Surface Leakage
4.7
Application Circuits
In applications where low input bias current is critical,
PCB (printed circuit board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6241/1R/1U/2/4 family’s bias current at 25°C
(1 pA, typical).
4.7.1
MATCHING THE IMPEDANCE AT
THE INPUTS
To minimize the effect of offset voltage in an amplifier
circuit, the impedances at the inverting and non-
inverting inputs need to be matched. This is done by
choosing the circuit resistor values so that the total
resistance at each input is the same. Figure 4-8 shows
a summing amplifier circuit.
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
RG2
VIN2
VIN1
RG1
RF
VDD
VIN-
VIN+
–
VSS
RX
RY
VOUT
MCP6241
+
RZ
FIGURE 4-8:
Summing Amplifier Circuit.
Guard Ring
Example Guard Ring Layout
To match the inputs, set all voltage sources to ground
and calculate the total resistance at the input nodes. In
this summing amplifier circuit, the resistance at the
inverting input is calculated by setting VIN1, VIN2 and
VOUT to ground. In this case, RG1, RG2 and RF are in
parallel. The total resistance at the inverting input is:
FIGURE 4-7:
for Inverting Gain.
1. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
1
RVIN – = ---------------------------------------------
1
1
1
b. Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
⎛
⎝
⎞
⎠
--------- + --------- + ------
RG1 RG2 RF
Where:
2. Inverting Gain and Transimpedance Amplifiers
(convert current to voltage, such as photo
detectors):
–
RVIN = total resistance at the inverting input
At the non-inverting input, VDD is the only voltage
source. When VDD is set to ground, both RX and RY are
in parallel. The total resistance at the non-inverting
input is:
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
1
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
RVIN = ------------------------- + RZ
+
1
1
⎛
⎝
⎞
⎠
------ + -----
RX RY
Where:
+
RVIN = total resistance at the inverting
input
To minimize offset voltage and increase circuit
accuracy, the resistor values need to meet the
condition:
RVIN = RVIN
–
+
© 2008 Microchip Technology Inc.
DS21882D-page 13
MCP6241/1R/1U/2/4
4.7.2
COMPENSATING FOR THE
PARASITIC CAPACITANCE
In analog circuit design, the PCB parasitic capacitance
can compromise the circuit behavior; Figure 4-9 shows
a typical scenario. If the input of an amplifier sees
parasitic capacitance of several picofarad (CPARA
,
which includes the common mode capacitance of 6 pF,
typical) and large RF and RG,the frequency response
of the circuit will include a zero. This parasitic zero
introduces gain peaking and can cause circuit
instability.
VAC
+
VOUT
MCP624X
–
RG
RF
VDC
CPARA
CF
RG
------
RF
CF = CPARA
•
FIGURE 4-9:
Effect of Parasitic
Capacitance at the Input.
One solution is to use smaller resistor values to push
the zero to a higher frequency. Another solution is to
compensate by introducing a pole at the point at which
the zero occurs. This can be done by adding CF in
parallel with the feedback resistor (RF). CF needs to be
selected so that the ratio CPARA:CF is equal to the ratio
of RF:RG.
DS21882D-page 14
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
5.4
Analog Demonstration and
Evaluation Boards
5.0
DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6241/1R/1U/2/4 family of op amps.
Microchip offers a broad spectrum of Analog Demon-
stration and Evaluation Boards that are designed to
help you achieve faster time to market. For a complete
listing of these boards and their corresponding user’s
guides and technical information, visit the Microchip
web site at www.microchip.com/analogtools.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6241/1R/
1U/2/4 op amps is available on the Microchip web site
at www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Two of our boards that are especially useful are:
• P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board
• P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP
Evaluation Board
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.5
Application Notes
The following Microchip Application Notes are avail-
able on the Microchip web site at www.microchip. com/
appnotes and are recommended as supplemental ref-
erence resources.
5.2
Mindi™ Circuit Designer &
Simulator
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power-management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams, simu-
late circuits. Circuits developed using the Mindi Circuit
Designer & Simulator can be downloaded to a personal
computer or workstation.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
5.3
Microchip Advanced Part Selector
(MAPS)
These application notes and others are listed in the
design guide:
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data sheets,
Purchase, and Sampling of Microchip parts.
“Signal Chain Design Guide”, DS21825
© 2008 Microchip Technology Inc.
DS21882D-page 15
MCP6241/1R/1U/2/4
NOTES:
DS21882D-page 16
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SC-70 (MCP6241U Only)
Example:
AT25
XXNN
Example:
5-Lead SOT-23 (MCP6241, MCP6241R, MCP6241U)
5
4
5
4
3
Device
MCP6241
Code
BQNN
BRNN
BSNN
BQ25
XXNN
MCP6241R
MCP6241U
1
2
3
1
2
Note:
Applies to 5-Lead SOT-23.
Example:
8-Lead DFN (2x3) (MCP6241 Only)
XXX
YWW
NN
AER
834
25
Example:
8-Lead MSOP
XXXXXX
6242E
834256
YWWNNN
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
MCP6242
3
MCP6242
e
E/P 256
0834
E/P256
OR
YYWW
0818
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2008 Microchip Technology Inc.
DS21882D-page 17
MCP6241/1R/1U/2/4
Package Marking Information (Continued)
8-Lead SOIC (150 mil)
Example:
MCP6242
XXXXXXXX
MCP6242E
E/SN0818
XXXXYYWW
SN^
e
3
0834
OR
256
NNN
256
14-Lead PDIP (300 mil) (MCP6244)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
MCP6244
e
3
E/P^
YYWWNNN
0546256
14-Lead SOIC (150 mil) (MCP6244)
Example:
MCP6244
XXXXXXXXXX
XXXXXXXXXX
e
3
E/SL^
YYWWNNN
0546256
Example:
14-Lead TSSOP (MCP6244)
6244E
0546
XXXXXXXX
YYWW
256
NNN
DS21882D-page 18
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢓꢄꢑꢉꢋꢉꢊꢔꢓꢆꢕꢂꢒꢖꢆꢗꢍꢘꢙꢚꢛ
ꢜꢔꢊꢃꢝ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
D
b
1
3
2
E1
E
4
5
e
e
A
A2
c
A1
L
.ꢆꢃꢍꢇ
ꢕ/00/ꢕꢌ%ꢌ1ꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
2
ꢅ
!
ꢗꢁ6!ꢉ"ꢜ#
3'ꢅꢓꢊꢏꢏꢉ7ꢅꢃꢚꢒꢍ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
ꢜꢍꢊꢆꢋꢈꢑꢑ
ꢛ
ꢗꢁ8ꢗ
ꢗꢁ8ꢗ
ꢗꢁꢗꢗ
ꢀꢁ8ꢗ
ꢀꢁꢀ!
ꢀꢁ8ꢗ
ꢗꢁꢀꢗ
ꢗꢁꢗ8
ꢗꢁꢀ!
M
M
M
ꢘꢁꢀꢗ
ꢀꢁꢘ!
ꢘꢁꢗꢗ
ꢗꢁꢘꢗ
M
ꢀꢁꢀꢗ
ꢀꢁꢗꢗ
ꢗꢁꢀꢗ
ꢘꢁ ꢗ
ꢀꢁ;!
ꢘꢁꢘ!
ꢗꢁ 6
ꢗꢁꢘ6
ꢗꢁ ꢗ
ꢛꢘ
ꢛꢀ
ꢌ
ꢌꢀ
ꢂ
0
ꢎ
5
3'ꢅꢓꢊꢏꢏꢉ:ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ:ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
)ꢈꢈꢍꢉ0ꢅꢆꢚꢍꢒ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
0ꢅꢊꢋꢉ:ꢃꢋꢍꢒ
M
ꢜꢔꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀꢘꢙꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
ꢘꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ "ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ <ꢗ6ꢀ"
© 2008 Microchip Technology Inc.
DS21882D-page 19
MCP6241/1R/1U/2/4
ꢜꢔꢊꢃꢝ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
DS21882D-page 20
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢓꢄꢑꢉꢋꢉꢊꢔꢓꢆꢕꢏꢒꢖꢆꢗꢍꢏꢒꢁ !ꢛ
ꢜꢔꢊꢃꢝ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
b
N
E
E1
3
2
1
e
e1
D
A2
c
A
φ
A1
L
L1
.ꢆꢃꢍꢇ
ꢕ/00/ꢕꢌ%ꢌ1ꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
0ꢅꢊꢋꢉ,ꢃꢍꢎꢒ
2
ꢅ
!
ꢗꢁ=!ꢉ"ꢜ#
3ꢐꢍꢇꢃꢋꢅꢉ0ꢅꢊꢋꢉ,ꢃꢍꢎꢒ
3'ꢅꢓꢊꢏꢏꢉ7ꢅꢃꢚꢒꢍ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
ꢜꢍꢊꢆꢋꢈꢑꢑ
3'ꢅꢓꢊꢏꢏꢉ:ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ:ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
)ꢈꢈꢍꢉ0ꢅꢆꢚꢍꢒ
)ꢈꢈꢍꢔꢓꢃꢆꢍ
)ꢈꢈꢍꢉꢛꢆꢚꢏꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
0ꢅꢊꢋꢉ:ꢃꢋꢍꢒ
ꢅꢀ
ꢛ
ꢛꢘ
ꢛꢀ
ꢌ
ꢌꢀ
ꢂ
0
ꢀꢁ=ꢗꢉ"ꢜ#
ꢗꢁ=ꢗ
ꢗꢁ8=
ꢗꢁꢗꢗ
ꢘꢁꢘꢗ
ꢀꢁ;ꢗ
ꢘꢁꢙꢗ
ꢗꢁꢀꢗ
ꢗꢁ;!
ꢗꢞ
M
M
M
M
M
M
M
M
M
M
M
ꢀꢁ !
ꢀꢁ;ꢗ
ꢗꢁꢀ!
;ꢁꢘꢗ
ꢀꢁ8ꢗ
;ꢁꢀꢗ
ꢗꢁ6ꢗ
ꢗꢁ8ꢗ
;ꢗꢞ
0ꢀ
ꢀ
ꢎ
5
ꢗꢁꢗ8
ꢗꢁꢘꢗ
ꢗꢁꢘ6
ꢗꢁ!ꢀ
ꢜꢔꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀꢘꢙꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
ꢘꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ "ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ <ꢗ=ꢀ"
© 2008 Microchip Technology Inc.
DS21882D-page 21
MCP6241/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ#ꢐꢄꢈꢆ$ꢈꢄꢊ%ꢆꢜꢔꢆꢂꢃꢄꢅꢆꢇꢄꢌ&ꢄ'ꢃꢆꢕ(ꢘꢖꢆMꢆ *!*ꢚ+,ꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗ#$ꢜꢛ
ꢜꢔꢊꢃꢝ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
e
D
b
N
N
L
K
E2
E
EXPOSED PAD
NOTE 1
NOTE 1
2
1
1
2
D2
BOTTOM VIEW
TOP VIEW
A
NOTE 2
A3
A1
.ꢆꢃꢍꢇ
ꢕ/00/ꢕꢌ%ꢌ1ꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
8
ꢗꢁ!ꢗꢉ"ꢜ#
ꢗꢁ=ꢗ
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
3'ꢅꢓꢊꢏꢏꢉ7ꢅꢃꢚꢒꢍ
ꢜꢍꢊꢆꢋꢈꢑꢑꢉ
#ꢈꢆꢍꢊꢎꢍꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ:ꢃꢋꢍꢒ
2
ꢅ
ꢛ
ꢛꢀ
ꢛ;
ꢂ
ꢗꢁ8ꢗ
ꢗꢁꢗꢗ
ꢀꢁꢗꢗ
ꢗꢁꢗ!
ꢗꢁꢗꢘ
ꢗꢁꢘꢗꢉ1ꢌ)
ꢘꢁꢗꢗꢉ"ꢜ#
;ꢁꢗꢗꢉ"ꢜ#
M
M
ꢗꢁꢘ!
ꢌ
ꢌꢖꢔꢈꢇꢅꢋꢉ,ꢊꢋꢉ0ꢅꢆꢚꢍꢒ
ꢌꢖꢔꢈꢇꢅꢋꢉ,ꢊꢋꢉ:ꢃꢋꢍꢒ
#ꢈꢆꢍꢊꢎꢍꢉ:ꢃꢋꢍꢒ
#ꢈꢆꢍꢊꢎꢍꢉ0ꢅꢆꢚꢍꢒ
#ꢈꢆꢍꢊꢎꢍ<ꢍꢈ<ꢌꢖꢔꢈꢇꢅꢋꢉ,ꢊꢋ
ꢂꢘ
ꢌꢘ
5
0
?
ꢀꢁ;ꢗ
ꢀꢁ!ꢗ
ꢗꢁꢘꢗ
ꢗꢁ;ꢗ
ꢗꢁꢘꢗ
ꢀꢁ!!
ꢀꢁꢙ!
ꢗꢁ;ꢗ
ꢗꢁ!ꢗ
M
ꢗꢁ ꢗ
M
ꢜꢔꢊꢃꢉꢝ
ꢀꢁ ,ꢃꢆꢉꢀꢉ'ꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊ&ꢉ'ꢊꢓ&+ꢉ5ꢐꢍꢉꢄꢐꢇꢍꢉ5ꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉ(ꢃꢍꢒꢃꢆꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
ꢘꢁ ,ꢊꢎ*ꢊꢚꢅꢉꢄꢊ&ꢉꢒꢊ'ꢅꢉꢈꢆꢅꢉꢈꢓꢉꢄꢈꢓꢅꢉꢅꢖꢔꢈꢇꢅꢋꢉꢍꢃꢅꢉ5ꢊꢓꢇꢉꢊꢍꢉꢅꢆꢋꢇꢁ
;ꢁ ,ꢊꢎ*ꢊꢚꢅꢉꢃꢇꢉꢇꢊ(ꢉꢇꢃꢆꢚꢐꢏꢊꢍꢅꢋꢁ
ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ "ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
1ꢌ)$ 1ꢅꢑꢅꢓꢅꢆꢎꢅꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆ+ꢉꢐꢇꢐꢊꢏꢏ&ꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅ+ꢉꢑꢈꢓꢉꢃꢆꢑꢈꢓꢄꢊꢍꢃꢈꢆꢉꢔꢐꢓꢔꢈꢇꢅꢇꢉꢈꢆꢏ&ꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ <ꢀꢘ;#
DS21882D-page 22
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ#ꢐꢄꢈꢆ$ꢈꢄꢊ%ꢆꢜꢔꢆꢂꢃꢄꢅꢆꢇꢄꢌ&ꢄ'ꢃꢆꢕ(ꢘꢖꢆMꢆ *!*ꢚ+,ꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗ#$ꢜꢛ
ꢜꢔꢊꢃꢝ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
© 2008 Microchip Technology Inc.
DS21882D-page 23
MCP6241/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ(ꢋꢌꢓꢔꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢇꢄꢌ&ꢄ'ꢃꢆꢕ(ꢍꢖꢆꢗ(ꢍꢏꢇꢛ
ꢜꢔꢊꢃꢝ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
D
N
E
E1
NOTE 1
2
b
1
e
c
φ
A2
A
L
L1
A1
.ꢆꢃꢍꢇ
ꢕ/00/ꢕꢌ%ꢌ1ꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
2
ꢅ
8
ꢗꢁ6!ꢉ"ꢜ#
3'ꢅꢓꢊꢏꢏꢉ7ꢅꢃꢚꢒꢍ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
ꢜꢍꢊꢆꢋꢈꢑꢑꢉ
3'ꢅꢓꢊꢏꢏꢉ:ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ:ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
)ꢈꢈꢍꢉ0ꢅꢆꢚꢍꢒ
ꢛ
M
ꢗꢁꢙ!
ꢗꢁꢗꢗ
M
ꢗꢁ8!
ꢀꢁꢀꢗ
ꢗꢁ=!
ꢗꢁꢀ!
ꢛꢘ
ꢛꢀ
ꢌ
ꢌꢀ
ꢂ
M
ꢁ=ꢗꢉ"ꢜ#
;ꢁꢗꢗꢉ"ꢜ#
;ꢁꢗꢗꢉ"ꢜ#
ꢗꢁ6ꢗ
0
ꢗꢁ ꢗ
ꢗꢁ8ꢗ
)ꢈꢈꢍꢔꢓꢃꢆꢍ
)ꢈꢈꢍꢉꢛꢆꢚꢏꢅ
0ꢀ
ꢀ
ꢗꢁ=!ꢉ1ꢌ)
M
ꢗꢞ
8ꢞ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
0ꢅꢊꢋꢉ:ꢃꢋꢍꢒ
ꢎ
5
ꢗꢁꢗ8
ꢗꢁꢘꢘ
M
M
ꢗꢁꢘ;
ꢗꢁ ꢗ
ꢜꢔꢊꢃꢉꢝ
ꢀꢁ ,ꢃꢆꢉꢀꢉ'ꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊ&ꢉ'ꢊꢓ&+ꢉ5ꢐꢍꢉꢄꢐꢇꢍꢉ5ꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉ(ꢃꢍꢒꢃꢆꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
ꢘꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀ!ꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
;ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ "ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
1ꢌ)$ 1ꢅꢑꢅꢓꢅꢆꢎꢅꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆ+ꢉꢐꢇꢐꢊꢏꢏ&ꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅ+ꢉꢑꢈꢓꢉꢃꢆꢑꢈꢓꢄꢊꢍꢃꢈꢆꢉꢔꢐꢓꢔꢈꢇꢅꢇꢉꢈꢆꢏ&ꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ <ꢀꢀꢀ"
DS21882D-page 24
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ#ꢐꢄꢈꢆ/ꢑꢁꢂꢋꢑꢃꢆꢕꢇꢖꢆMꢆ!ꢚꢚꢆꢎꢋꢈꢆ-ꢔꢅ.ꢆꢗꢇ#/ꢇꢛ
ꢜꢔꢊꢃꢝ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
A1
c
e
eB
b1
b
.ꢆꢃꢍꢇ
/2#7ꢌꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
8
ꢁꢀꢗꢗꢉ"ꢜ#
M
ꢁꢀ;ꢗ
M
ꢁ;ꢀꢗ
ꢁꢘ!ꢗ
ꢁ;6!
ꢁꢀ;ꢗ
ꢁꢗꢀꢗ
ꢁꢗ6ꢗ
ꢁꢗꢀ8
M
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
%ꢈꢔꢉꢍꢈꢉꢜꢅꢊꢍꢃꢆꢚꢉ,ꢏꢊꢆꢅ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
"ꢊꢇꢅꢉꢍꢈꢉꢜꢅꢊꢍꢃꢆꢚꢉ,ꢏꢊꢆꢅ
ꢜꢒꢈꢐꢏꢋꢅꢓꢉꢍꢈꢉꢜꢒꢈꢐꢏꢋꢅꢓꢉ:ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ:ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
2
ꢅ
ꢛ
ꢛꢘ
ꢛꢀ
ꢌ
ꢌꢀ
ꢂ
0
ꢎ
5ꢀ
5
ꢅ"
M
ꢁꢘꢀꢗ
ꢁꢀ=!
M
ꢁꢀꢀ!
ꢁꢗꢀ!
ꢁꢘ=ꢗ
ꢁꢘ ꢗ
ꢁ; 8
ꢁꢀꢀ!
ꢁꢗꢗ8
ꢁꢗ ꢗ
ꢁꢗꢀ
M
ꢁ;ꢘ!
ꢁꢘ8ꢗ
ꢁ ꢗꢗ
ꢁꢀ!ꢗ
ꢁꢗꢀ!
ꢁꢗꢙꢗ
ꢁꢗꢘꢘ
ꢁ ;ꢗ
%ꢃꢔꢉꢍꢈꢉꢜꢅꢊꢍꢃꢆꢚꢉ,ꢏꢊꢆꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
.ꢔꢔꢅꢓꢉ0ꢅꢊꢋꢉ:ꢃꢋꢍꢒ
0ꢈ(ꢅꢓꢉ0ꢅꢊꢋꢉ:ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ1ꢈ(ꢉꢜꢔꢊꢎꢃꢆꢚꢉꢉꢟ
ꢜꢔꢊꢃꢉꢝ
ꢀꢁ ,ꢃꢆꢉꢀꢉ'ꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊ&ꢉ'ꢊꢓ&+ꢉ5ꢐꢍꢉꢄꢐꢇꢍꢉ5ꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉ(ꢃꢍꢒꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
ꢘꢁ ꢟꢉꢜꢃꢚꢆꢃꢑꢃꢎꢊꢆꢍꢉ#ꢒꢊꢓꢊꢎꢍꢅꢓꢃꢇꢍꢃꢎꢁ
;ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢁꢗꢀꢗAꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ꢉ"ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ <ꢗꢀ8"
© 2008 Microchip Technology Inc.
DS21882D-page 25
MCP6241/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢜꢖꢆMꢆꢜꢄꢓꢓꢔ0%ꢆ!+,ꢚꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗꢍꢏ/ꢘꢛ
ꢜꢔꢊꢃꢝ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
D
e
N
E
E1
NOTE 1
1
2
3
α
h
b
h
c
φ
A2
A
L
A1
L1
β
.ꢆꢃꢍꢇ
ꢕ/00/ꢕꢌ%ꢌ1ꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
2
ꢅ
8
ꢀꢁꢘꢙꢉ"ꢜ#
3'ꢅꢓꢊꢏꢏꢉ7ꢅꢃꢚꢒꢍ
ꢛ
M
ꢀꢁꢘ!
ꢗꢁꢀꢗ
M
M
M
ꢀꢁꢙ!
M
ꢗꢁꢘ!
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
ꢜꢍꢊꢆꢋꢈꢑꢑꢉꢉ
ꢛꢘ
ꢛꢀ
ꢌ
ꢟ
3'ꢅꢓꢊꢏꢏꢉ:ꢃꢋꢍꢒ
6ꢁꢗꢗꢉ"ꢜ#
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ:ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
#ꢒꢊꢄꢑꢅꢓꢉBꢈꢔꢍꢃꢈꢆꢊꢏC
)ꢈꢈꢍꢉ0ꢅꢆꢚꢍꢒ
ꢌꢀ
ꢂ
ꢒ
;ꢁ=ꢗꢉ"ꢜ#
ꢁ=ꢗꢉ"ꢜ#
ꢗꢁꢘ!
ꢗꢁ ꢗ
M
M
ꢗꢁ!ꢗ
ꢀꢁꢘꢙ
0
)ꢈꢈꢍꢔꢓꢃꢆꢍ
)ꢈꢈꢍꢉꢛꢆꢚꢏꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
0ꢅꢊꢋꢉ:ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢉꢂꢓꢊꢑꢍꢉꢛꢆꢚꢏꢅꢉ%ꢈꢔ
ꢕꢈꢏꢋꢉꢂꢓꢊꢑꢍꢉꢛꢆꢚꢏꢅꢉ"ꢈꢍꢍꢈꢄ
0ꢀ
ꢀ
ꢀꢁꢗ ꢉ1ꢌ)
ꢗꢞ
ꢗꢁꢀꢙ
ꢗꢁ;ꢀ
!ꢞ
M
M
M
M
M
8ꢞ
ꢎ
5
ꢁ
ꢗꢁꢘ!
ꢗꢁ!ꢀ
ꢀ!ꢞ
ꢂ
!ꢞ
ꢀ!ꢞ
ꢜꢔꢊꢃꢉꢝ
ꢀꢁ ,ꢃꢆꢉꢀꢉ'ꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊ&ꢉ'ꢊꢓ&+ꢉ5ꢐꢍꢉꢄꢐꢇꢍꢉ5ꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉ(ꢃꢍꢒꢃꢆꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
ꢘꢁ ꢟꢉꢜꢃꢚꢆꢃꢑꢃꢎꢊꢆꢍꢉ#ꢒꢊꢓꢊꢎꢍꢅꢓꢃꢇꢍꢃꢎꢁ
;ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀ!ꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ "ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
1ꢌ)$ 1ꢅꢑꢅꢓꢅꢆꢎꢅꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆ+ꢉꢐꢇꢐꢊꢏꢏ&ꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅ+ꢉꢑꢈꢓꢉꢃꢆꢑꢈꢓꢄꢊꢍꢃꢈꢆꢉꢔꢐꢓꢔꢈꢇꢅꢇꢉꢈꢆꢏ&ꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ <ꢗ!ꢙ"
DS21882D-page 26
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢜꢖꢆMꢆꢜꢄꢓꢓꢔ0%ꢆ!+,ꢚꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗꢍꢏ/ꢘꢛ
ꢜꢔꢊꢃꢝ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
© 2008 Microchip Technology Inc.
DS21882D-page 27
MCP6241/1R/1U/2/4
12ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ#ꢐꢄꢈꢆ/ꢑꢁꢂꢋꢑꢃꢆꢕꢇꢖꢆMꢆ!ꢚꢚꢆꢎꢋꢈꢆ-ꢔꢅ.ꢆꢗꢇ#/ꢇꢛ
ꢜꢔꢊꢃꢝ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
c
A1
b1
b
e
eB
.ꢆꢃꢍꢇ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
/2#7ꢌꢜ
23ꢕ
ꢀ
ꢁꢀꢗꢗꢉ"ꢜ#
M
ꢕ/2
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
2
ꢅ
ꢛ
%ꢈꢔꢉꢍꢈꢉꢜꢅꢊꢍꢃꢆꢚꢉ,ꢏꢊꢆꢅ
M
ꢁꢘꢀꢗ
ꢁꢀ=!
M
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
"ꢊꢇꢅꢉꢍꢈꢉꢜꢅꢊꢍꢃꢆꢚꢉ,ꢏꢊꢆꢅ
ꢜꢒꢈꢐꢏꢋꢅꢓꢉꢍꢈꢉꢜꢒꢈꢐꢏꢋꢅꢓꢉ:ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ:ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
%ꢃꢔꢉꢍꢈꢉꢜꢅꢊꢍꢃꢆꢚꢉ,ꢏꢊꢆꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
.ꢔꢔꢅꢓꢉ0ꢅꢊꢋꢉ:ꢃꢋꢍꢒ
ꢛꢘ
ꢛꢀ
ꢌ
ꢌꢀ
ꢂ
0
ꢎ
5ꢀ
5
ꢅ"
ꢁꢀꢀ!
ꢁꢗꢀ!
ꢁꢘ=ꢗ
ꢁꢘ ꢗ
ꢁꢙ;!
ꢁꢀꢀ!
ꢁꢗꢗ8
ꢁꢗ !
ꢁꢗꢀ
M
ꢁꢀ;ꢗ
M
ꢁ;ꢀꢗ
ꢁꢘ!ꢗ
ꢁꢙ!ꢗ
ꢁꢀ;ꢗ
ꢁꢗꢀꢗ
ꢁꢗ6ꢗ
ꢁꢗꢀ8
M
ꢁ;ꢘ!
ꢁꢘ8ꢗ
ꢁꢙꢙ!
ꢁꢀ!ꢗ
ꢁꢗꢀ!
ꢁꢗꢙꢗ
ꢁꢗꢘꢘ
ꢁ ;ꢗ
0ꢈ(ꢅꢓꢉ0ꢅꢊꢋꢉ:ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ1ꢈ(ꢉꢜꢔꢊꢎꢃꢆꢚꢉꢉꢟ
ꢜꢔꢊꢃꢉꢝ
ꢀꢁ ,ꢃꢆꢉꢀꢉ'ꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊ&ꢉ'ꢊꢓ&+ꢉ5ꢐꢍꢉꢄꢐꢇꢍꢉ5ꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉ(ꢃꢍꢒꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
ꢘꢁ ꢟꢉꢜꢃꢚꢆꢃꢑꢃꢎꢊꢆꢍꢉ#ꢒꢊꢓꢊꢎꢍꢅꢓꢃꢇꢍꢃꢎꢁ
;ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢁꢗꢀꢗAꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ꢉ"ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ <ꢗꢗ!"
DS21882D-page 28
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
12ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢂꢖꢆMꢆꢜꢄꢓꢓꢔ0%ꢆ!+,ꢚꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗꢍꢏ/ꢘꢛ
ꢜꢔꢊꢃꢝ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
D
N
E
E1
NOTE 1
1
2
3
e
h
b
α
h
c
φ
A2
A
L
A1
β
L1
.ꢆꢃꢍꢇ
ꢕ/00/ꢕꢌ%ꢌ1ꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
2
ꢅ
ꢀ
ꢀꢁꢘꢙꢉ"ꢜ#
3'ꢅꢓꢊꢏꢏꢉ7ꢅꢃꢚꢒꢍ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
ꢜꢍꢊꢆꢋꢈꢑꢑꢉꢉꢟ
ꢛ
M
ꢀꢁꢘ!
ꢗꢁꢀꢗ
M
M
M
ꢀꢁꢙ!
M
ꢗꢁꢘ!
ꢛꢘ
ꢛꢀ
ꢌ
3'ꢅꢓꢊꢏꢏꢉ:ꢃꢋꢍꢒ
6ꢁꢗꢗꢉ"ꢜ#
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ:ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
#ꢒꢊꢄꢑꢅꢓꢉBꢈꢔꢍꢃꢈꢆꢊꢏC
)ꢈꢈꢍꢉ0ꢅꢆꢚꢍꢒ
ꢌꢀ
ꢂ
ꢒ
;ꢁ=ꢗꢉ"ꢜ#
8ꢁ6!ꢉ"ꢜ#
ꢗꢁꢘ!
ꢗꢁ ꢗ
M
M
ꢗꢁ!ꢗ
ꢀꢁꢘꢙ
0
)ꢈꢈꢍꢔꢓꢃꢆꢍ
)ꢈꢈꢍꢉꢛꢆꢚꢏꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
0ꢅꢊꢋꢉ:ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢉꢂꢓꢊꢑꢍꢉꢛꢆꢚꢏꢅꢉ%ꢈꢔ
ꢕꢈꢏꢋꢉꢂꢓꢊꢑꢍꢉꢛꢆꢚꢏꢅꢉ"ꢈꢍꢍꢈꢄ
0ꢀ
ꢀ
ꢀꢁꢗ ꢉ1ꢌ)
ꢗꢞ
ꢗꢁꢀꢙ
ꢗꢁ;ꢀ
!ꢞ
M
M
M
M
M
8ꢞ
ꢎ
5
ꢁ
ꢗꢁꢘ!
ꢗꢁ!ꢀ
ꢀ!ꢞ
ꢂ
!ꢞ
ꢀ!ꢞ
ꢜꢔꢊꢃꢉꢝ
ꢀꢁ ,ꢃꢆꢉꢀꢉ'ꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊ&ꢉ'ꢊꢓ&+ꢉ5ꢐꢍꢉꢄꢐꢇꢍꢉ5ꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉ(ꢃꢍꢒꢃꢆꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
ꢘꢁ ꢟꢉꢜꢃꢚꢆꢃꢑꢃꢎꢊꢆꢍꢉ#ꢒꢊꢓꢊꢎꢍꢅꢓꢃꢇꢍꢃꢎꢁ
;ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀ!ꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ "ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
1ꢌ)$ 1ꢅꢑꢅꢓꢅꢆꢎꢅꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆ+ꢉꢐꢇꢐꢊꢏꢏ&ꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅ+ꢉꢑꢈꢓꢉꢃꢆꢑꢈꢓꢄꢊꢍꢃꢈꢆꢉꢔꢐꢓꢔꢈꢇꢅꢇꢉꢈꢆꢏ&ꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ <ꢗ6!"
© 2008 Microchip Technology Inc.
DS21882D-page 29
MCP6241/1R/1U/2/4
ꢜꢔꢊꢃꢝ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
DS21882D-page 30
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
12ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢒ3ꢋꢑꢆꢍ3ꢓꢋꢑ&ꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢒꢖꢆMꢆ2+2ꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗꢒꢍꢍꢏꢇꢛ
ꢜꢔꢊꢃꢝ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
D
N
E
E1
NOTE 1
1
2
e
b
c
φ
A2
A
A1
L
L1
.ꢆꢃꢍꢇ
ꢕ/00/ꢕꢌ%ꢌ1ꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
2
ꢅ
ꢀ
ꢗꢁ6!ꢉ"ꢜ#
3'ꢅꢓꢊꢏꢏꢉ7ꢅꢃꢚꢒꢍ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
ꢜꢍꢊꢆꢋꢈꢑꢑꢉ
3'ꢅꢓꢊꢏꢏꢉ:ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ:ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ0ꢅꢆꢚꢍꢒ
)ꢈꢈꢍꢉ0ꢅꢆꢚꢍꢒ
ꢛ
M
ꢗꢁ8ꢗ
ꢗꢁꢗ!
M
ꢀꢁꢗꢗ
M
6ꢁ ꢗꢉ"ꢜ#
ꢁ ꢗ
!ꢁꢗꢗ
ꢗꢁ6ꢗ
ꢀꢁꢘꢗ
ꢀꢁꢗ!
ꢗꢁꢀ!
ꢛꢘ
ꢛꢀ
ꢌ
ꢌꢀ
ꢂ
ꢁ;ꢗ
ꢁ=ꢗ
ꢗꢁ !
ꢁ!ꢗ
!ꢁꢀꢗ
ꢗꢁꢙ!
0
)ꢈꢈꢍꢔꢓꢃꢆꢍ
)ꢈꢈꢍꢉꢛꢆꢚꢏꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
0ꢅꢊꢋꢉ:ꢃꢋꢍꢒ
0ꢀ
ꢀ
ꢀꢁꢗꢗꢉ1ꢌ)
ꢗꢞ
ꢗꢁꢗ=
ꢗꢁꢀ=
M
M
M
8ꢞ
ꢎ
5
ꢗꢁꢘꢗ
ꢗꢁ;ꢗ
ꢜꢔꢊꢃꢉꢝ
ꢀꢁ ,ꢃꢆꢉꢀꢉ'ꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊ&ꢉ'ꢊꢓ&+ꢉ5ꢐꢍꢉꢄꢐꢇꢍꢉ5ꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉ(ꢃꢍꢒꢃꢆꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
ꢘꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀ!ꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
;ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ "ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
1ꢌ)$ 1ꢅꢑꢅꢓꢅꢆꢎꢅꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆ+ꢉꢐꢇꢐꢊꢏꢏ&ꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅ+ꢉꢑꢈꢓꢉꢃꢆꢑꢈꢓꢄꢊꢍꢃꢈꢆꢉꢔꢐꢓꢔꢈꢇꢅꢇꢉꢈꢆꢏ&ꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ <ꢗ8ꢙ"
© 2008 Microchip Technology Inc.
DS21882D-page 31
MCP6241/1R/1U/2/4
NOTES:
DS21882D-page 32
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
APPENDIX A: REVISION HISTORY
Revision D (October 2008)
The following is the list of modifications:
1. Changed Heading “Available Tools” to “Design
Aids”.
2. Design Aids: Name change for Mindi Simulator
Tool.
3. Package Types: Added DFN to MCP6231
Device.
4. Absolute Maximum Ratings: Numerous
changes in this section.
5. Updated notes to Section 1.0 “Electrical Char-
acteristics”.
6. Added Figure 2-19.
7. Numerous changes to Section 3.0 “Pin
Descriptions”.
8. Added Section 4.1.1 “Phase Reversal”,
Section 4.1.2 “Input Voltage and Current
Limits”, and Section 4.1.3 “Normal Opera-
tion”.
9. Replaced Section 5.0 “Design Aids” with
additional information.
10. Added 2x3 DFN package to Section 6.0 “Pack-
aging Information” and updated Package Out-
line Drawings.
11. Added 2x3 DFN package to Product Identifica-
tion System section.
Revision C (March 2005)
The following is the list of modifications:
1. Added the MCP6244 quad op amp.
2. Re-compensated parts. Specifications that
change are: Gain Bandwidth Product (BWP)
and Phase Margin (PM) in AC Electrical
Characteristics table.
3. Corrected plots in Section 2.0 “Typical Perfor-
mance Curves”.
4. Added Section 3.0 “Pin Descriptions”.
5. Added new SC-70 package markings. Added
PDIP-14, SOIC-14, and TSSOP-14 packages
and corrected package marking information
(Section 6.0 “Packaging Information”).
6. Added Appendix A: “Revision History”.
Revision B (August 2004)
Undocumented changes.
Revision A (March 2004)
• Original Release of this Document.
© 2008 Microchip Technology Inc.
DS21882D-page 33
MCP6241/1R/1U/2/4
NOTES:
DS21882D-page 34
© 2008 Microchip Technology Inc.
MCP6241/1R/1U/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
-X
/XX
a) MCP6241-E/SN:
Extended Temp.,
8LD SOIC package.
Tape and Reel
and/or
Alternate Pinout
Temperature Package
Range
b) MCP6241-E/MS: Extended Temp.,
8LD MSOP package.
c) MCP6241-E/P:
Extended Temp.,
8LD PDIP package.
Device:
MCP6241:
MCP6241T:
Single Op Amp (MSOP, PDIP, SOIC)
Single Op Amp (Tape and Reel)
(MSOP, SOIC, SOT-23)
Single Op Amp (Tape and Reel)
(SOT-23)
d) MCP6241-E/MC: Extended Temp.,
8LD DFN package.
MCP6241RT:
e) MCP6241RT-E/OT: Tape and Reel,
Extended Temp.,
MCP6241UT: Single Op Amp (Tape and Reel)
(SC-70, SOT-23)
MCP6242:
Dual Op Amp
Dual Op Amp (Tape and Reel)
(MSOP, SOIC)
Quad Op Amp
Quad Op Amp (Tape and Reel)
(SOIC, TSSOP)
5LD SOT-23 package
MCP6242T:
f)
MCP6241UT-E/OT: Tape and Reel,
Extended Temp.,
MCP6244:
MCP6244T:
5LD SOT-23 package.
g) MCP6241UT-E/LT: Tape and Reel,
Extended Temp.,
Temperature Range:
Package:
E
=
-40° C to +125° C
5LD SC-70 package.
a) MCP6242-E/SN:
Extended Temp.,
8LD SOIC package.
LT
MC
=
=
Plastic Package (SC-70), 5-lead (MCP6241U only)
Plastic Dual Flat, No Lead (DFN), 8-lead,
(MCP6241 only)
Plastic Micro Small Outline (MSOP), 8-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6241, MCP6241R, MCP6241U)
Plastic SOIC (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead
Plastic TSSOP (4.4 mil Body), 14-lead
b) MCP6242-E/MS: Extended Temp.,
8LD MSOP package.
MS
P
OT
=
=
=
c) MCP6242-E/P:
Extended Temp.,
8LD PDIP package.
SN
SL
ST
=
=
=
d) MCP6242T-E/SN: Tape and Reel,
Extended Temp.,
8LD SOIC package.
a) MCP6244-E/P:
b) MCP6244-E/SL:
c) MCP6244-E/ST:
Extended Temp.,
14LD PDIP package.
Extended Temp.,
14LD SOIC package.
Extended Temp.,
14LD TSSOP
package.
d) MCP6244T-E/SL: Tape and Reel,
Extended Temp.,
14LD SOIC package.
e) MCP6244T-E/ST: Tape and Reel,
Extended Temp.,
14LD TSSOP
package.
© 2008 Microchip Technology Inc.
DS21882D-page 35
MCP6241/1R/1U/2/4
NOTES:
DS21882D-page 36
© 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2008 Microchip Technology Inc.
DS21882D-page 37
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/02/08
DS21882D-page 38
© 2008 Microchip Technology Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明